From 5d2c393fa42ae76dfdd9ba313b8c46e353e31d57 Mon Sep 17 00:00:00 2001 From: Akif Ejaz Date: Thu, 1 Jan 2026 14:22:29 +0500 Subject: [PATCH 01/19] Add RISC-V32 QEMU-virt example This commit introduces the complete example build environment for the RISC-V32/GNU port targeting the QEMU virt machine. It includes basic BSP components, startup code, drivers, linker script, and a minimal ThreadX demo application. Signed-off-by: Akif Ejaz --- .../gnu/example_build/qemu_virt/board.c | 42 ++ .../qemu_virt/build_libthreadx.sh | 5 + .../gnu/example_build/qemu_virt/csr.h | 343 +++++++++++++++ .../example_build/qemu_virt/demo_threadx.c | 393 ++++++++++++++++++ .../gnu/example_build/qemu_virt/entry.s | 58 +++ .../gnu/example_build/qemu_virt/hwtimer.c | 35 ++ .../gnu/example_build/qemu_virt/hwtimer.h | 23 + .../gnu/example_build/qemu_virt/link.lds | 49 +++ .../gnu/example_build/qemu_virt/plic.c | 72 ++++ .../gnu/example_build/qemu_virt/plic.h | 49 +++ .../gnu/example_build/qemu_virt/trap.c | 67 +++ .../qemu_virt/tx_initialize_low_level.S | 177 ++++++++ .../gnu/example_build/qemu_virt/uart.c | 102 +++++ .../gnu/example_build/qemu_virt/uart.h | 22 + 14 files changed, 1437 insertions(+) create mode 100644 ports/risc-v32/gnu/example_build/qemu_virt/board.c create mode 100755 ports/risc-v32/gnu/example_build/qemu_virt/build_libthreadx.sh create mode 100644 ports/risc-v32/gnu/example_build/qemu_virt/csr.h create mode 100644 ports/risc-v32/gnu/example_build/qemu_virt/demo_threadx.c create mode 100644 ports/risc-v32/gnu/example_build/qemu_virt/entry.s create mode 100644 ports/risc-v32/gnu/example_build/qemu_virt/hwtimer.c create mode 100644 ports/risc-v32/gnu/example_build/qemu_virt/hwtimer.h create mode 100644 ports/risc-v32/gnu/example_build/qemu_virt/link.lds create mode 100644 ports/risc-v32/gnu/example_build/qemu_virt/plic.c create mode 100644 ports/risc-v32/gnu/example_build/qemu_virt/plic.h create mode 100644 ports/risc-v32/gnu/example_build/qemu_virt/trap.c create mode 100644 ports/risc-v32/gnu/example_build/qemu_virt/tx_initialize_low_level.S create mode 100644 ports/risc-v32/gnu/example_build/qemu_virt/uart.c create mode 100644 ports/risc-v32/gnu/example_build/qemu_virt/uart.h diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/board.c b/ports/risc-v32/gnu/example_build/qemu_virt/board.c new file mode 100644 index 00000000..fc75de66 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/qemu_virt/board.c @@ -0,0 +1,42 @@ +/*************************************************************************** + * Copyright (c) 2025 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#include "plic.h" +#include "hwtimer.h" +#include "uart.h" +#include +#include + +void *memset(const void *des, int c,size_t n) +{ + if((des == NULL) || n <=0) + return (void*)des; + char* t = (char*)des; + int i; + for(i=0;i + +static inline uint32_t riscv_get_core() +{ + uint32_t x; + asm volatile("csrr %0, mhartid" : "=r" (x) ); + return x; +} + +static inline uint32_t riscv_get_mstatus() +{ + uint32_t x; + asm volatile("csrr %0, mstatus" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_mstatus(uint32_t x) +{ + asm volatile("csrw mstatus, %0" : : "r" (x)); +} + +static inline void riscv_writ_mepc(uint32_t x) +{ + asm volatile("csrw mepc, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_sstatus() +{ + uint32_t x; + asm volatile("csrr %0, sstatus" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_sstatus(uint32_t x) +{ + asm volatile("csrw sstatus, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_sip() +{ + uint32_t x; + asm volatile("csrr %0, sip" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_sip(uint32_t x) +{ + asm volatile("csrw sip, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_sie() +{ + uint32_t x; + asm volatile("csrr %0, sie" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_sie(uint32_t x) +{ + asm volatile("csrw sie, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_mie() +{ + uint32_t x; + asm volatile("csrr %0, mie" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_mie(uint32_t x) +{ + asm volatile("csrw mie, %0" : : "r" (x)); +} + +static inline void riscv_writ_sepc(uint32_t x) +{ + asm volatile("csrw sepc, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_sepc() +{ + uint32_t x; + asm volatile("csrr %0, sepc" : "=r" (x) ); + return x; +} + +static inline uint32_t riscv_get_medeleg() +{ + uint32_t x; + asm volatile("csrr %0, medeleg" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_medeleg(uint32_t x) +{ + asm volatile("csrw medeleg, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_mideleg() +{ + uint32_t x; + asm volatile("csrr %0, mideleg" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_mideleg(uint32_t x) +{ + asm volatile("csrw mideleg, %0" : : "r" (x)); +} + +static inline void riscv_writ_stvec(uint32_t x) +{ + asm volatile("csrw stvec, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_stvec() +{ + uint32_t x; + asm volatile("csrr %0, stvec" : "=r" (x) ); + return x; +} + +static inline uint32_t riscv_get_stimecmp() +{ + uint32_t x; + asm volatile("csrr %0, 0x14d" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_stimecmp(uint32_t x) +{ + asm volatile("csrw 0x14d, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_menvcfg() +{ + uint32_t x; + asm volatile("csrr %0, 0x30a" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_menvcfg(uint32_t x) +{ + asm volatile("csrw 0x30a, %0" : : "r" (x)); +} + +static inline void riscv_writ_pmpcfg0(uint32_t x) +{ + asm volatile("csrw pmpcfg0, %0" : : "r" (x)); +} + +static inline void riscv_writ_pmpaddr0(uint32_t x) +{ + asm volatile("csrw pmpaddr0, %0" : : "r" (x)); +} + +static inline void riscv_writ_satp(uint32_t x) +{ + asm volatile("csrw satp, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_satp() +{ + uint32_t x; + asm volatile("csrr %0, satp" : "=r" (x) ); + return x; +} + +static inline uint32_t riscv_get_scause() +{ + uint32_t x; + asm volatile("csrr %0, scause" : "=r" (x) ); + return x; +} + +static inline uint32_t riscv_get_stval() +{ + uint32_t x; + asm volatile("csrr %0, stval" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_mcounteren(uint32_t x) +{ + asm volatile("csrw mcounteren, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_mcounteren() +{ + uint32_t x; + asm volatile("csrr %0, mcounteren" : "=r" (x) ); + return x; +} + +static inline uint32_t riscv_get_time() +{ + uint32_t x; + asm volatile("csrr %0, time" : "=r" (x) ); + return x; +} + +static inline void riscv_sintr_on() +{ + uint32_t sstatus = riscv_get_sstatus(); + sstatus |= SSTATUS_SIE; + riscv_writ_sstatus(sstatus); +} + +static inline void riscv_sintr_off() +{ + uint32_t sstatus = riscv_get_sstatus(); + sstatus &= (~SSTATUS_SIE); + riscv_writ_sstatus(sstatus); +} + +static inline int riscv_sintr_get() +{ + uint32_t x = riscv_get_sstatus(); + return (x & SSTATUS_SIE) != 0; +} + +static inline void riscv_sintr_restore(int x) +{ + if(x) + riscv_sintr_on(); + else + riscv_sintr_off(); +} + +static inline void riscv_mintr_on() +{ + uint32_t mstatus = riscv_get_mstatus(); + mstatus |= MSTATUS_MIE; + riscv_writ_mstatus(mstatus); +} + +static inline void riscv_mintr_off() +{ + uint32_t mstatus = riscv_get_mstatus(); + mstatus &= (~MSTATUS_MIE); + riscv_writ_mstatus(mstatus); +} + +static inline int riscv_mintr_get() +{ + uint32_t x = riscv_get_mstatus(); + return (x & MSTATUS_MIE) != 0; +} + +static inline void riscv_mintr_restore(int x) +{ + if(x) + riscv_mintr_on(); + else + riscv_mintr_off(); +} + +static inline uint32_t riscv_get_sp() +{ + uint32_t x; + asm volatile("mv %0, sp" : "=r" (x) ); + return x; +} + +// read and write tp, the thread pointer, which xv6 uses to hold +// this core's hartid (core number), the index into cpus[]. +static inline uint32_t riscv_get_tp() +{ + uint32_t x; + asm volatile("mv %0, tp" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_tp(uint32_t x) +{ + asm volatile("mv tp, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_ra() +{ + uint32_t x; + asm volatile("mv %0, ra" : "=r" (x) ); + return x; +} + +// flush the TLB. +static inline void sfence_vma() +{ + // the zero, zero means flush all TLB entries. + asm volatile("sfence.vma zero, zero"); +} + +#endif // __ASSEMBLER__ + +#endif diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/demo_threadx.c b/ports/risc-v32/gnu/example_build/qemu_virt/demo_threadx.c new file mode 100644 index 00000000..f21dbb26 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/qemu_virt/demo_threadx.c @@ -0,0 +1,393 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" +#include "uart.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + +char *_to_str(ULONG val) +{ + static char buf[11]; /* 10 digits max + '\0' */ + char *p = buf + sizeof(buf) - 1; + + *p = '\0'; + do { + *--p = '0' + (val % 10); + val /= 10; + } while (val); + + return p; +} + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + CHAR *pointer = TX_NULL; + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + puts("[Thread] : thread_0_entry is here!"); + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + puts("[Thread] : thread_1_entry is here!"); + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) { + puts("[Thread 1] ERROR: Failed to send message!"); + break; + } + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + puts("[Thread] : thread_2_entry is here!"); + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)){ + puts("[Thread 2] ERROR: Failed to receive message ! Expected # "); + uart_puts(_to_str(thread_2_messages_received)); + puts(", but got # "); + uart_puts(_to_str(received_message)); + break; + } + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + puts("[Thread] : thread_3_and_4_entry is here!"); + + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + puts("[Thread] : thread_5_entry is here!"); + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + puts("[Thread] : thread_6_and_7_entry is here!"); + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/entry.s b/ports/risc-v32/gnu/example_build/qemu_virt/entry.s new file mode 100644 index 00000000..9b202ca1 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/qemu_virt/entry.s @@ -0,0 +1,58 @@ + +.section .text +.align 4 +.global _start +.extern main +.extern _sysstack_start +.extern _bss_start +.extern _bss_end +_start: + csrr t0, mhartid + bne t0, zero, 1f + li x1, 0 + li x2, 0 + li x3, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10, 0 + li x11, 0 + li x12, 0 + li x13, 0 + li x14, 0 + li x15, 0 + li x16, 0 + li x17, 0 + li x18, 0 + li x19, 0 + li x20, 0 + li x21, 0 + li x22, 0 + li x23, 0 + li x24, 0 + li x25, 0 + li x26, 0 + li x27, 0 + li x28, 0 + li x29, 0 + li x30, 0 + li x31, 0 + la t0, _sysstack_start + li t1, 0x1000 + add sp, t0, t1 + la t0, _bss_start + la t1, _bss_end +_bss_clean_start: + bgeu t0, t1, _bss_clean_end + sb zero, 0(t0) + addi t0, t0, 1 + j _bss_clean_start +_bss_clean_end: + call main +1: + /* todo smp */ + wfi + j 1b diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/hwtimer.c b/ports/risc-v32/gnu/example_build/qemu_virt/hwtimer.c new file mode 100644 index 00000000..33c49b63 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/qemu_virt/hwtimer.c @@ -0,0 +1,35 @@ +/*************************************************************************** + * Copyright (c) 2025 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#include "tx_port.h" +#include "csr.h" +#include "hwtimer.h" + +#define CLINT (0x02000000L) +#define CLINT_TIME (CLINT+0xBFF8) +#define CLINT_TIMECMP(hart_id) (CLINT+0x4000+8*(hart_id)) + + +int hwtimer_init(void) +{ + int hart = riscv_get_core(); + uint64_t time = *((uint64_t*)CLINT_TIME); + *((uint64_t*)CLINT_TIMECMP(hart)) = time + TICKNUM_PER_TIMER; + return 0; +} + +int hwtimer_handler(void) +{ + int hart = riscv_get_core(); + uint64_t time = *((uint64_t*)CLINT_TIME); + *((uint64_t*)CLINT_TIMECMP(hart)) = time + TICKNUM_PER_TIMER; + return 0; +} + diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/hwtimer.h b/ports/risc-v32/gnu/example_build/qemu_virt/hwtimer.h new file mode 100644 index 00000000..966b1abf --- /dev/null +++ b/ports/risc-v32/gnu/example_build/qemu_virt/hwtimer.h @@ -0,0 +1,23 @@ + +/*************************************************************************** + * Copyright (c) 2025 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#ifndef RISCV_HWTIMER_H +#define RISCV_HWTIMER_H + +#include + +#define TICKNUM_PER_SECOND 10000000 +#define TICKNUM_PER_TIMER (TICKNUM_PER_SECOND / 10) + +int hwtimer_init(void); +int hwtimer_handler(void); + +#endif diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/link.lds b/ports/risc-v32/gnu/example_build/qemu_virt/link.lds new file mode 100644 index 00000000..522f90d9 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/qemu_virt/link.lds @@ -0,0 +1,49 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY( _start ) + +SECTIONS +{ + /* + * ensure that entry.S / _entry is at 0x80000000, + * where qemu's -kernel jumps. + */ + . = 0x80000000; + + .text : { + *(.text .text.*) + . = ALIGN(0x1000); + PROVIDE(etext = .); + } + + .rodata : { + . = ALIGN(16); + *(.srodata .srodata.*) /* do not need to distinguish this from .rodata */ + . = ALIGN(16); + *(.rodata .rodata.*) + } + + .data : { + . = ALIGN(16); + *(.sdata .sdata.*) /* do not need to distinguish this from .data */ + . = ALIGN(16); + *(.data .data.*) + } + + .bss : { + . = ALIGN(16); + _bss_start = .; + *(.sbss .sbss.*) /* do not need to distinguish this from .bss */ + . = ALIGN(16); + *(.bss .bss.*) + _bss_end = .; + } + + .stack : { + . = ALIGN(4096); + _sysstack_start = .; + . += 0x1000; + _sysstack_end = .; + } + + PROVIDE(_end = .); +} diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/plic.c b/ports/risc-v32/gnu/example_build/qemu_virt/plic.c new file mode 100644 index 00000000..01e5c71a --- /dev/null +++ b/ports/risc-v32/gnu/example_build/qemu_virt/plic.c @@ -0,0 +1,72 @@ +#include "plic.h" +#include +irq_callback callbacks[MAX_CALLBACK_NUM]; + +void plic_irq_enable(int irqno) +{ + int hart = riscv_get_core(); + *(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) | (1 << irqno)); + return; +} + +void plic_irq_disable(int irqno) +{ + int hart = riscv_get_core(); + *(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) & (~(1 << irqno))); + return; +} + +void plic_prio_set(int irqno, int prio) +{ + PLIC_SET_PRIO(irqno, prio); +} + +int plic_prio_get(int irqno) +{ + return PLIC_GET_PRIO(irqno); +} + +int plic_register_callback(int irqno, irq_callback callback) +{ + if(!(irqno >=0 && irqno < MAX_CALLBACK_NUM)) + return -1; + callbacks[irqno] = callback; + return 0; +} + +int plic_unregister_callback(int irqno) +{ + return plic_register_callback(irqno, NULL); +} + +int plic_init(void) +{ + for(int i=0;i + +#define PLIC 0x0c000000L +#define PLIC_PRIORITY (PLIC + 0x0) +#define PLIC_PENDING (PLIC + 0x1000) +#define PLIC_MENABLE(hart) (PLIC + 0x2000 + (hart)*0x100) +#define PLIC_SENABLE(hart) (PLIC + 0x2080 + (hart)*0x100) +#define PLIC_MPRIORITY(hart) (PLIC + 0x200000 + (hart)*0x2000) +#define PLIC_SPRIORITY(hart) (PLIC + 0x201000 + (hart)*0x2000) +#define PLIC_MCLAIM(hart) (PLIC + 0x200004 + (hart)*0x2000) +#define PLIC_SCLAIM(hart) (PLIC + 0x201004 + (hart)*0x2000) +#define PLIC_MCOMPLETE(hart) (PLIC + 0x200004 + (hart)*0x2000) +#define PLIC_SCOMPLETE(hart) (PLIC + 0x201004 + (hart)*0x2000) + + +#define PLIC_GET_PRIO(irqno) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4)) +#define PLIC_SET_PRIO(irqno, prio) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4) = (prio)) + +#define MAX_CALLBACK_NUM 128 +typedef int (*irq_callback)(int irqno); + +void plic_irq_enable(int irqno); +void plic_irq_disable(int irqno); +int plic_prio_get(int irqno); +void plic_prio_set(int irqno, int prio); +int plic_register_callback(int irqno, irq_callback callback); +int plic_unregister_callback(int irqno); +int plic_init(void); +int plic_claim(void); +void plic_complete(int irqno); + +int plic_irq_intr(void); + +#endif + diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/trap.c b/ports/risc-v32/gnu/example_build/qemu_virt/trap.c new file mode 100644 index 00000000..a2733e02 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/qemu_virt/trap.c @@ -0,0 +1,67 @@ +#include "csr.h" +#include +#include "uart.h" +#include "hwtimer.h" +#include "plic.h" +#include +#include + +#define OS_IS_INTERUPT(mcause) (mcause & 0x80000000u) +#define OS_IS_EXCEPTION(mcause) (~(OS_IS_INTERUPT)) +#define OS_IS_TICK_INT(mcause) (mcause == 0x80000007u) +#define OS_IS_SOFT_INT(mcause) (mcause == 0x80000003u) +#define OS_IS_EXT_INT(mcause) (mcause == 0x8000000bu) +#define OS_IS_TRAP_USER(mcause) (mcause == 0x0000000bu) +extern void _tx_timer_interrupt(void); + +extern int uart_putc(int ch); + +static void print_hex(uintptr_t val) +{ + char digits[] = "0123456789ABCDEF"; + uart_putc('0'); + uart_putc('x'); + for(int i = (sizeof(uintptr_t)*2) - 1; i >= 0; i--) { + int d = (val >> (i*4)) & 0xF; + uart_putc(digits[d]); + } + uart_putc('\n'); +} + +void trap_handler(uintptr_t mcause, uintptr_t mepc, uintptr_t mtval) +{ + // uart_puts("DEBUG : threadx/ports/risc-v32/gnu/example_build/qemu_virt/trap.c, trap_handler\n"); + if(OS_IS_INTERUPT(mcause)) + { + if(OS_IS_TICK_INT(mcause)) + { + hwtimer_handler(); + _tx_timer_interrupt(); + } + else if(OS_IS_EXT_INT(mcause)) + { + int ret = plic_irq_intr(); + if(ret) + { + puts("[INTERRUPT]: handler irq error!"); + while(1) ; + } + } + else + { + puts("[INTERRUPT]: now can't deal with the interrupt!"); + while(1) ; + } + } + else + { + puts("[EXCEPTION] : Unkown Error!!"); + puts("mcause:"); + print_hex(mcause); + puts("mepc:"); + print_hex(mepc); + puts("mtval:"); + print_hex(mtval); + while(1) ; + } +} diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/tx_initialize_low_level.S b/ports/risc-v32/gnu/example_build/qemu_virt/tx_initialize_low_level.S new file mode 100644 index 00000000..62bb9abb --- /dev/null +++ b/ports/risc-v32/gnu/example_build/qemu_virt/tx_initialize_low_level.S @@ -0,0 +1,177 @@ +/*************************************************************************** + * Copyright (c) 2025 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#include "csr.h" +#include "tx_port.h" + + .section .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* trap_entry RISC-V32/GNU */ +/* 6.4.x */ +/* AUTHOR */ +/* */ +/* Akif Ejaz, 10xEngineers */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for riscv processor trap handle */ +/* It will do the contex save and call c trap_handler and do contex */ +/* load */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* trap_handler */ +/* */ +/* CALLED BY */ +/* */ +/* hardware exception */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 12-29-2025 Akif Ejaz Adapted for RV32 from RV64 port */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + .global trap_entry + .extern trap_handler + .extern _tx_thread_context_restore + trap_entry: +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, -65*REGBYTES // Allocate space for all registers - with floating point enabled +#else + addi sp, sp, -32*REGBYTES // Allocate space for all registers - without floating point enabled +#endif + + STORE x1, 28*REGBYTES(sp) // Store RA, 28*REGBYTES(because call will override ra [ra is a calle register in riscv]) + + call _tx_thread_context_save + + csrr a0, mcause + csrr a1, mepc + csrr a2, mtval + addi sp, sp, -4 + sw ra, 0(sp) + call trap_handler + lw ra, 0(sp) + addi sp, sp, 4 + call _tx_thread_context_restore + // it will nerver return +_err: + wfi + j _err + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level RISC-V32/GNU */ +/* 6.4.x */ +/* AUTHOR */ +/* */ +/* Akif Ejaz, 10xEngineers */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 12-29-2025 Akif Ejaz Adapted for RV32 from RV64 port */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ + .global _tx_initialize_low_level + .weak _tx_initialize_low_level + .extern _end + .extern board_init +_tx_initialize_low_level: + +/* debug print + .section .rodata +debug_str_init: + .string "DEBUG : threadx/ports/risc-v32/gnu/example_build/qemu_virt/tx_initialize_low_level.S, _tx_initialize_low_level\n" +*/ + .section .text + + la t0, _tx_thread_system_stack_ptr + sw sp, 0(t0) // Save system stack pointer + + la t0, _end // Pickup first free address + la t1, _tx_initialize_unused_memory + sw t0, 0(t1) // Save unused memory address + li t0, MSTATUS_MIE + csrrc zero, mstatus, t0 // clear MSTATUS_MIE bit + li t0, (MSTATUS_MPP_M | MSTATUS_MPIE ) + csrrs zero, mstatus, t0 // set MSTATUS_MPP, MPIE bit + li t0, (MIE_MTIE | MIE_MSIE | MIE_MEIE) + csrrs zero, mie, t0 // set mie +#ifdef __riscv_flen + li t0, MSTATUS_FS + csrrs zero, mstatus, t0 // set MSTATUS_FS bit to open f/d isa in riscv + fscsr x0 +#endif + addi sp, sp, -4 + sw ra, 0(sp) + call board_init +/* debug print + la a0, debug_str_init + call uart_puts +*/ + lw ra, 0(sp) + addi sp, sp, 4 + la t0, trap_entry + csrw mtvec, t0 + ret diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/uart.c b/ports/risc-v32/gnu/example_build/qemu_virt/uart.c new file mode 100644 index 00000000..a175b7d2 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/qemu_virt/uart.c @@ -0,0 +1,102 @@ +#include "uart.h" +#include "csr.h" +#include "plic.h" +#include + +// the UART control registers are memory-mapped +// at address UART0. this macro returns the +// address of one of the registers. +#define Reg(reg) ((volatile unsigned char *)(UART0 + (reg))) + +// the UART control registers. +// some have different meanings for +// read vs write. +// see http://byterunner.com/16550.html +#define RHR 0 // receive holding register (for input bytes) +#define THR 0 // transmit holding register (for output bytes) +#define IER 1 // interrupt enable register +#define IER_RX_ENABLE (1<<0) +#define IER_TX_ENABLE (1<<1) +#define FCR 2 // FIFO control register +#define FCR_FIFO_ENABLE (1<<0) +#define FCR_FIFO_CLEAR (3<<1) // clear the content of the two FIFOs +#define ISR 2 // interrupt status register +#define LCR 3 // line control register +#define LCR_EIGHT_BITS (3<<0) +#define LCR_BAUD_LATCH (1<<7) // special mode to set baud rate +#define LSR 5 // line status register +#define LSR_RX_READY (1<<0) // input is waiting to be read from RHR +#define LSR_TX_IDLE (1<<5) // THR can accept another character to send + +#define ReadReg(reg) (*(Reg(reg))) +#define WriteReg(reg, v) (*(Reg(reg)) = (v)) + +int uart_init(void) +{ + // disable interrupts. + WriteReg(IER, 0x00); + + // special mode to set baud rate. + WriteReg(LCR, LCR_BAUD_LATCH); + + // LSB for baud rate of 38.4K. + WriteReg(0, 0x03); + + // MSB for baud rate of 38.4K. + WriteReg(1, 0x00); + + // leave set-baud mode, + // and set word length to 8 bits, no parity. + WriteReg(LCR, LCR_EIGHT_BITS); + + // reset and enable FIFOs. + WriteReg(FCR, FCR_FIFO_ENABLE | FCR_FIFO_CLEAR); + + // enable transmit and receive interrupts. + // WriteReg(IER, IER_TX_ENABLE | IER_RX_ENABLE); + + //enable UART0 in PLIC + plic_irq_enable(UART0_IRQ); + + //set UART0 priority in PLIC + plic_prio_set(UART0_IRQ, 1); + + //register callback for UART0 + //plic_register_callback(UART0_IRQ, uart_intr); + puts("[UART0] : Uart Init Done, this is Test output!"); + return 0; +} + +void uart_putc_nolock(int ch) +{ + // wait for Transmit Holding Empty to be set in LSR. + while((ReadReg(LSR) & LSR_TX_IDLE) == 0) + ; + WriteReg(THR, ch); + return; +} + +int uart_putc(int ch) +{ + int intr_enable = riscv_mintr_get(); + riscv_mintr_off(); + uart_putc_nolock(ch); + riscv_mintr_restore(intr_enable); + return 1; +} + +int uart_puts(const char* str) +{ + int i; + int intr_enable = riscv_mintr_get(); + riscv_mintr_off(); + for(i=0;str[i]!=0;i++) + { + uart_putc_nolock(str[i]); + } + uart_putc_nolock('\n'); + riscv_mintr_restore(intr_enable); + return i; +} + + diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/uart.h b/ports/risc-v32/gnu/example_build/qemu_virt/uart.h new file mode 100644 index 00000000..19e8f73d --- /dev/null +++ b/ports/risc-v32/gnu/example_build/qemu_virt/uart.h @@ -0,0 +1,22 @@ +/*************************************************************************** + * Copyright (c) 2024 Microsoft Corporation + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#ifndef RISCV_UART_H +#define RISCV_UART_H + +#define UART0 0x10000000L +#define UART0_IRQ 10 + +#define puts uart_puts +int uart_init(void); +int uart_putc(int ch); +void uart_putc_nolock(int ch); +int uart_puts(const char* str); +#endif From a7961fe1909a5a15730f4fdf7cd5528f660ca756 Mon Sep 17 00:00:00 2001 From: Mehmet Eren Balasar Date: Tue, 6 Jan 2026 19:07:48 +0300 Subject: [PATCH 02/19] Fix VFP build failure in Cortex-A tx_thread_schedule.S When TX_ENABLE_VFP_SUPPORT is defined, the build fails due to missing IRQ_MASK and FIQ_MASK symbols in the restore logic. This adds the local definitions (0x80 and 0x40) to tx_thread_schedule.S to match tx_thread_interrupt_restore.S, enabling successful compilation on GNU and AC6 Cortex-A ports. --- ports/cortex_a12/ac6/src/tx_thread_schedule.S | 8 ++++++++ ports/cortex_a12/gnu/src/tx_thread_schedule.S | 8 ++++++++ ports/cortex_a15/ac6/src/tx_thread_schedule.S | 8 ++++++++ ports/cortex_a15/gnu/src/tx_thread_schedule.S | 8 ++++++++ ports/cortex_a17/ac6/src/tx_thread_schedule.S | 8 ++++++++ ports/cortex_a17/gnu/src/tx_thread_schedule.S | 8 ++++++++ ports/cortex_a5/ac6/src/tx_thread_schedule.S | 8 ++++++++ ports/cortex_a5/gnu/src/tx_thread_schedule.S | 8 ++++++++ ports/cortex_a7/ac6/src/tx_thread_schedule.S | 8 ++++++++ ports/cortex_a7/gnu/src/tx_thread_schedule.S | 8 ++++++++ ports/cortex_a8/ac6/src/tx_thread_schedule.S | 8 ++++++++ ports/cortex_a8/gnu/src/tx_thread_schedule.S | 8 ++++++++ ports/cortex_a9/ac6/src/tx_thread_schedule.S | 8 ++++++++ ports/cortex_a9/gnu/src/tx_thread_schedule.S | 8 ++++++++ 14 files changed, 112 insertions(+) diff --git a/ports/cortex_a12/ac6/src/tx_thread_schedule.S b/ports/cortex_a12/ac6/src/tx_thread_schedule.S index 07dd6f7f..54127015 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a12/ac6/src/tx_thread_schedule.S @@ -39,6 +39,14 @@ #define IRQ_MODE 0x12 // IRQ mode #define SVC_MODE 0x13 // SVC mode +#ifdef TX_ENABLE_VFP_SUPPORT +IRQ_MASK = 0x080 +#endif + +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif + /**************************************************************************/ /* */ /* FUNCTION RELEASE */ diff --git a/ports/cortex_a12/gnu/src/tx_thread_schedule.S b/ports/cortex_a12/gnu/src/tx_thread_schedule.S index 07dd6f7f..54127015 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a12/gnu/src/tx_thread_schedule.S @@ -39,6 +39,14 @@ #define IRQ_MODE 0x12 // IRQ mode #define SVC_MODE 0x13 // SVC mode +#ifdef TX_ENABLE_VFP_SUPPORT +IRQ_MASK = 0x080 +#endif + +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif + /**************************************************************************/ /* */ /* FUNCTION RELEASE */ diff --git a/ports/cortex_a15/ac6/src/tx_thread_schedule.S b/ports/cortex_a15/ac6/src/tx_thread_schedule.S index 07dd6f7f..54127015 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a15/ac6/src/tx_thread_schedule.S @@ -39,6 +39,14 @@ #define IRQ_MODE 0x12 // IRQ mode #define SVC_MODE 0x13 // SVC mode +#ifdef TX_ENABLE_VFP_SUPPORT +IRQ_MASK = 0x080 +#endif + +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif + /**************************************************************************/ /* */ /* FUNCTION RELEASE */ diff --git a/ports/cortex_a15/gnu/src/tx_thread_schedule.S b/ports/cortex_a15/gnu/src/tx_thread_schedule.S index 07dd6f7f..54127015 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a15/gnu/src/tx_thread_schedule.S @@ -39,6 +39,14 @@ #define IRQ_MODE 0x12 // IRQ mode #define SVC_MODE 0x13 // SVC mode +#ifdef TX_ENABLE_VFP_SUPPORT +IRQ_MASK = 0x080 +#endif + +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif + /**************************************************************************/ /* */ /* FUNCTION RELEASE */ diff --git a/ports/cortex_a17/ac6/src/tx_thread_schedule.S b/ports/cortex_a17/ac6/src/tx_thread_schedule.S index 07dd6f7f..54127015 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a17/ac6/src/tx_thread_schedule.S @@ -39,6 +39,14 @@ #define IRQ_MODE 0x12 // IRQ mode #define SVC_MODE 0x13 // SVC mode +#ifdef TX_ENABLE_VFP_SUPPORT +IRQ_MASK = 0x080 +#endif + +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif + /**************************************************************************/ /* */ /* FUNCTION RELEASE */ diff --git a/ports/cortex_a17/gnu/src/tx_thread_schedule.S b/ports/cortex_a17/gnu/src/tx_thread_schedule.S index 07dd6f7f..54127015 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a17/gnu/src/tx_thread_schedule.S @@ -39,6 +39,14 @@ #define IRQ_MODE 0x12 // IRQ mode #define SVC_MODE 0x13 // SVC mode +#ifdef TX_ENABLE_VFP_SUPPORT +IRQ_MASK = 0x080 +#endif + +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif + /**************************************************************************/ /* */ /* FUNCTION RELEASE */ diff --git a/ports/cortex_a5/ac6/src/tx_thread_schedule.S b/ports/cortex_a5/ac6/src/tx_thread_schedule.S index 07dd6f7f..54127015 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a5/ac6/src/tx_thread_schedule.S @@ -39,6 +39,14 @@ #define IRQ_MODE 0x12 // IRQ mode #define SVC_MODE 0x13 // SVC mode +#ifdef TX_ENABLE_VFP_SUPPORT +IRQ_MASK = 0x080 +#endif + +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif + /**************************************************************************/ /* */ /* FUNCTION RELEASE */ diff --git a/ports/cortex_a5/gnu/src/tx_thread_schedule.S b/ports/cortex_a5/gnu/src/tx_thread_schedule.S index 07dd6f7f..54127015 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a5/gnu/src/tx_thread_schedule.S @@ -39,6 +39,14 @@ #define IRQ_MODE 0x12 // IRQ mode #define SVC_MODE 0x13 // SVC mode +#ifdef TX_ENABLE_VFP_SUPPORT +IRQ_MASK = 0x080 +#endif + +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif + /**************************************************************************/ /* */ /* FUNCTION RELEASE */ diff --git a/ports/cortex_a7/ac6/src/tx_thread_schedule.S b/ports/cortex_a7/ac6/src/tx_thread_schedule.S index 07dd6f7f..54127015 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a7/ac6/src/tx_thread_schedule.S @@ -39,6 +39,14 @@ #define IRQ_MODE 0x12 // IRQ mode #define SVC_MODE 0x13 // SVC mode +#ifdef TX_ENABLE_VFP_SUPPORT +IRQ_MASK = 0x080 +#endif + +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif + /**************************************************************************/ /* */ /* FUNCTION RELEASE */ diff --git a/ports/cortex_a7/gnu/src/tx_thread_schedule.S b/ports/cortex_a7/gnu/src/tx_thread_schedule.S index 07dd6f7f..54127015 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a7/gnu/src/tx_thread_schedule.S @@ -39,6 +39,14 @@ #define IRQ_MODE 0x12 // IRQ mode #define SVC_MODE 0x13 // SVC mode +#ifdef TX_ENABLE_VFP_SUPPORT +IRQ_MASK = 0x080 +#endif + +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif + /**************************************************************************/ /* */ /* FUNCTION RELEASE */ diff --git a/ports/cortex_a8/ac6/src/tx_thread_schedule.S b/ports/cortex_a8/ac6/src/tx_thread_schedule.S index 07dd6f7f..54127015 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a8/ac6/src/tx_thread_schedule.S @@ -39,6 +39,14 @@ #define IRQ_MODE 0x12 // IRQ mode #define SVC_MODE 0x13 // SVC mode +#ifdef TX_ENABLE_VFP_SUPPORT +IRQ_MASK = 0x080 +#endif + +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif + /**************************************************************************/ /* */ /* FUNCTION RELEASE */ diff --git a/ports/cortex_a8/gnu/src/tx_thread_schedule.S b/ports/cortex_a8/gnu/src/tx_thread_schedule.S index 07dd6f7f..54127015 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a8/gnu/src/tx_thread_schedule.S @@ -39,6 +39,14 @@ #define IRQ_MODE 0x12 // IRQ mode #define SVC_MODE 0x13 // SVC mode +#ifdef TX_ENABLE_VFP_SUPPORT +IRQ_MASK = 0x080 +#endif + +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif + /**************************************************************************/ /* */ /* FUNCTION RELEASE */ diff --git a/ports/cortex_a9/ac6/src/tx_thread_schedule.S b/ports/cortex_a9/ac6/src/tx_thread_schedule.S index 07dd6f7f..54127015 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a9/ac6/src/tx_thread_schedule.S @@ -39,6 +39,14 @@ #define IRQ_MODE 0x12 // IRQ mode #define SVC_MODE 0x13 // SVC mode +#ifdef TX_ENABLE_VFP_SUPPORT +IRQ_MASK = 0x080 +#endif + +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif + /**************************************************************************/ /* */ /* FUNCTION RELEASE */ diff --git a/ports/cortex_a9/gnu/src/tx_thread_schedule.S b/ports/cortex_a9/gnu/src/tx_thread_schedule.S index 07dd6f7f..54127015 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a9/gnu/src/tx_thread_schedule.S @@ -39,6 +39,14 @@ #define IRQ_MODE 0x12 // IRQ mode #define SVC_MODE 0x13 // SVC mode +#ifdef TX_ENABLE_VFP_SUPPORT +IRQ_MASK = 0x080 +#endif + +#ifdef TX_ENABLE_FIQ_SUPPORT +FIQ_MASK = 0x040 +#endif + /**************************************************************************/ /* */ /* FUNCTION RELEASE */ From b443c0fe2d44b3bd46932f0b444f7830903618bd Mon Sep 17 00:00:00 2001 From: Sebastian Paarz Date: Tue, 11 Mar 2025 23:54:43 +0100 Subject: [PATCH 03/19] Added missing ULONG64 definition for RX ports --- ports/rxv1/ccrx/inc/tx_port.h | 2 ++ ports/rxv1/gnu/inc/tx_port.h | 2 ++ ports/rxv1/iar/inc/tx_port.h | 2 ++ ports/rxv2/ccrx/inc/tx_port.h | 2 ++ ports/rxv2/gnu/inc/tx_port.h | 2 ++ ports/rxv2/iar/inc/tx_port.h | 2 ++ ports/rxv3/ccrx/inc/tx_port.h | 2 ++ ports/rxv3/gnu/inc/tx_port.h | 2 ++ ports/rxv3/iar/inc/tx_port.h | 2 ++ 9 files changed, 18 insertions(+) diff --git a/ports/rxv1/ccrx/inc/tx_port.h b/ports/rxv1/ccrx/inc/tx_port.h index e729a7bb..abd67538 100644 --- a/ports/rxv1/ccrx/inc/tx_port.h +++ b/ports/rxv1/ccrx/inc/tx_port.h @@ -82,8 +82,10 @@ typedef int INT; typedef unsigned int UINT; typedef long LONG; typedef unsigned long ULONG; +typedef unsigned long long ULONG64; typedef short SHORT; typedef unsigned short USHORT; +#define ULONG64_DEFINED /* Define interrupt control options. */ diff --git a/ports/rxv1/gnu/inc/tx_port.h b/ports/rxv1/gnu/inc/tx_port.h index a0a79f76..8321ae85 100644 --- a/ports/rxv1/gnu/inc/tx_port.h +++ b/ports/rxv1/gnu/inc/tx_port.h @@ -84,8 +84,10 @@ typedef int INT; typedef unsigned int UINT; typedef long LONG; typedef unsigned long ULONG; +typedef unsigned long long ULONG64; typedef short SHORT; typedef unsigned short USHORT; +#define ULONG64_DEFINED /* Define interrupt control options. */ diff --git a/ports/rxv1/iar/inc/tx_port.h b/ports/rxv1/iar/inc/tx_port.h index 1befd176..f052bbb7 100644 --- a/ports/rxv1/iar/inc/tx_port.h +++ b/ports/rxv1/iar/inc/tx_port.h @@ -85,8 +85,10 @@ typedef int INT; typedef unsigned int UINT; typedef long LONG; typedef unsigned long ULONG; +typedef unsigned long long ULONG64; typedef short SHORT; typedef unsigned short USHORT; +#define ULONG64_DEFINED /* Define interrupt control options. */ diff --git a/ports/rxv2/ccrx/inc/tx_port.h b/ports/rxv2/ccrx/inc/tx_port.h index e003c9a9..f9ef4a91 100644 --- a/ports/rxv2/ccrx/inc/tx_port.h +++ b/ports/rxv2/ccrx/inc/tx_port.h @@ -84,8 +84,10 @@ typedef int INT; typedef unsigned int UINT; typedef long LONG; typedef unsigned long ULONG; +typedef unsigned long long ULONG64; typedef short SHORT; typedef unsigned short USHORT; +#define ULONG64_DEFINED /* Define interrupt control options. */ diff --git a/ports/rxv2/gnu/inc/tx_port.h b/ports/rxv2/gnu/inc/tx_port.h index d796e600..73662111 100644 --- a/ports/rxv2/gnu/inc/tx_port.h +++ b/ports/rxv2/gnu/inc/tx_port.h @@ -86,8 +86,10 @@ typedef int INT; typedef unsigned int UINT; typedef long LONG; typedef unsigned long ULONG; +typedef unsigned long long ULONG64; typedef short SHORT; typedef unsigned short USHORT; +#define ULONG64_DEFINED /* Define interrupt control options. */ diff --git a/ports/rxv2/iar/inc/tx_port.h b/ports/rxv2/iar/inc/tx_port.h index 97907737..709d4c0e 100644 --- a/ports/rxv2/iar/inc/tx_port.h +++ b/ports/rxv2/iar/inc/tx_port.h @@ -87,8 +87,10 @@ typedef int INT; typedef unsigned int UINT; typedef long LONG; typedef unsigned long ULONG; +typedef unsigned long long ULONG64; typedef short SHORT; typedef unsigned short USHORT; +#define ULONG64_DEFINED /* Define interrupt control options. */ diff --git a/ports/rxv3/ccrx/inc/tx_port.h b/ports/rxv3/ccrx/inc/tx_port.h index 62c637e3..86a29a9b 100644 --- a/ports/rxv3/ccrx/inc/tx_port.h +++ b/ports/rxv3/ccrx/inc/tx_port.h @@ -83,8 +83,10 @@ typedef int INT; typedef unsigned int UINT; typedef long LONG; typedef unsigned long ULONG; +typedef unsigned long long ULONG64; typedef short SHORT; typedef unsigned short USHORT; +#define ULONG64_DEFINED /* Define interrupt control options. */ diff --git a/ports/rxv3/gnu/inc/tx_port.h b/ports/rxv3/gnu/inc/tx_port.h index 765d7061..70ff629c 100644 --- a/ports/rxv3/gnu/inc/tx_port.h +++ b/ports/rxv3/gnu/inc/tx_port.h @@ -85,8 +85,10 @@ typedef int INT; typedef unsigned int UINT; typedef long LONG; typedef unsigned long ULONG; +typedef unsigned long long ULONG64; typedef short SHORT; typedef unsigned short USHORT; +#define ULONG64_DEFINED /* Define interrupt control options. */ diff --git a/ports/rxv3/iar/inc/tx_port.h b/ports/rxv3/iar/inc/tx_port.h index 1408a93e..624fec4d 100644 --- a/ports/rxv3/iar/inc/tx_port.h +++ b/ports/rxv3/iar/inc/tx_port.h @@ -86,8 +86,10 @@ typedef int INT; typedef unsigned int UINT; typedef long LONG; typedef unsigned long ULONG; +typedef unsigned long long ULONG64; typedef short SHORT; typedef unsigned short USHORT; +#define ULONG64_DEFINED /* Define interrupt control options. */ From 6c25effb405cc694578dec664a798fc8af3107e1 Mon Sep 17 00:00:00 2001 From: Akif Ejaz Date: Mon, 26 Jan 2026 15:48:46 +0500 Subject: [PATCH 04/19] improve port robustness, portability, and CSR handling - removed tx_port.h dependency from .S files - replaced tx_timer_interrupt.c with tx_timer_interrupt.S - made some cleanups, formatting to better readability - removed macros (LOAD/STORE/REGBYTES) changed register nomenclature to use RISC-V ABI names (ra, sp, t0, etc.) - added readme_threadx.txt Signed-off-by: Akif Ejaz --- ports/risc-v64/gnu/CMakeLists.txt | 2 +- ports/risc-v64/gnu/inc/tx_port.h | 52 +-- ports/risc-v64/gnu/readme_threadx.txt | 430 ++++++++++++++++++ .../gnu/src/tx_initialize_low_level.S | 66 +-- .../gnu/src/tx_thread_context_restore.S | 425 +++++++++-------- .../risc-v64/gnu/src/tx_thread_context_save.S | 373 ++++++++------- .../gnu/src/tx_thread_interrupt_control.S | 22 +- ports/risc-v64/gnu/src/tx_thread_schedule.S | 348 +++++++------- .../risc-v64/gnu/src/tx_thread_stack_build.S | 152 +++---- .../gnu/src/tx_thread_system_return.S | 121 +++-- ports/risc-v64/gnu/src/tx_timer_interrupt.S | 210 +++++++++ ports/risc-v64/gnu/src/tx_timer_interrupt.c | 134 ------ 12 files changed, 1466 insertions(+), 869 deletions(-) create mode 100644 ports/risc-v64/gnu/readme_threadx.txt create mode 100644 ports/risc-v64/gnu/src/tx_timer_interrupt.S delete mode 100644 ports/risc-v64/gnu/src/tx_timer_interrupt.c diff --git a/ports/risc-v64/gnu/CMakeLists.txt b/ports/risc-v64/gnu/CMakeLists.txt index b217065d..9357c697 100644 --- a/ports/risc-v64/gnu/CMakeLists.txt +++ b/ports/risc-v64/gnu/CMakeLists.txt @@ -9,7 +9,7 @@ target_sources(${PROJECT_NAME} ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S # {{END_TARGET_SOURCES}} ) diff --git a/ports/risc-v64/gnu/inc/tx_port.h b/ports/risc-v64/gnu/inc/tx_port.h index 855ecf82..346083e5 100644 --- a/ports/risc-v64/gnu/inc/tx_port.h +++ b/ports/risc-v64/gnu/inc/tx_port.h @@ -53,26 +53,6 @@ #ifndef TX_PORT_H #define TX_PORT_H -#ifdef __ASSEMBLER__ - - -#if __riscv_xlen == 64 -# define SLL32 sllw -# define STORE sd -# define LOAD ld -# define LWU lwu -# define LOG_REGBYTES 3 -#else -# define SLL32 sll -# define STORE sw -# define LOAD lw -# define LWU lw -# define LOG_REGBYTES 2 -#endif -#define REGBYTES (1 << LOG_REGBYTES) - -#else /*not __ASSEMBLER__ */ - /* Include for memset. */ #include @@ -86,10 +66,7 @@ alternately be defined on the command line. */ #include "tx_user.h" -#endif - - -/* Define compiler library include files. */ +#endif /* TX_INCLUDE_USER_DEFINE_FILE */ /* Define ThreadX basic types for this port. */ @@ -105,8 +82,6 @@ typedef unsigned long long ULONG64; typedef short SHORT; typedef unsigned short USHORT; #define ULONG64_DEFINED -#define ALIGN_TYPE_DEFINED -#define ALIGN_TYPE ULONG64 @@ -253,25 +228,25 @@ typedef unsigned short USHORT; is used to define a local function save area for the disable and restore macros. */ +/* Expose helper used to perform an atomic read/modify/write of mstatus. + The helper composes and returns the posture per ThreadX contract. */ +UINT _tx_thread_interrupt_control(UINT new_posture); + #ifdef TX_DISABLE_INLINE -ULONG64 _tx_thread_interrupt_control(unsigned int new_posture); - -#define TX_INTERRUPT_SAVE_AREA register ULONG64 interrupt_save; +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); #define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); #else -#define TX_INTERRUPT_SAVE_AREA ULONG64 interrupt_save; -/* Atomically read mstatus into interrupt_save and clear bit 3 of mstatus. */ -#define TX_DISABLE {__asm__ ("csrrci %0, mstatus, 0x08" : "=r" (interrupt_save) : );}; -/* We only care about mstatus.mie (bit 3), so mask interrupt_save and write to mstatus. */ -#define TX_RESTORE {register ULONG64 __tempmask = interrupt_save & 0x08; \ - __asm__ ("csrrs x0, mstatus, %0 \n\t" : : "r" (__tempmask) : );}; +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; -#endif +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); +#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); + +#endif /* TX_DISABLE_INLINE */ /* Define the interrupt lockout macros for each ThreadX object. */ @@ -291,7 +266,6 @@ CHAR _tx_version_id[] = "Copyright (c) 2024 Microsoft Corporation. * ThreadX RISC-V64/GNU Version 6.4.2 *"; #else extern CHAR _tx_version_id[]; -#endif +#endif /* TX_THREAD_INIT */ -#endif /*not __ASSEMBLER__ */ -#endif +#endif /* TX_PORT_H */ diff --git a/ports/risc-v64/gnu/readme_threadx.txt b/ports/risc-v64/gnu/readme_threadx.txt new file mode 100644 index 00000000..60854ecd --- /dev/null +++ b/ports/risc-v64/gnu/readme_threadx.txt @@ -0,0 +1,430 @@ + Eclipse Foundation's RTOS, ThreadX for RISC-V64 + + Using the GNU Tools + + +1. Building the ThreadX run-time Library + +Prerequisites +- Install a RISC-V64 bare-metal GNU toolchain with riscv64-unknown-elf prefix +- Common source: https://github.com/riscv-collab/riscv-gnu-toolchain + +Verify the toolchain: + riscv64-unknown-elf-gcc --version + riscv64-unknown-elf-objdump --version + +CMake-based build (recommended) + +From the ThreadX top-level directory: + + cmake -Bbuild -GNinja -DCMAKE_TOOLCHAIN_FILE=cmake/riscv64_gnu.cmake . + cmake --build ./build/ + +This uses cmake/riscv64_gnu.cmake and ports/risc-v64/gnu/CMakeLists.txt to +configure the cross-compiler flags and produce the ThreadX run-time library +and example binaries. + +Example build script + +The example demonstration contains a build script. See: + + ports/risc-v64/gnu/example_build/qemu_virt/build_libthreadx.sh + +This script builds the library and the demo application kernel.elf. + + +2. Demonstration System (QEMU) + +The provided example is targeted at QEMU's virt platform. After building the +example, the produced kernel.elf can be executed in QEMU: + + qemu-system-riscv64 -nographic -smp 1 -bios none -m 128M -machine virt -kernel kernel.elf + +Typical QEMU features used: +- Single-core CPU +- UART serial console +- PLIC (Platform-Level Interrupt Controller) +- CLINT (Core-Local Interruptor) for timer + + +3. System Initialization + +Entry Point + +The example startup code begins at the _start label in entry.s. This startup +code performs hardware initialization including: +- Check hart ID (only hart 0 continues; others enter WFI loop) +- Zero general-purpose registers +- Set up initial stack pointer +- Clear BSS section +- Jump to main() + +Low-Level Port Initialization (tx_initialize_low_level.S) + +The _tx_initialize_low_level function: +- Saves the system stack pointer to _tx_thread_system_stack_ptr +- Records first free RAM address from __tx_free_memory_start symbol +- Initializes floating-point control/status register (FCSR) if floating point enabled + +Board Initialization (board.c) + +After tx_initialize_low_level returns, main() calls board_init() to: +- Initialize PLIC (Platform-Level Interrupt Controller) +- Initialize UART +- Initialize hardware timer (CLINT) +- Set trap vector (mtvec) to point to trap handler + + +4. Register Usage and Stack Frames + +The RISC-V64 ABI defines t0-t6 and a0-a7 as caller-saved (scratch) registers. +All other registers used by a function must be preserved by the function. + +ThreadX takes advantage of this: when a context switch happens during a +function call, only the non-scratch registers need to be saved. + +Stack Frame Types + +Two types of stack frames exist: + +A. Interrupt Frame (stack type = 1) + Created when an interrupt occurs during thread execution. + Saves all registers including caller-saved registers. + Size: 65*8 = 520 bytes (with FP), or 32*8 = 256 bytes (without FP) + +B. Solicited Frame (stack type = 0) + Created when a thread voluntarily yields via ThreadX service calls. + Saves only callee-saved registers (s0-s11) and mstatus. + Size: 29*8 = 232 bytes (with FP), or 16*8 = 128 bytes (without FP) + + +Stack Layout for Interrupt Frame (with FP enabled): + + Index Offset Register Description + ───────────────────────────────────────────────── + 0 0x00 -- Stack type (1 = interrupt) + 1 0x08 s11 Preserved register + 2 0x10 s10 Preserved register + 3 0x18 s9 Preserved register + 4 0x20 s8 Preserved register + 5 0x28 s7 Preserved register + 6 0x30 s6 Preserved register + 7 0x38 s5 Preserved register + 8 0x40 s4 Preserved register + 9 0x48 s3 Preserved register + 10 0x50 s2 Preserved register + 11 0x58 s1 Preserved register + 12 0x60 s0 Preserved register + 13 0x68 t6 Scratch register + 14 0x70 t5 Scratch register + 15 0x78 t4 Scratch register + 16 0x80 t3 Scratch register + 17 0x88 t2 Scratch register + 18 0x90 t1 Scratch register + 19 0x98 t0 Scratch register + 20 0xA0 a7 Argument register + 21 0xA8 a6 Argument register + 22 0xB0 a5 Argument register + 23 0xB8 a4 Argument register + 24 0xC0 a3 Argument register + 25 0xC8 a2 Argument register + 26 0xD0 a1 Argument register + 27 0xD8 a0 Argument register + 28 0xE0 ra Return address + 29 0xE8 -- Reserved + 30 0xF0 mepc Machine exception PC + 31-46 0xF8-0x168 fs0-fs7 Preserved FP registers + 47-62 0x170-0x210 ft0-ft11 Scratch FP registers + 63 0x218 fcsr FP control/status register + ───────────────────────────────────────────────── + + +5. Interrupt Handling + +Machine Mode Operation + +ThreadX operates in machine mode (M-mode), the highest privilege level. +All interrupts and exceptions trap to machine mode. + +Interrupt Sources + +1. Machine Timer Interrupt (MTI): + - Triggered by CLINT when mtime >= mtimecmp + - Handled by _tx_timer_interrupt (src/tx_timer_interrupt.S) + - Called from trap handler in trap.c + +2. External Interrupts (MEI): + - Routed through PLIC + - Handler in trap.c calls registered ISR callbacks + +3. Software Interrupts (MSI): + - Supported but not actively used in this port + +Interrupt Flow + +1. Hardware trap entry (automatic): + - mepc <- PC (address of interrupted instruction) + - mcause <- exception/interrupt code + - mstatus.MPIE <- mstatus.MIE (save interrupt-enable state) + - mstatus.MIE <- 0 (disable interrupts) + - mstatus.MPP <- Machine mode + - PC <- mtvec (points to trap_entry in entry.s) + +2. Trap entry (entry.s): + - Allocates interrupt stack frame (32*8 or 65*8 bytes depending on FP) + - Saves RA (x1) on stack + - Calls _tx_thread_context_save + +3. Context save (_tx_thread_context_save.S): + - Increments _tx_thread_system_state (nested interrupt counter) + - If nested interrupt: saves remaining registers and returns to ISR + - If first interrupt: saves full context, switches to system stack + +4. Trap handler (trap.c): + - Examines mcause to determine interrupt type + - Dispatches to appropriate handler (_tx_timer_interrupt or PLIC handler) + - Returns to context restore + +5. Context restore (_tx_thread_context_restore.S): + - Decrements _tx_thread_system_state + - Checks if preemption needed + - Restores thread context or switches to next ready thread via scheduler + - Returns to interrupted thread or executes new thread + + +Interrupt Control Macros + +TX_DISABLE and TX_RESTORE macros atomically manage the MIE bit in mstatus: + + TX_DISABLE: Saves and clears MIE bit via csrrci (CSR read-clear immediate) + TX_RESTORE: Restores only MIE bit via csrrs (CSR read-set) + Other mstatus bits remain unchanged + +These are defined in ports/risc-v64/gnu/inc/tx_port.h and use the +_tx_thread_interrupt_control() function. + + +6. Thread Scheduling and Context Switching + +Thread Scheduler (src/tx_thread_schedule.S) + +The scheduler: +1. Enables interrupts while waiting for next thread +2. Spins until _tx_thread_execute_ptr becomes non-NULL +3. Disables interrupts (critical section) +4. Sets _tx_thread_current_ptr = _tx_thread_execute_ptr +5. Increments thread's run count +6. Switches to thread's stack +7. Determines stack frame type and restores context: + - Interrupt frame: full context restored, returns via mret + - Solicited frame: minimal context restored, returns via ret + +Initial Thread Stack Frame (src/tx_thread_stack_build.S) + +New threads start with a fake interrupt frame containing: +- All registers initialized to 0 +- ra (x1) = 0 +- mepc = entry function pointer +- Stack type = 1 (interrupt frame) +- Floating-point registers initialized based on ABI + + +7. Port Configuration and Macros + +Default Configurations (in ports/risc-v64/gnu/inc/tx_port.h): + + TX_MINIMUM_STACK 1024 /* Minimum thread stack size */ + TX_TIMER_THREAD_STACK_SIZE 1024 /* Timer thread stack size */ + TX_TIMER_THREAD_PRIORITY 0 /* Timer thread priority */ + TX_MAX_PRIORITIES 32 /* Must be multiple of 32 */ + +These can be overridden in tx_user.h or on the compiler command line. + + +8. Build Configuration + +CMake Toolchain File: cmake/riscv64_gnu.cmake + +Compiler Flags: + -march=rv64gc RV64 with IMAFD+C extensions + -mabi=lp64d 64-bit integers/pointers, double-precision FP in registers + -mcmodel=medany ±2GB addressability + -D__ASSEMBLER__ For assembly files + +ABI Selection + +The port uses lp64d ABI which includes: +- 64-bit integers and pointers +- Double-precision floating-point arguments in registers +- Floating-point registers f0-f31 + +When building with floating-point ABI: +- FP registers and FCSR are saved/restored in context switches +- Stack frames expand from 32*REGBYTES to 65*REGBYTES +- Conditional compilation uses __riscv_float_abi_double + + +9. File Organization + +Port-specific files (ports/risc-v64/gnu/): + +Core assembly files (src/): + - tx_initialize_low_level.S Initial setup and system state + - tx_thread_context_save.S Save context on interrupt entry + - tx_thread_context_restore.S Restore context on interrupt exit + - tx_thread_schedule.S Thread scheduler + - tx_thread_system_return.S Solicited context save for voluntary yield + - tx_thread_stack_build.S Build initial stack frame for new thread + - tx_thread_interrupt_control.S Interrupt enable/disable control + - tx_timer_interrupt.S Timer interrupt handler + +Header file (inc/): + - tx_port.h Port-specific defines and macros + +Example files (example_build/qemu_virt/): + - entry.s Startup code, trap entry point + - board.c, uart.c, hwtimer.c Platform-specific initialization + - plic.c PLIC interrupt controller driver + - trap.c Trap/exception dispatcher + - link.lds Linker script for QEMU virt + - build_libthreadx.sh Build script + + +10. Linker Script Requirements + +The linker script must provide: + +1. Entry point: + ENTRY(_start) + +2. Memory layout: + - .text section (code) + - .rodata section (read-only data) + - .data section (initialized data) + - .bss section (uninitialized data) + +3. Symbols: + - _end: First free memory address (used by ThreadX allocation) + - _bss_start, _bss_end: For zero initialization + - Initial stack space (example: 4KB) + +4. Alignment: + - 16-byte alignment throughout (RISC-V64 requirement) + +Example from QEMU virt build: + + SECTIONS + { + . = 0x80000000; /* QEMU virt base address */ + + .text : { *(.text .text.*) } + .rodata : { *(.rodata .rodata.*) } + .data : { *(.data .data.*) } + .bss : { *(.bss .bss.*) } + + .stack : { + . = ALIGN(4096); + _sysstack_start = .; + . += 0x1000; /* 4KB initial stack */ + _sysstack_end = .; + } + + PROVIDE(_end = .); + } + + +11. Floating-Point Support + +When building with lp64d ABI and FP enabled: + +- FP registers f0-f31 and FCSR are saved/restored during context switches +- Stack frames increase from 32*REGBYTES to 65*REGBYTES (256 to 520 bytes) +- MSTATUS.FS (floating-point state) field is set to indicate dirty FP state + +Stack frame differences: +- Without FP: 32*8 = 256 bytes (interrupt), 16*8 = 128 bytes (solicited) +- With FP: 65*8 = 520 bytes (interrupt), 29*8 = 232 bytes (solicited) + + +12. Performance and Debugging + +Performance Optimization + +Build optimizations: +- Use -O2 or -O3 for production (example uses -O0 for debugging) +- Enable -Wl,--gc-sections to remove unused code +- Define TX_DISABLE_ERROR_CHECKING to remove parameter checks +- Consider -flto for link-time optimization + +Debugging with QEMU and GDB + +Start QEMU in debug mode: + qemu-system-riscv64 -nographic -smp 1 -bios none -m 128M \ + -machine virt -kernel kernel.elf -s -S + + -s: Enable GDB server on TCP port 1234 + -S: Pause at startup waiting for GDB + +Connect GDB: + riscv64-unknown-elf-gdb kernel.elf + (gdb) target remote :1234 + (gdb) break main + (gdb) continue + +Useful GDB commands: + (gdb) info registers # View general registers + (gdb) info all-registers # Include CSR and FP registers + (gdb) p/x $mstatus # View machine status register + (gdb) x/32gx $sp # Examine stack memory + (gdb) p *_tx_thread_current_ptr # View current thread control block + + +13. Platform-Specific Notes (QEMU virt) + +PLIC Configuration + +The PLIC (Platform-Level Interrupt Controller) is memory-mapped at 0x0C000000: + +- Enables up to 1024 interrupt sources +- Supports priority levels 0-7 (0 = disabled) +- Requires per-hart priority threshold and enable register configuration + +Example PLIC usage (from plic.c): + plic_irq_enable(irq_number); # Enable specific interrupt + plic_prio_set(irq_number, priority);# Set priority level + +CLINT Configuration + +The CLINT (Core-Local Interruptor) is memory-mapped at 0x02000000: + +- CLINT_MSIP(hartid): 0x0000 + 4*hartid (software interrupt) +- CLINT_MTIMECMP(hartid): 0x4000 + 8*hartid (timer compare) +- CLINT_MTIME: 0xBFF8 (timer value, read-only) + +Timer frequency is platform-dependent (example uses 10MHz). + +Multi-Core Considerations + +The current port is single-core focused: +- Only hart 0 continues from reset; others enter WFI loop +- _tx_thread_system_state is a global variable +- No per-hart data structures + + +14. Revision History + +For generic code revision information, refer to readme_threadx_generic.txt. + +The following details the revision history for this RISC-V64 GNU port: + +01-26-2026 Akif Ejaz Comprehensive rewrite with accurate + technical details matching implementation, + register naming per RISC-V ABI, and + complete interrupt flow documentation + +03-08-2023 Scott Larson Initial Version 6.2.1 + + +Copyright (c) 1996-2026 Microsoft Corporation + +https://azure.com/rtos diff --git a/ports/risc-v64/gnu/src/tx_initialize_low_level.S b/ports/risc-v64/gnu/src/tx_initialize_low_level.S index ccafd5e2..68150c18 100644 --- a/ports/risc-v64/gnu/src/tx_initialize_low_level.S +++ b/ports/risc-v64/gnu/src/tx_initialize_low_level.S @@ -71,41 +71,45 @@ __tx_free_memory_start: .global _tx_initialize_low_level .weak _tx_initialize_low_level _tx_initialize_low_level: - sd sp, _tx_thread_system_stack_ptr, t0 // Save system stack pointer + /* Save the system stack pointer. */ + /* _tx_thread_system_stack_ptr = sp; */ + la t0, _tx_thread_system_stack_ptr + sd sp, 0(t0) /* Save system stack pointer */ - la t0, __tx_free_memory_start // Pickup first free address - sd t0, _tx_initialize_unused_memory, t1 // Save unused memory address + /* Pickup first free address. */ + /* _tx_initialize_unused_memory(__tx_free_memory_start); */ + la t0, __tx_free_memory_start /* Pickup first free address */ + la t1, _tx_initialize_unused_memory + sd t0, 0(t1) /* Save unused memory address */ + /* Initialize floating point control/status register if floating point is enabled. */ #ifdef __riscv_flen - fscsr x0 + li t0, 0 + csrw fcsr, t0 /* Clear FP control/status register */ #endif ret - - /* Define the actual timer interrupt/exception handler. */ - - .global timer1_plic_IRQHandler - //.global __minterrupt_000007 - //EXTWEAK __require_minterrupt_vector_table -timer1_plic_IRQHandler: -//__minterrupt_000007: - //REQUIRE __require_minterrupt_vector_table - - - /* Before calling _tx_thread_context_save, we have to allocate an interrupt - stack frame and save the current value of x1 (ra). */ -//#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) -// addi sp, sp, -520 // Allocate space for all registers - with floating point enabled -//#else -// addi sp, sp, -256 // Allocate space for all registers - without floating point enabled -//#endif -// sd x1, 224(sp) // Store RA -// call _tx_thread_context_save // Call ThreadX context save - - /* Call the ThreadX timer routine. */ - call _tx_timer_interrupt // Call timer interrupt handler - call timer1_interrupt - ret - /* Timer interrupt processing is done, jump to ThreadX context restore. */ -// j _tx_thread_context_restore // Jump to ThreadX context restore function. Note: this does not return! +/* Timer Interrupt Handler Note: + Platform-specific implementations must provide their own timer ISR. + The timer interrupt handler should follow this execution flow: + + 1. Disable interrupts (if not done by hardware exception entry) + 2. Allocate interrupt stack frame (65*8 bytes with FP, 32*8 bytes without) + 3. Save RA (x1) on the stack at offset 28*8 + 4. Call _tx_thread_context_save to save thread context + 5. Call _tx_timer_interrupt to process the timer tick + 6. Call _tx_thread_context_restore to resume execution (does not return) + + Example (for CLINT timer): + + _tx_timer_interrupt_handler: + addi sp, sp, -32*8 + sd ra, 28*8(sp) + call _tx_thread_context_save + call _tx_timer_interrupt + j _tx_thread_context_restore + + The port assumes Machine mode (M-mode) execution. + For Supervisor mode (S-mode), use sstatus and SIE/SPIE instead of mstatus. + See the RISC-V Privileged Specification for more details. */ diff --git a/ports/risc-v64/gnu/src/tx_thread_context_restore.S b/ports/risc-v64/gnu/src/tx_thread_context_restore.S index d805a59c..edacb8b6 100644 --- a/ports/risc-v64/gnu/src/tx_thread_context_restore.S +++ b/ports/risc-v64/gnu/src/tx_thread_context_restore.S @@ -19,7 +19,6 @@ /**************************************************************************/ /**************************************************************************/ -#include "tx_port.h" .section .text /**************************************************************************/ @@ -69,21 +68,21 @@ _tx_thread_context_restore: /* Lockout interrupts. */ - csrci mstatus, 0x08 // Disable interrupts + csrci mstatus, 0x08 /* Disable interrupts (MIE bit 3) */ #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - call _tx_execution_isr_exit // Call the ISR execution exit function + call _tx_execution_isr_exit /* Call the ISR execution exit function */ #endif /* Determine if interrupts are nested. */ /* if (--_tx_thread_system_state) { */ - la t0, _tx_thread_system_state // Pickup addr of nested interrupt count - LOAD t1, 0(t0) // Pickup nested interrupt count - addi t1, t1, -1 // Decrement the nested interrupt counter - STORE t1, 0(t0) // Store new nested count - beqz t1, _tx_thread_not_nested_restore // If 0, not nested restore + la t0, _tx_thread_system_state /* Pickup addr of nested interrupt count */ + ld t1, 0(t0) /* Pickup nested interrupt count */ + addi t1, t1, -1 /* Decrement the nested interrupt counter */ + sd t1, 0(t0) /* Store new nested count */ + beqz t1, _tx_thread_not_nested_restore /* If 0, not nested restore */ /* Interrupts are nested. */ @@ -92,51 +91,51 @@ _tx_thread_context_restore: /* Recover floating point registers. */ #if defined(__riscv_float_abi_single) - flw f0, 31*REGBYTES(sp) // Recover ft0 - flw f1, 32*REGBYTES(sp) // Recover ft1 - flw f2, 33*REGBYTES(sp) // Recover ft2 - flw f3, 34*REGBYTES(sp) // Recover ft3 - flw f4, 35*REGBYTES(sp) // Recover ft4 - flw f5, 36*REGBYTES(sp) // Recover ft5 - flw f6, 37*REGBYTES(sp) // Recover ft6 - flw f7, 38*REGBYTES(sp) // Recover ft7 - flw f10,41*REGBYTES(sp) // Recover fa0 - flw f11,42*REGBYTES(sp) // Recover fa1 - flw f12,43*REGBYTES(sp) // Recover fa2 - flw f13,44*REGBYTES(sp) // Recover fa3 - flw f14,45*REGBYTES(sp) // Recover fa4 - flw f15,46*REGBYTES(sp) // Recover fa5 - flw f16,47*REGBYTES(sp) // Recover fa6 - flw f17,48*REGBYTES(sp) // Recover fa7 - flw f28,59*REGBYTES(sp) // Recover ft8 - flw f29,60*REGBYTES(sp) // Recover ft9 - flw f30,61*REGBYTES(sp) // Recover ft10 - flw f31,62*REGBYTES(sp) // Recover ft11 - lw t0, 63*REGBYTES(sp) // Recover fcsr - csrw fcsr, t0 // + flw f0, 31*8(sp) /* Recover ft0 */ + flw f1, 32*8(sp) /* Recover ft1 */ + flw f2, 33*8(sp) /* Recover ft2 */ + flw f3, 34*8(sp) /* Recover ft3 */ + flw f4, 35*8(sp) /* Recover ft4 */ + flw f5, 36*8(sp) /* Recover ft5 */ + flw f6, 37*8(sp) /* Recover ft6 */ + flw f7, 38*8(sp) /* Recover ft7 */ + flw f10,41*8(sp) /* Recover fa0 */ + flw f11,42*8(sp) /* Recover fa1 */ + flw f12,43*8(sp) /* Recover fa2 */ + flw f13,44*8(sp) /* Recover fa3 */ + flw f14,45*8(sp) /* Recover fa4 */ + flw f15,46*8(sp) /* Recover fa5 */ + flw f16,47*8(sp) /* Recover fa6 */ + flw f17,48*8(sp) /* Recover fa7 */ + flw f28,59*8(sp) /* Recover ft8 */ + flw f29,60*8(sp) /* Recover ft9 */ + flw f30,61*8(sp) /* Recover ft10 */ + flw f31,62*8(sp) /* Recover ft11 */ + ld t0, 63*8(sp) /* Recover fcsr */ + csrw fcsr, t0 /* Restore fcsr */ #elif defined(__riscv_float_abi_double) - fld f0, 31*REGBYTES(sp) // Recover ft0 - fld f1, 32*REGBYTES(sp) // Recover ft1 - fld f2, 33*REGBYTES(sp) // Recover ft2 - fld f3, 34*REGBYTES(sp) // Recover ft3 - fld f4, 35*REGBYTES(sp) // Recover ft4 - fld f5, 36*REGBYTES(sp) // Recover ft5 - fld f6, 37*REGBYTES(sp) // Recover ft6 - fld f7, 38*REGBYTES(sp) // Recover ft7 - fld f10,41*REGBYTES(sp) // Recover fa0 - fld f11,42*REGBYTES(sp) // Recover fa1 - fld f12,43*REGBYTES(sp) // Recover fa2 - fld f13,44*REGBYTES(sp) // Recover fa3 - fld f14,45*REGBYTES(sp) // Recover fa4 - fld f15,46*REGBYTES(sp) // Recover fa5 - fld f16,47*REGBYTES(sp) // Recover fa6 - fld f17,48*REGBYTES(sp) // Recover fa7 - fld f28,59*REGBYTES(sp) // Recover ft8 - fld f29,60*REGBYTES(sp) // Recover ft9 - fld f30,61*REGBYTES(sp) // Recover ft10 - fld f31,62*REGBYTES(sp) // Recover ft11 - LOAD t0, 63*REGBYTES(sp) // Recover fcsr - csrw fcsr, t0 // + fld f0, 31*8(sp) /* Recover ft0 */ + fld f1, 32*8(sp) /* Recover ft1 */ + fld f2, 33*8(sp) /* Recover ft2 */ + fld f3, 34*8(sp) /* Recover ft3 */ + fld f4, 35*8(sp) /* Recover ft4 */ + fld f5, 36*8(sp) /* Recover ft5 */ + fld f6, 37*8(sp) /* Recover ft6 */ + fld f7, 38*8(sp) /* Recover ft7 */ + fld f10,41*8(sp) /* Recover fa0 */ + fld f11,42*8(sp) /* Recover fa1 */ + fld f12,43*8(sp) /* Recover fa2 */ + fld f13,44*8(sp) /* Recover fa3 */ + fld f14,45*8(sp) /* Recover fa4 */ + fld f15,46*8(sp) /* Recover fa5 */ + fld f16,47*8(sp) /* Recover fa6 */ + fld f17,48*8(sp) /* Recover fa7 */ + fld f28,59*8(sp) /* Recover ft8 */ + fld f29,60*8(sp) /* Recover ft9 */ + fld f30,61*8(sp) /* Recover ft10 */ + fld f31,62*8(sp) /* Recover ft11 */ + ld t0, 63*8(sp) /* Recover fcsr */ + csrw fcsr, t0 #endif /* Recover standard registers. */ @@ -146,39 +145,56 @@ _tx_thread_context_restore: Also skip the saved registers since they have been restored by any function we called, except s0 since we use it ourselves. */ - LOAD t0, 30*REGBYTES(sp) // Recover mepc - csrw mepc, t0 // Setup mepc - li t0, 0x1880 // Prepare MPIP + ld t0, 30*8(sp) /* Recover mepc */ + csrw mepc, t0 /* Setup mepc */ + + /* Compose mstatus via read/modify/write to avoid clobbering unrelated bits. + Set MPIE and restore MPP to Machine, preserve other fields. */ + + csrr t1, mstatus + + /* Clear MPP/MPIE/MIE bits in t1 then set desired values. */ + + li t2, 0x1888 /* MPP(0x1800) | MPIE(0x80) | MIE(0x08) */ + li t3, 0x1800 /* Set MPP to Machine mode (bits 12:11) */ + + /* Construct new mstatus in t1: clear mask bits, set MPP/MPIE and optionally FP bit, + preserve everything except the bits we will modify. */ + + li t4, ~0x1888 /* Clear mask for MPP/MPIE/MIE */ + and t1, t1, t4 + or t1, t1, t3 + #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - li t1, 1<<13 - or t0, t1, t0 + li t0, 0x2000 /* Set FS bits (bits 14:13 to 01) for FP state */ + or t1, t1, t0 #endif - csrw mstatus, t0 // Enable MPIP + csrw mstatus, t1 /* Update mstatus safely */ - LOAD x1, 28*REGBYTES(sp) // Recover RA - LOAD x5, 19*REGBYTES(sp) // Recover t0 - LOAD x6, 18*REGBYTES(sp) // Recover t1 - LOAD x7, 17*REGBYTES(sp) // Recover t2 - LOAD x8, 12*REGBYTES(sp) // Recover s0 - LOAD x10, 27*REGBYTES(sp) // Recover a0 - LOAD x11, 26*REGBYTES(sp) // Recover a1 - LOAD x12, 25*REGBYTES(sp) // Recover a2 - LOAD x13, 24*REGBYTES(sp) // Recover a3 - LOAD x14, 23*REGBYTES(sp) // Recover a4 - LOAD x15, 22*REGBYTES(sp) // Recover a5 - LOAD x16, 21*REGBYTES(sp) // Recover a6 - LOAD x17, 20*REGBYTES(sp) // Recover a7 - LOAD x28, 16*REGBYTES(sp) // Recover t3 - LOAD x29, 15*REGBYTES(sp) // Recover t4 - LOAD x30, 14*REGBYTES(sp) // Recover t5 - LOAD x31, 13*REGBYTES(sp) // Recover t6 + ld ra, 28*8(sp) /* Recover return address */ + ld t0, 19*8(sp) /* Recover t0 */ + ld t1, 18*8(sp) /* Recover t1 */ + ld t2, 17*8(sp) /* Recover t2 */ + ld s0, 12*8(sp) /* Recover s0 */ + ld a0, 27*8(sp) /* Recover a0 */ + ld a1, 26*8(sp) /* Recover a1 */ + ld a2, 25*8(sp) /* Recover a2 */ + ld a3, 24*8(sp) /* Recover a3 */ + ld a4, 23*8(sp) /* Recover a4 */ + ld a5, 22*8(sp) /* Recover a5 */ + ld a6, 21*8(sp) /* Recover a6 */ + ld a7, 20*8(sp) /* Recover a7 */ + ld t3, 16*8(sp) /* Recover t3 */ + ld t4, 15*8(sp) /* Recover t4 */ + ld t5, 14*8(sp) /* Recover t5 */ + ld t6, 13*8(sp) /* Recover t6 */ #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - addi sp, sp, 65*REGBYTES // Recover stack frame - with floating point enabled + addi sp, sp, 65*8 /* Recover stack frame - with floating point enabled */ #else - addi sp, sp, 32*REGBYTES // Recover stack frame - without floating point enabled + addi sp, sp, 32*8 /* Recover stack frame - without floating point enabled */ #endif - mret // Return to point of interrupt + mret /* Return to point of interrupt */ /* } */ _tx_thread_not_nested_restore: @@ -187,71 +203,74 @@ _tx_thread_not_nested_restore: || (_tx_thread_preempt_disable)) { */ - LOAD t1, _tx_thread_current_ptr // Pickup current thread pointer - beqz t1, _tx_thread_idle_system_restore // If NULL, idle system restore + la t0, _tx_thread_current_ptr /* Pickup current thread pointer address */ + ld t1, 0(t0) /* Pickup current thread pointer */ + beqz t1, _tx_thread_idle_system_restore /* If NULL, idle system restore */ - LOAD t2, _tx_thread_preempt_disable // Pickup preempt disable flag - bgtz t2, _tx_thread_no_preempt_restore // If set, restore interrupted thread + la t0, _tx_thread_preempt_disable /* Pickup preempt disable flag address */ + lw t2, 0(t0) /* Pickup preempt disable flag (UINT) */ + bgtz t2, _tx_thread_no_preempt_restore /* If set, restore interrupted thread */ - LOAD t2, _tx_thread_execute_ptr // Pickup thread execute pointer - bne t1, t2, _tx_thread_preempt_restore // If higher-priority thread is ready, preempt + la t0, _tx_thread_execute_ptr /* Pickup thread execute pointer address */ + ld t2, 0(t0) /* Pickup thread execute pointer */ + bne t1, t2, _tx_thread_preempt_restore /* If higher-priority thread is ready, preempt */ _tx_thread_no_preempt_restore: /* Restore interrupted thread or ISR. */ /* Pickup the saved stack pointer. */ - /* SP = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + /* sp = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ - LOAD sp, 2*REGBYTES(t1) // Switch back to thread's stack + ld sp, 16(t1) /* Switch back to thread's stack */ /* Recover floating point registers. */ #if defined(__riscv_float_abi_single) - flw f0, 31*REGBYTES(sp) // Recover ft0 - flw f1, 32*REGBYTES(sp) // Recover ft1 - flw f2, 33*REGBYTES(sp) // Recover ft2 - flw f3, 34*REGBYTES(sp) // Recover ft3 - flw f4, 35*REGBYTES(sp) // Recover ft4 - flw f5, 36*REGBYTES(sp) // Recover ft5 - flw f6, 37*REGBYTES(sp) // Recover ft6 - flw f7, 38*REGBYTES(sp) // Recover ft7 - flw f10,41*REGBYTES(sp) // Recover fa0 - flw f11,42*REGBYTES(sp) // Recover fa1 - flw f12,43*REGBYTES(sp) // Recover fa2 - flw f13,44*REGBYTES(sp) // Recover fa3 - flw f14,45*REGBYTES(sp) // Recover fa4 - flw f15,46*REGBYTES(sp) // Recover fa5 - flw f16,47*REGBYTES(sp) // Recover fa6 - flw f17,48*REGBYTES(sp) // Recover fa7 - flw f28,59*REGBYTES(sp) // Recover ft8 - flw f29,60*REGBYTES(sp) // Recover ft9 - flw f30,61*REGBYTES(sp) // Recover ft10 - flw f31,62*REGBYTES(sp) // Recover ft11 - lw t0, 63*REGBYTES(sp) // Recover fcsr - csrw fcsr, t0 // + flw f0, 31*8(sp) /* Recover ft0 */ + flw f1, 32*8(sp) /* Recover ft1 */ + flw f2, 33*8(sp) /* Recover ft2 */ + flw f3, 34*8(sp) /* Recover ft3 */ + flw f4, 35*8(sp) /* Recover ft4 */ + flw f5, 36*8(sp) /* Recover ft5 */ + flw f6, 37*8(sp) /* Recover ft6 */ + flw f7, 38*8(sp) /* Recover ft7 */ + flw f10,41*8(sp) /* Recover fa0 */ + flw f11,42*8(sp) /* Recover fa1 */ + flw f12,43*8(sp) /* Recover fa2 */ + flw f13,44*8(sp) /* Recover fa3 */ + flw f14,45*8(sp) /* Recover fa4 */ + flw f15,46*8(sp) /* Recover fa5 */ + flw f16,47*8(sp) /* Recover fa6 */ + flw f17,48*8(sp) /* Recover fa7 */ + flw f28,59*8(sp) /* Recover ft8 */ + flw f29,60*8(sp) /* Recover ft9 */ + flw f30,61*8(sp) /* Recover ft10 */ + flw f31,62*8(sp) /* Recover ft11 */ + ld t0, 63*8(sp) /* Recover fcsr */ + csrw fcsr, t0 /* Restore fcsr */ #elif defined(__riscv_float_abi_double) - fld f0, 31*REGBYTES(sp) // Recover ft0 - fld f1, 32*REGBYTES(sp) // Recover ft1 - fld f2, 33*REGBYTES(sp) // Recover ft2 - fld f3, 34*REGBYTES(sp) // Recover ft3 - fld f4, 35*REGBYTES(sp) // Recover ft4 - fld f5, 36*REGBYTES(sp) // Recover ft5 - fld f6, 37*REGBYTES(sp) // Recover ft6 - fld f7, 38*REGBYTES(sp) // Recover ft7 - fld f10,41*REGBYTES(sp) // Recover fa0 - fld f11,42*REGBYTES(sp) // Recover fa1 - fld f12,43*REGBYTES(sp) // Recover fa2 - fld f13,44*REGBYTES(sp) // Recover fa3 - fld f14,45*REGBYTES(sp) // Recover fa4 - fld f15,46*REGBYTES(sp) // Recover fa5 - fld f16,47*REGBYTES(sp) // Recover fa6 - fld f17,48*REGBYTES(sp) // Recover fa7 - fld f28,59*REGBYTES(sp) // Recover ft8 - fld f29,60*REGBYTES(sp) // Recover ft9 - fld f30,61*REGBYTES(sp) // Recover ft10 - fld f31,62*REGBYTES(sp) // Recover ft11 - LOAD t0, 63*REGBYTES(sp) // Recover fcsr - csrw fcsr, t0 // + fld f0, 31*8(sp) /* Recover ft0 */ + fld f1, 32*8(sp) /* Recover ft1 */ + fld f2, 33*8(sp) /* Recover ft2 */ + fld f3, 34*8(sp) /* Recover ft3 */ + fld f4, 35*8(sp) /* Recover ft4 */ + fld f5, 36*8(sp) /* Recover ft5 */ + fld f6, 37*8(sp) /* Recover ft6 */ + fld f7, 38*8(sp) /* Recover ft7 */ + fld f10,41*8(sp) /* Recover fa0 */ + fld f11,42*8(sp) /* Recover fa1 */ + fld f12,43*8(sp) /* Recover fa2 */ + fld f13,44*8(sp) /* Recover fa3 */ + fld f14,45*8(sp) /* Recover fa4 */ + fld f15,46*8(sp) /* Recover fa5 */ + fld f16,47*8(sp) /* Recover fa6 */ + fld f17,48*8(sp) /* Recover fa7 */ + fld f28,59*8(sp) /* Recover ft8 */ + fld f29,60*8(sp) /* Recover ft9 */ + fld f30,61*8(sp) /* Recover ft10 */ + fld f31,62*8(sp) /* Recover ft11 */ + ld t0, 63*8(sp) /* Recover fcsr */ + csrw fcsr, t0 /* Restore fcsr */ #endif /* Recover the saved context and return to the point of interrupt. */ @@ -260,39 +279,48 @@ _tx_thread_no_preempt_restore: /* Restore registers, Skip global pointer because that does not change */ - LOAD t0, 240(sp) // Recover mepc - csrw mepc, t0 // Setup mepc - li t0, 0x1880 // Prepare MPIP + ld t0, 30*8(sp) /* Recover mepc */ + csrw mepc, t0 /* Setup mepc */ + + /* Compose mstatus via read/modify/write to avoid clobbering unrelated bits. */ + + csrr t1, mstatus + li t2, 0x1888 /* MPP(0x1800) | MPIE(0x80) | MIE(0x08) */ + li t3, 0x1800 /* Set MPP to Machine mode */ + li t4, ~0x1888 /* Clear mask for MPP/MPIE/MIE */ + and t1, t1, t4 + or t1, t1, t3 + #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - li t1, 1<<13 - or t0, t1, t0 + li t0, 0x2000 /* Set FS bits for FP state */ + or t1, t1, t0 #endif - csrw mstatus, t0 // Enable MPIP + csrw mstatus, t1 /* Update mstatus safely */ - LOAD x1, 28*REGBYTES(sp) // Recover RA - LOAD x5, 19*REGBYTES(sp) // Recover t0 - LOAD x6, 18*REGBYTES(sp) // Recover t1 - LOAD x7, 17*REGBYTES(sp) // Recover t2 - LOAD x8, 12*REGBYTES(sp) // Recover s0 - LOAD x10, 27*REGBYTES(sp) // Recover a0 - LOAD x11, 26*REGBYTES(sp) // Recover a1 - LOAD x12, 25*REGBYTES(sp) // Recover a2 - LOAD x13, 24*REGBYTES(sp) // Recover a3 - LOAD x14, 23*REGBYTES(sp) // Recover a4 - LOAD x15, 22*REGBYTES(sp) // Recover a5 - LOAD x16, 21*REGBYTES(sp) // Recover a6 - LOAD x17, 20*REGBYTES(sp) // Recover a7 - LOAD x28, 16*REGBYTES(sp) // Recover t3 - LOAD x29, 15*REGBYTES(sp) // Recover t4 - LOAD x30, 14*REGBYTES(sp) // Recover t5 - LOAD x31, 13*REGBYTES(sp) // Recover t6 + ld ra, 28*8(sp) /* Recover return address */ + ld t0, 19*8(sp) /* Recover t0 */ + ld t1, 18*8(sp) /* Recover t1 */ + ld t2, 17*8(sp) /* Recover t2 */ + ld s0, 12*8(sp) /* Recover s0 */ + ld a0, 27*8(sp) /* Recover a0 */ + ld a1, 26*8(sp) /* Recover a1 */ + ld a2, 25*8(sp) /* Recover a2 */ + ld a3, 24*8(sp) /* Recover a3 */ + ld a4, 23*8(sp) /* Recover a4 */ + ld a5, 22*8(sp) /* Recover a5 */ + ld a6, 21*8(sp) /* Recover a6 */ + ld a7, 20*8(sp) /* Recover a7 */ + ld t3, 16*8(sp) /* Recover t3 */ + ld t4, 15*8(sp) /* Recover t4 */ + ld t5, 14*8(sp) /* Recover t5 */ + ld t6, 13*8(sp) /* Recover t6 */ #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - addi sp, sp, 65*REGBYTES // Recover stack frame - with floating point enabled + addi sp, sp, 65*8 /* Recover stack frame - with floating point enabled */ #else - addi sp, sp, 32*REGBYTES // Recover stack frame - without floating point enabled + addi sp, sp, 32*8 /* Recover stack frame - without floating point enabled */ #endif - mret // Return to point of interrupt + mret /* Return to point of interrupt */ /* } else @@ -301,52 +329,52 @@ _tx_thread_preempt_restore: /* Instead of directly activating the thread again, ensure we save the entire stack frame by saving the remaining registers. */ - LOAD t0, 2*REGBYTES(t1) // Pickup thread's stack pointer - ori t3, x0, 1 // Build interrupt stack type - STORE t3, 0(t0) // Store stack type + ld t0, 16(t1) /* Pickup thread's stack pointer */ + ori t3, zero, 1 /* Build interrupt stack type */ + sd t3, 0(t0) /* Store stack type */ /* Store floating point preserved registers. */ #ifdef __riscv_float_abi_single - fsw f8, 39*REGBYTES(t0) // Store fs0 - fsw f9, 40*REGBYTES(t0) // Store fs1 - fsw f18, 49*REGBYTES(t0) // Store fs2 - fsw f19, 50*REGBYTES(t0) // Store fs3 - fsw f20, 51*REGBYTES(t0) // Store fs4 - fsw f21, 52*REGBYTES(t0) // Store fs5 - fsw f22, 53*REGBYTES(t0) // Store fs6 - fsw f23, 54*REGBYTES(t0) // Store fs7 - fsw f24, 55*REGBYTES(t0) // Store fs8 - fsw f25, 56*REGBYTES(t0) // Store fs9 - fsw f26, 57*REGBYTES(t0) // Store fs10 - fsw f27, 58*REGBYTES(t0) // Store fs11 + fsw f8, 39*8(t0) /* Store fs0 */ + fsw f9, 40*8(t0) /* Store fs1 */ + fsw f18, 49*8(t0) /* Store fs2 */ + fsw f19, 50*8(t0) // Store fs3 + fsw f20, 51*8(t0) // Store fs4 + fsw f21, 52*8(t0) // Store fs5 + fsw f22, 53*8(t0) // Store fs6 + fsw f23, 54*8(t0) // Store fs7 + fsw f24, 55*8(t0) // Store fs8 + fsw f25, 56*8(t0) // Store fs9 + fsw f26, 57*8(t0) // Store fs10 + fsw f27, 58*8(t0) // Store fs11 #elif defined(__riscv_float_abi_double) - fsd f8, 39*REGBYTES(t0) // Store fs0 - fsd f9, 40*REGBYTES(t0) // Store fs1 - fsd f18, 49*REGBYTES(t0) // Store fs2 - fsd f19, 50*REGBYTES(t0) // Store fs3 - fsd f20, 51*REGBYTES(t0) // Store fs4 - fsd f21, 52*REGBYTES(t0) // Store fs5 - fsd f22, 53*REGBYTES(t0) // Store fs6 - fsd f23, 54*REGBYTES(t0) // Store fs7 - fsd f24, 55*REGBYTES(t0) // Store fs8 - fsd f25, 56*REGBYTES(t0) // Store fs9 - fsd f26, 57*REGBYTES(t0) // Store fs10 - fsd f27, 58*REGBYTES(t0) // Store fs11 + fsd f8, 39*8(t0) // Store fs0 + fsd f9, 40*8(t0) // Store fs1 + fsd f18, 49*8(t0) // Store fs2 + fsd f19, 50*8(t0) // Store fs3 + fsd f20, 51*8(t0) // Store fs4 + fsd f21, 52*8(t0) // Store fs5 + fsd f22, 53*8(t0) // Store fs6 + fsd f23, 54*8(t0) // Store fs7 + fsd f24, 55*8(t0) // Store fs8 + fsd f25, 56*8(t0) // Store fs9 + fsd f26, 57*8(t0) // Store fs10 + fsd f27, 58*8(t0) // Store fs11 #endif /* Store standard preserved registers. */ - STORE x9, 11*REGBYTES(t0) // Store s1 - STORE x18, 10*REGBYTES(t0) // Store s2 - STORE x19, 9*REGBYTES(t0) // Store s3 - STORE x20, 8*REGBYTES(t0) // Store s4 - STORE x21, 7*REGBYTES(t0) // Store s5 - STORE x22, 6*REGBYTES(t0) // Store s6 - STORE x23, 5*REGBYTES(t0) // Store s7 - STORE x24, 4*REGBYTES(t0) // Store s8 - STORE x25, 3*REGBYTES(t0) // Store s9 - STORE x26, 2*REGBYTES(t0) // Store s10 - STORE x27, 1*REGBYTES(t0) // Store s11 + sd x9, 11*8(t0) // Store s1 + sd x18, 10*8(t0) // Store s2 + sd x19, 9*8(t0) // Store s3 + sd x20, 8*8(t0) // Store s4 + sd x21, 7*8(t0) // Store s5 + sd x22, 6*8(t0) // Store s6 + sd x23, 5*8(t0) // Store s7 + sd x24, 4*8(t0) // Store s8 + sd x25, 3*8(t0) // Store s9 + sd x26, 2*8(t0) // Store s10 + sd x27, 1*8(t0) // Store s11 // Note: s0 is already stored! /* Save the remaining time-slice and disable it. */ @@ -354,14 +382,14 @@ _tx_thread_preempt_restore: { */ la t0, _tx_timer_time_slice // Pickup time slice variable address - LOAD t2, 0(t0) // Pickup time slice + ld t2, 0(t0) // Pickup time slice beqz t2, _tx_thread_dont_save_ts // If 0, skip time slice processing /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice _tx_timer_time_slice = 0; */ - STORE t2, 6*REGBYTES(t1) // Save current time slice - STORE x0, 0(t0) // Clear global time slice + sd t2, 48(t1) // Save current time slice + sd x0, 0(t0) // Clear global time slice /* } */ @@ -372,7 +400,8 @@ _tx_thread_dont_save_ts: /* Return to the scheduler. */ /* _tx_thread_schedule(); */ - STORE x0, _tx_thread_current_ptr, t0 // Clear current thread pointer*/ + la t0, _tx_thread_current_ptr // Pickup current thread pointer address + sd x0, 0(t0) // Clear current thread pointer*/ /* } */ _tx_thread_idle_system_restore: diff --git a/ports/risc-v64/gnu/src/tx_thread_context_save.S b/ports/risc-v64/gnu/src/tx_thread_context_save.S index a1f2a9b6..30704850 100644 --- a/ports/risc-v64/gnu/src/tx_thread_context_save.S +++ b/ports/risc-v64/gnu/src/tx_thread_context_save.S @@ -1,14 +1,3 @@ -/*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ - - /**************************************************************************/ /**************************************************************************/ /** */ @@ -19,8 +8,6 @@ /**************************************************************************/ /**************************************************************************/ -#include "tx_port.h" - .section .text /**************************************************************************/ /* */ @@ -67,97 +54,97 @@ _tx_thread_context_save: /* Upon entry to this routine, it is assumed that interrupts are locked - out and the interrupt stack fame has been allocated and x1 (ra) has + out and the interrupt stack frame has been allocated and ra has been saved on the stack. */ - STORE x5, 19*REGBYTES(sp) // First store t0 and t1 - STORE x6, 18*REGBYTES(sp) + sd t0, 19*8(sp) /* First store t0 and t1 */ + sd t1, 18*8(sp) - la x5, _tx_thread_system_state // Pickup address of system state - LOAD x6, 0(x5) // Pickup system state + la t0, _tx_thread_system_state /* Pickup address of system state */ + ld t1, 0(t0) /* Pickup system state */ /* Check for a nested interrupt condition. */ /* if (_tx_thread_system_state++) { */ - beqz x6, _tx_thread_not_nested_save // If 0, first interrupt condition - addi x6, x6, 1 // Increment the interrupt counter - STORE x6, 0(x5) // Store the interrupt counter + beqz t1, _tx_thread_not_nested_save /* If 0, first interrupt condition */ + addi t1, t1, 1 /* Increment the interrupt counter */ + sd t1, 0(t0) /* Store the interrupt counter */ /* Nested interrupt condition. - Save the reset of the scratch registers on the stack and return to the + Save the rest of the scratch registers on the stack and return to the calling ISR. */ - STORE x7, 17*REGBYTES(sp) // Store t2 - STORE x8, 12*REGBYTES(sp) // Store s0 - STORE x10, 27*REGBYTES(sp) // Store a0 - STORE x11, 26*REGBYTES(sp) // Store a1 - STORE x12, 25*REGBYTES(sp) // Store a2 - STORE x13, 24*REGBYTES(sp) // Store a3 - STORE x14, 23*REGBYTES(sp) // Store a4 - STORE x15, 22*REGBYTES(sp) // Store a5 - STORE x16, 21*REGBYTES(sp) // Store a6 - STORE x17, 20*REGBYTES(sp) // Store a7 - STORE x28, 16*REGBYTES(sp) // Store t3 - STORE x29, 15*REGBYTES(sp) // Store t4 - STORE x30, 14*REGBYTES(sp) // Store t5 - STORE x31, 13*REGBYTES(sp) // Store t6 - csrr t0, mepc // Load exception program counter - STORE t0, 30*REGBYTES(sp) // Save it on the stack + sd t2, 17*8(sp) /* Store t2 */ + sd s0, 12*8(sp) /* Store s0 */ + sd a0, 27*8(sp) /* Store a0 */ + sd a1, 26*8(sp) /* Store a1 */ + sd a2, 25*8(sp) /* Store a2 */ + sd a3, 24*8(sp) /* Store a3 */ + sd a4, 23*8(sp) /* Store a4 */ + sd a5, 22*8(sp) /* Store a5 */ + sd a6, 21*8(sp) /* Store a6 */ + sd a7, 20*8(sp) /* Store a7 */ + sd t3, 16*8(sp) /* Store t3 */ + sd t4, 15*8(sp) /* Store t4 */ + sd t5, 14*8(sp) /* Store t5 */ + sd t6, 13*8(sp) /* Store t6 */ + csrr t0, mepc /* Load exception program counter */ + sd t0, 30*8(sp) /* Save it on the stack */ - /* Save floating point scratch registers. */ -#if defined(__riscv_float_abi_single) - fsw f0, 31*REGBYTES(sp) // Store ft0 - fsw f1, 32*REGBYTES(sp) // Store ft1 - fsw f2, 33*REGBYTES(sp) // Store ft2 - fsw f3, 34*REGBYTES(sp) // Store ft3 - fsw f4, 35*REGBYTES(sp) // Store ft4 - fsw f5, 36*REGBYTES(sp) // Store ft5 - fsw f6, 37*REGBYTES(sp) // Store ft6 - fsw f7, 38*REGBYTES(sp) // Store ft7 - fsw f10,41*REGBYTES(sp) // Store fa0 - fsw f11,42*REGBYTES(sp) // Store fa1 - fsw f12,43*REGBYTES(sp) // Store fa2 - fsw f13,44*REGBYTES(sp) // Store fa3 - fsw f14,45*REGBYTES(sp) // Store fa4 - fsw f15,46*REGBYTES(sp) // Store fa5 - fsw f16,47*REGBYTES(sp) // Store fa6 - fsw f17,48*REGBYTES(sp) // Store fa7 - fsw f28,59*REGBYTES(sp) // Store ft8 - fsw f29,60*REGBYTES(sp) // Store ft9 - fsw f30,61*REGBYTES(sp) // Store ft10 - fsw f31,62*REGBYTES(sp) // Store ft11 + /* Save floating point scratch registers if floating point is enabled. */ +#ifdef __riscv_float_abi_single + fsw f0, 31*8(sp) /* Store ft0 */ + fsw f1, 32*8(sp) /* Store ft1 */ + fsw f2, 33*8(sp) /* Store ft2 */ + fsw f3, 34*8(sp) /* Store ft3 */ + fsw f4, 35*8(sp) /* Store ft4 */ + fsw f5, 36*8(sp) /* Store ft5 */ + fsw f6, 37*8(sp) /* Store ft6 */ + fsw f7, 38*8(sp) /* Store ft7 */ + fsw f10,41*8(sp) /* Store fa0 */ + fsw f11,42*8(sp) /* Store fa1 */ + fsw f12,43*8(sp) /* Store fa2 */ + fsw f13,44*8(sp) /* Store fa3 */ + fsw f14,45*8(sp) /* Store fa4 */ + fsw f15,46*8(sp) /* Store fa5 */ + fsw f16,47*8(sp) /* Store fa6 */ + fsw f17,48*8(sp) /* Store fa7 */ + fsw f28,59*8(sp) /* Store ft8 */ + fsw f29,60*8(sp) /* Store ft9 */ + fsw f30,61*8(sp) /* Store ft10 */ + fsw f31,62*8(sp) /* Store ft11 */ csrr t0, fcsr - STORE t0, 63*REGBYTES(sp) // Store fcsr + sd t0, 63*8(sp) /* Store fcsr */ #elif defined(__riscv_float_abi_double) - fsd f0, 31*REGBYTES(sp) // Store ft0 - fsd f1, 32*REGBYTES(sp) // Store ft1 - fsd f2, 33*REGBYTES(sp) // Store ft2 - fsd f3, 34*REGBYTES(sp) // Store ft3 - fsd f4, 35*REGBYTES(sp) // Store ft4 - fsd f5, 36*REGBYTES(sp) // Store ft5 - fsd f6, 37*REGBYTES(sp) // Store ft6 - fsd f7, 38*REGBYTES(sp) // Store ft7 - fsd f10,41*REGBYTES(sp) // Store fa0 - fsd f11,42*REGBYTES(sp) // Store fa1 - fsd f12,43*REGBYTES(sp) // Store fa2 - fsd f13,44*REGBYTES(sp) // Store fa3 - fsd f14,45*REGBYTES(sp) // Store fa4 - fsd f15,46*REGBYTES(sp) // Store fa5 - fsd f16,47*REGBYTES(sp) // Store fa6 - fsd f17,48*REGBYTES(sp) // Store fa7 - fsd f28,59*REGBYTES(sp) // Store ft8 - fsd f29,60*REGBYTES(sp) // Store ft9 - fsd f30,61*REGBYTES(sp) // Store ft10 - fsd f31,62*REGBYTES(sp) // Store ft11 + fsd f0, 31*8(sp) /* Store ft0 */ + fsd f1, 32*8(sp) /* Store ft1 */ + fsd f2, 33*8(sp) /* Store ft2 */ + fsd f3, 34*8(sp) /* Store ft3 */ + fsd f4, 35*8(sp) /* Store ft4 */ + fsd f5, 36*8(sp) /* Store ft5 */ + fsd f6, 37*8(sp) /* Store ft6 */ + fsd f7, 38*8(sp) /* Store ft7 */ + fsd f10,41*8(sp) /* Store fa0 */ + fsd f11,42*8(sp) /* Store fa1 */ + fsd f12,43*8(sp) /* Store fa2 */ + fsd f13,44*8(sp) /* Store fa3 */ + fsd f14,45*8(sp) /* Store fa4 */ + fsd f15,46*8(sp) /* Store fa5 */ + fsd f16,47*8(sp) /* Store fa6 */ + fsd f17,48*8(sp) /* Store fa7 */ + fsd f28,59*8(sp) /* Store ft8 */ + fsd f29,60*8(sp) /* Store ft9 */ + fsd f30,61*8(sp) /* Store ft10 */ + fsd f31,62*8(sp) /* Store ft11 */ csrr t0, fcsr - STORE t0, 63*REGBYTES(sp) // Store fcsr + sd t0, 63*8(sp) /* Store fcsr */ #endif #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - call _tx_execution_isr_enter // Call the ISR execution enter function + call _tx_execution_isr_enter /* Call the ISR execution enter function */ #endif - ret // Return to calling ISR + ret /* Return to calling ISR */ _tx_thread_not_nested_save: /* } */ @@ -165,81 +152,82 @@ _tx_thread_not_nested_save: /* Otherwise, not nested, check to see if a thread was running. */ /* else if (_tx_thread_current_ptr) { */ - addi x6, x6, 1 // Increment the interrupt counter - STORE x6, 0(x5) // Store the interrupt counter + addi t1, t1, 1 /* Increment the interrupt counter */ + sd t1, 0(t0) /* Store the interrupt counter */ /* Not nested: Find the user thread that was running and load our SP */ - LOAD x5, _tx_thread_current_ptr // Pickup current thread pointer - beqz x5, _tx_thread_idle_system_save // If NULL, idle system was interrupted + la t0, _tx_thread_current_ptr /* Pickup current thread pointer address */ + ld t0, 0(t0) /* Pickup current thread pointer */ + beqz t0, _tx_thread_idle_system_save /* If NULL, idle system was interrupted */ /* Save the standard scratch registers. */ - STORE x7, 17*REGBYTES(sp) // Store t2 - STORE x8, 12*REGBYTES(sp) // Store s0 - STORE x10, 27*REGBYTES(sp) // Store a0 - STORE x11, 26*REGBYTES(sp) // Store a1 - STORE x12, 25*REGBYTES(sp) // Store a2 - STORE x13, 24*REGBYTES(sp) // Store a3 - STORE x14, 23*REGBYTES(sp) // Store a4 - STORE x15, 22*REGBYTES(sp) // Store a5 - STORE x16, 21*REGBYTES(sp) // Store a6 - STORE x17, 20*REGBYTES(sp) // Store a7 - STORE x28, 16*REGBYTES(sp) // Store t3 - STORE x29, 15*REGBYTES(sp) // Store t4 - STORE x30, 14*REGBYTES(sp) // Store t5 - STORE x31, 13*REGBYTES(sp) // Store t6 + sd t2, 17*8(sp) /* Store t2 */ + sd s0, 12*8(sp) /* Store s0 */ + sd a0, 27*8(sp) /* Store a0 */ + sd a1, 26*8(sp) /* Store a1 */ + sd a2, 25*8(sp) /* Store a2 */ + sd a3, 24*8(sp) /* Store a3 */ + sd a4, 23*8(sp) /* Store a4 */ + sd a5, 22*8(sp) /* Store a5 */ + sd a6, 21*8(sp) /* Store a6 */ + sd a7, 20*8(sp) /* Store a7 */ + sd t3, 16*8(sp) /* Store t3 */ + sd t4, 15*8(sp) /* Store t4 */ + sd t5, 14*8(sp) /* Store t5 */ + sd t6, 13*8(sp) /* Store t6 */ - csrr t0, mepc // Load exception program counter - STORE t0, 30*REGBYTES(sp) // Save it on the stack + csrr t1, mepc /* Load exception program counter */ + sd t1, 30*8(sp) /* Save it on the stack */ - /* Save floating point scratch registers. */ -#if defined(__riscv_float_abi_single) - fsw f0, 31*REGBYTES(sp) // Store ft0 - fsw f1, 32*REGBYTES(sp) // Store ft1 - fsw f2, 33*REGBYTES(sp) // Store ft2 - fsw f3, 34*REGBYTES(sp) // Store ft3 - fsw f4, 35*REGBYTES(sp) // Store ft4 - fsw f5, 36*REGBYTES(sp) // Store ft5 - fsw f6, 37*REGBYTES(sp) // Store ft6 - fsw f7, 38*REGBYTES(sp) // Store ft7 - fsw f10,41*REGBYTES(sp) // Store fa0 - fsw f11,42*REGBYTES(sp) // Store fa1 - fsw f12,43*REGBYTES(sp) // Store fa2 - fsw f13,44*REGBYTES(sp) // Store fa3 - fsw f14,45*REGBYTES(sp) // Store fa4 - fsw f15,46*REGBYTES(sp) // Store fa5 - fsw f16,47*REGBYTES(sp) // Store fa6 - fsw f17,48*REGBYTES(sp) // Store fa7 - fsw f28,59*REGBYTES(sp) // Store ft8 - fsw f29,60*REGBYTES(sp) // Store ft9 - fsw f30,61*REGBYTES(sp) // Store ft10 - fsw f31,62*REGBYTES(sp) // Store ft11 + /* Save floating point scratch registers if floating point is enabled. */ +#ifdef __riscv_float_abi_single + fsw f0, 31*8(sp) /* Store ft0 */ + fsw f1, 32*8(sp) /* Store ft1 */ + fsw f2, 33*8(sp) /* Store ft2 */ + fsw f3, 34*8(sp) /* Store ft3 */ + fsw f4, 35*8(sp) /* Store ft4 */ + fsw f5, 36*8(sp) /* Store ft5 */ + fsw f6, 37*8(sp) /* Store ft6 */ + fsw f7, 38*8(sp) /* Store ft7 */ + fsw f10,41*8(sp) /* Store fa0 */ + fsw f11,42*8(sp) /* Store fa1 */ + fsw f12,43*8(sp) /* Store fa2 */ + fsw f13,44*8(sp) /* Store fa3 */ + fsw f14,45*8(sp) /* Store fa4 */ + fsw f15,46*8(sp) /* Store fa5 */ + fsw f16,47*8(sp) /* Store fa6 */ + fsw f17,48*8(sp) /* Store fa7 */ + fsw f28,59*8(sp) /* Store ft8 */ + fsw f29,60*8(sp) /* Store ft9 */ + fsw f30,61*8(sp) /* Store ft10 */ + fsw f31,62*8(sp) /* Store ft11 */ csrr t0, fcsr - STORE t0, 63*REGBYTES(sp) // Store fcsr + sd t0, 63*8(sp) /* Store fcsr */ #elif defined(__riscv_float_abi_double) - fsd f0, 31*REGBYTES(sp) // Store ft0 - fsd f1, 32*REGBYTES(sp) // Store ft1 - fsd f2, 33*REGBYTES(sp) // Store ft2 - fsd f3, 34*REGBYTES(sp) // Store ft3 - fsd f4, 35*REGBYTES(sp) // Store ft4 - fsd f5, 36*REGBYTES(sp) // Store ft5 - fsd f6, 37*REGBYTES(sp) // Store ft6 - fsd f7, 38*REGBYTES(sp) // Store ft7 - fsd f10,41*REGBYTES(sp) // Store fa0 - fsd f11,42*REGBYTES(sp) // Store fa1 - fsd f12,43*REGBYTES(sp) // Store fa2 - fsd f13,44*REGBYTES(sp) // Store fa3 - fsd f14,45*REGBYTES(sp) // Store fa4 - fsd f15,46*REGBYTES(sp) // Store fa5 - fsd f16,47*REGBYTES(sp) // Store fa6 - fsd f17,48*REGBYTES(sp) // Store fa7 - fsd f28,59*REGBYTES(sp) // Store ft8 - fsd f29,60*REGBYTES(sp) // Store ft9 - fsd f30,61*REGBYTES(sp) // Store ft10 - fsd f31,62*REGBYTES(sp) // Store ft11 + fsd f0, 31*8(sp) /* Store ft0 */ + fsd f1, 32*8(sp) /* Store ft1 */ + fsd f2, 33*8(sp) /* Store ft2 */ + fsd f3, 34*8(sp) /* Store ft3 */ + fsd f4, 35*8(sp) /* Store ft4 */ + fsd f5, 36*8(sp) /* Store ft5 */ + fsd f6, 37*8(sp) /* Store ft6 */ + fsd f7, 38*8(sp) /* Store ft7 */ + fsd f10,41*8(sp) /* Store fa0 */ + fsd f11,42*8(sp) /* Store fa1 */ + fsd f12,43*8(sp) /* Store fa2 */ + fsd f13,44*8(sp) /* Store fa3 */ + fsd f14,45*8(sp) /* Store fa4 */ + fsd f15,46*8(sp) /* Store fa5 */ + fsd f16,47*8(sp) /* Store fa6 */ + fsd f17,48*8(sp) /* Store fa7 */ + fsd f28,59*8(sp) /* Store ft8 */ + fsd f29,60*8(sp) /* Store ft9 */ + fsd f30,61*8(sp) /* Store ft10 */ + fsd f31,62*8(sp) /* Store ft11 */ csrr t0, fcsr - STORE t0, 63*REGBYTES(sp) // Store fcsr + sd t0, 63*8(sp) /* Store fcsr */ #endif /* Save the current stack pointer in the thread's control block. */ @@ -248,8 +236,86 @@ _tx_thread_not_nested_save: /* Switch to the system stack. */ /* sp = _tx_thread_system_stack_ptr; */ - LOAD t1, _tx_thread_current_ptr // Pickup current thread pointer - STORE sp, 2*REGBYTES(t1) // Save stack pointer + la t1, _tx_thread_current_ptr /* Pickup current thread pointer address */ + ld t1, 0(t1) /* Pickup current thread pointer */ + sd sp, 16(t1) /* Save stack pointer */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + /* _tx_execution_isr_enter is called with thread stack pointer */ + call _tx_execution_isr_enter /* Call the ISR execution enter function */ +#endif + + la t0, _tx_thread_system_stack_ptr /* Pickup system stack pointer address */ + ld sp, 0(t0) /* Switch to system stack */ + ret /* Return to calling ISR */ + + sd x17, 20*8(sp) // Store a7 + sd x28, 16*8(sp) // Store t3 + sd x29, 15*8(sp) // Store t4 + sd x30, 14*8(sp) // Store t5 + sd x31, 13*8(sp) // Store t6 + + csrr t0, mepc // Load exception program counter + sd t0, 30*8(sp) // Save it on the stack + + /* Save floating point scratch registers. */ +#if defined(__riscv_float_abi_single) + fsw f0, 31*8(sp) // Store ft0 + fsw f1, 32*8(sp) // Store ft1 + fsw f2, 33*8(sp) // Store ft2 + fsw f3, 34*8(sp) // Store ft3 + fsw f4, 35*8(sp) // Store ft4 + fsw f5, 36*8(sp) // Store ft5 + fsw f6, 37*8(sp) // Store ft6 + fsw f7, 38*8(sp) // Store ft7 + fsw f10,41*8(sp) // Store fa0 + fsw f11,42*8(sp) // Store fa1 + fsw f12,43*8(sp) // Store fa2 + fsw f13,44*8(sp) // Store fa3 + fsw f14,45*8(sp) // Store fa4 + fsw f15,46*8(sp) // Store fa5 + fsw f16,47*8(sp) // Store fa6 + fsw f17,48*8(sp) // Store fa7 + fsw f28,59*8(sp) // Store ft8 + fsw f29,60*8(sp) // Store ft9 + fsw f30,61*8(sp) // Store ft10 + fsw f31,62*8(sp) // Store ft11 + csrr t0, fcsr + sd t0, 63*8(sp) // Store fcsr +#elif defined(__riscv_float_abi_double) + fsd f0, 31*8(sp) // Store ft0 + fsd f1, 32*8(sp) // Store ft1 + fsd f2, 33*8(sp) // Store ft2 + fsd f3, 34*8(sp) // Store ft3 + fsd f4, 35*8(sp) // Store ft4 + fsd f5, 36*8(sp) // Store ft5 + fsd f6, 37*8(sp) // Store ft6 + fsd f7, 38*8(sp) // Store ft7 + fsd f10,41*8(sp) // Store fa0 + fsd f11,42*8(sp) // Store fa1 + fsd f12,43*8(sp) // Store fa2 + fsd f13,44*8(sp) // Store fa3 + fsd f14,45*8(sp) // Store fa4 + fsd f15,46*8(sp) // Store fa5 + fsd f16,47*8(sp) // Store fa6 + fsd f17,48*8(sp) // Store fa7 + fsd f28,59*8(sp) // Store ft8 + fsd f29,60*8(sp) // Store ft9 + fsd f30,61*8(sp) // Store ft10 + fsd f31,62*8(sp) // Store ft11 + csrr t0, fcsr + sd t0, 63*8(sp) // Store fcsr +#endif + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + la x5, _tx_thread_current_ptr // Pickup current thread pointer address + ld t1, 0(x5) // Pickup current thread pointer + sd sp, 16(t1) // Save stack pointer #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY /* _tx_execution_isr_enter is called with thread stack pointer */ @@ -257,7 +323,8 @@ _tx_thread_not_nested_save: #endif - LOAD sp, _tx_thread_system_stack_ptr // Switch to system stack + la x5, _tx_thread_system_stack_ptr // Pickup system stack pointer address + ld sp, 0(x5) // Switch to system stack ret // Return to calling ISR /* } @@ -276,8 +343,8 @@ _tx_thread_idle_system_save: /* } } */ #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - addi sp, sp, 65*REGBYTES // Recover stack frame - with floating point enabled + addi sp, sp, 65*8 // Recover stack frame - with floating point enabled #else - addi sp, sp, 32*REGBYTES // Recover the reserved stack space + addi sp, sp, 32*8 // Recover the reserved stack space #endif ret // Return to calling ISR diff --git a/ports/risc-v64/gnu/src/tx_thread_interrupt_control.S b/ports/risc-v64/gnu/src/tx_thread_interrupt_control.S index c75c7c47..57b25a52 100644 --- a/ports/risc-v64/gnu/src/tx_thread_interrupt_control.S +++ b/ports/risc-v64/gnu/src/tx_thread_interrupt_control.S @@ -19,8 +19,8 @@ /**************************************************************************/ /**************************************************************************/ - RETURN_MASK = 0x000000000000000F - SET_SR_MASK = 0xFFFFFFFFFFFFFFF0 + /* Define which mstatus bits this function will modify/return. */ + /* MSTATUS_MIE bit 3 = Machine Interrupt Enable */ .section .text /**************************************************************************/ @@ -66,16 +66,20 @@ .global _tx_thread_interrupt_control _tx_thread_interrupt_control: /* Pickup current interrupt lockout posture. */ + /* old_mstatus = mstatus; */ csrr t0, mstatus - mv t1, t0 // Save original mstatus for return + mv t1, t0 /* Save original mstatus for return */ - /* Apply the new interrupt posture. */ - - li t2, SET_SR_MASK // Build set SR mask - and t0, t0, t2 // Isolate interrupt lockout bits - or t0, t0, a0 // Put new lockout bits in + /* Apply the new interrupt posture while preserving unrelated mstatus bits. */ + /* Only modify the MIE bit (bit 3) */ + /* mstatus = (mstatus & ~MIE) | (new_posture & MIE); */ + + li t2, ~0x08 /* Build mask to clear MIE */ + and t0, t0, t2 /* Clear MIE bit */ + and a0, a0, 0x08 /* Mask incoming to only MIE bit */ + or t0, t0, a0 /* Set requested MIE state */ csrw mstatus, t0 - andi a0, t1, RETURN_MASK // Return original mstatus. + andi a0, t1, 0x08 /* Return original MIE bit */ ret /* } */ diff --git a/ports/risc-v64/gnu/src/tx_thread_schedule.S b/ports/risc-v64/gnu/src/tx_thread_schedule.S index c9be4c6f..4da4c244 100644 --- a/ports/risc-v64/gnu/src/tx_thread_schedule.S +++ b/ports/risc-v64/gnu/src/tx_thread_schedule.S @@ -19,8 +19,6 @@ /**************************************************************************/ /**************************************************************************/ -#include "tx_port.h" - .section .text /**************************************************************************/ /* */ @@ -69,236 +67,254 @@ _tx_thread_schedule: /* Enable interrupts. */ - csrsi mstatus, 0x08 // Enable interrupts + /* mstatus |= MIE; */ + csrsi mstatus, 0x08 /* Enable interrupts (MIE bit 3) */ /* Wait for a thread to execute. */ /* do { */ - la t0, _tx_thread_execute_ptr // Pickup address of execute ptr + la t0, _tx_thread_execute_ptr /* Pickup address of execute ptr */ _tx_thread_schedule_loop: - LOAD t1, 0(t0) // Pickup next thread to execute - beqz t1, _tx_thread_schedule_loop // If NULL, wait for thread to execute + ld t1, 0(t0) /* Pickup next thread to execute */ + +/* TX_USE_WFI_IDLE Configuration: + When defined, the scheduler enters WFI (Wait-For-Interrupt) mode when + no threads are ready, reducing power consumption. The core will wake + on any enabled interrupt. This is recommended for battery-powered or + low-power applications. Define TX_USE_WFI_IDLE in tx_user.h or via + compiler flags to enable this feature. */ +#ifdef TX_USE_WFI_IDLE + beqz t1, 1f + j 2f +1: wfi + j _tx_thread_schedule_loop +2: + beqz t1, _tx_thread_schedule_loop /* Fallback: If still NULL, loop */ +#else + beqz t1, _tx_thread_schedule_loop /* If NULL, wait for thread to execute */ +#endif /* } - while(_tx_thread_execute_ptr == TX_NULL); */ + while(_tx_thread_execute_ptr == NULL); */ /* Yes! We have a thread to execute. Lockout interrupts and transfer control to it. */ - csrci mstatus, 0x08 // Lockout interrupts + csrci mstatus, 0x08 /* Lockout interrupts */ /* Setup the current thread pointer. */ /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ - la t0, _tx_thread_current_ptr // Pickup current thread pointer address - STORE t1, 0(t0) // Set current thread pointer + la t0, _tx_thread_current_ptr /* Pickup current thread pointer address */ + sd t1, 0(t0) /* Set current thread pointer */ /* Increment the run count for this thread. */ /* _tx_thread_current_ptr -> tx_thread_run_count++; */ - LOAD t2, 1*REGBYTES(t1) // Pickup run count - LOAD t3, 6*REGBYTES(t1) // Pickup time slice value - addi t2, t2, 1 // Increment run count - STORE t2, 1*REGBYTES(t1) // Store new run count + ld t2, 8(t1) /* Pickup run count */ + ld t3, 48(t1) /* Pickup time slice value */ + addi t2, t2, 1 /* Increment run count */ + sd t2, 8(t1) /* Store new run count */ /* Setup time-slice, if present. */ /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ - la t2, _tx_timer_time_slice // Pickup time-slice variable address + la t2, _tx_timer_time_slice /* Pickup time-slice variable address */ /* Switch to the thread's stack. */ /* SP = _tx_thread_execute_ptr -> tx_thread_stack_ptr; */ - LOAD sp, 2*REGBYTES(t1) // Switch to thread's stack - STORE t3, 0(t2) // Store new time-slice*/ + ld sp, 16(t1) /* Switch to thread's stack */ + sd t3, 0(t2) /* Store new time-slice*/ #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - call _tx_execution_thread_enter // Call the thread execution enter function + call _tx_execution_thread_enter /* Call the thread execution enter function */ #endif /* Determine if an interrupt frame or a synchronous task suspension frame is present. */ - LOAD t2, 0(sp) // Pickup stack type - beqz t2, _tx_thread_synch_return // If 0, solicited thread return + ld t2, 0(sp) /* Pickup stack type */ + beqz t2, _tx_thread_synch_return /* If 0, solicited thread return */ /* Determine if floating point registers need to be recovered. */ #if defined(__riscv_float_abi_single) - flw f0, 31*REGBYTES(sp) // Recover ft0 - flw f1, 32*REGBYTES(sp) // Recover ft1 - flw f2, 33*REGBYTES(sp) // Recover ft2 - flw f3, 34*REGBYTES(sp) // Recover ft3 - flw f4, 35*REGBYTES(sp) // Recover ft4 - flw f5, 36*REGBYTES(sp) // Recover ft5 - flw f6, 37*REGBYTES(sp) // Recover ft6 - flw f7, 38*REGBYTES(sp) // Recover ft7 - flw f8, 39*REGBYTES(sp) // Recover fs0 - flw f9, 40*REGBYTES(sp) // Recover fs1 - flw f10,41*REGBYTES(sp) // Recover fa0 - flw f11,42*REGBYTES(sp) // Recover fa1 - flw f12,43*REGBYTES(sp) // Recover fa2 - flw f13,44*REGBYTES(sp) // Recover fa3 - flw f14,45*REGBYTES(sp) // Recover fa4 - flw f15,46*REGBYTES(sp) // Recover fa5 - flw f16,47*REGBYTES(sp) // Recover fa6 - flw f17,48*REGBYTES(sp) // Recover fa7 - flw f18,49*REGBYTES(sp) // Recover fs2 - flw f19,50*REGBYTES(sp) // Recover fs3 - flw f20,51*REGBYTES(sp) // Recover fs4 - flw f21,52*REGBYTES(sp) // Recover fs5 - flw f22,53*REGBYTES(sp) // Recover fs6 - flw f23,54*REGBYTES(sp) // Recover fs7 - flw f24,55*REGBYTES(sp) // Recover fs8 - flw f25,56*REGBYTES(sp) // Recover fs9 - flw f26,57*REGBYTES(sp) // Recover fs10 - flw f27,58*REGBYTES(sp) // Recover fs11 - flw f28,59*REGBYTES(sp) // Recover ft8 - flw f29,60*REGBYTES(sp) // Recover ft9 - flw f30,61*REGBYTES(sp) // Recover ft10 - flw f31,62*REGBYTES(sp) // Recover ft11 - LOAD t0, 63*REGBYTES(sp) // Recover fcsr - csrw fcsr, t0 // + flw f0, 31*8(sp) /* Recover ft0 */ + flw f1, 32*8(sp) /* Recover ft1 */ + flw f2, 33*8(sp) /* Recover ft2 */ + flw f3, 34*8(sp) /* Recover ft3 */ + flw f4, 35*8(sp) /* Recover ft4 */ + flw f5, 36*8(sp) /* Recover ft5 */ + flw f6, 37*8(sp) /* Recover ft6 */ + flw f7, 38*8(sp) /* Recover ft7 */ + flw f8, 39*8(sp) /* Recover fs0 */ + flw f9, 40*8(sp) /* Recover fs1 */ + flw f10,41*8(sp) /* Recover fa0 */ + flw f11,42*8(sp) /* Recover fa1 */ + flw f12,43*8(sp) /* Recover fa2 */ + flw f13,44*8(sp) /* Recover fa3 */ + flw f14,45*8(sp) /* Recover fa4 */ + flw f15,46*8(sp) /* Recover fa5 */ + flw f16,47*8(sp) /* Recover fa6 */ + flw f17,48*8(sp) /* Recover fa7 */ + flw f18,49*8(sp) /* Recover fs2 */ + flw f19,50*8(sp) /* Recover fs3 */ + flw f20,51*8(sp) /* Recover fs4 */ + flw f21,52*8(sp) /* Recover fs5 */ + flw f22,53*8(sp) /* Recover fs6 */ + flw f23,54*8(sp) /* Recover fs7 */ + flw f24,55*8(sp) /* Recover fs8 */ + flw f25,56*8(sp) /* Recover fs9 */ + flw f26,57*8(sp) /* Recover fs10 */ + flw f27,58*8(sp) /* Recover fs11 */ + flw f28,59*8(sp) /* Recover ft8 */ + flw f29,60*8(sp) /* Recover ft9 */ + flw f30,61*8(sp) /* Recover ft10 */ + flw f31,62*8(sp) /* Recover ft11 */ + ld t0, 63*8(sp) /* Recover fcsr */ + csrw fcsr, t0 /* Restore fcsr */ #elif defined(__riscv_float_abi_double) - fld f0, 31*REGBYTES(sp) // Recover ft0 - fld f1, 32*REGBYTES(sp) // Recover ft1 - fld f2, 33*REGBYTES(sp) // Recover ft2 - fld f3, 34*REGBYTES(sp) // Recover ft3 - fld f4, 35*REGBYTES(sp) // Recover ft4 - fld f5, 36*REGBYTES(sp) // Recover ft5 - fld f6, 37*REGBYTES(sp) // Recover ft6 - fld f7, 38*REGBYTES(sp) // Recover ft7 - fld f8, 39*REGBYTES(sp) // Recover fs0 - fld f9, 40*REGBYTES(sp) // Recover fs1 - fld f10,41*REGBYTES(sp) // Recover fa0 - fld f11,42*REGBYTES(sp) // Recover fa1 - fld f12,43*REGBYTES(sp) // Recover fa2 - fld f13,44*REGBYTES(sp) // Recover fa3 - fld f14,45*REGBYTES(sp) // Recover fa4 - fld f15,46*REGBYTES(sp) // Recover fa5 - fld f16,47*REGBYTES(sp) // Recover fa6 - fld f17,48*REGBYTES(sp) // Recover fa7 - fld f18,49*REGBYTES(sp) // Recover fs2 - fld f19,50*REGBYTES(sp) // Recover fs3 - fld f20,51*REGBYTES(sp) // Recover fs4 - fld f21,52*REGBYTES(sp) // Recover fs5 - fld f22,53*REGBYTES(sp) // Recover fs6 - fld f23,54*REGBYTES(sp) // Recover fs7 - fld f24,55*REGBYTES(sp) // Recover fs8 - fld f25,56*REGBYTES(sp) // Recover fs9 - fld f26,57*REGBYTES(sp) // Recover fs10 - fld f27,58*REGBYTES(sp) // Recover fs11 - fld f28,59*REGBYTES(sp) // Recover ft8 - fld f29,60*REGBYTES(sp) // Recover ft9 - fld f30,61*REGBYTES(sp) // Recover ft10 - fld f31,62*REGBYTES(sp) // Recover ft11 - LOAD t0, 63*REGBYTES(sp) // Recover fcsr + fld f0, 31*8(sp) // Recover ft0 + fld f1, 32*8(sp) // Recover ft1 + fld f2, 33*8(sp) // Recover ft2 + fld f3, 34*8(sp) // Recover ft3 + fld f4, 35*8(sp) // Recover ft4 + fld f5, 36*8(sp) // Recover ft5 + fld f6, 37*8(sp) // Recover ft6 + fld f7, 38*8(sp) // Recover ft7 + fld f8, 39*8(sp) // Recover fs0 + fld f9, 40*8(sp) // Recover fs1 + fld f10,41*8(sp) // Recover fa0 + fld f11,42*8(sp) // Recover fa1 + fld f12,43*8(sp) // Recover fa2 + fld f13,44*8(sp) // Recover fa3 + fld f14,45*8(sp) // Recover fa4 + fld f15,46*8(sp) // Recover fa5 + fld f16,47*8(sp) // Recover fa6 + fld f17,48*8(sp) // Recover fa7 + fld f18,49*8(sp) // Recover fs2 + fld f19,50*8(sp) // Recover fs3 + fld f20,51*8(sp) // Recover fs4 + fld f21,52*8(sp) // Recover fs5 + fld f22,53*8(sp) // Recover fs6 + fld f23,54*8(sp) // Recover fs7 + fld f24,55*8(sp) // Recover fs8 + fld f25,56*8(sp) // Recover fs9 + fld f26,57*8(sp) // Recover fs10 + fld f27,58*8(sp) // Recover fs11 + fld f28,59*8(sp) // Recover ft8 + fld f29,60*8(sp) // Recover ft9 + fld f30,61*8(sp) // Recover ft10 + fld f31,62*8(sp) // Recover ft11 + ld t0, 63*8(sp) // Recover fcsr + csrw fcsr, t0 // #endif /* Recover standard registers. */ - LOAD t0, 30*REGBYTES(sp) // Recover mepc - csrw mepc, t0 // Store mepc - li t0, 0x1880 // Prepare MPIP + ld t0, 30*8(sp) /* Recover mepc */ + csrw mepc, t0 /* Store mepc */ + li t0, 0x1880 /* Prepare mstatus: MPP=Machine(0x1800) | MPIE(0x80) */ #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - li t1, 1<<13 - or t0, t1, t0 + li t1, 0x2000 /* Set FS bits for FP state */ + or t0, t0, t1 #endif - csrw mstatus, t0 // Enable MPIP + csrw mstatus, t0 /* Set mstatus */ - LOAD x1, 28*REGBYTES(sp) // Recover RA - LOAD x5, 19*REGBYTES(sp) // Recover t0 - LOAD x6, 18*REGBYTES(sp) // Recover t1 - LOAD x7, 17*REGBYTES(sp) // Recover t2 - LOAD x8, 12*REGBYTES(sp) // Recover s0 - LOAD x9, 11*REGBYTES(sp) // Recover s1 - LOAD x10, 27*REGBYTES(sp) // Recover a0 - LOAD x11, 26*REGBYTES(sp) // Recover a1 - LOAD x12, 25*REGBYTES(sp) // Recover a2 - LOAD x13, 24*REGBYTES(sp) // Recover a3 - LOAD x14, 23*REGBYTES(sp) // Recover a4 - LOAD x15, 22*REGBYTES(sp) // Recover a5 - LOAD x16, 21*REGBYTES(sp) // Recover a6 - LOAD x17, 20*REGBYTES(sp) // Recover a7 - LOAD x18, 10*REGBYTES(sp) // Recover s2 - LOAD x19, 9*REGBYTES(sp) // Recover s3 - LOAD x20, 8*REGBYTES(sp) // Recover s4 - LOAD x21, 7*REGBYTES(sp) // Recover s5 - LOAD x22, 6*REGBYTES(sp) // Recover s6 - LOAD x23, 5*REGBYTES(sp) // Recover s7 - LOAD x24, 4*REGBYTES(sp) // Recover s8 - LOAD x25, 3*REGBYTES(sp) // Recover s9 - LOAD x26, 2*REGBYTES(sp) // Recover s10 - LOAD x27, 1*REGBYTES(sp) // Recover s11 - LOAD x28, 16*REGBYTES(sp) // Recover t3 - LOAD x29, 15*REGBYTES(sp) // Recover t4 - LOAD x30, 14*REGBYTES(sp) // Recover t5 - LOAD x31, 13*REGBYTES(sp) // Recover t6 + ld ra, 28*8(sp) /* Recover return address */ + ld t0, 19*8(sp) /* Recover t0 */ + ld t1, 18*8(sp) /* Recover t1 */ + ld t2, 17*8(sp) /* Recover t2 */ + ld s0, 12*8(sp) /* Recover s0 */ + ld s1, 11*8(sp) /* Recover s1 */ + ld a0, 27*8(sp) /* Recover a0 */ + ld a1, 26*8(sp) /* Recover a1 */ + ld a2, 25*8(sp) /* Recover a2 */ + ld a3, 24*8(sp) /* Recover a3 */ + ld a4, 23*8(sp) /* Recover a4 */ + ld a5, 22*8(sp) /* Recover a5 */ + ld a6, 21*8(sp) /* Recover a6 */ + ld a7, 20*8(sp) /* Recover a7 */ + ld s2, 10*8(sp) /* Recover s2 */ + ld s3, 9*8(sp) /* Recover s3 */ + ld s4, 8*8(sp) /* Recover s4 */ + ld s5, 7*8(sp) /* Recover s5 */ + ld s6, 6*8(sp) /* Recover s6 */ + ld s7, 5*8(sp) /* Recover s7 */ + ld s8, 4*8(sp) /* Recover s8 */ + ld s9, 3*8(sp) /* Recover s9 */ + ld s10, 2*8(sp) /* Recover s10 */ + ld s11, 1*8(sp) /* Recover s11 */ + ld t3, 16*8(sp) /* Recover t3 */ + ld t4, 15*8(sp) /* Recover t4 */ + ld t5, 14*8(sp) /* Recover t5 */ + ld t6, 13*8(sp) /* Recover t6 */ #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - addi sp, sp, 65*REGBYTES // Recover stack frame - with floating point registers + addi sp, sp, 65*8 // Recover stack frame - with floating point registers #else - addi sp, sp, 32*REGBYTES // Recover stack frame - without floating point registers + addi sp, sp, 32*8 // Recover stack frame - without floating point registers #endif mret // Return to point of interrupt _tx_thread_synch_return: #if defined(__riscv_float_abi_single) - flw f8, 15*REGBYTES(sp) // Recover fs0 - flw f9, 16*REGBYTES(sp) // Recover fs1 - flw f18,17*REGBYTES(sp) // Recover fs2 - flw f19,18*REGBYTES(sp) // Recover fs3 - flw f20,19*REGBYTES(sp) // Recover fs4 - flw f21,20*REGBYTES(sp) // Recover fs5 - flw f22,21*REGBYTES(sp) // Recover fs6 - flw f23,22*REGBYTES(sp) // Recover fs7 - flw f24,23*REGBYTES(sp) // Recover fs8 - flw f25,24*REGBYTES(sp) // Recover fs9 - flw f26,25*REGBYTES(sp) // Recover fs10 - flw f27,26*REGBYTES(sp) // Recover fs11 - LOAD t0, 27*REGBYTES(sp) // Recover fcsr + flw f8, 15*8(sp) // Recover fs0 + flw f9, 16*8(sp) // Recover fs1 + flw f18,17*8(sp) // Recover fs2 + flw f19,18*8(sp) // Recover fs3 + flw f20,19*8(sp) // Recover fs4 + flw f21,20*8(sp) // Recover fs5 + flw f22,21*8(sp) // Recover fs6 + flw f23,22*8(sp) // Recover fs7 + flw f24,23*8(sp) // Recover fs8 + flw f25,24*8(sp) // Recover fs9 + flw f26,25*8(sp) // Recover fs10 + flw f27,26*8(sp) // Recover fs11 + ld t0, 27*8(sp) // Recover fcsr csrw fcsr, t0 // #elif defined(__riscv_float_abi_double) - fld f8, 15*REGBYTES(sp) // Recover fs0 - fld f9, 16*REGBYTES(sp) // Recover fs1 - fld f18,17*REGBYTES(sp) // Recover fs2 - fld f19,18*REGBYTES(sp) // Recover fs3 - fld f20,19*REGBYTES(sp) // Recover fs4 - fld f21,20*REGBYTES(sp) // Recover fs5 - fld f22,21*REGBYTES(sp) // Recover fs6 - fld f23,22*REGBYTES(sp) // Recover fs7 - fld f24,23*REGBYTES(sp) // Recover fs8 - fld f25,24*REGBYTES(sp) // Recover fs9 - fld f26,25*REGBYTES(sp) // Recover fs10 - fld f27,26*REGBYTES(sp) // Recover fs11 - LOAD t0, 27*REGBYTES(sp) // Recover fcsr + fld f8, 15*8(sp) // Recover fs0 + fld f9, 16*8(sp) // Recover fs1 + fld f18,17*8(sp) // Recover fs2 + fld f19,18*8(sp) // Recover fs3 + fld f20,19*8(sp) // Recover fs4 + fld f21,20*8(sp) // Recover fs5 + fld f22,21*8(sp) // Recover fs6 + fld f23,22*8(sp) // Recover fs7 + fld f24,23*8(sp) // Recover fs8 + fld f25,24*8(sp) // Recover fs9 + fld f26,25*8(sp) // Recover fs10 + fld f27,26*8(sp) // Recover fs11 + ld t0, 27*8(sp) // Recover fcsr csrw fcsr, t0 // #endif /* Recover standard preserved registers. */ /* Recover standard registers. */ - LOAD x1, 13*REGBYTES(sp) // Recover RA - LOAD x8, 12*REGBYTES(sp) // Recover s0 - LOAD x9, 11*REGBYTES(sp) // Recover s1 - LOAD x18, 10*REGBYTES(sp) // Recover s2 - LOAD x19, 9*REGBYTES(sp) // Recover s3 - LOAD x20, 8*REGBYTES(sp) // Recover s4 - LOAD x21, 7*REGBYTES(sp) // Recover s5 - LOAD x22, 6*REGBYTES(sp) // Recover s6 - LOAD x23, 5*REGBYTES(sp) // Recover s7 - LOAD x24, 4*REGBYTES(sp) // Recover s8 - LOAD x25, 3*REGBYTES(sp) // Recover s9 - LOAD x26, 2*REGBYTES(sp) // Recover s10 - LOAD x27, 1*REGBYTES(sp) // Recover s11 - LOAD t0, 14*REGBYTES(sp) // Recover mstatus - csrw mstatus, t0 // Store mstatus, enables interrupt + ld ra, 13*8(sp) /* Recover RA */ + ld s0, 12*8(sp) /* Recover s0 */ + ld s1, 11*8(sp) /* Recover s1 */ + ld s2, 10*8(sp) /* Recover s2 */ + ld s3, 9*8(sp) /* Recover s3 */ + ld s4, 8*8(sp) /* Recover s4 */ + ld s5, 7*8(sp) /* Recover s5 */ + ld s6, 6*8(sp) /* Recover s6 */ + ld s7, 5*8(sp) /* Recover s7 */ + ld s8, 4*8(sp) /* Recover s8 */ + ld s9, 3*8(sp) /* Recover s9 */ + ld s10, 2*8(sp) /* Recover s10 */ + ld s11, 1*8(sp) /* Recover s11 */ + ld t0, 14*8(sp) /* Recover mstatus */ + csrw mstatus, t0 /* Store mstatus, enables interrupt */ #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - addi sp, sp, 29*REGBYTES // Recover stack frame + addi sp, sp, 29*8 // Recover stack frame #else - addi sp, sp, 16*REGBYTES // Recover stack frame + addi sp, sp, 16*8 // Recover stack frame #endif ret // Return to thread diff --git a/ports/risc-v64/gnu/src/tx_thread_stack_build.S b/ports/risc-v64/gnu/src/tx_thread_stack_build.S index 34d807ee..a8b32a91 100644 --- a/ports/risc-v64/gnu/src/tx_thread_stack_build.S +++ b/ports/risc-v64/gnu/src/tx_thread_stack_build.S @@ -19,8 +19,6 @@ /**************************************************************************/ /**************************************************************************/ -#include "tx_port.h" - .section .text /**************************************************************************/ /* */ @@ -43,7 +41,7 @@ /* thread_ptr Pointer to thread control blk */ /* function_ptr Pointer to return function */ /* */ -/* OUTPUT */ +/* OUTPUT */ /* */ /* None */ /* */ @@ -138,91 +136,91 @@ If floating point support: Stack Bottom: (higher memory address) */ - LOAD t0, 4*REGBYTES(a0) // Pickup end of stack area - li t1, ~15 // Build 16-byte alignment mask - and t0, t0, t1 // Make sure 16-byte alignment + ld t0, 32(a0) /* Pickup end of stack area */ + li t1, ~15 /* Build 16-byte alignment mask */ + and t0, t0, t1 /* Make sure 16-byte alignment */ /* Actually build the stack frame. */ #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - addi t0, t0, -65*REGBYTES + addi t0, t0, -65*8 #else - addi t0, t0, -32*REGBYTES // Allocate space for the stack frame + addi t0, t0, -32*8 /* Allocate space for the stack frame */ #endif - li t1, 1 // Build stack type - STORE t1, 0*REGBYTES(t0) // Place stack type on the top - STORE x0, 1*REGBYTES(t0) // Initial s11 - STORE x0, 2*REGBYTES(t0) // Initial s10 - STORE x0, 3*REGBYTES(t0) // Initial s9 - STORE x0, 4*REGBYTES(t0) // Initial s8 - STORE x0, 5*REGBYTES(t0) // Initial s7 - STORE x0, 6*REGBYTES(t0) // Initial s6 - STORE x0, 7*REGBYTES(t0) // Initial s5 - STORE x0, 8*REGBYTES(t0) // Initial s4 - STORE x0, 9*REGBYTES(t0) // Initial s3 - STORE x0, 10*REGBYTES(t0) // Initial s2 - STORE x0, 11*REGBYTES(t0) // Initial s1 - STORE x0, 12*REGBYTES(t0) // Initial s0 - STORE x0, 13*REGBYTES(t0) // Initial t6 - STORE x0, 14*REGBYTES(t0) // Initial t5 - STORE x0, 15*REGBYTES(t0) // Initial t4 - STORE x0, 16*REGBYTES(t0) // Initial t3 - STORE x0, 17*REGBYTES(t0) // Initial t2 - STORE x0, 18*REGBYTES(t0) // Initial t1 - STORE x0, 19*REGBYTES(t0) // Initial t0 - STORE x0, 20*REGBYTES(t0) // Initial a7 - STORE x0, 21*REGBYTES(t0) // Initial a6 - STORE x0, 22*REGBYTES(t0) // Initial a5 - STORE x0, 23*REGBYTES(t0) // Initial a4 - STORE x0, 24*REGBYTES(t0) // Initial a3 - STORE x0, 25*REGBYTES(t0) // Initial a2 - STORE x0, 26*REGBYTES(t0) // Initial a1 - STORE x0, 27*REGBYTES(t0) // Initial a0 - STORE x0, 28*REGBYTES(t0) // Initial ra - STORE a1, 30*REGBYTES(t0) // Initial mepc + li t1, 1 /* Build stack type */ + sd t1, 0*8(t0) /* Place stack type on the top */ + sd zero, 1*8(t0) /* Initial s11 */ + sd zero, 2*8(t0) /* Initial s10 */ + sd zero, 3*8(t0) /* Initial s9 */ + sd zero, 4*8(t0) /* Initial s8 */ + sd zero, 5*8(t0) /* Initial s7 */ + sd zero, 6*8(t0) /* Initial s6 */ + sd zero, 7*8(t0) /* Initial s5 */ + sd zero, 8*8(t0) /* Initial s4 */ + sd zero, 9*8(t0) /* Initial s3 */ + sd zero, 10*8(t0) /* Initial s2 */ + sd zero, 11*8(t0) /* Initial s1 */ + sd zero, 12*8(t0) /* Initial s0 */ + sd zero, 13*8(t0) /* Initial t6 */ + sd zero, 14*8(t0) /* Initial t5 */ + sd zero, 15*8(t0) /* Initial t4 */ + sd zero, 16*8(t0) /* Initial t3 */ + sd zero, 17*8(t0) /* Initial t2 */ + sd zero, 18*8(t0) /* Initial t1 */ + sd zero, 19*8(t0) /* Initial t0 */ + sd zero, 20*8(t0) /* Initial a7 */ + sd zero, 21*8(t0) /* Initial a6 */ + sd zero, 22*8(t0) /* Initial a5 */ + sd zero, 23*8(t0) /* Initial a4 */ + sd zero, 24*8(t0) /* Initial a3 */ + sd zero, 25*8(t0) /* Initial a2 */ + sd zero, 26*8(t0) /* Initial a1 */ + sd zero, 27*8(t0) /* Initial a0 */ + sd zero, 28*8(t0) /* Initial ra */ + sd a1, 30*8(t0) /* Initial mepc (thread entry point) */ #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - STORE x0, 31*REGBYTES(t0) // Inital ft0 - STORE x0, 32*REGBYTES(t0) // Inital ft1 - STORE x0, 33*REGBYTES(t0) // Inital ft2 - STORE x0, 34*REGBYTES(t0) // Inital ft3 - STORE x0, 35*REGBYTES(t0) // Inital ft4 - STORE x0, 36*REGBYTES(t0) // Inital ft5 - STORE x0, 37*REGBYTES(t0) // Inital ft6 - STORE x0, 38*REGBYTES(t0) // Inital ft7 - STORE x0, 39*REGBYTES(t0) // Inital fs0 - STORE x0, 40*REGBYTES(t0) // Inital fs1 - STORE x0, 41*REGBYTES(t0) // Inital fa0 - STORE x0, 42*REGBYTES(t0) // Inital fa1 - STORE x0, 43*REGBYTES(t0) // Inital fa2 - STORE x0, 44*REGBYTES(t0) // Inital fa3 - STORE x0, 45*REGBYTES(t0) // Inital fa4 - STORE x0, 46*REGBYTES(t0) // Inital fa5 - STORE x0, 47*REGBYTES(t0) // Inital fa6 - STORE x0, 48*REGBYTES(t0) // Inital fa7 - STORE x0, 49*REGBYTES(t0) // Inital fs2 - STORE x0, 50*REGBYTES(t0) // Inital fs3 - STORE x0, 51*REGBYTES(t0) // Inital fs4 - STORE x0, 52*REGBYTES(t0) // Inital fs5 - STORE x0, 53*REGBYTES(t0) // Inital fs6 - STORE x0, 54*REGBYTES(t0) // Inital fs7 - STORE x0, 55*REGBYTES(t0) // Inital fs8 - STORE x0, 56*REGBYTES(t0) // Inital fs9 - STORE x0, 57*REGBYTES(t0) // Inital fs10 - STORE x0, 58*REGBYTES(t0) // Inital fs11 - STORE x0, 59*REGBYTES(t0) // Inital ft8 - STORE x0, 60*REGBYTES(t0) // Inital ft9 - STORE x0, 61*REGBYTES(t0) // Inital ft10 - STORE x0, 62*REGBYTES(t0) // Inital ft11 - csrr a1, fcsr // Read fcsr and use it for initial value for each thread - STORE a1, 63*REGBYTES(t0) // Initial fscr - STORE x0, 64*REGBYTES(t0) // Reserved word (0) + sd zero, 31*8(t0) /* Initial ft0 */ + sd zero, 32*8(t0) /* Initial ft1 */ + sd zero, 33*8(t0) /* Initial ft2 */ + sd zero, 34*8(t0) /* Initial ft3 */ + sd zero, 35*8(t0) /* Initial ft4 */ + sd zero, 36*8(t0) /* Initial ft5 */ + sd zero, 37*8(t0) /* Initial ft6 */ + sd zero, 38*8(t0) /* Initial ft7 */ + sd zero, 39*8(t0) /* Initial fs0 */ + sd zero, 40*8(t0) /* Initial fs1 */ + sd zero, 41*8(t0) /* Initial fa0 */ + sd zero, 42*8(t0) /* Initial fa1 */ + sd zero, 43*8(t0) /* Initial fa2 */ + sd zero, 44*8(t0) /* Initial fa3 */ + sd zero, 45*8(t0) /* Initial fa4 */ + sd zero, 46*8(t0) /* Initial fa5 */ + sd zero, 47*8(t0) /* Initial fa6 */ + sd zero, 48*8(t0) /* Initial fa7 */ + sd zero, 49*8(t0) /* Initial fs2 */ + sd zero, 50*8(t0) /* Initial fs3 */ + sd zero, 51*8(t0) /* Initial fs4 */ + sd zero, 52*8(t0) /* Initial fs5 */ + sd zero, 53*8(t0) /* Initial fs6 */ + sd zero, 54*8(t0) /* Initial fs7 */ + sd zero, 55*8(t0) /* Initial fs8 */ + sd zero, 56*8(t0) /* Initial fs9 */ + sd zero, 57*8(t0) /* Initial fs10 */ + sd zero, 58*8(t0) /* Initial fs11 */ + sd zero, 59*8(t0) /* Initial ft8 */ + sd zero, 60*8(t0) /* Initial ft9 */ + sd zero, 61*8(t0) /* Initial ft10 */ + sd zero, 62*8(t0) /* Initial ft11 */ + csrr a1, fcsr /* Read fcsr for initial value */ + sd a1, 63*8(t0) /* Initial fcsr */ + sd zero, 64*8(t0) /* Reserved word (0) */ #else - STORE x0, 31*REGBYTES(t0) // Reserved word (0) + sd zero, 31*8(t0) /* Reserved word (0) */ #endif /* Setup stack pointer. */ /* thread_ptr -> tx_thread_stack_ptr = t0; */ - STORE t0, 2*REGBYTES(a0) // Save stack pointer in thread's - ret // control block and return + sd t0, 16(a0) /* Save stack pointer in thread's */ + ret /* control block and return */ /* } */ diff --git a/ports/risc-v64/gnu/src/tx_thread_system_return.S b/ports/risc-v64/gnu/src/tx_thread_system_return.S index 3da67ffb..2e698a62 100644 --- a/ports/risc-v64/gnu/src/tx_thread_system_return.S +++ b/ports/risc-v64/gnu/src/tx_thread_system_return.S @@ -19,8 +19,6 @@ /**************************************************************************/ /**************************************************************************/ -#include "tx_port.h" - .section .text /**************************************************************************/ /* */ @@ -68,99 +66,100 @@ _tx_thread_system_return: /* Save minimal context on the stack. */ + /* sp -= sizeof(stack_frame); */ #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - addi sp, sp, -29*REGBYTES // Allocate space on the stack - with floating point enabled + addi sp, sp, -29*8 /* Allocate space on the stack - with floating point enabled */ #else - addi sp, sp, -16*REGBYTES // Allocate space on the stack - without floating point enabled + addi sp, sp, -16*8 /* Allocate space on the stack - without floating point enabled */ #endif /* Store floating point preserved registers. */ #if defined(__riscv_float_abi_single) - fsw f8, 15*REGBYTES(sp) // Store fs0 - fsw f9, 16*REGBYTES(sp) // Store fs1 - fsw f18, 17*REGBYTES(sp) // Store fs2 - fsw f19, 18*REGBYTES(sp) // Store fs3 - fsw f20, 19*REGBYTES(sp) // Store fs4 - fsw f21, 20*REGBYTES(sp) // Store fs5 - fsw f22, 21*REGBYTES(sp) // Store fs6 - fsw f23, 22*REGBYTES(sp) // Store fs7 - fsw f24, 23*REGBYTES(sp) // Store fs8 - fsw f25, 24*REGBYTES(sp) // Store fs9 - fsw f26, 25*REGBYTES(sp) // Store fs10 - fsw f27, 26*REGBYTES(sp) // Store fs11 + fsw f8, 15*8(sp) /* Store fs0 */ + fsw f9, 16*8(sp) /* Store fs1 */ + fsw f18, 17*8(sp) /* Store fs2 */ + fsw f19, 18*8(sp) /* Store fs3 */ + fsw f20, 19*8(sp) /* Store fs4 */ + fsw f21, 20*8(sp) /* Store fs5 */ + fsw f22, 21*8(sp) /* Store fs6 */ + fsw f23, 22*8(sp) /* Store fs7 */ + fsw f24, 23*8(sp) /* Store fs8 */ + fsw f25, 24*8(sp) /* Store fs9 */ + fsw f26, 25*8(sp) /* Store fs10 */ + fsw f27, 26*8(sp) /* Store fs11 */ csrr t0, fcsr - STORE t0, 27*REGBYTES(sp) // Store fcsr + sd t0, 27*8(sp) /* Store fcsr */ #elif defined(__riscv_float_abi_double) - fsd f8, 15*REGBYTES(sp) // Store fs0 - fsd f9, 16*REGBYTES(sp) // Store fs1 - fsd f18, 17*REGBYTES(sp) // Store fs2 - fsd f19, 18*REGBYTES(sp) // Store fs3 - fsd f20, 19*REGBYTES(sp) // Store fs4 - fsd f21, 20*REGBYTES(sp) // Store fs5 - fsd f22, 21*REGBYTES(sp) // Store fs6 - fsd f23, 22*REGBYTES(sp) // Store fs7 - fsd f24, 23*REGBYTES(sp) // Store fs8 - fsd f25, 24*REGBYTES(sp) // Store fs9 - fsd f26, 25*REGBYTES(sp) // Store fs10 - fsd f27, 26*REGBYTES(sp) // Store fs11 + fsd f8, 15*8(sp) /* Store fs0 */ + fsd f9, 16*8(sp) /* Store fs1 */ + fsd f18, 17*8(sp) /* Store fs2 */ + fsd f19, 18*8(sp) /* Store fs3 */ + fsd f20, 19*8(sp) /* Store fs4 */ + fsd f21, 20*8(sp) /* Store fs5 */ + fsd f22, 21*8(sp) /* Store fs6 */ + fsd f23, 22*8(sp) /* Store fs7 */ + fsd f24, 23*8(sp) /* Store fs8 */ + fsd f25, 24*8(sp) /* Store fs9 */ + fsd f26, 25*8(sp) /* Store fs10 */ + fsd f27, 26*8(sp) /* Store fs11 */ csrr t0, fcsr - STORE t0, 27*REGBYTES(sp) // Store fcsr + sd t0, 27*8(sp) /* Store fcsr */ #endif - STORE x0, 0(sp) // Solicited stack type - STORE x1, 13*REGBYTES(sp) // Save RA - STORE x8, 12*REGBYTES(sp) // Save s0 - STORE x9, 11*REGBYTES(sp) // Save s1 - STORE x18, 10*REGBYTES(sp) // Save s2 - STORE x19, 9*REGBYTES(sp) // Save s3 - STORE x20, 8*REGBYTES(sp) // Save s4 - STORE x21, 7*REGBYTES(sp) // Save s5 - STORE x22, 6*REGBYTES(sp) // Save s6 - STORE x23, 5*REGBYTES(sp) // Save s7 - STORE x24, 4*REGBYTES(sp) // Save s8 - STORE x25, 3*REGBYTES(sp) // Save s9 - STORE x26, 2*REGBYTES(sp) // Save s10 - STORE x27, 1*REGBYTES(sp) // Save s11 - csrr t0, mstatus // Pickup mstatus - STORE t0, 14*REGBYTES(sp) // Save mstatus + sd zero, 0(sp) /* Solicited stack type */ + sd ra, 13*8(sp) /* Save return address */ + sd s0, 12*8(sp) /* Save s0 */ + sd s1, 11*8(sp) /* Save s1 */ + sd s2, 10*8(sp) /* Save s2 */ + sd s3, 9*8(sp) /* Save s3 */ + sd s4, 8*8(sp) /* Save s4 */ + sd s5, 7*8(sp) /* Save s5 */ + sd s6, 6*8(sp) /* Save s6 */ + sd s7, 5*8(sp) /* Save s7 */ + sd s8, 4*8(sp) /* Save s8 */ + sd s9, 3*8(sp) /* Save s9 */ + sd s10, 2*8(sp) /* Save s10 */ + sd s11, 1*8(sp) /* Save s11 */ + csrr t0, mstatus /* Pickup mstatus */ + sd t0, 14*8(sp) /* Save mstatus */ - /* Lockout interrupts. - will be enabled in _tx_thread_schedule */ + /* Lockout interrupts. will be enabled in _tx_thread_schedule */ - csrci mstatus, 0xF + csrci mstatus, 0x08 /* Disable interrupts (MIE bit 3) */ #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - call _tx_execution_thread_exit // Call the thread execution exit function + call _tx_execution_thread_exit /* Call the thread execution exit function */ #endif - la t0, _tx_thread_current_ptr // Pickup address of pointer - LOAD t1, 0(t0) // Pickup current thread pointer - la t2,_tx_thread_system_stack_ptr // Pickup stack pointer address + la t0, _tx_thread_current_ptr /* Pickup address of pointer */ + ld t1, 0(t0) /* Pickup current thread pointer */ + la t2, _tx_thread_system_stack_ptr /* Pickup stack pointer address */ /* Save current stack and switch to system stack. */ /* _tx_thread_current_ptr -> tx_thread_stack_ptr = SP; SP = _tx_thread_system_stack_ptr; */ - STORE sp, 2*REGBYTES(t1) // Save stack pointer - LOAD sp, 0(t2) // Switch to system stack + sd sp, 16(t1) /* Save stack pointer */ + ld sp, 0(t2) /* Switch to system stack */ /* Determine if the time-slice is active. */ /* if (_tx_timer_time_slice) { */ - la t4, _tx_timer_time_slice // Pickup time slice variable addr - LOAD t3, 0(t4) // Pickup time slice value - la t2, _tx_thread_schedule // Pickup address of scheduling loop - beqz t3, _tx_thread_dont_save_ts // If no time-slice, don't save it + la t4, _tx_timer_time_slice /* Pickup time slice variable addr */ + ld t3, 0(t4) /* Pickup time slice value */ + la t2, _tx_thread_schedule /* Pickup address of scheduling loop */ + beqz t3, _tx_thread_dont_save_ts /* If no time-slice, don't save it */ /* Save time-slice for the thread and clear the current time-slice. */ /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; _tx_timer_time_slice = 0; */ - STORE t3, 6*REGBYTES(t1) // Save current time-slice for thread - STORE x0, 0(t4) // Clear time-slice variable + sd t3, 48(t1) /* Save current time-slice for thread */ + sd zero, 0(t4) /* Clear time-slice variable */ /* } */ _tx_thread_dont_save_ts: @@ -168,7 +167,7 @@ _tx_thread_dont_save_ts: /* Clear the current thread pointer. */ /* _tx_thread_current_ptr = TX_NULL; */ - STORE x0, 0(t0) // Clear current thread pointer + sd x0, 0(t0) // Clear current thread pointer jr t2 // Return to thread scheduler /* } */ diff --git a/ports/risc-v64/gnu/src/tx_timer_interrupt.S b/ports/risc-v64/gnu/src/tx_timer_interrupt.S new file mode 100644 index 00000000..4b2acf61 --- /dev/null +++ b/ports/risc-v64/gnu/src/tx_timer_interrupt.S @@ -0,0 +1,210 @@ +/*************************************************************************** + * Copyright (c) 2024 Microsoft Corporation + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .section .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt RISC-V64/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_timer_interrupt(VOID) +{ */ + .global _tx_timer_interrupt +_tx_timer_interrupt: + + /* Increment the system clock. */ + /* _tx_timer_system_clock++; */ + + la t0, _tx_timer_system_clock /* Pickup address of system clock */ + ld t1, 0(t0) /* Pickup system clock */ + la t2, _tx_timer_time_slice /* Pickup address of time slice */ + ld t3, 0(t2) /* Pickup time slice */ + addi t1, t1, 1 /* Increment system clock */ + sd t1, 0(t0) /* Store new system clock */ + li t6, 0 /* Clear local expired flag */ + + /* Test for time-slice expiration. */ + /* if (_tx_timer_time_slice) + { */ + + beqz t3, _tx_timer_no_time_slice /* If 0, skip time slice processing */ + addi t3, t3, -1 /* Decrement the time slice */ + + /* Decrement the time_slice. */ + /* _tx_timer_time_slice--; */ + + sd t3, 0(t2) /* Store new time slice */ + + /* Check for expiration. */ + /* if (_tx_timer_time_slice == 0) */ + + bgtz t3, _tx_timer_no_time_slice /* If not 0, has not expired yet */ + li t1, 1 /* Build expired flag */ + + /* Set the time-slice expired flag. */ + /* _tx_timer_expired_time_slice = TX_TRUE; */ + + la t4, _tx_timer_expired_time_slice /* Get address of expired flag */ + sw t1, 0(t4) /* Set expired flag (UINT) */ + ori t6, t6, 1 /* Set local expired flag */ + + /* } */ + +_tx_timer_no_time_slice: + + /* Test for timer expiration. */ + /* if (*_tx_timer_current_ptr) + { */ + + la t0, _tx_timer_current_ptr /* Pickup address of current ptr */ + ld t1, 0(t0) /* Pickup current pointer (double word) */ + ld t3, 0(t1) /* Pickup the current timer entry (double word) */ + la t2, _tx_timer_expired /* Pickup address of timer expired flag */ + li t4, 1 /* Build TX_TRUE flag */ + beqz t3, _tx_timer_no_timer /* If NULL, no timer has expired */ + + /* Set expiration flag. */ + /* _tx_timer_expired = TX_TRUE; */ + + ori t6, t6, 2 /* Set local expired flag */ + sw t4, 0(t2) /* Set expired flag in memory (UINT) */ + j _tx_timer_done /* Finished timer processing */ + + + /* } + else + { */ +_tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + /* _tx_timer_current_ptr++; */ + + /* Check for wrap-around. */ + /* if (_tx_timer_current_ptr == _tx_timer_list_end) */ + + la t2, _tx_timer_list_end /* Pickup address of list end pointer */ + ld t3, 0(t2) /* Pickup actual list end */ + addi t1, t1, 8 /* Point to next timer entry */ + sd t1, 0(t0) /* Store new timer pointer */ + bne t1, t3, _tx_timer_skip_wrap /* If not same, good pointer */ + + /* Wrap to beginning of list. */ + /* _tx_timer_current_ptr = _tx_timer_list_start; */ + + la t2, _tx_timer_list_start /* Pickup address of list start pointer */ + ld t4, 0(t2) /* Pickup start of the list */ + sd t4, 0(t0) /* Store new timer pointer */ + + +_tx_timer_skip_wrap: + /* } */ + +_tx_timer_done: + + + /* See if anything has expired. */ + /* if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + { */ + + beqz t6, _tx_timer_nothing_expired /* If nothing expired skip the rest */ + addi sp, sp, -16 /* Allocate some storage on the stack */ + sd t6, 0(sp) /* Save local expired flag */ + sd ra, 8(sp) /* Save ra (8-byte aligned) */ + + /* Did a timer expire? */ + /* if (_tx_timer_expired) + { */ + + andi t2, t6, 2 /* Isolate the timer expired bit */ + beqz t2, _tx_timer_dont_activate /* No, timer not expired */ + + /* Call the timer expiration processing. */ + /* _tx_timer_expiration_process(void); */ + + call _tx_timer_expiration_process /* Call _tx_timer_expiration_process */ + ld t6, 0(sp) /* Recover local expired flag */ + + /* } */ +_tx_timer_dont_activate: + + /* Did time slice expire? */ + /* if (_tx_timer_expired_time_slice) + { */ + + andi t2, t6, 1 /* Is the timer expired bit set? */ + beqz t2, _tx_timer_not_ts_expiration /* If not, skip time slice processing */ + + /* Time slice interrupted thread. */ + /* _tx_thread_time_slice(); */ + + call _tx_thread_time_slice /* Call time slice */ + + /* } */ + +_tx_timer_not_ts_expiration: + + ld ra, 8(sp) /* Recover ra */ + addi sp, sp, 16 /* Recover stack space */ + /* } */ + +_tx_timer_nothing_expired: + + ret + +/* } */ diff --git a/ports/risc-v64/gnu/src/tx_timer_interrupt.c b/ports/risc-v64/gnu/src/tx_timer_interrupt.c deleted file mode 100644 index 3c90d0a6..00000000 --- a/ports/risc-v64/gnu/src/tx_timer_interrupt.c +++ /dev/null @@ -1,134 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Timer */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - -#define TX_SOURCE_CODE - -/* Include necessary system files. */ - -#include "tx_api.h" -#include "tx_timer.h" -#include "tx_thread.h" - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_timer_interrupt RISC-V64/GNU */ -/* 6.2.1 */ -/* AUTHOR */ -/* */ -/* Scott Larson, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function processes the hardware timer interrupt. This */ -/* processing includes incrementing the system clock and checking for */ -/* time slice and/or timer expiration. If either is found, the */ -/* interrupt context save/restore functions are called along with the */ -/* expiration functions. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_timer_expiration_process Timer expiration processing */ -/* _tx_thread_time_slice Time slice interrupted thread */ -/* */ -/* CALLED BY */ -/* */ -/* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ -/**************************************************************************/ -VOID _tx_timer_interrupt(VOID) -{ - /* Increment system clock. */ - _tx_timer_system_clock++; - - /* Test for time-slice expiration. */ - if (_tx_timer_time_slice) - { - /* Decrement the time_slice. */ - _tx_timer_time_slice--; - - /* Check for expiration. */ - if (_tx_timer_time_slice == 0) - { - - /* Set the time-slice expired flag. */ - _tx_timer_expired_time_slice = TX_TRUE; - } - } - - /* Test for timer expiration. */ - if (*_tx_timer_current_ptr) - { - - /* Set expiration flag. */ - _tx_timer_expired = TX_TRUE; - } - else - { - - /* No timer expired, increment the timer pointer. */ - _tx_timer_current_ptr++; - - /* Check for wrap-around. */ - if (_tx_timer_current_ptr == _tx_timer_list_end) - { - - /* Wrap to beginning of list. */ - _tx_timer_current_ptr = _tx_timer_list_start; - } - } - - /* See if anything has expired. */ - if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) - { - - /* Did a timer expire? */ - if (_tx_timer_expired) - { - - /* Process timer expiration. */ - _tx_timer_expiration_process(); - } - - /* Did time slice expire? */ - if (_tx_timer_expired_time_slice) - { - - /* Time slice interrupted thread. */ - _tx_thread_time_slice(); - } - } -} From 99ed67df5afeeac52827c2681438a4627c4198d7 Mon Sep 17 00:00:00 2001 From: Akif Ejaz Date: Mon, 26 Jan 2026 16:08:51 +0500 Subject: [PATCH 05/19] few cleanups Signed-off-by: Akif Ejaz --- ports/risc-v64/gnu/src/tx_thread_context_save.S | 11 +++++++++++ ports/risc-v64/gnu/src/tx_thread_interrupt_control.S | 2 -- ports/risc-v64/gnu/src/tx_thread_schedule.S | 1 - ports/risc-v64/gnu/src/tx_timer_interrupt.S | 6 +++--- 4 files changed, 14 insertions(+), 6 deletions(-) diff --git a/ports/risc-v64/gnu/src/tx_thread_context_save.S b/ports/risc-v64/gnu/src/tx_thread_context_save.S index 30704850..13281d7f 100644 --- a/ports/risc-v64/gnu/src/tx_thread_context_save.S +++ b/ports/risc-v64/gnu/src/tx_thread_context_save.S @@ -1,3 +1,14 @@ +/*************************************************************************** + * Copyright (c) 2024 Microsoft Corporation + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + /**************************************************************************/ /**************************************************************************/ /** */ diff --git a/ports/risc-v64/gnu/src/tx_thread_interrupt_control.S b/ports/risc-v64/gnu/src/tx_thread_interrupt_control.S index 57b25a52..a540ffdc 100644 --- a/ports/risc-v64/gnu/src/tx_thread_interrupt_control.S +++ b/ports/risc-v64/gnu/src/tx_thread_interrupt_control.S @@ -19,8 +19,6 @@ /**************************************************************************/ /**************************************************************************/ - /* Define which mstatus bits this function will modify/return. */ - /* MSTATUS_MIE bit 3 = Machine Interrupt Enable */ .section .text /**************************************************************************/ diff --git a/ports/risc-v64/gnu/src/tx_thread_schedule.S b/ports/risc-v64/gnu/src/tx_thread_schedule.S index 4da4c244..52f865c2 100644 --- a/ports/risc-v64/gnu/src/tx_thread_schedule.S +++ b/ports/risc-v64/gnu/src/tx_thread_schedule.S @@ -67,7 +67,6 @@ _tx_thread_schedule: /* Enable interrupts. */ - /* mstatus |= MIE; */ csrsi mstatus, 0x08 /* Enable interrupts (MIE bit 3) */ /* Wait for a thread to execute. */ diff --git a/ports/risc-v64/gnu/src/tx_timer_interrupt.S b/ports/risc-v64/gnu/src/tx_timer_interrupt.S index 4b2acf61..146b08f0 100644 --- a/ports/risc-v64/gnu/src/tx_timer_interrupt.S +++ b/ports/risc-v64/gnu/src/tx_timer_interrupt.S @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026 10xEngineers * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -29,7 +29,7 @@ /* 6.2.1 */ /* AUTHOR */ /* */ -/* Scott Larson, Microsoft Corporation */ +/* Akif Ejaz, 10xEngineers */ /* */ /* DESCRIPTION */ /* */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* 01-20-2023 Akif Ejaz Initial Version 6.2.1 */ /* */ /**************************************************************************/ /* VOID _tx_timer_interrupt(VOID) From 21256bed516345f0918f49b314758c60b5691562 Mon Sep 17 00:00:00 2001 From: Akif Ejaz Date: Thu, 5 Feb 2026 16:16:59 +0500 Subject: [PATCH 06/19] Cleanup the macros in tx_port.h & comments in inc/*.S - removed the trailing whitespaces Signed-off-by: Akif Ejaz --- ports/risc-v64/gnu/inc/tx_port.h | 19 +- .../gnu/src/tx_initialize_low_level.S | 28 +- .../gnu/src/tx_thread_context_restore.S | 340 +++++++++--------- .../risc-v64/gnu/src/tx_thread_context_save.S | 278 +++++++------- .../gnu/src/tx_thread_interrupt_control.S | 20 +- ports/risc-v64/gnu/src/tx_thread_schedule.S | 210 +++++------ .../risc-v64/gnu/src/tx_thread_stack_build.S | 152 ++++---- .../gnu/src/tx_thread_system_return.S | 120 +++---- ports/risc-v64/gnu/src/tx_timer_interrupt.S | 178 ++++----- 9 files changed, 677 insertions(+), 668 deletions(-) diff --git a/ports/risc-v64/gnu/inc/tx_port.h b/ports/risc-v64/gnu/inc/tx_port.h index 346083e5..d2385358 100644 --- a/ports/risc-v64/gnu/inc/tx_port.h +++ b/ports/risc-v64/gnu/inc/tx_port.h @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -236,8 +236,17 @@ UINT _tx_thread_interrupt_control(UIN #define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; -#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); -#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); +#define TX_DISABLE __asm__ volatile("csrrci %0, mstatus, 8" : "=r" (interrupt_save) :: "memory"); +#define TX_RESTORE { \ + unsigned long _temp_mstatus; \ + __asm__ volatile( \ + "csrc mstatus, 8\n" \ + "andi %0, %1, 8\n" \ + "csrs mstatus, %0" \ + : "=&r" (_temp_mstatus) \ + : "r" (interrupt_save) \ + : "memory"); \ + } #else diff --git a/ports/risc-v64/gnu/src/tx_initialize_low_level.S b/ports/risc-v64/gnu/src/tx_initialize_low_level.S index 68150c18..34003151 100644 --- a/ports/risc-v64/gnu/src/tx_initialize_low_level.S +++ b/ports/risc-v64/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,18 +74,18 @@ _tx_initialize_low_level: /* Save the system stack pointer. */ /* _tx_thread_system_stack_ptr = sp; */ la t0, _tx_thread_system_stack_ptr - sd sp, 0(t0) /* Save system stack pointer */ + sd sp, 0(t0) // Save system stack pointer /* Pickup first free address. */ /* _tx_initialize_unused_memory(__tx_free_memory_start); */ - la t0, __tx_free_memory_start /* Pickup first free address */ + la t0, __tx_free_memory_start // Pickup first free address la t1, _tx_initialize_unused_memory - sd t0, 0(t1) /* Save unused memory address */ + sd t0, 0(t1) // Save unused memory address /* Initialize floating point control/status register if floating point is enabled. */ #ifdef __riscv_flen li t0, 0 - csrw fcsr, t0 /* Clear FP control/status register */ + csrw fcsr, t0 // Clear FP control/status register #endif ret @@ -93,23 +93,23 @@ _tx_initialize_low_level: /* Timer Interrupt Handler Note: Platform-specific implementations must provide their own timer ISR. The timer interrupt handler should follow this execution flow: - + 1. Disable interrupts (if not done by hardware exception entry) 2. Allocate interrupt stack frame (65*8 bytes with FP, 32*8 bytes without) 3. Save RA (x1) on the stack at offset 28*8 4. Call _tx_thread_context_save to save thread context 5. Call _tx_timer_interrupt to process the timer tick 6. Call _tx_thread_context_restore to resume execution (does not return) - + Example (for CLINT timer): - + _tx_timer_interrupt_handler: - addi sp, sp, -32*8 - sd ra, 28*8(sp) + addi sp, sp, -32*8 + sd ra, 28*8(sp) call _tx_thread_context_save call _tx_timer_interrupt - j _tx_thread_context_restore - + j _tx_thread_context_restore + The port assumes Machine mode (M-mode) execution. For Supervisor mode (S-mode), use sstatus and SIE/SPIE instead of mstatus. See the RISC-V Privileged Specification for more details. */ diff --git a/ports/risc-v64/gnu/src/tx_thread_context_restore.S b/ports/risc-v64/gnu/src/tx_thread_context_restore.S index edacb8b6..1080e617 100644 --- a/ports/risc-v64/gnu/src/tx_thread_context_restore.S +++ b/ports/risc-v64/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,21 +68,21 @@ _tx_thread_context_restore: /* Lockout interrupts. */ - csrci mstatus, 0x08 /* Disable interrupts (MIE bit 3) */ + csrci mstatus, 0x08 // Disable interrupts (MIE bit 3) #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - call _tx_execution_isr_exit /* Call the ISR execution exit function */ + call _tx_execution_isr_exit // Call the ISR execution exit function #endif /* Determine if interrupts are nested. */ /* if (--_tx_thread_system_state) { */ - la t0, _tx_thread_system_state /* Pickup addr of nested interrupt count */ - ld t1, 0(t0) /* Pickup nested interrupt count */ - addi t1, t1, -1 /* Decrement the nested interrupt counter */ - sd t1, 0(t0) /* Store new nested count */ - beqz t1, _tx_thread_not_nested_restore /* If 0, not nested restore */ + la t0, _tx_thread_system_state // Pickup addr of nested interrupt count + ld t1, 0(t0) // Pickup nested interrupt count + addi t1, t1, -1 // Decrement the nested interrupt counter + sd t1, 0(t0) // Store new nested count + beqz t1, _tx_thread_not_nested_restore // If 0, not nested restore /* Interrupts are nested. */ @@ -91,51 +91,51 @@ _tx_thread_context_restore: /* Recover floating point registers. */ #if defined(__riscv_float_abi_single) - flw f0, 31*8(sp) /* Recover ft0 */ - flw f1, 32*8(sp) /* Recover ft1 */ - flw f2, 33*8(sp) /* Recover ft2 */ - flw f3, 34*8(sp) /* Recover ft3 */ - flw f4, 35*8(sp) /* Recover ft4 */ - flw f5, 36*8(sp) /* Recover ft5 */ - flw f6, 37*8(sp) /* Recover ft6 */ - flw f7, 38*8(sp) /* Recover ft7 */ - flw f10,41*8(sp) /* Recover fa0 */ - flw f11,42*8(sp) /* Recover fa1 */ - flw f12,43*8(sp) /* Recover fa2 */ - flw f13,44*8(sp) /* Recover fa3 */ - flw f14,45*8(sp) /* Recover fa4 */ - flw f15,46*8(sp) /* Recover fa5 */ - flw f16,47*8(sp) /* Recover fa6 */ - flw f17,48*8(sp) /* Recover fa7 */ - flw f28,59*8(sp) /* Recover ft8 */ - flw f29,60*8(sp) /* Recover ft9 */ - flw f30,61*8(sp) /* Recover ft10 */ - flw f31,62*8(sp) /* Recover ft11 */ - ld t0, 63*8(sp) /* Recover fcsr */ - csrw fcsr, t0 /* Restore fcsr */ + flw f0, 31*8(sp) // Recover ft0 + flw f1, 32*8(sp) // Recover ft1 + flw f2, 33*8(sp) // Recover ft2 + flw f3, 34*8(sp) // Recover ft3 + flw f4, 35*8(sp) // Recover ft4 + flw f5, 36*8(sp) // Recover ft5 + flw f6, 37*8(sp) // Recover ft6 + flw f7, 38*8(sp) // Recover ft7 + flw f10,41*8(sp) // Recover fa0 + flw f11,42*8(sp) // Recover fa1 + flw f12,43*8(sp) // Recover fa2 + flw f13,44*8(sp) // Recover fa3 + flw f14,45*8(sp) // Recover fa4 + flw f15,46*8(sp) // Recover fa5 + flw f16,47*8(sp) // Recover fa6 + flw f17,48*8(sp) // Recover fa7 + flw f28,59*8(sp) // Recover ft8 + flw f29,60*8(sp) // Recover ft9 + flw f30,61*8(sp) // Recover ft10 + flw f31,62*8(sp) // Recover ft11 + ld t0, 63*8(sp) // Recover fcsr + csrw fcsr, t0 // Restore fcsr #elif defined(__riscv_float_abi_double) - fld f0, 31*8(sp) /* Recover ft0 */ - fld f1, 32*8(sp) /* Recover ft1 */ - fld f2, 33*8(sp) /* Recover ft2 */ - fld f3, 34*8(sp) /* Recover ft3 */ - fld f4, 35*8(sp) /* Recover ft4 */ - fld f5, 36*8(sp) /* Recover ft5 */ - fld f6, 37*8(sp) /* Recover ft6 */ - fld f7, 38*8(sp) /* Recover ft7 */ - fld f10,41*8(sp) /* Recover fa0 */ - fld f11,42*8(sp) /* Recover fa1 */ - fld f12,43*8(sp) /* Recover fa2 */ - fld f13,44*8(sp) /* Recover fa3 */ - fld f14,45*8(sp) /* Recover fa4 */ - fld f15,46*8(sp) /* Recover fa5 */ - fld f16,47*8(sp) /* Recover fa6 */ - fld f17,48*8(sp) /* Recover fa7 */ - fld f28,59*8(sp) /* Recover ft8 */ - fld f29,60*8(sp) /* Recover ft9 */ - fld f30,61*8(sp) /* Recover ft10 */ - fld f31,62*8(sp) /* Recover ft11 */ - ld t0, 63*8(sp) /* Recover fcsr */ - csrw fcsr, t0 + fld f0, 31*8(sp) // Recover ft0 + fld f1, 32*8(sp) // Recover ft1 + fld f2, 33*8(sp) // Recover ft2 + fld f3, 34*8(sp) // Recover ft3 + fld f4, 35*8(sp) // Recover ft4 + fld f5, 36*8(sp) // Recover ft5 + fld f6, 37*8(sp) // Recover ft6 + fld f7, 38*8(sp) // Recover ft7 + fld f10,41*8(sp) // Recover fa0 + fld f11,42*8(sp) // Recover fa1 + fld f12,43*8(sp) // Recover fa2 + fld f13,44*8(sp) // Recover fa3 + fld f14,45*8(sp) // Recover fa4 + fld f15,46*8(sp) // Recover fa5 + fld f16,47*8(sp) // Recover fa6 + fld f17,48*8(sp) // Recover fa7 + fld f28,59*8(sp) // Recover ft8 + fld f29,60*8(sp) // Recover ft9 + fld f30,61*8(sp) // Recover ft10 + fld f31,62*8(sp) // Recover ft11 + ld t0, 63*8(sp) // Recover fcsr + csrw fcsr, t0 #endif /* Recover standard registers. */ @@ -145,56 +145,56 @@ _tx_thread_context_restore: Also skip the saved registers since they have been restored by any function we called, except s0 since we use it ourselves. */ - ld t0, 30*8(sp) /* Recover mepc */ - csrw mepc, t0 /* Setup mepc */ + ld t0, 30*8(sp) // Recover mepc + csrw mepc, t0 // Setup mepc /* Compose mstatus via read/modify/write to avoid clobbering unrelated bits. Set MPIE and restore MPP to Machine, preserve other fields. */ - + csrr t1, mstatus /* Clear MPP/MPIE/MIE bits in t1 then set desired values. */ - li t2, 0x1888 /* MPP(0x1800) | MPIE(0x80) | MIE(0x08) */ - li t3, 0x1800 /* Set MPP to Machine mode (bits 12:11) */ + li t2, 0x1888 // MPP(0x1800) | MPIE(0x80) | MIE(0x08) + li t3, 0x1800 // Set MPP to Machine mode (bits 12:11) /* Construct new mstatus in t1: clear mask bits, set MPP/MPIE and optionally FP bit, preserve everything except the bits we will modify. */ - li t4, ~0x1888 /* Clear mask for MPP/MPIE/MIE */ + li t4, ~0x1888 // Clear mask for MPP/MPIE/MIE and t1, t1, t4 or t1, t1, t3 #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - li t0, 0x2000 /* Set FS bits (bits 14:13 to 01) for FP state */ + li t0, 0x2000 // Set FS bits (bits 14:13 to 01) for FP state or t1, t1, t0 #endif - csrw mstatus, t1 /* Update mstatus safely */ + csrw mstatus, t1 // Update mstatus safely - ld ra, 28*8(sp) /* Recover return address */ - ld t0, 19*8(sp) /* Recover t0 */ - ld t1, 18*8(sp) /* Recover t1 */ - ld t2, 17*8(sp) /* Recover t2 */ - ld s0, 12*8(sp) /* Recover s0 */ - ld a0, 27*8(sp) /* Recover a0 */ - ld a1, 26*8(sp) /* Recover a1 */ - ld a2, 25*8(sp) /* Recover a2 */ - ld a3, 24*8(sp) /* Recover a3 */ - ld a4, 23*8(sp) /* Recover a4 */ - ld a5, 22*8(sp) /* Recover a5 */ - ld a6, 21*8(sp) /* Recover a6 */ - ld a7, 20*8(sp) /* Recover a7 */ - ld t3, 16*8(sp) /* Recover t3 */ - ld t4, 15*8(sp) /* Recover t4 */ - ld t5, 14*8(sp) /* Recover t5 */ - ld t6, 13*8(sp) /* Recover t6 */ + ld ra, 28*8(sp) // Recover return address + ld t0, 19*8(sp) // Recover t0 + ld t1, 18*8(sp) // Recover t1 + ld t2, 17*8(sp) // Recover t2 + ld s0, 12*8(sp) // Recover s0 + ld a0, 27*8(sp) // Recover a0 + ld a1, 26*8(sp) // Recover a1 + ld a2, 25*8(sp) // Recover a2 + ld a3, 24*8(sp) // Recover a3 + ld a4, 23*8(sp) // Recover a4 + ld a5, 22*8(sp) // Recover a5 + ld a6, 21*8(sp) // Recover a6 + ld a7, 20*8(sp) // Recover a7 + ld t3, 16*8(sp) // Recover t3 + ld t4, 15*8(sp) // Recover t4 + ld t5, 14*8(sp) // Recover t5 + ld t6, 13*8(sp) // Recover t6 #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - addi sp, sp, 65*8 /* Recover stack frame - with floating point enabled */ + addi sp, sp, 65*8 // Recover stack frame - with floating point enabled #else - addi sp, sp, 32*8 /* Recover stack frame - without floating point enabled */ + addi sp, sp, 32*8 // Recover stack frame - without floating point enabled #endif - mret /* Return to point of interrupt */ + mret // Return to point of interrupt /* } */ _tx_thread_not_nested_restore: @@ -203,17 +203,17 @@ _tx_thread_not_nested_restore: || (_tx_thread_preempt_disable)) { */ - la t0, _tx_thread_current_ptr /* Pickup current thread pointer address */ - ld t1, 0(t0) /* Pickup current thread pointer */ - beqz t1, _tx_thread_idle_system_restore /* If NULL, idle system restore */ + la t0, _tx_thread_current_ptr // Pickup current thread pointer address + ld t1, 0(t0) // Pickup current thread pointer + beqz t1, _tx_thread_idle_system_restore // If NULL, idle system restore - la t0, _tx_thread_preempt_disable /* Pickup preempt disable flag address */ - lw t2, 0(t0) /* Pickup preempt disable flag (UINT) */ - bgtz t2, _tx_thread_no_preempt_restore /* If set, restore interrupted thread */ + la t0, _tx_thread_preempt_disable // Pickup preempt disable flag address + lw t2, 0(t0) // Pickup preempt disable flag (UINT) + bgtz t2, _tx_thread_no_preempt_restore // If set, restore interrupted thread - la t0, _tx_thread_execute_ptr /* Pickup thread execute pointer address */ - ld t2, 0(t0) /* Pickup thread execute pointer */ - bne t1, t2, _tx_thread_preempt_restore /* If higher-priority thread is ready, preempt */ + la t0, _tx_thread_execute_ptr // Pickup thread execute pointer address + ld t2, 0(t0) // Pickup thread execute pointer + bne t1, t2, _tx_thread_preempt_restore // If higher-priority thread is ready, preempt _tx_thread_no_preempt_restore: @@ -222,55 +222,55 @@ _tx_thread_no_preempt_restore: /* Pickup the saved stack pointer. */ /* sp = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ - ld sp, 16(t1) /* Switch back to thread's stack */ + ld sp, 16(t1) // Switch back to thread's stack /* Recover floating point registers. */ #if defined(__riscv_float_abi_single) - flw f0, 31*8(sp) /* Recover ft0 */ - flw f1, 32*8(sp) /* Recover ft1 */ - flw f2, 33*8(sp) /* Recover ft2 */ - flw f3, 34*8(sp) /* Recover ft3 */ - flw f4, 35*8(sp) /* Recover ft4 */ - flw f5, 36*8(sp) /* Recover ft5 */ - flw f6, 37*8(sp) /* Recover ft6 */ - flw f7, 38*8(sp) /* Recover ft7 */ - flw f10,41*8(sp) /* Recover fa0 */ - flw f11,42*8(sp) /* Recover fa1 */ - flw f12,43*8(sp) /* Recover fa2 */ - flw f13,44*8(sp) /* Recover fa3 */ - flw f14,45*8(sp) /* Recover fa4 */ - flw f15,46*8(sp) /* Recover fa5 */ - flw f16,47*8(sp) /* Recover fa6 */ - flw f17,48*8(sp) /* Recover fa7 */ - flw f28,59*8(sp) /* Recover ft8 */ - flw f29,60*8(sp) /* Recover ft9 */ - flw f30,61*8(sp) /* Recover ft10 */ - flw f31,62*8(sp) /* Recover ft11 */ - ld t0, 63*8(sp) /* Recover fcsr */ - csrw fcsr, t0 /* Restore fcsr */ + flw f0, 31*8(sp) // Recover ft0 + flw f1, 32*8(sp) // Recover ft1 + flw f2, 33*8(sp) // Recover ft2 + flw f3, 34*8(sp) // Recover ft3 + flw f4, 35*8(sp) // Recover ft4 + flw f5, 36*8(sp) // Recover ft5 + flw f6, 37*8(sp) // Recover ft6 + flw f7, 38*8(sp) // Recover ft7 + flw f10,41*8(sp) // Recover fa0 + flw f11,42*8(sp) // Recover fa1 + flw f12,43*8(sp) // Recover fa2 + flw f13,44*8(sp) // Recover fa3 + flw f14,45*8(sp) // Recover fa4 + flw f15,46*8(sp) // Recover fa5 + flw f16,47*8(sp) // Recover fa6 + flw f17,48*8(sp) // Recover fa7 + flw f28,59*8(sp) // Recover ft8 + flw f29,60*8(sp) // Recover ft9 + flw f30,61*8(sp) // Recover ft10 + flw f31,62*8(sp) // Recover ft11 + ld t0, 63*8(sp) // Recover fcsr + csrw fcsr, t0 // Restore fcsr #elif defined(__riscv_float_abi_double) - fld f0, 31*8(sp) /* Recover ft0 */ - fld f1, 32*8(sp) /* Recover ft1 */ - fld f2, 33*8(sp) /* Recover ft2 */ - fld f3, 34*8(sp) /* Recover ft3 */ - fld f4, 35*8(sp) /* Recover ft4 */ - fld f5, 36*8(sp) /* Recover ft5 */ - fld f6, 37*8(sp) /* Recover ft6 */ - fld f7, 38*8(sp) /* Recover ft7 */ - fld f10,41*8(sp) /* Recover fa0 */ - fld f11,42*8(sp) /* Recover fa1 */ - fld f12,43*8(sp) /* Recover fa2 */ - fld f13,44*8(sp) /* Recover fa3 */ - fld f14,45*8(sp) /* Recover fa4 */ - fld f15,46*8(sp) /* Recover fa5 */ - fld f16,47*8(sp) /* Recover fa6 */ - fld f17,48*8(sp) /* Recover fa7 */ - fld f28,59*8(sp) /* Recover ft8 */ - fld f29,60*8(sp) /* Recover ft9 */ - fld f30,61*8(sp) /* Recover ft10 */ - fld f31,62*8(sp) /* Recover ft11 */ - ld t0, 63*8(sp) /* Recover fcsr */ - csrw fcsr, t0 /* Restore fcsr */ + fld f0, 31*8(sp) // Recover ft0 + fld f1, 32*8(sp) // Recover ft1 + fld f2, 33*8(sp) // Recover ft2 + fld f3, 34*8(sp) // Recover ft3 + fld f4, 35*8(sp) // Recover ft4 + fld f5, 36*8(sp) // Recover ft5 + fld f6, 37*8(sp) // Recover ft6 + fld f7, 38*8(sp) // Recover ft7 + fld f10,41*8(sp) // Recover fa0 + fld f11,42*8(sp) // Recover fa1 + fld f12,43*8(sp) // Recover fa2 + fld f13,44*8(sp) // Recover fa3 + fld f14,45*8(sp) // Recover fa4 + fld f15,46*8(sp) // Recover fa5 + fld f16,47*8(sp) // Recover fa6 + fld f17,48*8(sp) // Recover fa7 + fld f28,59*8(sp) // Recover ft8 + fld f29,60*8(sp) // Recover ft9 + fld f30,61*8(sp) // Recover ft10 + fld f31,62*8(sp) // Recover ft11 + ld t0, 63*8(sp) // Recover fcsr + csrw fcsr, t0 // Restore fcsr #endif /* Recover the saved context and return to the point of interrupt. */ @@ -279,48 +279,48 @@ _tx_thread_no_preempt_restore: /* Restore registers, Skip global pointer because that does not change */ - ld t0, 30*8(sp) /* Recover mepc */ - csrw mepc, t0 /* Setup mepc */ + ld t0, 30*8(sp) // Recover mepc + csrw mepc, t0 // Setup mepc /* Compose mstatus via read/modify/write to avoid clobbering unrelated bits. */ csrr t1, mstatus - li t2, 0x1888 /* MPP(0x1800) | MPIE(0x80) | MIE(0x08) */ - li t3, 0x1800 /* Set MPP to Machine mode */ - li t4, ~0x1888 /* Clear mask for MPP/MPIE/MIE */ + li t2, 0x1888 // MPP(0x1800) | MPIE(0x80) | MIE(0x08) + li t3, 0x1800 // Set MPP to Machine mode + li t4, ~0x1888 // Clear mask for MPP/MPIE/MIE and t1, t1, t4 or t1, t1, t3 - + #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - li t0, 0x2000 /* Set FS bits for FP state */ + li t0, 0x2000 // Set FS bits for FP state or t1, t1, t0 #endif - csrw mstatus, t1 /* Update mstatus safely */ + csrw mstatus, t1 // Update mstatus safely - ld ra, 28*8(sp) /* Recover return address */ - ld t0, 19*8(sp) /* Recover t0 */ - ld t1, 18*8(sp) /* Recover t1 */ - ld t2, 17*8(sp) /* Recover t2 */ - ld s0, 12*8(sp) /* Recover s0 */ - ld a0, 27*8(sp) /* Recover a0 */ - ld a1, 26*8(sp) /* Recover a1 */ - ld a2, 25*8(sp) /* Recover a2 */ - ld a3, 24*8(sp) /* Recover a3 */ - ld a4, 23*8(sp) /* Recover a4 */ - ld a5, 22*8(sp) /* Recover a5 */ - ld a6, 21*8(sp) /* Recover a6 */ - ld a7, 20*8(sp) /* Recover a7 */ - ld t3, 16*8(sp) /* Recover t3 */ - ld t4, 15*8(sp) /* Recover t4 */ - ld t5, 14*8(sp) /* Recover t5 */ - ld t6, 13*8(sp) /* Recover t6 */ + ld ra, 28*8(sp) // Recover return address + ld t0, 19*8(sp) // Recover t0 + ld t1, 18*8(sp) // Recover t1 + ld t2, 17*8(sp) // Recover t2 + ld s0, 12*8(sp) // Recover s0 + ld a0, 27*8(sp) // Recover a0 + ld a1, 26*8(sp) // Recover a1 + ld a2, 25*8(sp) // Recover a2 + ld a3, 24*8(sp) // Recover a3 + ld a4, 23*8(sp) // Recover a4 + ld a5, 22*8(sp) // Recover a5 + ld a6, 21*8(sp) // Recover a6 + ld a7, 20*8(sp) // Recover a7 + ld t3, 16*8(sp) // Recover t3 + ld t4, 15*8(sp) // Recover t4 + ld t5, 14*8(sp) // Recover t5 + ld t6, 13*8(sp) // Recover t6 #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - addi sp, sp, 65*8 /* Recover stack frame - with floating point enabled */ + addi sp, sp, 65*8 // Recover stack frame - with floating point enabled #else - addi sp, sp, 32*8 /* Recover stack frame - without floating point enabled */ + addi sp, sp, 32*8 // Recover stack frame - without floating point enabled #endif - mret /* Return to point of interrupt */ + mret // Return to point of interrupt /* } else @@ -329,15 +329,15 @@ _tx_thread_preempt_restore: /* Instead of directly activating the thread again, ensure we save the entire stack frame by saving the remaining registers. */ - ld t0, 16(t1) /* Pickup thread's stack pointer */ - ori t3, zero, 1 /* Build interrupt stack type */ - sd t3, 0(t0) /* Store stack type */ + ld t0, 16(t1) // Pickup thread's stack pointer + ori t3, zero, 1 // Build interrupt stack type + sd t3, 0(t0) // Store stack type /* Store floating point preserved registers. */ #ifdef __riscv_float_abi_single - fsw f8, 39*8(t0) /* Store fs0 */ - fsw f9, 40*8(t0) /* Store fs1 */ - fsw f18, 49*8(t0) /* Store fs2 */ + fsw f8, 39*8(t0) // Store fs0 + fsw f9, 40*8(t0) // Store fs1 + fsw f18, 49*8(t0) // Store fs2 fsw f19, 50*8(t0) // Store fs3 fsw f20, 51*8(t0) // Store fs4 fsw f21, 52*8(t0) // Store fs5 diff --git a/ports/risc-v64/gnu/src/tx_thread_context_save.S b/ports/risc-v64/gnu/src/tx_thread_context_save.S index 13281d7f..641c7793 100644 --- a/ports/risc-v64/gnu/src/tx_thread_context_save.S +++ b/ports/risc-v64/gnu/src/tx_thread_context_save.S @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,94 +68,94 @@ _tx_thread_context_save: out and the interrupt stack frame has been allocated and ra has been saved on the stack. */ - sd t0, 19*8(sp) /* First store t0 and t1 */ + sd t0, 19*8(sp) // First store t0 and t1 sd t1, 18*8(sp) - la t0, _tx_thread_system_state /* Pickup address of system state */ - ld t1, 0(t0) /* Pickup system state */ + la t0, _tx_thread_system_state // Pickup address of system state + ld t1, 0(t0) // Pickup system state /* Check for a nested interrupt condition. */ /* if (_tx_thread_system_state++) { */ - beqz t1, _tx_thread_not_nested_save /* If 0, first interrupt condition */ - addi t1, t1, 1 /* Increment the interrupt counter */ - sd t1, 0(t0) /* Store the interrupt counter */ + beqz t1, _tx_thread_not_nested_save // If 0, first interrupt condition + addi t1, t1, 1 // Increment the interrupt counter + sd t1, 0(t0) // Store the interrupt counter /* Nested interrupt condition. Save the rest of the scratch registers on the stack and return to the calling ISR. */ - sd t2, 17*8(sp) /* Store t2 */ - sd s0, 12*8(sp) /* Store s0 */ - sd a0, 27*8(sp) /* Store a0 */ - sd a1, 26*8(sp) /* Store a1 */ - sd a2, 25*8(sp) /* Store a2 */ - sd a3, 24*8(sp) /* Store a3 */ - sd a4, 23*8(sp) /* Store a4 */ - sd a5, 22*8(sp) /* Store a5 */ - sd a6, 21*8(sp) /* Store a6 */ - sd a7, 20*8(sp) /* Store a7 */ - sd t3, 16*8(sp) /* Store t3 */ - sd t4, 15*8(sp) /* Store t4 */ - sd t5, 14*8(sp) /* Store t5 */ - sd t6, 13*8(sp) /* Store t6 */ - csrr t0, mepc /* Load exception program counter */ - sd t0, 30*8(sp) /* Save it on the stack */ + sd t2, 17*8(sp) // Store t2 + sd s0, 12*8(sp) // Store s0 + sd a0, 27*8(sp) // Store a0 + sd a1, 26*8(sp) // Store a1 + sd a2, 25*8(sp) // Store a2 + sd a3, 24*8(sp) // Store a3 + sd a4, 23*8(sp) // Store a4 + sd a5, 22*8(sp) // Store a5 + sd a6, 21*8(sp) // Store a6 + sd a7, 20*8(sp) // Store a7 + sd t3, 16*8(sp) // Store t3 + sd t4, 15*8(sp) // Store t4 + sd t5, 14*8(sp) // Store t5 + sd t6, 13*8(sp) // Store t6 + csrr t0, mepc // Load exception program counter + sd t0, 30*8(sp) // Save it on the stack /* Save floating point scratch registers if floating point is enabled. */ #ifdef __riscv_float_abi_single - fsw f0, 31*8(sp) /* Store ft0 */ - fsw f1, 32*8(sp) /* Store ft1 */ - fsw f2, 33*8(sp) /* Store ft2 */ - fsw f3, 34*8(sp) /* Store ft3 */ - fsw f4, 35*8(sp) /* Store ft4 */ - fsw f5, 36*8(sp) /* Store ft5 */ - fsw f6, 37*8(sp) /* Store ft6 */ - fsw f7, 38*8(sp) /* Store ft7 */ - fsw f10,41*8(sp) /* Store fa0 */ - fsw f11,42*8(sp) /* Store fa1 */ - fsw f12,43*8(sp) /* Store fa2 */ - fsw f13,44*8(sp) /* Store fa3 */ - fsw f14,45*8(sp) /* Store fa4 */ - fsw f15,46*8(sp) /* Store fa5 */ - fsw f16,47*8(sp) /* Store fa6 */ - fsw f17,48*8(sp) /* Store fa7 */ - fsw f28,59*8(sp) /* Store ft8 */ - fsw f29,60*8(sp) /* Store ft9 */ - fsw f30,61*8(sp) /* Store ft10 */ - fsw f31,62*8(sp) /* Store ft11 */ + fsw f0, 31*8(sp) // Store ft0 + fsw f1, 32*8(sp) // Store ft1 + fsw f2, 33*8(sp) // Store ft2 + fsw f3, 34*8(sp) // Store ft3 + fsw f4, 35*8(sp) // Store ft4 + fsw f5, 36*8(sp) // Store ft5 + fsw f6, 37*8(sp) // Store ft6 + fsw f7, 38*8(sp) // Store ft7 + fsw f10,41*8(sp) // Store fa0 + fsw f11,42*8(sp) // Store fa1 + fsw f12,43*8(sp) // Store fa2 + fsw f13,44*8(sp) // Store fa3 + fsw f14,45*8(sp) // Store fa4 + fsw f15,46*8(sp) // Store fa5 + fsw f16,47*8(sp) // Store fa6 + fsw f17,48*8(sp) // Store fa7 + fsw f28,59*8(sp) // Store ft8 + fsw f29,60*8(sp) // Store ft9 + fsw f30,61*8(sp) // Store ft10 + fsw f31,62*8(sp) // Store ft11 csrr t0, fcsr - sd t0, 63*8(sp) /* Store fcsr */ + sd t0, 63*8(sp) // Store fcsr #elif defined(__riscv_float_abi_double) - fsd f0, 31*8(sp) /* Store ft0 */ - fsd f1, 32*8(sp) /* Store ft1 */ - fsd f2, 33*8(sp) /* Store ft2 */ - fsd f3, 34*8(sp) /* Store ft3 */ - fsd f4, 35*8(sp) /* Store ft4 */ - fsd f5, 36*8(sp) /* Store ft5 */ - fsd f6, 37*8(sp) /* Store ft6 */ - fsd f7, 38*8(sp) /* Store ft7 */ - fsd f10,41*8(sp) /* Store fa0 */ - fsd f11,42*8(sp) /* Store fa1 */ - fsd f12,43*8(sp) /* Store fa2 */ - fsd f13,44*8(sp) /* Store fa3 */ - fsd f14,45*8(sp) /* Store fa4 */ - fsd f15,46*8(sp) /* Store fa5 */ - fsd f16,47*8(sp) /* Store fa6 */ - fsd f17,48*8(sp) /* Store fa7 */ - fsd f28,59*8(sp) /* Store ft8 */ - fsd f29,60*8(sp) /* Store ft9 */ - fsd f30,61*8(sp) /* Store ft10 */ - fsd f31,62*8(sp) /* Store ft11 */ + fsd f0, 31*8(sp) // Store ft0 + fsd f1, 32*8(sp) // Store ft1 + fsd f2, 33*8(sp) // Store ft2 + fsd f3, 34*8(sp) // Store ft3 + fsd f4, 35*8(sp) // Store ft4 + fsd f5, 36*8(sp) // Store ft5 + fsd f6, 37*8(sp) // Store ft6 + fsd f7, 38*8(sp) // Store ft7 + fsd f10,41*8(sp) // Store fa0 + fsd f11,42*8(sp) // Store fa1 + fsd f12,43*8(sp) // Store fa2 + fsd f13,44*8(sp) // Store fa3 + fsd f14,45*8(sp) // Store fa4 + fsd f15,46*8(sp) // Store fa5 + fsd f16,47*8(sp) // Store fa6 + fsd f17,48*8(sp) // Store fa7 + fsd f28,59*8(sp) // Store ft8 + fsd f29,60*8(sp) // Store ft9 + fsd f30,61*8(sp) // Store ft10 + fsd f31,62*8(sp) // Store ft11 csrr t0, fcsr - sd t0, 63*8(sp) /* Store fcsr */ + sd t0, 63*8(sp) // Store fcsr #endif #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - call _tx_execution_isr_enter /* Call the ISR execution enter function */ + call _tx_execution_isr_enter // Call the ISR execution enter function #endif - ret /* Return to calling ISR */ + ret // Return to calling ISR _tx_thread_not_nested_save: /* } */ @@ -163,82 +163,82 @@ _tx_thread_not_nested_save: /* Otherwise, not nested, check to see if a thread was running. */ /* else if (_tx_thread_current_ptr) { */ - addi t1, t1, 1 /* Increment the interrupt counter */ - sd t1, 0(t0) /* Store the interrupt counter */ + addi t1, t1, 1 // Increment the interrupt counter + sd t1, 0(t0) // Store the interrupt counter /* Not nested: Find the user thread that was running and load our SP */ - la t0, _tx_thread_current_ptr /* Pickup current thread pointer address */ - ld t0, 0(t0) /* Pickup current thread pointer */ - beqz t0, _tx_thread_idle_system_save /* If NULL, idle system was interrupted */ + la t0, _tx_thread_current_ptr // Pickup current thread pointer address + ld t0, 0(t0) // Pickup current thread pointer + beqz t0, _tx_thread_idle_system_save // If NULL, idle system was interrupted /* Save the standard scratch registers. */ - sd t2, 17*8(sp) /* Store t2 */ - sd s0, 12*8(sp) /* Store s0 */ - sd a0, 27*8(sp) /* Store a0 */ - sd a1, 26*8(sp) /* Store a1 */ - sd a2, 25*8(sp) /* Store a2 */ - sd a3, 24*8(sp) /* Store a3 */ - sd a4, 23*8(sp) /* Store a4 */ - sd a5, 22*8(sp) /* Store a5 */ - sd a6, 21*8(sp) /* Store a6 */ - sd a7, 20*8(sp) /* Store a7 */ - sd t3, 16*8(sp) /* Store t3 */ - sd t4, 15*8(sp) /* Store t4 */ - sd t5, 14*8(sp) /* Store t5 */ - sd t6, 13*8(sp) /* Store t6 */ + sd t2, 17*8(sp) // Store t2 + sd s0, 12*8(sp) // Store s0 + sd a0, 27*8(sp) // Store a0 + sd a1, 26*8(sp) // Store a1 + sd a2, 25*8(sp) // Store a2 + sd a3, 24*8(sp) // Store a3 + sd a4, 23*8(sp) // Store a4 + sd a5, 22*8(sp) // Store a5 + sd a6, 21*8(sp) // Store a6 + sd a7, 20*8(sp) // Store a7 + sd t3, 16*8(sp) // Store t3 + sd t4, 15*8(sp) // Store t4 + sd t5, 14*8(sp) // Store t5 + sd t6, 13*8(sp) // Store t6 - csrr t1, mepc /* Load exception program counter */ - sd t1, 30*8(sp) /* Save it on the stack */ + csrr t1, mepc // Load exception program counter + sd t1, 30*8(sp) // Save it on the stack /* Save floating point scratch registers if floating point is enabled. */ #ifdef __riscv_float_abi_single - fsw f0, 31*8(sp) /* Store ft0 */ - fsw f1, 32*8(sp) /* Store ft1 */ - fsw f2, 33*8(sp) /* Store ft2 */ - fsw f3, 34*8(sp) /* Store ft3 */ - fsw f4, 35*8(sp) /* Store ft4 */ - fsw f5, 36*8(sp) /* Store ft5 */ - fsw f6, 37*8(sp) /* Store ft6 */ - fsw f7, 38*8(sp) /* Store ft7 */ - fsw f10,41*8(sp) /* Store fa0 */ - fsw f11,42*8(sp) /* Store fa1 */ - fsw f12,43*8(sp) /* Store fa2 */ - fsw f13,44*8(sp) /* Store fa3 */ - fsw f14,45*8(sp) /* Store fa4 */ - fsw f15,46*8(sp) /* Store fa5 */ - fsw f16,47*8(sp) /* Store fa6 */ - fsw f17,48*8(sp) /* Store fa7 */ - fsw f28,59*8(sp) /* Store ft8 */ - fsw f29,60*8(sp) /* Store ft9 */ - fsw f30,61*8(sp) /* Store ft10 */ - fsw f31,62*8(sp) /* Store ft11 */ + fsw f0, 31*8(sp) // Store ft0 + fsw f1, 32*8(sp) // Store ft1 + fsw f2, 33*8(sp) // Store ft2 + fsw f3, 34*8(sp) // Store ft3 + fsw f4, 35*8(sp) // Store ft4 + fsw f5, 36*8(sp) // Store ft5 + fsw f6, 37*8(sp) // Store ft6 + fsw f7, 38*8(sp) // Store ft7 + fsw f10,41*8(sp) // Store fa0 + fsw f11,42*8(sp) // Store fa1 + fsw f12,43*8(sp) // Store fa2 + fsw f13,44*8(sp) // Store fa3 + fsw f14,45*8(sp) // Store fa4 + fsw f15,46*8(sp) // Store fa5 + fsw f16,47*8(sp) // Store fa6 + fsw f17,48*8(sp) // Store fa7 + fsw f28,59*8(sp) // Store ft8 + fsw f29,60*8(sp) // Store ft9 + fsw f30,61*8(sp) // Store ft10 + fsw f31,62*8(sp) // Store ft11 csrr t0, fcsr - sd t0, 63*8(sp) /* Store fcsr */ + sd t0, 63*8(sp) // Store fcsr #elif defined(__riscv_float_abi_double) - fsd f0, 31*8(sp) /* Store ft0 */ - fsd f1, 32*8(sp) /* Store ft1 */ - fsd f2, 33*8(sp) /* Store ft2 */ - fsd f3, 34*8(sp) /* Store ft3 */ - fsd f4, 35*8(sp) /* Store ft4 */ - fsd f5, 36*8(sp) /* Store ft5 */ - fsd f6, 37*8(sp) /* Store ft6 */ - fsd f7, 38*8(sp) /* Store ft7 */ - fsd f10,41*8(sp) /* Store fa0 */ - fsd f11,42*8(sp) /* Store fa1 */ - fsd f12,43*8(sp) /* Store fa2 */ - fsd f13,44*8(sp) /* Store fa3 */ - fsd f14,45*8(sp) /* Store fa4 */ - fsd f15,46*8(sp) /* Store fa5 */ - fsd f16,47*8(sp) /* Store fa6 */ - fsd f17,48*8(sp) /* Store fa7 */ - fsd f28,59*8(sp) /* Store ft8 */ - fsd f29,60*8(sp) /* Store ft9 */ - fsd f30,61*8(sp) /* Store ft10 */ - fsd f31,62*8(sp) /* Store ft11 */ + fsd f0, 31*8(sp) // Store ft0 + fsd f1, 32*8(sp) // Store ft1 + fsd f2, 33*8(sp) // Store ft2 + fsd f3, 34*8(sp) // Store ft3 + fsd f4, 35*8(sp) // Store ft4 + fsd f5, 36*8(sp) // Store ft5 + fsd f6, 37*8(sp) // Store ft6 + fsd f7, 38*8(sp) // Store ft7 + fsd f10,41*8(sp) // Store fa0 + fsd f11,42*8(sp) // Store fa1 + fsd f12,43*8(sp) // Store fa2 + fsd f13,44*8(sp) // Store fa3 + fsd f14,45*8(sp) // Store fa4 + fsd f15,46*8(sp) // Store fa5 + fsd f16,47*8(sp) // Store fa6 + fsd f17,48*8(sp) // Store fa7 + fsd f28,59*8(sp) // Store ft8 + fsd f29,60*8(sp) // Store ft9 + fsd f30,61*8(sp) // Store ft10 + fsd f31,62*8(sp) // Store ft11 csrr t0, fcsr - sd t0, 63*8(sp) /* Store fcsr */ + sd t0, 63*8(sp) // Store fcsr #endif /* Save the current stack pointer in the thread's control block. */ @@ -247,18 +247,18 @@ _tx_thread_not_nested_save: /* Switch to the system stack. */ /* sp = _tx_thread_system_stack_ptr; */ - la t1, _tx_thread_current_ptr /* Pickup current thread pointer address */ - ld t1, 0(t1) /* Pickup current thread pointer */ - sd sp, 16(t1) /* Save stack pointer */ + la t1, _tx_thread_current_ptr // Pickup current thread pointer address + ld t1, 0(t1) // Pickup current thread pointer + sd sp, 16(t1) // Save stack pointer #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY /* _tx_execution_isr_enter is called with thread stack pointer */ - call _tx_execution_isr_enter /* Call the ISR execution enter function */ + call _tx_execution_isr_enter // Call the ISR execution enter function #endif - la t0, _tx_thread_system_stack_ptr /* Pickup system stack pointer address */ - ld sp, 0(t0) /* Switch to system stack */ - ret /* Return to calling ISR */ + la t0, _tx_thread_system_stack_ptr // Pickup system stack pointer address + ld sp, 0(t0) // Switch to system stack + ret // Return to calling ISR sd x17, 20*8(sp) // Store a7 sd x28, 16*8(sp) // Store t3 diff --git a/ports/risc-v64/gnu/src/tx_thread_interrupt_control.S b/ports/risc-v64/gnu/src/tx_thread_interrupt_control.S index a540ffdc..f5b538e8 100644 --- a/ports/risc-v64/gnu/src/tx_thread_interrupt_control.S +++ b/ports/risc-v64/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,17 +67,17 @@ _tx_thread_interrupt_control: /* old_mstatus = mstatus; */ csrr t0, mstatus - mv t1, t0 /* Save original mstatus for return */ + mv t1, t0 // Save original mstatus for return /* Apply the new interrupt posture while preserving unrelated mstatus bits. */ /* Only modify the MIE bit (bit 3) */ /* mstatus = (mstatus & ~MIE) | (new_posture & MIE); */ - - li t2, ~0x08 /* Build mask to clear MIE */ - and t0, t0, t2 /* Clear MIE bit */ - and a0, a0, 0x08 /* Mask incoming to only MIE bit */ - or t0, t0, a0 /* Set requested MIE state */ + + li t2, ~0x08 // Build mask to clear MIE + and t0, t0, t2 // Clear MIE bit + and a0, a0, 0x08 // Mask incoming to only MIE bit + or t0, t0, a0 // Set requested MIE state csrw mstatus, t0 - andi a0, t1, 0x08 /* Return original MIE bit */ + andi a0, t1, 0x08 // Return original MIE bit ret /* } */ diff --git a/ports/risc-v64/gnu/src/tx_thread_schedule.S b/ports/risc-v64/gnu/src/tx_thread_schedule.S index 52f865c2..2618e98b 100644 --- a/ports/risc-v64/gnu/src/tx_thread_schedule.S +++ b/ports/risc-v64/gnu/src/tx_thread_schedule.S @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,16 +67,16 @@ _tx_thread_schedule: /* Enable interrupts. */ - csrsi mstatus, 0x08 /* Enable interrupts (MIE bit 3) */ + csrsi mstatus, 0x08 // Enable interrupts (MIE bit 3) /* Wait for a thread to execute. */ /* do { */ - la t0, _tx_thread_execute_ptr /* Pickup address of execute ptr */ + la t0, _tx_thread_execute_ptr // Pickup address of execute ptr _tx_thread_schedule_loop: - ld t1, 0(t0) /* Pickup next thread to execute */ - + ld t1, 0(t0) // Pickup next thread to execute + /* TX_USE_WFI_IDLE Configuration: When defined, the scheduler enters WFI (Wait-For-Interrupt) mode when no threads are ready, reducing power consumption. The core will wake @@ -89,9 +89,9 @@ _tx_thread_schedule_loop: 1: wfi j _tx_thread_schedule_loop 2: - beqz t1, _tx_thread_schedule_loop /* Fallback: If still NULL, loop */ + beqz t1, _tx_thread_schedule_loop // Fallback: If still NULL, loop #else - beqz t1, _tx_thread_schedule_loop /* If NULL, wait for thread to execute */ + beqz t1, _tx_thread_schedule_loop // If NULL, wait for thread to execute #endif /* } @@ -99,81 +99,81 @@ _tx_thread_schedule_loop: /* Yes! We have a thread to execute. Lockout interrupts and transfer control to it. */ - csrci mstatus, 0x08 /* Lockout interrupts */ + csrci mstatus, 0x08 // Lockout interrupts /* Setup the current thread pointer. */ /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ - la t0, _tx_thread_current_ptr /* Pickup current thread pointer address */ - sd t1, 0(t0) /* Set current thread pointer */ + la t0, _tx_thread_current_ptr // Pickup current thread pointer address + sd t1, 0(t0) // Set current thread pointer /* Increment the run count for this thread. */ /* _tx_thread_current_ptr -> tx_thread_run_count++; */ - ld t2, 8(t1) /* Pickup run count */ - ld t3, 48(t1) /* Pickup time slice value */ - addi t2, t2, 1 /* Increment run count */ - sd t2, 8(t1) /* Store new run count */ + ld t2, 8(t1) // Pickup run count + ld t3, 48(t1) // Pickup time slice value + addi t2, t2, 1 // Increment run count + sd t2, 8(t1) // Store new run count /* Setup time-slice, if present. */ /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ - la t2, _tx_timer_time_slice /* Pickup time-slice variable address */ + la t2, _tx_timer_time_slice // Pickup time-slice variable address /* Switch to the thread's stack. */ /* SP = _tx_thread_execute_ptr -> tx_thread_stack_ptr; */ - ld sp, 16(t1) /* Switch to thread's stack */ - sd t3, 0(t2) /* Store new time-slice*/ + ld sp, 16(t1) // Switch to thread's stack + sd t3, 0(t2) // Store new time-slice #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - call _tx_execution_thread_enter /* Call the thread execution enter function */ + call _tx_execution_thread_enter // Call the thread execution enter function #endif /* Determine if an interrupt frame or a synchronous task suspension frame is present. */ - ld t2, 0(sp) /* Pickup stack type */ - beqz t2, _tx_thread_synch_return /* If 0, solicited thread return */ + ld t2, 0(sp) // Pickup stack type + beqz t2, _tx_thread_synch_return // If 0, solicited thread return /* Determine if floating point registers need to be recovered. */ #if defined(__riscv_float_abi_single) - flw f0, 31*8(sp) /* Recover ft0 */ - flw f1, 32*8(sp) /* Recover ft1 */ - flw f2, 33*8(sp) /* Recover ft2 */ - flw f3, 34*8(sp) /* Recover ft3 */ - flw f4, 35*8(sp) /* Recover ft4 */ - flw f5, 36*8(sp) /* Recover ft5 */ - flw f6, 37*8(sp) /* Recover ft6 */ - flw f7, 38*8(sp) /* Recover ft7 */ - flw f8, 39*8(sp) /* Recover fs0 */ - flw f9, 40*8(sp) /* Recover fs1 */ - flw f10,41*8(sp) /* Recover fa0 */ - flw f11,42*8(sp) /* Recover fa1 */ - flw f12,43*8(sp) /* Recover fa2 */ - flw f13,44*8(sp) /* Recover fa3 */ - flw f14,45*8(sp) /* Recover fa4 */ - flw f15,46*8(sp) /* Recover fa5 */ - flw f16,47*8(sp) /* Recover fa6 */ - flw f17,48*8(sp) /* Recover fa7 */ - flw f18,49*8(sp) /* Recover fs2 */ - flw f19,50*8(sp) /* Recover fs3 */ - flw f20,51*8(sp) /* Recover fs4 */ - flw f21,52*8(sp) /* Recover fs5 */ - flw f22,53*8(sp) /* Recover fs6 */ - flw f23,54*8(sp) /* Recover fs7 */ - flw f24,55*8(sp) /* Recover fs8 */ - flw f25,56*8(sp) /* Recover fs9 */ - flw f26,57*8(sp) /* Recover fs10 */ - flw f27,58*8(sp) /* Recover fs11 */ - flw f28,59*8(sp) /* Recover ft8 */ - flw f29,60*8(sp) /* Recover ft9 */ - flw f30,61*8(sp) /* Recover ft10 */ - flw f31,62*8(sp) /* Recover ft11 */ - ld t0, 63*8(sp) /* Recover fcsr */ - csrw fcsr, t0 /* Restore fcsr */ + flw f0, 31*8(sp) // Recover ft0 + flw f1, 32*8(sp) // Recover ft1 + flw f2, 33*8(sp) // Recover ft2 + flw f3, 34*8(sp) // Recover ft3 + flw f4, 35*8(sp) // Recover ft4 + flw f5, 36*8(sp) // Recover ft5 + flw f6, 37*8(sp) // Recover ft6 + flw f7, 38*8(sp) // Recover ft7 + flw f8, 39*8(sp) // Recover fs0 + flw f9, 40*8(sp) // Recover fs1 + flw f10,41*8(sp) // Recover fa0 + flw f11,42*8(sp) // Recover fa1 + flw f12,43*8(sp) // Recover fa2 + flw f13,44*8(sp) // Recover fa3 + flw f14,45*8(sp) // Recover fa4 + flw f15,46*8(sp) // Recover fa5 + flw f16,47*8(sp) // Recover fa6 + flw f17,48*8(sp) // Recover fa7 + flw f18,49*8(sp) // Recover fs2 + flw f19,50*8(sp) // Recover fs3 + flw f20,51*8(sp) // Recover fs4 + flw f21,52*8(sp) // Recover fs5 + flw f22,53*8(sp) // Recover fs6 + flw f23,54*8(sp) // Recover fs7 + flw f24,55*8(sp) // Recover fs8 + flw f25,56*8(sp) // Recover fs9 + flw f26,57*8(sp) // Recover fs10 + flw f27,58*8(sp) // Recover fs11 + flw f28,59*8(sp) // Recover ft8 + flw f29,60*8(sp) // Recover ft9 + flw f30,61*8(sp) // Recover ft10 + flw f31,62*8(sp) // Recover ft11 + ld t0, 63*8(sp) // Recover fcsr + csrw fcsr, t0 // Restore fcsr #elif defined(__riscv_float_abi_double) fld f0, 31*8(sp) // Recover ft0 fld f1, 32*8(sp) // Recover ft1 @@ -208,48 +208,48 @@ _tx_thread_schedule_loop: fld f30,61*8(sp) // Recover ft10 fld f31,62*8(sp) // Recover ft11 ld t0, 63*8(sp) // Recover fcsr - csrw fcsr, t0 // + csrw fcsr, t0 // Restore fcsr #endif /* Recover standard registers. */ - ld t0, 30*8(sp) /* Recover mepc */ - csrw mepc, t0 /* Store mepc */ - li t0, 0x1880 /* Prepare mstatus: MPP=Machine(0x1800) | MPIE(0x80) */ + ld t0, 30*8(sp) // Recover mepc + csrw mepc, t0 // Store mepc + li t0, 0x1880 // Prepare mstatus: MPP=Machine(0x1800) | MPIE(0x80) #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - li t1, 0x2000 /* Set FS bits for FP state */ + li t1, 0x2000 // Set FS bits for FP state or t0, t0, t1 #endif - csrw mstatus, t0 /* Set mstatus */ + csrw mstatus, t0 // Set mstatus - ld ra, 28*8(sp) /* Recover return address */ - ld t0, 19*8(sp) /* Recover t0 */ - ld t1, 18*8(sp) /* Recover t1 */ - ld t2, 17*8(sp) /* Recover t2 */ - ld s0, 12*8(sp) /* Recover s0 */ - ld s1, 11*8(sp) /* Recover s1 */ - ld a0, 27*8(sp) /* Recover a0 */ - ld a1, 26*8(sp) /* Recover a1 */ - ld a2, 25*8(sp) /* Recover a2 */ - ld a3, 24*8(sp) /* Recover a3 */ - ld a4, 23*8(sp) /* Recover a4 */ - ld a5, 22*8(sp) /* Recover a5 */ - ld a6, 21*8(sp) /* Recover a6 */ - ld a7, 20*8(sp) /* Recover a7 */ - ld s2, 10*8(sp) /* Recover s2 */ - ld s3, 9*8(sp) /* Recover s3 */ - ld s4, 8*8(sp) /* Recover s4 */ - ld s5, 7*8(sp) /* Recover s5 */ - ld s6, 6*8(sp) /* Recover s6 */ - ld s7, 5*8(sp) /* Recover s7 */ - ld s8, 4*8(sp) /* Recover s8 */ - ld s9, 3*8(sp) /* Recover s9 */ - ld s10, 2*8(sp) /* Recover s10 */ - ld s11, 1*8(sp) /* Recover s11 */ - ld t3, 16*8(sp) /* Recover t3 */ - ld t4, 15*8(sp) /* Recover t4 */ - ld t5, 14*8(sp) /* Recover t5 */ - ld t6, 13*8(sp) /* Recover t6 */ + ld ra, 28*8(sp) // Recover return address + ld t0, 19*8(sp) // Recover t0 + ld t1, 18*8(sp) // Recover t1 + ld t2, 17*8(sp) // Recover t2 + ld s0, 12*8(sp) // Recover s0 + ld s1, 11*8(sp) // Recover s1 + ld a0, 27*8(sp) // Recover a0 + ld a1, 26*8(sp) // Recover a1 + ld a2, 25*8(sp) // Recover a2 + ld a3, 24*8(sp) // Recover a3 + ld a4, 23*8(sp) // Recover a4 + ld a5, 22*8(sp) // Recover a5 + ld a6, 21*8(sp) // Recover a6 + ld a7, 20*8(sp) // Recover a7 + ld s2, 10*8(sp) // Recover s2 + ld s3, 9*8(sp) // Recover s3 + ld s4, 8*8(sp) // Recover s4 + ld s5, 7*8(sp) // Recover s5 + ld s6, 6*8(sp) // Recover s6 + ld s7, 5*8(sp) // Recover s7 + ld s8, 4*8(sp) // Recover s8 + ld s9, 3*8(sp) // Recover s9 + ld s10, 2*8(sp) // Recover s10 + ld s11, 1*8(sp) // Recover s11 + ld t3, 16*8(sp) // Recover t3 + ld t4, 15*8(sp) // Recover t4 + ld t5, 14*8(sp) // Recover t5 + ld t6, 13*8(sp) // Recover t6 #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) addi sp, sp, 65*8 // Recover stack frame - with floating point registers @@ -295,21 +295,21 @@ _tx_thread_synch_return: /* Recover standard preserved registers. */ /* Recover standard registers. */ - ld ra, 13*8(sp) /* Recover RA */ - ld s0, 12*8(sp) /* Recover s0 */ - ld s1, 11*8(sp) /* Recover s1 */ - ld s2, 10*8(sp) /* Recover s2 */ - ld s3, 9*8(sp) /* Recover s3 */ - ld s4, 8*8(sp) /* Recover s4 */ - ld s5, 7*8(sp) /* Recover s5 */ - ld s6, 6*8(sp) /* Recover s6 */ - ld s7, 5*8(sp) /* Recover s7 */ - ld s8, 4*8(sp) /* Recover s8 */ - ld s9, 3*8(sp) /* Recover s9 */ - ld s10, 2*8(sp) /* Recover s10 */ - ld s11, 1*8(sp) /* Recover s11 */ - ld t0, 14*8(sp) /* Recover mstatus */ - csrw mstatus, t0 /* Store mstatus, enables interrupt */ + ld ra, 13*8(sp) // Recover RA + ld s0, 12*8(sp) // Recover s0 + ld s1, 11*8(sp) // Recover s1 + ld s2, 10*8(sp) // Recover s2 + ld s3, 9*8(sp) // Recover s3 + ld s4, 8*8(sp) // Recover s4 + ld s5, 7*8(sp) // Recover s5 + ld s6, 6*8(sp) // Recover s6 + ld s7, 5*8(sp) // Recover s7 + ld s8, 4*8(sp) // Recover s8 + ld s9, 3*8(sp) // Recover s9 + ld s10, 2*8(sp) // Recover s10 + ld s11, 1*8(sp) // Recover s11 + ld t0, 14*8(sp) // Recover mstatus + csrw mstatus, t0 // Store mstatus, enables interrupt #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) addi sp, sp, 29*8 // Recover stack frame #else diff --git a/ports/risc-v64/gnu/src/tx_thread_stack_build.S b/ports/risc-v64/gnu/src/tx_thread_stack_build.S index a8b32a91..eecfbfec 100644 --- a/ports/risc-v64/gnu/src/tx_thread_stack_build.S +++ b/ports/risc-v64/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -136,91 +136,91 @@ If floating point support: Stack Bottom: (higher memory address) */ - ld t0, 32(a0) /* Pickup end of stack area */ - li t1, ~15 /* Build 16-byte alignment mask */ - and t0, t0, t1 /* Make sure 16-byte alignment */ + ld t0, 32(a0) // Pickup end of stack area + li t1, ~15 // Build 16-byte alignment mask + and t0, t0, t1 // Make sure 16-byte alignment /* Actually build the stack frame. */ #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) addi t0, t0, -65*8 #else - addi t0, t0, -32*8 /* Allocate space for the stack frame */ + addi t0, t0, -32*8 // Allocate space for the stack frame #endif - li t1, 1 /* Build stack type */ - sd t1, 0*8(t0) /* Place stack type on the top */ - sd zero, 1*8(t0) /* Initial s11 */ - sd zero, 2*8(t0) /* Initial s10 */ - sd zero, 3*8(t0) /* Initial s9 */ - sd zero, 4*8(t0) /* Initial s8 */ - sd zero, 5*8(t0) /* Initial s7 */ - sd zero, 6*8(t0) /* Initial s6 */ - sd zero, 7*8(t0) /* Initial s5 */ - sd zero, 8*8(t0) /* Initial s4 */ - sd zero, 9*8(t0) /* Initial s3 */ - sd zero, 10*8(t0) /* Initial s2 */ - sd zero, 11*8(t0) /* Initial s1 */ - sd zero, 12*8(t0) /* Initial s0 */ - sd zero, 13*8(t0) /* Initial t6 */ - sd zero, 14*8(t0) /* Initial t5 */ - sd zero, 15*8(t0) /* Initial t4 */ - sd zero, 16*8(t0) /* Initial t3 */ - sd zero, 17*8(t0) /* Initial t2 */ - sd zero, 18*8(t0) /* Initial t1 */ - sd zero, 19*8(t0) /* Initial t0 */ - sd zero, 20*8(t0) /* Initial a7 */ - sd zero, 21*8(t0) /* Initial a6 */ - sd zero, 22*8(t0) /* Initial a5 */ - sd zero, 23*8(t0) /* Initial a4 */ - sd zero, 24*8(t0) /* Initial a3 */ - sd zero, 25*8(t0) /* Initial a2 */ - sd zero, 26*8(t0) /* Initial a1 */ - sd zero, 27*8(t0) /* Initial a0 */ - sd zero, 28*8(t0) /* Initial ra */ - sd a1, 30*8(t0) /* Initial mepc (thread entry point) */ + li t1, 1 // Build stack type + sd t1, 0*8(t0) // Place stack type on the top + sd zero, 1*8(t0) // Initial s11 + sd zero, 2*8(t0) // Initial s10 + sd zero, 3*8(t0) // Initial s9 + sd zero, 4*8(t0) // Initial s8 + sd zero, 5*8(t0) // Initial s7 + sd zero, 6*8(t0) // Initial s6 + sd zero, 7*8(t0) // Initial s5 + sd zero, 8*8(t0) // Initial s4 + sd zero, 9*8(t0) // Initial s3 + sd zero, 10*8(t0) // Initial s2 + sd zero, 11*8(t0) // Initial s1 + sd zero, 12*8(t0) // Initial s0 + sd zero, 13*8(t0) // Initial t6 + sd zero, 14*8(t0) // Initial t5 + sd zero, 15*8(t0) // Initial t4 + sd zero, 16*8(t0) // Initial t3 + sd zero, 17*8(t0) // Initial t2 + sd zero, 18*8(t0) // Initial t1 + sd zero, 19*8(t0) // Initial t0 + sd zero, 20*8(t0) // Initial a7 + sd zero, 21*8(t0) // Initial a6 + sd zero, 22*8(t0) // Initial a5 + sd zero, 23*8(t0) // Initial a4 + sd zero, 24*8(t0) // Initial a3 + sd zero, 25*8(t0) // Initial a2 + sd zero, 26*8(t0) // Initial a1 + sd zero, 27*8(t0) // Initial a0 + sd zero, 28*8(t0) // Initial ra + sd a1, 30*8(t0) // Initial mepc (thread entry point) #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - sd zero, 31*8(t0) /* Initial ft0 */ - sd zero, 32*8(t0) /* Initial ft1 */ - sd zero, 33*8(t0) /* Initial ft2 */ - sd zero, 34*8(t0) /* Initial ft3 */ - sd zero, 35*8(t0) /* Initial ft4 */ - sd zero, 36*8(t0) /* Initial ft5 */ - sd zero, 37*8(t0) /* Initial ft6 */ - sd zero, 38*8(t0) /* Initial ft7 */ - sd zero, 39*8(t0) /* Initial fs0 */ - sd zero, 40*8(t0) /* Initial fs1 */ - sd zero, 41*8(t0) /* Initial fa0 */ - sd zero, 42*8(t0) /* Initial fa1 */ - sd zero, 43*8(t0) /* Initial fa2 */ - sd zero, 44*8(t0) /* Initial fa3 */ - sd zero, 45*8(t0) /* Initial fa4 */ - sd zero, 46*8(t0) /* Initial fa5 */ - sd zero, 47*8(t0) /* Initial fa6 */ - sd zero, 48*8(t0) /* Initial fa7 */ - sd zero, 49*8(t0) /* Initial fs2 */ - sd zero, 50*8(t0) /* Initial fs3 */ - sd zero, 51*8(t0) /* Initial fs4 */ - sd zero, 52*8(t0) /* Initial fs5 */ - sd zero, 53*8(t0) /* Initial fs6 */ - sd zero, 54*8(t0) /* Initial fs7 */ - sd zero, 55*8(t0) /* Initial fs8 */ - sd zero, 56*8(t0) /* Initial fs9 */ - sd zero, 57*8(t0) /* Initial fs10 */ - sd zero, 58*8(t0) /* Initial fs11 */ - sd zero, 59*8(t0) /* Initial ft8 */ - sd zero, 60*8(t0) /* Initial ft9 */ - sd zero, 61*8(t0) /* Initial ft10 */ - sd zero, 62*8(t0) /* Initial ft11 */ - csrr a1, fcsr /* Read fcsr for initial value */ - sd a1, 63*8(t0) /* Initial fcsr */ - sd zero, 64*8(t0) /* Reserved word (0) */ + sd zero, 31*8(t0) // Initial ft0 + sd zero, 32*8(t0) // Initial ft1 + sd zero, 33*8(t0) // Initial ft2 + sd zero, 34*8(t0) // Initial ft3 + sd zero, 35*8(t0) // Initial ft4 + sd zero, 36*8(t0) // Initial ft5 + sd zero, 37*8(t0) // Initial ft6 + sd zero, 38*8(t0) // Initial ft7 + sd zero, 39*8(t0) // Initial fs0 + sd zero, 40*8(t0) // Initial fs1 + sd zero, 41*8(t0) // Initial fa0 + sd zero, 42*8(t0) // Initial fa1 + sd zero, 43*8(t0) // Initial fa2 + sd zero, 44*8(t0) // Initial fa3 + sd zero, 45*8(t0) // Initial fa4 + sd zero, 46*8(t0) // Initial fa5 + sd zero, 47*8(t0) // Initial fa6 + sd zero, 48*8(t0) // Initial fa7 + sd zero, 49*8(t0) // Initial fs2 + sd zero, 50*8(t0) // Initial fs3 + sd zero, 51*8(t0) // Initial fs4 + sd zero, 52*8(t0) // Initial fs5 + sd zero, 53*8(t0) // Initial fs6 + sd zero, 54*8(t0) // Initial fs7 + sd zero, 55*8(t0) // Initial fs8 + sd zero, 56*8(t0) // Initial fs9 + sd zero, 57*8(t0) // Initial fs10 + sd zero, 58*8(t0) // Initial fs11 + sd zero, 59*8(t0) // Initial ft8 + sd zero, 60*8(t0) // Initial ft9 + sd zero, 61*8(t0) // Initial ft10 + sd zero, 62*8(t0) // Initial ft11 + csrr a1, fcsr // Read fcsr for initial value + sd a1, 63*8(t0) // Initial fcsr + sd zero, 64*8(t0) // Reserved word (0) #else - sd zero, 31*8(t0) /* Reserved word (0) */ + sd zero, 31*8(t0) // Reserved word (0) #endif /* Setup stack pointer. */ /* thread_ptr -> tx_thread_stack_ptr = t0; */ - sd t0, 16(a0) /* Save stack pointer in thread's */ - ret /* control block and return */ + sd t0, 16(a0) // Save stack pointer in thread's + ret // control block and return /* } */ diff --git a/ports/risc-v64/gnu/src/tx_thread_system_return.S b/ports/risc-v64/gnu/src/tx_thread_system_return.S index 2e698a62..b7dc9f3a 100644 --- a/ports/risc-v64/gnu/src/tx_thread_system_return.S +++ b/ports/risc-v64/gnu/src/tx_thread_system_return.S @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -69,97 +69,97 @@ _tx_thread_system_return: /* sp -= sizeof(stack_frame); */ #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - addi sp, sp, -29*8 /* Allocate space on the stack - with floating point enabled */ + addi sp, sp, -29*8 // Allocate space on the stack - with floating point enabled #else - addi sp, sp, -16*8 /* Allocate space on the stack - without floating point enabled */ + addi sp, sp, -16*8 // Allocate space on the stack - without floating point enabled #endif /* Store floating point preserved registers. */ #if defined(__riscv_float_abi_single) - fsw f8, 15*8(sp) /* Store fs0 */ - fsw f9, 16*8(sp) /* Store fs1 */ - fsw f18, 17*8(sp) /* Store fs2 */ - fsw f19, 18*8(sp) /* Store fs3 */ - fsw f20, 19*8(sp) /* Store fs4 */ - fsw f21, 20*8(sp) /* Store fs5 */ - fsw f22, 21*8(sp) /* Store fs6 */ - fsw f23, 22*8(sp) /* Store fs7 */ - fsw f24, 23*8(sp) /* Store fs8 */ - fsw f25, 24*8(sp) /* Store fs9 */ - fsw f26, 25*8(sp) /* Store fs10 */ - fsw f27, 26*8(sp) /* Store fs11 */ + fsw f8, 15*8(sp) // Store fs0 + fsw f9, 16*8(sp) // Store fs1 + fsw f18, 17*8(sp) // Store fs2 + fsw f19, 18*8(sp) // Store fs3 + fsw f20, 19*8(sp) // Store fs4 + fsw f21, 20*8(sp) // Store fs5 + fsw f22, 21*8(sp) // Store fs6 + fsw f23, 22*8(sp) // Store fs7 + fsw f24, 23*8(sp) // Store fs8 + fsw f25, 24*8(sp) // Store fs9 + fsw f26, 25*8(sp) // Store fs10 + fsw f27, 26*8(sp) // Store fs11 csrr t0, fcsr - sd t0, 27*8(sp) /* Store fcsr */ + sd t0, 27*8(sp) // Store fcsr #elif defined(__riscv_float_abi_double) - fsd f8, 15*8(sp) /* Store fs0 */ - fsd f9, 16*8(sp) /* Store fs1 */ - fsd f18, 17*8(sp) /* Store fs2 */ - fsd f19, 18*8(sp) /* Store fs3 */ - fsd f20, 19*8(sp) /* Store fs4 */ - fsd f21, 20*8(sp) /* Store fs5 */ - fsd f22, 21*8(sp) /* Store fs6 */ - fsd f23, 22*8(sp) /* Store fs7 */ - fsd f24, 23*8(sp) /* Store fs8 */ - fsd f25, 24*8(sp) /* Store fs9 */ - fsd f26, 25*8(sp) /* Store fs10 */ - fsd f27, 26*8(sp) /* Store fs11 */ + fsd f8, 15*8(sp) // Store fs0 + fsd f9, 16*8(sp) // Store fs1 + fsd f18, 17*8(sp) // Store fs2 + fsd f19, 18*8(sp) // Store fs3 + fsd f20, 19*8(sp) // Store fs4 + fsd f21, 20*8(sp) // Store fs5 + fsd f22, 21*8(sp) // Store fs6 + fsd f23, 22*8(sp) // Store fs7 + fsd f24, 23*8(sp) // Store fs8 + fsd f25, 24*8(sp) // Store fs9 + fsd f26, 25*8(sp) // Store fs10 + fsd f27, 26*8(sp) // Store fs11 csrr t0, fcsr - sd t0, 27*8(sp) /* Store fcsr */ + sd t0, 27*8(sp) // Store fcsr #endif - sd zero, 0(sp) /* Solicited stack type */ - sd ra, 13*8(sp) /* Save return address */ - sd s0, 12*8(sp) /* Save s0 */ - sd s1, 11*8(sp) /* Save s1 */ - sd s2, 10*8(sp) /* Save s2 */ - sd s3, 9*8(sp) /* Save s3 */ - sd s4, 8*8(sp) /* Save s4 */ - sd s5, 7*8(sp) /* Save s5 */ - sd s6, 6*8(sp) /* Save s6 */ - sd s7, 5*8(sp) /* Save s7 */ - sd s8, 4*8(sp) /* Save s8 */ - sd s9, 3*8(sp) /* Save s9 */ - sd s10, 2*8(sp) /* Save s10 */ - sd s11, 1*8(sp) /* Save s11 */ - csrr t0, mstatus /* Pickup mstatus */ - sd t0, 14*8(sp) /* Save mstatus */ + sd zero, 0(sp) // Solicited stack type + sd ra, 13*8(sp) // Save return address + sd s0, 12*8(sp) // Save s0 + sd s1, 11*8(sp) // Save s1 + sd s2, 10*8(sp) // Save s2 + sd s3, 9*8(sp) // Save s3 + sd s4, 8*8(sp) // Save s4 + sd s5, 7*8(sp) // Save s5 + sd s6, 6*8(sp) // Save s6 + sd s7, 5*8(sp) // Save s7 + sd s8, 4*8(sp) // Save s8 + sd s9, 3*8(sp) // Save s9 + sd s10, 2*8(sp) // Save s10 + sd s11, 1*8(sp) // Save s11 + csrr t0, mstatus // Pickup mstatus + sd t0, 14*8(sp) // Save mstatus /* Lockout interrupts. will be enabled in _tx_thread_schedule */ - csrci mstatus, 0x08 /* Disable interrupts (MIE bit 3) */ + csrci mstatus, 0x08 // Disable interrupts (MIE bit 3) #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - call _tx_execution_thread_exit /* Call the thread execution exit function */ + call _tx_execution_thread_exit // Call the thread execution exit function #endif - la t0, _tx_thread_current_ptr /* Pickup address of pointer */ - ld t1, 0(t0) /* Pickup current thread pointer */ - la t2, _tx_thread_system_stack_ptr /* Pickup stack pointer address */ + la t0, _tx_thread_current_ptr // Pickup address of pointer + ld t1, 0(t0) // Pickup current thread pointer + la t2, _tx_thread_system_stack_ptr // Pickup stack pointer address /* Save current stack and switch to system stack. */ /* _tx_thread_current_ptr -> tx_thread_stack_ptr = SP; SP = _tx_thread_system_stack_ptr; */ - sd sp, 16(t1) /* Save stack pointer */ - ld sp, 0(t2) /* Switch to system stack */ + sd sp, 16(t1) // Save stack pointer + ld sp, 0(t2) // Switch to system stack /* Determine if the time-slice is active. */ /* if (_tx_timer_time_slice) { */ - la t4, _tx_timer_time_slice /* Pickup time slice variable addr */ - ld t3, 0(t4) /* Pickup time slice value */ - la t2, _tx_thread_schedule /* Pickup address of scheduling loop */ - beqz t3, _tx_thread_dont_save_ts /* If no time-slice, don't save it */ + la t4, _tx_timer_time_slice // Pickup time slice variable addr + ld t3, 0(t4) // Pickup time slice value + la t2, _tx_thread_schedule // Pickup address of scheduling loop + beqz t3, _tx_thread_dont_save_ts // If no time-slice, don't save it /* Save time-slice for the thread and clear the current time-slice. */ /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; _tx_timer_time_slice = 0; */ - sd t3, 48(t1) /* Save current time-slice for thread */ - sd zero, 0(t4) /* Clear time-slice variable */ + sd t3, 48(t1) // Save current time-slice for thread + sd zero, 0(t4) // Clear time-slice variable /* } */ _tx_thread_dont_save_ts: diff --git a/ports/risc-v64/gnu/src/tx_timer_interrupt.S b/ports/risc-v64/gnu/src/tx_timer_interrupt.S index 146b08f0..1f08c878 100644 --- a/ports/risc-v64/gnu/src/tx_timer_interrupt.S +++ b/ports/risc-v64/gnu/src/tx_timer_interrupt.S @@ -1,18 +1,18 @@ /*************************************************************************** * Copyright (c) 2026 10xEngineers - * + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Timer */ /** */ @@ -21,48 +21,48 @@ .section .text .align 4 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ /* _tx_timer_interrupt RISC-V64/GNU */ /* 6.2.1 */ -/* AUTHOR */ -/* */ -/* Akif Ejaz, 10xEngineers */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function processes the hardware timer interrupt. This */ -/* processing includes incrementing the system clock and checking for */ -/* time slice and/or timer expiration. If either is found, the */ -/* interrupt context save/restore functions are called along with the */ -/* expiration functions. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_timer_expiration_process Timer expiration processing */ -/* _tx_thread_time_slice Time slice interrupted thread */ -/* */ -/* CALLED BY */ -/* */ -/* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-20-2023 Akif Ejaz Initial Version 6.2.1 */ -/* */ -/**************************************************************************/ +/* AUTHOR */ +/* */ +/* Akif Ejaz, 10xEngineers */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 01-20-2023 Akif Ejaz Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ /* VOID _tx_timer_interrupt(VOID) { */ .global _tx_timer_interrupt @@ -71,38 +71,38 @@ _tx_timer_interrupt: /* Increment the system clock. */ /* _tx_timer_system_clock++; */ - la t0, _tx_timer_system_clock /* Pickup address of system clock */ - ld t1, 0(t0) /* Pickup system clock */ - la t2, _tx_timer_time_slice /* Pickup address of time slice */ - ld t3, 0(t2) /* Pickup time slice */ - addi t1, t1, 1 /* Increment system clock */ - sd t1, 0(t0) /* Store new system clock */ - li t6, 0 /* Clear local expired flag */ + la t0, _tx_timer_system_clock // Pickup address of system clock + ld t1, 0(t0) // Pickup system clock + la t2, _tx_timer_time_slice // Pickup address of time slice + ld t3, 0(t2) // Pickup time slice + addi t1, t1, 1 // Increment system clock + sd t1, 0(t0) // Store new system clock + li t6, 0 // Clear local expired flag /* Test for time-slice expiration. */ /* if (_tx_timer_time_slice) { */ - beqz t3, _tx_timer_no_time_slice /* If 0, skip time slice processing */ - addi t3, t3, -1 /* Decrement the time slice */ + beqz t3, _tx_timer_no_time_slice // If 0, skip time slice processing + addi t3, t3, -1 // Decrement the time slice /* Decrement the time_slice. */ /* _tx_timer_time_slice--; */ - sd t3, 0(t2) /* Store new time slice */ + sd t3, 0(t2) // Store new time slice /* Check for expiration. */ /* if (_tx_timer_time_slice == 0) */ - bgtz t3, _tx_timer_no_time_slice /* If not 0, has not expired yet */ - li t1, 1 /* Build expired flag */ + bgtz t3, _tx_timer_no_time_slice // If not 0, has not expired yet + li t1, 1 // Build expired flag /* Set the time-slice expired flag. */ /* _tx_timer_expired_time_slice = TX_TRUE; */ - la t4, _tx_timer_expired_time_slice /* Get address of expired flag */ - sw t1, 0(t4) /* Set expired flag (UINT) */ - ori t6, t6, 1 /* Set local expired flag */ + la t4, _tx_timer_expired_time_slice // Get address of expired flag + sw t1, 0(t4) // Set expired flag (UINT) + ori t6, t6, 1 // Set local expired flag /* } */ @@ -112,19 +112,19 @@ _tx_timer_no_time_slice: /* if (*_tx_timer_current_ptr) { */ - la t0, _tx_timer_current_ptr /* Pickup address of current ptr */ - ld t1, 0(t0) /* Pickup current pointer (double word) */ - ld t3, 0(t1) /* Pickup the current timer entry (double word) */ - la t2, _tx_timer_expired /* Pickup address of timer expired flag */ - li t4, 1 /* Build TX_TRUE flag */ - beqz t3, _tx_timer_no_timer /* If NULL, no timer has expired */ + la t0, _tx_timer_current_ptr // Pickup address of current ptr + ld t1, 0(t0) // Pickup current pointer (double word) + ld t3, 0(t1) // Pickup the current timer entry (double word) + la t2, _tx_timer_expired // Pickup address of timer expired flag + li t4, 1 // Build TX_TRUE flag + beqz t3, _tx_timer_no_timer // If NULL, no timer has expired /* Set expiration flag. */ /* _tx_timer_expired = TX_TRUE; */ - ori t6, t6, 2 /* Set local expired flag */ - sw t4, 0(t2) /* Set expired flag in memory (UINT) */ - j _tx_timer_done /* Finished timer processing */ + ori t6, t6, 2 // Set local expired flag + sw t4, 0(t2) // Set expired flag in memory (UINT) + j _tx_timer_done // Finished timer processing /* } @@ -138,18 +138,18 @@ _tx_timer_no_timer: /* Check for wrap-around. */ /* if (_tx_timer_current_ptr == _tx_timer_list_end) */ - la t2, _tx_timer_list_end /* Pickup address of list end pointer */ - ld t3, 0(t2) /* Pickup actual list end */ - addi t1, t1, 8 /* Point to next timer entry */ - sd t1, 0(t0) /* Store new timer pointer */ - bne t1, t3, _tx_timer_skip_wrap /* If not same, good pointer */ + la t2, _tx_timer_list_end // Pickup address of list end pointer + ld t3, 0(t2) // Pickup actual list end + addi t1, t1, 8 // Point to next timer entry + sd t1, 0(t0) // Store new timer pointer + bne t1, t3, _tx_timer_skip_wrap // If not same, good pointer /* Wrap to beginning of list. */ /* _tx_timer_current_ptr = _tx_timer_list_start; */ - la t2, _tx_timer_list_start /* Pickup address of list start pointer */ - ld t4, 0(t2) /* Pickup start of the list */ - sd t4, 0(t0) /* Store new timer pointer */ + la t2, _tx_timer_list_start // Pickup address of list start pointer + ld t4, 0(t2) // Pickup start of the list + sd t4, 0(t0) // Store new timer pointer _tx_timer_skip_wrap: @@ -162,23 +162,23 @@ _tx_timer_done: /* if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) { */ - beqz t6, _tx_timer_nothing_expired /* If nothing expired skip the rest */ - addi sp, sp, -16 /* Allocate some storage on the stack */ - sd t6, 0(sp) /* Save local expired flag */ - sd ra, 8(sp) /* Save ra (8-byte aligned) */ + beqz t6, _tx_timer_nothing_expired // If nothing expired skip the rest + addi sp, sp, -16 // Allocate some storage on the stack + sd t6, 0(sp) // Save local expired flag + sd ra, 8(sp) // Save ra (8-byte aligned) /* Did a timer expire? */ /* if (_tx_timer_expired) { */ - andi t2, t6, 2 /* Isolate the timer expired bit */ - beqz t2, _tx_timer_dont_activate /* No, timer not expired */ + andi t2, t6, 2 // Isolate the timer expired bit + beqz t2, _tx_timer_dont_activate // No, timer not expired /* Call the timer expiration processing. */ /* _tx_timer_expiration_process(void); */ - call _tx_timer_expiration_process /* Call _tx_timer_expiration_process */ - ld t6, 0(sp) /* Recover local expired flag */ + call _tx_timer_expiration_process // Call _tx_timer_expiration_process + ld t6, 0(sp) // Recover local expired flag /* } */ _tx_timer_dont_activate: @@ -187,20 +187,20 @@ _tx_timer_dont_activate: /* if (_tx_timer_expired_time_slice) { */ - andi t2, t6, 1 /* Is the timer expired bit set? */ - beqz t2, _tx_timer_not_ts_expiration /* If not, skip time slice processing */ + andi t2, t6, 1 // Is the timer expired bit set? + beqz t2, _tx_timer_not_ts_expiration // If not, skip time slice processing /* Time slice interrupted thread. */ /* _tx_thread_time_slice(); */ - call _tx_thread_time_slice /* Call time slice */ + call _tx_thread_time_slice // Call time slice /* } */ _tx_timer_not_ts_expiration: - ld ra, 8(sp) /* Recover ra */ - addi sp, sp, 16 /* Recover stack space */ + ld ra, 8(sp) // Recover ra + addi sp, sp, 16 // Recover stack space /* } */ _tx_timer_nothing_expired: From ede5aa2867e857a247896151ba124caa6a94036e Mon Sep 17 00:00:00 2001 From: "shuta.lst" Date: Thu, 12 Feb 2026 22:55:52 +0800 Subject: [PATCH 07/19] Support XuanTie E906 CPU. - add ThreadX porting codes for XuanTie E906. - add example for XuanTie E906 running on QEMU smartl. --- ports/xuantie/e906/gnu/CMakeLists.txt | 17 + .../example_build/smartl_fpga/CMakeLists.txt | 78 + .../boards/board_riscv_dummy/include/board.h | 444 ++ .../board_riscv_dummy/include/csi_config.h | 26 + .../boards/board_riscv_dummy/src/board_init.c | 83 + .../board_riscv_dummy/src/uart/board_uart.c | 45 + .../smartl_fpga/build_libthreadx.sh | 7 + .../smartl_fpga/build_threadx_sample.sh | 7 + .../chip_riscv_dummy/gcc_flash_smartl.ld | 177 + .../include/asm/riscv_asm_macro.h | 538 ++ .../chip_riscv_dummy/include/asm/riscv_csr.h | 191 + .../chip_riscv_dummy/include/drv/dev_tag.h | 104 + .../chip_riscv_dummy/include/dw_timer_ll.h | 167 + .../chip_riscv_dummy/include/dw_uart.h | 0 .../chip_riscv_dummy/include/dw_uart_ll.h | 423 ++ .../components/chip_riscv_dummy/include/soc.h | 409 ++ .../chip_riscv_dummy/include/sys_clk.h | 117 + .../src/arch/e906fdp/startup.S | 224 + .../src/arch/e906fdp/system.c | 121 + .../src/arch/e906fdp/trap_c.c | 64 + .../src/arch/e906fdp/vectors.S | 898 +++ .../chip_riscv_dummy/src/drivers/dw_uart_ll.c | 164 + .../chip_riscv_dummy/src/drivers/uart.c | 809 +++ .../chip_riscv_dummy/src/sys/devices.c | 87 + .../chip_riscv_dummy/src/sys/feature.c | 311 + .../components/chip_riscv_dummy/src/sys/irq.c | 282 + .../chip_riscv_dummy/src/sys/irq_port.c | 147 + .../chip_riscv_dummy/src/sys/pre_main.c | 103 + .../chip_riscv_dummy/src/sys/sys_clk.c | 100 + .../chip_riscv_dummy/src/sys/target_get.c | 240 + .../chip_riscv_dummy/src/sys/tick.c | 341 + .../chip_riscv_dummy/src/sys/weak.c | 58 + .../csi/csi2/include/core/README.txt | 1 + .../csi/csi2/include/core/core_rv32.h | 1452 +++++ .../csi/csi2/include/core/core_rv64.h | 2002 ++++++ .../csi/csi2/include/core/csi_gcc.h | 3293 ++++++++++ .../csi/csi2/include/core/csi_rv32_gcc.h | 3374 ++++++++++ .../csi/csi2/include/core/csi_rv64_gcc.h | 4383 +++++++++++++ .../csi/csi2/include/core/csi_rv_common.h | 126 + .../csi/csi2/include/core/csi_rv_encoding.h | 716 ++ .../components/csi/csi2/include/csi_core.h | 224 + .../components/csi/csi2/include/drv/adc.h | 213 + .../components/csi/csi2/include/drv/aes.h | 309 + .../csi/csi2/include/drv/baud_calc.h | 60 + .../components/csi/csi2/include/drv/clk.h | 50 + .../components/csi/csi2/include/drv/codec.h | 450 ++ .../components/csi/csi2/include/drv/common.h | 154 + .../components/csi/csi2/include/drv/crc.h | 136 + .../components/csi/csi2/include/drv/des.h | 174 + .../components/csi/csi2/include/drv/dma.h | 306 + .../components/csi/csi2/include/drv/drv_fft.h | 83 + .../components/csi/csi2/include/drv/ecdh.h | 92 + .../components/csi/csi2/include/drv/ecdsa.h | 112 + .../components/csi/csi2/include/drv/eflash.h | 140 + .../components/csi/csi2/include/drv/efuse.h | 93 + .../components/csi/csi2/include/drv/etb.h | 102 + .../components/csi/csi2/include/drv/eth.h | 111 + .../components/csi/csi2/include/drv/eth_mac.h | 377 ++ .../components/csi/csi2/include/drv/eth_phy.h | 124 + .../components/csi/csi2/include/drv/fft.h | 87 + .../components/csi/csi2/include/drv/gpio.h | 214 + .../csi/csi2/include/drv/gpio_pin.h | 144 + .../components/csi/csi2/include/drv/hmac.h | 122 + .../components/csi/csi2/include/drv/i2s.h | 397 ++ .../components/csi/csi2/include/drv/iic.h | 338 + .../components/csi/csi2/include/drv/intc.h | 178 + .../components/csi/csi2/include/drv/io.h | 131 + .../components/csi/csi2/include/drv/irq.h | 149 + .../components/csi/csi2/include/drv/iso7816.h | 409 ++ .../components/csi/csi2/include/drv/list.h | 350 + .../components/csi/csi2/include/drv/mbox.h | 104 + .../components/csi/csi2/include/drv/pin.h | 198 + .../components/csi/csi2/include/drv/pm.h | 122 + .../components/csi/csi2/include/drv/pmu.h | 118 + .../components/csi/csi2/include/drv/porting.h | 184 + .../components/csi/csi2/include/drv/pwm.h | 172 + .../components/csi/csi2/include/drv/qspi.h | 304 + .../components/csi/csi2/include/drv/ringbuf.h | 62 + .../components/csi/csi2/include/drv/rng.h | 54 + .../components/csi/csi2/include/drv/rsa.h | 198 + .../components/csi/csi2/include/drv/rtc.h | 148 + .../components/csi/csi2/include/drv/sasc.h | 144 + .../components/csi/csi2/include/drv/sdif.h | 441 ++ .../components/csi/csi2/include/drv/sensor.h | 195 + .../components/csi/csi2/include/drv/sha.h | 128 + .../components/csi/csi2/include/drv/spi.h | 293 + .../csi/csi2/include/drv/spiflash.h | 303 + .../components/csi/csi2/include/drv/spinand.h | 321 + .../components/csi/csi2/include/drv/tee.h | 643 ++ .../components/csi/csi2/include/drv/tick.h | 92 + .../components/csi/csi2/include/drv/timer.h | 132 + .../components/csi/csi2/include/drv/tipc.h | 56 + .../components/csi/csi2/include/drv/uart.h | 241 + .../components/csi/csi2/include/drv/usi.h | 42 + .../components/csi/csi2/include/drv/usi_iic.h | 260 + .../components/csi/csi2/include/drv/usi_spi.h | 229 + .../csi/csi2/include/drv/usi_usart.h | 192 + .../components/csi/csi2/include/drv/wdt.h | 139 + .../csi/csi2/include/dsp/csi_common_tables.h | 316 + .../csi/csi2/include/dsp/csi_const_structs.h | 157 + .../csi/csi2/include/dsp/csi_instance.h | 1879 ++++++ .../csi/csi2/include/dsp/csi_math.h | 5739 +++++++++++++++++ .../csi/csi2/include/dsp/csky_common_tables.h | 229 + .../csi/csi2/include/dsp/csky_const_structs.h | 131 + .../csi/csi2/include/dsp/csky_math.h | 4637 +++++++++++++ .../include/dsp/csky_vdsp2_const_structs.h | 232 + .../csi/csi2/include/dsp/csky_vdsp2_math.h | 2378 +++++++ .../components/csi/csi2/include/syslog.h | 121 + .../components/csi/csi2/src/csi_misc.c | 25 + .../components/csi/csi2/src/csi_ringbuf.c | 184 + .../libc_threadx/compilers/gcc/sys/ioctl.h | 46 + .../libc_threadx/compilers/gcc/sys/termios.h | 291 + .../libc_threadx/compilers/gcc/time.h | 164 + .../components/libc_threadx/include/errno.h | 193 + .../libc_threadx/include/inttypes.h | 57 + .../include/serf/minilibc_stdio.h | 85 + .../libc_threadx/include/sys/_stdint.h | 45 + .../libc_threadx/include/sys/random.h | 34 + .../libc_threadx/include/sys/select.h | 52 + .../libc_threadx/include/sys/time.h | 134 + .../components/libc_threadx/mini_printf.c | 947 +++ .../components/libc_threadx/newlib_stub.c | 317 + .../example_build/smartl_fpga/demo_threadx.c | 372 ++ .../gnu/example_build/smartl_fpga/gdbinit | 1 + .../gnu/example_build/smartl_fpga/pre_main.c | 27 + .../gnu/example_build/smartl_fpga/tx_user.h | 370 ++ .../smartl_fpga/xuantie_e906_gnu.cmake | 15 + ports/xuantie/e906/gnu/inc/tx_port.h | 361 ++ ports/xuantie/e906/gnu/readme_threadx.txt | 334 + ports/xuantie/e906/gnu/src/tx_port.c | 110 + .../xuantie/e906/gnu/src/tx_thread_context.S | 283 + .../gnu/src/tx_thread_interrupt_control.S | 83 + .../xuantie/e906/gnu/src/tx_thread_schedule.S | 234 + .../e906/gnu/src/tx_thread_system_return.S | 78 + .../xuantie/e906/gnu/src/tx_timer_interrupt.c | 125 + 135 files changed, 54259 insertions(+) create mode 100644 ports/xuantie/e906/gnu/CMakeLists.txt create mode 100644 ports/xuantie/e906/gnu/example_build/smartl_fpga/CMakeLists.txt create mode 100644 ports/xuantie/e906/gnu/example_build/smartl_fpga/boards/board_riscv_dummy/include/board.h create mode 100644 ports/xuantie/e906/gnu/example_build/smartl_fpga/boards/board_riscv_dummy/include/csi_config.h create mode 100644 ports/xuantie/e906/gnu/example_build/smartl_fpga/boards/board_riscv_dummy/src/board_init.c create mode 100644 ports/xuantie/e906/gnu/example_build/smartl_fpga/boards/board_riscv_dummy/src/uart/board_uart.c create mode 100755 ports/xuantie/e906/gnu/example_build/smartl_fpga/build_libthreadx.sh create mode 100755 ports/xuantie/e906/gnu/example_build/smartl_fpga/build_threadx_sample.sh create mode 100644 ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/gcc_flash_smartl.ld create mode 100644 ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/asm/riscv_asm_macro.h create mode 100644 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ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/system.c create mode 100644 ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/trap_c.c create mode 100644 ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/vectors.S create mode 100644 ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/drivers/dw_uart_ll.c create mode 100644 ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/drivers/uart.c create mode 100644 ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/devices.c create mode 100644 ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/feature.c create mode 100644 ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/irq.c create mode 100644 ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/irq_port.c create mode 100644 ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/pre_main.c create mode 100644 ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/sys_clk.c create mode 100644 ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/target_get.c create mode 100644 ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/tick.c create mode 100644 ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/weak.c create mode 100644 ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/README.txt create mode 100644 ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/core_rv32.h create mode 100644 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ports/xuantie/e906/gnu/example_build/smartl_fpga/gdbinit create mode 100644 ports/xuantie/e906/gnu/example_build/smartl_fpga/pre_main.c create mode 100644 ports/xuantie/e906/gnu/example_build/smartl_fpga/tx_user.h create mode 100644 ports/xuantie/e906/gnu/example_build/smartl_fpga/xuantie_e906_gnu.cmake create mode 100644 ports/xuantie/e906/gnu/inc/tx_port.h create mode 100644 ports/xuantie/e906/gnu/readme_threadx.txt create mode 100644 ports/xuantie/e906/gnu/src/tx_port.c create mode 100644 ports/xuantie/e906/gnu/src/tx_thread_context.S create mode 100644 ports/xuantie/e906/gnu/src/tx_thread_interrupt_control.S create mode 100644 ports/xuantie/e906/gnu/src/tx_thread_schedule.S create mode 100644 ports/xuantie/e906/gnu/src/tx_thread_system_return.S create mode 100644 ports/xuantie/e906/gnu/src/tx_timer_interrupt.c diff --git a/ports/xuantie/e906/gnu/CMakeLists.txt b/ports/xuantie/e906/gnu/CMakeLists.txt new file mode 100644 index 00000000..33a3a43a --- /dev/null +++ b/ports/xuantie/e906/gnu/CMakeLists.txt @@ -0,0 +1,17 @@ + +target_sources(${PROJECT_NAME} + PRIVATE + # {{BEGIN_TARGET_SOURCES}} + ${CMAKE_CURRENT_LIST_DIR}/src/tx_port.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.c + # {{END_TARGET_SOURCES}} +) + +target_include_directories(${PROJECT_NAME} + PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/inc +) diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/CMakeLists.txt b/ports/xuantie/e906/gnu/example_build/smartl_fpga/CMakeLists.txt new file mode 100644 index 00000000..ed803a64 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/CMakeLists.txt @@ -0,0 +1,78 @@ +cmake_minimum_required(VERSION 3.15 FATAL_ERROR) + +project(demo_threadx + LANGUAGES C ASM +) + +set(SRCS + ${CMAKE_CURRENT_LIST_DIR}/demo_threadx.c + ${CMAKE_CURRENT_LIST_DIR}/pre_main.c + ${CMAKE_CURRENT_LIST_DIR}/boards/board_riscv_dummy/src/uart/board_uart.c + ${CMAKE_CURRENT_LIST_DIR}/boards/board_riscv_dummy/src/board_init.c + ${CMAKE_CURRENT_LIST_DIR}/components/csi/csi2/src/csi_misc.c + ${CMAKE_CURRENT_LIST_DIR}/components/csi/csi2/src/csi_ringbuf.c + ${CMAKE_CURRENT_LIST_DIR}/components/libc_threadx/mini_printf.c + ${CMAKE_CURRENT_LIST_DIR}/components/libc_threadx/newlib_stub.c + ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/arch/e906fdp/startup.S + ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/arch/e906fdp/vectors.S + ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/arch/e906fdp/system.c + ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/arch/e906fdp/trap_c.c + ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/drivers/dw_uart_ll.c + ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/drivers/uart.c + ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/sys/devices.c + ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/sys/feature.c + ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/sys/irq_port.c + ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/sys/irq.c + ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/sys/pre_main.c + ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/sys/sys_clk.c + ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/sys/target_get.c + ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/sys/tick.c + ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/sys/weak.c +) + +include_directories( + ${CMAKE_CURRENT_LIST_DIR}/../../../../../../common/inc + ${CMAKE_CURRENT_LIST_DIR}/../../inc + ${CMAKE_CURRENT_LIST_DIR} + ${CMAKE_CURRENT_LIST_DIR}/boards/board_riscv_dummy/include + ${CMAKE_CURRENT_LIST_DIR}/components/csi/csi2/include + ${CMAKE_CURRENT_LIST_DIR}/components/libc_threadx/include + ${CMAKE_CURRENT_LIST_DIR}/components/libc_threadx/compilers/gcc + ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/include + ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/include/asm +) + +add_compile_options( + -Os -g -Wno-main + -Wpointer-arith -Wno-undef -ffunction-sections -fdata-sections -fno-inline-functions -fno-builtin -fno-strict-aliasing + -DCONFIG_SUPPORT_TSPEND=1 + -DCONFIG_ARCH_MAINSTACK=4096 + -DCONFIG_ARCH_INTERRUPTSTACK=4096 + -DCONFIG_SUPPORT_IRQ_NESTED=1 + -DCONFIG_INTC_CLIC=1 + -DCONFIG_INTC_CLINT=1 + -DCONFIG_XIP=1 + -DCONFIG_LIBC_MINI_PRINTF_SUPPORT=1 + -DCONFIG_SYSTICK_HZ=100 + -DCONFIG_BOARD_SMARTL_EVB=1 + -DCONFIG_CPU_XUANTIE_E906FDP=1 + -DCONFIG_KERNEL_THREADX=1 + -DTX_INCLUDE_USER_DEFINE_FILE +) + +add_link_options( + -nostartfiles -Wl,--gc-sections + -T${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/gcc_flash_smartl.ld + -Wl,-zmax-page-size=1024 + -Wl,-Map=${PROJECT_NAME}.map +) + +link_directories(${CMAKE_CURRENT_LIST_DIR}/../../../../../../build) +add_executable(${PROJECT_NAME} ${SRCS}) +set_target_properties(${PROJECT_NAME} PROPERTIES OUTPUT_NAME "${PROJECT_NAME}.elf") +target_link_libraries(${PROJECT_NAME} PRIVATE threadx) + +add_custom_command(TARGET ${PROJECT_NAME} POST_BUILD + COMMAND ${OBJDUMP} -d $ > ${PROJECT_NAME}.asm + COMMENT "Generating ASM disassembly files" +) \ No newline at end of file diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/boards/board_riscv_dummy/include/board.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/boards/board_riscv_dummy/include/board.h new file mode 100644 index 00000000..6d5b756c --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/boards/board_riscv_dummy/include/board.h @@ -0,0 +1,444 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + This is an example board.h for Board Compment, New Board should flow the macro defines. +*/ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +// Common Board Features Define + +/* + The Common BOARD_XXX Macro Defines Boards supported features which may reference by Solutions. + Common board macro include: + . BOARD_NAME + · UART + · GPIO + · PWM + · ADC + · BUTTON + · LED + · WIFI + · BT + · AUDIO + BOARD_XXX Macro descripted below should be defined if the board support. +*/ + +/****************************************************************************/ + +/* + This riscv dummy board include: + · UART x1 + · GPIO x2 + · PWM x2 + · ADC x1 + · BUTTON x2 + · LED x2 + · WIFI x0 + · BT x0 + · AUDIO x1 +*/ + +#ifndef CONFIG_BOARD_UART +#define CONFIG_BOARD_UART 1 +#endif + +#ifndef CONFIG_BOARD_GPIO +#define CONFIG_BOARD_GPIO 0 +#endif + +#ifndef CONFIG_BOARD_PWM +#define CONFIG_BOARD_PWM 0 +#endif + +#ifndef CONFIG_BOARD_ADC +#define CONFIG_BOARD_ADC 0 +#endif + +#ifndef CONFIG_BOARD_BUTTON +#define CONFIG_BOARD_BUTTON 0 +#endif + +#ifndef CONFIG_BOARD_LED +#define CONFIG_BOARD_LED 0 +#endif + +#ifndef CONFIG_BOARD_WIFI +#define CONFIG_BOARD_WIFI 0 +#endif + +#ifndef CONFIG_BOARD_BT +#define CONFIG_BOARD_BT 0 +#endif + +#ifndef CONFIG_BOARD_AUDIO +#define CONFIG_BOARD_AUDIO 0 +#endif + +#define BOARD_NAME "RISCV_DUMMY" + +/* the board pins, can be used as uart, gpio, pwd... */ +#define BOARD_PIN0 (0) +#define BOARD_PIN1 (1) +#define BOARD_PIN2 (2) +#define BOARD_PIN3 (3) +#define BOARD_PIN4 (4) +#define BOARD_PIN5 (5) +#define BOARD_PIN6 (6) +#define BOARD_PIN7 (7) +#define BOARD_PIN8 (8) +#define BOARD_PIN9 (9) +#define BOARD_PIN10 (10) +#define BOARD_PIN11 (11) +#define BOARD_PIN12 (12) +//... + +#if defined(CONFIG_BOARD_UART) && CONFIG_BOARD_UART +// UART + +/* + The total supported uart numbers on this board, 0 meas No uart support. + the BOARD_UART_XXX, x in rang of (0, BOARD_UART_NUM - 1) +*/ +#ifndef BOARD_UART_NUM +#define BOARD_UART_NUM (1) +#endif + +#if defined(BOARD_UART_NUM) && BOARD_UART_NUM > 0 +/* the board uart0 tx pin */ +#define BOARD_UART0_TX_PIN (BOARD_PIN0) +/* the borad uart0 rx pin */ +#define BOARD_UART0_RX_PIN (BOARD_PIN1) +/* The real UART port reference to board logic port 0 */ +#define BOARD_UART0_IDX (0) +/* The default baudrate for uart0 */ +#define BOARD_UART0_BAUD (115200) + +//#define BOARD_UART1_IDX (1) +//#define BOARD_UART1_BAUD (115200) +// ... +#endif // defined(BOARD_UART_NUM) && BOARD_UART_NUM > 0 + +#endif // defined(CONFIG_BOARD_UART) && CONFIG_BOARD_UART + +#if defined(CONFIG_BOARD_GPIO) && CONFIG_BOARD_GPIO +// GPIO +/* + The total supported GPIO Pin numbers on this board, 0 meas No uart support. + the BOARD_GPIO_PIN, x in rang of (0, BOARD_GPIO_PIN_NUM - 1) +*/ +#ifndef BOARD_GPIO_PIN_NUM +#define BOARD_GPIO_PIN_NUM (2) +#endif + +#if defined(BOARD_GPIO_PIN_NUM) && BOARD_GPIO_PIN_NUM > 0 +/* The real gpio reference to board logic gpio pin */ +#define BOARD_GPIO_PIN0 (BOARD_PIN2) +#define BOARD_GPIO_PIN1 (BOARD_PIN3) +//#define BOARD_GPIO_PIN2 (x) +//#define BOARD_GPIO_PIN3 (x) +#endif // defined(BOARD_GPIO_PIN_NUM) && BOARD_GPIO_PIN_NUM > 0 +#endif // defined(CONFIG_BOARD_GPIO) && CONFIG_BOARD_GPIO + +#if defined(CONFIG_BOARD_PWM) && CONFIG_BOARD_PWM +// PWM +/* the board supported pwm channels */ +#ifndef BOARD_PWM_NUM +#define BOARD_PWM_NUM (2) +#endif + +#if defined(BOARD_PWM_NUM) && BOARD_PWM_NUM > 0 +/* the board pwm pin */ +#define BOARD_PWM0_PIN (BOARD_PIN4) +/* The real pwm channel reference to board logic pwm channel */ +#define BOARD_PWM0_CH (0) + +#define BOARD_PWM1_PIN (BOARD_PIN5) +#define BOARD_PWM1_CH (1) +#endif // defined(BOARD_PWM_NUM) && BOARD_PWM_NUM > 0 +#endif // defined(CONFIG_BOARD_PWM) && CONFIG_BOARD_PWM + +#if defined(CONFIG_BOARD_ADC) && CONFIG_BOARD_ADC > 0 +// ADC +/* the board supported adc channels */ +#ifndef BOARD_ADC_NUM +#define BOARD_ADC_NUM (1) +#endif + +#if defined(BOARD_ADC_NUM) && BOARD_ADC_NUM > 0 +/* the board adc pin */ +#define BOARD_ADC0_PIN (BOARD_PIN6) +/* The real adc channel reference to board logic adc channel */ +#define BOARD_ADC0_CH (0) +#endif // defined(BOARD_ADC_NUM) && BOARD_ADC_NUM > 0 +#endif // defined(CONFIG_BOARD_ADC) && CONFIG_BOARD_ADC > 0 + +#if defined(CONFIG_BOARD_BUTTON) && CONFIG_BOARD_BUTTON > 0 +// BUTTON +#ifndef BOARD_BUTTON_NUM +/* + the board supported buttons, include gpio button and adc button, + BOARD_BUTTON_NUM = BOARD_BUTTON_GPIO_NUM + BOARD_BUTTON_ADC_NUM. + +*/ +#define BOARD_BUTTON_NUM (4) +#endif + +#if defined(BOARD_BUTTON_NUM) && BOARD_BUTTON_NUM > 0 + +#define BOARD_BUTTON0_PIN (BOARD_PIN7) +#define BOARD_BUTTON1_PIN (BOARD_PIN8) +#define BOARD_BUTTON2_PIN (BOARD_PIN9) +#define BOARD_BUTTON3_PIN (BOARD_PIN10) + +// GPIO BUTTON +/* the board supported GPIO Buttons */ +#ifndef BOARD_BUTTON_GPIO_NUM +#define BOARD_BUTTON_GPIO_NUM (2) +#endif + +#if defined(BOARD_BUTTON_GPIO_NUM) && BOARD_BUTTON_GPIO_NUM > 0 +/* the board logic button id, in range of (0, BOARD_BUTTON_GPIO_NUM - 1) */ +#define BOARD_BUTTON0 (0) +/* for gpio button, define the pin numner. if the gpio pin used as gpio button, it shoudn't reference as BOARD_GPIO_PINx + */ +#define BOARD_BUTTON0_GPIO_PIN (BOARD_BUTTON0_PIN) + +#define BOARD_BUTTON1 (1) +#define BOARD_BUTTON1_GPIO_PIN (BOARD_BUTTON1_PIN) +#endif // defined(BOARD_BUTTON_GPIO_NUM) && BOARD_BUTTON_GPIO_NUM > 0 + +// ADC BUTTON +/* the board supported adc Buttons */ +#ifndef BOARD_BUTTON_ADC_NUM +#define BOARD_BUTTON_ADC_NUM (2) +#endif + +#if defined(BOARD_BUTTON_ADC_NUM) && BOARD_BUTTON_ADC_NUM > 0 +/* the board logic adc button id, in range of (BOARD_BUTTON_GPIO_NUM, BOARD_BUTTON_NUM - 1), if not suuport GPIO Button, + * BOARD_BUTTON_GPIO_NUM should be 0 */ +#define BOARD_BUTTON2 (BOARD_BUTTON_GPIO_NUM + 0) +#define BOARD_BUTTON2_ADC_PIN (BOARD_BUTTON2_PIN) +/* the adc channel used for button2, if the adc channel used as adc button, it shoudn't reference as BOARD_ADCx_CH*/ +#define BOARD_BUTTON2_ADC_CH (1) +/* the adc device name */ +#define BOARD_BUTTON2_ADC_NAME "adc1" +/* adc voltage reference */ +#define BOARD_BUTTON2_ADC_REF (100) +/* adc voltage range */ +#define BOARD_BUTTON2_ADC_RANG (500) + +#define BOARD_BUTTON3 (BOARD_BUTTON_GPIO_NUM + 1) +#define BOARD_BUTTON3_ADC_PIN (BOARD_BUTTON3_PIN) +#define BOARD_BUTTON3_ADC_CH (1) +#define BOARD_BUTTON3_ADC_NAME "adc1" +#define BOARD_BUTTON3_ADC_REF (600) +#define BOARD_BUTTON3_ADC_RANG (500) + +//#define BOARD_ADC_BUTTON2 (2) +//#define BOARD_ADC_BUTTON2_CH (1) +//#define BOARD_ADC_BUTTON2_NAME "adc1" +//#define BOARD_ADC_BUTTON2_REF xxx +//#define BOARD_ADC_BUTTON2_RANG xxx +#endif // defined(BOARD_BUTTON_ADC_NUM) && BOARD_BUTTON_ADC_NUM > 0 + +#endif // defined(BOARD_BUTTON_NUM) && BOARD_BUTTON_NUM > 0 + +#endif // defined(BOARD_BUTTON_NUM) && BOARD_BUTTON_NUM > 0 + +#if defined(CONFIG_BOARD_LED) && CONFIG_BOARD_LED > 0 +// LED +/* the board supported leds */ +#ifndef BOARD_LED_NUM +#define BOARD_LED_NUM (2) +#endif + +#define BOARD_LED0_PIN BOARD_PIN11 +#define BOARD_LED1_PIN BOARD_PIN12 + +// PWM LED +/* the board supported pwm leds */ +#ifndef BOARD_LED_PWM_NUM +#define BOARD_LED_PWM_NUM (1) +#endif + +#if defined(BOARD_LED_PWM_NUM) && BOARD_LED_PWM_NUM > 0 +#define BOARD_LED0_PWM_PIN (BOARD_LED0_PIN) +/* the pwm channel used for led0, if the pwm channel used as led0, it shoudn't reference as BOARD_PWMx_CH */ +#define BOARD_LED0_PWM_CH (0) +#endif // defined(BOARD_LED_PWM_NUM) && BOARD_LED_PWM_NUM > 0 + +// GPIO LED +#ifndef BOARD_LED_GPIO_NUM +#define BOARD_LED_GPIO_NUM (1) +#endif + +#if defined(BOARD_LED_GPIO_NUM) && BOARD_LED_GPIO_NUM > 0 +/* the gpio pin used for led0, if the gpio pin used as led, it shoudn't reference as BOARD_GPIO_PINx */ +#define BOARD_LED1_GPIO_PIN (BOARD_LED1_PIN) +#endif // defined(BOARD_LED_GPIO_NUM) && BOARD_LED_GPIO_NUM > 0 +#endif // defined(CONFIG_BOARD_LED) && CONFIG_BOARD_LED > 0 + +#if defined(CONFIG_BOARD_BT) && CONFIG_BOARD_BT > 0 +// BT +/* the board support bluetooth */ +#ifndef BOARD_BT_SUPPORT +#define BOARD_BT_SUPPORT 1 +#endif +#endif // defined(CONFIG_BOARD_BT) && CONFIG_BOARD_BT > 0 + +#if defined(CONFIG_BOARD_WIFI) && CONFIG_BOARD_WIFI > 0 +// WIFI +/* the board support wifi */ +#ifndef BOARD_WIFI_SUPPORT +#define BOARD_WIFI_SUPPORT 1 +#endif +#endif // defined(CONFIG_BOARD_WIFI) && CONFIG_BOARD_WIFI > 0 + +#if defined(CONFIG_BOARD_AUDIO) && CONFIG_BOARD_AUDIO > 0 +// Audio +/* the board support audio */ +#ifndef BOARD_AUDIO_SUPPORT +#define BOARD_AUDIO_SUPPORT 1 +#endif +#endif // defined(CONFIG_BOARD_AUDIO) && CONFIG_BOARD_AUDIO > 0 + +/****************************************************************************/ +// Common solutions defines + +// Console config, Almost all solutions and demos use these. +#ifndef CONSOLE_UART_IDX +#define CONSOLE_UART_IDX (BOARD_UART0_IDX) +#endif + +#ifndef CONFIG_CLI_USART_BAUD +#define CONFIG_CLI_USART_BAUD (BOARD_UART0_BAUD) +#endif + +#ifndef CONFIG_CONSOLE_UART_BUFSIZE +#define CONFIG_CONSOLE_UART_BUFSIZE (128) +#endif + +/****************************************************************************/ +// Commom test demos defines + +// i2c +#define EXAMPLE_IIC_IDX 0 // 1 +#define EXAMPLE_PIN_IIC_SDA 0 // PC1 +#define EXAMPLE_PIN_IIC_SCL 0 // PC0 +#define EXAMPLE_PIN_IIC_SDA_FUNC 0 // PC1_I2C1_SDA +#define EXAMPLE_PIN_IIC_SCL_FUNC 0 // PC0_I2C1_SCL + +// adc +#define EXAMPLE_ADC_CH0 0 // PA8 +#define EXAMPLE_ADC_CH0_FUNC 0 // PA8_ADC_A0 +#define EXAMPLE_ADC_CH12 0 // PA26 +#define EXAMPLE_ADC_CH12_FUNC 0 // PA26_ADC_A12 + +#define EXAMPLE_TIMER_IDX 0 + +/****************************************************************************/ +// Vendor board defines + +/* other board specific defines */ +//#define CUSTOM_BOARD_xxx + +/****************************************************************************/ +/** + * @brief init the board for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_init(void); + +/** + * @brief init the board gpio pin for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_gpio_pin_init(void); + +/** + * @brief init the board uart for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_uart_init(void); + +/** + * @brief init the board pwm for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_pwm_init(void); + +/** + * @brief init the board adc for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_adc_init(void); + +/** + * @brief init the board button for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_button_init(void); + +/** + * @brief init the board led for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_led_init(void); + +/** + * @brief init the board wifi for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_wifi_init(void); + +/** + * @brief init the board bt for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_bt_init(void); + +/** + * @brief init the board audio for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_audio_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_H__ */ \ No newline at end of file diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/boards/board_riscv_dummy/include/csi_config.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/boards/board_riscv_dummy/include/csi_config.h new file mode 100644 index 00000000..8e1af58f --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/boards/board_riscv_dummy/include/csi_config.h @@ -0,0 +1,26 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CSI_CONFIG_H__ +#define __CSI_CONFIG_H__ + + + + + +#endif /* __CSI_CONFIG_H__ */ \ No newline at end of file diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/boards/board_riscv_dummy/src/board_init.c b/ports/xuantie/e906/gnu/example_build/smartl_fpga/boards/board_riscv_dummy/src/board_init.c new file mode 100644 index 00000000..b994f6ce --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/boards/board_riscv_dummy/src/board_init.c @@ -0,0 +1,83 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include + +void board_init(void) +{ + /* some board preconfig */ + // board_xxx(); + +#if defined(BOARD_GPIO_PIN_NUM) && BOARD_GPIO_PIN_NUM > 0 + board_gpio_pin_init(); +#endif + +#if defined(BOARD_UART_NUM) && BOARD_UART_NUM > 0 +#if !defined(RT_DEBUG_INIT) || !RT_DEBUG_INIT + board_uart_init(); +#endif +#endif + +#if defined(BOARD_PWM_NUM) && BOARD_PWM_NUM > 0 + board_pwm_init(); +#endif + +#if defined(BOARD_ADC_NUM) && BOARD_ADC_NUM > 0 + board_adc_init(); +#endif + +#if defined(BOARD_BUTTON_NUM) && BOARD_BUTTON_NUM > 0 + board_button_init(); +#endif + +#if defined(BOARD_LED_NUM) && BOARD_LED_NUM > 0 + board_led_init(); +#endif + +#if defined(BOARD_WIFI_SUPPORT) && BOARD_WIFI_SUPPORT > 0 + board_wifi_init(); +#endif + +#if defined(BOARD_BT_SUPPORT) && BOARD_BT_SUPPORT > 0 + board_bt_init(); +#endif + +#if defined(BOARD_AUDIO_SUPPORT) && BOARD_AUDIO_SUPPORT > 0 + board_audio_init(); +#endif +} + +#ifdef CONFIG_KERNEL_THREADX +#include + +extern unsigned long g_heap_start; +extern unsigned long g_heap_end; + +TX_BYTE_POOL tx_byte_pool_0; +UCHAR *tx_memory_area; + +void tx_mem_pool_init(void) +{ + ULONG pool_size = g_heap_end - g_heap_start; + tx_memory_area = (UCHAR *)g_heap_start; + + tx_byte_pool_create(&tx_byte_pool_0, "byte pool sys 0", tx_memory_area, pool_size); +} +#endif diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/boards/board_riscv_dummy/src/uart/board_uart.c b/ports/xuantie/e906/gnu/example_build/smartl_fpga/boards/board_riscv_dummy/src/uart/board_uart.c new file mode 100644 index 00000000..315e3aed --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/boards/board_riscv_dummy/src/uart/board_uart.c @@ -0,0 +1,45 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#if CONFIG_DEVICES_RVM_HAL +#include +#else +#include +#endif + +#if CONFIG_DEVICES_RVM_HAL +void board_uart_init(void) +{ + rvm_uart_drv_register(0); +} +#else +__attribute__((weak)) csi_uart_t g_console_handle; + +void board_uart_init(void) +{ + /* init the console */ + csi_uart_init(&g_console_handle, CONSOLE_UART_IDX); + + /* config the UART */ + csi_uart_baud(&g_console_handle, CONFIG_CLI_USART_BAUD); + csi_uart_format(&g_console_handle, UART_DATA_BITS_8, UART_PARITY_NONE, UART_STOP_BITS_1); +} +#endif diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/build_libthreadx.sh b/ports/xuantie/e906/gnu/example_build/smartl_fpga/build_libthreadx.sh new file mode 100755 index 00000000..2f35e09e --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/build_libthreadx.sh @@ -0,0 +1,7 @@ +#!/bin/bash + +pushd ../../../../../../ +rm -rf build +cmake -Bbuild -GNinja -DCMAKE_TOOLCHAIN_FILE=ports/xuantie/e906/gnu/example_build/smartl_fpga/xuantie_e906_gnu.cmake . +cmake --build ./build/ +popd diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/build_threadx_sample.sh b/ports/xuantie/e906/gnu/example_build/smartl_fpga/build_threadx_sample.sh new file mode 100755 index 00000000..ec91e36a --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/build_threadx_sample.sh @@ -0,0 +1,7 @@ +#!/bin/bash + +bash build_libthreadx.sh + +rm -rf build +cmake -Bbuild -GNinja -DCMAKE_TOOLCHAIN_FILE=xuantie_e906_gnu.cmake . +cmake --build ./build/ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/gcc_flash_smartl.ld b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/gcc_flash_smartl.ld new file mode 100644 index 00000000..3cfad67d --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/gcc_flash_smartl.ld @@ -0,0 +1,177 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file gcc_csky.ld + * @brief csky linker file + * @version V1.0 + * @date 02. June 2017 + ******************************************************************************/ +MEMORY +{ + ISRAM : ORIGIN = 0x00000000 , LENGTH = 0x30000 /* ISRAM 192KB*/ + DSRAM : ORIGIN = 0x20000000 , LENGTH = 0xC0000 /* DSRAM 768KB*/ + SRAM : ORIGIN = 0x60000000 , LENGTH = 0x20000 /* SRAM 128KB, no cacheable*/ +} + +__min_heap_size = 0x200; +PROVIDE (__ram_end = 0x200C0000); +PROVIDE (__heap_end = __ram_end); + +REGION_ALIAS("REGION_TEXT", ISRAM); +REGION_ALIAS("REGION_RODATA", ISRAM); +REGION_ALIAS("REGION_DATA", DSRAM); +REGION_ALIAS("REGION_BSS", DSRAM); + +ENTRY(Reset_Handler) +SECTIONS +{ + .text : { + . = ALIGN(0x4) ; + __stext = . ; + KEEP(*startup.o(*.text)) + KEEP(*startup.o(*.vectors)) + KEEP(*vectors.o(*.text)) + KEEP(*whetstone.o(*.text)) + KEEP(*startup.S.obj(*.text)) + KEEP(*startup.S.obj(*.vectors)) + KEEP(*vectors.S.obj(*.text)) + KEEP(*whetstone.c.obj(*.text)) + KEEP(*(.text.entry)) + *(.text*) + *(.gnu.warning) + *(.stub) + *(.gnu.linkonce.t*) + *(.glue_7t) + *(.glue_7) + *(.jcr) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN (0x4) ; + PROVIDE(__ctbp = .); + *(.call_table_data) + *(.call_table_text) + . = ALIGN(0x10) ; + __etext = . ; + } > REGION_TEXT + .eh_frame_hdr : { + *(.eh_frame_hdr) + } > REGION_TEXT + .eh_frame : ONLY_IF_RO { + KEEP (*(.eh_frame)) + } > REGION_TEXT + .rodata : { + . = ALIGN(0x4) ; + __srodata = .; + *(.rdata) + *(.rdata*) + *(.rdata1) + *(.rdata.*) + *(.rodata*) + *(.srodata*) + . = ALIGN(0x4) ; + __init_array_start = .; + __ctors_start__ = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + __ctors_end__ = .; + + __fini_array_start = .; + __dtors_start__ = .; + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array)) + __fini_array_end = .; + __dtors_end__ = .; + . = ALIGN(0x4) ; + + __ctor_start__ = .; + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __ctor_end__ = .; + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __dtor_end__ = .; + . = ALIGN(0x4) ; + __erodata = .; + __rodata_end__ = .; + } > REGION_RODATA + .data : { + . = ALIGN(0x4) ; + __sdata = . ; + __data_start__ = . ; + data_start = . ; + *(.got.plt) + *(.got) + *(.gnu.linkonce.r*) + *(.data*) + *(.gnu.linkonce.d*) + *(.gcc_except_table*) + __start_init_call = .; + *(.initcall.init) + __stop_init_call = .; + __start_cmd = .; + *(.bootloaddata.cmd) + . = ALIGN(0x4) ; + __stop_cmd = .; + __global_pointer$ = .; + *(.sdata) + *(.sdata.*) + *(.sdata2.*) + *(.gnu.linkonce.s.*) + *(__libc_atexit) + *(__libc_subinit) + *(__libc_subfreeres) + *(.note.ABI-tag) + . = ALIGN(0x4) ; + __edata = .; + __data_end__ = .; + } > REGION_DATA AT > REGION_RODATA + ._ram_code : { + . = ALIGN(0x4) ; + __ram_code_start__ = .; + *(.ram.code*) + . = ALIGN(0x4) ; + __ram_code_end__ = .; + } > REGION_DATA AT > REGION_RODATA + .bss : ALIGN(0x20) { + __sbss = . ; + __bss_start__ = . ; + KEEP(*linpack.o(*.bss*)) + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.scommon) + *(.dynbss) + *(.bss*) + *(COMMON) + . = ALIGN(0x4) ; + __ebss = . ; + __bss_end__ = .; + __end = . ; + end = . ; + } > REGION_BSS AT > REGION_BSS + ._user_heap (NOLOAD): { + . = ALIGN(0x4) ; + *(.stack*) + . = ALIGN(0x4) ; + __heap_start = .; + . += __min_heap_size; + . = ALIGN(0x4) ; + } > REGION_BSS AT > REGION_BSS +} diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/asm/riscv_asm_macro.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/asm/riscv_asm_macro.h new file mode 100644 index 00000000..dfa08578 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/asm/riscv_asm_macro.h @@ -0,0 +1,538 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * attention: don't modify this file as a suggest + * you should copy from chip_riscv_dummy/include/asm/riscv_asm_macro.h and keep it newer + * please contact xuantie-rtos os team if have question + */ + +#ifndef __RISCV_ASM_MACRO_H__ +#define __RISCV_ASM_MACRO_H__ + + +#include "riscv_csr.h" + +.macro RESTORE_xSTATUS + /* t0 and t1 are not restored before using */ + /* now, sp is at the top of the stack (the lowest address)*/ + li t1, 0 +#if __riscv_matrix || __riscv_xtheadmatrix /* matrix registers */ +#if __riscv_xlen == 64 + addi t1, t1, (12 + 12) +#else + addi t1, t1, 12 +#endif /*__riscv_xlen */ + csrr t0, xmlenb + slli t0, t0, 3 + add t1, t1, t0 +#endif /* __riscv_matrix || __riscv_xtheadmatrix */ + +#ifdef __riscv_vector /* vector registers */ + csrr t0, vlenb + slli t0, t0, 5 + add t1, t1, t0 +#if __riscv_xlen == 64 + addi t1, t1, (20+20) +#else + addi t1, t1, 20 +#endif /* __riscv_xlen */ +#endif /* __riscv_vector */ + +#if __riscv_flen == 64 /* float registers */ +#if __riscv_xlen == 64 + addi t1, t1, 168 +#else + addi t1, t1, 164 +#endif /* __riscv_xlen */ + +#elif __riscv_flen == 32 + addi t1, t1, 84 +#endif /* __riscv_flen */ + +#ifdef __riscv_dsp /* vxsat register, 32-bit cpu only */ + addi t1, t1, 4 +#endif /* __riscv_dsp */ + +#if __riscv_xlen == 64 /*general purpose registers*/ + addi t1, t1, (72 + 72) +#elif __riscv_xlen == 32 + addi t1, t1, 72 +#endif + add t1, sp, t1 + + /* now, t1 is the position of mstatus */ + load_x t3, (0)(t1) + csrw MODE_PREFIX(status), t3 +.endm + +.macro SAVE_VECTOR_REGISTERS + /* t0,t1 saved before using */ + /* mstatus->t3 */ +#ifdef __riscv_vector +#if CONFIG_CHECK_VECTOR_DIRTY + /* check if VS filed of MSTATUS is 'dirty' */ + li t1, SR_VS_DIRTY + and t4, t3, t1 + bne t4, t1, 1f +#endif /* CONFIG_CHECK_VECTOR_DIRTY */ + + /* if dirty, save vector registers */ +#if __riscv_xlen == 64 + addi sp, sp, -(20+20) + csrr t0, vl + store_x t0, (0 +0 )(sp) + csrr t0, vtype + store_x t0, (4 +4 )(sp) + csrr t0, vstart + store_x t0, (8 +8 )(sp) + csrr t0, vxsat + store_x t0, (12 +12 )(sp) + csrr t0, vxrm + store_x t0, (16 +16 )(sp) +#else + addi sp, sp, -20 + csrr t0, vl + store_x t0, (0)(sp) + csrr t0, vtype + store_x t0, (4)(sp) + csrr t0, vstart + store_x t0, (8)(sp) + csrr t0, vxsat + store_x t0, (12)(sp) + csrr t0, vxrm + store_x t0, (16)(sp) +#endif /*__riscv_xlen */ + + csrr t0, vlenb + slli t0, t0, 3 + slli t1, t0, 2 + sub sp, sp, t1 +#if (__riscv_v == 7000) + vsetvli zero, zero, e8, m8 + vsb.v v0, (sp) + add sp, sp, t0 + vsb.v v8, (sp) + add sp, sp, t0 + vsb.v v16, (sp) + add sp, sp, t0 + vsb.v v24, (sp) +#elif (__riscv_v == 1000000) + vsetvli zero, zero, e8, m8, ta, ma + vs8r.v v0, (sp) + add sp, sp, t0 + vs8r.v v8, (sp) + add sp, sp, t0 + vs8r.v v16, (sp) + add sp, sp, t0 + vs8r.v v24, (sp) +#endif + sub t0, t1, t0 + sub sp, sp, t0 +#if CONFIG_CHECK_VECTOR_DIRTY + j 2f +1: /* don't need to save vector registers, set sp */ +#if __riscv_xlen == 64 + addi sp, sp, -(20+20) +#else + addi sp, sp, -20 +#endif + csrr t0, vlenb + slli t0, t0, 5 + sub sp, sp, t0 +2: +#endif /* CONFIG_CHECK_VECTOR_DIRTY */ +#endif /*__riscv_vector*/ +.endm + +.macro RESTORE_VECTOR_REGISTERS + /* t0,t1,t2 not restored before using, mstatus has been restored before using */ +#ifdef __riscv_vector +#if CONFIG_CHECK_VECTOR_DIRTY + /* check if VS filed of MSTATUS is 'dirty' */ + li t1, SR_VS_DIRTY + and t4, t3, t1 + bne t4, t1, 1f +#endif /* CONFIG_CHECK_VECTOR_DIRTY */ + + /* get the range of register */ + csrr t0, vlenb + slli t0, t0, 3 + + /* save */ +#if (__riscv_v == 7000) + vsetvli zero, zero, e8, m8 + vlb.v v0, (sp) + add sp, sp, t0 + vlb.v v8, (sp) + add sp, sp, t0 + vlb.v v16, (sp) + add sp, sp, t0 + vlb.v v24, (sp) + add sp, sp, t0 +#elif (__riscv_v == 1000000) + vsetvli zero, zero, e8, m8, ta, ma + vl8r.v v0, (sp) + add sp, sp, t0 + vl8r.v v8, (sp) + add sp, sp, t0 + vl8r.v v16, (sp) + add sp, sp, t0 + vl8r.v v24, (sp) + add sp, sp, t0 +#endif +#if __riscv_xlen == 64 + load_x t0, (0 +0)(sp) + load_x t1, (4 +4)(sp) + load_x t2, (8 +8)(sp) + vsetvl zero, t0, t1 + csrw vstart, t2 + load_x t2, (12 +12)(sp) + csrw vxsat, t2 + load_x t2, (16 +16)(sp) + csrw vxrm, t2 + addi sp, sp, (20+20) +#else + load_x t0, (0)(sp) + load_x t1, (4)(sp) + load_x t2, (8)(sp) + vsetvl zero, t0, t1 + csrw vstart, t2 + load_x t2, (12)(sp) + csrw vxsat, t2 + load_x t2, (16)(sp) + csrw vxrm, t2 + addi sp, sp, 20 +#endif /*__riscv_xlen */ +#if CONFIG_CHECK_VECTOR_DIRTY + j 2f +1: + /* don't restore, move sp only */ +#if __riscv_xlen == 64 + addi sp, sp, (20+20) +#else + addi sp, sp, (20) +#endif + csrr t0, vlenb + slli t0, t0, 5 + add sp, sp, t0 +2: +#endif /* CONFIG_CHECK_VECTOR_DIRTY */ +#endif /*__riscv_vector*/ +.endm + + +.macro SAVE_FLOAT_REGISTERS + /* t0, t1 saved before using */ +#if __riscv_flen == 64 +#if CONFIG_CHECK_FPU_DIRTY + /* check if FS filed of MSTATUS is 'dirty' */ + li t1, SR_FS_DIRTY + and t4, t3, t1 + bne t4, t1, 1f +#endif /*CONFIG_CHECK_FPU_DIRTY*/ + + /* save */ +#if __riscv_xlen == 64 + addi sp, sp, -(4+4) + frcsr t0 + store_x t0, (0 +0 )(sp) +#else + addi sp, sp, -4 + frcsr t0 + store_x t0, 0(sp) +#endif /*__riscv_xlen */ + + addi sp, sp, -160 + fstore_x ft0, (0 +0 )(sp) + fstore_x ft1, (4 +4 )(sp) + fstore_x ft2, (8 +8 )(sp) + fstore_x ft3, (12+12)(sp) + fstore_x ft4, (16+16)(sp) + fstore_x ft5, (20+20)(sp) + fstore_x ft6, (24+24)(sp) + fstore_x ft7, (28+28)(sp) + fstore_x fa0, (32+32)(sp) + fstore_x fa1, (36+36)(sp) + fstore_x fa2, (40+40)(sp) + fstore_x fa3, (44+44)(sp) + fstore_x fa4, (48+48)(sp) + fstore_x fa5, (52+52)(sp) + fstore_x fa6, (56+56)(sp) + fstore_x fa7, (60+60)(sp) + fstore_x ft8, (64+64)(sp) + fstore_x ft9, (68+68)(sp) + fstore_x ft10,(72+72)(sp) + fstore_x ft11,(76+76)(sp) +#elif __riscv_flen == 32 +#if CONFIG_CHECK_FPU_DIRTY + /* check if FS filed of MSTATUS is 'dirty' */ + li t1, SR_FS_DIRTY + and t4, t3, t1 + bne t4, t1, 1f +#endif /* CONFIG_CHECK_FPU_DIRTY */ + + addi sp, sp, -4 + frcsr t0 + store_x t0, 0(sp) + + addi sp, sp, -80 + fstore_x ft0, 0(sp) + fstore_x ft1, 4(sp) + fstore_x ft2, 8(sp) + fstore_x ft3, 12(sp) + fstore_x ft4, 16(sp) + fstore_x ft5, 20(sp) + fstore_x ft6, 24(sp) + fstore_x ft7, 28(sp) + fstore_x fa0, 32(sp) + fstore_x fa1, 36(sp) + fstore_x fa2, 40(sp) + fstore_x fa3, 44(sp) + fstore_x fa4, 48(sp) + fstore_x fa5, 52(sp) + fstore_x fa6, 56(sp) + fstore_x fa7, 60(sp) + fstore_x ft8, 64(sp) + fstore_x ft9, 68(sp) + fstore_x ft10,72(sp) + fstore_x ft11,76(sp) +#endif /*__riscv_flen */ +#if CONFIG_CHECK_FPU_DIRTY + j 2f +1: + /* don't store, move sp only */ +#if __riscv_flen == 64 +#if __riscv_xlen == 64 + addi sp, sp, -168 +#else + addi sp, sp, -164 +#endif /*__riscv_xlen */ +#elif __riscv_flen == 32 + addi sp, sp, -84 +#endif /* __riscv_xlen */ +2: +#endif +.endm + +.macro RESTORE_FLOAT_REGISTERS + /* t0 and t1 are not restored before using, mstatus has been restored before using */ +#if __riscv_flen == 64 +#if CONFIG_CHECK_FPU_DIRTY + /* check if FS filed of MSTATUS is 'dirty' */ + li t1, SR_FS_DIRTY + and t4, t3, t1 + bne t4, t1, 1f +#endif /* CONFIG_CHECK_FPU_DIRTY */ + + /* restore */ + fload_x ft0, (0 +0 )(sp) + fload_x ft1, (4 +4 )(sp) + fload_x ft2, (8 +8 )(sp) + fload_x ft3, (12+12)(sp) + fload_x ft4, (16+16)(sp) + fload_x ft5, (20+20)(sp) + fload_x ft6, (24+24)(sp) + fload_x ft7, (28+28)(sp) + fload_x fa0, (32+32)(sp) + fload_x fa1, (36+36)(sp) + fload_x fa2, (40+40)(sp) + fload_x fa3, (44+44)(sp) + fload_x fa4, (48+48)(sp) + fload_x fa5, (52+52)(sp) + fload_x fa6, (56+56)(sp) + fload_x fa7, (60+60)(sp) + fload_x ft8, (64+64)(sp) + fload_x ft9, (68+68)(sp) + fload_x ft10,(72+72)(sp) + fload_x ft11,(76+76)(sp) + addi sp, sp, 160 + +#if __riscv_xlen == 64 + load_x t0, (0 +0)(sp) + fscsr t0 + addi sp, sp, (4+4) +#else + load_x t0, 0(sp) + fscsr t0 + addi sp, sp, 4 +#endif /*__riscv_xlen */ +#elif __riscv_flen == 32 +#if CONFIG_CHECK_FPU_DIRTY + /* check if FS filed of MSTATUS is 'dirty' */ + li t1, SR_FS_DIRTY + and t4, t3, t1 + bne t4, t1, 1f +#endif /* CONFIG_CHECK_FPU_DIRTY */ + + /* restore */ + fload_x ft0, 0(sp) + fload_x ft1, 4(sp) + fload_x ft2, 8(sp) + fload_x ft3, 12(sp) + fload_x ft4, 16(sp) + fload_x ft5, 20(sp) + fload_x ft6, 24(sp) + fload_x ft7, 28(sp) + fload_x fa0, 32(sp) + fload_x fa1, 36(sp) + fload_x fa2, 40(sp) + fload_x fa3, 44(sp) + fload_x fa4, 48(sp) + fload_x fa5, 52(sp) + fload_x fa6, 56(sp) + fload_x fa7, 60(sp) + fload_x ft8, 64(sp) + fload_x ft9, 68(sp) + fload_x ft10,72(sp) + fload_x ft11,76(sp) + addi sp, sp, 80 + + load_x t0, 0(sp) + fscsr t0 + addi sp, sp, 4 +#endif /*__riscv_flen */ +#if CONFIG_CHECK_FPU_DIRTY + j 2f +1: + /* don't restore, move sp only */ +#if __riscv_flen == 64 +#if __riscv_xlen == 64 + addi sp, sp, 168 +#elif __riscv_xlen == 32 + addi sp, sp, 164 +#endif +#elif __riscv_flen == 32 + addi sp, sp, 84 +#endif /* __riscv_flen */ +2: +#endif /* CONFIG_CHECK_FPU_DIRTY */ +.endm + +.macro SAVE_MATRIX_REGISTERS + /* t0,t1 saved before using */ + +#if __riscv_matrix || __riscv_xtheadmatrix +#if CONFIG_CHECK_MATRIX_DIRTY + /* check if FS filed of MSTATUS is 'dirty' */ + li t1, SR_MS_DIRTY + and t4, t3, t1 + bne t4, t1, 1f +#endif /* CONFIG_CHECK_MATRIX_DIRTY */ + + /* store */ +#if __riscv_xlen == 64 + addi sp, sp, -(12+12) + csrr t0, xmrstart + store_x t0, (0 +0 )(sp) + csrr t0, xmcsr + store_x t0, (4 +4 )(sp) + csrr t0, xmsize + store_x t0, (8 +8 )(sp) +#else + addi sp, sp, -12 + csrr t0, xmrstart + store_x t0, (0)(sp) + csrr t0, xmcsr + store_x t0, (4)(sp) + csrr t0, xmsize + store_x t0, (8)(sp) +#endif /*__riscv_xlen */ + + csrr t0, xmlenb + slli t1, t0, 3 + sub sp, sp, t1 + csrw xmrstart, x0 + mst8mb m0, (sp) +#if CONFIG_CHECK_MATRIX_DIRTY + j 2f +1: + /* don't save, move sp only */ + csrr t0, xmlenb + slli t1, t0, 3 + sub sp, sp, t1 +#if __riscv_xlen == 64 + addi sp, sp, -24 +#else + addi sp, sp, -12 +#endif +2: +#endif /* CONFIG_CHECK_MATRIX_DIRTY */ +#endif /* __riscv_matrix || __riscv_xtheadmatrix */ +.endm + +.macro RESTORE_MATRIX_REGISTERS + /* t0 and t1 are not restored before using, mstatus has been restored before using */ + +#if __riscv_matrix || __riscv_xtheadmatrix +#if CONFIG_CHECK_MATRIX_DIRTY + /* check if FS filed of MSTATUS is 'dirty' */ + li t1, SR_MS_DIRTY + and t4, t3, t1 + bne t4, t1, 1f +#endif /* CONFIG_CHECK_MATRIX_DIRTY */ + + /* restore */ + csrr t0, xmlenb + slli t1, t0, 3 + csrw xmrstart, x0 + mld8mb m0, (sp) + add sp, sp, t1 +#if __riscv_xlen == 64 + load_x t0, (0 + 0)(sp) + csrw xmrstart, t0 + load_x t0, (4 + 4)(sp) + csrw xmcsr, t0 + load_x t0, (8 + 8)(sp) + csrw xmsize, t0 + addi sp, sp, (12+12) +#else + load_x t0, (0)(sp) + csrw xmrstart, t0 + load_x t0, (4)(sp) + csrw xmcsr, t0 + load_x t0, (8)(sp) + csrw xmsize, t0 + addi sp, sp, 12 +#endif /*__riscv_xlen */ +#if CONFIG_CHECK_MATRIX_DIRTY + j 2f +1: + /* don't restore, move sp only */ + csrr t0, xmlenb + slli t1, t0, 3 + add sp, sp, t1 +#if __riscv_xlen == 64 + addi sp, sp, 24 +#else + addi sp, sp, 12 +#endif +2: +#endif /* CONFIG_CHECK_MATRIX_DIRTY */ +#endif /* __riscv_matrix || __riscv_xtheadmatrix */ +.endm + +.macro RESTORE_SYS_GP + .option push + .option norelax + la gp, __global_pointer$ + .option pop +.endm + +#endif /* __RISCV_ASM_MACRO_H__ */ + diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/asm/riscv_csr.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/asm/riscv_csr.h new file mode 100644 index 00000000..0bea1b57 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/asm/riscv_csr.h @@ -0,0 +1,191 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * attention: don't modify this file as a suggest + * you should copy from chip_riscv_dummy/include/asm/riscv_csr.h and keep it newer + * please contact xuantie-rtos os team if have question + */ + +#ifndef __RISCV_CSR_H__ +#define __RISCV_CSR_H__ + +#if __riscv_xlen == 64 + #define store_x sd + #define load_x ld + #define portWORD_SIZE 8 +#elif __riscv_xlen == 32 + #define store_x sw + #define load_x lw + #define portWORD_SIZE 4 +#else + #error Assembler did not define __riscv_xlen +#endif + +#if __riscv_flen == 64 + #define fstore_x fsd + #define fload_x fld + #define portFPU_REG_SIZE 8 +#elif __riscv_flen == 32 + #define fstore_x fsw + #define fload_x flw + #define portFPU_REG_SIZE 4 +#endif + +#if CONFIG_RISCV_SMODE +#define MODE_PREFIX(suffix) s##suffix +#else +#define MODE_PREFIX(suffix) m##suffix +#endif + +/* Status register flags */ +#define SR_SIE 0x00000002UL /* Supervisor Interrupt Enable */ +#define SR_MIE 0x00000008UL /* Machine Interrupt Enable */ +#define SR_SPIE 0x00000020UL /* Previous Supervisor IE */ +#define SR_MPIE 0x00000080UL /* Previous Machine IE */ +#define SR_SPP_U 0x00000000UL /* Previously User mode */ +#define SR_SPP_S 0x00000100UL /* Previously Supervisor mode */ +#define SR_MPP_U 0x00000000UL /* Previously User mode */ +#define SR_MPP_S 0x00000800UL /* Previously Supervisor mode */ +#define SR_MPP_M 0x00001800UL /* Previously Machine mode */ +#define SR_SUM 0x00040000UL /* Supervisor User Memory Access */ + +#define SR_FS 0x00006000UL /* Floating-point Status */ +#define SR_FS_OFF 0x00000000UL +#define SR_FS_INITIAL 0x00002000UL +#define SR_FS_CLEAN 0x00004000UL +#define SR_FS_DIRTY 0x00006000UL + +#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \ + || CONFIG_CPU_XUANTIE_R920 \ + || CONFIG_CPU_XUANTIE_C920 +#define SR_VS 0x01800000 +#define SR_VS_OFF 0x00000000 +#define SR_VS_INITIAL 0x00800000 +#define SR_VS_CLEAN 0x01000000 +#define SR_VS_DIRTY 0x01800000 +#else +#define SR_VS 0x00000600 +#define SR_VS_OFF 0x00000000 +#define SR_VS_INITIAL 0x00000200 +#define SR_VS_CLEAN 0x00000400 +#define SR_VS_DIRTY 0x00000600 +#endif + +#if __riscv_matrix || __riscv_xtheadmatrix +#define SR_MS 0x06000000 +#define SR_MS_OFF 0x00000000 +#define SR_MS_INITIAL 0x02000000 +#define SR_MS_CLEAN 0x04000000 +#define SR_MS_DIRTY 0x06000000 +#endif + +/* Interrupt-enable Registers */ +#define IE_MTIE 0x00000080UL +#define IE_MEIE 0x00000800UL + +/* ===== Trap/Exception Causes ===== */ +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FETCH_ACCESS 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_LOAD_ACCESS 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_STORE_ACCESS 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_M 3 + + +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_SPIE_SHIFT 5 +#define MSTATUS_SPIE (1 << MSTATUS_SPIE_SHIFT) +#define MSTATUS_UBE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP_SHIFT 8 +#define MSTATUS_SPP (1 << MSTATUS_SPP_SHIFT) +#define MSTATUS_MPP_SHIFT 11 +#define MSTATUS_MPP (3 << MSTATUS_MPP_SHIFT) + +#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \ + || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 \ + || CONFIG_CPU_XUANTIE_C910 || CONFIG_CPU_XUANTIE_C920 +#define MSTATUS_VS_SHIFT 23 +#else +#define MSTATUS_VS_SHIFT 9 +#endif +#define MSTATUS_FS_SHIFT 13 +#define MSTATUS_MS_SHIFT 25 + +#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) + +#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \ + || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \ + || CONFIG_CPU_XUANTIE_C908_V2 || CONFIG_CPU_XUANTIE_C908V_V2 || CONFIG_CPU_XUANTIE_C908I_V2 \ + || CONFIG_CPU_XUANTIE_C908_CP_V2 || CONFIG_CPU_XUANTIE_C908V_CP_V2 || CONFIG_CPU_XUANTIE_C908I_CP_V2 \ + || CONFIG_CPU_XUANTIE_C908_CP_XT_V2 || CONFIG_CPU_XUANTIE_C908V_CP_XT_V2 || CONFIG_CPU_XUANTIE_C908I_CP_XT_V2 \ + || CONFIG_CPU_XUANTIE_C908VK_CP_V2 || CONFIG_CPU_XUANTIE_C908VK_CP_XT_V2 \ + || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 \ + || CONFIG_CPU_XUANTIE_C910 || CONFIG_CPU_XUANTIE_C920 \ + || CONFIG_CPU_XUANTIE_XT_C930_CP || CONFIG_CPU_XUANTIE_XT_C930V_CP +#define ATTR_SO (1ull << 4) +#define ATTR_CA (1ull << 3) +#define ATTR_BU (1ull << 2) +#define ATTR_SH (1ull << 1) +#define ATTR_SE (1ull << 0) + +#define UPPER_ATTRS_SHIFT (59) +#define UPPER_ATTRS(x) (((x) & 0x1f) << UPPER_ATTRS_SHIFT) +#else +#if __riscv_xlen == 32 +#define PTE_PBMT_SHIFT (30) +#else +#define PTE_PBMT_SHIFT (61) +#endif /* end __riscv_xlen */ +#define SVPBMT_PMA ((unsigned long)0x0 << PTE_PBMT_SHIFT) +#define SVPBMT_NC ((unsigned long)0x1 << PTE_PBMT_SHIFT) +#define SVPBMT_IO ((unsigned long)0x2 << PTE_PBMT_SHIFT) +#define SVPBMT_MASK ((unsigned long)0x3 << PTE_PBMT_SHIFT) + +#endif + +#define DIRTY_FLAG (1 << 6) +#define ACCESS_FLAG (1 << 5) +#define GLOBAL_FLAG (1 << 4) +#define AP_UNPRIV (1 << 3) +#define AP_X (1 << 2) +#define AP_W (1 << 1) +#define AP_R (1 << 0) + +#define LOWER_ATTRS_SHIFT 1 +#define LOWER_ATTRS(x) (((x) & 0x1ff) << LOWER_ATTRS_SHIFT) + + + +#endif /* __RISCV_CSR_H__ */ + diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/drv/dev_tag.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/drv/dev_tag.h new file mode 100644 index 00000000..4e7590c4 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/drv/dev_tag.h @@ -0,0 +1,104 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/dev_tag.h + * @brief Header File for DEV TAG Driver + * @version V1.0 + * @date 31. March 2020 + * @model common + ******************************************************************************/ + +#ifndef _DRV_DEV_TAG_H_ +#define _DRV_DEV_TAG_H_ + +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + DEV_BLANK_TAG = 0U, + DEV_DW_UART_TAG, + DEV_DW_AHB_DMA_TAG, + DEV_DW_AXI_DMA_TAG, + DEV_DW_GPIO_TAG, + DEV_DW_IIC_TAG, + DEV_DW_QSPI_TAG, + DEV_DW_SDMMC_TAG, + DEV_DW_SDHCI_TAG, + DEV_DW_SPI_TAG, + DEV_DW_TIMER_TAG, + DEV_DW_WDT_TAG, + DEV_WJ_ADC_TAG, + DEV_WJ_AES_TAG, + DEV_WJ_CODEC_TAG, + DEV_WJ_CRC_TAG, + DEV_WJ_DMA_TAG, + DEV_WJ_EFLASH_TAG, + DEV_WJ_EFUSE_TAG, + DEV_WJ_ETB_TAG, + DEV_WJ_FFT_TAG, + DEV_WJ_I2S_TAG, + DEV_WJ_MBOX_TAG, + DEV_WJ_PADREG_TAG, + DEV_WJ_PDM_TAG, + DEV_WJ_PINMUX_TAG, + DEV_WJ_PMU_TAG, + DEV_WJ_PWM_TAG, + DEV_WJ_RNG_TAG, + DEV_WJ_ROM_TAG, + DEV_WJ_RSA_TAG, + DEV_WJ_RTC_TAG, + DEV_WJ_SASC_TAG, + DEV_WJ_SHA_TAG, + DEV_WJ_SPDIF_TAG, + DEV_WJ_SPIDF_TAG, + DEV_WJ_TDM_TAG, + DEV_WJ_TIPC_TAG, + DEV_WJ_USB_TAG, + DEV_WJ_USI_TAG, + DEV_WJ_VAD_TAG, + DEV_CD_QSPI_TAG, + DEV_DCD_ISO7816_TAG, + DEV_OSR_RNG_TAG, + DEV_QX_RTC_TAG, + DEV_RCHBAND_CODEC_TAG, + DEV_CMSDK_UART_TAG, + DEV_RAMBUS_150B_PKA_TAG, + DEV_RAMBUS_150B_TRNG_TAG, + DEV_RAMBUS_120SI_TAG, + DEV_RAMBUS_120SII_TAG, + DEV_RAMBUS_120SIII_TAG, + DEV_WJ_AVFS_TAG, + DEV_WJ_BMU_TAG, + DEV_XT_IOPMP_TAG, +} csi_dev_tag_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_TAG_H_ */ + diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/dw_timer_ll.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/dw_timer_ll.h new file mode 100644 index 00000000..cb7bf108 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/dw_timer_ll.h @@ -0,0 +1,167 @@ +/* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + */ + +/******************************************************* + * @file dw_timer_ll.h + * @brief header file for timer ll driver + * @version V1.0 + * @date 9. April 2020 + * ******************************************************/ + +#ifndef _DW_TIMER_LL_H_ +#define _DW_TIMER_LL_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*! Timer1 Control Reg, offset: 0x08 */ +#define DW_TIMER_CTL_ENABLE_SEL_Pos (0U) +#define DW_TIMER_CTL_ENABLE_SEL_Msk (0x1U << DW_TIMER_CTL_ENABLE_SEL_Pos) +#define DW_TIMER_CTL_ENABLE_SEL_EN DW_TIMER_CTL_ENABLE_SEL_Msk + +#define DW_TIMER_CTL_MODE_SEL_Pos (1U) +#define DW_TIMER_CTL_MODE_SEL_Msk (0x1U << DW_TIMER_CTL_MODE_SEL_Pos) +#define DW_TIMER_CTL_MODE_SEL_EN DW_TIMER_CTL_MODE_SEL_Msk + +#define DW_TIMER_CTL_INT_MASK_Pos (2U) +#define DW_TIMER_CTL_INT_MASK_Msk (0x1U << DW_TIMER_CTL_INT_MASK_Pos) +#define DW_TIMER_CTL_INT_MAKS_EN DW_TIMER_CTL_INT_MASK_Msk + +#define DW_TIMER_CTL_HARD_TRIG_Pos (4U) +#define DW_TIMER_CTL_HARD_TRIG_Msk (0x1U << DW_TIMER_CTL_HARD_TRIG_Pos) +#define DW_TIMER_CTL_HARD_TRIG_EN DW_TIMER_CTL_HARD_TRIG_Msk + +/*! Timer EOI, offset: 0x0c */ +#define DW_TIMER_EOI_REG_Pos (0U) +#define DW_TIMER_EOI_REG_Msk (0x1U << DW_TIMER_EOI_REG_Pos) +#define DW_TIMER_EOI_REG_EN DW_TIMER_EOI_REG_Msk + +/*! Timer Int Status, offset: 0x10 */ +#define DW_TIMER_INT_STATUS_Pos (0U) +#define DW_TIMER_INT_STATUS_Msk (0x1U << DW_TIMER_INT_STATUS_Pos) +#define DW_TIMER_INT_STATUS_EN DW_TIMER_INT_STATUS_Msk + +/*! Timers Int Status, offset: 0xa0 */ +#define DW_TIMERS_INT_STATUS_Pos (0U) +#define DW_TIMERS_INT_STATUS_Msk (0x2U << DW_TIMERS_INT_STATUS_Pos) +#define DW_TIMERS_INT_STATUS_EN DW_TIMERS_INT_STATUS_Msk + +/*! Timers EOI, offset: 0xa4 */ +#define DW_TIMERS_EOI_REG_Pos (0U) +#define DW_TIMERS_EOI_REG_Msk (0x2U << DW_TIMERS_EOI_REG_Pos) +#define DW_TIMERS_EOI_REG_EN DW_TIMERS_EOI_REG_Msk + +/*! Timers Raw Int Status,offset: 0xa8 */ +#define DW_TIMERS_RAW_INT_STA_Pos (0U) +#define DW_TIMERS_RAW_INT_STA_Msk (0x2U << DW_TIMERS_RAW_INT_STA_Pos) +#define DW_TIMERS_RAW_INT_STA_EN DW_TIMERS_RAW_INT_STA_Msk + +typedef struct { + __IOM uint32_t TLC; /* Offset: 0x000 (R/W) TimerLoadCount */ + __IM uint32_t TCV; /* Offset: 0x004 (R/ ) TimerCurrentValue */ + __IOM uint32_t TCR; /* Offset: 0x008 (R/W) TimerControlReg */ + __IM uint32_t TEOI; /* Offset: 0x00c (R/ ) TimerEOI */ + __IM uint32_t TIS; /* Offset: 0x010 (R/ ) TimerIntStatus */ +} dw_timer_regs_t; + +typedef struct { + dw_timer_regs_t timer[8]; + __IM uint32_t TSIS; /* Offset: 0x0a0 (R/ ) TimersIntStatus */ + __IM uint32_t TSEOI; /* Offset: 0x0a4 (R/ ) TimersEOI */ + __IM uint32_t TSRIS; /* Offset: 0x0a8 (R/ ) TimersRawIntStatus */ +} dw_timer_general_regs_t; + +static inline uint32_t dw_timer_read_load(dw_timer_regs_t *timer_base) +{ + return (timer_base->TLC); +} +static inline void dw_timer_write_load(dw_timer_regs_t *timer_base, uint32_t value) +{ + timer_base->TLC = value; +} +static inline uint32_t dw_timer_get_current(dw_timer_regs_t *timer_base) +{ + return (timer_base->TCV); +} +static inline void dw_timer_set_enable(dw_timer_regs_t *timer_base) +{ + timer_base->TCR |= (DW_TIMER_CTL_ENABLE_SEL_EN); +} +static inline void dw_timer_set_disable(dw_timer_regs_t *timer_base) +{ + timer_base->TCR &= ~(DW_TIMER_CTL_ENABLE_SEL_EN); +} +static inline uint32_t dw_timer_get_enable(dw_timer_regs_t *timer_base) +{ + return (((timer_base->TCR) & DW_TIMER_CTL_ENABLE_SEL_EN) ? (uint32_t)1 : (uint32_t)0); +} +static inline void dw_timer_set_mode_free(dw_timer_regs_t *timer_base) +{ + timer_base->TCR &= ~(DW_TIMER_CTL_MODE_SEL_EN); +} +static inline void dw_timer_set_mode_load(dw_timer_regs_t *timer_base) +{ + timer_base->TCR |= (DW_TIMER_CTL_MODE_SEL_EN); +} +static inline uint32_t dw_timer_get_model(dw_timer_regs_t *timer_base) +{ + return (((timer_base->TCR) & DW_TIMER_CTL_MODE_SEL_EN) ? (uint32_t)1 : (uint32_t)0); +} +static inline void dw_timer_set_mask(dw_timer_regs_t *timer_base) +{ + timer_base->TCR |= (DW_TIMER_CTL_INT_MAKS_EN); +} +static inline void dw_timer_set_unmask(dw_timer_regs_t *timer_base) +{ + timer_base->TCR &= ~(DW_TIMER_CTL_INT_MAKS_EN); +} +static inline uint32_t dw_timer_get_mask(dw_timer_regs_t *timer_base) +{ + return (((timer_base->TCR) & DW_TIMER_CTL_INT_MAKS_EN) ? (uint32_t)1 : (uint32_t)0); +} +static inline void dw_timer_set_hardtrigger_en(dw_timer_regs_t *timer_base) +{ + timer_base->TCR |= (DW_TIMER_CTL_HARD_TRIG_EN); +} +static inline void dw_timer_set_hardtrigger_dis(dw_timer_regs_t *timer_base) +{ + timer_base->TCR &= ~(DW_TIMER_CTL_HARD_TRIG_EN); +} +static inline uint32_t dw_timer_get_hardtrigger(dw_timer_regs_t *timer_base) +{ + return (((timer_base->TCR) & DW_TIMER_CTL_HARD_TRIG_EN) ? (uint32_t)1 : (uint32_t)0); +} +static inline uint32_t dw_timer_clear_irq(dw_timer_regs_t *timer_base) +{ + return (((timer_base->TEOI) & DW_TIMER_EOI_REG_EN) ? (uint32_t)1 : (uint32_t)0); +} +static inline uint32_t dw_timer_get_int_status(dw_timer_regs_t *timer_base) +{ + return (((timer_base->TIS) & DW_TIMER_INT_STATUS_EN) ? (uint32_t)1 : (uint32_t)0); +} +static inline uint32_t dw_timer_general_active_after_mask(dw_timer_general_regs_t *timer_base) +{ + return ((timer_base->TSIS) & DW_TIMERS_INT_STATUS_EN); +} +static inline uint32_t dw_timer_general_clear_irq(dw_timer_general_regs_t *timer_base) +{ + return ((timer_base->TSEOI) & DW_TIMERS_EOI_REG_EN); +} +static inline uint32_t dw_timer_general_active_prior_mask(dw_timer_general_regs_t *timer_base) +{ + return ((timer_base->TSRIS) & DW_TIMERS_RAW_INT_STA_EN); +} + + +#ifdef __cplusplus +} +#endif + +#endif /* _DW_TIMER_LL_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/dw_uart.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/dw_uart.h new file mode 100644 index 00000000..e69de29b diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/dw_uart_ll.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/dw_uart_ll.h new file mode 100644 index 00000000..50a7de0b --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/dw_uart_ll.h @@ -0,0 +1,423 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file dw_uart_ll.h + * @brief header file for uart ll driver + * @version V1.0 + * @date 18. December 2024 + ******************************************************************************/ + +#ifndef _DW_UART_LL_H_ +#define _DW_UART_LL_H_ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! IER, offset: 0x4 */ +#define DW_UART_IER_ERBFI_Pos (0U) +#define DW_UART_IER_ERBFI_Msk (0x1U << DW_UART_IER_ERBFI_Pos) +#define DW_UART_IER_ERBFI_EN DW_UART_IER_ERBFI_Msk + +#define DW_UART_IER_ETBEI_Pos (1U) +#define DW_UART_IER_ETBEI_Msk (0x1U << DW_UART_IER_ETBEI_Pos) +#define DW_UART_IER_ETBEI_EN DW_UART_IER_ETBEI_Msk + +#define DW_UART_IER_ELSI_Pos (2U) +#define DW_UART_IER_ELSI_Msk (0x1U << DW_UART_IER_ELSI_Pos) +#define DW_UART_IER_ELSI_EN DW_UART_IER_ELSI_Msk + +#define DW_UART_IER_EDSSI_Pos (3U) +#define DW_UART_IER_EDSSI_Msk (0x1U << DW_UART_IER_EDSSI_Pos) +#define DW_UART_IER_EDSSI_EN DW_UART_IER_EDSSI_Msk + +/*! IIR, offset: 0x8 */ +#define DW_UART_IIR_IID_Pos (0U) +#define DW_UART_IIR_IID_Msk (0xFU << DW_UART_IIR_IID_Pos) +#define DW_UART_IIR_IID_MODEM_STATUS (0x0U) +#define DW_UART_IIR_IID_NO_INTERRUPT (0x1U) +#define DW_UART_IIR_IID_THR_EMPTY (0x2U) +#define DW_UART_IIR_IID_RECV_DATA_AVAIL (0x4U) +#define DW_UART_IIR_IID_RECV_LINE_STATUS (0x6U) +#define DW_UART_IIR_IID_BUSY_DETECT (0x7U) +#define DW_UART_IIR_IID_CHARACTER_TIMEOUT (0xCU) + +#define DW_UART_IIR_FIFOSE_Pos (6U) +#define DW_UART_IIR_FIFOSE_Msk (0x3U << DW_UART_IIR_FIFOSE_Pos) +#define DW_UART_IIR_FIFOSE_EN DW_UART_IIR_FIFOSE_Msk + +/*! FCR, offset: 0x8 */ +#define DW_UART_FCR_FIFOE_Pos (0U) +#define DW_UART_FCR_FIFOE_Msk (0x1U << DW_UART_FCR_FIFOE_Pos) +#define DW_UART_FCR_FIFOE_EN DW_UART_FCR_FIFOE_Msk + +#define DW_UART_FCR_RFIFOR_Pos (1U) +#define DW_UART_FCR_RFIFOR_Msk (0x1U << DW_UART_FCR_RFIFOR_Pos) +#define DW_UART_FCR_RFIFOR_RESET DW_UART_FCR_RFIFOR_Msk + +#define DW_UART_FCR_XFIFOR_Pos (2U) +#define DW_UART_FCR_XFIFOR_Msk (0x1U << DW_UART_FCR_XFIFOR_Pos) +#define DW_UART_FCR_XFIFOR_RESET DW_UART_FCR_XFIFOR_Msk + +#define DW_UART_FCR_TET_Pos (4U) +#define DW_UART_FCR_TET_Msk (0x3U << DW_UART_FCR_TET_Pos) +#define DW_UART_FCR_TET_FIFO_EMTPY (0x0U) +#define DW_UART_FCR_TET_FIFO_2_CHAR (0x1U << DW_UART_FCR_TET_Pos) +#define DW_UART_FCR_TET_FIFO_1_4_FULL (0x2U << DW_UART_FCR_TET_Pos) +#define DW_UART_FCR_TET_FIFO_1_2_FULL (0x3U << DW_UART_FCR_TET_Pos) + +#define DW_UART_FCR_RT_Pos (6U) +#define DW_UART_FCR_RT_Msk (0x3U << DW_UART_FCR_RT_Pos) +#define DW_UART_FCR_RT_FIFO_1_CHAR (0x0U) +#define DW_UART_FCR_RT_FIFO_1_4_FULL (0x1U << DW_UART_FCR_RT_Pos) +#define DW_UART_FCR_RT_FIFO_1_2_FULL (0x2U << DW_UART_FCR_RT_Pos) +#define DW_UART_FCR_RT_FIFO_2_LESS_FULL (0x3U << DW_UART_FCR_RT_Pos) + +/*! LCR, offset: 0xC */ +#define DW_UART_LCR_DLS_Pos (0U) +#define DW_UART_LCR_DLS_Msk (0x3U << DW_UART_LCR_DLS_Pos) +#define DW_UART_LCR_DLS_5_BITS (0x0U) +#define DW_UART_LCR_DLS_6_BITS (0x1U << DW_UART_LCR_DLS_Pos) +#define DW_UART_LCR_DLS_7_BITS (0x2U << DW_UART_LCR_DLS_Pos) +#define DW_UART_LCR_DLS_8_BITS (0x3U << DW_UART_LCR_DLS_Pos) + +#define DW_UART_LCR_STOP_Pos (2U) +#define DW_UART_LCR_STOP_Msk (0x1U << DW_UART_LCR_STOP_Pos) +#define DW_UART_LCR_STOP_1_BIT (0x0U) +#define DW_UART_LCR_STOP_2_BIT (0x1U << DW_UART_LCR_STOP_Pos) + +#define DW_UART_LCR_PEN_Pos (3U) +#define DW_UART_LCR_PEN_Msk (0x1U << DW_UART_LCR_PEN_Pos) +#define DW_UART_LCR_PEN_EN DW_UART_LCR_PEN_Msk + +#define DW_UART_LCR_EPS_Pos (4U) +#define DW_UART_LCR_EPS_Msk (0x1U << DW_UART_LCR_EPS_Pos) +#define DW_UART_LCR_EPS_EN DW_UART_LCR_EPS_Msk + +#define DW_UART_LCR_BC_Pos (6U) +#define DW_UART_LCR_BC_Msk (0x1U << DW_UART_LCR_BC_Pos) +#define DW_UART_LCR_BC_EN DW_UART_LCR_BC_Msk + +#define DW_UART_LCR_DLAB_Pos (7U) +#define DW_UART_LCR_DLAB_Msk (0x1U << DW_UART_LCR_DLAB_Pos) +#define DW_UART_LCR_DLAB_EN DW_UART_LCR_DLAB_Msk + +/*! MCR, offset: 0x10 */ +#define DW_UART_MCR_RTS_Pos (1U) +#define DW_UART_MCR_RTS_Msk (0x1U << DW_UART_MCR_RTS_Pos) +#define DW_UART_MCR_RTS_EN DW_UART_MCR_RTS_Msk + +#define DW_UART_MCR_LB_Pos (4U) +#define DW_UART_MCR_LB_Msk (0x1U << DW_UART_MCR_LB_Pos) +#define DW_UART_MCR_LB_EN DW_UART_MCR_LB_Msk + +#define DW_UART_MCR_AFCE_Pos (5U) +#define DW_UART_MCR_AFCE_Msk (0x1U << DW_UART_MCR_AFCE_Pos) +#define DW_UART_MCR_AFCE_EN DW_UART_MCR_AFCE_Msk + +/*! LSR, offset: 0x14 */ +#define DW_UART_LSR_DR_Pos (0U) +#define DW_UART_LSR_DR_Msk (0x1U << DW_UART_LSR_DR_Pos) +#define DW_UART_LSR_DR_READY DW_UART_LSR_DR_Msk + +#define DW_UART_LSR_OE_Pos (1U) +#define DW_UART_LSR_OE_Msk (0x1U << DW_UART_LSR_OE_Pos) +#define DW_UART_LSR_OE_ERROR DW_UART_LSR_OE_Msk + +#define DW_UART_LSR_PE_Pos (2U) +#define DW_UART_LSR_PE_Msk (0x1U << DW_UART_LSR_PE_Pos) +#define DW_UART_LSR_PE_ERROR DW_UART_LSR_PE_Msk + +#define DW_UART_LSR_FE_Pos (3U) +#define DW_UART_LSR_FE_Msk (0x1U << DW_UART_LSR_FE_Pos) +#define DW_UART_LSR_FE_ERROR DW_UART_LSR_FE_Msk + +#define DW_UART_LSR_BI_Pos (4U) +#define DW_UART_LSR_BI_Msk (0x1U << DW_UART_LSR_BI_Pos) +#define DW_UART_LSR_BI_SET DW_UART_LSR_BI_Msk + +#define DW_UART_LSR_THRE_Pos (5U) +#define DW_UART_LSR_THRE_Msk (0x1U << DW_UART_LSR_THRE_Pos) +#define DW_UART_LSR_THRE_SET DW_UART_LSR_THRE_Msk + +#define DW_UART_LSR_TEMT_Pos (6U) +#define DW_UART_LSR_TEMT_Msk (0x1U << DW_UART_LSR_TEMT_Pos) +#define DW_UART_LSR_TEMT_SET DW_UART_LSR_TEMT_Msk + +#define DW_UART_LSR_RFE_Pos (7U) +#define DW_UART_LSR_RFE_Msk (0x1U << DW_UART_LSR_RFE_Pos) +#define DW_UART_LSR_RFE_ERROR DW_UART_LSR_RFE_Msk + +/*! MSR, offset: 0x18 */ +#define DW_UART_MSR_DCTS_Pos (0U) +#define DW_UART_MSR_DCTS_Msk (0x1U << DW_UART_MSR_DCTS_Pos) +#define DW_UART_MSR_DCTS_CHANGE DW_UART_MSR_DCTS_Msk + +#define DW_UART_MSR_DDSR_Pos (1U) +#define DW_UART_MSR_DDSR_Msk (0x1U << DW_UART_MSR_DDSR_Pos) +#define DW_UART_MSR_DDSR_CHANGE DW_UART_MSR_DDSR_Msk + +#define DW_UART_MSR_TERI_Pos (2U) +#define DW_UART_MSR_TERI_Msk (0x1U << DW_UART_MSR_TERI_Pos) +#define DW_UART_MSR_TERI_CHANGE DW_UART_MSR_TERI_Msk + +#define DW_UART_MSR_DDCD_Pos (3U) +#define DW_UART_MSR_DDCD_Msk (0x1U << DW_UART_MSR_DDCD_Pos) +#define DW_UART_MSR_DDCD_CHANGE DW_UART_MSR_DDCD_Msk + +#define DW_UART_MSR_CTS_Pos (4U) +#define DW_UART_MSR_CTS_Msk (0x1U << DW_UART_MSR_CTS_Pos) +#define DW_UART_MSR_CTS_ASSERTED DW_UART_MSR_CTS_Msk + +#define DW_UART_MSR_DSR_Pos (5U) +#define DW_UART_MSR_DSR_Msk (0x1U << DW_UART_MSR_DSR_Pos) +#define DW_UART_MSR_DSR_ASSERTED DW_UART_MSR_DSR_Msk + +#define DW_UART_MSR_RI_Pos (6U) +#define DW_UART_MSR_RI_Msk (0x1U << DW_UART_MSR_RI_Pos) +#define DW_UART_MSR_RI_ASSERTED DW_UART_MSR_RI_Msk + +#define DW_UART_MSR_DCD_Pos (7U) +#define DW_UART_MSR_DCD_Msk (0x1U << DW_UART_MSR_DCD_Pos) +#define DW_UART_MSR_DCD_ASSERTED DW_UART_MSR_DCD_Msk + +/*! SCR, offset: 0x1C */ +#define DW_UART_SCR_SCRATCHPAD_Pos (0U) +#define DW_UART_SCR_SCRATCHPAD_Msk (0xFFU << DW_UART_SCR_SCRATCHPAD_Pos) + +/*! USR, offset: 0x7C */ +#define DW_UART_USR_BUSY_Pos (0U) +#define DW_UART_USR_BUSY_Msk (0x1U << DW_UART_USR_BUSY_Pos) +#define DW_UART_USR_BUSY_SET DW_UART_USR_BUSY_Msk + +#define DW_UART_USR_TFNF_Pos (1U) +#define DW_UART_USR_TFNF_Msk (0x1U << DW_UART_USR_TFNF_Pos) +#define DW_UART_USR_TFNF_SET DW_UART_USR_TFNF_Msk + +#define DW_UART_USR_TFE_Pos (2U) +#define DW_UART_USR_TFE_Msk (0x1U << DW_UART_USR_TFE_Pos) +#define DW_UART_USR_TFE_SET DW_UART_USR_TFE_Msk + +#define DW_UART_USR_RFNE_Pos (3U) +#define DW_UART_USR_RFNE_Msk (0x1U << DW_UART_USR_RFNE_Pos) +#define DW_UART_USR_RFNE_SET DW_UART_USR_RFNE_Msk + +#define DW_UART_USR_RFF_Pos (4U) +#define DW_UART_USR_RFF_Msk (0x1U << DW_UART_USR_RFF_Pos) +#define DW_UART_USR_RFF_SET DW_UART_USR_RFF_Msk + +/*! TFL, offset: 0x80 */ +#define DW_UART_TFL_TFIFOL_Pos (0U) +#define DW_UART_TFL_TFIFOL_Msk (0x1FU << DW_UART_TFL_TFIFOL_Pos) +#define DW_UART_TFL_TFIFOL(n) (nU << DW_UART_TFL_TFIFOL_Pos) + +/*! RFL, offset: 0x84 */ +#define DW_UART_RFL_RFIFOL_Pos (0U) +#define DW_UART_RFL_RFIFOL_Msk (0x1FU << DW_UART_RFL_RFIFOL_Pos) +#define DW_UART_RFL_RFIFOL(n) (nU << DW_UART_TFL_TFIFOL_Pos) + +/*! HTX, offset: 0xA4 */ +#define DW_UART_HTX_HALTTX_Pos (0U) +#define DW_UART_HTX_HALTTX_Msk (0x1U << DW_UART_HTX_HALTTX_Pos) +#define DW_UART_HTX_HALTTX_EN DW_UART_HTX_HALTTX_Msk + +#define DW_UART_HTX_RX_ETB_FUNC_Pos (6U) +#define DW_UART_HTX_RX_ETB_FUNC_Msk (0x1U << DW_UART_HTX_RX_ETB_FUNC_Pos) +#define DW_UART_HTX_RX_ETB_FUNC_EN DW_UART_HTX_RX_ETB_FUNC_Msk + +#define DW_UART_HTX_TX_ETB_FUNC_Pos (7U) +#define DW_UART_HTX_TX_ETB_FUNC_Msk (0x1U << DW_UART_HTX_TX_ETB_FUNC_Pos) +#define DW_UART_HTX_TX_ETB_FUNC_EN DW_UART_HTX_TX_ETB_FUNC_Msk + +/*! DMASA, offset: 0xA8 */ +#define DW_UART_DMASA_DMASACK_Pos (0U) +#define DW_UART_DMASA_DMASACK_Msk (0x1U << DW_UART_DMASA_DMASACK_Pos) +#define DW_UART_DMASA_DMASACK_SET DW_UART_DMASA_DMASACK_Msk + +/* FIFO CONFIG */ +#define UART_FIFO_INIT_CONFIG (DW_UART_FCR_FIFOE_EN | DW_UART_FCR_RT_FIFO_1_2_FULL|DW_UART_FCR_RFIFOR_RESET|DW_UART_FCR_XFIFOR_RESET) + +/*! UART_RATE, offset: 0x3FC */ +#define DW_UART_SUPPORT_RATE 0x10102U + +#define UART_BUSY_TIMEOUT 0x70000000U + +typedef struct { + union { + __IM uint32_t RBR; /* Offset: 0x000 (R/ ) Receive buffer register */ + __OM uint32_t THR; /* Offset: 0x000 ( /W) Transmission hold register */ + __IOM uint32_t DLL; /* Offset: 0x000 (R/W) Clock frequency division low section register */ + }; + union { + __IOM uint32_t DLH; /* Offset: 0x004 (R/W) Clock frequency division high section register */ + __IOM uint32_t IER; /* Offset: 0x004 (R/W) Interrupt enable register */ + }; + union { + __IM uint32_t IIR; /* Offset: 0x008 (R/ ) Interrupt identification register */ + __OM uint32_t FCR; /* Offset: 0x008 ( /W) FIFO control register */ + }; + __IOM uint32_t LCR; /* Offset: 0x00C (R/W) Line control register */ + __IOM uint32_t MCR; /* Offset: 0x010 (R/W) Modem control register */ + __IM uint32_t LSR; /* Offset: 0x014 (R/ ) Line state register */ + __IM uint32_t MSR; /* Offset: 0x018 (R/ ) Modem state register */ + uint32_t RESERVED1[21]; + __IM uint32_t USR; /* Offset: 0x07c (R/ ) UART state register */ +} dw_uart_regs_t; + +static inline void dw_uart_enable_recv_irq(dw_uart_regs_t *uart_base) +{ + uart_base->IER |= (DW_UART_IER_ERBFI_EN | DW_UART_IER_ELSI_EN); +} + +static inline void dw_uart_disable_recv_irq(dw_uart_regs_t *uart_base) +{ + uart_base->IER &= ~(DW_UART_IER_ERBFI_EN | DW_UART_IER_ELSI_EN); +} + +static inline void dw_uart_enable_trans_irq(dw_uart_regs_t *uart_base) +{ + uart_base->IER |= DW_UART_IER_ETBEI_EN; +} + +static inline void dw_uart_disable_trans_irq(dw_uart_regs_t *uart_base) +{ + uart_base->IER &= ~(DW_UART_IER_ETBEI_EN); +} + +static inline void dw_uart_fifo_init(dw_uart_regs_t *uart_base) +{ + /* FIFO enable */ + uart_base->FCR = UART_FIFO_INIT_CONFIG; +} + +static inline void dw_uart_fifo_enable(dw_uart_regs_t *uart_base) +{ + uart_base->FCR |= DW_UART_FCR_FIFOE_EN; +} + +static inline void dw_uart_fifo_disable(dw_uart_regs_t *uart_base) +{ + uart_base->FCR &= ~(DW_UART_FCR_FIFOE_EN); +} + +static inline uint32_t dw_uart_putready(dw_uart_regs_t *uart_base) +{ + uint32_t status = 0U, ret = 0U; + + status = uart_base->LSR & DW_UART_LSR_THRE_SET; + + if (status != 0U) { + ret = 1U; + } + + return ret; +} + +static inline uint32_t dw_uart_getready(dw_uart_regs_t *uart_base) +{ + uint32_t status = 0U, ret = 0U; + + status = uart_base->LSR & DW_UART_LSR_DR_READY; + + if (status != 0U) { + ret = 1U; + } + + return ret; +} + +static inline uint32_t dw_uart_get_line_status(dw_uart_regs_t *uart_base) +{ + return uart_base->LSR; +} + +static inline void dw_uart_config_stop_bits_1(dw_uart_regs_t *uart_base) +{ + uart_base->LCR &= ~(DW_UART_LCR_STOP_Msk); +} + +static inline void dw_uart_config_stop_bits_2(dw_uart_regs_t *uart_base) +{ + uart_base->LCR |= DW_UART_LCR_STOP_2_BIT; +} + +static inline void dw_uart_putchar(dw_uart_regs_t *uart_base, uint8_t ch) +{ + uart_base->THR = ch; +} + +static inline uint8_t dw_uart_getchar(dw_uart_regs_t *uart_base) +{ + return (uint8_t)(uart_base->RBR); +} + +static inline uint32_t dw_uart_get_intr_en_status(dw_uart_regs_t *uart_base) +{ + return uart_base->IER; +} + +static inline void dw_uart_set_intr_en_status(dw_uart_regs_t *uart_base, uint32_t status) +{ + uart_base->IER = status; +} + +static inline void dw_uart_set_fcr_reg(dw_uart_regs_t *uart_base, uint32_t value) +{ + uart_base->FCR = value; +} + +static inline void dw_uart_enable_auto_flow_control(dw_uart_regs_t *uart_base) +{ + uart_base->MCR |= DW_UART_MCR_AFCE_EN; + uart_base->MCR |= DW_UART_MCR_RTS_EN; +} + +static inline void dw_uart_disable_auto_flow_control(dw_uart_regs_t *uart_base) +{ + uart_base->MCR &= ~DW_UART_MCR_AFCE_EN; + uart_base->MCR &= ~DW_UART_MCR_RTS_EN; +} + +int32_t dw_uart_wait_timeout(dw_uart_regs_t *uart_base); + +int32_t dw_uart_wait_idle(dw_uart_regs_t *uart_base); + +int32_t dw_uart_config_baudrate(dw_uart_regs_t *uart_base, uint32_t baud, uint32_t uart_freq); + +int32_t dw_uart_config_stop_bits(dw_uart_regs_t *uart_base, uint32_t stop_bits); + +int32_t dw_uart_config_parity_none(dw_uart_regs_t *uart_base); + +int32_t dw_uart_config_parity_odd(dw_uart_regs_t *uart_base); + +int32_t dw_uart_config_parity_even(dw_uart_regs_t *uart_base); + +int32_t dw_uart_config_data_bits(dw_uart_regs_t *uart_base, uint32_t data_bits); + +#ifdef __cplusplus +} +#endif + +#endif /* _DW_UART_LL_H_ */ + diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/soc.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/soc.h new file mode 100644 index 00000000..e77cb305 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/soc.h @@ -0,0 +1,409 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _SOC_H_ +#define _SOC_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef EHS_VALUE +#define EHS_VALUE 20000000U +#endif + +#ifndef ELS_VALUE +#define ELS_VALUE 32768U +#endif + +#ifndef IHS_VALUE +#define IHS_VALUE 20000000U +#endif + +#ifndef ILS_VALUE +#define ILS_VALUE 32768U +#endif + +#if __riscv_xlen == 32 +#define INVALID_ADDRESS 0xFFFFFFFFU +#elif __riscv_xlen == 64 +#define INVALID_ADDRESS 0xFFFFFFFFFFFFFFFFULL +#else +#error "Unsupported RISC-V XLEN." +#endif + +typedef enum { + DW_UART0_RX_DMAN = 0U, + DW_UART0_TX_DMAN = 1U, + DW_UART1_RX_DMAN = 2U, + DW_UART1_TX_DMAN = 3U, + MEMORY_DMAN = 4U, +} dman_type_t; + +typedef enum { + PA0 = 0U, + PA1, + PA2, + PA3, + PA4, + PA5, + PA6, + PA7, + PA8, + PA9, + PA10, + PA11, + PA12, + PA13, + PA14, + PA15, + PA16, + PA17, + PA18, + PA19, + PA20, + PA21, + PA22, + PA23, + PA24, + PA25, + PA26, + PA27, + PA28, + PA29, + PA30, + PA31, + PIN_END = 0xFFFFFFFFU +} pin_name_t; + + +typedef enum { + PA0_I2S0_SCLK = 0U, + PA0_SPI0_CS = 1U, + PA0_UART0_RX = 2U, + PA0_PWM_CH0 = 3U, + PA1_I2S0_WSCLK = 0U, + PA1_SPI0_SCK = 1U, + PA1_UART0_TX = 2U, + PA1_PWM_CH1 = 3U, + PA2_I2S1_SCLK = 0U, + PA2_IIC0_SCL = 1U, + PA2_SPI1_CS = 2U, + PA2_PWM_CH2 = 3U, + PA2_ADC_A0 = 7U, + PA3_I2S1_WSCLK = 0U, + PA3_IIC0_SDA = 1U, + PA3_SPI1_SCK = 2U, + PA3_PWM_CH3 = 3U, + PA3_ADC_A1 = 8U, + PA4_I2S0_SDA = 0U, + PA4_SPI0_MOSI = 1U, + PA4_UART1_CTS = 2U, + PA4_PWM_CH4 = 3U, + PA4_ADC_A2 = 9U, + PA5_I2S1_SDA = 0U, + PA5_SPI0_MISO = 1U, + PA5_UART1_RTS = 2U, + PA5_PWM_CH5 = 3U, + PA5_ADC_A3 = 10U, + PA6_I2S0_SCLK = 0U, + PA6_UART0_TX = 1U, + PA6_SPI1_MOSI = 2U, + PA6_PWM_CH6 = 3U, + PA6_ADC_A4 = 11U, + PA7_I2S0_WSCLK = 0U, + PA7_PWMR_OUT = 1U, + PA7_SPI1_MISO = 2U, + PA7_PWM_CH7 = 3U, + PA7_ADC_A5 = 12U, + PA8_I2S0_SDA = 0U, + PA8_IIC0_SCL = 1U, + PA8_UART0_RX = 2U, + PA8_PWM_CH8 = 3U, + PA8_ADC_A6 = 13U, + PA9_I2S1_SDA = 0U, + PA9_IIC0_SDA = 1U, + PA9_PWMR_OUT = 2U, + PA9_PWM_CH9 = 3U, + PA9_ADC_A7 = 14U, + PA10_I2S0_MCLK = 0U, + PA10_UART0_TX = 1U, + PA10_SPI1_MOSI = 2U, + PA10_SPI1_MISO = 3U, + PA10_ADC_A8 = 15U, + PA15_IIC0_SCL = 0U, + PA15_SPI0_CS = 1U, + PA15_PWMR_OUT = 2U, + PA15_PWM_CH4 = 3U, + PA15_ADC_A9 = 20U, + PA16_IIC0_SDA = 0U, + PA16_SPI0_SCK = 1U, + PA16_UART1_TX = 2U, + PA16_PWM_CH5 = 3U, + PA16_ADC_A10 = 21U, + PA17_UART0_RX = 0U, + PA17_SPI0_MOSI = 1U, + PA17_I2S0_SCLK = 2U, + PA17_PWM_CH10 = 3U, + PA17_ADC_A11 = 22U, + PA18_UART0_TX = 0U, + PA18_SPI0_MISO = 1U, + PA18_I2S0_WSCLK = 2U, + PA18_PWM_CH11 = 3U, + PA18_ADC_A12 = 23U, + PA19_JTAG_TMS = 0U, + PA19_UART1_RX = 1U, + PA19_I2S1_SCLK = 2U, + PA19_IIC0_SCL = 3U, + PA19_ADC_A13 = 24U, + PA20_JTAG_TCK = 0U, + PA20_UART1_TX = 1U, + PA20_I2S1_WSCLK = 2U, + PA20_IIC0_SDA = 3U, + PA20_ADC_A14 = 25U, + PA21_UART0_CTS = 0U, + PA21_UART1_CTS = 1U, + PA21_I2S0_SDA = 2U, + PA21_IIC0_SCL = 3U, + PA21_ADC_A15 = 26U, + PA22_UART0_RTS = 0U, + PA22_UART1_RTS = 1U, + PA22_I2S1_SDA = 2U, + PA22_IIC0_SDA = 3U, + PA23_IIC0_SCL = 0U, + PA23_UART0_TX = 1U, + PA23_PWM_CH0 = 2U, + PA23_SPI0_CS = 3U, + PA24_IIC0_SDA = 0U, + PA24_UART0_RX = 1U, + PA24_PWM_CH1 = 2U, + PA24_SPI0_SCK = 3U, + PA25_PWMR_OUT = 0U, + PA25_UART0_CTS = 1U, + PA25_PWM_CH2 = 2U, + PA25_SPI0_MOSI = 3U, + PA26_I2S1_MCLK = 0U, + PA26_UART0_RTS = 1U, + PA26_PWM_CH3 = 2U, + PA26_SPI0_MISO = 3U, + PA27_I2S0_SCLK = 0U, + PA27_UART1_RX = 1U, + PA27_PWM_CH4 = 2U, + PA27_SPI1_CS = 3U, + PA28_I2S0_WSCLK = 0U, + PA28_UART1_TX = 1U, + PA28_PWM_CH5 = 2U, + PA28_SPI1_SCK = 3U, + PA29_I2S1_SCLK = 0U, + PA29_UART1_CTS = 1U, + PA29_PWM_CH6 = 2U, + PA29_SPI1_MOSI = 3U, + PA30_I2S1_WSCLK = 0U, + PA30_UART1_RTS = 1U, + PA30_PWM_CH7 = 2U, + PA30_SPI1_MISO = 3U, + PA31_I2S0_SDA = 0U, + PA31_PWMR_OUT = 1U, + PA31_PWM_CH8 = 2U, + PA31_UART0_TX = 3U, + PIN_FUNC_GPIO = 4U, + PIN_FUNC_END = 0xFFFFFFFFU +} pin_func_t; + +#define CONFIG_IRQ_NUM 64U +#if CONFIG_INTC_CLIC_PLIC +#undef CONFIG_IRQ_NUM +#define CONFIG_IRQ_NUM (64U + PLIC_IRQ_OFFSET) +#endif + +#if CONFIG_INTC_CLIC_APLIC +#undef CONFIG_IRQ_NUM +#define CONFIG_IRQ_NUM (64U + APLIC_IRQ_OFFSET) +#endif + +#if CONFIG_INTC_IMSIC_APLIC +#undef CONFIG_IRQ_NUM +#define CONFIG_IRQ_NUM (IMSIC_MAX_INTERRUPTS) +#endif + +///< AHB +#define SPIFLASH_BASE 0x18000000UL +#define SPIFLASH_SIZE 0x800000U +#define SRAM_BASE 0x20000000UL +#define SRAM_SIZE 0x20000U + +#if CONFIG_CPU_XUANTIE_E9XX + +typedef enum { + User_Software_IRQn = 0U, /* User software interrupt */ + Supervisor_Software_IRQn = 1U, /* Supervisor software interrupt */ + Machine_Software_IRQn = 3U, /* Machine software interrupt */ + User_Timer_IRQn = 4U, /* User timer interrupt */ + Supervisor_Timer_IRQn = 5U, /* Supervisor timer interrupt */ + CORET_IRQn = 7U, /* Machine timer interrupt */ + Machine_External_IRQn = 11U, /* Machine external interrupt */ + DW_UART0_IRQn = 16U, + TIM0_IRQn = 18U, /* timer0 Interrupt */ + TIM1_IRQn = 19U, /* timer1 Interrupt */ + TIM2_IRQn = 20U, /* timer2 Interrupt */ + TIM3_IRQn = 21U, /* timer3 Interrupt */ +} irqn_type_t; + +#if CONFIG_BOARD_SMARTM_EVB +#define DW_UART0_BASE 0x180000UL +#define DW_TIMER0_BASE 0x181000UL +#define DW_TIMER1_BASE 0x181014UL +#define DW_TIMER2_BASE 0x181028UL +#define DW_TIMER3_BASE 0x18103CUL + +#else + +#define DW_UART0_BASE 0x40015000UL +#define DW_TIMER0_BASE 0x40011000UL +#define DW_TIMER0_SIZE 0x14U +#define DW_TIMER1_BASE (DW_TIMER0_BASE+DW_TIMER0_SIZE) +#define DW_TIMER1_SIZE DW_TIMER0_SIZE +#define DW_TIMER2_BASE 0x40011028UL +#define DW_TIMER2_SIZE 0x14U +#define DW_TIMER3_BASE (DW_TIMER2_BASE+DW_TIMER2_SIZE) +#define DW_TIMER3_SIZE DW_TIMER2_SIZE +#if CONFIG_SUPPORT_NMI_DEMO +/* fake irq is not work, just for nmi test with smartl fpga(connected TIMER4 to nmi-exception on soc bit of smartl) */ +#define FAKE_IRQ_TIMER4 (-1) +#define DW_TIMER4_BASE (0x40021000UL) +#endif +#endif /* CONFIG_BOARD_SMARTM_EVB */ + +#else + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +#define Supervisor_Software_IRQn (1U) +#define Machine_Software_IRQn (3U) +#define Supervisor_Timer_IRQn (5U) +#define CORET_IRQn (7U) +#define Supervisor_External_IRQn (9U) +#define Machine_External_IRQn (11U) +#define L1_CACHE_ECC_IRQn (16U) + +#if CONFIG_BOARD_XIAOHUI_EVB + +#if CONFIG_INTC_CLIC_PLIC +typedef enum IRQn { + L2_CACHE_ECC_IRQn = 1U + PLIC_IRQ_OFFSET, /* l2 cache ecc Interrupt */ + + DW_DMA0_IRQn = 17U, /* dma0 Interrupt */ + DW_UART0_IRQn = 20U + PLIC_IRQ_OFFSET, /* uart Interrupt */ + TIM0_IRQn = 25U, /* timer0 Interrupt for CLIC*/ + TIM1_IRQn = 26U, /* timer1 Interrupt for CLIC*/ + TIM2_IRQn = 27U + PLIC_IRQ_OFFSET, /* timer2 Interrupt */ + TIM3_IRQn = 28U + PLIC_IRQ_OFFSET, /* timer3 Interrupt */ + IOPMP0_IRQn = 32U, /* iopmp0 Interrupt */ + END_IRQn = 1024U + PLIC_IRQ_OFFSET +} irqn_type_t; +#elif CONFIG_INTC_CLIC_APLIC +typedef enum IRQn { + L2_CACHE_ECC_IRQn = 1U + APLIC_IRQ_OFFSET, /* l2 cache ecc Interrupt */ + + DW_DMA0_IRQn = 17U, /* dma0 Interrupt */ + DW_UART0_IRQn = 20U + APLIC_IRQ_OFFSET, /* uart Interrupt */ + TIM0_IRQn = 25U, /* timer0 Interrupt for CLIC*/ + TIM1_IRQn = 26U, /* timer1 Interrupt for CLIC*/ + TIM2_IRQn = 27U + APLIC_IRQ_OFFSET, /* timer2 Interrupt */ + TIM3_IRQn = 28U + APLIC_IRQ_OFFSET, /* timer3 Interrupt */ + IOPMP0_IRQn = 32U, /* iopmp0 Interrupt */ + END_IRQn = 1024U + APLIC_IRQ_OFFSET +} irqn_type_t; +#else +/* extern irq number, 1-16 are reserved for inner-cpu */ +typedef enum IRQn { + L2_CACHE_ECC_IRQn = 1U, /* l2 cache ecc Interrupt */ + + DW_DMA0_IRQn = 17U, /* dma0 Interrupt */ + DW_UART0_IRQn = 20U, /* uart Interrupt */ + TIM0_IRQn = 25U, /* timer0 Interrupt */ + TIM1_IRQn = 26U, /* timer1 Interrupt */ + TIM2_IRQn = 27U, /* timer2 Interrupt */ + TIM3_IRQn = 28U, /* timer3 Interrupt */ + IOPMP0_IRQn = 32U, /* iopmp0 Interrupt */ +} irqn_type_t; +#endif /* CONFIG_INTC_CLIC_PLIC */ + +#define DW_UART0_BASE (0x1900d000UL) +#define DW_TIMER0_BASE (0x19001000UL) +#define DW_TIMER1_BASE (0x19001014UL) +#define DW_TIMER2_BASE (0x19001028UL) +#define DW_TIMER3_BASE (0x1900103CUL) +#if CONFIG_SUPPORT_NMI_DEMO +/* fake irq is not work, just for nmi test with smartl fpga(connected TIMER4 to nmi-exception on soc bit of smartl) */ +#define FAKE_IRQ_TIMER4 (-1) +#define DW_TIMER4_BASE (0x40021000UL) +#endif + +///////////////////////////////////////////////// +#define DW_DMA0_BASE (0x18000000UL) +#define XT_IOPMP0_BASE (0x26f00000UL) + +#define CONFIG_AXI_DMA_CHANNEL_NUM 8U +#define CONFIG_AXI_DMA_FIFO_SIZE 0x8U +#define CONFIG_AXI_DMA_BLK_MAX_SIZE 0x3FFFFFU + +// #define CONFIG_AHB_DMA_CHANNEL_NUM 8U +// #define CONFIG_AHB_DMA_FIFO_SIZE 0x8U +// #define CONFIG_AHB_DMA_BLK_MAX_SIZE 0xFFFU +///////////////////////////////////////////////// + +#else +#error "Not support soc!!!" +#endif /* CONFIG_BOARD_XIAOHUI_EVB */ + +#endif /* end exx*/ + +#if CONFIG_INTC_CLIC && CONFIG_INTC_PLIC +#error "CONFIG_INTC_CLIC and CONFIG_INTC_PLIC cannot coexist" +#endif + +#if CONFIG_INTC_CLIC && CONFIG_INTC_APLIC +#error "CONFIG_INTC_CLIC and CONFIG_INTC_APLIC cannot coexist" +#endif + +#if CONFIG_INTC_PLIC && CONFIG_INTC_APLIC +#error "CONFIG_INTC_PLIC and CONFIG_INTC_APLIC cannot coexist" +#endif + +#if CONFIG_INTC_CLIC && CONFIG_INTC_CLIC_PLIC +#error "CONFIG_INTC_CLIC and CONFIG_INTC_CLIC_PLIC cannot coexist" +#endif + +#if CONFIG_INTC_CLIC && CONFIG_INTC_CLIC_APLIC +#error "CONFIG_INTC_CLIC and CONFIG_INTC_CLIC_APLIC cannot coexist" +#endif + +#if CONFIG_INTC_CLIC_PLIC && CONFIG_INTC_CLIC_APLIC +#error "CONFIG_INTC_CLIC_PLIC and CONFIG_INTC_CLIC_APLIC cannot coexist" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/sys_clk.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/sys_clk.h new file mode 100644 index 00000000..3d74f5e9 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/sys_clk.h @@ -0,0 +1,117 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file sys_clk.h + * @brief header file for setting system frequency. + * @version V1.0 + * @date 9. April 2020 + ******************************************************************************/ +#ifndef _SYS_CLK_H_ +#define _SYS_CLK_H_ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define PMU_REG_BASE (wj_pmu_reg_t *)WJ_PMU_BASE + +typedef enum { + IHS_CLK = 0U, /* internal high speed clock */ + EHS_CLK, /* external high speed clock */ + ILS_CLK, /* internal low speed clock */ + ELS_CLK, /* external low speed clock */ + PLL_CLK /* PLL clock */ +} clk_src_t; + +typedef enum { + CPU_24MHZ = 24000000U +} sys_freq_t; + + +/* pllclkout : ( pllclkin / 2)*( FN + Frac/4096 ) */ +typedef struct { + + uint32_t pll_is_used; /* pll is used */ + + uint32_t pll_source; /* select pll input source clock */ + + uint32_t pll_src_clk_divider; /* ratio between pll_srcclk clock and pll_clkin clock */ + + uint32_t fn; /* integer value of frequency division */ + + uint32_t frac; /* decimal value of frequency division */ + +} pll_config_t; + + +typedef struct { + uint32_t system_clk; /* system clock */ + + pll_config_t pll_config; /* pll config struct */ + + uint32_t sys_clk_source; /* select sysclk source clock */ + + uint32_t rtc_clk_source; /* select rtcclk source clock */ + + uint32_t mclk_divider; /* ratio between fs_mclk clock and mclk clock */ + + uint32_t apb0_clk_divider; /* ratio between mclk clock and apb0 clock */ + + uint32_t apb1_clk_divider; /* ratio between mclk clock and apb1 clock */ + +} system_clk_config_t; + +typedef enum { + CLK_DIV1 = 0U, +} apb_div_t; + +typedef enum { + PLL_FN_18 = 0U, +} pll_fn_t; + +typedef enum { + UART0_CLK, +} clk_module_t; + + +/** + \brief Set the system clock according to the parameter + \param[in] config system clock config. + \return error code +*/ +csi_error_t soc_sysclk_config(system_clk_config_t *config); + +/** + \brief Set iic reset + \param[in] idx iic idx. + \return Null +*/ +void soc_reset_iic(uint32_t idx); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYS_CLK_H_ */ + diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/startup.S b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/startup.S new file mode 100644 index 00000000..2c6f8c3e --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/startup.S @@ -0,0 +1,224 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +#if !CONFIG_SUPPORT_NON_VECTOR_IRQ +.section .vectors, "aw", @progbits + .align 6 + .globl __Vectors + .type __Vectors, @object +__Vectors: + .long Default_Handler + .long Default_Handler + .long Default_Handler + .long tspend_handler + .long Default_Handler + .long Default_Handler + .long Default_Handler + .long Default_IRQHandler + .long Default_Handler + .long Default_Handler + .long Default_Handler + .long Default_Handler + .long Default_Handler + .long Default_Handler + .long Default_Handler + .long Default_Handler + + /* External interrupts */ + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler + .long Default_IRQHandler +#else /* CONFIG_SUPPORT_NON_VECTOR_IRQ */ +.section .vectors, "aw", @progbits + .align 6 + .globl __Vectors + .type __Vectors, @object +__Vectors: + .long do_irq + .long do_irq + .long do_irq + .long tspend_handler + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + + /* External interrupts */ + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq +#endif /* CONFIG_SUPPORT_NON_VECTOR_IRQ */ + + .size __Vectors, . - __Vectors + + .text + .align 2 + j Reset_Handler + .align 2 + .long 0x594B5343 /* CSKY ASCII */ + .long 0x594B5343 /* CSKY ASCII */ + .align 2 +_start: + .text + .align 2 + .global Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +.option push +.option norelax + la gp, __global_pointer$ +.option pop + la a0, Default_Handler + ori a0, a0, 3 + csrw mtvec, a0 + + la a0, __Vectors + csrw mtvt, a0 + + la sp, g_top_irqstack + csrw mscratch, sp +#ifdef CONFIG_KERNEL_NONE + la sp, g_top_mainstack +#endif + +#ifndef __NO_SYSTEM_INIT + jal SystemInit +#endif + + jal pre_main + + .size Reset_Handler, . - Reset_Handler + +__exit: + j __exit + +.section .stack, "aw", @nobits + .align 4 + .global g_base_irqstack + .global g_top_irqstack +g_base_irqstack: + .space CONFIG_ARCH_INTERRUPTSTACK +g_top_irqstack: +#ifdef CONFIG_KERNEL_NONE + .align 4 + .global g_base_mainstack + .global g_top_mainstack +g_base_mainstack: + .space CONFIG_ARCH_MAINSTACK +g_top_mainstack: +#endif + diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/system.c b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/system.c new file mode 100644 index 00000000..4b20c58f --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/system.c @@ -0,0 +1,121 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "riscv_csr.h" + +#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) +#error "Please check the current system is baremetal or not!!!" +#endif + +extern void section_data_copy(void); +extern void section_ram_code_copy(void); +extern void section_bss_clear(void); + +static void cache_init(void) +{ + csi_dcache_enable(); + csi_icache_enable(); +} + +static void section_init(void) +{ +#if CONFIG_XIP + section_data_copy(); + section_ram_code_copy(); + csi_dcache_clean(); + csi_icache_invalid(); +#endif + section_bss_clear(); +} + +static void clic_init(void) +{ + int i; + + /* get interrupt level from info */ + CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos); + + for (i = 0; i < 64; i++) { + CLIC->CLICINT[i].IP = 0; +#if !CONFIG_SUPPORT_NON_VECTOR_IRQ + CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */ +#else + CLIC->CLICINT[i].ATTR = 0; /* use non-vector interrupt */ +#endif + csi_vic_set_prio(i, 3); + } + /* tspend use vector&positive interrupt */ + CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3; + csi_vic_set_prio(Machine_Software_IRQn, 1); + csi_irq_enable(Machine_Software_IRQn); +} + +static void interrupt_init(void) +{ + clic_init(); +#ifdef CONFIG_KERNEL_NONE + __enable_excp_irq(); +#endif +} + +/** + * @brief initialize the system + * Initialize the psr and vbr. + * @param None + * @return None + */ +void SystemInit(void) +{ + extern int cpu_features_init(void); + cpu_features_init(); + + /* enable theadisaee & MM */ + uint32_t status = __get_MXSTATUS(); + status |= (1 << 22 | 1 << 15); + __set_MXSTATUS(status); + +#if __riscv_flen + /* enable float ISA */ + status = __get_MSTATUS(); + status |= (1 << MSTATUS_FS_SHIFT); + __set_MSTATUS(status); +#endif + /* enable mexstatus SPUSHEN and disable SPSWAPEN */ +#if CONFIG_CPU_XUANTIE_E906 || CONFIG_CPU_XUANTIE_E906F || CONFIG_CPU_XUANTIE_E906FD || CONFIG_CPU_XUANTIE_E906P || CONFIG_CPU_XUANTIE_E906FP || CONFIG_CPU_XUANTIE_E906FDP \ + || CONFIG_CPU_XUANTIE_E907 || CONFIG_CPU_XUANTIE_E907F || CONFIG_CPU_XUANTIE_E907FD || CONFIG_CPU_XUANTIE_E907P || CONFIG_CPU_XUANTIE_E907FP || CONFIG_CPU_XUANTIE_E907FDP + status = __get_MEXSTATUS(); + status |= (0x1 << 16); + status &= ~(0x2 << 16); + __set_MEXSTATUS(status); +#endif + + cache_init(); + section_init(); + interrupt_init(); + soc_set_sys_freq(20000000); + csi_tick_init(); +} + diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/trap_c.c b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/trap_c.c new file mode 100644 index 00000000..f36e86b2 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/trap_c.c @@ -0,0 +1,64 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include +#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) +#include +#else +#define printk printf +#endif + +void (*trap_c_callback)(void); + +void trap_c(uintptr_t *regs) +{ + int i; + unsigned long vec = 0; + + vec = __get_MCAUSE(); + + printk("CPU Exception(mcause);: NO.0x%lx", vec); + printk("\n"); + + for (i = 0; i < 31; i++) { + printk("x%d: %p\t", i + 1, (void *)regs[i]); + + if ((i % 4) == 3) { + printk("\n"); + } + } + + printk("\n"); + printk("mepc : %p\n", (void *)regs[31]); + printk("mstatus: %p\n", (void *)regs[32]); + + if (trap_c_callback) { + trap_c_callback(); + } + + while (1); +} + +__attribute__((weak)) void exceptionHandler(void *context) +{ + trap_c((uintptr_t *)context); +} + diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/vectors.S b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/vectors.S new file mode 100644 index 00000000..5c0aabb2 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/vectors.S @@ -0,0 +1,898 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_asm_macro.h" + +#define RISCV_MCAUSE_IRQ_POS 31 + +.section .stack, "aw", @nobits + .align 4 + .global g_trapstackbase + .global g_top_trapstack +g_trapstackbase: + .space CONFIG_ARCH_INTERRUPTSTACK +g_top_trapstack: + +#if CONFIG_SUPPORT_IRQ_NESTED +#define IRQ_NESTED_MAX (6) +.section .bss + .align 2 + irq_nested_level: + .long 0 + + irq_nested_mcause: + .long 0, 0, 0, 0, 0, 0 +#endif + +/* for interrupt tail-chaining debug */ +#if CONFIG_DEBUG_TAIL_CHAINING +.global g_irq_tailchain_loops +g_irq_tailchain_loops: +.long 0 +#endif + +.text + +#if !CONFIG_SUPPORT_IRQ_NESTED + .align 2 + .weak Default_IRQHandler + .type Default_IRQHandler, %function +Default_IRQHandler: +#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP + addi sp, sp, -4 + sw s0, (sp) +#endif + + csrw mscratch, sp + la sp, g_top_irqstack + addi sp, sp, -76 + sw t0, 4(sp) + sw t1, 8(sp) + csrr t0, mepc + csrr t1, mcause + sw t1, 64(sp) + sw t0, 68(sp) + csrr t1, mstatus + sw t1, 72(sp) + sw ra, 0(sp) + sw t2, 12(sp) + sw a0, 16(sp) + sw a1, 20(sp) + sw a2, 24(sp) + sw a3, 28(sp) + sw a4, 32(sp) + sw a5, 36(sp) + sw a6, 40(sp) + sw a7, 44(sp) + sw t3, 48(sp) + sw t4, 52(sp) + sw t5, 56(sp) + sw t6, 60(sp) + +#if __riscv_dsp + addi sp, sp, -4 + csrr t0, vxsat + sw t0, 0(sp) +#endif /*__riscv_dsp */ + +#if CONFIG_CHECK_FPU_DIRTY + mv t3, t1 +#endif + SAVE_FLOAT_REGISTERS + + la t0, do_irq + jalr t0 + + /* get mcause from sp */ + addi t0, sp, 64 +#if __riscv_dsp + addi t0, t0, 4 +#endif /*__riscv_dsp */ +#if __riscv_flen == 64 + addi t0, t0, 164 +#elif __riscv_flen == 32 + addi t0, t0, 84 +#endif + lw a1, (t0) + andi a0, a1, 0x3FF + slli a0, a0, 2 + + /* clear pending */ + li a2, 0xE0801000 + add a2, a2, a0 + lb a3, 0(a2) + li a4, 1 + not a4, a4 + and a5, a4, a3 + sb a5, 0(a2) + + RESTORE_xSTATUS + + csrw mcause, a1 + + RESTORE_FLOAT_REGISTERS + +#if __riscv_dsp + lw t0, 0(sp) + csrw vxsat, t0 + addi sp, sp, 4 +#endif /*__riscv_dsp */ + + lw t0, 68(sp) + csrw mepc, t0 + lw ra, 0(sp) + lw t0, 4(sp) + lw t1, 8(sp) + lw t2, 12(sp) + lw a0, 16(sp) + lw a1, 20(sp) + lw a2, 24(sp) + lw a3, 28(sp) + lw a4, 32(sp) + lw a5, 36(sp) + lw a6, 40(sp) + lw a7, 44(sp) + lw t3, 48(sp) + lw t4, 52(sp) + lw t5, 56(sp) + lw t6, 60(sp) + + addi sp, sp, 76 + csrr sp, mscratch + +#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP + addi sp, sp, 4 +#endif + mret +#else /* CONFIG_SUPPORT_IRQ_NESTED */ + .align 2 + .weak Default_IRQHandler + .type Default_IRQHandler, %function +Default_IRQHandler: + addi sp, sp, -8 + sw t0, 0(sp) + sw t1, 4(sp) + + la t0, irq_nested_level + lw t1, (t0) + addi t1, t1, 1 + sw t1, (t0) + + li t0, IRQ_NESTED_MAX + /* nested too deeply, may be error happens */ + bgt t1, t0, Default_Handler + + addi t1, t1, -1 + la t0, irq_nested_mcause + slli t1, t1, 2 + add t0, t0, t1 + csrr t1, mcause + sw t1, (t0) + + la t0, irq_nested_level + lw t1, (t0) + li t0, 1 + bgt t1, t0, .Lnested1 + +#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP + addi sp, sp, -8 + sw s0, (sp) + csrr t0, mepc + sw t0, 4(sp) +#endif + + csrw mscratch, sp + la sp, g_top_irqstack + j .Lnested2 +.Lnested1: + lw t0, 0(sp) + lw t1, 4(sp) + addi sp, sp, 8 +.Lnested2: + addi sp, sp, -76 + sw t0, 4(sp) + sw t1, 8(sp) + csrr t0, mepc + csrr t1, mcause + sw t1, 64(sp) + sw t0, 68(sp) + csrr t1, mstatus + sw t1, 72(sp) + + csrs mstatus, 8 + + sw ra, 0(sp) + sw t2, 12(sp) + sw a0, 16(sp) + sw a1, 20(sp) + sw a2, 24(sp) + sw a3, 28(sp) + sw a4, 32(sp) + sw a5, 36(sp) + sw a6, 40(sp) + sw a7, 44(sp) + sw t3, 48(sp) + sw t4, 52(sp) + sw t5, 56(sp) + sw t6, 60(sp) + +#if __riscv_dsp + addi sp, sp, -4 + csrr t0, vxsat + sw t0, 0(sp) +#endif /*__riscv_dsp */ + +#if CONFIG_CHECK_FPU_DIRTY + mv t3, t1 +#endif + SAVE_FLOAT_REGISTERS + + la t0, do_irq + jalr t0 + + csrc mstatus, 8 + + /* get mcause from sp */ + addi t0, sp, 64 +#if __riscv_dsp + addi t0, t0, 4 +#endif /*__riscv_dsp */ +#if __riscv_flen == 64 + addi t0, t0, 164 +#elif __riscv_flen == 32 + addi t0, t0, 84 +#endif + lw a1, (t0) + andi a0, a1, 0x3FF + slli a0, a0, 2 + + /* clear pending */ + li a2, 0xE0801000 + add a2, a2, a0 + lb a3, 0(a2) + li a4, 1 + not a4, a4 + and a5, a4, a3 + sb a5, 0(a2) + + la t0, irq_nested_level + lw t1, (t0) + addi t1, t1, -1 + sw t1, (t0) + bgt t1, zero, .Lnested3 + + RESTORE_xSTATUS + + csrw mcause, a1 + + RESTORE_FLOAT_REGISTERS + +#if __riscv_dsp + lw t0, 0(sp) + csrw vxsat, t0 + addi sp, sp, 4 +#endif /*__riscv_dsp */ + + lw t0, 68(sp) + csrw mepc, t0 + lw ra, 0(sp) + lw t0, 4(sp) + lw t1, 8(sp) + lw t2, 12(sp) + lw a0, 16(sp) + lw a1, 20(sp) + lw a2, 24(sp) + lw a3, 28(sp) + lw a4, 32(sp) + lw a5, 36(sp) + lw a6, 40(sp) + lw a7, 44(sp) + lw t3, 48(sp) + lw t4, 52(sp) + lw t5, 56(sp) + lw t6, 60(sp) + + addi sp, sp, 76 + csrr sp, mscratch +#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP + addi sp, sp, 8 +#endif + lw t0, 0(sp) + lw t1, 4(sp) + addi sp, sp, 8 + mret + +.Lnested3: + /* keep mpil in current mcause & load exception code before */ + addi t1, t1, -1 + la t0, irq_nested_mcause + slli t1, t1, 2 + add t1, t0, t1 + lw t0, (t1) + andi t0, t0, 0x3FF + andi a0, a1, 0xFFFFFC00 + or t0, a0, t0 + csrw mcause, t0 + + RESTORE_xSTATUS + + RESTORE_FLOAT_REGISTERS + +#if __riscv_dsp + lw t0, 0(sp) + csrw vxsat, t0 + addi sp, sp, 4 +#endif /*__riscv_dsp */ + + lw t0, 68(sp) + csrw mepc, t0 + + lw ra, 0(sp) + lw t0, 4(sp) + lw t1, 8(sp) + lw t2, 12(sp) + lw a0, 16(sp) + lw a1, 20(sp) + lw a2, 24(sp) + lw a3, 28(sp) + lw a4, 32(sp) + lw a5, 36(sp) + lw a6, 40(sp) + lw a7, 44(sp) + lw t3, 48(sp) + lw t4, 52(sp) + lw t5, 56(sp) + lw t6, 60(sp) + + addi sp, sp, 76 + mret +#endif /* CONFIG_SUPPORT_IRQ_NESTED */ + +/****************************************************************************** + * Functions: + * void trap(void); + * default exception handler + ******************************************************************************/ + .align 2 + .global trap + .type trap, %function +trap: + csrw mscratch, sp + la sp, g_top_trapstack + addi sp, sp, -140 + sw x1, ( 0 )(sp) + sw x3, ( 8 )(sp) + sw x4, ( 12)(sp) + sw x5, ( 16)(sp) + sw x6, ( 20)(sp) + sw x7, ( 24)(sp) + sw x8, ( 28)(sp) + sw x9, ( 32)(sp) + sw x10,( 36)(sp) + sw x11,( 40)(sp) + sw x12,( 44)(sp) + sw x13,( 48)(sp) + sw x14,( 52)(sp) + sw x15,( 56)(sp) + sw x16,( 60)(sp) + sw x17,( 64)(sp) + sw x18,( 68)(sp) + sw x19,( 72)(sp) + sw x20,( 76)(sp) + sw x21,( 80)(sp) + sw x22,( 84)(sp) + sw x23,( 88)(sp) + sw x24,( 92)(sp) + sw x25,( 96)(sp) + sw x26,(100)(sp) + sw x27,(104)(sp) + sw x28,(108)(sp) + sw x29,(112)(sp) + sw x30,(116)(sp) + sw x31,(120)(sp) + csrr a0, mepc + sw a0, (124)(sp) + csrr a0, mstatus + sw a0, (128)(sp) + csrr a0, mcause + sw a0, (132)(sp) + csrr a0, mtval + sw a0, (136)(sp) + csrr a0, mscratch + sw a0, ( 4 )(sp) + + mv a0, sp + la a1, exceptionHandler + jalr a1 + +/******************************************************************************* + * Functions: + * void Default_Handler(void); + * Non-Vector Interrupt Handler,Exception Handler,NMI Handler + ******************************************************************************/ +#if !CONFIG_SUPPORT_IRQ_NESTED + .align 6 + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + /* Check for nmi */ + addi sp, sp, -8 + sw t0, 0x0(sp) + sw t1, 0x4(sp) + csrr t0, mcause + + srli t1, t0, RISCV_MCAUSE_IRQ_POS + bnez t1, is_interrupt + + andi t0, t0, 0x3FF + li t1, 24 + beq t0, t1, .NMI_Handler + lw t0, 0x0(sp) + lw t1, 0x4(sp) + addi sp, sp, 8 + j trap + +is_interrupt: + lw t0, 0x0(sp) + lw t1, 0x4(sp) + addi sp, sp, 8 +#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP + addi sp, sp, -4 + sw s0, (sp) +#endif + csrw mscratch, sp + la sp, g_top_irqstack + addi sp, sp, -76 + sw t0, 4(sp) + sw t1, 8(sp) + csrr t0, mepc + csrr t1, mcause + sw t1, 64(sp) + sw t0, 68(sp) + csrr t1, mstatus + sw t1, 72(sp) + + sw ra, 0(sp) + sw t2, 12(sp) + sw a0, 16(sp) + sw a1, 20(sp) + sw a2, 24(sp) + sw a3, 28(sp) + sw a4, 32(sp) + sw a5, 36(sp) + sw a6, 40(sp) + sw a7, 44(sp) + sw t3, 48(sp) + sw t4, 52(sp) + sw t5, 56(sp) + sw t6, 60(sp) + +#if __riscv_dsp + addi sp, sp, -4 + csrr t0, vxsat + sw t0, 0(sp) +#endif /*__riscv_dsp */ + +#if CONFIG_CHECK_FPU_DIRTY + mv t3, t1 +#endif + SAVE_FLOAT_REGISTERS + +#if CONFIG_DEBUG_TAIL_CHAINING + li t2, 0 + la t1, g_irq_tailchain_loops + sw t2, 0(t1) +#endif + + csrrci t0, mnxti, MSTATUS_MIE + beqz t0, irq_done + +irq_loop: +#if CONFIG_DEBUG_TAIL_CHAINING + la t2, g_irq_tailchain_loops + lw t1, 0(t2) + addi t1, t1, 1 + sw t1, 0(t2) +#endif + lw t1, 0(t0) + jalr t1 + csrrci t0, mnxti, MSTATUS_MIE + bnez t0, irq_loop + +irq_done: + RESTORE_xSTATUS + + RESTORE_FLOAT_REGISTERS + +#if __riscv_dsp + lw t0, 0(sp) + csrw vxsat, t0 + addi sp, sp, 4 +#endif /*__riscv_dsp */ + + lw a1, 64(sp) + csrw mcause, a1 + + lw t0, 68(sp) + csrw mepc, t0 + + lw ra, 0(sp) + lw t0, 4(sp) + lw t1, 8(sp) + lw t2, 12(sp) + lw a0, 16(sp) + lw a1, 20(sp) + lw a2, 24(sp) + lw a3, 28(sp) + lw a4, 32(sp) + lw a5, 36(sp) + lw a6, 40(sp) + lw a7, 44(sp) + lw t3, 48(sp) + lw t4, 52(sp) + lw t5, 56(sp) + lw t6, 60(sp) + + addi sp, sp, 76 + csrr sp, mscratch + +#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP + addi sp, sp, 4 +#endif + mret + +#else /* CONFIG_SUPPORT_IRQ_NESTED */ + + .align 6 + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + addi sp, sp, -8 + sw t0, 0x0(sp) + sw t1, 0x4(sp) + + csrr t0, mcause + + /* Check is interrupt */ + srli t1, t0, RISCV_MCAUSE_IRQ_POS + bnez t1, is_interrupt + + /* Check for nmi */ + andi t0, t0, 0x3FF + li t1, 24 + beq t0, t1, .NMI_Handler + + lw t0, 0x0(sp) + lw t1, 0x4(sp) + addi sp, sp, 8 + + /* is exception */ + j trap + +is_interrupt: + la t0, irq_nested_level + lw t1, (t0) + addi t1, t1, 1 + sw t1, (t0) + + li t0, IRQ_NESTED_MAX + /* nested too deeply, may be error happens */ + bgt t1, t0, trap + + addi t1, t1, -1 + la t0, irq_nested_mcause + slli t1, t1, 2 + add t0, t0, t1 + csrr t1, mcause + sw t1, (t0) + + la t0, irq_nested_level + lw t1, (t0) + li t0, 1 + bgt t1, t0, .Nested_Context + +#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP + addi sp, sp, -8 + sw s0, (sp) + csrr t0, mepc + sw t0, 4(sp) +#endif + + csrw mscratch, sp + la sp, g_top_irqstack + j .Save_Context + +.Nested_Context: + lw t0, 0(sp) + lw t1, 4(sp) + addi sp, sp, 8 +.Save_Context: + addi sp, sp, -76 + sw t0, 4(sp) + sw t1, 8(sp) + csrr t0, mepc + csrr t1, mcause + sw t1, 64(sp) + sw t0, 68(sp) + csrr t1, mstatus + sw t1, 72(sp) + + sw ra, 0(sp) + sw t2, 12(sp) + sw a0, 16(sp) + sw a1, 20(sp) + sw a2, 24(sp) + sw a3, 28(sp) + sw a4, 32(sp) + sw a5, 36(sp) + sw a6, 40(sp) + sw a7, 44(sp) + sw t3, 48(sp) + sw t4, 52(sp) + sw t5, 56(sp) + sw t6, 60(sp) + +#if __riscv_dsp + addi sp, sp, -4 + csrr t0, vxsat + sw t0, 0(sp) +#endif /*__riscv_dsp */ + +#if CONFIG_CHECK_FPU_DIRTY + mv t3, t1 +#endif + SAVE_FLOAT_REGISTERS + + csrrci t0, mnxti, MSTATUS_MIE + csrs mstatus, 8 /* enable irq for preemption */ + lw t1, 0(t0) /* Get handler from vector table */ + jalr t1 /* Call handler */ + + csrc mstatus, 8 /* disable irq for critical section */ + + /* get mcause from sp */ + addi t0, sp, 64 +#if __riscv_dsp + addi t0, t0, 4 +#endif /*__riscv_dsp */ +#if __riscv_flen == 64 + addi t0, t0, 164 +#elif __riscv_flen == 32 + addi t0, t0, 84 +#endif + lw a1, (t0) + + la t0, irq_nested_level + lw t1, (t0) + addi t1, t1, -1 + sw t1, (t0) + bgt t1, zero, .Nested_Return + + RESTORE_xSTATUS + + csrw mcause, a1 + + RESTORE_FLOAT_REGISTERS + +#if __riscv_dsp + lw t0, 0(sp) + csrw vxsat, t0 + addi sp, sp, 4 +#endif /*__riscv_dsp */ + + lw t0, 68(sp) + csrw mepc, t0 + lw ra, 0(sp) + lw t0, 4(sp) + lw t1, 8(sp) + lw t2, 12(sp) + lw a0, 16(sp) + lw a1, 20(sp) + lw a2, 24(sp) + lw a3, 28(sp) + lw a4, 32(sp) + lw a5, 36(sp) + lw a6, 40(sp) + lw a7, 44(sp) + lw t3, 48(sp) + lw t4, 52(sp) + lw t5, 56(sp) + lw t6, 60(sp) + + addi sp, sp, 76 + csrr sp, mscratch +#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP + addi sp, sp, 8 +#endif + lw t0, 0(sp) + lw t1, 4(sp) + addi sp, sp, 8 + mret + +.Nested_Return: + /* keep mpil in current mcause & load exception code before */ + addi t1, t1, -1 + la t0, irq_nested_mcause + slli t1, t1, 2 + add t1, t0, t1 + lw t0, (t1) + andi t0, t0, 0x3FF + andi a0, a1, 0xFFFFFC00 + or t0, a0, t0 + csrw mcause, t0 + + RESTORE_xSTATUS + + RESTORE_FLOAT_REGISTERS + +#if __riscv_dsp + lw t0, 0(sp) + csrw vxsat, t0 + addi sp, sp, 4 +#endif /*__riscv_dsp */ + + lw t0, 68(sp) + csrw mepc, t0 + + lw ra, 0(sp) + lw t0, 4(sp) + lw t1, 8(sp) + lw t2, 12(sp) + lw a0, 16(sp) + lw a1, 20(sp) + lw a2, 24(sp) + lw a3, 28(sp) + lw a4, 32(sp) + lw a5, 36(sp) + lw a6, 40(sp) + lw a7, 44(sp) + lw t3, 48(sp) + lw t4, 52(sp) + lw t5, 56(sp) + lw t6, 60(sp) + + addi sp, sp, 76 + mret +#endif /* CONFIG_SUPPORT_IRQ_NESTED */ +.NMI_Handler: + /* mscratch may be used before */ + addi sp, sp, -4 + csrr t0, mscratch + sw t0, 0x0(sp) + + csrw mscratch, sp + la sp, g_top_trapstack + addi sp, sp, -76 + sw t0, 4(sp) + sw t1, 8(sp) + csrr t0, mepc + csrr t1, mcause + sw t1, 64(sp) + sw t0, 68(sp) + csrr t1, mstatus + sw t1, 72(sp) + + sw ra, 0(sp) + sw t2, 12(sp) + sw a0, 16(sp) + sw a1, 20(sp) + sw a2, 24(sp) + sw a3, 28(sp) + sw a4, 32(sp) + sw a5, 36(sp) + sw a6, 40(sp) + sw a7, 44(sp) + sw t3, 48(sp) + sw t4, 52(sp) + sw t5, 56(sp) + sw t6, 60(sp) + +#if __riscv_dsp + addi sp, sp, -4 + csrr t0, vxsat + sw t0, 0(sp) +#endif /*__riscv_dsp */ + +#if CONFIG_CHECK_FPU_DIRTY + mv t3, t1 +#endif + SAVE_FLOAT_REGISTERS + + la t0, handle_nmi_exception + jalr t0 + + /* get mcause from sp */ + addi t0, sp, 64 +#if __riscv_dsp + addi t0, t0, 4 +#endif /*__riscv_dsp */ +#if __riscv_flen == 64 + addi t0, t0, 164 +#elif __riscv_flen == 32 + addi t0, t0, 84 +#endif + lw a1, (t0) + andi a0, a1, 0x3FF + slli a0, a0, 2 + + /* clear pending */ + li a2, 0xE0801000 + add a2, a2, a0 + lb a3, 0(a2) + li a4, 1 + not a4, a4 + and a5, a4, a3 + sb a5, 0(a2) + + RESTORE_xSTATUS + + csrw mcause, a1 + + RESTORE_FLOAT_REGISTERS + +#if __riscv_dsp + lw t0, 0(sp) + csrw vxsat, t0 + addi sp, sp, 4 +#endif /*__riscv_dsp */ + + lw t0, 68(sp) + csrw mepc, t0 + lw t0, 72(sp) + csrw mstatus, t0 + + lw ra, 0(sp) + lw t0, 4(sp) + lw t1, 8(sp) + lw t2, 12(sp) + lw a0, 16(sp) + lw a1, 20(sp) + lw a2, 24(sp) + lw a3, 28(sp) + lw a4, 32(sp) + lw a5, 36(sp) + lw a6, 40(sp) + lw a7, 44(sp) + lw t3, 48(sp) + lw t4, 52(sp) + lw t5, 56(sp) + lw t6, 60(sp) + + addi sp, sp, 76 + csrr sp, mscratch + + /* restore mscratch */ + lw t0, 0x0(sp) + csrw mscratch, t0 + addi sp, sp, 4 + + lw t0, 0x0(sp) + lw t1, 0x4(sp) + addi sp, sp, 8 + + mret + + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/drivers/dw_uart_ll.c b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/drivers/dw_uart_ll.c new file mode 100644 index 00000000..15ae00be --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/drivers/dw_uart_ll.c @@ -0,0 +1,164 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file dw_uart_ll.c + * @brief dw uart ll driver + * @version V1.0 + * @date 18. December 2024 + ******************************************************************************/ +#include + +int32_t dw_uart_wait_idle(dw_uart_regs_t *uart_base) +{ + uint32_t timecount = 0U; + int32_t ret = 0; + + while ((uart_base->USR & DW_UART_USR_BUSY_SET) && (timecount < UART_BUSY_TIMEOUT)) { + timecount++; + } + + if (timecount >= UART_BUSY_TIMEOUT) { + ret = -1; + } + + return ret; +} + +int32_t dw_uart_wait_timeout(dw_uart_regs_t *uart_base) +{ + uint32_t timecount = 0U; + int32_t ret = 0; + + while ((uart_base->LSR & 0x81U) || (uart_base->USR & 0x1U)) { + uart_base->LSR; + uart_base->RBR; + timecount++; + + if (timecount >= UART_BUSY_TIMEOUT) { + ret = -1; + break; + } + } + + if (ret == 0) { + ret = dw_uart_wait_idle(uart_base); + } + + return ret; +} + +int32_t dw_uart_config_baudrate(dw_uart_regs_t *uart_base, uint32_t baud, uint32_t uart_freq) +{ + uint32_t divisor; + int32_t ret = 0; + ret = dw_uart_wait_timeout(uart_base); + + if (ret == 0) { + if ((uart_freq / 16) % baud >= (baud / 2)) + divisor = (uart_freq / 16) / baud + 1; + else + divisor = (uart_freq / 16) / baud; + + uart_base->LCR |= DW_UART_LCR_DLAB_EN; + + /* DLL and DLH is lower 8-bits and higher 8-bits of divisor.*/ + uart_base->DLH = (divisor >> 8U) & 0xFFU; + uart_base->DLL = divisor & 0xFFU; + /* + * The DLAB must be cleared after the baudrate is setted + * to access other registers. + */ + uart_base->LCR &= (~DW_UART_LCR_DLAB_EN); + } + + return ret; +} + +int32_t dw_uart_config_stop_bits(dw_uart_regs_t *uart_base, uint32_t stop_bits) +{ + int32_t ret; + ret = dw_uart_wait_timeout(uart_base); + + if (ret == 0) { + + //when data length is 5 bits, use dw_uart_config_stop_bits_2 will be 1.5 stop bits + if (stop_bits == 1U) { + dw_uart_config_stop_bits_1(uart_base); + } else if (stop_bits == 2U) { + dw_uart_config_stop_bits_2(uart_base); + } + } + + //FIXME: no console output sometimes + mdelay(1); + + return ret; +} + +int32_t dw_uart_config_parity_none(dw_uart_regs_t *uart_base) +{ + int32_t ret; + ret = dw_uart_wait_timeout(uart_base); + + if (ret == 0) { + uart_base->LCR &= (~DW_UART_LCR_PEN_EN); + } + + return ret; +} + +int32_t dw_uart_config_parity_odd(dw_uart_regs_t *uart_base) +{ + int32_t ret; + + ret = dw_uart_wait_timeout(uart_base); + + if (ret == 0) { + uart_base->LCR |= DW_UART_LCR_PEN_EN; + uart_base->LCR &= ~(DW_UART_LCR_EPS_EN); + } + + return ret; +} + +int32_t dw_uart_config_parity_even(dw_uart_regs_t *uart_base) +{ + int32_t ret; + + ret = dw_uart_wait_timeout(uart_base); + + if (ret == 0) { + uart_base->LCR |= DW_UART_LCR_PEN_EN; + uart_base->LCR |= DW_UART_LCR_EPS_EN; + } + + return ret; +} + +int32_t dw_uart_config_data_bits(dw_uart_regs_t *uart_base, uint32_t data_bits) +{ + int32_t ret; + + ret = dw_uart_wait_timeout(uart_base); + + uart_base->LCR &= 0xFCU; + uart_base->LCR |= (data_bits - 5U); + + return ret; +} diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/drivers/uart.c b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/drivers/uart.c new file mode 100644 index 00000000..5f335b4d --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/drivers/uart.c @@ -0,0 +1,809 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file uart.c + * @brief CSI Source File for uart Driver + * @version V2.01 + * @date 2020-04-09 + ******************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define UART_TIMEOUT 0x10000000U +#define UART_MAX_FIFO 0x10U + +extern uint16_t uart_tx_hs_num[]; +extern uint16_t uart_rx_hs_num[]; +extern const csi_pinmap_t uart_pinmap[]; + +static uint8_t find_max_prime_num(uint32_t num) +{ + uint8_t ret; + + if (!(num % 8U)) { + ret = 8U; + } else if (!(num % 4U)) { + ret = 4U; + } else { + ret = 1U; + } + + return ret; +} + +static void dw_uart_intr_recv_data(csi_uart_t *uart) +{ + dw_uart_regs_t *uart_base = (dw_uart_regs_t *)HANDLE_REG_BASE(uart); + uint32_t rxfifo_num = 1;/// uart->rx_size) ? uart->rx_size : rxfifo_num; + + if ((uart->rx_data == NULL) || (uart->rx_size == 0U)) { + if (uart->callback) { + uart->callback(uart, UART_EVENT_RECEIVE_FIFO_READABLE, uart->arg); + } else { + do { + dw_uart_getchar(uart_base); + } while (--rxfifo_num); + } + } else { + do { + *uart->rx_data = dw_uart_getchar(uart_base); + uart->rx_size--; + uart->rx_data++; + } while (--rxdata_num); + + if (uart->rx_size == 0U) { + uart->state.readable = 1U; + + if (uart->callback) { + uart->callback(uart, UART_EVENT_RECEIVE_COMPLETE, uart->arg); + } + } + } +} + +static void uart_intr_send_data(csi_uart_t *uart) +{ + uint32_t i = 0U, trans_num = 0U; + dw_uart_regs_t *uart_base = (dw_uart_regs_t *)uart->dev.reg_base; + + if (uart->tx_size > UART_MAX_FIFO) { + trans_num = UART_MAX_FIFO; + } else { + trans_num = uart->tx_size; + } + + for (i = 0U; i < trans_num; i++) { + //dw_uart_putchar(uart_base, *uart->tx_data); + csi_uart_putc(uart, *uart->tx_data); + uart->tx_size--; + uart->tx_data++; + } + + if (uart->tx_size == 0U) { + dw_uart_disable_trans_irq(uart_base); + uart->state.writeable = 1U; + + if (uart->callback) { + uart->callback(uart, UART_EVENT_SEND_COMPLETE, uart->arg); + } + } +} + +static void uart_intr_line_error(csi_uart_t *uart) +{ + uint32_t uart_status; + dw_uart_regs_t *uart_base = (dw_uart_regs_t *)HANDLE_REG_BASE(uart); + + uart->state.readable = 1U; + uart->state.writeable = 1U; + uart_status = dw_uart_get_line_status(uart_base); + + if (uart->callback) { + if (uart_status & DW_UART_LSR_OE_ERROR) { + uart->callback(uart, UART_EVENT_ERROR_OVERFLOW, uart->arg); + } + + if (uart_status & DW_UART_LSR_PE_ERROR) { + uart->callback(uart, UART_EVENT_ERROR_PARITY, uart->arg); + } + + if (uart_status & DW_UART_LSR_FE_ERROR) { + uart->callback(uart, UART_EVENT_ERROR_FRAMING, uart->arg); + } + + if (uart_status & DW_UART_LSR_BI_SET) { + uart->callback(uart, UART_ENENT_BREAK_INTR, uart->arg); + } + } +} + +void dw_uart_irq_handler(void *arg) +{ + csi_uart_t *uart = (csi_uart_t *)arg; + dw_uart_regs_t *uart_base = (dw_uart_regs_t *)uart->dev.reg_base; + + uint8_t intr_state; + + intr_state = (uint8_t)(uart_base->IIR & 0xfU); + + switch (intr_state) { + case DW_UART_IIR_IID_RECV_LINE_STATUS: /* interrupt source: Overrun/parity/framing errors or break interrupt */ + uart_intr_line_error(uart); + break; + + case DW_UART_IIR_IID_THR_EMPTY: /* interrupt source:sendter holding register empty */ + uart_intr_send_data(uart); + break; + + case DW_UART_IIR_IID_RECV_DATA_AVAIL: /* interrupt source:receiver data available or receiver fifo trigger level reached */ + case DW_UART_IIR_IID_CHARACTER_TIMEOUT: + dw_uart_intr_recv_data(uart); + break; + + default: + break; + } +} + +csi_error_t csi_uart_init(csi_uart_t *uart, uint32_t idx) +{ + CSI_PARAM_CHK(uart, CSI_ERROR); + + csi_error_t ret = CSI_OK; + dw_uart_regs_t *uart_base; + + ret = target_get(DEV_DW_UART_TAG, idx, &uart->dev); + + if (ret == CSI_OK) { + uart_base = (dw_uart_regs_t *)HANDLE_REG_BASE(uart); + + dw_uart_fifo_init(uart_base); + + uart->rx_size = 0U; + uart->tx_size = 0U; + uart->rx_data = NULL; + uart->tx_data = NULL; + uart->tx_dma = NULL; + uart->rx_dma = NULL; + dw_uart_disable_trans_irq(uart_base); + dw_uart_disable_recv_irq(uart_base); + dw_uart_disable_auto_flow_control(uart_base); + } + + return ret; +} + +void csi_uart_uninit(csi_uart_t *uart) +{ + CSI_PARAM_CHK_NORETVAL(uart); + + dw_uart_regs_t *uart_base; + uart_base = (dw_uart_regs_t *)HANDLE_REG_BASE(uart); + + uart->rx_size = 0U; + uart->tx_size = 0U; + uart->rx_data = NULL; + uart->tx_data = NULL; + + dw_uart_disable_trans_irq(uart_base); + dw_uart_disable_recv_irq(uart_base); + csi_irq_disable((uint32_t)(uart->dev.irq_num)); + csi_irq_detach((uint32_t)(uart->dev.irq_num)); +} + +csi_error_t csi_uart_baud(csi_uart_t *uart, uint32_t baud) +{ + CSI_PARAM_CHK(uart, CSI_ERROR); + + int32_t ret = 0; + csi_error_t csi_ret = CSI_OK; + dw_uart_regs_t *uart_base; + uart_base = (dw_uart_regs_t *)HANDLE_REG_BASE(uart); + + ret = dw_uart_config_baudrate(uart_base, baud, soc_get_uart_freq((uint32_t)(uart->dev.idx))); + + if (ret == 0) { + csi_ret = CSI_OK; + } else { + csi_ret = CSI_ERROR; + } + + return csi_ret; +} + +csi_error_t csi_uart_format(csi_uart_t *uart, csi_uart_data_bits_t data_bits, + csi_uart_parity_t parity, csi_uart_stop_bits_t stop_bits) +{ + CSI_PARAM_CHK(uart, CSI_ERROR); + + int32_t ret = 0; + csi_error_t csi_ret = CSI_OK; + dw_uart_regs_t *uart_base; + uart_base = (dw_uart_regs_t *)HANDLE_REG_BASE(uart); + + switch (data_bits) { + case UART_DATA_BITS_5: + ret = dw_uart_config_data_bits(uart_base, 5U); + break; + + case UART_DATA_BITS_6: + ret = dw_uart_config_data_bits(uart_base, 6U); + break; + + case UART_DATA_BITS_7: + ret = dw_uart_config_data_bits(uart_base, 7U); + break; + + case UART_DATA_BITS_8: + ret = dw_uart_config_data_bits(uart_base, 8U); + break; + + default: + ret = -1; + break; + } + + if (ret == 0) { + switch (parity) { + case UART_PARITY_NONE: + ret = dw_uart_config_parity_none(uart_base); + break; + + case UART_PARITY_ODD: + ret = dw_uart_config_parity_odd(uart_base); + break; + + case UART_PARITY_EVEN: + ret = dw_uart_config_parity_even(uart_base); + break; + + default: + ret = -1; + break; + } + + if (ret == 0) { + switch (stop_bits) { + case UART_STOP_BITS_1: + ret = dw_uart_config_stop_bits(uart_base, 1U); + break; + + case UART_STOP_BITS_2: + ret = dw_uart_config_stop_bits(uart_base, 2U); + break; + + case UART_STOP_BITS_1_5: + if (data_bits == UART_DATA_BITS_5) { + ret = dw_uart_config_stop_bits(uart_base, 2U); + break; + } + + default: + ret = -1; + break; + } + + if (ret != 0) { + csi_ret = CSI_ERROR; + } + + } else { + csi_ret = CSI_ERROR; + } + + } else { + csi_ret = CSI_ERROR; + } + + return csi_ret; +} + +csi_error_t csi_uart_flowctrl(csi_uart_t *uart, csi_uart_flowctrl_t flowctrl) +{ + CSI_PARAM_CHK(uart, CSI_ERROR); + csi_error_t csi_ret = CSI_OK; + dw_uart_regs_t *uart_base; + uart_base = (dw_uart_regs_t *)HANDLE_REG_BASE(uart); + + switch (flowctrl) { + case UART_FLOWCTRL_CTS: + dw_uart_wait_idle(uart_base); + dw_uart_enable_auto_flow_control(uart_base); + break; + + case UART_FLOWCTRL_RTS_CTS: + dw_uart_wait_idle(uart_base); + dw_uart_enable_auto_flow_control(uart_base); + break; + + case UART_FLOWCTRL_NONE: + dw_uart_wait_idle(uart_base); + break; + + case UART_FLOWCTRL_RTS: + default: + csi_ret = CSI_UNSUPPORTED; + break; + } + + return csi_ret; +} + +void csi_uart_putc(csi_uart_t *uart, uint8_t ch) +{ + CSI_PARAM_CHK_NORETVAL(uart); + + volatile int i = 10; + uint32_t timeout = UART_TIMEOUT; + dw_uart_regs_t *uart_base = (dw_uart_regs_t *)HANDLE_REG_BASE(uart); + + while (!dw_uart_putready(uart_base) && timeout--); + + if (timeout) { + //FIXME: fix print luanma on irq-mode sometimes. maybe hw bug + while (i--); + dw_uart_putchar(uart_base, ch); + } +} + +uint8_t csi_uart_getc(csi_uart_t *uart) +{ + CSI_PARAM_CHK(uart, 0U); + + dw_uart_regs_t *uart_base = (dw_uart_regs_t *)HANDLE_REG_BASE(uart); + + while (!dw_uart_getready(uart_base)); + + return dw_uart_getchar(uart_base); +} + +int32_t csi_uart_receive(csi_uart_t *uart, void *data, uint32_t size, uint32_t timeout) +{ + CSI_PARAM_CHK(uart, CSI_ERROR); + CSI_PARAM_CHK(data, CSI_ERROR); + + uint8_t *temp_data = (uint8_t *)data; + int32_t recv_num = 0; + uint32_t recv_start, timeout_flag = 0U; + uint32_t intr_en_status; + + recv_start = csi_tick_get_ms(); + dw_uart_regs_t *uart_base = (dw_uart_regs_t *)uart->dev.reg_base; + intr_en_status = dw_uart_get_intr_en_status(uart_base); + dw_uart_disable_recv_irq(uart_base); + + while (recv_num < (int32_t)size) { + while (!dw_uart_getready(uart_base)) { + if ((csi_tick_get_ms() - recv_start) >= timeout) { + timeout_flag = 1U; + break; + } + }; + + if (timeout_flag == 0U) { + *temp_data = dw_uart_getchar(uart_base); + temp_data++; + recv_num++; + recv_start = csi_tick_get_ms(); + } else { + break; + } + } + + dw_uart_set_intr_en_status(uart_base, intr_en_status); + + return recv_num; +} + +csi_error_t dw_uart_receive_intr(csi_uart_t *uart, void *data, uint32_t num) +{ + dw_uart_regs_t *uart_base = (dw_uart_regs_t *)HANDLE_REG_BASE(uart); + uart->rx_data = (uint8_t *)data; + uart->rx_size = num; + + dw_uart_enable_recv_irq(uart_base); + + return CSI_OK; +} + +csi_error_t csi_uart_receive_async(csi_uart_t *uart, void *data, uint32_t size) +{ + CSI_PARAM_CHK(uart, CSI_ERROR); + CSI_PARAM_CHK(data, CSI_ERROR); + CSI_PARAM_CHK(uart->callback, CSI_ERROR); + CSI_PARAM_CHK(uart->receive, CSI_ERROR); + + csi_error_t ret; + + ret = uart->receive(uart, data, size); + + if (ret == CSI_OK) { + uart->state.readable = 0U; + } + + return ret; +} + +int32_t csi_uart_send(csi_uart_t *uart, const void *data, uint32_t size, uint32_t timeout) +{ + /* check data and uart */ + CSI_PARAM_CHK(uart, CSI_ERROR); + CSI_PARAM_CHK(data, CSI_ERROR); + CSI_PARAM_CHK(size, CSI_ERROR); + + dw_uart_regs_t *uart_base; + uint8_t *ch = (uint8_t *)data; + int32_t trans_num = 0; + uint32_t send_start, timeout_flag = 0U; + uint32_t intr_en_status; + + uart_base = (dw_uart_regs_t *)uart->dev.reg_base; + /* store the status of intr */ + intr_en_status = dw_uart_get_intr_en_status(uart_base); + dw_uart_disable_trans_irq(uart_base); + + send_start = csi_tick_get_ms(); + + while (trans_num < (int32_t)size) { + while (!dw_uart_putready(uart_base)) { + if ((csi_tick_get_ms() - send_start) >= timeout) { + timeout_flag = 1U; + break; + } + }; + + if (timeout_flag == 0U) { + dw_uart_putchar(uart_base, *ch++); + /* update the timeout */ + send_start = csi_tick_get_ms(); + trans_num++; + } else { + break; + } + } + + dw_uart_set_intr_en_status(uart_base, intr_en_status); + + return trans_num; +} + +csi_error_t dw_uart_send_intr(csi_uart_t *uart, const void *data, uint32_t size) +{ + dw_uart_regs_t *uart_base = (dw_uart_regs_t *)uart->dev.reg_base; + + uart->tx_data = (uint8_t *)data; + uart->tx_size = size; + dw_uart_enable_trans_irq(uart_base); + + return CSI_OK; +} + +csi_error_t csi_uart_send_async(csi_uart_t *uart, const void *data, uint32_t size) +{ + CSI_PARAM_CHK(uart, CSI_ERROR); + CSI_PARAM_CHK(data, CSI_ERROR); + CSI_PARAM_CHK(uart->callback, CSI_ERROR); + CSI_PARAM_CHK(uart->send, CSI_ERROR); + + csi_error_t ret; + ret = uart->send(uart, data, size); + + if (ret == CSI_OK) { + uart->state.writeable = 0U; + } + + return ret; +} + +csi_error_t csi_uart_attach_callback(csi_uart_t *uart, void *callback, void *arg) +{ + CSI_PARAM_CHK(uart, CSI_ERROR); + + dw_uart_regs_t *uart_base; + uart_base = (dw_uart_regs_t *)HANDLE_REG_BASE(uart); + + uart->callback = callback; + uart->arg = arg; + uart->send = dw_uart_send_intr; + uart->receive = dw_uart_receive_intr; + csi_irq_attach((uint32_t)(uart->dev.irq_num), &dw_uart_irq_handler, &uart->dev); + csi_irq_enable((uint32_t)(uart->dev.irq_num)); + dw_uart_enable_recv_irq(uart_base); + + return CSI_OK; +} + +void csi_uart_detach_callback(csi_uart_t *uart) +{ + CSI_PARAM_CHK_NORETVAL(uart); + + dw_uart_regs_t *uart_base; + uart_base = (dw_uart_regs_t *)HANDLE_REG_BASE(uart); + + uart->callback = NULL; + uart->arg = NULL; + uart->send = NULL; + uart->receive = NULL; + dw_uart_disable_recv_irq(uart_base); + csi_irq_disable((uint32_t)(uart->dev.irq_num)); + csi_irq_detach((uint32_t)(uart->dev.irq_num)); +} + +csi_error_t csi_uart_get_state(csi_uart_t *uart, csi_state_t *state) +{ + CSI_PARAM_CHK(uart, CSI_ERROR); + CSI_PARAM_CHK(state, CSI_ERROR); + + *state = uart->state; + + return CSI_OK; +} + +static void dw_uart_dma_event_cb(csi_dma_ch_t *dma, csi_dma_event_t event, void *arg) +{ + csi_uart_t *uart = (csi_uart_t *)dma->parent; + dw_uart_regs_t *uart_base = (dw_uart_regs_t *)HANDLE_REG_BASE(uart); + + if (event == DMA_EVENT_TRANSFER_ERROR) {/* DMA transfer ERROR */ + if ((uart->tx_dma != NULL) && (uart->tx_dma->ch_id == dma->ch_id)) { + csi_dma_ch_stop(dma); + dw_uart_fifo_init(uart_base); + + uart->state.writeable = 1U; + + if (uart->callback) { + uart->callback(uart, UART_EVENT_ERROR_OVERFLOW, uart->arg); + } + } else { + csi_dma_ch_stop(dma); + dw_uart_fifo_init(uart_base); + /* enable received data available */ + dw_uart_enable_recv_irq(uart_base); + + uart->state.readable = 1U; + + if (uart->callback) { + uart->callback(uart, UART_EVENT_ERROR_FRAMING, uart->arg); + } + } + } else if (event == DMA_EVENT_TRANSFER_DONE) {/* DMA transfer complete */ + if ((uart->tx_dma != NULL) && (uart->tx_dma->ch_id == dma->ch_id)) { + + csi_dma_ch_stop(dma); + dw_uart_fifo_init(uart_base); + + uart->state.writeable = 1U; + + if (uart->callback) { + uart->callback(uart, UART_EVENT_SEND_COMPLETE, uart->arg); + } + } else { + csi_dma_ch_stop(dma); + dw_uart_fifo_init(uart_base); + /* enable received data available */ + dw_uart_enable_recv_irq(uart_base); + + uart->state.readable = 1U; + + if (uart->callback) { + uart->callback(uart, UART_EVENT_RECEIVE_COMPLETE, uart->arg); + } + } + } +} + +csi_error_t dw_uart_send_dma(csi_uart_t *uart, const void *data, uint32_t num) +{ + csi_dma_ch_config_t config; + memset(&config, 0, sizeof(csi_dma_ch_config_t)); + uint32_t fcr_reg = UART_FIFO_INIT_CONFIG; + dw_uart_regs_t *uart_base = (dw_uart_regs_t *)HANDLE_REG_BASE(uart); + csi_dma_ch_t *dma_ch = (csi_dma_ch_t *)uart->tx_dma; + + uart->tx_data = (uint8_t *)data; + uart->tx_size = num; + dw_uart_disable_recv_irq(uart_base); + dw_uart_disable_trans_irq(uart_base); + config.src_inc = DMA_ADDR_INC; + config.dst_inc = DMA_ADDR_CONSTANT; + config.src_tw = DMA_DATA_WIDTH_8_BITS; + config.dst_tw = DMA_DATA_WIDTH_8_BITS; + + /* config for wj_dma */ + config.group_len = find_max_prime_num(num); + config.trans_dir = DMA_MEM2PERH; + + /* config for etb */ + config.handshake = uart_tx_hs_num[uart->dev.idx]; + + csi_dma_ch_config(dma_ch, &config); + + fcr_reg &= ~(DW_UART_FCR_TET_Msk); + + if (config.group_len >= (UART_MAX_FIFO / 2U)) { + fcr_reg |= DW_UART_FCR_TET_FIFO_1_2_FULL; + } else if (config.group_len >= (UART_MAX_FIFO / 4U)) { + fcr_reg |= DW_UART_FCR_TET_FIFO_1_4_FULL; + } else if (config.group_len >= (UART_MAX_FIFO / 8U)) { + fcr_reg |= DW_UART_FCR_TET_FIFO_2_CHAR; + } else { + fcr_reg |= DW_UART_FCR_TET_FIFO_EMTPY; + } + + soc_dcache_clean_invalid_range((unsigned long)uart->tx_data, uart->tx_size); + dw_uart_set_fcr_reg(uart_base, fcr_reg); + csi_dma_ch_start(uart->tx_dma, (void *)uart->tx_data, (uint8_t *) & (uart_base->THR), uart->tx_size); + + return CSI_OK; +} + +csi_error_t dw_uart_receive_dma(csi_uart_t *uart, void *data, uint32_t num) +{ + csi_dma_ch_config_t config; + memset(&config, 0, sizeof(csi_dma_ch_config_t)); + csi_error_t ret = CSI_OK; + uint32_t fcr_reg = UART_FIFO_INIT_CONFIG; + dw_uart_regs_t *uart_base = (dw_uart_regs_t *)HANDLE_REG_BASE(uart); + csi_dma_ch_t *dma = (csi_dma_ch_t *)uart->rx_dma; + + dw_uart_disable_trans_irq(uart_base); + dw_uart_disable_recv_irq(uart_base); + uart->rx_data = (uint8_t *)data; + uart->rx_size = num; + config.src_inc = DMA_ADDR_CONSTANT; + config.dst_inc = DMA_ADDR_INC; + config.src_tw = DMA_DATA_WIDTH_8_BITS; + config.dst_tw = DMA_DATA_WIDTH_8_BITS; + config.group_len = find_max_prime_num(num); + config.trans_dir = DMA_PERH2MEM; + config.handshake = uart_rx_hs_num[uart->dev.idx]; + + ret = csi_dma_ch_config(dma, &config); + + if (ret == CSI_OK) { + + fcr_reg &= ~(DW_UART_FCR_RT_Msk); + + if (config.group_len >= (UART_MAX_FIFO / 2U)) { + fcr_reg |= DW_UART_FCR_RT_FIFO_1_2_FULL; + } else if (config.group_len >= (UART_MAX_FIFO / 4U)) { + fcr_reg |= DW_UART_FCR_RT_FIFO_1_4_FULL; + } else { + fcr_reg |= DW_UART_FCR_RT_FIFO_1_CHAR; + } + + soc_dcache_clean_invalid_range((unsigned long)uart->rx_data, uart->rx_size); + dw_uart_set_fcr_reg(uart_base, fcr_reg | DW_UART_FCR_RFIFOR_RESET); + csi_dma_ch_start(uart->rx_dma, (uint8_t *) & (uart_base->RBR), (void *)uart->rx_data, uart->rx_size); + } + + return ret; +} + +csi_error_t csi_uart_link_dma(csi_uart_t *uart, csi_dma_ch_t *tx_dma, csi_dma_ch_t *rx_dma) +{ + CSI_PARAM_CHK(uart, CSI_ERROR); + CSI_PARAM_CHK(uart->callback, CSI_ERROR); + csi_error_t ret = CSI_OK; + + if (tx_dma != NULL) { + tx_dma->parent = uart; + ret = csi_dma_ch_alloc(tx_dma, -1, -1); + + if (ret == CSI_OK) { + csi_dma_ch_attach_callback(tx_dma, dw_uart_dma_event_cb, NULL); + uart->tx_dma = tx_dma; + uart->send = dw_uart_send_dma; + } else { + tx_dma->parent = NULL; + } + } else { + if (uart->tx_dma) { + csi_dma_ch_detach_callback(uart->tx_dma); + csi_dma_ch_free(uart->tx_dma); + uart->tx_dma = NULL; + } + + uart->send = dw_uart_send_intr; + } + + if (ret != CSI_ERROR) { + if (rx_dma != NULL) { + rx_dma->parent = uart; + ret = csi_dma_ch_alloc(rx_dma, -1, -1); + + if (ret == CSI_OK) { + csi_dma_ch_attach_callback(rx_dma, dw_uart_dma_event_cb, NULL); + uart->rx_dma = rx_dma; + uart->receive = dw_uart_receive_dma; + } else { + rx_dma->parent = NULL; + } + } else { + if (uart->rx_dma) { + csi_dma_ch_detach_callback(uart->rx_dma); + csi_dma_ch_free(uart->rx_dma); + uart->rx_dma = NULL; + } + + uart->receive = dw_uart_receive_intr; + } + } + return ret; +} + +#ifdef CONFIG_PM +csi_error_t dw_uart_pm_action(csi_dev_t *dev, csi_pm_dev_action_t action) +{ + CSI_PARAM_CHK(dev, CSI_ERROR); + + csi_error_t ret = CSI_OK; + csi_pm_dev_t *pm_dev = &dev->pm_dev; + dw_uart_regs_t *uart_base = (dw_uart_regs_t *)dev->reg_base; + + switch (action) { + case PM_DEV_SUSPEND: + dw_uart_fifo_disable(uart_base); + dw_uart_fifo_enable(uart_base); + dw_uart_wait_idle(uart_base); + uart_base->LCR |= DW_UART_LCR_DLAB_EN; + csi_pm_dev_save_regs(pm_dev->reten_mem, (uint32_t *)dev->reg_base, 2U); + uart_base->LCR &= (~DW_UART_LCR_DLAB_EN); + csi_pm_dev_save_regs(pm_dev->reten_mem + 2, (uint32_t *)(dev->reg_base + 4U), 1U); + csi_pm_dev_save_regs(pm_dev->reten_mem + 2 + 1, (uint32_t *)(dev->reg_base + 12U), 2U); + break; + + case PM_DEV_RESUME: + dw_uart_fifo_disable(uart_base); + dw_uart_fifo_enable(uart_base); + dw_uart_wait_idle(uart_base); + uart_base->LCR |= DW_UART_LCR_DLAB_EN; + csi_pm_dev_restore_regs(pm_dev->reten_mem, (uint32_t *)dev->reg_base, 2U); + uart_base->LCR &= (~DW_UART_LCR_DLAB_EN); + csi_pm_dev_restore_regs(pm_dev->reten_mem + 2, (uint32_t *)(dev->reg_base + 4U), 1U); + csi_pm_dev_restore_regs(pm_dev->reten_mem + 2 + 1, (uint32_t *)(dev->reg_base + 12U), 2U); + break; + + default: + ret = CSI_ERROR; + break; + } + + return ret; +} + +csi_error_t csi_uart_enable_pm(csi_uart_t *uart) +{ + return csi_pm_dev_register(&uart->dev, dw_uart_pm_action, 20U, 0U); +} + +void csi_uart_disable_pm(csi_uart_t *uart) +{ + csi_pm_dev_unregister(&uart->dev); +} +#endif + diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/devices.c b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/devices.c new file mode 100644 index 00000000..3979c41d --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/devices.c @@ -0,0 +1,87 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +const csi_perip_info_t g_soc_info[] = { + {DW_UART0_BASE, DW_UART0_IRQn, 0, DEV_DW_UART_TAG}, + {DW_TIMER0_BASE, TIM0_IRQn, 0, DEV_DW_TIMER_TAG}, + {DW_TIMER1_BASE, TIM1_IRQn, 1, DEV_DW_TIMER_TAG}, + {DW_TIMER2_BASE, TIM2_IRQn, 2, DEV_DW_TIMER_TAG}, + {DW_TIMER3_BASE, TIM3_IRQn, 3, DEV_DW_TIMER_TAG}, +#if CONFIG_SUPPORT_NMI_DEMO + {DW_TIMER4_BASE, FAKE_IRQ_TIMER4, 4, DEV_DW_TIMER_TAG}, +#endif +#if defined(DW_DMA0_BASE) + {DW_DMA0_BASE, DW_DMA0_IRQn, 0, DEV_DW_AHB_DMA_TAG}, + {DW_DMA0_BASE, DW_DMA0_IRQn, 0, DEV_DW_AXI_DMA_TAG}, +#endif +#if defined(XT_IOPMP0_BASE) + {XT_IOPMP0_BASE, IOPMP0_IRQn, 0, DEV_XT_IOPMP_TAG}, +#endif + {0, 0, 0, 0} +}; + +const csi_dma_ch_info_t g_dma_chnum[] = { + {0, 8}, + {DEV_IDX_INVALID, 0}, +}; + +const uint16_t uart_tx_hs_num[1] = {}; +const uint16_t uart_rx_hs_num[1] = {}; + +const csi_dma_ch_desc_t uart0_dma_ch_list[] = { + {0xff, 0xff} +}; + +const csi_dma_ch_spt_list_t dma_spt_list[] = { + {0xFFFFU, 0xFFU, NULL}, +}; + +const csi_pinmap_t gpio_pinmap[] = { + {0xFFFFFFFFU, 0xFFU, 0xFFU, 0xFFFFFFFFU }, +}; + +const csi_pinmap_t uart_pinmap[] = { + {0xFFFFFFFFU, 0xFFU, 0xFFU, 0xFFFFFFFFU }, +}; + +const csi_clkmap_t clk_map[] = { + {0xFFFFFFFFU, 0xFFFFU, 0xFFU} +}; + +const csi_dma_handshake_ctrl_t xs0_dma0_handshake_ctrl_list[] = { + {DEV_IDX_INVALID, DEV_BLANK_TAG, 0xFFU, 0xFFU}, +}; + +const csi_dma_handshake_list_t g_handshake_list[] = { + {0, xs0_dma0_handshake_ctrl_list}, + {DEV_IDX_INVALID, NULL}, +}; diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/feature.c b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/feature.c new file mode 100644 index 00000000..018011df --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/feature.c @@ -0,0 +1,311 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +// I/D Cache will enable in cache_init +void cpu_features_init(void) +{ +#if CONFIG_CPU_XUANTIE_E901PLUS_CP || CONFIG_CPU_XUANTIE_E901PLUS_B_CP || CONFIG_CPU_XUANTIE_E901PLUS_M_CP || CONFIG_CPU_XUANTIE_E901PLUS_BM_CP + return; +#endif + +#if CONFIG_CPU_XUANTIE_E901_CP || CONFIG_CPU_XUANTIE_E901_B_CP || CONFIG_CPU_XUANTIE_E901_ZM_CP || CONFIG_CPU_XUANTIE_E901_BZM_CP + return; +#endif + +#if CONFIG_CPU_XUANTIE_E902 || CONFIG_CPU_XUANTIE_E902M + return; +#endif + +#if CONFIG_CPU_XUANTIE_E906 || CONFIG_CPU_XUANTIE_E906F || CONFIG_CPU_XUANTIE_E906FD || CONFIG_CPU_XUANTIE_E906P || CONFIG_CPU_XUANTIE_E906FP || CONFIG_CPU_XUANTIE_E906FDP + rv_csr_write(CSR_MXSTATUS, 0x440800); + rv_csr_write(CSR_MHCR, 0x103f & (~0x3)); + return; +#endif + +#if CONFIG_CPU_XUANTIE_E907 || CONFIG_CPU_XUANTIE_E907F || CONFIG_CPU_XUANTIE_E907FD || CONFIG_CPU_XUANTIE_E907P || CONFIG_CPU_XUANTIE_E907FP || CONFIG_CPU_XUANTIE_E907FDP + rv_csr_write(CSR_MXSTATUS, 0x440800); + rv_csr_write(CSR_MHINT, 0x600c); + rv_csr_write(CSR_MHCR, 0x103f & (~0x3)); + return; +#endif + + volatile unsigned int i, cpu_type, cpu_ver, cpu_tnmodel; + unsigned long version[8]; + + /* As CPUID is a fifo register, try to find + * the CPUID[0] whose index(bit[31:28]) == 0 */ + for (i = 0; i < 8; i++) { + version[0] = rv_csr_read(CSR_MCPUID); + if (((version[0]&0xf0000000) >> 28) == 0) + break; + } + + for (i = 1; i < 8; i++) + version[i] = rv_csr_read(CSR_MCPUID); + + cpu_type = (version[0] >> 18) & 0xf; + cpu_tnmodel = (version[0] >> 14) & 0x1; + cpu_ver = (version[1] >> 12) & 0xffff; + + rv_csr_write(CSR_MCOR, 0x70013); + + /* + * Warning: CSR_MCCR2 contains an L2 cache latency setting, + * you need to confirm it by your own soc design. + */ + switch (cpu_type) { + case 0x1: + if (cpu_ver >= 0x0) { + rv_csr_write(CSR_MSMPR, 0x1); + rv_csr_write(CSR_MCCR2, 0xe249000b); + rv_csr_write(CSR_MXSTATUS, 0x638000); + rv_csr_write(CSR_MHINT, 0x1ee30c); + rv_csr_write(CSR_MHCR, 0x11ff & (~0x3)); + rv_csr_write(CSR_MHINT2,0x180); + } else { + while(1); + } + break; + case 0x2: + if (cpu_ver >= 0x0) { + rv_csr_write(CSR_MSMPR, 0x1); + rv_csr_write(CSR_MCCR2, 0xa042000a); + rv_csr_write(CSR_MXSTATUS, 0x438100); + rv_csr_write(CSR_MHINT, 0x21aa10c); + rv_csr_write(CSR_MHCR, 0x10011ff & (~0x3)); + rv_csr_write(CSR_MHINT4, 0x10000080); +#if __riscv_xlen == 64 + rv_csr_write(CSR_MENVCFG, 0x4000000000000000); +#endif + } else { + while(1); + } + break; + case 0x3: + if (cpu_ver >= 0x1080 && cpu_ver <= 0x10bf) { //1.2.0~1.2.x + rv_csr_write(CSR_MCCR2, 0xe0010009); + rv_csr_write(CSR_MXSTATUS, 0x638000); + rv_csr_write(CSR_MHINT, 0x6e30c); + rv_csr_write(CSR_MHCR, 0x1ff & (~0x3)); + } else if (cpu_ver == 0x10ca) { //1.3.10 + rv_csr_write(CSR_MSMPR, 0x1); + rv_csr_write(CSR_MCCR2, 0xe2490009); + rv_csr_write(CSR_MXSTATUS, 0x638000); + rv_csr_write(CSR_MHINT, 0x66e30c); + rv_csr_write(CSR_MHCR, 0x17f & (~0x3)); + rv_csr_write(CSR_MHINT2, 0x420000); + rv_csr_write(CSR_MHINT4, 0x410); + } else if (cpu_ver >= 0x1100 && cpu_ver <= 0x113f) { //1.4.0~1.4.x + rv_csr_write(CSR_MSMPR, 0x1); + rv_csr_write(CSR_MCCR2, 0xe2490009); + rv_csr_write(CSR_MXSTATUS, 0x638000); + rv_csr_write(CSR_MHINT, 0x16e30c); + rv_csr_write(CSR_MHCR, 0x1ff & (~0x3)); + } else if (cpu_ver >= 0x1140 && cpu_ver <= 0x117f) { //1.5.0~1.5.x + rv_csr_write(CSR_MSMPR, 0x1); + rv_csr_write(CSR_MCCR2, 0xe2490009); + rv_csr_write(CSR_MXSTATUS, 0x638000); + rv_csr_write(CSR_MHINT, 0xe6e30c); + rv_csr_write(CSR_MHINT2, 0x180); + rv_csr_write(CSR_MHCR, 0x1ff & (~0x3)); + } else if (cpu_ver >= 0x1180 && cpu_ver <= 0x1183) { //1.6.0~1.6.3 + rv_csr_write(CSR_MSMPR, 0x1); + rv_csr_write(CSR_MCCR2, 0xe249000b); + rv_csr_write(CSR_MXSTATUS, 0x638000); + rv_csr_write(CSR_MHINT, 0x1ee30c); + rv_csr_write(CSR_MHINT2, 0x180); + rv_csr_write(CSR_MHCR, 0x1ff & (~0x3)); + } else if (cpu_ver >= 0x1184 && cpu_ver <= 0x123f) { //1.6.4~1.8.x + rv_csr_write(CSR_MSMPR, 0x1); + rv_csr_write(CSR_MCCR2, 0xe249000b); + rv_csr_write(CSR_MXSTATUS, 0x638000); + rv_csr_write(CSR_MHINT, 0x1ee30c); + rv_csr_write(CSR_MHINT2, 0x180); + rv_csr_write(CSR_MHCR, 0x11ff & (~0x3)); + } else if (cpu_ver >= 0x2000 && cpu_ver <= 0x200e) { //2.0.0~2.0.14 + rv_csr_write(CSR_MSMPR, 0x1); + rv_csr_write(CSR_MCCR2, 0xe249000b); + rv_csr_write(CSR_MXSTATUS, 0x438000); + rv_csr_write(CSR_MHINT, 0x31ea32c); + rv_csr_write(CSR_MHINT2, 0x180); + rv_csr_write(CSR_MHCR, 0x11ff & (~0x3)); +#if __riscv_xlen == 64 + rv_csr_write(CSR_MENVCFG, 0x4000000000000000); +#endif + } else if (cpu_ver >= 0x200f && cpu_ver <= 0x2045) { //2.0.15~2.1.5 + rv_csr_write(CSR_MSMPR, 0x1); + rv_csr_write(CSR_MCCR2, 0xe249000b); + rv_csr_write(CSR_MXSTATUS, 0x438000); + rv_csr_write(CSR_MHINT, 0x11ea32c); + rv_csr_write(CSR_MHINT2, 0x180); + rv_csr_write(CSR_MHCR, 0x11ff & (~0x3)); +#if __riscv_xlen == 64 + rv_csr_write(CSR_MENVCFG, 0x4000000000000000); +#endif + } else if (cpu_ver >= 0x2046 && cpu_ver <= 0x20c3) { //2.1.6~2.3.3 + rv_csr_write(CSR_MSMPR, 0x1); + rv_csr_write(CSR_MCCR2, 0xe249000b); + rv_csr_write(CSR_MXSTATUS, 0x438000); + rv_csr_write(CSR_MHINT, 0x31ea32c); + rv_csr_write(CSR_MHINT2, 0x180); + rv_csr_write(CSR_MHCR, 0x11ff & (~0x3)); +#if __riscv_xlen == 64 + rv_csr_write(CSR_MENVCFG, 0x4000000000000000); +#endif + } else if (cpu_ver >= 0x20c4 && cpu_ver <= 0x2fff) { //2.3.4~2.x.x + rv_csr_write(CSR_MSMPR, 0x1); + rv_csr_write(CSR_MCCR2, 0xe249000b); + rv_csr_write(CSR_MXSTATUS, 0x438100); + rv_csr_write(CSR_MHINT, 0x31ea32c); + rv_csr_write(CSR_MHINT2, 0x180); + rv_csr_write(CSR_MHCR, 0x11ff & (~0x3)); + rv_csr_write(CSR_MHINT4, 0x2080); +#if __riscv_xlen == 64 + rv_csr_write(CSR_MENVCFG, 0x4000000000000000); +#endif + } else if (cpu_ver >= 0x3000 && cpu_ver <= 0x3fff) { //3.0.0~3.x.x + rv_csr_write(CSR_MSMPR, 0x1); + rv_csr_write(CSR_MCCR2, 0xe249000b); + rv_csr_write(CSR_MXSTATUS, 0x438100); + rv_csr_write(CSR_MHINT, 0x31ea32c); + rv_csr_write(CSR_MHINT2, 0x180); + rv_csr_write(CSR_MHCR, 0x11ff & (~0x3)); + rv_csr_write(CSR_MHINT4, 0x2080); +#if __riscv_xlen == 64 + rv_csr_write(CSR_MENVCFG, 0x4000000000000000); +#endif + } else { + while(1); + } + break; + case 0x4: + if (cpu_ver >= 0x1002 && cpu_ver <= 0xffff) { + rv_csr_write(CSR_MHCR, 0x17f & (~0x3)); + rv_csr_write(CSR_MXSTATUS, 0x638000); + rv_csr_write(CSR_MHINT, 0x650c); + } else { + while(1); + } + break; + case 0x5: + if(cpu_tnmodel == 0) { //c908 + if (cpu_ver >= 0x0000 && cpu_ver <= 0x0007) { //0.0.0~0.0.7 + rv_csr_write(CSR_MSMPR, 0x1); + rv_csr_write(CSR_MCCR2, 0xe0420008); + rv_csr_write(CSR_MXSTATUS, 0x638000); + rv_csr_write(CSR_MHINT, 0x2c50c); + rv_csr_write(CSR_MHCR, 0x11ff & (~0x3)); + } else if (cpu_ver >= 0x0040 && cpu_ver <= 0x1002) { //0.1.0~1.0.2 + rv_csr_write(CSR_MSMPR, 0x1); + rv_csr_write(CSR_MCCR2, 0xa042000a); + rv_csr_write(CSR_MXSTATUS, 0x438000); + rv_csr_write(CSR_MHINT, 0x21aa10c); + rv_csr_write(CSR_MHCR, 0x10011ff & (~0x3)); +#if __riscv_xlen == 64 + rv_csr_write(CSR_MENVCFG, 0x4000000000000000); +#endif + } else if (cpu_ver >= 0x1003 && cpu_ver <= 0x100b) { //1.0.3~1.0.11 + + rv_csr_write(CSR_MSMPR, 0x1); + rv_csr_write(CSR_MCCR2, 0xa042000a); + rv_csr_write(CSR_MXSTATUS, 0x438000); + rv_csr_write(CSR_MHINT, 0x1aa10c); + rv_csr_write(CSR_MHCR, 0x10011ff & (~0x3)); +#if __riscv_xlen == 64 + rv_csr_write(CSR_MENVCFG, 0x4000000000000000); +#endif + } else if (cpu_ver >= 0x100c && cpu_ver <= 0x1fff) { //1.0.12~ + rv_csr_write(CSR_MSMPR, 0x1); + rv_csr_write(CSR_MCCR2, 0xa042000a); + rv_csr_write(CSR_MXSTATUS, 0x438100); + rv_csr_write(CSR_MHINT, 0x21aa10c); + rv_csr_write(CSR_MHCR, 0x10011ff & (~0x3)); + rv_csr_write(CSR_MHINT4, 0x10000080); +#if __riscv_xlen == 64 + rv_csr_write(CSR_MENVCFG, 0x4000000000000000); +#endif + } else if (cpu_ver >= 0x2000 && cpu_ver <= 0xffff) { //2.0.0~ + rv_csr_write(CSR_MSMPR, 0x1); + rv_csr_write(CSR_MCCR2, 0xa042000a); + rv_csr_write(CSR_MXSTATUS, 0x438100); + rv_csr_write(CSR_MHINT, 0x21aa10c); + rv_csr_write(CSR_MHCR, 0x10011ff & (~0x3)); + rv_csr_write(CSR_MHINT4, 0x10000080); +#if __riscv_xlen == 64 + rv_csr_write(CSR_MENVCFG, 0x4000000000000000); +#endif + } else { + while(1); + } + } else if (cpu_tnmodel == 1) { + if (cpu_ver >= 0x0) { + rv_csr_write(CSR_MSMPR, 0x1); + rv_csr_write(CSR_MCCR2, 0xA0420002); + rv_csr_write(CSR_MXSTATUS, 0x438100); + rv_csr_write(CSR_MHINT, 0x21AA10C); + rv_csr_write(CSR_MHCR, 0x10011FF & (~0x3)); + rv_csr_write(CSR_MHINT4, 0x10000080); +#if __riscv_xlen == 64 + rv_csr_write(CSR_MENVCFG, 0x4000000000000000); +#endif + } else { + while(1); + } + } else { + while(1); + } + break; + case 0x6: + if (cpu_ver >= 0x0) { + rv_csr_write(CSR_MSMPR, 0x1); + rv_csr_write(CSR_MCCR2, 0xA0420002); + rv_csr_write(CSR_MXSTATUS, 0x438000); + rv_csr_write(CSR_MHINT, 0x3A1AA10C); + rv_csr_write(CSR_MHCR, 0x10011BF & (~0x3)); +#if __riscv_xlen == 64 + rv_csr_write(CSR_MENVCFG, 0x4000000000000000); +#endif + } else { + while(1); + } + break; + case 0x7: + if (cpu_ver >= 0x0) { + rv_csr_clear(CSR_MXSTATUS, 0x1); + rv_csr_write(CSR_MISELECT,CSR_MNASTATUS); + rv_csr_write(CSR_MIREG,0x1e); + } else { + while(1); + } + break; + case 0x8: + if (cpu_ver >= 0x0) { + rv_csr_clear(CSR_MXSTATUS, 0x1); + rv_csr_write(CSR_MISELECT,CSR_MNASTATUS); + rv_csr_write(CSR_MIREG,0x1e); + } else { + while(1); + } + break; + default: + // FIXME: maybe qemu + break; + } +} diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/irq.c b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/irq.c new file mode 100644 index 00000000..dd38678e --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/irq.c @@ -0,0 +1,282 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include +#include + +extern uint32_t soc_irq_get_irq_num(void); +extern void soc_irq_end(uint32_t irq_num); + +#if CONFIG_AOS_OSAL +#include +#include +#define CSI_INTRPT_ENTER() aos_kernel_intrpt_enter() +#define CSI_INTRPT_EXIT() aos_kernel_intrpt_exit() +#else +#ifdef CONFIG_KERNEL_FREERTOS +#include +extern int freertos_intrpt_enter(void); +extern int freertos_intrpt_exit(void); +#define CSI_INTRPT_ENTER() freertos_intrpt_enter() +#define CSI_INTRPT_EXIT() freertos_intrpt_exit() +#elif defined(CONFIG_KERNEL_RTTHREAD) +#include +#define printk rt_kprintf +extern void rt_interrupt_enter(void); +extern void rt_interrupt_leave(void); +#define CSI_INTRPT_ENTER() rt_interrupt_enter() +#define CSI_INTRPT_EXIT() rt_interrupt_leave() +#else +#define printk printf +#define CSI_INTRPT_ENTER() +#define CSI_INTRPT_EXIT() +#endif +#endif /* end CONFIG_AOS_OSAL */ + + +#if CONFIG_INTC_IMSIC_APLIC +csi_dev_t *g_cpu_irq_table[CONFIG_NR_CPUS][CONFIG_IRQ_NUM]; +volatile msi_entry_t g_msi_map[CONFIG_NR_CPUS][CONFIG_IRQ_NUM]; +#define g_irq_table g_cpu_irq_table[csi_get_cpu_id()] +#else +csi_dev_t *g_irq_table[CONFIG_IRQ_NUM]; +#endif + +#if defined(CONFIG_SMP) && CONFIG_SMP +volatile uint32_t g_irq_nested_level[CONFIG_NR_CPUS]; +#else +volatile uint32_t g_irq_nested_level; +#endif + +/** + \brief register irq handler(deprecated). + \param[in] irq_num Number of IRQ. + \return None. +*/ +void csi_irq_attach(uint32_t irq_num, void *irq_handler, csi_dev_t *dev) +{ +#if CONFIG_INTC_IMSIC_APLIC + int cpu_id = csi_get_cpu_id(); + int msi_num = csi_imsic_irqnum_alloc(cpu_id, MSI_SOURCE_APLIC, irq_num); + g_cpu_irq_table[cpu_id][msi_num] = dev; + csi_imsic_irq_attach(cpu_id, msi_num, irq_handler); +#else + dev->irq_handler = irq_handler; + g_irq_table[irq_num] = dev; +#endif +} + +/** + \brief Attach irq handler2 for compatible(Recommended). + \param[in] irq_num Number of IRQ. + \param[in] irq_handler2 IRQ Handler. + \param[in] dev The dev to operate + \param[in] arg user data of irq_handler2 + \return None. +*/ +void csi_irq_attach2(uint32_t irq_num, void *irq_handler2, csi_dev_t *dev, void *arg) +{ +#if CONFIG_INTC_IMSIC_APLIC + int cpu_id = csi_get_cpu_id(); + int msi_num = csi_imsic_irqnum_alloc(cpu_id, MSI_SOURCE_APLIC, irq_num); + g_cpu_irq_table[cpu_id][msi_num] = dev; + csi_imsic_irq_attach2(cpu_id, msi_num, irq_handler2, arg); +#else + dev->arg = arg; + dev->irq_handler2 = irq_handler2; + g_irq_table[irq_num] = dev; +#endif +} + +/** + \brief unregister irq handler. + \param[in] irq_num Number of IRQ. + \param[in] irq_handler IRQ Handler. + \return None. +*/ +void csi_irq_detach(uint32_t irq_num) +{ +#if CONFIG_INTC_IMSIC_APLIC + int msi_num = csi_aplic_get_target_eiid(APLIC_BASE, irq_num); + int cpu_id = csi_aplic_get_target_hart(APLIC_BASE, irq_num); + CSI_ASSERT(csi_imsic_irq_detach(cpu_id, msi_num) == CSI_OK); + CSI_ASSERT(csi_imsic_irqnum_free(cpu_id, msi_num) == CSI_OK); + CSI_ASSERT(g_cpu_irq_table[cpu_id][msi_num] != NULL); + g_cpu_irq_table[cpu_id][msi_num] = NULL; +#else + g_irq_table[irq_num] = NULL; +#endif +} + +/** + \brief gets whether in irq context + \return true or false. +*/ +bool csi_irq_context(void) +{ +#if defined(CONFIG_SMP) && CONFIG_SMP + return ((g_irq_nested_level[csi_get_cpu_id()] > 0U) ? true : false); +#else + return ((g_irq_nested_level > 0U) ? true : false); +#endif +} + +static volatile int g_nmi_cnt; +__attribute__((weak)) void handle_nmi_exception(void) +{ + g_nmi_cnt++; +#if CONFIG_SUPPORT_NMI_DEMO + extern void timer_clear_irq(); + timer_clear_irq(); +#endif +} + +//FIXME: For Non CLIC mode +extern void tick_irq_handler(void *arg); +void CORET_IRQHandler(void) +{ +#if defined(CONFIG_SMP) && CONFIG_SMP + g_irq_nested_level[csi_get_cpu_id()]++; +#else + g_irq_nested_level++; +#endif + CSI_INTRPT_ENTER(); + tick_irq_handler(NULL); + CSI_INTRPT_EXIT(); +#if defined(CONFIG_SMP) && CONFIG_SMP + g_irq_nested_level[csi_get_cpu_id()]--; +#else + g_irq_nested_level--; +#endif +} + +#if CONFIG_ECC_L1_ENABLE || CONFIG_ECC_L2_ENABLE +static struct { + int err_cnt_l1; + int err_cnt_l2; +} g_ecc_stat; + +void __attribute__((weak)) ecc_l1_irqhandler(void *arg) +{ + g_ecc_stat.err_cnt_l1++; + + if (!(__get_MCER() >> 31) || (__get_MCER() & (0x1 << 30))) { + /* may be ecc fatal error happens */ + while (1); + } else { + /* clear MCER EE_VLD */ +#if __riscv_xlen == 32 + __set_MCER(0); + __set_MCERH(0); +#else + __set_MCER(0); +#endif + } +} + +void __attribute__((weak)) ecc_l2_irqhandler(void *arg) +{ + g_ecc_stat.err_cnt_l2++; + +#if __riscv_xlen == 32 + if((__get_MCER2H() >> 30) == 0x2) { + /* clear MCER EE_VLD */ + __set_MCER2(0); + __set_MCER2H(0); + } else { + /* may be ecc fatal error happens */ + while (1); + } +#else + if((__get_MCER2() >> 62) == 0x2) { + /* clear MCER EE_VLD */ + __set_MCER2(0); + } else { + /* may be ecc fatal error happens */ + while (1); + } +#endif +} + +void ECC_L1_IRQHandler(void) +{ +#if defined(CONFIG_SMP) && CONFIG_SMP + g_irq_nested_level[csi_get_cpu_id()]++; +#else + g_irq_nested_level++; +#endif + CSI_INTRPT_ENTER(); + ecc_l1_irqhandler(NULL); + CSI_INTRPT_EXIT(); +#if defined(CONFIG_SMP) && CONFIG_SMP + g_irq_nested_level[csi_get_cpu_id()]--; +#else + g_irq_nested_level--; +#endif +} +#endif /* CONFIG_ECC_L1_ENABLE || CONFIG_ECC_L2_ENABLE */ + +/** + \brief dispatching irq handlers(only handle external irq) + \return None. +*/ +void do_irq(void) +{ + uint32_t irqn; + +#if defined(CONFIG_SMP) && CONFIG_SMP + g_irq_nested_level[csi_get_cpu_id()]++; +#else + g_irq_nested_level++; +#endif + CSI_INTRPT_ENTER(); + irqn = soc_irq_get_irq_num(); + + if (irqn > sizeof(g_irq_table) / sizeof(g_irq_table[0]) - 1 ) { + printk("undefined interrupt: irqn = 0x%x\n", irqn); + while(1); + } + if (g_irq_table[irqn]) { + if (g_irq_table[irqn]->irq_handler) { + /* for compatibility */ + g_irq_table[irqn]->irq_handler(g_irq_table[irqn]); + } + else if (g_irq_table[irqn]->irq_handler2) { + g_irq_table[irqn]->irq_handler2(irqn, g_irq_table[irqn]->arg); + } + else { + printk("undefined interrupt2: irqn = 0x%x\n", irqn); + /*the interrupt has no registered isr*/ + while(1); + } + } else { + printk("null irq_handler: irqn = 0x%x\n", irqn); + while(1); + } + + soc_irq_end(irqn); + CSI_INTRPT_EXIT(); +#if defined(CONFIG_SMP) && CONFIG_SMP + g_irq_nested_level[csi_get_cpu_id()]--; +#else + g_irq_nested_level--; +#endif +} diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/irq_port.c b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/irq_port.c new file mode 100644 index 00000000..8caa0588 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/irq_port.c @@ -0,0 +1,147 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include + +void soc_irq_enable(uint32_t irq_num) +{ + csi_vic_enable_irq((int32_t)irq_num); +} + +void soc_irq_disable(uint32_t irq_num) +{ + csi_vic_disable_irq((int32_t)irq_num); +} + +bool soc_irq_is_enabled(uint32_t irq_num) +{ + bool ret; + + if (csi_vic_get_enabled_irq((int32_t)irq_num)) { + ret = true; + } else { + ret = false; + } + + return ret; +} + +void soc_irq_priority(uint32_t irq_num, uint32_t priority) +{ + csi_vic_set_prio((int32_t)irq_num, priority); +} + +/** + * @brief get irq vector num + * @return irq no + */ +uint32_t soc_irq_get_irq_num(void) +{ + int hartid = csi_get_cpu_id(); +#if CONFIG_INTC_CLIC + (void) hartid; +#if CONFIG_RISCV_SMODE + return (__get_SCAUSE() & 0x3FFU); +#else + return (__get_MCAUSE() & 0x3FFU); +#endif /* CONFIG_RISCV_SMODE */ +#endif /* CONFIG_INTC_CLIC */ + +#if CONFIG_INTC_PLIC || CONFIG_INTC_CLIC_PLIC + uint32_t num; +#if CONFIG_RISCV_SMODE + uint32_t irqn = __get_SCAUSE() & 0x3FFU; +#else + uint32_t irqn = __get_MCAUSE() & 0x3FFU; +#endif /* CONFIG_RISCV_SMODE */ + if (irqn == Machine_External_IRQn || irqn == Supervisor_External_IRQn) { +#if CONFIG_RISCV_SMODE + num = PLIC_Hn_MSCLAIM_VAL(&PLIC->PLIC_H0_SCLAIM, hartid); +#else + num = PLIC_Hn_MSCLAIM_VAL(&PLIC->PLIC_H0_MCLAIM, hartid); +#endif +#if CONFIG_INTC_CLIC_PLIC + num += PLIC_IRQ_OFFSET; +#endif + } else { + num = irqn; + } + return num; +#endif /* CONFIG_INTC_PLIC || CONFIG_INTC_CLIC_PLIC */ + +#if CONFIG_INTC_APLIC || CONFIG_INTC_CLIC_APLIC + uint32_t num; +#if CONFIG_RISCV_SMODE + uint32_t irqn = __get_SCAUSE() & 0x3FFU; +#else + uint32_t irqn = __get_MCAUSE() & 0x3FFU; +#endif /* CONFIG_RISCV_SMODE */ + if (irqn == Machine_External_IRQn || irqn == Supervisor_External_IRQn) { + num = csi_aplic_read_claimi(APLIC_BASE, hartid); +#if CONFIG_INTC_CLIC_APLIC + num += APLIC_IRQ_OFFSET; +#endif + } else { + num = irqn; + } + return num; +#endif /* CONFIG_INTC_APLIC || CONFIG_INTC_CLIC_APLIC */ + +#if CONFIG_INTC_IMSIC_APLIC + return g_handing_msi_num[hartid]; +#endif +} + +void soc_irq_end(uint32_t irq_num) +{ +#if CONFIG_INTC_CLIC + // DO NOTHING +#endif /* CONFIG_INTC_CLIC */ + + /** + * If aplic works in msi-mode + * and the current interrupt is level-triggered + * need retrigger + */ +#if CONFIG_INTC_IMSIC_APLIC + extern csi_dev_t *g_cpu_irq_table[CONFIG_NR_CPUS][CONFIG_IRQ_NUM]; + csi_aplic_retrigger_level_irq(APLIC_BASE, g_cpu_irq_table[csi_get_cpu_id()][irq_num]->irq_num); +#endif + + +#if CONFIG_INTC_PLIC || CONFIG_INTC_CLIC_PLIC +#if CONFIG_INTC_CLIC_PLIC + if (irq_num <= PLIC_IRQ_OFFSET) { + return; + } + irq_num -= PLIC_IRQ_OFFSET; +#endif /* CONFIG_INTC_CLIC_PLIC */ +#if CONFIG_RISCV_SMODE + PLIC_Hn_MSCLAIM_VAL(&PLIC->PLIC_H0_SCLAIM, csi_get_cpu_id()) = irq_num; +#else + PLIC_Hn_MSCLAIM_VAL(&PLIC->PLIC_H0_MCLAIM, csi_get_cpu_id()) = irq_num; +#endif +#endif /* CONFIG_INTC_PLIC || CONFIG_INTC_CLIC_PLIC */ + +#if CONFIG_INTC_APLIC || CONFIG_INTC_CLIC_APLIC + // DO NOTHING +#endif /* CONFIG_INTC_APLIC || CONFIG_INTC_CLIC_APLIC */ +} diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/pre_main.c b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/pre_main.c new file mode 100644 index 00000000..99e207c5 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/pre_main.c @@ -0,0 +1,103 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file pre_main.c + * @brief source file for the pre_main + * @version V1.0 + * @date 04. April 2024 + ******************************************************************************/ + +#include +#include +#include + +extern unsigned long __heap_start; +extern unsigned long __heap_end; +unsigned long g_heap_start = (unsigned long)&__heap_start; +unsigned long g_heap_end = (unsigned long)&__heap_end; + +extern int main(void); +/* + * The ranges of copy from/to are specified by following symbols + * __erodata: LMA of start of the section to copy from. Usually end of rodata + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ +void section_data_copy(void) +{ + extern unsigned long __erodata; + extern unsigned long __data_start__; + extern unsigned long __data_end__; + + if (((unsigned long)&__erodata != (unsigned long)&__data_start__)) { + unsigned long src_addr = (unsigned long)&__erodata; + memcpy((void *)(&__data_start__), \ + (void *)src_addr, \ + (unsigned long)(&__data_end__) - (unsigned long)(&__data_start__)); + } +} + +void section_ram_code_copy(void) +{ + extern unsigned long __erodata; + extern unsigned long __data_start__; + extern unsigned long __data_end__; + extern unsigned long __ram_code_start__; + extern unsigned long __ram_code_end__; + + if (((unsigned long)&__erodata != (unsigned long)&__data_start__)) { + unsigned long src_addr = (unsigned long)&__erodata; + src_addr += (unsigned long)(&__data_end__) - (unsigned long)(&__data_start__); + memcpy((void *)(&__ram_code_start__), \ + (void *)src_addr, \ + (unsigned long)(&__ram_code_end__) - (unsigned long)(&__ram_code_start__)); + } +} + +/* + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ +void section_bss_clear(void) +{ + extern unsigned long __bss_start__; + extern unsigned long __bss_end__; + + memset((void *)(&__bss_start__), \ + 0, \ + (unsigned long)(&__bss_end__) - (unsigned long)(&__bss_start__)); + +} + +__attribute__((weak)) void pre_main(void) +{ +#if (!defined(CONFIG_KERNEL_RHINO)) && (!defined(CONFIG_NUTTXMM_NONE)) \ + && (!defined(CONFIG_KERNEL_FREERTOS)) && (!defined(CONFIG_KERNEL_RTTHREAD)) \ + && (!defined(CONFIG_KERNEL_THREADX)) + extern void mm_heap_initialize(void); + mm_heap_initialize(); +#endif + + main(); +} diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/sys_clk.c b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/sys_clk.c new file mode 100644 index 00000000..f79105e8 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/sys_clk.c @@ -0,0 +1,100 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include + +uint32_t g_system_clock = IHS_VALUE; + +#if CONFIG_BOARD_XIAOHUI_EVB +uint32_t soc_get_cpu_freq(uint32_t idx) +{ +#ifndef CONFIG_CPU_FREQ_HZ + return 50*1000000; +#else + return CONFIG_CPU_FREQ_HZ; +#endif +} + +uint32_t soc_get_coretim_freq(void) +{ + return 25*1000000; +} + +uint32_t soc_get_uart_freq(uint32_t idx) +{ + return 36*1000000; +} + +uint32_t soc_get_timer_freq(uint32_t idx) +{ + return 25*1000000; +} + +#else +uint32_t soc_get_cpu_freq(uint32_t idx) +{ + return g_system_clock; +} + +uint32_t soc_get_cur_cpu_freq(void) +{ + return g_system_clock; +} + +uint32_t soc_get_coretim_freq(void) +{ + return g_system_clock; +} + +uint32_t soc_get_uart_freq(uint32_t idx) +{ + return g_system_clock; +} + +csi_error_t soc_sysclk_config(system_clk_config_t *config) +{ + return CSI_OK; +} + +void soc_reset_uart(uint32_t idx) +{ +} + +uint32_t soc_get_timer_freq(uint32_t idx) +{ + return g_system_clock; +} +#endif + +void soc_clk_enable(int32_t module) +{ +} + +void soc_clk_disable(int32_t module) +{ +} + +void soc_set_sys_freq(uint32_t val) +{ + g_system_clock = val; +} + + diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/target_get.c b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/target_get.c new file mode 100644 index 00000000..da53b1df --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/target_get.c @@ -0,0 +1,240 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +/****************************************************************************** + * @file target_get.c + * @brief CSI Source File for target API + * @version V1.0 + * @date 9. April 2020 + ******************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include + +extern const csi_perip_info_t g_soc_info[]; +extern const csi_dma_ch_bit_spt_list_t dma_spt_list[]; +extern const csi_dma_handshake_list_t g_handshake_list[]; + +csi_error_t target_get(csi_dev_tag_t dev_tag, uint32_t idx, csi_dev_t *dev) +{ + csi_error_t ret = CSI_OK; + csi_perip_info_t *info; + + if (dev == NULL) { + ret = CSI_ERROR; + } + + ///< 使用包å«å¤–设基地å€ï¼Œå¤–设中断å·ï¼Œå¤–设设备å·ï¼Œå¤–设设备类型æˆå‘˜çš„结构体数组å˜é‡åˆå§‹åŒ–info + info = (csi_perip_info_t *)&g_soc_info; + + ///< 获å–ç›¸åº”çš„è®¾å¤‡ç±»åž‹å’Œè®¾å¤‡å· + while (info->reg_base) { + if ((info->dev_tag == (uint16_t)dev_tag) && (info->idx == (uint8_t)idx)) { + break; + } + + info++; + } + + ///< åˆå§‹åŒ–设备的统一å¥æŸ„：基地å€ï¼Œä¸­æ–­å·ï¼Œè®¾å¤‡å·ï¼Œè®¾å¤‡ç±»åž‹ + if (info->reg_base == 0U) { + ret = CSI_ERROR; + } + + if (ret != CSI_ERROR) { + dev->reg_base = info->reg_base; + dev->irq_num = info->irq_num; + dev->idx = info->idx; + dev->dev_tag = (uint16_t)dev_tag; + } + + return ret; +} + +uint32_t target_pin_to_devidx(pin_name_t pin_name, const csi_pinmap_t *pinmap) +{ + const csi_pinmap_t *map = pinmap; + uint32_t ret = 0xFFFFFFFFU; + + while ((uint32_t)map->pin_name != 0xFFFFFFFFU) { + if ((map->pin_name == pin_name) && (csi_pin_get_mux(pin_name) == map->pin_func)) { + ret = map->idx; + break; + } + + map++; + } + + return ret; +} + +uint32_t target_pin_to_channel(pin_name_t pin_name, const csi_pinmap_t *pinmap) +{ + const csi_pinmap_t *map = pinmap; + uint32_t ret = 0xFFFFFFFFU; + + while ((uint32_t)map->pin_name != 0xFFFFFFFFU) { + if (map->pin_name == pin_name) { + ret = (uint32_t)map->channel; + break; + } + + map++; + } + + return ret; +} + +pin_name_t target_gpio_to_pin(uint8_t gpio_idx, uint8_t channel, const csi_pinmap_t *pinmap) +{ + const csi_pinmap_t *map = pinmap; + pin_name_t ret = (pin_name_t)0xFFU; + + while ((uint32_t)map->pin_name != 0xFFFFFFFFU) { + if ((map->idx == gpio_idx) && (map->channel == channel)) { + ret = map->pin_name; + break; + } + + map++; + } + + return ret; +} + +csi_error_t target_get_optimal_dma_channel(void *dma_list, uint32_t ctrl_num, csi_dev_t *parent_dev, void *ch_info) +{ + uint32_t spt_id, ch_id; + uint16_t ctrl_id = 0; + uint16_t index = 0; + csi_dma_t **list = (csi_dma_t **)dma_list; + csi_dma_ch_desc_t *dma_ch_info = (csi_dma_ch_desc_t *)ch_info; + + if (parent_dev == NULL) + { + /* the MEM2MEM mode */ + for (ctrl_id = 0U; ctrl_id < ctrl_num; ctrl_id++) + { + if (list[ctrl_id] == NULL) + { + continue; + } + + for (ch_id = 0U; ch_id < list[ctrl_id]->ch_num; ch_id++) + { + if (!(list[ctrl_id]->alloc_status & ((uint32_t)1 << ch_id))) + { + dma_ch_info->ch_idx = ch_id; + dma_ch_info->ctrl_idx = (uint8_t)ctrl_id; + /* find the channel */ + return CSI_OK; + } + } + } + } + else + { + /* the MEM2PERH mode or PERH2MEM mode */ + for (spt_id = 0U; dma_spt_list[spt_id].parent_dev_id != DEV_IDX_INVALID; spt_id++) + { + if ((dma_spt_list[spt_id].parent_dev_id == parent_dev->idx)) + { + const csi_dma_ch_bit_desc_t *dev_ch_info = dma_spt_list[spt_id].ch_list; + + for (index = 0U; dev_ch_info[index].ctrl_idx != DEV_IDX_INVALID; index++) + { + uint16_t tem_idx = dev_ch_info[index].ctrl_idx; + for (ch_id = 0U; ch_id < list[tem_idx]->ch_num; ch_id++) + { + + if (!(list[tem_idx]->alloc_status & ((uint32_t)1 << ch_id)) && (dev_ch_info[index].ch_bit_info & ((uint32_t)1 << ch_id))) + { + dma_ch_info->ch_idx = ch_id; + dma_ch_info->ctrl_idx = (uint8_t)tem_idx; + return CSI_OK; + } + } + } + return CSI_ERROR; + } + + } + } + return CSI_ERROR; +} + +csi_error_t target_get_check_dma_access(uint32_t ctrl_idx, void *srcaddr, void *dstaddr, void **dma_base_src_addr, void **dma_base_dst_addr) +{ + *dma_base_src_addr = srcaddr; + *dma_base_dst_addr = dstaddr; + return CSI_OK; +} + +csi_error_t target_get_dma_handshake(uint16_t dma_id, uint16_t dev_id, uint16_t dev_tag, uint8_t type, uint16_t *handshake) +{ + const csi_dma_handshake_list_t *handshake_list = &g_handshake_list[0]; + uint16_t index = 0; + uint8_t dma_found_flag = 0; + uint8_t dev_found_flag = 0; + + for (index = 0; handshake_list[index].ctrl_idx != DEV_IDX_INVALID; index++) + { + if (handshake_list[index].ctrl_idx == dma_id) + { + dma_found_flag = 0x1; + break; + } + } + + if (!dma_found_flag) + { + return CSI_UNSUPPORTED; + } + + const csi_dma_handshake_ctrl_t *handshake_ctrl_list = handshake_list[index].handshake_ctrl_list; + + for (index = 0; handshake_ctrl_list[index].parent_dev_id != DEV_IDX_INVALID; index++) + { + if (handshake_ctrl_list[index].parent_dev_id == dev_id && handshake_ctrl_list[index].dev_tag == dev_tag) + { + if (type == DMA_HANDSHAKE_TYPE_RX && handshake_ctrl_list[index].rx_hs != DMA_HANDSHAKE_NONE) + { + *handshake = handshake_ctrl_list[index].rx_hs; + dev_found_flag = 0x1; + } + else if (type == DMA_HANDSHAKE_TYPE_TX && handshake_ctrl_list[index].tx_hs != DMA_HANDSHAKE_NONE) + { + *handshake = handshake_ctrl_list[index].tx_hs; + dev_found_flag = 0x1; + } + break; + } + } + + if (!dev_found_flag) + { + return CSI_UNSUPPORTED; + } + return CSI_OK; +} diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/tick.c b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/tick.c new file mode 100644 index 00000000..1f121916 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/tick.c @@ -0,0 +1,341 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define __WEAK __attribute__((weak)) + +// from 1970-01-01 00:00:00 UTC +static volatile uint64_t timestamp_us_offset; + +#if defined(CONFIG_SMP) && CONFIG_SMP +static volatile uint32_t csi_tick[CONFIG_NR_CPUS] = {0U}; +#else +static volatile uint32_t csi_tick = 0U; +#endif +static volatile uint32_t last_time_ms = 0U; +static volatile uint64_t last_time_us = 0U; + +#ifdef CONFIG_TIMER_FOR_TICK +static csi_timer_t tick_timer; +#ifndef CONFIG_TICK_TIMER_IDX +#define CONFIG_TICK_TIMER_IDX 0U +#endif +#else /* !CONFIG_TIMER_FOR_TICK */ +static csi_dev_t tick_dev; +static volatile uint64_t timer_init_value = 0U; +#endif + +void csi_tick_increase(void) +{ +#if defined(CONFIG_SMP) && CONFIG_SMP + csi_tick[csi_get_cpu_id()]++; +#else + csi_tick++; +#endif +} + +uint32_t csi_tick_get(void) +{ +#if defined(CONFIG_SMP) && CONFIG_SMP + return csi_tick[csi_get_cpu_id()]; +#else + return csi_tick; +#endif +} + +#ifdef CONFIG_TIMER_FOR_TICK +void tick_event_cb(csi_timer_t *timer_handle, void *arg) +{ + csi_tick_increase(); +#if CONFIG_AOS_OSAL + extern void aos_sys_tick_handler(void); + aos_sys_tick_handler(); +#else +#ifdef CONFIG_KERNEL_FREERTOS + extern void xPortSysTickHandler(void); + xPortSysTickHandler(); +#elif defined(CONFIG_KERNEL_RTTHREAD) + extern void rt_tick_increase(void); + rt_tick_increase(); +#elif defined(CONFIG_KERNEL_THREADX) + extern void _tx_timer_interrupt(void); + _tx_timer_interrupt(); +#else +#endif +#endif /* end CONFIG_AOS_OSAL */ +} +#else /* !CONFIG_TIMER_FOR_TICK */ +void tick_irq_handler(void *arg) +{ + csi_tick_increase(); + csi_coret_config((soc_get_coretim_freq() / CONFIG_SYSTICK_HZ), tick_dev.irq_num); +#if CONFIG_AOS_OSAL + extern void aos_sys_tick_handler(void); + aos_sys_tick_handler(); +#else +#ifdef CONFIG_KERNEL_FREERTOS + extern void xPortSysTickHandler(void); + xPortSysTickHandler(); +#elif defined(CONFIG_KERNEL_RTTHREAD) + extern void rt_tick_increase(void); + rt_tick_increase(); +#elif defined(CONFIG_KERNEL_THREADX) + extern void _tx_timer_interrupt(void); + _tx_timer_interrupt(); +#else +#endif +#endif /* end CONFIG_AOS_OSAL */ + +} +#endif /* CONFIG_TIMER_FOR_TICK */ + +csi_error_t csi_tick_init(void) +{ +#if defined(CONFIG_SMP) && CONFIG_SMP + csi_tick[csi_get_cpu_id()] = 0; +#else + csi_tick = 0U; +#endif + +#ifdef CONFIG_TIMER_FOR_TICK + csi_error_t ret = csi_timer_init(&tick_timer, CONFIG_TICK_TIMER_IDX); + if (ret == CSI_OK) { + ret = csi_timer_attach_callback(&tick_timer, tick_event_cb, NULL); + if (ret == CSI_OK) { + ret = csi_timer_start(&tick_timer, (1000000U / CONFIG_SYSTICK_HZ)); + } + } + return ret; +#else /* !CONFIG_TIMER_FOR_TICK */ +#if CONFIG_RISCV_SMODE + tick_dev.irq_num = Supervisor_Timer_IRQn; +#else + tick_dev.irq_num = CORET_IRQn; +#endif +#if CONFIG_CPU_XUANTIE_E9XX || CONFIG_INTC_CLIC || CONFIG_INTC_CLIC_PLIC || CONFIG_INTC_CLIC_APLIC + csi_vic_set_prio(tick_dev.irq_num, 2); + csi_irq_attach(tick_dev.irq_num, &tick_irq_handler, &tick_dev); +#endif /* CONFIG_CPU_XUANTIE_E9XX || CONFIG_INTC_CLIC || CONFIG_INTC_CLIC_PLIC || CONFIG_INTC_CLIC_APLIC */ + timer_init_value = csi_coret_get_value2(); + csi_coret_reset_value2(); + csi_coret_config((soc_get_coretim_freq() / CONFIG_SYSTICK_HZ), tick_dev.irq_num); + csi_coret_irq_enable(); +#endif /* CONFIG_TIMER_FOR_TICK */ + return CSI_OK; +} + +void csi_tick_uninit(void) +{ +#ifdef CONFIG_TIMER_FOR_TICK + csi_timer_stop(&tick_timer); + csi_timer_uninit(&tick_timer); +#else + csi_coret_irq_disable(); +#if CONFIG_CPU_XUANTIE_E9XX || CONFIG_INTC_CLIC_PLIC + csi_irq_detach(tick_dev.irq_num); +#endif +#endif /* CONFIG_TIMER_FOR_TICK */ +} + +#ifdef CONFIG_TIMER_FOR_TICK +uint32_t csi_tick_get_ms(void) +{ + uint32_t time = last_time_ms, freq; + freq = csi_timer_get_load_value(&tick_timer) * CONFIG_SYSTICK_HZ; + + while (freq) { + time = (csi_tick * (1000U / CONFIG_SYSTICK_HZ)) + ((csi_timer_get_load_value(&tick_timer) - csi_timer_get_remaining_value(&tick_timer)) / (freq / 1000U)); + + if (time >= last_time_ms) { + break; + } + } + + last_time_ms = time; + return time; +} + +uint64_t csi_tick_get_us(void) +{ + uint64_t time, freq; + uint32_t temp; + freq = soc_get_timer_freq(CONFIG_TICK_TIMER_IDX); + + while (1) { + /* the time of coretim pass */ + temp = csi_timer_get_load_value(&tick_timer) - csi_timer_get_remaining_value(&tick_timer); + time = ((uint64_t)temp * 1000U) / (freq / 1000U); + /* the time of csi_tick */ + time += ((uint64_t)csi_tick * (1000000U / CONFIG_SYSTICK_HZ)); + + if (time >= last_time_us) { + break; + } + } + + last_time_us = time; + return time; +} + +static void _mdelay(void) +{ + uint32_t load = csi_timer_get_load_value(&tick_timer); + uint32_t start_r = csi_timer_get_remaining_value(&tick_timer); + uint32_t cur_r; + uint32_t cnt = (soc_get_timer_freq(CONFIG_TICK_TIMER_IDX) / 1000U); + + while (1) { + cur_r = csi_timer_get_remaining_value(&tick_timer); + + if (start_r > cur_r) { + if ((start_r - cur_r) >= cnt) { + break; + } + } else { + if (((load - cur_r) + start_r) >= cnt) { + break; + } + } + } +} + +static void _10udelay(void) +{ + uint32_t load = csi_timer_get_load_value(&tick_timer); + uint32_t start_r = csi_timer_get_remaining_value(&tick_timer); + uint32_t cur_r; + uint32_t cnt = (soc_get_timer_freq(CONFIG_TICK_TIMER_IDX) / 100000U); + + while (1) { + cur_r = csi_timer_get_remaining_value(&tick_timer); + + if (start_r > cur_r) { + if ((start_r - cur_r) >= cnt) { + break; + } + } else { + if (((load - cur_r) + start_r) >= cnt) { + break; + } + } + } +} + +#else /* !CONFIG_TIMER_FOR_TICK */ + +uint32_t csi_tick_get_ms(void) +{ + uint32_t time; + + time = (uint32_t)((csi_coret_get_value2() - timer_init_value) * 1000U / (uint64_t)soc_get_coretim_freq()); + last_time_ms = time; + return time; +} + +uint64_t csi_tick_get_us(void) +{ + uint64_t time; + + time = (csi_coret_get_value2() - timer_init_value) * 1000U * 1000U / (uint64_t)soc_get_coretim_freq(); + last_time_us = time; + return time; +} + +static void _mdelay(void) +{ + uint64_t start = csi_coret_get_value2(); + uint64_t cur; + uint32_t cnt = (soc_get_coretim_freq() / 1000U); + + while (1) { + cur = csi_coret_get_value2(); + + if (start > cur) { + if ((start - cur) >= cnt) { + break; + } + } else { + if (cur - start >= cnt) { + break; + } + } + } +} + +static void _10udelay(void) +{ + uint64_t cur; + uint64_t start = csi_coret_get_value2(); + uint32_t cnt = (soc_get_coretim_freq() / 1000U / 100U); + + while (1) { + cur = csi_coret_get_value2(); + + if (start > cur) { + if ((start - cur) >= cnt) { + break; + } + } else { + if (cur - start >= cnt) { + break; + } + } + } +} +#endif + +void csi_set_calendar_us(uint64_t timestamp) +{ + timestamp_us_offset = timestamp; +} + +uint64_t csi_get_calendar_us(void) +{ + return csi_tick_get_us() + timestamp_us_offset; +} + +__WEAK void mdelay(uint32_t ms) +{ + while (ms) { + ms--; + _mdelay(); + } +} + +/** + * Ps: At least delay over 10us +*/ +void udelay(uint32_t us) +{ + us /= 10U; + + while (us) { + us--; + _10udelay(); + } +} + diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/weak.c b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/weak.c new file mode 100644 index 00000000..d6e32655 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/weak.c @@ -0,0 +1,58 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file weak.c + * @brief source file for the weak + * @version V1.0 + * @date 04. April 2024 + ******************************************************************************/ + +#include +#include +#include + +__WEAK void soc_dcache_clean_invalid_range(unsigned long addr, uint32_t size) +{ + csi_dcache_clean_invalid_range((unsigned long *)addr, size); +} + +__WEAK void soc_dcache_clean_invalid_all(void) +{ + csi_dcache_clean_invalid(); +} + +__WEAK void soc_dcache_invalid_range(unsigned long addr, uint32_t size) +{ + csi_dcache_invalid_range((unsigned long *)addr, size); +} + +__WEAK void soc_dcache_clean(void) +{ + csi_dcache_clean(); +} + +__WEAK void soc_icache_invalid(void) +{ + csi_icache_invalid(); +} + +__WEAK unsigned long soc_dma_address_remap(unsigned long addr) +{ + return addr; +} diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/README.txt b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/README.txt new file mode 100644 index 00000000..bb1bf4a3 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/README.txt @@ -0,0 +1 @@ +Just include csi_core.h! diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/core_rv32.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/core_rv32.h new file mode 100644 index 00000000..c46e8428 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/core_rv32.h @@ -0,0 +1,1452 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +/****************************************************************************** + * @file core_rv32.h + * @brief CSI RV32 Core Peripheral Access Layer Header File + * @version V1.0 + * @date 01. Sep 2018 + ******************************************************************************/ + +#ifndef __CORE_RV32_H_GENERIC +#define __CORE_RV32_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * CSI definitions + ******************************************************************************/ +/** + \ingroup RV32 + @{ + */ + +#ifndef __RV32 +#define __RV32 (0x01U) +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_RV32_H_GENERIC */ + +#ifndef __CSI_GENERIC + +#ifndef __CORE_RV32_H_DEPENDANT +#define __CORE_RV32_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#ifndef __RV32_REV +#define __RV32_REV 0x0000U +#endif + +#ifndef __VIC_PRIO_BITS +#define __VIC_PRIO_BITS 2U +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 1U +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 1U +#endif + +#ifndef __ICACHE_PRESENT +#define __ICACHE_PRESENT 1U +#endif + +#ifndef __DCACHE_PRESENT +#define __DCACHE_PRESENT 1U +#endif + +#include + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CSI_glob_defs CSI Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group RV32 */ + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core CLIC Register + ******************************************************************************/ +/** + \defgroup CSI_core_register Defines and Type Definitions + \brief Type definitions and defines for CK80X processor based devices. +*/ + +/** + \ingroup CSI_core_register + \defgroup CSI_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \ingroup CSI_core_register + \defgroup CSI_CLIC Core-Local Interrupt Controller (CLIC) + \brief Type definitions for the CLIC Registers + @{ + */ + +/** + \brief Access to the structure of a vector interrupt controller. + */ +typedef struct { + __IOM uint8_t IP; /*!< Offset: 0x000 (R/W) Interrupt set pending register */ + __IOM uint8_t IE; /*!< Offset: 0x004 (R/W) Interrupt set enable register */ + __IOM uint8_t ATTR; /*!< Offset: 0x008 (R/W) Interrupt set attribute register */ + __IOM uint8_t CTL; /*!< Offset: 0x00C (R/W) Interrupt control register */ +} CLIC_INT_Control; + +typedef struct { + __IOM uint32_t CLICCFG:8; /*!< Offset: 0x000 (R/W) CLIC configure register */ + __IM uint32_t CLICINFO; + __IOM uint32_t MINTTHRESH; + uint32_t RESERVED[1021]; + CLIC_INT_Control CLICINT[4096]; +} CLIC_Type; + +#define CLIC_INFO_CLICINTCTLBITS_Pos 21U +#define CLIC_INFO_CLICINTCTLBITS_Msk (0xFUL << CLIC_INFO_CLICINTCTLBITS_Pos) + +#define CLIC_INTIP_IP_Pos 0U /*!< CLIC INTIP: IP Position */ +#define CLIC_INTIP_IP_Msk (0x1UL << CLIC_INTIP_IP_Pos) /*!< CLIC INTIP: IP Mask */ + +#define CLIC_INTIE_IE_Pos 0U /*!< CLIC INTIE: IE Position */ +#define CLIC_INTIE_IE_Msk (0x1UL << CLIC_INTIE_IE_Pos) /*!< CLIC INTIE: IE Mask */ + +#define CLIC_INTIE_T_Pos 7U /*!< CLIC INTIE: T Position */ +#define CLIC_INTIE_T_Msk (0x1UL << CLIC_INTIE_T_Pos) /*!< CLIC INTIE: T Mask */ + +#define CLIC_INTATTR_TRIG_Pos 1U /*!< CLIC INTATTR: TRIG Position */ +#define CLIC_INTATTR_TRIG_Msk (0x3UL << CLIC_INTATTR_TRIG_Pos) /*!< CLIC INTATTR: TRIG Mask */ + +#define CLIC_INTATTR_SHV_Pos 0U /*!< CLIC INTATTR: SHV Position */ +#define CLIC_INTATTR_SHV_Msk (0x1UL << CLIC_INTATTR_SHV_Pos) /*!< CLIC INTATTR: SHV Mask */ + +#define CLIC_INTCFG_NVBIT_Pos 5U /*!< CLIC INTCFG: NVBIT Position */ +#define CLIC_INTCFG_NVBIT_Msk (0x1UL << CLIC_INTCFG_NVBIT_Pos) /*!< CLIC INTCFG: NVBIT Mask */ + +#define CLIC_INTCFG_PRIO_Pos 5U /*!< CLIC INTCFG: INTCFG Position */ +#define CLIC_INTCFG_PRIO_Msk (0x7UL << CLIC_INTCFG_PRIO_Pos) /*!< CLIC INTCFG: INTCFG Mask */ + +#define CLIC_CLICCFG_NVBIT_Pos 0U /*!< CLIC CLICCFG: NVBIT Position */ +#define CLIC_CLICCFG_NVBIT_Msk (0x1UL << CLIC_CLICCFG_NVBIT_Pos) /*!< CLIC CLICCFG: NVBIT Mask */ + +#define CLIC_CLICCFG_NLBIT_Pos 1U /*!< CLIC CLICCFG: NLBIT Position */ +#define CLIC_CLICCFG_NLBIT_Msk (0xFUL << CLIC_CLICCFG_NLBIT_Pos) /*!< CLIC CLICCFG: NLBIT Mask */ + +#define CLIC_CLICCFG_NMBIT_Pos 5U /*!< CLIC CLICCFG: NMBIT Position */ +#define CLIC_CLICCFG_NMBIT_Msk (0x3UL << CLIC_CLICCFG_NMBIT_Pos) /*!< CLIC CLICCFG: NMBIT Mask */ + +/*@} end of group CSI_CLIC */ + +/** + \ingroup CSI_core_register + \defgroup CSI_PMP Physical Memory Protection (PMP) + \brief Type definitions for the PMP Registers + @{ + */ + +#define PMP_PMPCFG_R_Pos 0U /*!< PMP PMPCFG: R Position */ +#define PMP_PMPCFG_R_Msk (0x1UL << PMP_PMPCFG_R_Pos) /*!< PMP PMPCFG: R Mask */ + +#define PMP_PMPCFG_W_Pos 1U /*!< PMP PMPCFG: W Position */ +#define PMP_PMPCFG_W_Msk (0x1UL << PMP_PMPCFG_W_Pos) /*!< PMP PMPCFG: W Mask */ + +#define PMP_PMPCFG_X_Pos 2U /*!< PMP PMPCFG: X Position */ +#define PMP_PMPCFG_X_Msk (0x1UL << PMP_PMPCFG_X_Pos) /*!< PMP PMPCFG: X Mask */ + +#define PMP_PMPCFG_A_Pos 3U /*!< PMP PMPCFG: A Position */ +#define PMP_PMPCFG_A_Msk (0x3UL << PMP_PMPCFG_A_Pos) /*!< PMP PMPCFG: A Mask */ + +#define PMP_PMPCFG_L_Pos 7U /*!< PMP PMPCFG: L Position */ +#define PMP_PMPCFG_L_Msk (0x1UL << PMP_PMPCFG_L_Pos) /*!< PMP PMPCFG: L Mask */ + +typedef enum { + REGION_SIZE_4B = -1, + REGION_SIZE_8B = 0, + REGION_SIZE_16B = 1, + REGION_SIZE_32B = 2, + REGION_SIZE_64B = 3, + REGION_SIZE_128B = 4, + REGION_SIZE_256B = 5, + REGION_SIZE_512B = 6, + REGION_SIZE_1KB = 7, + REGION_SIZE_2KB = 8, + REGION_SIZE_4KB = 9, + REGION_SIZE_8KB = 10, + REGION_SIZE_16KB = 11, + REGION_SIZE_32KB = 12, + REGION_SIZE_64KB = 13, + REGION_SIZE_128KB = 14, + REGION_SIZE_256KB = 15, + REGION_SIZE_512KB = 16, + REGION_SIZE_1MB = 17, + REGION_SIZE_2MB = 18, + REGION_SIZE_4MB = 19, + REGION_SIZE_8MB = 20, + REGION_SIZE_16MB = 21, + REGION_SIZE_32MB = 22, + REGION_SIZE_64MB = 23, + REGION_SIZE_128MB = 24, + REGION_SIZE_256MB = 25, + REGION_SIZE_512MB = 26, + REGION_SIZE_1GB = 27, + REGION_SIZE_2GB = 28, + REGION_SIZE_4GB = 29, + REGION_SIZE_8GB = 30, + REGION_SIZE_16GB = 31 +} region_size_e; + +typedef enum { + ADDRESS_MATCHING_TOR = 1, + ADDRESS_MATCHING_NAPOT = 3 +} address_matching_e; + +typedef struct { + uint32_t r: 1; /* readable enable */ + uint32_t w: 1; /* writeable enable */ + uint32_t x: 1; /* execable enable */ + address_matching_e a: 2; /* address matching mode */ + uint32_t reserved: 2; /* reserved */ + uint32_t l: 1; /* lock enable */ +} pmp_region_attr_t; + +/*@} end of group CSI_PMP */ + +/* CACHE Register Definitions */ +#define CACHE_MHCR_BTB_Pos 12U /*!< CACHE MHCR: BTB Position */ +#define CACHE_MHCR_BTB_Msk (0x1UL << CACHE_MHCR_BTB_Pos) /*!< CACHE MHCR: WA Mask */ + +#define CACHE_MHCR_BPE_Pos 5U /*!< CACHE MHCR: BPE Position */ +#define CACHE_MHCR_BPE_Msk (0x1UL << CACHE_MHCR_BPE_Pos) /*!< CACHE MHCR: BPE Mask */ + +#define CACHE_MHCR_RS_Pos 4U /*!< CACHE MHCR: RS Position */ +#define CACHE_MHCR_RS_Msk (0x1UL << CACHE_MHCR_RS_Pos) /*!< CACHE MHCR: RS Mask */ + +#define CACHE_MHCR_WA_Pos 3U /*!< CACHE MHCR: WA Position */ +#define CACHE_MHCR_WA_Msk (0x1UL << CACHE_MHCR_WA_Pos) /*!< CACHE MHCR: WA Mask */ + +#define CACHE_MHCR_WB_Pos 2U /*!< CACHE MHCR: WB Position */ +#define CACHE_MHCR_WB_Msk (0x1UL << CACHE_MHCR_WB_Pos) /*!< CACHE MHCR: WB Mask */ + +#define CACHE_MHCR_DE_Pos 1U /*!< CACHE MHCR: DE Position */ +#define CACHE_MHCR_DE_Msk (0x1UL << CACHE_MHCR_DE_Pos) /*!< CACHE MHCR: DE Mask */ + +#define CACHE_MHCR_IE_Pos 0U /*!< CACHE MHCR: IE Position */ +#define CACHE_MHCR_IE_Msk (0x1UL << CACHE_MHCR_IE_Pos) /*!< CACHE MHCR: IE Mask */ + +#if CONFIG_CPU_XUANTIE_E902 || CONFIG_CPU_XUANTIE_E902M || CONFIG_CPU_XUANTIE_E902T || CONFIG_CPU_XUANTIE_E902MT \ + || CONFIG_CPU_XUANTIE_E901PLUS_CP || CONFIG_CPU_XUANTIE_E901PLUS_B_CP || CONFIG_CPU_XUANTIE_E901PLUS_M_CP || CONFIG_CPU_XUANTIE_E901PLUS_BM_CP \ + || CONFIG_CPU_XUANTIE_E901_CP || CONFIG_CPU_XUANTIE_E901_B_CP || CONFIG_CPU_XUANTIE_E901_ZM_CP || CONFIG_CPU_XUANTIE_E901_BZM_CP +#define CACHE_INV_ADDR_Pos 4U +#else +#define CACHE_INV_ADDR_Pos 5U +#endif +#define CACHE_INV_ADDR_Msk (0xFFFFFFFFUL << CACHE_INV_ADDR_Pos) + +/*@} end of group CSI_CACHE */ + +/** + \ingroup CSI_core_register + \defgroup CSI_SYSMAP system map (SYSMAP) + \brief Type definitions for the SYSMAP Registers + @{ + */ + +#define SYSMAP_SYSMAPCFG_B_Pos 0U /*!< SYSMAP SYSMAPCFG: B Position */ +#define SYSMAP_SYSMAPCFG_B_Msk (0x1UL << SYSMAP_SYSMAPCFG_B_Pos) /*!< SYSMAP SYSMAPCFG: B Mask */ + +#define SYSMAP_SYSMAPCFG_C_Pos 1U /*!< SYSMAP SYSMAPCFG: C Position */ +#define SYSMAP_SYSMAPCFG_C_Msk (0x1UL << SYSMAP_SYSMAPCFG_C_Pos) /*!< SYSMAP SYSMAPCFG: C Mask */ + +#define SYSMAP_SYSMAPCFG_SO_Pos 2U /*!< SYSMAP SYSMAPCFG: SO Position */ +#define SYSMAP_SYSMAPCFG_SO_Msk (0x1UL << SYSMAP_SYSMAPCFG_SO_Pos) /*!< SYSMAP SYSMAPCFG: SO Mask */ + +/** + \ingroup CSI_core_register + \defgroup CSI_SYSMAP system map (SYSMAP) + \brief Type definitions for the SYSMAP Registers + @{ + */ +typedef struct { + __IOM uint32_t SYSMAPADDR0; /*!< Offset: 0x000 (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPCFG0; /*!< Offset: 0x004 (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPADDR1; /*!< Offset: 0x008 (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPCFG1; /*!< Offset: 0x00c (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPADDR2; /*!< Offset: 0x010 (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPCFG2; /*!< Offset: 0x014 (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPADDR3; /*!< Offset: 0x018 (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPCFG3; /*!< Offset: 0x01c (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPADDR4; /*!< Offset: 0x020 (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPCFG4; /*!< Offset: 0x024 (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPADDR5; /*!< Offset: 0x028 (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPCFG5; /*!< Offset: 0x02c (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPADDR6; /*!< Offset: 0x030 (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPCFG6; /*!< Offset: 0x034 (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPADDR7; /*!< Offset: 0x038 (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPCFG7; /*!< Offset: 0x03c (R/W) SYSMAP configure register */ +} SYSMAP_Type; + + +/*@} end of group CSI_SYSMAP */ + + +/** + \ingroup CSI_core_register + \defgroup CSI_SysTick System Tick Timer (CORET) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief The data structure of the access system timer. + */ +typedef struct { + __IOM unsigned long long MTIMECMP; /*!< Offset: 0x000 (R/W) Timer compare register */ + uint32_t RESERVED[8188]; + __IM unsigned long long MTIME; /*!< Offset: 0x7FF8 (R) Timer current register */ +} CORET_Type; + +/*@} end of group CSI_SysTick */ + +/** + \ingroup CSI_core_register + \defgroup CSI_DCC + \brief Type definitions for the DCC. + @{ + */ + +/** + \brief Access to the data structure of DCC. + */ +typedef struct { + uint32_t RESERVED0[13U]; + __IOM uint32_t HCR; /*!< Offset: 0x034 (R/W) */ + __IM uint32_t EHSR; /*!< Offset: 0x03C (R/ ) */ + uint32_t RESERVED1[6U]; + union { + __IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) Data exchange register CPU read*/ + __OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) Data exchange register CPU writer*/ + }; + +} DCC_Type; + +#define DCC_HCR_JW_Pos 18U /*!< DCC HCR: jw_int_en Position */ +#define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /*!< DCC HCR: jw_int_en Mask */ + +#define DCC_HCR_JR_Pos 19U /*!< DCC HCR: jr_int_en Position */ +#define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /*!< DCC HCR: jr_int_en Mask */ + +#define DCC_EHSR_JW_Pos 1U /*!< DCC EHSR: jw_vld Position */ +#define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /*!< DCC EHSR: jw_vld Mask */ + +#define DCC_EHSR_JR_Pos 2U /*!< DCC EHSR: jr_vld Position */ +#define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /*!< DCC EHSR: jr_vld Mask */ + +/*@} end of group CSI_DCC */ + + +/** + \ingroup CSI_core_register + \defgroup CSI_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CSI_core_bitfield */ + +/** + \ingroup CSI_core_register + \defgroup CSI_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of THEAD CPU */ +#ifndef CONFIG_TCIP_BASE +#define CONFIG_TCIP_BASE 0xE0000000UL +#endif +#define CORET_BASE (CONFIG_TCIP_BASE + 0x4000UL) /*!< CORET Base Address */ +#define CLIC_BASE (CONFIG_TCIP_BASE + 0x800000UL) /*!< CLIC Base Address */ + +#define SYSMAP_BASE (0xEFFFF000UL) /*!< SYSMAP Base Address */ + +#define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */ +#define CLIC ((CLIC_Type *) CLIC_BASE ) /*!< CLIC configuration struct */ +#define SYSMAP ((SYSMAP_Type *) SYSMAP_BASE ) /*!< SYSMAP configuration struct */ + +/*@} */ + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core VIC Functions + - Core CORET Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CSI_Core_FunctionInterface Functions and Instructions Reference +*/ + +/** + \brief Get current hartid + \return hartid + */ +__STATIC_INLINE int csi_get_cpu_id(void) +{ + unsigned long result; + __ASM volatile("csrr %0, mhartid" : "=r"(result) : : "memory"); + return result; +} + +/** + \brief Get cache line size + \return cache line size + */ +__STATIC_INLINE int csi_get_cache_line_size(void) +{ +#if CONFIG_CPU_XUANTIE_E902 || CONFIG_CPU_XUANTIE_E902M || CONFIG_CPU_XUANTIE_E902T || CONFIG_CPU_XUANTIE_E902MT \ + || CONFIG_CPU_XUANTIE_E901PLUS_CP || CONFIG_CPU_XUANTIE_E901PLUS_B_CP || CONFIG_CPU_XUANTIE_E901PLUS_M_CP || CONFIG_CPU_XUANTIE_E901PLUS_BM_CP \ + || CONFIG_CPU_XUANTIE_E901_CP || CONFIG_CPU_XUANTIE_E901_B_CP || CONFIG_CPU_XUANTIE_E901_ZM_CP || CONFIG_CPU_XUANTIE_E901_BZM_CP + return 16; +#else + return 32; +#endif +} + +/* ########################## VIC functions #################################### */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_VICFunctions VIC Functions + \brief Functions that manage interrupts and exceptions via the VIC. + @{ + */ + +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 5UL) ) +#define _IP2_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +/** + \brief Enable External Interrupt + \details Enable a device-specific interrupt in the VIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_vic_enable_irq(int32_t IRQn) +{ + CLIC->CLICINT[IRQn].IE |= CLIC_INTIE_IE_Msk; + __DSB(); +} + +/** + \brief Disable External Interrupt + \details Disable a device-specific interrupt in the VIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_vic_disable_irq(int32_t IRQn) +{ + CLIC->CLICINT[IRQn].IE &= ~CLIC_INTIE_IE_Msk; + __DSB(); +} + +/** + \brief Check Interrupt is Enabled or not + \details Read the enabled register in the VIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not enabled. + \return 1 Interrupt status is enabled. + */ +__STATIC_INLINE uint32_t csi_vic_get_enabled_irq(int32_t IRQn) +{ + return (uint32_t)(CLIC->CLICINT[IRQn].IE & CLIC_INTIE_IE_Msk); +} + +/** + \brief Check Interrupt is Pending or not + \details Read the pending register in the VIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn) +{ + return (uint32_t)(CLIC->CLICINT[IRQn].IP & CLIC_INTIP_IP_Msk); +} + +/** + \brief Set Pending Interrupt + \details Set the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn) +{ + CLIC->CLICINT[IRQn].IP |= CLIC_INTIP_IP_Msk; + __DSB(); +} + +/** + \brief Clear Pending Interrupt + \details Clear the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn) +{ + CLIC->CLICINT[IRQn].IP &= ~CLIC_INTIP_IP_Msk; + __DSB(); +} + +/** + \brief Set Interrupt Priority + \details Set the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority) +{ + uint8_t nlbits = (CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos; + uint8_t ctl = CLIC->CLICINT[IRQn].CTL; + ctl <<= nlbits; + ctl >>= nlbits; + CLIC->CLICINT[IRQn].CTL = ctl | (priority << (8 - nlbits)); + __DSB(); +} + +/** + \brief Get Interrupt Priority + \details Read the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t csi_vic_get_prio(int32_t IRQn) +{ + uint8_t nlbits = (CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos; + return CLIC->CLICINT[IRQn].CTL >> (8 - nlbits); +} + +/** + \brief Get Interrupt thresh + \details Read the thresh of interrupt + Only the interrupt priority is greater than the value of thresh, the interrupt can be responded to + \return Interrupt thresh value(0~255). + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t csi_vic_get_thresh(void) +{ + return CLIC->MINTTHRESH >> 24; +} + +/** + \brief Set Interrupt thresh + \details Write the thresh of interrupt + Only the interrupt priority is greater than the value of thresh, the interrupt can be responded to + \param [in] Interrupt thresh value(0~255). + */ +__STATIC_INLINE uint32_t csi_vic_set_thresh(uint32_t thresh) +{ + uint32_t temp = CLIC->MINTTHRESH; + uint8_t nlbits = (CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos; + + if(!nlbits) + CLIC->MINTTHRESH = 0xff << 24; + + CLIC->MINTTHRESH = thresh << 24; + __DSB(); + return temp; +} + +/*@} end of CSI_Core_VICFunctions */ + +/* ########################## PMP functions #################################### */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_PMPFunctions PMP Functions + \brief Functions that manage interrupts and exceptions via the VIC. + @{ + */ + +/** + \brief configure physical memory protection region. + \details + \param [in] idx memory protection region (0, 1, 2, ..., 15). + \param [in] base_addr base address must be aligned with page size. + \param [in] size \ref region_size_e. memory protection region size. + \param [in] attr \ref pmp_region_attr_t. memory protection region attribute. + \param [in] enable enable or disable memory protection region. + */ +__STATIC_INLINE void csi_pmp_config_region(uint32_t idx, unsigned long base_addr, region_size_e size, + pmp_region_attr_t attr, uint32_t enable) +{ + uint8_t pmpxcfg = 0; + uint32_t addr = 0; + + if (idx > 15) { + return; + } + + if (!enable) { + attr.a = (address_matching_e)0; + } + + if (attr.a == ADDRESS_MATCHING_TOR) { + addr = base_addr >> 2; + } else { + if (size == REGION_SIZE_4B) { + addr = base_addr >> 2; + attr.a = (address_matching_e)2; + } else { + addr = ((base_addr >> 2) & (0xFFFFFFFFU - ((1 << (size + 1)) - 1))) | ((1 << size) - 1); + } + } + + __set_PMPADDRx(idx, addr); + + pmpxcfg |= (attr.r << PMP_PMPCFG_R_Pos) | (attr.w << PMP_PMPCFG_W_Pos) | + (attr.x << PMP_PMPCFG_X_Pos) | (attr.a << PMP_PMPCFG_A_Pos) | + (attr.l << PMP_PMPCFG_L_Pos); + + __set_PMPxCFG(idx, pmpxcfg); +} + +/** + \brief disable physical memory protection region by idx. + \details + \param [in] idx memory protection region (0, 1, 2, ..., 15). + */ +__STATIC_INLINE void csi_pmp_disable_region(uint32_t idx) +{ + __set_PMPxCFG(idx, __get_PMPxCFG(idx) & (~PMP_PMPCFG_A_Msk)); +} + +/*@} end of CSI_Core_PMPFunctions */ + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +__STATIC_INLINE uint32_t _csi_coret_config(unsigned long coret_base, uint64_t ticks, int32_t IRQn) +{ + CORET_Type *coret = (CORET_Type *)coret_base; + if ((coret->MTIMECMP != 0) && (coret->MTIMECMP != 0xFFFFFFFFFFFFFFFFULL)) { + coret->MTIMECMP = coret->MTIMECMP + ticks; + } else { + coret->MTIMECMP = coret->MTIME + ticks; + } + return (0UL); +} + +/** + \brief CORE timer Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \param [in] IRQn core timer Interrupt number. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t csi_coret_config(uint64_t ticks, int32_t IRQn) +{ + return _csi_coret_config(CORET_BASE, ticks, IRQn); +} + +/** + \brief get CORE timer reload value + \return CORE timer counter value(64bit). + */ +__STATIC_INLINE uint64_t csi_coret_get_load2(void) +{ + return CORET->MTIMECMP; +} + +/** + \brief get CORE timer reload value(deprecated) + \return CORE timer counter value. + */ +__STATIC_INLINE unsigned long csi_coret_get_load(void) +{ + return CORET->MTIMECMP & 0xFFFFFFFF; +} + +/** + \brief get CORE timer reload high value(deprecated) + \return CORE timer counter value. + */ +__STATIC_INLINE uint32_t csi_coret_get_loadh(void) +{ + return (CORET->MTIMECMP >> 32) & 0xFFFFFFFF; +} + +/** + \brief get CORE timer counter value + \return CORE timer counter value(64bit). + */ +__STATIC_INLINE uint64_t csi_coret_get_value2(void) +{ + return CORET->MTIME; +} + +/** + \brief get CORE timer counter value(deprecated) + \return CORE timer counter value. + */ +__STATIC_INLINE unsigned long csi_coret_get_value(void) +{ + return CORET->MTIME & 0xFFFFFFFF; +} + +/** + \brief get CORE timer counter high value(deprecated) + \return CORE timer counter value. + */ +__STATIC_INLINE uint32_t csi_coret_get_valueh(void) +{ + return (CORET->MTIME >> 32) & 0xFFFFFFFF; +} + +__STATIC_INLINE void csi_coret_reset_value2() +{ + CORET_Type *coret = (CORET_Type *)CORET_BASE; + coret->MTIMECMP = 0; +} + +/** + \brief Enable CoreTimer(within clint) Interrupts + */ +__ALWAYS_STATIC_INLINE void csi_coret_irq_enable(void) +{ + extern void soc_irq_enable(uint32_t irq_num); + return soc_irq_enable(7); +} + +/** + \brief Disable CoreTimer(within clint) Interrupts + */ +__ALWAYS_STATIC_INLINE void csi_coret_irq_disable(void) +{ + extern void soc_irq_disable(uint32_t irq_num); + return soc_irq_disable(7); +} + +/*@} end of CSI_Core_SysTickFunctions */ + +/* ########################## SYSMAP functions #################################### */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_SYSMAPFunctions SYSMAP Functions + \brief Functions that manage system map attribute + @{ + */ + +/** + \brief Get SYSMAPCFGx Register by index + \details Returns the content of the SYSMAPxCFG Register. + \param [in] idx SYSMAP region index + \return SYSMAPxCFG Register value + */ +__STATIC_INLINE uint8_t __get_SYSMAPCFGx(uint32_t idx) +{ + switch (idx) { + case 0: + return SYSMAP->SYSMAPCFG0; + case 1: + return SYSMAP->SYSMAPCFG1; + case 2: + return SYSMAP->SYSMAPCFG2; + case 3: + return SYSMAP->SYSMAPCFG3; + case 4: + return SYSMAP->SYSMAPCFG4; + case 5: + return SYSMAP->SYSMAPCFG5; + case 6: + return SYSMAP->SYSMAPCFG6; + case 7: + return SYSMAP->SYSMAPCFG7; + default: + return 0; + } +} + +/** + \brief Set SYSMAPCFGx by index + \details Writes the given value to the SYSMAPxCFG Register. + \param [in] idx SYSMAPx region index + \param [in] sysmapxcfg SYSMAPxCFG Register value to set + */ +__STATIC_INLINE void __set_SYSMAPCFGx(uint32_t idx, uint32_t sysmapxcfg) +{ + switch (idx) { + case 0: + SYSMAP->SYSMAPCFG0 = sysmapxcfg; + break; + case 1: + SYSMAP->SYSMAPCFG1 = sysmapxcfg; + break; + case 2: + SYSMAP->SYSMAPCFG2 = sysmapxcfg; + break; + case 3: + SYSMAP->SYSMAPCFG3 = sysmapxcfg; + break; + case 4: + SYSMAP->SYSMAPCFG4 = sysmapxcfg; + break; + case 5: + SYSMAP->SYSMAPCFG5 = sysmapxcfg; + break; + case 6: + SYSMAP->SYSMAPCFG6 = sysmapxcfg; + break; + case 7: + SYSMAP->SYSMAPCFG7 = sysmapxcfg; + break; + default: + return; + } +} + +/** + \brief Get SYSMAPADDRx Register by index + \details Returns the content of the SYSMAPADDRx Register. + \param [in] idx SYSMAP region index + \return SYSMAPADDRx Register value + */ +__STATIC_INLINE uint32_t __get_SYSMAPADDRx(uint32_t idx) +{ + switch(idx) { + case 0: + return SYSMAP->SYSMAPADDR0; + case 1: + return SYSMAP->SYSMAPADDR1; + case 2: + return SYSMAP->SYSMAPADDR2; + case 3: + return SYSMAP->SYSMAPADDR3; + case 4: + return SYSMAP->SYSMAPADDR4; + case 5: + return SYSMAP->SYSMAPADDR5; + case 6: + return SYSMAP->SYSMAPADDR6; + case 7: + return SYSMAP->SYSMAPADDR7; + default: + return 0; + } +} + +/** + \brief Set SYSMAPADDRx by index + \details Writes the given value to the SYSMAPADDRx Register. + \param [in] idx SYSMAP region index + \param [in] sysmapaddr SYSMAPADDRx Register value to set + */ +__STATIC_INLINE void __set_SYSMAPADDRx(uint32_t idx, uint32_t sysmapxaddr) +{ + switch (idx) { + case 0: + SYSMAP->SYSMAPADDR0 = sysmapxaddr; + break; + case 1: + SYSMAP->SYSMAPADDR1 = sysmapxaddr; + break; + case 2: + SYSMAP->SYSMAPADDR2 = sysmapxaddr; + break; + case 3: + SYSMAP->SYSMAPADDR3 = sysmapxaddr; + break; + case 4: + SYSMAP->SYSMAPADDR4 = sysmapxaddr; + break; + case 5: + SYSMAP->SYSMAPADDR5 = sysmapxaddr; + break; + case 6: + SYSMAP->SYSMAPADDR6 = sysmapxaddr; + break; + case 7: + SYSMAP->SYSMAPADDR7 = sysmapxaddr; + break; + default: + return; + } +} + +/** + \brief configure system map attribute. + \details + \param [in] idx system map region (0, 1, 2, ..., 7). + \param [in] base_addr base address must be aligned with page size. + \param [in] enable enable or disable memory protected region. + */ +__STATIC_INLINE void csi_sysmap_config_region(uint32_t idx, uint32_t base_addr, uint32_t attr) +{ + uint32_t addr = 0; + + if (idx > 7) { + return; + } + + addr = base_addr >> 12; + attr = attr << 2; + + __set_SYSMAPADDRx(idx, addr); + __set_SYSMAPCFGx(idx, attr); +} + +/*@} end of CSI_Core_SYSMAPFunctions */ + +/* ########################## Cache functions #################################### */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/** + \brief whether I-Cache enable + */ +__STATIC_INLINE int csi_icache_is_enable() +{ + uint32_t cache = __get_MHCR(); + return (cache & CACHE_MHCR_IE_Msk) >> CACHE_MHCR_IE_Pos; +} + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void csi_icache_enable (void) +{ +#if (__ICACHE_PRESENT == 1U) + if (!csi_icache_is_enable()) { + uint32_t cache; + __DSB(); + __ICACHE_IALL(); + cache = __get_MHCR(); + cache |= CACHE_MHCR_IE_Msk; + __set_MHCR(cache); + __DSB(); + } +#endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void csi_icache_disable (void) +{ +#if (__ICACHE_PRESENT == 1U) + if (csi_icache_is_enable()) { + uint32_t cache; + __DSB(); + cache = __get_MHCR(); + cache &= ~CACHE_MHCR_IE_Msk; /* disable icache */ + __set_MHCR(cache); + __ICACHE_IALL(); /* invalidate all icache */ + __DSB(); + } +#endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void csi_icache_invalid (void) +{ +#if (__ICACHE_PRESENT == 1U) + __DSB(); + __ICACHE_IALL(); /* invalidate all icache */ + __DSB(); +#endif +} + +/** + \brief whether D-Cache enable + */ +__STATIC_INLINE int csi_dcache_is_enable() +{ + uint32_t cache = __get_MHCR(); + return (cache & CACHE_MHCR_DE_Msk) >> CACHE_MHCR_DE_Pos; +} + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void csi_dcache_enable (void) +{ +#if (__DCACHE_PRESENT == 1U) + if (!csi_dcache_is_enable()) { + uint32_t cache; + __DSB(); + __DCACHE_IALL(); /* invalidate all dcache */ + cache = __get_MHCR(); + cache |= CACHE_MHCR_DE_Msk; /* enable dcache */ + __set_MHCR(cache); + + __DSB(); + } +#endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void csi_dcache_disable (void) +{ +#if (__DCACHE_PRESENT == 1U) + if (csi_dcache_is_enable()) { + uint32_t cache; + __DSB(); + cache = __get_MHCR(); + cache &= ~(uint32_t)CACHE_MHCR_DE_Msk; /* disable all Cache */ + __set_MHCR(cache); + __DCACHE_IALL(); /* invalidate all Cache */ + __DSB(); + } +#endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void csi_dcache_invalid (void) +{ +#if (__DCACHE_PRESENT == 1U) + __DSB(); + __DCACHE_IALL(); /* invalidate all Cache */ + __DSB(); +#endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void csi_dcache_clean (void) +{ +#if (__DCACHE_PRESENT == 1U) + __DSB(); + __DCACHE_CALL(); /* clean all Cache */ + __DSB(); +#endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void csi_dcache_clean_invalid (void) +{ +#if (__DCACHE_PRESENT == 1U) + __DSB(); + __DCACHE_CIALL(); /* clean and inv all Cache */ + __DSB(); +#endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void csi_dcache_invalid_range (unsigned long *addr, size_t dsize) +{ +#if (__DCACHE_PRESENT == 1U) + int linesize = csi_get_cache_line_size(); + long op_size = dsize + (unsigned long)addr % linesize; + unsigned long op_addr = (unsigned long)addr & CACHE_INV_ADDR_Msk; + + __DSB(); + + while (op_size > 0) { + __DCACHE_IPA(op_addr); + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); +#endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void csi_dcache_clean_range (unsigned long *addr, size_t dsize) +{ + +#if (__DCACHE_PRESENT == 1U) + int linesize = csi_get_cache_line_size(); + long op_size = dsize + (unsigned long)addr % linesize; + unsigned long op_addr = (unsigned long) addr & CACHE_INV_ADDR_Msk; + + __DSB(); + + while (op_size > 0) { + __DCACHE_CPA(op_addr); + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); +#endif + +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 16-byte boundary) + \param[in] dsize size of memory block (aligned to 16-byte boundary) +*/ +__STATIC_INLINE void csi_dcache_clean_invalid_range (unsigned long *addr, size_t dsize) +{ +#if (__DCACHE_PRESENT == 1U) + int linesize = csi_get_cache_line_size(); + long op_size = dsize + (unsigned long)addr % linesize; + unsigned long op_addr = (unsigned long) addr & CACHE_INV_ADDR_Msk; + + __DSB(); + + while (op_size > 0) { + __DCACHE_CIPA(op_addr); + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); +#endif +} + +/*@} end of CSI_Core_CacheFunctions */ + +#if (CONFIG_CPU_XUANTIE_E907 || CONFIG_CPU_XUANTIE_E907F || CONFIG_CPU_XUANTIE_E907FD || CONFIG_CPU_XUANTIE_E907P || CONFIG_CPU_XUANTIE_E907FP || CONFIG_CPU_XUANTIE_E907FDP) +/** + \ingroup CSI_tcm_register + \defgroup CSI_TCM + \brief Type definitions for the tcm Registers + @{ + */ + +/** + \brief Consortium definition for accessing protection area selection register(MITCMCR, csr<0x7f9>). + */ +typedef union { + struct { + uint32_t EN: 1; /*!< bit: 0 Instruction Tightly-Coupled Memory enable */ + uint32_t _reserved0: 1; /*!< bit: 1 Reserved */ + uint32_t _reserved1: 1; /*!< bit: 2 Reserved */ + uint32_t _reserved2: 1; /*!< bit: 3 Reserved */ + uint32_t Size: 4; /*!< bit: 4..7 Size of ITCM */ + uint32_t _reserved4: 4; /*!< bit: 8..11 Reserved */ + uint32_t Base_Address: 20; /*!< bit: 12..31 Base address of ITCM */ + } b; /*!< Structure Access by bit */ + uint32_t w; /*!< Type Access by whole register */ +} MITCMCR_Type; + +#define MITCMCR_Base_Address_Pos 12U /*!< MITCMCR: Base_Address Position */ +#define MITCMCR_Base_Address_Msk (0xfffffUL << MITCMCR_Base_Address_Pos) /*!< MITCMCR: Base_Address Mask */ + +#define MITCMCR_Size_Pos 4U /*!< MITCMCR: Size Position */ +#define MITCMCR_Size_Msk (0xfUL << MITCMCR_Size_Pos) /*!< MITCMCR: Size Mask */ + +#define MITCMCR_EN_Pos 0U /*!< MITCMCR: EN Position */ +#define MITCMCR_EN_Msk (0x1UL << MITCMCR_EN_Pos) /*!< MITCMCR: EN Mask */ + +/** + \brief Consortium definition for accessing protection area selection register(MDTCMCR, csr<0x7f8>). + */ +typedef union { + struct { + uint32_t EN: 1; /*!< bit: 0 Instruction Tightly-Coupled Memory enable */ + uint32_t _reserved0: 1; /*!< bit: 1 Reserved */ + uint32_t _reserved1: 1; /*!< bit: 2 Reserved */ + uint32_t _reserved2: 1; /*!< bit: 3 Reserved */ + uint32_t Size: 4; /*!< bit: 4..7 Size of DTCM */ + uint32_t _reserved4: 4; /*!< bit: 8..11 Reserved */ + uint32_t Base_Address: 20; /*!< bit: 12..31 Base address of DTCM */ + } b; /*!< Structure Access by bit */ + uint32_t w; /*!< Type Access by whole register */ +} MDTCMCR_Type; + +#define MDTCMCR_Base_Address_Pos 12U /*!< MDTCMCR: Base_Address Position */ +#define MDTCMCR_Base_Address_Msk (0xfffffUL << MDTCMCR_Base_Address_Pos) /*!< MDTCMCR: Base_Address Mask */ + +#define MDTCMCR_Size_Pos 4U /*!< MDTCMCR: Size Position */ +#define MDTCMCR_Size_Msk (0xfUL << MDTCMCR_Size_Pos) /*!< MDTCMCR: Size Mask */ + +#define MDTCMCR_EN_Pos 0U /*!< MDTCMCR: EN Position */ +#define MDTCMCR_EN_Msk (0x1UL << MDTCMCR_EN_Pos) /*!< MDTCMCR: EN Mask */ +/*@} end of group CSI_TCM_bitfield */ + +/* ########################## TCM functions #################################### */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_TCMFunctions TCM Functions + \brief Functions that configure TCM. + @{ + */ + +/** + \brief Enable ITCM + \details Turns on ITCM + */ +__STATIC_INLINE void csi_itcm_enable (void) +{ + __set_MITCMCR(__get_MITCMCR() | MITCMCR_EN_Msk); +} + +/** + \brief Enable DTCM + \details Turns on DTCM + */ +__STATIC_INLINE void csi_dtcm_enable (void) +{ + __set_MDTCMCR(__get_MDTCMCR() | MDTCMCR_EN_Msk); +} + +/** + \brief Enable ITCM + \details Turns on ITCM + */ +__STATIC_INLINE void csi_itcm_disable (void) +{ + __set_MITCMCR(__get_MITCMCR() & (~MITCMCR_EN_Msk)); +} + +/** + \brief Enable DTCM + \details Turns on DTCM + */ +__STATIC_INLINE void csi_dtcm_disable (void) +{ + __set_MDTCMCR(__get_MDTCMCR() & (~MDTCMCR_EN_Msk)); +} + +/** + \brief Get ITCM Size + \details Get ITCM Size + \return ITCM size (bytes). + */ +__STATIC_INLINE uint32_t csi_itcm_get_size(void) +{ + MITCMCR_Type sizemask; + uint32_t ret; + + sizemask.w = __get_MITCMCR(); + switch (sizemask.b.Size) + { + case 0x3: ret = 4 << 10; break; + case 0x4: ret = 8 << 10; break; + case 0x5: ret = 16 << 10; break; + case 0x6: ret = 32 << 10; break; + case 0x7: ret = 64 << 10; break; + case 0x8: ret = 128 << 10; break; + case 0x9: ret = 256 << 10; break; + case 0xa: ret = 512 << 10; break; + case 0xb: ret = 1 << 20; break; + case 0xc: ret = 2 << 20; break; + case 0xd: ret = 4 << 20; break; + case 0xe: ret = 8 << 20; break; + case 0xf: ret = 16 << 20; break; + default: ret = 0; break; + } + return ret; +} + +/** + \brief Get DTCM Size + \details Get DTCM Size + \return DTCM size (bytes). + */ +__STATIC_INLINE uint32_t csi_dtcm_get_size(void) +{ + MDTCMCR_Type sizemask; + uint32_t ret; + + sizemask.w = __get_MDTCMCR(); + switch (sizemask.b.Size) + { + case 0x3: ret = 4 << 10; break; + case 0x4: ret = 8 << 10; break; + case 0x5: ret = 16 << 10; break; + case 0x6: ret = 32 << 10; break; + case 0x7: ret = 64 << 10; break; + case 0x8: ret = 128 << 10; break; + case 0x9: ret = 256 << 10; break; + case 0xa: ret = 512 << 10; break; + case 0xb: ret = 1 << 20; break; + case 0xc: ret = 2 << 20; break; + case 0xd: ret = 4 << 20; break; + case 0xe: ret = 8 << 20; break; + case 0xf: ret = 16 << 20; break; + default: ret = 0; break; + } + return ret; +} + +/** + \brief Set ITCM Base Address + \details Set ITCM Base Address + \param [in] base_addr itcm base address. + */ +__STATIC_INLINE void csi_itcm_set_base_addr(unsigned long base_addr) +{ + __set_MITCMCR((__get_MITCMCR() & (~MITCMCR_Base_Address_Msk)) | (base_addr & MITCMCR_Base_Address_Msk)); +} + +/** + \brief Set DTCM Base Address + \details Set DTCM Base Address + \param [in] base_addr dtcm base address. + */ +__STATIC_INLINE void csi_dtcm_set_base_addr(unsigned long base_addr) +{ + __set_MDTCMCR((__get_MDTCMCR() & (~MDTCMCR_Base_Address_Msk)) | (base_addr & MDTCMCR_Base_Address_Msk)); +} + +/*@} end of CSI_Core_TCMFunctions */ +#endif /* end e907xx */ + + +/*@} end of CSI_core_DebugFunctions */ + +/* ################################## IRQ Functions ############################################ */ + +/** + \brief Save the Irq context + \details save the psr result before disable irq. + */ +__STATIC_INLINE uint32_t csi_irq_save(void) +{ + uint32_t result; + result = __get_MSTATUS(); + __disable_irq(); + return(result); +} + +/** + \brief Restore the Irq context + \details restore saved primask state. + \param [in] irq_state psr irq state. + */ +__STATIC_INLINE void csi_irq_restore(uint32_t irq_state) +{ + __set_MSTATUS(irq_state); +} + +/*@} end of IRQ Functions */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_RV32_H_DEPENDANT */ + +#endif /* __CSI_GENERIC */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/core_rv64.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/core_rv64.h new file mode 100644 index 00000000..c5463e93 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/core_rv64.h @@ -0,0 +1,2002 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +/****************************************************************************** + * @file core_rv64.h + * @brief CSI RV32 Core Peripheral Access Layer Header File + * @version V1.0 + * @date 01. Sep 2018 + ******************************************************************************/ + +#ifndef __CORE_RV64_H_GENERIC +#define __CORE_RV64_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * CSI definitions + ******************************************************************************/ +/** + \ingroup RV32 + @{ + */ + +#ifndef __RV64 +#define __RV64 (0x01U) +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif +#endif + +#if defined(CONFIG_PLIC_BASE) +#ifndef CORET_BASE +#define CORET_BASE (CONFIG_PLIC_BASE + 0x4000000UL) /*!< CORET Base Address */ +#endif +#define PLIC ((PLIC_Type *)CONFIG_PLIC_BASE) +#else +#error "CONFIG_PLIC_BASE is not defined!" +#endif /* end CONFIG_PLIC_BASE */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_RV32_H_GENERIC */ + +#ifndef __CSI_GENERIC + +#ifndef __CORE_RV32_H_DEPENDANT +#define __CORE_RV32_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#ifndef __RV64_REV +#define __RV64_REV 0x0000U +#endif + +#ifndef __VIC_PRIO_BITS +#define __VIC_PRIO_BITS 2U +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 1U +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 1U +#endif + +#ifndef __ICACHE_PRESENT +#define __ICACHE_PRESENT 1U +#endif + +#ifndef __DCACHE_PRESENT +#define __DCACHE_PRESENT 1U +#endif + + +#ifndef __L2CACHE_PRESENT +#define __L2CACHE_PRESENT 1U +#endif + +#include + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CSI_glob_defs CSI Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group C9xx/R9xx */ + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core CLINT Register + ******************************************************************************/ +/** + \defgroup CSI_core_register Defines and Type Definitions + \brief Type definitions and defines for CK80X processor based devices. +*/ + +/** + \ingroup CSI_core_register + \defgroup CSI_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +#if CONFIG_INTC_CLIC_PLIC +/** + \brief Access to the structure of a CLIC vector interrupt controller. + */ +typedef struct { + __IOM uint8_t IP; /*!< Offset: 0x000 (R/W) Interrupt set pending register */ + __IOM uint8_t IE; /*!< Offset: 0x004 (R/W) Interrupt set enable register */ + __IOM uint8_t ATTR; /*!< Offset: 0x008 (R/W) Interrupt set attribute register */ + __IOM uint8_t CTL; /*!< Offset: 0x00C (R/W) Interrupt control register */ +} CLIC_INT_Control; + +typedef struct { + __IOM uint32_t CLICCFG:8; /*!< Offset: 0x000 (R/W) CLIC configure register */ + __IM uint32_t CLICINFO; + __IOM uint32_t MINTTHRESH; + uint32_t RESERVED[1021]; + CLIC_INT_Control CLICINT[4096]; +} CLIC_Type; + +#define CLIC_INFO_CLICINTCTLBITS_Pos 21U +#define CLIC_INFO_CLICINTCTLBITS_Msk (0xFUL << CLIC_INFO_CLICINTCTLBITS_Pos) + +#define CLIC_INTIP_IP_Pos 0U /*!< CLIC INTIP: IP Position */ +#define CLIC_INTIP_IP_Msk (0x1UL << CLIC_INTIP_IP_Pos) /*!< CLIC INTIP: IP Mask */ + +#define CLIC_INTIE_IE_Pos 0U /*!< CLIC INTIE: IE Position */ +#define CLIC_INTIE_IE_Msk (0x1UL << CLIC_INTIE_IE_Pos) /*!< CLIC INTIE: IE Mask */ + +#define CLIC_INTIE_T_Pos 7U /*!< CLIC INTIE: T Position */ +#define CLIC_INTIE_T_Msk (0x1UL << CLIC_INTIE_T_Pos) /*!< CLIC INTIE: T Mask */ + +#define CLIC_INTATTR_TRIG_Pos 1U /*!< CLIC INTATTR: TRIG Position */ +#define CLIC_INTATTR_TRIG_Msk (0x3UL << CLIC_INTATTR_TRIG_Pos) /*!< CLIC INTATTR: TRIG Mask */ + +#define CLIC_INTATTR_SHV_Pos 0U /*!< CLIC INTATTR: SHV Position */ +#define CLIC_INTATTR_SHV_Msk (0x1UL << CLIC_INTATTR_SHV_Pos) /*!< CLIC INTATTR: SHV Mask */ + +#define CLIC_INTCFG_NVBIT_Pos 5U /*!< CLIC INTCFG: NVBIT Position */ +#define CLIC_INTCFG_NVBIT_Msk (0x1UL << CLIC_INTCFG_NVBIT_Pos) /*!< CLIC INTCFG: NVBIT Mask */ + +#define CLIC_INTCFG_PRIO_Pos 5U /*!< CLIC INTCFG: INTCFG Position */ +#define CLIC_INTCFG_PRIO_Msk (0x7UL << CLIC_INTCFG_PRIO_Pos) /*!< CLIC INTCFG: INTCFG Mask */ + +#define CLIC_CLICCFG_NVBIT_Pos 0U /*!< CLIC CLICCFG: NVBIT Position */ +#define CLIC_CLICCFG_NVBIT_Msk (0x1UL << CLIC_CLICCFG_NVBIT_Pos) /*!< CLIC CLICCFG: NVBIT Mask */ + +#define CLIC_CLICCFG_NLBIT_Pos 1U /*!< CLIC CLICCFG: NLBIT Position */ +#define CLIC_CLICCFG_NLBIT_Msk (0xFUL << CLIC_CLICCFG_NLBIT_Pos) /*!< CLIC CLICCFG: NLBIT Mask */ + +#define CLIC_CLICCFG_NMBIT_Pos 5U /*!< CLIC CLICCFG: NMBIT Position */ +#define CLIC_CLICCFG_NMBIT_Msk (0x3UL << CLIC_CLICCFG_NMBIT_Pos) /*!< CLIC CLICCFG: NMBIT Mask */ + +#if defined(CONFIG_CLIC_BASE) +#define CLIC ((CLIC_Type *)CONFIG_CLIC_BASE) /*!< CLIC configuration struct */ +#else +#error "CONFIG_CLIC_BASE is not defined!" +#endif /* end CONFIG_CLIC_BASE */ + +#endif /* CONFIG_INTC_CLIC_PLIC */ + + +/** + \brief Access to the structure of a PLIC vector interrupt controller. + */ + +typedef struct { + uint32_t RESERVED0; + __IOM uint32_t PLIC_PRIO[1023]; + __IOM uint32_t PLIC_IP[32]; + uint32_t RESERVED1[3972 / 4 - 1]; + __IOM uint32_t PLIC_H0_MIE[32]; + __IOM uint32_t PLIC_H0_SIE[32]; + __IOM uint32_t PLIC_H1_MIE[32]; + __IOM uint32_t PLIC_H1_SIE[32]; + __IOM uint32_t PLIC_H2_MIE[32]; + __IOM uint32_t PLIC_H2_SIE[32]; + __IOM uint32_t PLIC_H3_MIE[32]; + __IOM uint32_t PLIC_H3_SIE[32]; + __IOM uint32_t PLIC_H4_MIE[32]; + __IOM uint32_t PLIC_H4_SIE[32]; + __IOM uint32_t PLIC_H5_MIE[32]; + __IOM uint32_t PLIC_H5_SIE[32]; + __IOM uint32_t PLIC_H6_MIE[32]; + __IOM uint32_t PLIC_H6_SIE[32]; + __IOM uint32_t PLIC_H7_MIE[32]; + __IOM uint32_t PLIC_H7_SIE[32]; + + uint32_t RESERVED2[(0x01FFFFC - 0x00027FC) / 4 - 1]; + __IOM uint32_t PLIC_PER; + __IOM uint32_t PLIC_H0_MTH; + __IOM uint32_t PLIC_H0_MCLAIM; + uint32_t RESERVED3[0xFFC / 4 - 1]; + __IOM uint32_t PLIC_H0_STH; + __IOM uint32_t PLIC_H0_SCLAIM; + uint32_t RESERVED4[0xFFC / 4 - 1]; + + __IOM uint32_t PLIC_H1_MTH; + __IOM uint32_t PLIC_H1_MCLAIM; + uint32_t RESERVED5[0xFFC / 4 - 1]; + __IOM uint32_t PLIC_H1_STH; + __IOM uint32_t PLIC_H1_SCLAIM; + uint32_t RESERVED6[0xFFC / 4 - 1]; + + __IOM uint32_t PLIC_H2_MTH; + __IOM uint32_t PLIC_H2_MCLAIM; + uint32_t RESERVED7[0xFFC / 4 - 1]; + __IOM uint32_t PLIC_H2_STH; + __IOM uint32_t PLIC_H2_SCLAIM; + uint32_t RESERVED8[0xFFC / 4 - 1]; + + __IOM uint32_t PLIC_H3_MTH; + __IOM uint32_t PLIC_H3_MCLAIM; + uint32_t RESERVED9[0xFFC / 4 - 1]; + __IOM uint32_t PLIC_H3_STH; + __IOM uint32_t PLIC_H3_SCLAIM; + uint32_t RESERVED10[0xFFC / 4 - 1]; + + __IOM uint32_t PLIC_H4_MTH; + __IOM uint32_t PLIC_H4_MCLAIM; + uint32_t RESERVED11[0xFFC / 4 - 1]; + __IOM uint32_t PLIC_H4_STH; + __IOM uint32_t PLIC_H4_SCLAIM; + uint32_t RESERVED12[0xFFC / 4 - 1]; + + __IOM uint32_t PLIC_H5_MTH; + __IOM uint32_t PLIC_H5_MCLAIM; + uint32_t RESERVED13[0xFFC / 4 - 1]; + __IOM uint32_t PLIC_H5_STH; + __IOM uint32_t PLIC_H5_SCLAIM; + uint32_t RESERVED14[0xFFC / 4 - 1]; + + __IOM uint32_t PLIC_H6_MTH; + __IOM uint32_t PLIC_H6_MCLAIM; + uint32_t RESERVED15[0xFFC / 4 - 1]; + __IOM uint32_t PLIC_H6_STH; + __IOM uint32_t PLIC_H6_SCLAIM; + uint32_t RESERVED16[0xFFC / 4 - 1]; + + __IOM uint32_t PLIC_H7_MTH; + __IOM uint32_t PLIC_H7_MCLAIM; + uint32_t RESERVED17[0xFFC / 4 - 1]; + __IOM uint32_t PLIC_H7_STH; + __IOM uint32_t PLIC_H7_SCLAIM; + uint32_t RESERVED18[0xFFC / 4 - 1]; +} PLIC_Type; + + +/** + \ingroup CSI_core_register + \defgroup CSI_PMP Physical Memory Protection (PMP) + \brief Type definitions for the PMP Registers + @{ + */ + +#define PMP_PMPCFG_R_Pos 0U /*!< PMP PMPCFG: R Position */ +#define PMP_PMPCFG_R_Msk (0x1UL << PMP_PMPCFG_R_Pos) /*!< PMP PMPCFG: R Mask */ + +#define PMP_PMPCFG_W_Pos 1U /*!< PMP PMPCFG: W Position */ +#define PMP_PMPCFG_W_Msk (0x1UL << PMP_PMPCFG_W_Pos) /*!< PMP PMPCFG: W Mask */ + +#define PMP_PMPCFG_X_Pos 2U /*!< PMP PMPCFG: X Position */ +#define PMP_PMPCFG_X_Msk (0x1UL << PMP_PMPCFG_X_Pos) /*!< PMP PMPCFG: X Mask */ + +#define PMP_PMPCFG_A_Pos 3U /*!< PMP PMPCFG: A Position */ +#define PMP_PMPCFG_A_Msk (0x3UL << PMP_PMPCFG_A_Pos) /*!< PMP PMPCFG: A Mask */ + +#define PMP_PMPCFG_L_Pos 7U /*!< PMP PMPCFG: L Position */ +#define PMP_PMPCFG_L_Msk (0x1UL << PMP_PMPCFG_L_Pos) /*!< PMP PMPCFG: L Mask */ + +typedef enum { + REGION_SIZE_4B = -1, + REGION_SIZE_8B = 0, + REGION_SIZE_16B = 1, + REGION_SIZE_32B = 2, + REGION_SIZE_64B = 3, + REGION_SIZE_128B = 4, + REGION_SIZE_256B = 5, + REGION_SIZE_512B = 6, + REGION_SIZE_1KB = 7, + REGION_SIZE_2KB = 8, + REGION_SIZE_4KB = 9, + REGION_SIZE_8KB = 10, + REGION_SIZE_16KB = 11, + REGION_SIZE_32KB = 12, + REGION_SIZE_64KB = 13, + REGION_SIZE_128KB = 14, + REGION_SIZE_256KB = 15, + REGION_SIZE_512KB = 16, + REGION_SIZE_1MB = 17, + REGION_SIZE_2MB = 18, + REGION_SIZE_4MB = 19, + REGION_SIZE_8MB = 20, + REGION_SIZE_16MB = 21, + REGION_SIZE_32MB = 22, + REGION_SIZE_64MB = 23, + REGION_SIZE_128MB = 24, + REGION_SIZE_256MB = 25, + REGION_SIZE_512MB = 26, + REGION_SIZE_1GB = 27, + REGION_SIZE_2GB = 28, + REGION_SIZE_4GB = 29, + REGION_SIZE_8GB = 30, + REGION_SIZE_16GB = 31 +} region_size_e; + +typedef enum { + ADDRESS_MATCHING_TOR = 1, + ADDRESS_MATCHING_NAPOT = 3 +} address_matching_e; + +typedef struct { + uint32_t r: 1; /* readable enable */ + uint32_t w: 1; /* writeable enable */ + uint32_t x: 1; /* execable enable */ + address_matching_e a: 2; /* address matching mode */ + uint32_t reserved: 2; /* reserved */ + uint32_t l: 1; /* lock enable */ +} pmp_region_attr_t; + +/*@} end of group CSI_PMP */ + +/* CACHE Register Definitions */ +#define CACHE_MHCR_WBR_Pos 8U /*!< CACHE MHCR: WBR Position */ +#define CACHE_MHCR_WBR_Msk (0x1UL << CACHE_MHCR_WBR_Pos) /*!< CACHE MHCR: WBR Mask */ + +#define CACHE_MHCR_IBPE_Pos 7U /*!< CACHE MHCR: IBPE Position */ +#define CACHE_MHCR_IBPE_Msk (0x1UL << CACHE_MHCR_IBPE_Pos) /*!< CACHE MHCR: IBPE Mask */ + +#define CACHE_MHCR_BTB_Pos 6U /*!< CACHE MHCR: BTB Position */ +#define CACHE_MHCR_BTB_Msk (0x1UL << CACHE_MHCR_BTB_Pos) /*!< CACHE MHCR: BTB Mask */ + +#define CACHE_MHCR_BPE_Pos 5U /*!< CACHE MHCR: BPE Position */ +#define CACHE_MHCR_BPE_Msk (0x1UL << CACHE_MHCR_BPE_Pos) /*!< CACHE MHCR: BPE Mask */ + +#define CACHE_MHCR_RS_Pos 4U /*!< CACHE MHCR: RS Position */ +#define CACHE_MHCR_RS_Msk (0x1UL << CACHE_MHCR_RS_Pos) /*!< CACHE MHCR: RS Mask */ + +#define CACHE_MHCR_WB_Pos 3U /*!< CACHE MHCR: WB Position */ +#define CACHE_MHCR_WB_Msk (0x1UL << CACHE_MHCR_WB_Pos) /*!< CACHE MHCR: WB Mask */ + +#define CACHE_MHCR_WA_Pos 2U /*!< CACHE MHCR: WA Position */ +#define CACHE_MHCR_WA_Msk (0x1UL << CACHE_MHCR_WA_Pos) /*!< CACHE MHCR: WA Mask */ + +#define CACHE_MHCR_DE_Pos 1U /*!< CACHE MHCR: DE Position */ +#define CACHE_MHCR_DE_Msk (0x1UL << CACHE_MHCR_DE_Pos) /*!< CACHE MHCR: DE Mask */ + +#define CACHE_MHCR_IE_Pos 0U /*!< CACHE MHCR: IE Position */ +#define CACHE_MHCR_IE_Msk (0x1UL << CACHE_MHCR_IE_Pos) /*!< CACHE MHCR: IE Mask */ + +#if CONFIG_CPU_XUANTIE_R908 || CONFIG_CPU_XUANTIE_R908FD || CONFIG_CPU_XUANTIE_R908FDV \ + || CONFIG_CPU_XUANTIE_R908_CP || CONFIG_CPU_XUANTIE_R908FD_CP || CONFIG_CPU_XUANTIE_R908FDV_CP \ + || CONFIG_CPU_XUANTIE_R908_CP_XT || CONFIG_CPU_XUANTIE_R908FD_CP_XT || CONFIG_CPU_XUANTIE_R908FDV_CP_XT \ + || CONFIG_CPU_XUANTIE_C908X || CONFIG_CPU_XUANTIE_C908X_CP || CONFIG_CPU_XUANTIE_C908X_CP_XT +#define MCER_ECC_FATAL_Pos 34U +#define MCER_ECC_FATAL_Msk (0x1ULL << MCER_ECC_FATAL_Pos) + +#define MCER_ECC_VLD_Pos 35U +#define MCER_ECC_VLD_Msk (0x1ULL << MCER_ECC_VLD_Pos) + +#define MCER_RAMID_Pos 25U +#define MCER_RAMID_Msk (0x7ULL << MCER_RAMID_Pos) +#else +#define MCER_ECC_FATAL_Pos 30U +#define MCER_ECC_FATAL_Msk (0x1ULL << MCER_ECC_FATAL_Pos) +#define MCER_ECC_VLD_Pos 31U +#define MCER_ECC_VLD_Msk (0x1ULL << MCER_ECC_VLD_Pos) +#define MCER_RAMID_Pos 21U +#define MCER_RAMID_Msk (0x7ULL << MCER_RAMID_Pos) +#endif + +#define CACHE_MCER2_ECC_FATAL_Pos 62U +#define CACHE_MCER2_ECC_FATAL_Msk (0x1ULL << CACHE_MCER2_ECC_FATAL_Pos) + +#define CACHE_MCER2H_ECC_FATAL_Pos 30U +#define CACHE_MCER2H_ECC_FATAL_Msk (0x1ULL << CACHE_MCER2H_ECC_FATAL_Pos) + +#define CACHE_MCER2_ECC_VLD_Pos 63U +#define CACHE_MCER2_ECC_VLD_Msk (0x1ULL << CACHE_MCER2_ECC_VLD_Pos) + +#define CACHE_MCER2H_ECC_VLD_Pos 31U +#define CACHE_MCER2H_ECC_VLD_Msk (0x1ULL << CACHE_MCER2H_ECC_VLD_Pos) + +#define CACHE_MCER2_RAMID_Pos 53U +#define CACHE_MCER2_RAMID_Msk (0x3ULL << CACHE_MCER2_RAMID_Pos) + +#define CACHE_MCER2H_RAMID_Pos 21U +#define CACHE_MCER2H_RAMID_Msk (0x3ULL << CACHE_MCER2H_RAMID_Pos) + +#define CACHE_INV_ADDR_Pos 6U +#define CACHE_INV_ADDR_Msk (~((0x1ULL << CACHE_INV_ADDR_Pos) - 1)) + +enum MCER_FAULT_RAMID { + /* L1 Cache, JTLB and TCM (RAMID of MCER)*/ + MCER_FAULT_RAMID_L1_ICACHE_TAG = 0, + MCER_FAULT_RAMID_L1_ICACHE_DATA, + MCER_FAULT_RAMID_L1_DCACHE_TAG, + MCER_FAULT_RAMID_L1_DCACHE_DATA, + MCER_FAULT_RAMID_JTLB_TAG, + MCER_FAULT_RAMID_JTLB_DATA, + MCER_FAULT_RAMID_DTCM, + MCER_FAULT_RAMID_ITCM +}; + +enum MCER2_FAULT_RAMID { + MCER2_FAULT_RAMID_L2_CACHE_TAG = 0, + MCER2_FAULT_RAMID_L2_CACHE_DATA, + MCER2_FAULT_RAMID_L2_CACHE_DIRTY +}; + +/*@} end of group CSI_CACHE */ + +// MSTATUS Register +#define MSTATUS_TVM_MASK (1L << 20) // mstatus.TVM [20] +#define MSTATUS_MPP_MASK (3L << 11) // mstatus.SPP [11:12] +#ifndef MSTATUS_MPP_M +#define MSTATUS_MPP_M (3L << 11) // Machine mode 11 +#endif +#define MSTATUS_MPP_S (1L << 11) // Supervisor mode 01 +#define MSTATUS_MPP_U (0L << 11) // User mode 00 + +// SSTATUS Register +#define SSTATUS_SPP_MASK (3L << 8) // sstatus.SPP [8:9] +#define SSTATUS_SPP_S (1L << 8) // Supervisor mode 01 +#define SSTATUS_SPP_U (0L << 8) // User mode 00 + +typedef enum { + USER_MODE = 0, + SUPERVISOR_MODE = 1, + MACHINE_MODE = 3, +} cpu_work_mode_t; + +/** + \brief Get CPU WORK MODE + \details Returns CPU WORK MODE. + \return CPU WORK MODE + */ +__STATIC_INLINE int csi_get_cpu_work_mode(void) +{ + return (int)__get_CPU_WORK_MODE(); +} + +/** + \brief Get current hartid + \return hartid + */ +__STATIC_INLINE int csi_get_cpu_id(void) +{ + unsigned long result; + +#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE + return 0; +#endif + __ASM volatile("csrr %0, mhartid" : "=r"(result) : : "memory"); + return result; +} + +/** + \brief Get cache line size + \return cache line size + */ +__STATIC_INLINE int csi_get_cache_line_size(void) +{ + return 64; +} + + +/** + \ingroup CSI_core_register + \defgroup CSI_CINT Core Local Interrupt (CLINT) + \brief Type definitions for the Core Local Interrupt Registers. + @{ + */ + +/** + \brief The data structure of the access Clint. + */ +typedef struct { + __IOM uint32_t MSIP0; + __IOM uint32_t MSIP1; + __IOM uint32_t MSIP2; + __IOM uint32_t MSIP3; + __IOM uint32_t MSIP4; + __IOM uint32_t MSIP5; + __IOM uint32_t MSIP6; + __IOM uint32_t MSIP7; + uint32_t RESERVED0[(0x4004000 - 0x400001C) / 4 - 1]; + __IOM uint32_t MTIMECMPL0; + __IOM uint32_t MTIMECMPH0; + __IOM uint32_t MTIMECMPL1; + __IOM uint32_t MTIMECMPH1; + __IOM uint32_t MTIMECMPL2; + __IOM uint32_t MTIMECMPH2; + __IOM uint32_t MTIMECMPL3; + __IOM uint32_t MTIMECMPH3; + __IOM uint32_t MTIMECMPL4; + __IOM uint32_t MTIMECMPH4; + __IOM uint32_t MTIMECMPL5; + __IOM uint32_t MTIMECMPH5; + __IOM uint32_t MTIMECMPL6; + __IOM uint32_t MTIMECMPH6; + __IOM uint32_t MTIMECMPL7; + __IOM uint32_t MTIMECMPH7; + uint32_t RESERVED1[(0x400BFF8 - 0x400403C) / 4 - 1]; + __IOM uint32_t MTIMEL; + __IOM uint32_t MTIMEH; + __IOM uint32_t SSIP0; + __IOM uint32_t SSIP1; + __IOM uint32_t SSIP2; + __IOM uint32_t SSIP3; + __IOM uint32_t SSIP4; + __IOM uint32_t SSIP5; + __IOM uint32_t SSIP6; + __IOM uint32_t SSIP7; + uint32_t RESERVED2[(0x400D000 - 0x400C01C) / 4 - 1]; + __IOM uint32_t STIMECMPL0; + __IOM uint32_t STIMECMPH0; + __IOM uint32_t STIMECMPL1; + __IOM uint32_t STIMECMPH1; + __IOM uint32_t STIMECMPL2; + __IOM uint32_t STIMECMPH2; + __IOM uint32_t STIMECMPL3; + __IOM uint32_t STIMECMPH3; + __IOM uint32_t STIMECMPL4; + __IOM uint32_t STIMECMPH4; + __IOM uint32_t STIMECMPL5; + __IOM uint32_t STIMECMPH5; + __IOM uint32_t STIMECMPL6; + __IOM uint32_t STIMECMPH6; + __IOM uint32_t STIMECMPL7; + __IOM uint32_t STIMECMPH7; + uint32_t RESERVED3[(0x400FFF8 - 0x400D03C) / 4 - 1]; + __IOM uint32_t STIMEL; + __IOM uint32_t STIMEH; +} CLINT_Type; + +typedef struct { +#ifdef CONFIG_RISCV_SMODE + __IOM uint32_t STIMECMPL0; + __IOM uint32_t STIMECMPH0; +#else + __IOM uint32_t MTIMECMPL0; + __IOM uint32_t MTIMECMPH0; +#endif +} CLINT_CMP_Type; + +/*@} end of group CSI_SysTick */ + + +/** + \ingroup CSI_core_register + \defgroup CSI_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CSI_core_bitfield */ + +/** + \ingroup CSI_core_register + \defgroup CSI_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/*@} */ + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core VIC Functions + - Core CORET Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CSI_Core_FunctionInterface Functions and Instructions Reference +*/ + +/* ########################## VIC functions #################################### */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_VICFunctions VIC Functions + \brief Functions that manage interrupts and exceptions via the VIC. + @{ + */ + +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 5UL) ) +#define _IP2_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define PLIC_Hn_MSIE_ADDR(msie_base, hartid) ((unsigned long)(msie_base) + 0x100 * (hartid)) +#define PLIC_Hn_MSIE_VAL(msie_base, hartid) (*(__IOM uint32_t *)(PLIC_Hn_MSIE_ADDR(msie_base, hartid))) +#define PLIC_Hn_MSTH_ADDR(msth_base, hartid) ((unsigned long)(msth_base) + 0x2000 * (hartid)) +#define PLIC_Hn_MSTH_VAL(msth_base, hartid) (*(__IOM uint32_t *)(PLIC_Hn_MSTH_ADDR(msth_base, hartid))) +#define PLIC_Hn_MSCLAIM_ADDR(msclaim_base, hartid) ((unsigned long)(msclaim_base) + 0x2000 * (hartid)) +#define PLIC_Hn_MSCLAIM_VAL(msclaim_base, hartid) (*(__IOM uint32_t *)(PLIC_Hn_MSCLAIM_ADDR(msclaim_base, hartid))) + +/** + \brief Enable External Interrupt + \details Enable a device-specific interrupt in the VIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_vic_enable_irq(int32_t IRQn) +{ + int hartid = csi_get_cpu_id(); + PLIC_Type *plic = (PLIC_Type *)CONFIG_PLIC_BASE; + +#if CONFIG_INTC_CLIC_PLIC + if ((uint32_t)IRQn > PLIC_IRQ_OFFSET) { + IRQn -= PLIC_IRQ_OFFSET; + } else { + CLIC->CLICINT[IRQn].IE |= CLIC_INTIE_IE_Msk; + __DSB(); + return; + } +#endif +#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE + PLIC_Hn_MSIE_VAL(&plic->PLIC_H0_SIE[IRQn/32], hartid) = PLIC_Hn_MSIE_VAL(&plic->PLIC_H0_SIE[IRQn/32], hartid) | (0x1 << (IRQn%32)); +#else + PLIC_Hn_MSIE_VAL(&plic->PLIC_H0_MIE[IRQn/32], hartid) = PLIC_Hn_MSIE_VAL(&plic->PLIC_H0_MIE[IRQn/32], hartid) | (0x1 << (IRQn%32)); +#endif +} + +/** + \brief Enable External Interrupt(deprecated) + \details Enable a device-specific interrupt in the VIC interrupt controller. + \param [in] plic_base PLIC base address + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_plic_enable_irq(unsigned long plic_base, int32_t IRQn) +{ + int hartid = csi_get_cpu_id(); + PLIC_Type *plic = (PLIC_Type *)plic_base; + +#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE + PLIC_Hn_MSIE_VAL(&plic->PLIC_H0_SIE[IRQn/32], hartid) = PLIC_Hn_MSIE_VAL(&plic->PLIC_H0_SIE[IRQn/32], hartid) | (0x1 << (IRQn%32)); +#else + PLIC_Hn_MSIE_VAL(&plic->PLIC_H0_MIE[IRQn/32], hartid) = PLIC_Hn_MSIE_VAL(&plic->PLIC_H0_MIE[IRQn/32], hartid) | (0x1 << (IRQn%32)); +#endif +} + +/** + \brief Disable External Interrupt + \details Disable a device-specific interrupt in the VIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_vic_disable_irq(int32_t IRQn) +{ + int hartid = csi_get_cpu_id(); + PLIC_Type *plic = (PLIC_Type *)CONFIG_PLIC_BASE; + +#if CONFIG_INTC_CLIC_PLIC + if ((uint32_t)IRQn > PLIC_IRQ_OFFSET) { + IRQn -= PLIC_IRQ_OFFSET; + } else { + CLIC->CLICINT[IRQn].IE &= ~CLIC_INTIE_IE_Msk; + __DSB(); + return; + } +#endif +#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE + PLIC_Hn_MSIE_VAL(&plic->PLIC_H0_SIE[IRQn/32], hartid) = PLIC_Hn_MSIE_VAL(&plic->PLIC_H0_SIE[IRQn/32], hartid) & (~(0x1 << (IRQn%32))); +#else + PLIC_Hn_MSIE_VAL(&plic->PLIC_H0_MIE[IRQn/32], hartid) = PLIC_Hn_MSIE_VAL(&plic->PLIC_H0_MIE[IRQn/32], hartid) & (~(0x1 << (IRQn%32))); +#endif +} + +/** + \brief Disable External Interrupt(deprecated) + \details Disable a device-specific interrupt in the VIC interrupt controller. + \param [in] plic_base PLIC base address + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_plic_disable_irq(unsigned long plic_base, int32_t IRQn) +{ + int hartid = csi_get_cpu_id(); + PLIC_Type *plic = (PLIC_Type *)plic_base; + +#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE + PLIC_Hn_MSIE_VAL(&plic->PLIC_H0_SIE[IRQn/32], hartid) = PLIC_Hn_MSIE_VAL(&plic->PLIC_H0_SIE[IRQn/32], hartid) & (~(0x1 << (IRQn%32))); +#else + PLIC_Hn_MSIE_VAL(&plic->PLIC_H0_MIE[IRQn/32], hartid) = PLIC_Hn_MSIE_VAL(&plic->PLIC_H0_MIE[IRQn/32], hartid) & (~(0x1 << (IRQn%32))); +#endif +} + +/** + \brief Check Interrupt is Enabled or not + \details Read the enabled register in the VIC and returns the pending bit for the specified interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + \return 0 Interrupt status is not enabled. + \return 1 Interrupt status is enabled. + */ +__STATIC_INLINE uint32_t csi_vic_get_enabled_irq(int32_t IRQn) +{ + int hartid = csi_get_cpu_id(); + PLIC_Type *plic = (PLIC_Type *)CONFIG_PLIC_BASE; + +#if CONFIG_INTC_CLIC_PLIC + if ((uint32_t)IRQn > PLIC_IRQ_OFFSET) { + IRQn -= PLIC_IRQ_OFFSET; + } else { + return (uint32_t)(CLIC->CLICINT[IRQn].IE & CLIC_INTIE_IE_Msk); + } +#endif +#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE + return (uint32_t)((PLIC_Hn_MSIE_VAL(&plic->PLIC_H0_SIE[IRQn/32], hartid) >> IRQn%32) & 0x1); +#else + return (uint32_t)((PLIC_Hn_MSIE_VAL(&plic->PLIC_H0_MIE[IRQn/32], hartid) >> IRQn%32) & 0x1); +#endif +} + +/** + \brief Check Interrupt is Enabled or not(deprecated) + \details Read the enabled register in the VIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not enabled. + \return 1 Interrupt status is enabled. + */ +__STATIC_INLINE uint32_t csi_plic_get_enabled_irq(unsigned long plic_base, int32_t IRQn) +{ + int hartid = csi_get_cpu_id(); + PLIC_Type *plic = (PLIC_Type *)plic_base; + +#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE + return (uint32_t)((PLIC_Hn_MSIE_VAL(&plic->PLIC_H0_SIE[IRQn/32], hartid) >> IRQn%32) & 0x1); +#else + return (uint32_t)((PLIC_Hn_MSIE_VAL(&plic->PLIC_H0_MIE[IRQn/32], hartid) >> IRQn%32) & 0x1); +#endif +} + +/** + \brief Check Interrupt is Pending or not + \details Read the pending register in the VIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn) +{ + PLIC_Type *plic = (PLIC_Type *)CONFIG_PLIC_BASE; +#if CONFIG_INTC_CLIC_PLIC + if ((uint32_t)IRQn > PLIC_IRQ_OFFSET) { + IRQn -= PLIC_IRQ_OFFSET; + } else { + return (uint32_t)(CLIC->CLICINT[IRQn].IP & CLIC_INTIP_IP_Msk); + } +#endif + return (uint32_t)((plic->PLIC_IP[IRQn/32] >> IRQn%32) & 0x1); +} + +/** + \brief Set Pending Interrupt + \details Set the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn) +{ + PLIC_Type *plic = (PLIC_Type *)CONFIG_PLIC_BASE; +#if CONFIG_INTC_CLIC_PLIC + if ((uint32_t)IRQn > PLIC_IRQ_OFFSET) { + IRQn -= PLIC_IRQ_OFFSET; + } else { + CLIC->CLICINT[IRQn].IP |= CLIC_INTIP_IP_Msk; + __DSB(); + return; + } +#endif + plic->PLIC_IP[IRQn/32] = plic->PLIC_IP[IRQn/32] | (0x1 << (IRQn%32)); + __DSB(); +} + +/** + \brief Clear Pending Interrupt + \details Clear the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn) +{ + PLIC_Type *plic = (PLIC_Type *)CONFIG_PLIC_BASE; +#if CONFIG_INTC_CLIC_PLIC + if ((uint32_t)IRQn > PLIC_IRQ_OFFSET) { + IRQn -= PLIC_IRQ_OFFSET; + } else { + CLIC->CLICINT[IRQn].IP &= ~CLIC_INTIP_IP_Msk; + __DSB(); + return; + } +#endif + plic->PLIC_H0_SCLAIM = IRQn; + __DSB(); +} + +/** + \brief Check Interrupt is Pending or not(deprecated) + \details Read the pending register in the VIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t csi_plic_get_pending_irq(unsigned long plic_base, int32_t IRQn) +{ + PLIC_Type *plic = (PLIC_Type *)plic_base; + return (uint32_t)((plic->PLIC_IP[IRQn/32] >> IRQn%32) & 0x1); +} + +/** + \brief Set Pending Interrupt(deprecated) + \details Set the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_plic_set_pending_irq(unsigned long plic_base, int32_t IRQn) +{ + PLIC_Type *plic = (PLIC_Type *)plic_base; + plic->PLIC_IP[IRQn/32] = plic->PLIC_IP[IRQn/32] | (0x1 << (IRQn%32)); +} + +/** + \brief Clear Pending Interrupt(deprecated) + \details Clear the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_plic_clear_pending_irq(unsigned long plic_base, int32_t IRQn) +{ + PLIC_Type *plic = (PLIC_Type *)plic_base; + plic->PLIC_H0_SCLAIM = IRQn; +} + +/** + \brief Set Interrupt Priority + \details Set the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority) +{ + PLIC_Type *plic = (PLIC_Type *)CONFIG_PLIC_BASE; +#if CONFIG_INTC_CLIC_PLIC + if ((uint32_t)IRQn > PLIC_IRQ_OFFSET) { + IRQn -= PLIC_IRQ_OFFSET; + } else { + uint8_t nlbits = (CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos; + uint8_t ctl = CLIC->CLICINT[IRQn].CTL; + ctl <<= nlbits; + ctl >>= nlbits; + CLIC->CLICINT[IRQn].CTL = ctl | (priority << (8 - nlbits)); + __DSB(); + return; + } +#endif + plic->PLIC_PRIO[IRQn - 1] = priority; + __DSB(); +} + +/** + \brief Get Interrupt Priority + \details Read the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t csi_vic_get_prio(int32_t IRQn) +{ + PLIC_Type *plic = (PLIC_Type *)CONFIG_PLIC_BASE; +#if CONFIG_INTC_CLIC_PLIC + if ((uint32_t)IRQn > PLIC_IRQ_OFFSET) { + IRQn -= PLIC_IRQ_OFFSET; + } else { + uint8_t nlbits = (CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos; + return CLIC->CLICINT[IRQn].CTL >> (8 - nlbits); + } +#endif + uint32_t prio = plic->PLIC_PRIO[IRQn - 1]; + return prio; +} + +/** + \brief Set Interrupt Priority(deprecated) + \details Set the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void csi_plic_set_prio(unsigned long plic_base, int32_t IRQn, uint32_t priority) +{ + PLIC_Type *plic = (PLIC_Type *)plic_base; + plic->PLIC_PRIO[IRQn - 1] = priority; +} + +/** + \brief Get Interrupt Priority(deprecated) + \details Read the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t csi_plic_get_prio(unsigned long plic_base, int32_t IRQn) +{ + PLIC_Type *plic = (PLIC_Type *)plic_base; + uint32_t prio = plic->PLIC_PRIO[IRQn - 1]; + return prio; +} + +/*@} end of CSI_Core_VICFunctions */ + +/* ########################## PMP functions #################################### */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_PMPFunctions PMP Functions + \brief Functions that manage interrupts and exceptions via the VIC. + @{ + */ + +/** + \brief configure physical memory protection region. + \details + \param [in] idx memory protection region (0, 1, 2, ..., 15). + \param [in] base_addr base address must be aligned with page size. + \param [in] size \ref region_size_e. memory protection region size. + \param [in] attr \ref pmp_region_attr_t. memory protection region attribute. + \param [in] enable enable or disable memory protection region. + */ +__STATIC_INLINE void csi_pmp_config_region(uint32_t idx, unsigned long base_addr, region_size_e size, + pmp_region_attr_t attr, uint32_t enable) +{ + uint8_t pmpxcfg = 0; + uint32_t addr = 0; + + if (idx > 15) { + return; + } + + if (!enable) { + attr.a = (address_matching_e)0; + } + + if (attr.a == ADDRESS_MATCHING_TOR) { + addr = base_addr >> 2; + } else { + if (size == REGION_SIZE_4B) { + addr = base_addr >> 2; + attr.a = (address_matching_e)2; + } else { + addr = ((base_addr >> 2) & (0xFFFFFFFFFFFFFFFFUL - ((1 << (size + 1)) - 1))) | ((1 << size) - 1); + } + } + + __set_PMPADDRx(idx, addr); + + pmpxcfg |= (attr.r << PMP_PMPCFG_R_Pos) | (attr.w << PMP_PMPCFG_W_Pos) | + (attr.x << PMP_PMPCFG_X_Pos) | (attr.a << PMP_PMPCFG_A_Pos) | + (attr.l << PMP_PMPCFG_L_Pos); + + __set_PMPxCFG(idx, pmpxcfg); +} + +/** + \brief disable physical memory protection region by idx. + \details + \param [in] idx memory protection region (0, 1, 2, ..., 15). + */ +__STATIC_INLINE void csi_pmp_disable_region(uint32_t idx) +{ + __set_PMPxCFG(idx, __get_PMPxCFG(idx) & (~PMP_PMPCFG_A_Msk)); +} + +/*@} end of CSI_Core_PMPFunctions */ + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#define CLINT_TIMECMPn_ADDR(time_cmp_base, hartid) ((unsigned long)(time_cmp_base) + 8 * (hartid)) +#define CLINT_TIMECMPn_VAL(time_cmp_base, hartid) (*(__IOM uint32_t *)(CLINT_TIMECMPn_ADDR(time_cmp_base, hartid))) + +__STATIC_INLINE uint32_t _csi_clint_config2(unsigned long coret_base, uint16_t hartid, uint64_t ticks, int32_t IRQn) +{ + CLINT_Type *clint = (CLINT_Type *)coret_base; +#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE + uint64_t value = (((uint64_t)(CLINT_TIMECMPn_VAL(&clint->STIMECMPH0, hartid))) << 32) + \ + (uint64_t)(CLINT_TIMECMPn_VAL(&clint->STIMECMPL0, hartid)); + + if ((value != 0) && (value != 0xffffffffffffffff)) { + value = value + (uint64_t)ticks; + } else { + value = __get_MTIME() + ticks; + } + CLINT_TIMECMPn_VAL(&clint->STIMECMPH0, hartid) = (uint32_t)(value >> 32); + CLINT_TIMECMPn_VAL(&clint->STIMECMPL0, hartid) = (uint32_t)value; +#else + uint64_t value = (((uint64_t)(CLINT_TIMECMPn_VAL(&clint->MTIMECMPH0, hartid))) << 32) + \ + (uint64_t)(CLINT_TIMECMPn_VAL(&clint->MTIMECMPL0, hartid)); + + if ((value != 0) && (value != 0xffffffffffffffff)) { + value = value + (uint64_t)ticks; + } else { + value = __get_MTIME() + ticks; + } + CLINT_TIMECMPn_VAL(&clint->MTIMECMPH0, hartid) = (uint32_t)(value >> 32); + CLINT_TIMECMPn_VAL(&clint->MTIMECMPL0, hartid) = (uint32_t)value; +#endif + + return (0UL); +} + +__STATIC_INLINE uint32_t csi_clint_config(unsigned long coret_base, uint32_t ticks, int32_t IRQn) +{ + return _csi_clint_config2(coret_base, 0, ticks, IRQn); +} + +__STATIC_INLINE void csi_coret_reset_value2() +{ + uint32_t value = 0x0; + int hartid = csi_get_cpu_id(); + CLINT_Type *clint = (CLINT_Type *)CORET_BASE; + +#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE + CLINT_TIMECMPn_VAL(&clint->STIMECMPH0, hartid) = (uint32_t)value; + CLINT_TIMECMPn_VAL(&clint->STIMECMPL0, hartid) = (uint32_t)value; +#else + CLINT_TIMECMPn_VAL(&clint->MTIMECMPH0, hartid) = (uint32_t)value; + CLINT_TIMECMPn_VAL(&clint->MTIMECMPL0, hartid) = (uint32_t)value; +#endif +} + +__STATIC_INLINE void csi_coret_reset_value(unsigned long coret_base) +{ + uint32_t value = 0x0; + int hartid = csi_get_cpu_id(); + CLINT_Type *clint = (CLINT_Type *)coret_base; + +#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE + CLINT_TIMECMPn_VAL(&clint->STIMECMPH0, hartid) = (uint32_t)value; + CLINT_TIMECMPn_VAL(&clint->STIMECMPL0, hartid) = (uint32_t)value; +#else + CLINT_TIMECMPn_VAL(&clint->MTIMECMPH0, hartid) = (uint32_t)value; + CLINT_TIMECMPn_VAL(&clint->MTIMECMPL0, hartid) = (uint32_t)value; +#endif +} + +__STATIC_INLINE uint64_t _csi_clint_get_load2(unsigned long coret_base, uint16_t hartid) +{ + CLINT_Type *clint = (CLINT_Type *)coret_base; +#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE + uint64_t value = (((uint64_t)CLINT_TIMECMPn_VAL(&clint->STIMECMPH0, hartid)) << 32) + \ + (uint64_t)CLINT_TIMECMPn_VAL(&clint->STIMECMPL0, hartid); +#else + uint64_t value = (((uint64_t)CLINT_TIMECMPn_VAL(&clint->MTIMECMPH0, hartid)) << 32) + \ + (uint64_t)CLINT_TIMECMPn_VAL(&clint->MTIMECMPL0, hartid); +#endif + + return value; +} + +/** + \brief get CORE timer reload high value(deprecated) + \return CORE timer counter value. + */ +__STATIC_INLINE uint64_t csi_clint_get_load(unsigned long coret_base) +{ + return _csi_clint_get_load2(coret_base, 0); +} + +__STATIC_INLINE uint32_t _csi_clint_get_loadh2(unsigned long coret_base, uint16_t hartid) +{ + CLINT_Type *clint = (CLINT_Type *)coret_base; +#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE + uint64_t value = (((uint64_t)CLINT_TIMECMPn_VAL(&clint->STIMECMPH0, hartid)) << 32) + \ + (uint64_t)CLINT_TIMECMPn_VAL(&clint->STIMECMPL0, hartid); +#else + uint64_t value = (((uint64_t)CLINT_TIMECMPn_VAL(&clint->MTIMECMPH0, hartid)) << 32) + \ + (uint64_t)CLINT_TIMECMPn_VAL(&clint->MTIMECMPL0, hartid); +#endif + + return (value >> 32) & 0xFFFFFFFF; +} + +/** + \brief get CORE timer reload high value(deprecated) + \return CORE timer counter value. + */ +__STATIC_INLINE uint32_t csi_clint_get_loadh(unsigned long coret_base) +{ + return _csi_clint_get_loadh2(coret_base, 0); +} + +/** + \brief get CORE timer counter value(deprecated) + \return CORE timer counter value. + */ +__STATIC_INLINE unsigned long csi_clint_get_value(void) +{ + unsigned long result; + __ASM volatile("csrr %0, time" : "=r"(result)); + return result; +} + +/** + \brief get CORE timer counter high value(deprecated) + \return CORE timer counter value. + */ +__STATIC_INLINE uint32_t csi_clint_get_valueh(void) +{ + uint64_t result; + __ASM volatile("csrr %0, time" : "=r"(result)); + return (result >> 32) & 0xFFFFFFFF; +} + +/** + \brief CORE timer Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \param [in] IRQn core timer Interrupt number. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t csi_coret_config(uint64_t ticks, int32_t IRQn) +{ + return _csi_clint_config2(CORET_BASE, csi_get_cpu_id(), ticks, IRQn); +} + +/** + \brief get CORE timer reload value + \return CORE timer counter value. + */ +__STATIC_INLINE uint64_t csi_coret_get_load2(void) +{ + return _csi_clint_get_load2(CORET_BASE, csi_get_cpu_id()); +} + +/** + \brief get CORE timer counter value + \return CORE timer counter value. + */ +__STATIC_INLINE uint64_t csi_coret_get_value2() +{ +#if __riscv_xlen == 64 + return csi_clint_get_value(); +#else + uint64_t result; + unsigned long high, low; + + __ASM volatile("csrr %0, timeh" : "=r"(high)); + __ASM volatile("csrr %0, time" : "=r"(low)); + result = ((uint64_t)high << 32) | low; + + return result; +#endif +} + +/** + \brief Enable CoreTimer(within clint) Interrupts + */ +__ALWAYS_STATIC_INLINE void csi_coret_irq_enable(void) +{ +#if CONFIG_INTC_CLIC_PLIC + extern void soc_irq_enable(uint32_t irq_num); + return soc_irq_enable(7); +#else + return __enable_coret_irq(); +#endif +} + +/** + \brief Disable CoreTimer(within clint) Interrupts + */ +__ALWAYS_STATIC_INLINE void csi_coret_irq_disable(void) +{ +#if CONFIG_INTC_CLIC_PLIC + extern void soc_irq_disable(uint32_t irq_num); + return soc_irq_disable(7); +#else + return __disable_coret_irq(); +#endif +} + + +/*@} end of CSI_core_DebugFunctions */ + +/* ########################## Cache functions #################################### */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/** + \brief whether I-Cache enable + */ +__STATIC_INLINE int csi_icache_is_enable() +{ + uint32_t cache = __get_MHCR(); + return (cache & CACHE_MHCR_IE_Msk) >> CACHE_MHCR_IE_Pos; +} + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void csi_icache_enable(void) +{ +#if (__ICACHE_PRESENT == 1U) + if (!csi_icache_is_enable()) { + uint32_t cache; + __DSB(); + __ICACHE_IALL(); + cache = __get_MHCR(); + cache |= CACHE_MHCR_IE_Msk; + __set_MHCR(cache); + __DSB(); + } +#endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void csi_icache_disable(void) +{ +#if (__ICACHE_PRESENT == 1U) + if (csi_icache_is_enable()) { + uint32_t cache; + __DSB(); + cache = __get_MHCR(); + cache &= ~CACHE_MHCR_IE_Msk; /* disable icache */ + __set_MHCR(cache); + __ICACHE_IALL(); /* invalidate all icache */ + __DSB(); + } +#endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void csi_icache_invalid(void) +{ +#if (__ICACHE_PRESENT == 1U) + __DSB(); + __ICACHE_IALL(); /* invalidate all icache */ + __DSB(); +#endif +} + +/** + \brief whether D-Cache enable + */ +__STATIC_INLINE int csi_dcache_is_enable() +{ + uint32_t cache = __get_MHCR(); + return (cache & CACHE_MHCR_DE_Msk) >> CACHE_MHCR_DE_Pos; +} + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void csi_dcache_enable(void) +{ +#if (__DCACHE_PRESENT == 1U) + if (!csi_dcache_is_enable()) { + uint32_t cache; + __DSB(); + __DCACHE_IALL(); /* invalidate all dcache */ + cache = __get_MHCR(); + cache |= CACHE_MHCR_DE_Msk; /* enable dcache */ + __set_MHCR(cache); + + __DSB(); + } +#endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void csi_dcache_disable(void) +{ +#if (__DCACHE_PRESENT == 1U) + if (csi_dcache_is_enable()) { + uint32_t cache; + __DSB(); + cache = __get_MHCR(); + cache &= ~(uint32_t)CACHE_MHCR_DE_Msk; /* disable all Cache */ + __set_MHCR(cache); + __DCACHE_IALL(); /* invalidate all Cache */ + __DSB(); + } +#endif +} + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void csi_dcache_invalid(void) +{ +#if (__DCACHE_PRESENT == 1U) + __DSB(); + __DCACHE_IALL(); /* invalidate all Cache */ + __DSB(); +#endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void csi_dcache_clean(void) +{ +#if (__DCACHE_PRESENT == 1U) + __DSB(); + __DCACHE_CALL(); /* clean all Cache */ + __DSB(); +#endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void csi_dcache_clean_invalid(void) +{ +#if (__DCACHE_PRESENT == 1U) + __DSB(); + __DCACHE_CIALL(); /* clean and inv all Cache */ + __DSB(); +#endif +} + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 64-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void csi_dcache_invalid_range(unsigned long *addr, size_t dsize) +{ +#if (__DCACHE_PRESENT == 1U) + int linesize = csi_get_cache_line_size(); + long op_size = dsize + (unsigned long)addr % linesize; + unsigned long op_addr = (unsigned long)addr & CACHE_INV_ADDR_Msk; + + __DSB(); +#if CBO_INSN_SUPPORT + while (op_size > 0) { + __CBO_INVAL(op_addr); + op_addr += linesize; + op_size -= linesize; + } +#else + cpu_work_mode_t cpu_work_mode; + cpu_work_mode = (cpu_work_mode_t)__get_CPU_WORK_MODE(); + + if (cpu_work_mode == MACHINE_MODE) { + while (op_size > 0) { + __DCACHE_IPA(op_addr); + op_addr += linesize; + op_size -= linesize; + } + } else if (cpu_work_mode == SUPERVISOR_MODE) { + while (op_size > 0) { + __DCACHE_IVA(op_addr); + op_addr += linesize; + op_size -= linesize; + } + } +#endif + + __SYNC_IS(); + __DSB(); +#endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 64-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void csi_dcache_clean_range(unsigned long *addr, size_t dsize) +{ + +#if (__DCACHE_PRESENT == 1) + int linesize = csi_get_cache_line_size(); + long op_size = dsize + (unsigned long)addr % linesize; + unsigned long op_addr = (unsigned long) addr & CACHE_INV_ADDR_Msk; + + __DSB(); +#if CBO_INSN_SUPPORT + while (op_size > 0) { + __CBO_CLEAN(op_addr); + op_addr += linesize; + op_size -= linesize; + } +#else + cpu_work_mode_t cpu_work_mode; + cpu_work_mode = (cpu_work_mode_t)__get_CPU_WORK_MODE(); + + if (cpu_work_mode == MACHINE_MODE) { + while (op_size > 0) { + __DCACHE_CPA(op_addr); + op_addr += linesize; + op_size -= linesize; + } + } else if (cpu_work_mode == SUPERVISOR_MODE) { + while (op_size > 0) { + __DCACHE_CVA(op_addr); + op_addr += linesize; + op_size -= linesize; + } + } +#endif + __SYNC_IS(); + __DSB(); +#endif + +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 64-byte boundary) + \param[in] dsize size of memory block (aligned to 64-byte boundary) +*/ +__STATIC_INLINE void csi_dcache_clean_invalid_range(unsigned long *addr, size_t dsize) +{ +#if (__DCACHE_PRESENT == 1U) + int linesize = csi_get_cache_line_size(); + long op_size = dsize + (unsigned long)addr % linesize; + unsigned long op_addr = (unsigned long) addr & CACHE_INV_ADDR_Msk; + + __DSB(); +#if CBO_INSN_SUPPORT + while (op_size > 0) { + __CBO_FLUSH(op_addr); + op_addr += linesize; + op_size -= linesize; + } +#else + cpu_work_mode_t cpu_work_mode; + cpu_work_mode = (cpu_work_mode_t)__get_CPU_WORK_MODE(); + + if (cpu_work_mode == MACHINE_MODE) { + while (op_size > 0) { + __DCACHE_CIPA(op_addr); + op_addr += linesize; + op_size -= linesize; + } + } else if (cpu_work_mode == SUPERVISOR_MODE) { + while (op_size > 0) { + __DCACHE_CIVA(op_addr); + op_addr += linesize; + op_size -= linesize; + } + } +#endif + + __SYNC_IS(); + __DSB(); +#endif +} + +/*@} end of CSI_Core_CacheFunctions */ + +/* ########################## FPP functions #################################### */ +/** + \ingroup CSI_Core_FPPFunctionInterface + \defgroup CSI_Core_FPPFunctions FPP Functions + \brief Functions that configure FPP. + @{ + */ + +/** + \ingroup CSI_fpp_register + \defgroup CSI_FPP + \brief Type definitions for the FPP Registers + @{ + */ + +/** + \brief Consortium definition for Machine Mode FPP Configuration register(MFPPCR, 0xBC0). + */ +typedef union { + struct { + uint64_t EN: 1; /*!< bit: 0 FPP enable */ + uint64_t _reversed1: 11; /*!< bit: 1 11 Reserved */ + uint64_t Base_Address: 52; /*!< bit: 12 63 Base Address */ + } b; /*!< Structure Access by bit */ + uint64_t w; /*!< Type Access by whole register */ +} MFPPCR_Type; + +#define MFPPCR_Base_Address_Pos 12U /*!< MFPPCR: Base_Address Position */ +#define MFPPCR_Base_Address_Msk (0xFFFFFFFFFFFFFULL << MFPPCR_Base_Address_Pos) /*!< MFPPCR: Base_Address Mask */ + +#define MFPPCR_Base_EN_Pos 0U /*!< MFPPCR: Enable Bit Position */ +#define MFPPCR_Base_EN_Msk (0x1U << MFPPCR_Base_EN_Pos) /*!< MFPPCR: Enable Bit Mask */ + +/*@} end of group CSI_FPP_bitfield */ + +/** + \brief Enable FPP + \details Turns on FPP + */ +__STATIC_INLINE void csi_fpp_enable(void) +{ + __set_MFPPCR(__get_MFPPCR() | MFPPCR_Base_EN_Msk); +} + +/** + \brief Disable FPP + \details Turns off FPP + */ +__STATIC_INLINE void csi_fpp_disable(void) +{ + __set_MFPPCR(__get_MFPPCR() & (~MFPPCR_Base_EN_Msk)); +} + +/** + \brief Set FPP Base Address + \details Set FPP Base Address + \param [in] base_addr FPP Base Address. + */ +__STATIC_INLINE void csi_fpp_set_base_addr(unsigned long base_addr) +{ + __set_MFPPCR((__get_MFPPCR() & (~MFPPCR_Base_Address_Msk)) + | ((base_addr << MFPPCR_Base_Address_Pos) & MFPPCR_Base_Address_Msk)); +} + +/*@} end of CSI_Core_FPPFunctions */ + + +/* ########################## MMU functions #################################### */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_MMUFunctions MMU Functions + \brief Functions that configure MMU. + @{ + */ + +typedef enum { + PAGE_SIZE_4KB = 0x1000, + PAGE_SIZE_2MB = 0x200000, + PAGE_SIZE_1GB = 0x40000000, +} page_size_e; + +#define MMU_MODE_32 (0x1) +#define MMU_MODE_39 (0x8) +#define MMU_MODE_48 (0x9) +#define MMU_MODE_57 (0xa) +#define MMU_MODE_64 (0xb) + +/** + \brief set mmu mode(If there are multiple mmu modes) + \param[in] mode mode of the mmu + \details + */ +__STATIC_INLINE void csi_mmu_set_mode(int mode) +{ + extern int g_mmu_mode; + g_mmu_mode = mode; +} + +/** + \brief enable mmu + \details + */ +__STATIC_INLINE void csi_mmu_enable() +{ + extern int g_mmu_mode; +#if __riscv_xlen == 64 + __set_SATP(__get_SATP() | ((unsigned long)g_mmu_mode << 60)); +#else + __set_SATP(__get_SATP() | ((unsigned long)g_mmu_mode << 31)); +#endif +} + +/** + \brief disable mmu + \details + */ +__STATIC_INLINE void csi_mmu_disable(void) +{ +#if __riscv_xlen == 64 + __set_SATP(__get_SATP() & (~((unsigned long)0xf << 60))); +#else + __set_SATP(__get_SATP() & (~((unsigned long)0x1 << 31))); +#endif +} + +/** + \brief flush all mmu tlb. + \details + */ +__STATIC_INLINE void csi_mmu_invalid_tlb_all(void) +{ + __ASM volatile("sfence.vma" : : : "memory"); +} + +/*@} end of CSI_Core_MMUFunctions */ + +/* ########################## TCM functions #################################### */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_TCMFunctions TCM Functions + \brief Functions that configure TCM. + @{ + */ + +#if CONFIG_CPU_XUANTIE_C907 || CONFIG_CPU_XUANTIE_C907FD || CONFIG_CPU_XUANTIE_C907FDV || CONFIG_CPU_XUANTIE_C907FDVM \ + || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \ + || CONFIG_CPU_XUANTIE_C908X || CONFIG_CPU_XUANTIE_C908X_CP || CONFIG_CPU_XUANTIE_C908X_CP_XT \ + || CONFIG_CPU_XUANTIE_C910 || CONFIG_CPU_XUANTIE_C920 \ + || CONFIG_CPU_XUANTIE_C910V2 || CONFIG_CPU_XUANTIE_C920V2 \ + || CONFIG_CPU_XUANTIE_C910V3 || CONFIG_CPU_XUANTIE_C920V3 \ + || CONFIG_CPU_XUANTIE_C910V3_CP || CONFIG_CPU_XUANTIE_C920V3_CP \ + || CONFIG_CPU_XUANTIE_C910V3_CP_XT || CONFIG_CPU_XUANTIE_C920V3_CP_XT \ + || CONFIG_CPU_XUANTIE_R908 || CONFIG_CPU_XUANTIE_R908FD || CONFIG_CPU_XUANTIE_R908FDV \ + || CONFIG_CPU_XUANTIE_R908_CP || CONFIG_CPU_XUANTIE_R908FD_CP || CONFIG_CPU_XUANTIE_R908FDV_CP \ + || CONFIG_CPU_XUANTIE_R908_CP_XT || CONFIG_CPU_XUANTIE_R908FD_CP_XT || CONFIG_CPU_XUANTIE_R908FDV_CP_XT \ + || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 +/** + \ingroup CSI_tcm_register + \defgroup CSI_TCM + \brief Type definitions for the tcm Registers + @{ + */ + +/** + \brief Consortium definition for accessing protection area selection register(MITCMCR, 0x7f9). + */ +typedef union { + struct { + unsigned long EN: 1; /*!< bit: 0 Instruction Tightly-Coupled Memory enable */ + unsigned long ECC_EN: 1; /*!< bit: 1 ecc_en */ + unsigned long Interleave: 1; /*!< bit: 2 Interleave */ + unsigned long _reserved1: 1; /*!< bit: 3 Reserved */ + unsigned long Size: 4; /*!< bit: 4..7 Size of ITCM */ + unsigned long _reserved2: 4; /*!< bit: 8..11 Reserved */ + unsigned long Base_Address: 52; /*!< bit: 12..63 Base address of DTCM */ + } b; /*!< Structure Access by bit */ + unsigned long w; /*!< Type Access by whole register */ +} MITCMCR_Type; + +#define MITCMCR_Base_Address_Pos 12U /*!< MITCMCR: Base_Address Position */ +#define MITCMCR_Base_Address_Msk (0xfffffffffffffULL << MITCMCR_Base_Address_Pos) /*!< MITCMCR: Base_Address Mask */ + +#define MITCMCR_Size_Pos 4U /*!< MITCMCR: Size Position */ +#define MITCMCR_Size_Msk (0xfULL << MITCMCR_Size_Pos) /*!< MITCMCR: Size Mask */ + +#define MITCMCR_INTERLEAVE_Pos 2U /*!< MITCMCR: Interleave Position */ +#define MITCMCR_INTERLEAVE_Msk (0x1ULL << MITCMCR_INTERLEAVE_Pos) /*!< MITCMCR: Interleave Mask */ + +#define MITCMCR_ECC_EN_Pos 1U /*!< MITCMCR: ECC_EN Position */ +#define MITCMCR_ECC_EN_Msk (0x1ULL << MITCMCR_ECC_EN_Pos) /*!< MITCMCR: ECC_EN Mask */ + +#define MITCMCR_EN_Pos 0U /*!< MITCMCR: EN Position */ +#define MITCMCR_EN_Msk (0x1ULL << MITCMCR_EN_Pos) /*!< MITCMCR: EN Mask */ + +/** + \brief Consortium definition for accessing protection area selection register(MDTCMCR, 0x7f8). + */ +typedef union { + struct { + unsigned long EN: 1; /*!< bit: 0 Data Tightly-Coupled Memory enable */ + unsigned long ECC_EN: 1; /*!< bit: 1 ecc_en */ + unsigned long Interleave: 1; /*!< bit: 2 Interleave */ + unsigned long _reserved1: 1; /*!< bit: 3 Reserved */ + unsigned long Size: 4; /*!< bit: 4..7 Size of ITCM */ + unsigned long _reserved2: 4; /*!< bit: 8..11 Reserved */ + unsigned long Base_Address: 52; /*!< bit: 12..63 Base address of DTCM */ + } b; /*!< Structure Access by bit */ + unsigned long w; /*!< Type Access by whole register */ +} MDTCMCR_Type; + +#define MDTCMCR_Base_Address_Pos 12U /*!< MDTCMCR: Base_Address Position */ +#define MDTCMCR_Base_Address_Msk (0xfffffffffffffULL << MDTCMCR_Base_Address_Pos) /*!< MDTCMCR: Base_Address Mask */ + +#define MDTCMCR_Size_Pos 4U /*!< MDTCMCR: Size Position */ +#define MDTCMCR_Size_Msk (0xfULL << MDTCMCR_Size_Pos) /*!< MDTCMCR: Size Mask */ + +#define MDTCMCR_INTERLEAVE_Pos 2U /*!< MDTCMCR: Interleave Position */ +#define MDTCMCR_INTERLEAVE_Msk (0x1ULL << MDTCMCR_INTERLEAVE_Pos) /*!< MDTCMCR: Interleave Mask */ + +#define MDTCMCR_ECC_EN_Pos 1U /*!< MDTCMCR: ECC_EN Position */ +#define MDTCMCR_ECC_EN_Msk (0x1ULL << MDTCMCR_ECC_EN_Pos) /*!< MDTCMCR: ECC_EN Mask */ + +#define MDTCMCR_EN_Pos 0U /*!< MDTCMCR: EN Position */ +#define MDTCMCR_EN_Msk (0x1ULL << MDTCMCR_EN_Pos) /*!< MDTCMCR: EN Mask */ + +/*@} end of group CSI_TCM_bitfield */ + +/** + \brief Enable ITCM + \details Turns on ITCM + */ +__STATIC_INLINE void csi_itcm_enable (void) +{ + __set_MITCMCR(__get_MITCMCR() | MITCMCR_EN_Msk); +} + +/** + \brief Enable DTCM + \details Turns on DTCM + */ +__STATIC_INLINE void csi_dtcm_enable (void) +{ + __set_MDTCMCR(__get_MDTCMCR() | MDTCMCR_EN_Msk); +} + +/** + \brief Enable ITCM + \details Turns on ITCM + */ +__STATIC_INLINE void csi_itcm_disable (void) +{ + __set_MITCMCR(__get_MITCMCR() & (~MITCMCR_EN_Msk)); +} + +/** + \brief Enable DTCM + \details Turns on DTCM + */ +__STATIC_INLINE void csi_dtcm_disable (void) +{ + __set_MDTCMCR(__get_MDTCMCR() & (~MDTCMCR_EN_Msk)); +} + +/** + \brief Get ITCM Size + \details Get ITCM Size + \return ITCM size (bytes). + */ +__STATIC_INLINE uint32_t csi_itcm_get_size(void) +{ + MITCMCR_Type sizemask; + uint32_t ret; + + sizemask.w = __get_MITCMCR(); + switch (sizemask.b.Size) + { + case 0x3: ret = 8 << 10; break; + case 0x4: ret = 16 << 10; break; + case 0x5: ret = 32 << 10; break; + case 0x6: ret = 64 << 10; break; + case 0x7: ret = 128 << 10; break; + case 0x8: ret = 256 << 10; break; + case 0x9: ret = 512 << 10; break; + case 0xa: ret = 1024 << 10; break; + default: ret = 0; break; + } + return ret; +} + +/** + \brief Get DTCM Size + \details Get DTCM Size + \return DTCM size (bytes). + */ +__STATIC_INLINE uint32_t csi_dtcm_get_size(void) +{ + MDTCMCR_Type sizemask; + uint32_t ret; + + sizemask.w = __get_MDTCMCR(); + switch (sizemask.b.Size) + { + case 0x3: ret = 8 << 10; break; + case 0x4: ret = 16 << 10; break; + case 0x5: ret = 32 << 10; break; + case 0x6: ret = 64 << 10; break; + case 0x8: ret = 128 << 10; break; + case 0x9: ret = 256 << 10; break; + case 0xa: ret = 512 << 10; break; + case 0xb: ret = 1024 << 10; break; + default:ret = 0; break; + } + return ret; +} + +/** + \brief Set ITCM Base Address + \details Set ITCM Base Address + \param [in] base_addr itcm base address. + */ +__STATIC_INLINE void csi_itcm_set_base_addr(unsigned long base_addr) +{ + __set_MITCMCR((__get_MITCMCR() & (~MITCMCR_Base_Address_Msk)) | (base_addr << MITCMCR_Base_Address_Pos)); +} + +/** + \brief Set DTCM Base Address + \details Set DTCM Base Address + \param [in] base_addr dtcm base address. + */ +__STATIC_INLINE void csi_dtcm_set_base_addr(unsigned long base_addr) +{ + __set_MDTCMCR((__get_MDTCMCR() & (~MDTCMCR_Base_Address_Msk)) | (base_addr << MDTCMCR_Base_Address_Pos)); +} + +/*@} end of CSI_Core_TCMFunctions */ + +/* ########################## ECC functions #################################### */ + +/** + * \brief Enable ITCM-ECC + * \details Turns on ITCM-ECC + * */ +__STATIC_INLINE void csi_itcm_ecc_enable (void) +{ + __set_MITCMCR(__get_MITCMCR() | MITCMCR_ECC_EN_Msk); +} + +/** + * \brief Disable ITCM-ECC + * \details Turns off ITCM-ECC + * */ +__STATIC_INLINE void csi_itcm_ecc_disable (void) +{ + __set_MITCMCR(__get_MITCMCR() & (~MITCMCR_ECC_EN_Msk)); +} + +/** + * \brief Enable DTCM-ECC + * \details Turns on DTCM-ECC + * */ +__STATIC_INLINE void csi_dtcm_ecc_enable (void) +{ + __set_MDTCMCR(__get_MDTCMCR() | MDTCMCR_ECC_EN_Msk); +} + +/** + * \brief Disable DTCM-ECC + * \details Turns off DTCM-ECC + * */ +__STATIC_INLINE void csi_dtcm_ecc_disable (void) +{ + __set_MDTCMCR(__get_MDTCMCR() & (~MDTCMCR_ECC_EN_Msk)); +} + +/*@} end of CSI_Core_ECCFunctions */ +#endif /* end ecc */ + +/* ################################## IRQ Functions ############################################ */ + +/** + \brief Save the Irq context + \details save the psr result before disable irq. + */ +__STATIC_INLINE unsigned long csi_irq_save(void) +{ + unsigned long result; +#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE + result = __get_SSTATUS(); +#else + result = __get_MSTATUS(); +#endif + __disable_irq(); + return(result); +} + +/** + \brief Restore the Irq context + \details restore saved primask state. + \param [in] irq_state psr irq state. + */ +__STATIC_INLINE void csi_irq_restore(unsigned long irq_state) +{ +#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE + __set_SSTATUS(irq_state); +#else + __set_MSTATUS(irq_state); +#endif +} + +/*@} end of IRQ Functions */ + +/** + \brief Get the byte-width of vector register + \return the byte-width of vector register + */ +__STATIC_INLINE int csi_vlenb_get_value(void) +{ + int result; + __ASM volatile("csrr %0, vlenb" : "=r"(result) : : "memory"); + return result; +} + +#if __riscv_matrix || __riscv_xtheadmatrix +/** + \brief Get the bytes of matrix per register + \return the bytes of matrix per register + */ +__STATIC_INLINE int csi_xmlenb_get_value(void) +{ + int result; + __ASM volatile("csrr %0, xmlenb" : "=r"(result) : : "memory"); + return result; +} +#endif /* __riscv_matrix || __riscv_xtheadmatrix */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_RV32_H_DEPENDANT */ + +#endif /* __CSI_GENERIC */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/csi_gcc.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/csi_gcc.h new file mode 100644 index 00000000..75b42742 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/csi_gcc.h @@ -0,0 +1,3293 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file csi_gcc.h + * @brief CSI Header File for GCC. + * @version V1.0 + * @date 02. June 2020 + ******************************************************************************/ + +#ifndef _CSI_GCC_H_ +#define _CSI_GCC_H_ + +#include +#include + +#ifndef __ASM +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#endif + +#ifndef __INLINE +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#endif + +#ifndef __ALWAYS_STATIC_INLINE +#define __ALWAYS_STATIC_INLINE __attribute__((always_inline)) static inline +#endif + +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif + +#ifndef __NO_RETURN +#define __NO_RETURN __attribute__((__noreturn__)) +#endif + +#ifndef __USED +#define __USED __attribute__((used)) +#endif + +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif + +#ifndef __PACKED +#define __PACKED __attribute__((packed, aligned(1))) +#endif + +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif + +#ifndef __PACKED_UNION +#define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_RegAccFunctions CSI Core Register Access Functions + @{ + */ +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by setting the IE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile("psrset ie"); +} + + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by clearing the IE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile("psrclr ie"); +} + +/** + \brief Get PSR + \details Returns the content of the PSR Register. + \return PSR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_PSR(void) +{ + uint32_t result; + + __ASM volatile("mfcr %0, psr" : "=r"(result) :: "memory"); + return (result); +} + +/** + \brief Set PSR + \details Writes the given value to the PSR Register. + \param [in] psr PSR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_PSR(uint32_t psr) +{ + __ASM volatile("mtcr %0, psr" : : "r"(psr) : "memory"); +} + +/** + \brief Get SP + \details Returns the content of the SP Register. + \return SP Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_SP(void) +{ + uint32_t result; + + __ASM volatile("mov %0, sp" : "=r"(result)); + return (result); +} + +/** + \brief Set SP + \details Writes the given value to the SP Register. + \param [in] sp SP Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_SP(uint32_t sp) +{ + __ASM volatile("mov sp, %0" : : "r"(sp): "sp"); +} + +/** + \brief Get Int SP + \details Returns the content of the Int SP Register. + \return Int SP Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_Int_SP(void) +{ + uint32_t result; + + __ASM volatile("mfcr %0, cr<15, 1>" : "=r"(result)); + return (result); +} + +/** + \brief Set Int SP + \details Writes the given value to the Int SP Register. + \param [in] sp Int SP Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_Int_SP(uint32_t sp) +{ + __ASM volatile("mtcr %0, cr<15, 1>" : : "r"(sp)); +} + +/** + \brief Get VBR Register + \details Returns the content of the VBR Register. + \return VBR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_VBR(void) +{ + uint32_t result; + + __ASM volatile("mfcr %0, vbr" : "=r"(result)); + return (result); +} + +/** + \brief Set VBR + \details Writes the given value to the VBR Register. + \param [in] vbr VBR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_VBR(uint32_t vbr) +{ + __ASM volatile("mtcr %0, vbr" : : "r"(vbr)); +} + +/** + \brief Get EPC Register + \details Returns the content of the EPC Register. + \return EPC Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_EPC(void) +{ + uint32_t result; + + __ASM volatile("mfcr %0, epc" : "=r"(result)); + return (result); +} + +/** + \brief Set EPC + \details Writes the given value to the EPC Register. + \param [in] epc EPC Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_EPC(uint32_t epc) +{ + __ASM volatile("mtcr %0, epc" : : "r"(epc)); +} + +/** + \brief Get EPSR + \details Returns the content of the EPSR Register. + \return EPSR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_EPSR(void) +{ + uint32_t result; + + __ASM volatile("mfcr %0, epsr" : "=r"(result)); + return (result); +} + +/** + \brief Set EPSR + \details Writes the given value to the EPSR Register. + \param [in] epsr EPSR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_EPSR(uint32_t epsr) +{ + __ASM volatile("mtcr %0, epsr" : : "r"(epsr)); +} + +/** + \brief Get CPUID Register + \details Returns the content of the CPUID Register. + \return CPUID Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_CPUID(void) +{ + uint32_t result; + +#ifdef __CK610 + __ASM volatile("mfcr %0, cr13" : "=r"(result)); +#else + __ASM volatile("mfcr %0, cr<13, 0>" : "=r"(result)); +#endif + return (result); +} + +/** + \brief Get CCR + \details Returns the current value of the CCR. + \return CCR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_CCR(void) +{ + register uint32_t result; + +#ifdef __CK610 + __ASM volatile("mfcr %0, cr18\n" : "=r"(result)); +#else + __ASM volatile("mfcr %0, cr<18, 0>\n" : "=r"(result)); +#endif + return (result); +} + + +/** + \brief Set CCR + \details Assigns the given value to the CCR. + \param [in] ccr CCR value to set + */ +__ALWAYS_STATIC_INLINE void __set_CCR(uint32_t ccr) +{ +#ifdef __CK610 + __ASM volatile("mtcr %0, cr18\n" : : "r"(ccr)); +#else + __ASM volatile("mtcr %0, cr<18, 0>\n" : : "r"(ccr)); +#endif +} + +/** + \brief Get CCR2 + \details Returns the current value of the CCR2. + \return CCR2 Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_CCR2(void) +{ + register uint32_t result; + + __ASM volatile("mfcr %0, cr<31, 0>\n" : "=r"(result)); + return (result); +} + +/** + \brief Set CCR2 + \details Assigns the given value to the CCR2. + \param [in] ccr2 CCR2 value to set + */ +__ALWAYS_STATIC_INLINE void __set_CCR2(uint32_t ccr2) +{ + __ASM volatile("mtcr %0, cr<31, 0>\n" : : "r"(ccr2)); +} + +/** + \brief Get DCSR + \details Returns the content of the DCSR Register. + \return DCSR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_DCSR(void) +{ + uint32_t result; +#ifdef __CK610 + __ASM volatile("mfcr %0, cr14" : "=r"(result)); +#else + __ASM volatile("mfcr %0, cr<14, 0>" : "=r"(result)); +#endif + return (result); +} + + +/** + \brief Set DCSR + \details Writes the given value to the DCSR Register. + \param [in] dcsr DCSR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_DCSR(uint32_t dcsr) +{ +#ifdef __CK610 + __ASM volatile("mtcr %0, cr14" : : "r"(dcsr)); +#else + __ASM volatile("mtcr %0, cr<14, 0>" : : "r"(dcsr)); +#endif +} + + +/** + \brief Get CFR + \details Returns the content of the CFR Register. + \return CFR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_CFR(void) +{ + uint32_t result; +#ifdef __CK610 + __ASM volatile("mfcr %0, cr17" : "=r"(result)); +#else + __ASM volatile("mfcr %0, cr<17, 0>" : "=r"(result)); +#endif + + return (result); +} + + +/** + \brief Set CFR + \details Writes the given value to the CFR Register. + \param [in] cfr CFR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_CFR(uint32_t cfr) +{ +#ifdef __CK610 + __ASM volatile("mtcr %0, cr17" : : "r"(cfr)); +#else + __ASM volatile("mtcr %0, cr<17, 0>" : : "r"(cfr)); +#endif +} + + +/** + \brief Get CIR + \details Returns the content of the CIR Register. + \return CIR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_CIR(void) +{ + uint32_t result; +#ifdef __CK610 + __ASM volatile("mfcr %0, cr22" : "=r"(result)); +#else + __ASM volatile("mfcr %0, cr<22, 0>" : "=r"(result)); +#endif + return (result); +} + + +/** + \brief Set CIR + \details Writes the given value to the CIR Register. + \param [in] cir CIR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_CIR(uint32_t cir) +{ +#ifdef __CK610 + __ASM volatile("mtcr %0, cr22" : : "r"(cir)); +#else + __ASM volatile("mtcr %0, cr<22, 0>" : : "r"(cir)); +#endif +} + +/** + \brief Get ERRLC + \details Returns the current value of the ERRLC. + \return ERRLC Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_ERRLC(void) +{ + register uint32_t result; + + __ASM volatile("mfcr %0, cr<6, 1>\n" : "=r"(result)); + return (result); +} + +/** + \brief Set ERRLC + \details Assigns the given value to the ERRLC. + \param [in] errlc ERRLC value to set + */ +__ALWAYS_STATIC_INLINE void __set_ERRLC(uint32_t errlc) +{ + __ASM volatile("mtcr %0, cr<6, 1>\n" : : "r"(errlc)); +} + +/** + \brief Get ERRADDR + \details Returns the current value of the ERRADDR. + \return ERRADDR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_ERRADDR(void) +{ + register uint32_t result; + + __ASM volatile("mfcr %0, cr<7, 1>\n" : "=r"(result)); + return (result); +} + +/** + \brief Set ERRADDR + \details Assigns the given value to the ERRADDR. + \param [in] erraddr ERRADDR value to set + */ +__ALWAYS_STATIC_INLINE void __set_ERRADDR(uint32_t erraddr) +{ + __ASM volatile("mtcr %0, cr<7, 1>\n" : : "r"(erraddr)); +} + +/** + \brief Get ERRSTS + \details Returns the current value of the ERRSTS. + \return ERRSTS Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_ERRSTS(void) +{ + register uint32_t result; + + __ASM volatile("mfcr %0, cr<8, 1>\n" : "=r"(result)); + return (result); +} + +/** + \brief Set ERRSTS + \details Assigns the given value to the ERRSTS. + \param [in] errsts ERRSTS value to set + */ +__ALWAYS_STATIC_INLINE void __set_ERRSTS(uint32_t errsts) +{ + __ASM volatile("mtcr %0, cr<8, 1>\n" : : "r"(errsts)); +} + +/** + \brief Get ERRINJCR + \details Returns the current value of the ERRINJCR. + \return ERRINJCR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_ERRINJCR(void) +{ + register uint32_t result; + + __ASM volatile("mfcr %0, cr<9, 1>\n" : "=r"(result)); + return (result); +} + +/** + \brief Set ERRINJCR + \details Assigns the given value to the ERRINJCR. + \param [in] errinjcr ERRINJCR value to set + */ +__ALWAYS_STATIC_INLINE void __set_ERRINJCR(uint32_t errinjcr) +{ + __ASM volatile("mtcr %0, cr<9, 1>\n" : : "r"(errinjcr)); +} + +/** + \brief Get ERRINJCNT + \details Returns the current value of the ERRINJCNT. + \return ERRINJCNT Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_ERRINJCNT(void) +{ + register uint32_t result; + + __ASM volatile("mfcr %0, cr<10, 1>\n" : "=r"(result)); + return (result); +} + +/** + \brief Set ERRINJCNT + \details Assigns the given value to the ERRINJCNT. + \param [in] errinjcnt ERRINJCNT value to set + */ +__ALWAYS_STATIC_INLINE void __set_ERRINJCNT(uint32_t errinjcnt) +{ + __ASM volatile("mtcr %0, cr<10, 1>\n" : : "r"(errinjcnt)); +} + +/** + \brief Get ITCMCR + \details Returns the content of the ITCMCR Register. + \return ITCMCR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_ITCMCR(void) +{ + uint32_t result; + __ASM volatile("mfcr %0, cr<22, 1>" : "=r"(result)); + return (result); +} + +/** + \brief Set ITCMCR + \details Writes the given value to the ITCMCR Register. + \param [in] itcmcr ITCMCR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_ITCMCR(uint32_t itcmcr) +{ + __ASM volatile("mtcr %0, cr<22, 1>" : : "r"(itcmcr)); +} + +/** + \brief Get DTCMCR + \details Returns the content of the DTCMCR Register. + \return DTCMCR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_DTCMCR(void) +{ + uint32_t result; + __ASM volatile("mfcr %0, cr<23, 1>" : "=r"(result)); + return (result); +} + +/** + \brief Set DTCMCR + \details Writes the given value to the DTCMCR Register. + \param [in] dtcmcr DTCMCR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_DTCMCR(uint32_t dtcmcr) +{ + __ASM volatile("mtcr %0, cr<23, 1>" : : "r"(dtcmcr)); +} + +/** + \brief Get CINDEX + \details Returns the current value of the CINDEX. + \return CINDEX Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_CINDEX(void) +{ + register uint32_t result; + + __ASM volatile("mfcr %0, cr<26, 1>\n" : "=r"(result)); + return (result); +} + +/** + \brief Set CINDEX + \details Assigns the given value to the CINDEX. + \param [in] cindex CINDEX value to set + */ +__ALWAYS_STATIC_INLINE void __set_CINDEX(uint32_t cindex) +{ + __ASM volatile("mtcr %0, cr<26, 1>\n" : : "r"(cindex)); +} + +/** + \brief Get CDATAx + \details Returns the current value of the CDATAx. + \return CDATAx Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_CDATA0(void) +{ + register uint32_t result; + + __ASM volatile("mfcr %0, cr<27, 1>\n" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_CDATA1(void) +{ + register uint32_t result; + + __ASM volatile("mfcr %0, cr<28, 1>\n" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_CDATA2(void) +{ + register uint32_t result; + + __ASM volatile("mfcr %0, cr<29, 1>\n" : "=r"(result)); + return (result); +} + +/** + \brief Set CDATAx + \details Assigns the given value to the CDATAx. + \param [in] cdata CDATAx value to set + */ +__ALWAYS_STATIC_INLINE void __set_CDATA0(uint32_t cdata) +{ + __ASM volatile("mtcr %0, cr<27, 1>\n" : : "r"(cdata)); +} + +__ALWAYS_STATIC_INLINE void __set_CDATA1(uint32_t cdata) +{ + __ASM volatile("mtcr %0, cr<28, 1>\n" : : "r"(cdata)); +} + +__ALWAYS_STATIC_INLINE void __set_CDATA2(uint32_t cdata) +{ + __ASM volatile("mtcr %0, cr<29, 1>\n" : : "r"(cdata)); +} + +/** + \brief Get CINS + \details Returns the current value of the CINS. + \return CINS Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_CINS(void) +{ + register uint32_t result; + + __ASM volatile("mfcr %0, cr<31, 1>\n" : "=r"(result)); + return (result); +} + +/** + \brief Set CINS + \details Assigns the given value to the CINS. + \param [in] cins CINS value to set + */ +__ALWAYS_STATIC_INLINE void __set_CINS(uint32_t cins) +{ + __ASM volatile("mtcr %0, cr<31, 1>\n" : : "r"(cins)); +} + +/** + \brief Get CAPR + \details Returns the current value of the CAPR. + \return CAPR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_CAPR(void) +{ + register uint32_t result; + +#ifdef __CK610 + __ASM volatile("mfcr %0, cr19\n" : "=r"(result)); +#else + __ASM volatile("mfcr %0, cr<19, 0>\n" : "=r"(result)); +#endif + return (result); +} + +/** + \brief Set CAPR + \details Assigns the given value to the CAPR. + \param [in] capr CAPR value to set + */ +__ALWAYS_STATIC_INLINE void __set_CAPR(uint32_t capr) +{ +#ifdef __CK610 + __ASM volatile("mtcr %0, cr19\n" : : "r"(capr)); +#else + __ASM volatile("mtcr %0, cr<19, 0>\n" : : "r"(capr)); +#endif +} + +/** + \brief Get CAPR1 + \details Returns the current value of the CAPR1. + \return CAPR1 Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_CAPR1(void) +{ + register uint32_t result; + + __ASM volatile("mfcr %0, cr<16, 0>\n" : "=r"(result)); + return (result); +} + +/** + \brief Set CAPR1 + \details Assigns the given value to the CAPR1. + \param [in] capr1 CAPR1 value to set + */ +__ALWAYS_STATIC_INLINE void __set_CAPR1(uint32_t capr1) +{ + __ASM volatile("mtcr %0, cr<16, 0>\n" : : "r"(capr1)); +} + +/** + \brief Set PACR + \details Assigns the given value to the PACR. + + \param [in] pacr PACR value to set + */ +__ALWAYS_STATIC_INLINE void __set_PACR(uint32_t pacr) +{ +#ifdef __CK610 + __ASM volatile("mtcr %0, cr20\n" : : "r"(pacr)); +#else + __ASM volatile("mtcr %0, cr<20, 0>\n" : : "r"(pacr)); +#endif +} + + +/** + \brief Get PACR + \details Returns the current value of PACR. + \return PACR value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_PACR(void) +{ + uint32_t result; + +#ifdef __CK610 + __ASM volatile("mfcr %0, cr20" : "=r"(result)); +#else + __ASM volatile("mfcr %0, cr<20, 0>" : "=r"(result)); +#endif + return (result); +} + +/** + \brief Set PRSR + \details Assigns the given value to the PRSR. + + \param [in] prsr PRSR value to set + */ +__ALWAYS_STATIC_INLINE void __set_PRSR(uint32_t prsr) +{ +#ifdef __CK610 + __ASM volatile("mtcr %0, cr21\n" : : "r"(prsr)); +#else + __ASM volatile("mtcr %0, cr<21, 0>\n" : : "r"(prsr)); +#endif +} + +/** + \brief Get PRSR + \details Returns the current value of PRSR. + \return PRSR value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_PRSR(void) +{ + uint32_t result; + +#ifdef __CK610 + __ASM volatile("mfcr %0, cr21" : "=r"(result)); +#else + __ASM volatile("mfcr %0, cr<21, 0>" : "=r"(result)); +#endif + return (result); +} + +/** + \brief Set ATTR0 + \details Assigns the given value to the ATTR0. + + \param [in] attr0 ATTR0 value to set + */ +__ALWAYS_STATIC_INLINE void __set_ATTR0(uint32_t attr0) +{ + __ASM volatile("mtcr %0, cr<26, 0>\n" : : "r"(attr0)); +} + +/** + \brief Get ATTR0 + \details Returns the current value of ATTR0. + \return ATTR0 value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_ATTR0(void) +{ + uint32_t result; + + __ASM volatile("mfcr %0, cr<26, 0>" : "=r"(result)); + + return (result); +} + +/** + \brief Set ATTR1 + \details Assigns the given value to the ATTR1. + + \param [in] attr0 ATTR1 value to set + */ +__ALWAYS_STATIC_INLINE void __set_ATTR1(uint32_t attr1) +{ + __ASM volatile("mtcr %0, cr<27, 0>\n" : : "r"(attr1)); +} + +/** + \brief Get ATTR1 + \details Returns the current value of ATTR1. + \return ATTR1 value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_ATTR1(void) +{ + uint32_t result; + + __ASM volatile("mfcr %0, cr<27, 0>" : "=r"(result)); + + return (result); +} + +/** + \brief Get user sp + \details Returns the current value of user r14. + \return UR14 value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_UR14(void) +{ + uint32_t result; + +#ifdef __CK610 + __ASM volatile("mov %0, sp" : "=r"(result)); +#else + __ASM volatile("mfcr %0, cr<14, 1>" : "=r"(result)); +#endif + return (result); +} + +/** + \brief Set UR14 + \details Assigns the given value to the UR14. + \param [in] ur14 UR14 value to set + */ +__ALWAYS_STATIC_INLINE void __set_UR14(uint32_t ur14) +{ +#ifdef __CK610 + __ASM volatile("mov sp, %0" : "=r"(ur14)); +#else + __ASM volatile("mtcr %0, cr<14, 1>\n" : : "r"(ur14)); +#endif +} + +/** + \brief Get CHR Register + \details Returns the content of the CHR Register. + \return CHR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_CHR(void) +{ + uint32_t result; + + __ASM volatile("mfcr %0, cr<31, 0>\n" :"=r"(result)); + return (result); +} + +/** + \brief Set CHR + \details Assigns the given value to the CHR. + \param [in] chr CHR value to set + */ +__ALWAYS_STATIC_INLINE void __set_CHR(uint32_t chr) +{ + __ASM volatile("mtcr %0, cr<31, 0>\n" : : "r"(chr)); +} + +/** + \brief Get HINT + \details Returns the content of the HINT Register. + \return HINT Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_HINT(void) +{ + uint32_t result; +#ifdef __CK610 + __ASM volatile("mfcr %0, cr<30, 0>" : "=r"(result)); +#else + __ASM volatile("mfcr %0, cr<31, 0>" : "=r"(result)); +#endif + return (result); +} + +/** + \brief Set HINT + \details Writes the given value to the HINT Register. + \param [in] hint HINT Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_HINT(uint32_t hint) +{ +#ifdef __CK610 + __ASM volatile("mtcr %0, cr<30, 0>" : "=r"(hint)); +#else + __ASM volatile("mtcr %0, cr<31, 0>" : : "r"(hint)); +#endif +} + +/** + \brief Get MIR + \details Returns the content of the MIR Register. + \return MIR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MIR(void) +{ + uint32_t result; +#ifdef __CK610 + __ASM volatile("cpseti 15"); + __ASM volatile("cprcr %0, cpcr0" : "=r"(result)); +#else + __ASM volatile("mfcr %0, cr<0, 15>" : "=r"(result)); +#endif + return (result); +} + +/** + \brief Set MIR + \details Writes the given value to the MIR Register. + \param [in] mir MIR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MIR(uint32_t mir) +{ +#ifdef __CK610 + __ASM volatile("cpseti 15"); + __ASM volatile("cpwcr %0, cpcr0" : : "b"(mir)); +#else + __ASM volatile("mtcr %0, cr<0, 15>" : : "r"(mir)); +#endif +} + + +/** + \brief Get MEL0 + \details Returns the content of the MEL0 Register. + \return MEL0 Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MEL0(void) +{ + uint32_t result; +#ifdef __CK610 + __ASM volatile("cpseti 15"); + __ASM volatile("cprcr %0, cpcr2" : "=r"(result)); +#else + __ASM volatile("mfcr %0, cr<2, 15>" : "=r"(result)); +#endif + return (result); +} + +/** + \brief Set MEL0 + \details Writes the given value to the MEL0 Register. + \param [in] mel0 MEL0 Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MEL0(uint32_t mel0) +{ +#ifdef __CK610 + __ASM volatile("cpseti 15"); + __ASM volatile("cpwcr %0, cpcr2" : : "b"(mel0)); +#else + __ASM volatile("mtcr %0, cr<2, 15>" : : "r"(mel0)); +#endif +} + + +/** + \brief Get MEL1 + \details Returns the content of the MEL1 Register. + \return MEL1 Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MEL1(void) +{ + uint32_t result; +#ifdef __CK610 + __ASM volatile("cpseti 15"); + __ASM volatile("cprcr %0, cpcr3" : "=r"(result)); +#else + __ASM volatile("mfcr %0, cr<3, 15>" : "=r"(result)); +#endif + return (result); +} + +/** + \brief Set MEL1 + \details Writes the given value to the MEL1 Register. + \param [in] mel1 MEL1 Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MEL1(uint32_t mel1) +{ +#ifdef __CK610 + __ASM volatile("cpseti 15"); + __ASM volatile("cpwcr %0, cpcr3" : : "b"(mel1)); +#else + __ASM volatile("mtcr %0, cr<3, 15>" : : "r"(mel1)); +#endif +} + + +/** + \brief Get MEH + \details Returns the content of the MEH Register. + \return MEH Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MEH(void) +{ + uint32_t result; +#ifdef __CK610 + __ASM volatile("cpseti 15"); + __ASM volatile("cprcr %0, cpcr4" : "=r"(result)); +#else + __ASM volatile("mfcr %0, cr<4, 15>" : "=r"(result)); +#endif + return (result); +} + +/** + \brief Set MEH + \details Writes the given value to the MEH Register. + \param [in] meh MEH Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MEH(uint32_t meh) +{ +#ifdef __CK610 + __ASM volatile("cpseti 15"); + __ASM volatile("cpwcr %0, cpcr4" : : "b"(meh)); +#else + __ASM volatile("mtcr %0, cr<4, 15>" : : "r"(meh)); +#endif +} + + +/** + \brief Get MPR + \details Returns the content of the MPR Register. + \return MPR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MPR(void) +{ + uint32_t result; +#ifdef __CK610 + __ASM volatile("cpseti 15"); + __ASM volatile("cprcr %0, cpcr6" : "=r"(result)); +#else + __ASM volatile("mfcr %0, cr<6, 15>" : "=r"(result)); +#endif + return (result); +} + +/** + \brief Set MPR + \details Writes the given value to the MPR Register. + \param [in] mpr MPR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MPR(uint32_t mpr) +{ +#ifdef __CK610 + __ASM volatile("cpseti 15"); + __ASM volatile("cpwcr %0, cpcr6" : : "b"(mpr)); +#else + __ASM volatile("mtcr %0, cr<6, 15>" : : "r"(mpr)); +#endif +} + + +/** + \brief Get MCIR + \details Returns the content of the MCIR Register. + \return MCIR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MCIR(void) +{ + uint32_t result; +#ifdef __CK610 + __ASM volatile("cpseti 15"); + __ASM volatile("cprcr %0, cpcr8" : "=r"(result)); +#else + __ASM volatile("mfcr %0, cr<8, 15>" : "=r"(result)); +#endif + return (result); +} + +/** + \brief Set MCIR + \details Writes the given value to the MCIR Register. + \param [in] mcir MCIR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MCIR(uint32_t mcir) +{ +#ifdef __CK610 + __ASM volatile("cpseti 15"); + __ASM volatile("cpwcr %0, cpcr8" : : "b"(mcir)); +#else + __ASM volatile("mtcr %0, cr<8, 15>" : : "r"(mcir)); +#endif +} + + +/** + \brief Get MPGD + \details Returns the content of the MPGD Register. + \return MPGD Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MPGD(void) +{ + uint32_t result; +#ifdef __CK610 + __ASM volatile("cpseti 15"); + __ASM volatile("cprcr %0, cpcr29" : "=r"(result)); +#else + __ASM volatile("mfcr %0, cr<29, 15>" : "=r"(result)); +#endif + return (result); +} + +/** + \brief Set MPGD + \details Writes the given value to the MPGD Register. + \param [in] mpgd MPGD Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MPGD(uint32_t mpgd) +{ +#ifdef __CK610 + __ASM volatile("cpseti 15"); + __ASM volatile("cpwcr %0, cpcr29" : : "b"(mpgd)); +#else + __ASM volatile("mtcr %0, cr<29, 15>" : : "r"(mpgd)); +#endif +} + + +/** + \brief Get MSA0 + \details Returns the content of the MSA0 Register. + \return MSA0 Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MSA0(void) +{ + uint32_t result; +#ifdef __CK610 + __ASM volatile("cpseti 15"); + __ASM volatile("cprcr %0, cpcr30" : "=r"(result)); +#else + __ASM volatile("mfcr %0, cr<30, 15>" : "=r"(result)); +#endif + return (result); +} + +/** + \brief Set MSA0 + \details Writes the given value to the MSA0 Register. + \param [in] msa0 MSA0 Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MSA0(uint32_t msa0) +{ +#ifdef __CK610 + __ASM volatile("cpseti 15"); + __ASM volatile("cpwcr %0, cpcr30" : : "b"(msa0)); +#else + __ASM volatile("mtcr %0, cr<30, 15>" : : "r"(msa0)); +#endif +} + + +/** + \brief Get MSA1 + \details Returns the content of the MSA1 Register. + \return MSA1 Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MSA1(void) +{ + uint32_t result; + +#ifdef __CK610 + __ASM volatile("cpseti 15"); + __ASM volatile("cprcr %0, cpcr31" : "=r"(result)); +#else + __ASM volatile("mfcr %0, cr<31, 15>" : "=r"(result)); +#endif + return (result); +} + +/** + \brief Set MSA1 + \details Writes the given value to the MSA1 Register. + \param [in] msa1 MSA1 Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MSA1(uint32_t msa1) +{ +#ifdef __CK610 + __ASM volatile("cpseti 15"); + __ASM volatile("cpwcr %0, cpcr31" : : "b"(msa1)); +#else + __ASM volatile("mtcr %0, cr<31, 15>" : : "r"(msa1)); +#endif +} + + +/** + \brief Enable interrupts and exceptions + \details Enables interrupts and exceptions by setting the IE-bit and EE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __enable_excp_irq(void) +{ + __ASM volatile("psrset ee, ie"); +} + + +/** + \brief Disable interrupts and exceptions + \details Disables interrupts and exceptions by clearing the IE-bit and EE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __disable_excp_irq(void) +{ + __ASM volatile("psrclr ee, ie"); +} + +/** + \brief Get GSR + \details Returns the content of the GSR Register. + \return GSR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_GSR(void) +{ + uint32_t result; + +#ifdef __CK610 + __ASM volatile("mfcr %0, cr12" : "=r"(result)); +#else + __ASM volatile("mfcr %0, cr<12, 0>" : "=r"(result)); +#endif + return (result); +} + +/** + \brief Get GCR + \details Returns the content of the GCR Register. + \return GCR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_GCR(void) +{ + uint32_t result; + +#ifdef __CK610 + __ASM volatile("mfcr %0, cr11" : "=r"(result)); +#else + __ASM volatile("mfcr %0, cr<11, 0>" : "=r"(result)); +#endif + return (result); +} + +/** + \brief Set GCR + \details Writes the given value to the GCR Register. + \param [in] gcr GCR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_GCR(uint32_t gcr) +{ +#ifdef __CK610 + __ASM volatile("mtcr %0, cr11" : : "r"(gcr)); +#else + __ASM volatile("mtcr %0, cr<11, 0>" : : "r"(gcr)); +#endif +} + +/** + \brief Get WSSR + \details Returns the content of the WSSR Register, must be accessed in TEE + \return WSSR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_WSSR(void) +{ + uint32_t result; + + __ASM volatile("mfcr %0, cr<0, 3>" : "=r"(result)); + return (result); +} + +/** + \brief Get WRCR + \details Returns the content of the WRCR Register, must be accessed in TEE + \return WRCR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_WRCR(void) +{ + uint32_t result; + + __ASM volatile("mfcr %0, cr<1, 3>" : "=r"(result)); + return (result); +} + +/** + \brief Set WRCR + \details Writes the given value to the WRCR Register, must be accessed in TEE + \param [in] wrcr WRCR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_WRCR(uint32_t wrcr) +{ + __ASM volatile("mtcr %0, cr<1, 3>" : : "r"(wrcr)); +} + +/** + \brief Get DCR + \details Returns the content of the DCR Register, must be accessed in TEE + \return DCR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_DCR(void) +{ + uint32_t result; + + __ASM volatile("mfcr %0, cr<8, 3>" : "=r"(result)); + return (result); +} + +/** + \brief Set DCR + \details Writes the given value to the DCR Register, must be accessed in TEE + \param [in] dcr DCR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_DCR(uint32_t dcr) +{ + __ASM volatile("mtcr %0, cr<8, 3>" : : "r"(dcr)); +} + +/** + \brief Get PCR + \details Returns the content of the PCR Register, must be accessed in TEE + \return PCR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_PCR(void) +{ + uint32_t result; + + __ASM volatile("mfcr %0, cr<9, 3>" : "=r"(result)); + return (result); +} + +/** + \brief Set PCR + \details Writes the given value to the PCR Register, must be accessed in TEE + \param [in] pcr PCR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_PCR(uint32_t pcr) +{ + __ASM volatile("mtcr %0, cr<9, 3>" : : "r"(pcr)); +} + +/** + \brief Get EBR + \details Returns the content of the EBR Register. + \return EBR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_EBR(void) +{ + uint32_t result; + + __ASM volatile("mfcr %0, cr<1, 1>" : "=r"(result)); + return (result); +} + +/** + \brief Set EBR + \details Writes the given value to the EBR Register. + \param [in] ebr EBR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_EBR(uint32_t ebr) +{ + __ASM volatile("mtcr %0, cr<1, 1>" : : "r"(ebr)); +} + +/*@} end of CSI_Core_RegAccFunctions */ + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CSI_Core_InstructionInterface CSI Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#define __CSI_GCC_OUT_REG(r) "=r" (r) +#define __CSI_GCC_USE_REG(r) "r" (r) + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__ALWAYS_STATIC_INLINE void __NOP(void) +{ + __ASM volatile("nop"); +} + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +__ALWAYS_STATIC_INLINE void __WFI(void) +{ + __ASM volatile("wait"); +} + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one interrupt occurs. + */ +__ALWAYS_STATIC_INLINE void __WAIT(void) +{ + __ASM volatile("wait"); +} + +/** + \brief Doze For Interrupt + \details Doze For Interrupt is a hint instruction that suspends execution until one interrupt occurs. + */ +__ALWAYS_STATIC_INLINE void __DOZE(void) +{ + __ASM volatile("doze"); +} + +/** + \brief Stop For Interrupt + \details Stop For Interrupt is a hint instruction that suspends execution until one interrupt occurs. + */ +__ALWAYS_STATIC_INLINE void __STOP(void) +{ + __ASM volatile("stop"); +} + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__ALWAYS_STATIC_INLINE void __ISB(void) +{ + __ASM volatile("sync"::: "memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__ALWAYS_STATIC_INLINE void __DSB(void) +{ + __ASM volatile("sync"::: "memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__ALWAYS_STATIC_INLINE void __DMB(void) +{ + __ASM volatile("sync"::: "memory"); +} + +/** + \brief Search from the highest bit that the very first bit which's value is 1. + \param [in] value Value to bit search. + \return if the highest bit' value is 1, return 0, and if lowest bit's value is 1, return 31, otherwise return 32. + */ +#if !defined(__CK610) || !(__CK80X == 1) +__ALWAYS_STATIC_INLINE uint32_t __FF0(uint32_t value) +{ + uint32_t ret; + + __ASM volatile("ff0 %0, %1" : "=r"(ret) : "r"(value)); + return ret; +} +#endif + +/** + \brief Search from the highest bit that the very first bit which's value is 0. + \param [in] value Value to bit search. + \return if the highest bit' value is 0, return 0, and if lowest bit's value is 0, return 31, otherwise return 32. + */ +#if !(__CK80X == 1) +__ALWAYS_STATIC_INLINE uint32_t __FF1(uint32_t value) +{ + uint32_t ret; +#if !defined (__CK610) + __ASM volatile("ff1 %0, %1" : "=r"(ret) : "r"(value)); +#else + ret = value; + __ASM volatile("ff1 %0" : "=r"(ret):); +#endif + return ret; +} +#endif + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__ALWAYS_STATIC_INLINE uint32_t __REV(uint32_t value) +{ + return __builtin_bswap32(value); +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__ALWAYS_STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; +#if (__CK80X >= 2) + __ASM volatile("revh %0, %1" : __CSI_GCC_OUT_REG(result) : __CSI_GCC_USE_REG(value)); +#else + result = ((value & 0xFF000000) >> 8) | ((value & 0x00FF0000) << 8) | + ((value & 0x0000FF00) >> 8) | ((value & 0x000000FF) << 8); +#endif + return (result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__ALWAYS_STATIC_INLINE int32_t __REVSH(int32_t value) +{ + return (short)(((value & 0xFF00) >> 8) | ((value & 0x00FF) << 8)); +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__ALWAYS_STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + */ +__ALWAYS_STATIC_INLINE void __BKPT(void) +{ + __ASM volatile("bkpt"); +} + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__ALWAYS_STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__CK80X >= 0x03U) + __ASM volatile("brev %0, %1" : "=r"(result) : "r"(value)); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + + for (value >>= 1U; value; value >>= 1U) { + result <<= 1U; + result |= value & 1U; + s--; + } + + result <<= s; /* shift when v's highest bits are zero */ +#endif + return (result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz +/** + \details This function saturates a signed value. + \param [in] x Value to be saturated + \param [in] y Bit position to saturate to [1..32] + \return Saturated value. + */ +__ALWAYS_STATIC_INLINE int32_t __SSAT(int32_t x, uint32_t y) +{ + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + + for (i = 0; i < (y - 1); i++) { + posMax = posMax * 2; + } + + if (x > 0) { + posMax = (posMax - 1); + + if (x > posMax) { + x = posMax; + } + +// x &= (posMax * 2 + 1); + } else { + negMin = -posMax; + + if (x < negMin) { + x = negMin; + } + +// x &= (posMax * 2 - 1); + } + + return (x); +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__ALWAYS_STATIC_INLINE uint32_t __USAT(uint32_t value, uint32_t sat) +{ + uint32_t result; + + if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) { + result = 0xFFFFFFFF >> (32 - sat); + } else { + result = value; + } + + return (result); +} + +/** + \brief Unsigned Saturate for internal use + \details Saturates an unsigned value, should not call directly. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__ALWAYS_STATIC_INLINE uint32_t __IUSAT(uint32_t value, uint32_t sat) +{ + uint32_t result; + + if (value & 0x80000000) { /* only overflow set bit-31 */ + result = 0; + } else if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) { + result = 0xFFFFFFFF >> (32 - sat); + } else { + result = value; + } + + return (result); +} + +/** + \brief Rotate Right with Extend + \details This function moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \note carry input will always 0. + \param [in] op1 Value to rotate + \return Rotated value + */ +__ALWAYS_STATIC_INLINE uint32_t __RRX(uint32_t op1) +{ +#if (__CK80X >= 2) + uint32_t res = 0; + __ASM volatile("bgeni t0, 31\n\t" + "lsri %0, 1\n\t" + "movt %1, t0\n\t" + "or %1, %1, %0\n\t" + : "=r"(op1), "=r"(res): "0"(op1), "1"(res): "t0"); + return res; +#else + uint32_t res = 0; + __ASM volatile("movi r7, 0\n\t" + "bseti r7, 31\n\t" + "lsri %0, 1\n\t" + "bf 1f\n\t" + "mov %1, r7\n\t" + "1:\n\t" + "or %1, %1, %0\n\t" + : "=r"(op1), "=r"(res): "0"(op1), "1"(res): "r7"); + return res; +#endif +} + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] addr Pointer to location + \return value of type uint8_t at (*ptr) + */ +__ALWAYS_STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; +//#warning "__LDRBT" + __ASM volatile("ldb %0, (%1, 0)" : "=r"(result) : "r"(addr)); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] addr Pointer to location + \return value of type uint16_t at (*ptr) + */ +__ALWAYS_STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +//#warning "__LDRHT" + __ASM volatile("ldh %0, (%1, 0)" : "=r"(result) : "r"(addr)); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] addr Pointer to location + \return value of type uint32_t at (*ptr) + */ +__ALWAYS_STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + +//#warning "__LDRT" + __ASM volatile("ldw %0, (%1, 0)" : "=r"(result) : "r"(addr)); + return (result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] addr Pointer to location + */ +__ALWAYS_STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ +//#warning "__STRBT" + __ASM volatile("stb %1, (%0, 0)" :: "r"(addr), "r"((uint32_t)value) : "memory"); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] addr Pointer to location + */ +__ALWAYS_STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ +//#warning "__STRHT" + __ASM volatile("sth %1, (%0, 0)" :: "r"(addr), "r"((uint32_t)value) : "memory"); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] addr Pointer to location + */ +__ALWAYS_STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ +//#warning "__STRT" + __ASM volatile("stw %1, (%0, 0)" :: "r"(addr), "r"(value) : "memory"); +} + +/*@}*/ /* end of group CSI_Core_InstructionInterface */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type, always 0. + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__ALWAYS_STATIC_INLINE uint32_t __get_FPUType(void) +{ +//FIXME: + return 0; +} + +/*@} end of CSI_Core_FpuFunctions */ + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CSI_SIMD_intrinsics CSI SIMD Intrinsics + Access to dedicated SIMD instructions \n + Single Instruction Multiple Data (SIMD) extensions are provided to simplify development of application software. SIMD extensions increase the processing capability without materially increasing the power consumption. The SIMD extensions are completely transparent to the operating system (OS), allowing existing OS ports to be used. + + @{ +*/ + +/** + \brief Halfword packing instruction. Combines bits[15:0] of val1 with bits[31:16] + of val2 levitated with the val3. + \details Combine a halfword from one register with a halfword from another register. + The second argument can be left-shifted before extraction of the halfword. + \param [in] val1 first 16-bit operands + \param [in] val2 second 16-bit operands + \param [in] val3 value for left-shifting val2. Value range [0..31]. + \return the combination of halfwords. + \remark + res[15:0] = val1[15:0] \n + res[31:16] = val2[31:16] << val3 + */ +__ALWAYS_STATIC_INLINE uint32_t __PKHBT(uint32_t val1, uint32_t val2, uint32_t val3) +{ + return ((((int32_t)(val1) << 0) & (int32_t)0x0000FFFF) | (((int32_t)(val2) << val3) & (int32_t)0xFFFF0000)); +} + +/** + \brief Halfword packing instruction. Combines bits[31:16] of val1 with bits[15:0] + of val2 right-shifted with the val3. + \details Combine a halfword from one register with a halfword from another register. + The second argument can be right-shifted before extraction of the halfword. + \param [in] val1 first 16-bit operands + \param [in] val2 second 16-bit operands + \param [in] val3 value for right-shifting val2. Value range [1..32]. + \return the combination of halfwords. + \remark + res[15:0] = val2[15:0] >> val3 \n + res[31:16] = val1[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __PKHTB(uint32_t val1, uint32_t val2, uint32_t val3) +{ + return ((((int32_t)(val1) << 0) & (int32_t)0xFFFF0000) | (((int32_t)(val2) >> val3) & (int32_t)0x0000FFFF)); +} + +/** + \brief Dual 16-bit signed saturate. + \details This function saturates a signed value. + \param [in] x two signed 16-bit values to be saturated. + \param [in] y bit position for saturation, an integral constant expression in the range 1 to 16. + \return the sum of the absolute differences of the following bytes, added to the accumulation value:\n + the signed saturation of the low halfword in val1, saturated to the bit position specified in + val2 and returned in the low halfword of the return value.\n + the signed saturation of the high halfword in val1, saturated to the bit position specified in + val2 and returned in the high halfword of the return value. + */ +__ALWAYS_STATIC_INLINE uint32_t __SSAT16(int32_t x, const uint32_t y) +{ + int32_t r = 0, s = 0; + + r = __SSAT((((int32_t)x << 16) >> 16), y) & (int32_t)0x0000FFFF; + s = __SSAT((((int32_t)x) >> 16), y) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturate. + \details This function enables you to saturate two signed 16-bit values to a selected unsigned range. + \param [in] x two signed 16-bit values to be saturated. + \param [in] y bit position for saturation, an integral constant expression in the range 1 to 16. + \return the saturation of the two signed 16-bit values, as non-negative values: + the saturation of the low halfword in val1, saturated to the bit position specified in + val2 and returned in the low halfword of the return value.\n + the saturation of the high halfword in val1, saturated to the bit position specified in + val2 and returned in the high halfword of the return value. + */ +__ALWAYS_STATIC_INLINE uint32_t __USAT16(uint32_t x, const uint32_t y) +{ + int32_t r = 0, s = 0; + + r = __IUSAT(((x << 16) >> 16), y) & 0x0000FFFF; + s = __IUSAT(((x) >> 16), y) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Quad 8-bit saturating addition. + \details This function enables you to perform four 8-bit integer additions, + saturating the results to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the saturated addition of the first byte of each operand in the first byte of the return value.\n + the saturated addition of the second byte of each operand in the second byte of the return value.\n + the saturated addition of the third byte of each operand in the third byte of the return value.\n + the saturated addition of the fourth byte of each operand in the fourth byte of the return value.\n + The returned results are saturated to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1. + \remark + res[7:0] = val1[7:0] + val2[7:0] \n + res[15:8] = val1[15:8] + val2[15:8] \n + res[23:16] = val1[23:16] + val2[23:16] \n + res[31:24] = val1[31:24] + val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __QADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = __SSAT(((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((int32_t)x) >> 24) + (((int32_t)y) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned saturating addition. + \details This function enables you to perform four unsigned 8-bit integer additions, + saturating the results to the 8-bit unsigned integer range 0 < x < 2^8 - 1. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the saturated addition of the first byte of each operand in the first byte of the return value.\n + the saturated addition of the second byte of each operand in the second byte of the return value.\n + the saturated addition of the third byte of each operand in the third byte of the return value.\n + the saturated addition of the fourth byte of each operand in the fourth byte of the return value.\n + The returned results are saturated to the 8-bit signed integer range 0 <= x <= 2^8 - 1. + \remark + res[7:0] = val1[7:0] + val2[7:0] \n + res[15:8] = val1[15:8] + val2[15:8] \n + res[23:16] = val1[23:16] + val2[23:16] \n + res[31:24] = val1[31:24] + val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = __IUSAT((((x << 24) >> 24) + ((y << 24) >> 24)), 8) & 0x000000FF; + s = __IUSAT((((x << 16) >> 24) + ((y << 16) >> 24)), 8) & 0x000000FF; + t = __IUSAT((((x << 8) >> 24) + ((y << 8) >> 24)), 8) & 0x000000FF; + u = __IUSAT((((x) >> 24) + ((y) >> 24)), 8) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Quad 8-bit signed addition. + \details This function performs four 8-bit signed integer additions. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the addition of the first bytes from each operand, in the first byte of the return value.\n + the addition of the second bytes of each operand, in the second byte of the return value.\n + the addition of the third bytes of each operand, in the third byte of the return value.\n + the addition of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + res[7:0] = val1[7:0] + val2[7:0] \n + res[15:8] = val1[15:8] + val2[15:8] \n + res[23:16] = val1[23:16] + val2[23:16] \n + res[31:24] = val1[31:24] + val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __SADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = ((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)) & (int32_t)0x000000FF; + s = ((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)) & (int32_t)0x000000FF; + t = ((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)) & (int32_t)0x000000FF; + u = ((((int32_t)x) >> 24) + (((int32_t)y) >> 24)) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned addition. + \details This function performs four unsigned 8-bit integer additions. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the addition of the first bytes from each operand, in the first byte of the return value.\n + the addition of the second bytes of each operand, in the second byte of the return value.\n + the addition of the third bytes of each operand, in the third byte of the return value.\n + the addition of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + res[7:0] = val1[7:0] + val2[7:0] \n + res[15:8] = val1[15:8] + val2[15:8] \n + res[23:16] = val1[23:16] + val2[23:16] \n + res[31:24] = val1[31:24] + val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __UADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = (((x << 24) >> 24) + ((y << 24) >> 24)) & 0x000000FF; + s = (((x << 16) >> 24) + ((y << 16) >> 24)) & 0x000000FF; + t = (((x << 8) >> 24) + ((y << 8) >> 24)) & 0x000000FF; + u = (((x) >> 24) + ((y) >> 24)) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Quad 8-bit saturating subtract. + \details This function enables you to perform four 8-bit integer subtractions, + saturating the results to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the subtraction of the first byte of each operand in the first byte of the return value.\n + the subtraction of the second byte of each operand in the second byte of the return value.\n + the subtraction of the third byte of each operand in the third byte of the return value.\n + the subtraction of the fourth byte of each operand in the fourth byte of the return value.\n + The returned results are saturated to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1. + \remark + res[7:0] = val1[7:0] - val2[7:0] \n + res[15:8] = val1[15:8] - val2[15:8] \n + res[23:16] = val1[23:16] - val2[23:16] \n + res[31:24] = val1[31:24] - val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __QSUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = __SSAT(((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((int32_t)x) >> 24) - (((int32_t)y) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned saturating subtraction. + \details This function enables you to perform four unsigned 8-bit integer subtractions, + saturating the results to the 8-bit unsigned integer range 0 < x < 2^8 - 1. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the subtraction of the first byte of each operand in the first byte of the return value.\n + the subtraction of the second byte of each operand in the second byte of the return value.\n + the subtraction of the third byte of each operand in the third byte of the return value.\n + the subtraction of the fourth byte of each operand in the fourth byte of the return value.\n + The returned results are saturated to the 8-bit unsigned integer range 0 <= x <= 2^8 - 1. + \remark + res[7:0] = val1[7:0] - val2[7:0] \n + res[15:8] = val1[15:8] - val2[15:8] \n + res[23:16] = val1[23:16] - val2[23:16] \n + res[31:24] = val1[31:24] - val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQSUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = __IUSAT((((x << 24) >> 24) - ((y << 24) >> 24)), 8) & 0x000000FF; + s = __IUSAT((((x << 16) >> 24) - ((y << 16) >> 24)), 8) & 0x000000FF; + t = __IUSAT((((x << 8) >> 24) - ((y << 8) >> 24)), 8) & 0x000000FF; + u = __IUSAT((((x) >> 24) - ((y) >> 24)), 8) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Quad 8-bit signed subtraction. + \details This function enables you to perform four 8-bit signed integer subtractions. + \param [in] x first four 8-bit operands of each subtraction. + \param [in] y second four 8-bit operands of each subtraction. + \return the subtraction of the first bytes from each operand, in the first byte of the return value.\n + the subtraction of the second bytes of each operand, in the second byte of the return value.\n + the subtraction of the third bytes of each operand, in the third byte of the return value.\n + the subtraction of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + res[7:0] = val1[7:0] - val2[7:0] \n + res[15:8] = val1[15:8] - val2[15:8] \n + res[23:16] = val1[23:16] - val2[23:16] \n + res[31:24] = val1[31:24] - val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __SSUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = ((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)) & (int32_t)0x000000FF; + s = ((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)) & (int32_t)0x000000FF; + t = ((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)) & (int32_t)0x000000FF; + u = ((((int32_t)x) >> 24) - (((int32_t)y) >> 24)) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned subtract. + \details This function enables you to perform four 8-bit unsigned integer subtractions. + \param [in] x first four 8-bit operands of each subtraction. + \param [in] y second four 8-bit operands of each subtraction. + \return the subtraction of the first bytes from each operand, in the first byte of the return value.\n + the subtraction of the second bytes of each operand, in the second byte of the return value.\n + the subtraction of the third bytes of each operand, in the third byte of the return value.\n + the subtraction of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + res[7:0] = val1[7:0] - val2[7:0] \n + res[15:8] = val1[15:8] - val2[15:8] \n + res[23:16] = val1[23:16] - val2[23:16] \n + res[31:24] = val1[31:24] - val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __USUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = (((x << 24) >> 24) - ((y << 24) >> 24)) & 0x000000FF; + s = (((x << 16) >> 24) - ((y << 16) >> 24)) & 0x000000FF; + t = (((x << 8) >> 24) - ((y << 8) >> 24)) & 0x000000FF; + u = (((x) >> 24) - ((y) >> 24)) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Unsigned sum of quad 8-bit unsigned absolute difference. + \details This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values + of the differences together, returning the result as a single unsigned integer. + \param [in] x first four 8-bit operands of each subtraction. + \param [in] y second four 8-bit operands of each subtraction. + \return the subtraction of the first bytes from each operand, in the first byte of the return value.\n + the subtraction of the second bytes of each operand, in the second byte of the return value.\n + the subtraction of the third bytes of each operand, in the third byte of the return value.\n + the subtraction of the fourth bytes of each operand, in the fourth byte of the return value.\n + The sum is returned as a single unsigned integer. + \remark + absdiff1 = val1[7:0] - val2[7:0] \n + absdiff2 = val1[15:8] - val2[15:8] \n + absdiff3 = val1[23:16] - val2[23:16] \n + absdiff4 = val1[31:24] - val2[31:24] \n + res[31:0] = absdiff1 + absdiff2 + absdiff3 + absdiff4 + */ +__ALWAYS_STATIC_INLINE uint32_t __USAD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = (((x << 24) >> 24) - ((y << 24) >> 24)) & 0x000000FF; + s = (((x << 16) >> 24) - ((y << 16) >> 24)) & 0x000000FF; + t = (((x << 8) >> 24) - ((y << 8) >> 24)) & 0x000000FF; + u = (((x) >> 24) - ((y) >> 24)) & 0x000000FF; + + return (u + t + s + r); +} + +/** + \brief Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate. + \details This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values + of the differences to a 32-bit accumulate operand. + \param [in] x first four 8-bit operands of each subtraction. + \param [in] y second four 8-bit operands of each subtraction. + \param [in] sum accumulation value. + \return the sum of the absolute differences of the following bytes, added to the accumulation value: + the subtraction of the first bytes from each operand, in the first byte of the return value.\n + the subtraction of the second bytes of each operand, in the second byte of the return value.\n + the subtraction of the third bytes of each operand, in the third byte of the return value.\n + the subtraction of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + absdiff1 = val1[7:0] - val2[7:0] \n + absdiff2 = val1[15:8] - val2[15:8] \n + absdiff3 = val1[23:16] - val2[23:16] \n + absdiff4 = val1[31:24] - val2[31:24] \n + sum = absdiff1 + absdiff2 + absdiff3 + absdiff4 \n + res[31:0] = sum[31:0] + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __USADA8(uint32_t x, uint32_t y, uint32_t sum) +{ + int32_t r, s, t, u; + +#ifdef __cplusplus + r = (abs((long long)((x << 24) >> 24) - ((y << 24) >> 24))) & 0x000000FF; + s = (abs((long long)((x << 16) >> 24) - ((y << 16) >> 24))) & 0x000000FF; + t = (abs((long long)((x << 8) >> 24) - ((y << 8) >> 24))) & 0x000000FF; + u = (abs((long long)((x) >> 24) - ((y) >> 24))) & 0x000000FF; +#else + r = (abs(((x << 24) >> 24) - ((y << 24) >> 24))) & 0x000000FF; + s = (abs(((x << 16) >> 24) - ((y << 16) >> 24))) & 0x000000FF; + t = (abs(((x << 8) >> 24) - ((y << 8) >> 24))) & 0x000000FF; + u = (abs(((x) >> 24) - ((y) >> 24))) & 0x000000FF; +#endif + return (u + t + s + r + sum); +} + +/** + \brief Dual 16-bit saturating addition. + \details This function enables you to perform two 16-bit integer arithmetic additions in parallel, + saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the saturated addition of the low halfwords, in the low halfword of the return value.\n + the saturated addition of the high halfwords, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] + val2[15:0] \n + res[31:16] = val1[31:16] + val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __QADD16(uint32_t x, uint32_t y) +{ + int32_t r = 0, s = 0; + + r = __SSAT(((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((int32_t)x) >> 16) + (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturating addition. + \details This function enables you to perform two unsigned 16-bit integer additions, saturating + the results to the 16-bit unsigned integer range 0 < x < 2^16 - 1. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the saturated addition of the low halfwords, in the low halfword of the return value.\n + the saturated addition of the high halfwords, in the high halfword of the return value.\n + The results are saturated to the 16-bit unsigned integer range 0 < x < 2^16 - 1. + \remark + res[15:0] = val1[15:0] + val2[15:0] \n + res[31:16] = val1[31:16] + val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQADD16(uint32_t x, uint32_t y) +{ + int32_t r = 0, s = 0; + + r = __IUSAT((((x << 16) >> 16) + ((y << 16) >> 16)), 16) & 0x0000FFFF; + s = __IUSAT((((x) >> 16) + ((y) >> 16)), 16) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed addition. + \details This function enables you to perform two 16-bit signed integer additions. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the addition of the low halfwords in the low halfword of the return value.\n + the addition of the high halfwords in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] + val2[15:0] \n + res[31:16] = val1[31:16] + val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __SADD16(uint32_t x, uint32_t y) +{ + int32_t r = 0, s = 0; + + r = ((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF; + s = ((((int32_t)x) >> 16) + (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned addition + \details This function enables you to perform two 16-bit unsigned integer additions. + \param [in] x first two 16-bit summands for each addition. + \param [in] y second two 16-bit summands for each addition. + \return the addition of the low halfwords in the low halfword of the return value.\n + the addition of the high halfwords in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] + val2[15:0] \n + res[31:16] = val1[31:16] + val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __UADD16(uint32_t x, uint32_t y) +{ + int32_t r = 0, s = 0; + + r = (((x << 16) >> 16) + ((y << 16) >> 16)) & 0x0000FFFF; + s = (((x) >> 16) + ((y) >> 16)) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + + +/** + \brief Dual 16-bit signed addition with halved results. + \details This function enables you to perform two signed 16-bit integer additions, halving the results. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the halved addition of the low halfwords, in the low halfword of the return value.\n + the halved addition of the high halfwords, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] + val2[15:0]) >> 1 \n + res[31:16] = (val1[31:16] + val2[31:16]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHADD16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((int32_t)x) >> 16) + (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned addition with halved results. + \details This function enables you to perform two unsigned 16-bit integer additions, halving the results. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the halved addition of the low halfwords, in the low halfword of the return value.\n + the halved addition of the high halfwords, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] + val2[15:0]) >> 1 \n + res[31:16] = (val1[31:16] + val2[31:16]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHADD16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((x << 16) >> 16) + ((y << 16) >> 16)) >> 1) & 0x0000FFFF; + s = ((((x) >> 16) + ((y) >> 16)) >> 1) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Quad 8-bit signed addition with halved results. + \details This function enables you to perform four signed 8-bit integer additions, halving the results. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the halved addition of the first bytes from each operand, in the first byte of the return value.\n + the halved addition of the second bytes from each operand, in the second byte of the return value.\n + the halved addition of the third bytes from each operand, in the third byte of the return value.\n + the halved addition of the fourth bytes from each operand, in the fourth byte of the return value. + \remark + res[7:0] = (val1[7:0] + val2[7:0] ) >> 1 \n + res[15:8] = (val1[15:8] + val2[15:8] ) >> 1 \n + res[23:16] = (val1[23:16] + val2[23:16]) >> 1 \n + res[31:24] = (val1[31:24] + val2[31:24]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = (((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)) >> 1) & (int32_t)0x000000FF; + s = (((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)) >> 1) & (int32_t)0x000000FF; + t = (((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)) >> 1) & (int32_t)0x000000FF; + u = (((((int32_t)x) >> 24) + (((int32_t)y) >> 24)) >> 1) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned addition with halved results. + \details This function enables you to perform four unsigned 8-bit integer additions, halving the results. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the halved addition of the first bytes from each operand, in the first byte of the return value.\n + the halved addition of the second bytes from each operand, in the second byte of the return value.\n + the halved addition of the third bytes from each operand, in the third byte of the return value.\n + the halved addition of the fourth bytes from each operand, in the fourth byte of the return value. + \remark + res[7:0] = (val1[7:0] + val2[7:0] ) >> 1 \n + res[15:8] = (val1[15:8] + val2[15:8] ) >> 1 \n + res[23:16] = (val1[23:16] + val2[23:16]) >> 1 \n + res[31:24] = (val1[31:24] + val2[31:24]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = ((((x << 24) >> 24) + ((y << 24) >> 24)) >> 1) & 0x000000FF; + s = ((((x << 16) >> 24) + ((y << 16) >> 24)) >> 1) & 0x000000FF; + t = ((((x << 8) >> 24) + ((y << 8) >> 24)) >> 1) & 0x000000FF; + u = ((((x) >> 24) + ((y) >> 24)) >> 1) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Dual 16-bit saturating subtract. + \details This function enables you to perform two 16-bit integer subtractions in parallel, + saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the saturated subtraction of the low halfwords, in the low halfword of the return value.\n + the saturated subtraction of the high halfwords, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] - val2[15:0] \n + res[31:16] = val1[31:16] - val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __QSUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __SSAT(((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((int32_t)x) >> 16) - (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturating subtraction. + \details This function enables you to perform two unsigned 16-bit integer subtractions, + saturating the results to the 16-bit unsigned integer range 0 < x < 2^16 - 1. + \param [in] x first two 16-bit operands for each subtraction. + \param [in] y second two 16-bit operands for each subtraction. + \return the saturated subtraction of the low halfwords, in the low halfword of the return value.\n + the saturated subtraction of the high halfwords, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] - val2[15:0] \n + res[31:16] = val1[31:16] - val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQSUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __IUSAT((((x << 16) >> 16) - ((y << 16) >> 16)), 16) & 0x0000FFFF; + s = __IUSAT((((x) >> 16) - ((y) >> 16)), 16) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed subtraction. + \details This function enables you to perform two 16-bit signed integer subtractions. + \param [in] x first two 16-bit operands of each subtraction. + \param [in] y second two 16-bit operands of each subtraction. + \return the subtraction of the low halfword in the second operand from the low + halfword in the first operand, in the low halfword of the return value. \n + the subtraction of the high halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] - val2[15:0] \n + res[31:16] = val1[31:16] - val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __SSUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF; + s = ((((int32_t)x) >> 16) - (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned subtract. + \details This function enables you to perform two 16-bit unsigned integer subtractions. + \param [in] x first two 16-bit operands of each subtraction. + \param [in] y second two 16-bit operands of each subtraction. + \return the subtraction of the low halfword in the second operand from the low + halfword in the first operand, in the low halfword of the return value. \n + the subtraction of the high halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] - val2[15:0] \n + res[31:16] = val1[31:16] - val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __USUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((x << 16) >> 16) - ((y << 16) >> 16)) & 0x0000FFFF; + s = (((x) >> 16) - ((y) >> 16)) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed subtraction with halved results. + \details This function enables you to perform two signed 16-bit integer subtractions, halving the results. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the halved subtraction of the low halfwords, in the low halfword of the return value.\n + the halved subtraction of the high halfwords, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] - val2[15:0]) >> 1 \n + res[31:16] = (val1[31:16] - val2[31:16]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHSUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((int32_t)x) >> 16) - (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned subtraction with halved results. + \details This function enables you to perform two unsigned 16-bit integer subtractions, halving the results. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the halved subtraction of the low halfwords, in the low halfword of the return value.\n + the halved subtraction of the high halfwords, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] - val2[15:0]) >> 1 \n + res[31:16] = (val1[31:16] - val2[31:16]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHSUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((x << 16) >> 16) - ((y << 16) >> 16)) >> 1) & 0x0000FFFF; + s = ((((x) >> 16) - ((y) >> 16)) >> 1) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Quad 8-bit signed addition with halved results. + \details This function enables you to perform four signed 8-bit integer subtractions, halving the results. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the halved subtraction of the first bytes from each operand, in the first byte of the return value.\n + the halved subtraction of the second bytes from each operand, in the second byte of the return value.\n + the halved subtraction of the third bytes from each operand, in the third byte of the return value.\n + the halved subtraction of the fourth bytes from each operand, in the fourth byte of the return value. + \remark + res[7:0] = (val1[7:0] - val2[7:0] ) >> 1 \n + res[15:8] = (val1[15:8] - val2[15:8] ) >> 1 \n + res[23:16] = (val1[23:16] - val2[23:16]) >> 1 \n + res[31:24] = (val1[31:24] - val2[31:24]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHSUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = (((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)) >> 1) & (int32_t)0x000000FF; + s = (((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)) >> 1) & (int32_t)0x000000FF; + t = (((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)) >> 1) & (int32_t)0x000000FF; + u = (((((int32_t)x) >> 24) - (((int32_t)y) >> 24)) >> 1) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned subtraction with halved results. + \details This function enables you to perform four unsigned 8-bit integer subtractions, halving the results. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the halved subtraction of the first bytes from each operand, in the first byte of the return value.\n + the halved subtraction of the second bytes from each operand, in the second byte of the return value.\n + the halved subtraction of the third bytes from each operand, in the third byte of the return value.\n + the halved subtraction of the fourth bytes from each operand, in the fourth byte of the return value. + \remark + res[7:0] = (val1[7:0] - val2[7:0] ) >> 1 \n + res[15:8] = (val1[15:8] - val2[15:8] ) >> 1 \n + res[23:16] = (val1[23:16] - val2[23:16]) >> 1 \n + res[31:24] = (val1[31:24] - val2[31:24]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHSUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = ((((x << 24) >> 24) - ((y << 24) >> 24)) >> 1) & 0x000000FF; + s = ((((x << 16) >> 24) - ((y << 16) >> 24)) >> 1) & 0x000000FF; + t = ((((x << 8) >> 24) - ((y << 8) >> 24)) >> 1) & 0x000000FF; + u = ((((x) >> 24) - ((y) >> 24)) >> 1) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Dual 16-bit add and subtract with exchange. + \details This function enables you to exchange the halfwords of the one operand, + then add the high halfwords and subtract the low halfwords, + saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \param [in] x first operand for the subtraction in the low halfword, + and the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, + and the second operand for the addition in the low halfword. + \return the saturated subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the saturated addition of the high halfword in the first operand and the + low halfword in the second operand, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] - val2[31:16] \n + res[31:16] = val1[31:16] + val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __QASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __SSAT(((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturating addition and subtraction with exchange. + \details This function enables you to exchange the halfwords of the second operand and + perform one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, + saturating the results to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1. + \param [in] x first operand for the subtraction in the low halfword, + and the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, + and the second operand for the addition in the low halfword. + \return the saturated subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the saturated addition of the high halfword in the first operand and the + low halfword in the second operand, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1. + \remark + res[15:0] = val1[15:0] - val2[31:16] \n + res[31:16] = val1[31:16] + val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __IUSAT((((x << 16) >> 16) - ((y) >> 16)), 16) & 0x0000FFFF; + s = __IUSAT((((x) >> 16) + ((y << 16) >> 16)), 16) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit addition and subtraction with exchange. + \details It enables you to exchange the halfwords of the second operand, add the high halfwords + and subtract the low halfwords. + \param [in] x first operand for the subtraction in the low halfword, + and the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, + and the second operand for the addition in the low halfword. + \return the subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the addition of the high halfword in the first operand and the + low halfword in the second operand, in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] - val2[31:16] \n + res[31:16] = val1[31:16] + val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF; + s = ((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned addition and subtraction with exchange. + \details This function enables you to exchange the two halfwords of the second operand, + add the high halfwords and subtract the low halfwords. + \param [in] x first operand for the subtraction in the low halfword, + and the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, + and the second operand for the addition in the low halfword. + \return the subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the addition of the high halfword in the first operand and the + low halfword in the second operand, in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] - val2[31:16] \n + res[31:16] = val1[31:16] + val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __UASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((x << 16) >> 16) - ((y) >> 16)) & 0x0000FFFF; + s = (((x) >> 16) + ((y << 16) >> 16)) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed addition and subtraction with halved results. + \details This function enables you to exchange the two halfwords of one operand, perform one + signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results. + \param [in] x first 16-bit operands. + \param [in] y second 16-bit operands. + \return the halved subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the halved addition of the low halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] - val2[31:16]) >> 1 \n + res[31:16] = (val1[31:16] + val2[15:0]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned addition and subtraction with halved results and exchange. + \details This function enables you to exchange the halfwords of the second operand, + add the high halfwords and subtract the low halfwords, halving the results. + \param [in] x first operand for the subtraction in the low halfword, and + the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, and + the second operand for the addition in the low halfword. + \return the halved subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the halved addition of the low halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] - val2[31:16]) >> 1 \n + res[31:16] = (val1[31:16] + val2[15:0]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((x << 16) >> 16) - ((y) >> 16)) >> 1) & 0x0000FFFF; + s = ((((x) >> 16) + ((y << 16) >> 16)) >> 1) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit subtract and add with exchange. + \details This function enables you to exchange the halfwords of one operand, + then subtract the high halfwords and add the low halfwords, + saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \param [in] x first operand for the addition in the low halfword, + and the first operand for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, + and the second operand for the subtraction in the low halfword. + \return the saturated addition of the low halfword of the first operand and the high + halfword of the second operand, in the low halfword of the return value.\n + the saturated subtraction of the low halfword of the second operand from the + high halfword of the first operand, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] + val2[31:16] \n + res[31:16] = val1[31:16] - val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __QSAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __SSAT(((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturating subtraction and addition with exchange. + \details This function enables you to exchange the halfwords of the second operand and perform + one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating + the results to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1. + \param [in] x first operand for the addition in the low halfword, + and the first operand for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, + and the second operand for the subtraction in the low halfword. + \return the saturated addition of the low halfword of the first operand and the high + halfword of the second operand, in the low halfword of the return value.\n + the saturated subtraction of the low halfword of the second operand from the + high halfword of the first operand, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1. + \remark + res[15:0] = val1[15:0] + val2[31:16] \n + res[31:16] = val1[31:16] - val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQSAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __IUSAT((((x << 16) >> 16) + ((y) >> 16)), 16) & 0x0000FFFF; + s = __IUSAT((((x) >> 16) - ((y << 16) >> 16)), 16) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit unsigned subtract and add with exchange. + \details This function enables you to exchange the halfwords of the second operand, + subtract the high halfwords and add the low halfwords. + \param [in] x first operand for the addition in the low halfword, + and the first operand for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, + and the second operand for the subtraction in the low halfword. + \return the addition of the low halfword of the first operand and the high + halfword of the second operand, in the low halfword of the return value.\n + the subtraction of the low halfword of the second operand from the + high halfword of the first operand, in the high halfword of the return value.\n + \remark + res[15:0] = val1[15:0] + val2[31:16] \n + res[31:16] = val1[31:16] - val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __USAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((x << 16) >> 16) + ((y) >> 16)) & 0x0000FFFF; + s = (((x) >> 16) - ((y << 16) >> 16)) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed subtraction and addition with exchange. + \details This function enables you to exchange the two halfwords of one operand and perform one + 16-bit integer subtraction and one 16-bit addition. + \param [in] x first operand for the addition in the low halfword, and the first operand + for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, and the second + operand for the subtraction in the low halfword. + \return the addition of the low halfword of the first operand and the high + halfword of the second operand, in the low halfword of the return value.\n + the subtraction of the low halfword of the second operand from the + high halfword of the first operand, in the high halfword of the return value.\n + \remark + res[15:0] = val1[15:0] + val2[31:16] \n + res[31:16] = val1[31:16] - val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SSAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF; + s = ((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + + +/** + \brief Dual 16-bit signed subtraction and addition with halved results. + \details This function enables you to exchange the two halfwords of one operand, perform one signed + 16-bit integer subtraction and one signed 16-bit addition, and halve the results. + \param [in] x first 16-bit operands. + \param [in] y second 16-bit operands. + \return the halved addition of the low halfword in the first operand and the + high halfword in the second operand, in the low halfword of the return value.\n + the halved subtraction of the low halfword in the second operand from the + high halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] + val2[31:16]) >> 1 \n + res[31:16] = (val1[31:16] - val2[15:0]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHSAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned subtraction and addition with halved results and exchange. + \details This function enables you to exchange the halfwords of the second operand, + subtract the high halfwords and add the low halfwords, halving the results. + \param [in] x first operand for the addition in the low halfword, and + the first operand for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, and + the second operand for the subtraction in the low halfword. + \return the halved addition of the low halfword in the first operand and the + high halfword in the second operand, in the low halfword of the return value.\n + the halved subtraction of the low halfword in the second operand from the + high halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] + val2[31:16]) >> 1 \n + res[31:16] = (val1[31:16] - val2[15:0]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHSAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((x << 16) >> 16) + ((y) >> 16)) >> 1) & 0x0000FFFF; + s = ((((x) >> 16) - ((y << 16) >> 16)) >> 1) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed multiply with exchange returning difference. + \details This function enables you to perform two 16-bit signed multiplications, subtracting + one of the products from the other. The halfwords of the second operand are exchanged + before performing the arithmetic. This produces top * bottom and bottom * top multiplication. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \return the difference of the products of the two 16-bit signed multiplications. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[31:0] = p1 - p2 + */ +__ALWAYS_STATIC_INLINE uint32_t __SMUSDX(uint32_t x, uint32_t y) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)))); +} + +/** + \brief Sum of dual 16-bit signed multiply with exchange. + \details This function enables you to perform two 16-bit signed multiplications with exchanged + halfwords of the second operand, adding the products together. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \return the sum of the products of the two 16-bit signed multiplications with exchanged halfwords of the second operand. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[31:0] = p1 + p2 + */ +__ALWAYS_STATIC_INLINE uint32_t __SMUADX(uint32_t x, uint32_t y) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)))); +} + + +/** + \brief Saturating add. + \details This function enables you to obtain the saturating add of two integers. + \param [in] x first summand of the saturating add operation. + \param [in] y second summand of the saturating add operation. + \return the saturating addition of val1 and val2. + \remark + res[31:0] = SAT(val1 + SAT(val2)) + */ +__ALWAYS_STATIC_INLINE int32_t __QADD(int32_t x, int32_t y) +{ + int32_t result; + + if (y >= 0) { + if (x + y >= x) { + result = x + y; + } else { + result = 0x7FFFFFFF; + } + } else { + if (x + y < x) { + result = x + y; + } else { + result = 0x80000000; + } + } + + return result; +} + +/** + \brief Saturating subtract. + \details This function enables you to obtain the saturating add of two integers. + \param [in] x first summand of the saturating add operation. + \param [in] y second summand of the saturating add operation. + \return the saturating addition of val1 and val2. + \remark + res[31:0] = SAT(val1 - SAT(val2)) + */ +__ALWAYS_STATIC_INLINE int32_t __QSUB(int32_t x, int32_t y) +{ + int64_t tmp; + int32_t result; + + tmp = (int64_t)x - (int64_t)y; + + if (tmp > 0x7fffffff) { + tmp = 0x7fffffff; + } else if (tmp < (-2147483647 - 1)) { + tmp = -2147483647 - 1; + } + + result = tmp; + return result; +} + +/** + \brief Dual 16-bit signed multiply with single 32-bit accumulator. + \details This function enables you to perform two signed 16-bit multiplications, + adding both results to a 32-bit accumulate operand. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the product of each multiplication added to the accumulate value, as a 32-bit integer. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[31:0] = p1 + p2 + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SMLAD(uint32_t x, uint32_t y, uint32_t sum) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) + + (((int32_t)sum)))); +} + +/** + \brief Pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator. + \details This function enables you to perform two signed 16-bit multiplications with exchanged + halfwords of the second operand, adding both results to a 32-bit accumulate operand. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the product of each multiplication with exchanged halfwords of the second + operand added to the accumulate value, as a 32-bit integer. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[31:0] = p1 + p2 + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SMLADX(uint32_t x, uint32_t y, uint32_t sum) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) + + (((int32_t)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with exchange subtract with 32-bit accumulate. + \details This function enables you to perform two 16-bit signed multiplications, take the + difference of the products, subtracting the high halfword product from the low + halfword product, and add the difference to a 32-bit accumulate operand. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the difference of the product of each multiplication, added to the accumulate value. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[31:0] = p1 - p2 + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SMLSD(uint32_t x, uint32_t y, uint32_t sum) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) + + (((int32_t)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with exchange subtract with 32-bit accumulate. + \details This function enables you to exchange the halfwords in the second operand, then perform two 16-bit + signed multiplications. The difference of the products is added to a 32-bit accumulate operand. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the difference of the product of each multiplication, added to the accumulate value. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[31:0] = p1 - p2 + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SMLSDX(uint32_t x, uint32_t y, uint32_t sum) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) + + (((int32_t)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with single 64-bit accumulator. + \details This function enables you to perform two signed 16-bit multiplications, adding both results + to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. + This overflow is not detected if it occurs. Instead, the result wraps around modulo2^64. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the product of each multiplication added to the accumulate value. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + sum = p1 + p2 + val3[63:32][31:0] \n + res[63:32] = sum[63:32] \n + res[31:0] = sum[31:0] + */ +__ALWAYS_STATIC_INLINE uint64_t __SMLALD(uint32_t x, uint32_t y, uint64_t sum) +{ + return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) + + (((uint64_t)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with exchange with single 64-bit accumulator. + \details This function enables you to exchange the halfwords of the second operand, and perform two + signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow + is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. + Instead, the result wraps around modulo2^64. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the product of each multiplication added to the accumulate value. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + sum = p1 + p2 + val3[63:32][31:0] \n + res[63:32] = sum[63:32] \n + res[31:0] = sum[31:0] + */ +__ALWAYS_STATIC_INLINE uint64_t __SMLALDX(uint32_t x, uint32_t y, uint64_t sum) +{ + return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) + + (((uint64_t)sum)))); +} + +/** + \brief dual 16-bit signed multiply subtract with 64-bit accumulate. + \details This function It enables you to perform two 16-bit signed multiplications, take the difference + of the products, subtracting the high halfword product from the low halfword product, and add the + difference to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the + subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not + detected. Instead, the result wraps round to modulo2^64. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the difference of the product of each multiplication, added to the accumulate value. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[63:32][31:0] = p1 - p2 + val3[63:32][31:0] + */ +__ALWAYS_STATIC_INLINE uint64_t __SMLSLD(uint32_t x, uint32_t y, uint64_t sum) +{ + return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) + + (((uint64_t)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with exchange subtract with 64-bit accumulate. + \details This function enables you to exchange the halfwords of the second operand, perform two 16-bit multiplications, + adding the difference of the products to a 64-bit accumulate operand. Overflow cannot occur during the + multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow + is not detected. Instead, the result wraps round to modulo2^64. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the difference of the product of each multiplication, added to the accumulate value. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[63:32][31:0] = p1 - p2 + val3[63:32][31:0] + */ +__ALWAYS_STATIC_INLINE uint64_t __SMLSLDX(uint32_t x, uint32_t y, uint64_t sum) +{ + return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) + + (((uint64_t)sum)))); +} + +/** + \brief 32-bit signed multiply with 32-bit truncated accumulator. + \details This function enables you to perform a signed 32-bit multiplications, adding the most + significant 32 bits of the 64-bit result to a 32-bit accumulate operand. + \param [in] x first operand for multiplication. + \param [in] y second operand for multiplication. + \param [in] sum accumulate value. + \return the product of multiplication (most significant 32 bits) is added to the accumulate value, as a 32-bit integer. + \remark + p = val1 * val2 \n + res[31:0] = p[63:32] + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SMMLA(int32_t x, int32_t y, int32_t sum) +{ + return (uint32_t)((int32_t)((int64_t)((int64_t)x * (int64_t)y) >> 32) + sum); +} + +/** + \brief Sum of dual 16-bit signed multiply. + \details This function enables you to perform two 16-bit signed multiplications, adding the products together. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \return the sum of the products of the two 16-bit signed multiplications. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[31:0] = p1 + p2 + */ +__ALWAYS_STATIC_INLINE uint32_t __SMUAD(uint32_t x, uint32_t y) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)))); +} + +/** + \brief Dual 16-bit signed multiply returning difference. + \details This function enables you to perform two 16-bit signed multiplications, taking the difference + of the products by subtracting the high halfword product from the low halfword product. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \return the difference of the products of the two 16-bit signed multiplications. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[31:0] = p1 - p2 + */ +__ALWAYS_STATIC_INLINE uint32_t __SMUSD(uint32_t x, uint32_t y) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)))); +} + +/** + \brief Dual extracted 8-bit to 16-bit signed addition. + \details This function enables you to extract two 8-bit values from the second operand (at bit positions + [7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the first operand. + \param [in] x values added to the sign-extended to 16-bit values. + \param [in] y two 8-bit values to be extracted and sign-extended. + \return the addition of val1 and val2, where the 8-bit values in val2[7:0] and + val2[23:16] have been extracted and sign-extended prior to the addition. + \remark + res[15:0] = val1[15:0] + SignExtended(val2[7:0]) \n + res[31:16] = val1[31:16] + SignExtended(val2[23:16]) + */ +__ALWAYS_STATIC_INLINE uint32_t __SXTAB16(uint32_t x, uint32_t y) +{ + return ((uint32_t)((((((int32_t)y << 24) >> 24) + (((int32_t)x << 16) >> 16)) & (int32_t)0x0000FFFF) | + (((((int32_t)y << 8) >> 8) + (((int32_t)x >> 16) << 16)) & (int32_t)0xFFFF0000))); +} + +/** + \brief Extracted 16-bit to 32-bit unsigned addition. + \details This function enables you to extract two 8-bit values from one operand, zero-extend + them to 16 bits each, and add the results to two 16-bit values from another operand. + \param [in] x values added to the zero-extended to 16-bit values. + \param [in] y two 8-bit values to be extracted and zero-extended. + \return the addition of val1 and val2, where the 8-bit values in val2[7:0] and + val2[23:16] have been extracted and zero-extended prior to the addition. + \remark + res[15:0] = ZeroExt(val2[7:0] to 16 bits) + val1[15:0] \n + res[31:16] = ZeroExt(val2[31:16] to 16 bits) + val1[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __UXTAB16(uint32_t x, uint32_t y) +{ + return ((uint32_t)(((((y << 24) >> 24) + ((x << 16) >> 16)) & 0x0000FFFF) | + ((((y << 8) >> 8) + ((x >> 16) << 16)) & 0xFFFF0000))); +} + +/** + \brief Dual extract 8-bits and sign extend each to 16-bits. + \details This function enables you to extract two 8-bit values from an operand and sign-extend them to 16 bits each. + \param [in] x two 8-bit values in val[7:0] and val[23:16] to be sign-extended. + \return the 8-bit values sign-extended to 16-bit values.\n + sign-extended value of val[7:0] in the low halfword of the return value.\n + sign-extended value of val[23:16] in the high halfword of the return value. + \remark + res[15:0] = SignExtended(val[7:0]) \n + res[31:16] = SignExtended(val[23:16]) + */ +__ALWAYS_STATIC_INLINE uint32_t __SXTB16(uint32_t x) +{ + return ((uint32_t)(((((int32_t)x << 24) >> 24) & (int32_t)0x0000FFFF) | + ((((int32_t)x << 8) >> 8) & (int32_t)0xFFFF0000))); +} + +/** + \brief Dual extract 8-bits and zero-extend to 16-bits. + \details This function enables you to extract two 8-bit values from an operand and zero-extend them to 16 bits each. + \param [in] x two 8-bit values in val[7:0] and val[23:16] to be zero-extended. + \return the 8-bit values sign-extended to 16-bit values.\n + sign-extended value of val[7:0] in the low halfword of the return value.\n + sign-extended value of val[23:16] in the high halfword of the return value. + \remark + res[15:0] = SignExtended(val[7:0]) \n + res[31:16] = SignExtended(val[23:16]) + */ +__ALWAYS_STATIC_INLINE uint32_t __UXTB16(uint32_t x) +{ + return ((uint32_t)((((x << 24) >> 24) & 0x0000FFFF) | + (((x << 8) >> 8) & 0xFFFF0000))); +} + +#endif /* _CSI_GCC_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/csi_rv32_gcc.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/csi_rv32_gcc.h new file mode 100644 index 00000000..4c7d540c --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/csi_rv32_gcc.h @@ -0,0 +1,3374 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +/****************************************************************************** + * @file csi_rv32_gcc.h + * @brief CSI Header File for GCC. + * @version V1.0 + * @date 01. Sep 2018 + ******************************************************************************/ + +#ifndef _CSI_RV32_GCC_H_ +#define _CSI_RV32_GCC_H_ + +#include + +#if CONFIG_CPU_XUANTIE_E906 || CONFIG_CPU_XUANTIE_E906F || CONFIG_CPU_XUANTIE_E906FD || CONFIG_CPU_XUANTIE_E906P || CONFIG_CPU_XUANTIE_E906FP || CONFIG_CPU_XUANTIE_E906FDP \ + || CONFIG_CPU_XUANTIE_E907 || CONFIG_CPU_XUANTIE_E907F || CONFIG_CPU_XUANTIE_E907FD || CONFIG_CPU_XUANTIE_E907P || CONFIG_CPU_XUANTIE_E907FP || CONFIG_CPU_XUANTIE_E907FDP \ + || CONFIG_CPU_XUANTIE_E902 || CONFIG_CPU_XUANTIE_E902M || CONFIG_CPU_XUANTIE_E902T || CONFIG_CPU_XUANTIE_E902MT \ + || CONFIG_CPU_XUANTIE_E901PLUS_CP || CONFIG_CPU_XUANTIE_E901PLUS_B_CP || CONFIG_CPU_XUANTIE_E901PLUS_M_CP || CONFIG_CPU_XUANTIE_E901PLUS_BM_CP \ + || CONFIG_CPU_XUANTIE_E901_CP || CONFIG_CPU_XUANTIE_E901_B_CP || CONFIG_CPU_XUANTIE_E901_ZM_CP || CONFIG_CPU_XUANTIE_E901_BZM_CP +#define CONFIG_CPU_XUANTIE_E9XX 1 +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_RegAccFunctions CSI Core Register Access Functions + @{ + */ +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by setting the IE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile("csrs mstatus, 8"); +} + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by clearing the IE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile("csrc mstatus, 8"); +} + +/** + \brief Get MXSTATUS + \details Returns the content of the MXSTATUS Register. + \return MXSTATUS Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MXSTATUS(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mxstatus" : "=r"(result)); + return (result); +} + +/** + \brief Set MXSTATUS + \details Writes the given value to the MXSTATUS Register. + \param [in] MXSTATUS Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MXSTATUS(unsigned long mxstatus) +{ + __ASM volatile("csrw mxstatus, %0" : : "r"(mxstatus)); +} + +/** + \brief Get MEXSTATUS + \details Returns the content of the MEXSTATUS Register. + \return MEXSTATUS Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MEXSTATUS(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mexstatus" : "=r"(result)); + return (result); +} + +/** + \brief Set MEXSTATUS + \details Writes the given value to the MSTATUS Register. + \param [in] MEXSTATUS Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MEXSTATUS(unsigned long mexstatus) +{ + __ASM volatile("csrw mexstatus, %0" : : "r"(mexstatus)); +} + + +/** + \brief Get MRADDR + \details Returns the content of the MRADDR Register. + \return MRADDR Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MRADDR(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mraddr" : "=r"(result)); + return (result); +} + +/** + \brief Get FXCR + \details Returns the content of the FXCR Register. + \return FXCR Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_FXCR(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, fxcr" : "=r"(result)); + return (result); +} + + +/** + \brief Set FXCR + \details Writes the given value to the FXCR Register. + \param [in] FXCR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_FXCR(unsigned long fxcr) +{ + __ASM volatile("csrw fxcr, %0" : : "r"(fxcr)); +} + +/** + \brief Get MSTATUS + \details Returns the content of the MSTATUS Register. + \return MSTATUS Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MSTATUS(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mstatus" : "=r"(result)); + return (result); +} + +/** + \brief Set MSTATUS + \details Writes the given value to the MSTATUS Register. + \param [in] mstatus MSTATUS Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MSTATUS(unsigned long mstatus) +{ + __ASM volatile("csrw mstatus, %0" : : "r"(mstatus)); +} + +/** + \brief Get MHCR + \details Returns the content of the MHCR Register. + \return MHCR Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MHCR(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mhcr" : "=r"(result)); + return (result); +} + +/** + \brief Set MHCR + \details Writes the given value to the MHCR Register. + \param [in] MHCR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MHCR(unsigned long mhcr) +{ + __ASM volatile("csrw mhcr, %0" : : "r"(mhcr)); +} + +/** + \brief Get MHINT + \details Returns the content of the MHINT Register. + \return MHINT Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MHINT(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mhint" : "=r"(result)); + return (result); +} + +/** + \brief Set MHINT + \details Writes the given value to the MHINT Register. + \param [in] MHINT Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MHINT(unsigned long mhint) +{ + __ASM volatile("csrw mhint, %0" : : "r"(mhint)); +} + +/** + \brief Get MISA Register + \details Returns the content of the MISA Register. + \return MISA Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MISA(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, misa" : "=r"(result)); + return (result); +} + +/** + \brief Set MISA + \details Writes the given value to the MISA Register. + \param [in] misa MISA Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MISA(unsigned long misa) +{ + __ASM volatile("csrw misa, %0" : : "r"(misa)); +} + +/** + \brief Get MIE Register + \details Returns the content of the MIE Register. + \return MIE Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MIE(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mie" : "=r"(result)); + return (result); +} + +/** + \brief Set MIE + \details Writes the given value to the MIE Register. + \param [in] mie MIE Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MIE(unsigned long mie) +{ + __ASM volatile("csrw mie, %0" : : "r"(mie)); +} + +/** + \brief Get MTVEC Register + \details Returns the content of the MTVEC Register. + \return MTVEC Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MTVEC(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mtvec" : "=r"(result)); + return (result); +} + +/** + \brief Set MTVEC + \details Writes the given value to the MTVEC Register. + \param [in] mtvec MTVEC Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MTVEC(unsigned long mtvec) +{ + __ASM volatile("csrw mtvec, %0" : : "r"(mtvec)); +} + +/** + \brief Set MTVT + \details Writes the given value to the MTVT Register. + \param [in] mtvt MTVT Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MTVT(unsigned long mtvt) +{ + __ASM volatile("csrw mtvt, %0" : : "r"(mtvt)); +} + +/** + \brief Get MTVT Register + \details Returns the content of the MTVT Register. + \return MTVT Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MTVT(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mtvt" : "=r"(result)); + return (result); +} + +/** + \brief Get MTIME + \details Returns the content of the MTIME Register. + \return MTIME Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MTIME(void) +{ + unsigned long result; + __ASM volatile("rdtime %0" : "=r"(result)); + return (result); +} + +/** + \brief Get MTIMEH + \details Returns the content of the MTIME Register. + \return MTIME Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MTIMEH(void) +{ + unsigned long result; + __ASM volatile("rdtimeh %0" : "=r"(result)); + return (result); +} + +/** + \brief Get SP + \details Returns the content of the SP Register. + \return SP Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_SP(void) +{ + unsigned long result; + + __ASM volatile("mv %0, sp" : "=r"(result)); + return (result); +} + +/** + \brief Set SP + \details Writes the given value to the SP Register. + \param [in] sp SP Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_SP(unsigned long sp) +{ + __ASM volatile("mv sp, %0" : : "r"(sp): "sp"); +} + +/** + \brief Get MSCRATCH Register + \details Returns the content of the MSCRATCH Register. + \return MSCRATCH Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MSCRATCH(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mscratch" : "=r"(result)); + return (result); +} + +/** + \brief Set MSCRATCH + \details Writes the given value to the MSCRATCH Register. + \param [in] mscratch MSCRATCH Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MSCRATCH(unsigned long mscratch) +{ + __ASM volatile("csrw mscratch, %0" : : "r"(mscratch)); +} + +/** + \brief Get MEPC Register + \details Returns the content of the MEPC Register. + \return MEPC Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MEPC(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mepc" : "=r"(result)); + return (result); +} + +/** + \brief Set MEPC + \details Writes the given value to the MEPC Register. + \param [in] mepc MEPC Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MEPC(unsigned long mepc) +{ + __ASM volatile("csrw mepc, %0" : : "r"(mepc)); +} + +/** + \brief Get MCAUSE Register + \details Returns the content of the MCAUSE Register. + \return MCAUSE Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MCAUSE(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mcause" : "=r"(result)); + return (result); +} + +/** + \brief Get MNXTI Register + \details Returns the content of the MNXTI Register. + \return MNXTI Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MNXTI(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mnxti" : "=r"(result)); + return (result); +} + +/** + \brief Set MNXTI + \details Writes the given value to the MNXTI Register. + \param [in] mnxti MNXTI Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MNXTI(unsigned long mnxti) +{ + __ASM volatile("csrw mnxti, %0" : : "r"(mnxti)); +} + +/** + \brief Get MINTSTATUS Register + \details Returns the content of the MINTSTATUS Register. + \return MINTSTATUS Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MINTSTATUS(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mintstatus" : "=r"(result)); + return (result); +} + +/** + \brief Get MTVAL Register + \details Returns the content of the MTVAL Register. + \return MTVAL Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MTVAL(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mtval" : "=r"(result)); + return (result); +} + +/** + \brief Get MIP Register + \details Returns the content of the MIP Register. + \return MIP Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MIP(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mip" : "=r"(result)); + return (result); +} + +/** + \brief Set MIP + \details Writes the given value to the MIP Register. + \param [in] mip MIP Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MIP(unsigned long mip) +{ + __ASM volatile("csrw mip, %0" : : "r"(mip)); +} + +/** + \brief Get MCYCLEL Register + \details Returns the content of the MCYCLEL Register. + \return MCYCLE Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MCYCLE(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mcycle" : "=r"(result)); + return (result); +} + +/** + \brief Set MCYCLE + \details Write MCYCLE Register + \param [in] value MCYCLE Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MCYCLE(unsigned long value) +{ + __ASM volatile("csrw mcycle, %0" : : "r"(value)); +} + +/** + \brief Get MCYCLEH Register + \details Returns the content of the MCYCLEH Register. + \return MCYCLEH Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MCYCLEH(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mcycleh" : "=r"(result)); + return (result); +} + +/** + \brief Set MCYCLEH + \details Write MCYCLEH Register + \param [in] value MCYCLEH Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MCYCLEH(unsigned long value) +{ + __ASM volatile("csrw mcycleh, %0" : : "r"(value)); +} + +/** + \brief Get MINSTRET Register + \details Returns the content of the MINSTRET Register. + \return MINSTRET Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MINSTRET(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, minstret" : "=r"(result)); + return (result); +} + +/** + \brief Set MINSTRET + \details Write MINSTRET Register + \param [in] value MINSTRET Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MINSTRET(unsigned long value) +{ + __ASM volatile("csrw minstret, %0" : : "r"(value)); +} + +/** + \brief Get MINSTRETH Register + \details Returns the content of the MINSTRETH Register. + \return MINSTRETH Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MINSTRETH(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, minstreth" : "=r"(result)); + return (result); +} + +/** + \brief Set MINSTRETH + \details Write MINSTRETH Register + \param [in] value MINSTRETH Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MINSTRETH(unsigned long value) +{ + __ASM volatile("csrw minstreth, %0" : : "r"(value)); +} + +#if (CONFIG_CPU_XUANTIE_E907 || CONFIG_CPU_XUANTIE_E907F || CONFIG_CPU_XUANTIE_E907FD || CONFIG_CPU_XUANTIE_E907P || CONFIG_CPU_XUANTIE_E907FP || CONFIG_CPU_XUANTIE_E907FDP) +/** + \brief Get MITCMCR + \details Returns the content of the MITCMCR Register. + \return MITCMCR Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MITCMCR(void) +{ + unsigned long result; + __ASM volatile("csrr %0, mitcmcr" : "=r"(result)); + + return (result); +} + +/** + \brief Set MITCMCR + \details Writes the given value to the MITCMCR Register. + \param [in] itcmcr MITCMCR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MITCMCR(unsigned long mitcmcr) +{ + __ASM volatile("csrw mitcmcr, %0" : : "r"(mitcmcr)); +} + +/** + \brief Get MDTCMCR + \details Returns the content of the MDTCMCR Register. + \return MDTCMCR Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MDTCMCR(void) +{ + unsigned long result; + __ASM volatile("csrr %0, mdtcmcr" : "=r"(result)); + return (result); +} + +/** + \brief Set MDTCMCR + \details Writes the given value to the MDTCMCR Register. + \param [in] dtcmcr MDTCMCR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MDTCMCR(unsigned long mdtcmcr) +{ + __ASM volatile("csrw mdtcmcr, %0" : : "r"(mdtcmcr)); +} +#endif /* end e907xx */ + +/** + \brief Set MCOUNTINHIBIT + \details Write MCOUNTINHIBIT Register. + \param [in] value MCOUNTINHIBIT Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MCOUNTINHIBIT(uint32_t value) +{ + __ASM volatile("csrw mcountinhibit, %0" : : "r"(value)); +} + +/** + \brief Get MCOUNTINHIBIT + \details Read MCOUNTINHIBIT Register + \return MCOUNTINHIBIT Register value + */ +__ALWAYS_STATIC_INLINE unsigned int __get_MCOUNTINHIBIT(void) +{ + uint32_t result; + __ASM volatile("csrr %0, mcountinhibit" : "=r"(result)); + return result; +} + +/** + \brief Set MHPMEVENT + \details Write MHPMEVENT Register + \param [in] idx Index of MHPMEVENT Register + \param [in] value MHPMEVENT Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MHPMEVENT(unsigned long idx, unsigned long value) +{ + switch (idx) { + case 0: rv_csr_write(0x7E0, value); break; + case 2: rv_csr_write(0x7E1, value); break; + case 3: rv_csr_write(0x323, value); break; + case 4: rv_csr_write(0x324, value); break; + case 5: rv_csr_write(0x325, value); break; + case 6: rv_csr_write(0x326, value); break; + case 7: rv_csr_write(0x327, value); break; + case 8: rv_csr_write(0x328, value); break; + case 9: rv_csr_write(0x329, value); break; + case 10: rv_csr_write(0x32a, value); break; + case 11: rv_csr_write(0x32b, value); break; + case 12: rv_csr_write(0x32c, value); break; + case 13: rv_csr_write(0x32d, value); break; + case 14: rv_csr_write(0x32e, value); break; + case 15: rv_csr_write(0x32f, value); break; + case 16: rv_csr_write(0x330, value); break; + case 17: rv_csr_write(0x331, value); break; + case 18: rv_csr_write(0x332, value); break; + case 19: rv_csr_write(0x333, value); break; + case 20: rv_csr_write(0x334, value); break; + case 21: rv_csr_write(0x335, value); break; + case 22: rv_csr_write(0x336, value); break; + case 23: rv_csr_write(0x337, value); break; + case 24: rv_csr_write(0x338, value); break; + case 25: rv_csr_write(0x339, value); break; + case 26: rv_csr_write(0x33a, value); break; + case 27: rv_csr_write(0x33b, value); break; + case 28: rv_csr_write(0x33c, value); break; + case 29: rv_csr_write(0x33d, value); break; + case 30: rv_csr_write(0x33e, value); break; + case 31: rv_csr_write(0x33F, value); break; + default: break; + } +} + +/** + \brief Get MHPMEVENT + \details Read MHPMEVENT Register. + \param [in] idx Index of MHPMEVENT Register to read. + \return MHPMEVENT Register Value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MHPMEVENT(unsigned long idx) +{ + switch (idx) { + case 0: return rv_csr_read(0x7E0); + case 2: return rv_csr_read(0x7E1); + case 3: return rv_csr_read(0x323); + case 4: return rv_csr_read(0x324); + case 5: return rv_csr_read(0x325); + case 6: return rv_csr_read(0x326); + case 7: return rv_csr_read(0x327); + case 8: return rv_csr_read(0x328); + case 9: return rv_csr_read(0x329); + case 10: return rv_csr_read(0x32a); + case 11: return rv_csr_read(0x32b); + case 12: return rv_csr_read(0x32c); + case 13: return rv_csr_read(0x32d); + case 14: return rv_csr_read(0x32e); + case 15: return rv_csr_read(0x32f); + case 16: return rv_csr_read(0x330); + case 17: return rv_csr_read(0x331); + case 18: return rv_csr_read(0x332); + case 19: return rv_csr_read(0x333); + case 20: return rv_csr_read(0x334); + case 21: return rv_csr_read(0x335); + case 22: return rv_csr_read(0x336); + case 23: return rv_csr_read(0x337); + case 24: return rv_csr_read(0x338); + case 25: return rv_csr_read(0x339); + case 26: return rv_csr_read(0x33a); + case 27: return rv_csr_read(0x33b); + case 28: return rv_csr_read(0x33c); + case 29: return rv_csr_read(0x33d); + case 30: return rv_csr_read(0x33e); + case 31: return rv_csr_read(0x33F); + default: return 0; + } +} + +/** + \brief Set MHPMEVENTH + \details Write MHPMEVENTH Register + \param [in] idx Index of MHPMEVENT Register + \param [in] value MHPMEVENTH Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MHPMEVENTH(unsigned long idx, unsigned long value) +{ + switch (idx) { + case 3: rv_csr_write(0x723, value); break; + case 4: rv_csr_write(0x724, value); break; + case 5: rv_csr_write(0x725, value); break; + case 6: rv_csr_write(0x726, value); break; + case 7: rv_csr_write(0x727, value); break; + case 8: rv_csr_write(0x728, value); break; + case 9: rv_csr_write(0x729, value); break; + case 10: rv_csr_write(0x72A, value); break; + case 11: rv_csr_write(0x72B, value); break; + case 12: rv_csr_write(0x72C, value); break; + case 13: rv_csr_write(0x72D, value); break; + case 14: rv_csr_write(0x72E, value); break; + case 15: rv_csr_write(0x72F, value); break; + case 16: rv_csr_write(0x730, value); break; + case 17: rv_csr_write(0x731, value); break; + case 18: rv_csr_write(0x732, value); break; + case 19: rv_csr_write(0x733, value); break; + case 20: rv_csr_write(0x734, value); break; + case 21: rv_csr_write(0x735, value); break; + case 22: rv_csr_write(0x736, value); break; + case 23: rv_csr_write(0x737, value); break; + case 24: rv_csr_write(0x738, value); break; + case 25: rv_csr_write(0x739, value); break; + case 26: rv_csr_write(0x73A, value); break; + case 27: rv_csr_write(0x73B, value); break; + case 28: rv_csr_write(0x73C, value); break; + case 29: rv_csr_write(0x73D, value); break; + case 30: rv_csr_write(0x73E, value); break; + case 31: rv_csr_write(0x73F, value); break; + default: break; + } +} + +/** + \brief Get MHPMEVENTH + \details Read MHPMEVENTH Register. + \param [in] idx Index of MHPMEVENTH Register to read. + \return MHPMEVENTH Register Value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MHPMEVENTH(unsigned long idx) +{ + switch (idx) { + case 3: return rv_csr_read(0x723); + case 4: return rv_csr_read(0x724); + case 5: return rv_csr_read(0x725); + case 6: return rv_csr_read(0x726); + case 7: return rv_csr_read(0x727); + case 8: return rv_csr_read(0x728); + case 9: return rv_csr_read(0x729); + case 10: return rv_csr_read(0x72A); + case 11: return rv_csr_read(0x72B); + case 12: return rv_csr_read(0x72C); + case 13: return rv_csr_read(0x72D); + case 14: return rv_csr_read(0x72E); + case 15: return rv_csr_read(0x72F); + case 16: return rv_csr_read(0x730); + case 17: return rv_csr_read(0x731); + case 18: return rv_csr_read(0x732); + case 19: return rv_csr_read(0x733); + case 20: return rv_csr_read(0x734); + case 21: return rv_csr_read(0x735); + case 22: return rv_csr_read(0x736); + case 23: return rv_csr_read(0x737); + case 24: return rv_csr_read(0x738); + case 25: return rv_csr_read(0x739); + case 26: return rv_csr_read(0x73A); + case 27: return rv_csr_read(0x73B); + case 28: return rv_csr_read(0x73C); + case 29: return rv_csr_read(0x73D); + case 30: return rv_csr_read(0x73E); + case 31: return rv_csr_read(0x73F); + default: return 0; + } +} + +/** + \brief Set MHPMCOUNTER + \details Write MHPMCOUNTER Register + \param [in] idx Index of MHPMCOUNTER Register + \param [in] value MHPMCOUNTER Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MHPMCOUNTER(unsigned long idx, unsigned long value) +{ + switch (idx) { + case 3: rv_csr_write(0xB03, (value)); break; + case 4: rv_csr_write(0xB04, (value)); break; + case 5: rv_csr_write(0xB05, (value)); break; + case 6: rv_csr_write(0xB06, (value)); break; + case 7: rv_csr_write(0xB07, (value)); break; + case 8: rv_csr_write(0xB08, (value)); break; + case 9: rv_csr_write(0xB09, (value)); break; + case 10: rv_csr_write(0xB0A, (value)); break; + case 11: rv_csr_write(0xB0B, (value)); break; + case 12: rv_csr_write(0xB0C, (value)); break; + case 13: rv_csr_write(0xB0D, (value)); break; + case 14: rv_csr_write(0xB0E, (value)); break; + case 15: rv_csr_write(0xB0F, (value)); break; + case 16: rv_csr_write(0xB10, (value)); break; + case 17: rv_csr_write(0xB11, (value)); break; + case 18: rv_csr_write(0xB12, (value)); break; + case 19: rv_csr_write(0xB13, (value)); break; + case 20: rv_csr_write(0xB14, (value)); break; + case 21: rv_csr_write(0xB15, (value)); break; + case 22: rv_csr_write(0xB16, (value)); break; + case 23: rv_csr_write(0xB17, (value)); break; + case 24: rv_csr_write(0xB18, (value)); break; + case 25: rv_csr_write(0xB19, (value)); break; + case 26: rv_csr_write(0xB1A, (value)); break; + case 27: rv_csr_write(0xB1B, (value)); break; + case 28: rv_csr_write(0xB1C, (value)); break; + case 29: rv_csr_write(0xB1D, (value)); break; + case 30: rv_csr_write(0xB1E, (value)); break; + case 31: rv_csr_write(0xB1F, (value)); break; + default: break; + } +} + +/** + \brief Get MHPMCOUNTER + \details Write MHPMCOUNTER Register. + \param [in] idx Index of MHPMCOUNTER Register + \return MHPMCOUNTER Register Value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MHPMCOUNTER(unsigned long idx) +{ + switch (idx) { + case 3: return rv_csr_read(0xB03); + case 4: return rv_csr_read(0xB04); + case 5: return rv_csr_read(0xB05); + case 6: return rv_csr_read(0xB06); + case 7: return rv_csr_read(0xB07); + case 8: return rv_csr_read(0xB08); + case 9: return rv_csr_read(0xB09); + case 10: return rv_csr_read(0xB0A); + case 11: return rv_csr_read(0xB0B); + case 12: return rv_csr_read(0xB0C); + case 13: return rv_csr_read(0xB0D); + case 14: return rv_csr_read(0xB0E); + case 15: return rv_csr_read(0xB0F); + case 16: return rv_csr_read(0xB10); + case 17: return rv_csr_read(0xB11); + case 18: return rv_csr_read(0xB12); + case 19: return rv_csr_read(0xB13); + case 20: return rv_csr_read(0xB14); + case 21: return rv_csr_read(0xB15); + case 22: return rv_csr_read(0xB16); + case 23: return rv_csr_read(0xB17); + case 24: return rv_csr_read(0xB18); + case 25: return rv_csr_read(0xB19); + case 26: return rv_csr_read(0xB1A); + case 27: return rv_csr_read(0xB1B); + case 28: return rv_csr_read(0xB1C); + case 29: return rv_csr_read(0xB1D); + case 30: return rv_csr_read(0xB1E); + case 31: return rv_csr_read(0xB1F); + default: return 0; + } +} + +/** + \brief Set MHPMCOUNTERH + \details Write MHPMCOUNTERH Register + \param [in] idx Index of MHPMCOUNTERH Register + \param [in] value MHPMCOUNTERH Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MHPMCOUNTERH(unsigned long idx, unsigned long value) +{ + switch (idx) { + case 3: rv_csr_write(0xB83, (value)); break; + case 4: rv_csr_write(0xB84, (value)); break; + case 5: rv_csr_write(0xB85, (value)); break; + case 6: rv_csr_write(0xB86, (value)); break; + case 7: rv_csr_write(0xB87, (value)); break; + case 8: rv_csr_write(0xB88, (value)); break; + case 9: rv_csr_write(0xB89, (value)); break; + case 10: rv_csr_write(0xB8A, (value)); break; + case 11: rv_csr_write(0xB8B, (value)); break; + case 12: rv_csr_write(0xB8C, (value)); break; + case 13: rv_csr_write(0xB8D, (value)); break; + case 14: rv_csr_write(0xB8E, (value)); break; + case 15: rv_csr_write(0xB8F, (value)); break; + case 16: rv_csr_write(0xB90, (value)); break; + case 17: rv_csr_write(0xB91, (value)); break; + case 18: rv_csr_write(0xB92, (value)); break; + case 19: rv_csr_write(0xB93, (value)); break; + case 20: rv_csr_write(0xB94, (value)); break; + case 21: rv_csr_write(0xB95, (value)); break; + case 22: rv_csr_write(0xB96, (value)); break; + case 23: rv_csr_write(0xB97, (value)); break; + case 24: rv_csr_write(0xB98, (value)); break; + case 25: rv_csr_write(0xB99, (value)); break; + case 26: rv_csr_write(0xB9A, (value)); break; + case 27: rv_csr_write(0xB9B, (value)); break; + case 28: rv_csr_write(0xB9C, (value)); break; + case 29: rv_csr_write(0xB9D, (value)); break; + case 30: rv_csr_write(0xB9E, (value)); break; + case 31: rv_csr_write(0xB9F, (value)); break; + default: break; + } +} + +/** + \brief Get MHPMCOUNTERH + \details Write MHPMCOUNTERH Register. + \param [in] idx Index of MHPMCOUNTERH Register + \return MHPMCOUNTERH Register Value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MHPMCOUNTERH(unsigned long idx) +{ + switch (idx) { + case 3: return rv_csr_read(0xB83); + case 4: return rv_csr_read(0xB84); + case 5: return rv_csr_read(0xB85); + case 6: return rv_csr_read(0xB86); + case 7: return rv_csr_read(0xB87); + case 8: return rv_csr_read(0xB88); + case 9: return rv_csr_read(0xB89); + case 10: return rv_csr_read(0xB8A); + case 11: return rv_csr_read(0xB8B); + case 12: return rv_csr_read(0xB8C); + case 13: return rv_csr_read(0xB8D); + case 14: return rv_csr_read(0xB8E); + case 15: return rv_csr_read(0xB8F); + case 16: return rv_csr_read(0xB90); + case 17: return rv_csr_read(0xB91); + case 18: return rv_csr_read(0xB92); + case 19: return rv_csr_read(0xB93); + case 20: return rv_csr_read(0xB94); + case 21: return rv_csr_read(0xB95); + case 22: return rv_csr_read(0xB96); + case 23: return rv_csr_read(0xB97); + case 24: return rv_csr_read(0xB98); + case 25: return rv_csr_read(0xB99); + case 26: return rv_csr_read(0xB9A); + case 27: return rv_csr_read(0xB9B); + case 28: return rv_csr_read(0xB9C); + case 29: return rv_csr_read(0xB9D); + case 30: return rv_csr_read(0xB9E); + case 31: return rv_csr_read(0xB9F); + default: return 0; + } +} + +/** + \brief Get MVENDORID Register + \details Returns the content of the MVENDROID Register. + \return MVENDORID Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MVENDORID(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mvendorid" : "=r"(result)); + return (result); +} + +/** + \brief Get MARCHID Register + \details Returns the content of the MARCHID Register. + \return MARCHID Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MARCHID(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, marchid" : "=r"(result)); + return (result); +} + +/** + \brief Get MIMPID Register + \details Returns the content of the MIMPID Register. + \return MIMPID Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MIMPID(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mimpid" : "=r"(result)); + return (result); +} + +/** + \brief Get MHARTID Register + \details Returns the content of the MHARTID Register. + \return MHARTID Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MHARTID(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mhartid" : "=r"(result)); + return (result); +} + +/** + \brief Get PMPCFGx Register + \details Returns the content of the PMPCFGx Register. + \return PMPCFGx Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_PMPCFG0(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpcfg0" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPCFG1(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpcfg1" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPCFG2(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpcfg2" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPCFG3(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpcfg3" : "=r"(result)); + return (result); +} + +/** + \brief Get PMPxCFG Register by index + \details Returns the content of the PMPxCFG Register. + \param [in] idx PMP region index + \return PMPxCFG Register value + */ +__STATIC_INLINE uint8_t __get_PMPxCFG(unsigned long idx) +{ + unsigned long pmpcfgx = 0; + + if (idx < 4) { + pmpcfgx = __get_PMPCFG0(); + } else if (idx >=4 && idx < 8) { + idx -= 4; + pmpcfgx = __get_PMPCFG1(); + } else if (idx >=8 && idx < 12) { + idx -= 8; + pmpcfgx = __get_PMPCFG2(); + } else if (idx >=12 && idx < 16) { + idx -= 12; + pmpcfgx = __get_PMPCFG3(); + } else { + return 0; + } + + return (uint8_t)((pmpcfgx & (0xFF << (idx << 3))) >> (idx << 3)); +} + +/** + \brief Set PMPCFGx + \details Writes the given value to the PMPCFGx Register. + \param [in] pmpcfg PMPCFGx Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_PMPCFG0(unsigned long pmpcfg) +{ + __ASM volatile("csrw pmpcfg0, %0" : : "r"(pmpcfg)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPCFG1(unsigned long pmpcfg) +{ + __ASM volatile("csrw pmpcfg1, %0" : : "r"(pmpcfg)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPCFG2(unsigned long pmpcfg) +{ + __ASM volatile("csrw pmpcfg2, %0" : : "r"(pmpcfg)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPCFG3(unsigned long pmpcfg) +{ + __ASM volatile("csrw pmpcfg3, %0" : : "r"(pmpcfg)); +} + +/** + \brief Set PMPxCFG by index + \details Writes the given value to the PMPxCFG Register. + \param [in] idx PMPx region index + \param [in] pmpxcfg PMPxCFG Register value to set + */ +__STATIC_INLINE void __set_PMPxCFG(unsigned long idx, uint8_t pmpxcfg) +{ + unsigned long pmpcfgx = 0; + + if (idx < 4) { + pmpcfgx = __get_PMPCFG0(); + pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3)); + __set_PMPCFG0(pmpcfgx); + } else if (idx >=4 && idx < 8) { + idx -= 4; + pmpcfgx = __get_PMPCFG1(); + pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3)); + __set_PMPCFG1(pmpcfgx); + } else if (idx >=8 && idx < 12) { + idx -= 8; + pmpcfgx = __get_PMPCFG2(); + pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3)); + __set_PMPCFG2(pmpcfgx); + } else if (idx >=12 && idx < 16) { + idx -= 12; + pmpcfgx = __get_PMPCFG3(); + pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3)); + __set_PMPCFG3(pmpcfgx); + } else { + return; + } +} + +/** + \brief Get PMPADDRx Register + \details Returns the content of the PMPADDRx Register. + \return PMPADDRx Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR0(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr0" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR1(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr1" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR2(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr2" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR3(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr3" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR4(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr4" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR5(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr5" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR6(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr6" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR7(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr7" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR8(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr8" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR9(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr9" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR10(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr10" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR11(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr11" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR12(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr12" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR13(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr13" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR14(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr14" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR15(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr15" : "=r"(result)); + return (result); +} + +/** + \brief Get PMPADDRx Register by index + \details Returns the content of the PMPADDRx Register. + \param [in] idx PMP region index + \return PMPADDRx Register value + */ +__STATIC_INLINE unsigned long __get_PMPADDRx(unsigned long idx) +{ + switch (idx) { + case 0: return __get_PMPADDR0(); + case 1: return __get_PMPADDR1(); + case 2: return __get_PMPADDR2(); + case 3: return __get_PMPADDR3(); + case 4: return __get_PMPADDR4(); + case 5: return __get_PMPADDR5(); + case 6: return __get_PMPADDR6(); + case 7: return __get_PMPADDR7(); + case 8: return __get_PMPADDR8(); + case 9: return __get_PMPADDR9(); + case 10: return __get_PMPADDR10(); + case 11: return __get_PMPADDR11(); + case 12: return __get_PMPADDR12(); + case 13: return __get_PMPADDR13(); + case 14: return __get_PMPADDR14(); + case 15: return __get_PMPADDR15(); + default: return 0; + } +} + +/** + \brief Set PMPADDRx + \details Writes the given value to the PMPADDRx Register. + \param [in] pmpaddr PMPADDRx Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_PMPADDR0(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr0, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR1(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr1, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR2(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr2, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR3(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr3, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR4(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr4, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR5(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr5, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR6(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr6, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR7(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr7, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR8(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr8, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR9(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr9, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR10(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr10, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR11(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr11, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR12(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr12, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR13(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr13, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR14(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr14, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR15(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr15, %0" : : "r"(pmpaddr)); +} + +/** + \brief Set PMPADDRx by index + \details Writes the given value to the PMPADDRx Register. + \param [in] idx PMP region index + \param [in] pmpaddr PMPADDRx Register value to set + */ +__STATIC_INLINE void __set_PMPADDRx(unsigned long idx, unsigned long pmpaddr) +{ + switch (idx) { + case 0: __set_PMPADDR0(pmpaddr); break; + case 1: __set_PMPADDR1(pmpaddr); break; + case 2: __set_PMPADDR2(pmpaddr); break; + case 3: __set_PMPADDR3(pmpaddr); break; + case 4: __set_PMPADDR4(pmpaddr); break; + case 5: __set_PMPADDR5(pmpaddr); break; + case 6: __set_PMPADDR6(pmpaddr); break; + case 7: __set_PMPADDR7(pmpaddr); break; + case 8: __set_PMPADDR8(pmpaddr); break; + case 9: __set_PMPADDR9(pmpaddr); break; + case 10: __set_PMPADDR10(pmpaddr); break; + case 11: __set_PMPADDR11(pmpaddr); break; + case 12: __set_PMPADDR12(pmpaddr); break; + case 13: __set_PMPADDR13(pmpaddr); break; + case 14: __set_PMPADDR14(pmpaddr); break; + case 15: __set_PMPADDR15(pmpaddr); break; + default: return; + } +} + +/** + \brief Enable interrupts and exceptions + \details Enables interrupts and exceptions by setting the IE-bit and EE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __enable_excp_irq(void) +{ + __enable_irq(); +} + +/** + \brief Disable interrupts and exceptions + \details Disables interrupts and exceptions by clearing the IE-bit and EE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __disable_excp_irq(void) +{ + __disable_irq(); +} + +#define __CSI_GCC_OUT_REG(r) "=r" (r) +#define __CSI_GCC_USE_REG(r) "r" (r) + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__ALWAYS_STATIC_INLINE void __NOP(void) +{ + __ASM volatile("nop"); +} + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +__ALWAYS_STATIC_INLINE void __WFI(void) +{ + __ASM volatile("wfi"); +} + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one interrupt occurs. + */ +__ALWAYS_STATIC_INLINE void __WAIT(void) +{ + __ASM volatile("wfi"); +} + +/** + \brief Doze For Interrupt + \details Doze For Interrupt is a hint instruction that suspends execution until one interrupt occurs. + */ +__ALWAYS_STATIC_INLINE void __DOZE(void) +{ + __ASM volatile("wfi"); +} + +/** + \brief Stop For Interrupt + \details Stop For Interrupt is a hint instruction that suspends execution until one interrupt occurs. + */ +__ALWAYS_STATIC_INLINE void __STOP(void) +{ + __ASM volatile("wfi"); +} + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__ALWAYS_STATIC_INLINE void __ISB(void) +{ + __ASM volatile("fence.i"); + __ASM volatile("fence r, r"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__ALWAYS_STATIC_INLINE void __DSB(void) +{ + __ASM volatile("fence iorw, iorw"); +#if __riscv_xtheadsync + __ASM volatile("sync"); +#endif +} + +/** + \brief Invalid all icache + \details invalid all icache. + */ +__ALWAYS_STATIC_INLINE void __ICACHE_IALL(void) +{ +#if __riscv_xtheadcmo + __ASM volatile("icache.iall"); +#endif +} + +/** + \brief Invalid Icache by addr + \details Invalid Icache by addr. + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __ICACHE_IPA(unsigned long addr) +{ +#if __riscv_xtheadcmo + __ASM volatile("icache.ipa %0" : : "r"(addr)); +#endif +} + +/** + \brief Invalid all dcache + \details invalid all dcache. + */ +__ALWAYS_STATIC_INLINE void __DCACHE_IALL(void) +{ +#if __riscv_xtheadcmo + __ASM volatile("dcache.iall"); +#endif +} + +/** + \brief Clear all dcache + \details clear all dcache. + */ +__ALWAYS_STATIC_INLINE void __DCACHE_CALL(void) +{ +#if __riscv_xtheadcmo + __ASM volatile("dcache.call"); +#endif +} + +/** + \brief Clear&invalid all dcache + \details clear & invalid all dcache. + */ +__ALWAYS_STATIC_INLINE void __DCACHE_CIALL(void) +{ +#if __riscv_xtheadcmo + __ASM volatile("dcache.ciall"); +#endif +} + +/** + \brief Invalid Dcache by addr + \details Invalid Dcache by addr. + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __DCACHE_IPA(unsigned long addr) +{ +#if __riscv_xtheadcmo + __ASM volatile("dcache.ipa %0" : : "r"(addr)); +#endif +} + +/** + \brief Clear Dcache by addr + \details Clear Dcache by addr. + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __DCACHE_CPA(unsigned long addr) +{ +#if __riscv_xtheadcmo + __ASM volatile("dcache.cpa %0" : : "r"(addr)); +#endif +} + +/** + \brief Clear & Invalid Dcache by addr + \details Clear & Invalid Dcache by addr. + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __DCACHE_CIPA(unsigned long addr) +{ +#if __riscv_xtheadcmo + __ASM volatile("dcache.cipa %0" : : "r"(addr)); +#endif +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__ALWAYS_STATIC_INLINE void __DMB(void) +{ + __ASM volatile("fence"); +} + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__ALWAYS_STATIC_INLINE unsigned long __REV(unsigned long value) +{ + return __builtin_bswap32(value); +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__ALWAYS_STATIC_INLINE unsigned long __REV16(unsigned long value) +{ + unsigned long result; + + result = ((value & 0xFF000000) >> 8) | ((value & 0x00FF0000) << 8) | + ((value & 0x0000FF00) >> 8) | ((value & 0x000000FF) << 8); + + return (result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__ALWAYS_STATIC_INLINE int32_t __REVSH(int32_t value) +{ + return (short)(((value & 0xFF00) >> 8) | ((value & 0x00FF) << 8)); +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__ALWAYS_STATIC_INLINE unsigned long __ROR(unsigned long op1, unsigned long op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + */ +__ALWAYS_STATIC_INLINE void __BKPT(void) +{ + __ASM volatile("ebreak"); +} + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__ALWAYS_STATIC_INLINE unsigned long __RBIT(unsigned long value) +{ + unsigned long result; + + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + + for (value >>= 1U; value; value >>= 1U) { + result <<= 1U; + result |= value & 1U; + s--; + } + + result <<= s; /* shift when v's highest bits are zero */ + + return (result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz +/** + \details This function saturates a signed value. + \param [in] x Value to be saturated + \param [in] y Bit position to saturate to [1..32] + \return Saturated value. + */ +__ALWAYS_STATIC_INLINE int32_t __SSAT(int32_t x, unsigned long y) +{ + int32_t posMax, negMin; + unsigned long i; + + posMax = 1; + + for (i = 0; i < (y - 1); i++) { + posMax = posMax * 2; + } + + if (x > 0) { + posMax = (posMax - 1); + + if (x > posMax) { + x = posMax; + } + +// x &= (posMax * 2 + 1); + } else { + negMin = -posMax; + + if (x < negMin) { + x = negMin; + } + +// x &= (posMax * 2 - 1); + } + + return (x); +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__ALWAYS_STATIC_INLINE unsigned long __USAT(unsigned long value, unsigned long sat) +{ + unsigned long result; + + if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) { + result = 0xFFFFFFFF >> (32 - sat); + } else { + result = value; + } + + return (result); +} + +/** + \brief Unsigned Saturate for internal use + \details Saturates an unsigned value, should not call directly. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__ALWAYS_STATIC_INLINE unsigned long __IUSAT(unsigned long value, unsigned long sat) +{ + unsigned long result; + + if (value & 0x80000000) { /* only overflow set bit-31 */ + result = 0; + } else if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) { + result = 0xFFFFFFFF >> (32 - sat); + } else { + result = value; + } + + return (result); +} + +/** + \brief Rotate Right with Extend + \details This function moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \note carry input will always 0. + \param [in] op1 Value to rotate + \return Rotated value + */ +__ALWAYS_STATIC_INLINE unsigned long __RRX(unsigned long op1) +{ + return 0; +} + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] addr Pointer to location + \return value of type uint8_t at (*ptr) + */ +__ALWAYS_STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + unsigned long result; + + __ASM volatile("lb %0, 0(%1)" : "=r"(result) : "r"(addr)); + + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] addr Pointer to location + \return value of type uint16_t at (*ptr) + */ +__ALWAYS_STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + unsigned long result; + + __ASM volatile("lh %0, 0(%1)" : "=r"(result) : "r"(addr)); + + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] addr Pointer to location + \return value of type unsigned long at (*ptr) + */ +__ALWAYS_STATIC_INLINE unsigned long __LDRT(volatile unsigned long *addr) +{ + unsigned long result; + + __ASM volatile("lw %0, 0(%1)" : "=r"(result) : "r"(addr)); + + return (result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] addr Pointer to location + */ +__ALWAYS_STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile("sb %1, 0(%0)" :: "r"(addr), "r"((unsigned long)value) : "memory"); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] addr Pointer to location + */ +__ALWAYS_STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile("sh %1, 0(%0)" :: "r"(addr), "r"((unsigned long)value) : "memory"); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] addr Pointer to location + */ +__ALWAYS_STATIC_INLINE void __STRT(unsigned long value, volatile unsigned long *addr) +{ + __ASM volatile("sw %1, 0(%0)" :: "r"(addr), "r"(value) : "memory"); +} + +/*@}*/ /* end of group CSI_Core_InstructionInterface */ + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CSI_SIMD_intrinsics CSI SIMD Intrinsics + Access to dedicated SIMD instructions \n + Single Instruction Multiple Data (SIMD) extensions are provided to simplify development of application software. SIMD extensions increase the processing capability without materially increasing the power consumption. The SIMD extensions are completely transparent to the operating system (OS), allowing existing OS ports to be used. + + @{ +*/ + +/** + \brief Halfword packing instruction. Combines bits[15:0] of val1 with bits[31:16] + of val2 levitated with the val3. + \details Combine a halfword from one register with a halfword from another register. + The second argument can be left-shifted before extraction of the halfword. + \param [in] val1 first 16-bit operands + \param [in] val2 second 16-bit operands + \param [in] val3 value for left-shifting val2. Value range [0..31]. + \return the combination of halfwords. + \remark + res[15:0] = val1[15:0] \n + res[31:16] = val2[31:16] << val3 + */ +__ALWAYS_STATIC_INLINE unsigned long __PKHBT(unsigned long val1, unsigned long val2, unsigned long val3) +{ + return ((((int32_t)(val1) << 0) & (int32_t)0x0000FFFF) | (((int32_t)(val2) << val3) & (int32_t)0xFFFF0000)); +} + +/** + \brief Halfword packing instruction. Combines bits[31:16] of val1 with bits[15:0] + of val2 right-shifted with the val3. + \details Combine a halfword from one register with a halfword from another register. + The second argument can be right-shifted before extraction of the halfword. + \param [in] val1 first 16-bit operands + \param [in] val2 second 16-bit operands + \param [in] val3 value for right-shifting val2. Value range [1..32]. + \return the combination of halfwords. + \remark + res[15:0] = val2[15:0] >> val3 \n + res[31:16] = val1[31:16] + */ +__ALWAYS_STATIC_INLINE unsigned long __PKHTB(unsigned long val1, unsigned long val2, unsigned long val3) +{ + return ((((int32_t)(val1) << 0) & (int32_t)0xFFFF0000) | (((int32_t)(val2) >> val3) & (int32_t)0x0000FFFF)); +} + +/** + \brief Dual 16-bit signed saturate. + \details This function saturates a signed value. + \param [in] x two signed 16-bit values to be saturated. + \param [in] y bit position for saturation, an integral constant expression in the range 1 to 16. + \return the sum of the absolute differences of the following bytes, added to the accumulation value:\n + the signed saturation of the low halfword in val1, saturated to the bit position specified in + val2 and returned in the low halfword of the return value.\n + the signed saturation of the high halfword in val1, saturated to the bit position specified in + val2 and returned in the high halfword of the return value. + */ +__ALWAYS_STATIC_INLINE unsigned long __SSAT16(int32_t x, const unsigned long y) +{ + int32_t r = 0, s = 0; + + r = __SSAT((((int32_t)x << 16) >> 16), y) & (int32_t)0x0000FFFF; + s = __SSAT((((int32_t)x) >> 16), y) & (int32_t)0x0000FFFF; + + return ((unsigned long)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturate. + \details This function enables you to saturate two signed 16-bit values to a selected unsigned range. + \param [in] x two signed 16-bit values to be saturated. + \param [in] y bit position for saturation, an integral constant expression in the range 1 to 16. + \return the saturation of the two signed 16-bit values, as non-negative values: + the saturation of the low halfword in val1, saturated to the bit position specified in + val2 and returned in the low halfword of the return value.\n + the saturation of the high halfword in val1, saturated to the bit position specified in + val2 and returned in the high halfword of the return value. + */ +__ALWAYS_STATIC_INLINE unsigned long __USAT16(unsigned long x, const unsigned long y) +{ + int32_t r = 0, s = 0; + + r = __IUSAT(((x << 16) >> 16), y) & 0x0000FFFF; + s = __IUSAT(((x) >> 16), y) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Quad 8-bit saturating addition. + \details This function enables you to perform four 8-bit integer additions, + saturating the results to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the saturated addition of the first byte of each operand in the first byte of the return value.\n + the saturated addition of the second byte of each operand in the second byte of the return value.\n + the saturated addition of the third byte of each operand in the third byte of the return value.\n + the saturated addition of the fourth byte of each operand in the fourth byte of the return value.\n + The returned results are saturated to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1. + \remark + res[7:0] = val1[7:0] + val2[7:0] \n + res[15:8] = val1[15:8] + val2[15:8] \n + res[23:16] = val1[23:16] + val2[23:16] \n + res[31:24] = val1[31:24] + val2[31:24] + */ +__ALWAYS_STATIC_INLINE unsigned long __QADD8(unsigned long x, unsigned long y) +{ + int32_t r, s, t, u; + + r = __SSAT(((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((int32_t)x) >> 24) + (((int32_t)y) >> 24)), 8) & (int32_t)0x000000FF; + + return ((unsigned long)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned saturating addition. + \details This function enables you to perform four unsigned 8-bit integer additions, + saturating the results to the 8-bit unsigned integer range 0 < x < 2^8 - 1. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the saturated addition of the first byte of each operand in the first byte of the return value.\n + the saturated addition of the second byte of each operand in the second byte of the return value.\n + the saturated addition of the third byte of each operand in the third byte of the return value.\n + the saturated addition of the fourth byte of each operand in the fourth byte of the return value.\n + The returned results are saturated to the 8-bit signed integer range 0 <= x <= 2^8 - 1. + \remark + res[7:0] = val1[7:0] + val2[7:0] \n + res[15:8] = val1[15:8] + val2[15:8] \n + res[23:16] = val1[23:16] + val2[23:16] \n + res[31:24] = val1[31:24] + val2[31:24] + */ +__ALWAYS_STATIC_INLINE unsigned long __UQADD8(unsigned long x, unsigned long y) +{ + int32_t r, s, t, u; + + r = __IUSAT((((x << 24) >> 24) + ((y << 24) >> 24)), 8) & 0x000000FF; + s = __IUSAT((((x << 16) >> 24) + ((y << 16) >> 24)), 8) & 0x000000FF; + t = __IUSAT((((x << 8) >> 24) + ((y << 8) >> 24)), 8) & 0x000000FF; + u = __IUSAT((((x) >> 24) + ((y) >> 24)), 8) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Quad 8-bit signed addition. + \details This function performs four 8-bit signed integer additions. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the addition of the first bytes from each operand, in the first byte of the return value.\n + the addition of the second bytes of each operand, in the second byte of the return value.\n + the addition of the third bytes of each operand, in the third byte of the return value.\n + the addition of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + res[7:0] = val1[7:0] + val2[7:0] \n + res[15:8] = val1[15:8] + val2[15:8] \n + res[23:16] = val1[23:16] + val2[23:16] \n + res[31:24] = val1[31:24] + val2[31:24] + */ +__ALWAYS_STATIC_INLINE unsigned long __SADD8(unsigned long x, unsigned long y) +{ + int32_t r, s, t, u; + + r = ((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)) & (int32_t)0x000000FF; + s = ((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)) & (int32_t)0x000000FF; + t = ((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)) & (int32_t)0x000000FF; + u = ((((int32_t)x) >> 24) + (((int32_t)y) >> 24)) & (int32_t)0x000000FF; + + return ((unsigned long)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned addition. + \details This function performs four unsigned 8-bit integer additions. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the addition of the first bytes from each operand, in the first byte of the return value.\n + the addition of the second bytes of each operand, in the second byte of the return value.\n + the addition of the third bytes of each operand, in the third byte of the return value.\n + the addition of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + res[7:0] = val1[7:0] + val2[7:0] \n + res[15:8] = val1[15:8] + val2[15:8] \n + res[23:16] = val1[23:16] + val2[23:16] \n + res[31:24] = val1[31:24] + val2[31:24] + */ +__ALWAYS_STATIC_INLINE unsigned long __UADD8(unsigned long x, unsigned long y) +{ + int32_t r, s, t, u; + + r = (((x << 24) >> 24) + ((y << 24) >> 24)) & 0x000000FF; + s = (((x << 16) >> 24) + ((y << 16) >> 24)) & 0x000000FF; + t = (((x << 8) >> 24) + ((y << 8) >> 24)) & 0x000000FF; + u = (((x) >> 24) + ((y) >> 24)) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Quad 8-bit saturating subtract. + \details This function enables you to perform four 8-bit integer subtractions, + saturating the results to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the subtraction of the first byte of each operand in the first byte of the return value.\n + the subtraction of the second byte of each operand in the second byte of the return value.\n + the subtraction of the third byte of each operand in the third byte of the return value.\n + the subtraction of the fourth byte of each operand in the fourth byte of the return value.\n + The returned results are saturated to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1. + \remark + res[7:0] = val1[7:0] - val2[7:0] \n + res[15:8] = val1[15:8] - val2[15:8] \n + res[23:16] = val1[23:16] - val2[23:16] \n + res[31:24] = val1[31:24] - val2[31:24] + */ +__ALWAYS_STATIC_INLINE unsigned long __QSUB8(unsigned long x, unsigned long y) +{ + int32_t r, s, t, u; + + r = __SSAT(((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((int32_t)x) >> 24) - (((int32_t)y) >> 24)), 8) & (int32_t)0x000000FF; + + return ((unsigned long)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned saturating subtraction. + \details This function enables you to perform four unsigned 8-bit integer subtractions, + saturating the results to the 8-bit unsigned integer range 0 < x < 2^8 - 1. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the subtraction of the first byte of each operand in the first byte of the return value.\n + the subtraction of the second byte of each operand in the second byte of the return value.\n + the subtraction of the third byte of each operand in the third byte of the return value.\n + the subtraction of the fourth byte of each operand in the fourth byte of the return value.\n + The returned results are saturated to the 8-bit unsigned integer range 0 <= x <= 2^8 - 1. + \remark + res[7:0] = val1[7:0] - val2[7:0] \n + res[15:8] = val1[15:8] - val2[15:8] \n + res[23:16] = val1[23:16] - val2[23:16] \n + res[31:24] = val1[31:24] - val2[31:24] + */ +__ALWAYS_STATIC_INLINE unsigned long __UQSUB8(unsigned long x, unsigned long y) +{ + int32_t r, s, t, u; + + r = __IUSAT((((x << 24) >> 24) - ((y << 24) >> 24)), 8) & 0x000000FF; + s = __IUSAT((((x << 16) >> 24) - ((y << 16) >> 24)), 8) & 0x000000FF; + t = __IUSAT((((x << 8) >> 24) - ((y << 8) >> 24)), 8) & 0x000000FF; + u = __IUSAT((((x) >> 24) - ((y) >> 24)), 8) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Quad 8-bit signed subtraction. + \details This function enables you to perform four 8-bit signed integer subtractions. + \param [in] x first four 8-bit operands of each subtraction. + \param [in] y second four 8-bit operands of each subtraction. + \return the subtraction of the first bytes from each operand, in the first byte of the return value.\n + the subtraction of the second bytes of each operand, in the second byte of the return value.\n + the subtraction of the third bytes of each operand, in the third byte of the return value.\n + the subtraction of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + res[7:0] = val1[7:0] - val2[7:0] \n + res[15:8] = val1[15:8] - val2[15:8] \n + res[23:16] = val1[23:16] - val2[23:16] \n + res[31:24] = val1[31:24] - val2[31:24] + */ +__ALWAYS_STATIC_INLINE unsigned long __SSUB8(unsigned long x, unsigned long y) +{ + int32_t r, s, t, u; + + r = ((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)) & (int32_t)0x000000FF; + s = ((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)) & (int32_t)0x000000FF; + t = ((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)) & (int32_t)0x000000FF; + u = ((((int32_t)x) >> 24) - (((int32_t)y) >> 24)) & (int32_t)0x000000FF; + + return ((unsigned long)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned subtract. + \details This function enables you to perform four 8-bit unsigned integer subtractions. + \param [in] x first four 8-bit operands of each subtraction. + \param [in] y second four 8-bit operands of each subtraction. + \return the subtraction of the first bytes from each operand, in the first byte of the return value.\n + the subtraction of the second bytes of each operand, in the second byte of the return value.\n + the subtraction of the third bytes of each operand, in the third byte of the return value.\n + the subtraction of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + res[7:0] = val1[7:0] - val2[7:0] \n + res[15:8] = val1[15:8] - val2[15:8] \n + res[23:16] = val1[23:16] - val2[23:16] \n + res[31:24] = val1[31:24] - val2[31:24] + */ +__ALWAYS_STATIC_INLINE unsigned long __USUB8(unsigned long x, unsigned long y) +{ + int32_t r, s, t, u; + + r = (((x << 24) >> 24) - ((y << 24) >> 24)) & 0x000000FF; + s = (((x << 16) >> 24) - ((y << 16) >> 24)) & 0x000000FF; + t = (((x << 8) >> 24) - ((y << 8) >> 24)) & 0x000000FF; + u = (((x) >> 24) - ((y) >> 24)) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Unsigned sum of quad 8-bit unsigned absolute difference. + \details This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values + of the differences together, returning the result as a single unsigned integer. + \param [in] x first four 8-bit operands of each subtraction. + \param [in] y second four 8-bit operands of each subtraction. + \return the subtraction of the first bytes from each operand, in the first byte of the return value.\n + the subtraction of the second bytes of each operand, in the second byte of the return value.\n + the subtraction of the third bytes of each operand, in the third byte of the return value.\n + the subtraction of the fourth bytes of each operand, in the fourth byte of the return value.\n + The sum is returned as a single unsigned integer. + \remark + absdiff1 = val1[7:0] - val2[7:0] \n + absdiff2 = val1[15:8] - val2[15:8] \n + absdiff3 = val1[23:16] - val2[23:16] \n + absdiff4 = val1[31:24] - val2[31:24] \n + res[31:0] = absdiff1 + absdiff2 + absdiff3 + absdiff4 + */ +__ALWAYS_STATIC_INLINE unsigned long __USAD8(unsigned long x, unsigned long y) +{ + int32_t r, s, t, u; + + r = (((x << 24) >> 24) - ((y << 24) >> 24)) & 0x000000FF; + s = (((x << 16) >> 24) - ((y << 16) >> 24)) & 0x000000FF; + t = (((x << 8) >> 24) - ((y << 8) >> 24)) & 0x000000FF; + u = (((x) >> 24) - ((y) >> 24)) & 0x000000FF; + + return (u + t + s + r); +} + +#if 0 +/** + \brief Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate. + \details This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values + of the differences to a 32-bit accumulate operand. + \param [in] x first four 8-bit operands of each subtraction. + \param [in] y second four 8-bit operands of each subtraction. + \param [in] sum accumulation value. + \return the sum of the absolute differences of the following bytes, added to the accumulation value: + the subtraction of the first bytes from each operand, in the first byte of the return value.\n + the subtraction of the second bytes of each operand, in the second byte of the return value.\n + the subtraction of the third bytes of each operand, in the third byte of the return value.\n + the subtraction of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + absdiff1 = val1[7:0] - val2[7:0] \n + absdiff2 = val1[15:8] - val2[15:8] \n + absdiff3 = val1[23:16] - val2[23:16] \n + absdiff4 = val1[31:24] - val2[31:24] \n + sum = absdiff1 + absdiff2 + absdiff3 + absdiff4 \n + res[31:0] = sum[31:0] + val3[31:0] + */ +__ALWAYS_STATIC_INLINE unsigned long __USADA8(unsigned long x, unsigned long y, unsigned long sum) +{ + int32_t r, s, t, u; + +#ifdef __cplusplus + r = (abs((long long)((x << 24) >> 24) - ((y << 24) >> 24))) & 0x000000FF; + s = (abs((long long)((x << 16) >> 24) - ((y << 16) >> 24))) & 0x000000FF; + t = (abs((long long)((x << 8) >> 24) - ((y << 8) >> 24))) & 0x000000FF; + u = (abs((long long)((x) >> 24) - ((y) >> 24))) & 0x000000FF; +#else + r = (abs(((x << 24) >> 24) - ((y << 24) >> 24))) & 0x000000FF; + s = (abs(((x << 16) >> 24) - ((y << 16) >> 24))) & 0x000000FF; + t = (abs(((x << 8) >> 24) - ((y << 8) >> 24))) & 0x000000FF; + u = (abs(((x) >> 24) - ((y) >> 24))) & 0x000000FF; +#endif + return (u + t + s + r + sum); +} +#endif + +/** + \brief Dual 16-bit saturating addition. + \details This function enables you to perform two 16-bit integer arithmetic additions in parallel, + saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the saturated addition of the low halfwords, in the low halfword of the return value.\n + the saturated addition of the high halfwords, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] + val2[15:0] \n + res[31:16] = val1[31:16] + val2[31:16] + */ +__ALWAYS_STATIC_INLINE unsigned long __QADD16(unsigned long x, unsigned long y) +{ + int32_t r = 0, s = 0; + + r = __SSAT(((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((int32_t)x) >> 16) + (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((unsigned long)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturating addition. + \details This function enables you to perform two unsigned 16-bit integer additions, saturating + the results to the 16-bit unsigned integer range 0 < x < 2^16 - 1. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the saturated addition of the low halfwords, in the low halfword of the return value.\n + the saturated addition of the high halfwords, in the high halfword of the return value.\n + The results are saturated to the 16-bit unsigned integer range 0 < x < 2^16 - 1. + \remark + res[15:0] = val1[15:0] + val2[15:0] \n + res[31:16] = val1[31:16] + val2[31:16] + */ +__ALWAYS_STATIC_INLINE unsigned long __UQADD16(unsigned long x, unsigned long y) +{ + int32_t r = 0, s = 0; + + r = __IUSAT((((x << 16) >> 16) + ((y << 16) >> 16)), 16) & 0x0000FFFF; + s = __IUSAT((((x) >> 16) + ((y) >> 16)), 16) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed addition. + \details This function enables you to perform two 16-bit signed integer additions. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the addition of the low halfwords in the low halfword of the return value.\n + the addition of the high halfwords in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] + val2[15:0] \n + res[31:16] = val1[31:16] + val2[31:16] + */ +__ALWAYS_STATIC_INLINE unsigned long __SADD16(unsigned long x, unsigned long y) +{ + int32_t r = 0, s = 0; + + r = ((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF; + s = ((((int32_t)x) >> 16) + (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF; + + return ((unsigned long)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned addition + \details This function enables you to perform two 16-bit unsigned integer additions. + \param [in] x first two 16-bit summands for each addition. + \param [in] y second two 16-bit summands for each addition. + \return the addition of the low halfwords in the low halfword of the return value.\n + the addition of the high halfwords in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] + val2[15:0] \n + res[31:16] = val1[31:16] + val2[31:16] + */ +__ALWAYS_STATIC_INLINE unsigned long __UADD16(unsigned long x, unsigned long y) +{ + int32_t r = 0, s = 0; + + r = (((x << 16) >> 16) + ((y << 16) >> 16)) & 0x0000FFFF; + s = (((x) >> 16) + ((y) >> 16)) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + + +/** + \brief Dual 16-bit signed addition with halved results. + \details This function enables you to perform two signed 16-bit integer additions, halving the results. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the halved addition of the low halfwords, in the low halfword of the return value.\n + the halved addition of the high halfwords, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] + val2[15:0]) >> 1 \n + res[31:16] = (val1[31:16] + val2[31:16]) >> 1 + */ +__ALWAYS_STATIC_INLINE unsigned long __SHADD16(unsigned long x, unsigned long y) +{ + int32_t r, s; + + r = (((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((int32_t)x) >> 16) + (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((unsigned long)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned addition with halved results. + \details This function enables you to perform two unsigned 16-bit integer additions, halving the results. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the halved addition of the low halfwords, in the low halfword of the return value.\n + the halved addition of the high halfwords, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] + val2[15:0]) >> 1 \n + res[31:16] = (val1[31:16] + val2[31:16]) >> 1 + */ +__ALWAYS_STATIC_INLINE unsigned long __UHADD16(unsigned long x, unsigned long y) +{ + int32_t r, s; + + r = ((((x << 16) >> 16) + ((y << 16) >> 16)) >> 1) & 0x0000FFFF; + s = ((((x) >> 16) + ((y) >> 16)) >> 1) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Quad 8-bit signed addition with halved results. + \details This function enables you to perform four signed 8-bit integer additions, halving the results. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the halved addition of the first bytes from each operand, in the first byte of the return value.\n + the halved addition of the second bytes from each operand, in the second byte of the return value.\n + the halved addition of the third bytes from each operand, in the third byte of the return value.\n + the halved addition of the fourth bytes from each operand, in the fourth byte of the return value. + \remark + res[7:0] = (val1[7:0] + val2[7:0] ) >> 1 \n + res[15:8] = (val1[15:8] + val2[15:8] ) >> 1 \n + res[23:16] = (val1[23:16] + val2[23:16]) >> 1 \n + res[31:24] = (val1[31:24] + val2[31:24]) >> 1 + */ +__ALWAYS_STATIC_INLINE unsigned long __SHADD8(unsigned long x, unsigned long y) +{ + int32_t r, s, t, u; + + r = (((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)) >> 1) & (int32_t)0x000000FF; + s = (((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)) >> 1) & (int32_t)0x000000FF; + t = (((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)) >> 1) & (int32_t)0x000000FF; + u = (((((int32_t)x) >> 24) + (((int32_t)y) >> 24)) >> 1) & (int32_t)0x000000FF; + + return ((unsigned long)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned addition with halved results. + \details This function enables you to perform four unsigned 8-bit integer additions, halving the results. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the halved addition of the first bytes from each operand, in the first byte of the return value.\n + the halved addition of the second bytes from each operand, in the second byte of the return value.\n + the halved addition of the third bytes from each operand, in the third byte of the return value.\n + the halved addition of the fourth bytes from each operand, in the fourth byte of the return value. + \remark + res[7:0] = (val1[7:0] + val2[7:0] ) >> 1 \n + res[15:8] = (val1[15:8] + val2[15:8] ) >> 1 \n + res[23:16] = (val1[23:16] + val2[23:16]) >> 1 \n + res[31:24] = (val1[31:24] + val2[31:24]) >> 1 + */ +__ALWAYS_STATIC_INLINE unsigned long __UHADD8(unsigned long x, unsigned long y) +{ + int32_t r, s, t, u; + + r = ((((x << 24) >> 24) + ((y << 24) >> 24)) >> 1) & 0x000000FF; + s = ((((x << 16) >> 24) + ((y << 16) >> 24)) >> 1) & 0x000000FF; + t = ((((x << 8) >> 24) + ((y << 8) >> 24)) >> 1) & 0x000000FF; + u = ((((x) >> 24) + ((y) >> 24)) >> 1) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Dual 16-bit saturating subtract. + \details This function enables you to perform two 16-bit integer subtractions in parallel, + saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the saturated subtraction of the low halfwords, in the low halfword of the return value.\n + the saturated subtraction of the high halfwords, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] - val2[15:0] \n + res[31:16] = val1[31:16] - val2[31:16] + */ +__ALWAYS_STATIC_INLINE unsigned long __QSUB16(unsigned long x, unsigned long y) +{ + int32_t r, s; + + r = __SSAT(((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((int32_t)x) >> 16) - (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((unsigned long)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturating subtraction. + \details This function enables you to perform two unsigned 16-bit integer subtractions, + saturating the results to the 16-bit unsigned integer range 0 < x < 2^16 - 1. + \param [in] x first two 16-bit operands for each subtraction. + \param [in] y second two 16-bit operands for each subtraction. + \return the saturated subtraction of the low halfwords, in the low halfword of the return value.\n + the saturated subtraction of the high halfwords, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] - val2[15:0] \n + res[31:16] = val1[31:16] - val2[31:16] + */ +__ALWAYS_STATIC_INLINE unsigned long __UQSUB16(unsigned long x, unsigned long y) +{ + int32_t r, s; + + r = __IUSAT((((x << 16) >> 16) - ((y << 16) >> 16)), 16) & 0x0000FFFF; + s = __IUSAT((((x) >> 16) - ((y) >> 16)), 16) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed subtraction. + \details This function enables you to perform two 16-bit signed integer subtractions. + \param [in] x first two 16-bit operands of each subtraction. + \param [in] y second two 16-bit operands of each subtraction. + \return the subtraction of the low halfword in the second operand from the low + halfword in the first operand, in the low halfword of the return value. \n + the subtraction of the high halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] - val2[15:0] \n + res[31:16] = val1[31:16] - val2[31:16] + */ +__ALWAYS_STATIC_INLINE unsigned long __SSUB16(unsigned long x, unsigned long y) +{ + int32_t r, s; + + r = ((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF; + s = ((((int32_t)x) >> 16) - (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF; + + return ((unsigned long)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned subtract. + \details This function enables you to perform two 16-bit unsigned integer subtractions. + \param [in] x first two 16-bit operands of each subtraction. + \param [in] y second two 16-bit operands of each subtraction. + \return the subtraction of the low halfword in the second operand from the low + halfword in the first operand, in the low halfword of the return value. \n + the subtraction of the high halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] - val2[15:0] \n + res[31:16] = val1[31:16] - val2[31:16] + */ +__ALWAYS_STATIC_INLINE unsigned long __USUB16(unsigned long x, unsigned long y) +{ + int32_t r, s; + + r = (((x << 16) >> 16) - ((y << 16) >> 16)) & 0x0000FFFF; + s = (((x) >> 16) - ((y) >> 16)) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed subtraction with halved results. + \details This function enables you to perform two signed 16-bit integer subtractions, halving the results. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the halved subtraction of the low halfwords, in the low halfword of the return value.\n + the halved subtraction of the high halfwords, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] - val2[15:0]) >> 1 \n + res[31:16] = (val1[31:16] - val2[31:16]) >> 1 + */ +__ALWAYS_STATIC_INLINE unsigned long __SHSUB16(unsigned long x, unsigned long y) +{ + int32_t r, s; + + r = (((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((int32_t)x) >> 16) - (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((unsigned long)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned subtraction with halved results. + \details This function enables you to perform two unsigned 16-bit integer subtractions, halving the results. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the halved subtraction of the low halfwords, in the low halfword of the return value.\n + the halved subtraction of the high halfwords, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] - val2[15:0]) >> 1 \n + res[31:16] = (val1[31:16] - val2[31:16]) >> 1 + */ +__ALWAYS_STATIC_INLINE unsigned long __UHSUB16(unsigned long x, unsigned long y) +{ + int32_t r, s; + + r = ((((x << 16) >> 16) - ((y << 16) >> 16)) >> 1) & 0x0000FFFF; + s = ((((x) >> 16) - ((y) >> 16)) >> 1) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Quad 8-bit signed addition with halved results. + \details This function enables you to perform four signed 8-bit integer subtractions, halving the results. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the halved subtraction of the first bytes from each operand, in the first byte of the return value.\n + the halved subtraction of the second bytes from each operand, in the second byte of the return value.\n + the halved subtraction of the third bytes from each operand, in the third byte of the return value.\n + the halved subtraction of the fourth bytes from each operand, in the fourth byte of the return value. + \remark + res[7:0] = (val1[7:0] - val2[7:0] ) >> 1 \n + res[15:8] = (val1[15:8] - val2[15:8] ) >> 1 \n + res[23:16] = (val1[23:16] - val2[23:16]) >> 1 \n + res[31:24] = (val1[31:24] - val2[31:24]) >> 1 + */ +__ALWAYS_STATIC_INLINE unsigned long __SHSUB8(unsigned long x, unsigned long y) +{ + int32_t r, s, t, u; + + r = (((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)) >> 1) & (int32_t)0x000000FF; + s = (((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)) >> 1) & (int32_t)0x000000FF; + t = (((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)) >> 1) & (int32_t)0x000000FF; + u = (((((int32_t)x) >> 24) - (((int32_t)y) >> 24)) >> 1) & (int32_t)0x000000FF; + + return ((unsigned long)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned subtraction with halved results. + \details This function enables you to perform four unsigned 8-bit integer subtractions, halving the results. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the halved subtraction of the first bytes from each operand, in the first byte of the return value.\n + the halved subtraction of the second bytes from each operand, in the second byte of the return value.\n + the halved subtraction of the third bytes from each operand, in the third byte of the return value.\n + the halved subtraction of the fourth bytes from each operand, in the fourth byte of the return value. + \remark + res[7:0] = (val1[7:0] - val2[7:0] ) >> 1 \n + res[15:8] = (val1[15:8] - val2[15:8] ) >> 1 \n + res[23:16] = (val1[23:16] - val2[23:16]) >> 1 \n + res[31:24] = (val1[31:24] - val2[31:24]) >> 1 + */ +__ALWAYS_STATIC_INLINE unsigned long __UHSUB8(unsigned long x, unsigned long y) +{ + int32_t r, s, t, u; + + r = ((((x << 24) >> 24) - ((y << 24) >> 24)) >> 1) & 0x000000FF; + s = ((((x << 16) >> 24) - ((y << 16) >> 24)) >> 1) & 0x000000FF; + t = ((((x << 8) >> 24) - ((y << 8) >> 24)) >> 1) & 0x000000FF; + u = ((((x) >> 24) - ((y) >> 24)) >> 1) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Dual 16-bit add and subtract with exchange. + \details This function enables you to exchange the halfwords of the one operand, + then add the high halfwords and subtract the low halfwords, + saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \param [in] x first operand for the subtraction in the low halfword, + and the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, + and the second operand for the addition in the low halfword. + \return the saturated subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the saturated addition of the high halfword in the first operand and the + low halfword in the second operand, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] - val2[31:16] \n + res[31:16] = val1[31:16] + val2[15:0] + */ +__ALWAYS_STATIC_INLINE unsigned long __QASX(unsigned long x, unsigned long y) +{ + int32_t r, s; + + r = __SSAT(((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((unsigned long)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturating addition and subtraction with exchange. + \details This function enables you to exchange the halfwords of the second operand and + perform one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, + saturating the results to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1. + \param [in] x first operand for the subtraction in the low halfword, + and the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, + and the second operand for the addition in the low halfword. + \return the saturated subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the saturated addition of the high halfword in the first operand and the + low halfword in the second operand, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1. + \remark + res[15:0] = val1[15:0] - val2[31:16] \n + res[31:16] = val1[31:16] + val2[15:0] + */ +__ALWAYS_STATIC_INLINE unsigned long __UQASX(unsigned long x, unsigned long y) +{ + int32_t r, s; + + r = __IUSAT((((x << 16) >> 16) - ((y) >> 16)), 16) & 0x0000FFFF; + s = __IUSAT((((x) >> 16) + ((y << 16) >> 16)), 16) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit addition and subtraction with exchange. + \details It enables you to exchange the halfwords of the second operand, add the high halfwords + and subtract the low halfwords. + \param [in] x first operand for the subtraction in the low halfword, + and the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, + and the second operand for the addition in the low halfword. + \return the subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the addition of the high halfword in the first operand and the + low halfword in the second operand, in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] - val2[31:16] \n + res[31:16] = val1[31:16] + val2[15:0] + */ +__ALWAYS_STATIC_INLINE unsigned long __SASX(unsigned long x, unsigned long y) +{ + int32_t r, s; + + r = ((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF; + s = ((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF; + + return ((unsigned long)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned addition and subtraction with exchange. + \details This function enables you to exchange the two halfwords of the second operand, + add the high halfwords and subtract the low halfwords. + \param [in] x first operand for the subtraction in the low halfword, + and the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, + and the second operand for the addition in the low halfword. + \return the subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the addition of the high halfword in the first operand and the + low halfword in the second operand, in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] - val2[31:16] \n + res[31:16] = val1[31:16] + val2[15:0] + */ +__ALWAYS_STATIC_INLINE unsigned long __UASX(unsigned long x, unsigned long y) +{ + int32_t r, s; + + r = (((x << 16) >> 16) - ((y) >> 16)) & 0x0000FFFF; + s = (((x) >> 16) + ((y << 16) >> 16)) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed addition and subtraction with halved results. + \details This function enables you to exchange the two halfwords of one operand, perform one + signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results. + \param [in] x first 16-bit operands. + \param [in] y second 16-bit operands. + \return the halved subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the halved addition of the low halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] - val2[31:16]) >> 1 \n + res[31:16] = (val1[31:16] + val2[15:0]) >> 1 + */ +__ALWAYS_STATIC_INLINE unsigned long __SHASX(unsigned long x, unsigned long y) +{ + int32_t r, s; + + r = (((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((unsigned long)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned addition and subtraction with halved results and exchange. + \details This function enables you to exchange the halfwords of the second operand, + add the high halfwords and subtract the low halfwords, halving the results. + \param [in] x first operand for the subtraction in the low halfword, and + the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, and + the second operand for the addition in the low halfword. + \return the halved subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the halved addition of the low halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] - val2[31:16]) >> 1 \n + res[31:16] = (val1[31:16] + val2[15:0]) >> 1 + */ +__ALWAYS_STATIC_INLINE unsigned long __UHASX(unsigned long x, unsigned long y) +{ + int32_t r, s; + + r = ((((x << 16) >> 16) - ((y) >> 16)) >> 1) & 0x0000FFFF; + s = ((((x) >> 16) + ((y << 16) >> 16)) >> 1) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit subtract and add with exchange. + \details This function enables you to exchange the halfwords of one operand, + then subtract the high halfwords and add the low halfwords, + saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \param [in] x first operand for the addition in the low halfword, + and the first operand for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, + and the second operand for the subtraction in the low halfword. + \return the saturated addition of the low halfword of the first operand and the high + halfword of the second operand, in the low halfword of the return value.\n + the saturated subtraction of the low halfword of the second operand from the + high halfword of the first operand, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] + val2[31:16] \n + res[31:16] = val1[31:16] - val2[15:0] + */ +__ALWAYS_STATIC_INLINE unsigned long __QSAX(unsigned long x, unsigned long y) +{ + int32_t r, s; + + r = __SSAT(((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((unsigned long)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturating subtraction and addition with exchange. + \details This function enables you to exchange the halfwords of the second operand and perform + one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating + the results to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1. + \param [in] x first operand for the addition in the low halfword, + and the first operand for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, + and the second operand for the subtraction in the low halfword. + \return the saturated addition of the low halfword of the first operand and the high + halfword of the second operand, in the low halfword of the return value.\n + the saturated subtraction of the low halfword of the second operand from the + high halfword of the first operand, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1. + \remark + res[15:0] = val1[15:0] + val2[31:16] \n + res[31:16] = val1[31:16] - val2[15:0] + */ +__ALWAYS_STATIC_INLINE unsigned long __UQSAX(unsigned long x, unsigned long y) +{ + int32_t r, s; + + r = __IUSAT((((x << 16) >> 16) + ((y) >> 16)), 16) & 0x0000FFFF; + s = __IUSAT((((x) >> 16) - ((y << 16) >> 16)), 16) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit unsigned subtract and add with exchange. + \details This function enables you to exchange the halfwords of the second operand, + subtract the high halfwords and add the low halfwords. + \param [in] x first operand for the addition in the low halfword, + and the first operand for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, + and the second operand for the subtraction in the low halfword. + \return the addition of the low halfword of the first operand and the high + halfword of the second operand, in the low halfword of the return value.\n + the subtraction of the low halfword of the second operand from the + high halfword of the first operand, in the high halfword of the return value.\n + \remark + res[15:0] = val1[15:0] + val2[31:16] \n + res[31:16] = val1[31:16] - val2[15:0] + */ +__ALWAYS_STATIC_INLINE unsigned long __USAX(unsigned long x, unsigned long y) +{ + int32_t r, s; + + r = (((x << 16) >> 16) + ((y) >> 16)) & 0x0000FFFF; + s = (((x) >> 16) - ((y << 16) >> 16)) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed subtraction and addition with exchange. + \details This function enables you to exchange the two halfwords of one operand and perform one + 16-bit integer subtraction and one 16-bit addition. + \param [in] x first operand for the addition in the low halfword, and the first operand + for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, and the second + operand for the subtraction in the low halfword. + \return the addition of the low halfword of the first operand and the high + halfword of the second operand, in the low halfword of the return value.\n + the subtraction of the low halfword of the second operand from the + high halfword of the first operand, in the high halfword of the return value.\n + \remark + res[15:0] = val1[15:0] + val2[31:16] \n + res[31:16] = val1[31:16] - val2[15:0] + */ +__ALWAYS_STATIC_INLINE unsigned long __SSAX(unsigned long x, unsigned long y) +{ + int32_t r, s; + + r = ((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF; + s = ((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF; + + return ((unsigned long)((s << 16) | (r))); +} + + +/** + \brief Dual 16-bit signed subtraction and addition with halved results. + \details This function enables you to exchange the two halfwords of one operand, perform one signed + 16-bit integer subtraction and one signed 16-bit addition, and halve the results. + \param [in] x first 16-bit operands. + \param [in] y second 16-bit operands. + \return the halved addition of the low halfword in the first operand and the + high halfword in the second operand, in the low halfword of the return value.\n + the halved subtraction of the low halfword in the second operand from the + high halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] + val2[31:16]) >> 1 \n + res[31:16] = (val1[31:16] - val2[15:0]) >> 1 + */ +__ALWAYS_STATIC_INLINE unsigned long __SHSAX(unsigned long x, unsigned long y) +{ + int32_t r, s; + + r = (((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((unsigned long)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned subtraction and addition with halved results and exchange. + \details This function enables you to exchange the halfwords of the second operand, + subtract the high halfwords and add the low halfwords, halving the results. + \param [in] x first operand for the addition in the low halfword, and + the first operand for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, and + the second operand for the subtraction in the low halfword. + \return the halved addition of the low halfword in the first operand and the + high halfword in the second operand, in the low halfword of the return value.\n + the halved subtraction of the low halfword in the second operand from the + high halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] + val2[31:16]) >> 1 \n + res[31:16] = (val1[31:16] - val2[15:0]) >> 1 + */ +__ALWAYS_STATIC_INLINE unsigned long __UHSAX(unsigned long x, unsigned long y) +{ + int32_t r, s; + + r = ((((x << 16) >> 16) + ((y) >> 16)) >> 1) & 0x0000FFFF; + s = ((((x) >> 16) - ((y << 16) >> 16)) >> 1) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed multiply with exchange returning difference. + \details This function enables you to perform two 16-bit signed multiplications, subtracting + one of the products from the other. The halfwords of the second operand are exchanged + before performing the arithmetic. This produces top * bottom and bottom * top multiplication. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \return the difference of the products of the two 16-bit signed multiplications. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[31:0] = p1 - p2 + */ +__ALWAYS_STATIC_INLINE unsigned long __SMUSDX(unsigned long x, unsigned long y) +{ + return ((unsigned long)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)))); +} + +/** + \brief Sum of dual 16-bit signed multiply with exchange. + \details This function enables you to perform two 16-bit signed multiplications with exchanged + halfwords of the second operand, adding the products together. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \return the sum of the products of the two 16-bit signed multiplications with exchanged halfwords of the second operand. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[31:0] = p1 + p2 + */ +__ALWAYS_STATIC_INLINE unsigned long __SMUADX(unsigned long x, unsigned long y) +{ + return ((unsigned long)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)))); +} + + +/** + \brief Saturating add. + \details This function enables you to obtain the saturating add of two integers. + \param [in] x first summand of the saturating add operation. + \param [in] y second summand of the saturating add operation. + \return the saturating addition of val1 and val2. + \remark + res[31:0] = SAT(val1 + SAT(val2)) + */ +__ALWAYS_STATIC_INLINE int32_t __QADD(int32_t x, int32_t y) +{ + int32_t result; + + if (y >= 0) { + if ((int32_t)((unsigned long)x + (unsigned long)y) >= x) { + result = x + y; + } else { + result = 0x7FFFFFFF; + } + } else { + if ((int32_t)((unsigned long)x + (unsigned long)y) < x) { + result = x + y; + } else { + result = 0x80000000; + } + } + + return result; +} + +/** + \brief Saturating subtract. + \details This function enables you to obtain the saturating add of two integers. + \param [in] x first summand of the saturating add operation. + \param [in] y second summand of the saturating add operation. + \return the saturating addition of val1 and val2. + \remark + res[31:0] = SAT(val1 - SAT(val2)) + */ +__ALWAYS_STATIC_INLINE int32_t __QSUB(int32_t x, int32_t y) +{ + int64_t tmp; + int32_t result; + + tmp = (int64_t)x - (int64_t)y; + + if (tmp > 0x7fffffff) { + tmp = 0x7fffffff; + } else if (tmp < (-2147483647 - 1)) { + tmp = -2147483647 - 1; + } + + result = tmp; + return result; +} + +/** + \brief Dual 16-bit signed multiply with single 32-bit accumulator. + \details This function enables you to perform two signed 16-bit multiplications, + adding both results to a 32-bit accumulate operand. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the product of each multiplication added to the accumulate value, as a 32-bit integer. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[31:0] = p1 + p2 + val3[31:0] + */ +__ALWAYS_STATIC_INLINE unsigned long __SMLAD(unsigned long x, unsigned long y, unsigned long sum) +{ + return ((unsigned long)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) + + (((int32_t)sum)))); +} + +/** + \brief Pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator. + \details This function enables you to perform two signed 16-bit multiplications with exchanged + halfwords of the second operand, adding both results to a 32-bit accumulate operand. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the product of each multiplication with exchanged halfwords of the second + operand added to the accumulate value, as a 32-bit integer. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[31:0] = p1 + p2 + val3[31:0] + */ +__ALWAYS_STATIC_INLINE unsigned long __SMLADX(unsigned long x, unsigned long y, unsigned long sum) +{ + return ((unsigned long)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) + + (((int32_t)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with exchange subtract with 32-bit accumulate. + \details This function enables you to perform two 16-bit signed multiplications, take the + difference of the products, subtracting the high halfword product from the low + halfword product, and add the difference to a 32-bit accumulate operand. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the difference of the product of each multiplication, added to the accumulate value. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[31:0] = p1 - p2 + val3[31:0] + */ +__ALWAYS_STATIC_INLINE unsigned long __SMLSD(unsigned long x, unsigned long y, unsigned long sum) +{ + return ((unsigned long)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) + + (((int32_t)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with exchange subtract with 32-bit accumulate. + \details This function enables you to exchange the halfwords in the second operand, then perform two 16-bit + signed multiplications. The difference of the products is added to a 32-bit accumulate operand. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the difference of the product of each multiplication, added to the accumulate value. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[31:0] = p1 - p2 + val3[31:0] + */ +__ALWAYS_STATIC_INLINE unsigned long __SMLSDX(unsigned long x, unsigned long y, unsigned long sum) +{ + return ((unsigned long)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) + + (((int32_t)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with single 64-bit accumulator. + \details This function enables you to perform two signed 16-bit multiplications, adding both results + to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. + This overflow is not detected if it occurs. Instead, the result wraps around modulo2^64. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the product of each multiplication added to the accumulate value. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + sum = p1 + p2 + val3[63:32][31:0] \n + res[63:32] = sum[63:32] \n + res[31:0] = sum[31:0] + */ +__ALWAYS_STATIC_INLINE uint64_t __SMLALD(unsigned long x, unsigned long y, uint64_t sum) +{ + return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) + + (((uint64_t)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with exchange with single 64-bit accumulator. + \details This function enables you to exchange the halfwords of the second operand, and perform two + signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow + is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. + Instead, the result wraps around modulo2^64. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the product of each multiplication added to the accumulate value. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + sum = p1 + p2 + val3[63:32][31:0] \n + res[63:32] = sum[63:32] \n + res[31:0] = sum[31:0] + */ +__ALWAYS_STATIC_INLINE uint64_t __SMLALDX(unsigned long x, unsigned long y, uint64_t sum) +{ + return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) + + (((uint64_t)sum)))); +} + +/** + \brief dual 16-bit signed multiply subtract with 64-bit accumulate. + \details This function It enables you to perform two 16-bit signed multiplications, take the difference + of the products, subtracting the high halfword product from the low halfword product, and add the + difference to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the + subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not + detected. Instead, the result wraps round to modulo2^64. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the difference of the product of each multiplication, added to the accumulate value. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[63:32][31:0] = p1 - p2 + val3[63:32][31:0] + */ +__ALWAYS_STATIC_INLINE uint64_t __SMLSLD(unsigned long x, unsigned long y, uint64_t sum) +{ + return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) + + (((uint64_t)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with exchange subtract with 64-bit accumulate. + \details This function enables you to exchange the halfwords of the second operand, perform two 16-bit multiplications, + adding the difference of the products to a 64-bit accumulate operand. Overflow cannot occur during the + multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow + is not detected. Instead, the result wraps round to modulo2^64. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the difference of the product of each multiplication, added to the accumulate value. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[63:32][31:0] = p1 - p2 + val3[63:32][31:0] + */ +__ALWAYS_STATIC_INLINE uint64_t __SMLSLDX(unsigned long x, unsigned long y, uint64_t sum) +{ + return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) + + (((uint64_t)sum)))); +} + +/** + \brief 32-bit signed multiply with 32-bit truncated accumulator. + \details This function enables you to perform a signed 32-bit multiplications, adding the most + significant 32 bits of the 64-bit result to a 32-bit accumulate operand. + \param [in] x first operand for multiplication. + \param [in] y second operand for multiplication. + \param [in] sum accumulate value. + \return the product of multiplication (most significant 32 bits) is added to the accumulate value, as a 32-bit integer. + \remark + p = val1 * val2 \n + res[31:0] = p[63:32] + val3[31:0] + */ +__ALWAYS_STATIC_INLINE unsigned long __SMMLA(int32_t x, int32_t y, int32_t sum) +{ + return (unsigned long)((int32_t)((int64_t)((int64_t)x * (int64_t)y) >> 32) + sum); +} + +/** + \brief Sum of dual 16-bit signed multiply. + \details This function enables you to perform two 16-bit signed multiplications, adding the products together. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \return the sum of the products of the two 16-bit signed multiplications. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[31:0] = p1 + p2 + */ +__ALWAYS_STATIC_INLINE unsigned long __SMUAD(unsigned long x, unsigned long y) +{ + return ((unsigned long)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)))); +} + +/** + \brief Dual 16-bit signed multiply returning difference. + \details This function enables you to perform two 16-bit signed multiplications, taking the difference + of the products by subtracting the high halfword product from the low halfword product. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \return the difference of the products of the two 16-bit signed multiplications. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[31:0] = p1 - p2 + */ +__ALWAYS_STATIC_INLINE unsigned long __SMUSD(unsigned long x, unsigned long y) +{ + return ((unsigned long)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)))); +} + +/** + \brief Dual extracted 8-bit to 16-bit signed addition. + \details This function enables you to extract two 8-bit values from the second operand (at bit positions + [7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the first operand. + \param [in] x values added to the sign-extended to 16-bit values. + \param [in] y two 8-bit values to be extracted and sign-extended. + \return the addition of val1 and val2, where the 8-bit values in val2[7:0] and + val2[23:16] have been extracted and sign-extended prior to the addition. + \remark + res[15:0] = val1[15:0] + SignExtended(val2[7:0]) \n + res[31:16] = val1[31:16] + SignExtended(val2[23:16]) + */ +__ALWAYS_STATIC_INLINE unsigned long __SXTAB16(unsigned long x, unsigned long y) +{ + return ((unsigned long)((((((int32_t)y << 24) >> 24) + (((int32_t)x << 16) >> 16)) & (int32_t)0x0000FFFF) | + (((((int32_t)y << 8) >> 8) + (((int32_t)x >> 16) << 16)) & (int32_t)0xFFFF0000))); +} + +/** + \brief Extracted 16-bit to 32-bit unsigned addition. + \details This function enables you to extract two 8-bit values from one operand, zero-extend + them to 16 bits each, and add the results to two 16-bit values from another operand. + \param [in] x values added to the zero-extended to 16-bit values. + \param [in] y two 8-bit values to be extracted and zero-extended. + \return the addition of val1 and val2, where the 8-bit values in val2[7:0] and + val2[23:16] have been extracted and zero-extended prior to the addition. + \remark + res[15:0] = ZeroExt(val2[7:0] to 16 bits) + val1[15:0] \n + res[31:16] = ZeroExt(val2[31:16] to 16 bits) + val1[31:16] + */ +__ALWAYS_STATIC_INLINE unsigned long __UXTAB16(unsigned long x, unsigned long y) +{ + return ((unsigned long)(((((y << 24) >> 24) + ((x << 16) >> 16)) & 0x0000FFFF) | + ((((y << 8) >> 8) + ((x >> 16) << 16)) & 0xFFFF0000))); +} + +/** + \brief Dual extract 8-bits and sign extend each to 16-bits. + \details This function enables you to extract two 8-bit values from an operand and sign-extend them to 16 bits each. + \param [in] x two 8-bit values in val[7:0] and val[23:16] to be sign-extended. + \return the 8-bit values sign-extended to 16-bit values.\n + sign-extended value of val[7:0] in the low halfword of the return value.\n + sign-extended value of val[23:16] in the high halfword of the return value. + \remark + res[15:0] = SignExtended(val[7:0]) \n + res[31:16] = SignExtended(val[23:16]) + */ +__ALWAYS_STATIC_INLINE unsigned long __SXTB16(unsigned long x) +{ + return ((unsigned long)(((((int32_t)x << 24) >> 24) & (int32_t)0x0000FFFF) | + ((((int32_t)x << 8) >> 8) & (int32_t)0xFFFF0000))); +} + +/** + \brief Dual extract 8-bits and zero-extend to 16-bits. + \details This function enables you to extract two 8-bit values from an operand and zero-extend them to 16 bits each. + \param [in] x two 8-bit values in val[7:0] and val[23:16] to be zero-extended. + \return the 8-bit values sign-extended to 16-bit values.\n + sign-extended value of val[7:0] in the low halfword of the return value.\n + sign-extended value of val[23:16] in the high halfword of the return value. + \remark + res[15:0] = SignExtended(val[7:0]) \n + res[31:16] = SignExtended(val[23:16]) + */ +__ALWAYS_STATIC_INLINE unsigned long __UXTB16(unsigned long x) +{ + return ((unsigned long)((((x << 24) >> 24) & 0x0000FFFF) | + (((x << 8) >> 8) & 0xFFFF0000))); +} + +#endif /* _CSI_RV32_GCC_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/csi_rv64_gcc.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/csi_rv64_gcc.h new file mode 100644 index 00000000..9878668e --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/csi_rv64_gcc.h @@ -0,0 +1,4383 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +/****************************************************************************** + * @file csi_rv64_gcc.h + * @brief CSI Header File for GCC. + * @version V1.0 + * @date 01. Sep 2018 + ******************************************************************************/ + +#ifndef _CSI_RV64_GCC_H_ +#define _CSI_RV64_GCC_H_ + +#include + +#if CONFIG_CPU_XUANTIE_C907 || CONFIG_CPU_XUANTIE_C907FD || CONFIG_CPU_XUANTIE_C907FDV || CONFIG_CPU_XUANTIE_C907FDVM \ + || CONFIG_CPU_XUANTIE_C907_RV32 || CONFIG_CPU_XUANTIE_C907FD_RV32 || CONFIG_CPU_XUANTIE_C907FDV_RV32 || CONFIG_CPU_XUANTIE_C907FDVM_RV32 \ + || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \ + || CONFIG_CPU_XUANTIE_C908X || CONFIG_CPU_XUANTIE_C908X_CP || CONFIG_CPU_XUANTIE_C908X_CP_XT \ + || CONFIG_CPU_XUANTIE_C910V2 || CONFIG_CPU_XUANTIE_C920V2 \ + || CONFIG_CPU_XUANTIE_C910V3 || CONFIG_CPU_XUANTIE_C920V3 \ + || CONFIG_CPU_XUANTIE_C910V3_CP || CONFIG_CPU_XUANTIE_C920V3_CP \ + || CONFIG_CPU_XUANTIE_C910V3_CP_XT || CONFIG_CPU_XUANTIE_C920V3_CP_XT \ + || CONFIG_CPU_XUANTIE_R908 || CONFIG_CPU_XUANTIE_R908FD || CONFIG_CPU_XUANTIE_R908FDV \ + || CONFIG_CPU_XUANTIE_R908_CP || CONFIG_CPU_XUANTIE_R908FD_CP || CONFIG_CPU_XUANTIE_R908FDV_CP \ + || CONFIG_CPU_XUANTIE_R908_CP_XT || CONFIG_CPU_XUANTIE_R908FD_CP_XT || CONFIG_CPU_XUANTIE_R908FDV_CP_XT +#define CBO_INSN_SUPPORT 1 +#endif + +#if CONFIG_INTC_CLIC_PLIC +#ifndef CONFIG_PLIC_IRQ_OFFSET +#define PLIC_IRQ_OFFSET 255U +#else +#define PLIC_IRQ_OFFSET CONFIG_PLIC_IRQ_OFFSET +#endif +#endif /* CONFIG_INTC_CLIC_PLIC */ + +/* ########################### Core Function Access ########################### */ +/** \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_RegAccFunctions CSI Core Register Access Functions + @{ + */ +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by setting the IE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __enable_irq(void) +{ +#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE + __ASM volatile("csrs sstatus, 2"); + __ASM volatile("li a0, 0x222"); + __ASM volatile("csrs sie, a0"); +#else + __ASM volatile("csrs mstatus, 8"); + __ASM volatile("li a0, 0x888"); + __ASM volatile("csrs mie, a0"); +#endif +} + +/** + \brief Enable supervisor IRQ Interrupts + \details Enables IRQ interrupts by setting the IE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __enable_supervisor_irq(void) +{ + __ASM volatile("csrs sstatus, 2"); + __ASM volatile("li a0, 0x222"); + __ASM volatile("csrs sie, a0"); +} + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by clearing the IE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __disable_irq(void) +{ +#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE + __ASM volatile("csrc sstatus, 2"); +#else + __ASM volatile("csrc mstatus, 8"); +#endif +} + +/** + \brief Disable supervisor IRQ Interrupts + \details Disables supervisor IRQ interrupts by clearing the IE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __disable_supervisor_irq(void) +{ + __ASM volatile("csrc sstatus, 2"); +} + +/** + \brief Enable CoreTimer(within clint) Interrupts + */ +__ALWAYS_STATIC_INLINE void __enable_coret_irq(void) +{ +#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE + __ASM volatile("li a0, 0x20"); + __ASM volatile("csrs sie, a0"); +#else + __ASM volatile("li a0, 0x80"); + __ASM volatile("csrs mie, a0"); +#endif +} + +/** + \brief Disable CoreTimer(within clint) Interrupts + */ +__ALWAYS_STATIC_INLINE void __disable_coret_irq(void) +{ +#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE + __ASM volatile("li a0, 0x20"); + __ASM volatile("csrc sie, a0"); +#else + __ASM volatile("li a0, 0x80"); + __ASM volatile("csrc mie, a0"); +#endif +} + +/** + \brief Get MXSTATUS + \details Returns the content of the MXSTATUS Register. + \return MXSTATUS Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MXSTATUS(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mxstatus" : "=r"(result)); + return (result); +} + +/** + \brief Set MXSTATUS + \details Writes the given value to the MXSTATUS Register. + \param [in] mxstatus MXSTATUS Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MXSTATUS(unsigned long mxstatus) +{ + __ASM volatile("csrw mxstatus, %0" : : "r"(mxstatus)); +} + +/** + \brief Get SXSTATUS + \details Returns the content of the SXSTATUS Register. + \return SXSTATUS Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_SXSTATUS(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, sxstatus" : "=r"(result)); + return (result); +} + +#if __riscv_xlen == 32 +/** + \brief Get MENVCFGH + \details Returns the content of the MENVCFGH Register. + \return MENVCFGH Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MENVCFGH(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, menvcfgh" : "=r"(result)); + return (result); +} + +/** + \brief Set MENVCFGH + \details Writes the given value to the MENVCFGH Register. + \param [in] menvcfgh MENVCFGH Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MENVCFGH(unsigned long menvcfgh) +{ + __ASM volatile("csrw menvcfgh, %0" : : "r"(menvcfgh)); +} +#endif + +/** + \brief Get MENVCFG + \details Returns the content of the MENVCFG Register. + \return MENVCFG Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MENVCFG(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, menvcfg" : "=r"(result)); + return (result); +} + +/** + \brief Set MENVCFG + \details Writes the given value to the MENVCFG Register. + \param [in] menvcfg MENVCFG Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MENVCFG(unsigned long menvcfg) +{ + __ASM volatile("csrw menvcfg, %0" : : "r"(menvcfg)); +} + +/** + \brief Get CPU WORK MODE + \details Returns CPU WORK MODE. + \return CPU WORK MODE + */ +__ALWAYS_STATIC_INLINE unsigned long __get_CPU_WORK_MODE(void) +{ + unsigned long result; + __ASM volatile("csrr %0, sxstatus" : "=r"(result)); + return ((result >> 30U) & 0x3U); +} + +/** + \brief Set MEPC + \details Writes the given value to the MEPC Register. + \param [in] mepc MEPC Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MEPC(unsigned long mepc) +{ + __ASM volatile("csrw mepc, %0" : : "r"(mepc)); +} + +/** + \brief Get MEPC + \details Returns the content of the MEPC Register. + \return MEPC Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MEPC(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mepc" : "=r"(result)); + return (result); +} + +/** + \brief Set SEPC + \details Writes the given value to the SEPC Register. + \param [in] sepc SEPC Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_SEPC(unsigned long sepc) +{ + __ASM volatile("csrw sepc, %0" : : "r"(sepc)); +} + +/** + \brief Get SEPC + \details Returns the content of the SEPC Register. + \return SEPC Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_SEPC(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, sepc" : "=r"(result)); + return (result); +} + + +/** + \brief Get MSTATUS + \details Returns the content of the MSTATUS Register. + \return MSTATUS Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MSTATUS(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mstatus" : "=r"(result)); + return (result); +} + +/** + \brief Set MSTATUS + \details Writes the given value to the MSTATUS Register. + \param [in] mstatus MSTATUS Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MSTATUS(unsigned long mstatus) +{ + __ASM volatile("csrw mstatus, %0" : : "r"(mstatus)); +} + +/** + \brief Get MCOR + \details Returns the content of the MCOR Register. + \return MCOR Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MCOR(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mcor" : "=r"(result)); + return (result); +} + +/** + \brief Set MCOR + \details Writes the given value to the MCOR Register. + \param [in] mstatus MCOR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MCOR(unsigned long mcor) +{ + __ASM volatile("csrw mcor, %0" : : "r"(mcor)); +} + +/** + \brief Get MHCR + \details Returns the content of the MHCR Register. + \return MHCR Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MHCR(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mhcr" : "=r"(result)); + return (result); +} + +/** + \brief Set MHCR + \details Writes the given value to the MHCR Register. + \param [in] mstatus MHCR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MHCR(unsigned long mhcr) +{ + __ASM volatile("csrw mhcr, %0" : : "r"(mhcr)); +} + +/** + \brief Get MHINT + \details Returns the content of the MHINT Register. + \return MHINT Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MHINT(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mhint" : "=r"(result)); + return (result); +} + +/** + \brief Set MHINT + \details Writes the given value to the MHINT Register. + \param [in] mstatus MHINT Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MHINT(unsigned long mhint) +{ + __ASM volatile("csrw mhint, %0" : : "r"(mhint)); +} + +/** + \brief Get MCCR2 + \details Returns the content of the MCCR2 Register. + \return MCCR2 Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MCCR2(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mccr2" : "=r"(result)); + return (result); +} + +/** + \brief Set MCCR2 + \details Writes the given value to the MCCR2 Register. + \param [in] mstatus MCCR2 Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MCCR2(unsigned long mccr2) +{ + __ASM volatile("csrw mccr2, %0" : : "r"(mccr2)); +} + +/** + \brief Get MISA Register + \details Returns the content of the MISA Register. + \return MISA Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MISA(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, misa" : "=r"(result)); + return (result); +} + +/** + \brief Set MISA + \details Writes the given value to the MISA Register. + \param [in] misa MISA Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MISA(unsigned long misa) +{ + __ASM volatile("csrw misa, %0" : : "r"(misa)); +} + +/** + \brief Get MIE Register + \details Returns the content of the MIE Register. + \return MIE Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MIE(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mie" : "=r"(result)); + return (result); +} + +/** + \brief Set MIE + \details Writes the given value to the MIE Register. + \param [in] mie MIE Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MIE(unsigned long mie) +{ + __ASM volatile("csrw mie, %0" : : "r"(mie)); +} + +/** + \brief Get MTVEC Register + \details Returns the content of the MTVEC Register. + \return MTVEC Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MTVEC(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mtvec" : "=r"(result)); + return (result); +} + +/** + \brief Set MTVEC + \details Writes the given value to the MTVEC Register. + \param [in] mtvec MTVEC Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MTVEC(unsigned long mtvec) +{ + __ASM volatile("csrw mtvec, %0" : : "r"(mtvec)); +} + +/** + \brief Set MTVT + \details Writes the given value to the MTVT Register. + \param [in] mtvt MTVT Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MTVT(unsigned long mtvt) +{ + __ASM volatile("csrw mtvt, %0" : : "r"(mtvt)); +} + +/** + \brief Get MTVT Register + \details Returns the content of the MTVT Register. + \return MTVT Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MTVT(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mtvt" : "=r"(result)); + return (result); +} + +/** + \brief Get MTIME + \details Returns the content of the MTIME Register. + \return MTIME Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MTIME(void) +{ + unsigned long result; + + __ASM volatile("rdtime %0" : "=r"(result)); + //__ASM volatile("csrr %0, 0xc01" : "=r"(result)); + return (result); +} + +/** + \brief Get MTIMEH + \details Returns the content of the MTIME Register. + \return MTIME Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MTIMEH(void) +{ + unsigned long result; + __ASM volatile("rdtimeh %0" : "=r"(result)); + return (result); +} + +/** + \brief Get SP + \details Returns the content of the SP Register. + \return SP Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_SP(void) +{ + unsigned long result; + + __ASM volatile("mv %0, sp" : "=r"(result)); + return (result); +} + +/** + \brief Set SP + \details Writes the given value to the SP Register. + \param [in] sp SP Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_SP(unsigned long sp) +{ + __ASM volatile("mv sp, %0" : : "r"(sp): "sp"); +} + +/** + \brief Get MSCRATCH Register + \details Returns the content of the MSCRATCH Register. + \return MSCRATCH Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MSCRATCH(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mscratch" : "=r"(result)); + return (result); +} + +/** + \brief Set MSCRATCH + \details Writes the given value to the MSCRATCH Register. + \param [in] mscratch MSCRATCH Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MSCRATCH(unsigned long mscratch) +{ + __ASM volatile("csrw mscratch, %0" : : "r"(mscratch)); +} + +/** + \brief Get MCAUSE Register + \details Returns the content of the MCAUSE Register. + \return MCAUSE Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MCAUSE(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mcause" : "=r"(result)); + return (result); +} + +/** + \brief Get SCAUSE Register + \details Returns the content of the SCAUSE Register. + \return SCAUSE Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_SCAUSE(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, scause" : "=r"(result)); + return (result); +} + +/** + \brief Get MNXTI Register + \details Returns the content of the MNXTI Register. + \return MNXTI Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MNXTI(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mnxti" : "=r"(result)); + return (result); +} + +/** + \brief Set MNXTI + \details Writes the given value to the MNXTI Register. + \param [in] mnxti MNXTI Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MNXTI(unsigned long mnxti) +{ + __ASM volatile("csrw mnxti, %0" : : "r"(mnxti)); +} + +/** + \brief Get MINTSTATUS Register + \details Returns the content of the MINTSTATUS Register. + \return MINTSTATUS Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MINTSTATUS(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mintstatus" : "=r"(result)); + return (result); +} + +/** + \brief Get MTVAL Register + \details Returns the content of the MTVAL Register. + \return MTVAL Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MTVAL(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mtval" : "=r"(result)); + return (result); +} + +/** + \brief Get MIP Register + \details Returns the content of the MIP Register. + \return MIP Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MIP(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mip" : "=r"(result)); + return (result); +} + +/** + \brief Set MIP + \details Writes the given value to the MIP Register. + \param [in] mip MIP Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MIP(unsigned long mip) +{ + __ASM volatile("csrw mip, %0" : : "r"(mip)); +} + +/** + \brief Get MCYCLEL Register + \details Returns the content of the MCYCLEL Register. + \return MCYCLE Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MCYCLE(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mcycle" : "=r"(result)); + return (result); +} + +/** + \brief Set MCYCLE + \details Write MCYCLE Register + \param [in] value MCYCLE Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MCYCLE(unsigned long value) +{ + __ASM volatile("csrw mcycle, %0" : : "r"(value)); +} + +/** + \brief Get MCYCLEH Register + \details Returns the content of the MCYCLEH Register. + \return MCYCLEH Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MCYCLEH(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mcycleh" : "=r"(result)); + return (result); +} + +/** + \brief Set MCYCLEH + \details Write MCYCLEH Register + \param [in] value MCYCLEH Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MCYCLEH(unsigned long value) +{ + __ASM volatile("csrw mcycleh, %0" : : "r"(value)); +} + +/** + \brief Get MINSTRET Register + \details Returns the content of the MINSTRET Register. + \return MINSTRET Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MINSTRET(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, minstret" : "=r"(result)); + return (result); +} + +/** + \brief Set MINSTRET + \details Write MINSTRET Register + \param [in] value MINSTRET Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MINSTRET(unsigned long value) +{ + __ASM volatile("csrw minstret, %0" : : "r"(value)); +} + +/** + \brief Get MINSTRETH Register + \details Returns the content of the MINSTRETH Register. + \return MINSTRETH Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MINSTRETH(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, minstreth" : "=r"(result)); + return (result); +} + +/** + \brief Set MINSTRETH + \details Write MINSTRETH Register + \param [in] value MINSTRETH Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MINSTRETH(unsigned long value) +{ + __ASM volatile("csrw minstreth, %0" : : "r"(value)); +} + +/** + \brief Get MVENDORID Register + \details Returns the content of the MVENDROID Register. + \return MVENDORID Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MVENDORID(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mvendorid" : "=r"(result)); + return (result); +} + +/** + \brief Get MARCHID Register + \details Returns the content of the MARCHID Register. + \return MARCHID Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MARCHID(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, marchid" : "=r"(result)); + return (result); +} + +/** + \brief Get MIMPID Register + \details Returns the content of the MIMPID Register. + \return MIMPID Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MIMPID(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mimpid" : "=r"(result)); + return (result); +} + +/** + \brief Get MHARTID Register + \details Returns the content of the MHARTID Register. + \return MHARTID Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MHARTID(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, mhartid" : "=r"(result)); + return (result); +} + +/** + \brief Get PMPCFGx Register + \details Returns the content of the PMPCFGx Register. + \return PMPCFGx Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_PMPCFG0(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpcfg0" : "=r"(result)); + return (result); +} + +#if __riscv_xlen == 32 +__ALWAYS_STATIC_INLINE unsigned long __get_PMPCFG1(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpcfg1" : "=r"(result)); + return (result); +} +#endif + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPCFG2(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpcfg2" : "=r"(result)); + return (result); +} + +#if __riscv_xlen == 32 +__ALWAYS_STATIC_INLINE unsigned long __get_PMPCFG3(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpcfg3" : "=r"(result)); + return (result); +} +#endif + +/** + \brief Get PMPxCFG Register by index + \details Returns the content of the PMPxCFG Register. + \param [in] idx PMP region index + \return PMPxCFG Register value + */ +__STATIC_INLINE uint8_t __get_PMPxCFG(unsigned long idx) +{ + unsigned long pmpcfgx = 0; + +#if __riscv_xlen == 32 + if (idx < 4) { + pmpcfgx = __get_PMPCFG0(); + } else if (idx >= 4 && idx < 8) { + idx -= 4; + pmpcfgx = __get_PMPCFG1(); + } else if (idx >= 8 && idx < 12) { + idx -= 8; + pmpcfgx = __get_PMPCFG2(); + } else if (idx >= 12 && idx < 16) { + idx -= 12; + pmpcfgx = __get_PMPCFG3(); + } else { + return 0; + } +#else + if (idx < 8) { + pmpcfgx = __get_PMPCFG0(); + } else if (idx >= 8 && idx < 16) { + idx -= 8; + pmpcfgx = __get_PMPCFG2(); + } else { + return 0; + } +#endif + + return (uint8_t)((pmpcfgx & (0xFF << (idx << 3))) >> (idx << 3)); +} + +/** + \brief Set PMPCFGx + \details Writes the given value to the PMPCFGx Register. + \param [in] pmpcfg PMPCFGx Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_PMPCFG0(unsigned long pmpcfg) +{ + __ASM volatile("csrw pmpcfg0, %0" : : "r"(pmpcfg)); +} + +#if __riscv_xlen == 32 +__ALWAYS_STATIC_INLINE void __set_PMPCFG1(unsigned long pmpcfg) +{ + __ASM volatile("csrw pmpcfg1, %0" : : "r"(pmpcfg)); +} +#endif + +__ALWAYS_STATIC_INLINE void __set_PMPCFG2(unsigned long pmpcfg) +{ + __ASM volatile("csrw pmpcfg2, %0" : : "r"(pmpcfg)); +} + +#if __riscv_xlen == 32 +__ALWAYS_STATIC_INLINE void __set_PMPCFG3(unsigned long pmpcfg) +{ + __ASM volatile("csrw pmpcfg3, %0" : : "r"(pmpcfg)); +} +#endif + +/** + \brief Set PMPxCFG by index + \details Writes the given value to the PMPxCFG Register. + \param [in] idx PMPx region index + \param [in] pmpxcfg PMPxCFG Register value to set + */ +__STATIC_INLINE void __set_PMPxCFG(unsigned long idx, uint8_t pmpxcfg) +{ + unsigned long pmpcfgx = 0; + +#if __riscv_xlen == 32 + if (idx < 4) { + pmpcfgx = __get_PMPCFG0(); + pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | ((unsigned long)(pmpxcfg) << (idx << 3)); + __set_PMPCFG0(pmpcfgx); + } else if (idx >= 4 && idx < 8) { + idx -= 4; + pmpcfgx = __get_PMPCFG1(); + pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | ((unsigned long)(pmpxcfg) << (idx << 3)); + __set_PMPCFG1(pmpcfgx); + } else if (idx >= 8 && idx < 12) { + idx -= 8; + pmpcfgx = __get_PMPCFG2(); + pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | ((unsigned long)(pmpxcfg) << (idx << 3)); + __set_PMPCFG2(pmpcfgx); + } else if (idx >= 12 && idx < 16) { + idx -= 12; + pmpcfgx = __get_PMPCFG3(); + pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | ((unsigned long)(pmpxcfg) << (idx << 3)); + __set_PMPCFG3(pmpcfgx); + } else { + return; + } +#else + if (idx < 8) { + pmpcfgx = __get_PMPCFG0(); + pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | ((unsigned long)(pmpxcfg) << (idx << 3)); + __set_PMPCFG0(pmpcfgx); + } else if (idx >= 8 && idx < 16) { + idx -= 8; + pmpcfgx = __get_PMPCFG2(); + pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | ((unsigned long)(pmpxcfg) << (idx << 3)); + __set_PMPCFG2(pmpcfgx); + } else { + return; + } +#endif +} + +/** + \brief Get PMPADDRx Register + \details Returns the content of the PMPADDRx Register. + \return PMPADDRx Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR0(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr0" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR1(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr1" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR2(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr2" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR3(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr3" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR4(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr4" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR5(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr5" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR6(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr6" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR7(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr7" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR8(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr8" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR9(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr9" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR10(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr10" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR11(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr11" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR12(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr12" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR13(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr13" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR14(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr14" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR15(void) +{ + unsigned long result; + + __ASM volatile("csrr %0, pmpaddr15" : "=r"(result)); + return (result); +} + +/** + \brief Get PMPADDRx Register by index + \details Returns the content of the PMPADDRx Register. + \param [in] idx PMP region index + \return PMPADDRx Register value + */ +__STATIC_INLINE unsigned long __get_PMPADDRx(unsigned long idx) +{ + switch (idx) { + case 0: + return __get_PMPADDR0(); + + case 1: + return __get_PMPADDR1(); + + case 2: + return __get_PMPADDR2(); + + case 3: + return __get_PMPADDR3(); + + case 4: + return __get_PMPADDR4(); + + case 5: + return __get_PMPADDR5(); + + case 6: + return __get_PMPADDR6(); + + case 7: + return __get_PMPADDR7(); + + case 8: + return __get_PMPADDR8(); + + case 9: + return __get_PMPADDR9(); + + case 10: + return __get_PMPADDR10(); + + case 11: + return __get_PMPADDR11(); + + case 12: + return __get_PMPADDR12(); + + case 13: + return __get_PMPADDR13(); + + case 14: + return __get_PMPADDR14(); + + case 15: + return __get_PMPADDR15(); + + default: + return 0; + } +} + +/** + \brief Set PMPADDRx + \details Writes the given value to the PMPADDRx Register. + \param [in] pmpaddr PMPADDRx Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_PMPADDR0(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr0, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR1(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr1, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR2(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr2, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR3(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr3, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR4(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr4, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR5(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr5, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR6(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr6, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR7(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr7, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR8(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr8, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR9(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr9, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR10(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr10, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR11(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr11, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR12(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr12, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR13(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr13, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR14(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr14, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR15(unsigned long pmpaddr) +{ + __ASM volatile("csrw pmpaddr15, %0" : : "r"(pmpaddr)); +} + +/** + \brief Set PMPADDRx by index + \details Writes the given value to the PMPADDRx Register. + \param [in] idx PMP region index + \param [in] pmpaddr PMPADDRx Register value to set + */ +__STATIC_INLINE void __set_PMPADDRx(unsigned long idx, unsigned long pmpaddr) +{ + switch (idx) { + case 0: + __set_PMPADDR0(pmpaddr); + break; + + case 1: + __set_PMPADDR1(pmpaddr); + break; + + case 2: + __set_PMPADDR2(pmpaddr); + break; + + case 3: + __set_PMPADDR3(pmpaddr); + break; + + case 4: + __set_PMPADDR4(pmpaddr); + break; + + case 5: + __set_PMPADDR5(pmpaddr); + break; + + case 6: + __set_PMPADDR6(pmpaddr); + break; + + case 7: + __set_PMPADDR7(pmpaddr); + break; + + case 8: + __set_PMPADDR8(pmpaddr); + break; + + case 9: + __set_PMPADDR9(pmpaddr); + break; + + case 10: + __set_PMPADDR10(pmpaddr); + break; + + case 11: + __set_PMPADDR11(pmpaddr); + break; + + case 12: + __set_PMPADDR12(pmpaddr); + break; + + case 13: + __set_PMPADDR13(pmpaddr); + break; + + case 14: + __set_PMPADDR14(pmpaddr); + break; + + case 15: + __set_PMPADDR15(pmpaddr); + break; + + default: + return; + } +} + +/** + \brief Get MCOUNTEREN + \details Returns the content of the MCOUNTEREN Register. + \return MCOUNTEREN Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MCOUNTEREN(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mcounteren" : "=r"(result)); + return (result); +} + +/** + \brief Set MCOUNTEREN + \details Writes the given value to the MCOUNTEREN Register. + \param [in] mcounteren MCOUNTEREN Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MCOUNTEREN(uint32_t mcounteren) +{ + __ASM volatile("csrw mcounteren, %0" : : "r"(mcounteren)); +} + +/** + \brief Get MCOUNTERWEN + \details Returns the content of the MCOUNTERWEN Register. + \return MCOUNTERWEN Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MCOUNTERWEN(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mcounterwen" : "=r"(result)); + return (result); +} + +/** + \brief Set MCOUNTERWEN + \details Writes the given value to the MCOUNTERWEN Register. + \param [in] mcounterwen MCOUNTERWEN Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MCOUNTERWEN(uint32_t mcounterwen) +{ + __ASM volatile("csrw mcounterwen, %0" : : "r"(mcounterwen)); +} +/** + \brief Set MEDELEG Register + \details Writes the given value to the MEDELEG Register. + */ +__ALWAYS_STATIC_INLINE void __set_MEDELEG(unsigned long x) +{ + __ASM volatile("csrw medeleg, %0"::"r"(x)); +} + +/** + \brief Set MEDELEG Register + \details Writes the given value to the MEDELEG Register. + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MEDELEG(void) +{ + unsigned long x; + __ASM volatile("csrr %0, medeleg":"=r"(x)); + return x; +} + +/** + \brief Set MIDELEG Register + \details Writes the given value to the MIDELEG Register. + */ +__ALWAYS_STATIC_INLINE void __set_MIDELEG(unsigned long x) +{ + __ASM volatile("csrw mideleg, %0"::"r"(x)); +} + +/** + \brief Get MIDELEG Register + \details Returns the content of the MIDELEG Register. + \return MIDELEG Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MIDELEG(void) +{ + unsigned long x; + __ASM volatile("csrr %0, mideleg":"=r"(x)); + return x; +} + +/** + \brief Set SSTATUS Register + \details Writes the given value to the SSTATUS Register. + */ +__ALWAYS_STATIC_INLINE void __set_SSTATUS(unsigned long x) +{ + __ASM volatile("csrw sstatus, %0"::"r"(x)); +} + +/** + \brief Get SSTATUS Register + \details Returns the content of the SSTATUS Register. + \return SSTATUS Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_SSTATUS(void) +{ + unsigned long x; + __ASM volatile("csrr %0, sstatus":"=r"(x)); + return x; +} + +/** + \brief Set SXSTATUS Register + \details Writes the given value to the SXSTATUS Register. + */ +__ALWAYS_STATIC_INLINE void __set_SXSTATUS(unsigned long x) +{ + __ASM volatile("csrw sxstatus, %0"::"r"(x)); +} + +/** + \brief Get SXSTATUS Register + \details Returns the content of the SXSTATUS Register. + \return SXSTATUS Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get__SXSTATUS(void) +{ + unsigned long x; + __ASM volatile("csrr %0, sxstatus":"=r"(x)); + return x; +} + +/** + \brief Set SIE Register + \details Writes the given value to the SIE Register. + */ +__ALWAYS_STATIC_INLINE void __set_SIE(unsigned long x) +{ + __ASM volatile("csrw sie, %0"::"r"(x)); +} + +/** + \brief Get SIE Register + \details Returns the content of the SIE Register. + \return SIE Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_SIE(void) +{ + unsigned long x; + __ASM volatile("csrr %0, sie":"=r"(x)); + return x; +} + +/** + \brief Set STVAC Register + \details Writes the given value to the STVEC Register. + */ +__ALWAYS_STATIC_INLINE void __set_STVEC(unsigned long x) +{ + __ASM volatile("csrw stvec, %0"::"r"(x)); +} + +/** + \brief Get STVAC Register + \details Returns the content of the STVAC Register. + \return STVAC Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_STVEC(void) +{ + unsigned long x; + __ASM volatile("csrr %0, stvec":"=r"(x)); + return x; +} + +/** + \brief Enable interrupts and exceptions + \details Enables interrupts and exceptions by setting the IE-bit and EE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __enable_excp_irq(void) +{ +#ifdef CONFIG_MMU + __enable_supervisor_irq(); +#else + __enable_irq(); +#endif +} + + +/** + \brief Disable interrupts and exceptions + \details Disables interrupts and exceptions by clearing the IE-bit and EE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __disable_excp_irq(void) +{ +#ifdef CONFIG_MMU + __disable_supervisor_irq(); +#else + __disable_irq(); +#endif +} + +#define __CSI_GCC_OUT_REG(r) "=r" (r) +#define __CSI_GCC_USE_REG(r) "r" (r) + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__ALWAYS_STATIC_INLINE void __NOP(void) +{ + __ASM volatile("nop"); +} + +/** + \brief return from S-MODE + \details return from S-MODE. + */ +__ALWAYS_STATIC_INLINE void __SRET(void) +{ + __ASM volatile("sret"); +} + +/** + \brief return from M-MODE + \details return from M-MODE. + */ +__ALWAYS_STATIC_INLINE void __MRET(void) +{ + __ASM volatile("mret"); +} + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +__ALWAYS_STATIC_INLINE void __WFI(void) +{ + __ASM volatile("wfi"); +} + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one interrupt occurs. + */ +__ALWAYS_STATIC_INLINE void __WAIT(void) +{ + __ASM volatile("wfi"); +} + +/** + \brief Doze For Interrupt + \details Doze For Interrupt is a hint instruction that suspends execution until one interrupt occurs. + */ +__ALWAYS_STATIC_INLINE void __DOZE(void) +{ + __ASM volatile("wfi"); +} + +/** + \brief Stop For Interrupt + \details Stop For Interrupt is a hint instruction that suspends execution until one interrupt occurs. + */ +__ALWAYS_STATIC_INLINE void __STOP(void) +{ + __ASM volatile("wfi"); +} + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__ALWAYS_STATIC_INLINE void __ISB(void) +{ + __ASM volatile("fence.i"); + __ASM volatile("fence r, r"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__ALWAYS_STATIC_INLINE void __DSB(void) +{ + __ASM volatile("fence iorw, iorw"); +#if __riscv_xtheadsync + __ASM volatile("sync"); +#endif +} + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__ALWAYS_STATIC_INLINE void __DMB(void) +{ + __ASM volatile("fence rw, rw"); +} + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__ALWAYS_STATIC_INLINE void __SYNC_IS(void) +{ +#if __riscv_xtheadsync + __ASM volatile("sync.is"); +#endif +} + +/** + \brief Invalid all icache + \details invalid all icache. + */ +__ALWAYS_STATIC_INLINE void __ICACHE_IALL(void) +{ +#if __riscv_xtheadcmo + __ASM volatile("icache.iall"); +#endif +} + +/** + \brief Invalid all icache and broadcast to other cores + \details Invalid all icache and broadcast to other cores + */ +__ALWAYS_STATIC_INLINE void __ICACHE_IALLS(void) +{ +#if __riscv_xtheadcmo + __ASM volatile("icache.ialls"); +#endif +} + +/** + \brief Invalid Icache by physical addr + \details Invalid Icache by physical addr. + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __ICACHE_IPA(unsigned long addr) +{ +#if __riscv_xtheadcmo + __ASM volatile("icache.ipa %0" : : "r"(addr)); +#endif +} + +/** + \brief Invalid Icache by virsual addr + \details Invalid Icache by virsual addr. + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __ICACHE_IVA(unsigned long addr) +{ +#if __riscv_xtheadcmo + __ASM volatile("icache.iva %0" : : "r"(addr)); +#endif +} + +/** + \brief Invalid all L1dcache + \details invalid all L1dcache. + */ +__ALWAYS_STATIC_INLINE void __DCACHE_IALL(void) +{ +#if __riscv_xtheadcmo + __ASM volatile("dcache.iall"); +#endif +} + +/** + \brief Clear all dcache + \details clear all dcache. + */ +__ALWAYS_STATIC_INLINE void __DCACHE_CALL(void) +{ +#if __riscv_xtheadcmo + __ASM volatile("dcache.call"); +#endif +} + +/** + \brief Clear & invalid all dcache + \details clear & invalid all dcache. + */ +__ALWAYS_STATIC_INLINE void __DCACHE_CIALL(void) +{ +#if __riscv_xtheadcmo + __ASM volatile("dcache.ciall"); +#endif +} + +/** + \brief Clear & Invalid Dcache by way/set + \details Clear & Invalid Dcache by way/set + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __DCACHE_CISW(unsigned long wayset) +{ +#if __riscv_xtheadcmo + __ASM volatile("dcache.cisw %0" : : "r"(wayset)); +#endif +} + +#if CBO_INSN_SUPPORT +/** + \brief Clear Dcache/L2cache by addr + \details Clear Dcache/L2cache by addr. + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __CBO_CLEAN(unsigned long addr) +{ + __ASM volatile("cbo.clean 0(%0)" : : "r"(addr)); +} + +/** + \brief Clear & Invalid Dcache/L2cache by addr + \details Clear & Invalid Dcache/L2cache by addr. + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __CBO_FLUSH(unsigned long addr) +{ + __ASM volatile("cbo.flush 0(%0)" : : "r"(addr)); +} + +/** + \brief Invalid Dcache/L2cache by addr + \details Invalid Dcache/L2cache by addr. + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __CBO_INVAL(unsigned long addr) +{ + __ASM volatile("cbo.inval 0(%0)" : : "r"(addr)); +} + +/** + \brief Set Dcache to zero by addr + \details Set Dcache to zero by addr. + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __CBO_ZERO(unsigned long addr) +{ + __ASM volatile("cbo.zero %0" : : "r"(addr)); +} +#else +/** + \brief Clear Dcache/L2cache by physical addr + \details Clear Dcache/L2cache by physical addr. + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __DCACHE_CPA(unsigned long addr) +{ +#if __riscv_xtheadcmo + __ASM volatile("dcache.cpa %0" : : "r"(addr)); +#endif +} + +/** + \brief Clear Dcache/L2cache by virsual addr + \details Clear Dcache/L2cache by virsual addr. + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __DCACHE_CVA(unsigned long addr) +{ +#if __riscv_xtheadcmo + __ASM volatile("dcache.cva %0" : : "r"(addr)); +#endif +} + +/** + \brief Clear & Invalid Dcache by physical addr + \details Clear & Invalid Dcache by physical addr. + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __DCACHE_CIPA(unsigned long addr) +{ +#if __riscv_xtheadcmo + __ASM volatile("dcache.cipa %0" : : "r"(addr)); +#endif +} + +/** + \brief Clear & Invalid Dcache by virsual addr + \details Clear & Invalid Dcache by virsual addr. + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __DCACHE_CIVA(unsigned long addr) +{ +#if __riscv_xtheadcmo + __ASM volatile("dcache.civa %0" : : "r"(addr)); +#endif +} + +/** + \brief Invalid Dcache/L2cache by physical addr + \details Invalid Dcache/L2cache by physical addr. + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __DCACHE_IPA(unsigned long addr) +{ +#if __riscv_xtheadcmo + __ASM volatile("dcache.ipa %0" : : "r"(addr)); +#endif +} + +/** + \brief Invalid Dcache/L2cache by virsual addr + \details Invalid Dcache/L2cache by virsual addr. + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __DCACHE_IVA(unsigned long addr) +{ +#if __riscv_xtheadcmo + __ASM volatile("dcache.iva %0" : : "r"(addr)); +#endif +} + +#endif + +/** + \brief Clear L1-Dcache by physical addr and broadcast to other cores + \details Clear L1-Dcache by physical addr and broadcast to other cores + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __DCACHE_CPAL1(unsigned long addr) +{ +#if __riscv_xtheadcmo + __ASM volatile("dcache.cpal1 %0" : : "r"(addr)); +#endif +} + +/** + \brief Clear L1-Dcache by virsual addr and broadcast to other cores + \details Clear L1-Dcache by virsual addr and broadcast to other cores + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __DCACHE_CVAL1(unsigned long addr) +{ +#if __riscv_xtheadcmo + __ASM volatile("dcache.cval1 %0" : : "r"(addr)); +#endif +} + +/** + \brief Invalid Dcache by way/set + \details Invalid Dcache by way/set + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __DCACHE_ISW(unsigned long wayset) +{ +#if __riscv_xtheadcmo + __ASM volatile("dcache.isw %0" : : "r"(wayset)); +#endif +} + +#if (__L2CACHE_PRESENT == 1U) +/** + \brief Invalid L2 cache + \details invalid L2 cache. + */ +__ALWAYS_STATIC_INLINE void __L2CACHE_IALL(void) +{ + __ASM volatile("l2cache.iall"); +} + +/** + \brief Clear L2cache + \details clear L2cache. + */ +__ALWAYS_STATIC_INLINE void __L2CACHE_CALL(void) +{ + __ASM volatile("l2cache.call"); +} + +/** + \brief Clear&invalid L2cache + \details clear & invalid L2cache. + */ +__ALWAYS_STATIC_INLINE void __L2CACHE_CIALL(void) +{ + __ASM volatile("l2cache.ciall"); +} +#endif + +/** + \brief Get SATP + \details Returns the current value of the SATP. + \return SATP Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_SATP(void) +{ + register unsigned long result; + + __ASM volatile("csrr %0, satp" : "=r"(result)); + return (result); +} + +/** + \brief Set SATP + \details Assigns the given value to the SATP. + \param [in] satp SATP value to set + */ +__ALWAYS_STATIC_INLINE void __set_SATP(unsigned long satp) +{ + __ASM volatile("sfence.vma"); + __ASM volatile("csrw satp, %0" : : "r"(satp)); +} + +/** + \brief Get SCER2 + \details Returns the current value of the SCER2. + \return SCER2 Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_SCER2(void) +{ + register unsigned long result; + __ASM volatile("csrr %0, scer2" : "=r"(result)); + return (result); +} + +/** + \brief Set SCER2 + \details Assigns the given value to the SCER2. + \param [in] scer2 SCER2 value to set + */ +__ALWAYS_STATIC_INLINE void __set_SCER2(unsigned long scer2) +{ + __ASM volatile("csrw scer2, %0" : : "r"(scer2)); +} + +/** + \brief Get MCER2 + \details Returns the current value of the MCER2. + \return MCER2 Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MCER2(void) +{ + register unsigned long result; + __ASM volatile("csrr %0, mcer2" : "=r"(result)); + return (result); +} + +/** + \brief Set MCER2 + \details Assigns the given value to the MCER2. + \param [in] mcer2 MCER2 value to set + */ +__ALWAYS_STATIC_INLINE void __set_MCER2(unsigned long mcer2) +{ + __ASM volatile("csrw mcer2, %0" : : "r"(mcer2)); +} + +#if __riscv_xlen == 32 +/** + \brief Get MCER2H + \details Returns the current value of the MCER2H. + \return MCER2H Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MCER2H(void) +{ + register unsigned long result; + __ASM volatile("csrr %0, mcer2h" : "=r"(result)); + return (result); +} + +/** + \brief Set MCER2H + \details Assigns the given value to the MCER2H. + \param [in] mcer2h MCER2H value to set + */ +__ALWAYS_STATIC_INLINE void __set_MCER2H(unsigned long mcer2h) +{ + __ASM volatile("csrw mcer2h, %0" : : "r"(mcer2h)); +} +#endif + +/** + \brief Get SSBEPA2 + \details Returns the current value of the SSBEPA2. + \return SSBEPA2 Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_SSBEPA2(void) +{ + register unsigned long result; + //__ASM volatile("csrr %0, ssbepa2" : "=r"(result)); + __ASM volatile("csrr %0, 0x5d2" : "=r"(result)); + return (result); +} + +/** + \brief Set SSBEPA2 + \details Assigns the given value to the SSBEPA2. + \param [in] ssbepa2 SSBEPA2 value to set + */ +__ALWAYS_STATIC_INLINE void __set_SSBEPA2(unsigned long ssbepa2) +{ + //__ASM volatile("csrw ssbepa2, %0" : : "r"(ssbepa2)); + __ASM volatile("csrw 0x5d2, %0" : : "r"(ssbepa2)); +} + +/** + \brief Get MSBEPA2 + \details Returns the current value of the MSBEPA2. + \return MSBEPA2 Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MSBEPA2(void) +{ + register unsigned long result; + //__ASM volatile("csrr %0, msbepa2" : "=r"(result)); + __ASM volatile("csrr %0, 0x7fc" : "=r"(result)); + return (result); +} + +/** + \brief Set MSBEPA2 + \details Assigns the given value to the MSBEPA2. + \param [in] msbepa2 MSBEPA2 value to set + */ +__ALWAYS_STATIC_INLINE void __set_MSBEPA2(unsigned long msbepa2) +{ + //__ASM volatile("csrw msbepa2, %0" : : "r"(msbepa2)); + __ASM volatile("csrw 0x7fc, %0" : : "r"(msbepa2)); +} + +/** + \brief Get SCER + \details Returns the current value of the SCER. + \return SCER Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_SCER(void) +{ + register unsigned long result; + __ASM volatile("csrr %0, scer" : "=r"(result)); + return (result); +} + +/** + \brief Set SCER + \details Assigns the given value to the SCER. + \param [in] scer SCER value to set + */ +__ALWAYS_STATIC_INLINE void __set_SCER(unsigned long scer) +{ + __ASM volatile("csrw scer, %0" : : "r"(scer)); +} + +/** + \brief Get MCER + \details Returns the current value of the MCER. + \return MCER Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MCER(void) +{ + register unsigned long result; + __ASM volatile("csrr %0, mcer" : "=r"(result)); + return (result); +} + +/** + \brief Set MCER + \details Assigns the given value to the MCER. + \param [in] mcer MCER value to set + */ +__ALWAYS_STATIC_INLINE void __set_MCER(unsigned long mcer) +{ + __ASM volatile("csrw mcer, %0" : : "r"(mcer)); +} + +#if __riscv_xlen == 32 +/** + \brief Get MCERH + \details Returns the current value of the MCERH. + \return MCERH Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MCERH(void) +{ + register unsigned long result; + __ASM volatile("csrr %0, mcerh" : "=r"(result)); + return (result); +} + +/** + \brief Set MCERH + \details Assigns the given value to the MCERH. + \param [in] mcerh MCERH value to set + */ +__ALWAYS_STATIC_INLINE void __set_MCERH(unsigned long mcerh) +{ + __ASM volatile("csrw mcerh, %0" : : "r"(mcerh)); +} +#endif + +/** + \brief Get SSBEPA + \details Returns the current value of the SSBEPA. + \return SSBEPA Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_SSBEPA(void) +{ + register unsigned long result; + //__ASM volatile("csrr %0, ssbepa" : "=r"(result)); + __ASM volatile("csrr %0, 0x5d1" : "=r"(result)); + return (result); +} + +/** + \brief Set SSBEPA + \details Assigns the given value to the SSBEPA. + \param [in] ssbepa SSBEPA value to set + */ +__ALWAYS_STATIC_INLINE void __set_SSBEPA(unsigned long ssbepa) +{ + //__ASM volatile("csrw ssbepa, %0" : : "r"(ssbepa)); + __ASM volatile("csrw 0x5d1, %0" : : "r"(ssbepa)); +} + +/** + \brief Get MSBEPA + \details Returns the current value of the MSBEPA. + \return MSBEPA Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MSBEPA(void) +{ + register unsigned long result; + //__ASM volatile("csrr %0, msbepa" : "=r"(result)); + __ASM volatile("csrr %0, 0x7fb" : "=r"(result)); + return (result); +} + +/** + \brief Set MSBEPA + \details Assigns the given value to the MSBEPA. + \param [in] msbepa MSBEPA value to set + */ +__ALWAYS_STATIC_INLINE void __set_MSBEPA(unsigned long msbepa) +{ + //__ASM volatile("csrw msbepa, %0" : : "r"(msbepa)); + __ASM volatile("csrw 0x7fb, %0" : : "r"(msbepa)); +} + +/** + \brief Get ERRSTS + \details Returns the current value of the ERRSTS. + \return ERRSTS Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MIESR(void) +{ + register unsigned long result; + + __ASM volatile("csrr %0, miesr" : "=r"(result)); + return (result); +} + +/** + \brief Get MEICR2 + \details Returns the current value of the MEICR2. + \return MEICR2 Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MEICR2(void) +{ + register unsigned long result; + + __ASM volatile("csrr %0, meicr2" : "=r"(result)); + return (result); +} + +/** + \brief Set MEICR2 + \details Assigns the given value to the MEICR2. + \param [in] errinjcr MEICR2 value to set + */ +__ALWAYS_STATIC_INLINE void __set_MEICR2(unsigned long meicr2) +{ + __ASM volatile("csrw meicr2, %0" : : "r"(meicr2)); +} + +/** + \brief Get MEICR + \details Returns the current value of the MEICR. + \return MEICR Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MEICR(void) +{ + register unsigned long result; + + __ASM volatile("csrr %0, meicr" : "=r"(result)); + return (result); +} + +/** + \brief Set MEICR + \details Assigns the given value to the MEICR. + \param [in] errinjcr MEICR value to set + */ +__ALWAYS_STATIC_INLINE void __set_MEICR(unsigned long meicr) +{ + __ASM volatile("csrw meicr, %0" : : "r"(meicr)); +} + +/** + \brief Get ITCMCR + \details Returns the content of the ITCMCR Register. + \return ITCMCR Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MITCMCR(void) +{ + unsigned long result; + __ASM volatile("csrr %0, mitcmcr" : "=r"(result)); + return (result); +} + +/** + \brief Set ITCMCR + \details Writes the given value to the ITCMCR Register. + \param [in] itcmcr ITCMCR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MITCMCR(unsigned long itcmcr) +{ + __ASM volatile("csrw mitcmcr, %0" : : "r"(itcmcr)); +} + +/** + \brief Get DTCMCR + \details Returns the content of the DTCMCR Register. + \return DTCMCR Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MDTCMCR(void) +{ + unsigned long result; + __ASM volatile("csrr %0, mdtcmcr" : "=r"(result)); + return (result); +} + +/** + \brief Set DTCMCR + \details Writes the given value to the DTCMCR Register. + \param [in] dtcmcr DTCMCR Registed value to set + */ +__ALWAYS_STATIC_INLINE void __set_MDTCMCR(unsigned long dtcmcr) +{ + __ASM volatile("csrw mdtcmcr, %0" : : "r"(dtcmcr)); +} + +/** + \brief Get MFPPCR + \details Read MFPPCR Register. + \return MFPPCR Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MFPPCR(void) +{ + unsigned long result; + __ASM volatile("csrr %0, mfppcr" : "=r"(result)); + return (result); +} + +/** + \brief Set MFPPCR + \details Write MFPPCR Register. + \param [in] fppcr MFPPCR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MFPPCR(unsigned long fppcr) +{ + __ASM volatile("csrw mfppcr, %0" : : "r"(fppcr)); +} + +/** + \brief Set MCOUNTINHIBIT + \details Write MCOUNTINHIBIT Register. + \param [in] value MCOUNTINHIBIT Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MCOUNTINHIBIT(uint32_t value) +{ + __ASM volatile("csrw mcountinhibit, %0" : : "r"(value)); +} + +/** + \brief Get MCOUNTINHIBIT + \details Read MCOUNTINHIBIT Register + \return MCOUNTINHIBIT Register value + */ +__ALWAYS_STATIC_INLINE unsigned int __get_MCOUNTINHIBIT(void) +{ + uint32_t result; + __ASM volatile("csrr %0, mcountinhibit" : "=r"(result)); + return result; +} + +/** + \brief Set MHPMEVENT + \details Write MHPMEVENT Register + \param [in] idx Index of MHPMEVENT Register + \param [in] value MHPMEVENT Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MHPMEVENT(unsigned long idx, unsigned long value) +{ + switch (idx) { + case 0: rv_csr_write(0x7E0, value); break; + case 2: rv_csr_write(0x7E1, value); break; + case 3: rv_csr_write(0x323, value); break; + case 4: rv_csr_write(0x324, value); break; + case 5: rv_csr_write(0x325, value); break; + case 6: rv_csr_write(0x326, value); break; + case 7: rv_csr_write(0x327, value); break; + case 8: rv_csr_write(0x328, value); break; + case 9: rv_csr_write(0x329, value); break; + case 10: rv_csr_write(0x32a, value); break; + case 11: rv_csr_write(0x32b, value); break; + case 12: rv_csr_write(0x32c, value); break; + case 13: rv_csr_write(0x32d, value); break; + case 14: rv_csr_write(0x32e, value); break; + case 15: rv_csr_write(0x32f, value); break; + case 16: rv_csr_write(0x330, value); break; + case 17: rv_csr_write(0x331, value); break; + case 18: rv_csr_write(0x332, value); break; + case 19: rv_csr_write(0x333, value); break; + case 20: rv_csr_write(0x334, value); break; + case 21: rv_csr_write(0x335, value); break; + case 22: rv_csr_write(0x336, value); break; + case 23: rv_csr_write(0x337, value); break; + case 24: rv_csr_write(0x338, value); break; + case 25: rv_csr_write(0x339, value); break; + case 26: rv_csr_write(0x33a, value); break; + case 27: rv_csr_write(0x33b, value); break; + case 28: rv_csr_write(0x33c, value); break; + case 29: rv_csr_write(0x33d, value); break; + case 30: rv_csr_write(0x33e, value); break; + case 31: rv_csr_write(0x33F, value); break; + default: break; + } +} + +/** + \brief Get MHPMEVENT + \details Read MHPMEVENT Register. + \param [in] idx Index of MHPMEVENT Register to read. + \return MHPMEVENT Register Value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MHPMEVENT(unsigned long idx) +{ + switch (idx) { + case 0: return rv_csr_read(0x7E0); + case 2: return rv_csr_read(0x7E1); + case 3: return rv_csr_read(0x323); + case 4: return rv_csr_read(0x324); + case 5: return rv_csr_read(0x325); + case 6: return rv_csr_read(0x326); + case 7: return rv_csr_read(0x327); + case 8: return rv_csr_read(0x328); + case 9: return rv_csr_read(0x329); + case 10: return rv_csr_read(0x32a); + case 11: return rv_csr_read(0x32b); + case 12: return rv_csr_read(0x32c); + case 13: return rv_csr_read(0x32d); + case 14: return rv_csr_read(0x32e); + case 15: return rv_csr_read(0x32f); + case 16: return rv_csr_read(0x330); + case 17: return rv_csr_read(0x331); + case 18: return rv_csr_read(0x332); + case 19: return rv_csr_read(0x333); + case 20: return rv_csr_read(0x334); + case 21: return rv_csr_read(0x335); + case 22: return rv_csr_read(0x336); + case 23: return rv_csr_read(0x337); + case 24: return rv_csr_read(0x338); + case 25: return rv_csr_read(0x339); + case 26: return rv_csr_read(0x33a); + case 27: return rv_csr_read(0x33b); + case 28: return rv_csr_read(0x33c); + case 29: return rv_csr_read(0x33d); + case 30: return rv_csr_read(0x33e); + case 31: return rv_csr_read(0x33F); + default: return 0; + } +} + +/** + \brief Set MHPMEVENTH + \details Write MHPMEVENTH Register + \param [in] idx Index of MHPMEVENT Register + \param [in] value MHPMEVENTH Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MHPMEVENTH(unsigned long idx, unsigned long value) +{ + switch (idx) { + case 3: rv_csr_write(0x723, value); break; + case 4: rv_csr_write(0x724, value); break; + case 5: rv_csr_write(0x725, value); break; + case 6: rv_csr_write(0x726, value); break; + case 7: rv_csr_write(0x727, value); break; + case 8: rv_csr_write(0x728, value); break; + case 9: rv_csr_write(0x729, value); break; + case 10: rv_csr_write(0x72A, value); break; + case 11: rv_csr_write(0x72B, value); break; + case 12: rv_csr_write(0x72C, value); break; + case 13: rv_csr_write(0x72D, value); break; + case 14: rv_csr_write(0x72E, value); break; + case 15: rv_csr_write(0x72F, value); break; + case 16: rv_csr_write(0x730, value); break; + case 17: rv_csr_write(0x731, value); break; + case 18: rv_csr_write(0x732, value); break; + case 19: rv_csr_write(0x733, value); break; + case 20: rv_csr_write(0x734, value); break; + case 21: rv_csr_write(0x735, value); break; + case 22: rv_csr_write(0x736, value); break; + case 23: rv_csr_write(0x737, value); break; + case 24: rv_csr_write(0x738, value); break; + case 25: rv_csr_write(0x739, value); break; + case 26: rv_csr_write(0x73A, value); break; + case 27: rv_csr_write(0x73B, value); break; + case 28: rv_csr_write(0x73C, value); break; + case 29: rv_csr_write(0x73D, value); break; + case 30: rv_csr_write(0x73E, value); break; + case 31: rv_csr_write(0x73F, value); break; + default: break; + } +} + +/** + \brief Get MHPMEVENTH + \details Read MHPMEVENTH Register. + \param [in] idx Index of MHPMEVENTH Register to read. + \return MHPMEVENTH Register Value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MHPMEVENTH(unsigned long idx) +{ + switch (idx) { + case 3: return rv_csr_read(0x723); + case 4: return rv_csr_read(0x724); + case 5: return rv_csr_read(0x725); + case 6: return rv_csr_read(0x726); + case 7: return rv_csr_read(0x727); + case 8: return rv_csr_read(0x728); + case 9: return rv_csr_read(0x729); + case 10: return rv_csr_read(0x72A); + case 11: return rv_csr_read(0x72B); + case 12: return rv_csr_read(0x72C); + case 13: return rv_csr_read(0x72D); + case 14: return rv_csr_read(0x72E); + case 15: return rv_csr_read(0x72F); + case 16: return rv_csr_read(0x730); + case 17: return rv_csr_read(0x731); + case 18: return rv_csr_read(0x732); + case 19: return rv_csr_read(0x733); + case 20: return rv_csr_read(0x734); + case 21: return rv_csr_read(0x735); + case 22: return rv_csr_read(0x736); + case 23: return rv_csr_read(0x737); + case 24: return rv_csr_read(0x738); + case 25: return rv_csr_read(0x739); + case 26: return rv_csr_read(0x73A); + case 27: return rv_csr_read(0x73B); + case 28: return rv_csr_read(0x73C); + case 29: return rv_csr_read(0x73D); + case 30: return rv_csr_read(0x73E); + case 31: return rv_csr_read(0x73F); + default: return 0; + } +} + +/** + \brief Set MHPMCOUNTER + \details Write MHPMCOUNTER Register + \param [in] idx Index of MHPMCOUNTER Register + \param [in] value MHPMCOUNTER Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MHPMCOUNTER(unsigned long idx, unsigned long value) +{ + switch (idx) { + case 3: rv_csr_write(0xB03, (value)); break; + case 4: rv_csr_write(0xB04, (value)); break; + case 5: rv_csr_write(0xB05, (value)); break; + case 6: rv_csr_write(0xB06, (value)); break; + case 7: rv_csr_write(0xB07, (value)); break; + case 8: rv_csr_write(0xB08, (value)); break; + case 9: rv_csr_write(0xB09, (value)); break; + case 10: rv_csr_write(0xB0A, (value)); break; + case 11: rv_csr_write(0xB0B, (value)); break; + case 12: rv_csr_write(0xB0C, (value)); break; + case 13: rv_csr_write(0xB0D, (value)); break; + case 14: rv_csr_write(0xB0E, (value)); break; + case 15: rv_csr_write(0xB0F, (value)); break; + case 16: rv_csr_write(0xB10, (value)); break; + case 17: rv_csr_write(0xB11, (value)); break; + case 18: rv_csr_write(0xB12, (value)); break; + case 19: rv_csr_write(0xB13, (value)); break; + case 20: rv_csr_write(0xB14, (value)); break; + case 21: rv_csr_write(0xB15, (value)); break; + case 22: rv_csr_write(0xB16, (value)); break; + case 23: rv_csr_write(0xB17, (value)); break; + case 24: rv_csr_write(0xB18, (value)); break; + case 25: rv_csr_write(0xB19, (value)); break; + case 26: rv_csr_write(0xB1A, (value)); break; + case 27: rv_csr_write(0xB1B, (value)); break; + case 28: rv_csr_write(0xB1C, (value)); break; + case 29: rv_csr_write(0xB1D, (value)); break; + case 30: rv_csr_write(0xB1E, (value)); break; + case 31: rv_csr_write(0xB1F, (value)); break; + default: break; + } +} + +/** + \brief Get MHPMCOUNTER + \details Write MHPMCOUNTER Register. + \param [in] idx Index of MHPMCOUNTER Register + \return MHPMCOUNTER Register Value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MHPMCOUNTER(unsigned long idx) +{ + switch (idx) { + case 3: return rv_csr_read(0xB03); + case 4: return rv_csr_read(0xB04); + case 5: return rv_csr_read(0xB05); + case 6: return rv_csr_read(0xB06); + case 7: return rv_csr_read(0xB07); + case 8: return rv_csr_read(0xB08); + case 9: return rv_csr_read(0xB09); + case 10: return rv_csr_read(0xB0A); + case 11: return rv_csr_read(0xB0B); + case 12: return rv_csr_read(0xB0C); + case 13: return rv_csr_read(0xB0D); + case 14: return rv_csr_read(0xB0E); + case 15: return rv_csr_read(0xB0F); + case 16: return rv_csr_read(0xB10); + case 17: return rv_csr_read(0xB11); + case 18: return rv_csr_read(0xB12); + case 19: return rv_csr_read(0xB13); + case 20: return rv_csr_read(0xB14); + case 21: return rv_csr_read(0xB15); + case 22: return rv_csr_read(0xB16); + case 23: return rv_csr_read(0xB17); + case 24: return rv_csr_read(0xB18); + case 25: return rv_csr_read(0xB19); + case 26: return rv_csr_read(0xB1A); + case 27: return rv_csr_read(0xB1B); + case 28: return rv_csr_read(0xB1C); + case 29: return rv_csr_read(0xB1D); + case 30: return rv_csr_read(0xB1E); + case 31: return rv_csr_read(0xB1F); + default: return 0; + } +} + +/** + \brief Set MHPMCOUNTERH + \details Write MHPMCOUNTERH Register + \param [in] idx Index of MHPMCOUNTERH Register + \param [in] value MHPMCOUNTERH Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MHPMCOUNTERH(unsigned long idx, unsigned long value) +{ + switch (idx) { + case 3: rv_csr_write(0xB83, (value)); break; + case 4: rv_csr_write(0xB84, (value)); break; + case 5: rv_csr_write(0xB85, (value)); break; + case 6: rv_csr_write(0xB86, (value)); break; + case 7: rv_csr_write(0xB87, (value)); break; + case 8: rv_csr_write(0xB88, (value)); break; + case 9: rv_csr_write(0xB89, (value)); break; + case 10: rv_csr_write(0xB8A, (value)); break; + case 11: rv_csr_write(0xB8B, (value)); break; + case 12: rv_csr_write(0xB8C, (value)); break; + case 13: rv_csr_write(0xB8D, (value)); break; + case 14: rv_csr_write(0xB8E, (value)); break; + case 15: rv_csr_write(0xB8F, (value)); break; + case 16: rv_csr_write(0xB90, (value)); break; + case 17: rv_csr_write(0xB91, (value)); break; + case 18: rv_csr_write(0xB92, (value)); break; + case 19: rv_csr_write(0xB93, (value)); break; + case 20: rv_csr_write(0xB94, (value)); break; + case 21: rv_csr_write(0xB95, (value)); break; + case 22: rv_csr_write(0xB96, (value)); break; + case 23: rv_csr_write(0xB97, (value)); break; + case 24: rv_csr_write(0xB98, (value)); break; + case 25: rv_csr_write(0xB99, (value)); break; + case 26: rv_csr_write(0xB9A, (value)); break; + case 27: rv_csr_write(0xB9B, (value)); break; + case 28: rv_csr_write(0xB9C, (value)); break; + case 29: rv_csr_write(0xB9D, (value)); break; + case 30: rv_csr_write(0xB9E, (value)); break; + case 31: rv_csr_write(0xB9F, (value)); break; + default: break; + } +} + +/** + \brief Get MHPMCOUNTERH + \details Write MHPMCOUNTERH Register. + \param [in] idx Index of MHPMCOUNTERH Register + \return MHPMCOUNTERH Register Value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MHPMCOUNTERH(unsigned long idx) +{ + switch (idx) { + case 3: return rv_csr_read(0xB83); + case 4: return rv_csr_read(0xB84); + case 5: return rv_csr_read(0xB85); + case 6: return rv_csr_read(0xB86); + case 7: return rv_csr_read(0xB87); + case 8: return rv_csr_read(0xB88); + case 9: return rv_csr_read(0xB89); + case 10: return rv_csr_read(0xB8A); + case 11: return rv_csr_read(0xB8B); + case 12: return rv_csr_read(0xB8C); + case 13: return rv_csr_read(0xB8D); + case 14: return rv_csr_read(0xB8E); + case 15: return rv_csr_read(0xB8F); + case 16: return rv_csr_read(0xB90); + case 17: return rv_csr_read(0xB91); + case 18: return rv_csr_read(0xB92); + case 19: return rv_csr_read(0xB93); + case 20: return rv_csr_read(0xB94); + case 21: return rv_csr_read(0xB95); + case 22: return rv_csr_read(0xB96); + case 23: return rv_csr_read(0xB97); + case 24: return rv_csr_read(0xB98); + case 25: return rv_csr_read(0xB99); + case 26: return rv_csr_read(0xB9A); + case 27: return rv_csr_read(0xB9B); + case 28: return rv_csr_read(0xB9C); + case 29: return rv_csr_read(0xB9D); + case 30: return rv_csr_read(0xB9E); + case 31: return rv_csr_read(0xB9F); + default: return 0; + } +} + +#if 0 +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__ALWAYS_STATIC_INLINE unsigned long __REV(unsigned long value) +{ + return __builtin_bswap32(value); +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__ALWAYS_STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + result = ((value & 0xFF000000) >> 8) | ((value & 0x00FF0000) << 8) | + ((value & 0x0000FF00) >> 8) | ((value & 0x000000FF) << 8); + + return (result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__ALWAYS_STATIC_INLINE int32_t __REVSH(int32_t value) +{ + return (short)(((value & 0xFF00) >> 8) | ((value & 0x00FF) << 8)); +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__ALWAYS_STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + */ +__ALWAYS_STATIC_INLINE void __BKPT(void) +{ + __ASM volatile("ebreak"); +} + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__ALWAYS_STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + + for (value >>= 1U; value; value >>= 1U) { + result <<= 1U; + result |= value & 1U; + s--; + } + + result <<= s; /* shift when v's highest bits are zero */ + + return (result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz +/** + \details This function saturates a signed value. + \param [in] x Value to be saturated + \param [in] y Bit position to saturate to [1..32] + \return Saturated value. + */ +__ALWAYS_STATIC_INLINE int32_t __SSAT(int32_t x, uint32_t y) +{ + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + + for (i = 0; i < (y - 1); i++) { + posMax = posMax * 2; + } + + if (x > 0) { + posMax = (posMax - 1); + + if (x > posMax) { + x = posMax; + } + +// x &= (posMax * 2 + 1); + } else { + negMin = -posMax; + + if (x < negMin) { + x = negMin; + } + +// x &= (posMax * 2 - 1); + } + + return (x); +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__ALWAYS_STATIC_INLINE uint32_t __USAT(uint32_t value, uint32_t sat) +{ + uint32_t result; + + if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) { + result = 0xFFFFFFFF >> (32 - sat); + } else { + result = value; + } + + return (result); +} + +/** + \brief Unsigned Saturate for internal use + \details Saturates an unsigned value, should not call directly. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__ALWAYS_STATIC_INLINE uint32_t __IUSAT(uint32_t value, uint32_t sat) +{ + uint32_t result; + + if (value & 0x80000000) { /* only overflow set bit-31 */ + result = 0; + } else if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) { + result = 0xFFFFFFFF >> (32 - sat); + } else { + result = value; + } + + return (result); +} + +/** + \brief Rotate Right with Extend + \details This function moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \note carry input will always 0. + \param [in] op1 Value to rotate + \return Rotated value + */ +__ALWAYS_STATIC_INLINE uint32_t __RRX(uint32_t op1) +{ + return 0; +} + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] addr Pointer to location + \return value of type uint8_t at (*ptr) + */ +__ALWAYS_STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile("lb %0, 0(%1)" : "=r"(result) : "r"(addr)); + + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] addr Pointer to location + \return value of type uint16_t at (*ptr) + */ +__ALWAYS_STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile("lh %0, 0(%1)" : "=r"(result) : "r"(addr)); + + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] addr Pointer to location + \return value of type uint32_t at (*ptr) + */ +__ALWAYS_STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile("lw %0, 0(%1)" : "=r"(result) : "r"(addr)); + + return (result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] addr Pointer to location + */ +__ALWAYS_STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile("sb %1, 0(%0)" :: "r"(addr), "r"((uint32_t)value) : "memory"); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] addr Pointer to location + */ +__ALWAYS_STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile("sh %1, 0(%0)" :: "r"(addr), "r"((uint32_t)value) : "memory"); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] addr Pointer to location + */ +__ALWAYS_STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile("sw %1, 0(%0)" :: "r"(addr), "r"(value) : "memory"); +} + +/*@}*/ /* end of group CSI_Core_InstructionInterface */ + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CSI_SIMD_intrinsics CSI SIMD Intrinsics + Access to dedicated SIMD instructions \n + Single Instruction Multiple Data (SIMD) extensions are provided to simplify development of application software. SIMD extensions increase the processing capability without materially increasing the power consumption. The SIMD extensions are completely transparent to the operating system (OS), allowing existing OS ports to be used. + + @{ +*/ + +/** + \brief Halfword packing instruction. Combines bits[15:0] of val1 with bits[31:16] + of val2 levitated with the val3. + \details Combine a halfword from one register with a halfword from another register. + The second argument can be left-shifted before extraction of the halfword. + \param [in] val1 first 16-bit operands + \param [in] val2 second 16-bit operands + \param [in] val3 value for left-shifting val2. Value range [0..31]. + \return the combination of halfwords. + \remark + res[15:0] = val1[15:0] \n + res[31:16] = val2[31:16] << val3 + */ +__ALWAYS_STATIC_INLINE uint32_t __PKHBT(uint32_t val1, uint32_t val2, uint32_t val3) +{ + return ((((int32_t)(val1) << 0) & (int32_t)0x0000FFFF) | (((int32_t)(val2) << val3) & (int32_t)0xFFFF0000)); +} + +/** + \brief Halfword packing instruction. Combines bits[31:16] of val1 with bits[15:0] + of val2 right-shifted with the val3. + \details Combine a halfword from one register with a halfword from another register. + The second argument can be right-shifted before extraction of the halfword. + \param [in] val1 first 16-bit operands + \param [in] val2 second 16-bit operands + \param [in] val3 value for right-shifting val2. Value range [1..32]. + \return the combination of halfwords. + \remark + res[15:0] = val2[15:0] >> val3 \n + res[31:16] = val1[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __PKHTB(uint32_t val1, uint32_t val2, uint32_t val3) +{ + return ((((int32_t)(val1) << 0) & (int32_t)0xFFFF0000) | (((int32_t)(val2) >> val3) & (int32_t)0x0000FFFF)); +} + +/** + \brief Dual 16-bit signed saturate. + \details This function saturates a signed value. + \param [in] x two signed 16-bit values to be saturated. + \param [in] y bit position for saturation, an integral constant expression in the range 1 to 16. + \return the sum of the absolute differences of the following bytes, added to the accumulation value:\n + the signed saturation of the low halfword in val1, saturated to the bit position specified in + val2 and returned in the low halfword of the return value.\n + the signed saturation of the high halfword in val1, saturated to the bit position specified in + val2 and returned in the high halfword of the return value. + */ +__ALWAYS_STATIC_INLINE uint32_t __SSAT16(int32_t x, const uint32_t y) +{ + int32_t r = 0, s = 0; + + r = __SSAT((((int32_t)x << 16) >> 16), y) & (int32_t)0x0000FFFF; + s = __SSAT((((int32_t)x) >> 16), y) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturate. + \details This function enables you to saturate two signed 16-bit values to a selected unsigned range. + \param [in] x two signed 16-bit values to be saturated. + \param [in] y bit position for saturation, an integral constant expression in the range 1 to 16. + \return the saturation of the two signed 16-bit values, as non-negative values: + the saturation of the low halfword in val1, saturated to the bit position specified in + val2 and returned in the low halfword of the return value.\n + the saturation of the high halfword in val1, saturated to the bit position specified in + val2 and returned in the high halfword of the return value. + */ +__ALWAYS_STATIC_INLINE uint32_t __USAT16(uint32_t x, const uint32_t y) +{ + int32_t r = 0, s = 0; + + r = __IUSAT(((x << 16) >> 16), y) & 0x0000FFFF; + s = __IUSAT(((x) >> 16), y) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Quad 8-bit saturating addition. + \details This function enables you to perform four 8-bit integer additions, + saturating the results to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the saturated addition of the first byte of each operand in the first byte of the return value.\n + the saturated addition of the second byte of each operand in the second byte of the return value.\n + the saturated addition of the third byte of each operand in the third byte of the return value.\n + the saturated addition of the fourth byte of each operand in the fourth byte of the return value.\n + The returned results are saturated to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1. + \remark + res[7:0] = val1[7:0] + val2[7:0] \n + res[15:8] = val1[15:8] + val2[15:8] \n + res[23:16] = val1[23:16] + val2[23:16] \n + res[31:24] = val1[31:24] + val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __QADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = __SSAT(((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((int32_t)x) >> 24) + (((int32_t)y) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned saturating addition. + \details This function enables you to perform four unsigned 8-bit integer additions, + saturating the results to the 8-bit unsigned integer range 0 < x < 2^8 - 1. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the saturated addition of the first byte of each operand in the first byte of the return value.\n + the saturated addition of the second byte of each operand in the second byte of the return value.\n + the saturated addition of the third byte of each operand in the third byte of the return value.\n + the saturated addition of the fourth byte of each operand in the fourth byte of the return value.\n + The returned results are saturated to the 8-bit signed integer range 0 <= x <= 2^8 - 1. + \remark + res[7:0] = val1[7:0] + val2[7:0] \n + res[15:8] = val1[15:8] + val2[15:8] \n + res[23:16] = val1[23:16] + val2[23:16] \n + res[31:24] = val1[31:24] + val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = __IUSAT((((x << 24) >> 24) + ((y << 24) >> 24)), 8) & 0x000000FF; + s = __IUSAT((((x << 16) >> 24) + ((y << 16) >> 24)), 8) & 0x000000FF; + t = __IUSAT((((x << 8) >> 24) + ((y << 8) >> 24)), 8) & 0x000000FF; + u = __IUSAT((((x) >> 24) + ((y) >> 24)), 8) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Quad 8-bit signed addition. + \details This function performs four 8-bit signed integer additions. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the addition of the first bytes from each operand, in the first byte of the return value.\n + the addition of the second bytes of each operand, in the second byte of the return value.\n + the addition of the third bytes of each operand, in the third byte of the return value.\n + the addition of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + res[7:0] = val1[7:0] + val2[7:0] \n + res[15:8] = val1[15:8] + val2[15:8] \n + res[23:16] = val1[23:16] + val2[23:16] \n + res[31:24] = val1[31:24] + val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __SADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = ((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)) & (int32_t)0x000000FF; + s = ((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)) & (int32_t)0x000000FF; + t = ((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)) & (int32_t)0x000000FF; + u = ((((int32_t)x) >> 24) + (((int32_t)y) >> 24)) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned addition. + \details This function performs four unsigned 8-bit integer additions. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the addition of the first bytes from each operand, in the first byte of the return value.\n + the addition of the second bytes of each operand, in the second byte of the return value.\n + the addition of the third bytes of each operand, in the third byte of the return value.\n + the addition of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + res[7:0] = val1[7:0] + val2[7:0] \n + res[15:8] = val1[15:8] + val2[15:8] \n + res[23:16] = val1[23:16] + val2[23:16] \n + res[31:24] = val1[31:24] + val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __UADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = (((x << 24) >> 24) + ((y << 24) >> 24)) & 0x000000FF; + s = (((x << 16) >> 24) + ((y << 16) >> 24)) & 0x000000FF; + t = (((x << 8) >> 24) + ((y << 8) >> 24)) & 0x000000FF; + u = (((x) >> 24) + ((y) >> 24)) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Quad 8-bit saturating subtract. + \details This function enables you to perform four 8-bit integer subtractions, + saturating the results to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the subtraction of the first byte of each operand in the first byte of the return value.\n + the subtraction of the second byte of each operand in the second byte of the return value.\n + the subtraction of the third byte of each operand in the third byte of the return value.\n + the subtraction of the fourth byte of each operand in the fourth byte of the return value.\n + The returned results are saturated to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1. + \remark + res[7:0] = val1[7:0] - val2[7:0] \n + res[15:8] = val1[15:8] - val2[15:8] \n + res[23:16] = val1[23:16] - val2[23:16] \n + res[31:24] = val1[31:24] - val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __QSUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = __SSAT(((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((int32_t)x) >> 24) - (((int32_t)y) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned saturating subtraction. + \details This function enables you to perform four unsigned 8-bit integer subtractions, + saturating the results to the 8-bit unsigned integer range 0 < x < 2^8 - 1. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the subtraction of the first byte of each operand in the first byte of the return value.\n + the subtraction of the second byte of each operand in the second byte of the return value.\n + the subtraction of the third byte of each operand in the third byte of the return value.\n + the subtraction of the fourth byte of each operand in the fourth byte of the return value.\n + The returned results are saturated to the 8-bit unsigned integer range 0 <= x <= 2^8 - 1. + \remark + res[7:0] = val1[7:0] - val2[7:0] \n + res[15:8] = val1[15:8] - val2[15:8] \n + res[23:16] = val1[23:16] - val2[23:16] \n + res[31:24] = val1[31:24] - val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQSUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = __IUSAT((((x << 24) >> 24) - ((y << 24) >> 24)), 8) & 0x000000FF; + s = __IUSAT((((x << 16) >> 24) - ((y << 16) >> 24)), 8) & 0x000000FF; + t = __IUSAT((((x << 8) >> 24) - ((y << 8) >> 24)), 8) & 0x000000FF; + u = __IUSAT((((x) >> 24) - ((y) >> 24)), 8) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Quad 8-bit signed subtraction. + \details This function enables you to perform four 8-bit signed integer subtractions. + \param [in] x first four 8-bit operands of each subtraction. + \param [in] y second four 8-bit operands of each subtraction. + \return the subtraction of the first bytes from each operand, in the first byte of the return value.\n + the subtraction of the second bytes of each operand, in the second byte of the return value.\n + the subtraction of the third bytes of each operand, in the third byte of the return value.\n + the subtraction of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + res[7:0] = val1[7:0] - val2[7:0] \n + res[15:8] = val1[15:8] - val2[15:8] \n + res[23:16] = val1[23:16] - val2[23:16] \n + res[31:24] = val1[31:24] - val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __SSUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = ((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)) & (int32_t)0x000000FF; + s = ((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)) & (int32_t)0x000000FF; + t = ((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)) & (int32_t)0x000000FF; + u = ((((int32_t)x) >> 24) - (((int32_t)y) >> 24)) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned subtract. + \details This function enables you to perform four 8-bit unsigned integer subtractions. + \param [in] x first four 8-bit operands of each subtraction. + \param [in] y second four 8-bit operands of each subtraction. + \return the subtraction of the first bytes from each operand, in the first byte of the return value.\n + the subtraction of the second bytes of each operand, in the second byte of the return value.\n + the subtraction of the third bytes of each operand, in the third byte of the return value.\n + the subtraction of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + res[7:0] = val1[7:0] - val2[7:0] \n + res[15:8] = val1[15:8] - val2[15:8] \n + res[23:16] = val1[23:16] - val2[23:16] \n + res[31:24] = val1[31:24] - val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __USUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = (((x << 24) >> 24) - ((y << 24) >> 24)) & 0x000000FF; + s = (((x << 16) >> 24) - ((y << 16) >> 24)) & 0x000000FF; + t = (((x << 8) >> 24) - ((y << 8) >> 24)) & 0x000000FF; + u = (((x) >> 24) - ((y) >> 24)) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Unsigned sum of quad 8-bit unsigned absolute difference. + \details This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values + of the differences together, returning the result as a single unsigned integer. + \param [in] x first four 8-bit operands of each subtraction. + \param [in] y second four 8-bit operands of each subtraction. + \return the subtraction of the first bytes from each operand, in the first byte of the return value.\n + the subtraction of the second bytes of each operand, in the second byte of the return value.\n + the subtraction of the third bytes of each operand, in the third byte of the return value.\n + the subtraction of the fourth bytes of each operand, in the fourth byte of the return value.\n + The sum is returned as a single unsigned integer. + \remark + absdiff1 = val1[7:0] - val2[7:0] \n + absdiff2 = val1[15:8] - val2[15:8] \n + absdiff3 = val1[23:16] - val2[23:16] \n + absdiff4 = val1[31:24] - val2[31:24] \n + res[31:0] = absdiff1 + absdiff2 + absdiff3 + absdiff4 + */ +__ALWAYS_STATIC_INLINE uint32_t __USAD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = (((x << 24) >> 24) - ((y << 24) >> 24)) & 0x000000FF; + s = (((x << 16) >> 24) - ((y << 16) >> 24)) & 0x000000FF; + t = (((x << 8) >> 24) - ((y << 8) >> 24)) & 0x000000FF; + u = (((x) >> 24) - ((y) >> 24)) & 0x000000FF; + + return (u + t + s + r); +} + +/** + \brief Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate. + \details This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values + of the differences to a 32-bit accumulate operand. + \param [in] x first four 8-bit operands of each subtraction. + \param [in] y second four 8-bit operands of each subtraction. + \param [in] sum accumulation value. + \return the sum of the absolute differences of the following bytes, added to the accumulation value: + the subtraction of the first bytes from each operand, in the first byte of the return value.\n + the subtraction of the second bytes of each operand, in the second byte of the return value.\n + the subtraction of the third bytes of each operand, in the third byte of the return value.\n + the subtraction of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + absdiff1 = val1[7:0] - val2[7:0] \n + absdiff2 = val1[15:8] - val2[15:8] \n + absdiff3 = val1[23:16] - val2[23:16] \n + absdiff4 = val1[31:24] - val2[31:24] \n + sum = absdiff1 + absdiff2 + absdiff3 + absdiff4 \n + res[31:0] = sum[31:0] + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __USADA8(uint32_t x, uint32_t y, uint32_t sum) +{ + int32_t r, s, t, u; + +#ifdef __cplusplus + r = (abs((long long)((x << 24) >> 24) - ((y << 24) >> 24))) & 0x000000FF; + s = (abs((long long)((x << 16) >> 24) - ((y << 16) >> 24))) & 0x000000FF; + t = (abs((long long)((x << 8) >> 24) - ((y << 8) >> 24))) & 0x000000FF; + u = (abs((long long)((x) >> 24) - ((y) >> 24))) & 0x000000FF; +#else + r = (abs(((x << 24) >> 24) - ((y << 24) >> 24))) & 0x000000FF; + s = (abs(((x << 16) >> 24) - ((y << 16) >> 24))) & 0x000000FF; + t = (abs(((x << 8) >> 24) - ((y << 8) >> 24))) & 0x000000FF; + u = (abs(((x) >> 24) - ((y) >> 24))) & 0x000000FF; +#endif + return (u + t + s + r + sum); +} + +/** + \brief Dual 16-bit saturating addition. + \details This function enables you to perform two 16-bit integer arithmetic additions in parallel, + saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the saturated addition of the low halfwords, in the low halfword of the return value.\n + the saturated addition of the high halfwords, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] + val2[15:0] \n + res[31:16] = val1[31:16] + val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __QADD16(uint32_t x, uint32_t y) +{ + int32_t r = 0, s = 0; + + r = __SSAT(((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((int32_t)x) >> 16) + (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturating addition. + \details This function enables you to perform two unsigned 16-bit integer additions, saturating + the results to the 16-bit unsigned integer range 0 < x < 2^16 - 1. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the saturated addition of the low halfwords, in the low halfword of the return value.\n + the saturated addition of the high halfwords, in the high halfword of the return value.\n + The results are saturated to the 16-bit unsigned integer range 0 < x < 2^16 - 1. + \remark + res[15:0] = val1[15:0] + val2[15:0] \n + res[31:16] = val1[31:16] + val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQADD16(uint32_t x, uint32_t y) +{ + int32_t r = 0, s = 0; + + r = __IUSAT((((x << 16) >> 16) + ((y << 16) >> 16)), 16) & 0x0000FFFF; + s = __IUSAT((((x) >> 16) + ((y) >> 16)), 16) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed addition. + \details This function enables you to perform two 16-bit signed integer additions. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the addition of the low halfwords in the low halfword of the return value.\n + the addition of the high halfwords in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] + val2[15:0] \n + res[31:16] = val1[31:16] + val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __SADD16(uint32_t x, uint32_t y) +{ + int32_t r = 0, s = 0; + + r = ((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF; + s = ((((int32_t)x) >> 16) + (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned addition + \details This function enables you to perform two 16-bit unsigned integer additions. + \param [in] x first two 16-bit summands for each addition. + \param [in] y second two 16-bit summands for each addition. + \return the addition of the low halfwords in the low halfword of the return value.\n + the addition of the high halfwords in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] + val2[15:0] \n + res[31:16] = val1[31:16] + val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __UADD16(uint32_t x, uint32_t y) +{ + int32_t r = 0, s = 0; + + r = (((x << 16) >> 16) + ((y << 16) >> 16)) & 0x0000FFFF; + s = (((x) >> 16) + ((y) >> 16)) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + + +/** + \brief Dual 16-bit signed addition with halved results. + \details This function enables you to perform two signed 16-bit integer additions, halving the results. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the halved addition of the low halfwords, in the low halfword of the return value.\n + the halved addition of the high halfwords, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] + val2[15:0]) >> 1 \n + res[31:16] = (val1[31:16] + val2[31:16]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHADD16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((int32_t)x) >> 16) + (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned addition with halved results. + \details This function enables you to perform two unsigned 16-bit integer additions, halving the results. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the halved addition of the low halfwords, in the low halfword of the return value.\n + the halved addition of the high halfwords, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] + val2[15:0]) >> 1 \n + res[31:16] = (val1[31:16] + val2[31:16]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHADD16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((x << 16) >> 16) + ((y << 16) >> 16)) >> 1) & 0x0000FFFF; + s = ((((x) >> 16) + ((y) >> 16)) >> 1) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Quad 8-bit signed addition with halved results. + \details This function enables you to perform four signed 8-bit integer additions, halving the results. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the halved addition of the first bytes from each operand, in the first byte of the return value.\n + the halved addition of the second bytes from each operand, in the second byte of the return value.\n + the halved addition of the third bytes from each operand, in the third byte of the return value.\n + the halved addition of the fourth bytes from each operand, in the fourth byte of the return value. + \remark + res[7:0] = (val1[7:0] + val2[7:0] ) >> 1 \n + res[15:8] = (val1[15:8] + val2[15:8] ) >> 1 \n + res[23:16] = (val1[23:16] + val2[23:16]) >> 1 \n + res[31:24] = (val1[31:24] + val2[31:24]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = (((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)) >> 1) & (int32_t)0x000000FF; + s = (((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)) >> 1) & (int32_t)0x000000FF; + t = (((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)) >> 1) & (int32_t)0x000000FF; + u = (((((int32_t)x) >> 24) + (((int32_t)y) >> 24)) >> 1) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned addition with halved results. + \details This function enables you to perform four unsigned 8-bit integer additions, halving the results. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the halved addition of the first bytes from each operand, in the first byte of the return value.\n + the halved addition of the second bytes from each operand, in the second byte of the return value.\n + the halved addition of the third bytes from each operand, in the third byte of the return value.\n + the halved addition of the fourth bytes from each operand, in the fourth byte of the return value. + \remark + res[7:0] = (val1[7:0] + val2[7:0] ) >> 1 \n + res[15:8] = (val1[15:8] + val2[15:8] ) >> 1 \n + res[23:16] = (val1[23:16] + val2[23:16]) >> 1 \n + res[31:24] = (val1[31:24] + val2[31:24]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = ((((x << 24) >> 24) + ((y << 24) >> 24)) >> 1) & 0x000000FF; + s = ((((x << 16) >> 24) + ((y << 16) >> 24)) >> 1) & 0x000000FF; + t = ((((x << 8) >> 24) + ((y << 8) >> 24)) >> 1) & 0x000000FF; + u = ((((x) >> 24) + ((y) >> 24)) >> 1) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Dual 16-bit saturating subtract. + \details This function enables you to perform two 16-bit integer subtractions in parallel, + saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the saturated subtraction of the low halfwords, in the low halfword of the return value.\n + the saturated subtraction of the high halfwords, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] - val2[15:0] \n + res[31:16] = val1[31:16] - val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __QSUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __SSAT(((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((int32_t)x) >> 16) - (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturating subtraction. + \details This function enables you to perform two unsigned 16-bit integer subtractions, + saturating the results to the 16-bit unsigned integer range 0 < x < 2^16 - 1. + \param [in] x first two 16-bit operands for each subtraction. + \param [in] y second two 16-bit operands for each subtraction. + \return the saturated subtraction of the low halfwords, in the low halfword of the return value.\n + the saturated subtraction of the high halfwords, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] - val2[15:0] \n + res[31:16] = val1[31:16] - val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQSUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __IUSAT((((x << 16) >> 16) - ((y << 16) >> 16)), 16) & 0x0000FFFF; + s = __IUSAT((((x) >> 16) - ((y) >> 16)), 16) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed subtraction. + \details This function enables you to perform two 16-bit signed integer subtractions. + \param [in] x first two 16-bit operands of each subtraction. + \param [in] y second two 16-bit operands of each subtraction. + \return the subtraction of the low halfword in the second operand from the low + halfword in the first operand, in the low halfword of the return value. \n + the subtraction of the high halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] - val2[15:0] \n + res[31:16] = val1[31:16] - val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __SSUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF; + s = ((((int32_t)x) >> 16) - (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned subtract. + \details This function enables you to perform two 16-bit unsigned integer subtractions. + \param [in] x first two 16-bit operands of each subtraction. + \param [in] y second two 16-bit operands of each subtraction. + \return the subtraction of the low halfword in the second operand from the low + halfword in the first operand, in the low halfword of the return value. \n + the subtraction of the high halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] - val2[15:0] \n + res[31:16] = val1[31:16] - val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __USUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((x << 16) >> 16) - ((y << 16) >> 16)) & 0x0000FFFF; + s = (((x) >> 16) - ((y) >> 16)) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed subtraction with halved results. + \details This function enables you to perform two signed 16-bit integer subtractions, halving the results. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the halved subtraction of the low halfwords, in the low halfword of the return value.\n + the halved subtraction of the high halfwords, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] - val2[15:0]) >> 1 \n + res[31:16] = (val1[31:16] - val2[31:16]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHSUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((int32_t)x) >> 16) - (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned subtraction with halved results. + \details This function enables you to perform two unsigned 16-bit integer subtractions, halving the results. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the halved subtraction of the low halfwords, in the low halfword of the return value.\n + the halved subtraction of the high halfwords, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] - val2[15:0]) >> 1 \n + res[31:16] = (val1[31:16] - val2[31:16]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHSUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((x << 16) >> 16) - ((y << 16) >> 16)) >> 1) & 0x0000FFFF; + s = ((((x) >> 16) - ((y) >> 16)) >> 1) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Quad 8-bit signed addition with halved results. + \details This function enables you to perform four signed 8-bit integer subtractions, halving the results. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the halved subtraction of the first bytes from each operand, in the first byte of the return value.\n + the halved subtraction of the second bytes from each operand, in the second byte of the return value.\n + the halved subtraction of the third bytes from each operand, in the third byte of the return value.\n + the halved subtraction of the fourth bytes from each operand, in the fourth byte of the return value. + \remark + res[7:0] = (val1[7:0] - val2[7:0] ) >> 1 \n + res[15:8] = (val1[15:8] - val2[15:8] ) >> 1 \n + res[23:16] = (val1[23:16] - val2[23:16]) >> 1 \n + res[31:24] = (val1[31:24] - val2[31:24]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHSUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = (((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)) >> 1) & (int32_t)0x000000FF; + s = (((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)) >> 1) & (int32_t)0x000000FF; + t = (((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)) >> 1) & (int32_t)0x000000FF; + u = (((((int32_t)x) >> 24) - (((int32_t)y) >> 24)) >> 1) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned subtraction with halved results. + \details This function enables you to perform four unsigned 8-bit integer subtractions, halving the results. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the halved subtraction of the first bytes from each operand, in the first byte of the return value.\n + the halved subtraction of the second bytes from each operand, in the second byte of the return value.\n + the halved subtraction of the third bytes from each operand, in the third byte of the return value.\n + the halved subtraction of the fourth bytes from each operand, in the fourth byte of the return value. + \remark + res[7:0] = (val1[7:0] - val2[7:0] ) >> 1 \n + res[15:8] = (val1[15:8] - val2[15:8] ) >> 1 \n + res[23:16] = (val1[23:16] - val2[23:16]) >> 1 \n + res[31:24] = (val1[31:24] - val2[31:24]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHSUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = ((((x << 24) >> 24) - ((y << 24) >> 24)) >> 1) & 0x000000FF; + s = ((((x << 16) >> 24) - ((y << 16) >> 24)) >> 1) & 0x000000FF; + t = ((((x << 8) >> 24) - ((y << 8) >> 24)) >> 1) & 0x000000FF; + u = ((((x) >> 24) - ((y) >> 24)) >> 1) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Dual 16-bit add and subtract with exchange. + \details This function enables you to exchange the halfwords of the one operand, + then add the high halfwords and subtract the low halfwords, + saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \param [in] x first operand for the subtraction in the low halfword, + and the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, + and the second operand for the addition in the low halfword. + \return the saturated subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the saturated addition of the high halfword in the first operand and the + low halfword in the second operand, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] - val2[31:16] \n + res[31:16] = val1[31:16] + val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __QASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __SSAT(((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturating addition and subtraction with exchange. + \details This function enables you to exchange the halfwords of the second operand and + perform one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, + saturating the results to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1. + \param [in] x first operand for the subtraction in the low halfword, + and the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, + and the second operand for the addition in the low halfword. + \return the saturated subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the saturated addition of the high halfword in the first operand and the + low halfword in the second operand, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1. + \remark + res[15:0] = val1[15:0] - val2[31:16] \n + res[31:16] = val1[31:16] + val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __IUSAT((((x << 16) >> 16) - ((y) >> 16)), 16) & 0x0000FFFF; + s = __IUSAT((((x) >> 16) + ((y << 16) >> 16)), 16) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit addition and subtraction with exchange. + \details It enables you to exchange the halfwords of the second operand, add the high halfwords + and subtract the low halfwords. + \param [in] x first operand for the subtraction in the low halfword, + and the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, + and the second operand for the addition in the low halfword. + \return the subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the addition of the high halfword in the first operand and the + low halfword in the second operand, in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] - val2[31:16] \n + res[31:16] = val1[31:16] + val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF; + s = ((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned addition and subtraction with exchange. + \details This function enables you to exchange the two halfwords of the second operand, + add the high halfwords and subtract the low halfwords. + \param [in] x first operand for the subtraction in the low halfword, + and the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, + and the second operand for the addition in the low halfword. + \return the subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the addition of the high halfword in the first operand and the + low halfword in the second operand, in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] - val2[31:16] \n + res[31:16] = val1[31:16] + val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __UASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((x << 16) >> 16) - ((y) >> 16)) & 0x0000FFFF; + s = (((x) >> 16) + ((y << 16) >> 16)) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed addition and subtraction with halved results. + \details This function enables you to exchange the two halfwords of one operand, perform one + signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results. + \param [in] x first 16-bit operands. + \param [in] y second 16-bit operands. + \return the halved subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the halved addition of the low halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] - val2[31:16]) >> 1 \n + res[31:16] = (val1[31:16] + val2[15:0]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned addition and subtraction with halved results and exchange. + \details This function enables you to exchange the halfwords of the second operand, + add the high halfwords and subtract the low halfwords, halving the results. + \param [in] x first operand for the subtraction in the low halfword, and + the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, and + the second operand for the addition in the low halfword. + \return the halved subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the halved addition of the low halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] - val2[31:16]) >> 1 \n + res[31:16] = (val1[31:16] + val2[15:0]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((x << 16) >> 16) - ((y) >> 16)) >> 1) & 0x0000FFFF; + s = ((((x) >> 16) + ((y << 16) >> 16)) >> 1) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit subtract and add with exchange. + \details This function enables you to exchange the halfwords of one operand, + then subtract the high halfwords and add the low halfwords, + saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \param [in] x first operand for the addition in the low halfword, + and the first operand for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, + and the second operand for the subtraction in the low halfword. + \return the saturated addition of the low halfword of the first operand and the high + halfword of the second operand, in the low halfword of the return value.\n + the saturated subtraction of the low halfword of the second operand from the + high halfword of the first operand, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] + val2[31:16] \n + res[31:16] = val1[31:16] - val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __QSAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __SSAT(((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturating subtraction and addition with exchange. + \details This function enables you to exchange the halfwords of the second operand and perform + one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating + the results to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1. + \param [in] x first operand for the addition in the low halfword, + and the first operand for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, + and the second operand for the subtraction in the low halfword. + \return the saturated addition of the low halfword of the first operand and the high + halfword of the second operand, in the low halfword of the return value.\n + the saturated subtraction of the low halfword of the second operand from the + high halfword of the first operand, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1. + \remark + res[15:0] = val1[15:0] + val2[31:16] \n + res[31:16] = val1[31:16] - val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQSAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __IUSAT((((x << 16) >> 16) + ((y) >> 16)), 16) & 0x0000FFFF; + s = __IUSAT((((x) >> 16) - ((y << 16) >> 16)), 16) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit unsigned subtract and add with exchange. + \details This function enables you to exchange the halfwords of the second operand, + subtract the high halfwords and add the low halfwords. + \param [in] x first operand for the addition in the low halfword, + and the first operand for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, + and the second operand for the subtraction in the low halfword. + \return the addition of the low halfword of the first operand and the high + halfword of the second operand, in the low halfword of the return value.\n + the subtraction of the low halfword of the second operand from the + high halfword of the first operand, in the high halfword of the return value.\n + \remark + res[15:0] = val1[15:0] + val2[31:16] \n + res[31:16] = val1[31:16] - val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __USAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((x << 16) >> 16) + ((y) >> 16)) & 0x0000FFFF; + s = (((x) >> 16) - ((y << 16) >> 16)) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed subtraction and addition with exchange. + \details This function enables you to exchange the two halfwords of one operand and perform one + 16-bit integer subtraction and one 16-bit addition. + \param [in] x first operand for the addition in the low halfword, and the first operand + for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, and the second + operand for the subtraction in the low halfword. + \return the addition of the low halfword of the first operand and the high + halfword of the second operand, in the low halfword of the return value.\n + the subtraction of the low halfword of the second operand from the + high halfword of the first operand, in the high halfword of the return value.\n + \remark + res[15:0] = val1[15:0] + val2[31:16] \n + res[31:16] = val1[31:16] - val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SSAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF; + s = ((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + + +/** + \brief Dual 16-bit signed subtraction and addition with halved results. + \details This function enables you to exchange the two halfwords of one operand, perform one signed + 16-bit integer subtraction and one signed 16-bit addition, and halve the results. + \param [in] x first 16-bit operands. + \param [in] y second 16-bit operands. + \return the halved addition of the low halfword in the first operand and the + high halfword in the second operand, in the low halfword of the return value.\n + the halved subtraction of the low halfword in the second operand from the + high halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] + val2[31:16]) >> 1 \n + res[31:16] = (val1[31:16] - val2[15:0]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHSAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned subtraction and addition with halved results and exchange. + \details This function enables you to exchange the halfwords of the second operand, + subtract the high halfwords and add the low halfwords, halving the results. + \param [in] x first operand for the addition in the low halfword, and + the first operand for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, and + the second operand for the subtraction in the low halfword. + \return the halved addition of the low halfword in the first operand and the + high halfword in the second operand, in the low halfword of the return value.\n + the halved subtraction of the low halfword in the second operand from the + high halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] + val2[31:16]) >> 1 \n + res[31:16] = (val1[31:16] - val2[15:0]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHSAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((x << 16) >> 16) + ((y) >> 16)) >> 1) & 0x0000FFFF; + s = ((((x) >> 16) - ((y << 16) >> 16)) >> 1) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed multiply with exchange returning difference. + \details This function enables you to perform two 16-bit signed multiplications, subtracting + one of the products from the other. The halfwords of the second operand are exchanged + before performing the arithmetic. This produces top * bottom and bottom * top multiplication. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \return the difference of the products of the two 16-bit signed multiplications. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[31:0] = p1 - p2 + */ +__ALWAYS_STATIC_INLINE uint32_t __SMUSDX(uint32_t x, uint32_t y) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)))); +} + +/** + \brief Sum of dual 16-bit signed multiply with exchange. + \details This function enables you to perform two 16-bit signed multiplications with exchanged + halfwords of the second operand, adding the products together. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \return the sum of the products of the two 16-bit signed multiplications with exchanged halfwords of the second operand. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[31:0] = p1 + p2 + */ +__ALWAYS_STATIC_INLINE uint32_t __SMUADX(uint32_t x, uint32_t y) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)))); +} + + +/** + \brief Saturating add. + \details This function enables you to obtain the saturating add of two integers. + \param [in] x first summand of the saturating add operation. + \param [in] y second summand of the saturating add operation. + \return the saturating addition of val1 and val2. + \remark + res[31:0] = SAT(val1 + SAT(val2)) + */ +__ALWAYS_STATIC_INLINE int32_t __QADD(int32_t x, int32_t y) +{ + int32_t result; + + if (y >= 0) { + if ((int32_t)((uint32_t)x + (uint32_t)y) >= x) { + result = x + y; + } else { + result = 0x7FFFFFFF; + } + } else { + if ((int32_t)((uint32_t)x + (uint32_t)y) < x) { + result = x + y; + } else { + result = 0x80000000; + } + } + + return result; +} + +/** + \brief Saturating subtract. + \details This function enables you to obtain the saturating add of two integers. + \param [in] x first summand of the saturating add operation. + \param [in] y second summand of the saturating add operation. + \return the saturating addition of val1 and val2. + \remark + res[31:0] = SAT(val1 - SAT(val2)) + */ +__ALWAYS_STATIC_INLINE int32_t __QSUB(int32_t x, int32_t y) +{ + long tmp; + int32_t result; + + tmp = (long)x - (long)y; + + if (tmp > 0x7fffffff) { + tmp = 0x7fffffff; + } else if (tmp < (-2147483647 - 1)) { + tmp = -2147483647 - 1; + } + + result = tmp; + return result; +} + +/** + \brief Dual 16-bit signed multiply with single 32-bit accumulator. + \details This function enables you to perform two signed 16-bit multiplications, + adding both results to a 32-bit accumulate operand. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the product of each multiplication added to the accumulate value, as a 32-bit integer. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[31:0] = p1 + p2 + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SMLAD(uint32_t x, uint32_t y, uint32_t sum) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) + + (((int32_t)sum)))); +} + +/** + \brief Pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator. + \details This function enables you to perform two signed 16-bit multiplications with exchanged + halfwords of the second operand, adding both results to a 32-bit accumulate operand. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the product of each multiplication with exchanged halfwords of the second + operand added to the accumulate value, as a 32-bit integer. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[31:0] = p1 + p2 + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SMLADX(uint32_t x, uint32_t y, uint32_t sum) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) + + (((int32_t)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with exchange subtract with 32-bit accumulate. + \details This function enables you to perform two 16-bit signed multiplications, take the + difference of the products, subtracting the high halfword product from the low + halfword product, and add the difference to a 32-bit accumulate operand. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the difference of the product of each multiplication, added to the accumulate value. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[31:0] = p1 - p2 + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SMLSD(uint32_t x, uint32_t y, uint32_t sum) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) + + (((int32_t)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with exchange subtract with 32-bit accumulate. + \details This function enables you to exchange the halfwords in the second operand, then perform two 16-bit + signed multiplications. The difference of the products is added to a 32-bit accumulate operand. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the difference of the product of each multiplication, added to the accumulate value. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[31:0] = p1 - p2 + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SMLSDX(uint32_t x, uint32_t y, uint32_t sum) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) + + (((int32_t)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with single 64-bit accumulator. + \details This function enables you to perform two signed 16-bit multiplications, adding both results + to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. + This overflow is not detected if it occurs. Instead, the result wraps around modulo2^64. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the product of each multiplication added to the accumulate value. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + sum = p1 + p2 + val3[63:32][31:0] \n + res[63:32] = sum[63:32] \n + res[31:0] = sum[31:0] + */ +__ALWAYS_STATIC_INLINE unsigned long __SMLALD(uint32_t x, uint32_t y, unsigned long sum) +{ + return ((unsigned long)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) + + (((unsigned long)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with exchange with single 64-bit accumulator. + \details This function enables you to exchange the halfwords of the second operand, and perform two + signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow + is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. + Instead, the result wraps around modulo2^64. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the product of each multiplication added to the accumulate value. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + sum = p1 + p2 + val3[63:32][31:0] \n + res[63:32] = sum[63:32] \n + res[31:0] = sum[31:0] + */ +__ALWAYS_STATIC_INLINE unsigned long __SMLALDX(uint32_t x, uint32_t y, unsigned long sum) +{ + return ((unsigned long)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) + + (((unsigned long)sum)))); +} + +/** + \brief dual 16-bit signed multiply subtract with 64-bit accumulate. + \details This function It enables you to perform two 16-bit signed multiplications, take the difference + of the products, subtracting the high halfword product from the low halfword product, and add the + difference to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the + subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not + detected. Instead, the result wraps round to modulo2^64. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the difference of the product of each multiplication, added to the accumulate value. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[63:32][31:0] = p1 - p2 + val3[63:32][31:0] + */ +__ALWAYS_STATIC_INLINE unsigned long __SMLSLD(uint32_t x, uint32_t y, unsigned long sum) +{ + return ((unsigned long)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) + + (((unsigned long)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with exchange subtract with 64-bit accumulate. + \details This function enables you to exchange the halfwords of the second operand, perform two 16-bit multiplications, + adding the difference of the products to a 64-bit accumulate operand. Overflow cannot occur during the + multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow + is not detected. Instead, the result wraps round to modulo2^64. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the difference of the product of each multiplication, added to the accumulate value. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[63:32][31:0] = p1 - p2 + val3[63:32][31:0] + */ +__ALWAYS_STATIC_INLINE unsigned long __SMLSLDX(uint32_t x, uint32_t y, unsigned long sum) +{ + return ((unsigned long)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) + + (((unsigned long)sum)))); +} + +/** + \brief 32-bit signed multiply with 32-bit truncated accumulator. + \details This function enables you to perform a signed 32-bit multiplications, adding the most + significant 32 bits of the 64-bit result to a 32-bit accumulate operand. + \param [in] x first operand for multiplication. + \param [in] y second operand for multiplication. + \param [in] sum accumulate value. + \return the product of multiplication (most significant 32 bits) is added to the accumulate value, as a 32-bit integer. + \remark + p = val1 * val2 \n + res[31:0] = p[63:32] + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SMMLA(int32_t x, int32_t y, int32_t sum) +{ + return (uint32_t)((int32_t)((long)((long)x * (long)y) >> 32) + sum); +} + +/** + \brief Sum of dual 16-bit signed multiply. + \details This function enables you to perform two 16-bit signed multiplications, adding the products together. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \return the sum of the products of the two 16-bit signed multiplications. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[31:0] = p1 + p2 + */ +__ALWAYS_STATIC_INLINE uint32_t __SMUAD(uint32_t x, uint32_t y) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)))); +} + +/** + \brief Dual 16-bit signed multiply returning difference. + \details This function enables you to perform two 16-bit signed multiplications, taking the difference + of the products by subtracting the high halfword product from the low halfword product. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \return the difference of the products of the two 16-bit signed multiplications. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[31:0] = p1 - p2 + */ +__ALWAYS_STATIC_INLINE uint32_t __SMUSD(uint32_t x, uint32_t y) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)))); +} + +/** + \brief Dual extracted 8-bit to 16-bit signed addition. + \details This function enables you to extract two 8-bit values from the second operand (at bit positions + [7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the first operand. + \param [in] x values added to the sign-extended to 16-bit values. + \param [in] y two 8-bit values to be extracted and sign-extended. + \return the addition of val1 and val2, where the 8-bit values in val2[7:0] and + val2[23:16] have been extracted and sign-extended prior to the addition. + \remark + res[15:0] = val1[15:0] + SignExtended(val2[7:0]) \n + res[31:16] = val1[31:16] + SignExtended(val2[23:16]) + */ +__ALWAYS_STATIC_INLINE uint32_t __SXTAB16(uint32_t x, uint32_t y) +{ + return ((uint32_t)((((((int32_t)y << 24) >> 24) + (((int32_t)x << 16) >> 16)) & (int32_t)0x0000FFFF) | + (((((int32_t)y << 8) >> 8) + (((int32_t)x >> 16) << 16)) & (int32_t)0xFFFF0000))); +} + +/** + \brief Extracted 16-bit to 32-bit unsigned addition. + \details This function enables you to extract two 8-bit values from one operand, zero-extend + them to 16 bits each, and add the results to two 16-bit values from another operand. + \param [in] x values added to the zero-extended to 16-bit values. + \param [in] y two 8-bit values to be extracted and zero-extended. + \return the addition of val1 and val2, where the 8-bit values in val2[7:0] and + val2[23:16] have been extracted and zero-extended prior to the addition. + \remark + res[15:0] = ZeroExt(val2[7:0] to 16 bits) + val1[15:0] \n + res[31:16] = ZeroExt(val2[31:16] to 16 bits) + val1[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __UXTAB16(uint32_t x, uint32_t y) +{ + return ((uint32_t)(((((y << 24) >> 24) + ((x << 16) >> 16)) & 0x0000FFFF) | + ((((y << 8) >> 8) + ((x >> 16) << 16)) & 0xFFFF0000))); +} + +/** + \brief Dual extract 8-bits and sign extend each to 16-bits. + \details This function enables you to extract two 8-bit values from an operand and sign-extend them to 16 bits each. + \param [in] x two 8-bit values in val[7:0] and val[23:16] to be sign-extended. + \return the 8-bit values sign-extended to 16-bit values.\n + sign-extended value of val[7:0] in the low halfword of the return value.\n + sign-extended value of val[23:16] in the high halfword of the return value. + \remark + res[15:0] = SignExtended(val[7:0]) \n + res[31:16] = SignExtended(val[23:16]) + */ +__ALWAYS_STATIC_INLINE uint32_t __SXTB16(uint32_t x) +{ + return ((uint32_t)(((((int32_t)x << 24) >> 24) & (int32_t)0x0000FFFF) | + ((((int32_t)x << 8) >> 8) & (int32_t)0xFFFF0000))); +} + +/** + \brief Dual extract 8-bits and zero-extend to 16-bits. + \details This function enables you to extract two 8-bit values from an operand and zero-extend them to 16 bits each. + \param [in] x two 8-bit values in val[7:0] and val[23:16] to be zero-extended. + \return the 8-bit values sign-extended to 16-bit values.\n + sign-extended value of val[7:0] in the low halfword of the return value.\n + sign-extended value of val[23:16] in the high halfword of the return value. + \remark + res[15:0] = SignExtended(val[7:0]) \n + res[31:16] = SignExtended(val[23:16]) + */ +__ALWAYS_STATIC_INLINE uint32_t __UXTB16(uint32_t x) +{ + return ((uint32_t)((((x << 24) >> 24) & 0x0000FFFF) | + (((x << 8) >> 8) & 0xFFFF0000))); +} +#endif + +#endif /* _CSI_RV32_GCC_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/csi_rv_common.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/csi_rv_common.h new file mode 100644 index 00000000..4a57b718 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/csi_rv_common.h @@ -0,0 +1,126 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CSI_RV_COMMON_H__ +#define __CSI_RV_COMMON_H__ + +#include +#include + +#ifndef __ASM +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#endif + +#ifndef __INLINE +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#endif + +#ifndef __ALWAYS_STATIC_INLINE +#define __ALWAYS_STATIC_INLINE __attribute__((always_inline)) static inline +#endif + +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif + +#ifndef __NO_RETURN +#define __NO_RETURN __attribute__((__noreturn__)) +#endif + +#ifndef __USED +#define __USED __attribute__((used)) +#endif + +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif + +#ifndef __PACKED +#define __PACKED __attribute__((packed, aligned(1))) +#endif + +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif + +#ifndef __PACKED_UNION +#define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif + +#ifdef __ASSEMBLY__ +#define __ASM_STR(x) x +#else +#define __ASM_STR(x) #x +#endif + +#ifndef __ASSEMBLY__ +#define rv_csr_read(csr) \ + ({ \ + register unsigned long __v; \ + __asm__ __volatile__("csrr %0, " __ASM_STR(csr) \ + : "=r"(__v) \ + : \ + : "memory"); \ + __v; \ + }) + +#define rv_csr_write(csr, val) \ + ({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__("csrw " __ASM_STR(csr) ", %0" \ + : \ + : "rK"(__v) \ + : "memory"); \ + }) + +#define rv_csr_read_set(csr, val) \ + ({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__("csrrs %0, " __ASM_STR(csr) ", %1" \ + : "=r"(__v) : "rK"(__v) \ + : "memory"); \ + __v; \ + }) + +#define rv_csr_set(csr, val) \ + ({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__("csrs " __ASM_STR(csr) ", %0" \ + : : "rK"(__v) \ + : "memory"); \ + }) + +#define rv_csr_read_clear(csr, val) \ + ({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__("csrrc %0, " __ASM_STR(csr) ", %1" \ + : "=r"(__v) : "rK"(__v) \ + : "memory"); \ + __v; \ + }) + +#define rv_csr_clear(csr, val) \ + ({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__("csrc " __ASM_STR(csr) ", %0" \ + : : "rK"(__v) \ + : "memory"); \ + }) +#endif + +#endif /* __CSI_RV_COMMON_H__ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/csi_rv_encoding.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/csi_rv_encoding.h new file mode 100644 index 00000000..82df61a9 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/csi_rv_encoding.h @@ -0,0 +1,716 @@ +/* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CSI_RV_ENCODING_H__ +#define __CSI_RV_ENCODING_H__ + +/* ===== User-level CSRs ===== */ + +/* User Trap Setup (N-extension) */ +#define CSR_USTATUS 0x000 +#define CSR_UIE 0x004 +#define CSR_UTVEC 0x005 + +/* User Trap Handling (N-extension) */ +#define CSR_USCRATCH 0x040 +#define CSR_UEPC 0x041 +#define CSR_UCAUSE 0x042 +#define CSR_UTVAL 0x043 +#define CSR_UIP 0x044 + +/* User Floating-point CSRs */ +#define CSR_FFLAGS 0x001 +#define CSR_FRM 0x002 +#define CSR_FCSR 0x003 + +/* User Vector CSRs */ +#define CSR_VSTART 0x008 +#define CSR_VXSAT 0x009 +#define CSR_VXRM 0x00A +#define CSR_VCSR 0x00F +#define CSR_VL 0xC20 +#define CSR_VTYPE 0xC21 +#define CSR_VLENB 0xC22 + +/* User Counters/Timers */ +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f + +/* ===== Supervisor-level CSRs ===== */ + +/* Supervisor Trap Setup */ +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 + +/* Supervisor Counter Overflow CSR */ +#define CSR_SCOUNTOVF 0xda0 + +/* Supervisor Configuration */ +#define CSR_SENVCFG 0x10a + +/* Supervisor Trap Handling */ +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 + +/* Supervisor CLIC CSRs */ +#define CSR_STVT 0x107 +#define CSR_SNXTI 0x145 +#define CSR_SINTSTATUS 0xDB1 +#define CSR_SINTTHRESH 0x147 +#define CSR_SSCRATCHCSW 0x148 +#define CSR_SSCRATCHCSWL 0x149 + +/* Sstc extension */ +#define CSR_STIMECMP 0x14D +#define CSR_STIMECMPH 0x15D + +/* Supervisor Protection and Translation */ +#define CSR_SATP 0x180 + +/* Supervisor Debug/Trace */ +#define CSR_SCONTEXT 0x5a8 + +/* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ +#define CSR_SISELECT 0x150 +#define CSR_SIREG 0x151 +#define CSR_SIREG2 0x152 +#define CSR_SIREG3 0x153 +#define CSR_SIREG4 0x155 +#define CSR_SIREG5 0x156 +#define CSR_SIREG6 0x157 + +/* Supervisor-Level Interrupts (AIA) */ +#define CSR_STOPEI 0x15c +#define CSR_STOPI 0xdb0 + +/* Supervisor-Level High-Half CSRs (AIA) */ +#define CSR_SIEH 0x114 +#define CSR_SIPH 0x154 + +/* Supervisor stateen CSRs */ +#define CSR_SSTATEEN0 0x10C +#define CSR_SSTATEEN1 0x10D +#define CSR_SSTATEEN2 0x10E +#define CSR_SSTATEEN3 0x10F + +/* ===== Hypervisor-level CSRs ===== */ + +/* Hypervisor Trap Setup (H-extension) */ +#define CSR_HSTATUS 0x600 +#define CSR_HEDELEG 0x602 +#define CSR_HIDELEG 0x603 +#define CSR_HIE 0x604 +#define CSR_HCOUNTEREN 0x606 +#define CSR_HGEIE 0x607 + +/* Hypervisor Configuration */ +#define CSR_HENVCFG 0x60a +#define CSR_HENVCFGH 0x61a + +/* Hypervisor Trap Handling (H-extension) */ +#define CSR_HTVAL 0x643 +#define CSR_HIP 0x644 +#define CSR_HVIP 0x645 +#define CSR_HTINST 0x64a +#define CSR_HGEIP 0xe12 + +/* Hypervisor Protection and Translation (H-extension) */ +#define CSR_HGATP 0x680 + +/* Hypervisor Counter/Timer Virtualization Registers (H-extension) */ +#define CSR_HTIMEDELTA 0x605 +#define CSR_HTIMEDELTAH 0x615 + +/* Virtual Supervisor Registers (H-extension) */ +#define CSR_VSSTATUS 0x200 +#define CSR_VSIE 0x204 +#define CSR_VSTVEC 0x205 +#define CSR_VSSCRATCH 0x240 +#define CSR_VSEPC 0x241 +#define CSR_VSCAUSE 0x242 +#define CSR_VSTVAL 0x243 +#define CSR_VSIP 0x244 +#define CSR_VSATP 0x280 + +/* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ +#define CSR_HVIEN 0x608 +#define CSR_HVICTL 0x609 +#define CSR_HVIPRIO1 0x646 +#define CSR_HVIPRIO2 0x647 + +/* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */ +#define CSR_VSISELECT 0x250 +#define CSR_VSIREG 0x251 + +/* VS-Level Interrupts (H-extension with AIA) */ +#define CSR_VSTOPEI 0x25c +#define CSR_VSTOPI 0xeb0 + +/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ +#define CSR_HIDELEGH 0x613 +#define CSR_HVIENH 0x618 +#define CSR_HVIPH 0x655 +#define CSR_HVIPRIO1H 0x656 +#define CSR_HVIPRIO2H 0x657 +#define CSR_VSIEH 0x214 +#define CSR_VSIPH 0x254 + +/* Hypervisor stateen CSRs */ +#define CSR_HSTATEEN0 0x60C +#define CSR_HSTATEEN0H 0x61C +#define CSR_HSTATEEN1 0x60D +#define CSR_HSTATEEN1H 0x61D +#define CSR_HSTATEEN2 0x60E +#define CSR_HSTATEEN2H 0x61E +#define CSR_HSTATEEN3 0x60F +#define CSR_HSTATEEN3H 0x61F + +/* ===== Machine-level CSRs ===== */ + +/* Machine Information Registers */ +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_MCONFIGPTR 0xf15 + +/* Machine Trap Setup */ +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MSTATUSH 0x310 + +/* Machine Configuration */ +#define CSR_MENVCFG 0x30a +#define CSR_MENVCFGH 0x31a + +/* Machine Trap Handling */ +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MIP 0x344 +#define CSR_MTINST 0x34a +#define CSR_MTVAL2 0x34b + +/* Machine CLIC CSRs */ +#define CSR_MTVT 0x307 +#define CSR_MNXTI 0x345 +#define CSR_MINTSTATUS 0xFB1 +#define CSR_MINTTHRESH 0x347 +#define CSR_MSCRATCHCSW 0x348 +#define CSR_MSCRATCHCSWL 0x349 + +/* Machine Memory Protection */ +#define CSR_PMPCFG0 0x3a0 +#define CSR_PMPCFG1 0x3a1 +#define CSR_PMPCFG2 0x3a2 +#define CSR_PMPCFG3 0x3a3 +#define CSR_PMPCFG4 0x3a4 +#define CSR_PMPCFG5 0x3a5 +#define CSR_PMPCFG6 0x3a6 +#define CSR_PMPCFG7 0x3a7 +#define CSR_PMPCFG8 0x3a8 +#define CSR_PMPCFG9 0x3a9 +#define CSR_PMPCFG10 0x3aa +#define CSR_PMPCFG11 0x3ab +#define CSR_PMPCFG12 0x3ac +#define CSR_PMPCFG13 0x3ad +#define CSR_PMPCFG14 0x3ae +#define CSR_PMPCFG15 0x3af +#define CSR_PMPADDR0 0x3b0 +#define CSR_PMPADDR1 0x3b1 +#define CSR_PMPADDR2 0x3b2 +#define CSR_PMPADDR3 0x3b3 +#define CSR_PMPADDR4 0x3b4 +#define CSR_PMPADDR5 0x3b5 +#define CSR_PMPADDR6 0x3b6 +#define CSR_PMPADDR7 0x3b7 +#define CSR_PMPADDR8 0x3b8 +#define CSR_PMPADDR9 0x3b9 +#define CSR_PMPADDR10 0x3ba +#define CSR_PMPADDR11 0x3bb +#define CSR_PMPADDR12 0x3bc +#define CSR_PMPADDR13 0x3bd +#define CSR_PMPADDR14 0x3be +#define CSR_PMPADDR15 0x3bf +#define CSR_PMPADDR16 0x3c0 +#define CSR_PMPADDR17 0x3c1 +#define CSR_PMPADDR18 0x3c2 +#define CSR_PMPADDR19 0x3c3 +#define CSR_PMPADDR20 0x3c4 +#define CSR_PMPADDR21 0x3c5 +#define CSR_PMPADDR22 0x3c6 +#define CSR_PMPADDR23 0x3c7 +#define CSR_PMPADDR24 0x3c8 +#define CSR_PMPADDR25 0x3c9 +#define CSR_PMPADDR26 0x3ca +#define CSR_PMPADDR27 0x3cb +#define CSR_PMPADDR28 0x3cc +#define CSR_PMPADDR29 0x3cd +#define CSR_PMPADDR30 0x3ce +#define CSR_PMPADDR31 0x3cf +#define CSR_PMPADDR32 0x3d0 +#define CSR_PMPADDR33 0x3d1 +#define CSR_PMPADDR34 0x3d2 +#define CSR_PMPADDR35 0x3d3 +#define CSR_PMPADDR36 0x3d4 +#define CSR_PMPADDR37 0x3d5 +#define CSR_PMPADDR38 0x3d6 +#define CSR_PMPADDR39 0x3d7 +#define CSR_PMPADDR40 0x3d8 +#define CSR_PMPADDR41 0x3d9 +#define CSR_PMPADDR42 0x3da +#define CSR_PMPADDR43 0x3db +#define CSR_PMPADDR44 0x3dc +#define CSR_PMPADDR45 0x3dd +#define CSR_PMPADDR46 0x3de +#define CSR_PMPADDR47 0x3df +#define CSR_PMPADDR48 0x3e0 +#define CSR_PMPADDR49 0x3e1 +#define CSR_PMPADDR50 0x3e2 +#define CSR_PMPADDR51 0x3e3 +#define CSR_PMPADDR52 0x3e4 +#define CSR_PMPADDR53 0x3e5 +#define CSR_PMPADDR54 0x3e6 +#define CSR_PMPADDR55 0x3e7 +#define CSR_PMPADDR56 0x3e8 +#define CSR_PMPADDR57 0x3e9 +#define CSR_PMPADDR58 0x3ea +#define CSR_PMPADDR59 0x3eb +#define CSR_PMPADDR60 0x3ec +#define CSR_PMPADDR61 0x3ed +#define CSR_PMPADDR62 0x3ee +#define CSR_PMPADDR63 0x3ef + +/* Machine Counters/Timers */ +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f + +/* Machine Counter Setup */ +#define CSR_MCOUNTINHIBIT 0x320 +#define CSR_MCYCLECFG 0x321 +#define CSR_MINSTRETCFG 0x322 +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f + +/* For RV32 */ +#define CSR_MCYCLECFGH 0x721 +#define CSR_MINSTRETCFGH 0x722 +#define CSR_MHPMEVENT3H 0x723 +#define CSR_MHPMEVENT4H 0x724 +#define CSR_MHPMEVENT5H 0x725 +#define CSR_MHPMEVENT6H 0x726 +#define CSR_MHPMEVENT7H 0x727 +#define CSR_MHPMEVENT8H 0x728 +#define CSR_MHPMEVENT9H 0x729 +#define CSR_MHPMEVENT10H 0x72a +#define CSR_MHPMEVENT11H 0x72b +#define CSR_MHPMEVENT12H 0x72c +#define CSR_MHPMEVENT13H 0x72d +#define CSR_MHPMEVENT14H 0x72e +#define CSR_MHPMEVENT15H 0x72f +#define CSR_MHPMEVENT16H 0x730 +#define CSR_MHPMEVENT17H 0x731 +#define CSR_MHPMEVENT18H 0x732 +#define CSR_MHPMEVENT19H 0x733 +#define CSR_MHPMEVENT20H 0x734 +#define CSR_MHPMEVENT21H 0x735 +#define CSR_MHPMEVENT22H 0x736 +#define CSR_MHPMEVENT23H 0x737 +#define CSR_MHPMEVENT24H 0x738 +#define CSR_MHPMEVENT25H 0x739 +#define CSR_MHPMEVENT26H 0x73a +#define CSR_MHPMEVENT27H 0x73b +#define CSR_MHPMEVENT28H 0x73c +#define CSR_MHPMEVENT29H 0x73d +#define CSR_MHPMEVENT30H 0x73e +#define CSR_MHPMEVENT31H 0x73f + +/* Machine Security Configuration CSR (mseccfg) */ +#define CSR_MSECCFG 0x747 +#define CSR_MSECCFGH 0x757 + +/* Debug/Trace Registers */ +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_TINFO 0x7a4 +#define CSR_TCONTROL 0x7a5 +#define CSR_MCONTEXT 0x7a8 + +/* Debug Mode Registers */ +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH0 0x7b2 +#define CSR_DSCRATCH1 0x7b3 + +/* Machine-Level Window to Indirectly Accessed Registers */ +#define CSR_MISELECT 0x350 +#define CSR_MIREG 0x351 +#define CSR_MIREG2 0x352 +#define CSR_MIREG3 0x353 +#define CSR_MIREG4 0x355 +#define CSR_MIREG5 0x356 +#define CSR_MIREG6 0x357 + +/* Machine-Level Interrupts (AIA) */ +#define CSR_MTOPEI 0x35c +#define CSR_MTOPI 0xfb0 + +/* Virtual Interrupts for Supervisor Level (AIA) */ +#define CSR_MVIEN 0x308 +#define CSR_MVIP 0x309 + +/* Smstateen extension registers */ +/* Machine stateen CSRs */ +#define CSR_MSTATEEN0 0x30C +#define CSR_MSTATEEN0H 0x31C +#define CSR_MSTATEEN1 0x30D +#define CSR_MSTATEEN1H 0x31D +#define CSR_MSTATEEN2 0x30E +#define CSR_MSTATEEN2H 0x31E +#define CSR_MSTATEEN3 0x30F +#define CSR_MSTATEEN3H 0x31F + +/* Machine-Level High-Half CSRs (AIA) */ +#define CSR_MIDELEGH 0x313 +#define CSR_MIEH 0x314 +#define CSR_MVIENH 0x318 +#define CSR_MVIPH 0x319 +#define CSR_MIPH 0x354 + +/* XuanTie custom */ +/* Machine-Level XuanTie custom CSRs */ +#define CSR_MXSTATUS 0x7c0 +#define CSR_MHCR 0x7c1 +#define CSR_MCOR 0x7c2 +#define CSR_MCCR2 0x7c3 +#define CSR_MCER2 0x7c4 +#define CSR_MHINT 0x7c5 +#define CSR_MRMR 0x7c6 +#define CSR_MRVBR 0x7c7 +#define CSR_MCER 0x7c8 +#define CSR_MCOUNTERWEN 0x7c9 +#define CSR_MHINT2 0x7cc +#define CSR_MHINT3 0x7cd +#define CSR_MHINT4 0x7ce +#define CSR_MHPMEVENT0 0x7e0 +#define CSR_MHPMEVENT2 0x7e1 +#define CSR_MHPMCR 0x7f0 +#define CSR_MHPMSR 0x7f1 +#define CSR_MHPMER 0x7f2 +#define CSR_MSMPR 0x7f3 +#define CSR_MZONEID 0x7f5 +#define CSR_MLLCPID 0x7f6 +#define CSR_MLLWP 0x7f7 + +#define CSR_MCINS 0x7d2 +#define CSR_MCINDEX 0x7d3 +#define CSR_MCDATA0 0x7d4 +#define CSR_MCDATA1 0x7d5 +#define CSR_MEICR 0x7d6 +#define CSR_MEICR2 0x7d7 +#define CSR_MBEADDR 0x7d8 + +#define CSR_MCPUID 0xfc0 +#define CSR_MAPBADDR 0xfc1 + +#define CSR_MHALTCAUSE 0xfe0 +#define CSR_MDBGINFO 0xfe1 +#define CSR_MPCFIFO 0xfe2 +#define CSR_MDBGINFO2 0xfe3 + +#define CSR_MNASTATUS 0x8000000000000210 + +#define CSR_MRPLCNTLST 0xbd8 +#define CSR_MCACHELOCK 0xbd9 +#define CSR_MCACHERPLPRI0 0xbda +#define CSR_MCACHERPLPRI1 0xbdb +#define CSR_MCACHERPLPRI2 0xbdc +#define CSR_MCACHERPLPRI3 0xbdd +#define CSR_MCACHERPLPRI4 0xbde +#define CSR_MCACHERPLPRI5 0xbdf + +/* Supervisor-Level XuanTie custom CSRs */ +#define CSR_SXSTATUS 0x5c0 +#define CSR_SHCR 0x5c1 +#define CSR_SCER2 0x5c2 +#define CSR_SCER 0x5c3 +#define CSR_SHINT 0x5c6 +#define CSR_SHINT2 0x5c7 +#define CSR_SHPMINHIBIT 0x5c8 +#define CSR_SHPMCR 0x5c9 +#define CSR_SHPMSR 0x5ca +#define CSR_SHPMER 0x5cb +#define CSR_SL2PID 0x5cc +#define CSR_SL2WP 0x5cd +#define CSR_SBEADDR 0x5d0 +#define CSR_SSBEPA 0x5d1 +#define CSR_SSBEPA2 0x5d2 +#define CSR_SCYCLE 0x5e0 +#define CSR_SINSTRET 0x5e2 +#define CSR_SHPMCOUNTER3 0x5e3 +#define CSR_SHPMCOUNTER4 0x5e4 +#define CSR_SHPMCOUNTER5 0x5e5 +#define CSR_SHPMCOUNTER6 0x5e6 +#define CSR_SHPMCOUNTER7 0x5e7 +#define CSR_SHPMCOUNTER8 0x5e8 +#define CSR_SHPMCOUNTER9 0x5e9 +#define CSR_SHPMCOUNTER10 0x5ea +#define CSR_SHPMCOUNTER11 0x5eb +#define CSR_SHPMCOUNTER12 0x5ec +#define CSR_SHPMCOUNTER13 0x5ed +#define CSR_SHPMCOUNTER14 0x5ee +#define CSR_SHPMCOUNTER15 0x5ef +#define CSR_SHPMCOUNTER16 0x5f0 +#define CSR_SHPMCOUNTER17 0x5f1 +#define CSR_SHPMCOUNTER18 0x5f2 +#define CSR_SHPMCOUNTER19 0x5f3 +#define CSR_SHPMCOUNTER20 0x5f4 +#define CSR_SHPMCOUNTER21 0x5f5 +#define CSR_SHPMCOUNTER22 0x5f6 +#define CSR_SHPMCOUNTER23 0x5f7 +#define CSR_SHPMCOUNTER24 0x5f8 +#define CSR_SHPMCOUNTER25 0x5f9 +#define CSR_SHPMCOUNTER26 0x5fa +#define CSR_SHPMCOUNTER27 0x5fb +#define CSR_SHPMCOUNTER28 0x5fc +#define CSR_SHPMCOUNTER29 0x5fd +#define CSR_SHPMCOUNTER30 0x5fe +#define CSR_SHPMCOUNTER31 0x5ff +#define CSR_SCYCLEH 0x9e0 +#define CSR_SINSTRETH 0x9e2 +#define CSR_SHPMCOUNTER3H 0x9e3 +#define CSR_SHPMCOUNTER4H 0x9e4 +#define CSR_SHPMCOUNTER5H 0x9e5 +#define CSR_SHPMCOUNTER6H 0x9e6 +#define CSR_SHPMCOUNTER7H 0x9e7 +#define CSR_SHPMCOUNTER8H 0x9e8 +#define CSR_SHPMCOUNTER9H 0x9e9 +#define CSR_SHPMCOUNTER10H 0x9ea +#define CSR_SHPMCOUNTER11H 0x9eb +#define CSR_SHPMCOUNTER12H 0x9ec +#define CSR_SHPMCOUNTER13H 0x9ed +#define CSR_SHPMCOUNTER14H 0x9ee +#define CSR_SHPMCOUNTER15H 0x9ef +#define CSR_SHPMCOUNTER16H 0x9f0 +#define CSR_SHPMCOUNTER17H 0x9f1 +#define CSR_SHPMCOUNTER18H 0x9f2 +#define CSR_SHPMCOUNTER19H 0x9f3 +#define CSR_SHPMCOUNTER20H 0x9f4 +#define CSR_SHPMCOUNTER21H 0x9f5 +#define CSR_SHPMCOUNTER22H 0x9f6 +#define CSR_SHPMCOUNTER23H 0x9f7 +#define CSR_SHPMCOUNTER24H 0x9f8 +#define CSR_SHPMCOUNTER25H 0x9f9 +#define CSR_SHPMCOUNTER26H 0x9fa +#define CSR_SHPMCOUNTER27H 0x9fb +#define CSR_SHPMCOUNTER28H 0x9fc +#define CSR_SHPMCOUNTER29H 0x9fd +#define CSR_SHPMCOUNTER30H 0x9fe +#define CSR_SHPMCOUNTER31H 0x9ff + +#define CSR_SRPLCNTLST 0x9d8 +#define CSR_SCACHELOCK 0x9d9 +#define CSR_SCACHERPLPRI0 0x9da +#define CSR_SCACHERPLPRI1 0x9db +#define CSR_SCACHERPLPRI2 0x9dc +#define CSR_SCACHERPLPRI3 0x9dd +#define CSR_SCACHERPLPRI4 0x9de +#define CSR_SCACHERPLPRI5 0x9df + +/* User-Level XuanTie custom CSRs */ +#define CSR_TWCOUNTER 0x804 +#define CSR_FXCR 0x800 +#define CSR_XMRSTART 0x801 +#define CSR_XMCSR 0x802 +#define CSR_XMSIZE 0x803 +#define CSR_XMLENB 0xcc0 +#define CSR_XRLENB 0xcc1 +#define CSR_XMISA 0xcc2 + +#define CSR_URPLCNTLST 0x8e8 +#define CSR_UCACHELOCK 0x8e9 +#define CSR_UCACHERPLPRI0 0x8ea +#define CSR_UCACHERPLPRI1 0x8eb +#define CSR_UCACHERPLPRI2 0x8ec +#define CSR_UCACHERPLPRI3 0x8ed +#define CSR_UCACHERPLPRI4 0x8ee +#define CSR_UCACHERPLPRI5 0x8ef + +#endif /* __CSI_RV_ENCODING_H__ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/csi_core.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/csi_core.h new file mode 100644 index 00000000..bbb859ff --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/csi_core.h @@ -0,0 +1,224 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +/****************************************************************************** + * @file csi_core.h + * @brief CSI Core Layer Header File + * @version V1.0 + * @date 02. June 2017 + ******************************************************************************/ + +#ifndef _CORE_H_ +#define _CORE_H_ + +#include + +#if defined(__csky__) + +#if defined(__CK801__) || defined(__E801__) +#include +#elif defined(__CK802__) || defined(__E802__) || defined(__E802T__) || defined(__S802__) || defined(__S802T__) +#include +#elif defined(__CK804__) || defined(__E804D__) || defined(__E804DT__) || defined(__E804F__) || defined(__E804FT__) || defined (__E804DF__) || defined(__E804DFT__) +#include +#elif defined(__CK803__) || defined(__E803__) || defined(__E803T__) || defined(__S803__) || defined(__S803T__) +#include +#elif defined(__CK805__) || defined(__I805__) || defined(__I805F__) +#include +#elif defined(__CK610__) +#include +#elif defined(__CK810__) || defined(__C810__) || defined(__C810T__) || defined(__C810V__) || defined(__C810VT__) +#include +#elif defined(__CK807__) || defined(__C807__) || defined(__C807F__) || defined(__C807FV__) || defined(__R807__) +#include +#endif +#include + +#elif defined(__riscv) + +#include +#if CONFIG_CPU_XUANTIE_E906 || CONFIG_CPU_XUANTIE_E906F || CONFIG_CPU_XUANTIE_E906FD || CONFIG_CPU_XUANTIE_E906P || CONFIG_CPU_XUANTIE_E906FP || CONFIG_CPU_XUANTIE_E906FDP \ + || CONFIG_CPU_XUANTIE_E907 || CONFIG_CPU_XUANTIE_E907F || CONFIG_CPU_XUANTIE_E907FD || CONFIG_CPU_XUANTIE_E907P || CONFIG_CPU_XUANTIE_E907FP || CONFIG_CPU_XUANTIE_E907FDP \ + || CONFIG_CPU_XUANTIE_E902 || CONFIG_CPU_XUANTIE_E902M || CONFIG_CPU_XUANTIE_E902T || CONFIG_CPU_XUANTIE_E902MT \ + || CONFIG_CPU_XUANTIE_E901PLUS_CP || CONFIG_CPU_XUANTIE_E901PLUS_B_CP || CONFIG_CPU_XUANTIE_E901PLUS_M_CP || CONFIG_CPU_XUANTIE_E901PLUS_BM_CP \ + || CONFIG_CPU_XUANTIE_E901_CP || CONFIG_CPU_XUANTIE_E901_B_CP || CONFIG_CPU_XUANTIE_E901_ZM_CP || CONFIG_CPU_XUANTIE_E901_BZM_CP +#include +#include +#else +#include +#include +#endif /* end exx */ + +#endif /* __csky__ */ + +#ifdef __arm__ +#include +#endif + +#ifdef __ARM_ARCH_ISA_A64 +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#if CONFIG_CPU_XUANTIE_E9XX || CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV +#if CONFIG_SMP +#error "This CPU does not support SMP." +#endif +#endif + +__STATIC_INLINE const char* csi_get_cpu_name() +{ +#if CONFIG_CPU_XUANTIE_C906 + return "c906"; +#elif CONFIG_CPU_XUANTIE_C906FD + return "c906fd"; +#elif CONFIG_CPU_XUANTIE_C906FDV + return "c906fdv"; +#elif CONFIG_CPU_XUANTIE_C907 + return "c907"; +#elif CONFIG_CPU_XUANTIE_C907FD + return "c907fd"; +#elif CONFIG_CPU_XUANTIE_C907FDV + return "c907fdv"; +#elif CONFIG_CPU_XUANTIE_C907FDVM + return "c907fdvm"; +#elif CONFIG_CPU_XUANTIE_C907_RV32 + return "c907-rv32"; +#elif CONFIG_CPU_XUANTIE_C907FD_RV32 + return "c907fd-rv32"; +#elif CONFIG_CPU_XUANTIE_C907FDV_RV32 + return "c907fdv-rv32"; +#elif CONFIG_CPU_XUANTIE_C907FDVM_RV32 + return "c907fdvm-rv32"; +#elif CONFIG_CPU_XUANTIE_C908 + return "c908"; +#elif CONFIG_CPU_XUANTIE_C908V + return "c908v"; +#elif CONFIG_CPU_XUANTIE_C908I + return "c908i"; +#elif CONFIG_CPU_XUANTIE_C908X + return "c908x"; +#elif CONFIG_CPU_XUANTIE_C908X_CP + return "c908x-cp"; +#elif CONFIG_CPU_XUANTIE_C908X_CP_XT + return "c908x-cp-xt"; +#elif CONFIG_CPU_XUANTIE_C910 + return "c910"; +#elif CONFIG_CPU_XUANTIE_C920 + return "c920"; +#elif CONFIG_CPU_XUANTIE_C910V2 + return "c910v2"; +#elif CONFIG_CPU_XUANTIE_C910V3 + return "c910v3"; +#elif CONFIG_CPU_XUANTIE_C910V3_CP + return "c910v3-cp"; +#elif CONFIG_CPU_XUANTIE_C910V3_CP_XT + return "c910v3-cp-xt"; +#elif CONFIG_CPU_XUANTIE_C920V2 + return "c920v2"; +#elif CONFIG_CPU_XUANTIE_C920V3 + return "c920v3"; +#elif CONFIG_CPU_XUANTIE_C920V3_CP + return "c920v3-cp"; +#elif CONFIG_CPU_XUANTIE_C920V3_CP_XT + return "c920v3-cp-xt"; +#elif CONFIG_CPU_XUANTIE_R910 + return "r910"; +#elif CONFIG_CPU_XUANTIE_R920 + return "r920"; +#elif CONFIG_CPU_XUANTIE_R908 + return "r908"; +#elif CONFIG_CPU_XUANTIE_R908FD + return "r908fd"; +#elif CONFIG_CPU_XUANTIE_R908FDV + return "r908fdv"; +#elif CONFIG_CPU_XUANTIE_R908_CP + return "r908-cp"; +#elif CONFIG_CPU_XUANTIE_R908FD_CP + return "r908fd-cp"; +#elif CONFIG_CPU_XUANTIE_R908FDV_CP + return "r908fdv-cp"; +#elif CONFIG_CPU_XUANTIE_R908_CP_XT + return "r908-cp-xt"; +#elif CONFIG_CPU_XUANTIE_R908FD_CP_XT + return "r908fd-cp-xt"; +#elif CONFIG_CPU_XUANTIE_R908FDV_CP_XT + return "r908fdv-cp-xt"; +#elif CONFIG_CPU_XUANTIE_E901PLUS_CP + return "e901plus-cp"; +#elif CONFIG_CPU_XUANTIE_E901PLUS_B_CP + return "e901plusb-cp"; +#elif CONFIG_CPU_XUANTIE_E901PLUS_M_CP + return "e901plusm-cp"; +#elif CONFIG_CPU_XUANTIE_E901PLUS_BM_CP + return "e901plusbm-cp"; +#elif CONFIG_CPU_XUANTIE_E901_CP + return "e901-cp"; +#elif CONFIG_CPU_XUANTIE_E901_B_CP + return "e901b-cp"; +#elif CONFIG_CPU_XUANTIE_E901_ZM_CP + return "e901zm-cp"; +#elif CONFIG_CPU_XUANTIE_E901_BZM_CP + return "e901bzm-cp"; +#elif CONFIG_CPU_XUANTIE_E902 + return "e902"; +#elif CONFIG_CPU_XUANTIE_E902M + return "e902m"; +#elif CONFIG_CPU_XUANTIE_E902T + return "e902t"; +#elif CONFIG_CPU_XUANTIE_E902MT + return "e902mt"; +#elif CONFIG_CPU_XUANTIE_E906 + return "e906"; +#elif CONFIG_CPU_XUANTIE_E906F + return "e906f"; +#elif CONFIG_CPU_XUANTIE_E906FD + return "e906fd"; +#elif CONFIG_CPU_XUANTIE_E906P + return "e906p"; +#elif CONFIG_CPU_XUANTIE_E906FP + return "e906fp"; +#elif CONFIG_CPU_XUANTIE_E906FDP + return "e906fdp"; +#elif CONFIG_CPU_XUANTIE_E907 + return "e907"; +#elif CONFIG_CPU_XUANTIE_E907F + return "e907f"; +#elif CONFIG_CPU_XUANTIE_E907FD + return "e907fd"; +#elif CONFIG_CPU_XUANTIE_E907P + return "e907p"; +#elif CONFIG_CPU_XUANTIE_E907FP + return "e907fp"; +#elif CONFIG_CPU_XUANTIE_E907FDP + return "e907fdp"; +#else + return "unknown"; +#endif +} + + +#ifdef __cplusplus +} +#endif + +#endif /* _CORE_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/adc.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/adc.h new file mode 100755 index 00000000..dd69fd3d --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/adc.h @@ -0,0 +1,213 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/adc.h + * @brief Header File for ADC Driver + * @version V1.0 + * @date 08. Apr 2020 + * @model adc + ******************************************************************************/ + +#ifndef _DRV_ADC_H_ +#define _DRV_ADC_H_ + +#include +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/****** ADC Event *****/ +typedef enum { + ADC_EVENT_CONVERT_COMPLETE = 0, ///< All data convert completed + ADC_EVENT_CONVERT_HALF_DONE, ///< Convert half done + ADC_EVENT_ERROR ///< All errors including but not limited to what converted data has not been read before the new conversion result is load to the data register +} csi_adc_event_t; + +typedef struct csi_adc csi_adc_t; +struct csi_adc { + csi_dev_t dev; ///< Hw-device info + void (*callback)(csi_adc_t *adc, csi_adc_event_t event, void *arg); ///< User callback ,signaled by driver event + void *arg; ///< User private param ,passed to user callback + uint32_t *data; ///< Data buf + uint32_t num; ///< Data size by word + csi_dma_ch_t *dma; ///< Dma channel handle + csi_error_t (*start)(csi_adc_t *adc); ///< Start function + csi_error_t (*stop)(csi_adc_t *adc); ///< Stop function + csi_state_t state; ///< ADC current state + void *priv; +}; + +/** + \brief Initialize adc Interface. Initialize the resources needed for the adc interface + \param[in] adc ADC handle to operate + \param[in] idx ADC controller index + \return Error code \ref csi_error_t +*/ +csi_error_t csi_adc_init(csi_adc_t *adc, uint32_t idx); + +/** + \brief De-initialize adc Interface. stops operation and releases the software resources used by the interface + \param[in] handle ADC handle to operate + \return None +*/ +void csi_adc_uninit(csi_adc_t *adc); + +/** + \brief Set adc receive buffer + \param[in] adc ADC handle to operate + \param[in] num The receive data length by word. + \return Error code \ref csi_error_t +*/ +csi_error_t csi_adc_set_buffer(csi_adc_t *adc, uint32_t *data, uint32_t num); + +/** + \brief Start adc + \param[in] handle ADC handle to operate + \return Error code \ref csi_error_t +*/ +csi_error_t csi_adc_start(csi_adc_t *adc); + +/** + \brief Enable dma or interrupt, and start adc conversion + \param[in] handle ADC handle to operate + \return Error code \ref csi_error_t +*/ +csi_error_t csi_adc_start_async(csi_adc_t *adc); + +/** + \brief Stop adc + \param[in] handle ADC handle to operate + \return Error code \ref csi_error_t +*/ +csi_error_t csi_adc_stop(csi_adc_t *adc); + +/** + \brief Disable dma or interrupt, and stop adc conversion + \param[in] handle ADC handle to operate + \return Error code \ref csi_error_t +*/ +csi_error_t csi_adc_stop_async(csi_adc_t *adc); + +/** + \brief ADC channel enable + \param[in] adc ADC handle to operate + \param[in] ch_id ADC channel id + \param[in] is_enable true->enable, false->disable + \return Error code \ref csi_error_t +*/ +csi_error_t csi_adc_channel_enable(csi_adc_t *adc, uint8_t ch_id, bool is_enable); + +/** + \brief Set the ADC sampling time for the selected channel + \param[in] adc ADC handle to operate + \param[in] ch_id ADC channel id + \param[in] clock_num Channel sampling clock number + \return Error code \ref csi_error_t +*/ +csi_error_t csi_adc_channel_sampling_time(csi_adc_t *adc, uint8_t ch_id, uint16_t clock_num); + +/** + \brief Set the ADC controller sampling time + \param[in] adc ADC handle to operate + \param[in] clock_num ADC controller sampling clock number + \return Error code \ref csi_error_t +*/ +csi_error_t csi_adc_sampling_time(csi_adc_t *adc, uint16_t clock_num); + +/** + \brief Enable the continue mode of ADC + \param[in] adc ADC handle to operate + \param[in] is_enable true->enable, false->disable + \return Error code \ref csi_error_t +*/ +csi_error_t csi_adc_continue_mode(csi_adc_t *adc, bool is_enable); + +/** + \brief Set ADC frequence division + \param[in] adc ADC handle to operate + \param[in] div The division of frequence + \return The actual config frequency +*/ +uint32_t csi_adc_freq_div(csi_adc_t *adc, uint32_t div); + +/** + \brief Receiving data from ADC receiver + \param[in] handle ADC handle to operate + \return If read successful, this function shall return the result of convert value + otherwise, the function shall return error code +*/ +int32_t csi_adc_read(csi_adc_t *adc); + +/** + \brief Get ADC state + \param[in] adc ADC handle to operate + \param[in] state ADC state + \return Error code \ref csi_error_t +*/ +csi_error_t csi_adc_get_state(csi_adc_t *adc, csi_state_t *state); + +/** + \brief Attach the callback handler to adc + \param[in] adc Operate handle + \param[in] callback Callback function + \param[in] arg User can define it by himself as callback's param + \return Error code \ref csi_error_t +*/ +csi_error_t csi_adc_attach_callback(csi_adc_t *adc, void *callback, void *arg); + +/** + \brief Detach the callback handler + \param[in] adc Operate handle + \return None +*/ +void csi_adc_detach_callback(csi_adc_t *adc); + +/** + \brief Link DMA channel to adc device + \param[in] adc ADC handle to operate + \param[in] dma The DMA channel handle for send, when it is NULL means to unlink the channel + \return Error code \ref csi_error_t +*/ +csi_error_t csi_adc_link_dma(csi_adc_t *adc, csi_dma_ch_t *dma); + +/** + \brief Enable adc low power mode + \param[in] adc ADC handle to operate + \return Error code \ref csi_error_t +*/ +csi_error_t csi_adc_enable_pm(csi_adc_t *adc); + +/** + \brief Disable adc low power mode + \param[in] adc ADC handle to operate + \return None +*/ +void csi_adc_disable_pm(csi_adc_t *adc); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_ADC_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/aes.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/aes.h new file mode 100755 index 00000000..a395fa7c --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/aes.h @@ -0,0 +1,309 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/aes.h + * @brief Header File for AES Driver + * @version V1.0 + * @date 9. Oct 2020 + * @model aes + ******************************************************************************/ + +#ifndef _DRV_AES_H_ +#define _DRV_AES_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*----- Encrypt & Decrypt: Config key length -----*/ +typedef enum { + AES_KEY_LEN_BITS_128 = 0, /* 128 Data bits */ + AES_KEY_LEN_BITS_192, /* 192 Data bits */ + AES_KEY_LEN_BITS_256 /* 256 Data bits */ +} csi_aes_key_bits_t; + +/** +\brief AES Ctrl Block +*/ +typedef struct { + csi_dev_t dev; + void *priv; +} csi_aes_t; + +/** + \brief Initialize AES interface. Initializes the resources needed for the AES interface + \param[in] aes Handle to operate + \param[in] idx Device id + \return Error code \ref csi_error_t +*/ +csi_error_t csi_aes_init(csi_aes_t *aes, uint32_t idx); + +/** + \brief De-initialize AES interface. Stops operation and releases the software resources used by the interface + \param[in] aes Dandle to operate + \return None +*/ +void csi_aes_uninit(csi_aes_t *aes); + +/** + \brief Set encrypt key + \param[in] aes Handle to operate + \param[in] key Pointer to the key buf + \param[in] key_len Pointer to \ref csi_aes_key_bits_t + \return Error code \ref Csi_error_t +*/ +csi_error_t csi_aes_set_encrypt_key(csi_aes_t *aes, void *key, csi_aes_key_bits_t key_len); + +/** + \brief Set decrypt key + \param[in] aes Handle to operate + \param[in] key Pointer to the key buf + \param[in] key_len Pointer to \ref csi_aes_key_bits_t + \return Error code \ref Csi_error_t +*/ +csi_error_t csi_aes_set_decrypt_key(csi_aes_t *aes, void *key, csi_aes_key_bits_t key_len); +/** + \brief Set encrypt key2. This API is used for the algorithm which has two keys, + such as xts, used for the key of tweak + \param[in] aes Handle to operate + \param[in] key Pointer to the key buf + \param[in] key_len Pointer to \ref csi_aes_key_bits_t + \return Error code \ref Csi_error_t +*/ +csi_error_t csi_aes_set_encrypt_key2(csi_aes_t *aes, void *key, csi_aes_key_bits_t key_len); + +/** + \brief Set decrypt key2. This API is used for the algorithm which has two keys, + such as xts, used for the key of tweak + \param[in] aes Handle to operate + \param[in] key Pointer to the key buf + \param[in] key_len Pointer to \ref csi_aes_key_bits_t + \return Error code \ref Csi_error_t +*/ +csi_error_t csi_aes_set_decrypt_key2(csi_aes_t *aes, void *key, csi_aes_key_bits_t key_len); + +/** + \brief AES ecb encrypt + \param[in] aes Handle to operate + \param[in] in Pointer to the source data + \param[out] out Pointer to the result data + \param[in] size The source data size + \return Error code \ref Csi_error_t +*/ +csi_error_t csi_aes_ecb_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size); + +/** + \brief AES ecb decrypt + \param[in] aes Handle to operate + \param[in] in Pointer to the source data + \param[out] out Pointer to the result data + \param[in] size The source data size + \return Error code \ref Csi_error_t +*/ +csi_error_t csi_aes_ecb_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size); + +/** + \brief AES cbc encrypt + \param[in] aes Handle to operate + \param[in] in Pointer to the source data + \param[out] out Pointer to the result data + \param[in] size The source data size + \param[in] iv Init vector + \return Error code \ref Csi_error_t +*/ +csi_error_t csi_aes_cbc_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv); + +/** + \brief AES cbc decrypt + \param[in] aes Handle to operate + \param[in] in Pointer to the source data + \param[out] out Pointer to the result data + \param[in] size The source data size + \param[in] iv Init vector + \return Error code \ref Csi_error_t +*/ +csi_error_t csi_aes_cbc_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv); + +/** + \brief AES cfb1 encrypt + \param[in] aes Handle to operate + \param[in] in Pointer to the source data + \param[out] out Pointer to the result data + \param[in] size The source data size + \param[in] iv Init vector + \return Error code \ref Csi_error_t +*/ +csi_error_t csi_aes_cfb1_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv); + +/** + \brief AES cfb1 decrypt + \param[in] aes Handle to operate + \param[in] in Pointer to the source data + \param[out] out Pointer to the result data + \param[in] size The source data size + \param[in] iv Init vector + \return Error code \ref Csi_error_t +*/ +csi_error_t csi_aes_cfb1_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv); + +/** + \brief AES cfb8 encrypt + \param[in] aes Handle to operate + \param[in] in Pointer to the source data + \param[out] out Pointer to the result data + \param[in] size The source data size + \param[in] iv Init vector + \return Error code \ref Csi_error_t +*/ +csi_error_t csi_aes_cfb8_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv); + +/** + \brief AES cfb8 decrypt + \param[in] aes Handle to operate + \param[in] in Pointer to the source data + \param[out] out Pointer to the result data + \param[in] size The source data size + \param[in] iv Init vector + \return Error code \ref Csi_error_t +*/ +csi_error_t csi_aes_cfb8_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv); + +/** + \brief AES cfb128 decrypt + \param[in] aes Handle to operate + \param[in] in Pointer to the source data + \param[out] out Pointer to the result data + \param[in] size The source data size + \param[in] iv Init vector + \param[out] num The number of the 128-bit block we have used + \return Error code \ref csi_error_t +*/ +csi_error_t csi_aes_cfb128_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv, uint32_t *num); + +/** + \brief AES cfb128 encrypt + \param[in] aes Handle to operate + \param[in] in Pointer to the source data + \param[out] out Pointer to the result data + \param[in] size The source data size + \param[in] iv Init vector + \param[out] num The number of the 128-bit block we have used + \return Error code \ref csi_error_t +*/ +csi_error_t csi_aes_cfb128_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv, uint32_t *num); + +/** + \brief AES ofb encrypt + \param[in] aes Handle to operate + \param[in] in Pointer to the source data + \param[out] out Pointer to the result data + \param[in] size The source data size + \param[in] iv Init vector + \param[out] num The number of the 128-bit block we have used + \return Error code \ref csi_error_t +*/ +csi_error_t csi_aes_ofb_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv, uint32_t *num); + +/** + \brief AES ofb decrypt + \param[in] aes Handle to operate + \param[in] in Pointer to the source data + \param[out] out Pointer to the result data + \param[in] size The source data size + \param[in] iv Init vector + \param[out] num The number of the 128-bit block we have used + \return Error code \ref csi_error_t +*/ +csi_error_t csi_aes_ofb_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv, uint32_t *num); + +/** + \brief AES ctr encrypt + \param[in] aes Handle to operate + \param[in] in Pointer to the source data + \param[out] out Pointer to the result data + \param[in] size The source data size + \param[in] iv Init vector + \return Error code \ref csi_error_t +*/ +csi_error_t csi_aes_ctr_encrypt(csi_aes_t *aes, void *in,void *out, uint32_t size, void *iv); + +/** + \brief AES ctr decrypt + \param[in] aes Handle to operate + \param[in] in Pointer to the source data + \param[out] out Pointer to the result data + \param[in] size The source data size + \param[in] iv Init vecotr + \return Error code \ref csi_error_t +*/ +csi_error_t csi_aes_ctr_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv); + +/** + \brief AES cts encrypt + \param[in] aes Handle to operate + \param[in] in Pointer to the source data + \param[out] out Pointer to the result data + \param[in] size The source data size + \param[in] iv Init vector + \return Error code \ref csi_error_t +*/ +csi_error_t csi_aes_cts_encrypt(csi_aes_t *aes, void *in,void *out, uint32_t size, void *iv); + +/** + \brief AES cts decrypt + \param[in] aes Handle to operate + \param[in] in Pointer to the source data + \param[out] out Pointer to the result data + \param[in] size The source data size + \param[in] iv Init vecotr + \return Error code \ref csi_error_t +*/ +csi_error_t csi_aes_cts_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv); + + +/** + \brief AES xts encrypt + \param[in] aes Handle to operate + \param[in] in Pointer to the source data + \param[out] out Pointer to the result data + \param[in] size The source data size + \param[in] iv Init vector + \return Error code \ref csi_error_t +*/ +csi_error_t csi_aes_xts_encrypt(csi_aes_t *aes, void *in,void *out, uint32_t size, void *iv); + +/** + \brief AES xts decrypt + \param[in] aes Handle to operate + \param[in] in Pointer to the source data + \param[out] out Pointer to the result data + \param[in] size The source data size + \param[in] iv Init vecotr + \return Error code \ref csi_error_t +*/ +csi_error_t csi_aes_xts_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_AES_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/baud_calc.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/baud_calc.h new file mode 100755 index 00000000..1a077c10 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/baud_calc.h @@ -0,0 +1,60 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/baud_calc.h + * @brief Header File for the PWM capture uart bandrate Driver + * @version V1.0 + * @date 9. Oct 2020 + * @model baud_calc + ******************************************************************************/ + +#ifndef _DRV_BAUD_CALC_H_ +#define _DRV_BAUD_CALC_H_ + +#include +#include +#include +#include + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \brief Baud rate calculation(Algorithm level) + \param[in] idx PWM idx + \param[in] channel Channel num + \return Error code(-1) or Baudare value +*/ +int drv_calc_baud_adjust(uint32_t idx, uint32_t channel); + +/** + \brief Baud rate calculation(Capture level) + \param[in] idx PWM idx + \param[in] channel Channel num + \return Error code(-1) or Baudare value +*/ +int drv_calc_baud_original(uint32_t idx, uint32_t channel); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_BAUD_CALC_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/clk.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/clk.h new file mode 100755 index 00000000..9e9ee03e --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/clk.h @@ -0,0 +1,50 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/clk.h + * @brief Header File for CLK Driver. + * @version V1.0 + * @date 18. Mar 2020 + ******************************************************************************/ + +#ifndef _DRV_CLK_H_ +#define _DRV_CLK_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + uint32_t module; + uint16_t dev_tag; + uint8_t idx; +} csi_clkmap_t; + +void csi_clk_enable(csi_dev_t *dev); +void csi_clk_disable(csi_dev_t *dev); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_CLK_H_ */ + diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/codec.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/codec.h new file mode 100755 index 00000000..d96a40b0 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/codec.h @@ -0,0 +1,450 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/codec.h + * @brief head file for codec + * @version V1.0 + * @date 17. Mar 2020 + * @model codec + ******************************************************************************/ +#ifndef _DRV_CODEC_H_ +#define _DRV_CODEC_H_ + +#include +#include +#include +#include +#include "drv/ringbuf.h" + +typedef enum { + CODEC_EVENT_PERIOD_READ_COMPLETE = 0U, ///< A peroid data read completed + CODEC_EVENT_PERIOD_WRITE_COMPLETE = 1U, ///< A peroid data write completed + CODEC_EVENT_WRITE_BUFFER_EMPTY = 2U, ///< Fifo is empty + CODEC_EVENT_READ_BUFFER_FULL = 3U, ///< Fifo is full + CODEC_EVENT_ERROR_OVERFLOW = 4U, ///< Fifo overflow error + CODEC_EVENT_ERROR_UNDERFLOW = 5U, ///< Fifo underflow error + CODEC_EVENT_ERROR = 6U, ///< The device has a hardware error +} csi_codec_event_t; + +struct csi_codec; +typedef struct csi_codec csi_codec_t; +typedef struct csi_codec_output csi_codec_output_t; +struct csi_codec_output { + csi_codec_t *codec; + uint32_t ch_idx; ///< Codec output channel idx + void (*callback)(csi_codec_output_t *output, csi_codec_event_t event, void *arg); + void *arg; + csi_ringbuf_t *ring_buf; ///< The csi_ringbuf used to save audio data + uint32_t period; ///< When the period data is sent, the callback function will be called + uint32_t sound_channel_num; ///< Number of sound channel + csi_dma_ch_t *dma; ///< Dma channel handle + csi_state_t state; ///< Codec output channel current state + void *priv; + struct csi_codec_output *next; +}; + +typedef struct csi_codec_input csi_codec_input_t; +struct csi_codec_input { + csi_codec_t *codec; + uint32_t ch_idx; ///< Codec input channel idx + void (*callback)(csi_codec_input_t *input, csi_codec_event_t event, void *arg); + void *arg; + csi_ringbuf_t *ring_buf; ///< The csi_ringbuf used to save audio data + uint32_t period; ///< When the period data is received, the callback function will be called + uint32_t sound_channel_num; ///< Number of sound channel + csi_dma_ch_t *dma; ///< Codec input channel current state + csi_state_t state; ///< Dma channel handle + void *priv; + struct csi_codec_input *next; +}; + +struct csi_codec { + csi_dev_t dev; ///< Codec hw-device info + csi_codec_output_t *output_chs; ///< Codec output channel operate handle + csi_codec_input_t *input_chs; ///< Codec input channel operate handle + void *priv; ///< User private param passed to user callback +}; + +typedef enum { + CODEC_OUTPUT_SINGLE_ENDED, ///< Single-ended output + CODEC_OUTPUT_DIFFERENCE, ///< Differential output +} csi_codec_output_mode_t; + +typedef enum { + CODEC_INPUT_SINGLE_ENDED, ///< Single-ended input + CODEC_INPUT_DIFFERENCE, ///< Differential input +} csi_codec_input_mode_t; + +typedef struct { + uint32_t sample_rate; ///< Input data sample rate + uint32_t bit_width; ///< Input data sample width + csi_codec_input_mode_t mode; ///< Input work mode + uint8_t *buffer; ///< The buffer used to save audio data + uint32_t buffer_size; ///< Input buffer size + uint32_t period; ///< When a peroid data is reached,the callback function is called + uint32_t sound_channel_num; ///< Number of soundtrack per channel +} csi_codec_input_config_t; + +typedef struct { + uint32_t sample_rate; ///< Output data sample rate + uint32_t bit_width; ///< Onput data sample width + csi_codec_output_mode_t mode; ///< Onput work mode + uint8_t *buffer; ///< The buffer used to save audio data + uint32_t buffer_size; ///< Output buffer size + uint32_t period; ///< When a peroid data is reached,the callback function is called + uint32_t sound_channel_num; ///< Number of soundchannel per channel +} csi_codec_output_config_t; + +/** + \brief Init the codec according to the specified + \param[in] codec Codec handle to operate + \param[in] idx Codec interface idx + \return error code \ref csi_error_t +*/ +csi_error_t csi_codec_init(csi_codec_t *codec, uint32_t idx); + +/** + \brief Codec uninit + \param[in] codec Codec handle to operate + \return None +*/ +void csi_codec_uninit(csi_codec_t *codec); + +/** + \brief Open a codec output channel + \param[in] codec Codec handle to operate + \param[in] ch Codec output channel handle + \param[in] ch_idx Codec output channel idx + \return error code \ref csi_error_t +*/ +csi_error_t csi_codec_output_open(csi_codec_t *codec, csi_codec_output_t *ch, uint32_t ch_idx); + +/** + \brief Config codec output channel + \param[in] ch Codec output channel handle + \param[in] config Codec channel param. \ref csi_codec_output_config_t + \return error code \ref csi_error_t +*/ +csi_error_t csi_codec_output_config(csi_codec_output_t *ch, csi_codec_output_config_t *config); + +/** + \brief Attach the callback handler to codec output + \param[in] ch Codec output channel handle + \param[in] cb Callback function + \param[in] arg User private param + \return error code \ref csi_error_t +*/ +csi_error_t csi_codec_output_attach_callback(csi_codec_output_t *ch, void *callback, void *arg); + +/** + \brief Detach the callback handler + \param[in] ch Codec output channel handle + \return None +*/ +void csi_codec_output_detach_callback(csi_codec_output_t *ch); + +/** + \brief Close a codec output channel + \param[in] ch Codec output channel handle + \return error code \ref csi_error_t +*/ +void csi_codec_output_close(csi_codec_output_t *ch); + +/** + \brief Link DMA channel to codec output channel + \param[in] ch Codec output channel handle + \param[in] dma The codec output DMA channel handle, when it is NULL means to unlink the channel + \return error code \ref csi_error_t +*/ +csi_error_t csi_codec_output_link_dma(csi_codec_output_t *ch, csi_dma_ch_t *dma); + +/** + \brief Send an amount of data to buffer in blocking mode + \param[in] ch The codec output channel + \param[in] data Pointer to send data buffer + \param[in] size Send data size + \return the num of data witch is send successful +*/ +uint32_t csi_codec_output_write(csi_codec_output_t *ch, const void *data, uint32_t size); + +/** + \brief Send data to the buffer with asynchronous sending + The data is first written to the buffer and then output through the codec interface + This function does not block, and the return value is the number + Of data that was successfully written to the buffer + \param[in] ch The codec output channel + \param[in] data Pointer to send data buffer + \param[in] size Send data size + \return The data size that send to buffer +*/ +uint32_t csi_codec_output_write_async(csi_codec_output_t *ch, const void *data, uint32_t size); + +/** + \brief Start sending data from the buffer + \param[in] ch Codec output channel handle + \return error code \ref csi_error_t +*/ +csi_error_t csi_codec_output_start(csi_codec_output_t *ch); + +/** + \brief Stop sending data from the buffer + \param[in] ch Codec output channel handle + \return None +*/ +void csi_codec_output_stop(csi_codec_output_t *ch); + +/** + \brief Pause sending data from the buffer + \param[in] ch Codec output channel handle + \return error code \ref csi_error_t +*/ +csi_error_t csi_codec_output_pause(csi_codec_output_t *ch); + +/** + \brief Resume sending data from the buffer + \param[in] ch Codec output channel handle + \return error code \ref csi_error_t +*/ +csi_error_t csi_codec_output_resume(csi_codec_output_t *ch); + +/** + \brief Get output-buffer free space + \param[in] ch Codec output channel handle + \return Buffer free space (bytes) +*/ +uint32_t csi_codec_output_buffer_avail(csi_codec_output_t *ch); + +/** + \brief Get used space of output-buffer + \param[in] ch Codec output channel handle + \return Buffer free space (bytes) +*/ +uint32_t csi_codec_output_buffer_remain(csi_codec_output_t *ch); + +/** + \brief Reset the buf, discard all data in the buffer + \param[in] ch Codec output channel handle + \return error code \ref csi_error_t +*/ +csi_error_t csi_codec_output_buffer_reset(csi_codec_output_t *ch); + +/** + \brief Mute codec ouput channel + \param[in] ch Codec output channel handle + \param[in] en True enable codec mute. false disable codec mute + \return error code \ref csi_error_t +*/ +csi_error_t csi_codec_output_mute(csi_codec_output_t *ch, bool enable); + +/** + \brief Set codec ouput channel digital gain + \param[in] ch Codec output channel handle + \param[in] val Gain val + \return error code \ref csi_error_t +*/ +csi_error_t csi_codec_output_digital_gain(csi_codec_output_t *ch, uint32_t val); + +/** + \brief Set codec ouput channel analog gain + \param[in] ch Codec output channel handle + \param[in] val Gain val + \return error code \ref csi_error_t +*/ +csi_error_t csi_codec_output_analog_gain(csi_codec_output_t *ch, uint32_t val); + +/** + \brief Set codec ouput channel mix gain + \param[in] ch Codec output channel handle + \param[in] val Gain val + \return error code \ref csi_error_t +*/ +csi_error_t csi_codec_output_mix_gain(csi_codec_output_t *ch, uint32_t val); + +/** + \brief Get codec output channel state + \param[in] ch Codec output channel handle + \param[out] state Channel state. \ref csi_state_t + \return channel state +*/ +csi_error_t csi_codec_output_get_state(csi_codec_output_t *ch, csi_state_t *state); + +/** + \brief Open a codec input channel + \param[in] codec Codec handle to operate + \param[in] ch Codec input channel handle + \param[in] ch_idx Codec input channel idx + \return error code \ref csi_error_t +*/ +csi_error_t csi_codec_input_open(csi_codec_t *codec, csi_codec_input_t *ch, uint32_t ch_idx); + +/** + \brief Config codec input channel + \param[in] ch Codec input channel handle + \param[in] config Codec channel prarm. \ref csi_codec_input_config_t + \return error code \ref csi_error_t +*/ +csi_error_t csi_codec_input_config(csi_codec_input_t *ch, csi_codec_input_config_t *config); + +/** + \brief Attach the callback handler to codec output + \param[in] ch Codec input channel handle + \param[in] cb Callback function + \param[in] arg User private param for event callback + \return error code \ref csi_error_t +*/ +csi_error_t csi_codec_input_attach_callback(csi_codec_input_t *ch, void *callback, void *arg); + +/** + \brief Detach the callback handler + \param[in] ch Codec input channel handle + \return None +*/ +void csi_codec_input_detach_callback(csi_codec_input_t *ch); + +/** + \brief Close a codec input channel + \param[in] ch Codec input channel handle + \return None +*/ +void csi_codec_input_close(csi_codec_input_t *ch); + +/** + \brief Link DMA channel to codec input channel + \param[in] ch Codec input channel handle + \param[in] dma The codec input DMA channel handle, when it is NULL means to unlink the channel + \return error code \ref csi_error_t +*/ +csi_error_t csi_codec_input_link_dma(csi_codec_input_t *ch, csi_dma_ch_t *dma); + +/** + \brief Read an amount of data in blocking mode + \param[in] ch Codec input channel handle + \param[in] data Pointer to receive data buffer + \param[in] size Receive data size + \return The size of data read successfully +*/ +uint32_t csi_codec_input_read(csi_codec_input_t *ch, void *data, uint32_t size); + +/** + \brief Read data from the buffer + using asynchronous receive + this function read data from the buffer, returns the number of successful receive + and returns 0 if there is no data in the buffer + \param[in] ch Codec input channel handle + \param[in] data Pointer to receive data buffer + \param[in] size Receive data size + \return The size of data read successfully +*/ +uint32_t csi_codec_input_read_async(csi_codec_input_t *ch, void *data, uint32_t size); + +/** + \brief Start receive data to the buffer + \param[in] ch Codec input channel handle + \return error code \ref csi_error_t +*/ +csi_error_t csi_codec_input_start(csi_codec_input_t *ch); + +/** + \brief Stop receive data + \param[in] ch Codec input channel handle + \return None +*/ +void csi_codec_input_stop(csi_codec_input_t *ch); + +/** + \brief Reset the buf, discard all data in the buffer + \param[in] ch Codec input channel handle + \return error code \ref csi_error_t +*/ +csi_error_t csi_codec_input_buffer_reset(csi_codec_input_t *ch); + +/** + \brief Get input-buffer free space + \param[in] ch Codec input channel handle + \return Buffer free space (bytes) +*/ +uint32_t csi_codec_input_buffer_avail(csi_codec_input_t *ch); + +/** + \brief Get used space of input-buffer + \param[in] ch Codec input channel handle + \return Buffer free space (bytes) +*/ +uint32_t csi_codec_input_buffer_remain(csi_codec_input_t *ch); + +/** + \brief Mute codec input channel + \param[in] ch Codec input channel handle + \param[in] en True enable codec mute. false disable codec mute + \return error code \ref csi_error_t +*/ +csi_error_t csi_codec_input_mute(csi_codec_input_t *ch, bool en); + +/** + \brief Set codec input channel digital gain + \param[in] ch Codec input channel handle + \param[in] val Gain val + \return error code \ref csi_error_t +*/ +csi_error_t csi_codec_input_digital_gain(csi_codec_input_t *ch, uint32_t val); + +/** + \brief Set codec input channel analog gain + \param[in] ch Codec input channel handle + \param[in] val Gain val + \return error code \ref csi_error_t +*/ +csi_error_t csi_codec_input_analog_gain(csi_codec_input_t *ch, uint32_t val); + +/** + \brief Set codec input channel mix gain + \param[in] ch Codec input channel handle + \param[in] val Gain val + \return error code \ref csi_error_t +*/ +csi_error_t csi_codec_input_mix_gain(csi_codec_input_t *ch, uint32_t val); + +/** + \brief Get codec input channel state + \param[in] ch Codec input channel handle + \param[out] state Channel state + \return Channel state +*/ +csi_error_t csi_codec_input_get_state(csi_codec_input_t *ch, csi_state_t *state); + +/** + \brief Enable codec power manage + \param[in] codec Codec handle to operate + \return error code \ref csi_error_t +*/ +csi_error_t csi_codec_enable_pm(csi_codec_t *codec); + +/** + \brief Disable codec power manage + \param[in] codec Codec handle to operate + \return None +*/ +void csi_codec_disable_pm(csi_codec_t *codec); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_CODEC_H_ */ + diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/common.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/common.h new file mode 100755 index 00000000..c2c2f84f --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/common.h @@ -0,0 +1,154 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/common.h + * @brief Header File for Common Driver + * @version V1.0 + * @date 31. March 2020 + * @model common + ******************************************************************************/ + +#ifndef _DRV_COMMON_H_ +#define _DRV_COMMON_H_ + +#include +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef CONFIG_DEBUG_MODE +#define CSI_ASSERT(expr) \ + do { \ + if ((long)expr == (long)NULL) { \ + printf("PROGRAM ASSERT\n"); \ + while(1); \ + } \ + } while(0); +#else +#define CSI_ASSERT(expr) ((void)0U) +#endif + +#ifndef CONFIG_PARAM_NOT_CHECK +#define CSI_PARAM_CHK(para, err) \ + do \ + { \ + if ((unsigned long)para == (unsigned long)NULL) \ + { \ + return (err); \ + } \ + } while (0) + +#define CSI_PARAM_CHK_NORETVAL(para) \ + do \ + { \ + if ((unsigned long)para == (unsigned long)NULL) \ + { \ + return; \ + } \ + } while (0) +#else +#define CSI_PARAM_CHK(para, err) +#define CSI_PARAM_CHK_NORETVAL(para) +#endif + +typedef enum { + CSI_OK = 0, + CSI_ERROR = -1, + CSI_BUSY = -2, + CSI_TIMEOUT = -3, + CSI_UNSUPPORTED = -4 +} csi_error_t; + +typedef struct { + uint8_t readable; + uint8_t writeable; + uint8_t error; +} csi_state_t; + +typedef struct csi_dev csi_dev_t; + +#ifdef CONFIG_PM +typedef enum { + PM_DEV_SUSPEND, + PM_DEV_RESUME, +} csi_pm_dev_action_t; + +typedef enum { + PM_MODE_RUN = 0, ///< Running mode + PM_MODE_SLEEP_1, ///< Sleep LV1 mode + PM_MODE_SLEEP_2, ///< Sleep LV2 mode + PM_MODE_DEEP_SLEEP_1, ///< Deep sleep LV1 mode + PM_MODE_DEEP_SLEEP_2, ///< Deep sleep LV2 mode +} csi_pm_mode_t; + +typedef struct { + slist_t next; + csi_error_t (*pm_action)(csi_dev_t *dev, csi_pm_dev_action_t action); + uint32_t *reten_mem; + uint32_t size; +} csi_pm_dev_t; +#include +#endif + +struct csi_dev { + unsigned long reg_base; + uint16_t irq_num; + uint16_t idx; + uint16_t dev_tag; + void (*irq_handler)(void *); + void (*irq_handler2)(uint32_t irqn, void *arg); + void *arg; +#ifdef CONFIG_PM + csi_pm_dev_t pm_dev; +#endif +}; + +#define DEV_IDX_INVALID 0xFFFFU +#define HANDLE_REG_BASE(handle) (handle->dev.reg_base) +#define HANDLE_IRQ_NUM(handle) (handle->dev.irq_num) +#define HANDLE_DEV_IDX(handle) (handle->dev.idx) +#define HANDLE_IRQ_HANDLER(handle) (handle->dev.irq_handler) + +typedef struct { + unsigned long reg_base; + uint16_t irq_num; + uint16_t idx; + uint16_t dev_tag; +} csi_perip_info_t; + +csi_error_t target_get(csi_dev_tag_t dev_tag, uint32_t idx, csi_dev_t *dev); +csi_error_t target_get_optimal_dma_channel(void *dma_list, uint32_t ctrl_num, csi_dev_t *parent_dev, void *ch_info); +csi_error_t target_get_check_dma_access(uint32_t ctrl_idx, void *srcaddr, void *dstaddr, void **dma_base_src_addr, void **dma_base_dst_addr); +csi_error_t target_get_dma_handshake(uint16_t dma_id, uint16_t dev_id, uint16_t dev_tag, uint8_t type, uint16_t *handshake); +void mdelay(uint32_t ms); +void udelay(uint32_t us); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_COMMON_H_ */ + diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/crc.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/crc.h new file mode 100755 index 00000000..2fbd43db --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/crc.h @@ -0,0 +1,136 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file crc.h + * @brief Header File for CRC Driver + * @version V1.0 + * @date 02. June 2020 + * @model crc + ******************************************************************************/ + +#ifndef _DRV_CRC_H_ +#define _DRV_CRC_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Compute the CRC-7 checksum of a buffer. + * + * See JESD84-A441. Used by the MMC protocol. Uses 0x09 as the + * polynomial with no reflection. The CRC is left + * justified, so bit 7 of the result is bit 6 of the CRC. + * init = 0; poly = 0x09 refin = 0 refout = 0 xorout = 0 + * \param[in] crc Crc init value or crc immediate result + * \param[in] data Data buf to be calculate + * \param[in] size Data size + * + * \return The computed CRC7 value + */ +uint8_t csi_crc7_be(uint8_t crc, uint8_t *data, uint32_t size); + +/** + * \brief Compute the CRC-8 checksum of a buffer. + * init = 0 or 0xff; poly = 0x07 refin = 0 refout = 0 xorout = 0 + * \param[in] crc Crc init value or crc immediate result + * \param[in] data Data buf to be calculate + * \param[in] size Data size + * \return The computed CRC8 value + */ +uint8_t csi_crc8(uint8_t crc, uint8_t *data, size_t size); + +/** + * \brief Compute the CRC-8 checksum of a buffer. + * init = 0; poly = 0x31 refin = 1 refout = 1 xorout = 0 + * \param[in] crc Crc init value or crc immediate result + * \param[in] data Data buf to be calculate + * \param[in] size Data size + * \return The computed CRC8 value + */ +uint8_t csi_crc8_maxim(uint8_t crc, uint8_t *data, size_t size); + +/** + * \brief Compute the CRC-16 checksum of a buffer. + * init = 0 or 0xffff; poly = 0x8005 refin = 1 refout = 1 xorout = 0 + * \param[in] crc Crc init value or crc immediate result + * \param[in] data Data buf to be calculate + * \param[in] size Data size + * \return The computed CRC16 without xorout + */ +uint16_t csi_crc16(uint16_t crc, uint8_t *data, uint32_t size); + +/** + * \brief Compute the CRC-16 checksum of a buffer. + * init = 0; poly = 0x1021 refin = 1 refout = 1 xorout = 0 + * \param[in] crc Crc init value or crc immediate result + * \param[in] data Data buf to be calculate + * \param[in] size Data size + * \return The computed CRC16 without xorout + */ +uint16_t csi_crc16_ccitt(uint16_t crc, uint8_t *data, uint32_t size); + +/** + * \brief Compute the CRC-16 checksum of a buffer. + * init = 0; poly = 0x3d65 refin = 1 refout = 1 xorout = 0xffff + * \param[in] init_value Crc init value + * \param[in] data Data buf to be calculate + * \param[in] size Data size + * \return The computed CRC16 with xorout + */ +uint16_t csi_crc16_dnp(uint16_t init_value, uint8_t *data, uint32_t size); + +/** + * \brief Compute the CRC-16 checksum of a buffer. + * init = 0; poly = 0x1021 refin = 0 refout = 0 xorout = 0 + * \param[in] crc Crc init value or crc immediate result + * \param[in] data Data buf to be calculate + * \param[in] size Data size + * \return The computed CRC16 without xorout + */ +uint16_t csi_crc16_itu(uint16_t crc, uint8_t *data, uint32_t size); + +/** + * \brief Compute the CRC-32 checksum of a buffer.Little-endian by bit. + * init = 0; poly = 0xEDB88320 refin = 0 refout = 0 xorout = 0 + * \param[in] crc Crc init value or crc immediate result + * \param[in] data Data buf to be calculate + * \param[in] size Data size + * \return The computed CRC32 without xorout + */ +uint32_t csi_crc32_le(uint32_t crc, uint8_t *data, uint32_t size); + +/** + * \brief Compute the CRC-32 checksum of a buffer.Big-endian by bit. + * init = 0; poly = 0x04C11DB7 refin = 0 refout = 0 xorout = 0 + * \param[in] crc Crc init value or crc immediate result + * \param[in] data Data buf to be calculate + * \param[in] size Data size + * \return The computed CRC32 without xorout + */ +uint32_t csi_crc32_be(uint32_t crc, uint8_t *data, uint32_t size); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_CRC_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/des.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/des.h new file mode 100755 index 00000000..2b0540ea --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/des.h @@ -0,0 +1,174 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/des.h + * @brief Header File for DES Driver + * @version V1.0 + * @date 24. Oct 2022 + * @model des + ******************************************************************************/ + +#ifndef _DRV_DES_H_ +#define _DRV_DES_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** +\brief DES key-len-bits type +*/ +typedef enum { + DES_KEY_LEN_BITS_64 = 0, /*64 Data bits*/ + DES_KEY_LEN_BITS_128, /*128 Data bits*/ + DES_KEY_LEN_BITS_192, /*192 Data bits*/ +} csi_des_key_bits_t; + +/** +\brief DES Ctrl Block +*/ +typedef struct { + csi_dev_t dev; + void *priv; +} csi_des_t; + +/** + \brief Initialize DES interface. Initializes the resources needed for the DES interface + \param[in] des Handle to operate + \param[in] idx Device id + \return Error code \ref csi_error_t +*/ +csi_error_t csi_des_init(csi_des_t *des, uint32_t idx); + +/** + \brief De-initialize DES interface. Stops operation and releases the software resources used by the interface + \param[in] des Dandle to operate + \return None +*/ +void csi_des_uninit(csi_des_t *des); + +/** + \brief Set encrypt key + \param[in] des Handle to operate + \param[in] key Pointer to the key buf + \param[in] key_len Pointer to \ref csi_des_key_bits_t + \return Error code \ref Csi_error_t +*/ +csi_error_t csi_des_set_encrypt_key(csi_des_t *des, void *key, csi_des_key_bits_t key_len); + +/** + \brief Set decrypt key + \param[in] des Handle to operate + \param[in] key Pointer to the key buf + \param[in] key_len Pointer to \ref csi_des_key_bits_t + \return Error code \ref Csi_error_t +*/ +csi_error_t csi_des_set_decrypt_key(csi_des_t *des, void *key, csi_des_key_bits_t key_len); + +/** + \brief DES ecb encrypt + \param[in] des Handle to operate + \param[in] in Pointer to the source data + \param[out] out Pointer to the result data + \param[in] size The source data size + \return Error code \ref Csi_error_t +*/ +csi_error_t csi_des_ecb_encrypt(csi_des_t *des, void *in, void *out, uint32_t size); + +/** + \brief DES ecb decrypt + \param[in] des Handle to operate + \param[in] in Pointer to the source data + \param[out] out Pointer to the result data + \param[in] size The source data size + \return Error code \ref Csi_error_t +*/ +csi_error_t csi_des_ecb_decrypt(csi_des_t *des, void *in, void *out, uint32_t size); + +/** + \brief DES cbc encrypt + \param[in] des Handle to operate + \param[in] in Pointer to the source data + \param[out] out Pointer to the result data + \param[in] size The source data size + \param[in] iv Init vector + \return Error code \ref Csi_error_t +*/ +csi_error_t csi_des_cbc_encrypt(csi_des_t *des, void *in, void *out, uint32_t size, void *iv) ; + +/** + \brief DES cbc decrypt + \param[in] des Handle to operate + \param[in] in Pointer to the source data + \param[out] out Pointer to the result data + \param[in] size The source data size + \param[in] iv Init vector + \return Error code \ref Csi_error_t +*/ +csi_error_t csi_des_cbc_decrypt(csi_des_t *des, void *in, void *out, uint32_t size, void *iv); + +/** + \brief TDES ecb encrypt + \param[in] des Handle to operate + \param[in] in Pointer to the source data + \param[out] out Pointer to the result data + \param[in] size The source data size + \return Error code \ref Csi_error_t +*/ +csi_error_t csi_tdes_ecb_encrypt(csi_des_t *des, void *in, void *out, uint32_t size); + +/** + \brief TDES ecb decrypt + \param[in] des Handle to operate + \param[in] in Pointer to the source data + \param[out] out Pointer to the result data + \param[in] size The source data size + \return Error code \ref Csi_error_t +*/ +csi_error_t csi_tdes_ecb_decrypt(csi_des_t *des, void *in, void *out, uint32_t size); + +/** + \brief TDES cbc encrypt + \param[in] des Handle to operate + \param[in] in Pointer to the source data + \param[out] out Pointer to the result data + \param[in] size The source data size + \param[in] iv Init vector + \return Error code \ref Csi_error_t +*/ +csi_error_t csi_tdes_cbc_encrypt(csi_des_t *des, void *in, void *out, uint32_t size, void *iv) ; + +/** + \brief TDES cbc decrypt + \param[in] des Handle to operate + \param[in] in Pointer to the source data + \param[out] out Pointer to the result data + \param[in] size The source data size + \param[in] iv Init vector + \return Error code \ref Csi_error_t +*/ +csi_error_t csi_tdes_cbc_decrypt(csi_des_t *des, void *in, void *out, uint32_t size, void *iv); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_DES_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/dma.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/dma.h new file mode 100644 index 00000000..7dcf5b5c --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/dma.h @@ -0,0 +1,306 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file dma.h + * @brief header file for dma driver + * @version V1.0 + * @date 08. Apr 2020 + * @model dma + ******************************************************************************/ + +#ifndef _DRV_DMA_H_ +#define _DRV_DMA_H_ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/****** DMA Event *****/ +typedef enum { + DMA_EVENT_TRANSFER_DONE = 0, ///< transfer complete + DMA_EVENT_TRANSFER_BLOCK_DONE, ///< transfer block done + DMA_EVENT_TRANSFER_HALF_DONE, ///< transfer half done + DMA_EVENT_TRANSFER_ERROR, ///< transfer error +} csi_dma_event_t; + +typedef enum { + DMA_ADDR_INC = 0, + DMA_ADDR_DEC, + DMA_ADDR_CONSTANT +} csi_dma_addr_inc_t; + +typedef enum { + DMA_DATA_WIDTH_8_BITS = 0, + DMA_DATA_WIDTH_16_BITS, + DMA_DATA_WIDTH_32_BITS, + DMA_DATA_WIDTH_64_BITS, + DMA_DATA_WIDTH_128_BITS, + DMA_DATA_WIDTH_512_BITS +} csi_dma_data_width_t; + +typedef enum { + DMA_MEM2MEM = 0, + DMA_MEM2PERH, + DMA_PERH2MEM, +} csi_dma_trans_dir_t; + +typedef struct { + uint16_t ctrl_idx; + uint8_t ch_idx; +} csi_dma_ch_desc_t; + + typedef struct { + uint16_t dev_tag; + uint16_t ctrl_idx; + const csi_dma_ch_desc_t *ch_list; + } csi_dma_ch_spt_list_t; + +typedef struct { + uint16_t ctrl_idx; + uint64_t ch_bit_info; +} csi_dma_ch_bit_desc_t; + + +typedef struct { + uint16_t ctrl_idx; + uint8_t ch_num; +} csi_dma_ch_info_t; + +typedef struct { + uint16_t parent_dev_id; + uint16_t dev_tag; + const csi_dma_ch_bit_desc_t *ch_list; +} csi_dma_ch_bit_spt_list_t; + +#define DMA_HANDSHAKE_NONE 0xff + +typedef enum { + DMA_HANDSHAKE_TYPE_RX = 0x0, + DMA_HANDSHAKE_TYPE_TX = 0x1, +} csi_dma_handshake_type_t; + +typedef struct { + uint16_t parent_dev_id; + uint16_t dev_tag; + uint8_t rx_hs; + uint8_t tx_hs; +} csi_dma_handshake_ctrl_t; + +typedef struct { + uint16_t ctrl_idx; + const csi_dma_handshake_ctrl_t* handshake_ctrl_list; +} csi_dma_handshake_list_t; + +typedef struct { + void* cpu_base_addr; + void* dma_base_addr; + size_t mem_size; +} csi_dma_mem_desc_t; + +typedef struct { + uint16_t ctrl_idx; + const csi_dma_mem_desc_t *mem_list; +} csi_dma_mem_list_t; + +typedef enum { + DMA_LINK_LIST_STOP = 0, + DMA_LINK_LIST_RUNNING, + DMA_LINK_LIST_READY, +} csi_dma_link_list_state_t; + +typedef enum { + DMA_CYCLIC_STOP = 0, + DMA_CYCLIC_RUNNING, + DMA_CYCLIC_READY, +} csi_dma_cyclic_state_t; + +typedef struct { + void *srcaddr; + void *dstaddr; + uint32_t length; +} csi_dma_link_list_item_t; + +typedef struct { + csi_dma_addr_inc_t src_inc; ///< source address increment + csi_dma_addr_inc_t dst_inc; ///< destination address increment + csi_dma_data_width_t src_tw; ///< source transfer width in byte + csi_dma_data_width_t dst_tw; ///< destination transfer width in byte + csi_dma_trans_dir_t trans_dir; ///< transfer direction + uint16_t handshake; ///< handshake id + uint16_t group_len; ///< group transaction length (unit: bytes) + uint8_t src_reload_en; ///< 1:dma enable src addr auto reload, 0:disable + uint8_t dst_reload_en; ///< 1:dma enable dst addr auto reload, 0:disable + uint8_t half_int_en; ///< 1:dma enable half interrupt, 0: disable + uint8_t lli_src_en; ///< 1:dma enable llp, 0 disable + uint8_t lli_dst_en; ///< 1:dma enable llp, 0 disable + uint8_t link_list_en; ///< 1:dma enable link list mode, 0: disable + void *lli_buf; ///< link list config +} csi_dma_ch_config_t; + + +typedef struct { + csi_dma_addr_inc_t src_inc; ///< source address increment + csi_dma_addr_inc_t dst_inc; ///< destination address increment + csi_dma_data_width_t src_tw; ///< source transfer width in byte + csi_dma_data_width_t dst_tw; ///< destination transfer width in byte + uint16_t group_len; ///< group transaction length (unit: bytes) + uint8_t lli_src_en; ///< 1:dma enable llp, 0 disable + uint8_t lli_dst_en; ///< 1:dma enable llp, 0 disable +} csi_dma_lli_config_t; + +#ifndef DMA_LLI_SIZE +#define DMA_LLI_SIZE 64 +#endif + +#define DEFINE_DESC_BUF(buf_name, num) uint8_t buf_name[num * DMA_LLI_SIZE] __attribute__((aligned(64))); + +typedef struct csi_dma_ch csi_dma_ch_t; + +struct csi_dma_ch { + void *parent; + int8_t ctrl_id; + int8_t ch_id; + void (*callback)(csi_dma_ch_t *dma_ch, csi_dma_event_t event, void *arg); + void *arg; + uint32_t lli_num; //lli buffer len + uint32_t lli_count; //lli data count + int32_t lli_w_p; //write position + int32_t lli_r_p; //read position + void *lli; //lli buffer + uint32_t lli_loop_buf0; //lli loop data + uint32_t lli_loop_buf1; //lli loop data + uint8_t lli_loop[DMA_LLI_SIZE]; //lli loop handle + int16_t etb_ch_id; + csi_dma_trans_dir_t trans_dir; + csi_dma_link_list_state_t link_list_state; + slist_t next; +}; + +typedef struct { + csi_dev_t dev; + slist_t head; + uint64_t alloc_status; + uint32_t ch_num; + void *priv; +} csi_dma_t; + +/** + \brief Init dma controller + \param[in] dma the dma controller operate handle + \param[in] ctrl_id the dma controller id + \return csi error code +*/ +csi_error_t csi_dma_init(csi_dma_t *dma, int8_t ctrl_id); + +/** + \brief Uninit dma controller + \param[in] dma the dma controller operate handle + \return none +*/ +void csi_dma_uninit(csi_dma_t *dma); + +/** + \brief Alloc a dma channel + \param[in] dma_ch the dma channel operate handle + \param[in] ch_id the channel id of dma; when set -1, means auto alloc + \param[in] ctrl_id the dma controller id; when set -1, means auto alloc + \return csi error code +*/ +csi_error_t csi_dma_ch_alloc(csi_dma_ch_t *dma_ch, int8_t ch_id, int8_t ctrl_id); + +/** + \brief Free a dma channel + \param[in] dma_ch the dma channel operate handle + \return none +*/ +void csi_dma_ch_free(csi_dma_ch_t *dma_ch); + +/** + \brief Config a dma channel + \param[in] dma_ch the dma channel operate handle + \param[in] config the config structure for dma channel + \return csi error code +*/ +csi_error_t csi_dma_ch_config(csi_dma_ch_t *dma_ch, csi_dma_ch_config_t *config); + +/** + \brief Start a dma channel + \param[in] dma_ch the dma channel operate handle + \param[in] psrcaddr transfer source address + \param[in] pdstaddr transfer destination address + \param[in] length transfer length (unit: bytes), if set data_width is 16, the length should be the multiple of 2, and + if set data_width is 32, the length should be the multiple of 4 + \return none +*/ +void csi_dma_ch_start(csi_dma_ch_t *dma_ch, void *srcaddr, void *dstaddr, uint32_t length); + +/** + \brief Stop a dma channel + \param[in] dma_ch the dma channel operate handle + \return none +*/ +void csi_dma_ch_stop(csi_dma_ch_t *dma_ch); + +/** + \brief add dma lli + \param[in] dma_ch the dma channel operate handle + \param[in] config lli config + \param[in] item lli + \return csi error code +*/ +csi_error_t csi_dma_add_link_list_item(csi_dma_ch_t *dma_ch, csi_dma_lli_config_t *config, csi_dma_link_list_item_t *item); + +/** + \brief Attach the callback handler to DMA channel + \param[in] dma_ch operate handle. + \param[in] callback callback function + \param[in] arg user can define it by himself as callback's param + \return error code +*/ +csi_error_t csi_dma_ch_attach_callback(csi_dma_ch_t *dma_ch, void *callback, void *arg); + +/** + \brief detach the callback handler + \param[in] uart operate handle. +*/ +void csi_dma_ch_detach_callback(csi_dma_ch_t *dma_ch); + +/** + \brief enable dma power manage + \param[in] dma dma handle to operate. + \return error code +*/ +csi_error_t csi_dma_enable_pm(csi_dma_t *dma); + +/** + \brief disable dma power manage + \param[in] dma dma handle to operate. +*/ +void csi_dma_disable_pm(csi_dma_t *dma); + +#ifdef __cplusplus +} +#endif + +#endif /* _CSI_DMA_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/drv_fft.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/drv_fft.h new file mode 100755 index 00000000..76330849 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/drv_fft.h @@ -0,0 +1,83 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv_fft.h + * @brief header file for gpio driver + * @version V1.0 + * @date 11. Nov 2017 + * @model fft + ******************************************************************************/ + +#ifndef _CSI_FFT_H_ +#define _CSI_FFT_H_ + + +#include +#include +#include +//#include + +#ifdef __cplusplus + extern "C" { +#endif + +typedef enum { + // 512-point FFT + CSKY_MCA_FFT_LEN_512 = 0x1, + // 256-point FFT + CSKY_MCA_FFT_LEN_256 = 0x2, + // 128-point FFT + CSKY_MCA_FFT_LEN_128 = 0x4, + // 64-point FFT + CSKY_MCA_FFT_LEN_64 = 0x8, + // 32-point FFT + CSKY_MCA_FFT_LEN_32 = 0x10, + // 16-point FFT + CSKY_MCA_FFT_LEN_16 = 0x20, +} csky_mca_fft_len_t; + +/* 8-bit fixed-point numeric type in user-defined format */ +typedef int8_t fxp8_t; +/* 16-bit fixed-point numeric type in user-defined format */ +typedef int16_t fxp16_t; +/* 24-bit fixed-point numeric type in user-defined format */ +typedef int32_t fxp24_t; +/* 32-bit fixed-point numeric type in user-defined format */ +typedef int32_t fxp32_t; +/* 64-bit fixed-point numeric type in user-defined format */ +typedef int64_t fxp64_t; + +/* 8-bit fixed-point numeric type in 1.0.7 format */ +typedef fxp8_t q7_t; +/* 16-bit fixed-point numeric type in 1.0.15 format */ +typedef fxp16_t q15_t; +/* 32-bit fixed-point numeric type in 1.15.16 format */ +typedef fxp32_t q16_t; + +void csky_mca_rfft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, size_t input_size, fxp32_t *output); +void csky_mca_cfft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, fxp32_t *output); +void csky_mca_rifft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, fxp32_t *output); +void csky_mca_cifft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, fxp32_t *output); +void csky_mca_power_spectrum_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, size_t input_size, fxp64_t *output); + +#ifdef __cplusplus +} +#endif + +#endif /* _CSI_FFT_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/ecdh.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/ecdh.h new file mode 100755 index 00000000..5e9acf78 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/ecdh.h @@ -0,0 +1,92 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/ecdh.h + * @brief Header File for ECDH Driver + * @version V1.0 + * @date 9. May 2023 + * @model ecdh + ******************************************************************************/ + +#ifndef _DRV_ECDH_H_ +#define _DRV_ECDH_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** +\brief ECDH Ctrl Block +*/ +typedef struct { + csi_dev_t dev; + void *priv; +} csi_ecdh_t; + +/** + \brief Initialize ECDH interface. Initializes the resources needed for the ECDH interface + \param[in] ecdh Handle to operate + \param[in] idx Device id + \return Error code \ref csi_error_t +*/ +csi_error_t csi_ecdh_init(csi_ecdh_t *ecdh, uint32_t idx); + +/** + \brief De-initialize ECDH interface. Stops operation and releases the software resources used by the interface + \param[in] ecdh Dandle to operate + \return None +*/ +void csi_ecdh_uninit(csi_ecdh_t *ecdh); + +/** + \brief Load curve param to engin + \param[in] ecdh Handle to operate + \param[in] type Pointer to \ref csi_curve_type_t + \return Error code \ref csi_error_t +*/ +csi_error_t csi_ecdh_load_curve(csi_ecdh_t *ecdh, csi_curve_type_t type); + +/** + \brief ECDH generate key pair + \param[in] ecdh Handle to operate + \param[out] prikey Pointer to the private key buf + \param[out] pubkey Pointer to the public key buf + \return Error code \ref Csi_error_t +*/ +csi_error_t csi_ecdh_gen_keypair(csi_ecdh_t *ecdh, uint8_t *prikey, uint8_t *pubkey); + +/** + \brief ECDH generate secret key + \param[in] ecdh Handle to operate + \param[in] prikey Pointer to the private key buf + \param[in] pubkey Pointer to the public key buf + \param[out] sk Pointer to the secret key buf + \param[out] sk_len The secret key length + \return Error code \ref Csi_error_t +*/ +csi_error_t csi_ecdh_calc_secret(csi_ecdh_t *ecdh, const uint8_t *privkey, const uint8_t *pubkey, uint8_t *sk, uint32_t *sk_len); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_ECDH_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/ecdsa.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/ecdsa.h new file mode 100755 index 00000000..4c6d91a6 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/ecdsa.h @@ -0,0 +1,112 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/ecdsa.h + * @brief Header File for ECDSA Driver + * @version V1.0 + * @date 9. May 2023 + * @model ecdsa + ******************************************************************************/ + +#ifndef _DRV_ECDSA_H_ +#define _DRV_ECDSA_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** +\brief EC curve type +*/ +typedef enum { + CSI_CURVES_SECP256K1 = 0U, /* SECG curve over a 256 bit prime field */ + CSI_CURVES_SECP384R1, /* NIST/SECG curve over a 384 bit prime field */ + CSI_CURVES_SECP521R1, /* NIST/SECG curve over a 521 bit prime field */ + CSI_CURVES_BRAINPOOL256R1, /* RFC 5639 curve over a 256 prime field */ + CSI_CURVES_BRAINPOOL256T1, /* RFC 5639 curve over a 256 prime field */ + CSI_CURVES_BRAINPOOL512R1, /* RFC 5639 curve over a 512 prime field */ + CSI_CURVES_BRAINPOOL512T1, /* RFC 5639 curve over a 512 prime field */ +} csi_curve_type_t; + +/** +\brief ECDSA Ctrl Block +*/ +typedef struct { + csi_dev_t dev; + void *priv; +} csi_ecdsa_t; + +/** + \brief Initialize ECDSA interface. Initializes the resources needed for the ECDSA interface + \param[in] ecdsa Handle to operate + \param[in] idx Device id + \return Error code \ref csi_error_t +*/ +csi_error_t csi_ecdsa_init(csi_ecdsa_t *ecdsa, uint32_t idx); + +/** + \brief De-initialize ECDSA interface. Stops operation and releases the software resources used by the interface + \param[in] ecdsa Dandle to operate + \return None +*/ +void csi_ecdsa_uninit(csi_ecdsa_t *ecdsa); + +/** + \brief Load curve param to engin + \param[in] ecdsa Handle to operate + \param[in] type Pointer to \ref csi_curve_type_t + \return Error code \ref csi_error_t +*/ +csi_error_t csi_ecdsa_load_curve(csi_ecdsa_t *ecdsa, csi_curve_type_t type); + +/** + \brief Ecdsa Sign + \param[in] ecdsa Handle to operate + \param[in] prikey Pointer to the private key buf + \param[in] prikey_len The private key length + \param[in] dgst Pointer to the digest buf + \param[in] dgst_len The digest length + \param[out] sig Pointer to the signature buf + \param[out] sig_len The signature length + \return Error code \ref Csi_error_t +*/ +csi_error_t csi_ecdsa_sign(csi_ecdsa_t *ecdsa, const uint8_t *prikey, uint32_t prikey_len, + const uint8_t *dgst, uint32_t dgst_len, uint8_t *sig, uint32_t *sig_len); + +/** + \brief Ecdsa Verify + \param[in] ecdsa Handle to operate + \param[in] pubkey Pointer to the public key buf + \param[in] prikey_len The public key length + \param[in] dgst Pointer to the digest buf + \param[in] dgst_len The digest length + \param[in] sig Pointer to the signature buf + \param[in] sig_len The signature length + \return Error code \ref Csi_error_t +*/ +csi_error_t csi_ecdsa_verify(csi_ecdsa_t *ecdsa, const uint8_t *pubkey, uint32_t pubkey_len, + const uint8_t *dgst, uint32_t gst_len, const uint8_t *sig, uint32_t sig_len); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_ECDSA_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/eflash.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/eflash.h new file mode 100755 index 00000000..8d6c41d0 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/eflash.h @@ -0,0 +1,140 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file eflash.h + * @brief header file for eflash driver + * @version V1.0 + * @date 02. June 2017 + * @model eflash + ******************************************************************************/ +#ifndef _DRV_EFLASH_H_ +#define _DRV_EFLASH_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** +\brief Flash information +*/ +typedef struct { + uint32_t flash_size; ///< Chip End address (start+size-1) + uint32_t sector_size; ///< Uniform sector size in bytes + uint32_t erased_value; ///< erased value +} csi_eflash_info_t; + +/** +\brief Flash Status +*/ +typedef struct { + uint32_t busy : 1; ///< Flash busy flag + uint32_t error : 1; ///< Read/Program/Erase error flag (cleared on start of next operation) +} eflash_status_t; + +/// definition for eflash handle. +typedef struct { + csi_dev_t dev; + void *arg; + csi_eflash_info_t eflashinfo; + uint16_t prog; + uint16_t erase; + void *priv; +} csi_eflash_t; + +// Function documentation + +/** + \brief Initialize EFLASH Interface. 1. Initializes the resources needed for the EFLASH interface 2.registers event callback function + \param[in] eflash eflash handle to operate. + \param[in] idx device id + \param[in] arg User can define it by himself as callback's param + \return error code +*/ +csi_error_t csi_eflash_init(csi_eflash_t *eflash, int32_t idx, void *arg); + +/** + \brief De-initialize EFLASH Interface. stops operation and releases the software resources used by the interface + \param[in] eflash eflash handle to operate. + \return error code +*/ +csi_error_t csi_eflash_uninit(csi_eflash_t *eflash); + +/** + \brief Read data from Flash. + \param[in] eflash eflash handle to operate. + \param[in] offset Data address. + \param[out] data Pointer to a buffer storing the data read from Flash. + \param[in] size Number of data items to read. + \return error code +*/ +csi_error_t csi_eflash_read(csi_eflash_t *eflash, uint32_t offset, void *data, uint32_t size); + +/** + \brief Program data to Flash. + \param[in] eflash eflash handle to operate. + \param[in] offset Data address. + \param[in] data Pointer to a buffer containing the data to be programmed to Flash. + \param[in] size Number of data items to program. + \return error code +*/ +csi_error_t csi_eflash_program(csi_eflash_t *eflash, uint32_t offset, const void *data, uint32_t size); + +/** + \brief Erase Flash Sector. + \param[in] eflash eflash handle to operate. + \param[in] offset flash address, flash address need sector size aligned + \param[in] size erase size + \return error code +*/ +csi_error_t csi_eflash_erase(csi_eflash_t *eflash, uint32_t offset,uint32_t size); + +/** + \brief Erase whole flash + \param[in] eflash eflash handle to operate. + \return error code +*/ +csi_error_t csi_eflash_erase_chip(csi_eflash_t *eflash); + +/** + \brief Get Flash information. + \param[in] eflash eflash handle to operate. +*/ +void csi_eflash_dev_info(csi_eflash_t *eflash,csi_eflash_info_t *eflash_info); + +/** + \brief enable eflash power manage + \param[in] eflash eflash handle to operate. + \return error code +*/ +csi_error_t csi_eflash_enable_pm(csi_eflash_t *eflash); + +/** + \brief disable eflash power manage + \param[in] eflash eflash handle to operate. +*/ +void csi_eflash_disable_pm(csi_eflash_t *eflash); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_EFLASH_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/efuse.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/efuse.h new file mode 100755 index 00000000..2c697074 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/efuse.h @@ -0,0 +1,93 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/efuse.h + * @brief Header File for EFUSE Driver + * @version V1.0 + * @date 22. Mar 2020 + * @model efuse + ******************************************************************************/ +#ifndef _DEV_EFUSEC_H_ +#define _DEV_EFUSEC_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + uint32_t start; ///< Efuse start address + uint32_t end; ///< Efuse end address + uint32_t size; ///< Efuse size +} csi_efuse_info_t; + +typedef struct { + csi_dev_t dev; + csi_efuse_info_t info; +} csi_efuse_t; + +/** + \brief Initialize EFUSEC Interface. 1. Initializes the resources needed for the EFUSEC interface + \param[in] idx Device id + \return Error code +*/ +csi_error_t csi_efuse_init(csi_efuse_t *efuse, int32_t idx); + +/** + \brief De-initialize EFUSEC Interface. stops operation and releases the software resources used by the interface + \param[in] efuse Efuse efuse to operate. + \return None +*/ +void csi_efuse_uninit(csi_efuse_t *efuse); + +/** + \brief Read data from Efuse. + \param[in] efuse Efuse handle to operate. + \param[in] addr Data address. + \param[out] data Pointer to a buffer storing the data read from Efuse. + \param[in] size Number of data items to read. + \return Number of data items read or error code +*/ +int32_t csi_efuse_read(csi_efuse_t *efuse, uint32_t addr, void *data, uint32_t size); + +/** + \brief Program data to Efuse. + \param[in] efuse Efuse handle to operate. + \param[in] addr Data address. + \param[in] data Pointer to a buffer containing the data to be programmed to Efuse. + \param[in] cnt Number of data items to program. + \return number of data items programmed or error code +*/ +int32_t csi_efuse_program(csi_efuse_t *efuse, uint32_t addr, const void *data, uint32_t size); + +/** + \brief Get Efuse information. + \param[in] efuse Efuse handle to operate. + \param[out] info Efuse info \refs csi_efuse_info_t. + \return Error code +*/ +csi_error_t csi_efuse_get_info(csi_efuse_t *efuse, csi_efuse_info_t *info); + +#ifdef __cplusplus +} +#endif + +#endif /* _CSI_EFUSEC_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/etb.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/etb.h new file mode 100755 index 00000000..20dcfac7 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/etb.h @@ -0,0 +1,102 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv_etb.h + * @brief header file for event trigger driver + * @version V1.0 + * @date 27. octorber 2017 + * @model etb + ******************************************************************************/ + +#ifndef _DRV_ETB_H_ +#define _DRV_ETB_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ETB_HARDWARE_TRIG = 0, ///< etb channel inout is hardware trigger. + ETB_SOFTWARE_TRIG ///< etb channel inout is software trigger. +} csi_etb_trig_mode_t; + +typedef enum { + ETB_CH_ONE_TRIGGER_ONE = 0, ///< one device trig one deivce + ETB_CH_ONE_TRIGGER_MORE, ///< one device trig two for more device + ETB_CH_MORE_TRIGGER_ONE ///< two or more device trig one deivce +} csi_etb_ch_type_t; + +typedef struct { + uint8_t src_ip; ///< a specific number represent a location in an source trigger location map to trigger other ip(s). + uint8_t dst_ip; ///< a specific number represent an location in an dest trigger map to wait signal(s) from source ip(s) or location(s). + csi_etb_trig_mode_t trig_mode; ///< the input source is hardware trigger or software trigger. + csi_etb_ch_type_t ch_type; ///< channel type +} csi_etb_config_t; + +/** + \brief Init the etb device + \return error code +*/ +csi_error_t csi_etb_init(void); + +/** + \brief Uninit the etb device + \return none +*/ +void csi_etb_uninit(void); + +/** + \brief alloc an etb channel + \param[in] ch_mode etb channel work mode + \return channel id or CSI_ERROR +*/ +int32_t csi_etb_ch_alloc(csi_etb_ch_type_t ch_type); + +/** + \brief free an etb channel + \param[in] ch_id etb channel work mode + \return none +*/ +void csi_etb_ch_free(int32_t ch_id); + +/** + \brief config etb channel + \param[in] ch_id etb channel id + \param[in] config the config structure for etb channel + \return csi error code +*/ +csi_error_t csi_etb_ch_config(int32_t ch_id, csi_etb_config_t *config); + +/** + \brief start an etb channel + \param[in] ch_id etb channel id + \return none +*/ +void csi_etb_ch_start(int32_t ch_id); + +/** + \brief stop an etb channel + \param[in] etb etb channel id + \return none +*/ +void csi_etb_ch_stop(int32_t ch_id); + +#endif /* _CSI_ETB_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/eth.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/eth.h new file mode 100644 index 00000000..3a2aedb4 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/eth.h @@ -0,0 +1,111 @@ +/** + * Copyright (C) 2016 CSI Project. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _CSI_NET_H_ +#define _CSI_NET_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define CSI_ETH_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor)) + +/** +\brief Driver Version +*/ +typedef struct csi_driver_version { + uint16_t api; ///< API version + uint16_t drv; ///< Driver version +} csi_drv_version_t; + +/* General return codes */ +#define CSI_ETH_OK 0 ///< Operation succeeded +#define CSI_ETH_ERROR CSI_DRV_ERRNO_ETH_BASE+1 ///< Unspecified error +#define CSI_ETH_ERROR_BUSY CSI_DRV_ERRNO_ETH_BASE+2 ///< Driver is busy +#define CSI_ETH_ERROR_TIMEOUT CSI_DRV_ERRNO_ETH_BASE+3 ///< Timeout occurred +#define CSI_ETH_ERROR_UNSUPPORTED CSI_DRV_ERRNO_ETH_BASE+4 ///< Operation not supported +#define CSI_ETH_ERROR_PARAMETER CSI_DRV_ERRNO_ETH_BASE+5 ///< Parameter error +#define CSI_ETH_ERROR_SPECIFIC CSI_DRV_ERRNO_ETH_BASE+6 ///< Start of driver specific errors + +/** +\brief General power states +*/ +typedef enum eth_power_state { + CSI_ETH_POWER_OFF, ///< Power off: no operation possible + CSI_ETH_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events + CSI_ETH_POWER_FULL ///< Power on: full operation at maximum performance +} eth_power_state_t; + +/** +\brief Ethernet Media Interface type +*/ +#define CSI_ETH_INTERFACE_MII (0) ///< Media Independent Interface (MII) +#define CSI_ETH_INTERFACE_RMII (1) ///< Reduced Media Independent Interface (RMII) +#define CSI_ETH_INTERFACE_SMII (2) ///< Serial Media Independent Interface (SMII) + +/** +\brief Ethernet link speed +*/ +#define CSI_ETH_SPEED_10M (0) ///< 10 Mbps link speed +#define CSI_ETH_SPEED_100M (1) ///< 100 Mbps link speed +#define CSI_ETH_SPEED_1G (2) ///< 1 Gpbs link speed + +/** +\brief Ethernet duplex mode +*/ +#define CSI_ETH_DUPLEX_HALF (0) ///< Half duplex link +#define CSI_ETH_DUPLEX_FULL (1) ///< Full duplex link + +/** +\brief Ethernet auto-negotiation +*/ +#define CSI_ETH_AUTONEG_DISABLE (0) ///< Disable auto-negotiation +#define CSI_ETH_AUTONEG_ENABLE (1) ///< Enable auto-negotiation + +/** +\brief Ethernet link state +*/ +typedef enum eth_link_state { + ETH_LINK_DOWN, ///< Link is down + ETH_LINK_UP ///< Link is up +} eth_link_state_t; + +/** +\brief Ethernet link information +*/ +typedef volatile struct eth_link_info { + uint32_t speed : 2; ///< Link speed: 0= 10 MBit, 1= 100 MBit, 2= 1 GBit + uint32_t duplex : 1; ///< Duplex mode: 0= Half, 1= Full + uint32_t autoneg : 1; ///< Set the interface to Auto Negotiation mode of transmission parameters + uint32_t loopback : 1; ///< Set the interface into a Loop-back test mode + uint32_t isolation : 1; ///< Set to indicate electrical isolation of PHY interface from MII/RMII interface + uint32_t reserved : 26; +} eth_link_info_t; + +/** +\brief Ethernet MAC Address +*/ +typedef struct eth_mac_addr { + uint8_t b[6]; ///< MAC Address (6 bytes), MSB first +} eth_mac_addr_t; + +#ifdef __cplusplus +} +#endif + +#endif /* CSI_NET_H_ */ + diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/eth_mac.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/eth_mac.h new file mode 100644 index 00000000..bc5757d2 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/eth_mac.h @@ -0,0 +1,377 @@ +/** + * Copyright (C) 2016 CSI Project. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _CSI_ETH_H_ +#define _CSI_ETH_H_ + +#include +#include "drv/eth.h" +#include "drv/eth_phy.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void *eth_mac_handle_t; + +#define MAX_FRAMELEN 1518 /* (note: maximum ethernet frame length would be 1518) */ + +#define CSI_ETH_MAC_API_VERSION CSI_DRIVER_VERSION_MAJOR_MINOR(2,1) /* API version */ + +#define _CSI_Driver_ETH_MAC_(n) Driver_ETH_MAC##n +#define CSI_Driver_ETH_MAC_(n) _CSI_Driver_ETH_MAC_(n) + +/****** Ethernet MAC Control Codes *****/ + +#define CSI_ETH_MAC_CONFIGURE (0x01) ///< Configure MAC; arg = configuration +#define CSI_ETH_MAC_CONTROL_TX (0x02) ///< Transmitter; arg: 0=disabled (default), 1=enabled +#define CSI_ETH_MAC_CONTROL_RX (0x03) ///< Receiver; arg: 0=disabled (default), 1=enabled +#define CSI_ETH_MAC_FLUSH (0x04) ///< Flush buffer; arg = CSI_ETH_MAC_FLUSH_... +#define CSI_ETH_MAC_SLEEP (0x05) ///< Sleep mode; arg: 1=enter and wait for Magic packet, 0=exit +#define CSI_ETH_MAC_VLAN_FILTER (0x06) ///< VLAN Filter for received frames; arg15..0: VLAN Tag; arg16: optional CSI_ETH_MAC_VLAN_FILTER_ID_ONLY; 0=disabled (default) +#define DRV_ETH_MAC_ADJUST_LINK (0x07) ///< Adjust MAC link state according to phy state; arg: phy handle +#define DRV_ETH_MAC_CONTROL_IRQ (0x08) ///< Interrupt request; arg: 0=disable, 1=enable + +/*----- Ethernet MAC Configuration -----*/ +#define CSI_ETH_MAC_SPEED_Pos 0 +#define CSI_ETH_MAC_SPEED_Msk (3UL << CSI_ETH_MAC_SPEED_Pos) +#define CSI_ETH_MAC_SPEED_10M (CSI_ETH_SPEED_10M << CSI_ETH_MAC_SPEED_Pos) ///< 10 Mbps link speed +#define CSI_ETH_MAC_SPEED_100M (CSI_ETH_SPEED_100M << CSI_ETH_MAC_SPEED_Pos) ///< 100 Mbps link speed +#define CSI_ETH_MAC_SPEED_1G (CSI_ETH_SPEED_1G << CSI_ETH_MAC_SPEED_Pos) ///< 1 Gpbs link speed +#define CSI_ETH_MAC_DUPLEX_Pos 2 +#define CSI_ETH_MAC_DUPLEX_Msk (1UL << CSI_ETH_MAC_DUPLEX_Pos) +#define CSI_ETH_MAC_DUPLEX_HALF (CSI_ETH_DUPLEX_HALF << CSI_ETH_MAC_DUPLEX_Pos) ///< Half duplex link +#define CSI_ETH_MAC_DUPLEX_FULL (CSI_ETH_DUPLEX_FULL << CSI_ETH_MAC_DUPLEX_Pos) ///< Full duplex link +#define CSI_ETH_MAC_LOOPBACK (1UL << 4) ///< Loop-back test mode +#define CSI_ETH_MAC_CHECKSUM_OFFLOAD_RX (1UL << 5) ///< Receiver Checksum offload +#define CSI_ETH_MAC_CHECKSUM_OFFLOAD_TX (1UL << 6) ///< Transmitter Checksum offload +#define CSI_ETH_MAC_ADDRESS_BROADCAST (1UL << 7) ///< Accept frames with Broadcast address +#define CSI_ETH_MAC_ADDRESS_MULTICAST (1UL << 8) ///< Accept frames with any Multicast address +#define CSI_ETH_MAC_ADDRESS_ALL (1UL << 9) ///< Accept frames with any address (Promiscuous Mode) + +/*----- Ethernet MAC Flush Flags -----*/ +#define CSI_ETH_MAC_FLUSH_RX (1UL << 0) ///< Flush Receive buffer +#define CSI_ETH_MAC_FLUSH_TX (1UL << 1) ///< Flush Transmit buffer + +/*----- Ethernet MAC VLAN Filter Flag -----*/ +#define CSI_ETH_MAC_VLAN_FILTER_ID_ONLY (1UL << 16) ///< Compare only the VLAN Identifier (12-bit) + + +/****** Ethernet MAC Frame Transmit Flags *****/ +#define CSI_ETH_MAC_TX_FRAME_FRAGMENT (1UL << 0) ///< Indicate frame fragment +#define CSI_ETH_MAC_TX_FRAME_EVENT (1UL << 1) ///< Generate event when frame is transmitted +#define CSI_ETH_MAC_TX_FRAME_TIMESTAMP (1UL << 2) ///< Capture frame time stamp + + +/****** Ethernet MAC Timer Control Codes *****/ +#define CSI_ETH_MAC_TIMER_GET_TIME (0x01) ///< Get current time +#define CSI_ETH_MAC_TIMER_SET_TIME (0x02) ///< Set new time +#define CSI_ETH_MAC_TIMER_INC_TIME (0x03) ///< Increment current time +#define CSI_ETH_MAC_TIMER_DEC_TIME (0x04) ///< Decrement current time +#define CSI_ETH_MAC_TIMER_SET_ALCSI (0x05) ///< Set alarm time +#define CSI_ETH_MAC_TIMER_ADJUST_CLOCK (0x06) ///< Adjust clock frequency; time->ns: correction factor * 2^31 + + +/** +\brief Ethernet MAC Time +*/ +typedef struct eth_mac_time { + uint32_t ns; ///< Nano seconds + uint32_t sec; ///< Seconds +} eth_mac_time_t; + + +/****** Ethernet MAC Event *****/ +#define CSI_ETH_MAC_EVENT_RX_FRAME (1UL << 0) ///< Frame Received +#define CSI_ETH_MAC_EVENT_TX_FRAME (1UL << 1) ///< Frame Transmitted +#define CSI_ETH_MAC_EVENT_WAKEUP (1UL << 2) ///< Wake-up (on Magic Packet) +#define CSI_ETH_MAC_EVENT_TIMER_ALCSI (1UL << 3) ///< Timer Alarm +#define CSI_ETH_MAC_EVENT_LINK_CHANGE (1UL << 4) ///< Link state + +typedef void (*eth_event_cb_t)(int32_t idx, uint32_t event); ///< Pointer to \ref eth_event_cb_t : Signal Ethernet Event. + +typedef enum { + FRAME_FILTER_RULE_POSITIVE_MATCHING = 0, /*!< Specifies that a filter should match a given pattern */ + FRAME_FILTER_RULE_NEGATIVE_MATCHING = 1, /*!< Specifies that a filter should NOT match a given pattern */ +} frame_filter_rule_t; + +/** +\brief Ethernet MAC Capabilities +*/ +typedef struct eth_capabilities { + uint32_t checksum_offload_rx_ip4 : 1; ///< 1 = IPv4 header checksum verified on receive + uint32_t checksum_offload_rx_ip6 : 1; ///< 1 = IPv6 checksum verification supported on receive + uint32_t checksum_offload_rx_udp : 1; ///< 1 = UDP payload checksum verified on receive + uint32_t checksum_offload_rx_tcp : 1; ///< 1 = TCP payload checksum verified on receive + uint32_t checksum_offload_rx_icmp : 1; ///< 1 = ICMP payload checksum verified on receive + uint32_t checksum_offload_tx_ip4 : 1; ///< 1 = IPv4 header checksum generated on transmit + uint32_t checksum_offload_tx_ip6 : 1; ///< 1 = IPv6 checksum generation supported on transmit + uint32_t checksum_offload_tx_udp : 1; ///< 1 = UDP payload checksum generated on transmit + uint32_t checksum_offload_tx_tcp : 1; ///< 1 = TCP payload checksum generated on transmit + uint32_t checksum_offload_tx_icmp : 1; ///< 1 = ICMP payload checksum generated on transmit + uint32_t media_interface : 2; ///< Ethernet Media Interface type + uint32_t mac_address : 1; ///< 1 = driver provides initial valid MAC address + uint32_t event_rx_frame : 1; ///< 1 = callback event generated + uint32_t event_tx_frame : 1; ///< 1 = callback event generated + uint32_t event_wakeup : 1; ///< 1 = wakeup event generated + uint32_t precision_timer : 1; ///< 1 = Precision Timer supported + uint32_t reserved : 15; ///< Reserved (must be zero) +} eth_capabilities_t; + +/** + * Structure describing a frame filter list item + */ +typedef struct { + uint32_t id; /*!< Unique identifier for a packet filter item */ + frame_filter_rule_t rule; /*!< Filter matches are either POSITIVE or NEGATIVE matching */ + uint16_t offset; /*!< Offset in bytes to start filtering (referenced to the start of the ethernet packet) */ + uint16_t mask_size; /*!< Size of the mask in bytes */ + uint8_t *mask; /*!< Pattern mask bytes to be ANDed with the pattern eg. "\xff00" (must be in network byte order) */ + uint8_t *pattern; /*!< Pattern bytes used to filter eg. "\x0800" (must be in network byte order) */ + bool enabled_status; /*!< When returned from mhd_get_packet_filters, indicates if the filter is enabled */ +} eth_frame_filter_t; + +struct eth_frame_filter_list { + struct eth_frame_filter_list *next; +}; + +typedef struct eth_frame_filter_list eth_frame_filter_list_t; + +typedef struct { + eth_event_cb_t cb_event; + eth_capabilities_t capabilities; +} eth_mac_priv_t; + +/** + \brief Get driver version. + \param[in] handle ethernet handle + \return ethernet version including chip version and driver version +*/ +csi_drv_version_t csi_eth_mac_get_version(eth_mac_handle_t handle); + +/** + \brief Get driver capabilities. + \param[in] idx device id + \return ethernet capabilities +*/ +eth_capabilities_t csi_eth_mac_get_capabilities(int32_t idx); + +/** + \brief This function is used to initialize Ethernet device and related resource, an event callback is registered. It is called when the middleware component like TCPIP starts operation. + \param[in] idx device id + \param[in] cb callback to handle ethernet event + \return return ethernet handle if success + */ +eth_mac_handle_t csi_eth_mac_initialize(int32_t idx, eth_event_cb_t cb_event); + +/** + \brief This function is used to de-initialize Ethernet device. It is called when the middleware component stops operation and releases the software resources used by the interface. + \param[in] handle ethernet handle + \return error code + */ +int32_t csi_eth_mac_uninitialize(eth_mac_handle_t handle); + +/** + \brief Connect phy device to mac device. + \param[in] handle_mac mac handle + \param[in] handle_phy phy handle +*/ +void csi_eth_mac_connect_phy(eth_mac_handle_t handle_mac, eth_phy_handle_t handle_phy); + +/** + \brief Control Ethernet MAC Device Power. + \param[in] handle ethernet handle + \param[in] state Power state + \return error code +*/ +int32_t csi_eth_mac_power_control(eth_mac_handle_t handle, eth_power_state_t state); + +/** + \brief Get Ethernet MAC Address. + \param[in] handle ethernet handle + \param[in] mac Pointer to address + \return error code +*/ +int32_t csi_eth_mac_get_macaddr(eth_mac_handle_t handle, eth_mac_addr_t *mac); + +/** + \brief Set Ethernet MAC Address. + \param[in] handle ethernet handle + \param[in] mac Pointer to address + \return error code +*/ +int32_t csi_eth_mac_set_macaddr(eth_mac_handle_t handle, const eth_mac_addr_t *mac); + +/** + \brief Configure Address Filter. + \param[in] handle ethernet handle + \param[in] addr Pointer to addresses + \param[in] num_addr Number of addresses to configure + \return error code +*/ +int32_t csi_eth_mac_set_addrfilter(eth_mac_handle_t handle, const eth_mac_addr_t *addr, uint32_t num_addr); + +/** + \brief Send Ethernet frame. + \param[in] handle ethernet handle + \param[in] frame Pointer to frame buffer with data to send + \param[in] len Frame buffer length in bytes + \param[in] flags Frame transmit flags (see CSI_ETH_MAC_TX_FRAME_...) + \return error code +*/ +int32_t csi_eth_mac_send_frame(eth_mac_handle_t handle, const uint8_t *frame, uint32_t len, uint32_t flags); + +/** + \brief Read data of received Ethernet frame. + \param[in] handle ethernet handle + \param[in] frame Pointer to frame buffer for data to read into + \param[in] len Frame buffer length in bytes + \return number of data bytes read or execution status + - value >= 0: number of data bytes read + - value < 0: error occurred, value is execution status as defined with execution_status +*/ +int32_t csi_eth_mac_read_frame(eth_mac_handle_t handle, uint8_t *frame, uint32_t len); + +/** + \brief Request data of received Ethernet frame. + csi_eth_mac_request_frame() and csi_eth_mac_release_frame() + must be called in pairs. + \param[in] handle ethernet handle + \param[in] frame Pointer to frame buffer pointer + \return number of data bytes read or execution status + - value >= 0: number of data bytes read + - value < 0: error occurred +*/ +int32_t csi_eth_mac_request_frame(eth_mac_handle_t handle, uint8_t **frame); + +/** + \brief Release current Ethernet frame. + csi_eth_mac_request_frame() and csi_eth_mac_release_frame() + must be called in pairs. + \param[in] handle ethernet handle + \return error code +*/ +int32_t csi_eth_mac_release_frame(eth_mac_handle_t handle); + +/** + \brief Get size of received Ethernet frame. + \param[in] handle ethernet handle + \return number of bytes in received frame +*/ +int32_t csi_eth_mac_get_rx_framesize(eth_mac_handle_t handle); + +/** + \brief Get time of received Ethernet frame. + \param[in] handle ethernet handle + \param[in] time Pointer to time structure for data to read into + \return error code +*/ +int32_t csi_eth_mac_get_rx_frametime(eth_mac_handle_t handle, eth_mac_time_t *time); + +/** + \brief Get time of transmitted Ethernet frame. + \param[in] handle ethernet handle + \param[in] time Pointer to time structure for data to read into + \return error code +*/ +int32_t csi_eth_mac_get_tx_frametime(eth_mac_handle_t handle, eth_mac_time_t *time); + +/** + \brief Control Ethernet Interface. + \param[in] handle ethernet handle + \param[in] control Operation + \param[in] arg Argument of operation (optional) + \return error code +*/ +int32_t csi_eth_mac_control(eth_mac_handle_t handle, uint32_t control, uint32_t arg); + +/** + \brief Control Precision Timer. + \param[in] handle ethernet handle + \param[in] control Operation + \param[in] time Pointer to time structure + \return error code +*/ +int32_t csi_eth_mac_control_time(eth_mac_handle_t handle, uint32_t control, eth_mac_time_t *time); + +/** + \brief Read Ethernet PHY Register through Management Interface. + \param[in] handle ethernet handle + \param[in] phy_addr 5-bit device address + \param[in] reg_addr 5-bit register address + \param[out] data Pointer where the result is written to + \return error code +*/ +int32_t csi_eth_mac_phy_read(eth_mac_handle_t handle, uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); + +/** + \brief Write Ethernet PHY Register through Management Interface. + \param[in] handle ethernet handle + \param[in] phy_addr 5-bit device address + \param[in] reg_addr 5-bit register address + \param[in] data 16-bit data to write + \return error code +*/ +int32_t csi_eth_mac_phy_write(eth_mac_handle_t handle, uint8_t phy_addr, uint8_t reg_addr, uint16_t data); + +/** + \brief Callback function that signals a Ethernet Event. + \param[in] handle ethernet handle + \param[in] event event notification mask + \return none +*/ +void csi_eth_mac_signal_event(eth_mac_handle_t handle, uint32_t event); + +/** + \brief Add Frame Filter Setting with Filter ID. + \param[in] handle ethernet handle + \param[in] filter Pointer to filter setting + \return error code +*/ +int32_t csi_eth_mac_add_framefilter(eth_mac_handle_t handle, const eth_frame_filter_t *filter); + +/** + \brief Remove Frame Filter Setting. + \param[in] handle ethernet handle + \param[in] filter_id Frame Filter ID + \return error code +*/ +int32_t csi_eth_mac_remove_framefilter(eth_mac_handle_t handle, uint32_t filter_id); + +/** + \brief Enable/Disable Specified Frame Filter ID. + \param[in] handle ethernet handle + \param[in] filter_id Frame Filter ID + \param[in] en Enable or disable + \return error code +*/ +int32_t csi_eth_mac_en_framefilter(eth_mac_handle_t handle, uint32_t filter_id, bool en); + +/** + \brief Get frame filter table list. + \param[in] handle ethernet handle + \param[in] list frame filter table list + \param[in] count_out the count of filter setting added + \param[in] max_count max filter setting can be supported + \return error code +*/ +int32_t csi_eth_mac_get_framefilter(eth_mac_handle_t handle, eth_frame_filter_list_t *list, uint32_t *count_out, uint32_t max_count); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/eth_phy.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/eth_phy.h new file mode 100644 index 00000000..5ef87565 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/eth_phy.h @@ -0,0 +1,124 @@ +/** + * Copyright (C) 2016 CSI Project. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _CSI_ETH_PHY_H_ +#define _CSI_ETH_PHY_H_ + +#include "drv/eth.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void *eth_phy_handle_t; + +#define CSI_ETH_PHY_API_VERSION CSI_ETH_VERSION_MAJOR_MINOR(2,1) /* API version */ + + +#define _CSI_Driver_ETH_PHY_(n) Driver_ETH_PHY##n +#define CSI_Driver_ETH_PHY_(n) _CSI_Driver_ETH_PHY_(n) + + +/****** Ethernet PHY Mode *****/ +#define CSI_ETH_PHY_SPEED_Pos 0 +#define CSI_ETH_PHY_SPEED_Msk (3UL << CSI_ETH_PHY_SPEED_Pos) +#define CSI_ETH_PHY_SPEED_10M (CSI_ETH_SPEED_10M << CSI_ETH_PHY_SPEED_Pos) ///< 10 Mbps link speed +#define CSI_ETH_PHY_SPEED_100M (CSI_ETH_SPEED_100M << CSI_ETH_PHY_SPEED_Pos) ///< 100 Mbps link speed +#define CSI_ETH_PHY_SPEED_1G (CSI_ETH_SPEED_1G << CSI_ETH_PHY_SPEED_Pos) ///< 1 Gpbs link speed +#define CSI_ETH_PHY_DUPLEX_Pos 2 +#define CSI_ETH_PHY_DUPLEX_Msk (1UL << CSI_ETH_PHY_DUPLEX_Pos) +#define CSI_ETH_PHY_DUPLEX_HALF (CSI_ETH_DUPLEX_HALF << CSI_ETH_PHY_DUPLEX_Pos) ///< Half duplex link +#define CSI_ETH_PHY_DUPLEX_FULL (CSI_ETH_DUPLEX_FULL << CSI_ETH_PHY_DUPLEX_Pos) ///< Full duplex link +#define CSI_ETH_PHY_AUTO_NEGOTIATE (1UL << 3) ///< Auto Negotiation mode +#define CSI_ETH_PHY_LOOPBACK (1UL << 4) ///< Loop-back test mode +#define CSI_ETH_PHY_ISOLATE (1UL << 5) ///< Isolate PHY from MII/RMII interface + +typedef int32_t (*csi_eth_phy_read_t)(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); ///< Read Ethernet PHY Register. +typedef int32_t (*csi_eth_phy_write_t)(uint8_t phy_addr, uint8_t reg_addr, uint16_t data); ///< Write Ethernet PHY Register. + +typedef struct { + csi_eth_phy_read_t phy_read; + csi_eth_phy_write_t phy_write; + eth_link_info_t link_info; +} eth_phy_priv_t; + +// Function documentation +/** + \brief Get driver version. + \param[in] handle ethernet phy handle + \return driver version +*/ +csi_drv_version_t csi_eth_phy_get_version(eth_phy_handle_t handle); + +/** + \brief Initialize Ethernet PHY Device. + \param[in] fn_read + \param[in] fn_write + \return ethernet phy handle +*/ +eth_phy_handle_t csi_eth_phy_initialize(csi_eth_phy_read_t fn_read, csi_eth_phy_write_t fn_write); + +/** + \brief De-initialize Ethernet PHY Device. + \param[in] handle ethernet phy handle + \return error code +*/ +int32_t csi_eth_phy_uninitialize(eth_phy_handle_t handle); + +/** + \brief Control Ethernet PHY Device Power. + \param[in] handle ethernet phy handle + \param[in] state Power state + \return error code +*/ +int32_t csi_eth_phy_power_control(eth_phy_handle_t handle, eth_power_state_t state); + +/** + \brief Set Ethernet Media Interface. + \param[in] handle ethernet phy handle + \param[in] interface Media Interface type + \return error code +*/ +int32_t csi_eth_phy_set_interface(eth_phy_handle_t handle, uint32_t interface); + +/** + \brief Set Ethernet PHY Device Operation mode. + \param[in] handle ethernet phy handle + \param[in] mode Operation Mode + \return error code +*/ +int32_t csi_eth_phy_set_mode(eth_phy_handle_t handle, uint32_t mode); + +/** + \brief Get Ethernet PHY Device Link state. + \param[in] handle ethernet phy handle + \return current link status \ref eth_link_state_t +*/ +eth_link_state_t csi_eth_phy_get_linkstate(eth_phy_handle_t handle); + +/** + \brief Get Ethernet PHY Device Link information. + \param[in] handle ethernet phy handle + \return current link parameters \ref eth_link_info_t +*/ +eth_link_info_t csi_eth_phy_get_linkinfo(eth_phy_handle_t handle); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/fft.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/fft.h new file mode 100755 index 00000000..a3cd312b --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/fft.h @@ -0,0 +1,87 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/fft.h + * @brief Header File for FFT Driver + * @version V1.0 + * @date 11. Nov 2020 + * @model fft + ******************************************************************************/ + +#ifndef _DRV_FFT_H_ +#define _DRV_FFT_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ///< 512-point FFT + CSKY_MCA_FFT_LEN_512 = 0x1, + ///< 256-point FFT + CSKY_MCA_FFT_LEN_256 = 0x2, + ///< 128-point FFT + CSKY_MCA_FFT_LEN_128 = 0x4, + ///< 64-point FFT + CSKY_MCA_FFT_LEN_64 = 0x8, + ///< 32-point FFT + CSKY_MCA_FFT_LEN_32 = 0x10, + ///< 16-point FFT + CSKY_MCA_FFT_LEN_16 = 0x20, +} csky_mca_fft_len_t; + +/* 8-bit fixed-point numeric type in user-defined format */ +typedef int8_t fxp8_t; + +/* 16-bit fixed-point numeric type in user-defined format */ +typedef int16_t fxp16_t; + +/* 24-bit fixed-point numeric type in user-defined format */ +typedef int32_t fxp24_t; + +/* 32-bit fixed-point numeric type in user-defined format */ +typedef int32_t fxp32_t; + +/* 64-bit fixed-point numeric type in user-defined format */ +typedef int64_t fxp64_t; + +/* 8-bit fixed-point numeric type in 1.0.7 format */ +typedef fxp8_t q7_t; + +/* 16-bit fixed-point numeric type in 1.0.15 format */ +typedef fxp16_t q15_t; + +/* 32-bit fixed-point numeric type in 1.15.16 format */ +typedef fxp32_t q16_t; + +void csky_mca_rfft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, size_t input_size, fxp32_t *output); +void csky_mca_cfft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, fxp32_t *output); +void csky_mca_rifft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, fxp32_t *output); +void csky_mca_cifft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, fxp32_t *output); +void csky_mca_power_spectrum_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, size_t input_size, fxp64_t *output); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_FFT_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/gpio.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/gpio.h new file mode 100755 index 00000000..fb8aed65 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/gpio.h @@ -0,0 +1,214 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/gpio.h + * @brief Header File for GPIO Driver + * @version V1.0 + * @date 8. Apr 2020 + * @model gpio + ******************************************************************************/ + +#ifndef _DRV_GPIO_H_ +#define _DRV_GPIO_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \enum csi_gpio_dir_t + * \brief GPIO dir define + */ +typedef enum { + GPIO_DIRECTION_INPUT = 0, ///< GPIO as input + GPIO_DIRECTION_OUTPUT, ///< GPIO as output +} csi_gpio_dir_t; + +/** + * \enum csi_gpio_pin_state_t + * \brief GPIO pin state define + */ +typedef enum { + GPIO_PIN_LOW = 0, ///< GPIO low level + GPIO_PIN_HIGH, ///< GPIO high level +} csi_gpio_pin_state_t; + +/** + * \enum csi_gpio_mode_t + * \brief GPIO mode define + */ +typedef enum { + GPIO_MODE_PULLNONE = 0, ///< Pull none + GPIO_MODE_PULLUP, ///< Pull up for input + GPIO_MODE_PULLDOWN, ///< Pull down for input + GPIO_MODE_OPEN_DRAIN, ///< Open drain mode for output + GPIO_MODE_PUSH_PULL, ///< Push-pull mode for output +} csi_gpio_mode_t; + +/** + * \enum csi_gpio_irq_mode_t + * \brief GPIO irq triger type + */ +typedef enum { + GPIO_IRQ_MODE_RISING_EDGE = 0, ///< Interrupt mode for rising edge + GPIO_IRQ_MODE_FALLING_EDGE, ///< Interrupt mode for falling edge + GPIO_IRQ_MODE_BOTH_EDGE, ///< Interrupt mode for both edge + GPIO_IRQ_MODE_LOW_LEVEL, ///< Interrupt mode for low level + GPIO_IRQ_MODE_HIGH_LEVEL, ///< Interrupt mode for high level +} csi_gpio_irq_mode_t; + +/** + * \struct csi_gpio_t + * \brief GPIO control block + */ + +typedef struct csi_gpio csi_gpio_t; +struct csi_gpio { + csi_dev_t dev; ///< Hw-dev info + void (*callback)(csi_gpio_t *gpio, uint32_t pins, void *arg); ///< Call-back of gpio port + void *arg; ///< User param passed to callback + void *priv; ///< User private param +}; + +/** + \brief Initialize GPIO Port handle + \param[in] gpio GPIO port handle + \param[in] port_idx GPIO port index + \return Error code +*/ +csi_error_t csi_gpio_init(csi_gpio_t *gpio, uint32_t port_idx); + +/** + \brief De-initialize GPIO pin.stops operation + releases the software resources used by the gpio-pin + \param[in] gpio GPIO port handle + \return None +*/ +void csi_gpio_uninit(csi_gpio_t *gpio); + +/** + \brief Config pin direction + \param[in] gpio GPIO port handle + \param[in] pin_mask Pin mask need to be set + \param[in] dir \ref csi_gpio_dir_t + \return Error code +*/ +csi_error_t csi_gpio_dir(csi_gpio_t *gpio, uint32_t pin_mask, csi_gpio_dir_t dir); + +/** + \brief Config pin mode + If one of pins config error, then the rest of pins will not config, and function return CSI_ERROR + If one or more pin unsupport, function will return CSI_UNSUPPORT, but the other pin still configured + \param[in] gpio GPIO port handle + \param[in] pin_mask Pin mask need to be set + \param[in] mode \ref csi_gpio_mode_t + \return Error code +*/ +csi_error_t csi_gpio_mode(csi_gpio_t *gpio, uint32_t pin_mask, csi_gpio_mode_t mode); + +/** + \brief Config gpio irq params + \param[in] gpio GPIO port handle + \param[in] pin_mask Pin mask need to be set + \param[in] mode Interrupt trigger mode \ref csi_gpio_irq_mode_t + \return Error code +*/ +csi_error_t csi_gpio_irq_mode(csi_gpio_t *gpio, uint32_t pin_mask, csi_gpio_irq_mode_t mode); + +/** + \brief Enable or disable gpio pin interrupt + \param[in] gpio GPIO port handle + \param[in] pin_mask Pin mask need to be set + \param[in] enable 0:disable 1:enable + \return Error code +*/ +csi_error_t csi_gpio_irq_enable(csi_gpio_t *gpio, uint32_t pin_mask, bool enable); + +/** + \brief Set debounce of gpio when gpio configed as input + \param[in] gpio GPIO port handle + \param[in] pin_mask Pin mask need to be set + \param[in] enbale 0: disable 1:enable + \return Error code +*/ +csi_error_t csi_gpio_debounce(csi_gpio_t *gpio, uint32_t pin_mask, bool enable); +/** + \brief Set one or zero to the selected pin mask + \param[in] gpio GPIO port handle + \param[in] pin_mask Pin mask need to be set + \param[in] value Value to be set \ref csi_gpio_pin_state_t + \return None +*/ +void csi_gpio_write(csi_gpio_t *gpio, uint32_t pin_mask, csi_gpio_pin_state_t value); + +/** + \brief Toggle output gpio value,ex.if previous value is 1, then output 0 + \param[in] gpio GPIO port handle + \param[in] pin_mask Pin mask need to be set + \return None +*/ +void csi_gpio_toggle(csi_gpio_t *gpio, uint32_t pin_mask); + +/** + \brief Get the value of selected GPIO pin mask + \param[in] gpio GPIO port handle + \param[in] pin_mask Pin mask need to be set + \return According to the bit mask, the corresponding pin status is obtained +*/ +uint32_t csi_gpio_read(csi_gpio_t *gpio, uint32_t pin_mask); + +/** + \brief Attach the interrupt callback to the port + \param[in] gpio GPIO port handle + \param[in] callback Callback function + \param[in] arg User param passed to callback + \return Error code +*/ +csi_error_t csi_gpio_attach_callback(csi_gpio_t *gpio, void *callback, void *arg); + +/** + \brief Detach the interrupt callback to the port + \param[in] gpio GPIO port handle + \return None +*/ +void csi_gpio_detach_callback(csi_gpio_t *gpio); + +/** + \brief Enable gpio power manage + \param[in] gpio GPIO handle to operate + \return Error code +*/ +csi_error_t csi_gpio_enable_pm(csi_gpio_t *gpio); + +/** + \brief Disable gpio power manage + \param[in] gpio GPIO handle to operate + \return None +*/ +void csi_gpio_disable_pm(csi_gpio_t *gpio); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_GPIO_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/gpio_pin.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/gpio_pin.h new file mode 100755 index 00000000..1cb81fc3 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/gpio_pin.h @@ -0,0 +1,144 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/gpio_pin.h + * @brief Header File for GPIO PIN Driver + * @version v1.0 + * @date 2020-06-28 + * @note Only one of gpio or gpio_pin interface can be selected + ******************************************************************************/ + +#ifndef _DRV_GPIO_PIN_H_ +#define _DRV_GPIO_PIN_H_ + +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \struct csi_gpio_pin_t + * \brief GPIO PIN control block + */ + +typedef struct csi_gpio_pin csi_gpio_pin_t; +struct csi_gpio_pin { + csi_gpio_t *gpio; + uint32_t pin_idx; + void (*callback)(csi_gpio_pin_t *pin, void *arg); + void *arg; +}; + +/** + \brief Initialize GPIO pin handle + \param[in] pin GPIO pin handle + \param[in] pin_name GPIO pin name + \return Error code +*/ +csi_error_t csi_gpio_pin_init(csi_gpio_pin_t *pin, pin_name_t pin_name); + +/** + \brief De-initialize GPIO pin + \param[in] pin GPIO pin handle + \return None +*/ +void csi_gpio_pin_uninit(csi_gpio_pin_t *pin); + +/** + \brief Attach the interrupt callback to the GPIO pin + \param[in] pin GPIO pin handle + \param[in] callback Callback function + \param[in] arg User param passed to callback + \return Error code +*/ +csi_error_t csi_gpio_pin_attach_callback(csi_gpio_pin_t *pin, void *callback, void *arg); + +/** + \brief Config pin direction + \param[in] pin GPIO pin handle + \param[in] dir \ref csi_gpio_dir_t + \return Error code +*/ +csi_error_t csi_gpio_pin_dir(csi_gpio_pin_t *pin, csi_gpio_dir_t dir); + +/** + \brief Config pin mode + \param[in] pin GPIO pin handle + \param[in] mode \ref csi_gpio_mode_t + \return Error code +*/ +csi_error_t csi_gpio_pin_mode(csi_gpio_pin_t *pin, csi_gpio_mode_t mode); + +/** + \brief Config pin irq params + \param[in] pin GPIO pin handle + \param[in] mode Interrupt trigger mode \ref csi_gpio_irq_mode_t + \return Error code +*/ +csi_error_t csi_gpio_pin_irq_mode(csi_gpio_pin_t *pin, csi_gpio_irq_mode_t mode); + +/** + \brief Enable or disable gpio pin interrupt + \param[in] pin GPIO pin handle + \param[in] enable 0:disable 1:enable + \return Error code +*/ +csi_error_t csi_gpio_pin_irq_enable(csi_gpio_pin_t *pin, bool enable); + +/** + \brief Set debounce of pin when pin configed as input + \param[in] pin GPIO pin handle + \param[in] enbale 0: disable 1:enable + \return Error code +*/ +csi_error_t csi_gpio_pin_debounce(csi_gpio_pin_t *pin, bool enable); + +/** + \brief Set one or zero to specified pin + \param[in] pin GPIO pin handle + \param[in] value Value to be set \ref csi_gpio_pin_state_t + \return None +*/ +void csi_gpio_pin_write(csi_gpio_pin_t *pin, csi_gpio_pin_state_t value); + +/** + \brief Toggle output pin value,ex.if previous value is 1, then output 0 + \param[in] pin GPIO pin handle + \return None +*/ +void csi_gpio_pin_toggle(csi_gpio_pin_t *pin); + +/** + \brief Get the value of specified GPIO pin + \param[in] pin GPIO port handle + \return gpio pin state, \ref csi_gpio_pin_state_t +*/ +csi_gpio_pin_state_t csi_gpio_pin_read(csi_gpio_pin_t *pin); + +#ifdef __cplusplus +} +#endif + +#endif /* _GPIO_PIN_H_*/ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/hmac.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/hmac.h new file mode 100644 index 00000000..1033306e --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/hmac.h @@ -0,0 +1,122 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/****************************************************************************** + * @file drv/hmac.h + * @brief Header File for HMAC + * @version V1.0 + * @date 27. Apri 2023 + * @model hmac + ******************************************************************************/ +#ifndef _DRV_HMAC_H_ +#define _DRV_HMAC_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/****** HMAC Event ******/ +typedef enum { + HMAC_EVENT_COMPLETE = 0U, /* Calculate completed */ + HMAC_EVENT_ERROR /* Calculate error */ +} csi_hmac_event_t; + +/****** HMAC Context ******/ +typedef struct { + csi_sha_mode_t mode; /* SHA mode */ + uint32_t total[2]; /* Number of bytes processed */ + uint8_t buffer[128]; /* Data block being processed */ +} csi_hmac_context_t; + +/****** HMAC Ctrl ******/ +typedef struct csi_hmac { + csi_dev_t dev; + void *priv; +}csi_hmac_t; + +/** + \brief Initialize MAC Interface. Initializes the resources needed for the MAC interface + \param[in] mac operate handle. + \param[in] idx index of mac + \return error code \ref csi_error_t +*/ +csi_error_t csi_hmac_init(csi_hmac_t *mac, uint32_t idx); + +/** + \brief De-initialize MAC Interface. stops operation and releases the software resources used by the interface + \param[in] mac mac handle to operate. + \return none +*/ +void csi_hmac_uninit(csi_hmac_t *mac); + +/** + \brief MAC set key function. + \param[in] mac mac handle to operate. + \param[in] key Pointer to the mac key. + \param[in] key_len Length of key. + \return error code \ref csi_error_t +*/ +csi_error_t csi_hmac_set_key(csi_hmac_t *mac, uint8_t *key, uint32_t key_len); + +/** + \brief MAC start operation function. + \param[in] mac mac handle to operate. + \param[in] context mac context pointer. + \param[in] mode sc_sha_mode_t. + \return error code \ref csi_error_t +*/ +csi_error_t csi_hmac_start(csi_hmac_t *mac, csi_hmac_context_t *context, csi_sha_mode_t mode); + +/** + \brief MAC start operation function. + \param[in] mac mac handle to operate. + \param[in] msg Pointer to the mac input message. + \param[in] msg_len Length of msg. + \return error code \ref csi_error_t +*/ +csi_error_t csi_hmac_update(csi_hmac_t *mac, csi_hmac_context_t *context, uint8_t *msg, uint32_t msg_len); + +/** + \brief MAC start operation function. + \param[in] mac mac handle to operate. + \param[out] out mac buffer, malloc by caller. + \param[out] out_len out mac length, + \return error code \ref csi_error_t +*/ +csi_error_t csi_hmac_finish(csi_hmac_t *mac, csi_hmac_context_t *context, uint8_t *out, uint32_t *out_len); + +/** + \brief MAC cacl operation function. + \param[in] mac mac handle to operate. + \param[in] mode sc_sha_mode_t. + \param[in] msg Pointer to the mac input message. + \param[in] msg_len Length of msg. + \param[out] out mac buffer, malloc by caller. + \param[out] out_len out mac length, + \return error code \ref csi_error_t +*/ +csi_error_t csi_hmac_calc(csi_hmac_t *mac, csi_sha_mode_t mode, uint8_t *msg, + uint32_t msg_len, uint8_t *out, uint32_t *out_len); +#ifdef __cplusplus +} +#endif + +#endif /* _SC_MAC_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/i2s.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/i2s.h new file mode 100755 index 00000000..f783d21d --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/i2s.h @@ -0,0 +1,397 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/i2s.h + * @brief header file for i2s driver + * @version V1.0 + * @date 16. Mar 2020 + * @model i2s + ******************************************************************************/ + +#ifndef _DRV_I2S_H_ +#define _DRV_I2S_H_ + +#include +#include +#include +#include +#include "drv/ringbuf.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + I2S_MODE_MASTER, ///< I2s transmitter master mode + I2S_MODE_SLAVE, ///< I2s transmitter slave mode +} csi_i2s_mode_t; + +typedef enum { + I2S_PROTOCOL_I2S, ///< I2S protocol + I2S_PROTOCOL_MSB_JUSTIFIED, ///< MSB (left) justified protocol + I2S_PROTOCOL_LSB_JUSTIFIED, ///< LSB (right) justified protocol + I2S_PROTOCOL_PCM, ///< PCM protocol +} csi_i2s_protocol_t; + +typedef enum { + I2S_LEFT_POLARITY_LOW, ///< Low level represents the left channel + I2S_LEFT_POLARITY_HIGH, ///< High level represents the left channel +} csi_i2s_ws_left_polarity_t; + +typedef enum { + I2S_SAMPLE_RATE_8000 = 8000U, ///< I2S sample rate is 8000 + I2S_SAMPLE_RATE_11025 = 11025U, + I2S_SAMPLE_RATE_12000 = 12000U, + I2S_SAMPLE_RATE_16000 = 16000U, + I2S_SAMPLE_RATE_22050 = 22050U, + I2S_SAMPLE_RATE_24000 = 24000U, + I2S_SAMPLE_RATE_32000 = 32000U, + I2S_SAMPLE_RATE_44100 = 44100U, + I2S_SAMPLE_RATE_48000 = 48000U, + I2S_SAMPLE_RATE_96000 = 96000U, + I2S_SAMPLE_RATE_192000 = 192000U, + I2S_SAMPLE_RATE_256000 = 256000U, +} csi_i2s_sample_rate_t; + +typedef enum { + I2S_SAMPLE_WIDTH_16BIT = 16U, ///< I2S sample width is 16bit + I2S_SAMPLE_WIDTH_24BIT = 24U, + I2S_SAMPLE_WIDTH_32BIT = 32U, +} csi_i2s_sample_width_t; + +typedef enum { + I2S_SCLK_16FS = 16U, ///< SCLK frequency is 16 times that of I2S sample rate + I2S_SCLK_32FS = 32U, + I2S_SCLK_48FS = 48U, + I2S_SCLK_64FS = 64U, +} csi_i2s_sclk_freq_t; + +typedef enum { + I2S_MCLK_256FS = 256U, ///< MCLK frequency is 256 times that of I2S sample rate + I2S_MCLK_384FS = 384U, +} csi_i2s_mclk_freq_t; + +typedef struct { + csi_i2s_mode_t mode; ///< I2S work mode + csi_i2s_protocol_t protocol; ///< Protocols used by I2S + csi_i2s_ws_left_polarity_t polarity; ///< left channel polarity + csi_i2s_sample_rate_t rate; ///< I2S sample rate + csi_i2s_sample_width_t width; ///< I2S sample width + csi_i2s_sclk_freq_t sclk_nfs; ///< SCLK frequency is N times that of I2S sample rate + csi_i2s_mclk_freq_t mclk_nfs; ///< MCLK frequency is N times that of I2S sample rate +} csi_i2s_format_t; + +typedef enum { + I2S_LEFT_CHANNEL, + I2S_RIGHT_CHANNEL, + I2S_LEFT_RIGHT_CHANNEL, +} csi_i2s_sound_channel_t; + +typedef enum { + I2S_EVENT_SEND_COMPLETE, + I2S_EVENT_RECEIVE_COMPLETE, + I2S_EVENT_TX_BUFFER_EMPTY, + I2S_EVENT_RX_BUFFER_FULL, + I2S_EVENT_ERROR_OVERFLOW, + I2S_EVENT_ERROR_UNDERFLOW, + I2S_EVENT_ERROR, +} csi_i2s_event_t; + +typedef struct csi_i2s csi_i2s_t; + +struct csi_i2s { + csi_dev_t dev; ///< I2S hw-device info + void (*callback)(csi_i2s_t *i2s, csi_i2s_event_t event, void *arg); ///< I2S event callback for user + void *arg; ///< user private param passed to user callback + csi_ringbuf_t *tx_buf; ///< I2S send buffer + csi_ringbuf_t *rx_buf; ///< I2S receive buffer + csi_dma_ch_t *tx_dma; ///< send dma channel handle + csi_dma_ch_t *rx_dma; ///< receive dma channel handle + uint32_t tx_period; ///< I2S send period num data will callback + uint32_t rx_period; ///< I2S receive period num data will callback + csi_state_t state; ///< I2S communication state + void *priv; +}; + +/** + \brief Init i2s + \param[in] i2s I2s handle to operate + \param[in] idx I2s interface idx + \return error code \ref csi_error_t +*/ +csi_error_t csi_i2s_init(csi_i2s_t *i2s, uint32_t idx); + +/** + \brief Uninit i2s + \param[in] i2s I2s handle to operate + \return none +*/ +void csi_i2s_uninit(csi_i2s_t *i2s); + +/** + \brief Enable i2s + \param[in] i2s I2s handle to operate + \param[in] en True enable, False disable + \return None +*/ +void csi_i2s_enable(csi_i2s_t *i2s, bool enable); + +/** + \brief I2s config format + \param[in] i2s I2s handle to operate + \param[in] format I2s config param \ref csi_i2s_format_t + \return error code \ref csi_error_t +*/ +csi_error_t csi_i2s_format(csi_i2s_t *i2s, csi_i2s_format_t *format); + +/** + \brief Set the i2s tx mono + \param[in] i2s I2s handle to operate + \param[in] ch Mono channel selection + \return error code \ref csi_error_t +*/ +csi_error_t csi_i2s_tx_select_sound_channel(csi_i2s_t *i2s, csi_i2s_sound_channel_t ch); + +/** + \brief Set the i2s rx mono + \param[in] i2s I2s handle to operate + \param[in] ch Mono channel selection + \return error code \ref csi_error_t +*/ +csi_error_t csi_i2s_rx_select_sound_channel(csi_i2s_t *i2s, csi_i2s_sound_channel_t ch); + +/** + \brief Link DMA channel to i2s device + \param[in] i2s I2s handle to operate + \param[in] rx_dma The DMA channel for receive, when it is NULL means to unused dma + \return error code \ref csi_error_t +*/ +csi_error_t csi_i2s_rx_link_dma(csi_i2s_t *i2s, csi_dma_ch_t *rx_dma); + +/** + \brief Link DMA channel to i2s device + \param[in] i2s I2s handle to operate + \param[in] tx_dma The DMA channel for send, when it is NULL means to unused dma + \return error code \ref csi_error_t +*/ +csi_error_t csi_i2s_tx_link_dma(csi_i2s_t *i2s, csi_dma_ch_t *tx_dma); + +/** + \brief I2s rx buffer config + \param[in] i2s I2s handle to operate + \param[in] buffer I2s rx buffer + \return None +*/ +void csi_i2s_rx_set_buffer(csi_i2s_t *i2s, csi_ringbuf_t *buffer); + +/** + \brief I2s tx buffer config + \param[in] i2s I2s handle to operate + \param[in] buffer I2s tx buffer + \return None +*/ +void csi_i2s_tx_set_buffer(csi_i2s_t *i2s, csi_ringbuf_t *buffer); + +/** + \brief I2s rx set period.The value of period is to report a receive completion event + after each period value data is received + \param[in] i2s I2s handle to operate + \param[in] period I2s rx period + \return error code \ref csi_error_t +*/ +csi_error_t csi_i2s_rx_set_period(csi_i2s_t *i2s, uint32_t period); + +/** + \brief I2s tx set period.The value of period is to report a receive completion event + after each period value data is send + \param[in] i2s I2s handle to operate + \param[in] period I2s tx period + \return error code \ref csi_error_t +*/ +csi_error_t csi_i2s_tx_set_period(csi_i2s_t *i2s, uint32_t period); + +/** + \brief Get rx csi_ringbuf buffer free space + \param[in] i2s I2s handle to operate + \return Buffer free space (bytes) +*/ +uint32_t csi_i2s_rx_buffer_avail(csi_i2s_t *i2s); + +/** + \brief Get rx csi_ringbuf buffer used space + \param[in] i2s I2s handle to operate + \return Buffer used space (bytes) +*/ +uint32_t csi_i2s_rx_buffer_remain(csi_i2s_t *i2s); + +/** + \brief Reset the rx csi_ringbuf, discard all data in the buffer + \param[in] i2s I2s handle to operate + \return error code \ref csi_error_t +*/ +csi_error_t csi_i2s_rx_buffer_reset(csi_i2s_t *i2s); + +/** + \brief Get tx csi_ringbuf buffer free space + \param[in] i2s I2s handle to operate + \return Buffer free space (bytes) +*/ +uint32_t csi_i2s_tx_buffer_avail(csi_i2s_t *i2s); + +/** + \brief Get tx csi_ringbuf buffer used space + \param[in] i2s I2s handle to operate + \return Buffer used space (bytes) +*/ +uint32_t csi_i2s_tx_buffer_remain(csi_i2s_t *i2s); + +/** + \brief Reset the tx csi_ringbuf, discard all data in the buffer + \param[in] i2s Handle to operate + \return error code \ref csi_error_t +*/ +csi_error_t csi_i2s_tx_buffer_reset(csi_i2s_t *i2s); + +/** + \brief Send an amount of data to buffer in blocking mode + \param[in] i2s Operate handle + \param[in] data Pointer to send data buffer + \param[in] size Send data size + \return The num of data witch is send successful +*/ +int32_t csi_i2s_send(csi_i2s_t *i2s, const void *data, uint32_t size); + +/** + \brief Receive an amount of data to buffer in blocking mode + \param[in] i2s Operate handle + \param[out] data Pointer to receive data buffer + \param[in] size Receive data size + \return The size of data receive successfully +*/ +int32_t csi_i2s_receive(csi_i2s_t *i2s, void *data, uint32_t size); + +/** + \brief Write data to the buffer + With asynchronous sending + The data is first written to the buffer and then output through the i2s interface + Return value is the number of data that was successfully written to the buffer + \param[in] i2s Operate handle + \param[in] data Pointer to send data buffer + \param[in] size Send data size + \return The data size that write to buffer +*/ +uint32_t csi_i2s_send_async(csi_i2s_t *i2s, const void *data, uint32_t size); + +/** + \brief Read data from the buffer + Using asynchronous receive, i2s writes the received data to the buffer + This function reads data from the buffer, returns the number of successful reads + Returns 0 if there is no data in the buffer + \param[in] i2s Operate handle + \param[out] data Pointer to receive data buffer + \param[in] size Receive data size + \return The size of data read successfully +*/ +uint32_t csi_i2s_receive_async(csi_i2s_t *i2s, void *data, uint32_t size); + +/** + \brief Start i2s pause asynchronous send + \param[in] i2s Operate handle + \return error code \ref csi_error_t +*/ +csi_error_t csi_i2s_send_pause(csi_i2s_t *i2s); + +/** + \brief Start i2s resume asynchronous send + \param[in] i2s Operate handle + \return error code \ref csi_error_t +*/ +csi_error_t csi_i2s_send_resume(csi_i2s_t *i2s); + +/** + \brief Start i2s asynchronous send + \param[in] i2s Operate handle + \return error code \ref csi_error_t +*/ +csi_error_t csi_i2s_send_start(csi_i2s_t *i2s); + +/** + \brief Start i2s asynchronous receive + \param[in] i2s Operate handle + \return error code \ref csi_error_t +*/ +csi_error_t csi_i2s_receive_start(csi_i2s_t *i2s); + +/** + \brief Stop i2s asynchronous send + \param[in] i2s Operate handle + \return None +*/ +void csi_i2s_send_stop(csi_i2s_t *i2s); + +/** + \brief Stop i2s asynchronous receive + \param[in] i2s Operate handle + \return None +*/ +void csi_i2s_receive_stop(csi_i2s_t *i2s); + +/** + \brief Attach the callback handler to i2s + \param[in] i2s Operate handle + \param[in] cb Callback function + \param[in] arg User private param + \return error code \ref csi_error_t +*/ +csi_error_t csi_i2s_attach_callback(csi_i2s_t *i2s, void *callback, void *arg); + +/** + \brief Detach the callback handler + \param[in] i2s Operate handle + \return None +*/ +void csi_i2s_detach_callback(csi_i2s_t *i2s); + +/** + \brief Get i2s status + \param[in] i2s I2s handle to operate + \param[out] state I2s state + \return error code \ref csi_error_t +*/ +csi_error_t csi_i2s_get_state(csi_i2s_t *i2s, csi_state_t *state); + +/** + \brief Enable i2s power manage + \param[in] i2s I2s handle to operate + \return error code \ref csi_error_t +*/ +csi_error_t csi_i2s_enable_pm(csi_i2s_t *i2s); + +/** + \brief Disable i2s power manage + \param[in] i2s I2s handle to operate + \return None +*/ +void csi_i2s_disable_pm(csi_i2s_t *i2s); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_I2S_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/iic.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/iic.h new file mode 100755 index 00000000..ee46ea22 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/iic.h @@ -0,0 +1,338 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file iic.h + * @brief header file for iic driver + * @version V1.0 + * @date 08. Apr 2020 + * @model iic + ******************************************************************************/ + +#ifndef _DRV_IIC_H_ +#define _DRV_IIC_H_ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \enum csi_iic_mode_t + \brief iic work in master/slave mode + */ +typedef enum { + IIC_MODE_MASTER = 0U, ///< IIC master + IIC_MODE_SLAVE ///< IIC slave +} csi_iic_mode_t; + +/** + \enum csi_iic_speed_t + \brief iic speed mode + */ +typedef enum { + IIC_BUS_SPEED_STANDARD = 0U, ///< Standard Speed (<=100kHz) + IIC_BUS_SPEED_FAST, ///< Fast Speed (<=400kHz) + IIC_BUS_SPEED_FAST_PLUS, ///< Fast plus Speed (<= 1MHz) + IIC_BUS_SPEED_HIGH ///< High Speed (<=3.4MHz) +} csi_iic_speed_t; + +/** + \enum csi_iic_address_mode_t + \brief iic address mode + */ +typedef enum { + IIC_ADDRESS_7BIT = 0U, ///< 7-bit address mode + IIC_ADDRESS_10BIT ///< 10-bit address mode +} csi_iic_addr_mode_t; + +/** + \enum csi_iic_mem_addr_size_t + \brief iic memory address size + */ +typedef enum { + IIC_MEM_ADDR_SIZE_8BIT = 0U, ///< IIC e2prom 8bit address mode + IIC_MEM_ADDR_SIZE_16BIT ///< IIC e2prom 16bit address mode +} csi_iic_mem_addr_size_t; + +/** + \enum csi_iic_event_t + \brief iic event signaled by iic driver + */ +typedef enum { + IIC_EVENT_SEND_COMPLETE = 0U, ///< Master/slave Send finished + IIC_EVENT_RECEIVE_COMPLETE, ///< Master/slave Receive finished + IIC_EVENT_ERROR_OVERFLOW, ///< Master/slave fifo overflow error + IIC_EVENT_ERROR_UNDERFLOW, ///< Master/slave fifo underflow error + IIC_EVENT_ERROR ///< The receive buffer was completely filled to FIFO and more data arrived. That data is lost +} csi_iic_event_t; + +/** + \struct csi_iic_t + \brief iic ctrl block + */ +typedef struct csi_iic csi_iic_t; +struct csi_iic { + csi_dev_t dev; ///< IIC hw-device info + void (*callback)(csi_iic_t *iic, csi_iic_event_t event, void *arg); ///< IIC event callback for user + void *arg; ///< User private param passed to user callback + uint8_t *data; ///< IIC transfer-data buffer + uint32_t size; ///< IIC transfer-data size + csi_iic_mode_t mode; ///< IIC mode + csi_dma_ch_t *tx_dma; ///< Send dma channel handle + csi_dma_ch_t *rx_dma; ///< Receive dma channel handle + void *send; ///< Send function pointer asynchronously + void *receive; ///< Receive function pointer asynchronously + csi_state_t state; ///< IIC current state + void *priv; +}; + +typedef csi_error_t (*csi_iic_master_send_async_t)(csi_iic_t *iic, uint32_t devaddr, const void *data, uint32_t size); +typedef csi_error_t (*csi_iic_master_receive_async_t)(csi_iic_t *iic, uint32_t devaddr, void *data, uint32_t size); +typedef csi_error_t (*csi_iic_slave_send_async_t)(csi_iic_t *iic, const void *data, uint32_t size); +typedef csi_error_t (*csi_iic_slave_receive_async_t)(csi_iic_t *iic, void *data, uint32_t size); + +/** + \brief Init iic ctrl block + Initializes the resources needed for the iic instance + \param[in] iic Handle of iic instance + \param[in] idx Index of instance + \return error code \ref csi_error_t +*/ +csi_error_t csi_iic_init(csi_iic_t *iic, uint32_t idx); + +/** + \brief Uninit iic ctrl block + Stops operation and releases the software resources used by the instance + \param[in] iic Handle of iic instance + \return None +*/ +void csi_iic_uninit(csi_iic_t *iic); + +/** + \brief Config iic master or slave mode + \param[in] iic Handle of iic instance + \param[in] mode iic mode \ref csi_iic_mode_t + \return error code \ref csi_error_t +*/ +csi_error_t csi_iic_mode(csi_iic_t *iic, csi_iic_mode_t mode); + +/** + \brief Config iic addr mode + \param[in] iic Handle of iic instance + \param[in] addr_mode iic addr mode \ref csi_iic_addr_mode_t + \return error code \ref csi_error_t +*/ +csi_error_t csi_iic_addr_mode(csi_iic_t *iic, csi_iic_addr_mode_t addr_mode); + +/** + \brief Config iic speed + \param[in] iic Handle of iic instance + \param[in] speed iic speed mode \ref csi_iic_speed_t + \return error code \ref csi_error_t +*/ +csi_error_t csi_iic_speed(csi_iic_t *iic, csi_iic_speed_t speed); + +/** + \brief Config iic own addr + \param[in] iic Handle of iic instance + \param[in] own_addr iic set own addr at slave mode + \return error code \ref csi_error_t +*/ +csi_error_t csi_iic_own_addr(csi_iic_t *iic, uint32_t own_addr); + +/** + \brief Start sending data as iic master + This function is blocking + \param[in] iic Handle of iic instance + \param[in] devaddr Addrress of slave device + \param[in] data Pointer to send data buffer + \param[in] size Size of data items to send + \param[in] timout Unit of time delay(ms) + \return The amount of real data sent or error code +*/ +int32_t csi_iic_master_send(csi_iic_t *iic, uint32_t devaddr, const void *data, uint32_t size, uint32_t timeout); + +/** + \brief Start receiving data as iic master + This function is blocking + \param[in] iic Handle to operate + \param[in] devaddr iic addrress of slave device + \param[out] data Pointer to buffer for data to receive from iic receiver + \param[in] size Size of data items to receive + \param[in] timeout Unit of time delay(ms) + \return The amount of real data received or error code +*/ +int32_t csi_iic_master_receive(csi_iic_t *iic, uint32_t devaddr, void *data, uint32_t size, uint32_t timeout); + +/** + \brief Start sending data as iic master + This function is non-blocking,\ref csi_iic_event_t is signaled when transfer completes or error happens + \param[in] iic Handle to operate + \param[in] devaddr iic addrress of slave device + \param[in] data Pointer to send data buffer + \param[in] size Size of data items to send + \return error code \ref csi_error_t +*/ +csi_error_t csi_iic_master_send_async(csi_iic_t *iic, uint32_t devaddr, const void *data, uint32_t size); + +/** + \brief Start receiving data as iic master. + This function is non-blocking.\ref csi_iic_event_t is signaled when transfer completes or error happens + \param[in] iic Handle to operate + \param[in] devaddr iic addrress of slave device + \param[out] data Pointer to buffer for data to receive from iic receiver + \param[in] size Size of data items to receive + \return error code \ref csi_error_t +*/ +csi_error_t csi_iic_master_receive_async(csi_iic_t *iic, uint32_t devaddr, void *data, uint32_t size); + +/** + \brief Start sending data as iic master + This function is blocking + \param[in] iic Handle of iic instance + \param[in] devaddr Addrress of slave device + \param[in] memaddr Internal addr of device + \param[in] memaddr_size Internal addr mode of device + \param[in] data Pointer to send data buffer + \param[in] size Size of data items to send + \param[in] timout Unit of time delay(ms) + \return The amount of real data sent or error code +*/ +int32_t csi_iic_mem_send(csi_iic_t *iic, uint32_t devaddr, uint16_t memaddr, csi_iic_mem_addr_size_t memaddr_size, const void *data, uint32_t size, uint32_t timeout); + +/** + \brief Start receiving data as iic master + This function is blocking + \param[in] iic Handle to operate + \param[in] devaddr iic addrress of slave device + \param[in] memaddr Internal addr of device + \param[in] memaddr_mode Internal addr mode of device + \param[out] data Pointer to buffer for data to receive from eeprom device + \param[in] size Size of data items to receive + \param[in] timeout Unit of time delay(ms) + \return The amount of real data received or error code +*/ +int32_t csi_iic_mem_receive(csi_iic_t *iic, uint32_t devaddr, uint16_t memaddr, csi_iic_mem_addr_size_t memaddr_size, void *data, uint32_t size, uint32_t timeout); + +/** + \brief Start sending data as iic slave + This function is blocking + \param[in] iic Handle to operate + \param[in] data Pointer to buffer with data to send to iic master + \param[in] size Size of data items to send + \param[in] timeout Unit of time delay(ms) + \return The amount of real data sent or error code +*/ +int32_t csi_iic_slave_send(csi_iic_t *iic, const void *data, uint32_t size, uint32_t timeout); + +/** + \brief Start receiving data as iic slave + This function is blocking + \param[in] iic Handle to operate + \param[out] data Pointer to buffer for data to receive from iic master + \param[in] size Size of data items to receive + \param[in] timeout Unit of time delay(ms) + \return The amount of real data received or error code +*/ +int32_t csi_iic_slave_receive(csi_iic_t *iic, void *data, uint32_t size, uint32_t timeout); + +/** + \brief Start sending data as iic slave + This function is non-blocking,\ref csi_iic_event_t is signaled when transfer completes or error happens + \param[in] iic Handle to operate + \param[in] data Pointer to buffer with data to send to iic master + \param[in] size Size of data items to send + \return error code \ref csi_error_t +*/ +csi_error_t csi_iic_slave_send_async(csi_iic_t *iic, const void *data, uint32_t size); + +/** + \brief Start receiving data as iic slave + This function is non-blocking,\ref csi_iic_event_t is signaled when transfer completes or error happens + \param[in] handle iic handle to operate + \param[out] data Pointer to buffer for data to receive from iic master + \param[in] size Size of data items to receive + \return error code \ref csi_error_t +*/ +csi_error_t csi_iic_slave_receive_async(csi_iic_t *iic, void *data, uint32_t size); + +/** + \brief Attach callback to the iic + \param[in] iic iic handle to operate + \param[in] cb Event callback function \ref csi_iic_callback_t + \param[in] arg User private param for event callback + \return error code \ref csi_error_t +*/ +csi_error_t csi_iic_attach_callback(csi_iic_t *iic, void *callback, void *arg); + +/** + \brief Detach callback from the iic + \param[in] iic iic handle to operate + \return None +*/ +void csi_iic_detach_callback(csi_iic_t *iic); + +/** + \brief Config iic stop to generate + \param[in] iic iic handle to operate + \param[in] enable Transfer operation is pending - stop condition will not be generated + \return error code \ref csi_error_t +*/ +csi_error_t csi_iic_xfer_pending(csi_iic_t *iic, bool enable); + +/** + \brief Link DMA channel to iic device + \param[in] iic Handle to operate + \param[in] tx_dma The DMA channel handle for send, when it is NULL means to unlink the channel + \param[in] rx_dma The DMA channel handle for receive, when it is NULL means to unlink the channel + \return error code \ref csi_error_t +*/ +csi_error_t csi_iic_link_dma(csi_iic_t *iic, csi_dma_ch_t *tx_dma, csi_dma_ch_t *rx_dma); + +/** + \brief Get iic state + \param[in] iic Handle to operate + \param[out] state iic state \ref csi_state_t + \return error code \ref csi_error_t +*/ +csi_error_t csi_iic_get_state(csi_iic_t *iic, csi_state_t *state); + +/** + \brief Enable iic power manage + \param[in] iic iic handle to operate + \return error code \ref csi_error_t +*/ +csi_error_t csi_iic_enable_pm(csi_iic_t *iic); + +/** + \brief Disable iic power manage + \param[in] iic iic handle to operate + \return None +*/ +void csi_iic_disable_pm(csi_iic_t *iic); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_IIC_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/intc.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/intc.h new file mode 100755 index 00000000..573f33eb --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/intc.h @@ -0,0 +1,178 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/intc.h + * @brief Header File for INTC Driver + * @version V1.0 + * @date 02. June 2020 + * @model intc + ******************************************************************************/ + +#ifndef _DRV_INTC_H_ +#define _DRV_INTC_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif +typedef enum int_trigger_mode_t { + INT_MODE_LOW_LEVEL, + INT_MODE_HIGH_LEVEL, + INT_MODE_RISING_EDGE, + INT_MODE_FALLING_EDGE, + INT_MODE_DOUBLE_EDGE, +} int_trigger_mode_t; + +/** + \brief Initialize the INTC interrupt controller + */ +void csi_intc_init(void); + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the INTC interrupt controller. + \param[in] IRQn External interrupt number. Value cannot be negative. + */ +void csi_intc_enable_irq(int32_t IRQn); + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the INTC interrupt controller. + \param[in] IRQn External interrupt number. Value cannot be negative. + */ +void csi_intc_disable_irq(int32_t IRQn); + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the INTC and returns the pending bit for the specified interrupt. + \param[in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +uint32_t csi_intc_get_pending_irq(int32_t IRQn); + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param[in] IRQn Interrupt number. Value cannot be negative. + */ +void csi_intc_set_pending_irq(int32_t IRQn); + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param[in] IRQn External interrupt number. Value cannot be negative. + */ +void csi_intc_clear_pending_irq(int32_t IRQn); + +/** + \brief Get Wake up Interrupt + \details Reads the wake up register in the INTC and returns the pending bit for the specified interrupt. + \param[in] IRQn Interrupt number. + \return 0 Interrupt is not set as wake up interrupt. + \return 1 Interrupt is set as wake up interrupt. + */ +uint32_t csi_intc_get_wakeup_irq(int32_t IRQn); + +/** + \brief Set Wake up Interrupt + \details Sets the wake up bit of an external interrupt. + \param[in] IRQn Interrupt number. Value cannot be negative. + */ +void csi_intc_set_wakeup_irq(int32_t IRQn); + +/** + \brief Clear Wake up Interrupt + \details Clears the wake up bit of an external interrupt. + \param[in] IRQn External interrupt number. Value cannot be negative. + */ +void csi_intc_clear_wakeup_irq(int32_t IRQn); + +/** + \brief Get Active Interrupt + \details Reads the active register in the INTC and returns the active bit for the device specific interrupt. + \param[in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +uint32_t csi_intc_get_active(int32_t IRQn); + +/** + \brief Set Threshold register + \details set the threshold register in the INTC. + \param[in] VectThreshold specific vecter threshold. + \param[in] PrioThreshold specific priority threshold. + */ +void csi_intc_set_threshold(uint32_t VectThreshold, uint32_t PrioThreshold); + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param[in] IRQn Interrupt number. + \param[in] priority Priority to set. + */ +void csi_intc_set_prio(int32_t IRQn, uint32_t priority); + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param[in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +uint32_t csi_intc_get_prio(int32_t IRQn); + +/** + \brief funciton is acknowledge the IRQ. this interface is internally used by irq system + \param[in] irq irq number to operate + \return 0 on success; -1 on failure + */ +int csi_intc_ack_irq(int32_t IRQn); + +/** + \brief This function is set the attributes of an IRQ. + \param[in] irq irq number to operate + \param[in] priority interrupt priority + \param[in] trigger_mode interrupt trigger_mode + \return 0 on success; -1 on failure +*/ +int csi_intc_set_attribute(int32_t IRQn, uint32_t priority, int_trigger_mode_t trigger_mode); + +/** + \brief Set interrupt handler + \details Set the interrupt handler according to the interrupt num, the handler will be filled in g_irqvector[]. + \param[in] IRQn Interrupt number. + \param[in] handler Interrupt handler. + */ +void csi_intc_set_vector(int32_t IRQn, uint32_t handler); + +/** + \brief Get interrupt handler + \details Get the address of interrupt handler function. + \param[in] IRQn Interrupt number. + */ +uint32_t csi_intc_get_vector(int32_t IRQn); + +#endif /* _DRV_INTC_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/io.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/io.h new file mode 100755 index 00000000..5b970c33 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/io.h @@ -0,0 +1,131 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/io.h + * @brief Header File for register bits operation + * @version V1.0 + * @date 9. Oct 2020 + * @model io + ******************************************************************************/ + +#ifndef _DRV_IO_H_ +#define _DRV_IO_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Bit field operate*/ +#define REG64(addr) (*(volatile uint64_t *)(addr)) +#define REG32(addr) (*(volatile uint32_t *)(addr)) +#define REG16(addr) (*(volatile uint16_t *)(addr)) +#define REG8(addr) (*(volatile uint8_t *)(addr)) + +/* Insert value to some field in reg, other field is set to 0(the field make macro) */ +#define HAL_FMK(PER_REG_FIELD, val) \ + (((val) << PER_REG_FIELD##_SHIFT) & PER_REG_FIELD##_MASK) + +/* Get value of some field in reg(the field extract macro) */ +#define HAL_FEXT(reg, PER_REG_FIELD) \ + (((reg) & PER_REG_FIELD##_MASK) >> PER_REG_FIELD##_SHIFT) + +/* Insert value to some field in reg, other field don't change(the field insert macro) */ +#define HAL_FINS(reg, PER_REG_FIELD, val) \ + ((reg) = ((reg) & ~PER_REG_FIELD##_MASK) \ + | HAL_FMK(PER_REG_FIELD, val)) + + +/* Bit operate */ +/* Set one value to 1, other bit don't change*/ +#define HAL_BIT_SET(reg, bit) ((reg) = ((reg) | (1U << (bit)))) + +/* Set one value to 0, other bit don't change*/ +#define HAL_BIT_CLR(reg, bit) ((reg) = ((reg) & (~(1U << (bit))))) + +/* Get value of one bit(0/1) */ +#define HAL_GET_BIT_VAL(reg, bit) (((reg)>> (bit)) & 1U) + +/* Judge one bit is 1 or not */ +#define HAL_IS_BIT_SET(reg, pos) (((reg) & (1U << (pos))) != 0x0U) + +/* Judge one bit is 0 or not */ +#define HAL_IS_BIT_CLR(reg, pos) (((reg) & (1U << (pos))) == 0x0U) + +/* Set one value to bit, other bit don't change*/ +#define HAL_BIT_INSR(reg, bit, val) \ + ((reg) = (((reg) & (~(1U << (bit)))) | (((val) & 1U) << (bit)))) + + +static inline uint8_t getreg8(volatile void *addr) +{ + return *(volatile uint8_t *)addr; +} + +static inline void putreg8(uint8_t val, volatile void *addr) +{ + *(volatile uint8_t *)addr = val; +} + +static inline uint16_t getreg16(volatile void *addr) +{ + return *(volatile uint16_t *)addr; +} + +static inline void putreg16(uint16_t val, volatile void *addr) +{ + *(volatile uint16_t *)addr = val; +} + +static inline uint32_t getreg32(volatile void *addr) +{ + return *(volatile uint32_t *)addr; +} + +static inline void putreg32(uint32_t val, volatile void *addr) +{ + *(volatile uint32_t *)addr = val; +} + +static inline uint64_t getreg64(volatile void *addr) +{ + return *(volatile uint64_t *)addr; +} + +static inline void putreg64(uint32_t val, volatile void *addr) +{ + *(volatile uint64_t *)addr = val; +} + +static inline uint32_t inl(void *addr) +{ + return *(volatile uint32_t *)addr; +} + +static inline void outl(uint32_t val, void *addr) +{ + *(volatile uint32_t *)addr = val; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_IO_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/irq.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/irq.h new file mode 100755 index 00000000..6272d15b --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/irq.h @@ -0,0 +1,149 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/irq.h + * @brief header File for IRQ Driver + * @version V1.0 + * @date 16. Mar 2020 + * @model irq + ******************************************************************************/ + +#ifndef _DRV_IRQ_H_ +#define _DRV_IRQ_H_ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \brief Enable irq. + \param[in] irq_num Number of IRQ. + \return None. +*/ +__ALWAYS_STATIC_INLINE void csi_irq_enable(uint32_t irq_num) +{ + extern void soc_irq_enable(uint32_t irq_num); + soc_irq_enable(irq_num); +} + +/** + \brief Disable irq. + \param[in] irq_num Number of IRQ. + \return None. +*/ +__ALWAYS_STATIC_INLINE void csi_irq_disable(uint32_t irq_num) +{ + extern void soc_irq_disable(uint32_t irq_num); + soc_irq_disable(irq_num); +} + +/** + \brief Attach irq handler. + \param[in] irq_num Number of IRQ. + \param[in] irq_handler IRQ Handler. + \param[in] dev The dev to operate + \return None. +*/ +void csi_irq_attach(uint32_t irq_num, void *irq_handler, csi_dev_t *dev); + +/** + \brief Attach irq handler2 for compatible. + \param[in] irq_num Number of IRQ. + \param[in] irq_handler2 IRQ Handler. + \param[in] dev The dev to operate + \param[in] arg user data of irq_handler2 + \return None. +*/ +void csi_irq_attach2(uint32_t irq_num, void *irq_handler2, csi_dev_t *dev, void *arg); + +/** + \brief detach irq handler. + \param[in] irq_num Number of IRQ. + \param[in] irq_handler IRQ Handler. + \return None. +*/ +void csi_irq_detach(uint32_t irq_num); + +/** + \brief Set irq priority + \param[in] irq_num Number of IRQ. + \param[in] priority IRQ Priority. + \return None. +*/ +__ALWAYS_STATIC_INLINE void csi_irq_priority(uint32_t irq_num, uint32_t priority) +{ + extern void soc_irq_priority(uint32_t irq_num, uint32_t priority); + soc_irq_priority(irq_num, priority); +} + +/** + \brief Gets whether the interrupt is enabled + \param[in] irq_num Number of IRQ. + \return true or false. +*/ +static inline bool csi_irq_is_enabled(uint32_t irq_num) +{ + extern bool soc_irq_is_enabled(uint32_t irq_num); + return soc_irq_is_enabled(irq_num); +} + +/** + \brief Enable the interrupt wakeup attribution + \param[in] irq_num Number of IRQ. + \return None. +*/ +__ALWAYS_STATIC_INLINE void csi_irq_enable_wakeup(uint32_t irq_num) +{ + extern void soc_irq_enable_wakeup(uint32_t irq_num); + soc_irq_enable_wakeup(irq_num); +} + +/** + \brief Disable the interrupt wakeup attribution + \param[in] irq_num Number of IRQ. + \return None. +*/ +__ALWAYS_STATIC_INLINE void csi_irq_disable_wakeup(uint32_t irq_num) +{ + extern void soc_irq_disable_wakeup(uint32_t irq_num); + soc_irq_disable_wakeup(irq_num); +} + +/** + \brief Gets whether in irq context + \return true or false. +*/ +bool csi_irq_context(void); + +/** + \brief Dispatching irq handlers + \return None. +*/ +void do_irq(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_IRQ_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/iso7816.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/iso7816.h new file mode 100755 index 00000000..706d4fa6 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/iso7816.h @@ -0,0 +1,409 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/iso7816.h + * @brief Header File for ISO7816 Driver + * @version V1.0 + * @date 9. Oct 2020 + * @model iso7816 + ******************************************************************************/ + +#ifndef _DRV_ISO7816_H_ +#define _DRV_ISO7816_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + A_5V, + B_3_3V, + C_1_8V, +} dcd_vclass_t; + +typedef enum { + T0, + T1, +} iso7816_tprotocol_t; + +typedef enum { + ISO7816_EVENT_CARD_DETECTED, + ISO7816_EVENT_READ_COMPLETE, + ISO7816_EVENT_WRITE_COMPLETE, + ISO7816_EVENT_READ_ERROR, + ISO7816_EVENT_WRITE_ERROR, + ISO7816_EVENT_ACTIVATE_SUCCESS, + ISO7816_EVENT_ACTIVATE_FAILED, + ISO7816_EVENT_CARD_ERROR_DEACTIVATE, + ISO7816_EVENT_CARD_SESSION_CLOSED, + ISO7816_EVENT_RX_FULL, + ISO7816_EVENT_CWT_TIME_OUT, + ISO7816_EVENT_RX_OVER, + ISO7816_EVENT_CRC_ERR, + ISO7816_EVENT_PARITY_ERR, + ISO7816_EVENT_SLAVE_ATR_DETECTED, + ISO7816_EVENT_SLAVE_ATR_DONE, +} iso7816_event_t; + +typedef void (*iso7816_event_cb_t)(iso7816_event_t event, void *arg); + +typedef enum { + ISO7816_SLAVE, + ISO7816_MASTER, +} iso7816_mode_t; + +typedef struct { + uint8_t clk_div; + dcd_vclass_t vclass; + iso7816_mode_t mode; + int32_t card_detected_en; +} iso7816_config_t; + +typedef enum { + ISO7816_A_ONLY = 1U, + ISO7816_B_ONLY, + ISO7816_C_ONLY, + ISO7816_AB, + ISO7816_AC, + ISO7816_BC, + ISO7816_ABC, +} iso7816_voltage_class_t; + +typedef struct { + iso7816_voltage_class_t support_voltage_class; + int32_t proto_t; + int32_t clk_stop_is_support; + int32_t history_byte_num; + uint8_t history_data[15]; +} iso7816_atr_info_t; + +typedef enum { + EVEN_PARITY, + ODD_PARITY, +} iso7816_parity_type_t; + +typedef enum { + ISO7816_DRIECT, + ISO7816_INVERSE, +} iso7816_convention_t; + +typedef enum { + INVCTIVE, + ACTIVATEING, + PSS_TRF, + PSS_RECV, + ACTIVATE, +} iso7816_card_sta_t; + +/** + \brief Initialize ISO7816 master interface + \param[in] idx Master index + \param[in] cb_event Pointer to \ref iso7816_event_cb_t + \param[in] cb_arg Event callback arg + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_master_init(int idx, iso7816_event_cb_t cb_event, void *cb_arg); + +/** + \brief Uninit ISO7816 master interface + \param[in] idx Master index + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_master_uninit(int idx); + +/** + \brief Config ISO7816 master attributes + \param[in] idx Master index + \param[in] config master config \ref iso7816_config_t + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_master_config(int idx, iso7816_config_t *config); + +/** + \brief Receiving data from ISO7816 master receiver, used polling mode + \param[in] idx Master index + \param[in] buf Pointer to buffer for data to receive from i2s receiver + \param[in] len Size of receiver data + \param[in] time_out Receive time out value + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_master_receive(int idx, uint8_t *buf, uint32_t len, uint32_t time_out); + +/** + \brief Receiving data from ISO7816 master receiver, used interrupt mode + \param[in] idx Master index + \param[in] buf Pointer to buffer for data to receive from i2s receiver + \param[in] len Size of receiver data + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_master_receive_it(int idx, uint8_t *buf, uint32_t len); + +/** + \brief Sending data to ISO7816 master transmitter, used polling mode + \param[in] idx Master index + \param[in] buf Pointer to buffer for data to send + \param[in] len Size of tranmitter data + \param[in] time_out Send time out value + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_master_send(int idx, uint8_t *buf, uint32_t len, uint32_t time_out); + +/** + \brief Sending data to ISO7816 master transmitter, used interrupt mode + \param[in] idx Master index + \param[in] buf Pointer to buffer for data to send + \param[in] len Size of tranmitter data + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_master_send_it(int idx, uint8_t *buf, uint32_t len); + +/** + \brief ISO7816 master performs the activation smart card process, this process + is non-blocking,should monitor callback event or read card status to check card is activate + \param[in] idx Master index + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_master_card_activate(int idx); + +/** + \brief ISO7816 master performs the deactivation smart card process, this process + is non-blocking,should monitor callback event or read card status to check card is activate + \param[in] idx Master index + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_master_card_deactivate(int idx); + +/** + \brief The smard card session status + \param[in] idx Master index + \return smart card status. +*/ +iso7816_card_sta_t csi_iso7816_master_card_status(int idx); + +/** + \brief ISO7816 master performs the warm reset smart card process + \param[in] idx Master index + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_master_card_warm_reset(int idx); + +/** + \brief ISO7816 master performs clock stop + \param[in] idx Master index + \param[in] en The clk last state when power down + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_master_card_clk_stop_enable(int idx, int en); + +/** + \brief ISO7816 master performs pwoer down + \param[in] idx Master index + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_master_power_down(int idx); + +/** + \brief Get atr analytical results + \param[in] idx Master index + \param[out] info The result of atr information + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_master_atr_info(int idx, iso7816_atr_info_t *info); + +/** + \brief Initialize ISO7816 slave interface + \param[in] idx Slave index + \param[in] cb Pointer to \ref iso7816_event_cb_t + \param[in] cb_arg Event callback arg + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_slave_init(int idx, iso7816_event_cb_t cb, void *cb_arg); + +/** + \brief Uninit ISO7816 slave interface + \param[in] idx Slave index + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_slave_uninit(int idx); + +/** + \brief Enable ISO7816 slave interface + \param[in] idx Slave index + \param[in] en Slave enable + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_slave_enable(int idx, int en); + +/** + \brief Enable ISO7816 slave receive parity + \param[in] idx Slave index + \param[in] en Enable receive parity + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_slave_receive_parity_enable(int idx, int en); + +/** + \brief Set ISO7816 slave receive parity attributes + \param[in] idx Slave index + \param[in] type Set receiver parity type + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_slave_set_receive_parity(int idx, iso7816_parity_type_t type); + +/** + \brief Enable ISO7816 slave send parity + \param[in] idx Slave index + \param[in] en Enable send parity + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_slave_send_parity_enable(int idx, int en); + +/** + \brief Set ISO7816 slave send parity attributes + \param[in] idx Slave index + \param[in] type Set send parity attributes + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_slave_set_send_parity(int idx, iso7816_parity_type_t type); + +/** + \brief Set the number of ISO7816 slave receive retry + \param[in] idx Slave index + \param[in] val Set the number retry + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_slave_set_receive_retry(int idx, uint8_t val); + +/** + \brief Set the number of ISO7816 send send retry + \param[in] idx Slave index + \param[in] val Set the number retry + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_slave_set_send_retry(int idx, uint8_t val); + +/** + \brief Set the ISO7816 slave GT + \param[in] idx Slave index + \param[in] val Set the slave GT + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_slave_set_gt(int idx, uint8_t val); + +/** + \brief Set the ISO7816 slave WT + \param[in] idx Slave index + \param[in] val Set the slave WT + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_slave_set_wt(int idx, uint16_t val); + +/** + \brief Set the ISO7816 slave baud, baud = F/D + \param[in] idx Slave index + \param[in] val Set the slave baud + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_slave_set_baud(int idx, uint16_t val); + +/** + \brief Set the ISO7816 slave convention + \param[in] idx Slave index + \param[in] convention Set the slave convention \ref iso7816_convention_t + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_slave_set_convention(int idx, iso7816_convention_t convention); + +/** + \brief Set the ISO7816 slave art response time, val range is 400~40000 + \param[in] idx Slave index + \param[in] val Set the slave art response time + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_slave_set_atr_ack_time(int idx, int val); + +/** + \brief Set the ISO7816 slave send atr data + \param[in] idx Slave index + \param[in] buf Pointer to buffer for data to send + \param[in] len Size of tranmitter data + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_slave_send_atr(int idx, uint8_t *buf, int len); + +/** + \brief Receiving data from ISO7816 slave receiver, used polling mode + \param[in] idx Master index + \param[in] buf Pointer to buffer for data to receive from i2s receiver + \param[in] len Size of receiver data + \param[in] timer_out receive time out value + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_slave_receive(int idx, uint8_t *buf, uint32_t len, uint32_t time_out); + +/** + \brief Flushed the ISO7816 slave receive fifo + \param[in] idx Master index + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_slave_flushed_receive_fifo(int idx); + +/** + \brief Receiving data from ISO7816 slave receiver, used interrupt mode + \param[in] idx Master index + \param[in] buf Pointer to buffer for data to receive from i2s receiver + \param[in] len Size of receiver data + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_slave_receive_it(int idx, uint8_t *buf, uint32_t len); + +/** + \brief Sending data to ISO7816 slave transmitter, used polling mode + \param[in] idx Slave index + \param[in] buf Pointer to buffer for data to send + \param[in] len Size of tranmitter data + \param[in] timer_out Send time out value + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_slave_send(int idx, uint8_t *buf, uint32_t len, uint32_t time_out); + +/** + \brief Flushed the ISO7816 slave send fifo. + \param[in] idx Master index + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_slave_flushed_send_fifo(int idx); + +/** + \brief Sending data to ISO7816 slave transmitter, used interrupt mode + \param[in] idx Slave index + \param[in] buf Pointer to buffer for data to send + \param[in] len Size of tranmitter data + \return 0 for success, negative for error code +*/ +int32_t csi_iso7816_slave_send_it(int idx, uint8_t *buf, uint32_t len); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_ISO7816_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/list.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/list.h new file mode 100755 index 00000000..9f65050c --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/list.h @@ -0,0 +1,350 @@ +#ifndef AOS_LIST_H +#define AOS_LIST_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Get offset of a member variable. + * + * @param[in] type the type of the struct this is embedded in. + * @param[in] member the name of the variable within the struct. + */ +#define aos_offsetof(type, member) ((size_t)&(((type *)0)->member)) + +/* + * Get the struct for this entry. + * + * @param[in] ptr the list head to take the element from. + * @param[in] type the type of the struct this is embedded in. + * @param[in] member the name of the variable within the struct. + */ +#define aos_container_of(ptr, type, member) \ + ((type *) ((char *) (ptr) - aos_offsetof(type, member))) + +/* for double link list */ +typedef struct dlist_s { + struct dlist_s *prev; + struct dlist_s *next; +} dlist_t; + +static inline void __dlist_add(dlist_t *node, dlist_t *prev, dlist_t *next) +{ + node->next = next; + node->prev = prev; + + prev->next = node; + next->prev = node; +} + +/* + * Get the struct for this entry. + * + * @param[in] addr the list head to take the element from. + * @param[in] type the type of the struct this is embedded in. + * @param[in] member the name of the dlist_t within the struct. + */ +#define dlist_entry(addr, type, member) \ + ((type *)((long)addr - aos_offsetof(type, member))) + + +static inline void dlist_add(dlist_t *node, dlist_t *queue) +{ + __dlist_add(node, queue, queue->next); +} + +static inline void dlist_add_tail(dlist_t *node, dlist_t *queue) +{ + __dlist_add(node, queue->prev, queue); +} + +static inline void dlist_del(dlist_t *node) +{ + dlist_t *prev = node->prev; + dlist_t *next = node->next; + + prev->next = next; + next->prev = prev; +} + +static inline void dlist_init(dlist_t *node) +{ + node->next = node->prev = node; +} + +static inline void INIT_AOS_DLIST_HEAD(dlist_t *list) +{ + list->next = list; + list->prev = list; +} + +static inline int dlist_empty(const dlist_t *head) +{ + return head->next == head; +} + +/* + * Initialise the list. + * + * @param[in] list the list to be inited. + */ +#define AOS_DLIST_INIT(list) {&(list), &(list)} + +/* + * Get the first element from a list + * + * @param[in] ptr the list head to take the element from. + * @param[in] type the type of the struct this is embedded in. + * @param[in] member the name of the dlist_t within the struct. + */ +#define dlist_first_entry(ptr, type, member) \ + dlist_entry((ptr)->next, type, member) + +/* + * Iterate over a list. + * + * @param[in] pos the &struct dlist_t to use as a loop cursor. + * @param[in] head he head for your list. + */ +#define dlist_for_each(pos, head) \ + for (pos = (head)->next; pos != (head); pos = pos->next) + +/* + * Iterate over a list safe against removal of list entry. + * + * @param[in] pos the &struct dlist_t to use as a loop cursor. + * @param[in] n another &struct dlist_t to use as temporary storage. + * @param[in] head he head for your list. + */ +#define dlist_for_each_safe(pos, n, head) \ + for (pos = (head)->next, n = pos->next; pos != (head); \ + pos = n, n = pos->next) + +/* + * Iterate over list of given type. + * + * @param[in] queue he head for your list. + * @param[in] node the &struct dlist_t to use as a loop cursor. + * @param[in] type the type of the struct this is embedded in. + * @param[in] member the name of the dlist_t within the struct. + */ +#define dlist_for_each_entry(queue, node, type, member) \ + for (node = aos_container_of((queue)->next, type, member); \ + &node->member != (queue); \ + node = aos_container_of(node->member.next, type, member)) + +/* + * Iterate over list of given type safe against removal of list entry. + * + * @param[in] queue the head for your list. + * @param[in] n the type * to use as a temp. + * @param[in] node the type * to use as a loop cursor. + * @param[in] type the type of the struct this is embedded in. + * @param[in] member the name of the dlist_t within the struct. + */ +#define dlist_for_each_entry_safe(queue, n, node, type, member) \ + for (node = aos_container_of((queue)->next, type, member), \ + n = (queue)->next ? (queue)->next->next : NULL; \ + &node->member != (queue); \ + node = aos_container_of(n, type, member), n = n ? n->next : NULL) + +/* + * Get the struct for this entry. + * @param[in] ptr the list head to take the element from. + * @param[in] type the type of the struct this is embedded in. + * @param[in] member the name of the variable within the struct. + */ +#define list_entry(ptr, type, member) \ + aos_container_of(ptr, type, member) + + +/* + * Iterate backwards over list of given type. + * + * @param[in] pos the type * to use as a loop cursor. + * @param[in] head he head for your list. + * @param[in] member the name of the dlist_t within the struct. + * @param[in] type the type of the struct this is embedded in. + */ +#define dlist_for_each_entry_reverse(pos, head, member, type) \ + for (pos = list_entry((head)->prev, type, member); \ + &pos->member != (head); \ + pos = list_entry(pos->member.prev, type, member)) + + +/* + * Get the list length. + * + * @param[in] queue the head for your list. + */ +int dlist_entry_number(dlist_t *queue); + + + +/* + * Initialise the list. + * + * @param[in] name the list to be initialized. + */ +#define AOS_DLIST_HEAD_INIT(name) { &(name), &(name) } + +/* + * Initialise the list. + * + * @param[in] name the list to be initialized. + */ +#define AOS_DLIST_HEAD(name) \ + dlist_t name = AOS_DLIST_HEAD_INIT(name) + +/* for single link list */ +typedef struct slist_s { + struct slist_s *next; +} slist_t; + +static inline void slist_add(slist_t *node, slist_t *head) +{ + node->next = head->next; + head->next = node; +} + +void slist_add_tail(slist_t *node, slist_t *head); + +static inline void slist_del(slist_t *node, slist_t *head) +{ + while (head->next) { + if (head->next == node) { + head->next = node->next; + break; + } + + head = head->next; + } +} + +static inline int slist_empty(const slist_t *head) +{ + return !head->next; +} + +static inline void slist_init(slist_t *head) +{ + head->next = 0; +} + +static inline slist_t *slist_remove(slist_t *l, slist_t *n) +{ + /* remove slist head */ + struct slist_s *node = l; + while (node->next && node->next != n) node = node->next; + + /* remove node */ + if (node->next != (slist_t *)0) node->next = node->next->next; + + return l; +} + +static inline slist_t *slist_first(slist_t *l) +{ + return l->next; +} + +static inline slist_t *slist_tail(slist_t *l) +{ + while (l->next) l = l->next; + + return l; +} + +static inline slist_t *slist_next(slist_t *n) +{ + return n->next; +} + +/* +* Iterate over list of given type. +* +* @param[in] queue he head for your list. +* @param[in] node the type * to use as a loop cursor. +* @param[in] type the type of the struct this is embedded in. +* @param[in] member the name of the slist_t within the struct. +*/ +#define slist_for_each_entry(queue, node, type, member) \ + for (node = (queue)->next? aos_container_of((queue)->next, type, member) : NULL; \ + node; \ + node = node->member.next ? aos_container_of(node->member.next, type, member) : NULL) + +/* + * Iterate over list of given type safe against removal of list entry. + * + * @param[in] queue the head for your list. + * @param[in] tmp the type * to use as a temp. + * @param[in] node the type * to use as a loop cursor. + * @param[in] type the type of the struct this is embedded in. + * @param[in] member the name of the slist_t within the struct. + */ +#define slist_for_each_entry_safe(queue, tmp, node, type, member) \ + for (node = (queue)->next? aos_container_of((queue)->next, type, member) : NULL, \ + tmp = (queue)->next ? (queue)->next->next : NULL; \ + node; \ + node = tmp ? aos_container_of(tmp, type, member) : NULL, tmp = tmp ? tmp->next : NULL) + +/* + * Initialise the list. + * + * @param[in] name the list to be initialized. + */ +#define AOS_SLIST_HEAD_INIT(name) {0} + +/* + * Initialise the list. + * + * @param[in] name the list to be initialized. + */ +#define AOS_SLIST_HEAD(name) \ + slist_t name = AOS_SLIST_HEAD_INIT(name) + +/* + * Get the struct for this entry. + * @param[in] addr the list head to take the element from. + * @param[in] type the type of the struct this is embedded in. + * @param[in] member the name of the slist_t within the struct. + */ +#define slist_entry(addr, type, member) ( \ + addr ? (type *)((long)addr - aos_offsetof(type, member)) : (type *)addr \ +) + +/* +* Get the first element from a list. +* +* @param[in] ptr the list head to take the element from. +* @param[in] type the type of the struct this is embedded in. +* @param[in] member the name of the slist_t within the struct. +*/ +#define slist_first_entry(ptr, type, member) \ + slist_entry((ptr)->next, type, member) + +/** + * slist_tail_entry - get the tail element from a slist + * @ptr: the slist head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the slist_struct within the struct. + * + * Note, that slist is expected to be not empty. + */ +#define slist_tail_entry(ptr, type, member) \ + slist_entry(slist_tail(ptr), type, member) + +/* + * Get the list length. + * + * @param[in] queue the head for your list. + */ +int slist_entry_number(slist_t *queue); + +#ifdef __cplusplus +} +#endif + +#endif /* AOS_LIST_H */ + diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/mbox.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/mbox.h new file mode 100755 index 00000000..c5090425 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/mbox.h @@ -0,0 +1,104 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/mbox.h + * @brief Header File for MBOX Driver + * @version V1.0 + * @date 5. Apr 2020 + * @model mbox + ******************************************************************************/ + +#ifndef _DRV_MBOX_H_ +#define _DRV_MBOX_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + MBOX_EVENT_SEND_COMPLETE = 0U, ///< Send completed; however mbox may still transmit data + MBOX_EVENT_RECEIVED = 1U, ///< Data Received, only in mbox buf, call memcpy() get the data + MBOX_EVENT_ERROR = 2U, ///< Mbox transmit error occurred +} csi_mbox_event_t; + +typedef struct csi_mbox csi_mbox_t; +struct csi_mbox { + csi_dev_t dev; + void (*callback)(csi_mbox_t *mbox, csi_mbox_event_t event, uint32_t channel_id, uint32_t received_len, void *arg); + void *arg; + void *priv; +}; + +/** + \brief Initialize mbox Interface. + Initializes the resources needed for the mbox interface. + \param[in] mbox Operate handle. + \param[in] idx The device idx. + \return Error code \ref csi_error_t. +*/ +csi_error_t csi_mbox_init(csi_mbox_t *mbox, uint32_t idx); + +/** + \brief Uninitialize mbox interface. stops operation and releases the software resources used by the interface. + \param[in] mbox Operate handle. +*/ +void csi_mbox_uninit(csi_mbox_t *mbox); + +/** + \brief Start sending data to mbox transmitter. + \param[in] mbox Operate handle. + \param[in] channel_id Index of channel. + \param[in] data Pointer to buffer with data to send to mbox transmitter. + \param[in] size Number of data items to send. + \return sent Number of data or error code. +*/ +int32_t csi_mbox_send(csi_mbox_t *mbox, uint32_t channel_id, const void *data, uint32_t size); + +/** + \brief Start receiving data from mbox receiver. + \param[in] mbox Operate handle. + \param[in] channel_id Index of channel. + \param[out] data Pointer to buffer with data to receive from mailbox. + \param[in] size Number of data items to receive. + \return received Number or error code. +*/ +int32_t csi_mbox_receive(csi_mbox_t *mbox, uint32_t channel_id, void *data, uint32_t size); + +/** + \brief Attach callback to the mbox. + \param[in] mbox Operate handle. + \param[in] cb Event callback function. + \param[in] arg User private param for event callback. + \return Error code \ref csi_error_t. +*/ +csi_error_t csi_mbox_attach_callback(csi_mbox_t *mbox, void *callback, void *arg); + +/** + \brief Detach callback from the mbox + \param[in] mbox Operate handle. +*/ +void csi_mbox_detach_callback(csi_mbox_t *mbox); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_MBOX_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/pin.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/pin.h new file mode 100755 index 00000000..d1a614b6 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/pin.h @@ -0,0 +1,198 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file soc.h + * @brief For pin + * @version V1.0 + * @date 11. Mar 2020 + ******************************************************************************/ + +#ifndef _DRV_PIN_H_ +#define _DRV_PIN_H_ + +#include +#include +#include +#include + +typedef csi_gpio_mode_t csi_pin_mode_t; + +typedef enum { + PIN_SPEED_LV0 = 0U, + PIN_SPEED_LV1, + PIN_SPEED_LV2, + PIN_SPEED_LV3 +} csi_pin_speed_t; + +typedef enum { + PIN_DRIVE_LV0 = 0U, + PIN_DRIVE_LV1, + PIN_DRIVE_LV2, + PIN_DRIVE_LV3 +} csi_pin_drive_t; + +typedef enum{ + PIN_UART_TX = 0U, + PIN_UART_RX, + PIN_UART_CTS, + PIN_UART_RTS +}csi_pin_uart_t; + +typedef enum{ + PIN_IIC_SCL = 0U, + PIN_IIC_SDA +}csi_pin_iic_t; + +typedef enum{ + PIN_SPI_MISO = 0U, + PIN_SPI_MOSI, + PIN_SPI_SCK, + PIN_SPI_CS +}csi_pin_spi_t; + +typedef enum{ + PIN_I2S_MCLK = 0U, + PIN_I2S_SCLK, + PIN_I2S_WSCLK, + PIN_I2S_SDA, + PIN_I2S_SDI, + PIN_I2S_SDO +}csi_pin_i2s_t; + +typedef struct { + pin_name_t pin_name; + uint8_t idx; ///< ctrl idx. e.g: ADC0 channel 1, idx = 0, channel = 1 + uint8_t channel; ///< channel idx. e.g: same as the previous line + pin_func_t pin_func; +} csi_pinmap_t; + +extern uint32_t target_pin_to_devidx(pin_name_t pin_name, const csi_pinmap_t *pinmap); +extern uint32_t target_pin_to_channel(pin_name_t pin_name,const csi_pinmap_t *pinmap); +extern pin_name_t target_gpio_to_pin(uint8_t gpio_idx, uint8_t channel,const csi_pinmap_t *pinmap); + +/** + \brief Set pin mux function + \param[in] pin_name Pin name, defined in soc.h + \param[in] pin_func Pin function, defined in soc.h + \return \ref csi_error_t +*/ +csi_error_t csi_pin_set_mux(pin_name_t pin_name, pin_func_t pin_func); + +/** + \brief Get pin function + \param[in] pin_name Pin name, defined in soc.h + \return pin function +*/ +pin_func_t csi_pin_get_mux(pin_name_t pin_name); + +/** + \brief Set pin mode + \param[in] pin_name Pin name, defined in soc.h + \param[in] mode Push/pull mode + \return \ref csi_error_t +*/ +csi_error_t csi_pin_mode(pin_name_t pin_name, csi_pin_mode_t mode); + +/** + \brief Set pin speed + \param[in] pin_name Pin name, defined in soc.h + \param[in] speed Io speed + \return \ref csi_error_t +*/ +csi_error_t csi_pin_speed(pin_name_t pin_name, csi_pin_speed_t speed); + +/** + \brief Set pin drive + \param[in] pin_name Pin name, defined in soc.h + \param[in] drive Io drive + \return \ref csi_error_t +*/ +csi_error_t csi_pin_drive(pin_name_t pin_name, csi_pin_drive_t drive); + +/** + \brief Get ctrl idx by pin + \param[in] pin_name Pin name, defined in soc.h + \return idx +*/ +__ALWAYS_STATIC_INLINE uint32_t csi_pin_get_gpio_devidx(pin_name_t pin_name) +{ + extern const csi_pinmap_t gpio_pinmap[]; + return target_pin_to_devidx(pin_name, gpio_pinmap); +} + +__ALWAYS_STATIC_INLINE uint32_t csi_pin_get_uart_devidx(pin_name_t pin_name) +{ + extern const csi_pinmap_t uart_pinmap[]; + return target_pin_to_devidx(pin_name, uart_pinmap); +} + +__ALWAYS_STATIC_INLINE uint32_t csi_pin_get_iic_devidx(pin_name_t pin_name) +{ + extern const csi_pinmap_t iic_pinmap[]; + return target_pin_to_devidx(pin_name, iic_pinmap); +} + +__ALWAYS_STATIC_INLINE uint32_t csi_pin_get_spi_devidx(pin_name_t pin_name) +{ + extern const csi_pinmap_t spi_pinmap[]; + return target_pin_to_devidx(pin_name, spi_pinmap); +} + +__ALWAYS_STATIC_INLINE uint32_t csi_pin_get_i2s_devidx(pin_name_t pin_name) +{ + extern const csi_pinmap_t i2s_pinmap[]; + return target_pin_to_devidx(pin_name, i2s_pinmap); +} + +/** + \brief Get channel by pin + \param[in] pin_name Pin name, defined in soc.h + \return channel +*/ +__ALWAYS_STATIC_INLINE uint32_t csi_pin_get_adc_channel(pin_name_t pin_name) +{ + extern const csi_pinmap_t adc_pinmap[]; + return target_pin_to_channel(pin_name, adc_pinmap); +} + +__ALWAYS_STATIC_INLINE uint32_t csi_pin_get_pwm_channel(pin_name_t pin_name) +{ + extern const csi_pinmap_t pwm_pinmap[]; + return target_pin_to_channel(pin_name, pwm_pinmap); +} + +__ALWAYS_STATIC_INLINE uint32_t csi_pin_get_gpio_channel(pin_name_t pin_name) +{ + extern const csi_pinmap_t gpio_pinmap[]; + return target_pin_to_channel(pin_name, gpio_pinmap); +} + +/** + \brief Get pin name by gpio ctrl idx and channel + \param[in] gpio_idx Idx, defined in soc.h + \param[in] channel Channel, defined in soc.h + \return pin name +*/ +__ALWAYS_STATIC_INLINE pin_name_t csi_pin_get_pinname_by_gpio(uint8_t gpio_idx, uint8_t channel) +{ + extern const csi_pinmap_t gpio_pinmap[]; + return target_gpio_to_pin(gpio_idx,channel,gpio_pinmap); +} + +#endif /* _DRV_PIN_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/pm.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/pm.h new file mode 100755 index 00000000..1894f206 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/pm.h @@ -0,0 +1,122 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/pm.h + * @brief Header File for PM Driver + * @version V1.0 + * @date 10. Oct 2020 + * @model pm + ******************************************************************************/ + +#ifndef _DRV_PM_H_ +#define _DRV_PM_H_ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \brief Initialize PM module + \return Error code \ref csi_error_t +*/ +csi_error_t csi_pm_init(void); + +/** + \brief De-initialize PM module + \return None +*/ +void csi_pm_uninit(void); + +/** + \brief Set the retention memory used to save registers + \param[in] mem Retention memory(word align) + \param[in] num Number of memory(1: 1 word) + \return Error code \ref csi_error_t +*/ +csi_error_t csi_pm_set_reten_mem(uint32_t *mem, uint32_t num); + +/** + \brief Config the wakeup source + \param[in] wakeup_num Wakeup source num + \param[in] enable Flag control the wakeup source is enable or not + \return Error code \ref csi_error_t +*/ +csi_error_t csi_pm_config_wakeup_source(uint32_t wakeup_num, bool enable); + +/** + \brief System enter low-power mode + \param[in] mode Low-power mode, \ref csi_pm_mode_t + \return Error code \ref csi_error_t +*/ +csi_error_t csi_pm_enter_sleep(csi_pm_mode_t mode); + +/** + \brief Register device to the PM list + \param[in] dev Csi dev + \param[in] pm_action PM action function + \param[in] mem_size Size of memory for saving registers + \param[in] priority PM dev priority(0-3), The smaller the value, + the last execution before entering low power consumption, + the first execution after exiting low power consumption + \return Error code \ref csi_error_t +*/ +csi_error_t csi_pm_dev_register(csi_dev_t *dev, void *pm_action, uint32_t mem_size, uint8_t priority); + +/** + \brief Deregister device to the PM list + \param[in] dev Csi dev + \return None +*/ +void csi_pm_dev_unregister(csi_dev_t *dev); + +/** + \brief Save registers to memory + \param[in] mem Mem to store registers + \param[in] addr Registers address + \param[in] num Number of memory(1: 1 word) + \return None +*/ +void csi_pm_dev_save_regs(uint32_t *mem, uint32_t *addr, uint32_t num); + +/** + \brief Save registers to memory + \param[in] mem Mem to store registers + \param[in] addr Registers address + \param[in] num Number of memory(1: 1 word) + \return None +*/ +void csi_pm_dev_restore_regs(uint32_t *mem, uint32_t *addr, uint32_t num); + +/** + \brief Notify devices enter low-power states + \param[in] action Device low-power action + \return Error code \ref csi_error_t +*/ +csi_error_t csi_pm_dev_notify(csi_pm_dev_action_t action); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_PM_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/pmu.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/pmu.h new file mode 100755 index 00000000..ac5bbadf --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/pmu.h @@ -0,0 +1,118 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv_pmu.h + * @brief header file for pmu driver + * @version V1.0 + * @date 02. June 2017 + * @model pmu + ******************************************************************************/ + +#ifndef _DRV_PMU_H_ +#define _DRV_PMU_H_ + + +#include + +#ifdef __cplusplus +extern "C" { +#endif +/// definition for pmu handle. +typedef void *pmu_handle_t; + +/****** PMU specific error codes *****/ +typedef enum { + EDRV_PMU_MODE = (1), ///< Specified Mode not supported +} pmu_error_e; + +/*----- PMU Control Codes: Mode -----*/ +typedef enum { + PMU_MODE_RUN = 0, ///< Running mode + PMU_MODE_SLEEP, ///< Sleep mode + PMU_MODE_DOZE, ///< Doze mode + PMU_MODE_DORMANT, ///< Dormant mode + PMU_MODE_STANDBY, ///< Standby mode + PMU_MODE_SHUTDOWN ///< Shutdown mode +} pmu_mode_e; + +/*----- PMU Control Codes: Wakeup type -----*/ +typedef enum { + PMU_WAKEUP_TYPE_PULSE = 0, ///< Pulse interrupt + PMU_WAKEUP_TYPE_LEVEL ///< Level interrupt +} pmu_wakeup_type_e; + +/*----- PMU Control Codes: Wakeup polarity -----*/ +typedef enum { + PMU_WAKEUP_POL_LOW = 0, ///< Low or negedge + PMU_WAKEUP_POL_HIGH ///< High or posedge +} pmu_wakeup_pol_e; + +/****** PMU Event *****/ +typedef enum { + PMU_EVENT_SLEEP_DONE = 0, ///< Send completed; however PMU may still transmit data + PMU_EVENT_PREPARE_SLEEP = 1 +} pmu_event_e; + +typedef void (*pmu_event_cb_t)(int32_t idx, pmu_event_e event, pmu_mode_e mode); ///< Pointer to \ref pmu_event_cb_t : PMU Event call back. + +/** + \brief Initialize PMU Interface. 1. Initializes the resources needed for the PMU interface 2.registers event callback function + \param[in] idx the id of the pmu + \param[in] cb_event Pointer to \ref pmu_event_cb_t + \return return pmu handle if success +*/ +pmu_handle_t csi_pmu_initialize(int32_t idx, pmu_event_cb_t cb_event); + +/** + \brief De-initialize PMU Interface. stops operation and releases the software resources used by the interface + \param[in] handle pmu handle to operate. + \return error code +*/ +int32_t csi_pmu_uninitialize(pmu_handle_t handle); + +/** + \brief choose the pmu mode to enter + \param[in] handle pmu handle to operate. + \param[in] mode \ref pmu_mode_e + \return error code +*/ +int32_t csi_pmu_enter_sleep(pmu_handle_t handle, pmu_mode_e mode); + +/** + \brief control pmu power. + \param[in] handle pmu handle to operate. + \param[in] state power state.\ref csi_power_stat_e. + \return error code +*/ +/** + \brief Config the wakeup source. + \param[in] handle pmu handle to operate + \param[in] wakeup_num wakeup source num + \param[in] type \ref pmu_wakeup_type + \param[in] pol \ref pmu_wakeup_pol + \param[in] enable flag control the wakeup source is enable or not + \return error code +*/ +int32_t csi_pmu_config_wakeup_source(pmu_handle_t handle, uint32_t wakeup_num, pmu_wakeup_type_e type, pmu_wakeup_pol_e pol, uint8_t enable); + +#ifdef __cplusplus +} +#endif + +#endif /* _CSI_PMU_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/porting.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/porting.h new file mode 100755 index 00000000..6ea647a1 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/porting.h @@ -0,0 +1,184 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/porting.h + * @brief Header File for SOC Porting + * @version V1.0 + * @date 8. Apr 2020 + * @model porting + ******************************************************************************/ + +#ifndef _DRV_PORTING_H_ +#define _DRV_PORTING_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + BOOTREASON_WDT = 0, // System WDT reset + BOOTREASON_SOFT = 1, // soft reset + BOOTREASON_POWER = 2, // chip power on reset + BOOTREASON_OTHER = 0xFF +} boot_reason_t; + +/* + \brief Soc get boot reason + \return boot reason, \ref boot_reason_t +*/ +boot_reason_t soc_get_boot_reason(void); + +/** + \brief Soc get device frequence. + \param[in] idx Device index + \return frequence +*/ +uint32_t soc_get_apb_freq(uint32_t idx); +uint32_t soc_get_ahb_freq(uint32_t idx); +uint32_t soc_get_cpu_freq(uint32_t idx); + +uint32_t soc_get_uart_freq(uint32_t idx); +uint32_t soc_get_spi_freq(uint32_t idx); +uint32_t soc_get_iic_freq(uint32_t idx); +uint32_t soc_get_i2s_freq(uint32_t idx); +uint32_t soc_get_pwm_freq(uint32_t idx); +uint32_t soc_get_adc_freq(uint32_t idx); +uint32_t soc_get_qspi_freq(uint32_t idx); +uint32_t soc_get_usi_freq(uint32_t idx); +uint32_t soc_get_timer_freq(uint32_t idx); +uint32_t soc_get_rtc_freq(uint32_t idx); +uint32_t soc_get_wdt_freq(uint32_t idx); +uint32_t soc_get_sdio_freq(uint32_t idx); +uint32_t soc_get_emmc_freq(uint32_t idx); +uint32_t soc_get_usb_freq(uint32_t idx); +uint32_t soc_get_ref_clk_freq(uint32_t idx); +uint32_t soc_get_coretim_freq(void); +uint32_t soc_get_cur_cpu_freq(void); +uint32_t soc_get_sys_freq(void); + +/** + \brief Soc get device frequence. + \param[in] freq CPU frequence + \return none +*/ +void soc_set_sys_freq(uint32_t freq); + +/* + \brief Soc init clock unit + \return none +*/ +void soc_clk_init(void); + +/* + \brief Soc enable device clock + \param[in] module Clock module, defined in sys_clk.h, \ref clk_module_t + \return none +*/ +void soc_clk_enable(int32_t module); + +/* + \brief Soc disable device clock + \param[in] module Clock module, defined in sys_clk.h, \ref clk_module_t + \return none +*/ +void soc_clk_disable(int32_t module); + +/* + \brief Get CPU ID + \return CPU ID, the val is 0, 1, 2... +*/ +uint32_t soc_get_cpu_id(void); + +/** + \brief SOC Dcache clean & invalid by range. + \return None +*/ +void soc_dcache_clean_invalid_range(unsigned long addr, uint32_t size); + +/** + \brief SOC Dcache clean & invalid all. + \return None +*/ +void soc_dcache_clean_invalid_all(void); + +/** + \brief SOC Dcache invalid by range. + \return None +*/ +void soc_dcache_invalid_range(unsigned long addr, uint32_t size); + +/** + \brief SOC Dcache invalid all. + \return None +*/ +void soc_dcache_invalid(void); + +/** + \brief SOC Dcache clean all. + \return None +*/ +void soc_dcache_clean(void); + + +/** + \brief SOC Dcache clean by range. + \return None +*/ +void soc_dcache_clean_range(unsigned long addr, uint32_t size); + +/** + \brief SOC Icache invalid all. + \return None +*/ +void soc_icache_invalid(void); + +/** + \brief SOC dma address remap. + \return Remaped address +*/ +extern unsigned long soc_dma_address_remap(unsigned long addr); + + +#ifdef CONFIG_PM +/** + \brief SoC enter low-power mode, each chip's implementation is different + called by csi_pm_enter_sleep + \param[in] mode low-power mode + \return Error code +*/ +csi_error_t soc_pm_enter_sleep(csi_pm_mode_t mode); + +/** + \brief SoC the wakeup source. + \param[in] wakeup_num Wakeup source num + \param[in] enable Flag control the wakeup source is enable or not + \return Error code +*/ +csi_error_t soc_pm_config_wakeup_source(uint32_t wakeup_num, bool enable); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_PORTING_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/pwm.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/pwm.h new file mode 100755 index 00000000..0db71e97 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/pwm.h @@ -0,0 +1,172 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/pwm.h + * @brief Header File for PWM Driver + * @version V1.0 + * @date 9. Oct 2020 + * @model pwm + ******************************************************************************/ + +#ifndef _DRV_PWM_H_ +#define _DRV_PWM_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PWM_POLARITY_HIGH = 0U, ///< High level + PWM_POLARITY_LOW ///< Low level +} csi_pwm_polarity_t; + +typedef enum { + PWM_CAPTURE_POLARITY_POSEDGE = 0U, ///< Posedge Edge + PWM_CAPTURE_POLARITY_NEGEDGE, ///< Negedge Edge + PWM_CAPTURE_POLARITY_BOTHEDGE ///< Both Edge +} csi_pwm_capture_polarity_t; + +typedef enum { + PWM_EVENT_CAPTURE_POSEDGE = 0U, ///< Capture Posedge Event + PWM_EVENT_CAPTURE_NEGEDGE, ///< Capture Negedge Event + PWM_EVENT_CAPTURE_BOTHEDGE, ///< Capture Bothedge Event + PWM_EVENT_ERROR, ///< Error +} csi_pwm_event_t; + +typedef struct csi_pwm csi_pwm_t; + +struct csi_pwm { + csi_dev_t dev; + void (*callback)(csi_pwm_t *pwm, csi_pwm_event_t event, uint32_t ch, uint32_t time_us, void *arg); + void *arg; + void *priv; +}; + +/** + \brief Initialize PWM interface. Initializes the resources needed for the PWM interface + \param[in] pwm Handle to operate + \param[in] idx PWM idx + \return Error code \ref csi_error_t +*/ +csi_error_t csi_pwm_init(csi_pwm_t *pwm, uint32_t idx); + +/** + \brief De-initialize PWM interface. Stops operation and releases the software resources used by the interface + \param[in] pwm Handle to operate + \return None +*/ +void csi_pwm_uninit(csi_pwm_t *pwm); + +/** + \brief Config PWM out mode + \param[in] pwm Handle to operate + \param[in] channel Channel num + \param[in] period_us The PWM period in us + \param[in] pulse_width_us The PMW pulse width in us + \param[in] polarity The PWM polarity \ref csi_pwm_polarity_t + \return Error code \ref csi_error_t +*/ +csi_error_t csi_pwm_out_config(csi_pwm_t *pwm, + uint32_t channel, + uint32_t period_us, + uint32_t pulse_width_us, + csi_pwm_polarity_t polarity); + +/** + \brief Start generate PWM signal + \param[in] pwm Handle to operate + \param[in] channel Channel num + \return Error code \ref csi_error_t +*/ +csi_error_t csi_pwm_out_start(csi_pwm_t *pwm, uint32_t channel); + +/** + \brief Stop generate PWM signal + \param[in] pwm Handle to operate + \param[in] channel Channel num + \return None +*/ +void csi_pwm_out_stop(csi_pwm_t *pwm, uint32_t channel); + +/** + \brief Config PWM capture mode + \param[in] pwm Handle to operate + \param[in] channel Channel num + \param[in] polarity PWM capture polarity \ref csi_pwm_capture_polarity_t + \param[in] count PWM capture polarity count + \return Error code \ref csi_error_t +*/ +csi_error_t csi_pwm_capture_config(csi_pwm_t *pwm, + uint32_t channel, + csi_pwm_capture_polarity_t polarity, + uint32_t count); + +/** + \brief Start PWM capture + \param[in] pwm Handle to operate + \param[in] channel Channel num + \return Error code \ref csi_error_t +*/ +csi_error_t csi_pwm_capture_start(csi_pwm_t *pwm, uint32_t channel); + +/** + \brief Stop PWM capture + \param[in] pwm Handle to operate + \param[in] channel Channel num + \return None +*/ +void csi_pwm_capture_stop(csi_pwm_t *pwm, uint32_t channel); + +/** + \brief Attach PWM callback + \param[in] pwm Handle to operate + \param[in] callback Callback func + \param[in] arg Callback's param + \return Error code \ref csi_error_t +*/ +csi_error_t csi_pwm_attach_callback(csi_pwm_t *pwm, void *callback, void *arg); + +/** + \brief Detach PWM callback + \param[in] pwm Handle to operate + \return None +*/ +void csi_pwm_detach_callback(csi_pwm_t *pwm); + +/** + \brief Enable PWM power manage + \param[in] pwm Handle to operate + \return Error code \ref csi_error_t +*/ +csi_error_t csi_pwm_enable_pm(csi_pwm_t *pwm); + +/** + \brief Disable PWM power manage + \param[in] pwm Handle to operate + \return None +*/ +void csi_pwm_disable_pm(csi_pwm_t *pwm); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_PWM_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/qspi.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/qspi.h new file mode 100755 index 00000000..e8f33312 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/qspi.h @@ -0,0 +1,304 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/qspi.h + * @brief Header File for QSPI Driver + * @version V1.0 + * @date 8. Apr 2020 + * @model qspi + ******************************************************************************/ + +#ifndef _DRV_QSPI_H_ +#define _DRV_QSPI_H_ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \enum csi_qspi_clock_mode_t + * \brief QSPI clock mode + */ +typedef enum { + QSPI_CLOCK_MODE_0 = 0, ///< Clock Polarity 0, Clock Phase 0 + QSPI_CLOCK_MODE_1, ///< Clock Polarity 0, Clock Phase 1 + QSPI_CLOCK_MODE_2, ///< Clock Polarity 1, Clock Phase 0 + QSPI_CLOCK_MODE_3, ///< Clock Polarity 1, Clock Phase 1 +} csi_qspi_mode_t; + +/** + * \enum csi_qspi_bus_width_t + * \brief QSPI bus width + */ +typedef enum { + QSPI_CFG_BUS_SINGLE = 0, ///< Single line + QSPI_CFG_BUS_DUAL, ///< Two line + QSPI_CFG_BUS_QUAD, ///< Four line +} csi_qspi_bus_width_t; + +/** + * \enum csi_qspi_address_size_t + * \brief Address size in bits + */ +typedef enum { + QSPI_ADDRESS_8_BITS = 0, + QSPI_ADDRESS_16_BITS, + QSPI_ADDRESS_24_BITS, + QSPI_ADDRESS_32_BITS, +} csi_qspi_address_size_t; + +/** + * \enum csi_qspi_alternate_bytes_size_t + * rief QSPI alternate bytes + */ +typedef enum { + QSPI_ALTERNATE_8_BITS = 0, + QSPI_ALTERNATE_16_BITS, + QSPI_ALTERNATE_24_BITS, + QSPI_ALTERNATE_32_BITS, +} csi_qspi_alt_size_t; + +/** QSPI command + * + * Defines a frame format. It consists of instruction, address, alternative, dummy count and data + */ +typedef struct { + struct { + csi_qspi_bus_width_t bus_width; ///< Bus width for the instruction + uint8_t value; ///< Instruction value + bool disabled; ///< Instruction phase skipped if disabled is set to true + } instruction; + struct { + csi_qspi_bus_width_t bus_width; ///< Bus width for the address + csi_qspi_address_size_t size; ///< Address size + uint32_t value; ///< Address value + bool disabled; ///< Address phase skipped if disabled is set to true + } address; + struct { + csi_qspi_bus_width_t bus_width; ///< Bus width for alternative + csi_qspi_alt_size_t size; ///< Alternative size + uint32_t value; ///< Alternative value + bool disabled; ///< Alternative phase skipped if disabled is set to true + } alt; + uint8_t dummy_count; ///< Dummy cycles count + struct { + csi_qspi_bus_width_t bus_width; ///< Bus width for data + } data; + uint8_t ddr_enable; +} csi_qspi_command_t; + +/** + * \enum csi_qspi_event_t + * \brief QSPI event + */ +typedef enum { + QSPI_EVENT_COMMAND_COMPLETE = 0, ///< Command completed + QSPI_EVENT_ERROR, ///< An error has occurred +} csi_qspi_event_t; + +/** + * \struct csi_qspi_t + * \brief QSPI Handle Structure definition + */ + +typedef struct csi_qspi csi_qspi_t; +struct csi_qspi { + csi_dev_t dev; ///< QSPI hw-device info + void (*callback)(csi_qspi_t *qspi, csi_qspi_event_t event, void *arg); ///< User callback function + void *arg; ///< QSPI custom designed param passed to evt_cb + uint8_t *tx_data; ///< Pointer to QSPI Tx transfer Buffer + uint32_t tx_size; ///< QSPI Tx Transfer size + uint8_t *rx_data; ///< Pointer to QSPI Rx transfer Buffer + uint32_t rx_size; ///< QSPI Rx Transfer size + void *send; ///< The send_async func + void *receive; ///< The receive_async func + void *send_receive; ///< The send_receive_async func + csi_state_t state; ///< Peripheral state + csi_dma_ch_t *tx_dma; + csi_dma_ch_t *rx_dma; + void *priv; +}; + +/** + \brief Init QSPI ctrl block + 1. Initializes the QSPI mode according to the specified parameters in the csi_qspi_init_t + 2. Registers event callback function and user param for the callback + \param[in] qspi Handle of QSPI instance + \param[in] idx Index of instance + \return Error code +*/ +csi_error_t csi_qspi_init(csi_qspi_t *qspi, uint32_t idx); + + +/** + \brief De-initialize QSPI Instance + stops operation and releases the software resources used by the Instance + \param[in] qspi Handle of QSPI instance +*/ +void csi_qspi_uninit(csi_qspi_t *qspi); + +/** + \brief Attach the callback handler to QSPI + \param[in] qspi Operate handle + \param[in] callback Callback function + \param[in] arg User can define it by himself as callback's param + \return Error code +*/ +csi_error_t csi_qspi_attach_callback(csi_qspi_t *qspi, void *callback, void *arg); + +/** + \brief Detach the callback handler + \param[in] qspi Operate handle + \return None +*/ +void csi_qspi_detach_callback(csi_qspi_t *qspi); + +/** + \brief Config qspi frequence + \param[in] qspi Handle of qspi instance + \param[in] hz QSPI frequence + \return The actual config frequency +*/ +uint32_t csi_qspi_frequence(csi_qspi_t *qspi, uint32_t hz); + +/** + \brief Config qspi mode + \param[in] qspi Handle of qspi instance + \param[in] mode QSPI mode + \return Error code +*/ +csi_error_t csi_qspi_mode(csi_qspi_t *qspi, csi_qspi_mode_t mode); + +/** + \brief Send an amount of data in blocking mode + \param[in] qspi QSPI handle + \param[in] cmd Structure that contains the command configuration information + \param[in] data Pointer to data buffer + \param[in] size Size of data to send + \param[in] timeout Time out duration + \return If send successful, this function shall return the num of data witch is sent successful + otherwise, the function shall return error code + */ +int32_t csi_qspi_send(csi_qspi_t *qspi, csi_qspi_command_t *cmd, const void *data, uint32_t size, uint32_t timeout); + +/** + \brief Receive an amount of data in blocking mode + \param[in] qspi QSPI handle + \param[in] cmd Structure that contains the command configuration information + \param[out] data Pointer to data buffer + \param[in] size Size of data items to receive + \param[in] timeout Time out duration + \return If receive successful, this function shall return the num of data witch is received successfulful + otherwise, the function shall return error code + */ +int32_t csi_qspi_receive(csi_qspi_t *qspi, csi_qspi_command_t *cmd, void *data, uint32_t size, uint32_t timeout); + +/** + \brief Transfer an amount of data in blocking mode + \param[in] qspi QSPI handle + \param[in] cmd Structure that contains the command configuration information + \param[in] tx_data Pointer to send data buffer + \param[out] rx_data Pointer to receive data buffer + \param[in] size Size of data to transfer + \param[in] timeout Time out duration + \return If transfer successful, this function shall return the num of data witch is transfer successfulful + otherwise, the function shall return error code + */ +int32_t csi_qspi_send_receive(csi_qspi_t *qspi, csi_qspi_command_t *cmd, const void *tx_data, void *rx_data, uint32_t size, uint32_t timeout); + +/** + \brief Send an amount of data in async mode + \param[in] qspi QSPI handle + \param[in] cmd Structure that contains the command configuration information + \param[in] data Pointer to data buffer + \param[in] size Size of data to send + \return Data number send + */ +csi_error_t csi_qspi_send_async(csi_qspi_t *qspi, csi_qspi_command_t *cmd, const void *data, uint32_t size); + +/** + \brief Receive an amount of data in async mode + \param[in] qspi QSPI handle + \param[in] cmd Structure that contains the command configuration information + \param[out] data Pointer to data buffer + \param[in] size Size of data items to receive + \return Data number received + */ +csi_error_t csi_qspi_receive_async(csi_qspi_t *qspi, csi_qspi_command_t *cmd, void *data, uint32_t size); + +/** + \brief Transfer an amount of data in async mode + \param[in] qspi QSPI handle + \param[in] cmd Structure that contains the command configuration information + \param[in] tx_data Pointer to send data buffer + \param[out] rx_data Pointer to receive data buffer + \param[in] size Size of data to transfer + \return Data number transfered + */ +csi_error_t csi_qspi_send_receive_async(csi_qspi_t *qspi, csi_qspi_command_t *cmd, const void *tx_data, void *rx_data, uint32_t size); + +/** + \brief Link DMA channel to qspi device + \param[in] qspi QSPI handle to operate + \param[in] tx_dma The DMA channel handle for send, when it is NULL means to unlink the channel + \param[in] rx_dma The DMA channel handle for receive, when it is NULL means to unlink the channel + \return Error code +*/ +csi_error_t csi_qspi_link_dma(csi_qspi_t *qspi, csi_dma_ch_t *tx_dma, csi_dma_ch_t *rx_dma); + +/** + \brief Get the state of qspi device + \param[in] qspi QSPI handle + \param[in] state QSPI state \ref csi_state_t + \return Error code + */ +csi_error_t csi_qspi_get_state(csi_qspi_t *qspi, csi_state_t *state); + +/** + \brief Comfigure the memory mapped mode + \param[in] qspi QSPI handle + \param[in] cmd Structure that contains the command configuration information + \return Error code + */ +csi_error_t csi_qspi_memory_mapped(csi_qspi_t *qspi, csi_qspi_command_t *cmd); + +/** + \brief Enable qspi power manage + \param[in] qspi QSPI handle to operate + \return Error code +*/ +csi_error_t csi_qspi_enable_pm(csi_qspi_t *qspi); + +/** + \brief Disable qspi power manage + \param[in] qspi QSPI handle to operate + \return None +*/ +void csi_qspi_disable_pm(csi_qspi_t *qspi); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_QSPI_H_*/ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/ringbuf.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/ringbuf.h new file mode 100755 index 00000000..e5006e16 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/ringbuf.h @@ -0,0 +1,62 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** +* @file ringbuffer.h +* @brief header file for ringbuffer Driver +* @version V1.0 +* @date August 15. 2019 +******************************************************************************/ +#ifndef _RING_BUFFER_H_ +#define _RING_BUFFER_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "stdint.h" +#include + +typedef struct ringbuffer { + uint8_t *buffer; + uint32_t size; + uint32_t write; + uint32_t read; + uint32_t data_len; +} csi_ringbuf_t; + +void csi_ringbuf_reset(csi_ringbuf_t *fifo); +uint32_t csi_ringbuf_len(csi_ringbuf_t *fifo); +uint32_t csi_ringbuf_avail(csi_ringbuf_t *fifo); +bool csi_ringbuf_is_empty(csi_ringbuf_t *fifo); +bool csi_ringbuf_is_full(csi_ringbuf_t *fifo); + +/*write to ringbuffer*/ +uint32_t csi_ringbuf_in(csi_ringbuf_t *fifo, const void *in, uint32_t len); + +/*read to ringbuffer*/ +uint32_t csi_ringbuf_out(csi_ringbuf_t *fifo, void *out, uint32_t len); + +/*move to another ringbuffer*/ +uint32_t csi_ringbuf_move(csi_ringbuf_t *fifo_in, csi_ringbuf_t *fifo_out); + +#ifdef __cplusplus +} +#endif + +#endif /* _RING_BUFFER_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/rng.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/rng.h new file mode 100755 index 00000000..11e03f44 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/rng.h @@ -0,0 +1,54 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/tng.h + * @brief Header File for RNG Driver + * @version V1.0 + * @date 22. Apr 2020 + * @model tng + ******************************************************************************/ +#ifndef _DRV_TNG_H_ +#define _DRV_TNG_H_ + +#include "drv/common.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \brief Get data from the TNG engine + \param[out] Data Pointer to buffer with data get from TNG + \param[in] Num Number of data items,uinit in uint32 + \return Error code \ref csi_error_t +*/ +csi_error_t csi_rng_get_multi_word(uint32_t *data, uint32_t num); + +/** + \brief Get data from the TNG engine + \return Error code \ref csi_error_t +*/ +csi_error_t csi_rng_get_single_word(uint32_t* data); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_TNG_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/rsa.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/rsa.h new file mode 100755 index 00000000..ea5b005d --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/rsa.h @@ -0,0 +1,198 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/****************************************************************************** + * @file drv/rsa.h + * @brief Header File for RSA Driver + * @version V1.0 + * @date 02. June 2020 + * @model rsa + ******************************************************************************/ +#ifndef _DRV_RSA_H_ +#define _DRV_RSA_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/*----- RSA Control Codes: Mode Parameters: Key Bits -----*/ +/****** RSA Key bits Type *****/ +typedef enum { + RSA_KEY_BITS_192 = 0U, /* 192 Key bits */ + RSA_KEY_BITS_256, /* 256 Key bits */ + RSA_KEY_BITS_512, /* 512 Key bits */ + RSA_KEY_BITS_1024, /* 1024 Key bits */ + RSA_KEY_BITS_2048, /* 2048 Key bits */ + RSA_KEY_BITS_3072, /* 3072 Key bits */ + RSA_KEY_BITS_4096 /* 4096 Key bits */ +} csi_rsa_key_bits_t; + +/****** RSA Padding Type *****/ +typedef enum { + RSA_PADDING_MODE_NO = 0, /* RSA NO Padding Mode */ + RSA_PADDING_MODE_PKCS1, /* RSA PKCS1 Padding Mode */ + RSA_PADDING_MODE_PKCS1_OAEP, /* RSA PKCS1 OAEP Padding Mode */ + RSA_PADDING_MODE_SSLV23, /* RSA SSLV23 Padding Mode */ + RSA_PADDING_MODE_X931, /* RSA X931 Padding Mode */ + RSA_PADDING_MODE_PSS /* RSA PSS Padding Mode */ +} csi_rsa_padding_type_t; + +/****** RSA Hash Type *****/ +typedef enum { + RSA_HASH_TYPE_MD5 = 0, + RSA_HASH_TYPE_SHA1, + RSA_HASH_TYPE_SHA224, + RSA_HASH_TYPE_SHA256, + RSA_HASH_TYPE_SHA384, + RSA_HASH_TYPE_SHA512 +} csi_rsa_hash_type_t; + +/****** RSA Context *****/ +typedef struct { + void *n; /* Pointer to the public modulus */ + void *e; /* Pointer to the public exponent */ + void *d; /* Pointer to the private exponent */ + csi_rsa_key_bits_t key_bits; /* RSA KEY BITS */ + csi_rsa_padding_type_t padding_type; /* RSA PADDING TYPE */ +} csi_rsa_context_t; + +/****** RSA State *****/ +typedef struct { + uint8_t busy : 1; /* Calculate busy flag */ + uint8_t error : 1; /* Calculate error flag */ +} csi_rsa_state_t; + +/****** RSA Ctrl *****/ +typedef struct { + csi_dev_t dev; + void *cb; + void *arg; + csi_rsa_state_t state; + void *prim; +} csi_rsa_t; + +/****** RSA Moddle *****/ +typedef struct { + uint32_t pout[64]; + uint8_t *pouts; + uint32_t *pout_size; + uint32_t u32keywords; + uint8_t *pdst; + uint32_t u32padding; + uint32_t u32dst_words; + uint32_t u32type; + uint32_t rsa_state; +}rsa_middle_t; + +/****** RSA Event *****/ +typedef enum { + RSA_EVENT_COMPLETE = 0, /* rsa event completed */ + RSA_EVENT_VERIFY_SUCCESS, /* rsa event verify success */ + RSA_EVENT_VERIFY_FAILED, /* rsa event verify failed */ + RSA_EVENT_ERROR, /* rsa event error */ +} csi_rsa_event_t; + +typedef void (*csi_rsa_callback_t)(csi_rsa_t *rsa, csi_rsa_event_t event, void *arg); ///< Pointer to \ref csi_rsa_callback_t : RSA Event call back. + +/** + \brief Initialize RSA Interface. 1. Initializes the resources needed for the RSA interface 2.registers event callback function + \param[in] rsa RSA handle to operate. + \param[in] idx Device id + \return Error code \ref csi_error_t +*/ +csi_error_t csi_rsa_init(csi_rsa_t *rsa, uint32_t idx); + +/** + \brief De-initialize RSA Interface. stops operation and releases the software resources used by the interface + \param[in] rsa RSA handle to operate. + \return none +*/ +void csi_rsa_uninit(csi_rsa_t *rsa); + +/** + \brief Generate rsa key pair. + \param[in] rsa RSA handle to operate. + \param[out] context Pointer to the rsa context + \return Error code \ref csi_error_t +*/ +csi_error_t csi_rsa_gen_key(csi_rsa_t *rsa, csi_rsa_context_t *context); + +/** + \brief Encrypt + \param[in] rsa RSA handle to operate. + \param[in] context Pointer to the rsa context + \param[in] src Pointer to the source data. + \param[in] src_size The source data len + \param[out] out Pointer to the result buffer + \return Error code \ref csi_error_t +*/ +csi_error_t csi_rsa_encrypt(csi_rsa_t *rsa, csi_rsa_context_t *context, void *src, uint32_t src_size, void *out); + +/** + \brief decrypt + \param[in] rsa RSA handle to operate. + \param[in] context Pointer to the rsa context + \param[in] src Pointer to the source data. + \param[in] src_size The source data len + \param[out] out Pointer to the result buffer + \param[out] out_size The result size + \return Error code \ref csi_error_t +*/ +csi_error_t csi_rsa_decrypt(csi_rsa_t *rsa, csi_rsa_context_t *context, void *src, uint32_t src_size, void *out, uint32_t *out_size); + +/** + \brief RSA sign + \param[in] rsa RSA handle to operate. + \param[in] context Pointer to the rsa context + \param[in] src Pointer to the source data. + \param[in] src_size The source data len + \param[out] signature Pointer to the signature + \param[in] hash_type The source data hash type + \return Error code \ref csi_error_t +*/ +csi_error_t csi_rsa_sign(csi_rsa_t *rsa, csi_rsa_context_t *context, void *src, uint32_t src_size, void *signature, csi_rsa_hash_type_t hash_type); + +/** + \brief RSA verify + \param[in] rsa RSA handle to operate. + \param[in] context Pointer to the rsa context + \param[in] src Pointer to the source data. + \param[in] src_size The source data len + \param[in] signature Pointer to the signature + \param[in] sig_size The signature size + \param[in] hash_type The source data hash type + \return Verify result +*/ +bool csi_rsa_verify(csi_rsa_t *rsa, csi_rsa_context_t *context, void *src, uint32_t src_size, void *signature, uint32_t sig_size, csi_rsa_hash_type_t hash_type); + +/** + \brief Get big prime data + \param[in] rsa RSA handle to operate. + \param[in] p Pointer to the prime + \param[in] bit_length Pointer to the prime bit length + \return Error code \ref csi_error_t +*/ +csi_error_t csi_rsa_get_prime(csi_rsa_t *rsa, void *p, uint32_t bit_length); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_RSA_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/rtc.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/rtc.h new file mode 100755 index 00000000..29742f3c --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/rtc.h @@ -0,0 +1,148 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/rtc.h + * @brief Header File for RTC Driver + * @version V1.0 + * @date 9. Oct 2020 + * @model rtc + ******************************************************************************/ + +#ifndef _DRV_RTC_H_ +#define _DRV_RTC_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/****** RTC time ******/ +typedef struct { + int tm_sec; ///< Second. [0-59] + int tm_min; ///< Minute. [0-59] + int tm_hour; ///< Hour. [0-23] + int tm_mday; ///< Day. [1-31] + int tm_mon; ///< Month. [0-11] + int tm_year; ///< Year-1900. [70- ] !NOTE:Set 100 mean 2000 + int tm_wday; ///< Day of week. [0-6 ] !NOTE:Set 0 mean Sunday + int tm_yday; ///< Days in year.[0-365] !NOTE:Set 0 mean January 1st +} csi_rtc_time_t; + +/****** definition for RTC ******/ +typedef struct csi_rtc csi_rtc_t; + +struct csi_rtc { + csi_dev_t dev; + void (*callback)(csi_rtc_t *rtc, void *arg); + void *arg; + void *priv; +}; + +/** + \brief Initialize RTC interface. Initializes the resources needed for the RTC interface + \param[in] rtc Handle to operate + \param[in] idx RTC index + \return Error code \ref csi_error_t +*/ +csi_error_t csi_rtc_init(csi_rtc_t *rtc, uint32_t idx); + +/** + \brief De-initialize RTC interface. Stops operation and releases the software resources used by the interface + \param[in] rtc Handle to operate + \return None +*/ +void csi_rtc_uninit(csi_rtc_t *rtc); + +/** + \brief Set system date and wait for synchro + \param[in] rtc Handle to operate + \param[in] rtctime Pointer to RTC time + \return Error code \ref csi_error_t +*/ +csi_error_t csi_rtc_set_time(csi_rtc_t *rtc, const csi_rtc_time_t *rtctime); + +/** + \brief Set system date but no wait + \param[in] rtc Handle to operate + \param[in] rtctime Pointer to RTC time + \return Error code \ref csi_error_t +*/ +csi_error_t csi_rtc_set_time_no_wait(csi_rtc_t *rtc, const csi_rtc_time_t *rtctime); + +/** + \brief Get system date + \param[in] rtc Handle to operate + \param[out] rtctime Pointer to RTC time + \return Error code \ref csi_error_t +*/ +csi_error_t csi_rtc_get_time(csi_rtc_t *rtc, csi_rtc_time_t *rtctime); + +/** + \brief Get alarm remaining time + \param[in] rtc Handle to operate + \return The remaining time(s) +*/ +uint32_t csi_rtc_get_alarm_remaining_time(csi_rtc_t *rtc); + +/** + \brief Config RTC alarm timer + \param[in] rtc Handle to operate + \param[in] rtctime Time to wake up + \param[in] callback Callback function + \param[in] arg Callback's param + \return Error code \ref csi_error_t +*/ +csi_error_t csi_rtc_set_alarm(csi_rtc_t *rtc, const csi_rtc_time_t *rtctime, void *callback, void *arg); + +/** + \brief Cancel the RTC alarm + \param[in] rtc Handle to operate + \return Error code \ref csi_error_t +*/ +csi_error_t csi_rtc_cancel_alarm(csi_rtc_t *rtc); + +/** + \brief Judge RTC is running + \param[in] rtc Handle to operate + \return + true - RTC is running + false - RTC is not running +*/ +bool csi_rtc_is_running(csi_rtc_t *rtc); + +/** + \brief Enable RTC power manage + \param[in] rtc Handle to operate + \return Error code \ref csi_error_t +*/ +csi_error_t csi_rtc_enable_pm(csi_rtc_t *rtc); + +/** + \brief Disable RTC power manage + \param[in] rtc Handle to operate + \return None +*/ +void csi_rtc_disable_pm(csi_rtc_t *rtc); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_RTC_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/sasc.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/sasc.h new file mode 100755 index 00000000..6a7f6a04 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/sasc.h @@ -0,0 +1,144 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/sasc.h + * @brief Header File for SASC driver + * @version V1.0 + * @date 02. June 2020 + * @model sasc + ******************************************************************************/ +#ifndef _DRV_SASC_H_ +#define _DRV_SASC_H_ + + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif +typedef enum { + SASC_RW = 0, + SASC_RO = 1, + SASC_WO = 2, + SASC_AP_DENY = 3 +} csi_sasc_ap_t; + +typedef enum { + SASC_DI = 0, + SASC_DO = 1, + SASC_IO = 2, + SASC_DI_DENY = 3 +} csi_sasc_di_t; + +typedef enum { + SASC_RAM_4B = 5, + SASC_RAM_8B = 6, + SASC_RAM_16B = 7, + SASC_RAM_32B = 8, + SASC_RAM_64B = 9, + SASC_RAM_128B = 10, + SASC_RAM_256B = 11, + SASC_RAM_512B = 12, + SASC_RAM_1KB = 13, + SASC_RAM_2KB = 14, + SASC_RAM_4KB = 15, + SASC_RAM_8KB = 16, + SASC_RAM_16KB = 17, + SASC_RAM_32KB = 18, + SASC_RAM_64KB = 19, + SASC_RAM_128KB = 20, +} csi_sasc_ram_size_t; + +typedef enum { + SASC_FLASH_1S = 0, + SASC_FLASH_2S, + SASC_FLASH_4S, + SASC_FLASH_8S, + SASC_FLASH_16S, + SASC_FLASH_32S, + SASC_FLASH_64S, + SASC_FLASH_128S, + SASC_FLASH_256S, + SASC_FLASH_512S, + SASC_FLASH_1024S, + SASC_FLASH_2048S +} csi_sasc_flash_size_t; + +typedef struct { + csi_sasc_ap_t super_ap; + csi_sasc_ap_t user_ap; + csi_sasc_di_t super_di; + csi_sasc_di_t user_di; + bool is_secure; +} csi_sasc_attr_t; + +/** + \brief Config the sasc ram region attribute. + \param[in] region_id Config region index + \param[in] base_addr Config region base address. + \param[in] size config region size. + \param[in] attr Region attr. + \return Error code +*/ +csi_error_t csi_sasc_ram_config(uint8_t region_id, uint32_t base_addr, csi_sasc_ram_size_t size, csi_sasc_attr_t attr); + +/** + \brief Config the sasc flash region attribute. + \param[in] region_id Config region index + \param[in] base_addr Config region base address. + \param[in] size Config region size. + \param[in] attr Region attr. + \return Error code +*/ +csi_error_t csi_sasc_flash_config(uint8_t region_id, uint32_t base_addr, csi_sasc_flash_size_t size, csi_sasc_attr_t attr); + +/** + \brief Enable sasc ram config. + \param[in] region_id Region index + \return error code +*/ +csi_error_t csi_sasc_ram_enable(uint8_t region_id); + +/** + \brief Enable sasc flash config + \param[in] region_id Config region index + \return error code +*/ +csi_error_t csi_sasc_flash_enable(uint8_t region_id); + +/** + \brief Disable sasc ram config. + \param[in] region_id Region index + \return error code +*/ +csi_error_t csi_sasc_ram_disable(uint8_t region_id); + +/** + \brief Disable sasc flash config + \param[in] region_id Region index + \return error code +*/ +csi_error_t csi_sasc_flash_disable(uint8_t region_id); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_SASC_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/sdif.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/sdif.h new file mode 100755 index 00000000..0508912b --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/sdif.h @@ -0,0 +1,441 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/sdif.h + * @brief Header File for SDIF Driver + * @version V1.0 + * @date 28. June 2020 + * @model sdif + ******************************************************************************/ +#ifndef _DRV_SDIF_H_ +#define _DRV_SDIF_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void *sdif_handle_t; + +/*! @brief Construct a status code value from a group and code number. */ +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) + +/*! @brief Status group numbers. */ +enum _status_groups { + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ + kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ +}; + +/*! @brief Generic status return codes. */ +enum _generic_status { + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), + kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), +}; + +/*! @brief SDIF status */ +enum _sdif_status { + kStatus_SDIF_DescriptorBufferLenError = MAKE_STATUS(kStatusGroup_SDIF, 0U), /*!< Set DMA descriptor failed */ + kStatus_SDIF_InvalidArgument = MAKE_STATUS(kStatusGroup_SDIF, 1U), /*!< invalid argument status */ + kStatus_SDIF_SyncCmdTimeout = MAKE_STATUS(kStatusGroup_SDIF, 2U), /*!< sync command to CIU timeout status */ + kStatus_SDIF_SendCmdFail = MAKE_STATUS(kStatusGroup_SDIF, 3U), /*!< send command to card fail */ + kStatus_SDIF_SendCmdErrorBufferFull = + MAKE_STATUS(kStatusGroup_SDIF, 4U), /*!< send command to card fail, due to command buffer full + user need to resend this command */ + kStatus_SDIF_DMATransferFailWithFBE = + MAKE_STATUS(kStatusGroup_SDIF, 5U), /*!< DMA transfer data fail with fatal bus error , + to do with this error :issue a hard reset/controller reset*/ + kStatus_SDIF_DMATransferDescriptorUnavailable = + MAKE_STATUS(kStatusGroup_SDIF, 6U), /*!< DMA descriptor unavailable */ + kStatus_SDIF_DataTransferFail = MAKE_STATUS(kStatusGroup_SDIF, 6U), /*!< transfer data fail */ + kStatus_SDIF_ResponseError = MAKE_STATUS(kStatusGroup_SDIF, 7U), /*!< response error */ + kStatus_SDIF_DMAAddrNotAlign = MAKE_STATUS(kStatusGroup_SDIF, 8U), /*!< DMA address not align */ +}; + +/*! @brief Type used for all status and error return values. */ +typedef int32_t status_t; + +/*! @brief Computes the number of elements in an array. */ +#if !defined(ARRAY_SIZE) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1))) + +///< #define assert(__e) ((void)0) +/*! @name Min/max macros */ +#if !defined(MIN) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#endif + +#if !defined(MAX) +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#endif + +#define SDK_ALIGN(var, alignbytes) var + +static inline unsigned long cpu_to_dma(unsigned long addr) +{ + return addr; +} + +static inline unsigned long *ptr_cpu_to_dma(unsigned long *addr) +{ + return (unsigned long *)cpu_to_dma((unsigned long)addr); +} + +typedef enum { + SDIF_ERROR_CMD_CRC_FAIL = (1), ///< Command response received (but CRC check failed) + SDIF_ERROR_DATA_CRC_FAIL, ///< Data block sent/received (CRC check failed) + SDIF_ERROR_CMD_RSP_TIMEOUT, ///< Command response timeout + SDIF_ERROR_DATA_TIMEOUT, ///< Data timeout + SDIF_ERROR_TX_UNDERRUN, ///< Transmit FIFO underrun + SDIF_ERROR_RX_OVERRUN, ///< Receive FIFO overrun + SDIF_ERROR_ADDR_MISALIGNED, ///< Misaligned address + SDIF_ERROR_BLOCK_LEN_ERR, ///< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length + SDIF_ERROR_ERASE_SEQ_ERR, ///< An error in the sequence of erase command occurs + SDIF_ERROR_BAD_ERASE_PARAM, ///< An invalid selection for erase groups + SDIF_ERROR_WRITE_PROT_VIOLATION, ///< Attempt to program a write protect block + SDIF_ERROR_LOCK_UNLOCK_FAILED, ///< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card + SDIF_ERROR_COM_CRC_FAILED, ///< CRC check of the previous command failed + SDIF_ERROR_ILLEGAL_CMD, ///< Command is not legal for the card state + SDIF_ERROR_CARD_ECC_FAILED, ///< Card internal ECC was applied but failed to correct the data + SDIF_ERROR_CC_ERR, ///< Internal card controller error + SDIF_ERROR_GENERAL_UNKNOWN_ERR, ///< General or unknown error + SDIF_ERROR_STREAM_READ_UNDERRUN, ///< The card could not sustain data reading in stream rmode + SDIF_ERROR_STREAM_WRITE_OVERRUN, ///< The card could not sustain data programming in stream mode + SDIF_ERROR_CID_CSD_OVERWRITE, ///< CID/CSD overwrite error + SDIF_ERROR_WP_ERASE_SKIP, ///< Only partial address space was erased + SDIF_ERROR_CARD_ECC_DISABLED, ///< Command has been executed without using internal ECC + SDIF_ERROR_ERASE_RESET, ///< Erase sequence was cleared before executing because an out + SDIF_ERROR_AKE_SEQ_ERR, ///< Error in sequence of authentication + SDIF_ERROR_INVALID_VOLTRANGE, ///< Error in case of invalid voltage range + SDIF_ERROR_ADDR_OUT_OF_RANGE, ///< Error when addressed block is out of range + SDIF_ERROR_REQUEST_NOT_APPLICABLE, ///< Error when command request is not applicable + SDIF_ERROR_UNSUPPORTED_FEATURE, ///< Error when feature is not insupported +} sdif_error_e; + +/* Host controller capabilities flag mask */ +typedef enum { + SDIF_SUPPORT_HIGH_SPEED = 0x1U, ///< Support high-speed + SDIF_SUPPORT_DMA_SPEED = 0x2U, ///< Support DMA + SDIF_SUPPORT_USPEND_RESUME = 0x4U, ///< Support suspend/resume + SDIF_SUPPORT_V330 = 0x8U, ///< Support voltage 3.3V + SDIF_SUPPORT_4BIT = 0x10U, ///< Support 4 bit mode + SDIF_SUPPORT_8BIT = 0x20U, ///< Support 8 bit mode +} sdif_capability_flag_e; + +/* \brief define the internal DMA mode */ +typedef enum { + SDIF_CHAIN_DMA_MODE = 0x01U, ///< one descriptor with one buffer,but one descriptor point to another + SDIF_DUAL_DMA_MODE = 0x02U, ///< dual mode is one descriptor with two buffer +} sdif_dma_mode_e; + +/* The command type */ +typedef enum { + SDIF_CARD_COMMAND_NORMAL = 0U, ///< Normal command + SDIF_CARD_COMMAND_SUSPEND = 1U, ///< Suspend command + SDIF_CARD_COMMAND_RESUME = 2U, ///< Resume command + SDIF_CARD_COMMAND_ABORT = 3U, ///< Abort command +} sdif_card_command_type_e; + +/* The command response type */ +typedef enum { + SDIF_CARD_RESPONSE_NONE = 0U, ///< Response type: none + SDIF_CARD_RESPONSE_R1 = 1U, ///< Response type: R1 + SDIF_CARD_RESPONSE_R1b = 2U, ///< Response type: R1b + SDIF_CARD_RESPONSE_R2 = 3U, ///< Response type: R2 + SDIF_CARD_RESPONSE_R3 = 4U, ///< Response type: R3 + SDIF_CARD_RESPONSE_R4 = 5U, ///< Response type: R4 + SDIF_CARD_RESPONSE_R5 = 6U, ///< Response type: R5 + SDIF_CARD_RESPONSE_R5b = 7U, ///< Response type: R5b + SDIF_CARD_RESPONSE_R6 = 8U, ///< Response type: R6 + SDIF_CARD_RESPONSE_R7 = 9U, ///< Response type: R7 +} sdif_card_response_type_e; + +/* \brief define the card bus width type */ +typedef enum { + SDIF_BUS_1BIT_WIDTH = 0U, ///< 1bit bus width, 1bit mode and 4bit mode share one register bit + SDIF_BUS_4BIT_WIDTH = 1U, ///< 4bit mode mask + SDIF_BUS_8BIT_WIDTH = 2U, ///< support 8 bit mode +} sdif_bus_width_e; + +/* \brief Defines the internal DMA configure structure. */ +typedef struct { + bool enable_fix_burst_len; ///< fix burst len enable/disable flag,When set, the AHB will + ///< use only SINGLE, INCR4, INCR8 or INCR16 during start of + ///< normal burst transfers. When reset, the AHB will use SINGLE + ///< and INCR burst transfer operations + + sdif_dma_mode_e mode; ///< define the DMA mode */ + + + uint32_t *dma_des_buffer_start_addr; ///< internal DMA descriptor start address + uint32_t dma_des_buffer_len; ///< internal DMA buffer descriptor buffer len ,user need to pay attention to the + ///< dma descriptor buffer length if it is bigger enough for your transfer + uint8_t dma_dws_skip_len; ///< define the descriptor skip length ,the length between two descriptor + ///< this field is special for dual DMA mode +} sdif_dma_config_t; + +/* \brief sdif callback functions. */ +typedef struct { + void (*card_inserted)(uint32_t idx, void *user_data); ///< card insert call back + void (*card_removed)(uint32_t idx, void *user_data); ///< card remove call back + void (*sdif_interrupt)(uint32_t idx, void *user_data); ///< SDIF card interrupt occurs + void (*dma_des_unavailable)(uint32_t idx, void *user_data);///< DMA descriptor unavailable + void (*command_reload)(uint32_t idx, void *user_data); ///< command buffer full,need re-load + void (*transfer_complete)(uint32_t idx, + void *state, + int32_t status, + void *user_data); /// +#include +#include + + +typedef enum { + SENSOR_VDS_3V3_3V3 = 1, + SENSOR_VDS_2V5_3V3, + SENSOR_VDS_1V8_1V8, + SENSOR_VDS_1V5_1V8, + SENSOR_VDS_1V2_1V2, + SENSOR_VDS_1V1_1V2 +}drv_sensor_vds_t; + +typedef enum { + SENSOR_VHS_RANGE_15 = 0, + SENSOR_VHS_RANGE_12, + SENSOR_VHS_RANGE_9, + SENSOR_VHS_RANGE_6, +}drv_sensor_vhs_t; + +typedef enum { + SENSOR_VLS_RANGE_6 = 0, + SENSOR_VLS_RANGE_9, + SENSOR_VLS_RANGE_12, + SENSOR_VLS_RANGE_15, +}drv_sensor_vls_t; + +typedef enum { + SENSOR_TDHS_NEG_55 = 0, ///< -55 + SENSOR_TDHS_NEG_50, + SENSOR_TDHS_NEG_45, + SENSOR_TDHS_NEG_40, + SENSOR_TDHS_NEG_35, + SENSOR_TDHS_NEG_30, + SENSOR_TDHS_NEG_25, + SENSOR_TDHS_NEG_20, + SENSOR_TDHS_NEG_15, + SENSOR_TDHS_NEG_10, + SENSOR_TDHS_NEG_5, + SENSOR_TDHS_NEG_0, + SENSOR_TDHS_POS_5, ///< +5 + SENSOR_TDHS_POS_10, + SENSOR_TDHS_POS_15, + SENSOR_TDHS_POS_20, + SENSOR_TDHS_POS_25, + SENSOR_TDHS_POS_30, + SENSOR_TDHS_POS_35, + SENSOR_TDHS_POS_40, + SENSOR_TDHS_POS_45, + SENSOR_TDHS_POS_50, + SENSOR_TDHS_POS_55, + SENSOR_TDHS_POS_60, + SENSOR_TDHS_POS_65, + SENSOR_TDHS_POS_70, + SENSOR_TDHS_POS_75, + SENSOR_TDHS_POS_80, + SENSOR_TDHS_POS_85, + SENSOR_TDHS_POS_90, + SENSOR_TDHS_POS_95, + SENSOR_TDHS_POS_100, + SENSOR_TDHS_POS_105, + SENSOR_TDHS_POS_110, + SENSOR_TDHS_POS_115, + SENSOR_TDHS_POS_120, + SENSOR_TDHS_POS_125 +}drv_sensor_tdhs_t; + +typedef enum { + SENSOR_TDLS_NEG_55 = 0, ///< -55 + SENSOR_TDLS_NEG_50, + SENSOR_TDLS_NEG_45, + SENSOR_TDLS_NEG_40, + SENSOR_TDLS_NEG_35, + SENSOR_TDLS_NEG_30, + SENSOR_TDLS_NEG_25, + SENSOR_TDLS_NEG_20, + SENSOR_TDLS_NEG_15, + SENSOR_TDLS_NEG_10, + SENSOR_TDLS_NEG_5, + SENSOR_TDLS_NEG_0, + SENSOR_TDLS_POS_5, ///< +5 + SENSOR_TDLS_POS_10, + SENSOR_TDLS_POS_15, + SENSOR_TDLS_POS_20, +}drv_sensor_tdls_t; + +typedef enum { + SENSOR_FHS_RANGE_50 = 0, + SENSOR_FHS_RANGE_30, + SENSOR_FHS_RANGE_10, + SENSOR_FHS_RANGE_5, +}drv_sensor_fhs_t; + +typedef enum { + SENSOR_FLS_RANGE_50 = 0, + SENSOR_FLS_RANGE_30, + SENSOR_FLS_RANGE_10, + SENSOR_FLS_RANGE_5, +}drv_sensor_fls_t; + +typedef enum { + SENSOR_FHS_FREQ_33M = 0, + SENSOR_FHS_FREQ_66M, + SENSOR_FHS_FREQ_24M, + SENSOR_FHS_FREQ_12M, + SENSOR_FHS_FREQ_99M, + SENSOR_FHS_FREQ_198M, + SENSOR_FHS_FREQ_72M, + SENSOR_FHS_FREQ_36M, +}drv_sensor_freq_t; + +typedef enum { + SENSOR_WARN_H = 0, + SENSOR_WARN_L, + SENSOR_WARN_RST, +}drv_sensor_warn_t; + +/** + \brief Initialize Sensor VD + \param[in] vds Voltage range + \param[in] vhs Voltage high threshold + \param[in] vls Voltage low threshold + \param[in] vtm Used to modify the threshold value of the voltage detection point + \return Error code +*/ +csi_error_t drv_sensor_vd_init(drv_sensor_vds_t vds,drv_sensor_vhs_t vhs,drv_sensor_vls_t vls,uint8_t vtm); + +/** + \brief Get vd warn + \param[in] warn Vd warn select + \return Vd warn code +*/ +uint32_t drv_sensor_vd_get_warn(drv_sensor_warn_t warn); + +/** + \brief Initialize Sensor td + \param[in] hs Temp high threshold + \param[in] ls Temp low threshold + \return Error code +*/ +csi_error_t drv_sensor_td_init(drv_sensor_tdhs_t hs,drv_sensor_tdls_t ls); + +/** + \brief Get td warn + \param[in] warn Td warn select + \return Td warn code +*/ +uint32_t drv_sensor_td_get_warn(drv_sensor_warn_t warn); + +/** + \brief Initialize Sensor FD + \param[in] hs Temp high threshold + \param[in] ls Temp low threshold + \return Error code +*/ +csi_error_t drv_sensor_fd_init(drv_sensor_freq_t freq,drv_sensor_fhs_t fhs,drv_sensor_fls_t fls); + +/** + \brief Get fd warn + \param[in] warn Fd warn select + \return FD warn code +*/ +uint32_t drv_sensor_fd_get_warn(drv_sensor_warn_t warn); + +#endif /* _DRV_SENSOR_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/sha.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/sha.h new file mode 100755 index 00000000..668b9dcc --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/sha.h @@ -0,0 +1,128 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/sha.h + * @brief Header File for SHA Driver + * @version V1.0 + * @date 9. Oct 2020 + * @model sha + ******************************************************************************/ + +#ifndef _DRV_SHA_H_ +#define _DRV_SHA_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/****** SHA mode ******/ +typedef enum { + SHA_MODE_1 = 1U, /* SHA_1 mode */ + SHA_MODE_256, /* SHA_256 mode */ + SHA_MODE_224, /* SHA_224 mode */ + SHA_MODE_512, /* SHA_512 mode */ + SHA_MODE_384, /* SHA_384 mode */ + SHA_MODE_512_256, /* SHA_512_256 mode */ + SHA_MODE_512_224, /* SHA_512_224 mode */ + SHA_MODE_MD5 /* MD5 mode */ +} csi_sha_mode_t; + +/****** SHA State ******/ +typedef struct { + uint32_t busy : 1; /* Calculate busy flag */ + uint32_t error : 1; /* Calculate error flag */ +} csi_sha_state_t; + +/****** SHA Context ******/ +typedef struct { + csi_sha_mode_t mode; /* SHA mode */ + uint32_t total[2]; /* Number of bytes processed */ + uint32_t state[16]; /* Intermediate digest state */ + uint8_t buffer[128]; /* Data block being processed */ +} csi_sha_context_t; + +/****** SHA Event ******/ +typedef enum { + SHA_EVENT_COMPLETE = 0U, /*Calculate completed*/ + SHA_EVENT_ERROR /*Calculate error*/ +} csi_sha_event_t; + +/****** SHA Ctrl ******/ +typedef struct csi_sha csi_sha_t; +struct csi_sha{ + csi_dev_t dev; + void (*callback)(csi_sha_t *sha, csi_sha_event_t event, void *arg); /* SHA event callback for user */ + void *arg; /* SHA custom designed param passed to evt_cb */ + csi_dma_ch_t *dma_in; /* SHA in dma handle param */ + csi_sha_state_t state; /* SHA state */ + void *priv; +}; + +/** + \brief Initialize SHA Interface. Initializes the resources needed for the SHA interface + \param[in] sha Operate handle + \param[in] idx Index of SHA + \return Error code \ref csi_error_t +*/ +csi_error_t csi_sha_init(csi_sha_t *sha, uint32_t idx); + +/** + \brief De-initialize SHA Interface. Stops operation and releases the software resources used by the interface + \param[in] sha SHA handle to operate + \return None +*/ +void csi_sha_uninit(csi_sha_t *sha); + +/** + \brief Start the engine + \param[in] sha Handle to operate + \param[in] context Pointer to the SHA context \ref csi_sha_context_t + \param[in] mode SHA mode \ref csi_sha_mode_t + \return Error code \ref csi_error_t +*/ +csi_error_t csi_sha_start(csi_sha_t *sha, csi_sha_context_t *context, csi_sha_mode_t mode); + +/** + \brief Update the engine + \param[in] sha Handle to operate + \param[in] context Pointer to the SHA context \ref csi_sha_context_t + \param[in] input Pointer to the Source data + \param[in] size The data size + \return Error code \ref csi_error_t +*/ +csi_error_t csi_sha_update(csi_sha_t *sha, csi_sha_context_t *context, const void *input, uint32_t size); + +/** + \brief Finish the engine + \param[in] sha Handle to operate + \param[in] context Pointer to the SHA context \ref csi_sha_context_t + \param[out] output Pointer to the result data + \param[out] out_size Pointer to the result data size(bytes) + \return Error code \ref csi_error_t +*/ +csi_error_t csi_sha_finish(csi_sha_t *sha, csi_sha_context_t *context, void *output, uint32_t *out_size); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_SHA_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/spi.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/spi.h new file mode 100755 index 00000000..80f7e4d3 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/spi.h @@ -0,0 +1,293 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/spi.h + * @brief Header File for SPI Driver + * @version V1.0 + * @date 08. Apr 2020 + * @model spi + ******************************************************************************/ + +#ifndef _DRV_SPI_H_ +#define _DRV_SPI_H_ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \enum csi_spi_mode_t + * \brief Function mode of spi + */ +typedef enum { + SPI_MASTER, ///< SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps + SPI_SLAVE, ///< SPI Slave (Output on MISO, Input on MOSI) +} csi_spi_mode_t; + +/** + * \enum csi_spi_frame_len_t + * \brief SPI data width (4bit ~ 16bit) + */ +typedef enum { + SPI_FRAME_LEN_4 = 4, + SPI_FRAME_LEN_5, + SPI_FRAME_LEN_6, + SPI_FRAME_LEN_7, + SPI_FRAME_LEN_8, + SPI_FRAME_LEN_9, + SPI_FRAME_LEN_10, + SPI_FRAME_LEN_11, + SPI_FRAME_LEN_12, + SPI_FRAME_LEN_13, + SPI_FRAME_LEN_14, + SPI_FRAME_LEN_15, + SPI_FRAME_LEN_16 +} csi_spi_frame_len_t; + +/** + * \enum csi_spi_format_t + * \brief Timing format of spi + */ +typedef enum { + SPI_FORMAT_CPOL0_CPHA0 = 0, ///< Clock Polarity 0, Clock Phase 0 + SPI_FORMAT_CPOL0_CPHA1, ///< Clock Polarity 0, Clock Phase 1 + SPI_FORMAT_CPOL1_CPHA0, ///< Clock Polarity 1, Clock Phase 0 + SPI_FORMAT_CPOL1_CPHA1, ///< Clock Polarity 1, Clock Phase 1 +} csi_spi_cp_format_t; + +/** + * \enum csi_spi_event_t + * \brief Signaled event for user by driver + */ +typedef enum { + SPI_EVENT_SEND_COMPLETE, ///< Data Send completed. Occurs after call to csi_spi_send_async to indicate that all the data has been send over + SPI_EVENT_RECEIVE_COMPLETE, ///< Data Receive completed. Occurs after call to csi_spi_receive_async to indicate that all the data has been received + SPI_EVENT_SEND_RECEIVE_COMPLETE, ///< Data Send_receive completed. Occurs after call to csi_spi_send_receive_async to indicate that all the data has been send_received + SPI_EVENT_ERROR_OVERFLOW, ///< Data overflow: Receive overflow + SPI_EVENT_ERROR_UNDERFLOW, ///< Data underflow: Transmit underflow + SPI_EVENT_ERROR ///< Master Mode Fault (SS deactivated when Master).Occurs in master mode when Slave Select is deactivated and indicates Master Mode Fault +} csi_spi_event_t; + +/** + * \struct csi_spi_t + * \brief Ctrl block of spi instance + */ +typedef struct csi_spi csi_spi_t; +struct csi_spi { + csi_dev_t dev; ///< Hw-device info + void (*callback)(csi_spi_t *spi, csi_spi_event_t event, void *arg); ///< User callback ,signaled by driver event + void *arg; ///< User private param ,passed to user callback + uint8_t *tx_data; ///< Output data buf + uint32_t tx_size; ///< Output data size specified by user + uint8_t *rx_data; ///< Input data buf + uint32_t rx_size; ///< Input data size specified by user + csi_error_t (*send)(csi_spi_t *spi, const void *data, uint32_t size); ///< The send_async func + csi_error_t (*receive)(csi_spi_t *spi, void *data, uint32_t size); ///< The receive_async func + csi_error_t (*send_receive)(csi_spi_t *spi, const void *data_out, void *data_in, uint32_t size); ///< The send_receive_async func + csi_state_t state; ///< Peripheral state + csi_dma_ch_t *tx_dma; + csi_dma_ch_t *rx_dma; + void *priv; +}; + +/** + \brief Initialize SPI Interface + Initialize the resources needed for the SPI instance + \param[in] spi SPI handle + \param[in] idx SPI instance index + \return Error code +*/ +csi_error_t csi_spi_init(csi_spi_t *spi, uint32_t idx); + +/** + \brief De-initialize SPI Interface + stops Operation and releases the software resources used by the spi instance + \param[in] spi Handle + \return None +*/ +void csi_spi_uninit(csi_spi_t *spi); + +/** + \brief Attach the callback handler to SPI + \param[in] spi Operate handle + \param[in] callback Callback function + \param[in] arg User can define it by himself as callback's param + \return Error code +*/ +csi_error_t csi_spi_attach_callback(csi_spi_t *spi, void *callback, void *arg); + +/** + \brief Detach the callback handler + \param[in] spi Operate handle + \return None +*/ +void csi_spi_detach_callback(csi_spi_t *spi); + +/** + \brief Config spi mode (master or slave) + \param[in] spi SPI handle + \param[in] mode The mode of spi (master or slave) + \return Error code +*/ +csi_error_t csi_spi_mode(csi_spi_t *spi, csi_spi_mode_t mode); + +/** + \brief Config spi cp format + \param[in] spi SPI handle + \param[in] format SPI cp format + \return Error code +*/ +csi_error_t csi_spi_cp_format(csi_spi_t *spi, csi_spi_cp_format_t format); + +/** + \brief Config spi frame len + \param[in] spi SPI handle + \param[in] length SPI frame len + \return Error code +*/ +csi_error_t csi_spi_frame_len(csi_spi_t *spi, csi_spi_frame_len_t length); + +/** + \brief Config spi work frequence + \param[in] spi SPI handle + \param[in] baud SPI work baud + \return the actual config frequency +*/ +uint32_t csi_spi_baud(csi_spi_t *spi, uint32_t baud); + +/** + \brief Sending data to SPI transmitter,(received data is ignored) + blocking mode ,return unti all data has been sent or err happened + \param[in] spi Handle to operate + \param[in] data Pointer to buffer with data to send to SPI transmitter + \param[in] size Number of data to send(byte) + \param[in] timeout Unit in mini-second + \return If send successful, this function shall return the num of data witch is sent successful + otherwise, the function shall return Error code +*/ +int32_t csi_spi_send(csi_spi_t *spi, const void *data, uint32_t size, uint32_t timeout); + +/** + \brief Sending data to SPI transmitter,(received data is ignored) + non-blocking mode,transfer done event will be signaled by driver + \param[in] spi Handle to operate + \param[in] data Pointer to buffer with data to send to SPI transmitter + \param[in] size Number of data items to send(byte) + \return Error code +*/ +csi_error_t csi_spi_send_async(csi_spi_t *spi, const void *data, uint32_t size); + +/** + \brief Receiving data from SPI receiver + blocking mode, return untill curtain data items are readed + \param[in] spi Handle to operate + \param[out] data Pointer to buffer for data to receive from SPI receiver + \param[in] size Number of data items to receive(byte) + \param[in] timeout Unit in mini-second + \return If receive successful, this function shall return the num of data witch is received successful + otherwise, the function shall return Error code +*/ +int32_t csi_spi_receive(csi_spi_t *spi, void *data, uint32_t size, uint32_t timeout); + +/** + \brief Receiving data from SPI receiver + not-blocking mode, event will be signaled when receive done or err happend + \param[in] spi Handle to operate + \param[out] data Pointer to buffer for data to receive from SPI receiver + \param[in] size Number of data items to receive(byte) + \return Error code +*/ +csi_error_t csi_spi_receive_async(csi_spi_t *spi, void *data, uint32_t size); + +/** + \brief Dulplex,sending and receiving data at the same time + \ref csi_spi_event_t is signaled when operation completes or error happens + \ref csi_spi_get_state can get operation status + blocking mode, this function returns after operation completes or error happens + \param[in] spi SPI handle to operate + \param[in] data_out Pointer to buffer with data to send to SPI transmitter + \param[out] data_in Pointer to buffer for data to receive from SPI receiver + \param[in] size Data size(byte) + \return If transfer successful, this function shall return the num of data witch is transfer successful, + otherwise, the function shall return Error code +*/ +int32_t csi_spi_send_receive(csi_spi_t *spi, const void *data_out, void *data_in, uint32_t size, uint32_t timeout); + +/** + \brief Transmit first then receive ,receive will begin after transmit is done + if non-blocking mode, this function only starts the transfer, + \ref csi_spi_event_t is signaled when operation completes or error happens + \ref csi_spi_get_state can get operation status + \param[in] spi SPI handle to operate + \param[in] data_out Pointer to buffer with data to send to SPI transmitter + \param[out] data_in Pointer to buffer for data to receive from SPI receiver + \param[in] size Data size(byte) + \return Error code +*/ +csi_error_t csi_spi_send_receive_async(csi_spi_t *spi, const void *data_out, void *data_in, uint32_t size); + +/* + \brief Set slave select num. Only valid for master + \param[in] handle SPI handle to operate + \param[in] slave_num SPI slave num + \return None + */ +void csi_spi_select_slave(csi_spi_t *spi, uint32_t slave_num); + +/** + \brief Link DMA channel to spi device + \param[in] spi SPI handle to operate + \param[in] tx_dma The DMA channel handle for send, when it is NULL means to unlink the channel + \param[in] rx_dma The DMA channel handle for receive, when it is NULL means to unlink the channel + \return Error code +*/ +csi_error_t csi_spi_link_dma(csi_spi_t *spi, csi_dma_ch_t *tx_dma, csi_dma_ch_t *rx_dma); + +/** + \brief Get the state of spi device + \param[in] spi SPI handle to operate + \param[out] state The state of spi device + \return Error code +*/ +csi_error_t csi_spi_get_state(csi_spi_t *spi, csi_state_t *state); + +/** + \brief Enable spi power manage + \param[in] spi SPI handle to operate + \return Error code +*/ +csi_error_t csi_spi_enable_pm(csi_spi_t *spi); + +/** + \brief Disable spi power manage + \param[in] spi SPI handle to operate + \return Error code +*/ +void csi_spi_disable_pm(csi_spi_t *spi); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_SPI_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/spiflash.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/spiflash.h new file mode 100755 index 00000000..64a24ca9 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/spiflash.h @@ -0,0 +1,303 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/spiflash.h + * @brief Header File for SPIFLASH Driver + * @version V1.0 + * @date 02. June 2020 + * @model spiflash + ******************************************************************************/ +#ifndef _DRV_SPIFLASH_H_ +#define _DRV_SPIFLASH_H_ + +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* \brief Build a flash ID +* \param [in] vendor_id Vendor id(8bit) +* \param [in] device_id Flash device id (ID15~ID0) 16bit +* \return 24bit flash id +*/ +#define FLASH_ID_BUILD(VENDOR_ID,DEVICE_ID) + +/** +* \struct csi_spiflash_lock_info_t +* \ flash use status register 1 to protect data in memory array +* \ different flash vendor support different protect region (top/bottom/none) +* also support different protect number +* status1 register bif field show as follow +* 7 |6 |5 |4 |3 |2 |1 |0 +* --------------------------------------------------------------------- +* vensor def | vendor def | vendor def | BP2 | BP1 | BP0 | WEL | BUSY +* \ Protect type +* \ Protect block size : Vendor define ,user should check flash datasheet of vendor +* : Use w25q64fw as example , min protect block size is 128 KB +* \ TOP : Protect address from flash top address +* \ BOTTOM : Protect address from flash bottom address +* \ SEC : Protect addres base on sector unit and protect region only must not exceed one block +* \ BPx : Protect start addres base on TOP/BOTTOM feature,and BPx value denote protect number +* \ BP[x..0]'s value : 2^(n-1) protect block unit, ex, BP[x..0] = 5, protect block number = 2^(5-1) = 16 +* \ If BP[x..0] = 0 denote protect none +* \ If BP[x..0]'s all bis is 1 ,denote protect all flash +* \ +* \ NOTE: +* \ only support SEC = 0 +* \ only support CMP = 0 +* \ +* +* Sample table portion for 8MB flash (Winbond w25q64fw): +* +* SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion +* -------------------------------------------------------------------------- +* X | X | 0 | 0 | 0 | NONE | NONE +* 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64 +* 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32 +* 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16 +* 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8 +* 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 +* 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 +* X | X | 1 | 1 | 1 | 8 MB | ALL +* ------|-------|-------|-------|-------|---------------|------------------- +* 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64 +* 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32 +* 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16 +* 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8 +* 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4 +* 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2 +* +*/ +typedef enum { + LOCK_TP_NONE, + LOCK_TP_TOP, + LOCK_TP_BOTTOM, + LOCK_TP_DUAL +} csi_spiflash_lock_region_t; +typedef enum { + SPIFLASH_DATA_1_LINE = 1, + SPIFLASH_DATA_2_LINES = 2, + SPIFLASH_DATA_4_LINES = 4 +} csi_spiflash_data_line_t; +typedef union { + csi_spi_t spi; + csi_qspi_t qspi; +} csi_spi_qspi_t; + +/** +\brief Flash information +*/ +typedef struct { + char *flash_name; ///< Name string of spiflash + uint32_t flash_id; ///< JEDEC ID = manufature ID <<16 | device ID (ID15~ID0) + uint32_t flash_size; ///< Flash chip size + uint32_t xip_addr; ///< If use qspi controler to access flash ,code can be ececuted on flash ,the addr is xip addr + uint32_t sector_size; ///< Sector size + uint32_t page_size; ///< Page size for read or program +} csi_spiflash_info_t; + +typedef struct{ + struct{ + uint8_t buswidth; ///< cmd buswidth + }cmd; + struct { + uint8_t buswidth; ///< addr buswidth + }addr; + struct { + uint8_t nbytes; ///< dummy bytes + }dummy; + struct { + uint8_t buswidth; ///< data buswidth + }data; +} csi_spiflash_cmd_t; + +/** +\brief Flash control block +*/ +typedef struct { + csi_spi_qspi_t spi_qspi; ///< Spi/qspi handle + void (*spi_cs_callback)(csi_gpio_pin_state_t value); + void *flash_prv_info; ///< Point to vendor private feature struct + int32_t (*spi_send)(void *spi, uint8_t cmd, uint32_t addr, uint32_t addr_size, const void *data, uint32_t size); + int32_t (*spi_receive)(void *spi, uint8_t cmd, uint32_t addr, uint32_t addr_size, void *data, uint32_t size); + csi_error_t (*set_cmd)(void *spi, csi_spiflash_cmd_t *cmd); + void *priv; ///< User private param +} csi_spiflash_t; + +/** + \brief Initialize SPIFLASH with spi controler and probe flash device + \param[in] spiflash SPIFLASH handle + \param[in] spi_idx SPI controler index + \param[in] spi_cs GPIO info for chip select,if NULL, not use gpio cs + \return Error code +*/ +csi_error_t csi_spiflash_spi_init(csi_spiflash_t *spiflash, uint32_t spi_idx, void *spi_cs_callback); + +/** + \brief Initialize SPIFLASH with qspi controler and probe flash device + \param[in] spiflash SPIFLASH handle + \param[in] qspi_idx QSPI controler index + \return Error code +*/ +csi_error_t csi_spiflash_qspi_init(csi_spiflash_t *spiflash, uint32_t qspi_idx, void *qspi_cs_callback); + +/** + \brief De-initialize SPIFLASH Interface based on spi controler. stops operation and releases the software resources used by the interface + \param[in] spiflash SPIFLASH handle to operate + \return Error code +*/ +void csi_spiflash_spi_uninit(csi_spiflash_t *spiflash); + +/** + \brief De-initialize SPIFLASH Interface based on qspi controler. stops operation and releases the software resources used by the interface + \param[in] spiflash SPIFLASH handle to operate + \return Error code +*/ +void csi_spiflash_qspi_uninit(csi_spiflash_t *spiflash); + + +/** + \brief Get flash device infomation + \param[in] spiflash SPIFLASH handle to operate + \param[in] flash_info User storage to get flash vendor info after flash init + \return spiflash_info_t +*/ +csi_error_t csi_spiflash_get_flash_info(csi_spiflash_t *spiflash, csi_spiflash_info_t *flash_info); + + +/** + \brief Read data from Flash + \param[in] spiflash SPIFLASH handle to operate + \param[in] offset Data address, offset address relative to zero + \param[out] data Pointer to a buffer storing the data read from Flash + \param[in] size Number of data items to read + \return If receive successful, this function shall return the num of data witch is received successful + otherwise, the function shall return Error code +*/ +int32_t csi_spiflash_read(csi_spiflash_t *spiflash, uint32_t offset, void *data, uint32_t size); + +/** + \brief Program data to Flash + \param[in] spiflash SPIFLASH handle to operate + \param[in] offset Data address, offset address relative to zero + \param[in] data Pointer to a buffer containing the data to be programmed to Flash. + \param[in] size Number of data items to program + \return If program successful, this function shall return the num of data witch is program successful, + otherwise, the function shall return Error code +*/ +int32_t csi_spiflash_program(csi_spiflash_t *spiflash, uint32_t offset, const void *data, uint32_t size); + +/** + \brief Erase Flash Sector + \param[in] spiflash SPIFLASH handle to operate + \param[in] offset Data address, offset address relative to zero + \param[in] size Length to be erased + \return Error code +*/ +csi_error_t csi_spiflash_erase(csi_spiflash_t *spiflash, uint32_t offset, uint32_t size); + +/** + \brief Read flash status register + \param[in] spiflash SPIFLASH handle to operate + \param[in] cmd_code Cmd code + \param[out] data Data buf to save flash status register + \param[in] size Register length in byte + \return Error code +*/ +csi_error_t csi_spiflash_read_reg(csi_spiflash_t *spiflash, uint8_t cmd_code, uint8_t *data, uint32_t size); + +/** + \brief Write status register + \param[in] spiflash SPIFLASH handle to operate + \param[in] cmd Cmd code + \param[out] data Data buf to save flash status register + \param[in] size Register length in byte + \return Error code +*/ +csi_error_t csi_spiflash_write_reg(csi_spiflash_t *spiflash, uint8_t cmd_code, uint8_t *data, uint32_t size); + + +/** + \brief Enable spiflash write protection + \param[in] spiflash SPIFLASH handle to operate + \param[in] offset Protect flash offset,offset need protect block size aligned + \param[in] size Lock size(byte) + \return Error code +*/ +csi_error_t csi_spiflash_lock(csi_spiflash_t *spiflash, uint32_t offset, uint32_t size); + +/** + \brief Enable spiflash write protection + \param[in] spiflash SPIFLASH handle to operate + \param[in] offset Protect flash offset,offset need protect block size aligned + \param[in] size Unlock size(byte) + \return Error code +*/ +csi_error_t csi_spiflash_unlock(csi_spiflash_t *spiflash, uint32_t offset, uint32_t size); + +/** + \brief check flash is locked(write protect) + \param[in] spiflash SPIFLASH handle to operate + \param[in] offset Protect flash offset,offset need protect block size aligned + \param[in] size Locked size(byte) + \return 0:unlocked if query region overlay with locked region 1: locked if query reigon is fully in locked region +*/ +int csi_spiflash_is_locked(csi_spiflash_t *spiflash, uint32_t offset, uint32_t size); + +/** + \brief Set QSPI data line + \param[in] spiflash SPIFLASH handle to operate + \param[in] line SPIFLASH data line mode + \return Error code +*/ +csi_error_t csi_spiflash_config_data_line(csi_spiflash_t *spiflash, csi_spiflash_data_line_t line); + +/** + \brief Set QSPI frequence + \param[in] spiflash SPIFLASH handle to operate + \param[in] hz SPIFLASH frequence + \return The actual config frequency +*/ +uint32_t csi_spiflash_frequence(csi_spiflash_t *spiflash, uint32_t hz); + +/** + \brief Flash power down. + \param[in] spiflash SPIFLASH handle to operate. + \return error code +*/ +csi_error_t csi_spiflash_release_power_down(csi_spiflash_t *spiflash); + +/** + \brief Flash power release. + \param[in] spiflash SPIFLASH handle to operate. + \return none +*/ +void csi_spiflash_power_down(csi_spiflash_t *spiflash); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_SPIFLASH_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/spinand.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/spinand.h new file mode 100644 index 00000000..8a011987 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/spinand.h @@ -0,0 +1,321 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file spinand.h + * @brief header file for spinand driver + * @version V1.0 + * @date 17. Aug 2017 + * @model spinand + ******************************************************************************/ +#ifndef _DRV_NANDFLASH_H_ +#define _DRV_NANDFLASH_H_ + + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SPINAND_DEF_SPEED (1000000) +#define SPIANND_DEF_MAX_WAIT_TIME (1000) ///< max wait time in ms + +typedef union { + csi_qspi_t qspi; ///< hold qspi object +} csi_nand_spi_qspi_t; + + +typedef struct { +uint32_t target; ///< target in chip +uint32_t lun; ///< lun in target +uint32_t plane; ///< plane number in lun +uint32_t block; ///< block index in lun +uint32_t page; ///< page index in lun +uint32_t offset; ///< column offset within page +}csi_nand_pos_t; + +typedef enum{ + SPI_MEM_NODATA, ///< no data portion + SPI_MEM_DATA_IN, ///< read data + SPI_MEM_DATA_OUT ///< write data +}csi_spi_mem_dir_t; + +typedef struct{ + + struct{ + uint8_t buswidth; ///< cmd buswidth + uint8_t opcode; ///< cmd code + }cmd; + + struct { + uint8_t buswidth; ///< addr buswidth + uint8_t nbytes; ///< bytes of addr + uint64_t val; ///< addr value + }addr; + + struct { + uint8_t nbytes; ///< dummy bytes + uint8_t buswidth; ///< bus width + }dummy; + + + struct { + uint8_t buswidth; ///< data buswidth + uint32_t nbytes; ///< data len + csi_spi_mem_dir_t dir; ///< data xfer dir + union{ + void* in; ///< read data buf ptr + void* out; ///< write datat buf ptr + }buf; + }data; + +}spi_mem_op_t; + +typedef struct { + const uint8_t *id; ///< point to chip id array + const uint8_t len; ///< id length +}csi_spinand_id_t; + +typedef struct { + uint8_t id[4]; ///< id data + uint8_t len; ///< id length +}csi_nand_id_t; + + +typedef struct{ + uint16_t strength; ///< number of hw-ecc engine bits + uint16_t step_size; ///< corect size by ecc per-step +}csi_nand_ecc_req_t; + +typedef struct { + uint32_t bits_per_cell; ///< bit per-cell + uint32_t pagesize; ///< page size + uint32_t oobsize; ///< spare area size + uint32_t pages_per_eraseblock; ///< pages per block + uint32_t eraseblocks_per_lun; ///< blocks per lun(logic unit number== max block index ) + uint32_t max_bad_eraseblocks_per_lun; ///< max bad blocks per lun + uint32_t planes_per_lun; ///< planes per-lun + uint32_t luns_per_target; ///< luns per die + uint32_t ntargets; ///< target index +}csi_nand_mem_layout_t; + + + +typedef struct { + char *model; ///< chip name of vendor + uint32_t flags; ///< chip-specific feature bits group + csi_spinand_id_t devid; ///< devid of chip + csi_nand_mem_layout_t memorg; ///< mem layout of chip + csi_nand_ecc_req_t eccreq; ///< ecc capabilty of chip + csi_error_t (*select_target)(void *spinand, uint32_t target); ///< select target + csi_error_t (*check_ecc_status)(void *spinand,uint8_t status); ///< check vendor specific ecc status +}csi_spinand_info_t; + + +typedef struct { + csi_error_t (*init) (void *spinand); ///< vendor chip inition + void (*uninit) (void *spinand); ///< vendor chip uninition +}csi_spinand_manufacturer_ops_t; + +typedef struct { + uint8_t id; ///< vendor id + char *name; ///< vendor name + const csi_spinand_info_t *chips; ///< vendor chip param + uint32_t nchips; ///< chips number supported + const csi_spinand_manufacturer_ops_t *ops; ///< vendor specific operations +}csi_spinand_manufacturer_t; + + +typedef struct { + char *model_name; ///< name of nand-device module + uint16_t page_size; ///< page-size of nand-device + uint16_t oob_size; ///< oob-size(spare size) of nand-device + uint16_t pages_per_block; ///< pages-per-block + uint16_t max_bad_blocks; ///< max possible bad blocks of nand-device + uint32_t total_blocks; ///< total blocks of nand-device +}csi_spinand_dev_params_t; + +typedef struct +{ + void *xfer_buf; ///< point to xfer data buf + uint32_t xfer_buf_len; ///< length of xfer buf ,count in byte + uint16_t rxfer_copy_offset; ///< copy offset from word-aligned buf + uint16_t rxfer_origin_len; ///< copy length from word-aligned buf +}csi_xfer_data_buf_t; + + +/** +\brief Flash control block +*/ +typedef struct { + #define SPINAND_SCRAT_BUF_LEN 4 ///< scratch buf len + csi_nand_spi_qspi_t spi_qspi; ///< Spi/qspi handle + uint8_t scractbuf[SPINAND_SCRAT_BUF_LEN]; ///< scracthbuf for read/write id or reg + uint8_t cur_target; ///< current target + uint16_t max_tx_size; ///< max tx op size + uint16_t max_rx_size; ///< max rx op size + csi_xfer_data_buf_t xfer; ///< xfer buf + csi_spinand_info_t *chip_info; ///< Point to vendor private feature struct + csi_spinand_manufacturer_t *maf; ///< point to manufacture + void (*spi_cs_callback)(csi_gpio_pin_state_t value); ///< gpio chip select for spi or qspi + csi_error_t (*spi_mem)(void *spinand,spi_mem_op_t *op); ///< spi-mem op function + void *priv; ///< User private param +} csi_spinand_t; + +typedef enum { + XFER_CPU_POLLING, ///< transfer by qspi with cpu polling mode + XFER_DMA, ///< transfer by qspi with external dma engine + XFER_INTR, ///< transfer by qspi with cpu-interrut +}csi_spinand_xfer_t; + +/** + \brief Initialize NANDFLASH with qspi controler and probe flash device + \param[in] spinand NANDFLASH handle + \param[in] qspi_idx QSPI controler index + \param[in] spi_cs_callback GPIO info for chip select,if NULL, not use gpio cs + \return Error code +*/ +csi_error_t csi_spinand_qspi_init(csi_spinand_t *spinand, uint32_t qspi_idx,void *gpio_cs_callback); + +/** + \brief De-initialize NANDFLASH Interface based on spi controler. stops operation and releases the software resources used by the interface + \param[in] spinand NANDFLASH handle to operate + \return Error code +*/ +void csi_spinand_qspi_uninit(csi_spinand_t *spinand); + +/** + \brief set xfer mode + \param[in] spinand NANDFLASH handle to operate + \param[in] xfer_mode please ref csi_spinand_xfer_t + \return Error code +*/ +csi_error_t csi_spinand_set_xfer_mode(csi_spinand_t *spinand,csi_spinand_xfer_t xfer_mode); + + +/** + \brief get flash device infomation + \param[in] spinand NANDFLASH handle to operate + \param[in] flash_info User storage to get flash vendor info after flash init + \return spinand_info_t +*/ + +csi_error_t csi_spinand_get_flash_info(csi_spinand_t *spinand, csi_spinand_dev_params_t *flash_info); + +/** + \brief Read data from Flash + \param[in] spinand NANDFLASH handle to operate + \param[in] offset Data address, offset address relative to zero + \param[out] data Pointer to a buffer storing the data read from Flash + \param[in] cnt Number of data items to read + \return If receive successful, this function shall return the num of data witch is received successfulful + otherwise, the function shall return Error code +*/ +int32_t csi_spinand_read(csi_spinand_t *spinand, uint64_t offset, void *data, uint32_t size); + + +/** + \brief Read spare data from specific page + \param[in] spinand NANDFLASH handle to operate + \param[in] page_addr page addr, address relative to zero, addr need page size aligned + \param[in] spare_offset offset address within the spare area of the page + \param[out] data Pointer to a buffer storing the data read from Flash + \param[in] size Number of data items to read + \return If receive successful, this function shall return the num of data witch is received successfully + otherwise, the function shall return Error code +*/ +int32_t csi_spinand_read_spare_data(csi_spinand_t *spinand,uint64_t page_addr,uint32_t spare_offset,void *data, uint32_t size); + +/** + \brief write data to Flash + \param[in] spinand NANDFLASH handle to operate + \param[in] offset Data address, offset address relative to zero + \param[in] data Pointer to a buffer containing the data to be programmed to Flash. + \param[in] size Number of data items to program + \return If program successful, this function shall return the num of data witch is programed successfully + otherwise, the function shall return Error code +*/ +int32_t csi_spinand_write(csi_spinand_t *spinand, uint64_t offset, const void *data, uint64_t size); + +/** + \brief write spare data to specific page + \param[in] spinand NANDFLASH handle to operate + \param[in] page_addr page addr, address relative to zero, addr need page size aligned + \param[in] spare_offset offset address within the spare area of the page + \param[out] data Pointer to a buffer storing the data write to Flash + \param[in] size Number of data items to write + \return If program successful, this function shall return the num of data witch is programed successfully + otherwise, the function shall return Error code +*/ +int32_t csi_spinand_write_spare_data(csi_spinand_t *spinand,uint64_t page_addr,uint32_t spare_offset,void *data, uint32_t size); + + +/** + \brief Erase Flash Sector + \param[in] spinand NANDFLASH handle to operate + \param[in] offset Data address, offset address relative to zero + \param[in] size Length to be erased + \param[out] last erased block addr + \return Error code +*/ +csi_error_t csi_spinand_erase(csi_spinand_t *spinand, uint64_t offset, uint64_t size, uint64_t *last_fail_addr); + +/** + \brief check whether the block is bad + \param[in] spinand NANDFLASH handle to operate + \param[in] block_addr block addr (count in bytes) + \return 1: bad 0: not bad <0 err code +*/ + + +int32_t csi_spinand_block_is_bad(csi_spinand_t *spinand,uint64_t block_addr); + +/** + \brief mark block as a bad block + \param[in] spinand NANDFLASH handle to operate + \param[in] block_addr block addr (count in bytes) + \return Error code +*/ +csi_error_t csi_spinand_block_mark_bad(csi_spinand_t *spinand, uint64_t block_addr); + +/** + \brief reset spinand device + \param[in] spinand NANDFLASH handle to operate + \return Error code +*/ +int32_t csi_spinand_reset(csi_spinand_t *spinand); + +/** + \brief Set QSPI frequence + \param[in] spinand NANDFLASH handle to operate + \param[in] hz NANDFLASH frequence + \return The actual config frequency +*/ +uint32_t csi_spinand_frequence(csi_spinand_t *spinand, uint32_t hz); + + + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_NANDFLASH_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/tee.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/tee.h new file mode 100755 index 00000000..dc85c7b9 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/tee.h @@ -0,0 +1,643 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +/****************************************************************************** + * @file drv/tee.h + * @brief Header File for TEE Driver + * @version V1.0 + * @date 12 Sep 2020 + * @model tee + ******************************************************************************/ +#ifndef _DRV_TEE_H_ +#define _DRV_TEE_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif +/****** TEE AES mode *****/ +typedef enum { + TEE_AES_MODE_ECB = 0, ///< TEE AES ECB mode + TEE_AES_MODE_CBC = 1, ///< TEE AES CBC mode + TEE_AES_MODE_MAX, ///< invaild mode +} +tee_aes_mode_e; + +/** + \brief TEE AES encrypt + \note Length should be a multiple of the block size (16 bytes) + After calling this function, the content of iv is updated. + \param[in] in Pointer to plaintext buffer + \param[in] in_len Plaintext buffer length + \param[in] key Pointer to secret key + \param[in] key_len Secret key size,must be 16 bytes for AES128,24 bytes for AES192 or 32byes for AES256 + \param[out] out Pointer to ciphertext buffer + \param[in] mode \ref tee_aes_mode_e + \return Return 0 if successful,otherwise error code +*/ +int32_t csi_tee_aes_encrypt(const uint8_t *in, uint32_t in_len, + const uint8_t *key, uint32_t key_len, + uint8_t iv[16], + uint8_t *out, + tee_aes_mode_e mode); + +/** + \brief TEE AES decrypt + \note Length should be a multiple of the block size (16 bytes) + After calling this function, the content of iv is updated. + \param[in] in Pointer to ciphertext buffer + \param[in] in_len Ciphertext buffer length + \param[in] key Pointer to secret key + \param[in] key_len Secret key size,must be 16 bytes for AES128,24 bytes for AES192 or 32byes for AES256 + \param[out] out Pointer to plaintext buffer + \param[in] mode \ref tee_aes_mode_e + \return Return 0 if successful,otherwise error code +*/ +int32_t csi_tee_aes_decrypt(const uint8_t *in, uint32_t in_len, + const uint8_t *key, uint32_t key_len, + uint8_t iv[16], + uint8_t *out, + uint32_t mode); + +/** + \brief TEE AES ECB encrypt + \note Length should be a multiple of the block size (16 bytes) + After calling this function, the content of iv is updated. + \param[in] in Pointer to plaintext buffer + \param[in] in_len Plaintext buffer length + \param[in] key Pointer to secret key + \param[in] key_len Secret key size,must be 16 bytes for AES128,24 bytes for AES192 or 32byes for AES256 + \param[out] out Pointer to ciphertext buffer + \return Return 0 if successful,otherwise error code +*/ +#define csi_tee_aes_encrypt_ecb(in, in_len, key, key_len, out) \ + csi_tee_aes_encrypt(in, in_len, key, key_len, NULL, out, TEE_AES_MODE_ECB) + +/** + \brief TEE AES ECB decrypt + \note Length should be a multiple of the block size (16 bytes) + After calling this function, the content of iv is updated. + \param[in] in Pointer to ciphertext buffer + \param[in] in_len Ciphertext buffer length + \param[in] key Pointer to secret key + \param[in] key_len Secret key size,must be 16 bytes for AES128,24 bytes for AES192 or 32byes for AES256 + \param[out] out Pointer to plaintext buffer + \return Return 0 if successful,otherwise error code +*/ +#define csi_tee_aes_decrypt_ecb(in, in_len, key, key_len, out) \ + csi_tee_aes_decrypt(in, in_len, key, key_len, NULL, out, TEE_AES_MODE_ECB) + +/** + \brief TEE AES CBC encrypt + \note Length should be a multiple of the block size (16 bytes) + After calling this function, the content of iv is updated. + \param[in] in Pointer to ciphertext buffer + \param[in] in_len Ciphertext buffer length + \param[in] key Pointer to secret key + \param[in] key_len Secret key size,must be 16 bytes for AES128,24 bytes for AES192 or 32byes for AES256 + \param[out] out Pointer to plaintext buffer + \return Return 0 if successful,otherwise error code +*/ +#define csi_tee_aes_encrypt_cbc(in, in_len, key, key_len, iv, out) \ + csi_tee_aes_encrypt(in, in_len, key, key_len, iv, out, TEE_AES_MODE_CBC) + +/** + \brief TEE AES CBC decrypt + \note Length should be a multiple of the block size (16 bytes) + After calling this function, the content of iv is updated. + \param[in] in Pointer to ciphertext buffer + \param[in] in_len Ciphertext buffer length + \param[in] key Pointer to secret key + \param[in] key_len Secret key size,must be 16 bytes for AES128,24 bytes for AES192 or 32byes for AES256 + \param[out] out Pointer to plaintext buffer + \return Return 0 if successful,otherwise error code +*/ +#define csi_tee_aes_decrypt_cbc(in, in_len, key, key_len, iv, out) \ + csi_tee_aes_decrypt(in, in_len, key, key_len, iv, out, TEE_AES_MODE_CBC) + +/** + \brief TEE BASE64 encode/decode + \param[in] in Pointer to input data buffer + \param[in] in_len Input data buffer length + \param[out] out Pointer to output data buffer + \param[out] out_len Output data buffer length + \param[in] is_encode 1 encode 0 decode + \param[in] wsafe Base64 websafe feature,set 1, replace "+/" with "-_" + \return Return 0 if successful,otherwise error code +*/ +int32_t csi_tee_base64(const uint8_t *in, uint32_t in_len, + uint8_t *out, uint32_t *out_len, + uint32_t is_encode, + uint32_t wsafe); + +/** + \brief TEE BASE64 encode + \param[in] in Pointer to input data buffer + \param[in] in_len Input data buffer length + \param[out] out Pointer to output data buffer + \param[out] out_len Output data buffer length + \return Return 0 if successful,otherwise error code +*/ +#define csi_tee_base64_encode(in,in_len,out,out_len) \ + csi_tee_base64(in,in_len,out,out_len,1,0) + +/** + \brief TEE BASE64 decode + \param[in] in Pointer to input data buffer + \param[in] in_len Input data buffer length + \param[out] out Pointer to output data buffer + \param[out] out_len Output data buffer length + \return Return 0 if successful,otherwise error code +*/ +#define csi_tee_base64_decode(in,in_len,out,out_len) \ + csi_tee_base64(in,in_len,out,out_len,0,0) + +/** + \brief TEE BASE64 web safe encode + \param[in] in Pointer to input data buffer + \param[in] in_len Input data buffer length + \param[out] out Pointer to output data buffer + \param[out] out_len Output data buffer length + \return Return 0 if successful,otherwise error code +*/ +#define csi_tee_base64_websafe_encode(in,in_len,out,out_len) \ + csi_tee_base64(in,in_len,out,out_len,1,1) + +/** + \brief TEE BASE64 web safe decode + \param[in] in Pointer to input data buffer + \param[in] in_len Input data buffer length + \param[out] out Pointer to output data buffer + \param[out] out_len Output data buffer length + \return Return 0 if successful,otherwise error code +*/ +#define csi_tee_base64_websafe_decode(in,in_len,out,out_len) \ + csi_tee_base64(in,in_len,out,out_len,0,1) + +/** + \brief TEE obtain CID from Key Provisioning + \param[out] out Pointer to cid buffer + \param[out] out_len CID buffer length,if cid obtain successfully, + out_len is updated to actual cid sizes + \return Return 0 if successful,otherwise error code +*/ +int32_t csi_tee_get_cid(uint8_t *out, uint32_t *out_len); + +/****** lpm mode *****/ +typedef enum { + TEE_LPM_MODE_WAIT = 0, ///< lpm wait + TEE_LPM_MODE_DOZE = 1, ///< lpm doze + TEE_LPM_MODE_STOP = 2, ///< lpm stop + TEE_LPM_MODE_STANDBY = 3, ///< lpm standby + TEE_LPM_MODE_CLOCK = 4, ///< lpm clock gate + TEE_LPM_MODE_MAX, +} tee_lpm_mode_e; + +/** + \brief TEE set low power mode + \param[in] gate Not use for now + \param[in] irqid Not use for now + \param[in] mode \ref tee_lpm_mode_e + \return Return 0 if successful,otherwise error code +*/ +int32_t csi_tee_enter_lpm(uint32_t gate, uint32_t irqid, tee_lpm_mode_e mode); + +/** + \brief TEE obtain manifest info from manifest table + \note call csi_tee_get_sys_img_info, csi_tee_get_sys_os_version or csi_tee_get_sys_partition is better + \param[out] out Pointer to info buffer + \param[out] out_len Info buffer length,if info obtain successfully, + out_len is updated to actual sizes + \param[in] name info name + \return Return 0 if successful,otherwise error code +*/ +int32_t csi_tee_get_manifest_info(uint8_t *out, uint32_t *out_len, char *name); + +/** + \brief TEE obtain image buffer from manifest table + \param[out] out Pointer to image buffer + \param[out] out_len Image buffer length,if info obtain successfully, + out_len is updated to actual image buffer sizes + \param[in] img_name Image name + \return Return 0 if successful,otherwise error code +*/ +#define csi_tee_get_sys_img_info(out,out_len,img_name) \ + csi_tee_get_manifest_info(out,out_len,img_name) + +/** + \brief TEE obtain os version from manifest table + \param[out] out Pointer to os version buffer + \param[out] out_len OS version buffer length,if info obtain successfully, + out_len is updated to actual os version buffer sizes + \return Return 0 if successful,otherwise error code +*/ +#define csi_tee_get_sys_os_version(out,out_len) \ + csi_tee_get_manifest_info(out,out_len,"os_v") + +/** + \brief TEE obtain partition buffer from manifest table + \param[out] out Pointer to partition buffer + \param[out] out_len Partition buffer length,if info obtain successfully, + out_len is updated to actual partition buffer sizes + \return Return 0 if successful,otherwise error code +*/ +#define csi_tee_get_sys_partition(out,out_len) \ + csi_tee_get_manifest_info(out,out_len,"sys_p") + +/** + \brief TEE set random seed + \param[in] Seed random sedd + \return Return 0 if successful,otherwise error code +*/ +int32_t csi_tee_rand_seed(uint32_t seed); + +/** + \brief TEE ramdom date generation + \param[out] out Pointer to random data buffer + \param[in] out_len Data buffer length + \return Return 0 if successful,otherwise error code +*/ +int32_t csi_tee_rand_generate(uint8_t *out, uint32_t out_len); + +/****** TEE RSA sign type *****/ +typedef enum { + TEE_RSA_MD5 = 0, ///< MD5 + TEE_RSA_SHA1 = 1, ///< SHA1 + TEE_RSA_SHA256 = 3, ///< SHA256 + TEE_RSA_SIGN_TYPE_MAX, ///< invailed type +} tee_rsa_sign_type_e; + +/** + \brief TEE RSA sign with private key + \param[in] in Pointer to digest buffer + \param[in] in_len Digest buffer length + \param[in] key Pointer to private key,key contains n, e, d + \param[in] key_len Private key size,must be 128*3 = 384 bytes for RSA1024, 256*3 = 768 bytes for RSA2048 + \param[out] sign Pointer to sign buffer + \param[out] sign_len Sign buffer length + \param[in] type \ref tee_rsa_sign_type_e + \return Return 0 if successful,otherwise error code +*/ +int32_t csi_tee_rsa_sign(const uint8_t *in, uint32_t in_len, + const uint8_t *key, uint32_t key_len, + uint8_t *sign, uint32_t *sign_len, + tee_rsa_sign_type_e type); + +/** + \brief TEE RSA verify with public key + \param[in] in Pointer to digest buffer + \param[in] in_len Digest buffer length + \param[in] key Pointer to public key,key contains n, e + \param[in] key_len Public key size,must be 128*2 = 256 bytes for RSA1024, 256*2 = 512 bytes for RSA2048 + \param[in] sign Pointer to sign buffer + \param[in] sign_len Sign buffer length + \param[in] type \ref tee_rsa_sign_type_e + \return Return 0 if verify successful,otherwise error code +*/ +int32_t csi_tee_rsa_verify(const uint8_t *in, uint32_t in_len, + const uint8_t *key, uint32_t key_len, + uint8_t *sign, uint32_t sign_len, + tee_rsa_sign_type_e type); + +/****** TEE RSA padding mode *****/ +typedef enum { + TEE_RSA_PKCS1_PADDING = 0x01, ///< RSA PKCS padding mode + TEE_RSA_NO_PADDING = 0x02, ///< RSA no padding mode +} tee_rsa_padding_mode_e; + +/** + \brief TEE RSA encrypt with public key + \param[in] in Pointer to plaintext buffer + \param[in] in_len Plaintext buffer length + \param[in] key Pointer to public key,key contains n, e + \param[in] key_len Public key size, must be 128*2 = 256 bytes for RSA1024, 256*2 = 512 bytes for RSA2048 + \param[in] out Pointer to ciphertext buffer + \param[in] out_len Ciphertext buffer length + \param[in] padding \ref tee_rsa_padding_mode_e + \return Return 0 if successful,otherwise error code +*/ +int32_t csi_tee_rsa_encrypt(const uint8_t *in, uint32_t in_len, + const uint8_t *key, uint32_t key_len, + uint8_t *out, uint32_t *out_len, + tee_rsa_padding_mode_e padding); +/** + \brief TEE RSA decrypt with private key + \param[in] in Pointer to ciphertext buffer + \param[in] in_len Ciphertext buffer length + \param[in] key Pointer to private key,key contains n, e, d + \param[in] key_len Private key size,must be 128*3 = 384 bytes for RSA1024, 256*3 = 768 bytes for RSA2048 + \param[in] out Pointer to plaintext buffer + \param[in] out_len Plaintext buffer length + \param[in] padding \ref tee_rsa_padding_mode_e + \return Return 0 if successful,otherwise error code +*/ +int32_t csi_tee_rsa_decrypt(const uint8_t *in, uint32_t in_len, + const uint8_t *key, uint32_t key_len, + uint8_t *out, uint32_t *out_len, + tee_rsa_padding_mode_e padding); + +/** + \brief TEE RSA sign with internal private key + \note Only use if key provisioning exist + \param[in] in Pointer to digest buffer + \param[in] in_len Digest buffer length + \param[out] sign Pointer to sign buffer + \param[out] sign_len Sign buffer length + \param[in] type \ref tee_rsa_sign_type_e + \return Return 0 if successful,otherwise error code +*/ +#define csi_tee_cid_rsa_sign(in,in_len,sign,sign_len,type) \ + csi_tee_rsa_sign(in,in_len,NULL,0,sign,sign_len,type) + +/** + \brief TEE RSA verify with internal public key + \note Only use if key provisioning exist + \param[in] in Pointer to digest buffer + \param[in] in_len Digest buffer length + \param[in] sign Pointer to sign buffer + \param[in] sign_len Sign buffer length + \param[in] type \ref tee_rsa_sign_type_e + \return Return 0 if verify successful,otherwise error code +*/ +#define csi_tee_cid_rsa_verify(in,in_len,sign,sign_len,type) \ + csi_tee_rsa_verify(in,in_len,NULL,0,sign,sign_len,type) + +/** + \brief TEE RSA encrypt with internal public key + \note Only use if key provisioning exist + \param[in] in Pointer to plaintext buffer + \param[in] in_len Plaintext buffer length + \param[in] out Pointer to ciphertext buffer + \param[in] out_len Ciphertext buffer length + \param[in] padding \ref tee_rsa_padding_mode_e + \return Return 0 if successful,otherwise error code +*/ +#define csi_tee_cid_rsa_encrypt(in,in_len,out,out_len,padding) \ + csi_tee_rsa_encrypt(in,in_len,NULL,0,out,out_len,padding) + +/** + \brief TEE RSA decrypt with internal private key + \note Only use if key provisioning exist + \param[in] in Pointer to ciphertext buffer + \param[in] in_len Ciphertext buffer length + \param[in] key Pointer to private key,key contains n, e, d + \param[in] key_len Private key size,must be 128*3 = 384 bytes for RSA1024, 256*3 = 768 bytes for RSA2048 + \param[in] out Pointer to plaintext buffer + \param[in] out_len Plaintext buffer length + \param[in] padding \ref tee_rsa_padding_mode_e + \return Return 0 if successful,otherwise error code +*/ +#define csi_tee_cid_rsa_decrypt(in,in_len,out,out_len,padding) \ + csi_tee_rsa_decrypt(in,in_len,NULL,0,out,out_len,padding) + +/** + \brief verify boot image with boot public key + \note Only use if key provisioning exist + \param[in] in Pointer to digest buffer + \param[in] in_len Digest buffer length + \param[in] sign Pointer to sign buffer + \param[in] sign_len Sign buffer length + \param[in] type \ref tee_rsa_sign_type_e + \return Return 0 if verify successful,otherwise error code +*/ +int32_t csi_tee_img_rsa_verify(const uint8_t *in, uint32_t in_len, + uint8_t *sign, uint32_t sign_len, + tee_rsa_sign_type_e type); + +/****** TEE HASH operation mode *****/ +typedef enum { + TEE_HASH_OP_NONE = 0, ///< No operation + TEE_HASH_OP_START = 1, ///< HASH init + TEE_HASH_OP_UPDATA = 2, ///< HASH update + TEE_HASH_OP_FINISH = 3, ///< HASH finish + TEE_HASH_OP_MAX, ///< invailed operation +} tee_hash_op_e; + +/****** TEE HMAC type *****/ +typedef enum { + TEE_HMAC_SHA1 = 1, ///< HMAC with SHA1 +} tee_hmac_type_e; + +/** + \brief TEE HAMC + \note Call csi_tee_hmac_digest is better + out buffer size must be large enough according to type, eg. 20 bytes for TEE_HMAC_SHA1 + \param[in] in Pointer to input data buffer + \param[in] in_len Input data buffer length + \param[in] key Pointer to key buffer + \param[in] key_len Key buffer size + \param[out] out Pointer to output date buffer + \param[in] type \ref tee_hmac_type_e + \param[in] hash_op \ref tee_hash_op_e + \param[in] ctx Pointer to context of hmac + \return Return 0 if successful,otherwise error code +*/ +int32_t csi_tee_hmac(const uint8_t *in, uint32_t in_len, + const uint8_t *key, uint32_t key_len, + uint8_t *out, + tee_hmac_type_e type, + tee_hash_op_e hash_op, + uint32_t *ctx); + +/** + \brief TEE HAMC digest + \note out buffer size must be large enough according to type, eg. 20 bytes for TEE_HMAC_SHA1 + \param[in] in Pointer to input data buffer + \param[in] in_len Input data buffer length + \param[in] key Pointer to key buffer + \param[in] key_len Key buffer size + \param[out] out Pointer to output date buffer + \param[in] type \ref tee_hmac_type_e + \return Return 0 if successful,otherwise error code +*/ +#define csi_tee_hmac_digest(in,in_len,key,key_len,out,type) \ + csi_tee_hmac(in,in_len,key,key_len,out,type,TEE_HASH_OP_NONE,NULL) + +/****** TEE SHA type *****/ +typedef enum { + TEE_SHA1 = 0, ///< SHA1 + TEE_SHA256 = 1, ///< SHA256 + TEE_SHA224 = 2, ///< SHA224 + TEE_SHA384 = 3, ///< SHA384 + TEE_SHA512 = 4, ///< SHA512 + TEE_SHA_MAX, ///< invaild sha type +} tee_sha_type_t; + +/** + \brief TEE SHA + \note Call csi_tee_sha_digest, csi_tee_sha_start, csi_tee_sha_update or csi_tee_sha_finish is better + out buffer size must be large enough according to type, eg. 20 bytes for TEE_SHA1, 32 bytes for TEE_SHA256 + \param[in] in Pointer to input data buffer + \param[in] in_len Input data buffer length + \param[out] out Pointer to output date buffer + \param[in] type \ref tee_sha_type_t + \param[in] hash_op \ref tee_hash_op_e + \param[in] ctx Pointer to context of sha + \return Return 0 if successful,otherwise error code +*/ +int32_t csi_tee_sha(const uint8_t *in, uint32_t in_len, + uint8_t *out, + tee_sha_type_t type, + tee_hash_op_e hash_op, + void *ctx); + +/** + \brief TEE SHA digest + \note out buffer size must be large enough according to type, eg. 20 bytes for TEE_SHA1, 32 bytes for TEE_SHA256 + \param[in] in Pointer to input data buffer + \param[in] in_len Input data buffer length + \param[out] out Pointer to output date buffer + \param[in] type \ref tee_sha_type_t + \return Return 0 if successful,otherwise error code +*/ +#define csi_tee_sha_digest(in,in_len,out,type) \ + csi_tee_sha(in,in_len,out,type,TEE_HASH_OP_NONE,NULL); + +/** + \brief TEE SHA start, initial sha + \param[in] type \ref tee_sha_type_t + \param[in] ctx Pointer to context of sha + \return Return 0 if successful,otherwise error code +*/ +#define csi_tee_sha_start(type,ctx) \ + csi_tee_sha(NULL,0,NULL,type,TEE_HASH_OP_START,ctx); + +/** + \brief TEE SHA update, update data + \param[in] in Pointer to input data buffer + \param[in] in_len Input data buffer length + \param[in] ctx Pointer to context of sha + \return Return 0 if successful,otherwise error code +*/ +#define csi_tee_sha_update(in,in_len,ctx) \ + csi_tee_sha(in,in_len,NULL,0,TEE_HASH_OP_UPDATA,ctx); + +/** + \brief TEE SHA digest, get sha digest + \note out buffer size must be large enough according to type, eg. 20 bytes for TEE_SHA1, 32 bytes for TEE_SHA256 + \param[out] out Pointer to output date buffer + \param[in] ctx Pointer to context of sha + \return Return 0 if successful,otherwise error code +*/ +#define csi_tee_sha_finish(out,ctx) \ + csi_tee_sha(NULL,0,out,0,TEE_HASH_OP_FINISH,ctx); + +/** + \brief TEE get device name and product key + \param[in] name_encrypted Pointer to device name ciphertext + \param[in] name_encrypted_len device name ciphertext length + \param[in] product_key_encrypted Pointer to device product key ciphertext + \param[in] product_key_encrypted_len Device product key ciphertext length + \param[out] name Pointer to device name + \param[out] name_len Device name length + \param[out] product_key Pointer to device product key + \param[out] product_key_len Device product key length + \return Return 0 if successful,otherwise error code +*/ +int32_t csi_tee_dev_info_get(const uint8_t *name_encrypted, uint32_t name_encrypted_len, + const uint8_t *product_key_encrypted, uint32_t product_key_encrypted_len, + const uint8_t *name, uint32_t *name_len, + const uint8_t *product_key, uint32_t *product_key_len); + +/** + \brief TEE device info sign + \param[in] in Pointer to input date buffer + \param[in] in_len Input data buffer length + \param[in] device_secret Pointer to device secret ciphertext + \param[in] device_secret_len Device secret ciphertext length + \param[out] sign Pointer to signed buffer + \param[out] sign_len Signed buffer length + \return Return 0 if successful,otherwise error code +*/ +int32_t csi_tee_dev_info_sign(const uint8_t *in, uint32_t in_len, + const uint8_t *device_secret, uint32_t device_secret_len, + const uint8_t *sign, uint32_t *sign_len); + +/** + \brief TEE device info encrypt/decrypt + \param[in] in Pointer to input date buffer + \param[in] in_len Input data buffer length + \param[in] out Pointer to output date buffer + \param[in] out_len Onput data buffer length + \param[in] is_enc 1 incrypt 0 decrypt + \return Return 0 if successful,otherwise error code +*/ +int32_t csi_tee_dev_info_crypt(const uint8_t *in, uint32_t in_len, + uint8_t *out, uint32_t *out_len, + uint8_t is_enc); + +/** + \brief TEE device info encrypt + \param[in] in Pointer to input date buffer + \param[in] in_len Input data buffer length + \param[in] out Pointer to output date buffer + \param[in] out_len Onput data buffer length + \return Return 0 if successful,otherwise error code +*/ +#define csi_tee_dev_info_encrypt(in, in_len, out, out_len) \ + csi_tee_dev_info_crypt(in, in_len, out, out_len, 1) + +/** + \brief TEE device info decrypt + \param[in] in Pointer to input date buffer + \param[in] in_len Input data buffer length + \param[in] out Pointer to output date buffer + \param[in] out_len Onput data buffer length + \return Return 0 if successful,otherwise error code +*/ +#define csi_tee_dev_info_decrypt(in, in_len, out, out_len) \ + csi_tee_dev_info_crypt(in, in_len, out, out_len, 0) + +/** + \brief Set system frequence + \param[in] clk_src Indicate clock source type + \param[in] clk_val System freqence to be set + \return Return 0 if successful,otherwise error code +*/ +int32_t csi_tee_set_sys_freq(uint32_t clk_src, uint32_t clk_val); + +/** + \brief Get system frequence + \param[in] clk_val Value address to store system freqence + \return Return 0 if successful,otherwise error code +*/ +int32_t csi_tee_get_sys_freq(uint32_t *clk_val); + +/** + \brief Read system register + \param[in] addr Indicate register address + \param[out] val Value to read from the address + \return Return 0 if successful,otherwise error code +*/ +int32_t csi_tee_read_reg(uint32_t addr, uint32_t *val); + +/** + \brief Wrte system register + \param[in] addr Indicate register address + \param[in] val Value to be written into the address + \return Return 0 if successful,otherwise error code +*/ +int32_t csi_tee_write_reg(uint32_t addr, uint32_t val); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_TEE_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/tick.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/tick.h new file mode 100755 index 00000000..a5e0a3f1 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/tick.h @@ -0,0 +1,92 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file tick.h + * @brief Header File for TICK Driver + * @version V1.0 + * @date 28. Sep 2020 + ******************************************************************************/ + +#ifndef _DRV_TICK_H_ +#define _DRV_TICK_H_ + +#include +#include +#include + +#ifndef CONFIG_SYSTICK_HZ +#define CONFIG_SYSTICK_HZ 100U +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \brief Initializes the resources needed for the TICK interface + \return error code \ref csi_error_t +*/ +csi_error_t csi_tick_init(void); + +/** + \brief De-initialize TICK Interface +*/ +void csi_tick_uninit(void); + +/** + \brief Get the sys-tick, one tick == (1000 / CONFIG_SYSTICK_HZ) ms + \return the sys-tick +*/ +uint32_t csi_tick_get(void); + +/** + \brief Get the time which start from csi_tick_init + \return The time which start from csi_tick_init (ms) +*/ +uint32_t csi_tick_get_ms(void); + +/** + \brief Get the time which start from csi_tick_init + \return The time which start from csi_tick_init (us) +*/ +uint64_t csi_tick_get_us(void); + +/** + \brief Get the calendar time in microseconds + \return The absolute timestamp in microseconds since Unix epoch (1970-01-01 00:00:00 UTC) +*/ +uint64_t csi_get_calendar_us(void); + +/** + \brief Set the calendar time in microseconds + \param[in] timestamp The absolute timestamp in microseconds since Unix epoch (1970-01-01 00:00:00 UTC) + \return None +*/ +void csi_set_calendar_us(uint64_t timestamp); + +/** + \brief Increase the sys-tick +*/ +void csi_tick_increase(void); + +#ifdef __cplusplus +} +#endif + +#endif /*_DRV_TICK_H_*/ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/timer.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/timer.h new file mode 100755 index 00000000..9f1039c1 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/timer.h @@ -0,0 +1,132 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/timer.h + * @brief Header File for TIMER Driver + * @version V1.0 + * @date 9. Oct 2020 + * @model timer + ******************************************************************************/ + +#ifndef _DRV_TIMER_H_ +#define _DRV_TIMER_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct csi_timer csi_timer_t; + +struct csi_timer { + csi_dev_t dev; + void (*callback)(csi_timer_t *timer, void *arg); + void *arg; + void *priv; +}; + +/** + \brief Initialize TIMER interface. initializes the resources needed for the TIMER interface + \param[in] timer Handle to operate + \param[in] idx TIMER index + \return Error code \ref csi_error_t +*/ +csi_error_t csi_timer_init(csi_timer_t *timer, uint32_t idx); + +/** + \brief De-initialize TIMER interface. stops operation and releases the software resources used by the interface + \param[in] timer Handle to operate + \return None +*/ +void csi_timer_uninit(csi_timer_t *timer); + +/** + \brief Start TIMER + \param[in] timer Handle to operate + \param[in] timeout_us The timeout for TIMER + \return Error code \ref csi_error_t +*/ +csi_error_t csi_timer_start(csi_timer_t *timer, uint32_t timeout_us); + +/** + \brief Stop TIMER + \param[in] timer Handle to operate + \return None +*/ +void csi_timer_stop(csi_timer_t *timer); + +/** + \brief Get TIMER remaining value + \param[in] timer Handle to operate + \return remaining value +*/ +uint32_t csi_timer_get_remaining_value(csi_timer_t *timer); + +/** + \brief Get TIMER load value + \param[in] timer Handle to operate + \return Load value +*/ +uint32_t csi_timer_get_load_value(csi_timer_t *timer); + +/** + \brief Check TIMER is running + \param[in] timer Handle to operate + \return + true - TIMER is running + false - TIMER is stopped +*/ +bool csi_timer_is_running(csi_timer_t *timer); + +/** + \brief Attach the callback handler to TIMER + \param[in] timer Operate handle + \param[in] callback Callback function + \param[in] arg Callback's param + \return Error code \ref csi_error_t +*/ +csi_error_t csi_timer_attach_callback(csi_timer_t *timer, void *callback, void *arg); + +/** + \brief Detach the callback handler + \param[in] timer Operate handle + \return None +*/ +void csi_timer_detach_callback(csi_timer_t *timer); + +/** + \brief Enable TIMER power manage + \param[in] timer Handle to operate + \return Error code \ref csi_error_t +*/ +csi_error_t csi_timer_enable_pm(csi_timer_t *timer); + +/** + \brief Disable TIMER power manage + \param[in] timer Handle to operate + \return None +*/ +void csi_timer_disable_pm(csi_timer_t *timer); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_TIMER_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/tipc.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/tipc.h new file mode 100755 index 00000000..da117ebc --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/tipc.h @@ -0,0 +1,56 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/tipc.h + * @brief Header File for TIPC Driver + * @version V1.0 + * @date 08. Mar 2020 + * @model tipc + ******************************************************************************/ + +#ifndef _DRV_TIPC_H_ +#define _DRV_TIPC_H_ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + uint32_t ip; + uint16_t dev_tag; + uint8_t idx; +} csi_tipcmap_t; + +/** + \brief Config the tipc module properity + \param[in] dev Dev handle \ref csi_dev_t + \param[in] is_secure is secure or not +*/ +csi_error_t csi_dev_secure_config(csi_dev_t *dev, bool is_secure); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_TIPC_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/uart.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/uart.h new file mode 100755 index 00000000..20ecc29d --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/uart.h @@ -0,0 +1,241 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/uart.h + * @brief Header File for UART Driver + * @version V1.0 + * @date 08. Apr 2020 + * @model uart + ******************************************************************************/ + +#ifndef _DRV_UART_H_ +#define _DRV_UART_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*----- UART Control Codes: Mode Parameters: Data Bits -----*/ +typedef enum { + UART_DATA_BITS_5 = 0, ///< 5 Data bits + UART_DATA_BITS_6, ///< 6 Data bit + UART_DATA_BITS_7, ///< 7 Data bits + UART_DATA_BITS_8, ///< 8 Data bits (default) + UART_DATA_BITS_9 ///< 9 Data bits +} csi_uart_data_bits_t; + +/*----- UART Control Codes: Mode Parameters: Parity -----*/ +typedef enum { + UART_PARITY_NONE = 0, ///< No Parity (default) + UART_PARITY_EVEN, ///< Even Parity + UART_PARITY_ODD, ///< Odd Parity +} csi_uart_parity_t; + +/*----- UART Control Codes: Mode Parameters: Stop Bits -----*/ +typedef enum { + UART_STOP_BITS_1 = 0, ///< 1 Stop bit (default) + UART_STOP_BITS_2, ///< 2 Stop bits + UART_STOP_BITS_1_5, ///< 1.5 Stop bits +} csi_uart_stop_bits_t; + +/*----- UART Control Codes: Mode Parameters: Flow Control -----*/ +typedef enum { + UART_FLOWCTRL_NONE = 0, ///< none flowctrl + UART_FLOWCTRL_RTS, ///< RTS + UART_FLOWCTRL_CTS, ///< CTS + UART_FLOWCTRL_RTS_CTS ///< RTS & CTS +} csi_uart_flowctrl_t; + +/****** UART Event *****/ +typedef enum { + UART_EVENT_SEND_COMPLETE = 0, ///< Send data completed. + UART_EVENT_RECEIVE_COMPLETE, ///< Receive data completed. + UART_EVENT_RECEIVE_FIFO_READABLE, ///< Data in uart fifo, call csi_uart_receive() get the data. + UART_ENENT_BREAK_INTR, ///< the serial input,sin, is held in a logic '0' state for longer than the sum of start time+data bits+parity+stop bits. + UART_EVENT_ERROR_OVERFLOW, ///< A new data character was received before the previous data was read. + UART_EVENT_ERROR_PARITY, ///< Occur parity error in the receiver. + UART_EVENT_ERROR_FRAMING ///< the receiver does not detect a valid STOP bit in the received data. +} csi_uart_event_t; + +///< definition for uart. +typedef struct csi_uart csi_uart_t; + +struct csi_uart { + csi_dev_t dev; + void (*callback)(csi_uart_t *uart, csi_uart_event_t event, void *arg); + void *arg; + uint8_t *tx_data; + uint32_t tx_size; + uint8_t *rx_data; + uint32_t rx_size; + csi_dma_ch_t *tx_dma; + csi_dma_ch_t *rx_dma; + csi_error_t (*send)(csi_uart_t *uart, const void *data, uint32_t size); + csi_error_t (*receive)(csi_uart_t *uart, void *data, uint32_t size); + csi_state_t state; + void *priv; +}; + +/** + \brief Initializes the resources needed for the UART interface. + \param[in] uart Operate handle. + \param[in] idx The device idx. + \return Error code. +*/ +csi_error_t csi_uart_init(csi_uart_t *uart, uint32_t idx); + +/** + \brief De-initialize UART Interface. stops operation and releases the software resources used by the interface. + \param[in] uart Operate handle. + \return Error code. +*/ +void csi_uart_uninit(csi_uart_t *uart); + +/** + \brief Attach the callback handler to UART. + \param[in] uart Operate handle. + \param[in] callback Callback function. + \param[in] arg User can define it by himself as callback's param. + \return Error code. +*/ +csi_error_t csi_uart_attach_callback(csi_uart_t *uart, void *callback, void *arg); + +/** + \brief Detach the callback handler. + \param[in] uart Operate handle. +*/ +void csi_uart_detach_callback(csi_uart_t *uart); + +/** + \brief Config the baudrate. + \param[in] uart UART handle to operate. + \param[in] baud UART baudrate. + \return Error code. +*/ +csi_error_t csi_uart_baud(csi_uart_t *uart, uint32_t baud); + +/** + \brief Config the uart format. + \param[in] uart UART handle to operate. + \param[in] data_bit UART data bits. + \param[in] parity UART data parity. + \param[in] stop_bit UART stop bits. + \return Error code. +*/ +csi_error_t csi_uart_format(csi_uart_t *uart, csi_uart_data_bits_t data_bits, + csi_uart_parity_t parity, csi_uart_stop_bits_t stop_bits); + +/** + \brief Config the uart flow control. + \param[in] uart UART handle to operate. + \param[in] flowctrl UART flow control. + \return Error code. +*/ +csi_error_t csi_uart_flowctrl(csi_uart_t *uart, csi_uart_flowctrl_t flowctrl); + +/** + \brief Start send data to UART transmitter, this function is blocking. + \param[in] uart UART handle to operate. + \param[in] data Pointer to buffer with data to send to UART transmitter. + \param[in] size Number of data to send (byte). + \param[in] timeout The timeout between bytes(ms). + \return the num of data which is sent successfully or CSI_ERROR. +*/ +int32_t csi_uart_send(csi_uart_t *uart, const void *data, uint32_t size, uint32_t timeout); + +/** + \brief Start send data to UART transmitter, this function is non-blocking. + \param[in] uart UART handle to operate. + \param[in] data Pointer to buffer with data to send to UART transmitter. + \param[in] size Number of data to send (byte). + \return Error code. +*/ +csi_error_t csi_uart_send_async(csi_uart_t *uart, const void *data, uint32_t size); + +/** + \brief Query data from UART receiver FIFO, this function is blocking. + \param[in] uart UART handle to operate. + \param[out] data Pointer to buffer for data to receive from UART receiver. + \param[in] size Number of data to receive. + \param[in] timeout The timeout between bytes(ms). + \return the num of data witch is received successfully or CSI_ERROR. +*/ +int32_t csi_uart_receive(csi_uart_t *uart, void *data, uint32_t size, uint32_t timeout); + +/** + \brief Start receiving data from UART receiver, this function is non-blocking. + \param[in] uart UART handle to operate. + \param[out] data Pointer to buffer for data to receive from UART receiver. + \param[in] size Number of data to receive (byte). + \return Error code. +*/ +csi_error_t csi_uart_receive_async(csi_uart_t *uart, void *data, uint32_t size); + +/** + \brief Get character in query mode. + \param[in] uart UART handle to operate. + \return the character to get. +*/ +uint8_t csi_uart_getc(csi_uart_t *uart); + +/** + \brief Send character in query mode. + \param[in] uart UART handle to operate. + \param[in] ch The character to be send. +*/ +void csi_uart_putc(csi_uart_t *uart, uint8_t ch); + +/** + \brief Link DMA channel to uart device. + \param[in] uart UART handle to operate. + \param[in] tx_dma The DMA channel handle for send, when it is NULL means to unlink the channel. + \param[in] rx_dma The DMA channel handle for receive, when it is NULL means to unlink the channel. + \return Error code. +*/ +csi_error_t csi_uart_link_dma(csi_uart_t *uart, csi_dma_ch_t *tx_dma, csi_dma_ch_t *rx_dma); + +/** + \brief Get the state of uart device. + \param[in] uart UART handle to operate. + \param[out] state The state of uart device. + \return Error code. +*/ +csi_error_t csi_uart_get_state(csi_uart_t *uart, csi_state_t *state); + +/** + \brief Enable uart power manage. + \param[in] uart UART handle to operate. + \return Error code. +*/ +csi_error_t csi_uart_enable_pm(csi_uart_t *uart); + +/** + \brief Disable uart power manage. + \param[in] uart UART handle to operate. +*/ +void csi_uart_disable_pm(csi_uart_t *uart); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_UART_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/usi.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/usi.h new file mode 100755 index 00000000..8e8cb1d3 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/usi.h @@ -0,0 +1,42 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/usi.h + * @brief Header File for USI Driver + * @version V1.0 + * @date 02. June 2020 + * @model usi + ******************************************************************************/ + +#ifndef _DRV_USI_H_ +#define _DRV_USI_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_USI_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/usi_iic.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/usi_iic.h new file mode 100755 index 00000000..257b534a --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/usi_iic.h @@ -0,0 +1,260 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/drv_usi_iic.h + * @brief Header File for IIC driver + * @version V1.0 + * @date 02. June 2020 + * @model usi_iic + ******************************************************************************/ + +#ifndef _DRV_USI_IIC_H_ +#define _DRV_USI_IIC_H_ + +#include +#include +#include +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** + \brief Init iic ctrl block. + Initializes the resources needed for the iic instance. + \param[in] iic Handle of iic instance. + \param[in] idx Index of instance. + \return \ref csi_error_t. +*/ +csi_error_t csi_usi_iic_init(csi_iic_t *iic, uint32_t idx); + +/** + \brief Uninit iic ctrl block. + Stops operation and releases the software resources used by the instance. + \param[in] iic Handle of iic instance. +*/ +void csi_usi_iic_uninit(csi_iic_t *iic); + +/** + \brief Config iic master or slave mode. + \param[in] iic Handle of iic instance. + \param[in] mode IIC mode \ref csi_iic_mode_t. + \return \ref csi_error_t. +*/ +csi_error_t csi_usi_iic_mode(csi_iic_t *iic, csi_iic_mode_t mode); + +/** + \brief Config iic addr mode. + \param[in] iic Handle of iic instance. + \param[in] addr_mode IIC addr mode \ref csi_iic_addr_mode_t. + \return \ref csi_error_t. +*/ +csi_error_t csi_usi_iic_addr_mode(csi_iic_t *iic, csi_iic_addr_mode_t addr_mode); + +/** + \brief Config iic speed. + \param[in] iic Handle of iic instance. + \param[in] speed iic speed mode \ref csi_iic_speed_t. + \return \ref csi_error_t. +*/ +csi_error_t csi_usi_iic_speed(csi_iic_t *iic, csi_iic_speed_t speed); + +/** + \brief Config iic own addr. + \param[in] iic Handle of iic instance. + \param[in] own_addr IIC set own addr at slave mode. + \return \ref csi_error_t. +*/ +csi_error_t csi_usi_iic_own_addr(csi_iic_t *iic, uint32_t own_addr); + +/** + \brief Start sending data as iic master. + This function is blocking. + \param[in] iic Handle of iic instance. + \param[in] devaddr Addrress of slave device. + \param[in] data Pointer to send data buffer. + \param[in] size Size of data items to send. + \param[in] timout Unit of time delay(ms). + \return The amount of real data sent. +*/ +int32_t csi_usi_iic_master_send(csi_iic_t *iic, uint32_t devaddr, const void *data, uint32_t size, uint32_t timeout); + +/** + \brief Start receiving data as iic master. + This function is blocking. + \param[in] iic Handle to operate. + \param[in] devaddr IIC addrress of slave device. + \param[out] data Pointer to buffer for data to receive from iic receiver. + \param[in] size Size of data items to receive. + \param[in] timeout Unit of time delay(ms). + \return The amount of real data received. +*/ +int32_t csi_usi_iic_master_receive(csi_iic_t *iic, uint32_t devaddr, void *data, uint32_t size, uint32_t timeout); + +/** + \brief Start sending data as iic master. + This function is non-blocking,\ref csi_usi_iic_event_t is signaled when transfer completes or error happens. + \param[in] iic Handle to operate. + \param[in] devaddr IIC addrress of slave device. + \param[in] data Pointer to send data buffer. + \param[in] size Size of data items to send. + \return \ref csi_error_t. +*/ +csi_error_t csi_usi_iic_master_send_async(csi_iic_t *iic, uint32_t devaddr, const void *data, uint32_t size); + +/** + \brief Start receiving data as iic master. + This function is non-blocking.\ref csi_usi_iic_event_t is signaled when transfer completes or error happens. + \param[in] iic Handle to operate. + \param[in] devaddr IIC addrress of slave device. + \param[out] data Pointer to buffer for data to receive from iic receiver. + \param[in] size Size of data items to receive. + \return \ref csi_error_t. +*/ +csi_error_t csi_usi_iic_master_receive_async(csi_iic_t *iic, uint32_t devaddr, void *data, uint32_t size); + +/** + \brief Start sending data as iic master. + This function is blocking. + \param[in] iic Handle of iic instance. + \param[in] devaddr Addrress of slave device. + \param[in] memaddr Internal addr of device. + \param[in] memaddr_size Internal addr mode of device. + \param[in] data Pointer to send data buffer. + \param[in] size Size of data items to send. + \param[in] timout Unit of time delay(ms). + \return The amount of real data sent. +*/ +int32_t csi_usi_iic_mem_send(csi_iic_t *iic, uint32_t devaddr, uint16_t memaddr, csi_iic_mem_addr_size_t memaddr_size, const void *data, uint32_t size, uint32_t timeout); + +/** + \brief Start receiving data as iic master. + This function is blocking. + \param[in] iic Handle to operate. + \param[in] devaddr IIC addrress of slave device. + \param[in] memaddr Internal addr of device. + \param[in] memaddr_mode Internal addr mode of device. + \param[out] data Pointer to buffer for data to receive from eeprom device. + \param[in] size Size of data items to receive. + \param[in] timeout Unit of time delay(ms). + \return The amount of real data received. +*/ +int32_t csi_usi_iic_mem_receive(csi_iic_t *iic, uint32_t devaddr, uint16_t memaddr, csi_iic_mem_addr_size_t memaddr_size, void *data, uint32_t size, uint32_t timeout); + +/** + \brief Start sending data as iic slave. + This function is blocking. + \param[in] iic Handle to operate. + \param[in] data Pointer to buffer with data to send to iic master. + \param[in] size Size of data items to send. + \param[in] timeout Unit of time delay(ms). + \return The amount of real data sent. +*/ +int32_t csi_usi_iic_slave_send(csi_iic_t *iic, const void *data, uint32_t size, uint32_t timeout); + +/** + \brief Start receiving data as iic slave. + This function is blocking. + \param[in] iic Handle to operate. + \param[out] data Pointer to buffer for data to receive from iic master. + \param[in] size Size of data items to receive. + \param[in] timeout Unit of time delay(ms). + \return The amount of real data received. +*/ +int32_t csi_usi_iic_slave_receive(csi_iic_t *iic, void *data, uint32_t size, uint32_t timeout); + +/** + \brief Start sending data as iic slave. + This function is non-blocking,\ref csi_usi_iic_event_t is signaled when transfer completes or error happens. + \param[in] iic Handle to operate. + \param[in] data Pointer to buffer with data to send to iic master. + \param[in] size size of data items to send. + \return \ref csi_error_t. +*/ +csi_error_t csi_usi_iic_slave_send_async(csi_iic_t *iic, const void *data, uint32_t size); + +/** + \brief Start receiving data as iic slave. + This function is non-blocking,\ref csi_usi_iic_event_t is signaled when transfer completes or error happens. + \param[in] handle IIC handle to operate. + \param[out] data Pointer to buffer for data to receive from iic master. + \param[in] size Size of data items to receive. + \return \ref csi_error_t. +*/ +csi_error_t csi_usi_iic_slave_receive_async(csi_iic_t *iic, void *data, uint32_t size); + +/** + \brief Attach callback to the iic. + \param[in] iic IIC handle to operate. + \param[in] cb Event callback function \ref csi_usi_iic_callback_t. + \param[in] arg User private param for event callback. + \return \ref csi_error_t. +*/ +csi_error_t csi_usi_iic_attach_callback(csi_iic_t *iic, void *callback, void *arg); + +/** + \brief Detach callback from the iic. + \param[in] iic IIC handle to operate. + \return \ref csi_error_t. +*/ +void csi_usi_iic_detach_callback(csi_iic_t *iic); + +/** + \brief Config iic stop to generate. + \param[in] iic IIC handle to operate. + \param[in] enable Transfer operation is pending - stop condition will not be generated. + \return \ref csi_error_t. +*/ +csi_error_t csi_usi_iic_xfer_pending(csi_iic_t *iic, bool enable); + +/** + \brief Link DMA channel to iic device. + \param[in] iic Handle to operate. + \param[in] tx_dma The DMA channel handle for send, when it is NULL means to unlink the channel. + \param[in] rx_dma The DMA channel handle for receive, when it is NULL means to unlink the channel. + \return \ref csi_error_t. +*/ +csi_error_t csi_usi_iic_link_dma(csi_iic_t *iic, csi_dma_ch_t *tx_dma, csi_dma_ch_t *rx_dma); + +/** + \brief Get iic state. + \param[in] iic Handle to operate. + \param[out] state IIC state \ref csi_state_t. + \return \ref csi_error_t. +*/ +csi_error_t csi_usi_iic_get_state(csi_iic_t *iic, csi_state_t *state); + +/** + \brief Enable iic power manage. + \param[in] iic IIC handle to operate. + \return \ref csi_error_t. +*/ +csi_error_t csi_usi_iic_enable_pm(csi_iic_t *iic); + +/** + \brief Disable iic power manage. + \param[in] iic IIC handle to operate. +*/ +void csi_usi_iic_disable_pm(csi_iic_t *iic); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_USI_IIC_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/usi_spi.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/usi_spi.h new file mode 100755 index 00000000..eaa1f3e3 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/usi_spi.h @@ -0,0 +1,229 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/usi_spi.h + * @brief Header File for SPI Driver + * @version V1.0 + * @date 02. June 2020 + * @model usi_spi + ******************************************************************************/ + +#ifndef _DRV_SPI_USI_H_ +#define _DRV_SPI_USI_H_ + +#include +#include +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** + \brief Initialize SPI Interface. + Initializes the resources needed for the SPI instance + \param[in] spi SPI handle + \param[in] idx SPI instance index + \return Error code +*/ +csi_error_t csi_usi_spi_init(csi_spi_t *spi, uint32_t idx); + +/** + \brief De-initialize SPI Interface + Stops operation and releases the software resources used by the spi instance + \param[in] spi SPI handle + \return None +*/ +void csi_usi_spi_uninit(csi_spi_t *spi); + +/** + \brief Attach the callback handler to SPI + \param[in] spi Operate handle. + \param[in] callback Callback function + \param[in] arg User can define it by himself as callback's param + \return Error code +*/ +csi_error_t csi_usi_spi_attach_callback(csi_spi_t *spi, void *callback, void *arg); + +/** + \brief Detach the callback handler + \param[in] spi Operate handle. + \return None +*/ +void csi_usi_spi_detach_callback(csi_spi_t *spi); + + +/** + \brief Config spi mode (master or slave). + \param[in] spi SPI handle + \param[in] mode The mode of spi (master or slave) + \return Error code +*/ +csi_error_t csi_usi_spi_mode(csi_spi_t *spi, csi_spi_mode_t mode); + +/** + \brief Config spi cp format. + \param[in] spi SPI handle + \param[in] format SPI cp format + \return Error code +*/ +csi_error_t csi_usi_spi_cp_format(csi_spi_t *spi, csi_spi_cp_format_t format); + +/** + \brief Config spi frame len. + \param[in] spi SPI handle + \param[in] length spi frame len + \return error code +*/ +csi_error_t csi_usi_spi_frame_len(csi_spi_t *spi, csi_spi_frame_len_t length); + +/** + \brief Config spi work frequence. + \param[in] spi SPI handle + \param[in] baud SPI work baud + \return The actual config frequency +*/ +uint32_t csi_usi_spi_baud(csi_spi_t *spi, uint32_t baud); + +/** + \brief Config spi mode. + \param[in] Handle spi handle to operate. + \param[in] baud SPI baud rate. If negative, then this attribute not changed + \param[in] mode \ref spi_mode_e . If negative, then this attribute not changed + \param[in] format \ref spi_format_e . If negative, then this attribute not changed + \param[in] order \ref spi_bit_order_e . If negative, then this attribute not changed + \param[in] ss_mode \ref spi_ss_mode_t . If negative, then this attribute not changed + \param[in] bit_width SPI data bitwidth: (1 ~ SPI_DATAWIDTH_MAX) . If negative, then this attribute not changed + \return Error code +*/ +csi_error_t drv_usi_spi_config(csi_spi_t *spi, csi_spi_mode_t mode, csi_spi_frame_len_t width, csi_spi_cp_format_t format); + +/** + \brief Sending data to SPI transmitter,(received data is ignored). + Blocking mode ,return unti all data has been sent or err happened + \param[in] spi Handle to operate. + \param[in] data Pointer to buffer with data to send to SPI transmitter. + \param[in] size Number of data to send(byte) + \param[in] timeout Unit in mini-second + \return If send success, this function shall return the num of data witch is sent successful + otherwise, the function shall return error code +*/ +int32_t csi_usi_spi_send(csi_spi_t *spi, const void *data, uint32_t size, uint32_t timeout); + +/** + \brief Sending data to SPI transmitter,(received data is ignored). + non-blocking mode,transfer done event will be signaled by driver + \param[in] spi Handle to operate. + \param[in] data Pointer to buffer with data to send to SPI transmitter. + \param[in] size Number of data items to send(byte) + \return Error code +*/ +csi_error_t csi_usi_spi_send_async(csi_spi_t *spi, const void *data, uint32_t size); + +/** + \brief Receiving data from SPI receiver. + Blocking mode, return untill curtain data items are readed + \param[in] spi Handle to operate. + \param[out] data Pointer to buffer for data to receive from SPI receiver + \param[in] size Number of data items to receive(byte) + \param[in] timeout Unit in mini-second + \return If receive success, this function shall return the num of data witch is received successful + Otherwise, the function shall return error code +*/ +int32_t csi_usi_spi_receive(csi_spi_t *spi, void *data, uint32_t size, uint32_t timeout); + +/** + \brief Receiving data from SPI receiver. + Not-blocking mode, event will be signaled when receive done or err happend + \param[in] spi Handle to operate. + \param[out] data Pointer to buffer for data to receive from SPI receiver + \param[in] size Number of data items to receive(byte) + \return Error code +*/ +csi_error_t csi_usi_spi_receive_async(csi_spi_t *spi, void *data, uint32_t size); + +/** + \brief Dulplex,sending and receiving data at the same time + \ref csi_spi_event_t is signaled when operation completes or error happens. + \ref csi_spi_get_state can get operation status. + Blocking mode, this function returns after operation completes or error happens. + \param[in] Handle spi handle to operate. + \param[in] data_out Pointer to buffer with data to send to SPI transmitter + \param[out] data_in Pointer to buffer for data to receive from SPI receiver + \param[in] size Data size(byte) + \return If transfer success, this function shall return the num of data witch is transfer successful + otherwise, the function shall return error code +*/ +int32_t csi_usi_spi_send_receive(csi_spi_t *spi, const void *data_out, void *data_in, uint32_t size, uint32_t timeout); + +/** + \brief Transmit first then receive ,receive will begin after transmit is done + if non-blocking mode, this function only starts the transfer, + \ref csi_spi_event_t is signaled when operation completes or error happens. + \ref csi_spi_get_state can get operation status. + \param[in] handle spi Handle to operate. + \param[in] data_out Pointer to buffer with data to send to SPI transmitter + \param[out] data_in Pointer to buffer for data to receive from SPI receiver + \param[in] size Data size(byte) + \return Error code +*/ +csi_error_t csi_usi_spi_send_receive_async(csi_spi_t *spi, const void *data_out, void *data_in, uint32_t size); + +/* + \brief Set slave select num. Only valid for master + \param[in] Handle spi handle to operate. + \param[in] slave_num SPI slave num. + \return None + */ +void csi_usi_spi_select_slave(csi_spi_t *spi, uint32_t slave_num); + +/** + \brief Link DMA channel to spi device + \param[in] spi SPI handle to operate. + \param[in] tx_dma The DMA channel handle for send, when it is NULL means to unlink the channel + \param[in] rx_dma The DMA channel handle for receive, when it is NULL means to unlink the channel + \return Error code +*/ +csi_error_t csi_usi_spi_link_dma(csi_spi_t *spi, csi_dma_ch_t *tx_dma, csi_dma_ch_t *rx_dma); + +/** + \brief Get the state of spi device + \param[in] spi SPI handle to operate. + \param[out] state The state of spi device + \return Error code +*/ +csi_error_t csi_usi_spi_get_state(csi_spi_t *spi, csi_state_t *state); + +/** + \brief Enable spi power manage + \param[in] spi SPI handle to operate. + \return Error code +*/ +csi_error_t csi_usi_spi_enable_pm(csi_spi_t *spi); + +/** + \brief Disable spi power manage + \param[in] spi SPI handle to operate. + \return Error code +*/ +void csi_spi_disable_pm(csi_spi_t *spi); +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_SPI_USI_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/usi_usart.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/usi_usart.h new file mode 100755 index 00000000..59bfe554 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/usi_usart.h @@ -0,0 +1,192 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/usi_usart.h + * @brief Header File for USART Driver + * @version V1.0 + * @date 02. June 2020 + * @model usi_usart + ******************************************************************************/ + +#ifndef _DRV_USI_USART_H_ +#define _DRV_USI_USART_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \brief Initialize UART Interface. 1. Initializes the resources needed for the UART interface 2.registers event callback function + \param[in] uart Operate handle. + \param[in] idx The device idx + \param[in] cb_event Event call back function \ref uart_event_cb_t + \param[in] arg User can define it by himself + \return error code +*/ +csi_error_t csi_usi_uart_init(csi_uart_t *uart, uint32_t idx); + +/** + \brief De-initialize UART Interface. stops operation and releases the software resources used by the interface + \param[in] uart Operate handle. + \return Error code +*/ +void csi_usi_uart_uninit(csi_uart_t *uart); + +/** + \brief Attach the callback handler to UART + \param[in] uart Operate handle. + \param[in] cb Callback function + \param[in] arg User can define it by himself as callback's param + \return Error code +*/ +csi_error_t csi_usi_uart_attach_callback(csi_uart_t *uart, void * cb, void *arg); + +/** + \brief Detach the callback handler + \param[in] uart Operate handle. +*/ +void csi_usi_uart_detach_callback(csi_uart_t *uart); + +/** + \brief Config the baudrate. + \param[in] uart UART handle to operate. + \param[in] baud UART baudrate + \return Error code +*/ +csi_error_t csi_usi_uart_baud(csi_uart_t *uart, uint32_t baud); + +/** + \brief Config the uart format. + \param[in] uart UART handle to operate. + \param[in] data_bit UART data bits + \param[in] parity UART data parity + \param[in] stop_bit UART stop bits + \return Error code +*/ +csi_error_t csi_usi_uart_format(csi_uart_t *uart, csi_uart_data_bits_t data_bits, + csi_uart_parity_t parity, csi_uart_stop_bits_t stop_bits); + +/** + \brief Config the uart flow control. + \param[in] uart UART handle to operate. + \param[in] flowctrl UART flow control + \return Error code +*/ +csi_error_t csi_usi_uart_flowctrl(csi_uart_t *uart, csi_uart_flowctrl_t flowctrl); + +/** + \brief Start sending data to UART transmitter. + \param[in] uart UART handle to operate. + \param[in] data Pointer to buffer with data to send to UART transmitter. data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits + \param[in] num Number of data items to send (byte) + \param[in] Timeout is the number of queries, not time + \return The num of data witch is send successful +*/ +int32_t csi_usi_uart_send(csi_uart_t *uart, const void *data, uint32_t size, uint32_t timeout); + +/** + \brief Start sending data to UART transmitter (interrupt mode). + \param[in] uart UART handle to operate. + \param[in] data Pointer to buffer with data to send to UART transmitter. data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits + \param[in] num Number of data items to send + \return The status of send func +*/ +csi_error_t csi_usi_uart_send_async(csi_uart_t *uart, const void *data, uint32_t size); + +/** + \brief Get the num of data in RX_FIFO. + \param[in] uart UART handle to operate. + \return The num of data in RX_FIFO +*/ +uint32_t csi_usi_uart_get_recvfifo_waiting_num(csi_uart_t *uart); + +/** + \brief Start receiving data from UART receiver. \n + This function is non-blocking,\ref uart_event_e is signaled when operation completes or error happens. + \ref csi_uart_get_status can get operation status. + \param[in] uart UART handle to operate. + \param[out] data Pointer to buffer for data to receive from UART receiver.data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits + \param[in] num Number of data items to receive + \return Error code +*/ +csi_error_t csi_usi_uart_receive_async(csi_uart_t *uart, void *data, uint32_t size); + +/** + \brief Query data from UART receiver FIFO. + \param[in] uart UART handle to operate. + \param[out] data Pointer to buffer for data to receive from UART receiver + \param[in] num Number of data items to receive + \param[in] Timeout is the number of queries, not time + \return FIFO data num to receive +*/ +int32_t csi_usi_uart_receive(csi_uart_t *uart, void *data, uint32_t size, uint32_t timeout); + +/** + \brief Get character in query mode. + \param[in] uart UART handle to operate. + \param[out] ch The pointer to the received character. + \return Error code +*/ +uint8_t csi_usi_uart_getchar(csi_uart_t *uart); + +/** + \brief Transmit character in query mode. + \param[in] uart UART handle to operate. + \param[in] ch The input character + \return Error code +*/ +void csi_usi_uart_putchar(csi_uart_t *uart, uint8_t ch); + +/** + \brief Link DMA channel to uart device + \param[in] uart UART handle to operate. + \param[in] tx_dma The DMA channel handle for send, when it is NULL means to unlink the channel + \param[in] rx_dma The DMA channel handle for receive, when it is NULL means to unlink the channel + \return Error code +*/ +csi_error_t csi_usi_uart_link_dma(csi_uart_t *uart, csi_dma_ch_t *tx_dma, csi_dma_ch_t *rx_dma); + +/** + \brief Get the state of uart device. + \param[in] uart UART handle to operate. + \param[out] state The state of uart device. + \return Error code. +*/ +csi_error_t csi_usi_uart_get_state(csi_uart_t *uart, csi_state_t *state); + +/** + \brief Enable uart power manage. + \param[in] uart UART handle to operate. + \return Error code. +*/ +csi_error_t csi_usi_uart_enable_pm(csi_uart_t *uart); + +/** + \brief Disable uart power manage. + \param[in] uart UART handle to operate. +*/ +void csi_usi_uart_disable_pm(csi_uart_t *uart); +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_USI_USART_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/wdt.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/wdt.h new file mode 100755 index 00000000..d7a824ec --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/wdt.h @@ -0,0 +1,139 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file drv/wdt.h + * @brief Header File for WDT Driver + * @version V1.0 + * @date 9. Oct 2020 + * @model wdt + ******************************************************************************/ + +#ifndef _DRV_WDT_H_ +#define _DRV_WDT_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct csi_wdt csi_wdt_t; + +struct csi_wdt { + csi_dev_t dev; + void (*callback)(csi_wdt_t *wdt, void *arg); + void *arg; + void *priv; +}; + +/** + \brief Initialize WDT interface. Initializes the resources needed for the WDT interface + \param[in] wdt Handle to operate + \param[in] idx WDT index + \return Error code \ref csi_error_t +*/ +csi_error_t csi_wdt_init(csi_wdt_t *wdt, uint32_t idx); + +/** + \brief De-initialize WDT interface. Stops operation and releases the software resources used by the interface + \param[in] wdt Handle to operate + \return None +*/ +void csi_wdt_uninit(csi_wdt_t *wdt); + +/** + \brief Set the WDT value + \param[in] wdt Handle to operate + \param[in] ms The timeout value(ms) + \return Error code \ref csi_error_t +*/ +csi_error_t csi_wdt_set_timeout(csi_wdt_t *wdt, uint32_t ms); + +/** + \brief Start the WDT + \param[in] wdt Handle to operate + \return Error code \ref csi_error_t +*/ +csi_error_t csi_wdt_start(csi_wdt_t *wdt); + +/** + \brief Stop the WDT + \param[in] wdt Handle to operate + \return None +*/ +void csi_wdt_stop(csi_wdt_t *wdt); + +/** + \brief Feed the WDT + \param[in] wdt Handle to operate + \return Error code \ref csi_error_t +*/ +csi_error_t csi_wdt_feed(csi_wdt_t *wdt); + +/** + \brief Get the remaining time to timeout + \param[in] wdt Handle to operate + \return The remaining time of WDT(ms) +*/ +uint32_t csi_wdt_get_remaining_time(csi_wdt_t *wdt); + +/** + \brief Check WDT is running + \param[in] wdt Handle to operate + \return + true - WDT is running + false - WDT is stopped +*/ +bool csi_wdt_is_running(csi_wdt_t *wdt); + +/** + \brief Attach the callback handler to WDT + \param[in] wdt Handle to operate + \param[in] callback Callback function + \param[in] arg Callback's param + \return Error code \ref csi_error_t +*/ +csi_error_t csi_wdt_attach_callback(csi_wdt_t *wdt, void *callback, void *arg); + +/** + \brief Detach the callback handler + \param[in] wdt Handle to operate + \return None +*/ +void csi_wdt_detach_callback(csi_wdt_t *wdt); + +/** + \brief Enable WDT power manage + \param[in] wdt Handle to operate + \return Error code \ref csi_error_t +*/ +csi_error_t csi_wdt_enable_pm(csi_wdt_t *wdt); + +/** + \brief Disable WDT power manage + \param[in] wdt Handle to operate + \return None +*/ +void csi_wdt_disable_pm(csi_wdt_t *wdt); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRV_WDT_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csi_common_tables.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csi_common_tables.h new file mode 100644 index 00000000..7d5e4028 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csi_common_tables.h @@ -0,0 +1,316 @@ +/* + * Copyright (C) 2016-2019 C-SKY Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file csi_common_tables.h + * @brief This file has extern declaration for common tables like + * Bitreverse, reciprocal etc which are used across different functions. + * @version V1.0 + * @date 20. Dec 2016 + ******************************************************************************/ + +#ifndef _CSI_COMMON_TABLES_H +#define _CSI_COMMON_TABLES_H + +#include "csi_math.h" + +extern const uint16_t csiBitRevTable[1024]; +extern const q15_t csiRecipTableQ15[64]; +extern const q31_t csiRecipTableQ31[64]; +extern const uint32_t twiddleCoef_16[32]; +extern const uint32_t twiddleCoef_32[64]; +extern const uint32_t twiddleCoef_64[128]; +extern const uint32_t twiddleCoef_128[256]; +extern const uint32_t twiddleCoef_256[512]; +extern const uint32_t twiddleCoef_512[1024]; +extern const uint32_t twiddleCoef_1024[2048]; +extern const uint32_t twiddleCoef_2048[4096]; +extern const uint32_t twiddleCoef_4096[8192]; +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; +extern const float32_t twiddleCoef_rfft_8192[8192]; + +extern const q15_t twiddleCoef_fast_16_q15[24]; +extern const q15_t twiddleCoef_fast_32_q15[56]; +extern const q15_t twiddleCoef_fast_64_q15[120]; +extern const q15_t twiddleCoef_fast_128_q15[248]; +extern const q15_t twiddleCoef_fast_256_q15[504]; +extern const q15_t twiddleCoef_fast_512_q15[1016]; +extern const q15_t twiddleCoef_fast_1024_q15[2040]; +extern const q15_t twiddleCoef_fast_2048_q15[4088]; +extern const q15_t twiddleCoef_fast_4096_q15[8184]; + +extern const q31_t twiddleCoef_fast_16_q31[24]; +extern const q31_t twiddleCoef_fast_32_q31[56]; +extern const q31_t twiddleCoef_fast_64_q31[120]; +extern const q31_t twiddleCoef_fast_128_q31[248]; +extern const q31_t twiddleCoef_fast_256_q31[504]; +extern const q31_t twiddleCoef_fast_512_q31[1016]; +extern const q31_t twiddleCoef_fast_1024_q31[2040]; +extern const q31_t twiddleCoef_fast_2048_q31[4088]; +extern const q31_t twiddleCoef_fast_4096_q31[8184]; + +extern const uint32_t twiddleCoef_fast_16[24]; +extern const uint32_t twiddleCoef_fast_32[56]; +extern const uint32_t twiddleCoef_fast_64[120]; +extern const uint32_t twiddleCoef_fast_128[248]; +extern const uint32_t twiddleCoef_fast_256[504]; +extern const uint32_t twiddleCoef_fast_512[1016]; +extern const uint32_t twiddleCoef_fast_1024[2040]; +extern const uint32_t twiddleCoef_fast_2048[4088]; +extern const uint32_t twiddleCoef_fast_4096[8184]; + +extern const q15_t realCoefAQ15_8192[8192]; +extern const q31_t realCoefAQ31_8192[8192]; +extern const q15_t realCoefBQ15_8192[8192]; +extern const q31_t realCoefBQ31_8192[8192]; + +/*Tables for RFFT.*/ +extern const q15_t ALIGN4 realCoefAQ15_32[32]; +extern const q15_t ALIGN4 realCoefAQ15_64[64]; +extern const q15_t ALIGN4 realCoefAQ15_128[128]; +extern const q15_t ALIGN4 realCoefAQ15_256[256]; +extern const q15_t ALIGN4 realCoefAQ15_512[512]; +extern const q15_t ALIGN4 realCoefAQ15_1024[1024]; +extern const q15_t ALIGN4 realCoefAQ15_2048[2048]; +extern const q15_t ALIGN4 realCoefAQ15_4096[4096]; + +extern const q15_t ALIGN4 realCoefBQ15_32[32]; +extern const q15_t ALIGN4 realCoefBQ15_64[64]; +extern const q15_t ALIGN4 realCoefBQ15_128[128]; +extern const q15_t ALIGN4 realCoefBQ15_256[256]; +extern const q15_t ALIGN4 realCoefBQ15_512[512]; +extern const q15_t ALIGN4 realCoefBQ15_1024[1024]; +extern const q15_t ALIGN4 realCoefBQ15_2048[2048]; +extern const q15_t ALIGN4 realCoefBQ15_4096[4096]; + +extern const q31_t realCoefAQ31_32[32]; +extern const q31_t realCoefAQ31_64[64]; +extern const q31_t realCoefAQ31_128[128]; +extern const q31_t realCoefAQ31_256[256]; +extern const q31_t realCoefAQ31_512[512]; +extern const q31_t realCoefAQ31_1024[1024]; +extern const q31_t realCoefAQ31_2048[2048]; +extern const q31_t realCoefAQ31_4096[4096]; + +extern const q31_t realCoefBQ31_32[32]; +extern const q31_t realCoefBQ31_64[64]; +extern const q31_t realCoefBQ31_128[128]; +extern const q31_t realCoefBQ31_256[256]; +extern const q31_t realCoefBQ31_512[512]; +extern const q31_t realCoefBQ31_1024[1024]; +extern const q31_t realCoefBQ31_2048[2048]; +extern const q31_t realCoefBQ31_4096[4096]; + + +extern const float32_t realCoefA[8192]; +extern const float32_t realCoefB[8192]; + +extern const csi_cfft_instance_q15 csi_cfft_fast_sR_q15_len16; +extern const csi_cfft_instance_q15 csi_cfft_fast_sR_q15_len32; +extern const csi_cfft_instance_q15 csi_cfft_fast_sR_q15_len64; +extern const csi_cfft_instance_q15 csi_cfft_fast_sR_q15_len128; +extern const csi_cfft_instance_q15 csi_cfft_fast_sR_q15_len256; +extern const csi_cfft_instance_q15 csi_cfft_fast_sR_q15_len512; +extern const csi_cfft_instance_q15 csi_cfft_fast_sR_q15_len1024; +extern const csi_cfft_instance_q15 csi_cfft_fast_sR_q15_len2048; +extern const csi_cfft_instance_q15 csi_cfft_fast_sR_q15_len4096; + +extern const csi_cfft_instance_q31 csi_cfft_fast_sR_q31_len16; +extern const csi_cfft_instance_q31 csi_cfft_fast_sR_q31_len32; +extern const csi_cfft_instance_q31 csi_cfft_fast_sR_q31_len64; +extern const csi_cfft_instance_q31 csi_cfft_fast_sR_q31_len128; +extern const csi_cfft_instance_q31 csi_cfft_fast_sR_q31_len256; +extern const csi_cfft_instance_q31 csi_cfft_fast_sR_q31_len512; +extern const csi_cfft_instance_q31 csi_cfft_fast_sR_q31_len1024; +extern const csi_cfft_instance_q31 csi_cfft_fast_sR_q31_len2048; +extern const csi_cfft_instance_q31 csi_cfft_fast_sR_q31_len4096; + +extern csi_rfft_fast_instance_q15 csi_rfft_fast_sR_q15_len32; +extern csi_rfft_fast_instance_q15 csi_rfft_fast_sR_q15_len64; +extern csi_rfft_fast_instance_q15 csi_rfft_fast_sR_q15_len128; +extern csi_rfft_fast_instance_q15 csi_rfft_fast_sR_q15_len256; +extern csi_rfft_fast_instance_q15 csi_rfft_fast_sR_q15_len512; +extern csi_rfft_fast_instance_q15 csi_rfft_fast_sR_q15_len1024; +extern csi_rfft_fast_instance_q15 csi_rfft_fast_sR_q15_len2048; +extern csi_rfft_fast_instance_q15 csi_rfft_fast_sR_q15_len4096; +extern csi_rfft_fast_instance_q15 csi_rfft_fast_sR_q15_len8192; + +extern csi_rfft_fast_instance_q15 csi_inv_rfft_fast_sR_q15_len32; +extern csi_rfft_fast_instance_q15 csi_inv_rfft_fast_sR_q15_len64; +extern csi_rfft_fast_instance_q15 csi_inv_rfft_fast_sR_q15_len128; +extern csi_rfft_fast_instance_q15 csi_inv_rfft_fast_sR_q15_len256; +extern csi_rfft_fast_instance_q15 csi_inv_rfft_fast_sR_q15_len512; +extern csi_rfft_fast_instance_q15 csi_inv_rfft_fast_sR_q15_len1024; +extern csi_rfft_fast_instance_q15 csi_inv_rfft_fast_sR_q15_len2048; +extern csi_rfft_fast_instance_q15 csi_inv_rfft_fast_sR_q15_len4096; +extern csi_rfft_fast_instance_q15 csi_inv_rfft_fast_sR_q15_len8192; + +extern csi_rfft_fast_instance_q31 csi_rfft_fast_sR_q31_len32; +extern csi_rfft_fast_instance_q31 csi_rfft_fast_sR_q31_len64; +extern csi_rfft_fast_instance_q31 csi_rfft_fast_sR_q31_len128; +extern csi_rfft_fast_instance_q31 csi_rfft_fast_sR_q31_len256; +extern csi_rfft_fast_instance_q31 csi_rfft_fast_sR_q31_len512; +extern csi_rfft_fast_instance_q31 csi_rfft_fast_sR_q31_len1024; +extern csi_rfft_fast_instance_q31 csi_rfft_fast_sR_q31_len2048; +extern csi_rfft_fast_instance_q31 csi_rfft_fast_sR_q31_len4096; +extern csi_rfft_fast_instance_q31 csi_rfft_fast_sR_q31_len8192; + +extern csi_rfft_fast_instance_q31 csi_inv_rfft_fast_sR_q31_len32; +extern csi_rfft_fast_instance_q31 csi_inv_rfft_fast_sR_q31_len64; +extern csi_rfft_fast_instance_q31 csi_inv_rfft_fast_sR_q31_len128; +extern csi_rfft_fast_instance_q31 csi_inv_rfft_fast_sR_q31_len256; +extern csi_rfft_fast_instance_q31 csi_inv_rfft_fast_sR_q31_len512; +extern csi_rfft_fast_instance_q31 csi_inv_rfft_fast_sR_q31_len1024; +extern csi_rfft_fast_instance_q31 csi_inv_rfft_fast_sR_q31_len2048; +extern csi_rfft_fast_instance_q31 csi_inv_rfft_fast_sR_q31_len4096; +extern csi_rfft_fast_instance_q31 csi_inv_rfft_fast_sR_q31_len8192; + +extern csi_dct4_fast_instance_q15 csi_dct4_fast_sR_q15_len128; +extern csi_dct4_fast_instance_q15 csi_dct4_fast_sR_q15_len512; +extern csi_dct4_fast_instance_q15 csi_dct4_fast_sR_q15_len2048; +extern csi_dct4_fast_instance_q15 csi_dct4_fast_sR_q15_len8192; + +extern csi_dct4_fast_instance_q31 csi_dct4_fast_sR_q31_len128; +extern csi_dct4_fast_instance_q31 csi_dct4_fast_sR_q31_len512; +extern csi_dct4_fast_instance_q31 csi_dct4_fast_sR_q31_len2048; +extern csi_dct4_fast_instance_q31 csi_dct4_fast_sR_q31_len8192; + +/*Tables for DCT4*/ +#ifndef CSI_OPT_WEIGHT +extern const q15_t ALIGN4 WeightsQ15_128[256]; +extern const q15_t ALIGN4 WeightsQ15_512[1024]; +extern const q15_t ALIGN4 WeightsQ15_2048[4096]; +extern const q15_t ALIGN4 WeightsQ15_8192[16384]; +#else +extern const q15_t ALIGN4 WeightsQ15_128[128+2]; +extern const q15_t ALIGN4 WeightsQ15_512[512+2]; +extern const q15_t ALIGN4 WeightsQ15_2048[2048+2]; +extern const q15_t ALIGN4 WeightsQ15_8192[8192+2]; +#endif +extern const q15_t ALIGN4 cos_factorsQ15_128[128]; +extern const q15_t ALIGN4 cos_factorsQ15_512[512]; +extern const q15_t ALIGN4 cos_factorsQ15_2048[2048]; +extern const q15_t ALIGN4 cos_factorsQ15_8192[8192]; + +#ifndef CSI_OPT_WEIGHT +extern const q31_t WeightsQ31_128[256]; +extern const q31_t WeightsQ31_512[1024]; +extern const q31_t WeightsQ31_2048[4096]; +extern const q31_t WeightsQ31_8192[16384]; +#else +extern const q31_t WeightsQ31_128[128+2]; +extern const q31_t WeightsQ31_512[512+2]; +extern const q31_t WeightsQ31_2048[2048+2]; +extern const q31_t WeightsQ31_8192[8192+2]; +#endif + +extern const q31_t cos_factorsQ31_128[128]; +extern const q31_t cos_factorsQ31_512[512]; +extern const q31_t cos_factorsQ31_2048[2048]; +extern const q31_t cos_factorsQ31_8192[8192]; + +#ifndef CSI_OPT_WEIGHT +extern const float32_t Weights_128[256]; +extern const float32_t Weights_512[1024]; +extern const float32_t Weights_2048[4096]; +extern const float32_t Weights_8192[16384]; + +#else +extern const float32_t Weights_128[128+2]; +extern const float32_t Weights_512[512+2]; +extern const float32_t Weights_2048[2048+2]; +extern const float32_t Weights_8192[8192+2]; +#endif +extern const float32_t cos_factors_128[128]; +extern const float32_t cos_factors_512[512]; +extern const float32_t cos_factors_2048[2048]; +extern const float32_t cos_factors_8192[8192]; + +/* floating-point bit reversal tables */ +#define CSIBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20 ) +#define CSIBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48 ) +#define CSIBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56 ) +#define CSIBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) +#define CSIBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) +#define CSIBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define CSIBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) +#define CSIBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) +#define CSIBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t csiBitRevIndexTable16[CSIBITREVINDEXTABLE_16_TABLE_LENGTH]; +extern const uint16_t csiBitRevIndexTable32[CSIBITREVINDEXTABLE_32_TABLE_LENGTH]; +extern const uint16_t csiBitRevIndexTable64[CSIBITREVINDEXTABLE_64_TABLE_LENGTH]; +extern const uint16_t csiBitRevIndexTable128[CSIBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t csiBitRevIndexTable256[CSIBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t csiBitRevIndexTable512[CSIBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t csiBitRevIndexTable1024[CSIBITREVINDEXTABLE_1024_TABLE_LENGTH]; +extern const uint16_t csiBitRevIndexTable2048[CSIBITREVINDEXTABLE_2048_TABLE_LENGTH]; +extern const uint16_t csiBitRevIndexTable4096[CSIBITREVINDEXTABLE_4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define CSIBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12 ) +#define CSIBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24 ) +#define CSIBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56 ) +#define CSIBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112 ) +#define CSIBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240 ) +#define CSIBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480 ) +#define CSIBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) +#define CSIBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define CSIBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t csiBitRevIndexTable_fixed_16[CSIBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; +extern const uint16_t csiBitRevIndexTable_fixed_32[CSIBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; +extern const uint16_t csiBitRevIndexTable_fixed_64[CSIBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; +extern const uint16_t csiBitRevIndexTable_fixed_128[CSIBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; +extern const uint16_t csiBitRevIndexTable_fixed_256[CSIBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; +extern const uint16_t csiBitRevIndexTable_fixed_512[CSIBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; +extern const uint16_t csiBitRevIndexTable_fixed_1024[CSIBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t csiBitRevIndexTable_fixed_2048[CSIBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t csiBitRevIndexTable_fixed_4096[CSIBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* CSI_COMMON_TABLES_H */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csi_const_structs.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csi_const_structs.h new file mode 100644 index 00000000..09f8f367 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csi_const_structs.h @@ -0,0 +1,157 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file csi_const_structs.h + * @brief Constant structs that are initialized for user convenience. + * @version V1.0 + * @date Feb. 2020 + ******************************************************************************/ + + +#ifndef _RISCV_CONST_STRUCTS_H +#define _RISCV_CONST_STRUCTS_H + +#include "csi_math.h" +#include "csi_common_tables.h" + +extern const csi_cfft_instance_f32 csi_cfft_radix4_fast_sR_f32_len16; +extern const csi_cfft_instance_f32 csi_cfft_radix4_fast_sR_f32_len32; +extern const csi_cfft_instance_f32 csi_cfft_radix4_fast_sR_f32_len64; +extern const csi_cfft_instance_f32 csi_cfft_radix4_fast_sR_f32_len128; +extern const csi_cfft_instance_f32 csi_cfft_radix4_fast_sR_f32_len256; +extern const csi_cfft_instance_f32 csi_cfft_radix4_fast_sR_f32_len512; +extern const csi_cfft_instance_f32 csi_cfft_radix4_fast_sR_f32_len1024; +extern const csi_cfft_instance_f32 csi_cfft_radix4_fast_sR_f32_len2048; +extern const csi_cfft_instance_f32 csi_cfft_radix4_fast_sR_f32_len4096; + +extern const csi_cfft_instance_f32 csi_cfft_radix2_sR_f32_len16; +extern const csi_cfft_instance_f32 csi_cfft_radix2_sR_f32_len32; +extern const csi_cfft_instance_f32 csi_cfft_radix2_sR_f32_len64; +extern const csi_cfft_instance_f32 csi_cfft_radix2_sR_f32_len128; +extern const csi_cfft_instance_f32 csi_cfft_radix2_sR_f32_len256; +extern const csi_cfft_instance_f32 csi_cfft_radix2_sR_f32_len512; +extern const csi_cfft_instance_f32 csi_cfft_radix2_sR_f32_len1024; +extern const csi_cfft_instance_f32 csi_cfft_radix2_sR_f32_len2048; +extern const csi_cfft_instance_f32 csi_cfft_radix2_sR_f32_len4096; + +extern const csi_cfft_instance_f32 csi_cfft_radix4_sR_f32_len16; +extern const csi_cfft_instance_f32 csi_cfft_radix4_sR_f32_len32; +extern const csi_cfft_instance_f32 csi_cfft_radix4_sR_f32_len64; +extern const csi_cfft_instance_f32 csi_cfft_radix4_sR_f32_len128; +extern const csi_cfft_instance_f32 csi_cfft_radix4_sR_f32_len256; +extern const csi_cfft_instance_f32 csi_cfft_radix4_sR_f32_len512; +extern const csi_cfft_instance_f32 csi_cfft_radix4_sR_f32_len1024; +extern const csi_cfft_instance_f32 csi_cfft_radix4_sR_f32_len2048; +extern const csi_cfft_instance_f32 csi_cfft_radix4_sR_f32_len4096; + +extern const csi_cfft_instance_f32 csi_cfft_sR_f32_len16 ; +extern const csi_cfft_instance_f32 csi_cfft_sR_f32_len32 ; +extern const csi_cfft_instance_f32 csi_cfft_sR_f32_len64 ; +extern const csi_cfft_instance_f32 csi_cfft_sR_f32_len128 ; +extern const csi_cfft_instance_f32 csi_cfft_sR_f32_len256 ; +extern const csi_cfft_instance_f32 csi_cfft_sR_f32_len512 ; +extern const csi_cfft_instance_f32 csi_cfft_sR_f32_len1024 ; +extern const csi_cfft_instance_f32 csi_cfft_sR_f32_len2048 ; +extern const csi_cfft_instance_f32 csi_cfft_sR_f32_len4096 ; +extern const csi_cfft_instance_q31 csi_cfft_sR_q31_len16 ; +extern const csi_cfft_instance_q31 csi_cfft_sR_q31_len32 ; +extern const csi_cfft_instance_q31 csi_cfft_sR_q31_len64 ; +extern const csi_cfft_instance_q31 csi_cfft_sR_q31_len128 ; +extern const csi_cfft_instance_q31 csi_cfft_sR_q31_len256 ; +extern const csi_cfft_instance_q31 csi_cfft_sR_q31_len512 ; +extern const csi_cfft_instance_q31 csi_cfft_sR_q31_len1024 ; +extern const csi_cfft_instance_q31 csi_cfft_sR_q31_len2048 ; +extern const csi_cfft_instance_q31 csi_cfft_sR_q31_len4096 ; +extern const csi_cfft_instance_q15 csi_cfft_sR_q15_len16 ; +extern const csi_cfft_instance_q15 csi_cfft_sR_q15_len32 ; +extern const csi_cfft_instance_q15 csi_cfft_sR_q15_len64 ; +extern const csi_cfft_instance_q15 csi_cfft_sR_q15_len128 ; +extern const csi_cfft_instance_q15 csi_cfft_sR_q15_len256 ; +extern const csi_cfft_instance_q15 csi_cfft_sR_q15_len512 ; +extern const csi_cfft_instance_q15 csi_cfft_sR_q15_len1024 ; +extern const csi_cfft_instance_q15 csi_cfft_sR_q15_len2048 ; +extern const csi_cfft_instance_q15 csi_cfft_sR_q15_len4096 ; +extern const csi_rfft_fast_instance_f32 csi_rfft_sR_f32_len32 ; +extern const csi_rfft_fast_instance_f32 csi_rfft_sR_f32_len64 ; +extern const csi_rfft_fast_instance_f32 csi_rfft_sR_f32_len128 ; +extern const csi_rfft_fast_instance_f32 csi_rfft_sR_f32_len256 ; +extern const csi_rfft_fast_instance_f32 csi_rfft_sR_f32_len512 ; +extern const csi_rfft_fast_instance_f32 csi_rfft_sR_f32_len1024 ; +extern const csi_rfft_fast_instance_f32 csi_rfft_sR_f32_len2048 ; +extern const csi_rfft_fast_instance_f32 csi_rfft_sR_f32_len4096 ; +extern const csi_rfft_fast_instance_f32 csi_rfft_sR_f32_len8192 ; +extern const csi_rfft_instance_q31 csi_rfft_sR_q31_len32 ; +extern const csi_rfft_instance_q31 csi_rfft_sR_q31_len64 ; +extern const csi_rfft_instance_q31 csi_rfft_sR_q31_len128 ; +extern const csi_rfft_instance_q31 csi_rfft_sR_q31_len256 ; +extern const csi_rfft_instance_q31 csi_rfft_sR_q31_len512 ; +extern const csi_rfft_instance_q31 csi_rfft_sR_q31_len1024 ; +extern const csi_rfft_instance_q31 csi_rfft_sR_q31_len2048 ; +extern const csi_rfft_instance_q31 csi_rfft_sR_q31_len4096 ; +extern const csi_rfft_instance_q31 csi_rfft_sR_q31_len8192 ; +extern const csi_rfft_instance_q15 csi_rfft_sR_q15_len32 ; +extern const csi_rfft_instance_q15 csi_rfft_sR_q15_len64 ; +extern const csi_rfft_instance_q15 csi_rfft_sR_q15_len128 ; +extern const csi_rfft_instance_q15 csi_rfft_sR_q15_len256 ; +extern const csi_rfft_instance_q15 csi_rfft_sR_q15_len512 ; +extern const csi_rfft_instance_q15 csi_rfft_sR_q15_len1024 ; +extern const csi_rfft_instance_q15 csi_rfft_sR_q15_len2048 ; +extern const csi_rfft_instance_q15 csi_rfft_sR_q15_len4096 ; +extern const csi_rfft_instance_q15 csi_rfft_sR_q15_len8192 ; +extern const csi_rfft_instance_f32 csi_inv_rfft_sR_f32_len32; +extern const csi_rfft_instance_f32 csi_inv_rfft_sR_f32_len64; +extern const csi_rfft_instance_f32 csi_inv_rfft_sR_f32_len128; +extern const csi_rfft_instance_f32 csi_inv_rfft_sR_f32_len256; +extern const csi_rfft_instance_f32 csi_inv_rfft_sR_f32_len512; +extern const csi_rfft_instance_f32 csi_inv_rfft_sR_f32_len1024; +extern const csi_rfft_instance_f32 csi_inv_rfft_sR_f32_len2048; +extern const csi_rfft_instance_f32 csi_inv_rfft_sR_f32_len4096; +extern const csi_rfft_instance_f32 csi_inv_rfft_sR_f32_len8192; +extern const csi_rfft_instance_q31 csi_inv_rfft_sR_q31_len32; +extern const csi_rfft_instance_q31 csi_inv_rfft_sR_q31_len64; +extern const csi_rfft_instance_q31 csi_inv_rfft_sR_q31_len128; +extern const csi_rfft_instance_q31 csi_inv_rfft_sR_q31_len256; +extern const csi_rfft_instance_q31 csi_inv_rfft_sR_q31_len512; +extern const csi_rfft_instance_q31 csi_inv_rfft_sR_q31_len1024; +extern const csi_rfft_instance_q31 csi_inv_rfft_sR_q31_len2048; +extern const csi_rfft_instance_q31 csi_inv_rfft_sR_q31_len4096; +extern const csi_rfft_instance_q31 csi_inv_rfft_sR_q31_len8192; +extern const csi_rfft_instance_q15 csi_inv_rfft_sR_q15_len32; +extern const csi_rfft_instance_q15 csi_inv_rfft_sR_q15_len64; +extern const csi_rfft_instance_q15 csi_inv_rfft_sR_q15_len128; +extern const csi_rfft_instance_q15 csi_inv_rfft_sR_q15_len256; +extern const csi_rfft_instance_q15 csi_inv_rfft_sR_q15_len512; +extern const csi_rfft_instance_q15 csi_inv_rfft_sR_q15_len1024; +extern const csi_rfft_instance_q15 csi_inv_rfft_sR_q15_len2048; +extern const csi_rfft_instance_q15 csi_inv_rfft_sR_q15_len4096; +extern const csi_rfft_instance_q15 csi_inv_rfft_sR_q15_len8192; +extern const csi_dct4_instance_q31 csi_dct4_sR_q31_len128; +extern const csi_dct4_instance_q31 csi_dct4_sR_q31_len512; +extern const csi_dct4_instance_q31 csi_dct4_sR_q31_len2048; +extern const csi_dct4_instance_q31 csi_dct4_sR_q31_len8192; +extern const csi_dct4_instance_q15 csi_dct4_sR_q15_len128; +extern const csi_dct4_instance_q15 csi_dct4_sR_q15_len512; +extern const csi_dct4_instance_q15 csi_dct4_sR_q15_len2048; +extern const csi_dct4_instance_q15 csi_dct4_sR_q15_len8192; +extern const csi_dct4_instance_f32 csi_dct4_sR_f32_len128; +extern const csi_dct4_instance_f32 csi_dct4_sR_f32_len512; +extern const csi_dct4_instance_f32 csi_dct4_sR_f32_len2048; +extern const csi_dct4_instance_f32 csi_dct4_sR_f32_len8192; + +#endif diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csi_instance.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csi_instance.h new file mode 100644 index 00000000..a1aa7131 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csi_instance.h @@ -0,0 +1,1879 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file csi_instance.h + * @brief Some common define + * @version V1.0 + * @date Feb. 2020 + ******************************************************************************/ + + +#ifndef _CSI_INSTANCE_H +#define _CSI_INSTANCE_H + +#ifdef __cplusplus +extern "C" +{ +#endif + + +#include +#include +#include +#include +#include +#ifndef __CK860__ +#include "csi_core.h" +#else +#include +#endif + +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT + +#define F64_MAX ((float64_t)DBL_MAX) +#define F32_MAX ((float32_t)FLT_MAX) + +#define F64_MIN (-DBL_MAX) +#define F32_MIN (-FLT_MAX) + +#define F64_ABSMAX ((float64_t)DBL_MAX) +#define F32_ABSMAX ((float32_t)FLT_MAX) + +#define F64_ABSMIN ((float64_t)0.0) +#define F32_ABSMIN ((float32_t)0.0) + +#define Q31_MAX ((q31_t)(0x7FFFFFFFL)) +#define Q15_MAX ((q15_t)(0x7FFF)) +#define Q7_MAX ((q7_t)(0x7F)) +#define Q31_MIN ((q31_t)(0x80000000L)) +#define Q15_MIN ((q15_t)(0x8000)) +#define Q7_MIN ((q7_t)(0x80)) + +#define Q31_ABSMAX ((q31_t)(0x7FFFFFFFL)) +#define Q15_ABSMAX ((q15_t)(0x7FFF)) +#define Q7_ABSMAX ((q7_t)(0x7F)) +#define Q31_ABSMIN ((q31_t)0) +#define Q15_ABSMIN ((q15_t)0) +#define Q7_ABSMIN ((q7_t)0) + +/** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 ((q31_t)(0x100)) +#define DELTA_Q15 ((q15_t)0x5) +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #define ALIGN4 __attribute__((aligned(4))) +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + +/** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + +#define __STATIC_FORCEINLINE static inline __attribute__((unused)) +#define CSI_NEWTON_SQRTF +#ifdef __CK860__ +#define __STATIC_INLINE static inline __attribute__((unused)) + +#define __ALWAYS_STATIC_INLINE __attribute__((always_inline)) static inline + +#endif + + +/** + * @brief Macros required for SINE and COSINE Controller functions + */ +/* 1.31(q31) Fixed value of 2/360 */ +/* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + +/** + * @brief Macros for complex numbers + */ + +/* Dimension C vector space */ +#define CMPLX_DIM 2 + +/** + * @brief Error status returned by some functions in the library. + */ + +typedef enum { + CSI_MATH_SUCCESS = 0, /**< No error */ + CSI_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + CSI_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + CSI_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation */ + CSI_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + CSI_MATH_SINGULAR = -5, /**< Input matrix is singular and cannot be inverted */ + CSI_MATH_TEST_FAILURE = -6 /**< Test Failed */ +} csi_status; + +/** + * @brief 8-bit fractional data type in 1.7 format. + */ +typedef int8_t q7_t; + +/** + * @brief 16-bit fractional data type in 1.15 format. + */ +typedef int16_t q15_t; + +/** + * @brief 32-bit fractional data type in 1.31 format. + */ +typedef int32_t q31_t; + +/** + * @brief 64-bit fractional data type in 1.63 format. + */ +typedef int64_t q63_t; + +/** + * @brief 32-bit floating-point type definition. + */ +typedef float float32_t; + +/** + * @brief 64-bit floating-point type definition. + */ +typedef double float64_t; + +/** + @brief definition to read/write two 16 bit values. + @deprecated + */ +#define __SIMD32_TYPE int32_t +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr)) +#define __SIMD64(addr) (*( int64_t **) & (addr)) + +#define STEP(x) (x) <= 0 ? 0 : 1 +#define SQ(x) ((x) * (x)) + +__ALWAYS_STATIC_INLINE int32_t __SSAT_31(int32_t x) +{ + int32_t res = x; + if (x > 0x3fffffff) { + res = 0x3fffffff; + } else if (x < -1073741824) { + res = -1073741824; + } + + return res; +} + +__ALWAYS_STATIC_INLINE int32_t __SSAT_16(int32_t x) +{ + int32_t res = x; + if (x > 0x7fff) { + res = 0x7fff; + } else if (x < -32768) { + res = -32768; + } + + return res; +} + +__ALWAYS_STATIC_INLINE int32_t __SSAT_8(int32_t x) +{ + int32_t res = x; + if (x > 0x7f) { + res = 0x7f; + } else if (x < -128) { + res = -128; + } + + return res; +} + +/** + @brief Read 2 Q15 from Q15 pointer. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2 ( + q15_t * pQ15) +{ + q31_t val; + memcpy (&val, pQ15, 4); + return (val); +} + +/** + @brief Read 2 Q15 from Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2_ia ( + q15_t ** pQ15) +{ + q31_t val; + memcpy (&val, *pQ15, 4); + *pQ15 += 2; + return (val); +} + +/** + @brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2_da ( + q15_t ** pQ15) +{ + q31_t val; + memcpy (&val, *pQ15, 4); + *pQ15 -= 2; + return (val); +} + +/** + @brief Write 2 Q15 to Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x2_ia ( + q15_t ** pQ15, + q31_t value) +{ + q31_t val = value; + memcpy (*pQ15, &val, 4); + *pQ15 += 2; +} + +/** + @brief Write 2 Q15 to Q15 pointer. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x2 ( + q15_t * pQ15, + q31_t value) +{ + q31_t val = value; + memcpy (pQ15, &val, 4); +} + + +/** + @brief Read 4 Q7 from Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q7x4_ia ( + q7_t ** pQ7) +{ + q31_t val; + memcpy (&val, *pQ7, 4); + *pQ7 += 4; + return (val); +} + +/** + @brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards. + @param[in] pQ7 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q7x4_da ( + q7_t ** pQ7) +{ + q31_t val; + memcpy (&val, *pQ7, 4); + *pQ7 -= 4; + return (val); +} + +/** + @brief Write 4 Q7 to Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q7x4_ia ( + q7_t ** pQ7, + q31_t value) +{ + q31_t val = value; + memcpy (*pQ7, &val, 4); + *pQ7 += 4; +} + +#ifdef __CK860__ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data) +{ + if (data == 0U) { + return 32U; + } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) { + count += 1U; + mask = mask >> 1U; + } + + return count; +} + +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + + if (val > max) { + return max; + + } else if (val < min) { + return min; + } + } + + return val; +} + +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) { + const uint32_t max = ((1U << sat) - 1U); + + if (val > (int32_t)max) { + return max; + + } else if (val < 0) { + return 0U; + } + } + + return (uint32_t)val; +} +#endif +/** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + + +/** +* @brief definition to pack four 8 bit values. +*/ +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) + +/** + * @brief Clips Q63 to Q31 values. + */ +__STATIC_FORCEINLINE q31_t clip_q63_to_q31( + q63_t x) +{ + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; +} + +/** + * @brief Clips Q63 to Q15 values. + */ +__STATIC_FORCEINLINE q15_t clip_q63_to_q15( + q63_t x) +{ + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); +} + +/** + * @brief Clips Q31 to Q7 values. + */ +__STATIC_FORCEINLINE q7_t clip_q31_to_q7( + q31_t x) +{ + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; +} + +/** + * @brief Clips Q31 to Q15 values. + */ +__STATIC_FORCEINLINE q15_t clip_q31_to_q15( + q31_t x) +{ + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; +} + +/** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ +__STATIC_FORCEINLINE q63_t mult32x64( + q63_t x, + q31_t y) +{ + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y) ) ); +} + +/** + * @brief Integer exponentiation + * @param[in] x value + * @param[in] nb integer exponent >= 1 + * @return x^nb + * + */ +__STATIC_INLINE float32_t csi_exponent_f32(float32_t x, int32_t nb) +{ + float32_t r = x; + nb --; + + while(nb > 0) { + r = r * x; + nb--; + } + + return(r); +} + +/** + * @brief 64-bit to 32-bit unsigned normalization + * @param[in] in is input unsigned long long value + * @param[out] normalized is the 32-bit normalized value + * @param[out] norm is norm scale + */ +__STATIC_INLINE void csi_norm_64_to_32u(uint64_t in, int32_t * normalized, int32_t *norm) +{ + int32_t n1; + int32_t hi = (int32_t) (in >> 32); + int32_t lo = (int32_t) ((in << 32) >> 32); + n1 = __CLZ(hi) - 32; + + if (!n1) { + /* + * input fits in 32-bit + */ + n1 = __CLZ(lo); + + if (!n1) { + /* + * MSB set, need to scale down by 1 + */ + *norm = -1; + *normalized = (((uint32_t) lo) >> 1); + + } else { + if (n1 == 32) { + /* + * input is zero + */ + *norm = 0; + *normalized = 0; + + } else { + /* + * 32-bit normalization + */ + *norm = n1 - 1; + *normalized = lo << *norm; + } + } + + } else { + /* + * input fits in 64-bit + */ + n1 = 1 - n1; + *norm = -n1; + /* + * 64 bit normalization + */ + *normalized = (((uint32_t) lo) >> n1) | (hi << (32 - n1)); + } +} + +__STATIC_INLINE q31_t csi_div_q63_to_q31(q63_t num, q31_t den) +{ + q31_t result; + uint64_t absNum; + int32_t normalized; + int32_t norm; + /* + * if sum fits in 32bits + * avoid costly 64-bit division + */ + absNum = num > 0 ? num : -num; + csi_norm_64_to_32u(absNum, &normalized, &norm); + + if (norm > 0) + /* + * 32-bit division + */ + result = (q31_t) num / den; + + else + /* + * 64-bit division + */ + result = (q31_t) (num / den); + + return result; +} + +/* + * @brief C custom defined intrinsic functions + */ +#ifdef __CK860__ +/* + * @brief C custom defined QADD8 + */ +__STATIC_FORCEINLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) +{ + q31_t r, s, t, u; + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); +} + + +/* + * @brief C custom defined QSUB8 + */ +__STATIC_FORCEINLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) +{ + q31_t r, s, t, u; + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); +} + + +/* + * @brief C custom defined QADD16 + */ +__STATIC_FORCEINLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) +{ + /* q31_t r, s; without initialisation 'csi_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + return ((uint32_t)((s << 16) | (r ))); +} + + +/* + * @brief C custom defined SHADD16 + */ +__STATIC_FORCEINLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) +{ + q31_t r, s; + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + return ((uint32_t)((s << 16) | (r ))); +} + + +/* + * @brief C custom defined QSUB16 + */ +__STATIC_FORCEINLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) +{ + q31_t r, s; + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + return ((uint32_t)((s << 16) | (r ))); +} + + +/* + * @brief C custom defined SHSUB16 + */ +__STATIC_FORCEINLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) +{ + q31_t r, s; + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + return ((uint32_t)((s << 16) | (r ))); +} + + +/* + * @brief C custom defined QASX + */ +__STATIC_FORCEINLINE uint32_t __QASX( + uint32_t x, + uint32_t y) +{ + q31_t r, s; + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + return ((uint32_t)((s << 16) | (r ))); +} + + +/* + * @brief C custom defined SHASX + */ +__STATIC_FORCEINLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) +{ + q31_t r, s; + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + return ((uint32_t)((s << 16) | (r ))); +} + + +/* + * @brief C custom defined QSAX + */ +__STATIC_FORCEINLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) +{ + q31_t r, s; + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + return ((uint32_t)((s << 16) | (r ))); +} + + +/* + * @brief C custom defined SHSAX + */ +__STATIC_FORCEINLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) +{ + q31_t r, s; + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + return ((uint32_t)((s << 16) | (r ))); +} + + +/* + * @brief C custom defined SMUSDX + */ +__STATIC_FORCEINLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); +} + +/* + * @brief C custom defined SMUADX + */ +__STATIC_FORCEINLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); +} + + +/* + * @brief C custom defined QADD + */ +__STATIC_FORCEINLINE int32_t __QADD( + int32_t x, + int32_t y) +{ + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); +} + + +/* + * @brief C custom defined QSUB + */ +__STATIC_FORCEINLINE int32_t __QSUB( + int32_t x, + int32_t y) +{ + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); +} + + +/* + * @brief C custom defined SMLAD + */ +__STATIC_FORCEINLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); +} + + +/* + * @brief C custom defined SMLADX + */ +__STATIC_FORCEINLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); +} + + +/* + * @brief C custom defined SMLSDX + */ +__STATIC_FORCEINLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); +} + + +/* + * @brief C custom defined SMLALD + */ +__STATIC_FORCEINLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) +{ + /* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); +} + + +/* + * @brief C custom defined SMLALDX + */ +__STATIC_FORCEINLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) +{ + /* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); +} + + +/* + * @brief C custom defined SMUAD + */ +__STATIC_FORCEINLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); +} + + +/* + * @brief C custom defined SMUSD + */ +__STATIC_FORCEINLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); +} + + +/* + * @brief C custom defined SXTB16 + */ +__STATIC_FORCEINLINE uint32_t __SXTB16( + uint32_t x) +{ + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); +} +/* + * @brief C custom defined SMMLA + */ +__STATIC_FORCEINLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) +{ + return (sum + (int32_t) (((int64_t) x * y) >> 32)); +} +#endif +/** + * @brief Instance structure for the Q7 FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ +} csi_fir_instance_q7; + +/** + * @brief Instance structure for the Q15 FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ +} csi_fir_instance_q15; + +/** + * @brief Instance structure for the Q31 FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ +} csi_fir_instance_q31; + +/** + * @brief Instance structure for the floating-point FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ +} csi_fir_instance_f32; + +/** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ +typedef struct { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ +} csi_biquad_casd_df1_inst_q15; + +/** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ +typedef struct { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ +} csi_biquad_casd_df1_inst_q31; + +/** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ +typedef struct { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ +} csi_biquad_casd_df1_inst_f32; + +/** + * @brief Instance structure for the floating-point matrix structure. + */ +typedef struct { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ +} csi_matrix_instance_f32; + + +/** + * @brief Instance structure for the floating-point matrix structure. + */ +typedef struct { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ +} csi_matrix_instance_f64; + +/** + * @brief Instance structure for the Q15 matrix structure. + */ +typedef struct { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ +} csi_matrix_instance_q15; + +/** + * @brief Instance structure for the Q31 matrix structure. + */ +typedef struct { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ +} csi_matrix_instance_q31; + +/** + * @brief Instance structure for the Q15 PID Control. + */ +typedef struct { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q15_t A1; + q15_t A2; + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ +} csi_pid_instance_q15; + +/** + * @brief Instance structure for the Q31 PID Control. + */ +typedef struct { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ +} csi_pid_instance_q31; + +/** + * @brief Instance structure for the floating-point PID Control. + */ +typedef struct { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ +} csi_pid_instance_f32; + +/** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ +typedef struct { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ +} csi_linear_interp_instance_f32; + +/** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ +} csi_bilinear_interp_instance_f32; + +/** +* @brief Instance structure for the Q31 bilinear interpolation function. +*/ +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ +} csi_bilinear_interp_instance_q31; + +/** +* @brief Instance structure for the Q15 bilinear interpolation function. +*/ +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ +} csi_bilinear_interp_instance_q15; + +/** +* @brief Instance structure for the Q15 bilinear interpolation function. +*/ +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ +} csi_bilinear_interp_instance_q7; + +/** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} csi_cfft_radix2_instance_q15; + +/** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} csi_cfft_radix4_instance_q15; + +/** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} csi_cfft_radix2_instance_q31; + + +/** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} csi_cfft_radix4_instance_q31; + +/** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ +} csi_cfft_radix2_instance_f32; + +/** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ +} csi_cfft_radix4_instance_f32; + +/** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +} csi_cfft_instance_q15; + +/** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +} csi_cfft_instance_q31; + + +/** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +} csi_cfft_instance_f32; + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + q31_t *pTwiddleAReal; /**< points to the A real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the B real twiddle factor table. */ + const csi_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } csi_rfft_fast_instance_q31; + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + q15_t *pTwiddleAReal; /**< points to the A real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the B real twiddle factor table. */ + const csi_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } csi_rfft_fast_instance_q15; + +/** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ +typedef struct { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ +#if (!defined __riscv_xthead) && (defined __riscv) + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ +#endif + const csi_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ +} csi_rfft_instance_q15; + + +/** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ +typedef struct { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ +#if (!defined __riscv_xthead) && (defined __riscv) + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ +#endif + const csi_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ +} csi_rfft_instance_q31; + + +/** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + csi_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ +} csi_rfft_instance_f32; + +/** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct { + csi_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ +} csi_rfft_fast_instance_f32 ; + +/** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ +typedef struct { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + const float32_t *pTwiddle; /**< points to the twiddle factor table. */ + const float32_t *pCosFactor; /**< points to the cosFactor table. */ + csi_rfft_fast_instance_f32 *pRfft; /**< points to the real FFT instance. */ + csi_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ +} csi_dct4_instance_f32; + + +/** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ +typedef struct { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const q31_t *pCosFactor; /**< points to the cosFactor table. */ + csi_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + csi_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ +} csi_dct4_instance_q31; + + +/** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ +typedef struct { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const q15_t *pCosFactor; /**< points to the cosFactor table. */ + csi_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + csi_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ +} csi_dct4_instance_q15; + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + csi_rfft_fast_instance_q15 *pRfft; /**< points to the real FFT instance. */ + csi_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } csi_dct4_fast_instance_q15; + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + csi_rfft_fast_instance_q31 *pRfft; /**< points to the real FFT instance. */ + csi_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } csi_dct4_fast_instance_q31; + + csi_status csi_dct4_init_q31( + csi_dct4_instance_q31 * S, + csi_rfft_instance_q31 * S_RFFT, + csi_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + void csi_dct4_q31( + const csi_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + void csi_dct4_fast_q31( + const csi_dct4_fast_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + +/** + * @brief Instance structure for the Q15 FIR decimator. + */ +typedef struct { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ +} csi_fir_decimate_instance_q15; + +/** + * @brief Instance structure for the Q31 FIR decimator. + */ +typedef struct { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ +} csi_fir_decimate_instance_q31; + +/** + @brief Instance structure for floating-point FIR decimator. + */ +typedef struct { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ +} csi_fir_decimate_instance_f32; + +/** + * @brief Instance structure for the Q15 FIR interpolator. + */ +typedef struct { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ +} csi_fir_interpolate_instance_q15; + +/** + * @brief Instance structure for the Q31 FIR interpolator. + */ +typedef struct { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ +} csi_fir_interpolate_instance_q31; + +/** + * @brief Instance structure for the floating-point FIR interpolator. + */ +typedef struct { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ +} csi_fir_interpolate_instance_f32; + + +/** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ +typedef struct { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ +} csi_biquad_cas_df1_32x64_ins_q31; + +/** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ +typedef struct { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ +} csi_biquad_cascade_df2T_instance_f32; + +/** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ +typedef struct { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ +} csi_biquad_cascade_stereo_df2T_instance_f32; + +/** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ +typedef struct { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ +} csi_biquad_cascade_df2T_instance_f64; + +/** + * @brief Instance structure for the Q15 FIR lattice filter. + */ +typedef struct { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ +} csi_fir_lattice_instance_q15; + +/** + * @brief Instance structure for the Q31 FIR lattice filter. + */ +typedef struct { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ +} csi_fir_lattice_instance_q31; + +/** + * @brief Instance structure for the floating-point FIR lattice filter. + */ +typedef struct { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ +} csi_fir_lattice_instance_f32; + + +/** + * @brief Instance structure for the Q15 IIR lattice filter. + */ +typedef struct { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ +} csi_iir_lattice_instance_q15; + +/** + * @brief Instance structure for the Q31 IIR lattice filter. + */ +typedef struct { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ +} csi_iir_lattice_instance_q31; + +/** + * @brief Instance structure for the floating-point IIR lattice filter. + */ +typedef struct { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ +} csi_iir_lattice_instance_f32; + + +/** + * @brief Instance structure for the floating-point LMS filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ +} csi_lms_instance_f32; + + +/** + * @brief Instance structure for the Q15 LMS filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ +} csi_lms_instance_q15; + + +/** + * @brief Instance structure for the Q31 LMS filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ +} csi_lms_instance_q31; + + +/** + * @brief Instance structure for the floating-point normalized LMS filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ +} csi_lms_norm_instance_f32; + +/** + * @brief Instance structure for the Q31 normalized LMS filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ +} csi_lms_norm_instance_q31; + + +/** + * @brief Instance structure for the Q15 normalized LMS filter. + */ +typedef struct { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ +} csi_lms_norm_instance_q15; + +/** + * @brief Instance structure for the floating-point sparse FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} csi_fir_sparse_instance_f32; + +/** + * @brief Instance structure for the Q31 sparse FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} csi_fir_sparse_instance_q31; + +/** + * @brief Instance structure for the Q15 sparse FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} csi_fir_sparse_instance_q15; + +/** + * @brief Instance structure for the Q7 sparse FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} csi_fir_sparse_instance_q7; + + +/** +* @brief Struct for specifying SVM Kernel +* +*/ +typedef enum { + CSI_ML_KERNEL_LINEAR = 0, + /**< Linear kernel */ + CSI_ML_KERNEL_POLYNOMIAL = 1, + /**< Polynomial kernel */ + CSI_ML_KERNEL_RBF = 2, + /**< Radial Basis Function kernel */ + CSI_ML_KERNEL_SIGMOID = 3 + /**< Sigmoid kernel */ +} csi_ml_kernel_type; + + + +/** + * @brief Instance structure for linear SVM prediction function. + */ +typedef struct { + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ +} csi_svm_linear_instance_f32; + + +/** + * @brief Instance structure for polynomial SVM prediction function. + */ +typedef struct { + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + int32_t degree; /**< Polynomial degree */ + float32_t coef0; /**< Polynomial constant */ + float32_t gamma; /**< Gamma factor */ +} csi_svm_polynomial_instance_f32; + +/** + * @brief Instance structure for rbf SVM prediction function. + */ +typedef struct { + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float32_t gamma; /**< Gamma factor */ +} csi_svm_rbf_instance_f32; + +/** + * @brief Instance structure for sigmoid SVM prediction function. + */ +typedef struct { + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float32_t coef0; /**< Independant constant */ + float32_t gamma; /**< Gamma factor */ +} csi_svm_sigmoid_instance_f32; + +/** + * @brief Instance structure for Naive Gaussian Bayesian estimator. + */ +typedef struct { + uint32_t vectorDimension; /**< Dimension of vector space */ + uint32_t numberOfClasses; /**< Number of different classes */ + const float32_t *theta; /**< Mean values for the Gaussians */ + const float32_t *sigma; /**< Variances for the Gaussians */ + const float32_t *classPriors; /**< Class prior probabilities */ + float32_t epsilon; /**< Additive value to variances */ +} csi_gaussian_naive_bayes_instance_f32; + +#ifdef CSI_SIMD +/* SMMLAR */ +__ALWAYS_STATIC_INLINE int32_t multAcc_32x32_keep32_R(int32_t a, int32_t x, int32_t y) +{ + __ASM volatile("mula.s32.rhs %0, %1, %2\n\t" + :"=r" (a), "=r" (x), "=r" (y) : "0" (a), "1" (x), "2" (y)); + return a; +} + +/* SMMLSR */ +__ALWAYS_STATIC_INLINE int32_t multSub_32x32_keep32_R(int32_t a, int32_t x, int32_t y) +{ + __ASM volatile("muls.s32.rhs %0, %1, %2\n\t" + :"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y)); + return a; +} + +/* SMMULR */ +__ALWAYS_STATIC_INLINE int32_t mult_32x32_keep32_R(int32_t x, int32_t y) +{ + int32_t a; + __ASM volatile("mul.s32.rh %0, %1, %2\n\t" + :"=r" (a), "=r" (x), "=r" (y): "1" (x), "2" (y)); + return a; +} + +/* SMMLA */ +__ALWAYS_STATIC_INLINE int32_t multAcc_32x32_keep32(int32_t a, int32_t x, int32_t y) +{ + __ASM volatile("mula.s32.hs %0, %1, %2\n\t" + :"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y)); + return a; +} + +/* SMMLS */ +__ALWAYS_STATIC_INLINE int32_t multSub_32x32_keep32(int32_t a, int32_t x, int32_t y) +{ + __ASM volatile("muls.s32.hs %0, %1, %2\n\t" + :"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y)); + return a; +} + +/* SMMUL */ +__ALWAYS_STATIC_INLINE int32_t mult_32x32_keep32(int32_t x, int32_t y) +{ + int32_t a; + __ASM volatile("mul.s32.h %0, %1, %2\n\t" + :"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y)); + return a; +} + +__ALWAYS_STATIC_INLINE int32_t multAcc_16x16_keep32(int32_t a, int16_t x, int16_t y) +{ + __ASM volatile("mulall.s16 %0, %1, %2\n\t" + :"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y)); + return a; +} + +__ALWAYS_STATIC_INLINE int64_t multAcc_16x16_keep64(int64_t a, int16_t x, int16_t y) +{ + __ASM volatile("mulall.s16.e %0, %1, %2\n\t" + :"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y)); + return a; +} + +__ALWAYS_STATIC_INLINE int64_t mult_32x32_keep64(int32_t x, int32_t y) +{ + int64_t a; + __ASM volatile("mul.s32 %0, %1, %2\n\t" + :"=r" (a), "=r" (x), "=r" (y): "1" (x), "2" (y)); + return a; +} + +__ALWAYS_STATIC_INLINE int64_t multAcc_32x32_keep64(int64_t a, int32_t x, int32_t y) +{ + __ASM volatile("mula.s32 %0, %1, %2\n\t" + :"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y)); + return a; +} + +__ALWAYS_STATIC_INLINE int32_t mult_32x32_dext_31(int32_t x, int32_t y) +{ + int64_t tmp1; + int32_t tmp2; + __ASM volatile("mul.s32 %0, %1, %2\n\t" + "dexti %3, %0, %R0, 31" + :"=r" (tmp1), "=r" (x), "=r" (y), "=r" (tmp2): "1" (x), "2" (y)); + return tmp2; +} + +__ALWAYS_STATIC_INLINE int32_t mult_32x32_dext_30(int32_t x, int32_t y) +{ + int64_t tmp1; + int32_t tmp2; + __ASM volatile("mul.s32 %0, %1, %2\n\t" + "dexti %3, %0, %R0, 30" + :"=r" (tmp1), "=r" (x), "=r" (y), "=r" (tmp2): "1" (x), "2" (y)); + return tmp2; +} + +__ALWAYS_STATIC_INLINE int32_t mult_32x32_dext_4(int32_t x, int32_t y) +{ + int64_t tmp1; + int32_t tmp2; + __ASM volatile("mul.s32 %0, %1, %2\n\t" + "dexti %3, %0, %R0, 4" + :"=r" (tmp1), "=r" (x), "=r" (y), "=r" (tmp2): "1" (x), "2" (y)); + return tmp2; +} + +__ALWAYS_STATIC_INLINE int32_t mult_32x32_dext_33(int32_t x, int32_t y) +{ + int64_t tmp1; + int32_t tmp2; + __ASM volatile("mul.s32 %0, %1, %2\n\t" + "asri %3, %R0, 1" + :"=r" (tmp1), "=r" (x), "=r" (y), "=r" (tmp2): "1" (x), "2" (y)); + return tmp2; +} + +__ALWAYS_STATIC_INLINE int32_t dext_31(int64_t x) +{ + int32_t tmp1; + __ASM volatile( + "dexti %0, %1, %R1, 31" + :"=r" (tmp1), "=r" (x) : "1" (x)); + return tmp1; +} + +__ALWAYS_STATIC_INLINE int32_t mult_l16xl16_keep32(int32_t x, int32_t y) +{ + int32_t a; + __ASM volatile("mulll.s16 %0, %1, %2\n\t" + :"=r" (a), "=r" (x), "=r" (y): "1" (x), "2" (y)); + return a; +} + +__ALWAYS_STATIC_INLINE int32_t mult_h16xl16_keep32(int32_t x, int32_t y) +{ + int32_t a; + __ASM volatile("mulhl.s16 %0, %1, %2\n\t" + :"=r" (a), "=r" (x), "=r" (y): "1" (x), "2" (y)); + return a; +} + +__ALWAYS_STATIC_INLINE int32_t mult_h16xh16_keep32(int32_t x, int32_t y) +{ + int32_t a; + __ASM volatile("mulhh.s16 %0, %1, %2\n\t" + :"=r" (a), "=r" (x), "=r" (y): "1" (x), "2" (y)); + return a; +} + +#else + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) +#endif +#ifdef __cplusplus +} +#endif + + +#endif /* _CSI_MATH_H */ + +/** + * + * End of file. + */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csi_math.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csi_math.h new file mode 100644 index 00000000..24eb063a --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csi_math.h @@ -0,0 +1,5739 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file csi_math.h + * @brief Some common define + * @version V1.0 + * @date Feb. 2020 + ******************************************************************************/ + + +#ifndef _CSI_MATH_H +#define _CSI_MATH_H + +#ifdef __cplusplus +extern "C" +{ +#endif + + +#include +#include +#include +#include +#include +#include "csi_instance.h" + + +/** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void csi_fir_q7( + const csi_fir_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ +void csi_fir_init_q7( + csi_fir_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + +/** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void csi_fir_q15( + const csi_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +/** + * @brief Processing function for the fast Q15 FIR filter (fast version). + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void csi_fir_fast_q15( + const csi_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns either + * CSI_MATH_SUCCESS if initialization was successful or + * CSI_MATH_ARGUMENT_ERROR if numTaps is not a supported value. + */ +csi_status csi_fir_init_q15( + csi_fir_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + +/** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void csi_fir_q31( + const csi_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Processing function for the fast Q31 FIR filter (fast version). + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void csi_fir_fast_q31( + const csi_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ +void csi_fir_init_q31( + csi_fir_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + +/** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void csi_fir_f32( + const csi_fir_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ +void csi_fir_init_f32( + csi_fir_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void csi_biquad_cascade_df1_q15( + const csi_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ +void csi_biquad_cascade_df1_init_q15( + csi_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + const q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + +/** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void csi_biquad_cascade_df1_fast_q15( + const csi_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +/** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void csi_biquad_cascade_df1_q31( + const csi_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void csi_biquad_cascade_df1_fast_q31( + const csi_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ +void csi_biquad_cascade_df1_init_q31( + csi_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + +/** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void csi_biquad_cascade_df1_f32( + const csi_biquad_casd_df1_inst_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ +void csi_biquad_cascade_df1_init_f32( + csi_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + +/** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. + */ +csi_status csi_mat_add_f32( + const csi_matrix_instance_f32 * pSrcA, + const csi_matrix_instance_f32 * pSrcB, + csi_matrix_instance_f32 * pDst); + +/** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. + */ +csi_status csi_mat_add_q15( + const csi_matrix_instance_q15 * pSrcA, + const csi_matrix_instance_q15 * pSrcB, + csi_matrix_instance_q15 * pDst); + +/** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. + */ +csi_status csi_mat_add_q31( + const csi_matrix_instance_q31 * pSrcA, + const csi_matrix_instance_q31 * pSrcB, + csi_matrix_instance_q31 * pDst); + +/** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. + */ +csi_status csi_mat_cmplx_mult_f32( + const csi_matrix_instance_f32 * pSrcA, + const csi_matrix_instance_f32 * pSrcB, + csi_matrix_instance_f32 * pDst); + +/** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. + */ +csi_status csi_mat_cmplx_mult_q15( + const csi_matrix_instance_q15 * pSrcA, + const csi_matrix_instance_q15 * pSrcB, + csi_matrix_instance_q15 * pDst); + +void csi_mult_q15xq31_sht( + q15_t * pSrcA, + q31_t * pSrcB, + uint32_t shiftValue, + uint32_t blockSize); + +/** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. + */ +csi_status csi_mat_cmplx_mult_q31( + const csi_matrix_instance_q31 * pSrcA, + const csi_matrix_instance_q31 * pSrcB, + csi_matrix_instance_q31 * pDst); + +/** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either CSI_MATH_SIZE_MISMATCH + * or CSI_MATH_SUCCESS based on the outcome of size checking. + */ +csi_status csi_mat_trans_f32( + const csi_matrix_instance_f32 * pSrc, + csi_matrix_instance_f32 * pDst); + +/** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either CSI_MATH_SIZE_MISMATCH + * or CSI_MATH_SUCCESS based on the outcome of size checking. + */ +csi_status csi_mat_trans_q15( + const csi_matrix_instance_q15 * pSrc, + csi_matrix_instance_q15 * pDst); + +/** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either CSI_MATH_SIZE_MISMATCH + * or CSI_MATH_SUCCESS based on the outcome of size checking. + */ +csi_status csi_mat_trans_q31( + const csi_matrix_instance_q31 * pSrc, + csi_matrix_instance_q31 * pDst); + +/** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. + */ +csi_status csi_mat_mult_f32( + const csi_matrix_instance_f32 * pSrcA, + const csi_matrix_instance_f32 * pSrcB, + csi_matrix_instance_f32 * pDst); + +/** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. + */ +csi_status csi_mat_mult_q15( + const csi_matrix_instance_q15 * pSrcA, + const csi_matrix_instance_q15 * pSrcB, + csi_matrix_instance_q15 * pDst); + + csi_status csi_mat_mult_trans_q15( + const csi_matrix_instance_q15 * pSrcA, + const csi_matrix_instance_q15 * pSrcB, + csi_matrix_instance_q15 * pDst); + +/** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. + */ +csi_status csi_mat_mult_fast_q15( + const csi_matrix_instance_q15 * pSrcA, + const csi_matrix_instance_q15 * pSrcB, + csi_matrix_instance_q15 * pDst); + +/** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. + */ +csi_status csi_mat_mult_q31( + const csi_matrix_instance_q31 * pSrcA, + const csi_matrix_instance_q31 * pSrcB, + csi_matrix_instance_q31 * pDst); + +csi_status csi_mat_mult_trans_q31( + const csi_matrix_instance_q31 * pSrcA, + const csi_matrix_instance_q31 * pSrcB, + csi_matrix_instance_q31 * pDst); + +/** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. + */ +csi_status csi_mat_mult_fast_q31( + const csi_matrix_instance_q31 * pSrcA, + const csi_matrix_instance_q31 * pSrcB, + csi_matrix_instance_q31 * pDst); + +/** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. + */ +csi_status csi_mat_sub_f32( + const csi_matrix_instance_f32 * pSrcA, + const csi_matrix_instance_f32 * pSrcB, + csi_matrix_instance_f32 * pDst); + +/** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. + */ +csi_status csi_mat_sub_q15( + const csi_matrix_instance_q15 * pSrcA, + const csi_matrix_instance_q15 * pSrcB, + csi_matrix_instance_q15 * pDst); + +/** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. + */ +csi_status csi_mat_sub_q31( + const csi_matrix_instance_q31 * pSrcA, + const csi_matrix_instance_q31 * pSrcB, + csi_matrix_instance_q31 * pDst); + +void csi_sum_q15( + q15_t * pSrcA, + q63_t * pDst, + uint32_t blockSize); + +/** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. + */ +csi_status csi_mat_scale_f32( + const csi_matrix_instance_f32 * pSrc, + float32_t scale, + csi_matrix_instance_f32 * pDst); + +/** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. + */ +csi_status csi_mat_scale_q15( + const csi_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + csi_matrix_instance_q15 * pDst); + +/** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. + */ +csi_status csi_mat_scale_q31( + const csi_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + csi_matrix_instance_q31 * pDst); + +/** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void csi_mat_init_q31( + csi_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + +/** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void csi_mat_init_q15( + csi_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + +/** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void csi_mat_init_f32( + csi_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + +/** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ +void csi_pid_init_f32( + csi_pid_instance_f32 * S, + int32_t resetStateFlag); + + +/** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ +void csi_pid_reset_f32( + csi_pid_instance_f32 * S); + + +/** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ +void csi_pid_init_q31( + csi_pid_instance_q31 * S, + int32_t resetStateFlag); + + +/** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + +void csi_pid_reset_q31( + csi_pid_instance_q31 * S); + + +/** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ +void csi_pid_init_q15( + csi_pid_instance_q15 * S, + int32_t resetStateFlag); + + +/** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ +void csi_pid_reset_q15( + csi_pid_instance_q15 * S); + +/** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void csi_mult_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + +/** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void csi_mult_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + +void csi_mult_rnd_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void csi_mult_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void csi_mult_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + +/* Deprecated */ +csi_status csi_cfft_radix2_init_q15( + csi_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ +void csi_cfft_radix2_q15( + const csi_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + +/* Deprecated */ +csi_status csi_cfft_radix4_init_q15( + csi_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ +void csi_cfft_radix4_q15( + const csi_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + +/* Deprecated */ +csi_status csi_cfft_radix2_init_q31( + csi_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ +void csi_cfft_radix2_q31( + const csi_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + +/* Deprecated */ +void csi_cfft_radix4_q31( + const csi_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ +csi_status csi_cfft_radix4_init_q31( + csi_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + +/* Deprecated */ +csi_status csi_cfft_radix2_init_f32( + csi_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void csi_cfft_radix2_f32( + const csi_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag, + float32_t onebyfftLen); + + +/* Deprecated */ +csi_status csi_cfft_radix4_init_f32( + csi_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void csi_cfft_radix4_f32( + const csi_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag, + float32_t onebyfftLen); + + void csi_cfft_fast_radix4_f32( + const csi_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag, + float32_t onebyfftLen); + + +void csi_cfft_q15( + const csi_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +void csi_cfft_fast_q15( + const csi_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +void csi_cfft_q31( + const csi_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +void csi_cfft_fast_q31( + const csi_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + +void csi_cfft_f32( + const csi_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + +csi_status csi_rfft_init_q15( + csi_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +void csi_rfft_q15( + const csi_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + +void csi_rfft_fast_q15( + const csi_rfft_fast_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + +csi_status csi_rfft_init_q31( + csi_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +void csi_rfft_q31( + const csi_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + +void csi_rfft_fast_q31( + const csi_rfft_fast_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + +csi_status csi_rfft_init_f32( + csi_rfft_instance_f32 * S, + csi_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +void csi_rfft_f32( + const csi_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + +csi_status csi_rfft_fast_init_f32 ( + csi_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +csi_status csi_rfft_32_fast_init_f32 ( csi_rfft_fast_instance_f32 * S ); + +csi_status csi_rfft_64_fast_init_f32 ( csi_rfft_fast_instance_f32 * S ); + +csi_status csi_rfft_128_fast_init_f32 ( csi_rfft_fast_instance_f32 * S ); + +csi_status csi_rfft_256_fast_init_f32 ( csi_rfft_fast_instance_f32 * S ); + +csi_status csi_rfft_512_fast_init_f32 ( csi_rfft_fast_instance_f32 * S ); + +csi_status csi_rfft_1024_fast_init_f32 ( csi_rfft_fast_instance_f32 * S ); + +csi_status csi_rfft_2048_fast_init_f32 ( csi_rfft_fast_instance_f32 * S ); + +csi_status csi_rfft_4096_fast_init_f32 ( csi_rfft_fast_instance_f32 * S ); + + +void csi_rfft_fast_f32( + csi_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + +/** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return csi_status function returns CSI_MATH_SUCCESS if initialization is successful or CSI_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ +csi_status csi_dct4_init_f32( + csi_dct4_instance_f32 * S, + csi_rfft_fast_instance_f32 * S_RFFT, + csi_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + +/** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ +void csi_dct4_f32( + const csi_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + +/** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return csi_status function returns CSI_MATH_SUCCESS if initialization is successful or CSI_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ +csi_status csi_dct4_init_q31( + csi_dct4_instance_q31 * S, + csi_rfft_instance_q31 * S_RFFT, + csi_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + +/** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ +void csi_dct4_q31( + const csi_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + +void csi_dct4_fast_q31( + const csi_dct4_fast_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + +/** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return csi_status function returns CSI_MATH_SUCCESS if initialization is successful or CSI_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ +csi_status csi_dct4_init_q15( + csi_dct4_instance_q15 * S, + csi_rfft_instance_q15 * S_RFFT, + csi_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + +/** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ +void csi_dct4_q15( + const csi_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + +void csi_dct4_fast_q15( + const csi_dct4_fast_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + +/** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void csi_add_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + +/** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void csi_add_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + +/** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void csi_add_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void csi_add_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void csi_sub_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + +/** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void csi_sub_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + +/** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void csi_sub_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void csi_sub_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void csi_scale_f32( + const float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + +/** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void csi_scale_q7( + const q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + +/** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void csi_scale_q15( + const q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void csi_scale_q31( + const q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ +void csi_abs_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + +/** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ +void csi_abs_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + +/** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ +void csi_abs_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ +void csi_abs_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + void csi_abs_max_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + void csi_abs_max_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ +void csi_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + +/** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ +void csi_dot_prod_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + +/** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ +void csi_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + +/** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ +void csi_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + +/** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void csi_shift_q7( + const q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + +/** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void csi_shift_q15( + const q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void csi_shift_q31( + const q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void csi_offset_f32( + const float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + +/** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void csi_offset_q7( + const q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + +/** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void csi_offset_q15( + const q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void csi_offset_q31( + const q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void csi_negate_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + +/** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void csi_negate_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + +/** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void csi_negate_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void csi_negate_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void csi_copy_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + +/** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void csi_copy_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + +/** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void csi_copy_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void csi_copy_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void csi_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + +/** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void csi_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + +/** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void csi_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void csi_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ +void csi_conv_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ +void csi_conv_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ +void csi_conv_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + +/** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ +void csi_conv_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + +/** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ +void csi_conv_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ +void csi_conv_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + +/** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ +void csi_conv_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + +/** +* @brief Convolution of Q7 sequences. +* @param[in] pSrcA points to the first input sequence. +* @param[in] srcALen length of the first input sequence. +* @param[in] pSrcB points to the second input sequence. +* @param[in] srcBLen length of the second input sequence. +* @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. +* @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. +* @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). +*/ +void csi_conv_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ +void csi_conv_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + +/** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either CSI_MATH_SUCCESS if the function completed correctly or CSI_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +csi_status csi_conv_partial_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either CSI_MATH_SUCCESS if the function completed correctly or CSI_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +csi_status csi_conv_partial_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either CSI_MATH_SUCCESS if the function completed correctly or CSI_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +csi_status csi_conv_partial_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either CSI_MATH_SUCCESS if the function completed correctly or CSI_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +csi_status csi_conv_partial_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either CSI_MATH_SUCCESS if the function completed correctly or CSI_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +csi_status csi_conv_partial_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either CSI_MATH_SUCCESS if the function completed correctly or CSI_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +csi_status csi_conv_partial_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either CSI_MATH_SUCCESS if the function completed correctly or CSI_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +csi_status csi_conv_partial_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either CSI_MATH_SUCCESS if the function completed correctly or CSI_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +csi_status csi_conv_partial_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either CSI_MATH_SUCCESS if the function completed correctly or CSI_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +csi_status csi_conv_partial_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + +/** + @brief Processing function for floating-point FIR decimator. + @param[in] S points to an instance of the floating-point FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + */ +void csi_fir_decimate_f32( + const csi_fir_decimate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + +/** + @brief Initialization function for the floating-point FIR decimator. + @param[in,out] S points to an instance of the floating-point FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref CSI_MATH_SUCCESS : Operation successful + - \ref CSI_MATH_LENGTH_ERROR : blockSize is not a multiple of M + */ +csi_status csi_fir_decimate_init_f32( + csi_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ +void csi_fir_decimate_q15( + const csi_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ +void csi_fir_decimate_fast_q15( + const csi_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns CSI_MATH_SUCCESS if initialization is successful or CSI_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ +csi_status csi_fir_decimate_init_q15( + csi_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ +void csi_fir_decimate_q31( + const csi_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ +void csi_fir_decimate_fast_q31( + const csi_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns CSI_MATH_SUCCESS if initialization is successful or CSI_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ +csi_status csi_fir_decimate_init_q31( + csi_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + +/** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ +void csi_fir_interpolate_q15( + const csi_fir_interpolate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns CSI_MATH_SUCCESS if initialization is successful or CSI_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ +csi_status csi_fir_interpolate_init_q15( + csi_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ +void csi_fir_interpolate_q31( + const csi_fir_interpolate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns CSI_MATH_SUCCESS if initialization is successful or CSI_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ +csi_status csi_fir_interpolate_init_q31( + csi_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ +void csi_fir_interpolate_f32( + const csi_fir_interpolate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns CSI_MATH_SUCCESS if initialization is successful or CSI_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ +csi_status csi_fir_interpolate_init_f32( + csi_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + +/** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void csi_biquad_cas_df1_32x64_q31( + const csi_biquad_cas_df1_32x64_ins_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ +void csi_biquad_cas_df1_32x64_init_q31( + csi_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + +/** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void csi_biquad_cascade_df2T_f32( + const csi_biquad_cascade_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + +/** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void csi_biquad_cascade_stereo_df2T_f32( + const csi_biquad_cascade_stereo_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + +/** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void csi_biquad_cascade_df2T_f64( + const csi_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + +#if defined(CSI_MATH_NEON) +void csi_biquad_cascade_df2T_compute_coefs_f32( + csi_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs); +#endif +/** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ +void csi_biquad_cascade_df2T_init_f32( + csi_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + +/** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ +void csi_biquad_cascade_stereo_df2T_init_f32( + csi_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + +/** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ +void csi_biquad_cascade_df2T_init_f64( + csi_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + +/** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ +void csi_fir_lattice_init_q15( + csi_fir_lattice_instance_q15 * S, + uint16_t numStages, + const q15_t * pCoeffs, + q15_t * pState); + + +/** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void csi_fir_lattice_q15( + const csi_fir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ +void csi_fir_lattice_init_q31( + csi_fir_lattice_instance_q31 * S, + uint16_t numStages, + const q31_t * pCoeffs, + q31_t * pState); + + +/** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void csi_fir_lattice_q31( + const csi_fir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ +void csi_fir_lattice_init_f32( + csi_fir_lattice_instance_f32 * S, + uint16_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + +/** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void csi_fir_lattice_f32( + const csi_fir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + +/** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void csi_iir_lattice_f32( + const csi_iir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ +void csi_iir_lattice_init_f32( + csi_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void csi_iir_lattice_q31( + const csi_iir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ +void csi_iir_lattice_init_q31( + csi_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void csi_iir_lattice_q15( + const csi_iir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ +void csi_iir_lattice_init_q15( + csi_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + +/** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ +void csi_lms_f32( + const csi_lms_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + +/** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ +void csi_lms_init_f32( + csi_lms_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ +void csi_lms_init_q15( + csi_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + +/** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ +void csi_lms_q15( + const csi_lms_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + +/** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ +void csi_lms_q31( + const csi_lms_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + +/** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ +void csi_lms_init_q31( + csi_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + +/** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ +void csi_lms_norm_f32( + csi_lms_norm_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + +/** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ +void csi_lms_norm_init_f32( + csi_lms_norm_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + +/** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ +void csi_lms_norm_q31( + csi_lms_norm_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + +/** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ +void csi_lms_norm_init_q31( + csi_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + +/** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ +void csi_lms_norm_q15( + csi_lms_norm_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + +/** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ +void csi_lms_norm_init_q15( + csi_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + +/** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void csi_correlate_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + +/** + @brief Correlation of Q15 sequences + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. +*/ +void csi_correlate_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + +/** + @brief Correlation of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void csi_correlate_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + */ +void csi_correlate_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ +void csi_correlate_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + +/** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void csi_correlate_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + +/** + @brief Correlation of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void csi_correlate_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + +/** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ +void csi_correlate_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void csi_correlate_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + +/** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ +void csi_fir_sparse_f32( + csi_fir_sparse_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ +void csi_fir_sparse_init_f32( + csi_fir_sparse_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ +void csi_fir_sparse_q31( + csi_fir_sparse_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ +void csi_fir_sparse_init_q31( + csi_fir_sparse_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ +void csi_fir_sparse_q15( + csi_fir_sparse_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ +void csi_fir_sparse_init_q15( + csi_fir_sparse_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ +void csi_fir_sparse_q7( + csi_fir_sparse_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ +void csi_fir_sparse_init_q7( + csi_fir_sparse_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + +/** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ +void csi_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + +/** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ +void csi_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + +/** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ +void csi_cmplx_conj_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + +/** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ +void csi_cmplx_conj_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + +/** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ +void csi_cmplx_conj_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + +/** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ +void csi_cmplx_mag_squared_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + +/** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ +void csi_cmplx_mag_squared_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + +void csi_cmplx_mag_squared_q31_basic( + q31_t * pSrc, + q63_t * pDst, + uint32_t numSamples); + + +/** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ +void csi_cmplx_mag_squared_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + +/** + * @ingroup groupController + */ + +/** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+ *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ *    A0 = Kp + Ki + Kd
+ *    A1 = (-Kp ) - (2 * Kd )
+ *    A2 = Kd
+ *
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup PID + * @{ + */ + +/** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return processed output sample. + */ +__STATIC_FORCEINLINE float32_t csi_pid_f32( + csi_pid_instance_f32 * S, + float32_t in) +{ + float32_t out; + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + /* return to application */ + return (out); +} + +/** + @brief Process function for the Q31 PID Control. + @param[in,out] S points to an instance of the Q31 PID Control structure + @param[in] in input sample to process + @return processed output sample. + + \par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ +__STATIC_FORCEINLINE q31_t csi_pid_q31( + csi_pid_instance_q31 * S, + q31_t in) +{ + q63_t acc; + q31_t out; + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + /* out += y[n-1] */ + out += S->state[2]; + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + /* return to application */ + return (out); +} + + +/** + @brief Process function for the Q15 PID Control. + @param[in,out] S points to an instance of the Q15 PID Control structure + @param[in] in input sample to process + @return processed output sample. + + \par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ +__STATIC_FORCEINLINE q15_t csi_pid_q15( + csi_pid_instance_q15 * S, + q15_t in) +{ + q63_t acc; + q15_t out; +#if defined (CSI_MATH_DSP) + /* Implementation of PID controller */ + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)read_q15x2 (S->state), (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + /* saturate the output */ + out = (q15_t) (__SSAT((q31_t)(acc >> 15), 16)); + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + /* return to application */ + return (out); +} + +/** + * @} end of PID group + */ + + +/** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns CSI_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status CSI_MATH_SINGULAR. + */ +csi_status csi_mat_inverse_f32( + const csi_matrix_instance_f32 * src, + csi_matrix_instance_f32 * dst); + + +/** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns CSI_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status CSI_MATH_SINGULAR. + */ +csi_status csi_mat_inverse_f64( + const csi_matrix_instance_f64 * src, + csi_matrix_instance_f64 * dst); + + + +/** + * @ingroup groupController + */ + +/** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup clarke + * @{ + */ + +/** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @return none + */ +__STATIC_FORCEINLINE void csi_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) +{ + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); +} + + +/** + @brief Clarke transform for Q31 version + @param[in] Ia input three-phase coordinate a + @param[in] Ib input three-phase coordinate b + @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] pIbeta points to output two-phase orthogonal vector axis beta + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void csi_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); +} + +/** + * @} end of clarke group + */ + + +/** + * @ingroup groupController + */ + +/** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup inv_clarke + * @{ + */ + +/** +* @brief Floating-point Inverse Clarke transform +* @param[in] Ialpha input two-phase orthogonal vector axis alpha +* @param[in] Ibeta input two-phase orthogonal vector axis beta +* @param[out] pIa points to output three-phase coordinate a +* @param[out] pIb points to output three-phase coordinate b +* @return none +*/ +__STATIC_FORCEINLINE void csi_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) +{ + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; +} + + +/** + @brief Inverse Clarke transform for Q31 version + @param[in] Ialpha input two-phase orthogonal vector axis alpha + @param[in] Ibeta input two-phase orthogonal vector axis beta + @param[out] pIa points to output three-phase coordinate a + @param[out] pIb points to output three-phase coordinate b + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the subtraction, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void csi_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); +} + +/** + * @} end of inv_clarke group + */ + + + +/** + * @ingroup groupController + */ + +/** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup park + * @{ + */ + +/** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none + * + * The function implements the forward Park transform. + * + */ +__STATIC_FORCEINLINE void csi_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) +{ + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; +} + + +/** + @brief Park transform for Q31 version + @param[in] Ialpha input two-phase vector coordinate alpha + @param[in] Ibeta input two-phase vector coordinate beta + @param[out] pId points to output rotor reference frame d + @param[out] pIq points to output rotor reference frame q + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void csi_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) +{ +#ifdef CSI_SIMD + asm volatile( + "rmul.s32.h t0, %0, %3\n\t" + "rmul.s32.h t1, %1, %2\n\t" + "add.s32.s t0, t0, t1\n\t" + "st.w t0, (%4, 0x0)\n\t" + "rmul.s32.h t0, %0, %2\n\t" + "rmul.s32.h t1, %1, %3\n\t" + "sub.s32.s t1, t1, t0\n\t" + "st.w t1, (%5, 0x0)\n\t" + ::"r"(Ialpha),"r"(Ibeta),"r"(sinVal),"r"(cosVal),"r"(pId),"r"(pIq) + :"t0","t1", "memory"); +#else + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); +#endif +} + +/** + * @} end of park group + */ + + +/** + * @ingroup groupController + */ + +/** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup inv_park + * @{ + */ + +/** +* @brief Floating-point Inverse Park transform +* @param[in] Id input coordinate of rotor reference frame d +* @param[in] Iq input coordinate of rotor reference frame q +* @param[out] pIalpha points to output two-phase orthogonal vector axis alpha +* @param[out] pIbeta points to output two-phase orthogonal vector axis beta +* @param[in] sinVal sine value of rotation angle theta +* @param[in] cosVal cosine value of rotation angle theta +* @return none +*/ +__STATIC_FORCEINLINE void csi_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) +{ + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; +} + + +/** + @brief Inverse Park transform for Q31 version + @param[in] Id input coordinate of rotor reference frame d + @param[in] Iq input coordinate of rotor reference frame q + @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] pIbeta points to output two-phase orthogonal vector axis beta + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void csi_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) +{ +#ifdef CSI_SIMD + asm volatile( + "rmul.s32.h t0, %0, %3\n\t" + "rmul.s32.h t1, %1, %2\n\t" + "sub.s32.s t0, t0, t1\n\t" + "st.w t0, (%4, 0x0)\n\t" + "rmul.s32.h t0, %0, %2\n\t" + "rmul.s32.h t1, %1, %3\n\t" + "add.s32.s t0, t0, t1\n\t" + "st.w t0, (%5, 0x0)\n\t" + ::"r"(Id),"r"(Iq),"r"(sinVal),"r"(cosVal),"r"(pIalpha),"r"(pIbeta) + :"t0","t1", "memory"); +#else + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); +#endif +} + +/** + * @} end of Inverse park group + */ + + +/** + * @ingroup groupInterpolation + */ + +/** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+ *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ *       where x0, x1 are nearest values of input x
+ *             y0, y1 are nearest values to output y
+ *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + +/** + * @addtogroup LinearInterpolate + * @{ + */ + +/** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ +__STATIC_FORCEINLINE float32_t csi_linear_interp_f32( + csi_linear_interp_instance_f32 * S, + float32_t x) +{ + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + + } else if ((uint32_t)i >= (S->nValues - 1)) { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + + } else { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + } + + /* returns output value */ + return (y); +} + + +/** +* +* @brief Process function for the Q31 Linear Interpolation Function. +* @param[in] pYData pointer to Q31 Linear Interpolation table +* @param[in] x input sample to process +* @param[in] nValues number of table values +* @return y processed output sample. +* +* \par +* Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. +* This function can support maximum of table size 2^12. +* +*/ +__STATIC_FORCEINLINE q31_t csi_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) +{ + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) { + return (pYData[nValues - 1]); + + } else if (index < 0) { + return (pYData[0]); + + } else { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + /* Convert y to 1.31 format */ + return (y << 1U); + } +} + + +/** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ +__STATIC_FORCEINLINE q15_t csi_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) +{ + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) { + return (pYData[nValues - 1]); + + } else if (index < 0) { + return (pYData[0]); + + } else { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } +} + + +/** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ +__STATIC_FORCEINLINE q7_t csi_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) +{ + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) { + return (pYData[0]); + } + + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) { + return (pYData[nValues - 1]); + + } else { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } +} + +/** + * @} end of LinearInterpolate group + */ + +/** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ +float32_t csi_sin_f32( + float32_t x); + + +/** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ +q31_t csi_sin_q31( + q31_t x); + + +/** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ +q15_t csi_sin_q15( + q15_t x); + + +/** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ +float32_t csi_cos_f32( + float32_t x); + + +/** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ +q31_t csi_cos_q31( + q31_t x); + + +/** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ +q15_t csi_cos_q15( + q15_t x); + + +/** + @brief Floating-point vector of log values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ +void csi_vlog_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +/** + @brief Floating-point vector of exp values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ +void csi_vexp_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +/** + * @ingroup groupFastMath + */ + + +/** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+ *      x1 = x0 - f(x0)/f'(x0)
+ *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+ *     x0 = in/2                         [initial guess]
+ *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+ *
+ */ + + +/** + * @addtogroup SQRT + * @{ + */ + +/** + @brief Q15 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF + @param[out] pOut points to square root of input value + @return execution status + - \ref CSI_MATH_SUCCESS : input value is positive + - \ref CSI_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +csi_status csi_sqrt_q15( + q15_t in, + q15_t * pOut); + +/** + @brief Floating-point square root function. + @param[in] in input value + @param[out] pOut square root of input value + @return execution status + - \ref CSI_MATH_SUCCESS : input value is positive + - \ref CSI_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +#ifdef __riscv +__STATIC_FORCEINLINE csi_status csi_sqrt_f32( + float32_t in, + float32_t * pOut) +{ + if (in >= 0.0f) { +#ifdef CSI_NEWTON_SQRTF + float32_t eps = 0.000000011; + float32_t val = in / 2; + float32_t last; + + if (in <= eps) { + *pOut = 0.0f; + } else { + do { + last = val; + val = (val + in / val) / 2; + } while (fabsf(val - last) > eps); + *pOut = val; + } +#else + *pOut = sqrtf(in); +#endif + return (CSI_MATH_SUCCESS); + } else { + *pOut = 0.0f; + return (CSI_MATH_ARGUMENT_ERROR); + } +} +#else +csi_status csi_sqrt_f32( + float32_t in, + float32_t * pOut); +#endif + + +/** + @brief Q31 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF + @param[out] pOut points to square root of input value + @return execution status + - \ref CSI_MATH_SUCCESS : input value is positive + - \ref CSI_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +csi_status csi_sqrt_q31( + q31_t in, + q31_t * pOut); + +/** + * @brief Vector Floating-point square root function. + * @param[in] pIn input vector. + * @param[out] pOut vector of square roots of input elements. + * @param[in] len length of input vector. + * @return The function returns CSI_MATH_SUCCESS if input value is positive value or CSI_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ +#ifdef __csky__ + +void csi_vsqrt_f32( + float32_t * pIn, + float32_t * pOut, + uint16_t len); + + void csi_vsqrt_q15( + q15_t * pIn, + q15_t * pOut, + uint16_t len); + +void csi_vsqrt_q31( + q31_t * pIn, + q31_t * pOut, + uint16_t len); + +void csi_vsqrt_q7( + q7_t * pIn, + q7_t * pOut, + uint16_t len); + + +#else +__STATIC_FORCEINLINE void csi_vsqrt_f32( + float32_t * pIn, + float32_t * pOut, + uint16_t len) +{ + for (int i = 0; i < len; i++) { + csi_sqrt_f32(pIn[i], pOut + i); + } +} + +__STATIC_FORCEINLINE void csi_vsqrt_q15( + q15_t * pIn, + q15_t * pOut, + uint16_t len +) +{ + for (int i = 0; i < len; i++) { + csi_sqrt_q15(pIn[i], pOut + i); + } +} +__STATIC_FORCEINLINE void csi_vsqrt_q31( + q31_t * pIn, + q31_t * pOut, + uint16_t len +) +{ + for (int i = 0; i < len; i++) { + csi_sqrt_q31(pIn[i], pOut + i); + } +} +#endif +/** + * @} end of SQRT group + */ + +/** + * @brief floating-point Circular write function. + a*/ +#ifndef __csky__ +__STATIC_FORCEINLINE void csi_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) +{ + uint32_t i = 0U; + int32_t wOffset; + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + /* Update the input pointer */ + src += srcInc; + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; +} + + + +/** + * @brief floating-point Circular Read function. + */ +__STATIC_FORCEINLINE void csi_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) +{ + uint32_t i = 0U; + int32_t rOffset; + int32_t* dst_end; + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = dst_base + dst_length; + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; +} +#endif +/** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void csi_power_q31( + const q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + +void csi_power_int32( + int32_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + +/** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void csi_power_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + +/** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void csi_power_q15( + const q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + +/** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void csi_power_q7( + const q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + +/** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void csi_mean_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + +/** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void csi_mean_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + +/** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void csi_mean_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + +/** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void csi_mean_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + +/** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void csi_var_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + +/** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void csi_var_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + +/** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void csi_var_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + +/** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void csi_rms_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + +/** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void csi_rms_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + +/** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void csi_rms_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + +/** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void csi_std_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + +/** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void csi_std_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + +/** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void csi_std_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + +/** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ +void csi_cmplx_mag_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + +/** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ +void csi_cmplx_mag_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + +/** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ +void csi_cmplx_mag_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + +/** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ +void csi_cmplx_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + +/** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ +void csi_cmplx_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + void csi_dot_prod_u64xu8( + uint8_t * pSrcA, + uint64_t * pSrcB, + uint32_t blockSize, + uint64_t * result); + +/** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ +void csi_cmplx_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + +/** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ +void csi_cmplx_mult_real_q15( + const q15_t * pSrcCmplx, + const q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + +/** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ +void csi_cmplx_mult_real_q31( + const q31_t * pSrcCmplx, + const q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + +/** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ +void csi_cmplx_mult_real_f32( + const float32_t * pSrcCmplx, + const float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + +/** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ +void csi_min_q7( + const q7_t * pSrc, + uint16_t blockSize, + q7_t * result, + uint16_t * index); + + +/** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ +void csi_min_q15( + const q15_t * pSrc, + uint16_t blockSize, + q15_t * pResult, + uint16_t * pIndex); + + +/** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ +void csi_min_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ +void csi_min_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ +void csi_max_q7( + const q7_t * pSrc, + uint16_t blockSize, + q7_t * pResult, + uint16_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ +void csi_max_q15( + const q15_t * pSrc, + uint16_t blockSize, + q15_t * pResult, + uint16_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ +void csi_max_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ +void csi_max_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ +void csi_max_no_idx_f32( + const float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult); + +/** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ +void csi_cmplx_mult_cmplx_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + +/** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ +void csi_cmplx_mult_cmplx_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + +/** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ +void csi_cmplx_mult_cmplx_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + +void csi_cmplx_mult_cmplx_re_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + +/** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ +void csi_float_to_q31( + const float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ +void csi_float_to_q15( + const float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ +void csi_float_to_q7( + const float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ +void csi_q31_to_float( + const q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ +void csi_q31_to_q15( + const q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +void csi_q31_to_q7_rs( + q31_t * pSrc, + q7_t * pDst, + uint32_t shiftValue, + uint32_t blockSize); + +void csi_q63_to_q31_rs( + q63_t * pSrc, + q31_t * pDst, + uint32_t shiftValue, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ +void csi_q31_to_q7( + const q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ +void csi_q15_to_float( + const q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ +void csi_q15_to_q31( + const q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ +void csi_q15_to_q7( + const q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ +void csi_q7_to_float( + const q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void csi_q7_to_q31( + const q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void csi_q7_to_q15( + const q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief SVM linear instance init function + * @param[in] S Parameters for SVM functions + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @return none. + * + */ + + +void csi_svm_linear_init_f32(csi_svm_linear_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes); + +/** + * @brief SVM linear prediction + * @param[in] S Pointer to an instance of the linear SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ + +void csi_svm_linear_predict_f32(const csi_svm_linear_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + +/** + * @brief SVM polynomial instance init function + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] degree Polynomial degree + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + + +void csi_svm_polynomial_init_f32(csi_svm_polynomial_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + int32_t degree, + float32_t coef0, + float32_t gamma + ); + +/** + * @brief SVM polynomial prediction + * @param[in] S Pointer to an instance of the polynomial SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void csi_svm_polynomial_predict_f32(const csi_svm_polynomial_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + +/** + * @brief SVM radial basis function instance init function + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void csi_svm_rbf_init_f32(csi_svm_rbf_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + float32_t gamma + ); + +/** + * @brief SVM rbf prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult decision value + * @return none. + * + */ +void csi_svm_rbf_predict_f32(const csi_svm_rbf_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + +/** + * @brief SVM sigmoid instance init function + * @param[in] S points to an instance of the rbf SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void csi_svm_sigmoid_init_f32(csi_svm_sigmoid_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + float32_t coef0, + float32_t gamma + ); + +/** + * @brief SVM sigmoid prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void csi_svm_sigmoid_predict_f32(const csi_svm_sigmoid_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + +/** + * @brief Naive Gaussian Bayesian Estimator + * + * @param[in] S points to a naive bayes instance structure + * @param[in] in points to the elements of the input vector. + * @param[in] pBuffer points to a buffer of length numberOfClasses + * @return The predicted class + * + */ + + +uint32_t csi_gaussian_naive_bayes_predict_f32(const csi_gaussian_naive_bayes_instance_f32 *S, + const float32_t * in, + float32_t *pBuffer); + +/** + * @brief Computation of the LogSumExp + * + * In probabilistic computations, the dynamic of the probability values can be very + * wide because they come from gaussian functions. + * To avoid underflow and overflow issues, the values are represented by their log. + * In this representation, multiplying the original exp values is easy : their logs are added. + * But adding the original exp values is requiring some special handling and it is the + * goal of the LogSumExp function. + * + * If the values are x1...xn, the function is computing: + * + * ln(exp(x1) + ... + exp(xn)) and the computation is done in such a way that + * rounding issues are minimised. + * + * The max xm of the values is extracted and the function is computing: + * xm + ln(exp(x1 - xm) + ... + exp(xn - xm)) + * + * @param[in] *in Pointer to an array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return LogSumExp + * + */ + + +float32_t csi_logsumexp_f32(const float32_t *in, uint32_t blockSize); + +/** + * @brief Dot product with log arithmetic + * + * Vectors are containing the log of the samples + * + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[in] pTmpBuffer temporary buffer of length blockSize + * @return The log of the dot product . + * + */ + + +float32_t csi_logsumexp_dot_prod_f32(const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t *pTmpBuffer); + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + + +float32_t csi_entropy_f32(const float32_t * pSrcA,uint32_t blockSize); + + +/** + * @brief Kullback-Leibler + * + * @param[in] pSrcA Pointer to an array of input values for probability distribution A. + * @param[in] pSrcB Pointer to an array of input values for probability distribution B. + * @param[in] blockSize Number of samples in the input array. + * @return Kullback-Leibler Divergence D(A || B) + * + */ +float32_t csi_kullback_leibler_f32(const float32_t * pSrcA + ,const float32_t * pSrcB + ,uint32_t blockSize); + + +/** + * @brief Weighted sum + * + * + * @param[in] *in Array of input values. + * @param[in] *weigths Weights + * @param[in] blockSize Number of samples in the input array. + * @return Weighted sum + * + */ +float32_t csi_weighted_sum_f32(const float32_t *in + , const float32_t *weigths + , uint32_t blockSize); + + +/** + * @brief Barycenter + * + * + * @param[in] in List of vectors + * @param[in] weights Weights of the vectors + * @param[out] out Barycenter + * @param[in] nbVectors Number of vectors + * @param[in] vecDim Dimension of space (vector dimension) + * @return None + * + */ +void csi_barycenter_f32(const float32_t *in + , const float32_t *weights + , float32_t *out + , uint32_t nbVectors + , uint32_t vecDim); + +/** + * @brief Euclidean distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t csi_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Bray-Curtis distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t csi_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Canberra distance between two vectors + * + * This function may divide by zero when samples pA[i] and pB[i] are both zero. + * The result of the computation will be correct. So the division per zero may be + * ignored. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t csi_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + + +/** + * @brief Chebyshev distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t csi_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + + +/** + * @brief Cityblock (Manhattan) distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t csi_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Correlation distance between two vectors + * + * The input vectors are modified in place ! + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t csi_correlation_distance_f32(float32_t *pA,float32_t *pB, uint32_t blockSize); + +/** + * @brief Cosine distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t csi_cosine_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Jensen-Shannon distance between two vectors + * + * This function is assuming that elements of second vector are > 0 + * and 0 only when the corresponding element of first vector is 0. + * Otherwise the result of the computation does not make sense + * and for speed reasons, the cases returning NaN or Infinity are not + * managed. + * + * When the function is computing x log (x / y) with x 0 and y 0, + * it will compute the right value (0) but a division per zero will occur + * and shoudl be ignored in client code. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t csi_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB,uint32_t blockSize); + +/** + * @brief Minkowski distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] n Norm order (>= 2) + * @param[in] blockSize vector length + * @return distance + * + */ + + + +float32_t csi_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize); + +/** + * @brief Dice distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] order Distance order + * @param[in] blockSize Number of samples + * @return distance + * + */ + + +float32_t csi_dice_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Hamming distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t csi_hamming_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Jaccard distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t csi_jaccard_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Kulsinski distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t csi_kulsinski_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Roger Stanimoto distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t csi_rogerstanimoto_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Russell-Rao distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t csi_russellrao_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Sokal-Michener distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t csi_sokalmichener_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Sokal-Sneath distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t csi_sokalsneath_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Yule distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t csi_yule_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + + +/** + * @ingroup groupInterpolation + */ + +/** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+ *   typedef struct
+ *   {
+ *     uint16_t numRows;
+ *     uint16_t numCols;
+ *     float32_t *pData;
+ * } csi_bilinear_interp_instance_f32;
+ *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+ *     XF = floor(x)
+ *     YF = floor(y)
+ *
+ * \par + * The interpolated output point is computed as: + * 
+ *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + +/** + * @addtogroup BilinearInterpolate + * @{ + */ + +/** +* @brief Floating-point bilinear interpolation. +* @param[in,out] S points to an instance of the interpolation structure. +* @param[in] X interpolation coordinate. +* @param[in] Y interpolation coordinate. +* @return out interpolated value. +*/ +__STATIC_FORCEINLINE float32_t csi_bilinear_interp_f32( + const csi_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) +{ + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + /* return to application */ + return (out); +} + + +/** +* @brief Q31 bilinear interpolation. +* @param[in,out] S points to an instance of the interpolation structure. +* @param[in] X interpolation coordinate in 12.20 format. +* @param[in] Y interpolation coordinate in 12.20 format. +* @return out interpolated value. +*/ +__STATIC_FORCEINLINE q31_t csi_bilinear_interp_q31( + csi_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) +{ + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); +} + + +/** +* @brief Q15 bilinear interpolation. +* @param[in,out] S points to an instance of the interpolation structure. +* @param[in] X interpolation coordinate in 12.20 format. +* @param[in] Y interpolation coordinate in 12.20 format. +* @return out interpolated value. +*/ +__STATIC_FORCEINLINE q15_t csi_bilinear_interp_q15( + csi_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) +{ + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0xFFFFF - yfract)); + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); +} + + +/** +* @brief Q7 bilinear interpolation. +* @param[in,out] S points to an instance of the interpolation structure. +* @param[in] X interpolation coordinate in 12.20 format. +* @param[in] Y interpolation coordinate in 12.20 format. +* @return out interpolated value. +*/ +__STATIC_FORCEINLINE q7_t csi_bilinear_interp_q7( + csi_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) +{ + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); +} + +/** + * @} end of BilinearInterpolate group + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* _CSI_MATH_H */ + +/** + * + * End of file. + */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_common_tables.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_common_tables.h new file mode 100644 index 00000000..13a96dca --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_common_tables.h @@ -0,0 +1,229 @@ +/* + * Copyright (C) 2016-2019 C-SKY Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file csky_common_tables.h + * @brief This file has extern declaration for common tables like + * Bitreverse, reciprocal etc which are used across different functions. + * @version V1.0 + * @date 20. Dec 2016 + ******************************************************************************/ + +#ifndef _CSKY_COMMON_TABLES_H +#define _CSKY_COMMON_TABLES_H + +#include "csky_math.h" + +extern const uint16_t cskyBitRevTable[1024]; +extern const q15_t cskyRecipTableQ15[64]; +extern const q31_t cskyRecipTableQ31[64]; +extern const uint32_t twiddleCoef_16[32]; +extern const uint32_t twiddleCoef_32[64]; +extern const uint32_t twiddleCoef_64[128]; +extern const uint32_t twiddleCoef_128[256]; +extern const uint32_t twiddleCoef_256[512]; +extern const uint32_t twiddleCoef_512[1024]; +extern const uint32_t twiddleCoef_1024[2048]; +extern const uint32_t twiddleCoef_2048[4096]; +extern const uint32_t twiddleCoef_4096[8192]; +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; +extern const float32_t twiddleCoef_rfft_8192[8192]; + +extern const q15_t twiddleCoef_fast_16_q15[24]; +extern const q15_t twiddleCoef_fast_32_q15[56]; +extern const q15_t twiddleCoef_fast_64_q15[120]; +extern const q15_t twiddleCoef_fast_128_q15[248]; +extern const q15_t twiddleCoef_fast_256_q15[504]; +extern const q15_t twiddleCoef_fast_512_q15[1016]; +extern const q15_t twiddleCoef_fast_1024_q15[2040]; +extern const q15_t twiddleCoef_fast_2048_q15[4088]; +extern const q15_t twiddleCoef_fast_4096_q15[8184]; + +extern const q31_t twiddleCoef_fast_16_q31[24]; +extern const q31_t twiddleCoef_fast_32_q31[56]; +extern const q31_t twiddleCoef_fast_64_q31[120]; +extern const q31_t twiddleCoef_fast_128_q31[248]; +extern const q31_t twiddleCoef_fast_256_q31[504]; +extern const q31_t twiddleCoef_fast_512_q31[1016]; +extern const q31_t twiddleCoef_fast_1024_q31[2040]; +extern const q31_t twiddleCoef_fast_2048_q31[4088]; +extern const q31_t twiddleCoef_fast_4096_q31[8184]; + +extern const uint32_t twiddleCoef_fast_16[24]; +extern const uint32_t twiddleCoef_fast_32[56]; +extern const uint32_t twiddleCoef_fast_64[120]; +extern const uint32_t twiddleCoef_fast_128[248]; +extern const uint32_t twiddleCoef_fast_256[504]; +extern const uint32_t twiddleCoef_fast_512[1016]; +extern const uint32_t twiddleCoef_fast_1024[2040]; +extern const uint32_t twiddleCoef_fast_2048[4088]; +extern const uint32_t twiddleCoef_fast_4096[8184]; + +extern const q15_t realCoefAQ15_8192[8192]; +extern const q31_t realCoefAQ31_8192[8192]; +extern const q15_t realCoefBQ15_8192[8192]; +extern const q31_t realCoefBQ31_8192[8192]; + +/*Tables for RFFT.*/ +extern const q15_t ALIGN4 realCoefAQ15_32[32]; +extern const q15_t ALIGN4 realCoefAQ15_64[64]; +extern const q15_t ALIGN4 realCoefAQ15_128[128]; +extern const q15_t ALIGN4 realCoefAQ15_256[256]; +extern const q15_t ALIGN4 realCoefAQ15_512[512]; +extern const q15_t ALIGN4 realCoefAQ15_1024[1024]; +extern const q15_t ALIGN4 realCoefAQ15_2048[2048]; +extern const q15_t ALIGN4 realCoefAQ15_4096[4096]; + +extern const q15_t ALIGN4 realCoefBQ15_32[32]; +extern const q15_t ALIGN4 realCoefBQ15_64[64]; +extern const q15_t ALIGN4 realCoefBQ15_128[128]; +extern const q15_t ALIGN4 realCoefBQ15_256[256]; +extern const q15_t ALIGN4 realCoefBQ15_512[512]; +extern const q15_t ALIGN4 realCoefBQ15_1024[1024]; +extern const q15_t ALIGN4 realCoefBQ15_2048[2048]; +extern const q15_t ALIGN4 realCoefBQ15_4096[4096]; + +extern const q31_t realCoefAQ31_32[32]; +extern const q31_t realCoefAQ31_64[64]; +extern const q31_t realCoefAQ31_128[128]; +extern const q31_t realCoefAQ31_256[256]; +extern const q31_t realCoefAQ31_512[512]; +extern const q31_t realCoefAQ31_1024[1024]; +extern const q31_t realCoefAQ31_2048[2048]; +extern const q31_t realCoefAQ31_4096[4096]; + +extern const q31_t realCoefBQ31_32[32]; +extern const q31_t realCoefBQ31_64[64]; +extern const q31_t realCoefBQ31_128[128]; +extern const q31_t realCoefBQ31_256[256]; +extern const q31_t realCoefBQ31_512[512]; +extern const q31_t realCoefBQ31_1024[1024]; +extern const q31_t realCoefBQ31_2048[2048]; +extern const q31_t realCoefBQ31_4096[4096]; + + +extern const float32_t realCoefA[8192]; +extern const float32_t realCoefB[8192]; + + +/*Tables for DCT4*/ +extern const q15_t ALIGN4 WeightsQ15_128[128+2]; +extern const q15_t ALIGN4 WeightsQ15_512[512+2]; +extern const q15_t ALIGN4 WeightsQ15_2048[2048+2]; +extern const q15_t ALIGN4 WeightsQ15_8192[8192+2]; + +extern const q15_t ALIGN4 cos_factorsQ15_128[128]; +extern const q15_t ALIGN4 cos_factorsQ15_512[512]; +extern const q15_t ALIGN4 cos_factorsQ15_2048[2048]; +extern const q15_t ALIGN4 cos_factorsQ15_8192[8192]; + + +extern const q31_t WeightsQ31_128[128+2]; +extern const q31_t WeightsQ31_512[512+2]; +extern const q31_t WeightsQ31_2048[2048+2]; +extern const q31_t WeightsQ31_8192[8192+2]; + +extern const q31_t cos_factorsQ31_128[128]; +extern const q31_t cos_factorsQ31_512[512]; +extern const q31_t cos_factorsQ31_2048[2048]; +extern const q31_t cos_factorsQ31_8192[8192]; + + +extern const float32_t Weights_128[128+2]; +extern const float32_t Weights_512[512+2]; +extern const float32_t Weights_2048[2048+2]; +extern const float32_t Weights_8192[8192+2]; + +extern const float32_t cos_factors_128[128]; +extern const float32_t cos_factors_512[512]; +extern const float32_t cos_factors_2048[2048]; +extern const float32_t cos_factors_8192[8192]; + +/* floating-point bit reversal tables */ +#define CSKYBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) +#define CSKYBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) +#define CSKYBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) +#define CSKYBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) +#define CSKYBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) +#define CSKYBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define CSKYBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) +#define CSKYBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) +#define CSKYBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t cskyBitRevIndexTable16[CSKYBITREVINDEXTABLE__16_TABLE_LENGTH]; +extern const uint16_t cskyBitRevIndexTable32[CSKYBITREVINDEXTABLE__32_TABLE_LENGTH]; +extern const uint16_t cskyBitRevIndexTable64[CSKYBITREVINDEXTABLE__64_TABLE_LENGTH]; +extern const uint16_t cskyBitRevIndexTable128[CSKYBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t cskyBitRevIndexTable256[CSKYBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t cskyBitRevIndexTable512[CSKYBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t cskyBitRevIndexTable1024[CSKYBITREVINDEXTABLE1024_TABLE_LENGTH]; +extern const uint16_t cskyBitRevIndexTable2048[CSKYBITREVINDEXTABLE2048_TABLE_LENGTH]; +extern const uint16_t cskyBitRevIndexTable4096[CSKYBITREVINDEXTABLE4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define CSKYBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) +#define CSKYBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) +#define CSKYBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) +#define CSKYBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) +#define CSKYBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) +#define CSKYBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) +#define CSKYBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) +#define CSKYBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define CSKYBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t cskyBitRevIndexTable_fixed_16[CSKYBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; +extern const uint16_t cskyBitRevIndexTable_fixed_32[CSKYBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; +extern const uint16_t cskyBitRevIndexTable_fixed_64[CSKYBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; +extern const uint16_t cskyBitRevIndexTable_fixed_128[CSKYBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; +extern const uint16_t cskyBitRevIndexTable_fixed_256[CSKYBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; +extern const uint16_t cskyBitRevIndexTable_fixed_512[CSKYBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; +extern const uint16_t cskyBitRevIndexTable_fixed_1024[CSKYBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t cskyBitRevIndexTable_fixed_2048[CSKYBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t cskyBitRevIndexTable_fixed_4096[CSKYBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* CSKY_COMMON_TABLES_H */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_const_structs.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_const_structs.h new file mode 100644 index 00000000..1f5b5409 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_const_structs.h @@ -0,0 +1,131 @@ +/* + * Copyright (C) 2016-2019 C-SKY Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file csky_const_structs.h + * @brief This file has constant structs that are initialized for + * user convenience. For example, some can be given as + * arguments to the csky_cfft_f32() function. + * @version V1.0 + * @date 20. Dec 2016 + ******************************************************************************/ + +#ifndef _CSKY_CONST_STRUCTS_H +#define _CSKY_CONST_STRUCTS_H + +#include "csky_math.h" +#include "csky_common_tables.h" + + extern const csky_cfft_instance_f32 csky_cfft_sR_f32_len16; + extern const csky_cfft_instance_f32 csky_cfft_sR_f32_len32; + extern const csky_cfft_instance_f32 csky_cfft_sR_f32_len64; + extern const csky_cfft_instance_f32 csky_cfft_sR_f32_len128; + extern const csky_cfft_instance_f32 csky_cfft_sR_f32_len256; + extern const csky_cfft_instance_f32 csky_cfft_sR_f32_len512; + extern const csky_cfft_instance_f32 csky_cfft_sR_f32_len1024; + extern const csky_cfft_instance_f32 csky_cfft_sR_f32_len2048; + extern const csky_cfft_instance_f32 csky_cfft_sR_f32_len4096; + + extern const csky_cfft_instance_q31 csky_cfft_sR_q31_len16; + extern const csky_cfft_instance_q31 csky_cfft_sR_q31_len32; + extern const csky_cfft_instance_q31 csky_cfft_sR_q31_len64; + extern const csky_cfft_instance_q31 csky_cfft_sR_q31_len128; + extern const csky_cfft_instance_q31 csky_cfft_sR_q31_len256; + extern const csky_cfft_instance_q31 csky_cfft_sR_q31_len512; + extern const csky_cfft_instance_q31 csky_cfft_sR_q31_len1024; + extern const csky_cfft_instance_q31 csky_cfft_sR_q31_len2048; + extern const csky_cfft_instance_q31 csky_cfft_sR_q31_len4096; + + extern const csky_cfft_instance_q15 csky_cfft_sR_q15_len16; + extern const csky_cfft_instance_q15 csky_cfft_sR_q15_len32; + extern const csky_cfft_instance_q15 csky_cfft_sR_q15_len64; + extern const csky_cfft_instance_q15 csky_cfft_sR_q15_len128; + extern const csky_cfft_instance_q15 csky_cfft_sR_q15_len256; + extern const csky_cfft_instance_q15 csky_cfft_sR_q15_len512; + extern const csky_cfft_instance_q15 csky_cfft_sR_q15_len1024; + extern const csky_cfft_instance_q15 csky_cfft_sR_q15_len2048; + extern const csky_cfft_instance_q15 csky_cfft_sR_q15_len4096; + + extern csky_rfft_instance_q15 csky_rfft_sR_q15_len32; + extern csky_rfft_instance_q15 csky_rfft_sR_q15_len64; + extern csky_rfft_instance_q15 csky_rfft_sR_q15_len128; + extern csky_rfft_instance_q15 csky_rfft_sR_q15_len256; + extern csky_rfft_instance_q15 csky_rfft_sR_q15_len512; + extern csky_rfft_instance_q15 csky_rfft_sR_q15_len1024; + extern csky_rfft_instance_q15 csky_rfft_sR_q15_len2048; + extern csky_rfft_instance_q15 csky_rfft_sR_q15_len4096; + extern csky_rfft_instance_q15 csky_rfft_sR_q15_len8192; + + + extern csky_rfft_instance_q15 csky_inv_rfft_sR_q15_len32; + extern csky_rfft_instance_q15 csky_inv_rfft_sR_q15_len64; + extern csky_rfft_instance_q15 csky_inv_rfft_sR_q15_len128; + extern csky_rfft_instance_q15 csky_inv_rfft_sR_q15_len256; + extern csky_rfft_instance_q15 csky_inv_rfft_sR_q15_len512; + extern csky_rfft_instance_q15 csky_inv_rfft_sR_q15_len1024; + extern csky_rfft_instance_q15 csky_inv_rfft_sR_q15_len2048; + extern csky_rfft_instance_q15 csky_inv_rfft_sR_q15_len4096; + extern csky_rfft_instance_q15 csky_inv_rfft_sR_q15_len8192; + + + extern csky_rfft_instance_q31 csky_rfft_sR_q31_len32; + extern csky_rfft_instance_q31 csky_rfft_sR_q31_len64; + extern csky_rfft_instance_q31 csky_rfft_sR_q31_len128; + extern csky_rfft_instance_q31 csky_rfft_sR_q31_len256; + extern csky_rfft_instance_q31 csky_rfft_sR_q31_len512; + extern csky_rfft_instance_q31 csky_rfft_sR_q31_len1024; + extern csky_rfft_instance_q31 csky_rfft_sR_q31_len2048; + extern csky_rfft_instance_q31 csky_rfft_sR_q31_len4096; + extern csky_rfft_instance_q31 csky_rfft_sR_q31_len8192; + + extern csky_rfft_instance_q31 csky_inv_rfft_sR_q31_len32; + extern csky_rfft_instance_q31 csky_inv_rfft_sR_q31_len64; + extern csky_rfft_instance_q31 csky_inv_rfft_sR_q31_len128; + extern csky_rfft_instance_q31 csky_inv_rfft_sR_q31_len256; + extern csky_rfft_instance_q31 csky_inv_rfft_sR_q31_len512; + extern csky_rfft_instance_q31 csky_inv_rfft_sR_q31_len1024; + extern csky_rfft_instance_q31 csky_inv_rfft_sR_q31_len2048; + extern csky_rfft_instance_q31 csky_inv_rfft_sR_q31_len4096; + extern csky_rfft_instance_q31 csky_inv_rfft_sR_q31_len8192; + + + extern csky_rfft_fast_instance_f32 csky_rfft_sR_f32_len32; + extern csky_rfft_fast_instance_f32 csky_rfft_sR_f32_len64; + extern csky_rfft_fast_instance_f32 csky_rfft_sR_f32_len128; + extern csky_rfft_fast_instance_f32 csky_rfft_sR_f32_len256; + extern csky_rfft_fast_instance_f32 csky_rfft_sR_f32_len512; + extern csky_rfft_fast_instance_f32 csky_rfft_sR_f32_len1024; + extern csky_rfft_fast_instance_f32 csky_rfft_sR_f32_len2048; + extern csky_rfft_fast_instance_f32 csky_rfft_sR_f32_len4096; + extern csky_rfft_fast_instance_f32 csky_rfft_sR_f32_len8192; + + extern csky_dct4_instance_q15 csky_dct4_sR_q15_len128; + extern csky_dct4_instance_q15 csky_dct4_sR_q15_len512; + extern csky_dct4_instance_q15 csky_dct4_sR_q15_len2048; + extern csky_dct4_instance_q15 csky_dct4_sR_q15_len8192; + + extern csky_dct4_instance_q31 csky_dct4_sR_q31_len128; + extern csky_dct4_instance_q31 csky_dct4_sR_q31_len512; + extern csky_dct4_instance_q31 csky_dct4_sR_q31_len2048; + extern csky_dct4_instance_q31 csky_dct4_sR_q31_len8192; + + extern csky_dct4_instance_f32 csky_dct4_sR_f32_len128; + extern csky_dct4_instance_f32 csky_dct4_sR_f32_len512; + extern csky_dct4_instance_f32 csky_dct4_sR_f32_len2048; + extern csky_dct4_instance_f32 csky_dct4_sR_f32_len8192; +#endif diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_math.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_math.h new file mode 100644 index 00000000..d7adfecb --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_math.h @@ -0,0 +1,4637 @@ +/* + * Copyright (C) 2016-2019 C-SKY Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file csky_math.h + * @brief Public header file for CSI DSP Library. + * @version V1.0 + * @date 20. Dec 2016 + ******************************************************************************/ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CSI math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } csky_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function csky_mat_init_f32(), csky_mat_init_q31() + * and csky_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * csky_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * csky_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * csky_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     CSKY_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     CSKY_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     CSKY_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return CSKY_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + + +/** + * @defgroup groupYunvoice Yunvoice Functions + * These functions are designed for Yunvoice project, which are modified + * according to the CEVA DSP functions. So, one can porting the software + * from CEVA to CSKY straightforwardly. + */ + +/** + * @defgroup groupExamples Examples + */ + + +#ifndef _CSKY_MATH_H +#define _CSKY_MATH_H + +#define __CSI_GENERIC /* disable NVIC and Systick functions */ + +#include "csi_core.h" + +#include +#undef __CSI_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #define ALIGN4 __attribute__((aligned(4))) +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + +__ALWAYS_STATIC_INLINE int32_t __SSAT_31(int32_t x) +{ + int32_t res = x; + if (x > 0x3fffffff) { + res = 0x3fffffff; + } else if (x < -1073741824) { + res = -1073741824; + } + + return res; +} + +__ALWAYS_STATIC_INLINE int32_t __SSAT_16(int32_t x) +{ + int32_t res = x; + if (x > 0x7fff) { + res = 0x7fff; + } else if (x < -32768) { + res = -32768; + } + + return res; +} + +__ALWAYS_STATIC_INLINE int32_t __SSAT_8(int32_t x) +{ + int32_t res = x; + if (x > 0x7f) { + res = 0x7f; + } else if (x < -128) { + res = -128; + } + + return res; +} + +#ifdef CSKY_SIMD +/* SMMLAR */ +__ALWAYS_STATIC_INLINE int32_t multAcc_32x32_keep32_R(int32_t a, int32_t x, int32_t y) +{ + __ASM volatile("mula.s32.rhs %0, %1, %2\n\t" + :"=r" (a), "=r" (x), "=r" (y) : "0" (a), "1" (x), "2" (y)); + return a; +} + +/* SMMLSR */ +__ALWAYS_STATIC_INLINE int32_t multSub_32x32_keep32_R(int32_t a, int32_t x, int32_t y) +{ + __ASM volatile("muls.s32.rhs %0, %1, %2\n\t" + :"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y)); + return a; +} + +/* SMMULR */ +__ALWAYS_STATIC_INLINE int32_t mult_32x32_keep32_R(int32_t x, int32_t y) +{ + int32_t a; + __ASM volatile("mul.s32.rh %0, %1, %2\n\t" + :"=r" (a), "=r" (x), "=r" (y): "1" (x), "2" (y)); + return a; +} + +/* SMMLA */ +__ALWAYS_STATIC_INLINE int32_t multAcc_32x32_keep32(int32_t a, int32_t x, int32_t y) +{ + __ASM volatile("mula.s32.hs %0, %1, %2\n\t" + :"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y)); + return a; +} + +/* SMMLS */ +__ALWAYS_STATIC_INLINE int32_t multSub_32x32_keep32(int32_t a, int32_t x, int32_t y) +{ + __ASM volatile("muls.s32.hs %0, %1, %2\n\t" + :"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y)); + return a; +} + +/* SMMUL */ +__ALWAYS_STATIC_INLINE int32_t mult_32x32_keep32(int32_t x, int32_t y) +{ + int32_t a; + __ASM volatile("mul.s32.h %0, %1, %2\n\t" + :"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y)); + return a; +} + +__ALWAYS_STATIC_INLINE int32_t multAcc_16x16_keep32(int32_t a, int16_t x, int16_t y) +{ + __ASM volatile("mulall.s16 %0, %1, %2\n\t" + :"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y)); + return a; +} + +__ALWAYS_STATIC_INLINE int64_t multAcc_16x16_keep64(int64_t a, int16_t x, int16_t y) +{ + __ASM volatile("mulall.s16.e %0, %1, %2\n\t" + :"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y)); + return a; +} + +__ALWAYS_STATIC_INLINE int64_t mult_32x32_keep64(int32_t x, int32_t y) +{ + int64_t a; + __ASM volatile("mul.s32 %0, %1, %2\n\t" + :"=r" (a), "=r" (x), "=r" (y): "1" (x), "2" (y)); + return a; +} + +__ALWAYS_STATIC_INLINE int64_t multAcc_32x32_keep64(int64_t a, int32_t x, int32_t y) +{ + __ASM volatile("mula.s32 %0, %1, %2\n\t" + :"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y)); + return a; +} + +__ALWAYS_STATIC_INLINE int32_t mult_32x32_dext_31(int32_t x, int32_t y) +{ + int64_t tmp1; + int32_t tmp2; + __ASM volatile("mul.s32 %0, %1, %2\n\t" + "dexti %3, %0, %R0, 31" + :"=r" (tmp1), "=r" (x), "=r" (y), "=r" (tmp2): "1" (x), "2" (y)); + return tmp2; +} + +__ALWAYS_STATIC_INLINE int32_t mult_32x32_dext_30(int32_t x, int32_t y) +{ + int64_t tmp1; + int32_t tmp2; + __ASM volatile("mul.s32 %0, %1, %2\n\t" + "dexti %3, %0, %R0, 30" + :"=r" (tmp1), "=r" (x), "=r" (y), "=r" (tmp2): "1" (x), "2" (y)); + return tmp2; +} + +__ALWAYS_STATIC_INLINE int32_t mult_32x32_dext_4(int32_t x, int32_t y) +{ + int64_t tmp1; + int32_t tmp2; + __ASM volatile("mul.s32 %0, %1, %2\n\t" + "dexti %3, %0, %R0, 4" + :"=r" (tmp1), "=r" (x), "=r" (y), "=r" (tmp2): "1" (x), "2" (y)); + return tmp2; +} + +__ALWAYS_STATIC_INLINE int32_t mult_32x32_dext_33(int32_t x, int32_t y) +{ + int64_t tmp1; + int32_t tmp2; + __ASM volatile("mul.s32 %0, %1, %2\n\t" + "asri %3, %R0, 1" + :"=r" (tmp1), "=r" (x), "=r" (y), "=r" (tmp2): "1" (x), "2" (y)); + return tmp2; +} + +__ALWAYS_STATIC_INLINE int32_t dext_31(int64_t x) +{ + int32_t tmp1; + __ASM volatile( + "dexti %0, %1, %R1, 31" + :"=r" (tmp1), "=r" (x) : "1" (x)); + return tmp1; +} + +__ALWAYS_STATIC_INLINE int32_t mult_l16xl16_keep32(int32_t x, int32_t y) +{ + int32_t a; + __ASM volatile("mulll.s16 %0, %1, %2\n\t" + :"=r" (a), "=r" (x), "=r" (y): "1" (x), "2" (y)); + return a; +} + +__ALWAYS_STATIC_INLINE int32_t mult_h16xl16_keep32(int32_t x, int32_t y) +{ + int32_t a; + __ASM volatile("mulhl.s16 %0, %1, %2\n\t" + :"=r" (a), "=r" (x), "=r" (y): "1" (x), "2" (y)); + return a; +} + +__ALWAYS_STATIC_INLINE int32_t mult_h16xh16_keep32(int32_t x, int32_t y) +{ + int32_t a; + __ASM volatile("mulhh.s16 %0, %1, %2\n\t" + :"=r" (a), "=r" (x), "=r" (y): "1" (x), "2" (y)); + return a; +} + +#endif + + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + CSKY_MATH_SUCCESS = 0, /**< No error */ + CSKY_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + CSKY_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + CSKY_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + CSKY_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + CSKY_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + CSKY_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } csky_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief 32-bit fractional complex data type in 1.31 format. + */ + typedef struct + { + q31_t re; + q31_t im; + } cq31_t; + /** + * @brief 16-bit fractional complex data type in 1.15 format. + */ + typedef struct + { + q15_t re; + q15_t im; + } cq15_t; + /** + * @brief definition to read/write two 16 bit values. + */ + #define __SIMD32_TYPE int32_t + #define CSI_UNUSED __attribute__((unused)) + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (CSKY_MATH_NO_SIMD) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef CSKY_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } csky_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } csky_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } csky_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } csky_fir_instance_f32; + + void csky_fir_q7( + const csky_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + void csky_fir_init_q7( + csky_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + void csky_fir_q15( + const csky_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + void csky_fir_fast_q15( + const csky_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + csky_status csky_fir_init_q15( + csky_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + void csky_fir_q31( + const csky_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + void csky_fir_fast_q31( + const csky_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + void csky_fir_init_q31( + csky_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + void csky_fir_f32( + const csky_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + void csky_fir_init_f32( + csky_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } csky_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } csky_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } csky_biquad_casd_df1_inst_f32; + + void csky_biquad_cascade_df1_q15( + const csky_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + void csky_biquad_cascade_df1_init_q15( + csky_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + void csky_biquad_cascade_df1_fast_q15( + const csky_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + void csky_biquad_cascade_df1_q31( + const csky_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + void csky_biquad_cascade_df1_fast_q31( + const csky_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + void csky_biquad_cascade_df1_init_q31( + csky_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + void csky_biquad_cascade_df1_f32( + const csky_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + void csky_biquad_cascade_df1_init_f32( + csky_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } csky_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } csky_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } csky_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } csky_matrix_instance_q31; + + csky_status csky_mat_add_f32( + const csky_matrix_instance_f32 * pSrcA, + const csky_matrix_instance_f32 * pSrcB, + csky_matrix_instance_f32 * pDst); + + csky_status csky_mat_add_q15( + const csky_matrix_instance_q15 * pSrcA, + const csky_matrix_instance_q15 * pSrcB, + csky_matrix_instance_q15 * pDst); + + csky_status csky_mat_add_q31( + const csky_matrix_instance_q31 * pSrcA, + const csky_matrix_instance_q31 * pSrcB, + csky_matrix_instance_q31 * pDst); + + csky_status csky_mat_cmplx_mult_f32( + const csky_matrix_instance_f32 * pSrcA, + const csky_matrix_instance_f32 * pSrcB, + csky_matrix_instance_f32 * pDst); + + csky_status csky_mat_cmplx_mult_q15( + const csky_matrix_instance_q15 * pSrcA, + const csky_matrix_instance_q15 * pSrcB, + csky_matrix_instance_q15 * pDst); + + csky_status csky_mat_cmplx_mult_q31( + const csky_matrix_instance_q31 * pSrcA, + const csky_matrix_instance_q31 * pSrcB, + csky_matrix_instance_q31 * pDst); + + csky_status csky_mat_trans_f32( + const csky_matrix_instance_f32 * pSrc, + csky_matrix_instance_f32 * pDst); + + csky_status csky_mat_trans_q15( + const csky_matrix_instance_q15 * pSrc, + csky_matrix_instance_q15 * pDst); + + csky_status csky_mat_trans_q31( + const csky_matrix_instance_q31 * pSrc, + csky_matrix_instance_q31 * pDst); + + csky_status csky_mat_mult_f32( + const csky_matrix_instance_f32 * pSrcA, + const csky_matrix_instance_f32 * pSrcB, + csky_matrix_instance_f32 * pDst); + + csky_status csky_mat_mult_q15( + const csky_matrix_instance_q15 * pSrcA, + const csky_matrix_instance_q15 * pSrcB, + csky_matrix_instance_q15 * pDst); + + csky_status csky_mat_mult_fast_q15( + const csky_matrix_instance_q15 * pSrcA, + const csky_matrix_instance_q15 * pSrcB, + csky_matrix_instance_q15 * pDst); + + csky_status csky_mat_mult_q31( + const csky_matrix_instance_q31 * pSrcA, + const csky_matrix_instance_q31 * pSrcB, + csky_matrix_instance_q31 * pDst); + + csky_status csky_mat_mult_trans_q31( + const csky_matrix_instance_q31 * pSrcA, + const csky_matrix_instance_q31 * pSrcB, + csky_matrix_instance_q31 * pDst); + + csky_status csky_mat_mult_fast_q31( + const csky_matrix_instance_q31 * pSrcA, + const csky_matrix_instance_q31 * pSrcB, + csky_matrix_instance_q31 * pDst); + + csky_status csky_mat_sub_f32( + const csky_matrix_instance_f32 * pSrcA, + const csky_matrix_instance_f32 * pSrcB, + csky_matrix_instance_f32 * pDst); + + csky_status csky_mat_sub_q15( + const csky_matrix_instance_q15 * pSrcA, + const csky_matrix_instance_q15 * pSrcB, + csky_matrix_instance_q15 * pDst); + + csky_status csky_mat_sub_q31( + const csky_matrix_instance_q31 * pSrcA, + const csky_matrix_instance_q31 * pSrcB, + csky_matrix_instance_q31 * pDst); + + csky_status csky_mat_scale_f32( + const csky_matrix_instance_f32 * pSrc, + float32_t scale, + csky_matrix_instance_f32 * pDst); + + csky_status csky_mat_scale_q15( + const csky_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + csky_matrix_instance_q15 * pDst); + + csky_status csky_mat_scale_q31( + const csky_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + csky_matrix_instance_q31 * pDst); + + void csky_mat_init_q31( + csky_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + void csky_mat_init_q15( + csky_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + void csky_mat_init_f32( + csky_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q15_t A1; + q15_t A2; + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } csky_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } csky_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } csky_pid_instance_f32; + + void csky_pid_init_f32( + csky_pid_instance_f32 * S, + int32_t resetStateFlag); + + void csky_pid_reset_f32( + csky_pid_instance_f32 * S); + + void csky_pid_init_q31( + csky_pid_instance_q31 * S, + int32_t resetStateFlag); + + void csky_pid_reset_q31( + csky_pid_instance_q31 * S); + + void csky_pid_init_q15( + csky_pid_instance_q15 * S, + int32_t resetStateFlag); + + void csky_pid_reset_q15( + csky_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } csky_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } csky_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } csky_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } csky_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } csky_bilinear_interp_instance_q7; + + void csky_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + void csky_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + void csky_mult_rnd_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + void csky_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + void csky_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } csky_cfft_radix2_instance_q15; + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } csky_cfft_radix4_instance_q15; + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } csky_cfft_radix2_instance_q31; + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } csky_cfft_radix4_instance_q31; + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } csky_cfft_radix2_instance_f32; + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } csky_cfft_radix4_instance_f32; + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } csky_cfft_instance_q15; + +void csky_cfft_q15( + const csky_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } csky_cfft_instance_q31; + +void csky_cfft_q31( + const csky_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } csky_cfft_instance_f32; + + void csky_cfft_f32( + const csky_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const csky_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } csky_rfft_instance_q15; + + csky_status csky_rfft_init_q15( + csky_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void csky_rfft_q15( + const csky_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const csky_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } csky_rfft_instance_q31; + + csky_status csky_rfft_init_q31( + csky_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void csky_rfft_q31( + const csky_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + csky_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } csky_rfft_instance_f32; + + csky_status csky_rfft_init_f32( + csky_rfft_instance_f32 * S, + csky_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void csky_rfft_f32( + const csky_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + csky_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } csky_rfft_fast_instance_f32 ; + +csky_status csky_rfft_fast_init_f32 ( + csky_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void csky_rfft_fast_f32( + csky_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + csky_rfft_fast_instance_f32 *pRfft; /**< points to the real FFT fast instance. */ + csky_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } csky_dct4_instance_f32; + + csky_status csky_dct4_init_f32( + csky_dct4_instance_f32 * S, + csky_rfft_fast_instance_f32 * S_RFFT, + csky_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + void csky_dct4_f32( + const csky_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + csky_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + csky_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } csky_dct4_instance_q31; + + csky_status csky_dct4_init_q31( + csky_dct4_instance_q31 * S, + csky_rfft_instance_q31 * S_RFFT, + csky_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + void csky_dct4_q31( + const csky_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + csky_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + csky_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } csky_dct4_instance_q15; + + csky_status csky_dct4_init_q15( + csky_dct4_instance_q15 * S, + csky_rfft_instance_q15 * S_RFFT, + csky_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + void csky_dct4_q15( + const csky_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + void csky_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + void csky_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + void csky_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + void csky_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + void csky_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + void csky_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + void csky_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + void csky_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + void csky_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + void csky_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + void csky_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + void csky_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + void csky_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + void csky_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + void csky_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + void csky_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + void csky_abs_max_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + void csky_abs_max_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + void csky_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + void csky_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + void csky_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + void csky_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + void csky_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + void csky_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + void csky_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + void csky_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + void csky_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + void csky_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + void csky_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + void csky_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + void csky_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + void csky_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + void csky_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + void csky_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + void csky_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + void csky_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + void csky_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + void csky_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + void csky_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + void csky_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + void csky_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + void csky_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + void csky_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + void csky_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + void csky_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + void csky_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + void csky_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + void csky_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + void csky_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + void csky_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + csky_status csky_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + csky_status csky_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + csky_status csky_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + csky_status csky_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + csky_status csky_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + csky_status csky_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + csky_status csky_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + csky_status csky_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + csky_status csky_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * functions for the yunVoice functions. + */ + q15_t csky_dsp_lib_vec_max_abs16( + q15_t * A, + uint32_t N); + + q31_t csky_dsp_lib_vec_max_abs32( + q31_t * A, + uint32_t N); + + void csky_dsp_lib_vec_abs16( + q15_t * A, + uint32_t N, + q15_t * C); + + void csky_dsp_lib_vec_abs32( + q31_t * A, + uint32_t N, + q31_t * C); + + void csky_dsp_lib_vec_add16( + q15_t * A, + q15_t * B, + uint32_t N, + q15_t * C); + + void csky_dsp_lib_vec_add32( + q31_t * A, + q31_t * B, + uint32_t N, + q31_t * C); + + void csky_dsp_lib_vec_cx_conj_q15( + q15_t * A, + uint32_t N, + q15_t * B); + + void csky_dsp_lib_vec_cx_conj_q31( + q31_t * A, + uint32_t N, + q31_t * C); + + q31_t csky_dsp_lib_vec_dot_q15( + q15_t * A, + q15_t * B, + uint32_t N); + + q31_t csky_dsp_lib_vec_dot_q31( + q31_t * A, + q31_t * B, + uint32_t N); + + void csky_dsp_lib_mat_cx_add16( + cq15_t * A, + cq15_t * B, + uint32_t N, + uint32_t M, + cq15_t * C); + + void csky_dsp_lib_mat_cx_add32( + cq31_t * A, + cq31_t * B, + uint32_t N, + uint32_t M, + cq31_t * C); + + void csky_dsp_lib_mat_cx_mul_q15( + cq15_t * A, + cq15_t * B, + uint32_t N, + uint32_t M, + uint32_t L, + cq15_t * C); + + void csky_dsp_lib_mat_cx_mul_q31( + cq31_t * A, + cq31_t * B, + uint32_t N, + uint32_t M, + uint32_t L, + cq31_t * C); + + void csky_dsp_lib_mat_cx_sub16( + cq15_t * A, + cq15_t * B, + uint32_t N, + uint32_t M, + cq15_t * C); + + void csky_dsp_lib_mat_cx_sub32( + cq31_t * A, + cq31_t * B, + uint32_t N, + uint32_t M, + cq31_t * C); + + void csky_dsp_lib_vec_mul_q15( + q15_t * A, + q15_t * B, + uint32_t N, + q15_t * C); + + void csky_dsp_lib_vec_mul_q31( + q31_t * A, + q31_t * B, + uint32_t N, + q31_t * C); + + q31_t csky_dsp_lib_pow_int32( + q31_t arg_in_x, + q15_t arg_exp_in_x, + q31_t arg_in_y, + q15_t arg_exp_in_y, + q31_t *arg_exp_out); + + void csky_dsp_lib_vec_scale_q15( + q15_t * A, + q15_t scaleFract, + int8_t shift, + q15_t * B, + uint32_t N); + + void csky_dsp_lib_vec_scale_q31( + q31_t * A, + q31_t scaleFract, + int8_t shift, + q31_t * B, + uint32_t N); + + void csky_dsp_lib_vec_shf16( + q15_t * A, + int8_t shift_val, + uint32_t N, + q15_t * C); + + void csky_dsp_lib_vec_shf32( + q31_t * A, + q31_t shift_val, + uint32_t N, + q31_t * C); + + q15_t csky_dsp_lib_sqrt_int32( + q31_t x, + uint32_t rnd_flag); + + void csky_dsp_lib_vec_sub16( + q15_t * A, + q15_t * B, + uint32_t N, + q15_t * C); + + void csky_dsp_lib_vec_sub32( + q31_t * A, + q31_t * B, + uint32_t N, + q31_t * C); + + q63_t csky_dsp_lib_vec_sum16( + q15_t * A, + uint32_t N); + + q63_t csky_dsp_lib_vec_sum32( + q31_t * A, + uint32_t N); + + void csky_fft_lib_cx16_fft( + q31_t log2_buf_len, + q15_t * in_buf, + q15_t * out_buf, + const q15_t * twi_table, + const uint16_t * bitrev_tbl, + q15_t * temp_buf, + q7_t * ScaleShift, + q31_t br); + + void csky_fft_lib_cx32_fft( + q31_t log2_buf_len, + q31_t * in_buf, + q31_t * out_buf, + const q31_t * twi_table, + const uint16_t * bitrev_tbl, + q31_t * temp_buf, + q31_t br); + + void csky_fft_lib_cx16_ifft( + q31_t log2_buf_len, + q15_t * in_buf, + q15_t * out_buf, + const q15_t * twi_table, + const uint16_t * bitrev_tbl, + q15_t * temp_buf, + q7_t * ScaleShift, + q31_t br); + + void csky_fft_lib_cx32_ifft( + q31_t log2_buf_len, + q31_t * in_buf, + q31_t * out_buf, + const q31_t * twi_table, + const uint16_t * bitrev_tbl, + q31_t * temp_buf, + q31_t br); + + void csky_fft_lib_int16_fft( + q31_t log2_buf_len, + q15_t * in_buf, + q15_t * out_buf, + const q15_t * twi_table, + const q15_t * last_stage_twi_table, + const uint16_t * bitrev_tbl, + q15_t * temp_buf, + q7_t * ScaleShift, + q31_t br); + + void csky_fft_lib_int32_fft( + q31_t log2_buf_len, + q31_t * in_buf, + q31_t * out_buf, + const q31_t * twi_table, + const q31_t * last_stage_twi_table, + const uint16_t * bitrev_tbl, + q31_t * temp_buf, + q31_t br); + + void csky_fft_lib_int16_ifft( + q31_t log2_buf_len, + q15_t * in_buf, + q15_t * out_buf, + const q15_t * twi_table, + const q15_t * last_stage_twi_table, + const uint16_t * bitrev_tbl, + q15_t * temp_buf, + q7_t * ScaleShift, + q31_t br); + + void csky_fft_lib_int32_ifft( + q31_t log2_buf_len, + q31_t * in_buf, + q31_t * out_buf, + const q31_t * twi_table, + const q31_t * last_stage_twi_table, + const uint16_t * bitrev_tbl, + q31_t * temp_buf, + q31_t br); + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } csky_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } csky_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } csky_fir_decimate_instance_f32; + + void csky_fir_decimate_f32( + const csky_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + csky_status csky_fir_decimate_init_f32( + csky_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + void csky_fir_decimate_q15( + const csky_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + void csky_fir_decimate_fast_q15( + const csky_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + csky_status csky_fir_decimate_init_q15( + csky_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + void csky_fir_decimate_q31( + const csky_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + void csky_fir_decimate_fast_q31( + csky_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + csky_status csky_fir_decimate_init_q31( + csky_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } csky_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } csky_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } csky_fir_interpolate_instance_f32; + + void csky_fir_interpolate_q15( + const csky_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + csky_status csky_fir_interpolate_init_q15( + csky_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + void csky_fir_interpolate_q31( + const csky_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + csky_status csky_fir_interpolate_init_q31( + csky_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + void csky_fir_interpolate_f32( + const csky_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + csky_status csky_fir_interpolate_init_f32( + csky_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } csky_biquad_cas_df1_32x64_ins_q31; + + void csky_biquad_cas_df1_32x64_q31( + const csky_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + void csky_biquad_cas_df1_32x64_init_q31( + csky_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } csky_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } csky_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } csky_biquad_cascade_df2T_instance_f64; + + void csky_biquad_cascade_df2T_f32( + const csky_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + void csky_biquad_cascade_stereo_df2T_f32( + const csky_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + void csky_biquad_cascade_df2T_f64( + const csky_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + void csky_biquad_cascade_df2T_init_f32( + csky_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + void csky_biquad_cascade_stereo_df2T_init_f32( + csky_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + void csky_biquad_cascade_df2T_init_f64( + csky_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } csky_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } csky_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } csky_fir_lattice_instance_f32; + + void csky_fir_lattice_init_q15( + csky_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + void csky_fir_lattice_q15( + const csky_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + void csky_fir_lattice_init_q31( + csky_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + void csky_fir_lattice_q31( + const csky_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + void csky_fir_lattice_init_f32( + csky_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + void csky_fir_lattice_f32( + const csky_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } csky_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } csky_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } csky_iir_lattice_instance_f32; + + void csky_iir_lattice_f32( + const csky_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + void csky_iir_lattice_init_f32( + csky_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + void csky_iir_lattice_q31( + const csky_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + void csky_iir_lattice_init_q31( + csky_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + void csky_iir_lattice_q15( + const csky_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + void csky_iir_lattice_init_q15( + csky_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } csky_lms_instance_f32; + + void csky_lms_f32( + const csky_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + void csky_lms_init_f32( + csky_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } csky_lms_instance_q15; + + void csky_lms_init_q15( + csky_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + void csky_lms_q15( + const csky_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } csky_lms_instance_q31; + + void csky_lms_q31( + const csky_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + void csky_lms_init_q31( + csky_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } csky_lms_norm_instance_f32; + + void csky_lms_norm_f32( + csky_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + void csky_lms_norm_init_f32( + csky_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } csky_lms_norm_instance_q31; + + void csky_lms_norm_q31( + csky_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + void csky_lms_norm_init_q31( + csky_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } csky_lms_norm_instance_q15; + + void csky_lms_norm_q15( + csky_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + void csky_lms_norm_init_q15( + csky_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + void csky_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + void csky_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + void csky_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + void csky_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + void csky_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + void csky_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + void csky_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + void csky_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + void csky_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } csky_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } csky_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } csky_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } csky_fir_sparse_instance_q7; + + void csky_fir_sparse_f32( + csky_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + void csky_fir_sparse_init_f32( + csky_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + void csky_fir_sparse_q31( + csky_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + void csky_fir_sparse_init_q31( + csky_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + void csky_fir_sparse_q15( + csky_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + void csky_fir_sparse_init_q15( + csky_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + void csky_fir_sparse_q7( + csky_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + void csky_fir_sparse_init_q7( + csky_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + void csky_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + void csky_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + void csky_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + void csky_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + void csky_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + void csky_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + void csky_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + void csky_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + void csky_vsqrt_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + void csky_vsqrt_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + void csky_vsqrt_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t numSamples); + +/** + * @ingroup groupController + */ + +/** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+ *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ *    A0 = Kp + Ki + Kd
+ *    A1 = (-Kp ) - (2 * Kd )
+ *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup PID + * @{ + */ + +/** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + __ALWAYS_STATIC_INLINE float32_t csky_pid_f32( + csky_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + +/** + * @} +*/ // end of PID group + + +/** + * @addtogroup PID + * @{ + */ + +/** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + __ALWAYS_STATIC_INLINE q31_t csky_pid_q31( + csky_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + #ifdef CSKY_SIMD + /* acc = A0 * x[n] */ + acc = mult_32x32_keep64(S->A0, in); + + /* acc += A1 * x[n-1] */ + acc = multAcc_32x32_keep64(acc, S->A1, S->state[0]); + + /* acc += A2 * x[n-2] */ + acc = multAcc_32x32_keep64(acc, S->A2, S->state[1]); + + /* convert output to 1.31 format to add y[n-1] */ + out = dext_31(acc); + #else + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + #endif + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + +/** + * @} + */ // end of PID group + +/** + * @addtogroup PID + * @{ + */ +/** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + __ALWAYS_STATIC_INLINE q15_t csky_pid_q15( + csky_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT_16((acc >> 15))); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } +/** + * @} + */ // end of PID group + + csky_status csky_mat_inverse_f32( + const csky_matrix_instance_f32 * src, + csky_matrix_instance_f32 * dst); + + csky_status csky_mat_inverse_f64( + const csky_matrix_instance_f64 * src, + csky_matrix_instance_f64 * dst); + +/** + * @ingroup groupController + */ + +/** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup clarke + * @{ + */ + +/** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + __ALWAYS_STATIC_INLINE void csky_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + +/** + * @} + */ // end of clarke group + + +/** + * @addtogroup clarke + * @{ + */ + +/** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + __ALWAYS_STATIC_INLINE void csky_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + #ifdef CSKY_SIMD + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = mult_32x32_dext_30(Ia, 0x24F34E8B); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = mult_32x32_dext_30(Ib, 0x49E69D16); + #else + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + #endif + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + +/** + * @} + */ // end of clarke group + + void csky_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @ingroup groupController + */ +/** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + __ALWAYS_STATIC_INLINE void csky_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + +/** + * @} + */ // end of inv_clarke group + +/** + * @addtogroup inv_clarke + * @{ + */ + +/** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + __ALWAYS_STATIC_INLINE void csky_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + #ifdef CSKY_SIMD + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = mult_32x32_dext_31(Ialpha, 0x40000000); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = mult_32x32_dext_31(Ibeta, 0x6ED9EBA1); + #else + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + #endif + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + +/** + * @} + */ // end of inv_clarke group + + void csky_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +/** + * @ingroup groupController + */ +/** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ +/** + * @addtogroup park + * @{ + */ +/** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + __ALWAYS_STATIC_INLINE void csky_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) +{ + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; +} +/** + * @} + */ // end of park group + +/** + * @addtogroup park + * @{ + */ +/** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + __ALWAYS_STATIC_INLINE void csky_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) +{ +#ifdef CSKY_SIMD + __ASM volatile( + "rmul.s32.h t0, %0, %3\n\t" + "rmul.s32.h t1, %1, %2\n\t" + "add.s32.s t0, t0, t1\n\t" + "st.w t0, (%4, 0x0)\n\t" + "rmul.s32.h t0, %0, %2\n\t" + "rmul.s32.h t1, %1, %3\n\t" + "sub.s32.s t1, t1, t0\n\t" + "st.w t1, (%5, 0x0)\n\t" + ::"r"(Ialpha),"r"(Ibeta),"r"(sinVal),"r"(cosVal),"r"(pId),"r"(pIq) + :"t0","t1", "memory"); +#else + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = clip_q63_to_q31 (((q63_t) (Ialpha) * (cosVal)) >> 31); + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = clip_q63_to_q31 (((q63_t) (Ibeta) * (sinVal)) >> 31); + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = clip_q63_to_q31 (((q63_t) (Ialpha) * (sinVal)) >> 31); + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = clip_q63_to_q31 (((q63_t) (Ibeta) * (cosVal)) >> 31); + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); +#endif +} +/** + * @} + */ // end of park group + + void csky_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +/** + * @ingroup groupController + */ +/** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ +/** + * @addtogroup inv_park + * @{ + */ + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + __ALWAYS_STATIC_INLINE void csky_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) +{ + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; +} +/** + * @} + */ // end of inv_park group + +/** + * @addtogroup inv_park + * @{ + */ +/** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + __ALWAYS_STATIC_INLINE void csky_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) +{ +#ifdef CSKY_SIMD + __ASM volatile( + "rmul.s32.h t0, %0, %3\n\t" + "rmul.s32.h t1, %1, %2\n\t" + "sub.s32.s t0, t0, t1\n\t" + "st.w t0, (%4, 0x0)\n\t" + "rmul.s32.h t0, %0, %2\n\t" + "rmul.s32.h t1, %1, %3\n\t" + "add.s32.s t0, t0, t1\n\t" + "st.w t0, (%5, 0x0)\n\t" + ::"r"(Id),"r"(Iq),"r"(sinVal),"r"(cosVal),"r"(pIalpha),"r"(pIbeta) + :"t0","t1", "memory"); + +#else + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = clip_q63_to_q31 (((q63_t) (Id) * (cosVal)) >> 31); + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = clip_q63_to_q31 (((q63_t) (Iq) * (sinVal)) >> 31); + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = clip_q63_to_q31 (((q63_t) (Id) * (sinVal)) >> 31); + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = clip_q63_to_q31 (((q63_t) (Iq) * (cosVal)) >> 31); + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); +#endif +} + +/** + * @} + */ // end of inv_park group + + void csky_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +/** + * @ingroup groupInterpolation + */ +/** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+ *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ *       where x0, x1 are nearest values of input x
+ *             y0, y1 are nearest values to output y
+ *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ +/** + * @addtogroup LinearInterpolate + * @{ + */ +/** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ +__ALWAYS_STATIC_INLINE float32_t csky_linear_interp_f32( +csky_linear_interp_instance_f32 * S, +float32_t x) +{ + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + } + /* returns output value */ + return (y); +} +/** + * @} + */ // end of LinearInterpolate group + +/** + * @addtogroup LinearInterpolate + * @{ + */ + +/** + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ +__ALWAYS_STATIC_INLINE q31_t csky_linear_interp_q31( +q31_t * pYData, +q31_t x, +uint32_t nValues) +{ + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; +#ifdef CSKY_SIMD + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = mult_32x32_keep32(y0, (0x7FFFFFFF - fract)); + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y = multAcc_32x32_keep32(y, y1, fract); +#else + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); +#endif + /* Convert y to 1.31 format */ + return (y << 1u); + } +} +/** + * @} + */ // end of LinearInterpolate group + +/** + * @addtogroup LinearInterpolate + * @{ + */ +/** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ +__ALWAYS_STATIC_INLINE q15_t csky_linear_interp_q15( +q15_t * pYData, +q31_t x, +uint32_t nValues) +{ + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; +#ifdef CSKY_SIMD + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = mult_32x32_keep64(y0, (0xFFFFF - fract)); + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y = multAcc_32x32_keep64(y, y1, (fract)); +#else + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); +#endif + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } +} +/** + * @} + */ // end of LinearInterpolate group + +/** + * @addtogroup LinearInterpolate + * @{ + */ +/** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ +__ALWAYS_STATIC_INLINE q7_t csky_linear_interp_q7( +q7_t * pYData, +q31_t x, +uint32_t nValues) +{ + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } +} +/** + * @} + */ // end of LinearInterpolate group + + float32_t csky_sin_f32( + float32_t x); + + q31_t csky_sin_q31( + q31_t x); + + q15_t csky_sin_q15( + q15_t x); + + float32_t csky_cos_f32( + float32_t x); + + q31_t csky_cos_q31( + q31_t x); + + q15_t csky_cos_q15( + q15_t x); + + csky_status csky_sqrt_f32( + float32_t in, + float32_t * pOut); + + csky_status csky_sqrt_q31( + q31_t in, + q31_t * pOut); + + csky_status csky_sqrt_q15( + q15_t in, + q15_t * pOut); + + void csky_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + void csky_power_int32( + int32_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + void csky_power_int32( + int32_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + void csky_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + void csky_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + void csky_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + void csky_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + void csky_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + void csky_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + void csky_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + void csky_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + void csky_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + void csky_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + void csky_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + void csky_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + void csky_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + void csky_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + void csky_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + void csky_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + void csky_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + void csky_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + void csky_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + void csky_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + void csky_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + void csky_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + void csky_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + void csky_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + void csky_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + void csky_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + void csky_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + void csky_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + void csky_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + void csky_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + void csky_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + void csky_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + void csky_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + void csky_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + void csky_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + void csky_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + void csky_cmplx_mult_cmplx_re_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + void csky_cmplx_mult_cmplx_re_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + void csky_cmplx_mult_cmplx_re_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + void csky_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + void csky_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + void csky_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + void csky_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + void csky_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + void csky_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + void csky_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + void csky_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + +/** + * @ingroup groupInterpolation + */ +/** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CSI DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+ *   typedef struct
+ *   {
+ *     uint16_t numRows;
+ *     uint16_t numCols;
+ *     float32_t *pData;
+ * } csky_bilinear_interp_instance_f32;
+ *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+ *     XF = floor(x)
+ *     YF = floor(y)
+ *
+ * \par + * The interpolated output point is computed as: + * 
+ *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ +/** + * @addtogroup BilinearInterpolate + * @{ + */ +/** +* +* @brief Floating-point bilinear interpolation. +* @param[in,out] S points to an instance of the interpolation structure. +* @param[in] X interpolation coordinate. +* @param[in] Y interpolation coordinate. +* @return out interpolated value. +*/ +__ALWAYS_STATIC_INLINE float32_t csky_bilinear_interp_f32( +const csky_bilinear_interp_instance_f32 * S, +float32_t X, +float32_t Y) +{ + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + /* return to application */ + return (out); +} +/** + * @} + */ // end of BilinearInterpolate group + +/** + * @addtogroup BilinearInterpolate + * @{ + */ +/** +* +* @brief Q31 bilinear interpolation. +* @param[in,out] S points to an instance of the interpolation structure. +* @param[in] X interpolation coordinate in 12.20 format. +* @param[in] Y interpolation coordinate in 12.20 format. +* @return out interpolated value. +*/ +__ALWAYS_STATIC_INLINE q31_t csky_bilinear_interp_q31( +csky_bilinear_interp_instance_q31 * S, +q31_t X, +q31_t Y) +{ + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; +#ifdef CSKY_SIMD + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = mult_32x32_keep32(x1, (0x7FFFFFFF - xfract)); + acc = mult_32x32_keep32(out, (0x7FFFFFFF - yfract)); + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = mult_32x32_keep32(x2, (0x7FFFFFFF - yfract)); + acc = multAcc_32x32_keep32(acc, out, xfract); + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = mult_32x32_keep32(y1, (0x7FFFFFFF - xfract)); + acc = multAcc_32x32_keep32(acc, out, yfract); + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = mult_32x32_keep32(y2, xfract); + acc = multAcc_32x32_keep32(acc, out, yfract); +#else + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); +#endif + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); +} +/** + * @} + */ // end of BilinearInterpolate group + +/** + * @addtogroup BilinearInterpolate + * @{ + */ +/** +* @brief Q15 bilinear interpolation. +* @param[in,out] S points to an instance of the interpolation structure. +* @param[in] X interpolation coordinate in 12.20 format. +* @param[in] Y interpolation coordinate in 12.20 format. +* @return out interpolated value. +*/ +__ALWAYS_STATIC_INLINE q15_t csky_bilinear_interp_q15( +csky_bilinear_interp_instance_q15 * S, +q31_t X, +q31_t Y) +{ + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ +#ifdef CSKY_SIMD + out = mult_32x32_dext_4(x1, (0xFFFFF - xfract)); + acc = mult_32x32_keep64(out, (0xFFFFF - yfract)); + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = mult_32x32_dext_4(x2, (0xFFFFF - yfract)); + acc = multAcc_32x32_keep64(acc, out, (xfract)); + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = mult_32x32_dext_4(y1, (0xFFFFF - xfract)); + acc = multAcc_32x32_keep64(acc, out, (yfract)); + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = mult_32x32_dext_4(y2, (xfract)); + acc = multAcc_32x32_keep64(acc, out, (yfract)); +#else + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); +#endif + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); +} +/** + * @} + */ // end of BilinearInterpolate group + +/** + * @addtogroup BilinearInterpolate + * @{ + */ +/** +* @brief Q7 bilinear interpolation. +* @param[in,out] S points to an instance of the interpolation structure. +* @param[in] X interpolation coordinate in 12.20 format. +* @param[in] Y interpolation coordinate in 12.20 format. +* @return out interpolated value. +*/ +__ALWAYS_STATIC_INLINE q7_t csky_bilinear_interp_q7( +csky_bilinear_interp_instance_q7 * S, +q31_t X, +q31_t Y) +{ + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); +#ifdef CSKY_SIMD + acc = multAcc_32x32_keep64(acc, out, (0xFFFFF - yfract)); + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc = multAcc_32x32_keep64(acc, out, xfract); + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc = multAcc_32x32_keep64(acc, out, yfract); + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc = multAcc_32x32_keep64(acc, out, xfract); +#else + acc = (((q63_t) out * (0xFFFFF - yfract))); + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); +#endif + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); +} +/** + * @} + */ // end of BilinearInterpolate group + +/** + * @ingroup groupMath + */ + +/** + * @defgroup ShiftRight Right Shift + * + * Shift the input value to right with appointed bits, its basic format is: + * 
+ *     a = (a) >> (shift),   1 =< shift <= bitof(a) - 1.
+ *
+ * The basic format is only designed for q31. + * + * and the extended format should be rounding to +inf: + * 
+ *     a = (a + (1<<(shift - 1)) >> (shift),   1 =< shift <= bitof(a) - 1.
+ *
+ * + * which are designed for q31, q31 positive and q63. + */ + +/** + * @addtogroup ShiftRight + * @{ + */ +/** + * @brief right shift Q31 version + * @param[in] a input value to be shift. + * @param[in] shift input positive value, the number of bits to be shift. + * @param[out] result the shifted a. + * + * Scaling and Overflow Behavior: + * \par + * The function is only used for right shift. So, the value of shift is + * between[1,31]. + */ + __ALWAYS_STATIC_INLINE q31_t csky_shr_q31( + q31_t a, + q31_t shift) +{ + q31_t res; +#ifdef CSKY_SIMD + __ASM volatile( + "asr %0, %1, %2\n\t" + :"=r"(res), "=r"(a),"=r"(shift):"0"(res), "1"(a), "2"(shift)); +#else + res = ((a) >> (shift)); +#endif + return res; +} + +#define SHR(a, shift) csky_shr_q31(a, shift) + +/** + * @} + */ // end of ShiftRight group + + +/** + * @addtogroup ShiftRight + * @{ + */ +/** + * @brief right shift Q31 version + * @param[in] a input value to be shift. + * @param[in] shift input positive value, the number of bits to be shift. + * @param[out] result the shifted a. + * + * Scaling and Overflow Behavior: + * \par + * The function is only used for right shift. So, the value of shift is + * between[1,31]. And the output value is rounding to +inf. + */ + __ALWAYS_STATIC_INLINE q31_t csky_pshr_q31( + q31_t a, + q31_t shift) +{ + q31_t res; +#ifdef CSKY_SIMD + __ASM volatile( + "asr.s32.r %0, %1, %2\n\t" + :"=r"(res), "=r"(a),"=r"(shift):"0"(res), "1"(a), "2"(shift)); +#else + res = (a >= 0?(SHR((a) + (1<<(shift - 1)), shift))\ + :(SHR((a) + ((1<>1) -1, shift))); +#endif + return res; +} + +/** + * @} + */ // end of ShiftRight group + + +/** + * @addtogroup ShiftRight + * @{ + */ +/** + * @brief right shift Q31 version + * @param[in] a input positive value to be shift. + * @param[in] shift input positive value, the number of bits to be shift. + * @param[out] result the shifted a. + * + * Scaling and Overflow Behavior: + * \par + * The function is only used for right shift. So, the value of shift is + * between[1,31]. And the output value is rounding to +inf. + */ + __ALWAYS_STATIC_INLINE q31_t csky_pshr_pos_q31( + q31_t a, + q31_t shift) +{ + q31_t res; +#ifdef CSKY_SIMD + __ASM volatile( + "asr.s32.r %0, %1, %2\n\t" + :"=r"(res), "=r"(a),"=r"(shift):"0"(res), "1"(a), "2"(shift)); +#else + res = SHR((a) + (1<<(shift - 1)), shift); +#endif + return res; +} + +/** + * @} + */ // end of ShiftRight group + + +/** + * @addtogroup ShiftRight + * @{ + */ +/** + * @brief right shift Q63 version + * @param[in] a input value to be shift. + * @param[in] shift input positive value, the number of bits to be shift. + * @param[out] result the shifted a. + * + * Scaling and Overflow Behavior: + * \par + * The function is only used for right shift. So, the value of shift is + * between[1,63]. And the output value is rounding to +inf. + */ + __ALWAYS_STATIC_INLINE q63_t csky_pshr_q63( + q63_t a, + q31_t shift) +{ + q63_t res; +#ifdef CSKY_SIMD + __ASM volatile( + "subi t0, %2, 1\n\t" + "cmphsi t0, 32\n\t" + "bt 1f\n\t" + "movi t1, 1\n\t" + "lsl t0, t1, t0\n\t" + "movi t1, 0\n\t" + "add.s64.s %1, %1, t0\n\t" + "dext %0, %1, %R1, %2\n\t" + "asr %R0, %R1, %2\n\t" + "br 2f\n\t" + "1:\n\t" + "subi %2, %2, 32\n\t" + "subi t0, t0, 32\n\t" + "movi t1, 1\n\t" + "lsl t1, t1, t0\n\t" + "add.s32.s %R1, %R1, t1\n\t" + "asr %0, %R1, %2\n\t" + "asri %R0, %R1, 31\n\t" + "2:\n\t" + :"=r"(res), "=r"(a),"=r"(shift):"0"(res), "1"(a), "2"(shift):"t0", "t1"); +#else + res = (a >= 0?(SHR((a) + ((q63_t)1<<(shift - 1)), shift))\ + :(SHR((a) + (((q63_t)1<>1) -1, shift))); +#endif + return res; +} + +/** + * @} + */ // end of ShiftRight group + +//#define SHR(a, shift) csky_shr_q31(a, shift) +#define PSHR(a, shift) csky_pshr_q31(a, shift) +#define PSHR_POSITIVE(a, shift) csky_pshr_pos_q31(a, shift) +#define PSHR64(a, shift) csky_pshr_q63(a, shift) + + +#ifdef CSKY_SIMD +#else +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _CSKY_MATH_H */ + +/** + * + * End of file. + */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_vdsp2_const_structs.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_vdsp2_const_structs.h new file mode 100644 index 00000000..618f5f92 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_vdsp2_const_structs.h @@ -0,0 +1,232 @@ +/* + * Copyright (C) 2016-2019 C-SKY Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file csky_vdsp2_const_structs.h + * @brief This file has constant structs that are initialized for + * user convenience. For example, some can be given as + * arguments to the csky_vdsp2_cfft_f32() function. + * @version V1.0 + * @date 20. Dec 2016 + ******************************************************************************/ + +#ifndef _CSKY_CONST_STRUCTS_H +#define _CSKY_CONST_STRUCTS_H + +#include "csky_vdsp2_math.h" +#include "csky_common_tables.h" + + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_sR_f32_len16; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_sR_f32_len32; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_sR_f32_len64; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_sR_f32_len128; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_sR_f32_len256; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_sR_f32_len512; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_sR_f32_len1024; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_sR_f32_len2048; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_sR_f32_len4096; + + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_sR_f32_len16; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_sR_f32_len32; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_sR_f32_len64; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_sR_f32_len128; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_sR_f32_len256; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_sR_f32_len512; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_sR_f32_len1024; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_sR_f32_len2048; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_sR_f32_len4096; + + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_fast_sR_f32_len16; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_fast_sR_f32_len32; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_fast_sR_f32_len64; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_fast_sR_f32_len128; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_fast_sR_f32_len256; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_fast_sR_f32_len512; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_fast_sR_f32_len1024; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_fast_sR_f32_len2048; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_fast_sR_f32_len4096; + + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix2_sR_f32_len16; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix2_sR_f32_len32; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix2_sR_f32_len64; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix2_sR_f32_len128; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix2_sR_f32_len256; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix2_sR_f32_len512; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix2_sR_f32_len1024; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix2_sR_f32_len2048; + extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix2_sR_f32_len4096; + + extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_sR_q31_len16; + extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_sR_q31_len32; + extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_sR_q31_len64; + extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_sR_q31_len128; + extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_sR_q31_len256; + extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_sR_q31_len512; + extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_sR_q31_len1024; + extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_sR_q31_len2048; + extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_sR_q31_len4096; + + extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_sR_q15_len16; + extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_sR_q15_len32; + extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_sR_q15_len64; + extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_sR_q15_len128; + extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_sR_q15_len256; + extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_sR_q15_len512; + extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_sR_q15_len1024; + extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_sR_q15_len2048; + extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_sR_q15_len4096; + + extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_fast_sR_q15_len16; + extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_fast_sR_q15_len32; + extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_fast_sR_q15_len64; + extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_fast_sR_q15_len128; + extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_fast_sR_q15_len256; + extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_fast_sR_q15_len512; + extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_fast_sR_q15_len1024; + extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_fast_sR_q15_len2048; + extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_fast_sR_q15_len4096; + + extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_fast_sR_q31_len16; + extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_fast_sR_q31_len32; + extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_fast_sR_q31_len64; + extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_fast_sR_q31_len128; + extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_fast_sR_q31_len256; + extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_fast_sR_q31_len512; + extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_fast_sR_q31_len1024; + extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_fast_sR_q31_len2048; + extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_fast_sR_q31_len4096; + + extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_rfft_sR_q15_len32; + extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_rfft_sR_q15_len64; + extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_rfft_sR_q15_len128; + extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_rfft_sR_q15_len256; + extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_rfft_sR_q15_len512; + extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_rfft_sR_q15_len1024; + extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_rfft_sR_q15_len2048; + extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_rfft_sR_q15_len4096; + extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_rfft_sR_q15_len8192; + + + extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_inv_rfft_sR_q15_len32; + extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_inv_rfft_sR_q15_len64; + extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_inv_rfft_sR_q15_len128; + extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_inv_rfft_sR_q15_len256; + extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_inv_rfft_sR_q15_len512; + extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_inv_rfft_sR_q15_len1024; + extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_inv_rfft_sR_q15_len2048; + extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_inv_rfft_sR_q15_len4096; + extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_inv_rfft_sR_q15_len8192; + + extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_rfft_fast_sR_q15_len32; + extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_rfft_fast_sR_q15_len64; + extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_rfft_fast_sR_q15_len128; + extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_rfft_fast_sR_q15_len256; + extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_rfft_fast_sR_q15_len512; + extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_rfft_fast_sR_q15_len1024; + extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_rfft_fast_sR_q15_len2048; + extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_rfft_fast_sR_q15_len4096; + extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_rfft_fast_sR_q15_len8192; + + + extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_inv_rfft_fast_sR_q15_len32; + extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_inv_rfft_fast_sR_q15_len64; + extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_inv_rfft_fast_sR_q15_len128; + extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_inv_rfft_fast_sR_q15_len256; + extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_inv_rfft_fast_sR_q15_len512; + extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_inv_rfft_fast_sR_q15_len1024; + extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_inv_rfft_fast_sR_q15_len2048; + extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_inv_rfft_fast_sR_q15_len4096; + extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_inv_rfft_fast_sR_q15_len8192; + + + extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_rfft_sR_q31_len32; + extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_rfft_sR_q31_len64; + extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_rfft_sR_q31_len128; + extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_rfft_sR_q31_len256; + extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_rfft_sR_q31_len512; + extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_rfft_sR_q31_len1024; + extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_rfft_sR_q31_len2048; + extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_rfft_sR_q31_len4096; + extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_rfft_sR_q31_len8192; + + extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_inv_rfft_sR_q31_len32; + extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_inv_rfft_sR_q31_len64; + extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_inv_rfft_sR_q31_len128; + extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_inv_rfft_sR_q31_len256; + extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_inv_rfft_sR_q31_len512; + extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_inv_rfft_sR_q31_len1024; + extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_inv_rfft_sR_q31_len2048; + extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_inv_rfft_sR_q31_len4096; + extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_inv_rfft_sR_q31_len8192; + + extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_rfft_fast_sR_q31_len32; + extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_rfft_fast_sR_q31_len64; + extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_rfft_fast_sR_q31_len128; + extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_rfft_fast_sR_q31_len256; + extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_rfft_fast_sR_q31_len512; + extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_rfft_fast_sR_q31_len1024; + extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_rfft_fast_sR_q31_len2048; + extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_rfft_fast_sR_q31_len4096; + extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_rfft_fast_sR_q31_len8192; + + extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_inv_rfft_fast_sR_q31_len32; + extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_inv_rfft_fast_sR_q31_len64; + extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_inv_rfft_fast_sR_q31_len128; + extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_inv_rfft_fast_sR_q31_len256; + extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_inv_rfft_fast_sR_q31_len512; + extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_inv_rfft_fast_sR_q31_len1024; + extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_inv_rfft_fast_sR_q31_len2048; + extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_inv_rfft_fast_sR_q31_len4096; + extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_inv_rfft_fast_sR_q31_len8192; + + + extern csky_vdsp2_rfft_fast_instance_f32 csky_vdsp2_rfft_sR_f32_len32; + extern csky_vdsp2_rfft_fast_instance_f32 csky_vdsp2_rfft_sR_f32_len64; + extern csky_vdsp2_rfft_fast_instance_f32 csky_vdsp2_rfft_sR_f32_len128; + extern csky_vdsp2_rfft_fast_instance_f32 csky_vdsp2_rfft_sR_f32_len256; + extern csky_vdsp2_rfft_fast_instance_f32 csky_vdsp2_rfft_sR_f32_len512; + extern csky_vdsp2_rfft_fast_instance_f32 csky_vdsp2_rfft_sR_f32_len1024; + extern csky_vdsp2_rfft_fast_instance_f32 csky_vdsp2_rfft_sR_f32_len2048; + extern csky_vdsp2_rfft_fast_instance_f32 csky_vdsp2_rfft_sR_f32_len4096; + extern csky_vdsp2_rfft_fast_instance_f32 csky_vdsp2_rfft_sR_f32_len8192; + + extern csky_vdsp2_dct4_instance_q15 csky_vdsp2_dct4_sR_q15_len128; + extern csky_vdsp2_dct4_instance_q15 csky_vdsp2_dct4_sR_q15_len512; + extern csky_vdsp2_dct4_instance_q15 csky_vdsp2_dct4_sR_q15_len2048; + extern csky_vdsp2_dct4_instance_q15 csky_vdsp2_dct4_sR_q15_len8192; + + extern csky_vdsp2_dct4_instance_q31 csky_vdsp2_dct4_sR_q31_len128; + extern csky_vdsp2_dct4_instance_q31 csky_vdsp2_dct4_sR_q31_len512; + extern csky_vdsp2_dct4_instance_q31 csky_vdsp2_dct4_sR_q31_len2048; + extern csky_vdsp2_dct4_instance_q31 csky_vdsp2_dct4_sR_q31_len8192; + + extern csky_vdsp2_dct4_fast_instance_q15 csky_vdsp2_dct4_fast_sR_q15_len128; + extern csky_vdsp2_dct4_fast_instance_q15 csky_vdsp2_dct4_fast_sR_q15_len512; + extern csky_vdsp2_dct4_fast_instance_q15 csky_vdsp2_dct4_fast_sR_q15_len2048; + extern csky_vdsp2_dct4_fast_instance_q15 csky_vdsp2_dct4_fast_sR_q15_len8192; + + extern csky_vdsp2_dct4_fast_instance_q31 csky_vdsp2_dct4_fast_sR_q31_len128; + extern csky_vdsp2_dct4_fast_instance_q31 csky_vdsp2_dct4_fast_sR_q31_len512; + extern csky_vdsp2_dct4_fast_instance_q31 csky_vdsp2_dct4_fast_sR_q31_len2048; + extern csky_vdsp2_dct4_fast_instance_q31 csky_vdsp2_dct4_fast_sR_q31_len8192; + + extern csky_vdsp2_dct4_instance_f32 csky_vdsp2_dct4_sR_f32_len128; + extern csky_vdsp2_dct4_instance_f32 csky_vdsp2_dct4_sR_f32_len512; + extern csky_vdsp2_dct4_instance_f32 csky_vdsp2_dct4_sR_f32_len2048; + extern csky_vdsp2_dct4_instance_f32 csky_vdsp2_dct4_sR_f32_len8192; +#endif diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_vdsp2_math.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_vdsp2_math.h new file mode 100644 index 00000000..55ced0f4 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_vdsp2_math.h @@ -0,0 +1,2378 @@ +/* + * Copyright (C) 2016-2019 C-SKY Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file csky_vdsp2_math.h + * @brief Public header file for CSI DSP Library. + * @version V1.0 + * @date 20. Dec 2016 + ******************************************************************************/ + +#ifndef _CSKY_VDSP2_MATH_H +#define _CSKY_VDSP2_MATH_H + +#include +#include + +#ifdef CSKY_VDSP2_MATH_DSP +#include "csi_core.h" +#endif + +#ifdef __cplusplus +extern "C" +{ +#endif + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + CSKY_VDSP2_MATH_SUCCESS = 0, /**< No error */ + CSKY_VDSP2_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + CSKY_VDSP2_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + CSKY_VDSP2_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + CSKY_VDSP2_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + CSKY_VDSP2_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + CSKY_VDSP2_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } csky_vdsp2_status; + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } csky_vdsp2_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } csky_vdsp2_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } csky_vdsp2_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } csky_vdsp2_fir_instance_f32; + + void csky_vdsp2_fir_q7( + const csky_vdsp2_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_fir_init_q7( + csky_vdsp2_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + void csky_vdsp2_fir_q15( + const csky_vdsp2_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_fir_fast_q15( + const csky_vdsp2_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + csky_vdsp2_status csky_vdsp2_fir_init_q15( + csky_vdsp2_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + void csky_vdsp2_fir_q31( + const csky_vdsp2_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_fir_fast_q31( + const csky_vdsp2_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_fir_init_q31( + csky_vdsp2_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + void csky_vdsp2_fir_f32( + const csky_vdsp2_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_fir_init_f32( + csky_vdsp2_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } csky_vdsp2_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } csky_vdsp2_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } csky_vdsp2_biquad_casd_df1_inst_f32; + + void csky_vdsp2_biquad_cascade_df1_q15( + const csky_vdsp2_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_biquad_cascade_df1_init_q15( + csky_vdsp2_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + void csky_vdsp2_biquad_cascade_df1_fast_q15( + const csky_vdsp2_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_biquad_cascade_df1_q31( + const csky_vdsp2_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_biquad_cascade_df1_fast_q31( + const csky_vdsp2_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_biquad_cascade_df1_init_q31( + csky_vdsp2_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + void csky_vdsp2_biquad_cascade_df1_f32( + const csky_vdsp2_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_biquad_cascade_df1_init_f32( + csky_vdsp2_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } csky_vdsp2_matrix_instance_f32; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } csky_vdsp2_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } csky_vdsp2_matrix_instance_q31; + + csky_vdsp2_status csky_vdsp2_mat_add_f32( + const csky_vdsp2_matrix_instance_f32 * pSrcA, + const csky_vdsp2_matrix_instance_f32 * pSrcB, + csky_vdsp2_matrix_instance_f32 * pDst); + + csky_vdsp2_status csky_vdsp2_mat_add_q15( + const csky_vdsp2_matrix_instance_q15 * pSrcA, + const csky_vdsp2_matrix_instance_q15 * pSrcB, + csky_vdsp2_matrix_instance_q15 * pDst); + + csky_vdsp2_status csky_vdsp2_mat_add_q31( + const csky_vdsp2_matrix_instance_q31 * pSrcA, + const csky_vdsp2_matrix_instance_q31 * pSrcB, + csky_vdsp2_matrix_instance_q31 * pDst); + + csky_vdsp2_status csky_vdsp2_mat_cmplx_mult_f32( + const csky_vdsp2_matrix_instance_f32 * pSrcA, + const csky_vdsp2_matrix_instance_f32 * pSrcB, + csky_vdsp2_matrix_instance_f32 * pDst); + + csky_vdsp2_status csky_vdsp2_mat_cmplx_mult_q15( + const csky_vdsp2_matrix_instance_q15 * pSrcA, + const csky_vdsp2_matrix_instance_q15 * pSrcB, + csky_vdsp2_matrix_instance_q15 * pDst); + + csky_vdsp2_status csky_vdsp2_mat_cmplx_mult_q31( + const csky_vdsp2_matrix_instance_q31 * pSrcA, + const csky_vdsp2_matrix_instance_q31 * pSrcB, + csky_vdsp2_matrix_instance_q31 * pDst); + + csky_vdsp2_status csky_vdsp2_mat_trans_f32( + const csky_vdsp2_matrix_instance_f32 * pSrc, + csky_vdsp2_matrix_instance_f32 * pDst); + + csky_vdsp2_status csky_vdsp2_mat_trans_q15( + const csky_vdsp2_matrix_instance_q15 * pSrc, + csky_vdsp2_matrix_instance_q15 * pDst); + + csky_vdsp2_status csky_vdsp2_mat_trans_q31( + const csky_vdsp2_matrix_instance_q31 * pSrc, + csky_vdsp2_matrix_instance_q31 * pDst); + + csky_vdsp2_status csky_vdsp2_mat_mult_f32( + const csky_vdsp2_matrix_instance_f32 * pSrcA, + const csky_vdsp2_matrix_instance_f32 * pSrcB, + csky_vdsp2_matrix_instance_f32 * pDst); + + csky_vdsp2_status csky_vdsp2_mat_mult_trans_f32( + const csky_vdsp2_matrix_instance_f32 * pSrcA, + const csky_vdsp2_matrix_instance_f32 * pSrcB, + csky_vdsp2_matrix_instance_f32 * pDst); + + csky_vdsp2_status csky_vdsp2_mat_mult_q15( + const csky_vdsp2_matrix_instance_q15 * pSrcA, + const csky_vdsp2_matrix_instance_q15 * pSrcB, + csky_vdsp2_matrix_instance_q15 * pDst); + + csky_vdsp2_status csky_vdsp2_mat_mult_trans_q15( + const csky_vdsp2_matrix_instance_q15 * pSrcA, + const csky_vdsp2_matrix_instance_q15 * pSrcB, + csky_vdsp2_matrix_instance_q15 * pDst); + + csky_vdsp2_status csky_vdsp2_mat_mult_q31( + const csky_vdsp2_matrix_instance_q31 * pSrcA, + const csky_vdsp2_matrix_instance_q31 * pSrcB, + csky_vdsp2_matrix_instance_q31 * pDst); + + csky_vdsp2_status csky_vdsp2_mat_mult_trans_q31( + const csky_vdsp2_matrix_instance_q31 * pSrcA, + const csky_vdsp2_matrix_instance_q31 * pSrcB, + csky_vdsp2_matrix_instance_q31 * pDst); + + csky_vdsp2_status csky_vdsp2_mat_sub_f32( + const csky_vdsp2_matrix_instance_f32 * pSrcA, + const csky_vdsp2_matrix_instance_f32 * pSrcB, + csky_vdsp2_matrix_instance_f32 * pDst); + + csky_vdsp2_status csky_vdsp2_mat_sub_q15( + const csky_vdsp2_matrix_instance_q15 * pSrcA, + const csky_vdsp2_matrix_instance_q15 * pSrcB, + csky_vdsp2_matrix_instance_q15 * pDst); + + csky_vdsp2_status csky_vdsp2_mat_sub_q31( + const csky_vdsp2_matrix_instance_q31 * pSrcA, + const csky_vdsp2_matrix_instance_q31 * pSrcB, + csky_vdsp2_matrix_instance_q31 * pDst); + + csky_vdsp2_status csky_vdsp2_mat_scale_f32( + const csky_vdsp2_matrix_instance_f32 * pSrc, + float32_t scale, + csky_vdsp2_matrix_instance_f32 * pDst); + + csky_vdsp2_status csky_vdsp2_mat_scale_q15( + const csky_vdsp2_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + csky_vdsp2_matrix_instance_q15 * pDst); + + csky_vdsp2_status csky_vdsp2_mat_scale_q31( + const csky_vdsp2_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + csky_vdsp2_matrix_instance_q31 * pDst); + + void csky_vdsp2_mat_init_q31( + csky_vdsp2_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + void csky_vdsp2_mat_init_q15( + csky_vdsp2_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + void csky_vdsp2_mat_init_f32( + csky_vdsp2_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + void csky_vdsp2_mult_q15xq31_sht( + q15_t * pSrcA, + q31_t * pSrcB, + uint32_t shiftValue, + uint32_t blockSize); + + void csky_vdsp2_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_mult_rnd_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } csky_vdsp2_cfft_radix2_instance_q15; + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } csky_vdsp2_cfft_radix4_instance_q15; + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } csky_vdsp2_cfft_radix2_instance_q31; + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } csky_vdsp2_cfft_radix4_instance_q31; + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } csky_vdsp2_cfft_radix2_instance_f32; + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } csky_vdsp2_cfft_radix4_instance_f32; + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } csky_vdsp2_cfft_instance_q15; + +void csky_vdsp2_cfft_q15( + const csky_vdsp2_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +void csky_vdsp2_cfft_fast_q15( + const csky_vdsp2_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } csky_vdsp2_cfft_instance_q31; + +void csky_vdsp2_cfft_q31( + const csky_vdsp2_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +void csky_vdsp2_cfft_fast_q31( + const csky_vdsp2_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } csky_vdsp2_cfft_instance_f32; + + void csky_vdsp2_cfft_f32( + const csky_vdsp2_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const csky_vdsp2_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } csky_vdsp2_rfft_instance_q15; + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + q15_t *pTwiddleAReal; /**< points to the A real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the B real twiddle factor table. */ + const csky_vdsp2_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } csky_vdsp2_rfft_fast_instance_q15; + + csky_vdsp2_status csky_vdsp2_rfft_init_q15( + csky_vdsp2_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void csky_vdsp2_rfft_q15( + const csky_vdsp2_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + void csky_vdsp2_rfft_fast_q15( + const csky_vdsp2_rfft_fast_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const csky_vdsp2_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } csky_vdsp2_rfft_instance_q31; + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + q31_t *pTwiddleAReal; /**< points to the A real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the B real twiddle factor table. */ + const csky_vdsp2_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } csky_vdsp2_rfft_fast_instance_q31; + + csky_vdsp2_status csky_vdsp2_rfft_init_q31( + csky_vdsp2_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void csky_vdsp2_rfft_q31( + const csky_vdsp2_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + void csky_vdsp2_rfft_fast_q31( + const csky_vdsp2_rfft_fast_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + csky_vdsp2_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } csky_vdsp2_rfft_instance_f32; + + csky_vdsp2_status csky_vdsp2_rfft_init_f32( + csky_vdsp2_rfft_instance_f32 * S, + csky_vdsp2_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void csky_vdsp2_cfft_radix4_f32( + const csky_vdsp2_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag, + float32_t onebyfftLen); + + void csky_vdsp2_cfft_fast_radix4_f32( + const csky_vdsp2_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag, + float32_t onebyfftLen); + + void csky_vdsp2_cfft_radix2_f32( + const csky_vdsp2_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag, + float32_t onebyfftLen); + + void csky_vdsp2_rfft_f32( + const csky_vdsp2_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + csky_vdsp2_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } csky_vdsp2_rfft_fast_instance_f32 ; + +csky_vdsp2_status csky_vdsp2_rfft_fast_init_f32 ( + csky_vdsp2_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void csky_vdsp2_rfft_fast_f32( + csky_vdsp2_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + csky_vdsp2_rfft_fast_instance_f32 *pRfft; /**< points to the real FFT fast instance. */ + csky_vdsp2_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } csky_vdsp2_dct4_instance_f32; + + csky_vdsp2_status csky_vdsp2_dct4_init_f32( + csky_vdsp2_dct4_instance_f32 * S, + csky_vdsp2_rfft_fast_instance_f32 * S_RFFT, + csky_vdsp2_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + void csky_vdsp2_dct4_f32( + const csky_vdsp2_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + csky_vdsp2_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + csky_vdsp2_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } csky_vdsp2_dct4_instance_q31; + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + csky_vdsp2_rfft_fast_instance_q31 *pRfft; /**< points to the real FFT instance. */ + csky_vdsp2_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } csky_vdsp2_dct4_fast_instance_q31; + + csky_vdsp2_status csky_vdsp2_dct4_init_q31( + csky_vdsp2_dct4_instance_q31 * S, + csky_vdsp2_rfft_instance_q31 * S_RFFT, + csky_vdsp2_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + void csky_vdsp2_dct4_q31( + const csky_vdsp2_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + void csky_vdsp2_dct4_fast_q31( + const csky_vdsp2_dct4_fast_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + csky_vdsp2_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + csky_vdsp2_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } csky_vdsp2_dct4_instance_q15; + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + csky_vdsp2_rfft_fast_instance_q15 *pRfft; /**< points to the real FFT instance. */ + csky_vdsp2_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } csky_vdsp2_dct4_fast_instance_q15; + + csky_vdsp2_status csky_vdsp2_dct4_init_q15( + csky_vdsp2_dct4_instance_q15 * S, + csky_vdsp2_rfft_instance_q15 * S_RFFT, + csky_vdsp2_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + void csky_vdsp2_dct4_q15( + const csky_vdsp2_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + void csky_vdsp2_dct4_fast_q15( + const csky_vdsp2_dct4_fast_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + void csky_vdsp2_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_sum_q15( + q15_t * pSrcA, + q63_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_abs_max_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_abs_max_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + void csky_vdsp2_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + void csky_vdsp2_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + void csky_vdsp2_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + void csky_vdsp2_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + void csky_vdsp2_dot_prod_u64xu8( + uint8_t * pSrcA, + uint64_t * pSrcB, + uint32_t blockSize, + uint64_t * result); + + void csky_vdsp2_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + void csky_vdsp2_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + void csky_vdsp2_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + void csky_vdsp2_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + void csky_vdsp2_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + void csky_vdsp2_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + void csky_vdsp2_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + void csky_vdsp2_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + void csky_vdsp2_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + csky_vdsp2_status csky_vdsp2_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + csky_vdsp2_status csky_vdsp2_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + csky_vdsp2_status csky_vdsp2_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + csky_vdsp2_status csky_vdsp2_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + csky_vdsp2_status csky_vdsp2_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + csky_vdsp2_status csky_vdsp2_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + csky_vdsp2_status csky_vdsp2_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + csky_vdsp2_status csky_vdsp2_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + csky_vdsp2_status csky_vdsp2_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } csky_vdsp2_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } csky_vdsp2_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } csky_vdsp2_fir_decimate_instance_f32; + + void csky_vdsp2_fir_decimate_f32( + const csky_vdsp2_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + csky_vdsp2_status csky_vdsp2_fir_decimate_init_f32( + csky_vdsp2_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + void csky_vdsp2_fir_decimate_q15( + const csky_vdsp2_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_fir_decimate_fast_q15( + const csky_vdsp2_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + csky_vdsp2_status csky_vdsp2_fir_decimate_init_q15( + csky_vdsp2_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + void csky_vdsp2_fir_decimate_q31( + const csky_vdsp2_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_fir_decimate_fast_q31( + csky_vdsp2_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + csky_vdsp2_status csky_vdsp2_fir_decimate_init_q31( + csky_vdsp2_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } csky_vdsp2_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } csky_vdsp2_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } csky_vdsp2_fir_interpolate_instance_f32; + + void csky_vdsp2_fir_interpolate_q15( + const csky_vdsp2_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + csky_vdsp2_status csky_vdsp2_fir_interpolate_init_q15( + csky_vdsp2_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + void csky_vdsp2_fir_interpolate_q31( + const csky_vdsp2_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + csky_vdsp2_status csky_vdsp2_fir_interpolate_init_q31( + csky_vdsp2_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + void csky_vdsp2_fir_interpolate_f32( + const csky_vdsp2_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + csky_vdsp2_status csky_vdsp2_fir_interpolate_init_f32( + csky_vdsp2_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } csky_vdsp2_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } csky_vdsp2_biquad_cascade_stereo_df2T_instance_f32; + + void csky_vdsp2_biquad_cascade_df2T_f32( + const csky_vdsp2_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_biquad_cascade_stereo_df2T_f32( + const csky_vdsp2_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_biquad_cascade_df2T_init_f32( + csky_vdsp2_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + void csky_vdsp2_biquad_cascade_stereo_df2T_init_f32( + csky_vdsp2_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } csky_vdsp2_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } csky_vdsp2_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } csky_vdsp2_fir_lattice_instance_f32; + + void csky_vdsp2_fir_lattice_init_q15( + csky_vdsp2_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + void csky_vdsp2_fir_lattice_q15( + const csky_vdsp2_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_fir_lattice_init_q31( + csky_vdsp2_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + void csky_vdsp2_fir_lattice_q31( + const csky_vdsp2_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_fir_lattice_init_f32( + csky_vdsp2_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + void csky_vdsp2_fir_lattice_f32( + const csky_vdsp2_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } csky_vdsp2_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } csky_vdsp2_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } csky_vdsp2_iir_lattice_instance_f32; + + void csky_vdsp2_iir_lattice_f32( + const csky_vdsp2_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_iir_lattice_init_f32( + csky_vdsp2_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + void csky_vdsp2_iir_lattice_q31( + const csky_vdsp2_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_iir_lattice_init_q31( + csky_vdsp2_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + void csky_vdsp2_iir_lattice_q15( + const csky_vdsp2_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_iir_lattice_init_q15( + csky_vdsp2_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } csky_vdsp2_lms_instance_f32; + + void csky_vdsp2_lms_f32( + const csky_vdsp2_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + void csky_vdsp2_lms_init_f32( + csky_vdsp2_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } csky_vdsp2_lms_instance_q15; + + void csky_vdsp2_lms_init_q15( + csky_vdsp2_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + void csky_vdsp2_lms_q15( + const csky_vdsp2_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } csky_vdsp2_lms_instance_q31; + + void csky_vdsp2_lms_q31( + const csky_vdsp2_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + void csky_vdsp2_lms_init_q31( + csky_vdsp2_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } csky_vdsp2_lms_norm_instance_f32; + + void csky_vdsp2_lms_norm_f32( + csky_vdsp2_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + void csky_vdsp2_lms_norm_init_f32( + csky_vdsp2_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } csky_vdsp2_lms_norm_instance_q31; + + void csky_vdsp2_lms_norm_q31( + csky_vdsp2_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + void csky_vdsp2_lms_norm_init_q31( + csky_vdsp2_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } csky_vdsp2_lms_norm_instance_q15; + + void csky_vdsp2_lms_norm_q15( + csky_vdsp2_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + void csky_vdsp2_lms_norm_init_q15( + csky_vdsp2_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + void csky_vdsp2_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + void csky_vdsp2_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + void csky_vdsp2_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + void csky_vdsp2_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + void csky_vdsp2_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + void csky_vdsp2_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + void csky_vdsp2_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + void csky_vdsp2_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + void csky_vdsp2_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } csky_vdsp2_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } csky_vdsp2_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } csky_vdsp2_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } csky_vdsp2_fir_sparse_instance_q7; + + void csky_vdsp2_fir_sparse_f32( + csky_vdsp2_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + void csky_vdsp2_fir_sparse_init_f32( + csky_vdsp2_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + void csky_vdsp2_fir_sparse_q31( + csky_vdsp2_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + void csky_vdsp2_fir_sparse_init_q31( + csky_vdsp2_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + void csky_vdsp2_fir_sparse_q15( + csky_vdsp2_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + void csky_vdsp2_fir_sparse_init_q15( + csky_vdsp2_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + void csky_vdsp2_fir_sparse_q7( + csky_vdsp2_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + void csky_vdsp2_fir_sparse_init_q7( + csky_vdsp2_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + void csky_vdsp2_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + void csky_vdsp2_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + void csky_vdsp2_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + void csky_vdsp2_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + void csky_vdsp2_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + void csky_vdsp2_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + void csky_vdsp2_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + void csky_vdsp2_cmplx_mag_squared_q31_basic( + q31_t * pSrc, + q63_t * pDst, + uint32_t numSamples); + + void csky_vdsp2_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + void csky_vdsp2_vsqrt_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + void csky_vdsp2_vsqrt_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + void csky_vdsp2_vsqrt_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + void csky_vdsp2_vsqrt_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t numSamples); + + void csky_vdsp2_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + csky_vdsp2_status csky_vdsp2_sqrt_f32( + float32_t in, + float32_t * pOut); + + csky_vdsp2_status csky_vdsp2_sqrt_q31( + q31_t in, + q31_t * pOut); + + csky_vdsp2_status csky_vdsp2_sqrt_q15( + q15_t in, + q15_t * pOut); + + void csky_vdsp2_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + void csky_vdsp2_power_int32( + int32_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + void csky_vdsp2_power_int32( + int32_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + void csky_vdsp2_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + void csky_vdsp2_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + void csky_vdsp2_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + void csky_vdsp2_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + void csky_vdsp2_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + void csky_vdsp2_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + void csky_vdsp2_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + void csky_vdsp2_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + void csky_vdsp2_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + void csky_vdsp2_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + void csky_vdsp2_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + void csky_vdsp2_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + void csky_vdsp2_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + void csky_vdsp2_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + void csky_vdsp2_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + void csky_vdsp2_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + void csky_vdsp2_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + void csky_vdsp2_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + void csky_vdsp2_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + void csky_vdsp2_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + void csky_vdsp2_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + void csky_vdsp2_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + void csky_vdsp2_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + void csky_vdsp2_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + void csky_vdsp2_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + void csky_vdsp2_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + void csky_vdsp2_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + void csky_vdsp2_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + void csky_vdsp2_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + void csky_vdsp2_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + void csky_vdsp2_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + void csky_vdsp2_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + void csky_vdsp2_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + void csky_vdsp2_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + void csky_vdsp2_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + void csky_vdsp2_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + void csky_vdsp2_cmplx_mult_cmplx_re_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + void csky_vdsp2_cmplx_mult_cmplx_re_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + void csky_vdsp2_cmplx_mult_cmplx_re_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + void csky_vdsp2_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_q31_to_q7_rs( + q31_t * pSrc, + q7_t * pDst, + uint32_t shiftValue, + uint32_t blockSize); + + void csky_vdsp2_q63_to_q31_rs( + q63_t * pSrc, + q31_t * pDst, + uint32_t shiftValue, + uint32_t blockSize); + + void csky_vdsp2_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + void csky_vdsp2_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + +#ifdef __cplusplus +} +#endif +#endif /* _CSKY_VDSP2_MATH_H */ + +/** + * + * End of file. + */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/syslog.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/syslog.h new file mode 100755 index 00000000..063649c8 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/syslog.h @@ -0,0 +1,121 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file syslog.h + * @brief Defines syslog APIs and usage + * @version V1.1 + * @date 14. February 2019 + * @usage Add 3 lines codes below at head of source code file + * // 0: Err; 1: Err&Warn; 2: Err&Warn&Info; 3: Err&Warn&Info&Debug + * #define LOG_LEVEL 3 + * #include + ******************************************************************************/ +#include + +#ifndef _SYSLOG_H_ +#define _SYSLOG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef LOG_LEVEL +#if (LOG_LEVEL >= 3) && \ + (defined CONFIG_SYSLOG_LEVEL_DEBUG) +#define LOG_ENABLE_D +#endif + +#if (LOG_LEVEL >= 2) && \ + (defined CONFIG_SYSLOG_LEVEL_DEBUG || \ + defined CONFIG_SYSLOG_LEVEL_INFO) +#define LOG_ENABLE_I +#endif + +#if (LOG_LEVEL >= 1) && \ + (defined CONFIG_SYSLOG_LEVEL_DEBUG || \ + defined CONFIG_SYSLOG_LEVEL_INFO || \ + defined CONFIG_SYSLOG_LEVEL_WARN) +#define LOG_ENABLE_W +#endif + +#if (LOG_LEVEL >= 0) && \ + (defined CONFIG_SYSLOG_LEVEL_DEBUG || \ + defined CONFIG_SYSLOG_LEVEL_INFO || \ + defined CONFIG_SYSLOG_LEVEL_WARN || \ + defined CONFIG_SYSLOG_LEVEL_ERROR) +#define LOG_ENABLE_E +#endif +#endif /* #ifdef LOG_LEVEL */ + +/* [LogLevel:FileName:Function:Line] */ +extern const char *PFORMAT_D; +extern const char *PFORMAT_I; +extern const char *PFORMAT_W; +extern const char *PFORMAT_E; + +#define LOG_E_BASE_ARGS __FUNCTION__, __LINE__ +#define LOG_W_BASE_ARGS __FUNCTION__, __LINE__ +#define LOG_I_BASE_ARGS __FUNCTION__, __LINE__ +#define LOG_D_BASE_ARGS __FUNCTION__, __LINE__ + +/* Log in freely format without prefix */ +#define LOG_F(fmt, args...) printf(fmt,##args) + +/* Log debug */ +#ifdef LOG_ENABLE_D +#define LOG_D(fmt, args...) \ + do {printf(PFORMAT_D,LOG_D_BASE_ARGS); printf(fmt,##args);} while(0) +#else +#define LOG_D(fmt, args...) +#endif + +/* Log information */ +#ifdef LOG_ENABLE_I +#define LOG_I(fmt, args...) \ + do {printf(PFORMAT_I ,LOG_I_BASE_ARGS); printf(fmt,##args);} while(0) +#else +#define LOG_I(fmt, args...) +#endif + +/* Log warning */ +#ifdef LOG_ENABLE_W +#define LOG_W(fmt, args...) \ + do {printf(PFORMAT_W,LOG_W_BASE_ARGS); printf(fmt,##args);} while(0) +#else +#define LOG_W(fmt, args...) +#endif + +/* Log error */ +#ifdef LOG_ENABLE_E +#define LOG_E(fmt, args...) \ + do {printf(PFORMAT_E,LOG_E_BASE_ARGS); printf(fmt,##args);} while(0) +#else +#define LOG_E(fmt, args...) +#endif + +#define ENTER() LOG_D("Enter\n") +#define EXIT_VOID() do { LOG_D("Exit\n"); return;} while(0) +#define EXIT_INT(val) do { LOG_D("Exit, return val=%d\n", (int)val); return val;} while(0) +#define EXIT_PTR(ptr) do { LOG_D("Exit, return ptr=%p\n", (void*)ptr); return ptr;} while(0) + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSLOG_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/src/csi_misc.c b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/src/csi_misc.c new file mode 100644 index 00000000..f9fd6ee2 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/src/csi_misc.c @@ -0,0 +1,25 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include + +/* used by csi_mmu_set_mode(If there are multiple mmu modes) */ +int g_mmu_mode = 0; diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/src/csi_ringbuf.c b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/src/csi_ringbuf.c new file mode 100644 index 00000000..364b682c --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/src/csi_ringbuf.c @@ -0,0 +1,184 @@ +#include +#include +#include +#include +#include "drv/ringbuf.h" + +#define min(a, b) (((a) < (b)) ? (a) : (b)) + +/** + * \brief Removes the entire FIFO contents. + * \param [in] fifo: The fifo to be emptied. + * \return None. + */ +void csi_ringbuf_reset(csi_ringbuf_t *fifo) +{ + uint32_t stat = csi_irq_save(); + fifo->write = fifo->read = 0; + fifo->data_len = 0; + csi_irq_restore(stat); +} + +/** + * \brief Returns the size of the FIFO in bytes. + * \param [in] fifo: The fifo to be used. + * \return The size of the FIFO. + */ +static inline uint32_t csi_ringbuf_size(csi_ringbuf_t *fifo) +{ + return fifo->size; +} + +/** + * \brief Returns the number of used bytes in the FIFO. + * \param [in] fifo: The fifo to be used. + * \return The number of used bytes. + */ +uint32_t csi_ringbuf_len(csi_ringbuf_t *fifo) +{ + return fifo->data_len; +} + +/** + * \brief Returns the number of bytes available in the FIFO. + * \param [in] fifo: The fifo to be used. + * \return The number of bytes available. + */ +uint32_t csi_ringbuf_avail(csi_ringbuf_t *fifo) +{ + return csi_ringbuf_size(fifo) - csi_ringbuf_len(fifo); +} + +/** + * \brief Is the FIFO empty? + * \param [in] fifo: The fifo to be used. + * \retval true: Yes. + * \retval false: No. + */ +bool csi_ringbuf_is_empty(csi_ringbuf_t *fifo) +{ + return csi_ringbuf_len(fifo) == 0; +} + +/** + * \brief Is the FIFO full? + * \param [in] fifo: The fifo to be used. + * \retval true: Yes. + * \retval false: No. + */ +bool csi_ringbuf_is_full(csi_ringbuf_t *fifo) +{ + return csi_ringbuf_avail(fifo) == 0; +} + +/** + * \brief Puts some data into the FIFO. + * \param [in] fifo: The fifo to be used. + * \param [in] in: The data to be added. + * \param [in] len: The length of the data to be added. + * \return The number of bytes copied. + * \note This function copies at most @len bytes from the @in into + * the FIFO depending on the free space, and returns the number + * of bytes copied. + */ +uint32_t csi_ringbuf_in(csi_ringbuf_t *fifo, const void *datptr, uint32_t len) +{ + uint32_t writelen = 0, tmplen = 0; + + if(csi_ringbuf_is_full(fifo)) + return 0; + + tmplen = fifo->size - fifo->data_len; + writelen = tmplen > len ? len : tmplen; + + if(fifo->write < fifo->read) { + memcpy((void*)&fifo->buffer[fifo->write], (void*)datptr, writelen); + } else { + tmplen = fifo->size - fifo->write; + if(writelen <= tmplen) { + memcpy((void*)&fifo->buffer[fifo->write], (void*)datptr, writelen); + } else { + memcpy((void*)&fifo->buffer[fifo->write], (void*)datptr, tmplen); + memcpy((void*)fifo->buffer, (uint8_t*)datptr + tmplen, writelen - tmplen); + } + } + + uint32_t stat = csi_irq_save(); + fifo->write = (fifo->write + writelen) % fifo->size; + fifo->data_len += writelen; + csi_irq_restore(stat); + + return writelen; +} + +/** + * \brief Gets some data from the FIFO. + * \param [in] fifo: The fifo to be used. + * \param [in] out: Where the data must be copied. + * \param [in] len: The size of the destination buffer. + * \return The number of copied bytes. + * \note This function copies at most @len bytes from the FIFO into + * the @out and returns the number of copied bytes. + */ +uint32_t csi_ringbuf_out(csi_ringbuf_t *fifo, void *outbuf, uint32_t len) +{ + uint32_t readlen = 0, tmplen = 0; + if(csi_ringbuf_is_empty(fifo)) + return 0; + + uint32_t data_len = fifo->data_len; + readlen = len > data_len ? data_len : len; + tmplen = fifo->size - fifo->read; + + if(NULL != outbuf) { + if(readlen <= tmplen) { + memcpy((void*)outbuf, (void*)&fifo->buffer[fifo->read], readlen); + } else { + memcpy((void*)outbuf,(void*)&fifo->buffer[fifo->read], tmplen); + memcpy((uint8_t*)outbuf + tmplen,(void*)fifo->buffer,readlen - tmplen); + } + } + + uint32_t stat = csi_irq_save(); + fifo->read = (fifo->read + readlen) % fifo->size; + fifo->data_len -= readlen; + csi_irq_restore(stat); + + return readlen; +} + +/** + * \brief Move FIFO buffer to another FIFO. + * \param [in] fifo_in: The fifo to be used. + * \param [in] fifo_out: The fifo to be used. + * \return The number of copied bytes. + * \note This function copies at most @len bytes from the FIFO into + * the @out and returns the number of copied bytes. + */ +uint32_t csi_ringbuf_move(csi_ringbuf_t *fifo_in, csi_ringbuf_t *fifo_out) +{ + uint32_t readlen = 0, tmplen_out = 0; + if(csi_ringbuf_is_empty(fifo_out)) + return 0; + + uint32_t len = csi_ringbuf_avail(fifo_in); + + uint32_t data_len = fifo_out->data_len; + readlen = len > data_len ? data_len : len; + tmplen_out = fifo_out->size - fifo_out->read; + + if(readlen <= tmplen_out) { + csi_ringbuf_in(fifo_in, (void*)&fifo_out->buffer[fifo_out->read], readlen); + } else { + csi_ringbuf_in(fifo_in, (void*)&fifo_out->buffer[fifo_out->read], tmplen_out); + csi_ringbuf_in(fifo_in, (void*)fifo_out->buffer, readlen - tmplen_out); + } + + uint32_t stat = csi_irq_save(); + fifo_out->read = (fifo_out->read + readlen) % fifo_out->size; + fifo_out->data_len -= readlen; + csi_irq_restore(stat); + + return readlen; +} + diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/compilers/gcc/sys/ioctl.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/compilers/gcc/sys/ioctl.h new file mode 100644 index 00000000..8ab7ef9a --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/compilers/gcc/sys/ioctl.h @@ -0,0 +1,46 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_SYS_IOCTL_H +#define __INCLUDE_SYS_IOCTL_H +#ifdef __cplusplus +extern "C" { +#endif + + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +int ioctl(int fd, int req, ...); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __INCLUDE_SYS_IOCTL_H */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/compilers/gcc/sys/termios.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/compilers/gcc/sys/termios.h new file mode 100644 index 00000000..137d937c --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/compilers/gcc/sys/termios.h @@ -0,0 +1,291 @@ +/* + * Copyright (C) 2020-2021 Alibaba Group Holding Limited + * A modified version of termios in Haiku OS + * Distributed under the terms of the MIT License. + */ + +#ifndef _SYS_TERMIOS_H_ +#define _SYS_TERMIOS_H_ + +#include + +typedef unsigned long tcflag_t; +typedef unsigned long speed_t; +typedef unsigned char cc_t; + +#define NCCS 12 /* number of control characters */ + +struct termios { + tcflag_t c_iflag; /* input modes */ + tcflag_t c_oflag; /* output modes */ + tcflag_t c_cflag; /* control modes */ + tcflag_t c_lflag; /* local modes */ + cc_t c_cc[NCCS]; /* control characters */ +}; + +/* control characters */ +#define VINTR 0 +#define VQUIT 1 +#define VERASE 2 +#define VKILL 3 +#define VEOF 4 +#define VEOL 5 +#define VMIN 6 +#define VTIME 7 +#define VEOL2 8 +#define VSTART 9 +#define VSTOP 10 +#define VSUSP 11 + +/* c_iflag - input control modes */ +#define IGNBRK 0x0001 /* ignore break condition */ +#define BRKINT 0x0002 /* break sends interrupt */ +#define IGNPAR 0x0004 /* ignore characters with parity errors */ +#define PARMRK 0x0008 /* mark parity errors */ +#define INPCK 0x0010 /* enable input parity checking */ +#define ISTRIP 0x0020 /* strip high bit from characters */ +#define INLCR 0x0040 /* maps newline to CR on input */ +#define IGNCR 0x0080 /* ignore carriage returns */ +#define ICRNL 0x0100 /* map CR to newline on input */ +#define IUCLC 0x0200 /* map all upper case to lower */ +#define IXON 0x0400 /* enable input SW flow control */ +#define IXANY 0x0800 /* any character will restart input */ +#define IXOFF 0x1000 /* enable output SW flow control */ + +/* c_oflag - output control modes */ +#define OPOST 0x0001 /* enable postprocessing of output */ +#define OLCUC 0x0002 /* map lowercase to uppercase */ +#define ONLCR 0x0004 /* map NL to CR-NL on output */ +#define OCRNL 0x0008 /* map CR to NL on output */ +#define ONOCR 0x0010 /* no CR output when at column 0 */ +#define ONLRET 0x0020 /* newline performs CR function */ +#define OFILL 0x0040 /* use fill characters for delays */ +#define OFDEL 0x0080 /* Fills are DEL, otherwise NUL */ +#define NLDLY 0x0100 /* Newline delays: */ +#define NL0 0x0000 +#define NL1 0x0100 +#define CRDLY 0x0600 /* Carriage return delays: */ +#define CR0 0x0000 +#define CR1 0x0200 +#define CR2 0x0400 +#define CR3 0x0600 +#define TABDLY 0x1800 /* Tab delays: */ +#define TAB0 0x0000 +#define TAB1 0x0800 +#define TAB2 0x1000 +#define TAB3 0x1800 +#define BSDLY 0x2000 /* Backspace delays: */ +#define BS0 0x0000 +#define BS1 0x2000 +#define VTDLY 0x4000 /* Vertical tab delays: */ +#define VT0 0x0000 +#define VT1 0x4000 +#define FFDLY 0x8000 /* Form feed delays: */ +#define FF0 0x0000 +#define FF1 0x8000 + +/* c_cflag - control modes */ +#define CBAUD 0x1000F /* line speed definitions */ +#define B0 0x00 /* hang up */ +#define B50 0x01 /* 50 baud */ +#define B75 0x02 +#define B110 0x03 +#define B134 0x04 +#define B150 0x05 +#define B200 0x06 +#define B300 0x07 +#define B600 0x08 +#define B1200 0x09 +#define B1800 0x0A +#define B2400 0x0B +#define B4800 0x0C +#define B9600 0x0D +#define B19200 0x0E +#define B38400 0x0F +#define CBAUDEX 0x10000 +#define B57600 0x10001 +#define B115200 0x10002 +#define B230400 0x10003 +#define B460800 0x10004 +#define B500000 0x10005 +#define B576000 0x10006 +#define B921600 0x10007 +#define B1000000 0x10008 +#define B1152000 0x10009 +#define B1500000 0x1000A +#define B2000000 0x1000B +#define B2500000 0x1000C +#define B3000000 0x1000D +#define B3500000 0x1000E +#define B4000000 0x1000F +#define CSIZE 0x0030 /* character size */ +#define CS5 0x0000 +#define CS6 0x0010 +#define CS7 0x0020 +#define CS8 0x0030 +#define CSTOPB 0x0040 /* send 2 stop bits, not 1 */ +#define CREAD 0x0080 /* enable receiver */ +#define PARENB 0x0100 /* parity enable */ +#define PARODD 0x0200 /* odd parity, else even */ +#define HUPCL 0x0400 /* hangs up on last close */ +#define CLOCAL 0x0800 /* indicates local line */ +#define XLOBLK 0x1000 /* block layer output? */ +#define CTSFLOW 0x2000 /* enable CTS flow */ +#define RTSFLOW 0x4000 /* enable RTS flow */ +#define CRTSCTS (RTSFLOW | CTSFLOW) + +/* c_lflag - local modes */ +#define ISIG 0x0001 /* enable signals */ +#define ICANON 0x0002 /* Canonical input */ +#define XCASE 0x0004 /* Canonical u/l case */ +#define ECHO 0x0008 /* Enable echo */ +#define ECHOE 0x0010 /* Echo erase as bs-sp-bs */ +#define ECHOK 0x0020 /* Echo nl after kill */ +#define ECHONL 0x0040 /* Echo nl */ +#define NOFLSH 0x0080 /* Disable flush after int or quit */ +#define TOSTOP 0x0100 /* stop bg processes that write to tty */ +#define IEXTEN 0x0200 /* implementation defined extensions */ +#define ECHOCTL 0x0400 +#define ECHOPRT 0x0800 +#define ECHOKE 0x1000 +#define FLUSHO 0x2000 +#define PENDIN 0x4000 + +/* options to tcsetattr() */ +#define TCSANOW 0x01 /* make change immediate */ +#define TCSADRAIN 0x02 /* drain output, then change */ +#define TCSAFLUSH 0x04 /* drain output, flush input */ + +/* actions for tcflow() */ +#define TCOOFF 0x01 /* suspend output */ +#define TCOON 0x02 /* restart output */ +#define TCIOFF 0x04 /* transmit STOP character, intended to stop input data */ +#define TCION 0x08 /* transmit START character, intended to resume input data */ + +/* values for tcflush() */ +#define TCIFLUSH 0x01 /* flush pending input */ +#define TCOFLUSH 0x02 /* flush untransmitted output */ +#define TCIOFLUSH 0x03 /* flush both */ + +#define cfmakeraw(termios) \ + do { \ + (termios)->c_iflag &= ~(IGNBRK | BRKINT | PARMRK | ISTRIP | \ + INLCR | IGNCR | ICRNL | IXON); \ + (termios)->c_oflag &= ~OPOST; \ + (termios)->c_lflag &= ~(ECHO | ECHONL | ICANON | ISIG | IEXTEN); \ + (termios)->c_cflag &= ~(CSIZE | PARENB); \ + (termios)->c_cflag |= CS8; \ + } while (0) + +#define cfsetspeed(termios, speed) \ + ({ \ + tcflag_t flag; \ + int ret = 0; \ + switch (speed) { \ + case 0: \ + flag = B0; \ + break; \ + case 50: \ + flag = B50; \ + break; \ + case 75: \ + flag = B75; \ + break; \ + case 110: \ + flag = B110; \ + break; \ + case 134: \ + flag = B134; \ + break; \ + case 150: \ + flag = B150; \ + break; \ + case 200: \ + flag = B200; \ + break; \ + case 300: \ + flag = B300; \ + break; \ + case 600: \ + flag = B600; \ + break; \ + case 1200: \ + flag = B1200; \ + break; \ + case 1800: \ + flag = B1800; \ + break; \ + case 2400: \ + flag = B2400; \ + break; \ + case 4800: \ + flag = B4800; \ + break; \ + case 9600: \ + flag = B9600; \ + break; \ + case 19200: \ + flag = B19200; \ + break; \ + case 38400: \ + flag = B38400; \ + break; \ + case 57600: \ + flag = B57600; \ + break; \ + case 115200: \ + flag = B115200; \ + break; \ + case 230400: \ + flag = B230400; \ + break; \ + case 460800: \ + flag = B460800; \ + break; \ + case 500000: \ + flag = B500000; \ + break; \ + case 576000: \ + flag = B576000; \ + break; \ + case 921600: \ + flag = B921600; \ + break; \ + case 1000000: \ + flag = B1000000; \ + break; \ + case 1152000: \ + flag = B1152000; \ + break; \ + case 1500000: \ + flag = B1500000; \ + break; \ + case 2000000: \ + flag = B2000000; \ + break; \ + case 2500000: \ + flag = B2500000; \ + break; \ + case 3000000: \ + flag = B3000000; \ + break; \ + case 3500000: \ + flag = B3500000; \ + break; \ + case 4000000: \ + flag = B4000000; \ + break; \ + default: \ + ret = -1; \ + break; \ + } \ + if (ret) { \ + errno = EINVAL; \ + } else { \ + (termios)->c_cflag &= ~CBAUD; \ + (termios)->c_cflag |= flag; \ + } \ + ret; \ + }) + +#endif /* _SYS_TERMIOS_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/compilers/gcc/time.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/compilers/gcc/time.h new file mode 100644 index 00000000..febb819e --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/compilers/gcc/time.h @@ -0,0 +1,164 @@ +/* + * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_TIME_H +#define __INCLUDE_TIME_H + +/******************************************************************************** + * Included Files + ********************************************************************************/ +#include +#include +#include +#include +#include + +/******************************************************************************** + * Pre-processor Definitions + ********************************************************************************/ + +/* Clock tick of the system (frequency Hz). + * + * NOTE: This symbolic name CLK_TCK has been removed from the standard. It is + * replaced with CLOCKS_PER_SEC. Both are defined here. + * + * The default value is 100Hz + */ +# define CLK_TCK (1000000) +# define CLOCKS_PER_SEC (1000000) + +#define NSEC_PER_SEC 1000000000 +#define USEC_PER_SEC 1000000 +#define NSEC_PER_USEC 1000 +#define USEC_PER_MSEC 1000 +#define MSEC_PER_SEC 1000 +#define NSEC_PER_MSEC 1000000 +#define TICK2MSEC(tick) ((tick)* (1000 / CLOCKS_PER_SEC)) + +extern long timezone; + +/* CLOCK_REALTIME refers to the standard time source. For most + * implementations, the standard time source is the system timer interrupt. + * However, if the platform supports an RTC, then the standard time source + * will be the RTC for the clock_gettime() and clock_settime() interfaces + * (the system timer is still the time source for all of the interfaces). + * + * CLOCK_REALTIME represents the machine's best-guess as to the current + * wall-clock, time-of-day time. This means that CLOCK_REALTIME can jump + * forward and backward as the system time-of-day clock is changed. + */ + +#define CLOCK_REALTIME 0 + +/* Clock that cannot be set and represents monotonic time since some + * unspecified starting point. It is not affected by changes in the + * system time-of-day clock. + */ +#define CLOCK_MONOTONIC 1 + +/* This is a flag that may be passed to the timer_settime() function */ + +#define TIMER_ABSTIME 1 + +/* Local time is the same as gmtime in this implementation */ +// # define localtime(c) gmtime(c) +// # define localtime_r(c,r) gmtime_r(c,r) + +/******************************************************************************** + * Public Types + ********************************************************************************/ +/* Scalar types */ + +// #ifndef _TIME_T_DECLARED +// #define _TIME_T_DECLARED +// typedef int32_t time_t; /* Holds time in seconds */ +// #endif + + +// #ifndef _CLOCK_T_DECLARED +// #define _CLOCK_T_DECLARED +// typedef uint32_t clock_t; +// #endif + +/* struct tm is the standard representation for "broken out" time. + * + * REVISIT: This structure could be packed better using uint8_t's and + * uint16_t's. The standard definition does, however, call out type int for + * all of the members. NOTE: Any changes to this structure must be also be + * reflected in struct rtc_time defined in include/nuttx/timers/rtc.h; these + * two structures must be cast compatible. + */ + +struct tm +{ + int tm_sec; /* Seconds (0-61, allows for leap seconds) */ + int tm_min; /* Minutes (0-59) */ + int tm_hour; /* Hours (0-23) */ + int tm_mday; /* Day of the month (1-31) */ + int tm_mon; /* Month (0-11) */ + int tm_year; /* Years since 1900 */ + int tm_wday; /* Day of the week (0-6) */ + int tm_yday; /* Day of the year (0-365) */ + int tm_isdst; /* Non-0 if daylight savings time is in effect */ +}; + +/* forward reference (defined in signal.h) */ + +struct sigevent; + +/******************************************************************************** + * Public Data + ********************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/******************************************************************************** + * Public Function Prototypes + ********************************************************************************/ +int clock_settime(clockid_t clockid, const struct timespec *tp); +int clock_gettime(clockid_t clockid, struct timespec *tp); + +time_t mktime(struct tm *tp); +struct tm *gmtime(const time_t *timep); +struct tm *gmtime_r(const time_t *timep, struct tm *result); +struct tm *localtime (const time_t *timep); +struct tm *localtime_r(const time_t *timep, struct tm *result); + +size_t strftime( char *s, size_t max, const char *format, + const struct tm *tm); + +char *ctime( const time_t *timep); + +time_t time( time_t *timep); + +clock_t clock(void); + +double difftime(time_t tim1, time_t tim2); +char *asctime(const struct tm *tim_p); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __INCLUDE_TIME_H */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/errno.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/errno.h new file mode 100644 index 00000000..0c280ce2 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/errno.h @@ -0,0 +1,193 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file errno.h + * @brief header file for error num + * @version V1.0 + * @date 02. June 2017 + ******************************************************************************/ +#ifndef __ERRNO_H__ +#define __ERRNO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************** + * Error Number Definitions + ****************************************************************************/ +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Argument list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ + +/* + * This error code is special: arch syscall entry code will return + * -ENOSYS if users try to call a syscall that doesn't exist. To keep + * failures of syscalls that really do exist distinguishable from + * failures due to attempts to use a nonexistent syscall, syscall + * implementations should refrain from returning -ENOSYS. + */ +#define ENOSYS 38 /* Invalid system call number */ + +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ + +#define EDEADLOCK EDEADLK + +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ + +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ +#define ECANCELED 125 /* Operation Canceled */ +#define ENOKEY 126 /* Required key not available */ +#define EKEYEXPIRED 127 /* Key has expired */ +#define EKEYREVOKED 128 /* Key has been revoked */ +#define EKEYREJECTED 129 /* Key was rejected by service */ + +/* for robust mutexes */ +#define EOWNERDEAD 130 /* Owner died */ +#define ENOTRECOVERABLE 131 /* State not recoverable */ + +#define ERFKILL 132 /* Operation not possible due to RF-kill */ + +#define EHWPOISON 133 /* Memory page has hardware error */ + +#define ENOTSUP 134 /* Not supported */ + +extern int errno; + +#ifdef __cplusplus +} +#endif + +#endif /* __ERRNO_H__ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/inttypes.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/inttypes.h new file mode 100644 index 00000000..cd8b619a --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/inttypes.h @@ -0,0 +1,57 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _PRIV_INTTYPES_H_ +#define _PRIV_INTTYPES_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#include_next + +#undef PRId32 +#undef PRIi32 +#undef PRIo32 +#undef PRIu32 +#undef PRIx32 +#undef PRIX32 + +#undef SCNd32 +#undef SCNi32 +#undef SCNo32 +#undef SCNu32 +#undef SCNx32 + +#define PRId32 __STRINGIFY(d) +#define PRIi32 __STRINGIFY(i) +#define PRIo32 __STRINGIFY(o) +#define PRIu32 __STRINGIFY(u) +#define PRIx32 __STRINGIFY(x) +#define PRIX32 __STRINGIFY(X) + +#define SCNd32 __STRINGIFY(d) +#define SCNi32 __STRINGIFY(i) +#define SCNo32 __STRINGIFY(o) +#define SCNu32 __STRINGIFY(u) +#define SCNx32 __STRINGIFY(x) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/serf/minilibc_stdio.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/serf/minilibc_stdio.h new file mode 100644 index 00000000..67b6bb40 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/serf/minilibc_stdio.h @@ -0,0 +1,85 @@ +/* + * minilibc stdio + * + * Copyright (C): 2012 Hangzhou C-SKY Microsystem Co.,LTD. + * Author: Junshan Hu (junshan_hu@c-sky.com) + * Contrbutior: Chunqiang Li + * Date: 2012-5-4 + */ + +#ifndef _MINILIBC_STDIO_H_ +#define _MINILIBC_STDIO_H_ + +#include + +#define BUFSIZE 2048 + +struct __stdio_file { + int fd; + int flags; + unsigned int bs; /* read: bytes in buffer */ + unsigned int bm; /* position in buffer */ +// unsigned int buflen; /* length of buf */ +// char *buf; + struct __stdio_file *next; /* for fflush */ + unsigned char ungetbuf; + char ungotten; + unsigned int lock; +}; + +#define ERRORINDICATOR 1 +#define EOFINDICATOR 2 +#define BUFINPUT 4 +#define BUFLINEWISE 8 +#define NOBUF 16 +#define STATICBUF 32 +#define FDPIPE 64 +#define CANREAD 128 +#define CANWRITE 256 + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void (*fmt_out_fn)(char * strbuf, int len); +typedef int (*fmt_in_fn)(void); +extern fmt_out_fn g_current_outputs; +extern fmt_in_fn g_current_inputs; +#define print_current_out_set(fn) do{g_current_outputs = fn;}while(0) +#define print_current_in_set(fn) do{g_current_inputs = fn;}while(0) +static inline int is_normal_outputs(void) +{ + if(g_current_inputs) + return 0; + return 1; +} + +/* ..scanf */ +struct arg_scanf { + void *data; + int (*getch)(void*); + int (*putch)(int,void*); +}; + +int __v_scanf(struct arg_scanf* fn, const char *format, va_list arg_ptr); + +struct arg_printf { + void *data; + int (*put)(void*,size_t,void*); +}; + +int yoc__v_printf(struct arg_printf* fn, const char *format, va_list arg_ptr); +int __isinf(double d); +int __isnan(double d); +int __dtostr(double d,char *buf,unsigned int maxlen,unsigned int prec,unsigned int prec2); +int __lltostr(char *s, int size, unsigned long long i, int base, char UpCase); +int __ltostr(char *s, unsigned int size, unsigned long i, unsigned int base, int UpCase); + + +#ifdef __cplusplus +} +#endif + +#endif /* _MINILIBC_STDIO_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/sys/_stdint.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/sys/_stdint.h new file mode 100644 index 00000000..88d8fe4d --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/sys/_stdint.h @@ -0,0 +1,45 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _PRIV_STDINT_H_ +#define _PRIV_STDINT_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#if __STDC_HOSTED__ +/* For newlib and minilibc utint32_t are not same */ +#undef _UINT32_T_DECLARED +#define _UINT32_T_DECLARED +typedef unsigned int uint32_t; + +#undef _INT32_T_DECLARED +#define _INT32_T_DECLARED +typedef signed int int32_t; + +#endif /* __STDC_HOSTED__ */ + +#define IN_ADDR_T_DEFINED + +#include_next + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/sys/random.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/sys/random.h new file mode 100644 index 00000000..bce4b7f7 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/sys/random.h @@ -0,0 +1,34 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __SYS_RANDOM__ +#define __SYS_RANDOM__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +ssize_t getrandom(void *buf, size_t buflen, unsigned int flags); + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif //__SYS_RANDOM__ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/sys/select.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/sys/select.h new file mode 100644 index 00000000..56f479c3 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/sys/select.h @@ -0,0 +1,52 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __SYS_SELECT_H +#define __SYS_SELECT_H + +#include + +#ifndef FD_SETSIZE +#define FD_SETSIZE 1024 +#endif + +typedef unsigned long fd_mask; +typedef struct { + unsigned long fds_bits[FD_SETSIZE / 8 / sizeof(long)]; +} fd_set; + +#define FD_ZERO(s) memset((void*)(s), 0, sizeof(*(s))) +#define FD_SET(d, s) ((s)->fds_bits[(d) / (8 * sizeof(long))] |= (1UL << ((d) % (8 * sizeof(long))))) +#define FD_CLR(d, s) ((s)->fds_bits[(d) / (8 * sizeof(long))] &= ~(1UL << ((d) % (8 * sizeof(long))))) +#define FD_ISSET(d, s) (!!((s)->fds_bits[(d) / (8 * sizeof(long))] & (1UL << ((d) % (8 * sizeof(long)))))) + +#ifdef __cplusplus +extern "C" { +#endif + +int select(int nfds, fd_set *readfds, fd_set *writefds, fd_set *errorfds, + struct timeval *timeout); + +extern int select2(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset, + struct timeval *timeout, void *semaphore); + +#ifdef __cplusplus +} +#endif + +#endif /*__SYS_SELECT_H*/ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/sys/time.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/sys/time.h new file mode 100644 index 00000000..0e4ed9d5 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/sys/time.h @@ -0,0 +1,134 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __INCLUDE_SYS_TIME_H +#define __INCLUDE_SYS_TIME_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef _TIME_T_DECLARED +#define _TIME_T_DECLARED +typedef int32_t time_t; +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Type Definitions + ****************************************************************************/ +#ifndef _TIMEVAL_DEFINED +#define _TIMEVAL_DEFINED +/* struct timeval represents time as seconds plus microseconds */ + +struct timeval +{ + time_t tv_sec; /* Seconds */ + long tv_usec; /* Microseconds */ +}; +#endif + +/* The use of the struct timezone is obsolete; the tz argument should + * normally be specified as NULL (and is ignored in any event). + */ + +struct timezone +{ + int tz_minuteswest; /* Minutes west of Greenwich */ + int tz_dsttime; /* Type of DST correction */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: gettimeofday + * + * Description: + * Get the current time + * + * Conforming to SVr4, 4.3BSD. POSIX.1-2001 describes gettimeofday(). + * POSIX.1-2008 marks gettimeofday() as obsolete, recommending the use of + * clock_gettime(2) instead. + * + * NuttX implements gettimeofday() as a thin layer around clock_gettime(); + * + * Input Parameters: + * tv - The location to return the current time + * tz - Ignored + * + * Returned value: + * Zero (OK) on success; -1 is returned on failure with the errno variable + * set appropriately. + * + ****************************************************************************/ + +int gettimeofday( struct timeval *tv, struct timezone *tz); + +/**************************************************************************** + * Name: settimeofday + * + * Description: + * Set the current time + * + * Conforming to SVr4, 4.3BSD. POSIX.1-2001 describes gettimeofday() but + * not settimeofday(). + * + * NuttX implements settimeofday() as a thin layer around clock_settime(); + * + * Input Parameters: + * tv - The net to time to be set + * tz - Ignored + * + * Returned value: + * Zero (OK) on success; -1 is returned on failure with the errno variable + * set appropriately. + * + ****************************************************************************/ + +int settimeofday( const struct timeval *tv, const struct timezone *tz); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __INCLUDE_SYS_TIME_H */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/mini_printf.c b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/mini_printf.c new file mode 100644 index 00000000..e1aea6e6 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/mini_printf.c @@ -0,0 +1,947 @@ +/////////////////////////////////////////////////////////////////////////////// +// \author (c) Marco Paland (info@paland.com) +// 2014-2019, PALANDesign Hannover, Germany +// +// \license The MIT License (MIT) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. +// +// \brief Tiny printf, sprintf and (v)snprintf implementation, optimized for speed on +// embedded systems with a very limited resources. These routines are thread +// safe and reentrant! +// Use this instead of the bloated standard/newlib printf cause these use +// malloc for printf (and may not be thread safe). +// +/////////////////////////////////////////////////////////////////////////////// + +#if CONFIG_LIBC_MINI_PRINTF_SUPPORT +#include +#include +#include + +#include +#include +#include +#include +#include + + +// define this globally (e.g. gcc -DPRINTF_INCLUDE_CONFIG_H ...) to include the +// printf_config.h header file +// default: undefined +#ifdef PRINTF_INCLUDE_CONFIG_H +#include "printf_config.h" +#endif + + +// 'ntoa' conversion buffer size, this must be big enough to hold one converted +// numeric number including padded zeros (dynamically created on stack) +// default: 32 byte +#ifndef PRINTF_NTOA_BUFFER_SIZE +#define PRINTF_NTOA_BUFFER_SIZE 32U +#endif + +// 'ftoa' conversion buffer size, this must be big enough to hold one converted +// float number including padded zeros (dynamically created on stack) +// default: 32 byte +#ifndef PRINTF_FTOA_BUFFER_SIZE +#define PRINTF_FTOA_BUFFER_SIZE 32U +#endif + +// support for the floating point type (%f) +// default: activated +#ifndef PRINTF_DISABLE_SUPPORT_FLOAT +#define PRINTF_SUPPORT_FLOAT +#endif + +// support for exponential floating point notation (%e/%g) +// default: activated +#ifndef PRINTF_DISABLE_SUPPORT_EXPONENTIAL +#define PRINTF_SUPPORT_EXPONENTIAL +#endif + +// define the default floating point precision +// default: 6 digits +#ifndef PRINTF_DEFAULT_FLOAT_PRECISION +#define PRINTF_DEFAULT_FLOAT_PRECISION 6U +#endif + +// define the largest float suitable to print with %f +// default: 1e9 +#ifndef PRINTF_MAX_FLOAT +#define PRINTF_MAX_FLOAT 1e9 +#endif + +// support for the long long types (%llu or %p) +// default: activated +#ifndef PRINTF_DISABLE_SUPPORT_LONG_LONG +#define PRINTF_SUPPORT_LONG_LONG +#endif + +// support for the ptrdiff_t type (%t) +// ptrdiff_t is normally defined in as long or long long type +// default: activated +#ifndef PRINTF_DISABLE_SUPPORT_PTRDIFF_T +#define PRINTF_SUPPORT_PTRDIFF_T +#endif + +/////////////////////////////////////////////////////////////////////////////// + +// internal flag definitions +#define FLAGS_ZEROPAD (1U << 0U) +#define FLAGS_LEFT (1U << 1U) +#define FLAGS_PLUS (1U << 2U) +#define FLAGS_SPACE (1U << 3U) +#define FLAGS_HASH (1U << 4U) +#define FLAGS_UPPERCASE (1U << 5U) +#define FLAGS_CHAR (1U << 6U) +#define FLAGS_SHORT (1U << 7U) +#define FLAGS_LONG (1U << 8U) +#define FLAGS_LONG_LONG (1U << 9U) +#define FLAGS_PRECISION (1U << 10U) +#define FLAGS_ADAPT_EXP (1U << 11U) + + +// import float.h for DBL_MAX +#if defined(PRINTF_SUPPORT_FLOAT) +#include +#endif + +extern csi_uart_t g_console_handle; + +static void _putchar(char character) +{ + if (character == '\n') { + csi_uart_putc(&g_console_handle, '\r'); + } + + csi_uart_putc(&g_console_handle, character); +} + +// output function type +typedef void (*out_fct_type)(char character, void* buffer, size_t idx, size_t maxlen); + + +// wrapper (used as buffer) for output function type +typedef struct { + void (*fct)(char character, void* arg); + void* arg; +} out_fct_wrap_type; + + +// internal buffer output +static inline void _out_buffer(char character, void* buffer, size_t idx, size_t maxlen) +{ + if (idx < maxlen) { + ((char*)buffer)[idx] = character; + } +} + + +// internal null output +static inline void _out_null(char character, void* buffer, size_t idx, size_t maxlen) +{ + (void)character; + (void)buffer; + (void)idx; + (void)maxlen; +} + + +// internal _putchar wrapper +static inline void _out_char(char character, void* buffer, size_t idx, size_t maxlen) +{ + (void)buffer; + (void)idx; + (void)maxlen; + if (character) { + _putchar(character); + } +} + + +// internal output function wrapper +static inline void _out_fct(char character, void* buffer, size_t idx, size_t maxlen) +{ + (void)idx; + (void)maxlen; + if (character) { + // buffer is the output fct pointer + ((out_fct_wrap_type*)buffer)->fct(character, ((out_fct_wrap_type*)buffer)->arg); + } +} + + +// internal secure strlen +// \return The length of the string (excluding the terminating 0) limited by 'maxsize' +static inline unsigned int _strnlen_s(const char* str, size_t maxsize) +{ + const char* s; + for (s = str; *s && maxsize--; ++s); + return (unsigned int)(s - str); +} + + +// internal test if char is a digit (0-9) +// \return true if char is a digit +static inline bool _is_digit(char ch) +{ + return (ch >= '0') && (ch <= '9'); +} + + +// internal ASCII string to unsigned int conversion +static unsigned int _atoi(const char** str) +{ + unsigned int i = 0U; + while (_is_digit(**str)) { + i = i * 10U + (unsigned int)(*((*str)++) - '0'); + } + return i; +} + + +// output the specified string in reverse, taking care of any zero-padding +static size_t _out_rev(out_fct_type out, char* buffer, size_t idx, size_t maxlen, const char* buf, size_t len, unsigned int width, unsigned int flags) +{ + const size_t start_idx = idx; + + // pad spaces up to given width + if (!(flags & FLAGS_LEFT) && !(flags & FLAGS_ZEROPAD)) { + for (size_t i = len; i < width; i++) { + out(' ', buffer, idx++, maxlen); + } + } + + // reverse string + while (len) { + out(buf[--len], buffer, idx++, maxlen); + } + + // append pad spaces up to given width + if (flags & FLAGS_LEFT) { + while (idx - start_idx < width) { + out(' ', buffer, idx++, maxlen); + } + } + + return idx; +} + + +// internal itoa format +static size_t _ntoa_format(out_fct_type out, char* buffer, size_t idx, size_t maxlen, char* buf, size_t len, bool negative, unsigned int base, unsigned int prec, unsigned int width, unsigned int flags) +{ + // pad leading zeros + if (!(flags & FLAGS_LEFT)) { + if (width && (flags & FLAGS_ZEROPAD) && (negative || (flags & (FLAGS_PLUS | FLAGS_SPACE)))) { + width--; + } + while ((len < prec) && (len < PRINTF_NTOA_BUFFER_SIZE)) { + buf[len++] = '0'; + } + while ((flags & FLAGS_ZEROPAD) && (len < width) && (len < PRINTF_NTOA_BUFFER_SIZE)) { + buf[len++] = '0'; + } + } + + // handle hash + if (flags & FLAGS_HASH) { + if (!(flags & FLAGS_PRECISION) && len && ((len == prec) || (len == width))) { + len--; + if (len && (base == 16U)) { + len--; + } + } + if ((base == 16U) && !(flags & FLAGS_UPPERCASE) && (len < PRINTF_NTOA_BUFFER_SIZE)) { + buf[len++] = 'x'; + } else if ((base == 16U) && (flags & FLAGS_UPPERCASE) && (len < PRINTF_NTOA_BUFFER_SIZE)) { + buf[len++] = 'X'; + } else if ((base == 2U) && (len < PRINTF_NTOA_BUFFER_SIZE)) { + buf[len++] = 'b'; + } + if (len < PRINTF_NTOA_BUFFER_SIZE) { + buf[len++] = '0'; + } + } + + if (len < PRINTF_NTOA_BUFFER_SIZE) { + if (negative) { + buf[len++] = '-'; + } else if (flags & FLAGS_PLUS) { + buf[len++] = '+'; // ignore the space if the '+' exists + } else if (flags & FLAGS_SPACE) { + buf[len++] = ' '; + } + } + + return _out_rev(out, buffer, idx, maxlen, buf, len, width, flags); +} + + +// internal itoa for 'long' type +static size_t _ntoa_long(out_fct_type out, char* buffer, size_t idx, size_t maxlen, unsigned long value, bool negative, unsigned long base, unsigned int prec, unsigned int width, unsigned int flags) +{ + char buf[PRINTF_NTOA_BUFFER_SIZE]; + size_t len = 0U; + + // no hash for 0 values + if (!value) { + flags &= ~FLAGS_HASH; + } + + // write if precision != 0 and value is != 0 + if (!(flags & FLAGS_PRECISION) || value) { + do { + const char digit = (char)(value % base); + buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; + value /= base; + } while (value && (len < PRINTF_NTOA_BUFFER_SIZE)); + } + + return _ntoa_format(out, buffer, idx, maxlen, buf, len, negative, (unsigned int)base, prec, width, flags); +} + + +// internal itoa for 'long long' type +#if defined(PRINTF_SUPPORT_LONG_LONG) +static size_t _ntoa_long_long(out_fct_type out, char* buffer, size_t idx, size_t maxlen, unsigned long long value, bool negative, unsigned long long base, unsigned int prec, unsigned int width, unsigned int flags) +{ + char buf[PRINTF_NTOA_BUFFER_SIZE]; + size_t len = 0U; + + // no hash for 0 values + if (!value) { + flags &= ~FLAGS_HASH; + } + + // write if precision != 0 and value is != 0 + if (!(flags & FLAGS_PRECISION) || value) { + do { + const char digit = (char)(value % base); + buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; + value /= base; + } while (value && (len < PRINTF_NTOA_BUFFER_SIZE)); + } + + return _ntoa_format(out, buffer, idx, maxlen, buf, len, negative, (unsigned int)base, prec, width, flags); +} +#endif // PRINTF_SUPPORT_LONG_LONG + + +#if defined(PRINTF_SUPPORT_FLOAT) + +#if defined(PRINTF_SUPPORT_EXPONENTIAL) +// forward declaration so that _ftoa can switch to exp notation for values > PRINTF_MAX_FLOAT +static size_t _etoa(out_fct_type out, char* buffer, size_t idx, size_t maxlen, double value, unsigned int prec, unsigned int width, unsigned int flags); +#endif + + +// internal ftoa for fixed decimal floating point +static size_t _ftoa(out_fct_type out, char* buffer, size_t idx, size_t maxlen, double value, unsigned int prec, unsigned int width, unsigned int flags) +{ + char buf[PRINTF_FTOA_BUFFER_SIZE]; + size_t len = 0U; + double diff = 0.0; + + // powers of 10 + static const double pow10[] = { 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000, 1000000000 }; + + // test for special values + if (value != value) + return _out_rev(out, buffer, idx, maxlen, "nan", 3, width, flags); + if (value < -DBL_MAX) + return _out_rev(out, buffer, idx, maxlen, "fni-", 4, width, flags); + if (value > DBL_MAX) + return _out_rev(out, buffer, idx, maxlen, (flags & FLAGS_PLUS) ? "fni+" : "fni", (flags & FLAGS_PLUS) ? 4U : 3U, width, flags); + + // test for very large values + // standard printf behavior is to print EVERY whole number digit -- which could be 100s of characters overflowing your buffers == bad + if ((value > PRINTF_MAX_FLOAT) || (value < -PRINTF_MAX_FLOAT)) { +#if defined(PRINTF_SUPPORT_EXPONENTIAL) + return _etoa(out, buffer, idx, maxlen, value, prec, width, flags); +#else + return 0U; +#endif + } + + // test for negative + bool negative = false; + if (value < 0) { + negative = true; + value = 0 - value; + } + + // set default precision, if not set explicitly + if (!(flags & FLAGS_PRECISION)) { + prec = PRINTF_DEFAULT_FLOAT_PRECISION; + } + // limit precision to 9, cause a prec >= 10 can lead to overflow errors + while ((len < PRINTF_FTOA_BUFFER_SIZE) && (prec > 9U)) { + buf[len++] = '0'; + prec--; + } + + int whole = (int)value; + double tmp = (value - whole) * pow10[prec]; + unsigned long frac = (unsigned long)tmp; + diff = tmp - frac; + + if (diff > 0.5) { + ++frac; + // handle rollover, e.g. case 0.99 with prec 1 is 1.0 + if (frac >= pow10[prec]) { + frac = 0; + ++whole; + } + } else if (diff < 0.5) { + } else if ((frac == 0U) || (frac & 1U)) { + // if halfway, round up if odd OR if last digit is 0 + ++frac; + } + + if (prec == 0U) { + diff = value - (double)whole; + if ((!(diff < 0.5) || (diff > 0.5)) && (whole & 1)) { + // exactly 0.5 and ODD, then round up + // 1.5 -> 2, but 2.5 -> 2 + ++whole; + } + } else { + unsigned int count = prec; + // now do fractional part, as an unsigned number + while (len < PRINTF_FTOA_BUFFER_SIZE) { + --count; + buf[len++] = (char)(48U + (frac % 10U)); + if (!(frac /= 10U)) { + break; + } + } + // add extra 0s + while ((len < PRINTF_FTOA_BUFFER_SIZE) && (count-- > 0U)) { + buf[len++] = '0'; + } + if (len < PRINTF_FTOA_BUFFER_SIZE) { + // add decimal + buf[len++] = '.'; + } + } + + // do whole part, number is reversed + while (len < PRINTF_FTOA_BUFFER_SIZE) { + buf[len++] = (char)(48 + (whole % 10)); + if (!(whole /= 10)) { + break; + } + } + + // pad leading zeros + if (!(flags & FLAGS_LEFT) && (flags & FLAGS_ZEROPAD)) { + if (width && (negative || (flags & (FLAGS_PLUS | FLAGS_SPACE)))) { + width--; + } + while ((len < width) && (len < PRINTF_FTOA_BUFFER_SIZE)) { + buf[len++] = '0'; + } + } + + if (len < PRINTF_FTOA_BUFFER_SIZE) { + if (negative) { + buf[len++] = '-'; + } else if (flags & FLAGS_PLUS) { + buf[len++] = '+'; // ignore the space if the '+' exists + } else if (flags & FLAGS_SPACE) { + buf[len++] = ' '; + } + } + + return _out_rev(out, buffer, idx, maxlen, buf, len, width, flags); +} + + +#if defined(PRINTF_SUPPORT_EXPONENTIAL) +// internal ftoa variant for exponential floating-point type, contributed by Martijn Jasperse +static size_t _etoa(out_fct_type out, char* buffer, size_t idx, size_t maxlen, double value, unsigned int prec, unsigned int width, unsigned int flags) +{ + // check for NaN and special values + if ((value != value) || (value > DBL_MAX) || (value < -DBL_MAX)) { + return _ftoa(out, buffer, idx, maxlen, value, prec, width, flags); + } + + // determine the sign + const bool negative = value < 0; + if (negative) { + value = -value; + } + + // default precision + if (!(flags & FLAGS_PRECISION)) { + prec = PRINTF_DEFAULT_FLOAT_PRECISION; + } + + // determine the decimal exponent + // based on the algorithm by David Gay (https://www.ampl.com/netlib/fp/dtoa.c) + union { + uint64_t U; + double F; + } conv; + + conv.F = value; + int exp2 = (int)((conv.U >> 52U) & 0x07FFU) - 1023; // effectively log2 + conv.U = (conv.U & ((1ULL << 52U) - 1U)) | (1023ULL << 52U); // drop the exponent so conv.F is now in [1,2) + // now approximate log10 from the log2 integer part and an expansion of ln around 1.5 + int expval = (int)(0.1760912590558 + exp2 * 0.301029995663981 + (conv.F - 1.5) * 0.289529654602168); + // now we want to compute 10^expval but we want to be sure it won't overflow + exp2 = (int)(expval * 3.321928094887362 + 0.5); + const double z = expval * 2.302585092994046 - exp2 * 0.6931471805599453; + const double z2 = z * z; + conv.U = (uint64_t)(exp2 + 1023) << 52U; + // compute exp(z) using continued fractions, see https://en.wikipedia.org/wiki/Exponential_function#Continued_fractions_for_ex + conv.F *= 1 + 2 * z / (2 - z + (z2 / (6 + (z2 / (10 + z2 / 14))))); + // correct for rounding errors + if (value < conv.F) { + expval--; + conv.F /= 10; + } + + // the exponent format is "%+03d" and largest value is "307", so set aside 4-5 characters + unsigned int minwidth = ((expval < 100) && (expval > -100)) ? 4U : 5U; + + // in "%g" mode, "prec" is the number of *significant figures* not decimals + if (flags & FLAGS_ADAPT_EXP) { + // do we want to fall-back to "%f" mode? + if ((value >= 1e-4) && (value < 1e6)) { + if ((int)prec > expval) { + prec = (unsigned)((int)prec - expval - 1); + } else { + prec = 0; + } + flags |= FLAGS_PRECISION; // make sure _ftoa respects precision + // no characters in exponent + minwidth = 0U; + expval = 0; + } else { + // we use one sigfig for the whole part + if ((prec > 0) && (flags & FLAGS_PRECISION)) { + --prec; + } + } + } + + // will everything fit? + unsigned int fwidth = width; + if (width > minwidth) { + // we didn't fall-back so subtract the characters required for the exponent + fwidth -= minwidth; + } else { + // not enough characters, so go back to default sizing + fwidth = 0U; + } + if ((flags & FLAGS_LEFT) && minwidth) { + // if we're padding on the right, DON'T pad the floating part + fwidth = 0U; + } + + // rescale the float value + if (expval) { + value /= conv.F; + } + + // output the floating part + const size_t start_idx = idx; + idx = _ftoa(out, buffer, idx, maxlen, negative ? -value : value, prec, fwidth, flags & ~FLAGS_ADAPT_EXP); + + // output the exponent part + if (minwidth) { + // output the exponential symbol + out((flags & FLAGS_UPPERCASE) ? 'E' : 'e', buffer, idx++, maxlen); + // output the exponent value + idx = _ntoa_long(out, buffer, idx, maxlen, (expval < 0) ? -expval : expval, expval < 0, 10, 0, minwidth-1, FLAGS_ZEROPAD | FLAGS_PLUS); + // might need to right-pad spaces + if (flags & FLAGS_LEFT) { + while (idx - start_idx < width) out(' ', buffer, idx++, maxlen); + } + } + return idx; +} +#endif // PRINTF_SUPPORT_EXPONENTIAL +#endif // PRINTF_SUPPORT_FLOAT + + +// internal vsnprintf +static int _vsnprintf(out_fct_type out, char* buffer, const size_t maxlen, const char* format, va_list va) +{ + unsigned int flags, width, precision, n; + size_t idx = 0U; + + if (!buffer) { + // use null output function + out = _out_null; + } + + while (*format) { + // format specifier? %[flags][width][.precision][length] + if (*format != '%') { + // no + out(*format, buffer, idx++, maxlen); + format++; + continue; + } else { + // yes, evaluate it + format++; + } + + // evaluate flags + flags = 0U; + do { + switch (*format) { + case '0': + flags |= FLAGS_ZEROPAD; + format++; + n = 1U; + break; + case '-': + flags |= FLAGS_LEFT; + format++; + n = 1U; + break; + case '+': + flags |= FLAGS_PLUS; + format++; + n = 1U; + break; + case ' ': + flags |= FLAGS_SPACE; + format++; + n = 1U; + break; + case '#': + flags |= FLAGS_HASH; + format++; + n = 1U; + break; + default : + n = 0U; + break; + } + } while (n); + + // evaluate width field + width = 0U; + if (_is_digit(*format)) { + width = _atoi(&format); + } else if (*format == '*') { + const int w = va_arg(va, int); + if (w < 0) { + flags |= FLAGS_LEFT; // reverse padding + width = (unsigned int)-w; + } else { + width = (unsigned int)w; + } + format++; + } + + // evaluate precision field + precision = 0U; + if (*format == '.') { + flags |= FLAGS_PRECISION; + format++; + if (_is_digit(*format)) { + precision = _atoi(&format); + } else if (*format == '*') { + const int prec = (int)va_arg(va, int); + precision = prec > 0 ? (unsigned int)prec : 0U; + format++; + } + } + + // evaluate length field + switch (*format) { + case 'l' : + flags |= FLAGS_LONG; + format++; + if (*format == 'l') { + flags |= FLAGS_LONG_LONG; + format++; + } + break; + case 'h' : + flags |= FLAGS_SHORT; + format++; + if (*format == 'h') { + flags |= FLAGS_CHAR; + format++; + } + break; +#if defined(PRINTF_SUPPORT_PTRDIFF_T) + case 't' : + flags |= (sizeof(ptrdiff_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG); + format++; + break; +#endif + case 'j' : + flags |= (sizeof(intmax_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG); + format++; + break; + case 'z' : + flags |= (sizeof(size_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG); + format++; + break; + default : + break; + } + + // evaluate specifier + switch (*format) { + case 'd' : + case 'i' : + case 'u' : + case 'x' : + case 'X' : + case 'o' : + case 'b' : { + // set the base + unsigned int base; + if (*format == 'x' || *format == 'X') { + base = 16U; + } else if (*format == 'o') { + base = 8U; + } else if (*format == 'b') { + base = 2U; + } else { + base = 10U; + flags &= ~FLAGS_HASH; // no hash for dec format + } + // uppercase + if (*format == 'X') { + flags |= FLAGS_UPPERCASE; + } + + // no plus or space flag for u, x, X, o, b + if ((*format != 'i') && (*format != 'd')) { + flags &= ~(FLAGS_PLUS | FLAGS_SPACE); + } + + // ignore '0' flag when precision is given + if (flags & FLAGS_PRECISION) { + flags &= ~FLAGS_ZEROPAD; + } + + // convert the integer + if ((*format == 'i') || (*format == 'd')) { + // signed + if (flags & FLAGS_LONG_LONG) { +#if defined(PRINTF_SUPPORT_LONG_LONG) + const long long value = va_arg(va, long long); + idx = _ntoa_long_long(out, buffer, idx, maxlen, (unsigned long long)(value > 0 ? value : 0 - value), value < 0, base, precision, width, flags); +#endif + } else if (flags & FLAGS_LONG) { + const long value = va_arg(va, long); + idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long)(value > 0 ? value : 0 - value), value < 0, base, precision, width, flags); + } else { + const int value = (flags & FLAGS_CHAR) ? (char)va_arg(va, int) : (flags & FLAGS_SHORT) ? (short int)va_arg(va, int) : va_arg(va, int); + idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned int)(value > 0 ? value : 0 - value), value < 0, base, precision, width, flags); + } + } else { + // unsigned + if (flags & FLAGS_LONG_LONG) { +#if defined(PRINTF_SUPPORT_LONG_LONG) + idx = _ntoa_long_long(out, buffer, idx, maxlen, va_arg(va, unsigned long long), false, base, precision, width, flags); +#endif + } else if (flags & FLAGS_LONG) { + idx = _ntoa_long(out, buffer, idx, maxlen, va_arg(va, unsigned long), false, base, precision, width, flags); + } else { + const unsigned int value = (flags & FLAGS_CHAR) ? (unsigned char)va_arg(va, unsigned int) : (flags & FLAGS_SHORT) ? (unsigned short int)va_arg(va, unsigned int) : va_arg(va, unsigned int); + idx = _ntoa_long(out, buffer, idx, maxlen, value, false, base, precision, width, flags); + } + } + format++; + break; + } +#if defined(PRINTF_SUPPORT_FLOAT) + case 'f' : + case 'F' : + if (*format == 'F') flags |= FLAGS_UPPERCASE; + idx = _ftoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags); + format++; + break; +#if defined(PRINTF_SUPPORT_EXPONENTIAL) + case 'e': + case 'E': + case 'g': + case 'G': + if ((*format == 'g')||(*format == 'G')) flags |= FLAGS_ADAPT_EXP; + if ((*format == 'E')||(*format == 'G')) flags |= FLAGS_UPPERCASE; + idx = _etoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags); + format++; + break; +#endif // PRINTF_SUPPORT_EXPONENTIAL +#endif // PRINTF_SUPPORT_FLOAT + case 'c' : { + unsigned int l = 1U; + // pre padding + if (!(flags & FLAGS_LEFT)) { + while (l++ < width) { + out(' ', buffer, idx++, maxlen); + } + } + // char output + out((char)va_arg(va, int), buffer, idx++, maxlen); + // post padding + if (flags & FLAGS_LEFT) { + while (l++ < width) { + out(' ', buffer, idx++, maxlen); + } + } + format++; + break; + } + + case 's' : { + const char* p = va_arg(va, char*); + unsigned int l = _strnlen_s(p, precision ? precision : (size_t)-1); + // pre padding + if (flags & FLAGS_PRECISION) { + l = (l < precision ? l : precision); + } + if (!(flags & FLAGS_LEFT)) { + while (l++ < width) { + out(' ', buffer, idx++, maxlen); + } + } + // string output + while ((*p != 0) && (!(flags & FLAGS_PRECISION) || precision--)) { + out(*(p++), buffer, idx++, maxlen); + } + // post padding + if (flags & FLAGS_LEFT) { + while (l++ < width) { + out(' ', buffer, idx++, maxlen); + } + } + format++; + break; + } + + case 'p' : { + width = sizeof(void*) * 2U; + flags |= FLAGS_ZEROPAD | FLAGS_UPPERCASE; +#if defined(PRINTF_SUPPORT_LONG_LONG) + const bool is_ll = sizeof(uintptr_t) == sizeof(long long); + if (is_ll) { + idx = _ntoa_long_long(out, buffer, idx, maxlen, (uintptr_t)va_arg(va, void*), false, 16U, precision, width, flags); + } else { +#endif + idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long)((uintptr_t)va_arg(va, void*)), false, 16U, precision, width, flags); +#if defined(PRINTF_SUPPORT_LONG_LONG) + } +#endif + format++; + break; + } + + case '%' : + out('%', buffer, idx++, maxlen); + format++; + break; + + default : + out(*format, buffer, idx++, maxlen); + format++; + break; + } + } + + // termination + out((char)0, buffer, idx < maxlen ? idx : maxlen - 1U, maxlen); + + // return written chars without terminating \0 + return (int)idx; +} + + +/////////////////////////////////////////////////////////////////////////////// + +int printf(const char* format, ...) +{ + va_list va; + va_start(va, format); + char buffer[1]; + const int ret = _vsnprintf(_out_char, buffer, (size_t)-1, format, va); + va_end(va); + return ret; +} + +int fprintf(FILE *stream, const char* format, ...) +{ + + va_list va; + va_start(va, format); + char buffer[1]; + const int ret = _vsnprintf(_out_char, buffer, (size_t)-1, format, va); + va_end(va); + return ret; +} + + + +int sprintf(char* buffer, const char* format, ...) +{ + va_list va; + va_start(va, format); + const int ret = _vsnprintf(_out_buffer, buffer, (size_t)-1, format, va); + va_end(va); + return ret; +} + + +int snprintf(char* buffer, size_t count, const char* format, ...) +{ + va_list va; + va_start(va, format); + const int ret = _vsnprintf(_out_buffer, buffer, count, format, va); + va_end(va); + return ret; +} + + +int vprintf(const char* format, va_list va) +{ + char buffer[1]; + return _vsnprintf(_out_char, buffer, (size_t)-1, format, va); +} + + +int vsnprintf(char* buffer, size_t count, const char* format, va_list va) +{ + return _vsnprintf(_out_buffer, buffer, count, format, va); +} + + +int fctprintf(void (*out)(char character, void* arg), void* arg, const char* format, ...) +{ + va_list va; + va_start(va, format); + const out_fct_wrap_type out_fct_wrap = { out, arg }; + const int ret = _vsnprintf(_out_fct, (char*)(uintptr_t)&out_fct_wrap, (size_t)-1, format, va); + va_end(va); + return ret; +} +#endif + diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/newlib_stub.c b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/newlib_stub.c new file mode 100644 index 00000000..593d8572 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/newlib_stub.c @@ -0,0 +1,317 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern csi_uart_t g_console_handle; + +int _execve_r(struct _reent *ptr, const char *name, char *const *argv, + char *const *env) +{ + ptr->_errno = ENOSYS; + return -1; +} + +int _fcntl_r(struct _reent *ptr, int fd, int cmd, int arg) +{ + ptr->_errno = EBADF; + return -1; +} + +int _fork_r(struct _reent *ptr) +{ + ptr->_errno = ENOSYS; + return -1; +} + +int _getpid_r(struct _reent *ptr) +{ + ptr->_errno = ENOSYS; + return 0; +} + +int _isatty_r(struct _reent *ptr, int fd) +{ + if (fd >= 0 && fd < 3) { + return 1; + } + + ptr->_errno = ENOTTY; + return 0; +} + +int _kill_r(struct _reent *ptr, int pid, int sig) +{ + ptr->_errno = ENOSYS; + return -1; +} + +_off_t _lseek_r(struct _reent *ptr, int fd, _off_t pos, int whence) +{ + ptr->_errno = ENOSYS; + return -1; +} + +int _mkdir_r(struct _reent *ptr, const char *name, int mode) +{ + ptr->_errno = ENOSYS; + return -1; +} + +int _open_r(struct _reent *ptr, const char *file, int flags, int mode) +{ + ptr->_errno = ENOSYS; + return -1; +} + +int _close_r(struct _reent *ptr, int fd) +{ + ptr->_errno = EBADF; + return -1; +} + +_ssize_t _read_r(struct _reent *ptr, int fd, void *buf, size_t nbytes) +{ + ptr->_errno = EBADF; + return -1; +} + +int fputc(int ch, FILE *stream) +{ + if (ch == '\n') { + csi_uart_putc(&g_console_handle, '\r'); + } + + csi_uart_putc(&g_console_handle, ch); + return 0; +} + +int fgetc(FILE *stream) +{ + (void)stream; + + return csi_uart_getc(&g_console_handle); +} + +int putc(int c, FILE *stream) +{ + return fputc(c, stream); +} + +int puts(const char *s) +{ + while(*s !='\0') { + fputc(*s, (void *)-1); + s++; + } + fputc('\n', (void *)-1); + return 0; +} + +static void _putchar(char character) +{ + if (character == '\n') { + csi_uart_putc(&g_console_handle, '\r'); + } + + csi_uart_putc(&g_console_handle, character); + +} + +int putchar(int c) +{ + _putchar(c); + return 0; +} + +_ssize_t _write_r(struct _reent *ptr, int fd, const void *buf, size_t nbytes) +{ + if ((fd == STDOUT_FILENO) || (fd == STDERR_FILENO)) { + for (int i = 0; i < nbytes; i++) + _putchar((*((char*)buf + i))); + return nbytes; + } else { + return -1; + } +} + +int ioctl(int fildes, int request, ... /* arg */) +{ + return -1; +} + +int _rename_r(struct _reent *ptr, const char *oldname, const char *newname) +{ + ptr->_errno = ENOSYS; + return -1; +} + +void *_sbrk_r(struct _reent *ptr, ptrdiff_t incr) +{ + ptr->_errno = ENOSYS; + return NULL; +} + +int _stat_r(struct _reent *ptr, const char *file, struct stat *pstat) +{ + ptr->_errno = ENOSYS; + return -1; +} + +int _fstat_r(struct _reent *ptr, int fd, struct stat *buf) +{ + ptr->_errno = EBADF; + return -1; +} + +_CLOCK_T_ _times_r(struct _reent *ptr, struct tms *ptms) +{ + ptr->_errno = ENOSYS; + return -1; +} + +int _link_r(struct _reent *ptr, const char *oldpath, const char *newpath) +{ + ptr->_errno = ENOSYS; + return -1; +} + +int _unlink_r(struct _reent *ptr, const char *file) +{ + ptr->_errno = ENOSYS; + return -1; +} + +int _wait_r(struct _reent *ptr, int *status) +{ + ptr->_errno = ENOSYS; + return -1; +} + +int _gettimeofday_r(struct _reent *ptr, struct timeval *tv, void *__tzp) +{ + return 0; +} + +long timezone = 8; /* default CTS */ + +struct tm* localtime_r(const time_t* t, struct tm* r) +{ + time_t time_tmp; + time_tmp = *t + timezone * 3600; + return gmtime_r(&time_tmp, r); +} + +struct tm* localtime(const time_t* t) +{ + struct tm* timeinfo; + static struct tm tm_tmp; + + timeinfo = localtime_r(t, &tm_tmp); + + return timeinfo; +} + +extern TX_BYTE_POOL tx_byte_pool_0; +void *_malloc_r(struct _reent *ptr, size_t size) +{ + UINT ret; + void *p; + + ret = tx_byte_allocate(&tx_byte_pool_0, &p, size, TX_NO_WAIT); + if(ret != TX_SUCCESS) { + return NULL; + } + return p; +} + +void *_realloc_r(struct _reent *ptr, void *old, size_t newlen) +{ + return NULL; +} + +void *_calloc_r(struct _reent *ptr, size_t size, size_t len) +{ + UINT ret; + void *p; + + ret = tx_byte_allocate(&tx_byte_pool_0, &p, size * len, TX_NO_WAIT); + if(ret != TX_SUCCESS) { + return NULL; + } + memset(p, 0, size * len); + + return p; +} + +void *_memalign_r(struct _reent *ptr, size_t alignment, size_t size) +{ + return NULL; +} + +void _free_r(struct _reent *ptr, void *addr) +{ + if (!addr) + return; + tx_byte_release(addr); +} + +void _exit(int status) +{ + while (1) + ; +} + +void exit(int status) +{ + __builtin_unreachable(); // fix noreturn warning +} + +__attribute__((weak)) void _fini() +{ +} + +void _system(const char *s) +{ + return; +} + +void abort(void) +{ + __builtin_unreachable(); // fix noreturn warning +} + +int isatty(int fd) +{ + if (fd == fileno(stdin) || fd == fileno(stdout) || fd == fileno(stderr)) { + return -1; + } + return 0; +} + diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/demo_threadx.c b/ports/xuantie/e906/gnu/example_build/smartl_fpga/demo_threadx.c new file mode 100644 index 00000000..5f17f954 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/demo_threadx.c @@ -0,0 +1,372 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; +UCHAR memory_area[DEMO_BYTE_POOL_SIZE]; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + puts("[Thread] : thread_0_entry is here!"); + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + puts("[Thread] : thread_1_entry is here!"); + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + puts("[Thread] : thread_2_entry is here!"); + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + puts("[Thread] : thread_3_and_4_entry is here!"); + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + puts("[Thread] : thread_5_entry is here!"); + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + puts("[Thread] : thread_6_and_7_entry is here!"); + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/gdbinit b/ports/xuantie/e906/gnu/example_build/smartl_fpga/gdbinit new file mode 100644 index 00000000..1042ec78 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/gdbinit @@ -0,0 +1 @@ +target remote localhost:1234 \ No newline at end of file diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/pre_main.c b/ports/xuantie/e906/gnu/example_build/smartl_fpga/pre_main.c new file mode 100644 index 00000000..7227633d --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/pre_main.c @@ -0,0 +1,27 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +extern int main(); + +void pre_main(void) +{ + board_init(); + main(); +} \ No newline at end of file diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/tx_user.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/tx_user.h new file mode 100644 index 00000000..896e2233 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/tx_user.h @@ -0,0 +1,370 @@ +/*************************************************************************** + * Copyright (c) 2024 Microsoft Corporation + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** User Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_user.h PORTABLE C */ +/* 6.3.0 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains user defines for configuring ThreadX in specific */ +/* ways. This file will have an effect only if the application and */ +/* ThreadX library are built with TX_INCLUDE_USER_DEFINE_FILE defined. */ +/* Note that all the defines in this file may also be made on the */ +/* command line when building ThreadX library and application objects. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ +/* 03-02-2021 Scott Larson Modified comment(s), */ +/* added option to remove */ +/* FileX pointer, */ +/* resulting in version 6.1.5 */ +/* 06-02-2021 Scott Larson Added options for multiple */ +/* block pool search & delay, */ +/* resulting in version 6.1.7 */ +/* 10-15-2021 Yuxin Zhou Modified comment(s), added */ +/* user-configurable symbol */ +/* TX_TIMER_TICKS_PER_SECOND */ +/* resulting in version 6.1.9 */ +/* 04-25-2022 Wenhui Xie Modified comment(s), */ +/* optimized the definition of */ +/* TX_TIMER_TICKS_PER_SECOND, */ +/* resulting in version 6.1.11 */ +/* 10-31-2023 Xiuwen Cai Modified comment(s), */ +/* added option for random */ +/* number stack filling, */ +/* resulting in version 6.3.0 */ +/* */ +/**************************************************************************/ + +#ifndef TX_USER_H +#define TX_USER_H + +#ifndef __ASSEMBLY__ +/* define extra stack size */ +#if __riscv_matrix || __riscv_xtheadmatrix +static inline int _csi_xmlenb_get_value(void) +{ + int result; + __asm volatile("csrr %0, xmlenb" : "=r"(result) : : "memory"); + return result; +} +#define STACK_M_EXTRAL_SIZE (_csi_xmlenb_get_value() * 8 + 24) +#else +#define STACK_M_EXTRAL_SIZE 0 +#endif /* __riscv_matrix || __riscv_xtheadmatrix */ + +#ifdef __riscv_vector +static inline int _csi_vlenb_get_value(void) +{ + int result; + __asm volatile("csrr %0, vlenb" : "=r"(result) : : "memory"); + return result; +} + +#define STACK_V_EXTRAL_SIZE (_csi_vlenb_get_value() * 32 + 40) +#else +#define STACK_V_EXTRAL_SIZE 0 +#endif /* __riscv_vector */ + +#ifdef __riscv_flen +#define STACK_F_EXTRAL_SIZE (__riscv_flen / 8 * 32 + 8) +#else +#define STACK_F_EXTRAL_SIZE 0 +#endif /*__riscv_flen*/ + +#define CSK_CPU_STACK_EXTRAL (STACK_M_EXTRAL_SIZE + STACK_V_EXTRAL_SIZE + STACK_F_EXTRAL_SIZE) + +#ifndef STATIC_CSK_CPU_STACK_EXTRAL +#if defined(__riscv_matrix) || defined(__riscv_xtheadmatrix) || defined(__riscv_vector) +/* FIXME: for static allocate stack */ +#define STATIC_CSK_CPU_STACK_EXTRAL (8192) +#else +#define STATIC_CSK_CPU_STACK_EXTRAL (0) +#endif +#endif /* STATIC_CSK_CPU_STACK_EXTRAL */ + +#endif /* __ASSEMBLY__ */ + +/* Define various build options for the ThreadX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. + + For maximum speed, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + TX_REACTIVATE_INLINE + TX_DISABLE_STACK_FILLING + TX_INLINE_THREAD_RESUME_SUSPEND + + For minimum size, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NO_FILEX_POINTER + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + + Of course, many of these defines reduce functionality and/or change the behavior of the + system in ways that may not be worth the trade-off. For example, the TX_TIMER_PROCESS_IN_ISR + results in faster and smaller code, however, it increases the amount of processing in the ISR. + In addition, some services that are available in timers are not available from ISRs and will + therefore return an error if this option is used. This may or may not be desirable for a + given application. */ + + +/* Override various options with default values already assigned in tx_port.h. Please also refer + to tx_port.h for descriptions on each of these options. */ + +#define TX_MAX_PRIORITIES 32 +#define TX_MINIMUM_STACK (512 + CSK_CPU_STACK_EXTRAL) +#define TX_TIMER_THREAD_STACK_SIZE (512 + STATIC_CSK_CPU_STACK_EXTRAL) +/* +#define TX_MAX_PRIORITIES 32 +#define TX_MINIMUM_STACK ???? +#define TX_THREAD_USER_EXTENSION ???? +#define TX_TIMER_THREAD_STACK_SIZE ???? +#define TX_TIMER_THREAD_PRIORITY ???? +*/ + +/* Define the common timer tick reference for use by other middleware components. The default + value is 10ms (i.e. 100 ticks, defined in tx_api.h), but may be replaced by a port-specific + version in tx_port.h or here. + Note: the actual hardware timer value may need to be changed (usually in tx_initialize_low_level). */ + +#ifdef CONFIG_SYSTICK_HZ +#define TX_TIMER_TICKS_PER_SECOND CONFIG_SYSTICK_HZ +#else +#define TX_TIMER_TICKS_PER_SECOND 100 +#endif +/* +#define TX_TIMER_TICKS_PER_SECOND (100UL) +*/ + +/* Determine if there is a FileX pointer in the thread control block. + By default, the pointer is there for legacy/backwards compatibility. + The pointer must also be there for applications using FileX. + Define this to save space in the thread control block. +*/ + +/* +#define TX_NO_FILEX_POINTER +*/ + +/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls + should be processed within the a system timer thread or directly in the timer ISR. + By default, the timer thread is used. When the following is defined, the timer expiration + processing is done directly from the timer ISR, thereby eliminating the timer thread control + block, stack, and context switching to activate it. */ + +/* +#define TX_TIMER_PROCESS_IN_ISR +*/ + +/* Determine if in-line timer reactivation should be used within the timer expiration processing. + By default, this is disabled and a function call is used. When the following is defined, + reactivating is performed in-line resulting in faster timer processing but slightly larger + code size. */ + +/* +#define TX_REACTIVATE_INLINE +*/ + +/* Determine is stack filling is enabled. By default, ThreadX stack filling is enabled, + which places an 0xEF pattern in each byte of each thread's stack. This is used by + debuggers with ThreadX-awareness and by the ThreadX run-time stack checking feature. */ + +/* +#define TX_DISABLE_STACK_FILLING +*/ + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +/* +#define TX_ENABLE_STACK_CHECKING +*/ + +/* Determine if random number is used for stack filling. By default, ThreadX uses a fixed + pattern for stack filling. When the following is defined, ThreadX uses a random number + for stack filling. This is effective only when TX_ENABLE_STACK_CHECKING is defined. */ + +/* +#define TX_ENABLE_RANDOM_NUMBER_STACK_FILLING +*/ + +/* Determine if preemption-threshold should be disabled. By default, preemption-threshold is + enabled. If the application does not use preemption-threshold, it may be disabled to reduce + code size and improve performance. */ + +/* +#define TX_DISABLE_PREEMPTION_THRESHOLD +*/ + +/* Determine if global ThreadX variables should be cleared. If the compiler startup code clears + the .bss section prior to ThreadX running, the define can be used to eliminate unnecessary + clearing of ThreadX global variables. */ + +/* +#define TX_DISABLE_REDUNDANT_CLEARING +*/ + +/* Determine if no timer processing is required. This option will help eliminate the timer + processing when not needed. The user will also have to comment out the call to + tx_timer_interrupt, which is typically made from assembly language in + tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR + must also be used and tx_timer_initialize must be removed from ThreadX library. */ + +/* +#define TX_NO_TIMER +#ifndef TX_TIMER_PROCESS_IN_ISR +#define TX_TIMER_PROCESS_IN_ISR +#endif +*/ + +/* Determine if the notify callback option should be disabled. By default, notify callbacks are + enabled. If the application does not use notify callbacks, they may be disabled to reduce + code size and improve performance. */ + +/* +#define TX_DISABLE_NOTIFY_CALLBACKS +*/ + + +/* Determine if the tx_thread_resume and tx_thread_suspend services should have their internal + code in-line. This results in a larger image, but improves the performance of the thread + resume and suspend services. */ + +/* +#define TX_INLINE_THREAD_RESUME_SUSPEND +*/ + + +/* Determine if the internal ThreadX code is non-interruptable. This results in smaller code + size and less processing overhead, but increases the interrupt lockout time. */ + +/* +#define TX_NOT_INTERRUPTABLE +*/ + + +/* Determine if the trace event logging code should be enabled. This causes slight increases in + code size and overhead, but provides the ability to generate system trace information which + is available for viewing in TraceX. */ + +/* +#define TX_ENABLE_EVENT_TRACE +*/ + + +/* Determine if block pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various block pool performance information. */ + +/* +#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if byte pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various byte pool performance information. */ + +/* +#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if event flags performance gathering is required by the application. When the following is + defined, ThreadX gathers various event flags performance information. */ + +/* +#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if mutex performance gathering is required by the application. When the following is + defined, ThreadX gathers various mutex performance information. */ + +/* +#define TX_MUTEX_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if queue performance gathering is required by the application. When the following is + defined, ThreadX gathers various queue performance information. */ + +/* +#define TX_QUEUE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if semaphore performance gathering is required by the application. When the following is + defined, ThreadX gathers various semaphore performance information. */ + +/* +#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if thread performance gathering is required by the application. When the following is + defined, ThreadX gathers various thread performance information. */ + +/* +#define TX_THREAD_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if timer performance gathering is required by the application. When the following is + defined, ThreadX gathers various timer performance information. */ + +/* +#define TX_TIMER_ENABLE_PERFORMANCE_INFO +*/ + +/* Override options for byte pool searches of multiple blocks. */ + +/* +#define TX_BYTE_POOL_MULTIPLE_BLOCK_SEARCH 20 +*/ + +/* Override options for byte pool search delay to avoid thrashing. */ + +/* +#define TX_BYTE_POOL_DELAY_VALUE 3 +*/ + +#endif + diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/xuantie_e906_gnu.cmake b/ports/xuantie/e906/gnu/example_build/smartl_fpga/xuantie_e906_gnu.cmake new file mode 100644 index 00000000..2f6e9d91 --- /dev/null +++ b/ports/xuantie/e906/gnu/example_build/smartl_fpga/xuantie_e906_gnu.cmake @@ -0,0 +1,15 @@ +# Name of the target +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_PROCESSOR xuantie_e906) + +set(THREADX_ARCH "xuantie_e906") +set(THREADX_TOOLCHAIN "gnu") +set(ARCH_FLAGS "-g -mcpu=e906fdp -mcmodel=medlow") +set(CFLAGS "${ARCH_FLAGS}") +set(ASFLAGS "${ARCH_FLAGS}") +set(LDFLAGS "${ARCH_FLAGS}") + +set(TX_USER_FILE ${CMAKE_CURRENT_LIST_DIR}/tx_user.h) +set(THREADX_CUSTOM_PORT ${CMAKE_CURRENT_LIST_DIR}/../../) + +include(${CMAKE_CURRENT_LIST_DIR}/../../../../../../cmake/riscv64-unknown-elf.cmake) \ No newline at end of file diff --git a/ports/xuantie/e906/gnu/inc/tx_port.h b/ports/xuantie/e906/gnu/inc/tx_port.h new file mode 100644 index 00000000..50f87587 --- /dev/null +++ b/ports/xuantie/e906/gnu/inc/tx_port.h @@ -0,0 +1,361 @@ +/*************************************************************************** + * Copyright (c) 2024 Microsoft Corporation + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h RISC-V64/GNU */ +/* 6.2.1 */ +/* */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + +#include +#include + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long long ULONG64; +typedef short SHORT; +typedef unsigned short USHORT; +#define ULONG64_DEFINED + +#define ALIGN_TYPE_DEFINED +#define ALIGN_TYPE ULONG + + +typedef struct thread_stack_frame { + unsigned long epc; /* epc - epc - program counter */ + unsigned long ra; /* x1 - ra - return address for jumps */ + unsigned long t0; /* x5 - t0 - temporary register 0 */ + unsigned long t1; /* x6 - t1 - temporary register 1 */ + unsigned long t2; /* x7 - t2 - temporary register 2 */ + unsigned long s0_fp; /* x8 - s0/fp - saved register 0 or frame pointer */ + unsigned long s1; /* x9 - s1 - saved register 1 */ + unsigned long a0; /* x10 - a0 - return value or function argument 0 */ + unsigned long a1; /* x11 - a1 - return value or function argument 1 */ + unsigned long a2; /* x12 - a2 - function argument 2 */ + unsigned long a3; /* x13 - a3 - function argument 3 */ + unsigned long a4; /* x14 - a4 - function argument 4 */ + unsigned long a5; /* x15 - a5 - function argument 5 */ + unsigned long a6; /* x16 - a6 - function argument 6 */ + unsigned long a7; /* x17 - s7 - function argument 7 */ + unsigned long s2; /* x18 - s2 - saved register 2 */ + unsigned long s3; /* x19 - s3 - saved register 3 */ + unsigned long s4; /* x20 - s4 - saved register 4 */ + unsigned long s5; /* x21 - s5 - saved register 5 */ + unsigned long s6; /* x22 - s6 - saved register 6 */ + unsigned long s7; /* x23 - s7 - saved register 7 */ + unsigned long s8; /* x24 - s8 - saved register 8 */ + unsigned long s9; /* x25 - s9 - saved register 9 */ + unsigned long s10; /* x26 - s10 - saved register 10 */ + unsigned long s11; /* x27 - s11 - saved register 11 */ + unsigned long t3; /* x28 - t3 - temporary register 3 */ + unsigned long t4; /* x29 - t4 - temporary register 4 */ + unsigned long t5; /* x30 - t5 - temporary register 5 */ + unsigned long t6; /* x31 - t6 - temporary register 6 */ + unsigned long mstatus; /* - machine status register */ +} tx_stack_frame_t; + +typedef struct __attribute__((packed)) { + unsigned long fcsr; +#if __riscv_float_abi_single + unsigned long f[32]; /* f0~f31 */ +#elif __riscv_float_abi_double + unsigned long long f[32]; /* f0~f31 */ +#endif +} tx_stack_f_frame_t; + +typedef struct { + unsigned long vxsat; +} tx_stack_p_frame_t; + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 1024 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX RISC-V port. */ + +#define TX_INT_DISABLE 0x00000000 /* Disable interrupts value */ +#define TX_INT_ENABLE 0x00000008 /* Enable interrupt value */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; \ + VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; +#endif +#ifndef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#define TX_THREAD_EXTENSION_3 +#else +#define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ + unsigned long long tx_thread_execution_time_last_start; +#endif + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef TX_DISABLE_INLINE + +#define TX_INTERRUPT_SAVE_AREA register ULONG interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); +#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA ULONG interrupt_save; +/* Atomically read mstatus into interrupt_save and clear bit 3 of mstatus. */ +#define TX_DISABLE {__asm__ volatile ("csrrci %0, mstatus, 0x08" : "=r" (interrupt_save) : : "memory");}; +/* We only care about mstatus.mie (bit 3), so mask interrupt_save and write to mstatus. */ +#define TX_RESTORE {register ULONG __tempmask = interrupt_save & 0x08; \ + __asm__ volatile ("csrrs x0, mstatus, %0 \n\t" : : "r" (__tempmask) : "memory");}; + +#endif + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) 2024 Microsoft Corporation. * ThreadX RISC-V32/GNU Version 6.4.2 *"; +#else +extern CHAR _tx_version_id[]; +#endif + +#endif diff --git a/ports/xuantie/e906/gnu/readme_threadx.txt b/ports/xuantie/e906/gnu/readme_threadx.txt new file mode 100644 index 00000000..56189b6e --- /dev/null +++ b/ports/xuantie/e906/gnu/readme_threadx.txt @@ -0,0 +1,334 @@ + Eclipse Foundation's RTOS, ThreadX for XuanTie E906 + + Using the GNU Tools + +The XuanTie E906 is a fully synthesizable, middle-end, microcontroller-class processor that is compatible to the RISC-V RV32IMA[F][D]C[P] ISA. It +delivers considerable integer and enhanced, energy-efficient floating-point compute performance especially the double precision. + +1. Building the ThreadX run-time Library + +Prerequisites +- Install a XuanTie bare-metal GNU toolchain with riscv64-unknown-elf prefix +- Download URL: https://www.xrvm.cn/community/download?versionId=4460156621967921152 +- Toolchain archive name: XuanTie-900-gcc-elf-newlib-x86_64-V3.2.0-20250627.tar.gz + +Verify the toolchain: + riscv64-unknown-elf-gcc --version + riscv64-unknown-elf-objdump --version + +Library build script + ports/xuantie/e906/gnu/example_build/smartl_fpga/build_libthreadx.sh + +Example build script + +The example demonstration contains a build script. See: + + ports/xuantie/e906/gnu/example_build/smartl_fpga/build_threadx_sample.sh + +This script builds the library and the demo application demo_threadx.elf. + + +2. Demonstration System (QEMU) + +Prerequisites +- Install a XuanTie QEMU +- Download URL: https://www.xrvm.cn/community/download?versionId=4468398114511851520 +- QEMU archive name: XuanTie-qemu-x86_64-Ubuntu-20.04-V5.2.8-B20250721-0303.tar.gz + +The provided example is targeted at XuanTie QEMU's smartl platform. After building the +example, the produced demo_threadx.elf can be executed in QEMU: + + qemu-system-riscv32 -nographic -machine smartl -cpu e906fdp -kernel demo_threadx.elf + +Typical QEMU features used: +- Single-core CPU +- UART serial console +- CLIC (Core-Local Interrupt Controller) + +3. System Initialization + +Entry Point + +The example startup code begins at the Reset_Handler label in startup.S. This startup +code performs hardware initialization including: +- Initialize gp register +- Set up the entry for interrupt and exception handler +- Set up initial stack pointer +- Jump to SystemInit() for initialize CLICã€Clear BSSã€Cacheã€System Clockã€System Tick +- Jump to pre_main() + +In pre_main(), the following initialization is performed: +Board Initialization (board_init.c) +- Initialize UART + +Then jump to main(). + +4. Register Usage and Stack Frames + +The RISC-V32 ABI defines t0-t6 and a0-a7 as caller-saved (temporary) registers. +All other registers used by a function must be preserved by the function. + +Stack Layout for Task Frame (with FP double and P-extension enabled): + + Index Offset Register Description + ───────────────────────────────────────────────── + 0 0x00 mepc machine exception PC + 1 0x04 ra return address + 2 0x08 t0 temporary register 0 + 3 0x0C t1 temporary register 1 + 4 0x10 t2 temporary register 2 + 5 0x14 s0 saved register 0 or frame pointer + 6 0x18 s1 saved register 1 + 7 0x1C a0 argument register 0 + 8 0x20 a1 argument register 1 + 9 0x24 a2 argument register 2 + 10 0x28 a3 argument register 3 + 11 0x2C a4 argument register 4 + 12 0x30 a5 argument register 5 + 13 0x34 a6 argument register 6 + 14 0x38 a7 argument register 7 + 15 0x3C s2 saved register 2 + 16 0x40 s3 saved register 3 + 17 0x44 s4 saved register 4 + 18 0x48 s5 saved register 5 + 19 0x4C s6 saved register 6 + 20 0x50 s7 saved register 7 + 21 0x54 s8 saved register 8 + 22 0x58 s9 saved register 9 + 23 0x5C s10 saved register 10 + 24 0x60 s11 saved register 11 + 25 0x64 t3 temporary register 3 + 26 0x68 t4 temporary register 4 + 27 0x6C t5 temporary register 5 + 28 0x70 t6 temporary register 6 + 29 0x74 mstatus machine status register + + 30 0x78 fcsr FP control/status register + 31 0x7C ft0 FP temporary register 0 + 32 0x84 ft1 FP temporary register 1 + 33 0x8C ft2 FP temporary register 2 + 34 0x94 ft3 FP temporary register 3 + 35 0x9C ft4 FP temporary register 4 + 36 0xA4 ft5 FP temporary register 5 + 37 0xAC ft6 FP temporary register 6 + 38 0xB4 ft7 FP temporary register 7 + 39 0xBC fs0 FP saved register 0 + 40 0xC4 fs1 FP saved register 1 + 41 0xCC fa0 FP argument register 0 + 42 0xD4 fa1 FP argument register 1 + 43 0xDC fa2 FP argument register 2 + 44 0xE4 fa3 FP argument register 3 + 45 0xEC fa4 FP argument register 4 + 46 0xF4 fa5 FP argument register 5 + 47 0xFC fa6 FP argument register 6 + 48 0x104 fa7 FP argument register 7 + 49 0x10C fs2 FP saved register 2 + 50 0x114 fs3 FP saved register 3 + 51 0x11C fs4 FP saved register 4 + 52 0x124 fs5 FP saved register 5 + 53 0x12C fs6 FP saved register 6 + 54 0x134 fs7 FP saved register 7 + 55 0x13C fs8 FP saved register 8 + 56 0x144 fs9 FP saved register 9 + 57 0x14C fs10 FP saved register 10 + 58 0x154 fs11 FP saved register 11 + 59 0x15C ft8 FP temporary register 8 + 60 0x164 ft9 FP temporary register 9 + 61 0x16C ft10 FP temporary register 10 + 62 0x174 ft11 FP temporary register 11 + + 63 0x17C vxsat fixed-point saturation flag register + ───────────────────────────────────────────────── + + +5. Interrupt Handling + +Machine Mode Operation + +ThreadX operates in machine mode (M-mode), the highest privilege level. +All interrupts and exceptions trap to machine mode. + +Interrupt Sources + +1. Machine Timer Interrupt (MTI): + - Triggered by CLINT when mtime >= mtimecmp + - Handled by _tx_timer_interrupt (src/tx_timer_interrupt.c) + - Called from tick_irq_handler() in example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/tick.c + +2. External Interrupts (MEI): + - Routed through CLIC + - Handled by do_irq() in example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/irq.c + +3. Software Interrupts (MSI): + - Routed through CLIC + - Handled by tspend_handler() in src/tx_thread_context.S + +Interrupt Control Macros + +TX_DISABLE and TX_RESTORE macros atomically manage the MIE bit in mstatus: + + TX_DISABLE: Saves and clears MIE bit via csrrci (CSR read-clear immediate) + TX_RESTORE: Restores only MIE bit via csrrs (CSR read-set) + Other mstatus bits remain unchanged + +These are defined in ports/xuantie/e906/gnu/inc/tx_port.h and use the +_tx_thread_interrupt_control() function. + + +6. Thread Scheduling and Context Switching + +Fist Thread Switch (src/tx_thread_schedule.S) +1. Enables interrupts while waiting a thread +2. Spins until _tx_thread_execute_ptr becomes non-NULL +3. Disables interrupts (critical section) +4. Sets _tx_thread_current_ptr = _tx_thread_execute_ptr +5. Increments thread's run count +6. Switches to thread's stack +7. Restores the thread's context, then returns via mret + +Thread Scheduler (src/tx_thread_system_return.S, src/tx_thread_context.S) +1. Set a software interrupt to trigger context switch +2. Come to software interrupt handler (tspend_handler) +3. Save previous thread's context +4. Check and waiting for _tx_thread_execute_ptr != NULL +5. Switch thread sp to _tx_thread_execute_ptr +6. Restores the thread's context, then returns via mret + +Initial Thread Stack Frame (src/tx_thread_stack_build.S) + +New threads start with a fake interrupt frame containing: +- All registers initialized to 0 +- ra (x1) = _tx_thread_exit +- mepc = entry function pointer +- mstatus = mstatus.FS=1 | mstatus.MPP=3 | mstatus.MPIE=1 +- Floating-point registers initialized based on ABI + + +7. Port Configuration and Macros + +Default Configurations (in ports/risc-v64/gnu/inc/tx_port.h): + + TX_MINIMUM_STACK 1024 /* Minimum thread stack size */ + TX_TIMER_THREAD_STACK_SIZE 1024 /* Timer thread stack size */ + TX_TIMER_THREAD_PRIORITY 0 /* Timer thread priority */ + TX_MAX_PRIORITIES 32 /* Must be multiple of 32 */ + +These can be overridden in tx_user.h or on the compiler command line. + + +8. Build Configuration + +CMake Toolchain File: example_build/smartl_fpga/xuantie_e906_gnu.cmake + +Compiler Flags: + -mcpu=e906fdp RISC-V RV32IMA[F][D]C[P] + -mcmodel=medlow ±2GB addressability + -D__ASSEMBLER__ For assembly files + + +9. File Organization + +Port-specific files (ports/risc-v64/gnu/): + +Core assembly files (src/): + - tx_port.c Initial setup and system state, Build initial stack frame for new thread + - tx_thread_context.S Thread context switch by software interrupt + - tx_thread_schedule.S Fist Thread scheduler + - tx_thread_system_return.S Trigger a software interrupt for voluntary yield + - tx_thread_interrupt_control.S Interrupt enable/disable control + - tx_timer_interrupt.S Timer interrupt handler + +Header file (inc/): + - tx_port.h Port-specific defines and macros + +Example files (example_build/smartl_fpga/): + - components/chip_riscv_dummy/src/arch/e906fdp Startup code, Interrupt handlers + - components/chip_riscv_dummy/src/drivers The basic peripheral drivers for the platform + - components/chip_riscv_dummy/src/sys System initialization + - components/chip_riscv_dummy/gcc_flash_smartl.ld Linker script for QEMU smartl + - components/csi CPU core and peripheral API + - components/libc_threadx Minimum printf and malloc implementation + - boards/board_riscv_dummy/src Bsp initialization + - pre_main.c Call main function + - tx_user.h ThreadX user defines + - build_libthreadx.sh Build script + + +10. Linker Script Requirements + +The linker script must provide: + +1. Entry point: + ENTRY(Reset_Handler) + +2. Memory layout: + - .text section (code) + - .rodata section (read-only data) + - .data section (initialized data) + - .bss section (uninitialized data) + +3. Symbols: + - __data_start__, __data_end__: For data copy from Flash when executed in DRAM + - __bss_start__, __bss_end__: For zero initialization + - __heap_start, __heap_end: For ThreadX allocation memory + +4. Alignment: + - 4-byte alignment throughout + +11. Performance and Debugging + +Performance Optimization + +Build optimizations: +- Use -O2 or -O3 for production (example uses -O0 for debugging) +- Enable -Wl,--gc-sections to remove unused code +- Define TX_DISABLE_ERROR_CHECKING to remove parameter checks +- Consider -flto for link-time optimization + +Debugging with QEMU and GDB + +Start QEMU in debug mode: + qemu-system-riscv32 -nographic -machine smartl -cpu e906fdp -kernel demo_threadx.elf -s -S + + -s: Enable GDB server on TCP port 1234 + -S: Pause at startup waiting for GDB + +Connect GDB: + riscv64-unknown-elf-gdb demo_threadx.elf + (gdb) target remote :1234 + (gdb) break main + (gdb) continue + +Useful GDB commands: + (gdb) info registers # View general registers + (gdb) info all-registers # Include CSR and FP registers + (gdb) p/x $mstatus # View machine status register + (gdb) x/32gx $sp # Examine stack memory + (gdb) p *_tx_thread_current_ptr # View current thread control block + + +12. Platform-Specific Notes (QEMU smartl) +See https://www.xrvm.com/soft-tools/tools/QEMU + +Timer frequency is platform-dependent (example uses 100MHz). + + +13. Revision History + +For generic code revision information, refer to ports/risc-v64/gnu/readme_threadx.txt. + +The following details the revision history for this xuantie/e906 GNU port: + +12-02-2026 Steven Lin Support XuanTie E906 + +01-26-2026 Akif Ejaz Comprehensive rewrite with accurate + technical details matching implementation, + register naming per RISC-V ABI, and + complete interrupt flow documentation + +03-08-2023 Scott Larson Initial Version 6.2.1 + + +Copyright (c) 1996-2026 Microsoft Corporation + +https://azure.com/rtos diff --git a/ports/xuantie/e906/gnu/src/tx_port.c b/ports/xuantie/e906/gnu/src/tx_port.c new file mode 100644 index 00000000..1fee892a --- /dev/null +++ b/ports/xuantie/e906/gnu/src/tx_port.c @@ -0,0 +1,110 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "tx_api.h" +#include "tx_timer.h" +#include "tx_thread.h" +#include "tx_initialize.h" + +void thread_switch_ext(void) +{ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + _tx_execution_thread_exit(); +#endif + + if(!_tx_thread_execute_ptr) { + unsigned long mcause; + __asm__ volatile( + "csrr %0, mcause\n\t" + "csrsi mstatus, 0x8" + : "=r"(mcause) + : + : "memory" + ); + while (!_tx_thread_execute_ptr) { + __asm__ volatile("wfi"); + } + __asm__ volatile( + "csrci mstatus, 0x8\n\t" + "csrw mcause, %0" + : + : "r"(mcause) + : "memory" + ); + } + /* Determine if the time-slice is active. */ + if (_tx_timer_time_slice && _tx_thread_current_ptr) { + /* Preserve current remaining time-slice for the thread and clear the current time-slice. */ + _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; + } + _tx_thread_current_ptr = _tx_thread_execute_ptr; +} + +VOID _tx_initialize_low_level(VOID) +{ + _tx_initialize_unused_memory = NULL; + _tx_thread_interrupt_control(0); +} + +VOID _tx_thread_exit(VOID) +{ + while (1) { + __asm__ volatile("wfi"); + } +} + +VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +{ + int i; + uint8_t *stk; + tx_stack_frame_t *frame; + + stk = thread_ptr -> tx_thread_stack_end; + stk = (uint8_t *)(((unsigned long)stk) & (~(unsigned long)(sizeof(ALIGN_TYPE) - 1))); + stk -= sizeof(tx_stack_frame_t); + + frame = (tx_stack_frame_t *)stk; + + for (i = 0; i < sizeof(tx_stack_frame_t) / sizeof(unsigned long); i++) { + ((unsigned long*)frame)[i] = 0; + } + + frame->epc = (unsigned long)function_ptr; + frame->ra = (unsigned long)_tx_thread_exit; + frame->mstatus = (3UL << 11) | (1UL << 7); // mstatus.MPP=3, MPIE=1 + +#if __riscv_flen + frame->mstatus |= (1UL << 13); // mstatus.FS=1 + stk -= sizeof(tx_stack_f_frame_t); + tx_stack_f_frame_t *f_frame = (tx_stack_f_frame_t *)stk; + f_frame->fcsr = 0; + for (int i = 0; i < 32; i++) { + f_frame->f[i] = 0; + } +#endif + +#if __riscv_dsp + stk -= sizeof(tx_stack_p_frame_t); + tx_stack_p_frame_t *p_frame = (tx_stack_p_frame_t *)stk; + p_frame->vxsat = 0; +#endif + + thread_ptr -> tx_thread_stack_ptr = stk; +} + diff --git a/ports/xuantie/e906/gnu/src/tx_thread_context.S b/ports/xuantie/e906/gnu/src/tx_thread_context.S new file mode 100644 index 00000000..220520bb --- /dev/null +++ b/ports/xuantie/e906/gnu/src/tx_thread_context.S @@ -0,0 +1,283 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +.section .text + + .align 3 + .global tspend_handler + .type tspend_handler, @function +tspend_handler: + addi sp, sp, -(30 * 4) + sw x1, 1 * 4(sp) /* RA */ + sw x5, 2 * 4(sp) + sw x6, 3 * 4(sp) + sw x7, 4 * 4(sp) + sw x8, 5 * 4(sp) + sw x9, 6 * 4(sp) + sw x10, 7 * 4(sp) + sw x11, 8 * 4(sp) + sw x12, 9 * 4(sp) + sw x13, 10 * 4(sp) + sw x14, 11 * 4(sp) + sw x15, 12 * 4(sp) + sw x16, 13 * 4(sp) + sw x17, 14 * 4(sp) + sw x18, 15 * 4(sp) + sw x19, 16 * 4(sp) + sw x20, 17 * 4(sp) + sw x21, 18 * 4(sp) + sw x22, 19 * 4(sp) + sw x23, 20 * 4(sp) + sw x24, 21 * 4(sp) + sw x25, 22 * 4(sp) + sw x26, 23 * 4(sp) + sw x27, 24 * 4(sp) + sw x28, 25 * 4(sp) + sw x29, 26 * 4(sp) + sw x30, 27 * 4(sp) + sw x31, 28 * 4(sp) + + csrr t0, mepc + sw t0, 0(sp) + + csrr t3, mstatus + sw t3, 29 * 4(sp) + +#if __riscv_flen + addi sp, sp, -4 + frcsr t0 + sw t0, 0(sp) +#if __riscv_float_abi_single + addi sp, sp, -(32 * 4) + fsw f0, 0 * 4(sp) + fsw f1, 1 * 4(sp) + fsw f2, 2 * 4(sp) + fsw f3, 3 * 4(sp) + fsw f4, 4 * 4(sp) + fsw f5, 5 * 4(sp) + fsw f6, 6 * 4(sp) + fsw f7, 7 * 4(sp) + fsw f8, 8 * 4(sp) + fsw f9, 9 * 4(sp) + fsw f10, 10 * 4(sp) + fsw f11, 11 * 4(sp) + fsw f12, 12 * 4(sp) + fsw f13, 13 * 4(sp) + fsw f14, 14 * 4(sp) + fsw f15, 15 * 4(sp) + fsw f16, 16 * 4(sp) + fsw f17, 17 * 4(sp) + fsw f18, 18 * 4(sp) + fsw f19, 19 * 4(sp) + fsw f20, 20 * 4(sp) + fsw f21, 21 * 4(sp) + fsw f22, 22 * 4(sp) + fsw f23, 23 * 4(sp) + fsw f24, 24 * 4(sp) + fsw f25, 25 * 4(sp) + fsw f26, 26 * 4(sp) + fsw f27, 27 * 4(sp) + fsw f28, 28 * 4(sp) + fsw f29, 29 * 4(sp) + fsw f30, 30 * 4(sp) + fsw f31, 31 * 4(sp) +#elif __riscv_float_abi_double + addi sp, sp, -(32 * 8) + fsw f0, 0 * 8(sp) + fsw f1, 1 * 8(sp) + fsw f2, 2 * 8(sp) + fsw f3, 3 * 8(sp) + fsw f4, 4 * 8(sp) + fsw f5, 5 * 8(sp) + fsw f6, 6 * 8(sp) + fsw f7, 7 * 8(sp) + fsw f8, 8 * 8(sp) + fsw f9, 9 * 8(sp) + fsw f10, 10 * 8(sp) + fsw f11, 11 * 8(sp) + fsw f12, 12 * 8(sp) + fsw f13, 13 * 8(sp) + fsw f14, 14 * 8(sp) + fsw f15, 15 * 8(sp) + fsw f16, 16 * 8(sp) + fsw f17, 17 * 8(sp) + fsw f18, 18 * 8(sp) + fsw f19, 19 * 8(sp) + fsw f20, 20 * 8(sp) + fsw f21, 21 * 8(sp) + fsw f22, 22 * 8(sp) + fsw f23, 23 * 8(sp) + fsw f24, 24 * 8(sp) + fsw f25, 25 * 8(sp) + fsw f26, 26 * 8(sp) + fsw f27, 27 * 8(sp) + fsw f28, 28 * 8(sp) + fsw f29, 29 * 8(sp) + fsw f30, 30 * 8(sp) + fsw f31, 31 * 8(sp) +#endif +#endif /* __riscv_flen */ + +#if __riscv_dsp + addi sp, sp, -4 + csrr t0, vxsat + sw t0, 0(sp) +#endif /*__riscv_dsp */ + + /* If _tx_thread_current_ptr is null, no sp need to be saved */ + la t0, _tx_thread_current_ptr + lw t0, 0(t0) + beqz t0, _tx_thread_switch + /* Store sp to task stack to _tx_thread_current_ptr -> tx_thread_stack_ptr */ + sw sp, 2 * 4(t0) + +_tx_thread_switch: + jal thread_switch_ext + /*clear software interrupt*/ + /* Edge-triggered vector interrupts do not require software to clear the pending bit. */ + + /* Switch task context to _tx_thread_execute_ptr */ + la t0, _tx_thread_execute_ptr + lw t0, 0(t0) + lw sp, 2 * 4(t0) + + /* Pop additional registers */ +#if __riscv_dsp + lw t0, 0(sp) + csrw vxsat, t0 + addi sp, sp, 4 +#endif /*__riscv_dsp */ + +#if __riscv_flen +#if __riscv_float_abi_single + flw f0, 0 * 4(sp) + flw f1, 1 * 4(sp) + flw f2, 2 * 4(sp) + flw f3, 3 * 4(sp) + flw f4, 4 * 4(sp) + flw f5, 5 * 4(sp) + flw f6, 6 * 4(sp) + flw f7, 7 * 4(sp) + flw f8, 8 * 4(sp) + flw f9, 9 * 4(sp) + flw f10, 10 * 4(sp) + flw f11, 11 * 4(sp) + flw f12, 12 * 4(sp) + flw f13, 13 * 4(sp) + flw f14, 14 * 4(sp) + flw f15, 15 * 4(sp) + flw f16, 16 * 4(sp) + flw f17, 17 * 4(sp) + flw f18, 18 * 4(sp) + flw f19, 19 * 4(sp) + flw f20, 20 * 4(sp) + flw f21, 21 * 4(sp) + flw f22, 22 * 4(sp) + flw f23, 23 * 4(sp) + flw f24, 24 * 4(sp) + flw f25, 25 * 4(sp) + flw f26, 26 * 4(sp) + flw f27, 27 * 4(sp) + flw f28, 28 * 4(sp) + flw f29, 29 * 4(sp) + flw f30, 30 * 4(sp) + flw f31, 31 * 4(sp) + addi sp, sp, (32 * 4) +#elif __riscv_float_abi_double + flw f0, 0 * 8(sp) + flw f1, 1 * 8(sp) + flw f2, 2 * 8(sp) + flw f3, 3 * 8(sp) + flw f4, 4 * 8(sp) + flw f5, 5 * 8(sp) + flw f6, 6 * 8(sp) + flw f7, 7 * 8(sp) + flw f8, 8 * 8(sp) + flw f9, 9 * 8(sp) + flw f10, 10 * 8(sp) + flw f11, 11 * 8(sp) + flw f12, 12 * 8(sp) + flw f13, 13 * 8(sp) + flw f14, 14 * 8(sp) + flw f15, 15 * 8(sp) + flw f16, 16 * 8(sp) + flw f17, 17 * 8(sp) + flw f18, 18 * 8(sp) + flw f19, 19 * 8(sp) + flw f20, 20 * 8(sp) + flw f21, 21 * 8(sp) + flw f22, 22 * 8(sp) + flw f23, 23 * 8(sp) + flw f24, 24 * 8(sp) + flw f25, 25 * 8(sp) + flw f26, 26 * 8(sp) + flw f27, 27 * 8(sp) + flw f28, 28 * 8(sp) + flw f29, 29 * 8(sp) + flw f30, 30 * 8(sp) + flw f31, 31 * 8(sp) + addi sp, sp, (32 * 8) +#endif + + lw t0, 0(sp) + fscsr t0 + addi sp, sp, 4 +#endif /* __riscv_flen */ + + /* Pop PC from stack and set MEPC */ + lw t0, 0 * 4(sp) + csrw mepc, t0 + + /* Pop mstatus from stack and set it */ + lw t0, 29 * 4(sp) + csrw mstatus, t0 + + /* Interrupt still disable here */ + /* Restore Registers from Stack */ + lw x1, 1 * 4(sp) /* RA */ + lw x5, 2 * 4(sp) + lw x6, 3 * 4(sp) + lw x7, 4 * 4(sp) + lw x8, 5 * 4(sp) + lw x9, 6 * 4(sp) + lw x10, 7 * 4(sp) + lw x11, 8 * 4(sp) + lw x12, 9 * 4(sp) + lw x13, 10 * 4(sp) + lw x14, 11 * 4(sp) + lw x15, 12 * 4(sp) + lw x16, 13 * 4(sp) + lw x17, 14 * 4(sp) + lw x18, 15 * 4(sp) + lw x19, 16 * 4(sp) + lw x20, 17 * 4(sp) + lw x21, 18 * 4(sp) + lw x22, 19 * 4(sp) + lw x23, 20 * 4(sp) + lw x24, 21 * 4(sp) + lw x25, 22 * 4(sp) + lw x26, 23 * 4(sp) + lw x27, 24 * 4(sp) + lw x28, 25 * 4(sp) + lw x29, 26 * 4(sp) + lw x30, 27 * 4(sp) + lw x31, 28 * 4(sp) + addi sp, sp, (30 * 4) + + mret + + .size tspend_handler, . - tspend_handler diff --git a/ports/xuantie/e906/gnu/src/tx_thread_interrupt_control.S b/ports/xuantie/e906/gnu/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..f5b538e8 --- /dev/null +++ b/ports/xuantie/e906/gnu/src/tx_thread_interrupt_control.S @@ -0,0 +1,83 @@ +/*************************************************************************** + * Copyright (c) 2024 Microsoft Corporation + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control RISC-V64/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_control(UINT new_posture) +{ */ + .global _tx_thread_interrupt_control +_tx_thread_interrupt_control: + /* Pickup current interrupt lockout posture. */ + /* old_mstatus = mstatus; */ + + csrr t0, mstatus + mv t1, t0 // Save original mstatus for return + + /* Apply the new interrupt posture while preserving unrelated mstatus bits. */ + /* Only modify the MIE bit (bit 3) */ + /* mstatus = (mstatus & ~MIE) | (new_posture & MIE); */ + + li t2, ~0x08 // Build mask to clear MIE + and t0, t0, t2 // Clear MIE bit + and a0, a0, 0x08 // Mask incoming to only MIE bit + or t0, t0, a0 // Set requested MIE state + csrw mstatus, t0 + andi a0, t1, 0x08 // Return original MIE bit + ret +/* } */ diff --git a/ports/xuantie/e906/gnu/src/tx_thread_schedule.S b/ports/xuantie/e906/gnu/src/tx_thread_schedule.S new file mode 100644 index 00000000..09d67ec2 --- /dev/null +++ b/ports/xuantie/e906/gnu/src/tx_thread_schedule.S @@ -0,0 +1,234 @@ +/*************************************************************************** + * Copyright (c) 2024 Microsoft Corporation + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule RISC-V64/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_schedule(VOID) +{ */ + .align 3 + .global _tx_thread_schedule + .type _tx_thread_schedule, @function +_tx_thread_schedule: + /* Enable interrupts. */ + csrsi mstatus, 0x08 // Enable interrupts + + /* Wait for a thread to execute. */ + /* do + { */ + la t0, _tx_thread_execute_ptr // Pickup address of execute ptr +_tx_thread_schedule_loop: + lw t1, 0(t0) // Pickup next thread to execute + beqz t1, _tx_thread_schedule_loop // If NULL, wait for thread to execute + /* } + while(_tx_thread_execute_ptr == TX_NULL); */ + + /* Yes! We have a thread to execute. Lockout interrupts and + transfer control to it. */ + csrci mstatus, 0x08 // Lockout interrupts + + /* Setup the current thread pointer. */ + /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ + la t0, _tx_thread_current_ptr // Pickup current thread pointer address + sw t1, 0(t0) // Set current thread pointer + + /* Increment the run count for this thread. */ + /* _tx_thread_current_ptr -> tx_thread_run_count++; */ + lw t2, 1 * 4(t1) // Pickup run count + lw t3, 6 * 4(t1) // Pickup time slice value + addi t2, t2, 1 // Increment run count + sw t2, 1 * 4(t1) // Store new run count + + /* Setup time-slice, if present. */ + /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ + la t2, _tx_timer_time_slice // Pickup time-slice variable address + + /* Switch to the thread's stack. */ + /* SP = _tx_thread_execute_ptr -> tx_thread_stack_ptr; */ + lw sp, 2 * 4(t1) // Switch to thread's stack + sw t3, 0(t2) // Store new time-slice*/ + +#if __riscv_dsp + lw t0, 0(sp) + csrw vxsat, t0 + addi sp, sp, 4 +#endif /*__riscv_dsp */ + +#if __riscv_flen +#if __riscv_float_abi_single + flw f0, 0 * 4(sp) + flw f1, 1 * 4(sp) + flw f2, 2 * 4(sp) + flw f3, 3 * 4(sp) + flw f4, 4 * 4(sp) + flw f5, 5 * 4(sp) + flw f6, 6 * 4(sp) + flw f7, 7 * 4(sp) + flw f8, 8 * 4(sp) + flw f9, 9 * 4(sp) + flw f10, 10 * 4(sp) + flw f11, 11 * 4(sp) + flw f12, 12 * 4(sp) + flw f13, 13 * 4(sp) + flw f14, 14 * 4(sp) + flw f15, 15 * 4(sp) + flw f16, 16 * 4(sp) + flw f17, 17 * 4(sp) + flw f18, 18 * 4(sp) + flw f19, 19 * 4(sp) + flw f20, 20 * 4(sp) + flw f21, 21 * 4(sp) + flw f22, 22 * 4(sp) + flw f23, 23 * 4(sp) + flw f24, 24 * 4(sp) + flw f25, 25 * 4(sp) + flw f26, 26 * 4(sp) + flw f27, 27 * 4(sp) + flw f28, 28 * 4(sp) + flw f29, 29 * 4(sp) + flw f30, 30 * 4(sp) + flw f31, 31 * 4(sp) + addi sp, sp, (32 * 4) +#elif __riscv_float_abi_double + flw f0, 0 * 8(sp) + flw f1, 1 * 8(sp) + flw f2, 2 * 8(sp) + flw f3, 3 * 8(sp) + flw f4, 4 * 8(sp) + flw f5, 5 * 8(sp) + flw f6, 6 * 8(sp) + flw f7, 7 * 8(sp) + flw f8, 8 * 8(sp) + flw f9, 9 * 8(sp) + flw f10, 10 * 8(sp) + flw f11, 11 * 8(sp) + flw f12, 12 * 8(sp) + flw f13, 13 * 8(sp) + flw f14, 14 * 8(sp) + flw f15, 15 * 8(sp) + flw f16, 16 * 8(sp) + flw f17, 17 * 8(sp) + flw f18, 18 * 8(sp) + flw f19, 19 * 8(sp) + flw f20, 20 * 8(sp) + flw f21, 21 * 8(sp) + flw f22, 22 * 8(sp) + flw f23, 23 * 8(sp) + flw f24, 24 * 8(sp) + flw f25, 25 * 8(sp) + flw f26, 26 * 8(sp) + flw f27, 27 * 8(sp) + flw f28, 28 * 8(sp) + flw f29, 29 * 8(sp) + flw f30, 30 * 8(sp) + flw f31, 31 * 8(sp) + addi sp, sp, (32 * 8) +#endif + + lw t0, 0(sp) + fscsr t0 + addi sp, sp, 4 +#endif /* __riscv_flen */ + + /* Pop PC from stack and set MEPC */ + lw t0, 0 * 4(sp) + csrw mepc, t0 + + /* Pop mstatus from stack and set it */ + lw t0, 29 * 4(sp) + csrw mstatus, t0 + + /* Interrupt still disable here */ + /* Restore Registers from Stack */ + lw x1, 1 * 4(sp) /* RA */ + lw x5, 2 * 4(sp) + lw x6, 3 * 4(sp) + lw x7, 4 * 4(sp) + lw x8, 5 * 4(sp) + lw x9, 6 * 4(sp) + lw x10, 7 * 4(sp) + lw x11, 8 * 4(sp) + lw x12, 9 * 4(sp) + lw x13, 10 * 4(sp) + lw x14, 11 * 4(sp) + lw x15, 12 * 4(sp) + lw x16, 13 * 4(sp) + lw x17, 14 * 4(sp) + lw x18, 15 * 4(sp) + lw x19, 16 * 4(sp) + lw x20, 17 * 4(sp) + lw x21, 18 * 4(sp) + lw x22, 19 * 4(sp) + lw x23, 20 * 4(sp) + lw x24, 21 * 4(sp) + lw x25, 22 * 4(sp) + lw x26, 23 * 4(sp) + lw x27, 24 * 4(sp) + lw x28, 25 * 4(sp) + lw x29, 26 * 4(sp) + lw x30, 27 * 4(sp) + lw x31, 28 * 4(sp) + addi sp, sp, (30 * 4) + + mret + + .size _tx_thread_schedule, . - _tx_thread_schedule + +/* } */ diff --git a/ports/xuantie/e906/gnu/src/tx_thread_system_return.S b/ports/xuantie/e906/gnu/src/tx_thread_system_return.S new file mode 100644 index 00000000..598bc283 --- /dev/null +++ b/ports/xuantie/e906/gnu/src/tx_thread_system_return.S @@ -0,0 +1,78 @@ +/*************************************************************************** + * Copyright (c) 2024 Microsoft Corporation + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return RISC-V64/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the system. Only a minimal context */ +/* is saved since the compiler assumes temp registers are going to get */ +/* slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_system_return(VOID) +{ */ + .align 3 + .global _tx_thread_system_return + .type _tx_thread_system_return, @function +_tx_thread_system_return: + li t0, 0xE080100C + lb t1, (t0) + li t2, 0x01 + or t1, t1, t2 + sb t1, (t0) + + fence + ret + .size _tx_thread_system_return, . - _tx_thread_system_return + +/* } */ diff --git a/ports/xuantie/e906/gnu/src/tx_timer_interrupt.c b/ports/xuantie/e906/gnu/src/tx_timer_interrupt.c new file mode 100644 index 00000000..aea1119b --- /dev/null +++ b/ports/xuantie/e906/gnu/src/tx_timer_interrupt.c @@ -0,0 +1,125 @@ +/*************************************************************************** + * Copyright (c) 2024 Microsoft Corporation + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_timer.h" +#include "tx_thread.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt RISC-V64/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +VOID _tx_timer_interrupt(VOID) +{ + /* Increment system clock. */ + _tx_timer_system_clock++; + + /* Test for time-slice expiration. */ + if (_tx_timer_time_slice) + { + /* Decrement the time_slice. */ + _tx_timer_time_slice--; + /* Check for expiration. */ + if (_tx_timer_time_slice == 0) + { + /* Set the time-slice expired flag. */ + _tx_timer_expired_time_slice = TX_TRUE; + } + } + + /* Test for timer expiration. */ + if (*_tx_timer_current_ptr) + { + /* Set expiration flag. */ + _tx_timer_expired = TX_TRUE; + } + else + { + /* No timer expired, increment the timer pointer. */ + _tx_timer_current_ptr++; + /* Check for wrap-around. */ + if (_tx_timer_current_ptr == _tx_timer_list_end) + { + /* Wrap to beginning of list. */ + _tx_timer_current_ptr = _tx_timer_list_start; + } + } + + /* See if anything has expired. */ + if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + { + /* Did a timer expire? */ + if (_tx_timer_expired) + { + /* Process timer expiration. */ + _tx_timer_expiration_process(); + } + + /* Did time slice expire? */ + if (_tx_timer_expired_time_slice) + { + /* Time slice interrupted thread. */ + _tx_thread_time_slice(); + } + } +} From c1bff3ae3488cb647b982b8bce769a32dc28e296 Mon Sep 17 00:00:00 2001 From: Akif Ejaz Date: Mon, 16 Feb 2026 13:57:51 +0500 Subject: [PATCH 08/19] removed dead code in riscv64/gnu port Signed-off-by: Akif Ejaz --- ports/risc-v64/gnu/inc/tx_port.h | 11 +++ .../risc-v64/gnu/src/tx_thread_context_save.S | 78 ------------------- 2 files changed, 11 insertions(+), 78 deletions(-) diff --git a/ports/risc-v64/gnu/inc/tx_port.h b/ports/risc-v64/gnu/inc/tx_port.h index d2385358..ed985072 100644 --- a/ports/risc-v64/gnu/inc/tx_port.h +++ b/ports/risc-v64/gnu/inc/tx_port.h @@ -53,6 +53,8 @@ #ifndef TX_PORT_H #define TX_PORT_H +#ifndef __ASSEMBLER__ + /* Include for memset. */ #include @@ -68,10 +70,14 @@ #include "tx_user.h" #endif /* TX_INCLUDE_USER_DEFINE_FILE */ +#endif /* __ASSEMBLER__ */ + /* Define ThreadX basic types for this port. */ #define VOID void + +#ifndef __ASSEMBLER__ typedef char CHAR; typedef unsigned char UCHAR; typedef int INT; @@ -82,6 +88,7 @@ typedef unsigned long long ULONG64; typedef short SHORT; typedef unsigned short USHORT; #define ULONG64_DEFINED +#endif /* __ASSEMBLER__ */ @@ -230,7 +237,9 @@ typedef unsigned short USHORT; /* Expose helper used to perform an atomic read/modify/write of mstatus. The helper composes and returns the posture per ThreadX contract. */ +#ifndef __ASSEMBLER__ UINT _tx_thread_interrupt_control(UINT new_posture); +#endif #ifdef TX_DISABLE_INLINE @@ -270,11 +279,13 @@ UINT _tx_thread_interrupt_control(UIN /* Define the version ID of ThreadX. This may be utilized by the application. */ +#ifndef __ASSEMBLER__ #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = "Copyright (c) 2024 Microsoft Corporation. * ThreadX RISC-V64/GNU Version 6.4.2 *"; #else extern CHAR _tx_version_id[]; #endif /* TX_THREAD_INIT */ +#endif /* __ASSEMBLER__ */ #endif /* TX_PORT_H */ diff --git a/ports/risc-v64/gnu/src/tx_thread_context_save.S b/ports/risc-v64/gnu/src/tx_thread_context_save.S index 641c7793..b9aa13c9 100644 --- a/ports/risc-v64/gnu/src/tx_thread_context_save.S +++ b/ports/risc-v64/gnu/src/tx_thread_context_save.S @@ -260,84 +260,6 @@ _tx_thread_not_nested_save: ld sp, 0(t0) // Switch to system stack ret // Return to calling ISR - sd x17, 20*8(sp) // Store a7 - sd x28, 16*8(sp) // Store t3 - sd x29, 15*8(sp) // Store t4 - sd x30, 14*8(sp) // Store t5 - sd x31, 13*8(sp) // Store t6 - - csrr t0, mepc // Load exception program counter - sd t0, 30*8(sp) // Save it on the stack - - /* Save floating point scratch registers. */ -#if defined(__riscv_float_abi_single) - fsw f0, 31*8(sp) // Store ft0 - fsw f1, 32*8(sp) // Store ft1 - fsw f2, 33*8(sp) // Store ft2 - fsw f3, 34*8(sp) // Store ft3 - fsw f4, 35*8(sp) // Store ft4 - fsw f5, 36*8(sp) // Store ft5 - fsw f6, 37*8(sp) // Store ft6 - fsw f7, 38*8(sp) // Store ft7 - fsw f10,41*8(sp) // Store fa0 - fsw f11,42*8(sp) // Store fa1 - fsw f12,43*8(sp) // Store fa2 - fsw f13,44*8(sp) // Store fa3 - fsw f14,45*8(sp) // Store fa4 - fsw f15,46*8(sp) // Store fa5 - fsw f16,47*8(sp) // Store fa6 - fsw f17,48*8(sp) // Store fa7 - fsw f28,59*8(sp) // Store ft8 - fsw f29,60*8(sp) // Store ft9 - fsw f30,61*8(sp) // Store ft10 - fsw f31,62*8(sp) // Store ft11 - csrr t0, fcsr - sd t0, 63*8(sp) // Store fcsr -#elif defined(__riscv_float_abi_double) - fsd f0, 31*8(sp) // Store ft0 - fsd f1, 32*8(sp) // Store ft1 - fsd f2, 33*8(sp) // Store ft2 - fsd f3, 34*8(sp) // Store ft3 - fsd f4, 35*8(sp) // Store ft4 - fsd f5, 36*8(sp) // Store ft5 - fsd f6, 37*8(sp) // Store ft6 - fsd f7, 38*8(sp) // Store ft7 - fsd f10,41*8(sp) // Store fa0 - fsd f11,42*8(sp) // Store fa1 - fsd f12,43*8(sp) // Store fa2 - fsd f13,44*8(sp) // Store fa3 - fsd f14,45*8(sp) // Store fa4 - fsd f15,46*8(sp) // Store fa5 - fsd f16,47*8(sp) // Store fa6 - fsd f17,48*8(sp) // Store fa7 - fsd f28,59*8(sp) // Store ft8 - fsd f29,60*8(sp) // Store ft9 - fsd f30,61*8(sp) // Store ft10 - fsd f31,62*8(sp) // Store ft11 - csrr t0, fcsr - sd t0, 63*8(sp) // Store fcsr -#endif - - /* Save the current stack pointer in the thread's control block. */ - /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ - - /* Switch to the system stack. */ - /* sp = _tx_thread_system_stack_ptr; */ - - la x5, _tx_thread_current_ptr // Pickup current thread pointer address - ld t1, 0(x5) // Pickup current thread pointer - sd sp, 16(t1) // Save stack pointer - -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - /* _tx_execution_isr_enter is called with thread stack pointer */ - call _tx_execution_isr_enter // Call the ISR execution enter function -#endif - - - la x5, _tx_thread_system_stack_ptr // Pickup system stack pointer address - ld sp, 0(x5) // Switch to system stack - ret // Return to calling ISR - /* } else { */ From 757db54d6d10edc655eee9cfe02ecd4d93be5fed Mon Sep 17 00:00:00 2001 From: Akif Ejaz Date: Mon, 16 Feb 2026 17:15:13 +0500 Subject: [PATCH 09/19] Add RISC-V32 arch. port layer This update adapts the ThreadX low-level kernel routines for RV32, including: - startup and initialization logic - context save/restore implementations - interrupt control and scheduler entry - thread stack build and system return paths - timer interrupt handling - made it complient as per new risc-v64/gnu & threadx style - added reademe for risc-v32/gnu port These changes provide full low-level support needed to run ThreadX on RISC-V32 targets. Signed-off-by: Akif Ejaz --- cmake/riscv32-unknown-elf.cmake | 29 ++ cmake/riscv32_gnu.cmake | 12 + ports/risc-v32/gnu/CMakeLists.txt | 19 + ports/risc-v32/gnu/inc/tx_port.h | 291 ++++++++++++ ports/risc-v32/gnu/readme_threadx.txt | 432 ++++++++++++++++++ .../gnu/src/tx_initialize_low_level.S | 118 +++++ .../gnu/src/tx_thread_context_restore.S | 416 +++++++++++++++++ .../risc-v32/gnu/src/tx_thread_context_save.S | 277 +++++++++++ .../gnu/src/tx_thread_interrupt_control.S | 94 ++++ ports/risc-v32/gnu/src/tx_thread_schedule.S | 324 +++++++++++++ .../risc-v32/gnu/src/tx_thread_stack_build.S | 227 +++++++++ .../gnu/src/tx_thread_system_return.S | 174 +++++++ ports/risc-v32/gnu/src/tx_timer_interrupt.S | 210 +++++++++ 13 files changed, 2623 insertions(+) create mode 100644 cmake/riscv32-unknown-elf.cmake create mode 100644 cmake/riscv32_gnu.cmake create mode 100644 ports/risc-v32/gnu/CMakeLists.txt create mode 100644 ports/risc-v32/gnu/inc/tx_port.h create mode 100644 ports/risc-v32/gnu/readme_threadx.txt create mode 100644 ports/risc-v32/gnu/src/tx_initialize_low_level.S create mode 100644 ports/risc-v32/gnu/src/tx_thread_context_restore.S create mode 100644 ports/risc-v32/gnu/src/tx_thread_context_save.S create mode 100644 ports/risc-v32/gnu/src/tx_thread_interrupt_control.S create mode 100644 ports/risc-v32/gnu/src/tx_thread_schedule.S create mode 100644 ports/risc-v32/gnu/src/tx_thread_stack_build.S create mode 100644 ports/risc-v32/gnu/src/tx_thread_system_return.S create mode 100644 ports/risc-v32/gnu/src/tx_timer_interrupt.S diff --git a/cmake/riscv32-unknown-elf.cmake b/cmake/riscv32-unknown-elf.cmake new file mode 100644 index 00000000..cfd9f7ea --- /dev/null +++ b/cmake/riscv32-unknown-elf.cmake @@ -0,0 +1,29 @@ +# Toolchain settings +set(CMAKE_C_COMPILER riscv32-unknown-elf-gcc) +set(CMAKE_CXX_COMPILER riscv32-unknown-elf-g++) +set(AS riscv32-unknown-elf-as) +set(AR riscv32-unknown-elf-ar) +set(OBJCOPY riscv32-unknown-elf-objcopy) +set(OBJDUMP riscv32-unknown-elf-objdump) +set(SIZE riscv32-unknown-elf-size) + +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY) + +# this makes the test compiles use static library option so that we don't need to pre-set linker flags and scripts +set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) + +set(CMAKE_C_FLAGS "${CFLAGS}" CACHE INTERNAL "c compiler flags") +set(CMAKE_CXX_FLAGS "${CXXFLAGS}" CACHE INTERNAL "cxx compiler flags") +set(CMAKE_ASM_FLAGS "${ASFLAGS} -D__ASSEMBLER__ -D__riscv_float_abi_single" CACHE INTERNAL "asm compiler flags") +set(CMAKE_EXE_LINKER_FLAGS "${LDFLAGS}" CACHE INTERNAL "exe link flags") + +SET(CMAKE_C_FLAGS_DEBUG "-Og -g -ggdb3" CACHE INTERNAL "c debug compiler flags") +SET(CMAKE_CXX_FLAGS_DEBUG "-Og -g -ggdb3" CACHE INTERNAL "cxx debug compiler flags") +SET(CMAKE_ASM_FLAGS_DEBUG "-g -ggdb3" CACHE INTERNAL "asm debug compiler flags") + +SET(CMAKE_C_FLAGS_RELEASE "-O3" CACHE INTERNAL "c release compiler flags") +SET(CMAKE_CXX_FLAGS_RELEASE "-O3" CACHE INTERNAL "cxx release compiler flags") +SET(CMAKE_ASM_FLAGS_RELEASE "" CACHE INTERNAL "asm release compiler flags") diff --git a/cmake/riscv32_gnu.cmake b/cmake/riscv32_gnu.cmake new file mode 100644 index 00000000..617b1276 --- /dev/null +++ b/cmake/riscv32_gnu.cmake @@ -0,0 +1,12 @@ +# Name of the target +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_PROCESSOR risc-v32) + +set(THREADX_ARCH "risc-v32") +set(THREADX_TOOLCHAIN "gnu") +set(ARCH_FLAGS "-g -march=rv32gc -mabi=ilp32d -mcmodel=medany") +set(CFLAGS "${ARCH_FLAGS}") +set(ASFLAGS "${ARCH_FLAGS}") +set(LDFLAGS "${ARCH_FLAGS}") + +include(${CMAKE_CURRENT_LIST_DIR}/riscv32-unknown-elf.cmake) diff --git a/ports/risc-v32/gnu/CMakeLists.txt b/ports/risc-v32/gnu/CMakeLists.txt new file mode 100644 index 00000000..9357c697 --- /dev/null +++ b/ports/risc-v32/gnu/CMakeLists.txt @@ -0,0 +1,19 @@ + +target_sources(${PROJECT_NAME} + PRIVATE + # {{BEGIN_TARGET_SOURCES}} + ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S + # {{END_TARGET_SOURCES}} +) + +target_include_directories(${PROJECT_NAME} + PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/inc +) diff --git a/ports/risc-v32/gnu/inc/tx_port.h b/ports/risc-v32/gnu/inc/tx_port.h new file mode 100644 index 00000000..f4dd75af --- /dev/null +++ b/ports/risc-v32/gnu/inc/tx_port.h @@ -0,0 +1,291 @@ +/*************************************************************************** + * Copyright (c) 2025 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h RISC-V32/GNU */ +/* 6.4.x */ +/* */ +/* AUTHOR */ +/* */ +/* Akif Ejaz, 10xEngineers */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + +#ifndef __ASSEMBLER__ + +/* Include for memset. */ +#include + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif /* TX_INCLUDE_USER_DEFINE_FILE */ + +#endif /* __ASSEMBLER__ */ + + +/* Define ThreadX basic types for this port. */ + +#define VOID void + +#ifndef __ASSEMBLER__ +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long long ULONG64; +typedef short SHORT; +typedef unsigned short USHORT; +#define ULONG64_DEFINED +#endif /* __ASSEMBLER__ */ + + + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 1024 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX RISC-V port. */ + +#define TX_INT_DISABLE 0x00000000 /* Disable interrupts value */ +#define TX_INT_ENABLE 0x00000008 /* Enable interrupt value */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +/* Expose helper used to perform an atomic read/modify/write of mstatus. + The helper composes and returns the posture per ThreadX contract. */ +#ifndef __ASSEMBLER__ +UINT _tx_thread_interrupt_control(UINT new_posture); +#endif + +#ifdef TX_DISABLE_INLINE + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE __asm__ volatile("csrrci %0, mstatus, 8" : "=r" (interrupt_save) :: "memory"); +#define TX_RESTORE { \ + unsigned long _temp_mstatus; \ + __asm__ volatile( \ + "csrc mstatus, 8\n" \ + "andi %0, %1, 8\n" \ + "csrs mstatus, %0" \ + : "=&r" (_temp_mstatus) \ + : "r" (interrupt_save) \ + : "memory"); \ + } + +#else + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); +#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); + +#endif /* TX_DISABLE_INLINE */ + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifndef __ASSEMBLER__ +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) 2024 Microsoft Corporation. * ThreadX RISC-V32/GNU Version 6.4.2 *"; +#else +extern CHAR _tx_version_id[]; +#endif /* TX_THREAD_INIT */ +#endif /* __ASSEMBLER__ */ + +#endif /* TX_PORT_H */ \ No newline at end of file diff --git a/ports/risc-v32/gnu/readme_threadx.txt b/ports/risc-v32/gnu/readme_threadx.txt new file mode 100644 index 00000000..e4f16971 --- /dev/null +++ b/ports/risc-v32/gnu/readme_threadx.txt @@ -0,0 +1,432 @@ + Eclipse Foundation's RTOS, ThreadX for RISC-V32 + + Using the GNU Tools + + +1. Building the ThreadX run-time Library + +Prerequisites +- Install a RISC-V32 bare-metal GNU toolchain with riscv32-unknown-elf prefix +- Common source: https://github.com/riscv-collab/riscv-gnu-toolchain + +Verify the toolchain: + riscv32-unknown-elf-gcc --version + riscv32-unknown-elf-objdump --version + +CMake-based build (recommended) + +From the ThreadX top-level directory: + + cmake -Bbuild -GNinja -DCMAKE_TOOLCHAIN_FILE=cmake/riscv32_gnu.cmake . + cmake --build ./build/ + +This uses cmake/riscv32_gnu.cmake and ports/risc-v32/gnu/CMakeLists.txt to +configure the cross-compiler flags and produce the ThreadX run-time library +and example binaries. + +Example build script + +The example demonstration contains a build script. See: + + ports/risc-v32/gnu/example_build/qemu_virt/build_libthreadx.sh + +This script builds the library and the demo application kernel.elf. + + +2. Demonstration System (QEMU) + +The provided example is targeted at QEMU's virt platform. After building the +example, the produced kernel.elf can be executed in QEMU: + + qemu-system-riscv32 -nographic -smp 1 -bios none -m 128M -machine virt -kernel kernel.elf + +Typical QEMU features used: +- Single-core CPU +- UART serial console +- PLIC (Platform-Level Interrupt Controller) +- CLINT (Core-Local Interruptor) for timer + + +3. System Initialization + +Entry Point + +The example startup code begins at the _start label in entry.s. This startup +code performs hardware initialization including: +- Check hart ID (only hart 0 continues; others enter WFI loop) +- Zero general-purpose registers +- Set up initial stack pointer +- Clear BSS section +- Jump to main() + +Low-Level Port Initialization (tx_initialize_low_level.S) + +The _tx_initialize_low_level function: +- Saves the system stack pointer to _tx_thread_system_stack_ptr +- Records first free RAM address from __tx_free_memory_start symbol +- Initializes floating-point control/status register (FCSR) if floating point enabled + +Board Initialization (board.c) + +After tx_initialize_low_level returns, main() calls board_init() to: +- Initialize PLIC (Platform-Level Interrupt Controller) +- Initialize UART +- Initialize hardware timer (CLINT) +- Set trap vector (mtvec) to point to trap handler + + +4. Register Usage and Stack Frames + +The RISC-V32 ABI defines t0-t6 and a0-a7 as caller-saved (scratch) registers. +All other registers used by a function must be preserved by the function. + +ThreadX takes advantage of this: when a context switch happens during a +function call, only the non-scratch registers need to be saved. + +Stack Frame Types + +Two types of stack frames exist: + +A. Interrupt Frame (stack type = 1) + Created when an interrupt occurs during thread execution. + Saves all registers including caller-saved registers. + Size: 65*4 = 260 bytes (with FP), or 32*4 = 128 bytes (without FP) + +B. Solicited Frame (stack type = 0) + Created when a thread voluntarily yields via ThreadX service calls. + Saves only callee-saved registers (s0-s11) and mstatus. + Size: 29*4 = 116 bytes (with FP), or 16*4 = 64 bytes (without FP) + + +Stack Layout for Interrupt Frame (with FP enabled): + + Index Offset Register Description + ───────────────────────────────────────────────── + 0 0x00 -- Stack type (1 = interrupt) + 1 0x04 s11 Preserved register + 2 0x08 s10 Preserved register + 3 0x0C s9 Preserved register + 4 0x10 s8 Preserved register + 5 0x14 s7 Preserved register + 6 0x18 s6 Preserved register + 7 0x1C s5 Preserved register + 8 0x20 s4 Preserved register + 9 0x24 s3 Preserved register + 10 0x28 s2 Preserved register + 11 0x2C s1 Preserved register + 12 0x30 s0 Preserved register + 13 0x34 t6 Scratch register + 14 0x38 t5 Scratch register + 15 0x3C t4 Scratch register + 16 0x40 t3 Scratch register + 17 0x44 t2 Scratch register + 18 0x48 t1 Scratch register + 19 0x4C t0 Scratch register + 20 0x50 a7 Argument register + 21 0x54 a6 Argument register + 22 0x58 a5 Argument register + 23 0x5C a4 Argument register + 24 0x60 a3 Argument register + 25 0x64 a2 Argument register + 26 0x68 a1 Argument register + 27 0x6C a0 Argument register + 28 0x70 ra Return address + 29 0x74 -- Reserved + 30 0x78 mepc Machine exception PC + 31-46 0x7C-0xB8 fs0-fs7 Preserved FP registers* + 47-62 0xBC-0xF8 ft0-ft11 Scratch FP registers* + 63 0xFC fcsr FP control/status register + ───────────────────────────────────────────────── + *Note: In ilp32d ABI, FP registers are 8 bytes each, but current + port implementation uses 4-byte indexing which may cause + overlap if fsd/fld are used. + + +5. Interrupt Handling + +Machine Mode Operation + +ThreadX operates in machine mode (M-mode), the highest privilege level. +All interrupts and exceptions trap to machine mode. + +Interrupt Sources + +1. Machine Timer Interrupt (MTI): + - Triggered by CLINT when mtime >= mtimecmp + - Handled by _tx_timer_interrupt (src/tx_timer_interrupt.S) + - Called from trap handler in trap.c + +2. External Interrupts (MEI): + - Routed through PLIC + - Handler in trap.c calls registered ISR callbacks + +3. Software Interrupts (MSI): + - Supported but not actively used in this port + +Interrupt Flow + +1. Hardware trap entry (automatic): + - mepc <- PC (address of interrupted instruction) + - mcause <- exception/interrupt code + - mstatus.MPIE <- mstatus.MIE (save interrupt-enable state) + - mstatus.MIE <- 0 (disable interrupts) + - mstatus.MPP <- Machine mode + - PC <- mtvec (points to trap_entry in entry.s) + +2. Trap entry (entry.s): + - Allocates interrupt stack frame (32*4 or 65*4 bytes depending on FP) + - Saves RA (x1) on stack + - Calls _tx_thread_context_save + +3. Context save (_tx_thread_context_save.S): + - Increments _tx_thread_system_state (nested interrupt counter) + - If nested interrupt: saves remaining registers and returns to ISR + - If first interrupt: saves full context, switches to system stack + +4. Trap handler (trap.c): + - Examines mcause to determine interrupt type + - Dispatches to appropriate handler (_tx_timer_interrupt or PLIC handler) + - Returns to context restore + +5. Context restore (_tx_thread_context_restore.S): + - Decrements _tx_thread_system_state + - Checks if preemption needed + - Restores thread context or switches to next ready thread via scheduler + - Returns to interrupted thread or executes new thread + + +Interrupt Control Macros + +TX_DISABLE and TX_RESTORE macros atomically manage the MIE bit in mstatus: + + TX_DISABLE: Saves and clears MIE bit via csrrci (CSR read-clear immediate) + TX_RESTORE: Restores only MIE bit via csrrs (CSR read-set) + Other mstatus bits remain unchanged + +These are defined in ports/risc-v32/gnu/inc/tx_port.h and use the +_tx_thread_interrupt_control() function. + + +6. Thread Scheduling and Context Switching + +Thread Scheduler (src/tx_thread_schedule.S) + +The scheduler: +1. Enables interrupts while waiting for next thread +2. Spins until _tx_thread_execute_ptr becomes non-NULL +3. Disables interrupts (critical section) +4. Sets _tx_thread_current_ptr = _tx_thread_execute_ptr +5. Increments thread's run count +6. Switches to thread's stack +7. Determines stack frame type and restores context: + - Interrupt frame: full context restored, returns via mret + - Solicited frame: minimal context restored, returns via ret + +Initial Thread Stack Frame (src/tx_thread_stack_build.S) + +New threads start with a fake interrupt frame containing: +- All registers initialized to 0 +- ra (x1) = 0 +- mepc = entry function pointer +- Stack type = 1 (interrupt frame) +- Floating-point registers initialized based on ABI + + +7. Port Configuration and Macros + +Default Configurations (in ports/risc-v32/gnu/inc/tx_port.h): + + TX_MINIMUM_STACK 1024 /* Minimum thread stack size */ + TX_TIMER_THREAD_STACK_SIZE 1024 /* Timer thread stack size */ + TX_TIMER_THREAD_PRIORITY 0 /* Timer thread priority */ + TX_MAX_PRIORITIES 32 /* Must be multiple of 32 */ + +These can be overridden in tx_user.h or on the compiler command line. + + +8. Build Configuration + +CMake Toolchain File: cmake/riscv32_gnu.cmake + +Compiler Flags: + -march=rv32gc RV32 with IMAFD+C extensions + -mabi=ilp32d 32-bit integers/pointers, double-precision FP in registers + -mcmodel=medany ±2GB addressability + -D__ASSEMBLER__ For assembly files + +ABI Selection + +The port uses ilp32d ABI which includes: +- 32-bit integers and pointers +- Double-precision floating-point arguments in registers +- Floating-point registers f0-f31 + +When building with floating-point ABI: +- FP registers and FCSR are saved/restored in context switches +- Stack frames expand from 32*REGBYTES to 65*REGBYTES +- Conditional compilation uses __riscv_float_abi_double / __riscv_float_abi_single + + +9. File Organization + +Port-specific files (ports/risc-v32/gnu/): + +Core assembly files (src/): + - tx_initialize_low_level.S Initial setup and system state + - tx_thread_context_save.S Save context on interrupt entry + - tx_thread_context_restore.S Restore context on interrupt exit + - tx_thread_schedule.S Thread scheduler + - tx_thread_system_return.S Solicited context save for voluntary yield + - tx_thread_stack_build.S Build initial stack frame for new thread + - tx_thread_interrupt_control.S Interrupt enable/disable control + - tx_timer_interrupt.S Timer interrupt handler + +Header file (inc/): + - tx_port.h Port-specific defines and macros + +Example files (example_build/qemu_virt/): + - entry.s Startup code, trap entry point + - board.c, uart.c, hwtimer.c Platform-specific initialization + - plic.c PLIC interrupt controller driver + - trap.c Trap/exception dispatcher + - link.lds Linker script for QEMU virt + - build_libthreadx.sh Build script + + +10. Linker Script Requirements + +The linker script must provide: + +1. Entry point: + ENTRY(_start) + +2. Memory layout: + - .text section (code) + - .rodata section (read-only data) + - .data section (initialized data) + - .bss section (uninitialized data) + +3. Symbols: + - _end: First free memory address (used by ThreadX allocation) + - _bss_start, _bss_end: For zero initialization + - Initial stack space (example: 4KB) + +4. Alignment: + - 16-byte alignment throughout (RISC-V requirement) + +Example from QEMU virt build: + + SECTIONS + { + . = 0x80000000; /* QEMU virt base address */ + + .text : { *(.text .text.*) } + .rodata : { *(.rodata .rodata.*) } + .data : { *(.data .data.*) } + .bss : { *(.bss .bss.*) } + + .stack : { + . = ALIGN(4096); + _sysstack_start = .; + . += 0x1000; /* 4KB initial stack */ + _sysstack_end = .; + } + + PROVIDE(_end = .); + } + + +11. Floating-Point Support + +When building with ilp32d ABI and FP enabled: + +- FP registers f0-f31 and FCSR are saved/restored during context switches +- Stack frames increase from 32*REGBYTES to 65*REGBYTES (128 to 260 bytes) +- MSTATUS.FS (floating-point state) field is set to indicate dirty FP state + +Stack frame differences: +- Without FP: 32*4 = 128 bytes (interrupt), 16*4 = 64 bytes (solicited) +- With FP: 65*4 = 260 bytes (interrupt), 29*4 = 116 bytes (solicited) + + +12. Performance and Debugging + +Performance Optimization + +Build optimizations: +- Use -O2 or -O3 for production (example uses -O0 for debugging) +- Enable -Wl,--gc-sections to remove unused code +- Define TX_DISABLE_ERROR_CHECKING to remove parameter checks +- Consider -flto for link-time optimization + +Debugging with QEMU and GDB + +Start QEMU in debug mode: + qemu-system-riscv32 -nographic -smp 1 -bios none -m 128M \ + -machine virt -kernel kernel.elf -s -S + + -s: Enable GDB server on TCP port 1234 + -S: Pause at startup waiting for GDB + +Connect GDB: + riscv32-unknown-elf-gdb kernel.elf + (gdb) target remote :1234 + (gdb) break main + (gdb) continue + +Useful GDB commands: + (gdb) info registers # View general registers + (gdb) info all-registers # Include CSR and FP registers + (gdb) p/x $mstatus # View machine status register + (gdb) x/32xw $sp # Examine stack memory + (gdb) p *_tx_thread_current_ptr # View current thread control block + + +13. Platform-Specific Notes (QEMU virt) + +PLIC Configuration + +The PLIC (Platform-Level Interrupt Controller) is memory-mapped at 0x0C000000: + +- Enables up to 1024 interrupt sources +- Supports priority levels 0-7 (0 = disabled) +- Requires per-hart priority threshold and enable register configuration + +Example PLIC usage (from plic.c): + plic_irq_enable(irq_number); # Enable specific interrupt + plic_prio_set(irq_number, priority);# Set priority level + +CLINT Configuration + +The CLINT (Core-Local Interruptor) is memory-mapped at 0x02000000: + +- CLINT_MSIP(hartid): 0x0000 + 4*hartid (software interrupt) +- CLINT_MTIMECMP(hartid): 0x4000 + 8*hartid (timer compare) +- CLINT_MTIME: 0xBFF8 (timer value, read-only) + +Timer frequency is platform-dependent (example uses 10MHz). + +Multi-Core Considerations + +The current port is single-core focused: +- Only hart 0 continues from reset; others enter WFI loop +- _tx_thread_system_state is a global variable +- No per-hart data structures + + +14. Revision History + +For generic code revision information, refer to readme_threadx_generic.txt. + +The following details the revision history for this RISC-V32 GNU port: + +01-26-2026 Akif Ejaz Brief rewrite with accurate + technical details matching implementation, + register naming per RISC-V ABI, and + complete interrupt flow documentation + (Adapted from RISC-V64 port) + + +Copyright (c) 1996-2026 Microsoft Corporation + +https://azure.com/rtos diff --git a/ports/risc-v32/gnu/src/tx_initialize_low_level.S b/ports/risc-v32/gnu/src/tx_initialize_low_level.S new file mode 100644 index 00000000..70fefc84 --- /dev/null +++ b/ports/risc-v32/gnu/src/tx_initialize_low_level.S @@ -0,0 +1,118 @@ +/*************************************************************************** + * Copyright (c) 2025 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .section .data + .global __tx_free_memory_start +__tx_free_memory_start: + + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level RISC-V32/GNU */ +/* 6.4.x */ +/* AUTHOR */ +/* */ +/* Akif Ejaz, 10xEngineers */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ + .global _tx_initialize_low_level + .weak _tx_initialize_low_level +_tx_initialize_low_level: + + /* Save the system stack pointer. */ + /* _tx_thread_system_stack_ptr = sp; */ + + la t0, _tx_thread_system_stack_ptr // Pickup address of system stack ptr + sw sp, 0(t0) // Save system stack pointer + + /* Pickup first free address. */ + /* _tx_initialize_unused_memory(__tx_free_memory_start); */ + + la t0, __tx_free_memory_start // Pickup first free address + la t1, _tx_initialize_unused_memory // Pickup address of unused memory + sw t0, 0(t1) // Save unused memory address + + /* Initialize floating point control/status register if floating point is enabled. */ +#ifdef __riscv_flen + li t0, 0 + csrw fcsr, t0 // Clear FP control/status register +#endif + + ret + +/* Timer Interrupt Handler Note: + Platform-specific implementations must provide their own timer ISR. + The timer interrupt handler should follow this execution flow: + + 1. Disable interrupts (if not done by hardware exception entry) + 2. Allocate interrupt stack frame (65*4 bytes with FP, 32*4 bytes without) + 3. Save RA (x1) on the stack at offset 28*4 + 4. Call _tx_thread_context_save to save thread context + 5. Call _tx_timer_interrupt to process the timer tick + 6. Call _tx_thread_context_restore to resume execution (does not return) + + Example (for CLINT timer): + + _tx_timer_interrupt_handler: + addi sp, sp, -32*4 + sw ra, 28*4(sp) + call _tx_thread_context_save + call _tx_timer_interrupt + j _tx_thread_context_restore + + The port assumes Machine mode (M-mode) execution. + For Supervisor mode (S-mode), use sstatus and SIE/SPIE instead of mstatus. + See the RISC-V Privileged Specification for more details. */ \ No newline at end of file diff --git a/ports/risc-v32/gnu/src/tx_thread_context_restore.S b/ports/risc-v32/gnu/src/tx_thread_context_restore.S new file mode 100644 index 00000000..ba553a46 --- /dev/null +++ b/ports/risc-v32/gnu/src/tx_thread_context_restore.S @@ -0,0 +1,416 @@ +/*************************************************************************** + * Copyright (c) 2025 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore RISC-V32/GNU */ +/* 6.4.x */ +/* AUTHOR */ +/* */ +/* Akif Ejaz, 10xEngineers */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_restore(VOID) +{ */ + .global _tx_thread_context_restore +_tx_thread_context_restore: + + /* Lockout interrupts. */ + + csrci mstatus, 0x08 // Disable interrupts (MIE bit 3) + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + call _tx_execution_isr_exit // Call the ISR execution exit function +#endif + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) + { */ + + la t0, _tx_thread_system_state // Pickup addr of nested interrupt count + lw t1, 0(t0) // Pickup nested interrupt count + addi t1, t1, -1 // Decrement the nested interrupt counter + sw t1, 0(t0) // Store new nested count + beqz t1, _tx_thread_not_nested_restore // If 0, not nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + /* Recover floating point registers. */ +#if defined(__riscv_float_abi_single) + flw f0, 31*4(sp) // Recover ft0 + flw f1, 32*4(sp) // Recover ft1 + flw f2, 33*4(sp) // Recover ft2 + flw f3, 34*4(sp) // Recover ft3 + flw f4, 35*4(sp) // Recover ft4 + flw f5, 36*4(sp) // Recover ft5 + flw f6, 37*4(sp) // Recover ft6 + flw f7, 38*4(sp) // Recover ft7 + flw f10, 41*4(sp) // Recover fa0 + flw f11, 42*4(sp) // Recover fa1 + flw f12, 43*4(sp) // Recover fa2 + flw f13, 44*4(sp) // Recover fa3 + flw f14, 45*4(sp) // Recover fa4 + flw f15, 46*4(sp) // Recover fa5 + flw f16, 47*4(sp) // Recover fa6 + flw f17, 48*4(sp) // Recover fa7 + flw f28, 59*4(sp) // Recover ft8 + flw f29, 60*4(sp) // Recover ft9 + flw f30, 61*4(sp) // Recover ft10 + flw f31, 62*4(sp) // Recover ft11 + lw t0, 63*4(sp) // Recover fcsr + csrw fcsr, t0 // Restore fcsr +#elif defined(__riscv_float_abi_double) + fld f0, 31*4(sp) // Recover ft0 + fld f1, 32*4(sp) // Recover ft1 + fld f2, 33*4(sp) // Recover ft2 + fld f3, 34*4(sp) // Recover ft3 + fld f4, 35*4(sp) // Recover ft4 + fld f5, 36*4(sp) // Recover ft5 + fld f6, 37*4(sp) // Recover ft6 + fld f7, 38*4(sp) // Recover ft7 + fld f10, 41*4(sp) // Recover fa0 + fld f11, 42*4(sp) // Recover fa1 + fld f12, 43*4(sp) // Recover fa2 + fld f13, 44*4(sp) // Recover fa3 + fld f14, 45*4(sp) // Recover fa4 + fld f15, 46*4(sp) // Recover fa5 + fld f16, 47*4(sp) // Recover fa6 + fld f17, 48*4(sp) // Recover fa7 + fld f28, 59*4(sp) // Recover ft8 + fld f29, 60*4(sp) // Recover ft9 + fld f30, 61*4(sp) // Recover ft10 + fld f31, 62*4(sp) // Recover ft11 + lw t0, 63*4(sp) // Recover fcsr + csrw fcsr, t0 // Restore fcsr +#endif + + /* Recover standard registers. */ + + /* Restore registers, + Skip global pointer because that does not change. + Also skip the saved registers since they have been restored by any function we called, + except s0 since we use it ourselves. */ + + lw t0, 30*4(sp) // Recover mepc + csrw mepc, t0 // Setup mepc + + /* Compose mstatus via read/modify/write to avoid clobbering unrelated bits. + Set MPIE and restore MPP to Machine, preserve other fields. */ + + csrr t1, mstatus + + /* Clear MPP/MPIE/MIE bits in t1 then set desired values. */ + + li t2, 0x1888 // MPP(0x1800) | MPIE(0x80) | MIE(0x08) + li t3, 0x1800 // Set MPP to Machine mode (bits 12:11) + + /* Construct new mstatus in t1: clear mask bits, set MPP/MPIE and optionally FP bit, + preserve everything except the bits we will modify. */ + + li t4, ~0x1888 // Clear mask for MPP/MPIE/MIE + and t1, t1, t4 + or t1, t1, t3 + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + li t0, 0x2000 // Set FS bits (bits 14:13 to 01) for FP state + or t1, t1, t0 +#endif + csrw mstatus, t1 // Update mstatus safely + + lw ra, 28*4(sp) // Recover return address + lw t0, 19*4(sp) // Recover t0 + lw t1, 18*4(sp) // Recover t1 + lw t2, 17*4(sp) // Recover t2 + lw s0, 12*4(sp) // Recover s0 + lw a0, 27*4(sp) // Recover a0 + lw a1, 26*4(sp) // Recover a1 + lw a2, 25*4(sp) // Recover a2 + lw a3, 24*4(sp) // Recover a3 + lw a4, 23*4(sp) // Recover a4 + lw a5, 22*4(sp) // Recover a5 + lw a6, 21*4(sp) // Recover a6 + lw a7, 20*4(sp) // Recover a7 + lw t3, 16*4(sp) // Recover t3 + lw t4, 15*4(sp) // Recover t4 + lw t5, 14*4(sp) // Recover t5 + lw t6, 13*4(sp) // Recover t6 + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, 65*4 // Recover stack frame - with floating point enabled +#else + addi sp, sp, 32*4 // Recover stack frame - without floating point enabled +#endif + mret // Return to point of interrupt + + /* } */ +_tx_thread_not_nested_restore: + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + || (_tx_thread_preempt_disable)) + { */ + + la t0, _tx_thread_current_ptr // Pickup current thread pointer address + lw t1, 0(t0) // Pickup current thread pointer + + beqz t1, _tx_thread_idle_system_restore // If NULL, idle system restore + + + la t0, _tx_thread_preempt_disable // Pickup preempt disable flag address + lw t2, 0(t0) // Pickup preempt disable flag (UINT) + + bgtz t2, _tx_thread_no_preempt_restore // If set, restore interrupted thread + + + la t0, _tx_thread_execute_ptr // Pickup thread execute pointer address + lw t2, 0(t0) // Pickup thread execute pointer + + bne t1, t2, _tx_thread_preempt_restore // If higher-priority thread is ready, preempt + + +_tx_thread_no_preempt_restore: + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* sp = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + lw sp, 8(t1) // Switch back to thread's stack + + /* Recover floating point registers. */ +#if defined(__riscv_float_abi_single) + flw f0, 31*4(sp) // Recover ft0 + flw f1, 32*4(sp) // Recover ft1 + flw f2, 33*4(sp) // Recover ft2 + flw f3, 34*4(sp) // Recover ft3 + flw f4, 35*4(sp) // Recover ft4 + flw f5, 36*4(sp) // Recover ft5 + flw f6, 37*4(sp) // Recover ft6 + flw f7, 38*4(sp) // Recover ft7 + flw f10, 41*4(sp) // Recover fa0 + flw f11, 42*4(sp) // Recover fa1 + flw f12, 43*4(sp) // Recover fa2 + flw f13, 44*4(sp) // Recover fa3 + flw f14, 45*4(sp) // Recover fa4 + flw f15, 46*4(sp) // Recover fa5 + flw f16, 47*4(sp) // Recover fa6 + flw f17, 48*4(sp) // Recover fa7 + flw f28, 59*4(sp) // Recover ft8 + flw f29, 60*4(sp) // Recover ft9 + flw f30, 61*4(sp) // Recover ft10 + flw f31, 62*4(sp) // Recover ft11 + lw t0, 63*4(sp) // Recover fcsr + csrw fcsr, t0 // Restore fcsr +#elif defined(__riscv_float_abi_double) + fld f0, 31*4(sp) // Recover ft0 + fld f1, 32*4(sp) // Recover ft1 + fld f2, 33*4(sp) // Recover ft2 + fld f3, 34*4(sp) // Recover ft3 + fld f4, 35*4(sp) // Recover ft4 + fld f5, 36*4(sp) // Recover ft5 + fld f6, 37*4(sp) // Recover ft6 + fld f7, 38*4(sp) // Recover ft7 + fld f10, 41*4(sp) // Recover fa0 + fld f11, 42*4(sp) // Recover fa1 + fld f12, 43*4(sp) // Recover fa2 + fld f13, 44*4(sp) // Recover fa3 + fld f14, 45*4(sp) // Recover fa4 + fld f15, 46*4(sp) // Recover fa5 + fld f16, 47*4(sp) // Recover fa6 + fld f17, 48*4(sp) // Recover fa7 + fld f28, 59*4(sp) // Recover ft8 + fld f29, 60*4(sp) // Recover ft9 + fld f30, 61*4(sp) // Recover ft10 + fld f31, 62*4(sp) // Recover ft11 + lw t0, 63*4(sp) // Recover fcsr + csrw fcsr, t0 // Restore fcsr +#endif + + /* Recover the saved context and return to the point of interrupt. */ + + /* Recover standard registers. */ + /* Restore registers, + Skip global pointer because that does not change */ + + lw t0, 30*4(sp) // Recover mepc + csrw mepc, t0 // Setup mepc + + /* Compose mstatus via read/modify/write to avoid clobbering unrelated bits. */ + + csrr t1, mstatus + li t2, 0x1888 // MPP(0x1800) | MPIE(0x80) | MIE(0x08) + li t3, 0x1800 // Set MPP to Machine mode + li t4, ~0x1888 // Clear mask for MPP/MPIE/MIE + and t1, t1, t4 + or t1, t1, t3 + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + li t0, 0x2000 // Set FS bits for FP state + or t1, t1, t0 +#endif + csrw mstatus, t1 // Update mstatus safely + + lw ra, 28*4(sp) // Recover return address + lw t0, 19*4(sp) // Recover t0 + lw t1, 18*4(sp) // Recover t1 + lw t2, 17*4(sp) // Recover t2 + lw s0, 12*4(sp) // Recover s0 + lw a0, 27*4(sp) // Recover a0 + lw a1, 26*4(sp) // Recover a1 + lw a2, 25*4(sp) // Recover a2 + lw a3, 24*4(sp) // Recover a3 + lw a4, 23*4(sp) // Recover a4 + lw a5, 22*4(sp) // Recover a5 + lw a6, 21*4(sp) // Recover a6 + lw a7, 20*4(sp) // Recover a7 + lw t3, 16*4(sp) // Recover t3 + lw t4, 15*4(sp) // Recover t4 + lw t5, 14*4(sp) // Recover t5 + lw t6, 13*4(sp) // Recover t6 + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, 65*4 // Recover stack frame - with floating point enabled +#else + addi sp, sp, 32*4 // Recover stack frame - without floating point enabled +#endif + mret // Return to point of interrupt + + /* } + else + { */ +_tx_thread_preempt_restore: + /* Instead of directly activating the thread again, ensure we save the + entire stack frame by saving the remaining registers. */ + + lw t0, 8(t1) // Pickup thread's stack pointer + ori t3, zero, 1 // Build interrupt stack type + sw t3, 0(t0) // Store stack type + + /* Store floating point preserved registers. */ +#ifdef __riscv_float_abi_single + fsw f8, 39*4(t0) // Store fs0 + fsw f9, 40*4(t0) // Store fs1 + fsw f18, 49*4(t0) // Store fs2 + fsw f19, 50*4(t0) // Store fs3 + fsw f20, 51*4(t0) // Store fs4 + fsw f21, 52*4(t0) // Store fs5 + fsw f22, 53*4(t0) // Store fs6 + fsw f23, 54*4(t0) // Store fs7 + fsw f24, 55*4(t0) // Store fs8 + fsw f25, 56*4(t0) // Store fs9 + fsw f26, 57*4(t0) // Store fs10 + fsw f27, 58*4(t0) // Store fs11 +#elif defined(__riscv_float_abi_double) + fsd f8, 39*4(t0) // Store fs0 + fsd f9, 40*4(t0) // Store fs1 + fsd f18, 49*4(t0) // Store fs2 + fsd f19, 50*4(t0) // Store fs3 + fsd f20, 51*4(t0) // Store fs4 + fsd f21, 52*4(t0) // Store fs5 + fsd f22, 53*4(t0) // Store fs6 + fsd f23, 54*4(t0) // Store fs7 + fsd f24, 55*4(t0) // Store fs8 + fsd f25, 56*4(t0) // Store fs9 + fsd f26, 57*4(t0) // Store fs10 + fsd f27, 58*4(t0) // Store fs11 +#endif + + /* Store standard preserved registers. */ + + sw x9, 11*4(t0) // Store s1 + sw x18, 10*4(t0) // Store s2 + sw x19, 9*4(t0) // Store s3 + sw x20, 8*4(t0) // Store s4 + sw x21, 7*4(t0) // Store s5 + sw x22, 6*4(t0) // Store s6 + sw x23, 5*4(t0) // Store s7 + sw x24, 4*4(t0) // Store s8 + sw x25, 3*4(t0) // Store s9 + sw x26, 2*4(t0) // Store s10 + sw x27, 1*4(t0) // Store s11 + // Note: s0 is already stored! + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) + { */ + + la t0, _tx_timer_time_slice // Pickup time slice variable address + lw t2, 0(t0) // Pickup time slice + beqz t2, _tx_thread_dont_save_ts // If 0, skip time slice processing + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice + _tx_timer_time_slice = 0; */ + + sw t2, 24(t1) // Save current time slice + sw x0, 0(t0) // Clear global time slice + + + /* } */ +_tx_thread_dont_save_ts: + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + la t0, _tx_thread_current_ptr // Pickup current thread pointer address + sw x0, 0(t0) // Clear current thread pointer + + /* } */ + +_tx_thread_idle_system_restore: + /* Just return back to the scheduler! */ + j _tx_thread_schedule // Return to scheduler + +/* } */ diff --git a/ports/risc-v32/gnu/src/tx_thread_context_save.S b/ports/risc-v32/gnu/src/tx_thread_context_save.S new file mode 100644 index 00000000..3b7496b3 --- /dev/null +++ b/ports/risc-v32/gnu/src/tx_thread_context_save.S @@ -0,0 +1,277 @@ +/*************************************************************************** + * Copyright (c) 2025 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save RISC-V32/GNU */ +/* 6.4.x */ +/* AUTHOR */ +/* */ +/* Akif Ejaz, 10xEngineers */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_save(VOID) +{ */ + .global _tx_thread_context_save +_tx_thread_context_save: + + /* Upon entry to this routine, RA/x1 has been saved on the stack + and the stack has been already allocated for the entire context: + addi sp, sp, -32*4 (or -65*4) + sw ra, 28*4(sp) + */ + + sw t0, 19*4(sp) // Store t0 + sw t1, 18*4(sp) // Store t1 + + /* Check for a nested interrupt. */ + /* if (_tx_thread_system_state++) + { */ + + la t0, _tx_thread_system_state // Pickup addr of system state var + lw t1, 0(t0) // Pickup system state + addi t1, t1, 1 // Increment system state + sw t1, 0(t0) // Store system state + li t0, 1 + bgt t1, t0, _tx_thread_nested_save // If it's more than 1, nested interrupt + + /* First level interrupt, save the rest of the scratch registers and + check for a thread to preempt. */ + + sw t2, 17*4(sp) // Store t2 + sw s0, 12*4(sp) // Store s0 + sw a0, 27*4(sp) // Store a0 + sw a1, 26*4(sp) // Store a1 + sw a2, 25*4(sp) // Store a2 + sw a3, 24*4(sp) // Store a3 + sw a4, 23*4(sp) // Store a4 + sw a5, 22*4(sp) // Store a5 + sw a6, 21*4(sp) // Store a6 + sw a7, 20*4(sp) // Store a7 + sw t3, 16*4(sp) // Store t3 + sw t4, 15*4(sp) // Store t4 + sw t5, 14*4(sp) // Store t5 + sw t6, 13*4(sp) // Store t6 + + /* Save floating point registers. */ +#if defined(__riscv_float_abi_single) + fsw f0, 31*4(sp) // Store ft0 + fsw f1, 32*4(sp) // Store ft1 + fsw f2, 33*4(sp) // Store ft2 + fsw f3, 34*4(sp) // Store ft3 + fsw f4, 35*4(sp) // Store ft4 + fsw f5, 36*4(sp) // Store ft5 + fsw f6, 37*4(sp) // Store ft6 + fsw f7, 38*4(sp) // Store ft7 + fsw f10, 41*4(sp) // Store fa0 + fsw f11, 42*4(sp) // Store fa1 + fsw f12, 43*4(sp) // Store fa2 + fsw f13, 44*4(sp) // Store fa3 + fsw f14, 45*4(sp) // Store fa4 + fsw f15, 46*4(sp) // Store fa5 + fsw f16, 47*4(sp) // Store fa6 + fsw f17, 48*4(sp) // Store fa7 + fsw f28, 59*4(sp) // Store ft8 + fsw f29, 60*4(sp) // Store ft9 + fsw f30, 61*4(sp) // Store ft10 + fsw f31, 62*4(sp) // Store ft11 + csrr t0, fcsr + sw t0, 63*4(sp) // Store fcsr +#elif defined(__riscv_float_abi_double) + fsd f0, 31*4(sp) // Store ft0 + fsd f1, 32*4(sp) // Store ft1 + fsd f2, 33*4(sp) // Store ft2 + fsd f3, 34*4(sp) // Store ft3 + fsd f4, 35*4(sp) // Store ft4 + fsd f5, 36*4(sp) // Store ft5 + fsd f6, 37*4(sp) // Store ft6 + fsd f7, 38*4(sp) // Store ft7 + fsd f10, 41*4(sp) // Store fa0 + fsd f11, 42*4(sp) // Store fa1 + fsd f12, 43*4(sp) // Store fa2 + fsd f13, 44*4(sp) // Store fa3 + fsd f14, 45*4(sp) // Store fa4 + fsd f15, 46*4(sp) // Store fa5 + fsd f16, 47*4(sp) // Store fa6 + fsd f17, 48*4(sp) // Store fa7 + fsd f28, 59*4(sp) // Store ft8 + fsd f29, 60*4(sp) // Store ft9 + fsd f30, 61*4(sp) // Store ft10 + fsd f31, 62*4(sp) // Store ft11 + csrr t0, fcsr + sw t0, 63*4(sp) // Store fcsr +#endif + + csrr t0, mepc + sw t0, 30*4(sp) // Save it on the stack + + /* Save mstatus. */ + csrr t0, mstatus + sw t0, 29*4(sp) + + la t1, _tx_thread_current_ptr // Pickup address of current thread ptr + lw t2, 0(t1) // Pickup current thread pointer + beqz t2, _tx_thread_idle_system_save // If NULL, idle system was interrupted + + /* Save the current thread's stack pointer and switch to the system stack. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; + sp = _tx_thread_system_stack_ptr; */ + + sw sp, 8(t2) // Save stack pointer + la t0, _tx_thread_system_stack_ptr + lw sp, 0(t0) // Switch to system stack + + /* Call the ISR execution exit function if enabled. */ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + call _tx_execution_isr_enter // Call the ISR execution enter function +#endif + + ret // Return to ISR + +_tx_thread_nested_save: + + /* Nested interrupt! Just save the scratch registers and return to the ISR. */ + + sw t2, 17*4(sp) // Store t2 + sw s0, 12*4(sp) // Store s0 + sw a0, 27*4(sp) // Store a0 + sw a1, 26*4(sp) // Store a1 + sw a2, 25*4(sp) // Store a2 + sw a3, 24*4(sp) // Store a3 + sw a4, 23*4(sp) // Store a4 + sw a5, 22*4(sp) // Store a5 + sw a6, 21*4(sp) // Store a6 + sw a7, 20*4(sp) // Store a7 + sw t3, 16*4(sp) // Store t3 + sw t4, 15*4(sp) // Store t4 + sw t5, 14*4(sp) // Store t5 + sw t6, 13*4(sp) // Store t6 + + /* Save floating point registers. */ +#if defined(__riscv_float_abi_single) + fsw f0, 31*4(sp) // Store ft0 + fsw f1, 32*4(sp) // Store ft1 + fsw f2, 33*4(sp) // Store ft2 + fsw f3, 34*4(sp) // Store ft3 + fsw f4, 35*4(sp) // Store ft4 + fsw f5, 36*4(sp) // Store ft5 + fsw f6, 37*4(sp) // Store ft6 + fsw f7, 38*4(sp) // Store ft7 + fsw f10, 41*4(sp) // Store fa0 + fsw f11, 42*4(sp) // Store fa1 + fsw f12, 43*4(sp) // Store fa2 + fsw f13, 44*4(sp) // Store fa3 + fsw f14, 45*4(sp) // Store fa4 + fsw f15, 46*4(sp) // Store fa5 + fsw f16, 47*4(sp) // Store fa6 + fsw f17, 48*4(sp) // Store fa7 + fsw f28, 59*4(sp) // Store ft8 + fsw f29, 60*4(sp) // Store ft9 + fsw f30, 61*4(sp) // Store ft10 + fsw f31, 62*4(sp) // Store ft11 + csrr t0, fcsr + sw t0, 63*4(sp) // Store fcsr +#elif defined(__riscv_float_abi_double) + fsd f0, 31*4(sp) // Store ft0 + fsd f1, 32*4(sp) // Store ft1 + fsd f2, 33*4(sp) // Store ft2 + fsd f3, 34*4(sp) // Store ft3 + fsd f4, 35*4(sp) // Store ft4 + fsd f5, 36*4(sp) // Store ft5 + fsd f6, 37*4(sp) // Store ft6 + fsd f7, 38*4(sp) // Store ft7 + fsd f10, 41*4(sp) // Store fa0 + fsd f11, 42*4(sp) // Store fa1 + fsd f12, 43*4(sp) // Store fa2 + fsd f13, 44*4(sp) // Store fa3 + fsd f14, 45*4(sp) // Store fa4 + fsd f15, 46*4(sp) // Store fa5 + fsd f16, 47*4(sp) // Store fa6 + fsd f17, 48*4(sp) // Store fa7 + fsd f28, 59*4(sp) // Store ft8 + fsd f29, 60*4(sp) // Store ft9 + fsd f30, 61*4(sp) // Store ft10 + fsd f31, 62*4(sp) // Store ft11 + csrr t0, fcsr + sw t0, 63*4(sp) // Store fcsr +#endif + + csrr t0, mepc + sw t0, 30*4(sp) // Save it on stack + + csrr t0, mstatus + sw t0, 29*4(sp) + + /* Call the ISR execution exit function if enabled. */ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + call _tx_execution_isr_enter // Call the ISR execution enter function +#endif + + ret // Return to ISR + +_tx_thread_idle_system_save: + + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + call _tx_execution_isr_enter // Call the ISR execution enter function +#endif + + /* Interrupt occurred in the scheduling loop. */ + + /* } +} */ +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, 65*4 // Recover stack frame - with floating point enabled +#else + addi sp, sp, 32*4 // Recover the reserved stack space +#endif + ret // Return to calling ISR diff --git a/ports/risc-v32/gnu/src/tx_thread_interrupt_control.S b/ports/risc-v32/gnu/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..8e28cf74 --- /dev/null +++ b/ports/risc-v32/gnu/src/tx_thread_interrupt_control.S @@ -0,0 +1,94 @@ +/*************************************************************************** + * Copyright (c) 2025 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control RISC-V32/GNU */ +/* 6.4.x */ +/* AUTHOR */ +/* */ +/* Akif Ejaz, 10xEngineers */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_control(UINT new_posture) +{ */ + .global _tx_thread_interrupt_control +_tx_thread_interrupt_control: + + /* Pickup current interrupt posture. */ + + csrr a1, mstatus // Pickup mstatus + andi a1, a1, 0x08 // Mask out all but MIE + + /* Check for the new posture. */ + + beqz a0, _tx_thread_interrupt_disable // If 0, disable interrupts + + /* Enable interrupts. */ + + csrsi mstatus, 0x08 // Enable interrupts (MIE bit 3) + j _tx_thread_interrupt_control_exit // Return to caller + +_tx_thread_interrupt_disable: + + /* Disable interrupts. */ + + csrci mstatus, 0x08 // Disable interrupts (MIE bit 3) + +_tx_thread_interrupt_control_exit: + + /* Return the old interrupt posture. */ + + mv a0, a1 // Setup return value + ret // Return to caller + +/* } */ diff --git a/ports/risc-v32/gnu/src/tx_thread_schedule.S b/ports/risc-v32/gnu/src/tx_thread_schedule.S new file mode 100644 index 00000000..edf3462f --- /dev/null +++ b/ports/risc-v32/gnu/src/tx_thread_schedule.S @@ -0,0 +1,324 @@ +/*************************************************************************** + * Copyright (c) 2025 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule RISC-V32/GNU */ +/* 6.4.x */ +/* AUTHOR */ +/* */ +/* Akif Ejaz, 10xEngineers */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_schedule(VOID) +{ */ + .global _tx_thread_schedule +_tx_thread_schedule: + + /* Enable interrupts. */ + + csrsi mstatus, 0x08 // Enable interrupts (MIE bit 3) + + /* Wait for a thread to execute. */ + /* do + { */ +_tx_thread_schedule_loop: + + la t0, _tx_thread_execute_ptr // Pickup address of execute ptr + lw t1, 0(t0) // Pickup execute pointer + bnez t1, _tx_thread_ready_to_run // If non-NULL, a thread is ready to run + +#ifndef TX_NO_WFI + wfi // Wait for interrupt +#endif + j _tx_thread_schedule_loop // Check again + + /* } + while (_tx_thread_execute_ptr == TX_NULL); */ + +_tx_thread_ready_to_run: + + /* At this point, t1 contains the pointer to the thread to execute. + Lockout interrupts. */ + + csrci mstatus, 0x08 // Disable interrupts (MIE bit 3) + + /* Check _tx_thread_execute_ptr again, in case an interrupt occurred + between the check and the disable. */ + + lw t1, 0(t0) // Pickup execute pointer + beqz t1, _tx_thread_schedule_loop // If NULL, go back to wait loop + + /* Yes! We have a thread to execute. */ + /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ + + la t0, _tx_thread_current_ptr // Pickup address of current thread + sw t1, 0(t0) // Setup current thread pointer + + /* Increment the run count for this thread. */ + /* _tx_thread_current_ptr -> tx_thread_run_count++; */ + + lw t2, 4(t1) // Pickup run count + addi t2, t2, 1 // Increment run count + sw t2, 4(t1) // Store run count + + /* Setup time-slice values. */ + /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ + + lw t2, 24(t1) // Pickup thread time-slice + la t3, _tx_timer_time_slice // Pickup address of time-slice + sw t2, 0(t3) // Setup time-slice + + /* Call the thread execution enter function if enabled. */ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + call _tx_execution_thread_enter // Call the thread execution enter function +#endif + + /* Switch to the thread's stack. */ + /* sp = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + lw sp, 8(t1) // Switch to thread stack + + /* Determine the type of stack frame. */ + /* if (*sp) + { */ + + lw t0, 0(sp) // Pickup stack type + beqz t0, _tx_thread_solicited_return // If 0, solicited return + + /* Recover floating point registers. */ +#if defined(__riscv_float_abi_single) + flw f0, 31*4(sp) // Recover ft0 + flw f1, 32*4(sp) // Recover ft1 + flw f2, 33*4(sp) // Recover ft2 + flw f3, 34*4(sp) // Recover ft3 + flw f4, 35*4(sp) // Recover ft4 + flw f5, 36*4(sp) // Recover ft5 + flw f6, 37*4(sp) // Recover ft6 + flw f7, 38*4(sp) // Recover ft7 + flw f8, 39*4(sp) // Recover fs0 + flw f9, 40*4(sp) // Recover fs1 + flw f10, 41*4(sp) // Recover fa0 + flw f11, 42*4(sp) // Recover fa1 + flw f12, 43*4(sp) // Recover fa2 + flw f13, 44*4(sp) // Recover fa3 + flw f14, 45*4(sp) // Recover fa4 + flw f15, 46*4(sp) // Recover fa5 + flw f16, 47*4(sp) // Recover fa6 + flw f17, 48*4(sp) // Recover fa7 + flw f18, 49*4(sp) // Recover fs2 + flw f19, 50*4(sp) // Recover fs3 + flw f20, 51*4(sp) // Recover fs4 + flw f21, 52*4(sp) // Recover fs5 + flw f22, 53*4(sp) // Recover fs6 + flw f23, 54*4(sp) // Recover fs7 + flw f24, 55*4(sp) // Recover fs8 + flw f25, 56*4(sp) // Recover fs9 + flw f26, 57*4(sp) // Recover fs10 + flw f27, 58*4(sp) // Recover fs11 + flw f28, 59*4(sp) // Recover ft8 + flw f29, 60*4(sp) // Recover ft9 + flw f30, 61*4(sp) // Recover ft10 + flw f31, 62*4(sp) // Recover ft11 + lw t0, 63*4(sp) // Recover fcsr + csrw fcsr, t0 // Restore fcsr +#elif defined(__riscv_float_abi_double) + fld f0, 31*4(sp) // Recover ft0 + fld f1, 32*4(sp) // Recover ft1 + fld f2, 33*4(sp) // Recover ft2 + fld f3, 34*4(sp) // Recover ft3 + fld f4, 35*4(sp) // Recover ft4 + fld f5, 36*4(sp) // Recover ft5 + fld f6, 37*4(sp) // Recover ft6 + fld f7, 38*4(sp) // Recover ft7 + fld f8, 39*4(sp) // Recover fs0 + fld f9, 40*4(sp) // Recover fs1 + fld f10, 41*4(sp) // Recover fa0 + fld f11, 42*4(sp) // Recover fa1 + fld f12, 43*4(sp) // Recover fa2 + fld f13, 44*4(sp) // Recover fa3 + fld f14, 45*4(sp) // Recover fa4 + fld f15, 46*4(sp) // Recover fa5 + fld f16, 47*4(sp) // Recover fa6 + fld f17, 48*4(sp) // Recover fa7 + fld f18, 49*4(sp) // Recover fs2 + fld f19, 50*4(sp) // Recover fs3 + fld f20, 51*4(sp) // Recover fs4 + fld f21, 52*4(sp) // Recover fs5 + fld f22, 53*4(sp) // Recover fs6 + fld f23, 54*4(sp) // Recover fs7 + fld f24, 55*4(sp) // Recover fs8 + fld f25, 56*4(sp) // Recover fs9 + fld f26, 57*4(sp) // Recover fs10 + fld f27, 58*4(sp) // Recover fs11 + fld f28, 59*4(sp) // Recover ft8 + fld f29, 60*4(sp) // Recover ft9 + fld f30, 61*4(sp) // Recover ft10 + fld f31, 62*4(sp) // Recover ft11 + lw t0, 63*4(sp) // Recover fcsr + csrw fcsr, t0 // Restore fcsr +#endif + + /* Recover standard registers. */ + + lw t0, 30*4(sp) // Recover mepc + csrw mepc, t0 // Setup mepc + + li t0, 0x1880 // Prepare mstatus: MPP=Machine(0x1800) | MPIE(0x80) +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + li t1, 0x2000 // Set FS bits for FP state + or t0, t0, t1 +#endif + csrw mstatus, t0 // Set mstatus + + lw ra, 28*4(sp) // Recover return address + lw t0, 19*4(sp) // Recover t0 + lw t1, 18*4(sp) // Recover t1 + lw t2, 17*4(sp) // Recover t2 + lw s0, 12*4(sp) // Recover s0 + lw x9, 11*4(sp) // Recover s1 + lw a0, 27*4(sp) // Recover a0 + lw a1, 26*4(sp) // Recover a1 + lw a2, 25*4(sp) // Recover a2 + lw a3, 24*4(sp) // Recover a3 + lw a4, 23*4(sp) // Recover a4 + lw a5, 22*4(sp) // Recover a5 + lw a6, 21*4(sp) // Recover a6 + lw a7, 20*4(sp) // Recover a7 + lw t3, 16*4(sp) // Recover t3 + lw t4, 15*4(sp) // Recover t4 + lw t5, 14*4(sp) // Recover t5 + lw t6, 13*4(sp) // Recover t6 + lw x18, 10*4(sp) // Recover s2 + lw x19, 9*4(sp) // Recover s3 + lw x20, 8*4(sp) // Recover s4 + lw x21, 7*4(sp) // Recover s5 + lw x22, 6*4(sp) // Recover s6 + lw x23, 5*4(sp) // Recover s7 + lw x24, 4*4(sp) // Recover s8 + lw x25, 3*4(sp) // Recover s9 + lw x26, 2*4(sp) // Recover s10 + lw x27, 1*4(sp) // Recover s11 + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, 65*4 // Recover stack frame - with floating point enabled +#else + addi sp, sp, 32*4 // Recover stack frame - without floating point enabled +#endif + mret // Return to thread + +_tx_thread_solicited_return: + + /* Recover floating point registers. */ +#if defined(__riscv_float_abi_single) + flw f8, 15*4(sp) // Recover fs0 + flw f9, 16*4(sp) // Recover fs1 + flw f18, 17*4(sp) // Recover fs2 + flw f19, 18*4(sp) // Recover fs3 + flw f20, 19*4(sp) // Recover fs4 + flw f21, 20*4(sp) // Recover fs5 + flw f22, 21*4(sp) // Recover fs6 + flw f23, 22*4(sp) // Recover fs7 + flw f24, 23*4(sp) // Recover fs8 + flw f25, 24*4(sp) // Recover fs9 + flw f26, 25*4(sp) // Recover fs10 + flw f27, 26*4(sp) // Recover fs11 + lw t0, 27*4(sp) // Recover fcsr + csrw fcsr, t0 // Restore fcsr +#elif defined(__riscv_float_abi_double) + fld f8, 15*4(sp) // Recover fs0 + fld f9, 16*4(sp) // Recover fs1 + fld f18, 17*4(sp) // Recover fs2 + fld f19, 18*4(sp) // Recover fs3 + fld f20, 19*4(sp) // Recover fs4 + fld f21, 20*4(sp) // Recover fs5 + fld f22, 21*4(sp) // Recover fs6 + fld f23, 22*4(sp) // Recover fs7 + fld f24, 23*4(sp) // Recover fs8 + fld f25, 24*4(sp) // Recover fs9 + fld f26, 25*4(sp) // Recover fs10 + fld f27, 26*4(sp) // Recover fs11 + lw t0, 27*4(sp) // Recover fcsr + csrw fcsr, t0 // Restore fcsr +#endif + + /* Recover standard registers. */ + + lw t0, 14*4(sp) // Recover mstatus + csrw mstatus, t0 // Restore mstatus + + lw ra, 13*4(sp) // Recover return address + lw s0, 12*4(sp) // Recover s0 + lw s1, 11*4(sp) // Recover s1 + lw x18, 10*4(sp) // Recover s2 + lw x19, 9*4(sp) // Recover s3 + lw x20, 8*4(sp) // Recover s4 + lw x21, 7*4(sp) // Recover s5 + lw x22, 6*4(sp) // Recover s6 + lw x23, 5*4(sp) // Recover s7 + lw x24, 4*4(sp) // Recover s8 + lw x25, 3*4(sp) // Recover s9 + lw x26, 2*4(sp) // Recover s10 + lw x27, 1*4(sp) // Recover s11 + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, 29*4 // Recover stack frame - with floating point enabled +#else + addi sp, sp, 16*4 // Recover stack frame - without floating point enabled +#endif + ret // Return to thread + +/* } */ diff --git a/ports/risc-v32/gnu/src/tx_thread_stack_build.S b/ports/risc-v32/gnu/src/tx_thread_stack_build.S new file mode 100644 index 00000000..36f9b317 --- /dev/null +++ b/ports/risc-v32/gnu/src/tx_thread_stack_build.S @@ -0,0 +1,227 @@ +/*************************************************************************** + * Copyright (c) 2025 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build RISC-V32/GNU */ +/* 6.4.x */ +/* AUTHOR */ +/* */ +/* Akif Ejaz, 10xEngineers */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +{ */ + .global _tx_thread_stack_build +_tx_thread_stack_build: + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the RISC-V should look like the following after it is built: + Reg Index + Stack Top: 1 0 Interrupt stack frame type + x27 1 Initial s11 + x26 2 Initial s10 + x25 3 Initial s9 + x24 4 Initial s8 + x23 5 Initial s7 + x22 6 Initial s6 + x21 7 Initial s5 + x20 8 Initial s4 + x19 9 Initial s3 + x18 10 Initial s2 + x9 11 Initial s1 + x8 12 Initial s0 + x31 13 Initial t6 + x30 14 Initial t5 + x29 15 Initial t4 + x28 16 Initial t3 + x7 17 Initial t2 + x6 18 Initial t1 + x5 19 Initial t0 + x17 20 Initial a7 + x16 21 Initial a6 + x15 22 Initial a5 + x14 23 Initial a4 + x13 24 Initial a3 + x12 25 Initial a2 + x11 26 Initial a1 + x10 27 Initial a0 + x1 28 Initial ra + -- 29 reserved + mepc 30 Initial mepc +If floating point support: + f0 31 Initial ft0 + f1 32 Initial ft1 + f2 33 Initial ft2 + f3 34 Initial ft3 + f4 35 Initial ft4 + f5 36 Initial ft5 + f6 37 Initial ft6 + f7 38 Initial ft7 + f8 39 Initial fs0 + f9 40 Initial fs1 + f10 41 Initial fa0 + f11 42 Initial fa1 + f12 43 Initial fa2 + f13 44 Initial fa3 + f14 45 Initial fa4 + f15 46 Initial fa5 + f16 47 Initial fa6 + f17 48 Initial fa7 + f18 49 Initial fs2 + f19 50 Initial fs3 + f20 51 Initial fs4 + f21 52 Initial fs5 + f22 53 Initial fs6 + f23 54 Initial fs7 + f24 55 Initial fs8 + f25 56 Initial fs9 + f26 57 Initial fs10 + f27 58 Initial fs11 + f28 59 Initial ft8 + f29 60 Initial ft9 + f30 61 Initial ft10 + f31 62 Initial ft11 + fscr 63 Initial fscr + + Stack Bottom: (higher memory address) */ + + lw t0, 16(a0) // Pickup end of stack area + li t1, ~15 // Build 16-byte alignment mask + and t0, t0, t1 // Make sure 16-byte alignment + + /* Actually build the stack frame. */ + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi t0, t0, -65*4 +#else + addi t0, t0, -32*4 // Allocate space for the stack frame +#endif + li t1, 1 // Build stack type + sw t1, 0*4(t0) // Place stack type on the top + sw zero, 1*4(t0) // Initial s11 + sw zero, 2*4(t0) // Initial s10 + sw zero, 3*4(t0) // Initial s9 + sw zero, 4*4(t0) // Initial s8 + sw zero, 5*4(t0) // Initial s7 + sw zero, 6*4(t0) // Initial s6 + sw zero, 7*4(t0) // Initial s5 + sw zero, 8*4(t0) // Initial s4 + sw zero, 9*4(t0) // Initial s3 + sw zero, 10*4(t0) // Initial s2 + sw zero, 11*4(t0) // Initial s1 + sw zero, 12*4(t0) // Initial s0 + sw zero, 13*4(t0) // Initial t6 + sw zero, 14*4(t0) // Initial t5 + sw zero, 15*4(t0) // Initial t4 + sw zero, 16*4(t0) // Initial t3 + sw zero, 17*4(t0) // Initial t2 + sw zero, 18*4(t0) // Initial t1 + sw zero, 19*4(t0) // Initial t0 + sw zero, 20*4(t0) // Initial a7 + sw zero, 21*4(t0) // Initial a6 + sw zero, 22*4(t0) // Initial a5 + sw zero, 23*4(t0) // Initial a4 + sw zero, 24*4(t0) // Initial a3 + sw zero, 25*4(t0) // Initial a2 + sw zero, 26*4(t0) // Initial a1 + sw zero, 27*4(t0) // Initial a0 + sw zero, 28*4(t0) // Initial ra + sw a1, 30*4(t0) // Initial mepc (thread entry point) +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + sw zero, 31*4(t0) // Initial ft0 + sw zero, 32*4(t0) // Initial ft1 + sw zero, 33*4(t0) // Initial ft2 + sw zero, 34*4(t0) // Initial ft3 + sw zero, 35*4(t0) // Initial ft4 + sw zero, 36*4(t0) // Initial ft5 + sw zero, 37*4(t0) // Initial ft6 + sw zero, 38*4(t0) // Initial ft7 + sw zero, 39*4(t0) // Initial fs0 + sw zero, 40*4(t0) // Initial fs1 + sw zero, 41*4(t0) // Initial fa0 + sw zero, 42*4(t0) // Initial fa1 + sw zero, 43*4(t0) // Initial fa2 + sw zero, 44*4(t0) // Initial fa3 + sw zero, 45*4(t0) // Initial fa4 + sw zero, 46*4(t0) // Initial fa5 + sw zero, 47*4(t0) // Initial fa6 + sw zero, 48*4(t0) // Initial fa7 + sw zero, 49*4(t0) // Initial fs2 + sw zero, 50*4(t0) // Initial fs3 + sw zero, 51*4(t0) // Initial fs4 + sw zero, 52*4(t0) // Initial fs5 + sw zero, 53*4(t0) // Initial fs6 + sw zero, 54*4(t0) // Initial fs7 + sw zero, 55*4(t0) // Initial fs8 + sw zero, 56*4(t0) // Initial fs9 + sw zero, 57*4(t0) // Initial fs10 + sw zero, 58*4(t0) // Initial fs11 + sw zero, 59*4(t0) // Initial ft8 + sw zero, 60*4(t0) // Initial ft9 + sw zero, 61*4(t0) // Initial ft10 + sw zero, 62*4(t0) // Initial ft11 + csrr a1, fcsr // Read fcsr for initial value + sw a1, 63*4(t0) // Initial fcsr + sw zero, 64*4(t0) // Reserved word (0) +#else + sw zero, 31*4(t0) // Reserved word (0) +#endif + + /* Setup stack pointer. */ + /* thread_ptr -> tx_thread_stack_ptr = t0; */ + + sw t0, 8(a0) // Save stack pointer in thread's + ret // control block and return +/* } */ diff --git a/ports/risc-v32/gnu/src/tx_thread_system_return.S b/ports/risc-v32/gnu/src/tx_thread_system_return.S new file mode 100644 index 00000000..110f6ac1 --- /dev/null +++ b/ports/risc-v32/gnu/src/tx_thread_system_return.S @@ -0,0 +1,174 @@ +/*************************************************************************** + * Copyright (c) 2025 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return RISC-V32/GNU */ +/* 6.4.x */ +/* AUTHOR */ +/* */ +/* Akif Ejaz, 10xEngineers */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the system. Only a minimal context */ +/* is saved since the compiler assumes temp registers are going to get */ +/* slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_system_return(VOID) +{ */ + .global _tx_thread_system_return +_tx_thread_system_return: + + /* Save minimal context on the stack. */ + /* sp -= sizeof(stack_frame); */ + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, -29*4 // Allocate space on the stack - with floating point enabled +#else + addi sp, sp, -16*4 // Allocate space on the stack - without floating point enabled +#endif + + /* Store floating point preserved registers. */ +#if defined(__riscv_float_abi_single) + fsw f8, 15*4(sp) // Store fs0 + fsw f9, 16*4(sp) // Store fs1 + fsw f18, 17*4(sp) // Store fs2 + fsw f19, 18*4(sp) // Store fs3 + fsw f20, 19*4(sp) // Store fs4 + fsw f21, 20*4(sp) // Store fs5 + fsw f22, 21*4(sp) // Store fs6 + fsw f23, 22*4(sp) // Store fs7 + fsw f24, 23*4(sp) // Store fs8 + fsw f25, 24*4(sp) // Store fs9 + fsw f26, 25*4(sp) // Store fs10 + fsw f27, 26*4(sp) // Store fs11 + csrr t0, fcsr + sw t0, 27*4(sp) // Store fcsr +#elif defined(__riscv_float_abi_double) + fsd f8, 15*4(sp) // Store fs0 + fsd f9, 16*4(sp) // Store fs1 + fsd f18, 17*4(sp) // Store fs2 + fsd f19, 18*4(sp) // Store fs3 + fsd f20, 19*4(sp) // Store fs4 + fsd f21, 20*4(sp) // Store fs5 + fsd f22, 21*4(sp) // Store fs6 + fsd f23, 22*4(sp) // Store fs7 + fsd f24, 23*4(sp) // Store fs8 + fsd f25, 24*4(sp) // Store fs9 + fsd f26, 25*4(sp) // Store fs10 + fsd f27, 26*4(sp) // Store fs11 + csrr t0, fcsr + sw t0, 27*4(sp) // Store fcsr +#endif + + sw zero, 0(sp) // Solicited stack type + sw ra, 13*4(sp) // Save return address + sw s0, 12*4(sp) // Save s0 + sw s1, 11*4(sp) // Save s1 + sw s2, 10*4(sp) // Save s2 + sw s3, 9*4(sp) // Save s3 + sw s4, 8*4(sp) // Save s4 + sw s5, 7*4(sp) // Save s5 + sw s6, 6*4(sp) // Save s6 + sw s7, 5*4(sp) // Save s7 + sw s8, 4*4(sp) // Save s8 + sw s9, 3*4(sp) // Save s9 + sw s10, 2*4(sp) // Save s10 + sw s11, 1*4(sp) // Save s11 + csrr t0, mstatus // Pickup mstatus + sw t0, 14*4(sp) // Save mstatus + + + /* Lockout interrupts. will be enabled in _tx_thread_schedule */ + + csrci mstatus, 0x08 // Disable interrupts (MIE bit 3) + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + call _tx_execution_thread_exit // Call the thread execution exit function +#endif + + la t0, _tx_thread_current_ptr // Pickup address of pointer + lw t1, 0(t0) // Pickup current thread pointer + la t2, _tx_thread_system_stack_ptr // Pickup stack pointer address + + /* Save current stack and switch to system stack. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = SP; + SP = _tx_thread_system_stack_ptr; */ + + sw sp, 8(t1) // Save stack pointer + lw sp, 0(t2) // Switch to system stack + + /* Determine if the time-slice is active. */ + /* if (_tx_timer_time_slice) + { */ + + la t4, _tx_timer_time_slice // Pickup time slice variable addr + lw t3, 0(t4) // Pickup time slice value + la t2, _tx_thread_schedule // Pickup address of scheduling loop + beqz t3, _tx_thread_dont_save_ts // If no time-slice, don't save it + + /* Save time-slice for the thread and clear the current time-slice. */ + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + sw t3, 24(t1) // Save current time-slice for thread + sw zero, 0(t4) // Clear time-slice variable + + /* } */ +_tx_thread_dont_save_ts: + + /* Clear the current thread pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + sw x0, 0(t0) // Clear current thread pointer + jr t2 // Return to thread scheduler + +/* } */ diff --git a/ports/risc-v32/gnu/src/tx_timer_interrupt.S b/ports/risc-v32/gnu/src/tx_timer_interrupt.S new file mode 100644 index 00000000..92b5c6b6 --- /dev/null +++ b/ports/risc-v32/gnu/src/tx_timer_interrupt.S @@ -0,0 +1,210 @@ +/*************************************************************************** + * Copyright (c) 2026 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .section .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt RISC-V32/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Akif Ejaz, 10xEngineers */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 01-20-2023 Akif Ejaz Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_timer_interrupt(VOID) +{ */ + .global _tx_timer_interrupt +_tx_timer_interrupt: + + /* Increment the system clock. */ + /* _tx_timer_system_clock++; */ + + la t0, _tx_timer_system_clock // Pickup address of system clock + lw t1, 0(t0) // Pickup system clock + la t2, _tx_timer_time_slice // Pickup address of time slice + lw t3, 0(t2) // Pickup time slice + addi t1, t1, 1 // Increment system clock + sw t1, 0(t0) // Store new system clock + li t6, 0 // Clear local expired flag + + /* Test for time-slice expiration. */ + /* if (_tx_timer_time_slice) + { */ + + beqz t3, _tx_timer_no_time_slice // If 0, skip time slice processing + addi t3, t3, -1 // Decrement the time slice + + /* Decrement the time_slice. */ + /* _tx_timer_time_slice--; */ + + sw t3, 0(t2) // Store new time slice + + /* Check for expiration. */ + /* if (_tx_timer_time_slice == 0) */ + + bgtz t3, _tx_timer_no_time_slice // If not 0, has not expired yet + li t1, 1 // Build expired flag + + /* Set the time-slice expired flag. */ + /* _tx_timer_expired_time_slice = TX_TRUE; */ + + la t4, _tx_timer_expired_time_slice // Get address of expired flag + sw t1, 0(t4) // Set expired flag (UINT) + ori t6, t6, 1 // Set local expired flag + + /* } */ + +_tx_timer_no_time_slice: + + /* Test for timer expiration. */ + /* if (*_tx_timer_current_ptr) + { */ + + la t0, _tx_timer_current_ptr // Pickup address of current ptr + lw t1, 0(t0) // Pickup current pointer (word) + lw t3, 0(t1) // Pickup the current timer entry (word) + la t2, _tx_timer_expired // Pickup address of timer expired flag + li t4, 1 // Build TX_TRUE flag + beqz t3, _tx_timer_no_timer // If NULL, no timer has expired + + /* Set expiration flag. */ + /* _tx_timer_expired = TX_TRUE; */ + + ori t6, t6, 2 // Set local expired flag + sw t4, 0(t2) // Set expired flag in memory (UINT) + j _tx_timer_done // Finished timer processing + + + /* } + else + { */ +_tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + /* _tx_timer_current_ptr++; */ + + /* Check for wrap-around. */ + /* if (_tx_timer_current_ptr == _tx_timer_list_end) */ + + la t2, _tx_timer_list_end // Pickup address of list end pointer + lw t3, 0(t2) // Pickup actual list end + addi t1, t1, 4 // Point to next timer entry + sw t1, 0(t0) // Store new timer pointer + bne t1, t3, _tx_timer_skip_wrap // If not same, good pointer + + /* Wrap to beginning of list. */ + /* _tx_timer_current_ptr = _tx_timer_list_start; */ + + la t2, _tx_timer_list_start // Pickup address of list start pointer + lw t4, 0(t2) // Pickup start of the list + sw t4, 0(t0) // Store new timer pointer + + +_tx_timer_skip_wrap: + /* } */ + +_tx_timer_done: + + + /* See if anything has expired. */ + /* if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + { */ + + beqz t6, _tx_timer_nothing_expired // If nothing expired skip the rest + addi sp, sp, -16 // Allocate some storage on the stack + sw t6, 0(sp) // Save local expired flag + sw ra, 4(sp) // Save ra + + /* Did a timer expire? */ + /* if (_tx_timer_expired) + { */ + + andi t2, t6, 2 // Isolate the timer expired bit + beqz t2, _tx_timer_dont_activate // No, timer not expired + + /* Call the timer expiration processing. */ + /* _tx_timer_expiration_process(void); */ + + call _tx_timer_expiration_process // Call _tx_timer_expiration_process + lw t6, 0(sp) // Recover local expired flag + + /* } */ +_tx_timer_dont_activate: + + /* Did time slice expire? */ + /* if (_tx_timer_expired_time_slice) + { */ + + andi t2, t6, 1 // Is the timer expired bit set? + beqz t2, _tx_timer_not_ts_expiration // If not, skip time slice processing + + /* Time slice interrupted thread. */ + /* _tx_thread_time_slice(); */ + + call _tx_thread_time_slice // Call time slice + + /* } */ + +_tx_timer_not_ts_expiration: + + lw ra, 4(sp) // Recover ra + addi sp, sp, 16 // Recover stack space + /* } */ + +_tx_timer_nothing_expired: + + ret + +/* } */ \ No newline at end of file From 1d796d5fded025719dd57a16b545621cadca65eb Mon Sep 17 00:00:00 2001 From: Akif Ejaz Date: Mon, 16 Feb 2026 17:15:13 +0500 Subject: [PATCH 10/19] Add RISC-V32 arch. port layer This update adapts the ThreadX low-level kernel routines for RV32, including: - startup and initialization logic - context save/restore implementations - interrupt control and scheduler entry - thread stack build and system return paths - timer interrupt handling - made it complient as per new risc-v64/gnu & threadx style - added reademe for risc-v32/gnu port These changes provide full low-level support needed to run ThreadX on RISC-V32 targets. Signed-off-by: Akif Ejaz --- cmake/riscv32-unknown-elf.cmake | 29 ++ cmake/riscv32_gnu.cmake | 12 + ports/risc-v32/gnu/CMakeLists.txt | 19 + ports/risc-v32/gnu/inc/tx_port.h | 291 ++++++++++++ ports/risc-v32/gnu/readme_threadx.txt | 432 ++++++++++++++++++ .../gnu/src/tx_initialize_low_level.S | 118 +++++ .../gnu/src/tx_thread_context_restore.S | 416 +++++++++++++++++ .../risc-v32/gnu/src/tx_thread_context_save.S | 277 +++++++++++ .../gnu/src/tx_thread_interrupt_control.S | 94 ++++ ports/risc-v32/gnu/src/tx_thread_schedule.S | 324 +++++++++++++ .../risc-v32/gnu/src/tx_thread_stack_build.S | 227 +++++++++ .../gnu/src/tx_thread_system_return.S | 174 +++++++ ports/risc-v32/gnu/src/tx_timer_interrupt.S | 210 +++++++++ 13 files changed, 2623 insertions(+) create mode 100644 cmake/riscv32-unknown-elf.cmake create mode 100644 cmake/riscv32_gnu.cmake create mode 100644 ports/risc-v32/gnu/CMakeLists.txt create mode 100644 ports/risc-v32/gnu/inc/tx_port.h create mode 100644 ports/risc-v32/gnu/readme_threadx.txt create mode 100644 ports/risc-v32/gnu/src/tx_initialize_low_level.S create mode 100644 ports/risc-v32/gnu/src/tx_thread_context_restore.S create mode 100644 ports/risc-v32/gnu/src/tx_thread_context_save.S create mode 100644 ports/risc-v32/gnu/src/tx_thread_interrupt_control.S create mode 100644 ports/risc-v32/gnu/src/tx_thread_schedule.S create mode 100644 ports/risc-v32/gnu/src/tx_thread_stack_build.S create mode 100644 ports/risc-v32/gnu/src/tx_thread_system_return.S create mode 100644 ports/risc-v32/gnu/src/tx_timer_interrupt.S diff --git a/cmake/riscv32-unknown-elf.cmake b/cmake/riscv32-unknown-elf.cmake new file mode 100644 index 00000000..cfd9f7ea --- /dev/null +++ b/cmake/riscv32-unknown-elf.cmake @@ -0,0 +1,29 @@ +# Toolchain settings +set(CMAKE_C_COMPILER riscv32-unknown-elf-gcc) +set(CMAKE_CXX_COMPILER riscv32-unknown-elf-g++) +set(AS riscv32-unknown-elf-as) +set(AR riscv32-unknown-elf-ar) +set(OBJCOPY riscv32-unknown-elf-objcopy) +set(OBJDUMP riscv32-unknown-elf-objdump) +set(SIZE riscv32-unknown-elf-size) + +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY) + +# this makes the test compiles use static library option so that we don't need to pre-set linker flags and scripts +set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) + +set(CMAKE_C_FLAGS "${CFLAGS}" CACHE INTERNAL "c compiler flags") +set(CMAKE_CXX_FLAGS "${CXXFLAGS}" CACHE INTERNAL "cxx compiler flags") +set(CMAKE_ASM_FLAGS "${ASFLAGS} -D__ASSEMBLER__ -D__riscv_float_abi_single" CACHE INTERNAL "asm compiler flags") +set(CMAKE_EXE_LINKER_FLAGS "${LDFLAGS}" CACHE INTERNAL "exe link flags") + +SET(CMAKE_C_FLAGS_DEBUG "-Og -g -ggdb3" CACHE INTERNAL "c debug compiler flags") +SET(CMAKE_CXX_FLAGS_DEBUG "-Og -g -ggdb3" CACHE INTERNAL "cxx debug compiler flags") +SET(CMAKE_ASM_FLAGS_DEBUG "-g -ggdb3" CACHE INTERNAL "asm debug compiler flags") + +SET(CMAKE_C_FLAGS_RELEASE "-O3" CACHE INTERNAL "c release compiler flags") +SET(CMAKE_CXX_FLAGS_RELEASE "-O3" CACHE INTERNAL "cxx release compiler flags") +SET(CMAKE_ASM_FLAGS_RELEASE "" CACHE INTERNAL "asm release compiler flags") diff --git a/cmake/riscv32_gnu.cmake b/cmake/riscv32_gnu.cmake new file mode 100644 index 00000000..617b1276 --- /dev/null +++ b/cmake/riscv32_gnu.cmake @@ -0,0 +1,12 @@ +# Name of the target +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_PROCESSOR risc-v32) + +set(THREADX_ARCH "risc-v32") +set(THREADX_TOOLCHAIN "gnu") +set(ARCH_FLAGS "-g -march=rv32gc -mabi=ilp32d -mcmodel=medany") +set(CFLAGS "${ARCH_FLAGS}") +set(ASFLAGS "${ARCH_FLAGS}") +set(LDFLAGS "${ARCH_FLAGS}") + +include(${CMAKE_CURRENT_LIST_DIR}/riscv32-unknown-elf.cmake) diff --git a/ports/risc-v32/gnu/CMakeLists.txt b/ports/risc-v32/gnu/CMakeLists.txt new file mode 100644 index 00000000..9357c697 --- /dev/null +++ b/ports/risc-v32/gnu/CMakeLists.txt @@ -0,0 +1,19 @@ + +target_sources(${PROJECT_NAME} + PRIVATE + # {{BEGIN_TARGET_SOURCES}} + ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S + # {{END_TARGET_SOURCES}} +) + +target_include_directories(${PROJECT_NAME} + PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/inc +) diff --git a/ports/risc-v32/gnu/inc/tx_port.h b/ports/risc-v32/gnu/inc/tx_port.h new file mode 100644 index 00000000..f4dd75af --- /dev/null +++ b/ports/risc-v32/gnu/inc/tx_port.h @@ -0,0 +1,291 @@ +/*************************************************************************** + * Copyright (c) 2025 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h RISC-V32/GNU */ +/* 6.4.x */ +/* */ +/* AUTHOR */ +/* */ +/* Akif Ejaz, 10xEngineers */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + +#ifndef __ASSEMBLER__ + +/* Include for memset. */ +#include + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif /* TX_INCLUDE_USER_DEFINE_FILE */ + +#endif /* __ASSEMBLER__ */ + + +/* Define ThreadX basic types for this port. */ + +#define VOID void + +#ifndef __ASSEMBLER__ +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long long ULONG64; +typedef short SHORT; +typedef unsigned short USHORT; +#define ULONG64_DEFINED +#endif /* __ASSEMBLER__ */ + + + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 1024 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX RISC-V port. */ + +#define TX_INT_DISABLE 0x00000000 /* Disable interrupts value */ +#define TX_INT_ENABLE 0x00000008 /* Enable interrupt value */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +/* Expose helper used to perform an atomic read/modify/write of mstatus. + The helper composes and returns the posture per ThreadX contract. */ +#ifndef __ASSEMBLER__ +UINT _tx_thread_interrupt_control(UINT new_posture); +#endif + +#ifdef TX_DISABLE_INLINE + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE __asm__ volatile("csrrci %0, mstatus, 8" : "=r" (interrupt_save) :: "memory"); +#define TX_RESTORE { \ + unsigned long _temp_mstatus; \ + __asm__ volatile( \ + "csrc mstatus, 8\n" \ + "andi %0, %1, 8\n" \ + "csrs mstatus, %0" \ + : "=&r" (_temp_mstatus) \ + : "r" (interrupt_save) \ + : "memory"); \ + } + +#else + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); +#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); + +#endif /* TX_DISABLE_INLINE */ + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifndef __ASSEMBLER__ +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) 2024 Microsoft Corporation. * ThreadX RISC-V32/GNU Version 6.4.2 *"; +#else +extern CHAR _tx_version_id[]; +#endif /* TX_THREAD_INIT */ +#endif /* __ASSEMBLER__ */ + +#endif /* TX_PORT_H */ \ No newline at end of file diff --git a/ports/risc-v32/gnu/readme_threadx.txt b/ports/risc-v32/gnu/readme_threadx.txt new file mode 100644 index 00000000..e4f16971 --- /dev/null +++ b/ports/risc-v32/gnu/readme_threadx.txt @@ -0,0 +1,432 @@ + Eclipse Foundation's RTOS, ThreadX for RISC-V32 + + Using the GNU Tools + + +1. Building the ThreadX run-time Library + +Prerequisites +- Install a RISC-V32 bare-metal GNU toolchain with riscv32-unknown-elf prefix +- Common source: https://github.com/riscv-collab/riscv-gnu-toolchain + +Verify the toolchain: + riscv32-unknown-elf-gcc --version + riscv32-unknown-elf-objdump --version + +CMake-based build (recommended) + +From the ThreadX top-level directory: + + cmake -Bbuild -GNinja -DCMAKE_TOOLCHAIN_FILE=cmake/riscv32_gnu.cmake . + cmake --build ./build/ + +This uses cmake/riscv32_gnu.cmake and ports/risc-v32/gnu/CMakeLists.txt to +configure the cross-compiler flags and produce the ThreadX run-time library +and example binaries. + +Example build script + +The example demonstration contains a build script. See: + + ports/risc-v32/gnu/example_build/qemu_virt/build_libthreadx.sh + +This script builds the library and the demo application kernel.elf. + + +2. Demonstration System (QEMU) + +The provided example is targeted at QEMU's virt platform. After building the +example, the produced kernel.elf can be executed in QEMU: + + qemu-system-riscv32 -nographic -smp 1 -bios none -m 128M -machine virt -kernel kernel.elf + +Typical QEMU features used: +- Single-core CPU +- UART serial console +- PLIC (Platform-Level Interrupt Controller) +- CLINT (Core-Local Interruptor) for timer + + +3. System Initialization + +Entry Point + +The example startup code begins at the _start label in entry.s. This startup +code performs hardware initialization including: +- Check hart ID (only hart 0 continues; others enter WFI loop) +- Zero general-purpose registers +- Set up initial stack pointer +- Clear BSS section +- Jump to main() + +Low-Level Port Initialization (tx_initialize_low_level.S) + +The _tx_initialize_low_level function: +- Saves the system stack pointer to _tx_thread_system_stack_ptr +- Records first free RAM address from __tx_free_memory_start symbol +- Initializes floating-point control/status register (FCSR) if floating point enabled + +Board Initialization (board.c) + +After tx_initialize_low_level returns, main() calls board_init() to: +- Initialize PLIC (Platform-Level Interrupt Controller) +- Initialize UART +- Initialize hardware timer (CLINT) +- Set trap vector (mtvec) to point to trap handler + + +4. Register Usage and Stack Frames + +The RISC-V32 ABI defines t0-t6 and a0-a7 as caller-saved (scratch) registers. +All other registers used by a function must be preserved by the function. + +ThreadX takes advantage of this: when a context switch happens during a +function call, only the non-scratch registers need to be saved. + +Stack Frame Types + +Two types of stack frames exist: + +A. Interrupt Frame (stack type = 1) + Created when an interrupt occurs during thread execution. + Saves all registers including caller-saved registers. + Size: 65*4 = 260 bytes (with FP), or 32*4 = 128 bytes (without FP) + +B. Solicited Frame (stack type = 0) + Created when a thread voluntarily yields via ThreadX service calls. + Saves only callee-saved registers (s0-s11) and mstatus. + Size: 29*4 = 116 bytes (with FP), or 16*4 = 64 bytes (without FP) + + +Stack Layout for Interrupt Frame (with FP enabled): + + Index Offset Register Description + ───────────────────────────────────────────────── + 0 0x00 -- Stack type (1 = interrupt) + 1 0x04 s11 Preserved register + 2 0x08 s10 Preserved register + 3 0x0C s9 Preserved register + 4 0x10 s8 Preserved register + 5 0x14 s7 Preserved register + 6 0x18 s6 Preserved register + 7 0x1C s5 Preserved register + 8 0x20 s4 Preserved register + 9 0x24 s3 Preserved register + 10 0x28 s2 Preserved register + 11 0x2C s1 Preserved register + 12 0x30 s0 Preserved register + 13 0x34 t6 Scratch register + 14 0x38 t5 Scratch register + 15 0x3C t4 Scratch register + 16 0x40 t3 Scratch register + 17 0x44 t2 Scratch register + 18 0x48 t1 Scratch register + 19 0x4C t0 Scratch register + 20 0x50 a7 Argument register + 21 0x54 a6 Argument register + 22 0x58 a5 Argument register + 23 0x5C a4 Argument register + 24 0x60 a3 Argument register + 25 0x64 a2 Argument register + 26 0x68 a1 Argument register + 27 0x6C a0 Argument register + 28 0x70 ra Return address + 29 0x74 -- Reserved + 30 0x78 mepc Machine exception PC + 31-46 0x7C-0xB8 fs0-fs7 Preserved FP registers* + 47-62 0xBC-0xF8 ft0-ft11 Scratch FP registers* + 63 0xFC fcsr FP control/status register + ───────────────────────────────────────────────── + *Note: In ilp32d ABI, FP registers are 8 bytes each, but current + port implementation uses 4-byte indexing which may cause + overlap if fsd/fld are used. + + +5. Interrupt Handling + +Machine Mode Operation + +ThreadX operates in machine mode (M-mode), the highest privilege level. +All interrupts and exceptions trap to machine mode. + +Interrupt Sources + +1. Machine Timer Interrupt (MTI): + - Triggered by CLINT when mtime >= mtimecmp + - Handled by _tx_timer_interrupt (src/tx_timer_interrupt.S) + - Called from trap handler in trap.c + +2. External Interrupts (MEI): + - Routed through PLIC + - Handler in trap.c calls registered ISR callbacks + +3. Software Interrupts (MSI): + - Supported but not actively used in this port + +Interrupt Flow + +1. Hardware trap entry (automatic): + - mepc <- PC (address of interrupted instruction) + - mcause <- exception/interrupt code + - mstatus.MPIE <- mstatus.MIE (save interrupt-enable state) + - mstatus.MIE <- 0 (disable interrupts) + - mstatus.MPP <- Machine mode + - PC <- mtvec (points to trap_entry in entry.s) + +2. Trap entry (entry.s): + - Allocates interrupt stack frame (32*4 or 65*4 bytes depending on FP) + - Saves RA (x1) on stack + - Calls _tx_thread_context_save + +3. Context save (_tx_thread_context_save.S): + - Increments _tx_thread_system_state (nested interrupt counter) + - If nested interrupt: saves remaining registers and returns to ISR + - If first interrupt: saves full context, switches to system stack + +4. Trap handler (trap.c): + - Examines mcause to determine interrupt type + - Dispatches to appropriate handler (_tx_timer_interrupt or PLIC handler) + - Returns to context restore + +5. Context restore (_tx_thread_context_restore.S): + - Decrements _tx_thread_system_state + - Checks if preemption needed + - Restores thread context or switches to next ready thread via scheduler + - Returns to interrupted thread or executes new thread + + +Interrupt Control Macros + +TX_DISABLE and TX_RESTORE macros atomically manage the MIE bit in mstatus: + + TX_DISABLE: Saves and clears MIE bit via csrrci (CSR read-clear immediate) + TX_RESTORE: Restores only MIE bit via csrrs (CSR read-set) + Other mstatus bits remain unchanged + +These are defined in ports/risc-v32/gnu/inc/tx_port.h and use the +_tx_thread_interrupt_control() function. + + +6. Thread Scheduling and Context Switching + +Thread Scheduler (src/tx_thread_schedule.S) + +The scheduler: +1. Enables interrupts while waiting for next thread +2. Spins until _tx_thread_execute_ptr becomes non-NULL +3. Disables interrupts (critical section) +4. Sets _tx_thread_current_ptr = _tx_thread_execute_ptr +5. Increments thread's run count +6. Switches to thread's stack +7. Determines stack frame type and restores context: + - Interrupt frame: full context restored, returns via mret + - Solicited frame: minimal context restored, returns via ret + +Initial Thread Stack Frame (src/tx_thread_stack_build.S) + +New threads start with a fake interrupt frame containing: +- All registers initialized to 0 +- ra (x1) = 0 +- mepc = entry function pointer +- Stack type = 1 (interrupt frame) +- Floating-point registers initialized based on ABI + + +7. Port Configuration and Macros + +Default Configurations (in ports/risc-v32/gnu/inc/tx_port.h): + + TX_MINIMUM_STACK 1024 /* Minimum thread stack size */ + TX_TIMER_THREAD_STACK_SIZE 1024 /* Timer thread stack size */ + TX_TIMER_THREAD_PRIORITY 0 /* Timer thread priority */ + TX_MAX_PRIORITIES 32 /* Must be multiple of 32 */ + +These can be overridden in tx_user.h or on the compiler command line. + + +8. Build Configuration + +CMake Toolchain File: cmake/riscv32_gnu.cmake + +Compiler Flags: + -march=rv32gc RV32 with IMAFD+C extensions + -mabi=ilp32d 32-bit integers/pointers, double-precision FP in registers + -mcmodel=medany ±2GB addressability + -D__ASSEMBLER__ For assembly files + +ABI Selection + +The port uses ilp32d ABI which includes: +- 32-bit integers and pointers +- Double-precision floating-point arguments in registers +- Floating-point registers f0-f31 + +When building with floating-point ABI: +- FP registers and FCSR are saved/restored in context switches +- Stack frames expand from 32*REGBYTES to 65*REGBYTES +- Conditional compilation uses __riscv_float_abi_double / __riscv_float_abi_single + + +9. File Organization + +Port-specific files (ports/risc-v32/gnu/): + +Core assembly files (src/): + - tx_initialize_low_level.S Initial setup and system state + - tx_thread_context_save.S Save context on interrupt entry + - tx_thread_context_restore.S Restore context on interrupt exit + - tx_thread_schedule.S Thread scheduler + - tx_thread_system_return.S Solicited context save for voluntary yield + - tx_thread_stack_build.S Build initial stack frame for new thread + - tx_thread_interrupt_control.S Interrupt enable/disable control + - tx_timer_interrupt.S Timer interrupt handler + +Header file (inc/): + - tx_port.h Port-specific defines and macros + +Example files (example_build/qemu_virt/): + - entry.s Startup code, trap entry point + - board.c, uart.c, hwtimer.c Platform-specific initialization + - plic.c PLIC interrupt controller driver + - trap.c Trap/exception dispatcher + - link.lds Linker script for QEMU virt + - build_libthreadx.sh Build script + + +10. Linker Script Requirements + +The linker script must provide: + +1. Entry point: + ENTRY(_start) + +2. Memory layout: + - .text section (code) + - .rodata section (read-only data) + - .data section (initialized data) + - .bss section (uninitialized data) + +3. Symbols: + - _end: First free memory address (used by ThreadX allocation) + - _bss_start, _bss_end: For zero initialization + - Initial stack space (example: 4KB) + +4. Alignment: + - 16-byte alignment throughout (RISC-V requirement) + +Example from QEMU virt build: + + SECTIONS + { + . = 0x80000000; /* QEMU virt base address */ + + .text : { *(.text .text.*) } + .rodata : { *(.rodata .rodata.*) } + .data : { *(.data .data.*) } + .bss : { *(.bss .bss.*) } + + .stack : { + . = ALIGN(4096); + _sysstack_start = .; + . += 0x1000; /* 4KB initial stack */ + _sysstack_end = .; + } + + PROVIDE(_end = .); + } + + +11. Floating-Point Support + +When building with ilp32d ABI and FP enabled: + +- FP registers f0-f31 and FCSR are saved/restored during context switches +- Stack frames increase from 32*REGBYTES to 65*REGBYTES (128 to 260 bytes) +- MSTATUS.FS (floating-point state) field is set to indicate dirty FP state + +Stack frame differences: +- Without FP: 32*4 = 128 bytes (interrupt), 16*4 = 64 bytes (solicited) +- With FP: 65*4 = 260 bytes (interrupt), 29*4 = 116 bytes (solicited) + + +12. Performance and Debugging + +Performance Optimization + +Build optimizations: +- Use -O2 or -O3 for production (example uses -O0 for debugging) +- Enable -Wl,--gc-sections to remove unused code +- Define TX_DISABLE_ERROR_CHECKING to remove parameter checks +- Consider -flto for link-time optimization + +Debugging with QEMU and GDB + +Start QEMU in debug mode: + qemu-system-riscv32 -nographic -smp 1 -bios none -m 128M \ + -machine virt -kernel kernel.elf -s -S + + -s: Enable GDB server on TCP port 1234 + -S: Pause at startup waiting for GDB + +Connect GDB: + riscv32-unknown-elf-gdb kernel.elf + (gdb) target remote :1234 + (gdb) break main + (gdb) continue + +Useful GDB commands: + (gdb) info registers # View general registers + (gdb) info all-registers # Include CSR and FP registers + (gdb) p/x $mstatus # View machine status register + (gdb) x/32xw $sp # Examine stack memory + (gdb) p *_tx_thread_current_ptr # View current thread control block + + +13. Platform-Specific Notes (QEMU virt) + +PLIC Configuration + +The PLIC (Platform-Level Interrupt Controller) is memory-mapped at 0x0C000000: + +- Enables up to 1024 interrupt sources +- Supports priority levels 0-7 (0 = disabled) +- Requires per-hart priority threshold and enable register configuration + +Example PLIC usage (from plic.c): + plic_irq_enable(irq_number); # Enable specific interrupt + plic_prio_set(irq_number, priority);# Set priority level + +CLINT Configuration + +The CLINT (Core-Local Interruptor) is memory-mapped at 0x02000000: + +- CLINT_MSIP(hartid): 0x0000 + 4*hartid (software interrupt) +- CLINT_MTIMECMP(hartid): 0x4000 + 8*hartid (timer compare) +- CLINT_MTIME: 0xBFF8 (timer value, read-only) + +Timer frequency is platform-dependent (example uses 10MHz). + +Multi-Core Considerations + +The current port is single-core focused: +- Only hart 0 continues from reset; others enter WFI loop +- _tx_thread_system_state is a global variable +- No per-hart data structures + + +14. Revision History + +For generic code revision information, refer to readme_threadx_generic.txt. + +The following details the revision history for this RISC-V32 GNU port: + +01-26-2026 Akif Ejaz Brief rewrite with accurate + technical details matching implementation, + register naming per RISC-V ABI, and + complete interrupt flow documentation + (Adapted from RISC-V64 port) + + +Copyright (c) 1996-2026 Microsoft Corporation + +https://azure.com/rtos diff --git a/ports/risc-v32/gnu/src/tx_initialize_low_level.S b/ports/risc-v32/gnu/src/tx_initialize_low_level.S new file mode 100644 index 00000000..70fefc84 --- /dev/null +++ b/ports/risc-v32/gnu/src/tx_initialize_low_level.S @@ -0,0 +1,118 @@ +/*************************************************************************** + * Copyright (c) 2025 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .section .data + .global __tx_free_memory_start +__tx_free_memory_start: + + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level RISC-V32/GNU */ +/* 6.4.x */ +/* AUTHOR */ +/* */ +/* Akif Ejaz, 10xEngineers */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ + .global _tx_initialize_low_level + .weak _tx_initialize_low_level +_tx_initialize_low_level: + + /* Save the system stack pointer. */ + /* _tx_thread_system_stack_ptr = sp; */ + + la t0, _tx_thread_system_stack_ptr // Pickup address of system stack ptr + sw sp, 0(t0) // Save system stack pointer + + /* Pickup first free address. */ + /* _tx_initialize_unused_memory(__tx_free_memory_start); */ + + la t0, __tx_free_memory_start // Pickup first free address + la t1, _tx_initialize_unused_memory // Pickup address of unused memory + sw t0, 0(t1) // Save unused memory address + + /* Initialize floating point control/status register if floating point is enabled. */ +#ifdef __riscv_flen + li t0, 0 + csrw fcsr, t0 // Clear FP control/status register +#endif + + ret + +/* Timer Interrupt Handler Note: + Platform-specific implementations must provide their own timer ISR. + The timer interrupt handler should follow this execution flow: + + 1. Disable interrupts (if not done by hardware exception entry) + 2. Allocate interrupt stack frame (65*4 bytes with FP, 32*4 bytes without) + 3. Save RA (x1) on the stack at offset 28*4 + 4. Call _tx_thread_context_save to save thread context + 5. Call _tx_timer_interrupt to process the timer tick + 6. Call _tx_thread_context_restore to resume execution (does not return) + + Example (for CLINT timer): + + _tx_timer_interrupt_handler: + addi sp, sp, -32*4 + sw ra, 28*4(sp) + call _tx_thread_context_save + call _tx_timer_interrupt + j _tx_thread_context_restore + + The port assumes Machine mode (M-mode) execution. + For Supervisor mode (S-mode), use sstatus and SIE/SPIE instead of mstatus. + See the RISC-V Privileged Specification for more details. */ \ No newline at end of file diff --git a/ports/risc-v32/gnu/src/tx_thread_context_restore.S b/ports/risc-v32/gnu/src/tx_thread_context_restore.S new file mode 100644 index 00000000..ba553a46 --- /dev/null +++ b/ports/risc-v32/gnu/src/tx_thread_context_restore.S @@ -0,0 +1,416 @@ +/*************************************************************************** + * Copyright (c) 2025 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore RISC-V32/GNU */ +/* 6.4.x */ +/* AUTHOR */ +/* */ +/* Akif Ejaz, 10xEngineers */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_restore(VOID) +{ */ + .global _tx_thread_context_restore +_tx_thread_context_restore: + + /* Lockout interrupts. */ + + csrci mstatus, 0x08 // Disable interrupts (MIE bit 3) + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + call _tx_execution_isr_exit // Call the ISR execution exit function +#endif + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) + { */ + + la t0, _tx_thread_system_state // Pickup addr of nested interrupt count + lw t1, 0(t0) // Pickup nested interrupt count + addi t1, t1, -1 // Decrement the nested interrupt counter + sw t1, 0(t0) // Store new nested count + beqz t1, _tx_thread_not_nested_restore // If 0, not nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + /* Recover floating point registers. */ +#if defined(__riscv_float_abi_single) + flw f0, 31*4(sp) // Recover ft0 + flw f1, 32*4(sp) // Recover ft1 + flw f2, 33*4(sp) // Recover ft2 + flw f3, 34*4(sp) // Recover ft3 + flw f4, 35*4(sp) // Recover ft4 + flw f5, 36*4(sp) // Recover ft5 + flw f6, 37*4(sp) // Recover ft6 + flw f7, 38*4(sp) // Recover ft7 + flw f10, 41*4(sp) // Recover fa0 + flw f11, 42*4(sp) // Recover fa1 + flw f12, 43*4(sp) // Recover fa2 + flw f13, 44*4(sp) // Recover fa3 + flw f14, 45*4(sp) // Recover fa4 + flw f15, 46*4(sp) // Recover fa5 + flw f16, 47*4(sp) // Recover fa6 + flw f17, 48*4(sp) // Recover fa7 + flw f28, 59*4(sp) // Recover ft8 + flw f29, 60*4(sp) // Recover ft9 + flw f30, 61*4(sp) // Recover ft10 + flw f31, 62*4(sp) // Recover ft11 + lw t0, 63*4(sp) // Recover fcsr + csrw fcsr, t0 // Restore fcsr +#elif defined(__riscv_float_abi_double) + fld f0, 31*4(sp) // Recover ft0 + fld f1, 32*4(sp) // Recover ft1 + fld f2, 33*4(sp) // Recover ft2 + fld f3, 34*4(sp) // Recover ft3 + fld f4, 35*4(sp) // Recover ft4 + fld f5, 36*4(sp) // Recover ft5 + fld f6, 37*4(sp) // Recover ft6 + fld f7, 38*4(sp) // Recover ft7 + fld f10, 41*4(sp) // Recover fa0 + fld f11, 42*4(sp) // Recover fa1 + fld f12, 43*4(sp) // Recover fa2 + fld f13, 44*4(sp) // Recover fa3 + fld f14, 45*4(sp) // Recover fa4 + fld f15, 46*4(sp) // Recover fa5 + fld f16, 47*4(sp) // Recover fa6 + fld f17, 48*4(sp) // Recover fa7 + fld f28, 59*4(sp) // Recover ft8 + fld f29, 60*4(sp) // Recover ft9 + fld f30, 61*4(sp) // Recover ft10 + fld f31, 62*4(sp) // Recover ft11 + lw t0, 63*4(sp) // Recover fcsr + csrw fcsr, t0 // Restore fcsr +#endif + + /* Recover standard registers. */ + + /* Restore registers, + Skip global pointer because that does not change. + Also skip the saved registers since they have been restored by any function we called, + except s0 since we use it ourselves. */ + + lw t0, 30*4(sp) // Recover mepc + csrw mepc, t0 // Setup mepc + + /* Compose mstatus via read/modify/write to avoid clobbering unrelated bits. + Set MPIE and restore MPP to Machine, preserve other fields. */ + + csrr t1, mstatus + + /* Clear MPP/MPIE/MIE bits in t1 then set desired values. */ + + li t2, 0x1888 // MPP(0x1800) | MPIE(0x80) | MIE(0x08) + li t3, 0x1800 // Set MPP to Machine mode (bits 12:11) + + /* Construct new mstatus in t1: clear mask bits, set MPP/MPIE and optionally FP bit, + preserve everything except the bits we will modify. */ + + li t4, ~0x1888 // Clear mask for MPP/MPIE/MIE + and t1, t1, t4 + or t1, t1, t3 + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + li t0, 0x2000 // Set FS bits (bits 14:13 to 01) for FP state + or t1, t1, t0 +#endif + csrw mstatus, t1 // Update mstatus safely + + lw ra, 28*4(sp) // Recover return address + lw t0, 19*4(sp) // Recover t0 + lw t1, 18*4(sp) // Recover t1 + lw t2, 17*4(sp) // Recover t2 + lw s0, 12*4(sp) // Recover s0 + lw a0, 27*4(sp) // Recover a0 + lw a1, 26*4(sp) // Recover a1 + lw a2, 25*4(sp) // Recover a2 + lw a3, 24*4(sp) // Recover a3 + lw a4, 23*4(sp) // Recover a4 + lw a5, 22*4(sp) // Recover a5 + lw a6, 21*4(sp) // Recover a6 + lw a7, 20*4(sp) // Recover a7 + lw t3, 16*4(sp) // Recover t3 + lw t4, 15*4(sp) // Recover t4 + lw t5, 14*4(sp) // Recover t5 + lw t6, 13*4(sp) // Recover t6 + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, 65*4 // Recover stack frame - with floating point enabled +#else + addi sp, sp, 32*4 // Recover stack frame - without floating point enabled +#endif + mret // Return to point of interrupt + + /* } */ +_tx_thread_not_nested_restore: + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + || (_tx_thread_preempt_disable)) + { */ + + la t0, _tx_thread_current_ptr // Pickup current thread pointer address + lw t1, 0(t0) // Pickup current thread pointer + + beqz t1, _tx_thread_idle_system_restore // If NULL, idle system restore + + + la t0, _tx_thread_preempt_disable // Pickup preempt disable flag address + lw t2, 0(t0) // Pickup preempt disable flag (UINT) + + bgtz t2, _tx_thread_no_preempt_restore // If set, restore interrupted thread + + + la t0, _tx_thread_execute_ptr // Pickup thread execute pointer address + lw t2, 0(t0) // Pickup thread execute pointer + + bne t1, t2, _tx_thread_preempt_restore // If higher-priority thread is ready, preempt + + +_tx_thread_no_preempt_restore: + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* sp = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + lw sp, 8(t1) // Switch back to thread's stack + + /* Recover floating point registers. */ +#if defined(__riscv_float_abi_single) + flw f0, 31*4(sp) // Recover ft0 + flw f1, 32*4(sp) // Recover ft1 + flw f2, 33*4(sp) // Recover ft2 + flw f3, 34*4(sp) // Recover ft3 + flw f4, 35*4(sp) // Recover ft4 + flw f5, 36*4(sp) // Recover ft5 + flw f6, 37*4(sp) // Recover ft6 + flw f7, 38*4(sp) // Recover ft7 + flw f10, 41*4(sp) // Recover fa0 + flw f11, 42*4(sp) // Recover fa1 + flw f12, 43*4(sp) // Recover fa2 + flw f13, 44*4(sp) // Recover fa3 + flw f14, 45*4(sp) // Recover fa4 + flw f15, 46*4(sp) // Recover fa5 + flw f16, 47*4(sp) // Recover fa6 + flw f17, 48*4(sp) // Recover fa7 + flw f28, 59*4(sp) // Recover ft8 + flw f29, 60*4(sp) // Recover ft9 + flw f30, 61*4(sp) // Recover ft10 + flw f31, 62*4(sp) // Recover ft11 + lw t0, 63*4(sp) // Recover fcsr + csrw fcsr, t0 // Restore fcsr +#elif defined(__riscv_float_abi_double) + fld f0, 31*4(sp) // Recover ft0 + fld f1, 32*4(sp) // Recover ft1 + fld f2, 33*4(sp) // Recover ft2 + fld f3, 34*4(sp) // Recover ft3 + fld f4, 35*4(sp) // Recover ft4 + fld f5, 36*4(sp) // Recover ft5 + fld f6, 37*4(sp) // Recover ft6 + fld f7, 38*4(sp) // Recover ft7 + fld f10, 41*4(sp) // Recover fa0 + fld f11, 42*4(sp) // Recover fa1 + fld f12, 43*4(sp) // Recover fa2 + fld f13, 44*4(sp) // Recover fa3 + fld f14, 45*4(sp) // Recover fa4 + fld f15, 46*4(sp) // Recover fa5 + fld f16, 47*4(sp) // Recover fa6 + fld f17, 48*4(sp) // Recover fa7 + fld f28, 59*4(sp) // Recover ft8 + fld f29, 60*4(sp) // Recover ft9 + fld f30, 61*4(sp) // Recover ft10 + fld f31, 62*4(sp) // Recover ft11 + lw t0, 63*4(sp) // Recover fcsr + csrw fcsr, t0 // Restore fcsr +#endif + + /* Recover the saved context and return to the point of interrupt. */ + + /* Recover standard registers. */ + /* Restore registers, + Skip global pointer because that does not change */ + + lw t0, 30*4(sp) // Recover mepc + csrw mepc, t0 // Setup mepc + + /* Compose mstatus via read/modify/write to avoid clobbering unrelated bits. */ + + csrr t1, mstatus + li t2, 0x1888 // MPP(0x1800) | MPIE(0x80) | MIE(0x08) + li t3, 0x1800 // Set MPP to Machine mode + li t4, ~0x1888 // Clear mask for MPP/MPIE/MIE + and t1, t1, t4 + or t1, t1, t3 + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + li t0, 0x2000 // Set FS bits for FP state + or t1, t1, t0 +#endif + csrw mstatus, t1 // Update mstatus safely + + lw ra, 28*4(sp) // Recover return address + lw t0, 19*4(sp) // Recover t0 + lw t1, 18*4(sp) // Recover t1 + lw t2, 17*4(sp) // Recover t2 + lw s0, 12*4(sp) // Recover s0 + lw a0, 27*4(sp) // Recover a0 + lw a1, 26*4(sp) // Recover a1 + lw a2, 25*4(sp) // Recover a2 + lw a3, 24*4(sp) // Recover a3 + lw a4, 23*4(sp) // Recover a4 + lw a5, 22*4(sp) // Recover a5 + lw a6, 21*4(sp) // Recover a6 + lw a7, 20*4(sp) // Recover a7 + lw t3, 16*4(sp) // Recover t3 + lw t4, 15*4(sp) // Recover t4 + lw t5, 14*4(sp) // Recover t5 + lw t6, 13*4(sp) // Recover t6 + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, 65*4 // Recover stack frame - with floating point enabled +#else + addi sp, sp, 32*4 // Recover stack frame - without floating point enabled +#endif + mret // Return to point of interrupt + + /* } + else + { */ +_tx_thread_preempt_restore: + /* Instead of directly activating the thread again, ensure we save the + entire stack frame by saving the remaining registers. */ + + lw t0, 8(t1) // Pickup thread's stack pointer + ori t3, zero, 1 // Build interrupt stack type + sw t3, 0(t0) // Store stack type + + /* Store floating point preserved registers. */ +#ifdef __riscv_float_abi_single + fsw f8, 39*4(t0) // Store fs0 + fsw f9, 40*4(t0) // Store fs1 + fsw f18, 49*4(t0) // Store fs2 + fsw f19, 50*4(t0) // Store fs3 + fsw f20, 51*4(t0) // Store fs4 + fsw f21, 52*4(t0) // Store fs5 + fsw f22, 53*4(t0) // Store fs6 + fsw f23, 54*4(t0) // Store fs7 + fsw f24, 55*4(t0) // Store fs8 + fsw f25, 56*4(t0) // Store fs9 + fsw f26, 57*4(t0) // Store fs10 + fsw f27, 58*4(t0) // Store fs11 +#elif defined(__riscv_float_abi_double) + fsd f8, 39*4(t0) // Store fs0 + fsd f9, 40*4(t0) // Store fs1 + fsd f18, 49*4(t0) // Store fs2 + fsd f19, 50*4(t0) // Store fs3 + fsd f20, 51*4(t0) // Store fs4 + fsd f21, 52*4(t0) // Store fs5 + fsd f22, 53*4(t0) // Store fs6 + fsd f23, 54*4(t0) // Store fs7 + fsd f24, 55*4(t0) // Store fs8 + fsd f25, 56*4(t0) // Store fs9 + fsd f26, 57*4(t0) // Store fs10 + fsd f27, 58*4(t0) // Store fs11 +#endif + + /* Store standard preserved registers. */ + + sw x9, 11*4(t0) // Store s1 + sw x18, 10*4(t0) // Store s2 + sw x19, 9*4(t0) // Store s3 + sw x20, 8*4(t0) // Store s4 + sw x21, 7*4(t0) // Store s5 + sw x22, 6*4(t0) // Store s6 + sw x23, 5*4(t0) // Store s7 + sw x24, 4*4(t0) // Store s8 + sw x25, 3*4(t0) // Store s9 + sw x26, 2*4(t0) // Store s10 + sw x27, 1*4(t0) // Store s11 + // Note: s0 is already stored! + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) + { */ + + la t0, _tx_timer_time_slice // Pickup time slice variable address + lw t2, 0(t0) // Pickup time slice + beqz t2, _tx_thread_dont_save_ts // If 0, skip time slice processing + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice + _tx_timer_time_slice = 0; */ + + sw t2, 24(t1) // Save current time slice + sw x0, 0(t0) // Clear global time slice + + + /* } */ +_tx_thread_dont_save_ts: + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + la t0, _tx_thread_current_ptr // Pickup current thread pointer address + sw x0, 0(t0) // Clear current thread pointer + + /* } */ + +_tx_thread_idle_system_restore: + /* Just return back to the scheduler! */ + j _tx_thread_schedule // Return to scheduler + +/* } */ diff --git a/ports/risc-v32/gnu/src/tx_thread_context_save.S b/ports/risc-v32/gnu/src/tx_thread_context_save.S new file mode 100644 index 00000000..3b7496b3 --- /dev/null +++ b/ports/risc-v32/gnu/src/tx_thread_context_save.S @@ -0,0 +1,277 @@ +/*************************************************************************** + * Copyright (c) 2025 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save RISC-V32/GNU */ +/* 6.4.x */ +/* AUTHOR */ +/* */ +/* Akif Ejaz, 10xEngineers */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_save(VOID) +{ */ + .global _tx_thread_context_save +_tx_thread_context_save: + + /* Upon entry to this routine, RA/x1 has been saved on the stack + and the stack has been already allocated for the entire context: + addi sp, sp, -32*4 (or -65*4) + sw ra, 28*4(sp) + */ + + sw t0, 19*4(sp) // Store t0 + sw t1, 18*4(sp) // Store t1 + + /* Check for a nested interrupt. */ + /* if (_tx_thread_system_state++) + { */ + + la t0, _tx_thread_system_state // Pickup addr of system state var + lw t1, 0(t0) // Pickup system state + addi t1, t1, 1 // Increment system state + sw t1, 0(t0) // Store system state + li t0, 1 + bgt t1, t0, _tx_thread_nested_save // If it's more than 1, nested interrupt + + /* First level interrupt, save the rest of the scratch registers and + check for a thread to preempt. */ + + sw t2, 17*4(sp) // Store t2 + sw s0, 12*4(sp) // Store s0 + sw a0, 27*4(sp) // Store a0 + sw a1, 26*4(sp) // Store a1 + sw a2, 25*4(sp) // Store a2 + sw a3, 24*4(sp) // Store a3 + sw a4, 23*4(sp) // Store a4 + sw a5, 22*4(sp) // Store a5 + sw a6, 21*4(sp) // Store a6 + sw a7, 20*4(sp) // Store a7 + sw t3, 16*4(sp) // Store t3 + sw t4, 15*4(sp) // Store t4 + sw t5, 14*4(sp) // Store t5 + sw t6, 13*4(sp) // Store t6 + + /* Save floating point registers. */ +#if defined(__riscv_float_abi_single) + fsw f0, 31*4(sp) // Store ft0 + fsw f1, 32*4(sp) // Store ft1 + fsw f2, 33*4(sp) // Store ft2 + fsw f3, 34*4(sp) // Store ft3 + fsw f4, 35*4(sp) // Store ft4 + fsw f5, 36*4(sp) // Store ft5 + fsw f6, 37*4(sp) // Store ft6 + fsw f7, 38*4(sp) // Store ft7 + fsw f10, 41*4(sp) // Store fa0 + fsw f11, 42*4(sp) // Store fa1 + fsw f12, 43*4(sp) // Store fa2 + fsw f13, 44*4(sp) // Store fa3 + fsw f14, 45*4(sp) // Store fa4 + fsw f15, 46*4(sp) // Store fa5 + fsw f16, 47*4(sp) // Store fa6 + fsw f17, 48*4(sp) // Store fa7 + fsw f28, 59*4(sp) // Store ft8 + fsw f29, 60*4(sp) // Store ft9 + fsw f30, 61*4(sp) // Store ft10 + fsw f31, 62*4(sp) // Store ft11 + csrr t0, fcsr + sw t0, 63*4(sp) // Store fcsr +#elif defined(__riscv_float_abi_double) + fsd f0, 31*4(sp) // Store ft0 + fsd f1, 32*4(sp) // Store ft1 + fsd f2, 33*4(sp) // Store ft2 + fsd f3, 34*4(sp) // Store ft3 + fsd f4, 35*4(sp) // Store ft4 + fsd f5, 36*4(sp) // Store ft5 + fsd f6, 37*4(sp) // Store ft6 + fsd f7, 38*4(sp) // Store ft7 + fsd f10, 41*4(sp) // Store fa0 + fsd f11, 42*4(sp) // Store fa1 + fsd f12, 43*4(sp) // Store fa2 + fsd f13, 44*4(sp) // Store fa3 + fsd f14, 45*4(sp) // Store fa4 + fsd f15, 46*4(sp) // Store fa5 + fsd f16, 47*4(sp) // Store fa6 + fsd f17, 48*4(sp) // Store fa7 + fsd f28, 59*4(sp) // Store ft8 + fsd f29, 60*4(sp) // Store ft9 + fsd f30, 61*4(sp) // Store ft10 + fsd f31, 62*4(sp) // Store ft11 + csrr t0, fcsr + sw t0, 63*4(sp) // Store fcsr +#endif + + csrr t0, mepc + sw t0, 30*4(sp) // Save it on the stack + + /* Save mstatus. */ + csrr t0, mstatus + sw t0, 29*4(sp) + + la t1, _tx_thread_current_ptr // Pickup address of current thread ptr + lw t2, 0(t1) // Pickup current thread pointer + beqz t2, _tx_thread_idle_system_save // If NULL, idle system was interrupted + + /* Save the current thread's stack pointer and switch to the system stack. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; + sp = _tx_thread_system_stack_ptr; */ + + sw sp, 8(t2) // Save stack pointer + la t0, _tx_thread_system_stack_ptr + lw sp, 0(t0) // Switch to system stack + + /* Call the ISR execution exit function if enabled. */ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + call _tx_execution_isr_enter // Call the ISR execution enter function +#endif + + ret // Return to ISR + +_tx_thread_nested_save: + + /* Nested interrupt! Just save the scratch registers and return to the ISR. */ + + sw t2, 17*4(sp) // Store t2 + sw s0, 12*4(sp) // Store s0 + sw a0, 27*4(sp) // Store a0 + sw a1, 26*4(sp) // Store a1 + sw a2, 25*4(sp) // Store a2 + sw a3, 24*4(sp) // Store a3 + sw a4, 23*4(sp) // Store a4 + sw a5, 22*4(sp) // Store a5 + sw a6, 21*4(sp) // Store a6 + sw a7, 20*4(sp) // Store a7 + sw t3, 16*4(sp) // Store t3 + sw t4, 15*4(sp) // Store t4 + sw t5, 14*4(sp) // Store t5 + sw t6, 13*4(sp) // Store t6 + + /* Save floating point registers. */ +#if defined(__riscv_float_abi_single) + fsw f0, 31*4(sp) // Store ft0 + fsw f1, 32*4(sp) // Store ft1 + fsw f2, 33*4(sp) // Store ft2 + fsw f3, 34*4(sp) // Store ft3 + fsw f4, 35*4(sp) // Store ft4 + fsw f5, 36*4(sp) // Store ft5 + fsw f6, 37*4(sp) // Store ft6 + fsw f7, 38*4(sp) // Store ft7 + fsw f10, 41*4(sp) // Store fa0 + fsw f11, 42*4(sp) // Store fa1 + fsw f12, 43*4(sp) // Store fa2 + fsw f13, 44*4(sp) // Store fa3 + fsw f14, 45*4(sp) // Store fa4 + fsw f15, 46*4(sp) // Store fa5 + fsw f16, 47*4(sp) // Store fa6 + fsw f17, 48*4(sp) // Store fa7 + fsw f28, 59*4(sp) // Store ft8 + fsw f29, 60*4(sp) // Store ft9 + fsw f30, 61*4(sp) // Store ft10 + fsw f31, 62*4(sp) // Store ft11 + csrr t0, fcsr + sw t0, 63*4(sp) // Store fcsr +#elif defined(__riscv_float_abi_double) + fsd f0, 31*4(sp) // Store ft0 + fsd f1, 32*4(sp) // Store ft1 + fsd f2, 33*4(sp) // Store ft2 + fsd f3, 34*4(sp) // Store ft3 + fsd f4, 35*4(sp) // Store ft4 + fsd f5, 36*4(sp) // Store ft5 + fsd f6, 37*4(sp) // Store ft6 + fsd f7, 38*4(sp) // Store ft7 + fsd f10, 41*4(sp) // Store fa0 + fsd f11, 42*4(sp) // Store fa1 + fsd f12, 43*4(sp) // Store fa2 + fsd f13, 44*4(sp) // Store fa3 + fsd f14, 45*4(sp) // Store fa4 + fsd f15, 46*4(sp) // Store fa5 + fsd f16, 47*4(sp) // Store fa6 + fsd f17, 48*4(sp) // Store fa7 + fsd f28, 59*4(sp) // Store ft8 + fsd f29, 60*4(sp) // Store ft9 + fsd f30, 61*4(sp) // Store ft10 + fsd f31, 62*4(sp) // Store ft11 + csrr t0, fcsr + sw t0, 63*4(sp) // Store fcsr +#endif + + csrr t0, mepc + sw t0, 30*4(sp) // Save it on stack + + csrr t0, mstatus + sw t0, 29*4(sp) + + /* Call the ISR execution exit function if enabled. */ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + call _tx_execution_isr_enter // Call the ISR execution enter function +#endif + + ret // Return to ISR + +_tx_thread_idle_system_save: + + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + call _tx_execution_isr_enter // Call the ISR execution enter function +#endif + + /* Interrupt occurred in the scheduling loop. */ + + /* } +} */ +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, 65*4 // Recover stack frame - with floating point enabled +#else + addi sp, sp, 32*4 // Recover the reserved stack space +#endif + ret // Return to calling ISR diff --git a/ports/risc-v32/gnu/src/tx_thread_interrupt_control.S b/ports/risc-v32/gnu/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..8e28cf74 --- /dev/null +++ b/ports/risc-v32/gnu/src/tx_thread_interrupt_control.S @@ -0,0 +1,94 @@ +/*************************************************************************** + * Copyright (c) 2025 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control RISC-V32/GNU */ +/* 6.4.x */ +/* AUTHOR */ +/* */ +/* Akif Ejaz, 10xEngineers */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_control(UINT new_posture) +{ */ + .global _tx_thread_interrupt_control +_tx_thread_interrupt_control: + + /* Pickup current interrupt posture. */ + + csrr a1, mstatus // Pickup mstatus + andi a1, a1, 0x08 // Mask out all but MIE + + /* Check for the new posture. */ + + beqz a0, _tx_thread_interrupt_disable // If 0, disable interrupts + + /* Enable interrupts. */ + + csrsi mstatus, 0x08 // Enable interrupts (MIE bit 3) + j _tx_thread_interrupt_control_exit // Return to caller + +_tx_thread_interrupt_disable: + + /* Disable interrupts. */ + + csrci mstatus, 0x08 // Disable interrupts (MIE bit 3) + +_tx_thread_interrupt_control_exit: + + /* Return the old interrupt posture. */ + + mv a0, a1 // Setup return value + ret // Return to caller + +/* } */ diff --git a/ports/risc-v32/gnu/src/tx_thread_schedule.S b/ports/risc-v32/gnu/src/tx_thread_schedule.S new file mode 100644 index 00000000..edf3462f --- /dev/null +++ b/ports/risc-v32/gnu/src/tx_thread_schedule.S @@ -0,0 +1,324 @@ +/*************************************************************************** + * Copyright (c) 2025 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule RISC-V32/GNU */ +/* 6.4.x */ +/* AUTHOR */ +/* */ +/* Akif Ejaz, 10xEngineers */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_schedule(VOID) +{ */ + .global _tx_thread_schedule +_tx_thread_schedule: + + /* Enable interrupts. */ + + csrsi mstatus, 0x08 // Enable interrupts (MIE bit 3) + + /* Wait for a thread to execute. */ + /* do + { */ +_tx_thread_schedule_loop: + + la t0, _tx_thread_execute_ptr // Pickup address of execute ptr + lw t1, 0(t0) // Pickup execute pointer + bnez t1, _tx_thread_ready_to_run // If non-NULL, a thread is ready to run + +#ifndef TX_NO_WFI + wfi // Wait for interrupt +#endif + j _tx_thread_schedule_loop // Check again + + /* } + while (_tx_thread_execute_ptr == TX_NULL); */ + +_tx_thread_ready_to_run: + + /* At this point, t1 contains the pointer to the thread to execute. + Lockout interrupts. */ + + csrci mstatus, 0x08 // Disable interrupts (MIE bit 3) + + /* Check _tx_thread_execute_ptr again, in case an interrupt occurred + between the check and the disable. */ + + lw t1, 0(t0) // Pickup execute pointer + beqz t1, _tx_thread_schedule_loop // If NULL, go back to wait loop + + /* Yes! We have a thread to execute. */ + /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ + + la t0, _tx_thread_current_ptr // Pickup address of current thread + sw t1, 0(t0) // Setup current thread pointer + + /* Increment the run count for this thread. */ + /* _tx_thread_current_ptr -> tx_thread_run_count++; */ + + lw t2, 4(t1) // Pickup run count + addi t2, t2, 1 // Increment run count + sw t2, 4(t1) // Store run count + + /* Setup time-slice values. */ + /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ + + lw t2, 24(t1) // Pickup thread time-slice + la t3, _tx_timer_time_slice // Pickup address of time-slice + sw t2, 0(t3) // Setup time-slice + + /* Call the thread execution enter function if enabled. */ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + call _tx_execution_thread_enter // Call the thread execution enter function +#endif + + /* Switch to the thread's stack. */ + /* sp = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + lw sp, 8(t1) // Switch to thread stack + + /* Determine the type of stack frame. */ + /* if (*sp) + { */ + + lw t0, 0(sp) // Pickup stack type + beqz t0, _tx_thread_solicited_return // If 0, solicited return + + /* Recover floating point registers. */ +#if defined(__riscv_float_abi_single) + flw f0, 31*4(sp) // Recover ft0 + flw f1, 32*4(sp) // Recover ft1 + flw f2, 33*4(sp) // Recover ft2 + flw f3, 34*4(sp) // Recover ft3 + flw f4, 35*4(sp) // Recover ft4 + flw f5, 36*4(sp) // Recover ft5 + flw f6, 37*4(sp) // Recover ft6 + flw f7, 38*4(sp) // Recover ft7 + flw f8, 39*4(sp) // Recover fs0 + flw f9, 40*4(sp) // Recover fs1 + flw f10, 41*4(sp) // Recover fa0 + flw f11, 42*4(sp) // Recover fa1 + flw f12, 43*4(sp) // Recover fa2 + flw f13, 44*4(sp) // Recover fa3 + flw f14, 45*4(sp) // Recover fa4 + flw f15, 46*4(sp) // Recover fa5 + flw f16, 47*4(sp) // Recover fa6 + flw f17, 48*4(sp) // Recover fa7 + flw f18, 49*4(sp) // Recover fs2 + flw f19, 50*4(sp) // Recover fs3 + flw f20, 51*4(sp) // Recover fs4 + flw f21, 52*4(sp) // Recover fs5 + flw f22, 53*4(sp) // Recover fs6 + flw f23, 54*4(sp) // Recover fs7 + flw f24, 55*4(sp) // Recover fs8 + flw f25, 56*4(sp) // Recover fs9 + flw f26, 57*4(sp) // Recover fs10 + flw f27, 58*4(sp) // Recover fs11 + flw f28, 59*4(sp) // Recover ft8 + flw f29, 60*4(sp) // Recover ft9 + flw f30, 61*4(sp) // Recover ft10 + flw f31, 62*4(sp) // Recover ft11 + lw t0, 63*4(sp) // Recover fcsr + csrw fcsr, t0 // Restore fcsr +#elif defined(__riscv_float_abi_double) + fld f0, 31*4(sp) // Recover ft0 + fld f1, 32*4(sp) // Recover ft1 + fld f2, 33*4(sp) // Recover ft2 + fld f3, 34*4(sp) // Recover ft3 + fld f4, 35*4(sp) // Recover ft4 + fld f5, 36*4(sp) // Recover ft5 + fld f6, 37*4(sp) // Recover ft6 + fld f7, 38*4(sp) // Recover ft7 + fld f8, 39*4(sp) // Recover fs0 + fld f9, 40*4(sp) // Recover fs1 + fld f10, 41*4(sp) // Recover fa0 + fld f11, 42*4(sp) // Recover fa1 + fld f12, 43*4(sp) // Recover fa2 + fld f13, 44*4(sp) // Recover fa3 + fld f14, 45*4(sp) // Recover fa4 + fld f15, 46*4(sp) // Recover fa5 + fld f16, 47*4(sp) // Recover fa6 + fld f17, 48*4(sp) // Recover fa7 + fld f18, 49*4(sp) // Recover fs2 + fld f19, 50*4(sp) // Recover fs3 + fld f20, 51*4(sp) // Recover fs4 + fld f21, 52*4(sp) // Recover fs5 + fld f22, 53*4(sp) // Recover fs6 + fld f23, 54*4(sp) // Recover fs7 + fld f24, 55*4(sp) // Recover fs8 + fld f25, 56*4(sp) // Recover fs9 + fld f26, 57*4(sp) // Recover fs10 + fld f27, 58*4(sp) // Recover fs11 + fld f28, 59*4(sp) // Recover ft8 + fld f29, 60*4(sp) // Recover ft9 + fld f30, 61*4(sp) // Recover ft10 + fld f31, 62*4(sp) // Recover ft11 + lw t0, 63*4(sp) // Recover fcsr + csrw fcsr, t0 // Restore fcsr +#endif + + /* Recover standard registers. */ + + lw t0, 30*4(sp) // Recover mepc + csrw mepc, t0 // Setup mepc + + li t0, 0x1880 // Prepare mstatus: MPP=Machine(0x1800) | MPIE(0x80) +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + li t1, 0x2000 // Set FS bits for FP state + or t0, t0, t1 +#endif + csrw mstatus, t0 // Set mstatus + + lw ra, 28*4(sp) // Recover return address + lw t0, 19*4(sp) // Recover t0 + lw t1, 18*4(sp) // Recover t1 + lw t2, 17*4(sp) // Recover t2 + lw s0, 12*4(sp) // Recover s0 + lw x9, 11*4(sp) // Recover s1 + lw a0, 27*4(sp) // Recover a0 + lw a1, 26*4(sp) // Recover a1 + lw a2, 25*4(sp) // Recover a2 + lw a3, 24*4(sp) // Recover a3 + lw a4, 23*4(sp) // Recover a4 + lw a5, 22*4(sp) // Recover a5 + lw a6, 21*4(sp) // Recover a6 + lw a7, 20*4(sp) // Recover a7 + lw t3, 16*4(sp) // Recover t3 + lw t4, 15*4(sp) // Recover t4 + lw t5, 14*4(sp) // Recover t5 + lw t6, 13*4(sp) // Recover t6 + lw x18, 10*4(sp) // Recover s2 + lw x19, 9*4(sp) // Recover s3 + lw x20, 8*4(sp) // Recover s4 + lw x21, 7*4(sp) // Recover s5 + lw x22, 6*4(sp) // Recover s6 + lw x23, 5*4(sp) // Recover s7 + lw x24, 4*4(sp) // Recover s8 + lw x25, 3*4(sp) // Recover s9 + lw x26, 2*4(sp) // Recover s10 + lw x27, 1*4(sp) // Recover s11 + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, 65*4 // Recover stack frame - with floating point enabled +#else + addi sp, sp, 32*4 // Recover stack frame - without floating point enabled +#endif + mret // Return to thread + +_tx_thread_solicited_return: + + /* Recover floating point registers. */ +#if defined(__riscv_float_abi_single) + flw f8, 15*4(sp) // Recover fs0 + flw f9, 16*4(sp) // Recover fs1 + flw f18, 17*4(sp) // Recover fs2 + flw f19, 18*4(sp) // Recover fs3 + flw f20, 19*4(sp) // Recover fs4 + flw f21, 20*4(sp) // Recover fs5 + flw f22, 21*4(sp) // Recover fs6 + flw f23, 22*4(sp) // Recover fs7 + flw f24, 23*4(sp) // Recover fs8 + flw f25, 24*4(sp) // Recover fs9 + flw f26, 25*4(sp) // Recover fs10 + flw f27, 26*4(sp) // Recover fs11 + lw t0, 27*4(sp) // Recover fcsr + csrw fcsr, t0 // Restore fcsr +#elif defined(__riscv_float_abi_double) + fld f8, 15*4(sp) // Recover fs0 + fld f9, 16*4(sp) // Recover fs1 + fld f18, 17*4(sp) // Recover fs2 + fld f19, 18*4(sp) // Recover fs3 + fld f20, 19*4(sp) // Recover fs4 + fld f21, 20*4(sp) // Recover fs5 + fld f22, 21*4(sp) // Recover fs6 + fld f23, 22*4(sp) // Recover fs7 + fld f24, 23*4(sp) // Recover fs8 + fld f25, 24*4(sp) // Recover fs9 + fld f26, 25*4(sp) // Recover fs10 + fld f27, 26*4(sp) // Recover fs11 + lw t0, 27*4(sp) // Recover fcsr + csrw fcsr, t0 // Restore fcsr +#endif + + /* Recover standard registers. */ + + lw t0, 14*4(sp) // Recover mstatus + csrw mstatus, t0 // Restore mstatus + + lw ra, 13*4(sp) // Recover return address + lw s0, 12*4(sp) // Recover s0 + lw s1, 11*4(sp) // Recover s1 + lw x18, 10*4(sp) // Recover s2 + lw x19, 9*4(sp) // Recover s3 + lw x20, 8*4(sp) // Recover s4 + lw x21, 7*4(sp) // Recover s5 + lw x22, 6*4(sp) // Recover s6 + lw x23, 5*4(sp) // Recover s7 + lw x24, 4*4(sp) // Recover s8 + lw x25, 3*4(sp) // Recover s9 + lw x26, 2*4(sp) // Recover s10 + lw x27, 1*4(sp) // Recover s11 + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, 29*4 // Recover stack frame - with floating point enabled +#else + addi sp, sp, 16*4 // Recover stack frame - without floating point enabled +#endif + ret // Return to thread + +/* } */ diff --git a/ports/risc-v32/gnu/src/tx_thread_stack_build.S b/ports/risc-v32/gnu/src/tx_thread_stack_build.S new file mode 100644 index 00000000..36f9b317 --- /dev/null +++ b/ports/risc-v32/gnu/src/tx_thread_stack_build.S @@ -0,0 +1,227 @@ +/*************************************************************************** + * Copyright (c) 2025 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build RISC-V32/GNU */ +/* 6.4.x */ +/* AUTHOR */ +/* */ +/* Akif Ejaz, 10xEngineers */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +{ */ + .global _tx_thread_stack_build +_tx_thread_stack_build: + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the RISC-V should look like the following after it is built: + Reg Index + Stack Top: 1 0 Interrupt stack frame type + x27 1 Initial s11 + x26 2 Initial s10 + x25 3 Initial s9 + x24 4 Initial s8 + x23 5 Initial s7 + x22 6 Initial s6 + x21 7 Initial s5 + x20 8 Initial s4 + x19 9 Initial s3 + x18 10 Initial s2 + x9 11 Initial s1 + x8 12 Initial s0 + x31 13 Initial t6 + x30 14 Initial t5 + x29 15 Initial t4 + x28 16 Initial t3 + x7 17 Initial t2 + x6 18 Initial t1 + x5 19 Initial t0 + x17 20 Initial a7 + x16 21 Initial a6 + x15 22 Initial a5 + x14 23 Initial a4 + x13 24 Initial a3 + x12 25 Initial a2 + x11 26 Initial a1 + x10 27 Initial a0 + x1 28 Initial ra + -- 29 reserved + mepc 30 Initial mepc +If floating point support: + f0 31 Initial ft0 + f1 32 Initial ft1 + f2 33 Initial ft2 + f3 34 Initial ft3 + f4 35 Initial ft4 + f5 36 Initial ft5 + f6 37 Initial ft6 + f7 38 Initial ft7 + f8 39 Initial fs0 + f9 40 Initial fs1 + f10 41 Initial fa0 + f11 42 Initial fa1 + f12 43 Initial fa2 + f13 44 Initial fa3 + f14 45 Initial fa4 + f15 46 Initial fa5 + f16 47 Initial fa6 + f17 48 Initial fa7 + f18 49 Initial fs2 + f19 50 Initial fs3 + f20 51 Initial fs4 + f21 52 Initial fs5 + f22 53 Initial fs6 + f23 54 Initial fs7 + f24 55 Initial fs8 + f25 56 Initial fs9 + f26 57 Initial fs10 + f27 58 Initial fs11 + f28 59 Initial ft8 + f29 60 Initial ft9 + f30 61 Initial ft10 + f31 62 Initial ft11 + fscr 63 Initial fscr + + Stack Bottom: (higher memory address) */ + + lw t0, 16(a0) // Pickup end of stack area + li t1, ~15 // Build 16-byte alignment mask + and t0, t0, t1 // Make sure 16-byte alignment + + /* Actually build the stack frame. */ + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi t0, t0, -65*4 +#else + addi t0, t0, -32*4 // Allocate space for the stack frame +#endif + li t1, 1 // Build stack type + sw t1, 0*4(t0) // Place stack type on the top + sw zero, 1*4(t0) // Initial s11 + sw zero, 2*4(t0) // Initial s10 + sw zero, 3*4(t0) // Initial s9 + sw zero, 4*4(t0) // Initial s8 + sw zero, 5*4(t0) // Initial s7 + sw zero, 6*4(t0) // Initial s6 + sw zero, 7*4(t0) // Initial s5 + sw zero, 8*4(t0) // Initial s4 + sw zero, 9*4(t0) // Initial s3 + sw zero, 10*4(t0) // Initial s2 + sw zero, 11*4(t0) // Initial s1 + sw zero, 12*4(t0) // Initial s0 + sw zero, 13*4(t0) // Initial t6 + sw zero, 14*4(t0) // Initial t5 + sw zero, 15*4(t0) // Initial t4 + sw zero, 16*4(t0) // Initial t3 + sw zero, 17*4(t0) // Initial t2 + sw zero, 18*4(t0) // Initial t1 + sw zero, 19*4(t0) // Initial t0 + sw zero, 20*4(t0) // Initial a7 + sw zero, 21*4(t0) // Initial a6 + sw zero, 22*4(t0) // Initial a5 + sw zero, 23*4(t0) // Initial a4 + sw zero, 24*4(t0) // Initial a3 + sw zero, 25*4(t0) // Initial a2 + sw zero, 26*4(t0) // Initial a1 + sw zero, 27*4(t0) // Initial a0 + sw zero, 28*4(t0) // Initial ra + sw a1, 30*4(t0) // Initial mepc (thread entry point) +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + sw zero, 31*4(t0) // Initial ft0 + sw zero, 32*4(t0) // Initial ft1 + sw zero, 33*4(t0) // Initial ft2 + sw zero, 34*4(t0) // Initial ft3 + sw zero, 35*4(t0) // Initial ft4 + sw zero, 36*4(t0) // Initial ft5 + sw zero, 37*4(t0) // Initial ft6 + sw zero, 38*4(t0) // Initial ft7 + sw zero, 39*4(t0) // Initial fs0 + sw zero, 40*4(t0) // Initial fs1 + sw zero, 41*4(t0) // Initial fa0 + sw zero, 42*4(t0) // Initial fa1 + sw zero, 43*4(t0) // Initial fa2 + sw zero, 44*4(t0) // Initial fa3 + sw zero, 45*4(t0) // Initial fa4 + sw zero, 46*4(t0) // Initial fa5 + sw zero, 47*4(t0) // Initial fa6 + sw zero, 48*4(t0) // Initial fa7 + sw zero, 49*4(t0) // Initial fs2 + sw zero, 50*4(t0) // Initial fs3 + sw zero, 51*4(t0) // Initial fs4 + sw zero, 52*4(t0) // Initial fs5 + sw zero, 53*4(t0) // Initial fs6 + sw zero, 54*4(t0) // Initial fs7 + sw zero, 55*4(t0) // Initial fs8 + sw zero, 56*4(t0) // Initial fs9 + sw zero, 57*4(t0) // Initial fs10 + sw zero, 58*4(t0) // Initial fs11 + sw zero, 59*4(t0) // Initial ft8 + sw zero, 60*4(t0) // Initial ft9 + sw zero, 61*4(t0) // Initial ft10 + sw zero, 62*4(t0) // Initial ft11 + csrr a1, fcsr // Read fcsr for initial value + sw a1, 63*4(t0) // Initial fcsr + sw zero, 64*4(t0) // Reserved word (0) +#else + sw zero, 31*4(t0) // Reserved word (0) +#endif + + /* Setup stack pointer. */ + /* thread_ptr -> tx_thread_stack_ptr = t0; */ + + sw t0, 8(a0) // Save stack pointer in thread's + ret // control block and return +/* } */ diff --git a/ports/risc-v32/gnu/src/tx_thread_system_return.S b/ports/risc-v32/gnu/src/tx_thread_system_return.S new file mode 100644 index 00000000..110f6ac1 --- /dev/null +++ b/ports/risc-v32/gnu/src/tx_thread_system_return.S @@ -0,0 +1,174 @@ +/*************************************************************************** + * Copyright (c) 2025 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return RISC-V32/GNU */ +/* 6.4.x */ +/* AUTHOR */ +/* */ +/* Akif Ejaz, 10xEngineers */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the system. Only a minimal context */ +/* is saved since the compiler assumes temp registers are going to get */ +/* slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_system_return(VOID) +{ */ + .global _tx_thread_system_return +_tx_thread_system_return: + + /* Save minimal context on the stack. */ + /* sp -= sizeof(stack_frame); */ + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, -29*4 // Allocate space on the stack - with floating point enabled +#else + addi sp, sp, -16*4 // Allocate space on the stack - without floating point enabled +#endif + + /* Store floating point preserved registers. */ +#if defined(__riscv_float_abi_single) + fsw f8, 15*4(sp) // Store fs0 + fsw f9, 16*4(sp) // Store fs1 + fsw f18, 17*4(sp) // Store fs2 + fsw f19, 18*4(sp) // Store fs3 + fsw f20, 19*4(sp) // Store fs4 + fsw f21, 20*4(sp) // Store fs5 + fsw f22, 21*4(sp) // Store fs6 + fsw f23, 22*4(sp) // Store fs7 + fsw f24, 23*4(sp) // Store fs8 + fsw f25, 24*4(sp) // Store fs9 + fsw f26, 25*4(sp) // Store fs10 + fsw f27, 26*4(sp) // Store fs11 + csrr t0, fcsr + sw t0, 27*4(sp) // Store fcsr +#elif defined(__riscv_float_abi_double) + fsd f8, 15*4(sp) // Store fs0 + fsd f9, 16*4(sp) // Store fs1 + fsd f18, 17*4(sp) // Store fs2 + fsd f19, 18*4(sp) // Store fs3 + fsd f20, 19*4(sp) // Store fs4 + fsd f21, 20*4(sp) // Store fs5 + fsd f22, 21*4(sp) // Store fs6 + fsd f23, 22*4(sp) // Store fs7 + fsd f24, 23*4(sp) // Store fs8 + fsd f25, 24*4(sp) // Store fs9 + fsd f26, 25*4(sp) // Store fs10 + fsd f27, 26*4(sp) // Store fs11 + csrr t0, fcsr + sw t0, 27*4(sp) // Store fcsr +#endif + + sw zero, 0(sp) // Solicited stack type + sw ra, 13*4(sp) // Save return address + sw s0, 12*4(sp) // Save s0 + sw s1, 11*4(sp) // Save s1 + sw s2, 10*4(sp) // Save s2 + sw s3, 9*4(sp) // Save s3 + sw s4, 8*4(sp) // Save s4 + sw s5, 7*4(sp) // Save s5 + sw s6, 6*4(sp) // Save s6 + sw s7, 5*4(sp) // Save s7 + sw s8, 4*4(sp) // Save s8 + sw s9, 3*4(sp) // Save s9 + sw s10, 2*4(sp) // Save s10 + sw s11, 1*4(sp) // Save s11 + csrr t0, mstatus // Pickup mstatus + sw t0, 14*4(sp) // Save mstatus + + + /* Lockout interrupts. will be enabled in _tx_thread_schedule */ + + csrci mstatus, 0x08 // Disable interrupts (MIE bit 3) + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + call _tx_execution_thread_exit // Call the thread execution exit function +#endif + + la t0, _tx_thread_current_ptr // Pickup address of pointer + lw t1, 0(t0) // Pickup current thread pointer + la t2, _tx_thread_system_stack_ptr // Pickup stack pointer address + + /* Save current stack and switch to system stack. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = SP; + SP = _tx_thread_system_stack_ptr; */ + + sw sp, 8(t1) // Save stack pointer + lw sp, 0(t2) // Switch to system stack + + /* Determine if the time-slice is active. */ + /* if (_tx_timer_time_slice) + { */ + + la t4, _tx_timer_time_slice // Pickup time slice variable addr + lw t3, 0(t4) // Pickup time slice value + la t2, _tx_thread_schedule // Pickup address of scheduling loop + beqz t3, _tx_thread_dont_save_ts // If no time-slice, don't save it + + /* Save time-slice for the thread and clear the current time-slice. */ + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + sw t3, 24(t1) // Save current time-slice for thread + sw zero, 0(t4) // Clear time-slice variable + + /* } */ +_tx_thread_dont_save_ts: + + /* Clear the current thread pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + sw x0, 0(t0) // Clear current thread pointer + jr t2 // Return to thread scheduler + +/* } */ diff --git a/ports/risc-v32/gnu/src/tx_timer_interrupt.S b/ports/risc-v32/gnu/src/tx_timer_interrupt.S new file mode 100644 index 00000000..92b5c6b6 --- /dev/null +++ b/ports/risc-v32/gnu/src/tx_timer_interrupt.S @@ -0,0 +1,210 @@ +/*************************************************************************** + * Copyright (c) 2026 10xEngineers + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .section .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt RISC-V32/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Akif Ejaz, 10xEngineers */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 01-20-2023 Akif Ejaz Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_timer_interrupt(VOID) +{ */ + .global _tx_timer_interrupt +_tx_timer_interrupt: + + /* Increment the system clock. */ + /* _tx_timer_system_clock++; */ + + la t0, _tx_timer_system_clock // Pickup address of system clock + lw t1, 0(t0) // Pickup system clock + la t2, _tx_timer_time_slice // Pickup address of time slice + lw t3, 0(t2) // Pickup time slice + addi t1, t1, 1 // Increment system clock + sw t1, 0(t0) // Store new system clock + li t6, 0 // Clear local expired flag + + /* Test for time-slice expiration. */ + /* if (_tx_timer_time_slice) + { */ + + beqz t3, _tx_timer_no_time_slice // If 0, skip time slice processing + addi t3, t3, -1 // Decrement the time slice + + /* Decrement the time_slice. */ + /* _tx_timer_time_slice--; */ + + sw t3, 0(t2) // Store new time slice + + /* Check for expiration. */ + /* if (_tx_timer_time_slice == 0) */ + + bgtz t3, _tx_timer_no_time_slice // If not 0, has not expired yet + li t1, 1 // Build expired flag + + /* Set the time-slice expired flag. */ + /* _tx_timer_expired_time_slice = TX_TRUE; */ + + la t4, _tx_timer_expired_time_slice // Get address of expired flag + sw t1, 0(t4) // Set expired flag (UINT) + ori t6, t6, 1 // Set local expired flag + + /* } */ + +_tx_timer_no_time_slice: + + /* Test for timer expiration. */ + /* if (*_tx_timer_current_ptr) + { */ + + la t0, _tx_timer_current_ptr // Pickup address of current ptr + lw t1, 0(t0) // Pickup current pointer (word) + lw t3, 0(t1) // Pickup the current timer entry (word) + la t2, _tx_timer_expired // Pickup address of timer expired flag + li t4, 1 // Build TX_TRUE flag + beqz t3, _tx_timer_no_timer // If NULL, no timer has expired + + /* Set expiration flag. */ + /* _tx_timer_expired = TX_TRUE; */ + + ori t6, t6, 2 // Set local expired flag + sw t4, 0(t2) // Set expired flag in memory (UINT) + j _tx_timer_done // Finished timer processing + + + /* } + else + { */ +_tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + /* _tx_timer_current_ptr++; */ + + /* Check for wrap-around. */ + /* if (_tx_timer_current_ptr == _tx_timer_list_end) */ + + la t2, _tx_timer_list_end // Pickup address of list end pointer + lw t3, 0(t2) // Pickup actual list end + addi t1, t1, 4 // Point to next timer entry + sw t1, 0(t0) // Store new timer pointer + bne t1, t3, _tx_timer_skip_wrap // If not same, good pointer + + /* Wrap to beginning of list. */ + /* _tx_timer_current_ptr = _tx_timer_list_start; */ + + la t2, _tx_timer_list_start // Pickup address of list start pointer + lw t4, 0(t2) // Pickup start of the list + sw t4, 0(t0) // Store new timer pointer + + +_tx_timer_skip_wrap: + /* } */ + +_tx_timer_done: + + + /* See if anything has expired. */ + /* if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + { */ + + beqz t6, _tx_timer_nothing_expired // If nothing expired skip the rest + addi sp, sp, -16 // Allocate some storage on the stack + sw t6, 0(sp) // Save local expired flag + sw ra, 4(sp) // Save ra + + /* Did a timer expire? */ + /* if (_tx_timer_expired) + { */ + + andi t2, t6, 2 // Isolate the timer expired bit + beqz t2, _tx_timer_dont_activate // No, timer not expired + + /* Call the timer expiration processing. */ + /* _tx_timer_expiration_process(void); */ + + call _tx_timer_expiration_process // Call _tx_timer_expiration_process + lw t6, 0(sp) // Recover local expired flag + + /* } */ +_tx_timer_dont_activate: + + /* Did time slice expire? */ + /* if (_tx_timer_expired_time_slice) + { */ + + andi t2, t6, 1 // Is the timer expired bit set? + beqz t2, _tx_timer_not_ts_expiration // If not, skip time slice processing + + /* Time slice interrupted thread. */ + /* _tx_thread_time_slice(); */ + + call _tx_thread_time_slice // Call time slice + + /* } */ + +_tx_timer_not_ts_expiration: + + lw ra, 4(sp) // Recover ra + addi sp, sp, 16 // Recover stack space + /* } */ + +_tx_timer_nothing_expired: + + ret + +/* } */ \ No newline at end of file From 7bf83088b8ef82aea8d182c2b0a8991aa9ddb3da Mon Sep 17 00:00:00 2001 From: "shuta.lst" Date: Wed, 25 Feb 2026 11:00:35 +0800 Subject: [PATCH 11/19] Support XuanTie E906 CPU - Place the E906 implementation in the ports/risc-v32/gnu directory; - Remove code unrelated to the xuantie_smartl_fpga demo; --- .../xuantie_smartl_fpga}/CMakeLists.txt | 5 +- .../boards/board_riscv_dummy/include/board.h | 10 +- .../board_riscv_dummy/include/csi_config.h | 0 .../boards/board_riscv_dummy/src/board_init.c | 0 .../board_riscv_dummy/src/uart/board_uart.c | 0 .../xuantie_smartl_fpga/build_libthreadx.sh | 7 + .../build_threadx_sample.sh | 0 .../chip_riscv_dummy/gcc_flash_smartl.ld | 0 .../include/asm/riscv_asm_macro.h | 0 .../chip_riscv_dummy/include/asm/riscv_csr.h | 0 .../chip_riscv_dummy/include/drv/dev_tag.h | 0 .../chip_riscv_dummy/include/dw_timer_ll.h | 0 .../chip_riscv_dummy/include/dw_uart.h | 0 .../chip_riscv_dummy/include/dw_uart_ll.h | 0 .../components/chip_riscv_dummy/include/soc.h | 0 .../chip_riscv_dummy/include/sys_clk.h | 0 .../src/arch/e906fdp/startup.S | 0 .../src/arch/e906fdp/system.c | 2 - .../src/arch/e906fdp/trap_c.c | 0 .../src/arch/e906fdp/vectors.S | 2 + .../chip_riscv_dummy/src/drivers/dw_uart_ll.c | 0 .../chip_riscv_dummy/src/drivers/uart.c | 0 .../chip_riscv_dummy/src/sys/devices.c | 8 +- .../chip_riscv_dummy/src/sys/feature.c | 0 .../components/chip_riscv_dummy/src/sys/irq.c | 0 .../chip_riscv_dummy/src/sys/irq_port.c | 0 .../chip_riscv_dummy/src/sys/pre_main.c | 0 .../chip_riscv_dummy/src/sys/sys_clk.c | 2 +- .../chip_riscv_dummy/src/sys/target_get.c | 0 .../chip_riscv_dummy/src/sys/tick.c | 0 .../chip_riscv_dummy/src/sys/weak.c | 0 .../csi/csi2/include/core/README.txt | 0 .../csi/csi2/include/core/core_rv32.h | 0 .../csi/csi2/include/core/core_rv64.h | 0 .../csi/csi2/include/core/csi_rv32_gcc.h | 0 .../csi/csi2/include/core/csi_rv64_gcc.h | 0 .../csi/csi2/include/core/csi_rv_common.h | 0 .../csi/csi2/include/core/csi_rv_encoding.h | 0 .../components/csi/csi2/include/csi_core.h | 0 .../components/csi/csi2/include/drv/clk.h | 0 .../components/csi/csi2/include/drv/common.h | 0 .../components/csi/csi2/include/drv/dma.h | 0 .../components/csi/csi2/include/drv/gpio.h | 0 .../components/csi/csi2/include/drv/irq.h | 0 .../components/csi/csi2/include/drv/list.h | 0 .../components/csi/csi2/include/drv/pin.h | 0 .../components/csi/csi2/include/drv/porting.h | 0 .../components/csi/csi2/include/drv/tick.h | 0 .../components/csi/csi2/include/drv/timer.h | 0 .../components/csi/csi2/include/drv/uart.h | 0 .../components/csi/csi2/include/syslog.h | 0 .../components/csi/csi2/src/csi_misc.c | 0 .../libc_threadx/compilers/gcc/sys/ioctl.h | 0 .../libc_threadx/compilers/gcc/sys/termios.h | 0 .../libc_threadx/compilers/gcc/time.h | 0 .../components/libc_threadx/include/errno.h | 0 .../libc_threadx/include/inttypes.h | 0 .../include/serf/minilibc_stdio.h | 0 .../libc_threadx/include/sys/_stdint.h | 0 .../libc_threadx/include/sys/random.h | 0 .../libc_threadx/include/sys/select.h | 0 .../libc_threadx/include/sys/time.h | 0 .../components/libc_threadx/mini_printf.c | 0 .../components/libc_threadx/newlib_stub.c | 0 .../xuantie_smartl_fpga}/demo_threadx.c | 0 .../xuantie_smartl_fpga}/gdbinit | 0 .../xuantie_smartl_fpga}/pre_main.c | 0 .../xuantie_smartl_fpga/readme_e906.txt} | 130 +- .../xuantie_smartl_fpga}/tx_user.h | 0 .../xuantie_e906_gnu.cmake | 4 +- ports/xuantie/e906/gnu/CMakeLists.txt | 17 - .../smartl_fpga/build_libthreadx.sh | 7 - .../csi/csi2/include/core/csi_gcc.h | 3293 ---------- .../components/csi/csi2/include/drv/adc.h | 213 - .../components/csi/csi2/include/drv/aes.h | 309 - .../csi/csi2/include/drv/baud_calc.h | 60 - .../components/csi/csi2/include/drv/codec.h | 450 -- .../components/csi/csi2/include/drv/crc.h | 136 - .../components/csi/csi2/include/drv/des.h | 174 - .../components/csi/csi2/include/drv/drv_fft.h | 83 - .../components/csi/csi2/include/drv/ecdh.h | 92 - .../components/csi/csi2/include/drv/ecdsa.h | 112 - .../components/csi/csi2/include/drv/eflash.h | 140 - .../components/csi/csi2/include/drv/efuse.h | 93 - .../components/csi/csi2/include/drv/etb.h | 102 - .../components/csi/csi2/include/drv/eth.h | 111 - .../components/csi/csi2/include/drv/eth_mac.h | 377 -- .../components/csi/csi2/include/drv/eth_phy.h | 124 - .../components/csi/csi2/include/drv/fft.h | 87 - .../csi/csi2/include/drv/gpio_pin.h | 144 - .../components/csi/csi2/include/drv/hmac.h | 122 - .../components/csi/csi2/include/drv/i2s.h | 397 -- .../components/csi/csi2/include/drv/iic.h | 338 - .../components/csi/csi2/include/drv/intc.h | 178 - .../components/csi/csi2/include/drv/io.h | 131 - .../components/csi/csi2/include/drv/iso7816.h | 409 -- .../components/csi/csi2/include/drv/mbox.h | 104 - .../components/csi/csi2/include/drv/pm.h | 122 - .../components/csi/csi2/include/drv/pmu.h | 118 - .../components/csi/csi2/include/drv/pwm.h | 172 - .../components/csi/csi2/include/drv/qspi.h | 304 - .../components/csi/csi2/include/drv/ringbuf.h | 62 - .../components/csi/csi2/include/drv/rng.h | 54 - .../components/csi/csi2/include/drv/rsa.h | 198 - .../components/csi/csi2/include/drv/rtc.h | 148 - .../components/csi/csi2/include/drv/sasc.h | 144 - .../components/csi/csi2/include/drv/sdif.h | 441 -- .../components/csi/csi2/include/drv/sensor.h | 195 - .../components/csi/csi2/include/drv/sha.h | 128 - .../components/csi/csi2/include/drv/spi.h | 293 - .../csi/csi2/include/drv/spiflash.h | 303 - .../components/csi/csi2/include/drv/spinand.h | 321 - .../components/csi/csi2/include/drv/tee.h | 643 -- .../components/csi/csi2/include/drv/tipc.h | 56 - .../components/csi/csi2/include/drv/usi.h | 42 - .../components/csi/csi2/include/drv/usi_iic.h | 260 - .../components/csi/csi2/include/drv/usi_spi.h | 229 - .../csi/csi2/include/drv/usi_usart.h | 192 - .../components/csi/csi2/include/drv/wdt.h | 139 - .../csi/csi2/include/dsp/csi_common_tables.h | 316 - .../csi/csi2/include/dsp/csi_const_structs.h | 157 - .../csi/csi2/include/dsp/csi_instance.h | 1879 ------ .../csi/csi2/include/dsp/csi_math.h | 5739 ----------------- .../csi/csi2/include/dsp/csky_common_tables.h | 229 - .../csi/csi2/include/dsp/csky_const_structs.h | 131 - .../csi/csi2/include/dsp/csky_math.h | 4637 ------------- .../include/dsp/csky_vdsp2_const_structs.h | 232 - .../csi/csi2/include/dsp/csky_vdsp2_math.h | 2378 ------- .../components/csi/csi2/src/csi_ringbuf.c | 184 - ports/xuantie/e906/gnu/inc/tx_port.h | 361 -- ports/xuantie/e906/gnu/src/tx_port.c | 110 - .../xuantie/e906/gnu/src/tx_thread_context.S | 283 - .../gnu/src/tx_thread_interrupt_control.S | 83 - .../xuantie/e906/gnu/src/tx_thread_schedule.S | 234 - .../e906/gnu/src/tx_thread_system_return.S | 78 - .../xuantie/e906/gnu/src/tx_timer_interrupt.c | 125 - 136 files changed, 39 insertions(+), 29654 deletions(-) rename ports/{xuantie/e906/gnu/example_build/smartl_fpga => risc-v32/gnu/example_build/xuantie_smartl_fpga}/CMakeLists.txt (94%) rename ports/{xuantie/e906/gnu/example_build/smartl_fpga => risc-v32/gnu/example_build/xuantie_smartl_fpga}/boards/board_riscv_dummy/include/board.h (97%) rename ports/{xuantie/e906/gnu/example_build/smartl_fpga => risc-v32/gnu/example_build/xuantie_smartl_fpga}/boards/board_riscv_dummy/include/csi_config.h (100%) rename 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risc-v32/gnu/example_build/xuantie_smartl_fpga}/components/chip_riscv_dummy/include/asm/riscv_csr.h (100%) rename ports/{xuantie/e906/gnu/example_build/smartl_fpga => risc-v32/gnu/example_build/xuantie_smartl_fpga}/components/chip_riscv_dummy/include/drv/dev_tag.h (100%) rename ports/{xuantie/e906/gnu/example_build/smartl_fpga => risc-v32/gnu/example_build/xuantie_smartl_fpga}/components/chip_riscv_dummy/include/dw_timer_ll.h (100%) rename ports/{xuantie/e906/gnu/example_build/smartl_fpga => risc-v32/gnu/example_build/xuantie_smartl_fpga}/components/chip_riscv_dummy/include/dw_uart.h (100%) rename ports/{xuantie/e906/gnu/example_build/smartl_fpga => risc-v32/gnu/example_build/xuantie_smartl_fpga}/components/chip_riscv_dummy/include/dw_uart_ll.h (100%) rename ports/{xuantie/e906/gnu/example_build/smartl_fpga => risc-v32/gnu/example_build/xuantie_smartl_fpga}/components/chip_riscv_dummy/include/soc.h (100%) rename ports/{xuantie/e906/gnu/example_build/smartl_fpga => risc-v32/gnu/example_build/xuantie_smartl_fpga}/components/chip_riscv_dummy/include/sys_clk.h (100%) rename ports/{xuantie/e906/gnu/example_build/smartl_fpga => risc-v32/gnu/example_build/xuantie_smartl_fpga}/components/chip_riscv_dummy/src/arch/e906fdp/startup.S (100%) rename ports/{xuantie/e906/gnu/example_build/smartl_fpga => risc-v32/gnu/example_build/xuantie_smartl_fpga}/components/chip_riscv_dummy/src/arch/e906fdp/system.c (98%) rename ports/{xuantie/e906/gnu/example_build/smartl_fpga => risc-v32/gnu/example_build/xuantie_smartl_fpga}/components/chip_riscv_dummy/src/arch/e906fdp/trap_c.c (100%) rename ports/{xuantie/e906/gnu/example_build/smartl_fpga => risc-v32/gnu/example_build/xuantie_smartl_fpga}/components/chip_riscv_dummy/src/arch/e906fdp/vectors.S (99%) rename ports/{xuantie/e906/gnu/example_build/smartl_fpga => risc-v32/gnu/example_build/xuantie_smartl_fpga}/components/chip_riscv_dummy/src/drivers/dw_uart_ll.c (100%) rename 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ports/xuantie/e906/gnu/src/tx_timer_interrupt.c diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/CMakeLists.txt b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/CMakeLists.txt similarity index 94% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/CMakeLists.txt rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/CMakeLists.txt index ed803a64..0d8c22ea 100644 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/CMakeLists.txt +++ b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/CMakeLists.txt @@ -10,7 +10,6 @@ set(SRCS ${CMAKE_CURRENT_LIST_DIR}/boards/board_riscv_dummy/src/uart/board_uart.c ${CMAKE_CURRENT_LIST_DIR}/boards/board_riscv_dummy/src/board_init.c ${CMAKE_CURRENT_LIST_DIR}/components/csi/csi2/src/csi_misc.c - ${CMAKE_CURRENT_LIST_DIR}/components/csi/csi2/src/csi_ringbuf.c ${CMAKE_CURRENT_LIST_DIR}/components/libc_threadx/mini_printf.c ${CMAKE_CURRENT_LIST_DIR}/components/libc_threadx/newlib_stub.c ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/arch/e906fdp/startup.S @@ -31,7 +30,7 @@ set(SRCS ) include_directories( - ${CMAKE_CURRENT_LIST_DIR}/../../../../../../common/inc + ${CMAKE_CURRENT_LIST_DIR}/../../../../../common/inc ${CMAKE_CURRENT_LIST_DIR}/../../inc ${CMAKE_CURRENT_LIST_DIR} ${CMAKE_CURRENT_LIST_DIR}/boards/board_riscv_dummy/include @@ -67,7 +66,7 @@ add_link_options( -Wl,-Map=${PROJECT_NAME}.map ) -link_directories(${CMAKE_CURRENT_LIST_DIR}/../../../../../../build) +link_directories(${CMAKE_CURRENT_LIST_DIR}/../../../../../build) add_executable(${PROJECT_NAME} ${SRCS}) set_target_properties(${PROJECT_NAME} PROPERTIES OUTPUT_NAME "${PROJECT_NAME}.elf") target_link_libraries(${PROJECT_NAME} PRIVATE threadx) diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/boards/board_riscv_dummy/include/board.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/boards/board_riscv_dummy/include/board.h similarity index 97% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/boards/board_riscv_dummy/include/board.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/boards/board_riscv_dummy/include/board.h index 6d5b756c..a0f81d7a 100644 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/boards/board_riscv_dummy/include/board.h +++ b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/boards/board_riscv_dummy/include/board.h @@ -17,7 +17,7 @@ */ /* - This is an example board.h for Board Compment, New Board should flow the macro defines. + This is an example board.h for Board Component, New Board should follow the macro defines. */ #ifndef __BOARD_H__ @@ -44,7 +44,7 @@ extern "C" { · WIFI · BT · AUDIO - BOARD_XXX Macro descripted below should be defined if the board support. + BOARD_XXX Macro described below should be defined if the board support. */ /****************************************************************************/ @@ -120,8 +120,8 @@ extern "C" { // UART /* - The total supported uart numbers on this board, 0 meas No uart support. - the BOARD_UART_XXX, x in rang of (0, BOARD_UART_NUM - 1) + The total supported uart numbers on this board, 0 means No uart support. + the BOARD_UART_XXX, x in range of (0, BOARD_UART_NUM - 1) */ #ifndef BOARD_UART_NUM #define BOARD_UART_NUM (1) @@ -441,4 +441,4 @@ void board_audio_init(void); } #endif -#endif /* __BOARD_H__ */ \ No newline at end of file +#endif /* __BOARD_H__ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/boards/board_riscv_dummy/include/csi_config.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/boards/board_riscv_dummy/include/csi_config.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/boards/board_riscv_dummy/include/csi_config.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/boards/board_riscv_dummy/include/csi_config.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/boards/board_riscv_dummy/src/board_init.c b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/boards/board_riscv_dummy/src/board_init.c similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/boards/board_riscv_dummy/src/board_init.c rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/boards/board_riscv_dummy/src/board_init.c diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/boards/board_riscv_dummy/src/uart/board_uart.c b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/boards/board_riscv_dummy/src/uart/board_uart.c similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/boards/board_riscv_dummy/src/uart/board_uart.c rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/boards/board_riscv_dummy/src/uart/board_uart.c diff --git a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/build_libthreadx.sh b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/build_libthreadx.sh new file mode 100755 index 00000000..ff9bb930 --- /dev/null +++ b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/build_libthreadx.sh @@ -0,0 +1,7 @@ +#!/bin/bash + +pushd ../../../../../ +rm -rf build +cmake -Bbuild -GNinja -DCMAKE_TOOLCHAIN_FILE=ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/xuantie_e906_gnu.cmake . +cmake --build ./build/ +popd diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/build_threadx_sample.sh b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/build_threadx_sample.sh similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/build_threadx_sample.sh rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/build_threadx_sample.sh diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/gcc_flash_smartl.ld b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/gcc_flash_smartl.ld similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/gcc_flash_smartl.ld rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/gcc_flash_smartl.ld diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/asm/riscv_asm_macro.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/include/asm/riscv_asm_macro.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/asm/riscv_asm_macro.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/include/asm/riscv_asm_macro.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/asm/riscv_csr.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/include/asm/riscv_csr.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/asm/riscv_csr.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/include/asm/riscv_csr.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/drv/dev_tag.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/include/drv/dev_tag.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/drv/dev_tag.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/include/drv/dev_tag.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/dw_timer_ll.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/include/dw_timer_ll.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/dw_timer_ll.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/include/dw_timer_ll.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/dw_uart.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/include/dw_uart.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/dw_uart.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/include/dw_uart.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/dw_uart_ll.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/include/dw_uart_ll.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/dw_uart_ll.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/include/dw_uart_ll.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/soc.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/include/soc.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/soc.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/include/soc.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/sys_clk.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/include/sys_clk.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/include/sys_clk.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/include/sys_clk.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/startup.S b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/startup.S similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/startup.S rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/startup.S diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/system.c b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/system.c similarity index 98% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/system.c rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/system.c index 4b20c58f..468eeda3 100644 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/system.c +++ b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/system.c @@ -22,8 +22,6 @@ #include #include #include -#include -#include #include "riscv_csr.h" #if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/trap_c.c b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/trap_c.c similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/trap_c.c rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/trap_c.c diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/vectors.S b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/vectors.S similarity index 99% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/vectors.S rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/vectors.S index 5c0aabb2..20840bc5 100644 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/vectors.S +++ b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/arch/e906fdp/vectors.S @@ -896,3 +896,5 @@ is_interrupt: .weak \handler_name .set \handler_name, Default_Handler .endm + + def_irq_handler tspend_handler diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/drivers/dw_uart_ll.c b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/drivers/dw_uart_ll.c similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/drivers/dw_uart_ll.c rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/drivers/dw_uart_ll.c diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/drivers/uart.c b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/drivers/uart.c similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/drivers/uart.c rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/drivers/uart.c diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/devices.c b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/sys/devices.c similarity index 96% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/devices.c rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/sys/devices.c index 3979c41d..48011f2a 100644 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/devices.c +++ b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/sys/devices.c @@ -22,10 +22,10 @@ #include #include #include -#include -#include -#include -#include +// #include +// #include +// #include +// #include #include #include #include diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/feature.c b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/sys/feature.c similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/feature.c rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/sys/feature.c diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/irq.c b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/sys/irq.c similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/irq.c rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/sys/irq.c diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/irq_port.c b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/sys/irq_port.c similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/irq_port.c rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/sys/irq_port.c diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/pre_main.c b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/sys/pre_main.c similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/pre_main.c rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/sys/pre_main.c diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/sys_clk.c b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/sys/sys_clk.c similarity index 98% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/sys_clk.c rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/sys/sys_clk.c index f79105e8..2ef6f11e 100644 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/sys_clk.c +++ b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/sys/sys_clk.c @@ -19,7 +19,7 @@ #include #include #include -#include +// #include uint32_t g_system_clock = IHS_VALUE; diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/target_get.c b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/sys/target_get.c similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/target_get.c rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/sys/target_get.c diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/tick.c b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/sys/tick.c similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/tick.c rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/sys/tick.c diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/weak.c b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/sys/weak.c similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/weak.c rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/sys/weak.c diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/README.txt b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/core/README.txt similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/README.txt rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/core/README.txt diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/core_rv32.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/core/core_rv32.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/core_rv32.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/core/core_rv32.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/core_rv64.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/core/core_rv64.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/core_rv64.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/core/core_rv64.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/csi_rv32_gcc.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/core/csi_rv32_gcc.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/csi_rv32_gcc.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/core/csi_rv32_gcc.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/csi_rv64_gcc.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/core/csi_rv64_gcc.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/csi_rv64_gcc.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/core/csi_rv64_gcc.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/csi_rv_common.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/core/csi_rv_common.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/csi_rv_common.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/core/csi_rv_common.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/csi_rv_encoding.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/core/csi_rv_encoding.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/csi_rv_encoding.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/core/csi_rv_encoding.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/csi_core.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/csi_core.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/csi_core.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/csi_core.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/clk.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/clk.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/clk.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/clk.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/common.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/common.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/common.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/common.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/dma.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/dma.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/dma.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/dma.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/gpio.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/gpio.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/gpio.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/gpio.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/irq.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/irq.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/irq.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/irq.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/list.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/list.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/list.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/list.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/pin.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/pin.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/pin.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/pin.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/porting.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/porting.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/porting.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/porting.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/tick.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/tick.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/tick.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/tick.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/timer.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/timer.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/timer.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/timer.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/uart.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/uart.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/uart.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/uart.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/syslog.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/syslog.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/syslog.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/syslog.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/src/csi_misc.c b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/src/csi_misc.c similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/src/csi_misc.c rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/src/csi_misc.c diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/compilers/gcc/sys/ioctl.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/libc_threadx/compilers/gcc/sys/ioctl.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/compilers/gcc/sys/ioctl.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/libc_threadx/compilers/gcc/sys/ioctl.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/compilers/gcc/sys/termios.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/libc_threadx/compilers/gcc/sys/termios.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/compilers/gcc/sys/termios.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/libc_threadx/compilers/gcc/sys/termios.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/compilers/gcc/time.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/libc_threadx/compilers/gcc/time.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/compilers/gcc/time.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/libc_threadx/compilers/gcc/time.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/errno.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/libc_threadx/include/errno.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/errno.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/libc_threadx/include/errno.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/inttypes.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/libc_threadx/include/inttypes.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/inttypes.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/libc_threadx/include/inttypes.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/serf/minilibc_stdio.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/libc_threadx/include/serf/minilibc_stdio.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/serf/minilibc_stdio.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/libc_threadx/include/serf/minilibc_stdio.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/sys/_stdint.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/libc_threadx/include/sys/_stdint.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/sys/_stdint.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/libc_threadx/include/sys/_stdint.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/sys/random.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/libc_threadx/include/sys/random.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/sys/random.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/libc_threadx/include/sys/random.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/sys/select.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/libc_threadx/include/sys/select.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/sys/select.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/libc_threadx/include/sys/select.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/sys/time.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/libc_threadx/include/sys/time.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/include/sys/time.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/libc_threadx/include/sys/time.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/mini_printf.c b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/libc_threadx/mini_printf.c similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/mini_printf.c rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/libc_threadx/mini_printf.c diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/newlib_stub.c b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/libc_threadx/newlib_stub.c similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/components/libc_threadx/newlib_stub.c rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/libc_threadx/newlib_stub.c diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/demo_threadx.c b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/demo_threadx.c similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/demo_threadx.c rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/demo_threadx.c diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/gdbinit b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/gdbinit similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/gdbinit rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/gdbinit diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/pre_main.c b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/pre_main.c similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/pre_main.c rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/pre_main.c diff --git a/ports/xuantie/e906/gnu/readme_threadx.txt b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/readme_e906.txt similarity index 55% rename from ports/xuantie/e906/gnu/readme_threadx.txt rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/readme_e906.txt index 56189b6e..2ffd7618 100644 --- a/ports/xuantie/e906/gnu/readme_threadx.txt +++ b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/readme_e906.txt @@ -17,13 +17,13 @@ Verify the toolchain: riscv64-unknown-elf-objdump --version Library build script - ports/xuantie/e906/gnu/example_build/smartl_fpga/build_libthreadx.sh + build_libthreadx.sh Example build script The example demonstration contains a build script. See: - ports/xuantie/e906/gnu/example_build/smartl_fpga/build_threadx_sample.sh + build_threadx_sample.sh This script builds the library and the demo application demo_threadx.elf. @@ -63,85 +63,7 @@ Board Initialization (board_init.c) Then jump to main(). -4. Register Usage and Stack Frames - -The RISC-V32 ABI defines t0-t6 and a0-a7 as caller-saved (temporary) registers. -All other registers used by a function must be preserved by the function. - -Stack Layout for Task Frame (with FP double and P-extension enabled): - - Index Offset Register Description - ───────────────────────────────────────────────── - 0 0x00 mepc machine exception PC - 1 0x04 ra return address - 2 0x08 t0 temporary register 0 - 3 0x0C t1 temporary register 1 - 4 0x10 t2 temporary register 2 - 5 0x14 s0 saved register 0 or frame pointer - 6 0x18 s1 saved register 1 - 7 0x1C a0 argument register 0 - 8 0x20 a1 argument register 1 - 9 0x24 a2 argument register 2 - 10 0x28 a3 argument register 3 - 11 0x2C a4 argument register 4 - 12 0x30 a5 argument register 5 - 13 0x34 a6 argument register 6 - 14 0x38 a7 argument register 7 - 15 0x3C s2 saved register 2 - 16 0x40 s3 saved register 3 - 17 0x44 s4 saved register 4 - 18 0x48 s5 saved register 5 - 19 0x4C s6 saved register 6 - 20 0x50 s7 saved register 7 - 21 0x54 s8 saved register 8 - 22 0x58 s9 saved register 9 - 23 0x5C s10 saved register 10 - 24 0x60 s11 saved register 11 - 25 0x64 t3 temporary register 3 - 26 0x68 t4 temporary register 4 - 27 0x6C t5 temporary register 5 - 28 0x70 t6 temporary register 6 - 29 0x74 mstatus machine status register - - 30 0x78 fcsr FP control/status register - 31 0x7C ft0 FP temporary register 0 - 32 0x84 ft1 FP temporary register 1 - 33 0x8C ft2 FP temporary register 2 - 34 0x94 ft3 FP temporary register 3 - 35 0x9C ft4 FP temporary register 4 - 36 0xA4 ft5 FP temporary register 5 - 37 0xAC ft6 FP temporary register 6 - 38 0xB4 ft7 FP temporary register 7 - 39 0xBC fs0 FP saved register 0 - 40 0xC4 fs1 FP saved register 1 - 41 0xCC fa0 FP argument register 0 - 42 0xD4 fa1 FP argument register 1 - 43 0xDC fa2 FP argument register 2 - 44 0xE4 fa3 FP argument register 3 - 45 0xEC fa4 FP argument register 4 - 46 0xF4 fa5 FP argument register 5 - 47 0xFC fa6 FP argument register 6 - 48 0x104 fa7 FP argument register 7 - 49 0x10C fs2 FP saved register 2 - 50 0x114 fs3 FP saved register 3 - 51 0x11C fs4 FP saved register 4 - 52 0x124 fs5 FP saved register 5 - 53 0x12C fs6 FP saved register 6 - 54 0x134 fs7 FP saved register 7 - 55 0x13C fs8 FP saved register 8 - 56 0x144 fs9 FP saved register 9 - 57 0x14C fs10 FP saved register 10 - 58 0x154 fs11 FP saved register 11 - 59 0x15C ft8 FP temporary register 8 - 60 0x164 ft9 FP temporary register 9 - 61 0x16C ft10 FP temporary register 10 - 62 0x174 ft11 FP temporary register 11 - - 63 0x17C vxsat fixed-point saturation flag register - ───────────────────────────────────────────────── - - -5. Interrupt Handling +4. Interrupt Handling Machine Mode Operation @@ -153,11 +75,11 @@ Interrupt Sources 1. Machine Timer Interrupt (MTI): - Triggered by CLINT when mtime >= mtimecmp - Handled by _tx_timer_interrupt (src/tx_timer_interrupt.c) - - Called from tick_irq_handler() in example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/tick.c + - Called from tick_irq_handler() in example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/sys/tick.c 2. External Interrupts (MEI): - Routed through CLIC - - Handled by do_irq() in example_build/smartl_fpga/components/chip_riscv_dummy/src/sys/irq.c + - Handled by do_irq() in example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/sys/irq.c 3. Software Interrupts (MSI): - Routed through CLIC @@ -175,7 +97,7 @@ These are defined in ports/xuantie/e906/gnu/inc/tx_port.h and use the _tx_thread_interrupt_control() function. -6. Thread Scheduling and Context Switching +5. Thread Scheduling and Context Switching Fist Thread Switch (src/tx_thread_schedule.S) 1. Enables interrupts while waiting a thread @@ -204,7 +126,7 @@ New threads start with a fake interrupt frame containing: - Floating-point registers initialized based on ABI -7. Port Configuration and Macros +6. Port Configuration and Macros Default Configurations (in ports/risc-v64/gnu/inc/tx_port.h): @@ -216,9 +138,9 @@ Default Configurations (in ports/risc-v64/gnu/inc/tx_port.h): These can be overridden in tx_user.h or on the compiler command line. -8. Build Configuration +7. Build Configuration -CMake Toolchain File: example_build/smartl_fpga/xuantie_e906_gnu.cmake +CMake Toolchain File: example_build/xuantie_smartl_fpga/xuantie_e906_gnu.cmake Compiler Flags: -mcpu=e906fdp RISC-V RV32IMA[F][D]C[P] @@ -226,22 +148,9 @@ Compiler Flags: -D__ASSEMBLER__ For assembly files -9. File Organization +8. File Organization -Port-specific files (ports/risc-v64/gnu/): - -Core assembly files (src/): - - tx_port.c Initial setup and system state, Build initial stack frame for new thread - - tx_thread_context.S Thread context switch by software interrupt - - tx_thread_schedule.S Fist Thread scheduler - - tx_thread_system_return.S Trigger a software interrupt for voluntary yield - - tx_thread_interrupt_control.S Interrupt enable/disable control - - tx_timer_interrupt.S Timer interrupt handler - -Header file (inc/): - - tx_port.h Port-specific defines and macros - -Example files (example_build/smartl_fpga/): +Example files (example_build/xuantie_smartl_fpga/): - components/chip_riscv_dummy/src/arch/e906fdp Startup code, Interrupt handlers - components/chip_riscv_dummy/src/drivers The basic peripheral drivers for the platform - components/chip_riscv_dummy/src/sys System initialization @@ -254,7 +163,7 @@ Example files (example_build/smartl_fpga/): - build_libthreadx.sh Build script -10. Linker Script Requirements +9. Linker Script Requirements The linker script must provide: @@ -275,7 +184,7 @@ The linker script must provide: 4. Alignment: - 4-byte alignment throughout -11. Performance and Debugging +10. Performance and Debugging Performance Optimization @@ -307,27 +216,20 @@ Useful GDB commands: (gdb) p *_tx_thread_current_ptr # View current thread control block -12. Platform-Specific Notes (QEMU smartl) +11. Platform-Specific Notes (QEMU smartl) See https://www.xrvm.com/soft-tools/tools/QEMU Timer frequency is platform-dependent (example uses 100MHz). -13. Revision History +12. Revision History -For generic code revision information, refer to ports/risc-v64/gnu/readme_threadx.txt. +For generic code revision information, refer to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/readme_e906.txt. The following details the revision history for this xuantie/e906 GNU port: 12-02-2026 Steven Lin Support XuanTie E906 -01-26-2026 Akif Ejaz Comprehensive rewrite with accurate - technical details matching implementation, - register naming per RISC-V ABI, and - complete interrupt flow documentation - -03-08-2023 Scott Larson Initial Version 6.2.1 - Copyright (c) 1996-2026 Microsoft Corporation diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/tx_user.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/tx_user.h similarity index 100% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/tx_user.h rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/tx_user.h diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/xuantie_e906_gnu.cmake b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/xuantie_e906_gnu.cmake similarity index 72% rename from ports/xuantie/e906/gnu/example_build/smartl_fpga/xuantie_e906_gnu.cmake rename to ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/xuantie_e906_gnu.cmake index 2f6e9d91..b724b0d7 100644 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/xuantie_e906_gnu.cmake +++ b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/xuantie_e906_gnu.cmake @@ -4,7 +4,7 @@ set(CMAKE_SYSTEM_PROCESSOR xuantie_e906) set(THREADX_ARCH "xuantie_e906") set(THREADX_TOOLCHAIN "gnu") -set(ARCH_FLAGS "-g -mcpu=e906fdp -mcmodel=medlow") +set(ARCH_FLAGS "-g -mcpu=e906fd -mcmodel=medlow") set(CFLAGS "${ARCH_FLAGS}") set(ASFLAGS "${ARCH_FLAGS}") set(LDFLAGS "${ARCH_FLAGS}") @@ -12,4 +12,4 @@ set(LDFLAGS "${ARCH_FLAGS}") set(TX_USER_FILE ${CMAKE_CURRENT_LIST_DIR}/tx_user.h) set(THREADX_CUSTOM_PORT ${CMAKE_CURRENT_LIST_DIR}/../../) -include(${CMAKE_CURRENT_LIST_DIR}/../../../../../../cmake/riscv64-unknown-elf.cmake) \ No newline at end of file +include(${CMAKE_CURRENT_LIST_DIR}/../../../../../cmake/riscv64-unknown-elf.cmake) \ No newline at end of file diff --git a/ports/xuantie/e906/gnu/CMakeLists.txt b/ports/xuantie/e906/gnu/CMakeLists.txt deleted file mode 100644 index 33a3a43a..00000000 --- a/ports/xuantie/e906/gnu/CMakeLists.txt +++ /dev/null @@ -1,17 +0,0 @@ - -target_sources(${PROJECT_NAME} - PRIVATE - # {{BEGIN_TARGET_SOURCES}} - ${CMAKE_CURRENT_LIST_DIR}/src/tx_port.c - ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.c - # {{END_TARGET_SOURCES}} -) - -target_include_directories(${PROJECT_NAME} - PUBLIC - ${CMAKE_CURRENT_LIST_DIR}/inc -) diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/build_libthreadx.sh b/ports/xuantie/e906/gnu/example_build/smartl_fpga/build_libthreadx.sh deleted file mode 100755 index 2f35e09e..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/build_libthreadx.sh +++ /dev/null @@ -1,7 +0,0 @@ -#!/bin/bash - -pushd ../../../../../../ -rm -rf build -cmake -Bbuild -GNinja -DCMAKE_TOOLCHAIN_FILE=ports/xuantie/e906/gnu/example_build/smartl_fpga/xuantie_e906_gnu.cmake . -cmake --build ./build/ -popd diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/csi_gcc.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/csi_gcc.h deleted file mode 100644 index 75b42742..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/core/csi_gcc.h +++ /dev/null @@ -1,3293 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file csi_gcc.h - * @brief CSI Header File for GCC. - * @version V1.0 - * @date 02. June 2020 - ******************************************************************************/ - -#ifndef _CSI_GCC_H_ -#define _CSI_GCC_H_ - -#include -#include - -#ifndef __ASM -#define __ASM __asm /*!< asm keyword for GNU Compiler */ -#endif - -#ifndef __INLINE -#define __INLINE inline /*!< inline keyword for GNU Compiler */ -#endif - -#ifndef __ALWAYS_STATIC_INLINE -#define __ALWAYS_STATIC_INLINE __attribute__((always_inline)) static inline -#endif - -#ifndef __STATIC_INLINE -#define __STATIC_INLINE static inline -#endif - -#ifndef __NO_RETURN -#define __NO_RETURN __attribute__((__noreturn__)) -#endif - -#ifndef __USED -#define __USED __attribute__((used)) -#endif - -#ifndef __WEAK -#define __WEAK __attribute__((weak)) -#endif - -#ifndef __PACKED -#define __PACKED __attribute__((packed, aligned(1))) -#endif - -#ifndef __PACKED_STRUCT -#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif - -#ifndef __PACKED_UNION -#define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CSI_Core_FunctionInterface - \defgroup CSI_Core_RegAccFunctions CSI Core Register Access Functions - @{ - */ -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by setting the IE-bit in the PSR. - Can only be executed in Privileged modes. - */ -__ALWAYS_STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile("psrset ie"); -} - - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by clearing the IE-bit in the PSR. - Can only be executed in Privileged modes. - */ -__ALWAYS_STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile("psrclr ie"); -} - -/** - \brief Get PSR - \details Returns the content of the PSR Register. - \return PSR Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_PSR(void) -{ - uint32_t result; - - __ASM volatile("mfcr %0, psr" : "=r"(result) :: "memory"); - return (result); -} - -/** - \brief Set PSR - \details Writes the given value to the PSR Register. - \param [in] psr PSR Register value to set - */ -__ALWAYS_STATIC_INLINE void __set_PSR(uint32_t psr) -{ - __ASM volatile("mtcr %0, psr" : : "r"(psr) : "memory"); -} - -/** - \brief Get SP - \details Returns the content of the SP Register. - \return SP Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_SP(void) -{ - uint32_t result; - - __ASM volatile("mov %0, sp" : "=r"(result)); - return (result); -} - -/** - \brief Set SP - \details Writes the given value to the SP Register. - \param [in] sp SP Register value to set - */ -__ALWAYS_STATIC_INLINE void __set_SP(uint32_t sp) -{ - __ASM volatile("mov sp, %0" : : "r"(sp): "sp"); -} - -/** - \brief Get Int SP - \details Returns the content of the Int SP Register. - \return Int SP Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_Int_SP(void) -{ - uint32_t result; - - __ASM volatile("mfcr %0, cr<15, 1>" : "=r"(result)); - return (result); -} - -/** - \brief Set Int SP - \details Writes the given value to the Int SP Register. - \param [in] sp Int SP Register value to set - */ -__ALWAYS_STATIC_INLINE void __set_Int_SP(uint32_t sp) -{ - __ASM volatile("mtcr %0, cr<15, 1>" : : "r"(sp)); -} - -/** - \brief Get VBR Register - \details Returns the content of the VBR Register. - \return VBR Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_VBR(void) -{ - uint32_t result; - - __ASM volatile("mfcr %0, vbr" : "=r"(result)); - return (result); -} - -/** - \brief Set VBR - \details Writes the given value to the VBR Register. - \param [in] vbr VBR Register value to set - */ -__ALWAYS_STATIC_INLINE void __set_VBR(uint32_t vbr) -{ - __ASM volatile("mtcr %0, vbr" : : "r"(vbr)); -} - -/** - \brief Get EPC Register - \details Returns the content of the EPC Register. - \return EPC Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_EPC(void) -{ - uint32_t result; - - __ASM volatile("mfcr %0, epc" : "=r"(result)); - return (result); -} - -/** - \brief Set EPC - \details Writes the given value to the EPC Register. - \param [in] epc EPC Register value to set - */ -__ALWAYS_STATIC_INLINE void __set_EPC(uint32_t epc) -{ - __ASM volatile("mtcr %0, epc" : : "r"(epc)); -} - -/** - \brief Get EPSR - \details Returns the content of the EPSR Register. - \return EPSR Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_EPSR(void) -{ - uint32_t result; - - __ASM volatile("mfcr %0, epsr" : "=r"(result)); - return (result); -} - -/** - \brief Set EPSR - \details Writes the given value to the EPSR Register. - \param [in] epsr EPSR Register value to set - */ -__ALWAYS_STATIC_INLINE void __set_EPSR(uint32_t epsr) -{ - __ASM volatile("mtcr %0, epsr" : : "r"(epsr)); -} - -/** - \brief Get CPUID Register - \details Returns the content of the CPUID Register. - \return CPUID Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_CPUID(void) -{ - uint32_t result; - -#ifdef __CK610 - __ASM volatile("mfcr %0, cr13" : "=r"(result)); -#else - __ASM volatile("mfcr %0, cr<13, 0>" : "=r"(result)); -#endif - return (result); -} - -/** - \brief Get CCR - \details Returns the current value of the CCR. - \return CCR Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_CCR(void) -{ - register uint32_t result; - -#ifdef __CK610 - __ASM volatile("mfcr %0, cr18\n" : "=r"(result)); -#else - __ASM volatile("mfcr %0, cr<18, 0>\n" : "=r"(result)); -#endif - return (result); -} - - -/** - \brief Set CCR - \details Assigns the given value to the CCR. - \param [in] ccr CCR value to set - */ -__ALWAYS_STATIC_INLINE void __set_CCR(uint32_t ccr) -{ -#ifdef __CK610 - __ASM volatile("mtcr %0, cr18\n" : : "r"(ccr)); -#else - __ASM volatile("mtcr %0, cr<18, 0>\n" : : "r"(ccr)); -#endif -} - -/** - \brief Get CCR2 - \details Returns the current value of the CCR2. - \return CCR2 Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_CCR2(void) -{ - register uint32_t result; - - __ASM volatile("mfcr %0, cr<31, 0>\n" : "=r"(result)); - return (result); -} - -/** - \brief Set CCR2 - \details Assigns the given value to the CCR2. - \param [in] ccr2 CCR2 value to set - */ -__ALWAYS_STATIC_INLINE void __set_CCR2(uint32_t ccr2) -{ - __ASM volatile("mtcr %0, cr<31, 0>\n" : : "r"(ccr2)); -} - -/** - \brief Get DCSR - \details Returns the content of the DCSR Register. - \return DCSR Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_DCSR(void) -{ - uint32_t result; -#ifdef __CK610 - __ASM volatile("mfcr %0, cr14" : "=r"(result)); -#else - __ASM volatile("mfcr %0, cr<14, 0>" : "=r"(result)); -#endif - return (result); -} - - -/** - \brief Set DCSR - \details Writes the given value to the DCSR Register. - \param [in] dcsr DCSR Register value to set - */ -__ALWAYS_STATIC_INLINE void __set_DCSR(uint32_t dcsr) -{ -#ifdef __CK610 - __ASM volatile("mtcr %0, cr14" : : "r"(dcsr)); -#else - __ASM volatile("mtcr %0, cr<14, 0>" : : "r"(dcsr)); -#endif -} - - -/** - \brief Get CFR - \details Returns the content of the CFR Register. - \return CFR Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_CFR(void) -{ - uint32_t result; -#ifdef __CK610 - __ASM volatile("mfcr %0, cr17" : "=r"(result)); -#else - __ASM volatile("mfcr %0, cr<17, 0>" : "=r"(result)); -#endif - - return (result); -} - - -/** - \brief Set CFR - \details Writes the given value to the CFR Register. - \param [in] cfr CFR Register value to set - */ -__ALWAYS_STATIC_INLINE void __set_CFR(uint32_t cfr) -{ -#ifdef __CK610 - __ASM volatile("mtcr %0, cr17" : : "r"(cfr)); -#else - __ASM volatile("mtcr %0, cr<17, 0>" : : "r"(cfr)); -#endif -} - - -/** - \brief Get CIR - \details Returns the content of the CIR Register. - \return CIR Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_CIR(void) -{ - uint32_t result; -#ifdef __CK610 - __ASM volatile("mfcr %0, cr22" : "=r"(result)); -#else - __ASM volatile("mfcr %0, cr<22, 0>" : "=r"(result)); -#endif - return (result); -} - - -/** - \brief Set CIR - \details Writes the given value to the CIR Register. - \param [in] cir CIR Register value to set - */ -__ALWAYS_STATIC_INLINE void __set_CIR(uint32_t cir) -{ -#ifdef __CK610 - __ASM volatile("mtcr %0, cr22" : : "r"(cir)); -#else - __ASM volatile("mtcr %0, cr<22, 0>" : : "r"(cir)); -#endif -} - -/** - \brief Get ERRLC - \details Returns the current value of the ERRLC. - \return ERRLC Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_ERRLC(void) -{ - register uint32_t result; - - __ASM volatile("mfcr %0, cr<6, 1>\n" : "=r"(result)); - return (result); -} - -/** - \brief Set ERRLC - \details Assigns the given value to the ERRLC. - \param [in] errlc ERRLC value to set - */ -__ALWAYS_STATIC_INLINE void __set_ERRLC(uint32_t errlc) -{ - __ASM volatile("mtcr %0, cr<6, 1>\n" : : "r"(errlc)); -} - -/** - \brief Get ERRADDR - \details Returns the current value of the ERRADDR. - \return ERRADDR Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_ERRADDR(void) -{ - register uint32_t result; - - __ASM volatile("mfcr %0, cr<7, 1>\n" : "=r"(result)); - return (result); -} - -/** - \brief Set ERRADDR - \details Assigns the given value to the ERRADDR. - \param [in] erraddr ERRADDR value to set - */ -__ALWAYS_STATIC_INLINE void __set_ERRADDR(uint32_t erraddr) -{ - __ASM volatile("mtcr %0, cr<7, 1>\n" : : "r"(erraddr)); -} - -/** - \brief Get ERRSTS - \details Returns the current value of the ERRSTS. - \return ERRSTS Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_ERRSTS(void) -{ - register uint32_t result; - - __ASM volatile("mfcr %0, cr<8, 1>\n" : "=r"(result)); - return (result); -} - -/** - \brief Set ERRSTS - \details Assigns the given value to the ERRSTS. - \param [in] errsts ERRSTS value to set - */ -__ALWAYS_STATIC_INLINE void __set_ERRSTS(uint32_t errsts) -{ - __ASM volatile("mtcr %0, cr<8, 1>\n" : : "r"(errsts)); -} - -/** - \brief Get ERRINJCR - \details Returns the current value of the ERRINJCR. - \return ERRINJCR Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_ERRINJCR(void) -{ - register uint32_t result; - - __ASM volatile("mfcr %0, cr<9, 1>\n" : "=r"(result)); - return (result); -} - -/** - \brief Set ERRINJCR - \details Assigns the given value to the ERRINJCR. - \param [in] errinjcr ERRINJCR value to set - */ -__ALWAYS_STATIC_INLINE void __set_ERRINJCR(uint32_t errinjcr) -{ - __ASM volatile("mtcr %0, cr<9, 1>\n" : : "r"(errinjcr)); -} - -/** - \brief Get ERRINJCNT - \details Returns the current value of the ERRINJCNT. - \return ERRINJCNT Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_ERRINJCNT(void) -{ - register uint32_t result; - - __ASM volatile("mfcr %0, cr<10, 1>\n" : "=r"(result)); - return (result); -} - -/** - \brief Set ERRINJCNT - \details Assigns the given value to the ERRINJCNT. - \param [in] errinjcnt ERRINJCNT value to set - */ -__ALWAYS_STATIC_INLINE void __set_ERRINJCNT(uint32_t errinjcnt) -{ - __ASM volatile("mtcr %0, cr<10, 1>\n" : : "r"(errinjcnt)); -} - -/** - \brief Get ITCMCR - \details Returns the content of the ITCMCR Register. - \return ITCMCR Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_ITCMCR(void) -{ - uint32_t result; - __ASM volatile("mfcr %0, cr<22, 1>" : "=r"(result)); - return (result); -} - -/** - \brief Set ITCMCR - \details Writes the given value to the ITCMCR Register. - \param [in] itcmcr ITCMCR Register value to set - */ -__ALWAYS_STATIC_INLINE void __set_ITCMCR(uint32_t itcmcr) -{ - __ASM volatile("mtcr %0, cr<22, 1>" : : "r"(itcmcr)); -} - -/** - \brief Get DTCMCR - \details Returns the content of the DTCMCR Register. - \return DTCMCR Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_DTCMCR(void) -{ - uint32_t result; - __ASM volatile("mfcr %0, cr<23, 1>" : "=r"(result)); - return (result); -} - -/** - \brief Set DTCMCR - \details Writes the given value to the DTCMCR Register. - \param [in] dtcmcr DTCMCR Register value to set - */ -__ALWAYS_STATIC_INLINE void __set_DTCMCR(uint32_t dtcmcr) -{ - __ASM volatile("mtcr %0, cr<23, 1>" : : "r"(dtcmcr)); -} - -/** - \brief Get CINDEX - \details Returns the current value of the CINDEX. - \return CINDEX Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_CINDEX(void) -{ - register uint32_t result; - - __ASM volatile("mfcr %0, cr<26, 1>\n" : "=r"(result)); - return (result); -} - -/** - \brief Set CINDEX - \details Assigns the given value to the CINDEX. - \param [in] cindex CINDEX value to set - */ -__ALWAYS_STATIC_INLINE void __set_CINDEX(uint32_t cindex) -{ - __ASM volatile("mtcr %0, cr<26, 1>\n" : : "r"(cindex)); -} - -/** - \brief Get CDATAx - \details Returns the current value of the CDATAx. - \return CDATAx Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_CDATA0(void) -{ - register uint32_t result; - - __ASM volatile("mfcr %0, cr<27, 1>\n" : "=r"(result)); - return (result); -} - -__ALWAYS_STATIC_INLINE uint32_t __get_CDATA1(void) -{ - register uint32_t result; - - __ASM volatile("mfcr %0, cr<28, 1>\n" : "=r"(result)); - return (result); -} - -__ALWAYS_STATIC_INLINE uint32_t __get_CDATA2(void) -{ - register uint32_t result; - - __ASM volatile("mfcr %0, cr<29, 1>\n" : "=r"(result)); - return (result); -} - -/** - \brief Set CDATAx - \details Assigns the given value to the CDATAx. - \param [in] cdata CDATAx value to set - */ -__ALWAYS_STATIC_INLINE void __set_CDATA0(uint32_t cdata) -{ - __ASM volatile("mtcr %0, cr<27, 1>\n" : : "r"(cdata)); -} - -__ALWAYS_STATIC_INLINE void __set_CDATA1(uint32_t cdata) -{ - __ASM volatile("mtcr %0, cr<28, 1>\n" : : "r"(cdata)); -} - -__ALWAYS_STATIC_INLINE void __set_CDATA2(uint32_t cdata) -{ - __ASM volatile("mtcr %0, cr<29, 1>\n" : : "r"(cdata)); -} - -/** - \brief Get CINS - \details Returns the current value of the CINS. - \return CINS Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_CINS(void) -{ - register uint32_t result; - - __ASM volatile("mfcr %0, cr<31, 1>\n" : "=r"(result)); - return (result); -} - -/** - \brief Set CINS - \details Assigns the given value to the CINS. - \param [in] cins CINS value to set - */ -__ALWAYS_STATIC_INLINE void __set_CINS(uint32_t cins) -{ - __ASM volatile("mtcr %0, cr<31, 1>\n" : : "r"(cins)); -} - -/** - \brief Get CAPR - \details Returns the current value of the CAPR. - \return CAPR Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_CAPR(void) -{ - register uint32_t result; - -#ifdef __CK610 - __ASM volatile("mfcr %0, cr19\n" : "=r"(result)); -#else - __ASM volatile("mfcr %0, cr<19, 0>\n" : "=r"(result)); -#endif - return (result); -} - -/** - \brief Set CAPR - \details Assigns the given value to the CAPR. - \param [in] capr CAPR value to set - */ -__ALWAYS_STATIC_INLINE void __set_CAPR(uint32_t capr) -{ -#ifdef __CK610 - __ASM volatile("mtcr %0, cr19\n" : : "r"(capr)); -#else - __ASM volatile("mtcr %0, cr<19, 0>\n" : : "r"(capr)); -#endif -} - -/** - \brief Get CAPR1 - \details Returns the current value of the CAPR1. - \return CAPR1 Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_CAPR1(void) -{ - register uint32_t result; - - __ASM volatile("mfcr %0, cr<16, 0>\n" : "=r"(result)); - return (result); -} - -/** - \brief Set CAPR1 - \details Assigns the given value to the CAPR1. - \param [in] capr1 CAPR1 value to set - */ -__ALWAYS_STATIC_INLINE void __set_CAPR1(uint32_t capr1) -{ - __ASM volatile("mtcr %0, cr<16, 0>\n" : : "r"(capr1)); -} - -/** - \brief Set PACR - \details Assigns the given value to the PACR. - - \param [in] pacr PACR value to set - */ -__ALWAYS_STATIC_INLINE void __set_PACR(uint32_t pacr) -{ -#ifdef __CK610 - __ASM volatile("mtcr %0, cr20\n" : : "r"(pacr)); -#else - __ASM volatile("mtcr %0, cr<20, 0>\n" : : "r"(pacr)); -#endif -} - - -/** - \brief Get PACR - \details Returns the current value of PACR. - \return PACR value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_PACR(void) -{ - uint32_t result; - -#ifdef __CK610 - __ASM volatile("mfcr %0, cr20" : "=r"(result)); -#else - __ASM volatile("mfcr %0, cr<20, 0>" : "=r"(result)); -#endif - return (result); -} - -/** - \brief Set PRSR - \details Assigns the given value to the PRSR. - - \param [in] prsr PRSR value to set - */ -__ALWAYS_STATIC_INLINE void __set_PRSR(uint32_t prsr) -{ -#ifdef __CK610 - __ASM volatile("mtcr %0, cr21\n" : : "r"(prsr)); -#else - __ASM volatile("mtcr %0, cr<21, 0>\n" : : "r"(prsr)); -#endif -} - -/** - \brief Get PRSR - \details Returns the current value of PRSR. - \return PRSR value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_PRSR(void) -{ - uint32_t result; - -#ifdef __CK610 - __ASM volatile("mfcr %0, cr21" : "=r"(result)); -#else - __ASM volatile("mfcr %0, cr<21, 0>" : "=r"(result)); -#endif - return (result); -} - -/** - \brief Set ATTR0 - \details Assigns the given value to the ATTR0. - - \param [in] attr0 ATTR0 value to set - */ -__ALWAYS_STATIC_INLINE void __set_ATTR0(uint32_t attr0) -{ - __ASM volatile("mtcr %0, cr<26, 0>\n" : : "r"(attr0)); -} - -/** - \brief Get ATTR0 - \details Returns the current value of ATTR0. - \return ATTR0 value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_ATTR0(void) -{ - uint32_t result; - - __ASM volatile("mfcr %0, cr<26, 0>" : "=r"(result)); - - return (result); -} - -/** - \brief Set ATTR1 - \details Assigns the given value to the ATTR1. - - \param [in] attr0 ATTR1 value to set - */ -__ALWAYS_STATIC_INLINE void __set_ATTR1(uint32_t attr1) -{ - __ASM volatile("mtcr %0, cr<27, 0>\n" : : "r"(attr1)); -} - -/** - \brief Get ATTR1 - \details Returns the current value of ATTR1. - \return ATTR1 value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_ATTR1(void) -{ - uint32_t result; - - __ASM volatile("mfcr %0, cr<27, 0>" : "=r"(result)); - - return (result); -} - -/** - \brief Get user sp - \details Returns the current value of user r14. - \return UR14 value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_UR14(void) -{ - uint32_t result; - -#ifdef __CK610 - __ASM volatile("mov %0, sp" : "=r"(result)); -#else - __ASM volatile("mfcr %0, cr<14, 1>" : "=r"(result)); -#endif - return (result); -} - -/** - \brief Set UR14 - \details Assigns the given value to the UR14. - \param [in] ur14 UR14 value to set - */ -__ALWAYS_STATIC_INLINE void __set_UR14(uint32_t ur14) -{ -#ifdef __CK610 - __ASM volatile("mov sp, %0" : "=r"(ur14)); -#else - __ASM volatile("mtcr %0, cr<14, 1>\n" : : "r"(ur14)); -#endif -} - -/** - \brief Get CHR Register - \details Returns the content of the CHR Register. - \return CHR Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_CHR(void) -{ - uint32_t result; - - __ASM volatile("mfcr %0, cr<31, 0>\n" :"=r"(result)); - return (result); -} - -/** - \brief Set CHR - \details Assigns the given value to the CHR. - \param [in] chr CHR value to set - */ -__ALWAYS_STATIC_INLINE void __set_CHR(uint32_t chr) -{ - __ASM volatile("mtcr %0, cr<31, 0>\n" : : "r"(chr)); -} - -/** - \brief Get HINT - \details Returns the content of the HINT Register. - \return HINT Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_HINT(void) -{ - uint32_t result; -#ifdef __CK610 - __ASM volatile("mfcr %0, cr<30, 0>" : "=r"(result)); -#else - __ASM volatile("mfcr %0, cr<31, 0>" : "=r"(result)); -#endif - return (result); -} - -/** - \brief Set HINT - \details Writes the given value to the HINT Register. - \param [in] hint HINT Register value to set - */ -__ALWAYS_STATIC_INLINE void __set_HINT(uint32_t hint) -{ -#ifdef __CK610 - __ASM volatile("mtcr %0, cr<30, 0>" : "=r"(hint)); -#else - __ASM volatile("mtcr %0, cr<31, 0>" : : "r"(hint)); -#endif -} - -/** - \brief Get MIR - \details Returns the content of the MIR Register. - \return MIR Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_MIR(void) -{ - uint32_t result; -#ifdef __CK610 - __ASM volatile("cpseti 15"); - __ASM volatile("cprcr %0, cpcr0" : "=r"(result)); -#else - __ASM volatile("mfcr %0, cr<0, 15>" : "=r"(result)); -#endif - return (result); -} - -/** - \brief Set MIR - \details Writes the given value to the MIR Register. - \param [in] mir MIR Register value to set - */ -__ALWAYS_STATIC_INLINE void __set_MIR(uint32_t mir) -{ -#ifdef __CK610 - __ASM volatile("cpseti 15"); - __ASM volatile("cpwcr %0, cpcr0" : : "b"(mir)); -#else - __ASM volatile("mtcr %0, cr<0, 15>" : : "r"(mir)); -#endif -} - - -/** - \brief Get MEL0 - \details Returns the content of the MEL0 Register. - \return MEL0 Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_MEL0(void) -{ - uint32_t result; -#ifdef __CK610 - __ASM volatile("cpseti 15"); - __ASM volatile("cprcr %0, cpcr2" : "=r"(result)); -#else - __ASM volatile("mfcr %0, cr<2, 15>" : "=r"(result)); -#endif - return (result); -} - -/** - \brief Set MEL0 - \details Writes the given value to the MEL0 Register. - \param [in] mel0 MEL0 Register value to set - */ -__ALWAYS_STATIC_INLINE void __set_MEL0(uint32_t mel0) -{ -#ifdef __CK610 - __ASM volatile("cpseti 15"); - __ASM volatile("cpwcr %0, cpcr2" : : "b"(mel0)); -#else - __ASM volatile("mtcr %0, cr<2, 15>" : : "r"(mel0)); -#endif -} - - -/** - \brief Get MEL1 - \details Returns the content of the MEL1 Register. - \return MEL1 Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_MEL1(void) -{ - uint32_t result; -#ifdef __CK610 - __ASM volatile("cpseti 15"); - __ASM volatile("cprcr %0, cpcr3" : "=r"(result)); -#else - __ASM volatile("mfcr %0, cr<3, 15>" : "=r"(result)); -#endif - return (result); -} - -/** - \brief Set MEL1 - \details Writes the given value to the MEL1 Register. - \param [in] mel1 MEL1 Register value to set - */ -__ALWAYS_STATIC_INLINE void __set_MEL1(uint32_t mel1) -{ -#ifdef __CK610 - __ASM volatile("cpseti 15"); - __ASM volatile("cpwcr %0, cpcr3" : : "b"(mel1)); -#else - __ASM volatile("mtcr %0, cr<3, 15>" : : "r"(mel1)); -#endif -} - - -/** - \brief Get MEH - \details Returns the content of the MEH Register. - \return MEH Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_MEH(void) -{ - uint32_t result; -#ifdef __CK610 - __ASM volatile("cpseti 15"); - __ASM volatile("cprcr %0, cpcr4" : "=r"(result)); -#else - __ASM volatile("mfcr %0, cr<4, 15>" : "=r"(result)); -#endif - return (result); -} - -/** - \brief Set MEH - \details Writes the given value to the MEH Register. - \param [in] meh MEH Register value to set - */ -__ALWAYS_STATIC_INLINE void __set_MEH(uint32_t meh) -{ -#ifdef __CK610 - __ASM volatile("cpseti 15"); - __ASM volatile("cpwcr %0, cpcr4" : : "b"(meh)); -#else - __ASM volatile("mtcr %0, cr<4, 15>" : : "r"(meh)); -#endif -} - - -/** - \brief Get MPR - \details Returns the content of the MPR Register. - \return MPR Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_MPR(void) -{ - uint32_t result; -#ifdef __CK610 - __ASM volatile("cpseti 15"); - __ASM volatile("cprcr %0, cpcr6" : "=r"(result)); -#else - __ASM volatile("mfcr %0, cr<6, 15>" : "=r"(result)); -#endif - return (result); -} - -/** - \brief Set MPR - \details Writes the given value to the MPR Register. - \param [in] mpr MPR Register value to set - */ -__ALWAYS_STATIC_INLINE void __set_MPR(uint32_t mpr) -{ -#ifdef __CK610 - __ASM volatile("cpseti 15"); - __ASM volatile("cpwcr %0, cpcr6" : : "b"(mpr)); -#else - __ASM volatile("mtcr %0, cr<6, 15>" : : "r"(mpr)); -#endif -} - - -/** - \brief Get MCIR - \details Returns the content of the MCIR Register. - \return MCIR Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_MCIR(void) -{ - uint32_t result; -#ifdef __CK610 - __ASM volatile("cpseti 15"); - __ASM volatile("cprcr %0, cpcr8" : "=r"(result)); -#else - __ASM volatile("mfcr %0, cr<8, 15>" : "=r"(result)); -#endif - return (result); -} - -/** - \brief Set MCIR - \details Writes the given value to the MCIR Register. - \param [in] mcir MCIR Register value to set - */ -__ALWAYS_STATIC_INLINE void __set_MCIR(uint32_t mcir) -{ -#ifdef __CK610 - __ASM volatile("cpseti 15"); - __ASM volatile("cpwcr %0, cpcr8" : : "b"(mcir)); -#else - __ASM volatile("mtcr %0, cr<8, 15>" : : "r"(mcir)); -#endif -} - - -/** - \brief Get MPGD - \details Returns the content of the MPGD Register. - \return MPGD Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_MPGD(void) -{ - uint32_t result; -#ifdef __CK610 - __ASM volatile("cpseti 15"); - __ASM volatile("cprcr %0, cpcr29" : "=r"(result)); -#else - __ASM volatile("mfcr %0, cr<29, 15>" : "=r"(result)); -#endif - return (result); -} - -/** - \brief Set MPGD - \details Writes the given value to the MPGD Register. - \param [in] mpgd MPGD Register value to set - */ -__ALWAYS_STATIC_INLINE void __set_MPGD(uint32_t mpgd) -{ -#ifdef __CK610 - __ASM volatile("cpseti 15"); - __ASM volatile("cpwcr %0, cpcr29" : : "b"(mpgd)); -#else - __ASM volatile("mtcr %0, cr<29, 15>" : : "r"(mpgd)); -#endif -} - - -/** - \brief Get MSA0 - \details Returns the content of the MSA0 Register. - \return MSA0 Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_MSA0(void) -{ - uint32_t result; -#ifdef __CK610 - __ASM volatile("cpseti 15"); - __ASM volatile("cprcr %0, cpcr30" : "=r"(result)); -#else - __ASM volatile("mfcr %0, cr<30, 15>" : "=r"(result)); -#endif - return (result); -} - -/** - \brief Set MSA0 - \details Writes the given value to the MSA0 Register. - \param [in] msa0 MSA0 Register value to set - */ -__ALWAYS_STATIC_INLINE void __set_MSA0(uint32_t msa0) -{ -#ifdef __CK610 - __ASM volatile("cpseti 15"); - __ASM volatile("cpwcr %0, cpcr30" : : "b"(msa0)); -#else - __ASM volatile("mtcr %0, cr<30, 15>" : : "r"(msa0)); -#endif -} - - -/** - \brief Get MSA1 - \details Returns the content of the MSA1 Register. - \return MSA1 Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_MSA1(void) -{ - uint32_t result; - -#ifdef __CK610 - __ASM volatile("cpseti 15"); - __ASM volatile("cprcr %0, cpcr31" : "=r"(result)); -#else - __ASM volatile("mfcr %0, cr<31, 15>" : "=r"(result)); -#endif - return (result); -} - -/** - \brief Set MSA1 - \details Writes the given value to the MSA1 Register. - \param [in] msa1 MSA1 Register value to set - */ -__ALWAYS_STATIC_INLINE void __set_MSA1(uint32_t msa1) -{ -#ifdef __CK610 - __ASM volatile("cpseti 15"); - __ASM volatile("cpwcr %0, cpcr31" : : "b"(msa1)); -#else - __ASM volatile("mtcr %0, cr<31, 15>" : : "r"(msa1)); -#endif -} - - -/** - \brief Enable interrupts and exceptions - \details Enables interrupts and exceptions by setting the IE-bit and EE-bit in the PSR. - Can only be executed in Privileged modes. - */ -__ALWAYS_STATIC_INLINE void __enable_excp_irq(void) -{ - __ASM volatile("psrset ee, ie"); -} - - -/** - \brief Disable interrupts and exceptions - \details Disables interrupts and exceptions by clearing the IE-bit and EE-bit in the PSR. - Can only be executed in Privileged modes. - */ -__ALWAYS_STATIC_INLINE void __disable_excp_irq(void) -{ - __ASM volatile("psrclr ee, ie"); -} - -/** - \brief Get GSR - \details Returns the content of the GSR Register. - \return GSR Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_GSR(void) -{ - uint32_t result; - -#ifdef __CK610 - __ASM volatile("mfcr %0, cr12" : "=r"(result)); -#else - __ASM volatile("mfcr %0, cr<12, 0>" : "=r"(result)); -#endif - return (result); -} - -/** - \brief Get GCR - \details Returns the content of the GCR Register. - \return GCR Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_GCR(void) -{ - uint32_t result; - -#ifdef __CK610 - __ASM volatile("mfcr %0, cr11" : "=r"(result)); -#else - __ASM volatile("mfcr %0, cr<11, 0>" : "=r"(result)); -#endif - return (result); -} - -/** - \brief Set GCR - \details Writes the given value to the GCR Register. - \param [in] gcr GCR Register value to set - */ -__ALWAYS_STATIC_INLINE void __set_GCR(uint32_t gcr) -{ -#ifdef __CK610 - __ASM volatile("mtcr %0, cr11" : : "r"(gcr)); -#else - __ASM volatile("mtcr %0, cr<11, 0>" : : "r"(gcr)); -#endif -} - -/** - \brief Get WSSR - \details Returns the content of the WSSR Register, must be accessed in TEE - \return WSSR Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_WSSR(void) -{ - uint32_t result; - - __ASM volatile("mfcr %0, cr<0, 3>" : "=r"(result)); - return (result); -} - -/** - \brief Get WRCR - \details Returns the content of the WRCR Register, must be accessed in TEE - \return WRCR Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_WRCR(void) -{ - uint32_t result; - - __ASM volatile("mfcr %0, cr<1, 3>" : "=r"(result)); - return (result); -} - -/** - \brief Set WRCR - \details Writes the given value to the WRCR Register, must be accessed in TEE - \param [in] wrcr WRCR Register value to set - */ -__ALWAYS_STATIC_INLINE void __set_WRCR(uint32_t wrcr) -{ - __ASM volatile("mtcr %0, cr<1, 3>" : : "r"(wrcr)); -} - -/** - \brief Get DCR - \details Returns the content of the DCR Register, must be accessed in TEE - \return DCR Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_DCR(void) -{ - uint32_t result; - - __ASM volatile("mfcr %0, cr<8, 3>" : "=r"(result)); - return (result); -} - -/** - \brief Set DCR - \details Writes the given value to the DCR Register, must be accessed in TEE - \param [in] dcr DCR Register value to set - */ -__ALWAYS_STATIC_INLINE void __set_DCR(uint32_t dcr) -{ - __ASM volatile("mtcr %0, cr<8, 3>" : : "r"(dcr)); -} - -/** - \brief Get PCR - \details Returns the content of the PCR Register, must be accessed in TEE - \return PCR Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_PCR(void) -{ - uint32_t result; - - __ASM volatile("mfcr %0, cr<9, 3>" : "=r"(result)); - return (result); -} - -/** - \brief Set PCR - \details Writes the given value to the PCR Register, must be accessed in TEE - \param [in] pcr PCR Register value to set - */ -__ALWAYS_STATIC_INLINE void __set_PCR(uint32_t pcr) -{ - __ASM volatile("mtcr %0, cr<9, 3>" : : "r"(pcr)); -} - -/** - \brief Get EBR - \details Returns the content of the EBR Register. - \return EBR Register value - */ -__ALWAYS_STATIC_INLINE uint32_t __get_EBR(void) -{ - uint32_t result; - - __ASM volatile("mfcr %0, cr<1, 1>" : "=r"(result)); - return (result); -} - -/** - \brief Set EBR - \details Writes the given value to the EBR Register. - \param [in] ebr EBR Register value to set - */ -__ALWAYS_STATIC_INLINE void __set_EBR(uint32_t ebr) -{ - __ASM volatile("mtcr %0, cr<1, 1>" : : "r"(ebr)); -} - -/*@} end of CSI_Core_RegAccFunctions */ - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CSI_Core_InstructionInterface CSI Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#define __CSI_GCC_OUT_REG(r) "=r" (r) -#define __CSI_GCC_USE_REG(r) "r" (r) - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__ALWAYS_STATIC_INLINE void __NOP(void) -{ - __ASM volatile("nop"); -} - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -__ALWAYS_STATIC_INLINE void __WFI(void) -{ - __ASM volatile("wait"); -} - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one interrupt occurs. - */ -__ALWAYS_STATIC_INLINE void __WAIT(void) -{ - __ASM volatile("wait"); -} - -/** - \brief Doze For Interrupt - \details Doze For Interrupt is a hint instruction that suspends execution until one interrupt occurs. - */ -__ALWAYS_STATIC_INLINE void __DOZE(void) -{ - __ASM volatile("doze"); -} - -/** - \brief Stop For Interrupt - \details Stop For Interrupt is a hint instruction that suspends execution until one interrupt occurs. - */ -__ALWAYS_STATIC_INLINE void __STOP(void) -{ - __ASM volatile("stop"); -} - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__ALWAYS_STATIC_INLINE void __ISB(void) -{ - __ASM volatile("sync"::: "memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__ALWAYS_STATIC_INLINE void __DSB(void) -{ - __ASM volatile("sync"::: "memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__ALWAYS_STATIC_INLINE void __DMB(void) -{ - __ASM volatile("sync"::: "memory"); -} - -/** - \brief Search from the highest bit that the very first bit which's value is 1. - \param [in] value Value to bit search. - \return if the highest bit' value is 1, return 0, and if lowest bit's value is 1, return 31, otherwise return 32. - */ -#if !defined(__CK610) || !(__CK80X == 1) -__ALWAYS_STATIC_INLINE uint32_t __FF0(uint32_t value) -{ - uint32_t ret; - - __ASM volatile("ff0 %0, %1" : "=r"(ret) : "r"(value)); - return ret; -} -#endif - -/** - \brief Search from the highest bit that the very first bit which's value is 0. - \param [in] value Value to bit search. - \return if the highest bit' value is 0, return 0, and if lowest bit's value is 0, return 31, otherwise return 32. - */ -#if !(__CK80X == 1) -__ALWAYS_STATIC_INLINE uint32_t __FF1(uint32_t value) -{ - uint32_t ret; -#if !defined (__CK610) - __ASM volatile("ff1 %0, %1" : "=r"(ret) : "r"(value)); -#else - ret = value; - __ASM volatile("ff1 %0" : "=r"(ret):); -#endif - return ret; -} -#endif - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -__ALWAYS_STATIC_INLINE uint32_t __REV(uint32_t value) -{ - return __builtin_bswap32(value); -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -__ALWAYS_STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; -#if (__CK80X >= 2) - __ASM volatile("revh %0, %1" : __CSI_GCC_OUT_REG(result) : __CSI_GCC_USE_REG(value)); -#else - result = ((value & 0xFF000000) >> 8) | ((value & 0x00FF0000) << 8) | - ((value & 0x0000FF00) >> 8) | ((value & 0x000000FF) << 8); -#endif - return (result); -} - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -__ALWAYS_STATIC_INLINE int32_t __REVSH(int32_t value) -{ - return (short)(((value & 0xFF00) >> 8) | ((value & 0x00FF) << 8)); -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__ALWAYS_STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - */ -__ALWAYS_STATIC_INLINE void __BKPT(void) -{ - __ASM volatile("bkpt"); -} - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__ALWAYS_STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if (__CK80X >= 0x03U) - __ASM volatile("brev %0, %1" : "=r"(result) : "r"(value)); -#else - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - - for (value >>= 1U; value; value >>= 1U) { - result <<= 1U; - result |= value & 1U; - s--; - } - - result <<= s; /* shift when v's highest bits are zero */ -#endif - return (result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz -/** - \details This function saturates a signed value. - \param [in] x Value to be saturated - \param [in] y Bit position to saturate to [1..32] - \return Saturated value. - */ -__ALWAYS_STATIC_INLINE int32_t __SSAT(int32_t x, uint32_t y) -{ - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - - for (i = 0; i < (y - 1); i++) { - posMax = posMax * 2; - } - - if (x > 0) { - posMax = (posMax - 1); - - if (x > posMax) { - x = posMax; - } - -// x &= (posMax * 2 + 1); - } else { - negMin = -posMax; - - if (x < negMin) { - x = negMin; - } - -// x &= (posMax * 2 - 1); - } - - return (x); -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__ALWAYS_STATIC_INLINE uint32_t __USAT(uint32_t value, uint32_t sat) -{ - uint32_t result; - - if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) { - result = 0xFFFFFFFF >> (32 - sat); - } else { - result = value; - } - - return (result); -} - -/** - \brief Unsigned Saturate for internal use - \details Saturates an unsigned value, should not call directly. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__ALWAYS_STATIC_INLINE uint32_t __IUSAT(uint32_t value, uint32_t sat) -{ - uint32_t result; - - if (value & 0x80000000) { /* only overflow set bit-31 */ - result = 0; - } else if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) { - result = 0xFFFFFFFF >> (32 - sat); - } else { - result = value; - } - - return (result); -} - -/** - \brief Rotate Right with Extend - \details This function moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \note carry input will always 0. - \param [in] op1 Value to rotate - \return Rotated value - */ -__ALWAYS_STATIC_INLINE uint32_t __RRX(uint32_t op1) -{ -#if (__CK80X >= 2) - uint32_t res = 0; - __ASM volatile("bgeni t0, 31\n\t" - "lsri %0, 1\n\t" - "movt %1, t0\n\t" - "or %1, %1, %0\n\t" - : "=r"(op1), "=r"(res): "0"(op1), "1"(res): "t0"); - return res; -#else - uint32_t res = 0; - __ASM volatile("movi r7, 0\n\t" - "bseti r7, 31\n\t" - "lsri %0, 1\n\t" - "bf 1f\n\t" - "mov %1, r7\n\t" - "1:\n\t" - "or %1, %1, %0\n\t" - : "=r"(op1), "=r"(res): "0"(op1), "1"(res): "r7"); - return res; -#endif -} - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] addr Pointer to location - \return value of type uint8_t at (*ptr) - */ -__ALWAYS_STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) -{ - uint32_t result; -//#warning "__LDRBT" - __ASM volatile("ldb %0, (%1, 0)" : "=r"(result) : "r"(addr)); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] addr Pointer to location - \return value of type uint16_t at (*ptr) - */ -__ALWAYS_STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) -{ - uint32_t result; - -//#warning "__LDRHT" - __ASM volatile("ldh %0, (%1, 0)" : "=r"(result) : "r"(addr)); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] addr Pointer to location - \return value of type uint32_t at (*ptr) - */ -__ALWAYS_STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) -{ - uint32_t result; - -//#warning "__LDRT" - __ASM volatile("ldw %0, (%1, 0)" : "=r"(result) : "r"(addr)); - return (result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] addr Pointer to location - */ -__ALWAYS_STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) -{ -//#warning "__STRBT" - __ASM volatile("stb %1, (%0, 0)" :: "r"(addr), "r"((uint32_t)value) : "memory"); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] addr Pointer to location - */ -__ALWAYS_STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) -{ -//#warning "__STRHT" - __ASM volatile("sth %1, (%0, 0)" :: "r"(addr), "r"((uint32_t)value) : "memory"); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] addr Pointer to location - */ -__ALWAYS_STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) -{ -//#warning "__STRT" - __ASM volatile("stw %1, (%0, 0)" :: "r"(addr), "r"(value) : "memory"); -} - -/*@}*/ /* end of group CSI_Core_InstructionInterface */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CSI_Core_FunctionInterface - \defgroup CSI_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type, always 0. - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__ALWAYS_STATIC_INLINE uint32_t __get_FPUType(void) -{ -//FIXME: - return 0; -} - -/*@} end of CSI_Core_FpuFunctions */ - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CSI_SIMD_intrinsics CSI SIMD Intrinsics - Access to dedicated SIMD instructions \n - Single Instruction Multiple Data (SIMD) extensions are provided to simplify development of application software. SIMD extensions increase the processing capability without materially increasing the power consumption. The SIMD extensions are completely transparent to the operating system (OS), allowing existing OS ports to be used. - - @{ -*/ - -/** - \brief Halfword packing instruction. Combines bits[15:0] of val1 with bits[31:16] - of val2 levitated with the val3. - \details Combine a halfword from one register with a halfword from another register. - The second argument can be left-shifted before extraction of the halfword. - \param [in] val1 first 16-bit operands - \param [in] val2 second 16-bit operands - \param [in] val3 value for left-shifting val2. Value range [0..31]. - \return the combination of halfwords. - \remark - res[15:0] = val1[15:0] \n - res[31:16] = val2[31:16] << val3 - */ -__ALWAYS_STATIC_INLINE uint32_t __PKHBT(uint32_t val1, uint32_t val2, uint32_t val3) -{ - return ((((int32_t)(val1) << 0) & (int32_t)0x0000FFFF) | (((int32_t)(val2) << val3) & (int32_t)0xFFFF0000)); -} - -/** - \brief Halfword packing instruction. Combines bits[31:16] of val1 with bits[15:0] - of val2 right-shifted with the val3. - \details Combine a halfword from one register with a halfword from another register. - The second argument can be right-shifted before extraction of the halfword. - \param [in] val1 first 16-bit operands - \param [in] val2 second 16-bit operands - \param [in] val3 value for right-shifting val2. Value range [1..32]. - \return the combination of halfwords. - \remark - res[15:0] = val2[15:0] >> val3 \n - res[31:16] = val1[31:16] - */ -__ALWAYS_STATIC_INLINE uint32_t __PKHTB(uint32_t val1, uint32_t val2, uint32_t val3) -{ - return ((((int32_t)(val1) << 0) & (int32_t)0xFFFF0000) | (((int32_t)(val2) >> val3) & (int32_t)0x0000FFFF)); -} - -/** - \brief Dual 16-bit signed saturate. - \details This function saturates a signed value. - \param [in] x two signed 16-bit values to be saturated. - \param [in] y bit position for saturation, an integral constant expression in the range 1 to 16. - \return the sum of the absolute differences of the following bytes, added to the accumulation value:\n - the signed saturation of the low halfword in val1, saturated to the bit position specified in - val2 and returned in the low halfword of the return value.\n - the signed saturation of the high halfword in val1, saturated to the bit position specified in - val2 and returned in the high halfword of the return value. - */ -__ALWAYS_STATIC_INLINE uint32_t __SSAT16(int32_t x, const uint32_t y) -{ - int32_t r = 0, s = 0; - - r = __SSAT((((int32_t)x << 16) >> 16), y) & (int32_t)0x0000FFFF; - s = __SSAT((((int32_t)x) >> 16), y) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r))); -} - -/** - \brief Dual 16-bit unsigned saturate. - \details This function enables you to saturate two signed 16-bit values to a selected unsigned range. - \param [in] x two signed 16-bit values to be saturated. - \param [in] y bit position for saturation, an integral constant expression in the range 1 to 16. - \return the saturation of the two signed 16-bit values, as non-negative values: - the saturation of the low halfword in val1, saturated to the bit position specified in - val2 and returned in the low halfword of the return value.\n - the saturation of the high halfword in val1, saturated to the bit position specified in - val2 and returned in the high halfword of the return value. - */ -__ALWAYS_STATIC_INLINE uint32_t __USAT16(uint32_t x, const uint32_t y) -{ - int32_t r = 0, s = 0; - - r = __IUSAT(((x << 16) >> 16), y) & 0x0000FFFF; - s = __IUSAT(((x) >> 16), y) & 0x0000FFFF; - - return ((s << 16) | (r)); -} - -/** - \brief Quad 8-bit saturating addition. - \details This function enables you to perform four 8-bit integer additions, - saturating the results to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1. - \param [in] x first four 8-bit summands. - \param [in] y second four 8-bit summands. - \return the saturated addition of the first byte of each operand in the first byte of the return value.\n - the saturated addition of the second byte of each operand in the second byte of the return value.\n - the saturated addition of the third byte of each operand in the third byte of the return value.\n - the saturated addition of the fourth byte of each operand in the fourth byte of the return value.\n - The returned results are saturated to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1. - \remark - res[7:0] = val1[7:0] + val2[7:0] \n - res[15:8] = val1[15:8] + val2[15:8] \n - res[23:16] = val1[23:16] + val2[23:16] \n - res[31:24] = val1[31:24] + val2[31:24] - */ -__ALWAYS_STATIC_INLINE uint32_t __QADD8(uint32_t x, uint32_t y) -{ - int32_t r, s, t, u; - - r = __SSAT(((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((int32_t)x) >> 24) + (((int32_t)y) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); -} - -/** - \brief Quad 8-bit unsigned saturating addition. - \details This function enables you to perform four unsigned 8-bit integer additions, - saturating the results to the 8-bit unsigned integer range 0 < x < 2^8 - 1. - \param [in] x first four 8-bit summands. - \param [in] y second four 8-bit summands. - \return the saturated addition of the first byte of each operand in the first byte of the return value.\n - the saturated addition of the second byte of each operand in the second byte of the return value.\n - the saturated addition of the third byte of each operand in the third byte of the return value.\n - the saturated addition of the fourth byte of each operand in the fourth byte of the return value.\n - The returned results are saturated to the 8-bit signed integer range 0 <= x <= 2^8 - 1. - \remark - res[7:0] = val1[7:0] + val2[7:0] \n - res[15:8] = val1[15:8] + val2[15:8] \n - res[23:16] = val1[23:16] + val2[23:16] \n - res[31:24] = val1[31:24] + val2[31:24] - */ -__ALWAYS_STATIC_INLINE uint32_t __UQADD8(uint32_t x, uint32_t y) -{ - int32_t r, s, t, u; - - r = __IUSAT((((x << 24) >> 24) + ((y << 24) >> 24)), 8) & 0x000000FF; - s = __IUSAT((((x << 16) >> 24) + ((y << 16) >> 24)), 8) & 0x000000FF; - t = __IUSAT((((x << 8) >> 24) + ((y << 8) >> 24)), 8) & 0x000000FF; - u = __IUSAT((((x) >> 24) + ((y) >> 24)), 8) & 0x000000FF; - - return ((u << 24) | (t << 16) | (s << 8) | (r)); -} - -/** - \brief Quad 8-bit signed addition. - \details This function performs four 8-bit signed integer additions. - \param [in] x first four 8-bit summands. - \param [in] y second four 8-bit summands. - \return the addition of the first bytes from each operand, in the first byte of the return value.\n - the addition of the second bytes of each operand, in the second byte of the return value.\n - the addition of the third bytes of each operand, in the third byte of the return value.\n - the addition of the fourth bytes of each operand, in the fourth byte of the return value. - \remark - res[7:0] = val1[7:0] + val2[7:0] \n - res[15:8] = val1[15:8] + val2[15:8] \n - res[23:16] = val1[23:16] + val2[23:16] \n - res[31:24] = val1[31:24] + val2[31:24] - */ -__ALWAYS_STATIC_INLINE uint32_t __SADD8(uint32_t x, uint32_t y) -{ - int32_t r, s, t, u; - - r = ((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)) & (int32_t)0x000000FF; - s = ((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)) & (int32_t)0x000000FF; - t = ((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)) & (int32_t)0x000000FF; - u = ((((int32_t)x) >> 24) + (((int32_t)y) >> 24)) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); -} - -/** - \brief Quad 8-bit unsigned addition. - \details This function performs four unsigned 8-bit integer additions. - \param [in] x first four 8-bit summands. - \param [in] y second four 8-bit summands. - \return the addition of the first bytes from each operand, in the first byte of the return value.\n - the addition of the second bytes of each operand, in the second byte of the return value.\n - the addition of the third bytes of each operand, in the third byte of the return value.\n - the addition of the fourth bytes of each operand, in the fourth byte of the return value. - \remark - res[7:0] = val1[7:0] + val2[7:0] \n - res[15:8] = val1[15:8] + val2[15:8] \n - res[23:16] = val1[23:16] + val2[23:16] \n - res[31:24] = val1[31:24] + val2[31:24] - */ -__ALWAYS_STATIC_INLINE uint32_t __UADD8(uint32_t x, uint32_t y) -{ - int32_t r, s, t, u; - - r = (((x << 24) >> 24) + ((y << 24) >> 24)) & 0x000000FF; - s = (((x << 16) >> 24) + ((y << 16) >> 24)) & 0x000000FF; - t = (((x << 8) >> 24) + ((y << 8) >> 24)) & 0x000000FF; - u = (((x) >> 24) + ((y) >> 24)) & 0x000000FF; - - return ((u << 24) | (t << 16) | (s << 8) | (r)); -} - -/** - \brief Quad 8-bit saturating subtract. - \details This function enables you to perform four 8-bit integer subtractions, - saturating the results to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1. - \param [in] x first four 8-bit summands. - \param [in] y second four 8-bit summands. - \return the subtraction of the first byte of each operand in the first byte of the return value.\n - the subtraction of the second byte of each operand in the second byte of the return value.\n - the subtraction of the third byte of each operand in the third byte of the return value.\n - the subtraction of the fourth byte of each operand in the fourth byte of the return value.\n - The returned results are saturated to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1. - \remark - res[7:0] = val1[7:0] - val2[7:0] \n - res[15:8] = val1[15:8] - val2[15:8] \n - res[23:16] = val1[23:16] - val2[23:16] \n - res[31:24] = val1[31:24] - val2[31:24] - */ -__ALWAYS_STATIC_INLINE uint32_t __QSUB8(uint32_t x, uint32_t y) -{ - int32_t r, s, t, u; - - r = __SSAT(((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((int32_t)x) >> 24) - (((int32_t)y) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); -} - -/** - \brief Quad 8-bit unsigned saturating subtraction. - \details This function enables you to perform four unsigned 8-bit integer subtractions, - saturating the results to the 8-bit unsigned integer range 0 < x < 2^8 - 1. - \param [in] x first four 8-bit summands. - \param [in] y second four 8-bit summands. - \return the subtraction of the first byte of each operand in the first byte of the return value.\n - the subtraction of the second byte of each operand in the second byte of the return value.\n - the subtraction of the third byte of each operand in the third byte of the return value.\n - the subtraction of the fourth byte of each operand in the fourth byte of the return value.\n - The returned results are saturated to the 8-bit unsigned integer range 0 <= x <= 2^8 - 1. - \remark - res[7:0] = val1[7:0] - val2[7:0] \n - res[15:8] = val1[15:8] - val2[15:8] \n - res[23:16] = val1[23:16] - val2[23:16] \n - res[31:24] = val1[31:24] - val2[31:24] - */ -__ALWAYS_STATIC_INLINE uint32_t __UQSUB8(uint32_t x, uint32_t y) -{ - int32_t r, s, t, u; - - r = __IUSAT((((x << 24) >> 24) - ((y << 24) >> 24)), 8) & 0x000000FF; - s = __IUSAT((((x << 16) >> 24) - ((y << 16) >> 24)), 8) & 0x000000FF; - t = __IUSAT((((x << 8) >> 24) - ((y << 8) >> 24)), 8) & 0x000000FF; - u = __IUSAT((((x) >> 24) - ((y) >> 24)), 8) & 0x000000FF; - - return ((u << 24) | (t << 16) | (s << 8) | (r)); -} - -/** - \brief Quad 8-bit signed subtraction. - \details This function enables you to perform four 8-bit signed integer subtractions. - \param [in] x first four 8-bit operands of each subtraction. - \param [in] y second four 8-bit operands of each subtraction. - \return the subtraction of the first bytes from each operand, in the first byte of the return value.\n - the subtraction of the second bytes of each operand, in the second byte of the return value.\n - the subtraction of the third bytes of each operand, in the third byte of the return value.\n - the subtraction of the fourth bytes of each operand, in the fourth byte of the return value. - \remark - res[7:0] = val1[7:0] - val2[7:0] \n - res[15:8] = val1[15:8] - val2[15:8] \n - res[23:16] = val1[23:16] - val2[23:16] \n - res[31:24] = val1[31:24] - val2[31:24] - */ -__ALWAYS_STATIC_INLINE uint32_t __SSUB8(uint32_t x, uint32_t y) -{ - int32_t r, s, t, u; - - r = ((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)) & (int32_t)0x000000FF; - s = ((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)) & (int32_t)0x000000FF; - t = ((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)) & (int32_t)0x000000FF; - u = ((((int32_t)x) >> 24) - (((int32_t)y) >> 24)) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); -} - -/** - \brief Quad 8-bit unsigned subtract. - \details This function enables you to perform four 8-bit unsigned integer subtractions. - \param [in] x first four 8-bit operands of each subtraction. - \param [in] y second four 8-bit operands of each subtraction. - \return the subtraction of the first bytes from each operand, in the first byte of the return value.\n - the subtraction of the second bytes of each operand, in the second byte of the return value.\n - the subtraction of the third bytes of each operand, in the third byte of the return value.\n - the subtraction of the fourth bytes of each operand, in the fourth byte of the return value. - \remark - res[7:0] = val1[7:0] - val2[7:0] \n - res[15:8] = val1[15:8] - val2[15:8] \n - res[23:16] = val1[23:16] - val2[23:16] \n - res[31:24] = val1[31:24] - val2[31:24] - */ -__ALWAYS_STATIC_INLINE uint32_t __USUB8(uint32_t x, uint32_t y) -{ - int32_t r, s, t, u; - - r = (((x << 24) >> 24) - ((y << 24) >> 24)) & 0x000000FF; - s = (((x << 16) >> 24) - ((y << 16) >> 24)) & 0x000000FF; - t = (((x << 8) >> 24) - ((y << 8) >> 24)) & 0x000000FF; - u = (((x) >> 24) - ((y) >> 24)) & 0x000000FF; - - return ((u << 24) | (t << 16) | (s << 8) | (r)); -} - -/** - \brief Unsigned sum of quad 8-bit unsigned absolute difference. - \details This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values - of the differences together, returning the result as a single unsigned integer. - \param [in] x first four 8-bit operands of each subtraction. - \param [in] y second four 8-bit operands of each subtraction. - \return the subtraction of the first bytes from each operand, in the first byte of the return value.\n - the subtraction of the second bytes of each operand, in the second byte of the return value.\n - the subtraction of the third bytes of each operand, in the third byte of the return value.\n - the subtraction of the fourth bytes of each operand, in the fourth byte of the return value.\n - The sum is returned as a single unsigned integer. - \remark - absdiff1 = val1[7:0] - val2[7:0] \n - absdiff2 = val1[15:8] - val2[15:8] \n - absdiff3 = val1[23:16] - val2[23:16] \n - absdiff4 = val1[31:24] - val2[31:24] \n - res[31:0] = absdiff1 + absdiff2 + absdiff3 + absdiff4 - */ -__ALWAYS_STATIC_INLINE uint32_t __USAD8(uint32_t x, uint32_t y) -{ - int32_t r, s, t, u; - - r = (((x << 24) >> 24) - ((y << 24) >> 24)) & 0x000000FF; - s = (((x << 16) >> 24) - ((y << 16) >> 24)) & 0x000000FF; - t = (((x << 8) >> 24) - ((y << 8) >> 24)) & 0x000000FF; - u = (((x) >> 24) - ((y) >> 24)) & 0x000000FF; - - return (u + t + s + r); -} - -/** - \brief Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate. - \details This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values - of the differences to a 32-bit accumulate operand. - \param [in] x first four 8-bit operands of each subtraction. - \param [in] y second four 8-bit operands of each subtraction. - \param [in] sum accumulation value. - \return the sum of the absolute differences of the following bytes, added to the accumulation value: - the subtraction of the first bytes from each operand, in the first byte of the return value.\n - the subtraction of the second bytes of each operand, in the second byte of the return value.\n - the subtraction of the third bytes of each operand, in the third byte of the return value.\n - the subtraction of the fourth bytes of each operand, in the fourth byte of the return value. - \remark - absdiff1 = val1[7:0] - val2[7:0] \n - absdiff2 = val1[15:8] - val2[15:8] \n - absdiff3 = val1[23:16] - val2[23:16] \n - absdiff4 = val1[31:24] - val2[31:24] \n - sum = absdiff1 + absdiff2 + absdiff3 + absdiff4 \n - res[31:0] = sum[31:0] + val3[31:0] - */ -__ALWAYS_STATIC_INLINE uint32_t __USADA8(uint32_t x, uint32_t y, uint32_t sum) -{ - int32_t r, s, t, u; - -#ifdef __cplusplus - r = (abs((long long)((x << 24) >> 24) - ((y << 24) >> 24))) & 0x000000FF; - s = (abs((long long)((x << 16) >> 24) - ((y << 16) >> 24))) & 0x000000FF; - t = (abs((long long)((x << 8) >> 24) - ((y << 8) >> 24))) & 0x000000FF; - u = (abs((long long)((x) >> 24) - ((y) >> 24))) & 0x000000FF; -#else - r = (abs(((x << 24) >> 24) - ((y << 24) >> 24))) & 0x000000FF; - s = (abs(((x << 16) >> 24) - ((y << 16) >> 24))) & 0x000000FF; - t = (abs(((x << 8) >> 24) - ((y << 8) >> 24))) & 0x000000FF; - u = (abs(((x) >> 24) - ((y) >> 24))) & 0x000000FF; -#endif - return (u + t + s + r + sum); -} - -/** - \brief Dual 16-bit saturating addition. - \details This function enables you to perform two 16-bit integer arithmetic additions in parallel, - saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. - \param [in] x first two 16-bit summands. - \param [in] y second two 16-bit summands. - \return the saturated addition of the low halfwords, in the low halfword of the return value.\n - the saturated addition of the high halfwords, in the high halfword of the return value.\n - The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. - \remark - res[15:0] = val1[15:0] + val2[15:0] \n - res[31:16] = val1[31:16] + val2[31:16] - */ -__ALWAYS_STATIC_INLINE uint32_t __QADD16(uint32_t x, uint32_t y) -{ - int32_t r = 0, s = 0; - - r = __SSAT(((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((int32_t)x) >> 16) + (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r))); -} - -/** - \brief Dual 16-bit unsigned saturating addition. - \details This function enables you to perform two unsigned 16-bit integer additions, saturating - the results to the 16-bit unsigned integer range 0 < x < 2^16 - 1. - \param [in] x first two 16-bit summands. - \param [in] y second two 16-bit summands. - \return the saturated addition of the low halfwords, in the low halfword of the return value.\n - the saturated addition of the high halfwords, in the high halfword of the return value.\n - The results are saturated to the 16-bit unsigned integer range 0 < x < 2^16 - 1. - \remark - res[15:0] = val1[15:0] + val2[15:0] \n - res[31:16] = val1[31:16] + val2[31:16] - */ -__ALWAYS_STATIC_INLINE uint32_t __UQADD16(uint32_t x, uint32_t y) -{ - int32_t r = 0, s = 0; - - r = __IUSAT((((x << 16) >> 16) + ((y << 16) >> 16)), 16) & 0x0000FFFF; - s = __IUSAT((((x) >> 16) + ((y) >> 16)), 16) & 0x0000FFFF; - - return ((s << 16) | (r)); -} - -/** - \brief Dual 16-bit signed addition. - \details This function enables you to perform two 16-bit signed integer additions. - \param [in] x first two 16-bit summands. - \param [in] y second two 16-bit summands. - \return the addition of the low halfwords in the low halfword of the return value.\n - the addition of the high halfwords in the high halfword of the return value. - \remark - res[15:0] = val1[15:0] + val2[15:0] \n - res[31:16] = val1[31:16] + val2[31:16] - */ -__ALWAYS_STATIC_INLINE uint32_t __SADD16(uint32_t x, uint32_t y) -{ - int32_t r = 0, s = 0; - - r = ((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF; - s = ((((int32_t)x) >> 16) + (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r))); -} - -/** - \brief Dual 16-bit unsigned addition - \details This function enables you to perform two 16-bit unsigned integer additions. - \param [in] x first two 16-bit summands for each addition. - \param [in] y second two 16-bit summands for each addition. - \return the addition of the low halfwords in the low halfword of the return value.\n - the addition of the high halfwords in the high halfword of the return value. - \remark - res[15:0] = val1[15:0] + val2[15:0] \n - res[31:16] = val1[31:16] + val2[31:16] - */ -__ALWAYS_STATIC_INLINE uint32_t __UADD16(uint32_t x, uint32_t y) -{ - int32_t r = 0, s = 0; - - r = (((x << 16) >> 16) + ((y << 16) >> 16)) & 0x0000FFFF; - s = (((x) >> 16) + ((y) >> 16)) & 0x0000FFFF; - - return ((s << 16) | (r)); -} - - -/** - \brief Dual 16-bit signed addition with halved results. - \details This function enables you to perform two signed 16-bit integer additions, halving the results. - \param [in] x first two 16-bit summands. - \param [in] y second two 16-bit summands. - \return the halved addition of the low halfwords, in the low halfword of the return value.\n - the halved addition of the high halfwords, in the high halfword of the return value. - \remark - res[15:0] = (val1[15:0] + val2[15:0]) >> 1 \n - res[31:16] = (val1[31:16] + val2[31:16]) >> 1 - */ -__ALWAYS_STATIC_INLINE uint32_t __SHADD16(uint32_t x, uint32_t y) -{ - int32_t r, s; - - r = (((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((int32_t)x) >> 16) + (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r))); -} - -/** - \brief Dual 16-bit unsigned addition with halved results. - \details This function enables you to perform two unsigned 16-bit integer additions, halving the results. - \param [in] x first two 16-bit summands. - \param [in] y second two 16-bit summands. - \return the halved addition of the low halfwords, in the low halfword of the return value.\n - the halved addition of the high halfwords, in the high halfword of the return value. - \remark - res[15:0] = (val1[15:0] + val2[15:0]) >> 1 \n - res[31:16] = (val1[31:16] + val2[31:16]) >> 1 - */ -__ALWAYS_STATIC_INLINE uint32_t __UHADD16(uint32_t x, uint32_t y) -{ - int32_t r, s; - - r = ((((x << 16) >> 16) + ((y << 16) >> 16)) >> 1) & 0x0000FFFF; - s = ((((x) >> 16) + ((y) >> 16)) >> 1) & 0x0000FFFF; - - return ((s << 16) | (r)); -} - -/** - \brief Quad 8-bit signed addition with halved results. - \details This function enables you to perform four signed 8-bit integer additions, halving the results. - \param [in] x first four 8-bit summands. - \param [in] y second four 8-bit summands. - \return the halved addition of the first bytes from each operand, in the first byte of the return value.\n - the halved addition of the second bytes from each operand, in the second byte of the return value.\n - the halved addition of the third bytes from each operand, in the third byte of the return value.\n - the halved addition of the fourth bytes from each operand, in the fourth byte of the return value. - \remark - res[7:0] = (val1[7:0] + val2[7:0] ) >> 1 \n - res[15:8] = (val1[15:8] + val2[15:8] ) >> 1 \n - res[23:16] = (val1[23:16] + val2[23:16]) >> 1 \n - res[31:24] = (val1[31:24] + val2[31:24]) >> 1 - */ -__ALWAYS_STATIC_INLINE uint32_t __SHADD8(uint32_t x, uint32_t y) -{ - int32_t r, s, t, u; - - r = (((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)) >> 1) & (int32_t)0x000000FF; - s = (((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)) >> 1) & (int32_t)0x000000FF; - t = (((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)) >> 1) & (int32_t)0x000000FF; - u = (((((int32_t)x) >> 24) + (((int32_t)y) >> 24)) >> 1) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); -} - -/** - \brief Quad 8-bit unsigned addition with halved results. - \details This function enables you to perform four unsigned 8-bit integer additions, halving the results. - \param [in] x first four 8-bit summands. - \param [in] y second four 8-bit summands. - \return the halved addition of the first bytes from each operand, in the first byte of the return value.\n - the halved addition of the second bytes from each operand, in the second byte of the return value.\n - the halved addition of the third bytes from each operand, in the third byte of the return value.\n - the halved addition of the fourth bytes from each operand, in the fourth byte of the return value. - \remark - res[7:0] = (val1[7:0] + val2[7:0] ) >> 1 \n - res[15:8] = (val1[15:8] + val2[15:8] ) >> 1 \n - res[23:16] = (val1[23:16] + val2[23:16]) >> 1 \n - res[31:24] = (val1[31:24] + val2[31:24]) >> 1 - */ -__ALWAYS_STATIC_INLINE uint32_t __UHADD8(uint32_t x, uint32_t y) -{ - int32_t r, s, t, u; - - r = ((((x << 24) >> 24) + ((y << 24) >> 24)) >> 1) & 0x000000FF; - s = ((((x << 16) >> 24) + ((y << 16) >> 24)) >> 1) & 0x000000FF; - t = ((((x << 8) >> 24) + ((y << 8) >> 24)) >> 1) & 0x000000FF; - u = ((((x) >> 24) + ((y) >> 24)) >> 1) & 0x000000FF; - - return ((u << 24) | (t << 16) | (s << 8) | (r)); -} - -/** - \brief Dual 16-bit saturating subtract. - \details This function enables you to perform two 16-bit integer subtractions in parallel, - saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. - \param [in] x first two 16-bit summands. - \param [in] y second two 16-bit summands. - \return the saturated subtraction of the low halfwords, in the low halfword of the return value.\n - the saturated subtraction of the high halfwords, in the high halfword of the return value.\n - The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. - \remark - res[15:0] = val1[15:0] - val2[15:0] \n - res[31:16] = val1[31:16] - val2[31:16] - */ -__ALWAYS_STATIC_INLINE uint32_t __QSUB16(uint32_t x, uint32_t y) -{ - int32_t r, s; - - r = __SSAT(((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((int32_t)x) >> 16) - (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r))); -} - -/** - \brief Dual 16-bit unsigned saturating subtraction. - \details This function enables you to perform two unsigned 16-bit integer subtractions, - saturating the results to the 16-bit unsigned integer range 0 < x < 2^16 - 1. - \param [in] x first two 16-bit operands for each subtraction. - \param [in] y second two 16-bit operands for each subtraction. - \return the saturated subtraction of the low halfwords, in the low halfword of the return value.\n - the saturated subtraction of the high halfwords, in the high halfword of the return value.\n - The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. - \remark - res[15:0] = val1[15:0] - val2[15:0] \n - res[31:16] = val1[31:16] - val2[31:16] - */ -__ALWAYS_STATIC_INLINE uint32_t __UQSUB16(uint32_t x, uint32_t y) -{ - int32_t r, s; - - r = __IUSAT((((x << 16) >> 16) - ((y << 16) >> 16)), 16) & 0x0000FFFF; - s = __IUSAT((((x) >> 16) - ((y) >> 16)), 16) & 0x0000FFFF; - - return ((s << 16) | (r)); -} - -/** - \brief Dual 16-bit signed subtraction. - \details This function enables you to perform two 16-bit signed integer subtractions. - \param [in] x first two 16-bit operands of each subtraction. - \param [in] y second two 16-bit operands of each subtraction. - \return the subtraction of the low halfword in the second operand from the low - halfword in the first operand, in the low halfword of the return value. \n - the subtraction of the high halfword in the second operand from the high - halfword in the first operand, in the high halfword of the return value. - \remark - res[15:0] = val1[15:0] - val2[15:0] \n - res[31:16] = val1[31:16] - val2[31:16] - */ -__ALWAYS_STATIC_INLINE uint32_t __SSUB16(uint32_t x, uint32_t y) -{ - int32_t r, s; - - r = ((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF; - s = ((((int32_t)x) >> 16) - (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r))); -} - -/** - \brief Dual 16-bit unsigned subtract. - \details This function enables you to perform two 16-bit unsigned integer subtractions. - \param [in] x first two 16-bit operands of each subtraction. - \param [in] y second two 16-bit operands of each subtraction. - \return the subtraction of the low halfword in the second operand from the low - halfword in the first operand, in the low halfword of the return value. \n - the subtraction of the high halfword in the second operand from the high - halfword in the first operand, in the high halfword of the return value. - \remark - res[15:0] = val1[15:0] - val2[15:0] \n - res[31:16] = val1[31:16] - val2[31:16] - */ -__ALWAYS_STATIC_INLINE uint32_t __USUB16(uint32_t x, uint32_t y) -{ - int32_t r, s; - - r = (((x << 16) >> 16) - ((y << 16) >> 16)) & 0x0000FFFF; - s = (((x) >> 16) - ((y) >> 16)) & 0x0000FFFF; - - return ((s << 16) | (r)); -} - -/** - \brief Dual 16-bit signed subtraction with halved results. - \details This function enables you to perform two signed 16-bit integer subtractions, halving the results. - \param [in] x first two 16-bit summands. - \param [in] y second two 16-bit summands. - \return the halved subtraction of the low halfwords, in the low halfword of the return value.\n - the halved subtraction of the high halfwords, in the high halfword of the return value. - \remark - res[15:0] = (val1[15:0] - val2[15:0]) >> 1 \n - res[31:16] = (val1[31:16] - val2[31:16]) >> 1 - */ -__ALWAYS_STATIC_INLINE uint32_t __SHSUB16(uint32_t x, uint32_t y) -{ - int32_t r, s; - - r = (((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((int32_t)x) >> 16) - (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r))); -} - -/** - \brief Dual 16-bit unsigned subtraction with halved results. - \details This function enables you to perform two unsigned 16-bit integer subtractions, halving the results. - \param [in] x first two 16-bit summands. - \param [in] y second two 16-bit summands. - \return the halved subtraction of the low halfwords, in the low halfword of the return value.\n - the halved subtraction of the high halfwords, in the high halfword of the return value. - \remark - res[15:0] = (val1[15:0] - val2[15:0]) >> 1 \n - res[31:16] = (val1[31:16] - val2[31:16]) >> 1 - */ -__ALWAYS_STATIC_INLINE uint32_t __UHSUB16(uint32_t x, uint32_t y) -{ - int32_t r, s; - - r = ((((x << 16) >> 16) - ((y << 16) >> 16)) >> 1) & 0x0000FFFF; - s = ((((x) >> 16) - ((y) >> 16)) >> 1) & 0x0000FFFF; - - return ((s << 16) | (r)); -} - -/** - \brief Quad 8-bit signed addition with halved results. - \details This function enables you to perform four signed 8-bit integer subtractions, halving the results. - \param [in] x first four 8-bit summands. - \param [in] y second four 8-bit summands. - \return the halved subtraction of the first bytes from each operand, in the first byte of the return value.\n - the halved subtraction of the second bytes from each operand, in the second byte of the return value.\n - the halved subtraction of the third bytes from each operand, in the third byte of the return value.\n - the halved subtraction of the fourth bytes from each operand, in the fourth byte of the return value. - \remark - res[7:0] = (val1[7:0] - val2[7:0] ) >> 1 \n - res[15:8] = (val1[15:8] - val2[15:8] ) >> 1 \n - res[23:16] = (val1[23:16] - val2[23:16]) >> 1 \n - res[31:24] = (val1[31:24] - val2[31:24]) >> 1 - */ -__ALWAYS_STATIC_INLINE uint32_t __SHSUB8(uint32_t x, uint32_t y) -{ - int32_t r, s, t, u; - - r = (((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)) >> 1) & (int32_t)0x000000FF; - s = (((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)) >> 1) & (int32_t)0x000000FF; - t = (((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)) >> 1) & (int32_t)0x000000FF; - u = (((((int32_t)x) >> 24) - (((int32_t)y) >> 24)) >> 1) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); -} - -/** - \brief Quad 8-bit unsigned subtraction with halved results. - \details This function enables you to perform four unsigned 8-bit integer subtractions, halving the results. - \param [in] x first four 8-bit summands. - \param [in] y second four 8-bit summands. - \return the halved subtraction of the first bytes from each operand, in the first byte of the return value.\n - the halved subtraction of the second bytes from each operand, in the second byte of the return value.\n - the halved subtraction of the third bytes from each operand, in the third byte of the return value.\n - the halved subtraction of the fourth bytes from each operand, in the fourth byte of the return value. - \remark - res[7:0] = (val1[7:0] - val2[7:0] ) >> 1 \n - res[15:8] = (val1[15:8] - val2[15:8] ) >> 1 \n - res[23:16] = (val1[23:16] - val2[23:16]) >> 1 \n - res[31:24] = (val1[31:24] - val2[31:24]) >> 1 - */ -__ALWAYS_STATIC_INLINE uint32_t __UHSUB8(uint32_t x, uint32_t y) -{ - int32_t r, s, t, u; - - r = ((((x << 24) >> 24) - ((y << 24) >> 24)) >> 1) & 0x000000FF; - s = ((((x << 16) >> 24) - ((y << 16) >> 24)) >> 1) & 0x000000FF; - t = ((((x << 8) >> 24) - ((y << 8) >> 24)) >> 1) & 0x000000FF; - u = ((((x) >> 24) - ((y) >> 24)) >> 1) & 0x000000FF; - - return ((u << 24) | (t << 16) | (s << 8) | (r)); -} - -/** - \brief Dual 16-bit add and subtract with exchange. - \details This function enables you to exchange the halfwords of the one operand, - then add the high halfwords and subtract the low halfwords, - saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. - \param [in] x first operand for the subtraction in the low halfword, - and the first operand for the addition in the high halfword. - \param [in] y second operand for the subtraction in the high halfword, - and the second operand for the addition in the low halfword. - \return the saturated subtraction of the high halfword in the second operand from the - low halfword in the first operand, in the low halfword of the return value.\n - the saturated addition of the high halfword in the first operand and the - low halfword in the second operand, in the high halfword of the return value.\n - The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. - \remark - res[15:0] = val1[15:0] - val2[31:16] \n - res[31:16] = val1[31:16] + val2[15:0] - */ -__ALWAYS_STATIC_INLINE uint32_t __QASX(uint32_t x, uint32_t y) -{ - int32_t r, s; - - r = __SSAT(((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r))); -} - -/** - \brief Dual 16-bit unsigned saturating addition and subtraction with exchange. - \details This function enables you to exchange the halfwords of the second operand and - perform one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, - saturating the results to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1. - \param [in] x first operand for the subtraction in the low halfword, - and the first operand for the addition in the high halfword. - \param [in] y second operand for the subtraction in the high halfword, - and the second operand for the addition in the low halfword. - \return the saturated subtraction of the high halfword in the second operand from the - low halfword in the first operand, in the low halfword of the return value.\n - the saturated addition of the high halfword in the first operand and the - low halfword in the second operand, in the high halfword of the return value.\n - The returned results are saturated to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1. - \remark - res[15:0] = val1[15:0] - val2[31:16] \n - res[31:16] = val1[31:16] + val2[15:0] - */ -__ALWAYS_STATIC_INLINE uint32_t __UQASX(uint32_t x, uint32_t y) -{ - int32_t r, s; - - r = __IUSAT((((x << 16) >> 16) - ((y) >> 16)), 16) & 0x0000FFFF; - s = __IUSAT((((x) >> 16) + ((y << 16) >> 16)), 16) & 0x0000FFFF; - - return ((s << 16) | (r)); -} - -/** - \brief Dual 16-bit addition and subtraction with exchange. - \details It enables you to exchange the halfwords of the second operand, add the high halfwords - and subtract the low halfwords. - \param [in] x first operand for the subtraction in the low halfword, - and the first operand for the addition in the high halfword. - \param [in] y second operand for the subtraction in the high halfword, - and the second operand for the addition in the low halfword. - \return the subtraction of the high halfword in the second operand from the - low halfword in the first operand, in the low halfword of the return value.\n - the addition of the high halfword in the first operand and the - low halfword in the second operand, in the high halfword of the return value. - \remark - res[15:0] = val1[15:0] - val2[31:16] \n - res[31:16] = val1[31:16] + val2[15:0] - */ -__ALWAYS_STATIC_INLINE uint32_t __SASX(uint32_t x, uint32_t y) -{ - int32_t r, s; - - r = ((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF; - s = ((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r))); -} - -/** - \brief Dual 16-bit unsigned addition and subtraction with exchange. - \details This function enables you to exchange the two halfwords of the second operand, - add the high halfwords and subtract the low halfwords. - \param [in] x first operand for the subtraction in the low halfword, - and the first operand for the addition in the high halfword. - \param [in] y second operand for the subtraction in the high halfword, - and the second operand for the addition in the low halfword. - \return the subtraction of the high halfword in the second operand from the - low halfword in the first operand, in the low halfword of the return value.\n - the addition of the high halfword in the first operand and the - low halfword in the second operand, in the high halfword of the return value. - \remark - res[15:0] = val1[15:0] - val2[31:16] \n - res[31:16] = val1[31:16] + val2[15:0] - */ -__ALWAYS_STATIC_INLINE uint32_t __UASX(uint32_t x, uint32_t y) -{ - int32_t r, s; - - r = (((x << 16) >> 16) - ((y) >> 16)) & 0x0000FFFF; - s = (((x) >> 16) + ((y << 16) >> 16)) & 0x0000FFFF; - - return ((s << 16) | (r)); -} - -/** - \brief Dual 16-bit signed addition and subtraction with halved results. - \details This function enables you to exchange the two halfwords of one operand, perform one - signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results. - \param [in] x first 16-bit operands. - \param [in] y second 16-bit operands. - \return the halved subtraction of the high halfword in the second operand from the - low halfword in the first operand, in the low halfword of the return value.\n - the halved addition of the low halfword in the second operand from the high - halfword in the first operand, in the high halfword of the return value. - \remark - res[15:0] = (val1[15:0] - val2[31:16]) >> 1 \n - res[31:16] = (val1[31:16] + val2[15:0]) >> 1 - */ -__ALWAYS_STATIC_INLINE uint32_t __SHASX(uint32_t x, uint32_t y) -{ - int32_t r, s; - - r = (((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r))); -} - -/** - \brief Dual 16-bit unsigned addition and subtraction with halved results and exchange. - \details This function enables you to exchange the halfwords of the second operand, - add the high halfwords and subtract the low halfwords, halving the results. - \param [in] x first operand for the subtraction in the low halfword, and - the first operand for the addition in the high halfword. - \param [in] y second operand for the subtraction in the high halfword, and - the second operand for the addition in the low halfword. - \return the halved subtraction of the high halfword in the second operand from the - low halfword in the first operand, in the low halfword of the return value.\n - the halved addition of the low halfword in the second operand from the high - halfword in the first operand, in the high halfword of the return value. - \remark - res[15:0] = (val1[15:0] - val2[31:16]) >> 1 \n - res[31:16] = (val1[31:16] + val2[15:0]) >> 1 - */ -__ALWAYS_STATIC_INLINE uint32_t __UHASX(uint32_t x, uint32_t y) -{ - int32_t r, s; - - r = ((((x << 16) >> 16) - ((y) >> 16)) >> 1) & 0x0000FFFF; - s = ((((x) >> 16) + ((y << 16) >> 16)) >> 1) & 0x0000FFFF; - - return ((s << 16) | (r)); -} - -/** - \brief Dual 16-bit subtract and add with exchange. - \details This function enables you to exchange the halfwords of one operand, - then subtract the high halfwords and add the low halfwords, - saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. - \param [in] x first operand for the addition in the low halfword, - and the first operand for the subtraction in the high halfword. - \param [in] y second operand for the addition in the high halfword, - and the second operand for the subtraction in the low halfword. - \return the saturated addition of the low halfword of the first operand and the high - halfword of the second operand, in the low halfword of the return value.\n - the saturated subtraction of the low halfword of the second operand from the - high halfword of the first operand, in the high halfword of the return value.\n - The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. - \remark - res[15:0] = val1[15:0] + val2[31:16] \n - res[31:16] = val1[31:16] - val2[15:0] - */ -__ALWAYS_STATIC_INLINE uint32_t __QSAX(uint32_t x, uint32_t y) -{ - int32_t r, s; - - r = __SSAT(((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r))); -} - -/** - \brief Dual 16-bit unsigned saturating subtraction and addition with exchange. - \details This function enables you to exchange the halfwords of the second operand and perform - one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating - the results to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1. - \param [in] x first operand for the addition in the low halfword, - and the first operand for the subtraction in the high halfword. - \param [in] y second operand for the addition in the high halfword, - and the second operand for the subtraction in the low halfword. - \return the saturated addition of the low halfword of the first operand and the high - halfword of the second operand, in the low halfword of the return value.\n - the saturated subtraction of the low halfword of the second operand from the - high halfword of the first operand, in the high halfword of the return value.\n - The returned results are saturated to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1. - \remark - res[15:0] = val1[15:0] + val2[31:16] \n - res[31:16] = val1[31:16] - val2[15:0] - */ -__ALWAYS_STATIC_INLINE uint32_t __UQSAX(uint32_t x, uint32_t y) -{ - int32_t r, s; - - r = __IUSAT((((x << 16) >> 16) + ((y) >> 16)), 16) & 0x0000FFFF; - s = __IUSAT((((x) >> 16) - ((y << 16) >> 16)), 16) & 0x0000FFFF; - - return ((s << 16) | (r)); -} - -/** - \brief Dual 16-bit unsigned subtract and add with exchange. - \details This function enables you to exchange the halfwords of the second operand, - subtract the high halfwords and add the low halfwords. - \param [in] x first operand for the addition in the low halfword, - and the first operand for the subtraction in the high halfword. - \param [in] y second operand for the addition in the high halfword, - and the second operand for the subtraction in the low halfword. - \return the addition of the low halfword of the first operand and the high - halfword of the second operand, in the low halfword of the return value.\n - the subtraction of the low halfword of the second operand from the - high halfword of the first operand, in the high halfword of the return value.\n - \remark - res[15:0] = val1[15:0] + val2[31:16] \n - res[31:16] = val1[31:16] - val2[15:0] - */ -__ALWAYS_STATIC_INLINE uint32_t __USAX(uint32_t x, uint32_t y) -{ - int32_t r, s; - - r = (((x << 16) >> 16) + ((y) >> 16)) & 0x0000FFFF; - s = (((x) >> 16) - ((y << 16) >> 16)) & 0x0000FFFF; - - return ((s << 16) | (r)); -} - -/** - \brief Dual 16-bit signed subtraction and addition with exchange. - \details This function enables you to exchange the two halfwords of one operand and perform one - 16-bit integer subtraction and one 16-bit addition. - \param [in] x first operand for the addition in the low halfword, and the first operand - for the subtraction in the high halfword. - \param [in] y second operand for the addition in the high halfword, and the second - operand for the subtraction in the low halfword. - \return the addition of the low halfword of the first operand and the high - halfword of the second operand, in the low halfword of the return value.\n - the subtraction of the low halfword of the second operand from the - high halfword of the first operand, in the high halfword of the return value.\n - \remark - res[15:0] = val1[15:0] + val2[31:16] \n - res[31:16] = val1[31:16] - val2[15:0] - */ -__ALWAYS_STATIC_INLINE uint32_t __SSAX(uint32_t x, uint32_t y) -{ - int32_t r, s; - - r = ((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF; - s = ((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r))); -} - - -/** - \brief Dual 16-bit signed subtraction and addition with halved results. - \details This function enables you to exchange the two halfwords of one operand, perform one signed - 16-bit integer subtraction and one signed 16-bit addition, and halve the results. - \param [in] x first 16-bit operands. - \param [in] y second 16-bit operands. - \return the halved addition of the low halfword in the first operand and the - high halfword in the second operand, in the low halfword of the return value.\n - the halved subtraction of the low halfword in the second operand from the - high halfword in the first operand, in the high halfword of the return value. - \remark - res[15:0] = (val1[15:0] + val2[31:16]) >> 1 \n - res[31:16] = (val1[31:16] - val2[15:0]) >> 1 - */ -__ALWAYS_STATIC_INLINE uint32_t __SHSAX(uint32_t x, uint32_t y) -{ - int32_t r, s; - - r = (((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r))); -} - -/** - \brief Dual 16-bit unsigned subtraction and addition with halved results and exchange. - \details This function enables you to exchange the halfwords of the second operand, - subtract the high halfwords and add the low halfwords, halving the results. - \param [in] x first operand for the addition in the low halfword, and - the first operand for the subtraction in the high halfword. - \param [in] y second operand for the addition in the high halfword, and - the second operand for the subtraction in the low halfword. - \return the halved addition of the low halfword in the first operand and the - high halfword in the second operand, in the low halfword of the return value.\n - the halved subtraction of the low halfword in the second operand from the - high halfword in the first operand, in the high halfword of the return value. - \remark - res[15:0] = (val1[15:0] + val2[31:16]) >> 1 \n - res[31:16] = (val1[31:16] - val2[15:0]) >> 1 - */ -__ALWAYS_STATIC_INLINE uint32_t __UHSAX(uint32_t x, uint32_t y) -{ - int32_t r, s; - - r = ((((x << 16) >> 16) + ((y) >> 16)) >> 1) & 0x0000FFFF; - s = ((((x) >> 16) - ((y << 16) >> 16)) >> 1) & 0x0000FFFF; - - return ((s << 16) | (r)); -} - -/** - \brief Dual 16-bit signed multiply with exchange returning difference. - \details This function enables you to perform two 16-bit signed multiplications, subtracting - one of the products from the other. The halfwords of the second operand are exchanged - before performing the arithmetic. This produces top * bottom and bottom * top multiplication. - \param [in] x first 16-bit operands for each multiplication. - \param [in] y second 16-bit operands for each multiplication. - \return the difference of the products of the two 16-bit signed multiplications. - \remark - p1 = val1[15:0] * val2[31:16] \n - p2 = val1[31:16] * val2[15:0] \n - res[31:0] = p1 - p2 - */ -__ALWAYS_STATIC_INLINE uint32_t __SMUSDX(uint32_t x, uint32_t y) -{ - return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) - - ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)))); -} - -/** - \brief Sum of dual 16-bit signed multiply with exchange. - \details This function enables you to perform two 16-bit signed multiplications with exchanged - halfwords of the second operand, adding the products together. - \param [in] x first 16-bit operands for each multiplication. - \param [in] y second 16-bit operands for each multiplication. - \return the sum of the products of the two 16-bit signed multiplications with exchanged halfwords of the second operand. - \remark - p1 = val1[15:0] * val2[31:16] \n - p2 = val1[31:16] * val2[15:0] \n - res[31:0] = p1 + p2 - */ -__ALWAYS_STATIC_INLINE uint32_t __SMUADX(uint32_t x, uint32_t y) -{ - return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) + - ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)))); -} - - -/** - \brief Saturating add. - \details This function enables you to obtain the saturating add of two integers. - \param [in] x first summand of the saturating add operation. - \param [in] y second summand of the saturating add operation. - \return the saturating addition of val1 and val2. - \remark - res[31:0] = SAT(val1 + SAT(val2)) - */ -__ALWAYS_STATIC_INLINE int32_t __QADD(int32_t x, int32_t y) -{ - int32_t result; - - if (y >= 0) { - if (x + y >= x) { - result = x + y; - } else { - result = 0x7FFFFFFF; - } - } else { - if (x + y < x) { - result = x + y; - } else { - result = 0x80000000; - } - } - - return result; -} - -/** - \brief Saturating subtract. - \details This function enables you to obtain the saturating add of two integers. - \param [in] x first summand of the saturating add operation. - \param [in] y second summand of the saturating add operation. - \return the saturating addition of val1 and val2. - \remark - res[31:0] = SAT(val1 - SAT(val2)) - */ -__ALWAYS_STATIC_INLINE int32_t __QSUB(int32_t x, int32_t y) -{ - int64_t tmp; - int32_t result; - - tmp = (int64_t)x - (int64_t)y; - - if (tmp > 0x7fffffff) { - tmp = 0x7fffffff; - } else if (tmp < (-2147483647 - 1)) { - tmp = -2147483647 - 1; - } - - result = tmp; - return result; -} - -/** - \brief Dual 16-bit signed multiply with single 32-bit accumulator. - \details This function enables you to perform two signed 16-bit multiplications, - adding both results to a 32-bit accumulate operand. - \param [in] x first 16-bit operands for each multiplication. - \param [in] y second 16-bit operands for each multiplication. - \param [in] sum accumulate value. - \return the product of each multiplication added to the accumulate value, as a 32-bit integer. - \remark - p1 = val1[15:0] * val2[15:0] \n - p2 = val1[31:16] * val2[31:16] \n - res[31:0] = p1 + p2 + val3[31:0] - */ -__ALWAYS_STATIC_INLINE uint32_t __SMLAD(uint32_t x, uint32_t y, uint32_t sum) -{ - return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) + - ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) + - (((int32_t)sum)))); -} - -/** - \brief Pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator. - \details This function enables you to perform two signed 16-bit multiplications with exchanged - halfwords of the second operand, adding both results to a 32-bit accumulate operand. - \param [in] x first 16-bit operands for each multiplication. - \param [in] y second 16-bit operands for each multiplication. - \param [in] sum accumulate value. - \return the product of each multiplication with exchanged halfwords of the second - operand added to the accumulate value, as a 32-bit integer. - \remark - p1 = val1[15:0] * val2[31:16] \n - p2 = val1[31:16] * val2[15:0] \n - res[31:0] = p1 + p2 + val3[31:0] - */ -__ALWAYS_STATIC_INLINE uint32_t __SMLADX(uint32_t x, uint32_t y, uint32_t sum) -{ - return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) + - ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) + - (((int32_t)sum)))); -} - -/** - \brief Dual 16-bit signed multiply with exchange subtract with 32-bit accumulate. - \details This function enables you to perform two 16-bit signed multiplications, take the - difference of the products, subtracting the high halfword product from the low - halfword product, and add the difference to a 32-bit accumulate operand. - \param [in] x first 16-bit operands for each multiplication. - \param [in] y second 16-bit operands for each multiplication. - \param [in] sum accumulate value. - \return the difference of the product of each multiplication, added to the accumulate value. - \remark - p1 = val1[15:0] * val2[15:0] \n - p2 = val1[31:16] * val2[31:16] \n - res[31:0] = p1 - p2 + val3[31:0] - */ -__ALWAYS_STATIC_INLINE uint32_t __SMLSD(uint32_t x, uint32_t y, uint32_t sum) -{ - return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) - - ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) + - (((int32_t)sum)))); -} - -/** - \brief Dual 16-bit signed multiply with exchange subtract with 32-bit accumulate. - \details This function enables you to exchange the halfwords in the second operand, then perform two 16-bit - signed multiplications. The difference of the products is added to a 32-bit accumulate operand. - \param [in] x first 16-bit operands for each multiplication. - \param [in] y second 16-bit operands for each multiplication. - \param [in] sum accumulate value. - \return the difference of the product of each multiplication, added to the accumulate value. - \remark - p1 = val1[15:0] * val2[31:16] \n - p2 = val1[31:16] * val2[15:0] \n - res[31:0] = p1 - p2 + val3[31:0] - */ -__ALWAYS_STATIC_INLINE uint32_t __SMLSDX(uint32_t x, uint32_t y, uint32_t sum) -{ - return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) - - ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) + - (((int32_t)sum)))); -} - -/** - \brief Dual 16-bit signed multiply with single 64-bit accumulator. - \details This function enables you to perform two signed 16-bit multiplications, adding both results - to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. - This overflow is not detected if it occurs. Instead, the result wraps around modulo2^64. - \param [in] x first 16-bit operands for each multiplication. - \param [in] y second 16-bit operands for each multiplication. - \param [in] sum accumulate value. - \return the product of each multiplication added to the accumulate value. - \remark - p1 = val1[15:0] * val2[15:0] \n - p2 = val1[31:16] * val2[31:16] \n - sum = p1 + p2 + val3[63:32][31:0] \n - res[63:32] = sum[63:32] \n - res[31:0] = sum[31:0] - */ -__ALWAYS_STATIC_INLINE uint64_t __SMLALD(uint32_t x, uint32_t y, uint64_t sum) -{ - return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) + - ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) + - (((uint64_t)sum)))); -} - -/** - \brief Dual 16-bit signed multiply with exchange with single 64-bit accumulator. - \details This function enables you to exchange the halfwords of the second operand, and perform two - signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow - is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. - Instead, the result wraps around modulo2^64. - \param [in] x first 16-bit operands for each multiplication. - \param [in] y second 16-bit operands for each multiplication. - \param [in] sum accumulate value. - \return the product of each multiplication added to the accumulate value. - \remark - p1 = val1[15:0] * val2[31:16] \n - p2 = val1[31:16] * val2[15:0] \n - sum = p1 + p2 + val3[63:32][31:0] \n - res[63:32] = sum[63:32] \n - res[31:0] = sum[31:0] - */ -__ALWAYS_STATIC_INLINE uint64_t __SMLALDX(uint32_t x, uint32_t y, uint64_t sum) -{ - return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) + - ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) + - (((uint64_t)sum)))); -} - -/** - \brief dual 16-bit signed multiply subtract with 64-bit accumulate. - \details This function It enables you to perform two 16-bit signed multiplications, take the difference - of the products, subtracting the high halfword product from the low halfword product, and add the - difference to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the - subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not - detected. Instead, the result wraps round to modulo2^64. - \param [in] x first 16-bit operands for each multiplication. - \param [in] y second 16-bit operands for each multiplication. - \param [in] sum accumulate value. - \return the difference of the product of each multiplication, added to the accumulate value. - \remark - p1 = val1[15:0] * val2[15:0] \n - p2 = val1[31:16] * val2[31:16] \n - res[63:32][31:0] = p1 - p2 + val3[63:32][31:0] - */ -__ALWAYS_STATIC_INLINE uint64_t __SMLSLD(uint32_t x, uint32_t y, uint64_t sum) -{ - return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) - - ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) + - (((uint64_t)sum)))); -} - -/** - \brief Dual 16-bit signed multiply with exchange subtract with 64-bit accumulate. - \details This function enables you to exchange the halfwords of the second operand, perform two 16-bit multiplications, - adding the difference of the products to a 64-bit accumulate operand. Overflow cannot occur during the - multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow - is not detected. Instead, the result wraps round to modulo2^64. - \param [in] x first 16-bit operands for each multiplication. - \param [in] y second 16-bit operands for each multiplication. - \param [in] sum accumulate value. - \return the difference of the product of each multiplication, added to the accumulate value. - \remark - p1 = val1[15:0] * val2[31:16] \n - p2 = val1[31:16] * val2[15:0] \n - res[63:32][31:0] = p1 - p2 + val3[63:32][31:0] - */ -__ALWAYS_STATIC_INLINE uint64_t __SMLSLDX(uint32_t x, uint32_t y, uint64_t sum) -{ - return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) - - ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) + - (((uint64_t)sum)))); -} - -/** - \brief 32-bit signed multiply with 32-bit truncated accumulator. - \details This function enables you to perform a signed 32-bit multiplications, adding the most - significant 32 bits of the 64-bit result to a 32-bit accumulate operand. - \param [in] x first operand for multiplication. - \param [in] y second operand for multiplication. - \param [in] sum accumulate value. - \return the product of multiplication (most significant 32 bits) is added to the accumulate value, as a 32-bit integer. - \remark - p = val1 * val2 \n - res[31:0] = p[63:32] + val3[31:0] - */ -__ALWAYS_STATIC_INLINE uint32_t __SMMLA(int32_t x, int32_t y, int32_t sum) -{ - return (uint32_t)((int32_t)((int64_t)((int64_t)x * (int64_t)y) >> 32) + sum); -} - -/** - \brief Sum of dual 16-bit signed multiply. - \details This function enables you to perform two 16-bit signed multiplications, adding the products together. - \param [in] x first 16-bit operands for each multiplication. - \param [in] y second 16-bit operands for each multiplication. - \return the sum of the products of the two 16-bit signed multiplications. - \remark - p1 = val1[15:0] * val2[15:0] \n - p2 = val1[31:16] * val2[31:16] \n - res[31:0] = p1 + p2 - */ -__ALWAYS_STATIC_INLINE uint32_t __SMUAD(uint32_t x, uint32_t y) -{ - return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) + - ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)))); -} - -/** - \brief Dual 16-bit signed multiply returning difference. - \details This function enables you to perform two 16-bit signed multiplications, taking the difference - of the products by subtracting the high halfword product from the low halfword product. - \param [in] x first 16-bit operands for each multiplication. - \param [in] y second 16-bit operands for each multiplication. - \return the difference of the products of the two 16-bit signed multiplications. - \remark - p1 = val1[15:0] * val2[15:0] \n - p2 = val1[31:16] * val2[31:16] \n - res[31:0] = p1 - p2 - */ -__ALWAYS_STATIC_INLINE uint32_t __SMUSD(uint32_t x, uint32_t y) -{ - return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) - - ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)))); -} - -/** - \brief Dual extracted 8-bit to 16-bit signed addition. - \details This function enables you to extract two 8-bit values from the second operand (at bit positions - [7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the first operand. - \param [in] x values added to the sign-extended to 16-bit values. - \param [in] y two 8-bit values to be extracted and sign-extended. - \return the addition of val1 and val2, where the 8-bit values in val2[7:0] and - val2[23:16] have been extracted and sign-extended prior to the addition. - \remark - res[15:0] = val1[15:0] + SignExtended(val2[7:0]) \n - res[31:16] = val1[31:16] + SignExtended(val2[23:16]) - */ -__ALWAYS_STATIC_INLINE uint32_t __SXTAB16(uint32_t x, uint32_t y) -{ - return ((uint32_t)((((((int32_t)y << 24) >> 24) + (((int32_t)x << 16) >> 16)) & (int32_t)0x0000FFFF) | - (((((int32_t)y << 8) >> 8) + (((int32_t)x >> 16) << 16)) & (int32_t)0xFFFF0000))); -} - -/** - \brief Extracted 16-bit to 32-bit unsigned addition. - \details This function enables you to extract two 8-bit values from one operand, zero-extend - them to 16 bits each, and add the results to two 16-bit values from another operand. - \param [in] x values added to the zero-extended to 16-bit values. - \param [in] y two 8-bit values to be extracted and zero-extended. - \return the addition of val1 and val2, where the 8-bit values in val2[7:0] and - val2[23:16] have been extracted and zero-extended prior to the addition. - \remark - res[15:0] = ZeroExt(val2[7:0] to 16 bits) + val1[15:0] \n - res[31:16] = ZeroExt(val2[31:16] to 16 bits) + val1[31:16] - */ -__ALWAYS_STATIC_INLINE uint32_t __UXTAB16(uint32_t x, uint32_t y) -{ - return ((uint32_t)(((((y << 24) >> 24) + ((x << 16) >> 16)) & 0x0000FFFF) | - ((((y << 8) >> 8) + ((x >> 16) << 16)) & 0xFFFF0000))); -} - -/** - \brief Dual extract 8-bits and sign extend each to 16-bits. - \details This function enables you to extract two 8-bit values from an operand and sign-extend them to 16 bits each. - \param [in] x two 8-bit values in val[7:0] and val[23:16] to be sign-extended. - \return the 8-bit values sign-extended to 16-bit values.\n - sign-extended value of val[7:0] in the low halfword of the return value.\n - sign-extended value of val[23:16] in the high halfword of the return value. - \remark - res[15:0] = SignExtended(val[7:0]) \n - res[31:16] = SignExtended(val[23:16]) - */ -__ALWAYS_STATIC_INLINE uint32_t __SXTB16(uint32_t x) -{ - return ((uint32_t)(((((int32_t)x << 24) >> 24) & (int32_t)0x0000FFFF) | - ((((int32_t)x << 8) >> 8) & (int32_t)0xFFFF0000))); -} - -/** - \brief Dual extract 8-bits and zero-extend to 16-bits. - \details This function enables you to extract two 8-bit values from an operand and zero-extend them to 16 bits each. - \param [in] x two 8-bit values in val[7:0] and val[23:16] to be zero-extended. - \return the 8-bit values sign-extended to 16-bit values.\n - sign-extended value of val[7:0] in the low halfword of the return value.\n - sign-extended value of val[23:16] in the high halfword of the return value. - \remark - res[15:0] = SignExtended(val[7:0]) \n - res[31:16] = SignExtended(val[23:16]) - */ -__ALWAYS_STATIC_INLINE uint32_t __UXTB16(uint32_t x) -{ - return ((uint32_t)((((x << 24) >> 24) & 0x0000FFFF) | - (((x << 8) >> 8) & 0xFFFF0000))); -} - -#endif /* _CSI_GCC_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/adc.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/adc.h deleted file mode 100755 index dd69fd3d..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/adc.h +++ /dev/null @@ -1,213 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/adc.h - * @brief Header File for ADC Driver - * @version V1.0 - * @date 08. Apr 2020 - * @model adc - ******************************************************************************/ - -#ifndef _DRV_ADC_H_ -#define _DRV_ADC_H_ - -#include -#include - -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/****** ADC Event *****/ -typedef enum { - ADC_EVENT_CONVERT_COMPLETE = 0, ///< All data convert completed - ADC_EVENT_CONVERT_HALF_DONE, ///< Convert half done - ADC_EVENT_ERROR ///< All errors including but not limited to what converted data has not been read before the new conversion result is load to the data register -} csi_adc_event_t; - -typedef struct csi_adc csi_adc_t; -struct csi_adc { - csi_dev_t dev; ///< Hw-device info - void (*callback)(csi_adc_t *adc, csi_adc_event_t event, void *arg); ///< User callback ,signaled by driver event - void *arg; ///< User private param ,passed to user callback - uint32_t *data; ///< Data buf - uint32_t num; ///< Data size by word - csi_dma_ch_t *dma; ///< Dma channel handle - csi_error_t (*start)(csi_adc_t *adc); ///< Start function - csi_error_t (*stop)(csi_adc_t *adc); ///< Stop function - csi_state_t state; ///< ADC current state - void *priv; -}; - -/** - \brief Initialize adc Interface. Initialize the resources needed for the adc interface - \param[in] adc ADC handle to operate - \param[in] idx ADC controller index - \return Error code \ref csi_error_t -*/ -csi_error_t csi_adc_init(csi_adc_t *adc, uint32_t idx); - -/** - \brief De-initialize adc Interface. stops operation and releases the software resources used by the interface - \param[in] handle ADC handle to operate - \return None -*/ -void csi_adc_uninit(csi_adc_t *adc); - -/** - \brief Set adc receive buffer - \param[in] adc ADC handle to operate - \param[in] num The receive data length by word. - \return Error code \ref csi_error_t -*/ -csi_error_t csi_adc_set_buffer(csi_adc_t *adc, uint32_t *data, uint32_t num); - -/** - \brief Start adc - \param[in] handle ADC handle to operate - \return Error code \ref csi_error_t -*/ -csi_error_t csi_adc_start(csi_adc_t *adc); - -/** - \brief Enable dma or interrupt, and start adc conversion - \param[in] handle ADC handle to operate - \return Error code \ref csi_error_t -*/ -csi_error_t csi_adc_start_async(csi_adc_t *adc); - -/** - \brief Stop adc - \param[in] handle ADC handle to operate - \return Error code \ref csi_error_t -*/ -csi_error_t csi_adc_stop(csi_adc_t *adc); - -/** - \brief Disable dma or interrupt, and stop adc conversion - \param[in] handle ADC handle to operate - \return Error code \ref csi_error_t -*/ -csi_error_t csi_adc_stop_async(csi_adc_t *adc); - -/** - \brief ADC channel enable - \param[in] adc ADC handle to operate - \param[in] ch_id ADC channel id - \param[in] is_enable true->enable, false->disable - \return Error code \ref csi_error_t -*/ -csi_error_t csi_adc_channel_enable(csi_adc_t *adc, uint8_t ch_id, bool is_enable); - -/** - \brief Set the ADC sampling time for the selected channel - \param[in] adc ADC handle to operate - \param[in] ch_id ADC channel id - \param[in] clock_num Channel sampling clock number - \return Error code \ref csi_error_t -*/ -csi_error_t csi_adc_channel_sampling_time(csi_adc_t *adc, uint8_t ch_id, uint16_t clock_num); - -/** - \brief Set the ADC controller sampling time - \param[in] adc ADC handle to operate - \param[in] clock_num ADC controller sampling clock number - \return Error code \ref csi_error_t -*/ -csi_error_t csi_adc_sampling_time(csi_adc_t *adc, uint16_t clock_num); - -/** - \brief Enable the continue mode of ADC - \param[in] adc ADC handle to operate - \param[in] is_enable true->enable, false->disable - \return Error code \ref csi_error_t -*/ -csi_error_t csi_adc_continue_mode(csi_adc_t *adc, bool is_enable); - -/** - \brief Set ADC frequence division - \param[in] adc ADC handle to operate - \param[in] div The division of frequence - \return The actual config frequency -*/ -uint32_t csi_adc_freq_div(csi_adc_t *adc, uint32_t div); - -/** - \brief Receiving data from ADC receiver - \param[in] handle ADC handle to operate - \return If read successful, this function shall return the result of convert value - otherwise, the function shall return error code -*/ -int32_t csi_adc_read(csi_adc_t *adc); - -/** - \brief Get ADC state - \param[in] adc ADC handle to operate - \param[in] state ADC state - \return Error code \ref csi_error_t -*/ -csi_error_t csi_adc_get_state(csi_adc_t *adc, csi_state_t *state); - -/** - \brief Attach the callback handler to adc - \param[in] adc Operate handle - \param[in] callback Callback function - \param[in] arg User can define it by himself as callback's param - \return Error code \ref csi_error_t -*/ -csi_error_t csi_adc_attach_callback(csi_adc_t *adc, void *callback, void *arg); - -/** - \brief Detach the callback handler - \param[in] adc Operate handle - \return None -*/ -void csi_adc_detach_callback(csi_adc_t *adc); - -/** - \brief Link DMA channel to adc device - \param[in] adc ADC handle to operate - \param[in] dma The DMA channel handle for send, when it is NULL means to unlink the channel - \return Error code \ref csi_error_t -*/ -csi_error_t csi_adc_link_dma(csi_adc_t *adc, csi_dma_ch_t *dma); - -/** - \brief Enable adc low power mode - \param[in] adc ADC handle to operate - \return Error code \ref csi_error_t -*/ -csi_error_t csi_adc_enable_pm(csi_adc_t *adc); - -/** - \brief Disable adc low power mode - \param[in] adc ADC handle to operate - \return None -*/ -void csi_adc_disable_pm(csi_adc_t *adc); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_ADC_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/aes.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/aes.h deleted file mode 100755 index a395fa7c..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/aes.h +++ /dev/null @@ -1,309 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/aes.h - * @brief Header File for AES Driver - * @version V1.0 - * @date 9. Oct 2020 - * @model aes - ******************************************************************************/ - -#ifndef _DRV_AES_H_ -#define _DRV_AES_H_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/*----- Encrypt & Decrypt: Config key length -----*/ -typedef enum { - AES_KEY_LEN_BITS_128 = 0, /* 128 Data bits */ - AES_KEY_LEN_BITS_192, /* 192 Data bits */ - AES_KEY_LEN_BITS_256 /* 256 Data bits */ -} csi_aes_key_bits_t; - -/** -\brief AES Ctrl Block -*/ -typedef struct { - csi_dev_t dev; - void *priv; -} csi_aes_t; - -/** - \brief Initialize AES interface. Initializes the resources needed for the AES interface - \param[in] aes Handle to operate - \param[in] idx Device id - \return Error code \ref csi_error_t -*/ -csi_error_t csi_aes_init(csi_aes_t *aes, uint32_t idx); - -/** - \brief De-initialize AES interface. Stops operation and releases the software resources used by the interface - \param[in] aes Dandle to operate - \return None -*/ -void csi_aes_uninit(csi_aes_t *aes); - -/** - \brief Set encrypt key - \param[in] aes Handle to operate - \param[in] key Pointer to the key buf - \param[in] key_len Pointer to \ref csi_aes_key_bits_t - \return Error code \ref Csi_error_t -*/ -csi_error_t csi_aes_set_encrypt_key(csi_aes_t *aes, void *key, csi_aes_key_bits_t key_len); - -/** - \brief Set decrypt key - \param[in] aes Handle to operate - \param[in] key Pointer to the key buf - \param[in] key_len Pointer to \ref csi_aes_key_bits_t - \return Error code \ref Csi_error_t -*/ -csi_error_t csi_aes_set_decrypt_key(csi_aes_t *aes, void *key, csi_aes_key_bits_t key_len); -/** - \brief Set encrypt key2. This API is used for the algorithm which has two keys, - such as xts, used for the key of tweak - \param[in] aes Handle to operate - \param[in] key Pointer to the key buf - \param[in] key_len Pointer to \ref csi_aes_key_bits_t - \return Error code \ref Csi_error_t -*/ -csi_error_t csi_aes_set_encrypt_key2(csi_aes_t *aes, void *key, csi_aes_key_bits_t key_len); - -/** - \brief Set decrypt key2. This API is used for the algorithm which has two keys, - such as xts, used for the key of tweak - \param[in] aes Handle to operate - \param[in] key Pointer to the key buf - \param[in] key_len Pointer to \ref csi_aes_key_bits_t - \return Error code \ref Csi_error_t -*/ -csi_error_t csi_aes_set_decrypt_key2(csi_aes_t *aes, void *key, csi_aes_key_bits_t key_len); - -/** - \brief AES ecb encrypt - \param[in] aes Handle to operate - \param[in] in Pointer to the source data - \param[out] out Pointer to the result data - \param[in] size The source data size - \return Error code \ref Csi_error_t -*/ -csi_error_t csi_aes_ecb_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size); - -/** - \brief AES ecb decrypt - \param[in] aes Handle to operate - \param[in] in Pointer to the source data - \param[out] out Pointer to the result data - \param[in] size The source data size - \return Error code \ref Csi_error_t -*/ -csi_error_t csi_aes_ecb_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size); - -/** - \brief AES cbc encrypt - \param[in] aes Handle to operate - \param[in] in Pointer to the source data - \param[out] out Pointer to the result data - \param[in] size The source data size - \param[in] iv Init vector - \return Error code \ref Csi_error_t -*/ -csi_error_t csi_aes_cbc_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv); - -/** - \brief AES cbc decrypt - \param[in] aes Handle to operate - \param[in] in Pointer to the source data - \param[out] out Pointer to the result data - \param[in] size The source data size - \param[in] iv Init vector - \return Error code \ref Csi_error_t -*/ -csi_error_t csi_aes_cbc_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv); - -/** - \brief AES cfb1 encrypt - \param[in] aes Handle to operate - \param[in] in Pointer to the source data - \param[out] out Pointer to the result data - \param[in] size The source data size - \param[in] iv Init vector - \return Error code \ref Csi_error_t -*/ -csi_error_t csi_aes_cfb1_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv); - -/** - \brief AES cfb1 decrypt - \param[in] aes Handle to operate - \param[in] in Pointer to the source data - \param[out] out Pointer to the result data - \param[in] size The source data size - \param[in] iv Init vector - \return Error code \ref Csi_error_t -*/ -csi_error_t csi_aes_cfb1_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv); - -/** - \brief AES cfb8 encrypt - \param[in] aes Handle to operate - \param[in] in Pointer to the source data - \param[out] out Pointer to the result data - \param[in] size The source data size - \param[in] iv Init vector - \return Error code \ref Csi_error_t -*/ -csi_error_t csi_aes_cfb8_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv); - -/** - \brief AES cfb8 decrypt - \param[in] aes Handle to operate - \param[in] in Pointer to the source data - \param[out] out Pointer to the result data - \param[in] size The source data size - \param[in] iv Init vector - \return Error code \ref Csi_error_t -*/ -csi_error_t csi_aes_cfb8_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv); - -/** - \brief AES cfb128 decrypt - \param[in] aes Handle to operate - \param[in] in Pointer to the source data - \param[out] out Pointer to the result data - \param[in] size The source data size - \param[in] iv Init vector - \param[out] num The number of the 128-bit block we have used - \return Error code \ref csi_error_t -*/ -csi_error_t csi_aes_cfb128_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv, uint32_t *num); - -/** - \brief AES cfb128 encrypt - \param[in] aes Handle to operate - \param[in] in Pointer to the source data - \param[out] out Pointer to the result data - \param[in] size The source data size - \param[in] iv Init vector - \param[out] num The number of the 128-bit block we have used - \return Error code \ref csi_error_t -*/ -csi_error_t csi_aes_cfb128_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv, uint32_t *num); - -/** - \brief AES ofb encrypt - \param[in] aes Handle to operate - \param[in] in Pointer to the source data - \param[out] out Pointer to the result data - \param[in] size The source data size - \param[in] iv Init vector - \param[out] num The number of the 128-bit block we have used - \return Error code \ref csi_error_t -*/ -csi_error_t csi_aes_ofb_encrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv, uint32_t *num); - -/** - \brief AES ofb decrypt - \param[in] aes Handle to operate - \param[in] in Pointer to the source data - \param[out] out Pointer to the result data - \param[in] size The source data size - \param[in] iv Init vector - \param[out] num The number of the 128-bit block we have used - \return Error code \ref csi_error_t -*/ -csi_error_t csi_aes_ofb_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv, uint32_t *num); - -/** - \brief AES ctr encrypt - \param[in] aes Handle to operate - \param[in] in Pointer to the source data - \param[out] out Pointer to the result data - \param[in] size The source data size - \param[in] iv Init vector - \return Error code \ref csi_error_t -*/ -csi_error_t csi_aes_ctr_encrypt(csi_aes_t *aes, void *in,void *out, uint32_t size, void *iv); - -/** - \brief AES ctr decrypt - \param[in] aes Handle to operate - \param[in] in Pointer to the source data - \param[out] out Pointer to the result data - \param[in] size The source data size - \param[in] iv Init vecotr - \return Error code \ref csi_error_t -*/ -csi_error_t csi_aes_ctr_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv); - -/** - \brief AES cts encrypt - \param[in] aes Handle to operate - \param[in] in Pointer to the source data - \param[out] out Pointer to the result data - \param[in] size The source data size - \param[in] iv Init vector - \return Error code \ref csi_error_t -*/ -csi_error_t csi_aes_cts_encrypt(csi_aes_t *aes, void *in,void *out, uint32_t size, void *iv); - -/** - \brief AES cts decrypt - \param[in] aes Handle to operate - \param[in] in Pointer to the source data - \param[out] out Pointer to the result data - \param[in] size The source data size - \param[in] iv Init vecotr - \return Error code \ref csi_error_t -*/ -csi_error_t csi_aes_cts_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv); - - -/** - \brief AES xts encrypt - \param[in] aes Handle to operate - \param[in] in Pointer to the source data - \param[out] out Pointer to the result data - \param[in] size The source data size - \param[in] iv Init vector - \return Error code \ref csi_error_t -*/ -csi_error_t csi_aes_xts_encrypt(csi_aes_t *aes, void *in,void *out, uint32_t size, void *iv); - -/** - \brief AES xts decrypt - \param[in] aes Handle to operate - \param[in] in Pointer to the source data - \param[out] out Pointer to the result data - \param[in] size The source data size - \param[in] iv Init vecotr - \return Error code \ref csi_error_t -*/ -csi_error_t csi_aes_xts_decrypt(csi_aes_t *aes, void *in, void *out, uint32_t size, void *iv); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_AES_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/baud_calc.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/baud_calc.h deleted file mode 100755 index 1a077c10..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/baud_calc.h +++ /dev/null @@ -1,60 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/baud_calc.h - * @brief Header File for the PWM capture uart bandrate Driver - * @version V1.0 - * @date 9. Oct 2020 - * @model baud_calc - ******************************************************************************/ - -#ifndef _DRV_BAUD_CALC_H_ -#define _DRV_BAUD_CALC_H_ - -#include -#include -#include -#include - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \brief Baud rate calculation(Algorithm level) - \param[in] idx PWM idx - \param[in] channel Channel num - \return Error code(-1) or Baudare value -*/ -int drv_calc_baud_adjust(uint32_t idx, uint32_t channel); - -/** - \brief Baud rate calculation(Capture level) - \param[in] idx PWM idx - \param[in] channel Channel num - \return Error code(-1) or Baudare value -*/ -int drv_calc_baud_original(uint32_t idx, uint32_t channel); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_BAUD_CALC_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/codec.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/codec.h deleted file mode 100755 index d96a40b0..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/codec.h +++ /dev/null @@ -1,450 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/codec.h - * @brief head file for codec - * @version V1.0 - * @date 17. Mar 2020 - * @model codec - ******************************************************************************/ -#ifndef _DRV_CODEC_H_ -#define _DRV_CODEC_H_ - -#include -#include -#include -#include -#include "drv/ringbuf.h" - -typedef enum { - CODEC_EVENT_PERIOD_READ_COMPLETE = 0U, ///< A peroid data read completed - CODEC_EVENT_PERIOD_WRITE_COMPLETE = 1U, ///< A peroid data write completed - CODEC_EVENT_WRITE_BUFFER_EMPTY = 2U, ///< Fifo is empty - CODEC_EVENT_READ_BUFFER_FULL = 3U, ///< Fifo is full - CODEC_EVENT_ERROR_OVERFLOW = 4U, ///< Fifo overflow error - CODEC_EVENT_ERROR_UNDERFLOW = 5U, ///< Fifo underflow error - CODEC_EVENT_ERROR = 6U, ///< The device has a hardware error -} csi_codec_event_t; - -struct csi_codec; -typedef struct csi_codec csi_codec_t; -typedef struct csi_codec_output csi_codec_output_t; -struct csi_codec_output { - csi_codec_t *codec; - uint32_t ch_idx; ///< Codec output channel idx - void (*callback)(csi_codec_output_t *output, csi_codec_event_t event, void *arg); - void *arg; - csi_ringbuf_t *ring_buf; ///< The csi_ringbuf used to save audio data - uint32_t period; ///< When the period data is sent, the callback function will be called - uint32_t sound_channel_num; ///< Number of sound channel - csi_dma_ch_t *dma; ///< Dma channel handle - csi_state_t state; ///< Codec output channel current state - void *priv; - struct csi_codec_output *next; -}; - -typedef struct csi_codec_input csi_codec_input_t; -struct csi_codec_input { - csi_codec_t *codec; - uint32_t ch_idx; ///< Codec input channel idx - void (*callback)(csi_codec_input_t *input, csi_codec_event_t event, void *arg); - void *arg; - csi_ringbuf_t *ring_buf; ///< The csi_ringbuf used to save audio data - uint32_t period; ///< When the period data is received, the callback function will be called - uint32_t sound_channel_num; ///< Number of sound channel - csi_dma_ch_t *dma; ///< Codec input channel current state - csi_state_t state; ///< Dma channel handle - void *priv; - struct csi_codec_input *next; -}; - -struct csi_codec { - csi_dev_t dev; ///< Codec hw-device info - csi_codec_output_t *output_chs; ///< Codec output channel operate handle - csi_codec_input_t *input_chs; ///< Codec input channel operate handle - void *priv; ///< User private param passed to user callback -}; - -typedef enum { - CODEC_OUTPUT_SINGLE_ENDED, ///< Single-ended output - CODEC_OUTPUT_DIFFERENCE, ///< Differential output -} csi_codec_output_mode_t; - -typedef enum { - CODEC_INPUT_SINGLE_ENDED, ///< Single-ended input - CODEC_INPUT_DIFFERENCE, ///< Differential input -} csi_codec_input_mode_t; - -typedef struct { - uint32_t sample_rate; ///< Input data sample rate - uint32_t bit_width; ///< Input data sample width - csi_codec_input_mode_t mode; ///< Input work mode - uint8_t *buffer; ///< The buffer used to save audio data - uint32_t buffer_size; ///< Input buffer size - uint32_t period; ///< When a peroid data is reached,the callback function is called - uint32_t sound_channel_num; ///< Number of soundtrack per channel -} csi_codec_input_config_t; - -typedef struct { - uint32_t sample_rate; ///< Output data sample rate - uint32_t bit_width; ///< Onput data sample width - csi_codec_output_mode_t mode; ///< Onput work mode - uint8_t *buffer; ///< The buffer used to save audio data - uint32_t buffer_size; ///< Output buffer size - uint32_t period; ///< When a peroid data is reached,the callback function is called - uint32_t sound_channel_num; ///< Number of soundchannel per channel -} csi_codec_output_config_t; - -/** - \brief Init the codec according to the specified - \param[in] codec Codec handle to operate - \param[in] idx Codec interface idx - \return error code \ref csi_error_t -*/ -csi_error_t csi_codec_init(csi_codec_t *codec, uint32_t idx); - -/** - \brief Codec uninit - \param[in] codec Codec handle to operate - \return None -*/ -void csi_codec_uninit(csi_codec_t *codec); - -/** - \brief Open a codec output channel - \param[in] codec Codec handle to operate - \param[in] ch Codec output channel handle - \param[in] ch_idx Codec output channel idx - \return error code \ref csi_error_t -*/ -csi_error_t csi_codec_output_open(csi_codec_t *codec, csi_codec_output_t *ch, uint32_t ch_idx); - -/** - \brief Config codec output channel - \param[in] ch Codec output channel handle - \param[in] config Codec channel param. \ref csi_codec_output_config_t - \return error code \ref csi_error_t -*/ -csi_error_t csi_codec_output_config(csi_codec_output_t *ch, csi_codec_output_config_t *config); - -/** - \brief Attach the callback handler to codec output - \param[in] ch Codec output channel handle - \param[in] cb Callback function - \param[in] arg User private param - \return error code \ref csi_error_t -*/ -csi_error_t csi_codec_output_attach_callback(csi_codec_output_t *ch, void *callback, void *arg); - -/** - \brief Detach the callback handler - \param[in] ch Codec output channel handle - \return None -*/ -void csi_codec_output_detach_callback(csi_codec_output_t *ch); - -/** - \brief Close a codec output channel - \param[in] ch Codec output channel handle - \return error code \ref csi_error_t -*/ -void csi_codec_output_close(csi_codec_output_t *ch); - -/** - \brief Link DMA channel to codec output channel - \param[in] ch Codec output channel handle - \param[in] dma The codec output DMA channel handle, when it is NULL means to unlink the channel - \return error code \ref csi_error_t -*/ -csi_error_t csi_codec_output_link_dma(csi_codec_output_t *ch, csi_dma_ch_t *dma); - -/** - \brief Send an amount of data to buffer in blocking mode - \param[in] ch The codec output channel - \param[in] data Pointer to send data buffer - \param[in] size Send data size - \return the num of data witch is send successful -*/ -uint32_t csi_codec_output_write(csi_codec_output_t *ch, const void *data, uint32_t size); - -/** - \brief Send data to the buffer with asynchronous sending - The data is first written to the buffer and then output through the codec interface - This function does not block, and the return value is the number - Of data that was successfully written to the buffer - \param[in] ch The codec output channel - \param[in] data Pointer to send data buffer - \param[in] size Send data size - \return The data size that send to buffer -*/ -uint32_t csi_codec_output_write_async(csi_codec_output_t *ch, const void *data, uint32_t size); - -/** - \brief Start sending data from the buffer - \param[in] ch Codec output channel handle - \return error code \ref csi_error_t -*/ -csi_error_t csi_codec_output_start(csi_codec_output_t *ch); - -/** - \brief Stop sending data from the buffer - \param[in] ch Codec output channel handle - \return None -*/ -void csi_codec_output_stop(csi_codec_output_t *ch); - -/** - \brief Pause sending data from the buffer - \param[in] ch Codec output channel handle - \return error code \ref csi_error_t -*/ -csi_error_t csi_codec_output_pause(csi_codec_output_t *ch); - -/** - \brief Resume sending data from the buffer - \param[in] ch Codec output channel handle - \return error code \ref csi_error_t -*/ -csi_error_t csi_codec_output_resume(csi_codec_output_t *ch); - -/** - \brief Get output-buffer free space - \param[in] ch Codec output channel handle - \return Buffer free space (bytes) -*/ -uint32_t csi_codec_output_buffer_avail(csi_codec_output_t *ch); - -/** - \brief Get used space of output-buffer - \param[in] ch Codec output channel handle - \return Buffer free space (bytes) -*/ -uint32_t csi_codec_output_buffer_remain(csi_codec_output_t *ch); - -/** - \brief Reset the buf, discard all data in the buffer - \param[in] ch Codec output channel handle - \return error code \ref csi_error_t -*/ -csi_error_t csi_codec_output_buffer_reset(csi_codec_output_t *ch); - -/** - \brief Mute codec ouput channel - \param[in] ch Codec output channel handle - \param[in] en True enable codec mute. false disable codec mute - \return error code \ref csi_error_t -*/ -csi_error_t csi_codec_output_mute(csi_codec_output_t *ch, bool enable); - -/** - \brief Set codec ouput channel digital gain - \param[in] ch Codec output channel handle - \param[in] val Gain val - \return error code \ref csi_error_t -*/ -csi_error_t csi_codec_output_digital_gain(csi_codec_output_t *ch, uint32_t val); - -/** - \brief Set codec ouput channel analog gain - \param[in] ch Codec output channel handle - \param[in] val Gain val - \return error code \ref csi_error_t -*/ -csi_error_t csi_codec_output_analog_gain(csi_codec_output_t *ch, uint32_t val); - -/** - \brief Set codec ouput channel mix gain - \param[in] ch Codec output channel handle - \param[in] val Gain val - \return error code \ref csi_error_t -*/ -csi_error_t csi_codec_output_mix_gain(csi_codec_output_t *ch, uint32_t val); - -/** - \brief Get codec output channel state - \param[in] ch Codec output channel handle - \param[out] state Channel state. \ref csi_state_t - \return channel state -*/ -csi_error_t csi_codec_output_get_state(csi_codec_output_t *ch, csi_state_t *state); - -/** - \brief Open a codec input channel - \param[in] codec Codec handle to operate - \param[in] ch Codec input channel handle - \param[in] ch_idx Codec input channel idx - \return error code \ref csi_error_t -*/ -csi_error_t csi_codec_input_open(csi_codec_t *codec, csi_codec_input_t *ch, uint32_t ch_idx); - -/** - \brief Config codec input channel - \param[in] ch Codec input channel handle - \param[in] config Codec channel prarm. \ref csi_codec_input_config_t - \return error code \ref csi_error_t -*/ -csi_error_t csi_codec_input_config(csi_codec_input_t *ch, csi_codec_input_config_t *config); - -/** - \brief Attach the callback handler to codec output - \param[in] ch Codec input channel handle - \param[in] cb Callback function - \param[in] arg User private param for event callback - \return error code \ref csi_error_t -*/ -csi_error_t csi_codec_input_attach_callback(csi_codec_input_t *ch, void *callback, void *arg); - -/** - \brief Detach the callback handler - \param[in] ch Codec input channel handle - \return None -*/ -void csi_codec_input_detach_callback(csi_codec_input_t *ch); - -/** - \brief Close a codec input channel - \param[in] ch Codec input channel handle - \return None -*/ -void csi_codec_input_close(csi_codec_input_t *ch); - -/** - \brief Link DMA channel to codec input channel - \param[in] ch Codec input channel handle - \param[in] dma The codec input DMA channel handle, when it is NULL means to unlink the channel - \return error code \ref csi_error_t -*/ -csi_error_t csi_codec_input_link_dma(csi_codec_input_t *ch, csi_dma_ch_t *dma); - -/** - \brief Read an amount of data in blocking mode - \param[in] ch Codec input channel handle - \param[in] data Pointer to receive data buffer - \param[in] size Receive data size - \return The size of data read successfully -*/ -uint32_t csi_codec_input_read(csi_codec_input_t *ch, void *data, uint32_t size); - -/** - \brief Read data from the buffer - using asynchronous receive - this function read data from the buffer, returns the number of successful receive - and returns 0 if there is no data in the buffer - \param[in] ch Codec input channel handle - \param[in] data Pointer to receive data buffer - \param[in] size Receive data size - \return The size of data read successfully -*/ -uint32_t csi_codec_input_read_async(csi_codec_input_t *ch, void *data, uint32_t size); - -/** - \brief Start receive data to the buffer - \param[in] ch Codec input channel handle - \return error code \ref csi_error_t -*/ -csi_error_t csi_codec_input_start(csi_codec_input_t *ch); - -/** - \brief Stop receive data - \param[in] ch Codec input channel handle - \return None -*/ -void csi_codec_input_stop(csi_codec_input_t *ch); - -/** - \brief Reset the buf, discard all data in the buffer - \param[in] ch Codec input channel handle - \return error code \ref csi_error_t -*/ -csi_error_t csi_codec_input_buffer_reset(csi_codec_input_t *ch); - -/** - \brief Get input-buffer free space - \param[in] ch Codec input channel handle - \return Buffer free space (bytes) -*/ -uint32_t csi_codec_input_buffer_avail(csi_codec_input_t *ch); - -/** - \brief Get used space of input-buffer - \param[in] ch Codec input channel handle - \return Buffer free space (bytes) -*/ -uint32_t csi_codec_input_buffer_remain(csi_codec_input_t *ch); - -/** - \brief Mute codec input channel - \param[in] ch Codec input channel handle - \param[in] en True enable codec mute. false disable codec mute - \return error code \ref csi_error_t -*/ -csi_error_t csi_codec_input_mute(csi_codec_input_t *ch, bool en); - -/** - \brief Set codec input channel digital gain - \param[in] ch Codec input channel handle - \param[in] val Gain val - \return error code \ref csi_error_t -*/ -csi_error_t csi_codec_input_digital_gain(csi_codec_input_t *ch, uint32_t val); - -/** - \brief Set codec input channel analog gain - \param[in] ch Codec input channel handle - \param[in] val Gain val - \return error code \ref csi_error_t -*/ -csi_error_t csi_codec_input_analog_gain(csi_codec_input_t *ch, uint32_t val); - -/** - \brief Set codec input channel mix gain - \param[in] ch Codec input channel handle - \param[in] val Gain val - \return error code \ref csi_error_t -*/ -csi_error_t csi_codec_input_mix_gain(csi_codec_input_t *ch, uint32_t val); - -/** - \brief Get codec input channel state - \param[in] ch Codec input channel handle - \param[out] state Channel state - \return Channel state -*/ -csi_error_t csi_codec_input_get_state(csi_codec_input_t *ch, csi_state_t *state); - -/** - \brief Enable codec power manage - \param[in] codec Codec handle to operate - \return error code \ref csi_error_t -*/ -csi_error_t csi_codec_enable_pm(csi_codec_t *codec); - -/** - \brief Disable codec power manage - \param[in] codec Codec handle to operate - \return None -*/ -void csi_codec_disable_pm(csi_codec_t *codec); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_CODEC_H_ */ - diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/crc.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/crc.h deleted file mode 100755 index 2fbd43db..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/crc.h +++ /dev/null @@ -1,136 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file crc.h - * @brief Header File for CRC Driver - * @version V1.0 - * @date 02. June 2020 - * @model crc - ******************************************************************************/ - -#ifndef _DRV_CRC_H_ -#define _DRV_CRC_H_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Compute the CRC-7 checksum of a buffer. - * - * See JESD84-A441. Used by the MMC protocol. Uses 0x09 as the - * polynomial with no reflection. The CRC is left - * justified, so bit 7 of the result is bit 6 of the CRC. - * init = 0; poly = 0x09 refin = 0 refout = 0 xorout = 0 - * \param[in] crc Crc init value or crc immediate result - * \param[in] data Data buf to be calculate - * \param[in] size Data size - * - * \return The computed CRC7 value - */ -uint8_t csi_crc7_be(uint8_t crc, uint8_t *data, uint32_t size); - -/** - * \brief Compute the CRC-8 checksum of a buffer. - * init = 0 or 0xff; poly = 0x07 refin = 0 refout = 0 xorout = 0 - * \param[in] crc Crc init value or crc immediate result - * \param[in] data Data buf to be calculate - * \param[in] size Data size - * \return The computed CRC8 value - */ -uint8_t csi_crc8(uint8_t crc, uint8_t *data, size_t size); - -/** - * \brief Compute the CRC-8 checksum of a buffer. - * init = 0; poly = 0x31 refin = 1 refout = 1 xorout = 0 - * \param[in] crc Crc init value or crc immediate result - * \param[in] data Data buf to be calculate - * \param[in] size Data size - * \return The computed CRC8 value - */ -uint8_t csi_crc8_maxim(uint8_t crc, uint8_t *data, size_t size); - -/** - * \brief Compute the CRC-16 checksum of a buffer. - * init = 0 or 0xffff; poly = 0x8005 refin = 1 refout = 1 xorout = 0 - * \param[in] crc Crc init value or crc immediate result - * \param[in] data Data buf to be calculate - * \param[in] size Data size - * \return The computed CRC16 without xorout - */ -uint16_t csi_crc16(uint16_t crc, uint8_t *data, uint32_t size); - -/** - * \brief Compute the CRC-16 checksum of a buffer. - * init = 0; poly = 0x1021 refin = 1 refout = 1 xorout = 0 - * \param[in] crc Crc init value or crc immediate result - * \param[in] data Data buf to be calculate - * \param[in] size Data size - * \return The computed CRC16 without xorout - */ -uint16_t csi_crc16_ccitt(uint16_t crc, uint8_t *data, uint32_t size); - -/** - * \brief Compute the CRC-16 checksum of a buffer. - * init = 0; poly = 0x3d65 refin = 1 refout = 1 xorout = 0xffff - * \param[in] init_value Crc init value - * \param[in] data Data buf to be calculate - * \param[in] size Data size - * \return The computed CRC16 with xorout - */ -uint16_t csi_crc16_dnp(uint16_t init_value, uint8_t *data, uint32_t size); - -/** - * \brief Compute the CRC-16 checksum of a buffer. - * init = 0; poly = 0x1021 refin = 0 refout = 0 xorout = 0 - * \param[in] crc Crc init value or crc immediate result - * \param[in] data Data buf to be calculate - * \param[in] size Data size - * \return The computed CRC16 without xorout - */ -uint16_t csi_crc16_itu(uint16_t crc, uint8_t *data, uint32_t size); - -/** - * \brief Compute the CRC-32 checksum of a buffer.Little-endian by bit. - * init = 0; poly = 0xEDB88320 refin = 0 refout = 0 xorout = 0 - * \param[in] crc Crc init value or crc immediate result - * \param[in] data Data buf to be calculate - * \param[in] size Data size - * \return The computed CRC32 without xorout - */ -uint32_t csi_crc32_le(uint32_t crc, uint8_t *data, uint32_t size); - -/** - * \brief Compute the CRC-32 checksum of a buffer.Big-endian by bit. - * init = 0; poly = 0x04C11DB7 refin = 0 refout = 0 xorout = 0 - * \param[in] crc Crc init value or crc immediate result - * \param[in] data Data buf to be calculate - * \param[in] size Data size - * \return The computed CRC32 without xorout - */ -uint32_t csi_crc32_be(uint32_t crc, uint8_t *data, uint32_t size); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_CRC_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/des.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/des.h deleted file mode 100755 index 2b0540ea..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/des.h +++ /dev/null @@ -1,174 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/des.h - * @brief Header File for DES Driver - * @version V1.0 - * @date 24. Oct 2022 - * @model des - ******************************************************************************/ - -#ifndef _DRV_DES_H_ -#define _DRV_DES_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** -\brief DES key-len-bits type -*/ -typedef enum { - DES_KEY_LEN_BITS_64 = 0, /*64 Data bits*/ - DES_KEY_LEN_BITS_128, /*128 Data bits*/ - DES_KEY_LEN_BITS_192, /*192 Data bits*/ -} csi_des_key_bits_t; - -/** -\brief DES Ctrl Block -*/ -typedef struct { - csi_dev_t dev; - void *priv; -} csi_des_t; - -/** - \brief Initialize DES interface. Initializes the resources needed for the DES interface - \param[in] des Handle to operate - \param[in] idx Device id - \return Error code \ref csi_error_t -*/ -csi_error_t csi_des_init(csi_des_t *des, uint32_t idx); - -/** - \brief De-initialize DES interface. Stops operation and releases the software resources used by the interface - \param[in] des Dandle to operate - \return None -*/ -void csi_des_uninit(csi_des_t *des); - -/** - \brief Set encrypt key - \param[in] des Handle to operate - \param[in] key Pointer to the key buf - \param[in] key_len Pointer to \ref csi_des_key_bits_t - \return Error code \ref Csi_error_t -*/ -csi_error_t csi_des_set_encrypt_key(csi_des_t *des, void *key, csi_des_key_bits_t key_len); - -/** - \brief Set decrypt key - \param[in] des Handle to operate - \param[in] key Pointer to the key buf - \param[in] key_len Pointer to \ref csi_des_key_bits_t - \return Error code \ref Csi_error_t -*/ -csi_error_t csi_des_set_decrypt_key(csi_des_t *des, void *key, csi_des_key_bits_t key_len); - -/** - \brief DES ecb encrypt - \param[in] des Handle to operate - \param[in] in Pointer to the source data - \param[out] out Pointer to the result data - \param[in] size The source data size - \return Error code \ref Csi_error_t -*/ -csi_error_t csi_des_ecb_encrypt(csi_des_t *des, void *in, void *out, uint32_t size); - -/** - \brief DES ecb decrypt - \param[in] des Handle to operate - \param[in] in Pointer to the source data - \param[out] out Pointer to the result data - \param[in] size The source data size - \return Error code \ref Csi_error_t -*/ -csi_error_t csi_des_ecb_decrypt(csi_des_t *des, void *in, void *out, uint32_t size); - -/** - \brief DES cbc encrypt - \param[in] des Handle to operate - \param[in] in Pointer to the source data - \param[out] out Pointer to the result data - \param[in] size The source data size - \param[in] iv Init vector - \return Error code \ref Csi_error_t -*/ -csi_error_t csi_des_cbc_encrypt(csi_des_t *des, void *in, void *out, uint32_t size, void *iv) ; - -/** - \brief DES cbc decrypt - \param[in] des Handle to operate - \param[in] in Pointer to the source data - \param[out] out Pointer to the result data - \param[in] size The source data size - \param[in] iv Init vector - \return Error code \ref Csi_error_t -*/ -csi_error_t csi_des_cbc_decrypt(csi_des_t *des, void *in, void *out, uint32_t size, void *iv); - -/** - \brief TDES ecb encrypt - \param[in] des Handle to operate - \param[in] in Pointer to the source data - \param[out] out Pointer to the result data - \param[in] size The source data size - \return Error code \ref Csi_error_t -*/ -csi_error_t csi_tdes_ecb_encrypt(csi_des_t *des, void *in, void *out, uint32_t size); - -/** - \brief TDES ecb decrypt - \param[in] des Handle to operate - \param[in] in Pointer to the source data - \param[out] out Pointer to the result data - \param[in] size The source data size - \return Error code \ref Csi_error_t -*/ -csi_error_t csi_tdes_ecb_decrypt(csi_des_t *des, void *in, void *out, uint32_t size); - -/** - \brief TDES cbc encrypt - \param[in] des Handle to operate - \param[in] in Pointer to the source data - \param[out] out Pointer to the result data - \param[in] size The source data size - \param[in] iv Init vector - \return Error code \ref Csi_error_t -*/ -csi_error_t csi_tdes_cbc_encrypt(csi_des_t *des, void *in, void *out, uint32_t size, void *iv) ; - -/** - \brief TDES cbc decrypt - \param[in] des Handle to operate - \param[in] in Pointer to the source data - \param[out] out Pointer to the result data - \param[in] size The source data size - \param[in] iv Init vector - \return Error code \ref Csi_error_t -*/ -csi_error_t csi_tdes_cbc_decrypt(csi_des_t *des, void *in, void *out, uint32_t size, void *iv); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_DES_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/drv_fft.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/drv_fft.h deleted file mode 100755 index 76330849..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/drv_fft.h +++ /dev/null @@ -1,83 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv_fft.h - * @brief header file for gpio driver - * @version V1.0 - * @date 11. Nov 2017 - * @model fft - ******************************************************************************/ - -#ifndef _CSI_FFT_H_ -#define _CSI_FFT_H_ - - -#include -#include -#include -//#include - -#ifdef __cplusplus - extern "C" { -#endif - -typedef enum { - // 512-point FFT - CSKY_MCA_FFT_LEN_512 = 0x1, - // 256-point FFT - CSKY_MCA_FFT_LEN_256 = 0x2, - // 128-point FFT - CSKY_MCA_FFT_LEN_128 = 0x4, - // 64-point FFT - CSKY_MCA_FFT_LEN_64 = 0x8, - // 32-point FFT - CSKY_MCA_FFT_LEN_32 = 0x10, - // 16-point FFT - CSKY_MCA_FFT_LEN_16 = 0x20, -} csky_mca_fft_len_t; - -/* 8-bit fixed-point numeric type in user-defined format */ -typedef int8_t fxp8_t; -/* 16-bit fixed-point numeric type in user-defined format */ -typedef int16_t fxp16_t; -/* 24-bit fixed-point numeric type in user-defined format */ -typedef int32_t fxp24_t; -/* 32-bit fixed-point numeric type in user-defined format */ -typedef int32_t fxp32_t; -/* 64-bit fixed-point numeric type in user-defined format */ -typedef int64_t fxp64_t; - -/* 8-bit fixed-point numeric type in 1.0.7 format */ -typedef fxp8_t q7_t; -/* 16-bit fixed-point numeric type in 1.0.15 format */ -typedef fxp16_t q15_t; -/* 32-bit fixed-point numeric type in 1.15.16 format */ -typedef fxp32_t q16_t; - -void csky_mca_rfft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, size_t input_size, fxp32_t *output); -void csky_mca_cfft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, fxp32_t *output); -void csky_mca_rifft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, fxp32_t *output); -void csky_mca_cifft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, fxp32_t *output); -void csky_mca_power_spectrum_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, size_t input_size, fxp64_t *output); - -#ifdef __cplusplus -} -#endif - -#endif /* _CSI_FFT_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/ecdh.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/ecdh.h deleted file mode 100755 index 5e9acf78..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/ecdh.h +++ /dev/null @@ -1,92 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/ecdh.h - * @brief Header File for ECDH Driver - * @version V1.0 - * @date 9. May 2023 - * @model ecdh - ******************************************************************************/ - -#ifndef _DRV_ECDH_H_ -#define _DRV_ECDH_H_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** -\brief ECDH Ctrl Block -*/ -typedef struct { - csi_dev_t dev; - void *priv; -} csi_ecdh_t; - -/** - \brief Initialize ECDH interface. Initializes the resources needed for the ECDH interface - \param[in] ecdh Handle to operate - \param[in] idx Device id - \return Error code \ref csi_error_t -*/ -csi_error_t csi_ecdh_init(csi_ecdh_t *ecdh, uint32_t idx); - -/** - \brief De-initialize ECDH interface. Stops operation and releases the software resources used by the interface - \param[in] ecdh Dandle to operate - \return None -*/ -void csi_ecdh_uninit(csi_ecdh_t *ecdh); - -/** - \brief Load curve param to engin - \param[in] ecdh Handle to operate - \param[in] type Pointer to \ref csi_curve_type_t - \return Error code \ref csi_error_t -*/ -csi_error_t csi_ecdh_load_curve(csi_ecdh_t *ecdh, csi_curve_type_t type); - -/** - \brief ECDH generate key pair - \param[in] ecdh Handle to operate - \param[out] prikey Pointer to the private key buf - \param[out] pubkey Pointer to the public key buf - \return Error code \ref Csi_error_t -*/ -csi_error_t csi_ecdh_gen_keypair(csi_ecdh_t *ecdh, uint8_t *prikey, uint8_t *pubkey); - -/** - \brief ECDH generate secret key - \param[in] ecdh Handle to operate - \param[in] prikey Pointer to the private key buf - \param[in] pubkey Pointer to the public key buf - \param[out] sk Pointer to the secret key buf - \param[out] sk_len The secret key length - \return Error code \ref Csi_error_t -*/ -csi_error_t csi_ecdh_calc_secret(csi_ecdh_t *ecdh, const uint8_t *privkey, const uint8_t *pubkey, uint8_t *sk, uint32_t *sk_len); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_ECDH_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/ecdsa.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/ecdsa.h deleted file mode 100755 index 4c6d91a6..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/ecdsa.h +++ /dev/null @@ -1,112 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/ecdsa.h - * @brief Header File for ECDSA Driver - * @version V1.0 - * @date 9. May 2023 - * @model ecdsa - ******************************************************************************/ - -#ifndef _DRV_ECDSA_H_ -#define _DRV_ECDSA_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** -\brief EC curve type -*/ -typedef enum { - CSI_CURVES_SECP256K1 = 0U, /* SECG curve over a 256 bit prime field */ - CSI_CURVES_SECP384R1, /* NIST/SECG curve over a 384 bit prime field */ - CSI_CURVES_SECP521R1, /* NIST/SECG curve over a 521 bit prime field */ - CSI_CURVES_BRAINPOOL256R1, /* RFC 5639 curve over a 256 prime field */ - CSI_CURVES_BRAINPOOL256T1, /* RFC 5639 curve over a 256 prime field */ - CSI_CURVES_BRAINPOOL512R1, /* RFC 5639 curve over a 512 prime field */ - CSI_CURVES_BRAINPOOL512T1, /* RFC 5639 curve over a 512 prime field */ -} csi_curve_type_t; - -/** -\brief ECDSA Ctrl Block -*/ -typedef struct { - csi_dev_t dev; - void *priv; -} csi_ecdsa_t; - -/** - \brief Initialize ECDSA interface. Initializes the resources needed for the ECDSA interface - \param[in] ecdsa Handle to operate - \param[in] idx Device id - \return Error code \ref csi_error_t -*/ -csi_error_t csi_ecdsa_init(csi_ecdsa_t *ecdsa, uint32_t idx); - -/** - \brief De-initialize ECDSA interface. Stops operation and releases the software resources used by the interface - \param[in] ecdsa Dandle to operate - \return None -*/ -void csi_ecdsa_uninit(csi_ecdsa_t *ecdsa); - -/** - \brief Load curve param to engin - \param[in] ecdsa Handle to operate - \param[in] type Pointer to \ref csi_curve_type_t - \return Error code \ref csi_error_t -*/ -csi_error_t csi_ecdsa_load_curve(csi_ecdsa_t *ecdsa, csi_curve_type_t type); - -/** - \brief Ecdsa Sign - \param[in] ecdsa Handle to operate - \param[in] prikey Pointer to the private key buf - \param[in] prikey_len The private key length - \param[in] dgst Pointer to the digest buf - \param[in] dgst_len The digest length - \param[out] sig Pointer to the signature buf - \param[out] sig_len The signature length - \return Error code \ref Csi_error_t -*/ -csi_error_t csi_ecdsa_sign(csi_ecdsa_t *ecdsa, const uint8_t *prikey, uint32_t prikey_len, - const uint8_t *dgst, uint32_t dgst_len, uint8_t *sig, uint32_t *sig_len); - -/** - \brief Ecdsa Verify - \param[in] ecdsa Handle to operate - \param[in] pubkey Pointer to the public key buf - \param[in] prikey_len The public key length - \param[in] dgst Pointer to the digest buf - \param[in] dgst_len The digest length - \param[in] sig Pointer to the signature buf - \param[in] sig_len The signature length - \return Error code \ref Csi_error_t -*/ -csi_error_t csi_ecdsa_verify(csi_ecdsa_t *ecdsa, const uint8_t *pubkey, uint32_t pubkey_len, - const uint8_t *dgst, uint32_t gst_len, const uint8_t *sig, uint32_t sig_len); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_ECDSA_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/eflash.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/eflash.h deleted file mode 100755 index 8d6c41d0..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/eflash.h +++ /dev/null @@ -1,140 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file eflash.h - * @brief header file for eflash driver - * @version V1.0 - * @date 02. June 2017 - * @model eflash - ******************************************************************************/ -#ifndef _DRV_EFLASH_H_ -#define _DRV_EFLASH_H_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** -\brief Flash information -*/ -typedef struct { - uint32_t flash_size; ///< Chip End address (start+size-1) - uint32_t sector_size; ///< Uniform sector size in bytes - uint32_t erased_value; ///< erased value -} csi_eflash_info_t; - -/** -\brief Flash Status -*/ -typedef struct { - uint32_t busy : 1; ///< Flash busy flag - uint32_t error : 1; ///< Read/Program/Erase error flag (cleared on start of next operation) -} eflash_status_t; - -/// definition for eflash handle. -typedef struct { - csi_dev_t dev; - void *arg; - csi_eflash_info_t eflashinfo; - uint16_t prog; - uint16_t erase; - void *priv; -} csi_eflash_t; - -// Function documentation - -/** - \brief Initialize EFLASH Interface. 1. Initializes the resources needed for the EFLASH interface 2.registers event callback function - \param[in] eflash eflash handle to operate. - \param[in] idx device id - \param[in] arg User can define it by himself as callback's param - \return error code -*/ -csi_error_t csi_eflash_init(csi_eflash_t *eflash, int32_t idx, void *arg); - -/** - \brief De-initialize EFLASH Interface. stops operation and releases the software resources used by the interface - \param[in] eflash eflash handle to operate. - \return error code -*/ -csi_error_t csi_eflash_uninit(csi_eflash_t *eflash); - -/** - \brief Read data from Flash. - \param[in] eflash eflash handle to operate. - \param[in] offset Data address. - \param[out] data Pointer to a buffer storing the data read from Flash. - \param[in] size Number of data items to read. - \return error code -*/ -csi_error_t csi_eflash_read(csi_eflash_t *eflash, uint32_t offset, void *data, uint32_t size); - -/** - \brief Program data to Flash. - \param[in] eflash eflash handle to operate. - \param[in] offset Data address. - \param[in] data Pointer to a buffer containing the data to be programmed to Flash. - \param[in] size Number of data items to program. - \return error code -*/ -csi_error_t csi_eflash_program(csi_eflash_t *eflash, uint32_t offset, const void *data, uint32_t size); - -/** - \brief Erase Flash Sector. - \param[in] eflash eflash handle to operate. - \param[in] offset flash address, flash address need sector size aligned - \param[in] size erase size - \return error code -*/ -csi_error_t csi_eflash_erase(csi_eflash_t *eflash, uint32_t offset,uint32_t size); - -/** - \brief Erase whole flash - \param[in] eflash eflash handle to operate. - \return error code -*/ -csi_error_t csi_eflash_erase_chip(csi_eflash_t *eflash); - -/** - \brief Get Flash information. - \param[in] eflash eflash handle to operate. -*/ -void csi_eflash_dev_info(csi_eflash_t *eflash,csi_eflash_info_t *eflash_info); - -/** - \brief enable eflash power manage - \param[in] eflash eflash handle to operate. - \return error code -*/ -csi_error_t csi_eflash_enable_pm(csi_eflash_t *eflash); - -/** - \brief disable eflash power manage - \param[in] eflash eflash handle to operate. -*/ -void csi_eflash_disable_pm(csi_eflash_t *eflash); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_EFLASH_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/efuse.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/efuse.h deleted file mode 100755 index 2c697074..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/efuse.h +++ /dev/null @@ -1,93 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/efuse.h - * @brief Header File for EFUSE Driver - * @version V1.0 - * @date 22. Mar 2020 - * @model efuse - ******************************************************************************/ -#ifndef _DEV_EFUSEC_H_ -#define _DEV_EFUSEC_H_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - uint32_t start; ///< Efuse start address - uint32_t end; ///< Efuse end address - uint32_t size; ///< Efuse size -} csi_efuse_info_t; - -typedef struct { - csi_dev_t dev; - csi_efuse_info_t info; -} csi_efuse_t; - -/** - \brief Initialize EFUSEC Interface. 1. Initializes the resources needed for the EFUSEC interface - \param[in] idx Device id - \return Error code -*/ -csi_error_t csi_efuse_init(csi_efuse_t *efuse, int32_t idx); - -/** - \brief De-initialize EFUSEC Interface. stops operation and releases the software resources used by the interface - \param[in] efuse Efuse efuse to operate. - \return None -*/ -void csi_efuse_uninit(csi_efuse_t *efuse); - -/** - \brief Read data from Efuse. - \param[in] efuse Efuse handle to operate. - \param[in] addr Data address. - \param[out] data Pointer to a buffer storing the data read from Efuse. - \param[in] size Number of data items to read. - \return Number of data items read or error code -*/ -int32_t csi_efuse_read(csi_efuse_t *efuse, uint32_t addr, void *data, uint32_t size); - -/** - \brief Program data to Efuse. - \param[in] efuse Efuse handle to operate. - \param[in] addr Data address. - \param[in] data Pointer to a buffer containing the data to be programmed to Efuse. - \param[in] cnt Number of data items to program. - \return number of data items programmed or error code -*/ -int32_t csi_efuse_program(csi_efuse_t *efuse, uint32_t addr, const void *data, uint32_t size); - -/** - \brief Get Efuse information. - \param[in] efuse Efuse handle to operate. - \param[out] info Efuse info \refs csi_efuse_info_t. - \return Error code -*/ -csi_error_t csi_efuse_get_info(csi_efuse_t *efuse, csi_efuse_info_t *info); - -#ifdef __cplusplus -} -#endif - -#endif /* _CSI_EFUSEC_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/etb.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/etb.h deleted file mode 100755 index 20dcfac7..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/etb.h +++ /dev/null @@ -1,102 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv_etb.h - * @brief header file for event trigger driver - * @version V1.0 - * @date 27. octorber 2017 - * @model etb - ******************************************************************************/ - -#ifndef _DRV_ETB_H_ -#define _DRV_ETB_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ETB_HARDWARE_TRIG = 0, ///< etb channel inout is hardware trigger. - ETB_SOFTWARE_TRIG ///< etb channel inout is software trigger. -} csi_etb_trig_mode_t; - -typedef enum { - ETB_CH_ONE_TRIGGER_ONE = 0, ///< one device trig one deivce - ETB_CH_ONE_TRIGGER_MORE, ///< one device trig two for more device - ETB_CH_MORE_TRIGGER_ONE ///< two or more device trig one deivce -} csi_etb_ch_type_t; - -typedef struct { - uint8_t src_ip; ///< a specific number represent a location in an source trigger location map to trigger other ip(s). - uint8_t dst_ip; ///< a specific number represent an location in an dest trigger map to wait signal(s) from source ip(s) or location(s). - csi_etb_trig_mode_t trig_mode; ///< the input source is hardware trigger or software trigger. - csi_etb_ch_type_t ch_type; ///< channel type -} csi_etb_config_t; - -/** - \brief Init the etb device - \return error code -*/ -csi_error_t csi_etb_init(void); - -/** - \brief Uninit the etb device - \return none -*/ -void csi_etb_uninit(void); - -/** - \brief alloc an etb channel - \param[in] ch_mode etb channel work mode - \return channel id or CSI_ERROR -*/ -int32_t csi_etb_ch_alloc(csi_etb_ch_type_t ch_type); - -/** - \brief free an etb channel - \param[in] ch_id etb channel work mode - \return none -*/ -void csi_etb_ch_free(int32_t ch_id); - -/** - \brief config etb channel - \param[in] ch_id etb channel id - \param[in] config the config structure for etb channel - \return csi error code -*/ -csi_error_t csi_etb_ch_config(int32_t ch_id, csi_etb_config_t *config); - -/** - \brief start an etb channel - \param[in] ch_id etb channel id - \return none -*/ -void csi_etb_ch_start(int32_t ch_id); - -/** - \brief stop an etb channel - \param[in] etb etb channel id - \return none -*/ -void csi_etb_ch_stop(int32_t ch_id); - -#endif /* _CSI_ETB_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/eth.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/eth.h deleted file mode 100644 index 3a2aedb4..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/eth.h +++ /dev/null @@ -1,111 +0,0 @@ -/** - * Copyright (C) 2016 CSI Project. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -#ifndef _CSI_NET_H_ -#define _CSI_NET_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#define CSI_ETH_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor)) - -/** -\brief Driver Version -*/ -typedef struct csi_driver_version { - uint16_t api; ///< API version - uint16_t drv; ///< Driver version -} csi_drv_version_t; - -/* General return codes */ -#define CSI_ETH_OK 0 ///< Operation succeeded -#define CSI_ETH_ERROR CSI_DRV_ERRNO_ETH_BASE+1 ///< Unspecified error -#define CSI_ETH_ERROR_BUSY CSI_DRV_ERRNO_ETH_BASE+2 ///< Driver is busy -#define CSI_ETH_ERROR_TIMEOUT CSI_DRV_ERRNO_ETH_BASE+3 ///< Timeout occurred -#define CSI_ETH_ERROR_UNSUPPORTED CSI_DRV_ERRNO_ETH_BASE+4 ///< Operation not supported -#define CSI_ETH_ERROR_PARAMETER CSI_DRV_ERRNO_ETH_BASE+5 ///< Parameter error -#define CSI_ETH_ERROR_SPECIFIC CSI_DRV_ERRNO_ETH_BASE+6 ///< Start of driver specific errors - -/** -\brief General power states -*/ -typedef enum eth_power_state { - CSI_ETH_POWER_OFF, ///< Power off: no operation possible - CSI_ETH_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events - CSI_ETH_POWER_FULL ///< Power on: full operation at maximum performance -} eth_power_state_t; - -/** -\brief Ethernet Media Interface type -*/ -#define CSI_ETH_INTERFACE_MII (0) ///< Media Independent Interface (MII) -#define CSI_ETH_INTERFACE_RMII (1) ///< Reduced Media Independent Interface (RMII) -#define CSI_ETH_INTERFACE_SMII (2) ///< Serial Media Independent Interface (SMII) - -/** -\brief Ethernet link speed -*/ -#define CSI_ETH_SPEED_10M (0) ///< 10 Mbps link speed -#define CSI_ETH_SPEED_100M (1) ///< 100 Mbps link speed -#define CSI_ETH_SPEED_1G (2) ///< 1 Gpbs link speed - -/** -\brief Ethernet duplex mode -*/ -#define CSI_ETH_DUPLEX_HALF (0) ///< Half duplex link -#define CSI_ETH_DUPLEX_FULL (1) ///< Full duplex link - -/** -\brief Ethernet auto-negotiation -*/ -#define CSI_ETH_AUTONEG_DISABLE (0) ///< Disable auto-negotiation -#define CSI_ETH_AUTONEG_ENABLE (1) ///< Enable auto-negotiation - -/** -\brief Ethernet link state -*/ -typedef enum eth_link_state { - ETH_LINK_DOWN, ///< Link is down - ETH_LINK_UP ///< Link is up -} eth_link_state_t; - -/** -\brief Ethernet link information -*/ -typedef volatile struct eth_link_info { - uint32_t speed : 2; ///< Link speed: 0= 10 MBit, 1= 100 MBit, 2= 1 GBit - uint32_t duplex : 1; ///< Duplex mode: 0= Half, 1= Full - uint32_t autoneg : 1; ///< Set the interface to Auto Negotiation mode of transmission parameters - uint32_t loopback : 1; ///< Set the interface into a Loop-back test mode - uint32_t isolation : 1; ///< Set to indicate electrical isolation of PHY interface from MII/RMII interface - uint32_t reserved : 26; -} eth_link_info_t; - -/** -\brief Ethernet MAC Address -*/ -typedef struct eth_mac_addr { - uint8_t b[6]; ///< MAC Address (6 bytes), MSB first -} eth_mac_addr_t; - -#ifdef __cplusplus -} -#endif - -#endif /* CSI_NET_H_ */ - diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/eth_mac.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/eth_mac.h deleted file mode 100644 index bc5757d2..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/eth_mac.h +++ /dev/null @@ -1,377 +0,0 @@ -/** - * Copyright (C) 2016 CSI Project. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef _CSI_ETH_H_ -#define _CSI_ETH_H_ - -#include -#include "drv/eth.h" -#include "drv/eth_phy.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef void *eth_mac_handle_t; - -#define MAX_FRAMELEN 1518 /* (note: maximum ethernet frame length would be 1518) */ - -#define CSI_ETH_MAC_API_VERSION CSI_DRIVER_VERSION_MAJOR_MINOR(2,1) /* API version */ - -#define _CSI_Driver_ETH_MAC_(n) Driver_ETH_MAC##n -#define CSI_Driver_ETH_MAC_(n) _CSI_Driver_ETH_MAC_(n) - -/****** Ethernet MAC Control Codes *****/ - -#define CSI_ETH_MAC_CONFIGURE (0x01) ///< Configure MAC; arg = configuration -#define CSI_ETH_MAC_CONTROL_TX (0x02) ///< Transmitter; arg: 0=disabled (default), 1=enabled -#define CSI_ETH_MAC_CONTROL_RX (0x03) ///< Receiver; arg: 0=disabled (default), 1=enabled -#define CSI_ETH_MAC_FLUSH (0x04) ///< Flush buffer; arg = CSI_ETH_MAC_FLUSH_... -#define CSI_ETH_MAC_SLEEP (0x05) ///< Sleep mode; arg: 1=enter and wait for Magic packet, 0=exit -#define CSI_ETH_MAC_VLAN_FILTER (0x06) ///< VLAN Filter for received frames; arg15..0: VLAN Tag; arg16: optional CSI_ETH_MAC_VLAN_FILTER_ID_ONLY; 0=disabled (default) -#define DRV_ETH_MAC_ADJUST_LINK (0x07) ///< Adjust MAC link state according to phy state; arg: phy handle -#define DRV_ETH_MAC_CONTROL_IRQ (0x08) ///< Interrupt request; arg: 0=disable, 1=enable - -/*----- Ethernet MAC Configuration -----*/ -#define CSI_ETH_MAC_SPEED_Pos 0 -#define CSI_ETH_MAC_SPEED_Msk (3UL << CSI_ETH_MAC_SPEED_Pos) -#define CSI_ETH_MAC_SPEED_10M (CSI_ETH_SPEED_10M << CSI_ETH_MAC_SPEED_Pos) ///< 10 Mbps link speed -#define CSI_ETH_MAC_SPEED_100M (CSI_ETH_SPEED_100M << CSI_ETH_MAC_SPEED_Pos) ///< 100 Mbps link speed -#define CSI_ETH_MAC_SPEED_1G (CSI_ETH_SPEED_1G << CSI_ETH_MAC_SPEED_Pos) ///< 1 Gpbs link speed -#define CSI_ETH_MAC_DUPLEX_Pos 2 -#define CSI_ETH_MAC_DUPLEX_Msk (1UL << CSI_ETH_MAC_DUPLEX_Pos) -#define CSI_ETH_MAC_DUPLEX_HALF (CSI_ETH_DUPLEX_HALF << CSI_ETH_MAC_DUPLEX_Pos) ///< Half duplex link -#define CSI_ETH_MAC_DUPLEX_FULL (CSI_ETH_DUPLEX_FULL << CSI_ETH_MAC_DUPLEX_Pos) ///< Full duplex link -#define CSI_ETH_MAC_LOOPBACK (1UL << 4) ///< Loop-back test mode -#define CSI_ETH_MAC_CHECKSUM_OFFLOAD_RX (1UL << 5) ///< Receiver Checksum offload -#define CSI_ETH_MAC_CHECKSUM_OFFLOAD_TX (1UL << 6) ///< Transmitter Checksum offload -#define CSI_ETH_MAC_ADDRESS_BROADCAST (1UL << 7) ///< Accept frames with Broadcast address -#define CSI_ETH_MAC_ADDRESS_MULTICAST (1UL << 8) ///< Accept frames with any Multicast address -#define CSI_ETH_MAC_ADDRESS_ALL (1UL << 9) ///< Accept frames with any address (Promiscuous Mode) - -/*----- Ethernet MAC Flush Flags -----*/ -#define CSI_ETH_MAC_FLUSH_RX (1UL << 0) ///< Flush Receive buffer -#define CSI_ETH_MAC_FLUSH_TX (1UL << 1) ///< Flush Transmit buffer - -/*----- Ethernet MAC VLAN Filter Flag -----*/ -#define CSI_ETH_MAC_VLAN_FILTER_ID_ONLY (1UL << 16) ///< Compare only the VLAN Identifier (12-bit) - - -/****** Ethernet MAC Frame Transmit Flags *****/ -#define CSI_ETH_MAC_TX_FRAME_FRAGMENT (1UL << 0) ///< Indicate frame fragment -#define CSI_ETH_MAC_TX_FRAME_EVENT (1UL << 1) ///< Generate event when frame is transmitted -#define CSI_ETH_MAC_TX_FRAME_TIMESTAMP (1UL << 2) ///< Capture frame time stamp - - -/****** Ethernet MAC Timer Control Codes *****/ -#define CSI_ETH_MAC_TIMER_GET_TIME (0x01) ///< Get current time -#define CSI_ETH_MAC_TIMER_SET_TIME (0x02) ///< Set new time -#define CSI_ETH_MAC_TIMER_INC_TIME (0x03) ///< Increment current time -#define CSI_ETH_MAC_TIMER_DEC_TIME (0x04) ///< Decrement current time -#define CSI_ETH_MAC_TIMER_SET_ALCSI (0x05) ///< Set alarm time -#define CSI_ETH_MAC_TIMER_ADJUST_CLOCK (0x06) ///< Adjust clock frequency; time->ns: correction factor * 2^31 - - -/** -\brief Ethernet MAC Time -*/ -typedef struct eth_mac_time { - uint32_t ns; ///< Nano seconds - uint32_t sec; ///< Seconds -} eth_mac_time_t; - - -/****** Ethernet MAC Event *****/ -#define CSI_ETH_MAC_EVENT_RX_FRAME (1UL << 0) ///< Frame Received -#define CSI_ETH_MAC_EVENT_TX_FRAME (1UL << 1) ///< Frame Transmitted -#define CSI_ETH_MAC_EVENT_WAKEUP (1UL << 2) ///< Wake-up (on Magic Packet) -#define CSI_ETH_MAC_EVENT_TIMER_ALCSI (1UL << 3) ///< Timer Alarm -#define CSI_ETH_MAC_EVENT_LINK_CHANGE (1UL << 4) ///< Link state - -typedef void (*eth_event_cb_t)(int32_t idx, uint32_t event); ///< Pointer to \ref eth_event_cb_t : Signal Ethernet Event. - -typedef enum { - FRAME_FILTER_RULE_POSITIVE_MATCHING = 0, /*!< Specifies that a filter should match a given pattern */ - FRAME_FILTER_RULE_NEGATIVE_MATCHING = 1, /*!< Specifies that a filter should NOT match a given pattern */ -} frame_filter_rule_t; - -/** -\brief Ethernet MAC Capabilities -*/ -typedef struct eth_capabilities { - uint32_t checksum_offload_rx_ip4 : 1; ///< 1 = IPv4 header checksum verified on receive - uint32_t checksum_offload_rx_ip6 : 1; ///< 1 = IPv6 checksum verification supported on receive - uint32_t checksum_offload_rx_udp : 1; ///< 1 = UDP payload checksum verified on receive - uint32_t checksum_offload_rx_tcp : 1; ///< 1 = TCP payload checksum verified on receive - uint32_t checksum_offload_rx_icmp : 1; ///< 1 = ICMP payload checksum verified on receive - uint32_t checksum_offload_tx_ip4 : 1; ///< 1 = IPv4 header checksum generated on transmit - uint32_t checksum_offload_tx_ip6 : 1; ///< 1 = IPv6 checksum generation supported on transmit - uint32_t checksum_offload_tx_udp : 1; ///< 1 = UDP payload checksum generated on transmit - uint32_t checksum_offload_tx_tcp : 1; ///< 1 = TCP payload checksum generated on transmit - uint32_t checksum_offload_tx_icmp : 1; ///< 1 = ICMP payload checksum generated on transmit - uint32_t media_interface : 2; ///< Ethernet Media Interface type - uint32_t mac_address : 1; ///< 1 = driver provides initial valid MAC address - uint32_t event_rx_frame : 1; ///< 1 = callback event generated - uint32_t event_tx_frame : 1; ///< 1 = callback event generated - uint32_t event_wakeup : 1; ///< 1 = wakeup event generated - uint32_t precision_timer : 1; ///< 1 = Precision Timer supported - uint32_t reserved : 15; ///< Reserved (must be zero) -} eth_capabilities_t; - -/** - * Structure describing a frame filter list item - */ -typedef struct { - uint32_t id; /*!< Unique identifier for a packet filter item */ - frame_filter_rule_t rule; /*!< Filter matches are either POSITIVE or NEGATIVE matching */ - uint16_t offset; /*!< Offset in bytes to start filtering (referenced to the start of the ethernet packet) */ - uint16_t mask_size; /*!< Size of the mask in bytes */ - uint8_t *mask; /*!< Pattern mask bytes to be ANDed with the pattern eg. "\xff00" (must be in network byte order) */ - uint8_t *pattern; /*!< Pattern bytes used to filter eg. "\x0800" (must be in network byte order) */ - bool enabled_status; /*!< When returned from mhd_get_packet_filters, indicates if the filter is enabled */ -} eth_frame_filter_t; - -struct eth_frame_filter_list { - struct eth_frame_filter_list *next; -}; - -typedef struct eth_frame_filter_list eth_frame_filter_list_t; - -typedef struct { - eth_event_cb_t cb_event; - eth_capabilities_t capabilities; -} eth_mac_priv_t; - -/** - \brief Get driver version. - \param[in] handle ethernet handle - \return ethernet version including chip version and driver version -*/ -csi_drv_version_t csi_eth_mac_get_version(eth_mac_handle_t handle); - -/** - \brief Get driver capabilities. - \param[in] idx device id - \return ethernet capabilities -*/ -eth_capabilities_t csi_eth_mac_get_capabilities(int32_t idx); - -/** - \brief This function is used to initialize Ethernet device and related resource, an event callback is registered. It is called when the middleware component like TCPIP starts operation. - \param[in] idx device id - \param[in] cb callback to handle ethernet event - \return return ethernet handle if success - */ -eth_mac_handle_t csi_eth_mac_initialize(int32_t idx, eth_event_cb_t cb_event); - -/** - \brief This function is used to de-initialize Ethernet device. It is called when the middleware component stops operation and releases the software resources used by the interface. - \param[in] handle ethernet handle - \return error code - */ -int32_t csi_eth_mac_uninitialize(eth_mac_handle_t handle); - -/** - \brief Connect phy device to mac device. - \param[in] handle_mac mac handle - \param[in] handle_phy phy handle -*/ -void csi_eth_mac_connect_phy(eth_mac_handle_t handle_mac, eth_phy_handle_t handle_phy); - -/** - \brief Control Ethernet MAC Device Power. - \param[in] handle ethernet handle - \param[in] state Power state - \return error code -*/ -int32_t csi_eth_mac_power_control(eth_mac_handle_t handle, eth_power_state_t state); - -/** - \brief Get Ethernet MAC Address. - \param[in] handle ethernet handle - \param[in] mac Pointer to address - \return error code -*/ -int32_t csi_eth_mac_get_macaddr(eth_mac_handle_t handle, eth_mac_addr_t *mac); - -/** - \brief Set Ethernet MAC Address. - \param[in] handle ethernet handle - \param[in] mac Pointer to address - \return error code -*/ -int32_t csi_eth_mac_set_macaddr(eth_mac_handle_t handle, const eth_mac_addr_t *mac); - -/** - \brief Configure Address Filter. - \param[in] handle ethernet handle - \param[in] addr Pointer to addresses - \param[in] num_addr Number of addresses to configure - \return error code -*/ -int32_t csi_eth_mac_set_addrfilter(eth_mac_handle_t handle, const eth_mac_addr_t *addr, uint32_t num_addr); - -/** - \brief Send Ethernet frame. - \param[in] handle ethernet handle - \param[in] frame Pointer to frame buffer with data to send - \param[in] len Frame buffer length in bytes - \param[in] flags Frame transmit flags (see CSI_ETH_MAC_TX_FRAME_...) - \return error code -*/ -int32_t csi_eth_mac_send_frame(eth_mac_handle_t handle, const uint8_t *frame, uint32_t len, uint32_t flags); - -/** - \brief Read data of received Ethernet frame. - \param[in] handle ethernet handle - \param[in] frame Pointer to frame buffer for data to read into - \param[in] len Frame buffer length in bytes - \return number of data bytes read or execution status - - value >= 0: number of data bytes read - - value < 0: error occurred, value is execution status as defined with execution_status -*/ -int32_t csi_eth_mac_read_frame(eth_mac_handle_t handle, uint8_t *frame, uint32_t len); - -/** - \brief Request data of received Ethernet frame. - csi_eth_mac_request_frame() and csi_eth_mac_release_frame() - must be called in pairs. - \param[in] handle ethernet handle - \param[in] frame Pointer to frame buffer pointer - \return number of data bytes read or execution status - - value >= 0: number of data bytes read - - value < 0: error occurred -*/ -int32_t csi_eth_mac_request_frame(eth_mac_handle_t handle, uint8_t **frame); - -/** - \brief Release current Ethernet frame. - csi_eth_mac_request_frame() and csi_eth_mac_release_frame() - must be called in pairs. - \param[in] handle ethernet handle - \return error code -*/ -int32_t csi_eth_mac_release_frame(eth_mac_handle_t handle); - -/** - \brief Get size of received Ethernet frame. - \param[in] handle ethernet handle - \return number of bytes in received frame -*/ -int32_t csi_eth_mac_get_rx_framesize(eth_mac_handle_t handle); - -/** - \brief Get time of received Ethernet frame. - \param[in] handle ethernet handle - \param[in] time Pointer to time structure for data to read into - \return error code -*/ -int32_t csi_eth_mac_get_rx_frametime(eth_mac_handle_t handle, eth_mac_time_t *time); - -/** - \brief Get time of transmitted Ethernet frame. - \param[in] handle ethernet handle - \param[in] time Pointer to time structure for data to read into - \return error code -*/ -int32_t csi_eth_mac_get_tx_frametime(eth_mac_handle_t handle, eth_mac_time_t *time); - -/** - \brief Control Ethernet Interface. - \param[in] handle ethernet handle - \param[in] control Operation - \param[in] arg Argument of operation (optional) - \return error code -*/ -int32_t csi_eth_mac_control(eth_mac_handle_t handle, uint32_t control, uint32_t arg); - -/** - \brief Control Precision Timer. - \param[in] handle ethernet handle - \param[in] control Operation - \param[in] time Pointer to time structure - \return error code -*/ -int32_t csi_eth_mac_control_time(eth_mac_handle_t handle, uint32_t control, eth_mac_time_t *time); - -/** - \brief Read Ethernet PHY Register through Management Interface. - \param[in] handle ethernet handle - \param[in] phy_addr 5-bit device address - \param[in] reg_addr 5-bit register address - \param[out] data Pointer where the result is written to - \return error code -*/ -int32_t csi_eth_mac_phy_read(eth_mac_handle_t handle, uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); - -/** - \brief Write Ethernet PHY Register through Management Interface. - \param[in] handle ethernet handle - \param[in] phy_addr 5-bit device address - \param[in] reg_addr 5-bit register address - \param[in] data 16-bit data to write - \return error code -*/ -int32_t csi_eth_mac_phy_write(eth_mac_handle_t handle, uint8_t phy_addr, uint8_t reg_addr, uint16_t data); - -/** - \brief Callback function that signals a Ethernet Event. - \param[in] handle ethernet handle - \param[in] event event notification mask - \return none -*/ -void csi_eth_mac_signal_event(eth_mac_handle_t handle, uint32_t event); - -/** - \brief Add Frame Filter Setting with Filter ID. - \param[in] handle ethernet handle - \param[in] filter Pointer to filter setting - \return error code -*/ -int32_t csi_eth_mac_add_framefilter(eth_mac_handle_t handle, const eth_frame_filter_t *filter); - -/** - \brief Remove Frame Filter Setting. - \param[in] handle ethernet handle - \param[in] filter_id Frame Filter ID - \return error code -*/ -int32_t csi_eth_mac_remove_framefilter(eth_mac_handle_t handle, uint32_t filter_id); - -/** - \brief Enable/Disable Specified Frame Filter ID. - \param[in] handle ethernet handle - \param[in] filter_id Frame Filter ID - \param[in] en Enable or disable - \return error code -*/ -int32_t csi_eth_mac_en_framefilter(eth_mac_handle_t handle, uint32_t filter_id, bool en); - -/** - \brief Get frame filter table list. - \param[in] handle ethernet handle - \param[in] list frame filter table list - \param[in] count_out the count of filter setting added - \param[in] max_count max filter setting can be supported - \return error code -*/ -int32_t csi_eth_mac_get_framefilter(eth_mac_handle_t handle, eth_frame_filter_list_t *list, uint32_t *count_out, uint32_t max_count); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/eth_phy.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/eth_phy.h deleted file mode 100644 index 5ef87565..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/eth_phy.h +++ /dev/null @@ -1,124 +0,0 @@ -/** - * Copyright (C) 2016 CSI Project. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef _CSI_ETH_PHY_H_ -#define _CSI_ETH_PHY_H_ - -#include "drv/eth.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef void *eth_phy_handle_t; - -#define CSI_ETH_PHY_API_VERSION CSI_ETH_VERSION_MAJOR_MINOR(2,1) /* API version */ - - -#define _CSI_Driver_ETH_PHY_(n) Driver_ETH_PHY##n -#define CSI_Driver_ETH_PHY_(n) _CSI_Driver_ETH_PHY_(n) - - -/****** Ethernet PHY Mode *****/ -#define CSI_ETH_PHY_SPEED_Pos 0 -#define CSI_ETH_PHY_SPEED_Msk (3UL << CSI_ETH_PHY_SPEED_Pos) -#define CSI_ETH_PHY_SPEED_10M (CSI_ETH_SPEED_10M << CSI_ETH_PHY_SPEED_Pos) ///< 10 Mbps link speed -#define CSI_ETH_PHY_SPEED_100M (CSI_ETH_SPEED_100M << CSI_ETH_PHY_SPEED_Pos) ///< 100 Mbps link speed -#define CSI_ETH_PHY_SPEED_1G (CSI_ETH_SPEED_1G << CSI_ETH_PHY_SPEED_Pos) ///< 1 Gpbs link speed -#define CSI_ETH_PHY_DUPLEX_Pos 2 -#define CSI_ETH_PHY_DUPLEX_Msk (1UL << CSI_ETH_PHY_DUPLEX_Pos) -#define CSI_ETH_PHY_DUPLEX_HALF (CSI_ETH_DUPLEX_HALF << CSI_ETH_PHY_DUPLEX_Pos) ///< Half duplex link -#define CSI_ETH_PHY_DUPLEX_FULL (CSI_ETH_DUPLEX_FULL << CSI_ETH_PHY_DUPLEX_Pos) ///< Full duplex link -#define CSI_ETH_PHY_AUTO_NEGOTIATE (1UL << 3) ///< Auto Negotiation mode -#define CSI_ETH_PHY_LOOPBACK (1UL << 4) ///< Loop-back test mode -#define CSI_ETH_PHY_ISOLATE (1UL << 5) ///< Isolate PHY from MII/RMII interface - -typedef int32_t (*csi_eth_phy_read_t)(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); ///< Read Ethernet PHY Register. -typedef int32_t (*csi_eth_phy_write_t)(uint8_t phy_addr, uint8_t reg_addr, uint16_t data); ///< Write Ethernet PHY Register. - -typedef struct { - csi_eth_phy_read_t phy_read; - csi_eth_phy_write_t phy_write; - eth_link_info_t link_info; -} eth_phy_priv_t; - -// Function documentation -/** - \brief Get driver version. - \param[in] handle ethernet phy handle - \return driver version -*/ -csi_drv_version_t csi_eth_phy_get_version(eth_phy_handle_t handle); - -/** - \brief Initialize Ethernet PHY Device. - \param[in] fn_read - \param[in] fn_write - \return ethernet phy handle -*/ -eth_phy_handle_t csi_eth_phy_initialize(csi_eth_phy_read_t fn_read, csi_eth_phy_write_t fn_write); - -/** - \brief De-initialize Ethernet PHY Device. - \param[in] handle ethernet phy handle - \return error code -*/ -int32_t csi_eth_phy_uninitialize(eth_phy_handle_t handle); - -/** - \brief Control Ethernet PHY Device Power. - \param[in] handle ethernet phy handle - \param[in] state Power state - \return error code -*/ -int32_t csi_eth_phy_power_control(eth_phy_handle_t handle, eth_power_state_t state); - -/** - \brief Set Ethernet Media Interface. - \param[in] handle ethernet phy handle - \param[in] interface Media Interface type - \return error code -*/ -int32_t csi_eth_phy_set_interface(eth_phy_handle_t handle, uint32_t interface); - -/** - \brief Set Ethernet PHY Device Operation mode. - \param[in] handle ethernet phy handle - \param[in] mode Operation Mode - \return error code -*/ -int32_t csi_eth_phy_set_mode(eth_phy_handle_t handle, uint32_t mode); - -/** - \brief Get Ethernet PHY Device Link state. - \param[in] handle ethernet phy handle - \return current link status \ref eth_link_state_t -*/ -eth_link_state_t csi_eth_phy_get_linkstate(eth_phy_handle_t handle); - -/** - \brief Get Ethernet PHY Device Link information. - \param[in] handle ethernet phy handle - \return current link parameters \ref eth_link_info_t -*/ -eth_link_info_t csi_eth_phy_get_linkinfo(eth_phy_handle_t handle); - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/fft.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/fft.h deleted file mode 100755 index a3cd312b..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/fft.h +++ /dev/null @@ -1,87 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/fft.h - * @brief Header File for FFT Driver - * @version V1.0 - * @date 11. Nov 2020 - * @model fft - ******************************************************************************/ - -#ifndef _DRV_FFT_H_ -#define _DRV_FFT_H_ - -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ///< 512-point FFT - CSKY_MCA_FFT_LEN_512 = 0x1, - ///< 256-point FFT - CSKY_MCA_FFT_LEN_256 = 0x2, - ///< 128-point FFT - CSKY_MCA_FFT_LEN_128 = 0x4, - ///< 64-point FFT - CSKY_MCA_FFT_LEN_64 = 0x8, - ///< 32-point FFT - CSKY_MCA_FFT_LEN_32 = 0x10, - ///< 16-point FFT - CSKY_MCA_FFT_LEN_16 = 0x20, -} csky_mca_fft_len_t; - -/* 8-bit fixed-point numeric type in user-defined format */ -typedef int8_t fxp8_t; - -/* 16-bit fixed-point numeric type in user-defined format */ -typedef int16_t fxp16_t; - -/* 24-bit fixed-point numeric type in user-defined format */ -typedef int32_t fxp24_t; - -/* 32-bit fixed-point numeric type in user-defined format */ -typedef int32_t fxp32_t; - -/* 64-bit fixed-point numeric type in user-defined format */ -typedef int64_t fxp64_t; - -/* 8-bit fixed-point numeric type in 1.0.7 format */ -typedef fxp8_t q7_t; - -/* 16-bit fixed-point numeric type in 1.0.15 format */ -typedef fxp16_t q15_t; - -/* 32-bit fixed-point numeric type in 1.15.16 format */ -typedef fxp32_t q16_t; - -void csky_mca_rfft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, size_t input_size, fxp32_t *output); -void csky_mca_cfft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, fxp32_t *output); -void csky_mca_rifft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, fxp32_t *output); -void csky_mca_cifft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, fxp32_t *output); -void csky_mca_power_spectrum_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, size_t input_size, fxp64_t *output); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_FFT_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/gpio_pin.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/gpio_pin.h deleted file mode 100755 index 1cb81fc3..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/gpio_pin.h +++ /dev/null @@ -1,144 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/gpio_pin.h - * @brief Header File for GPIO PIN Driver - * @version v1.0 - * @date 2020-06-28 - * @note Only one of gpio or gpio_pin interface can be selected - ******************************************************************************/ - -#ifndef _DRV_GPIO_PIN_H_ -#define _DRV_GPIO_PIN_H_ - -#include -#include -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \struct csi_gpio_pin_t - * \brief GPIO PIN control block - */ - -typedef struct csi_gpio_pin csi_gpio_pin_t; -struct csi_gpio_pin { - csi_gpio_t *gpio; - uint32_t pin_idx; - void (*callback)(csi_gpio_pin_t *pin, void *arg); - void *arg; -}; - -/** - \brief Initialize GPIO pin handle - \param[in] pin GPIO pin handle - \param[in] pin_name GPIO pin name - \return Error code -*/ -csi_error_t csi_gpio_pin_init(csi_gpio_pin_t *pin, pin_name_t pin_name); - -/** - \brief De-initialize GPIO pin - \param[in] pin GPIO pin handle - \return None -*/ -void csi_gpio_pin_uninit(csi_gpio_pin_t *pin); - -/** - \brief Attach the interrupt callback to the GPIO pin - \param[in] pin GPIO pin handle - \param[in] callback Callback function - \param[in] arg User param passed to callback - \return Error code -*/ -csi_error_t csi_gpio_pin_attach_callback(csi_gpio_pin_t *pin, void *callback, void *arg); - -/** - \brief Config pin direction - \param[in] pin GPIO pin handle - \param[in] dir \ref csi_gpio_dir_t - \return Error code -*/ -csi_error_t csi_gpio_pin_dir(csi_gpio_pin_t *pin, csi_gpio_dir_t dir); - -/** - \brief Config pin mode - \param[in] pin GPIO pin handle - \param[in] mode \ref csi_gpio_mode_t - \return Error code -*/ -csi_error_t csi_gpio_pin_mode(csi_gpio_pin_t *pin, csi_gpio_mode_t mode); - -/** - \brief Config pin irq params - \param[in] pin GPIO pin handle - \param[in] mode Interrupt trigger mode \ref csi_gpio_irq_mode_t - \return Error code -*/ -csi_error_t csi_gpio_pin_irq_mode(csi_gpio_pin_t *pin, csi_gpio_irq_mode_t mode); - -/** - \brief Enable or disable gpio pin interrupt - \param[in] pin GPIO pin handle - \param[in] enable 0:disable 1:enable - \return Error code -*/ -csi_error_t csi_gpio_pin_irq_enable(csi_gpio_pin_t *pin, bool enable); - -/** - \brief Set debounce of pin when pin configed as input - \param[in] pin GPIO pin handle - \param[in] enbale 0: disable 1:enable - \return Error code -*/ -csi_error_t csi_gpio_pin_debounce(csi_gpio_pin_t *pin, bool enable); - -/** - \brief Set one or zero to specified pin - \param[in] pin GPIO pin handle - \param[in] value Value to be set \ref csi_gpio_pin_state_t - \return None -*/ -void csi_gpio_pin_write(csi_gpio_pin_t *pin, csi_gpio_pin_state_t value); - -/** - \brief Toggle output pin value,ex.if previous value is 1, then output 0 - \param[in] pin GPIO pin handle - \return None -*/ -void csi_gpio_pin_toggle(csi_gpio_pin_t *pin); - -/** - \brief Get the value of specified GPIO pin - \param[in] pin GPIO port handle - \return gpio pin state, \ref csi_gpio_pin_state_t -*/ -csi_gpio_pin_state_t csi_gpio_pin_read(csi_gpio_pin_t *pin); - -#ifdef __cplusplus -} -#endif - -#endif /* _GPIO_PIN_H_*/ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/hmac.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/hmac.h deleted file mode 100644 index 1033306e..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/hmac.h +++ /dev/null @@ -1,122 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -/****************************************************************************** - * @file drv/hmac.h - * @brief Header File for HMAC - * @version V1.0 - * @date 27. Apri 2023 - * @model hmac - ******************************************************************************/ -#ifndef _DRV_HMAC_H_ -#define _DRV_HMAC_H_ - -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/****** HMAC Event ******/ -typedef enum { - HMAC_EVENT_COMPLETE = 0U, /* Calculate completed */ - HMAC_EVENT_ERROR /* Calculate error */ -} csi_hmac_event_t; - -/****** HMAC Context ******/ -typedef struct { - csi_sha_mode_t mode; /* SHA mode */ - uint32_t total[2]; /* Number of bytes processed */ - uint8_t buffer[128]; /* Data block being processed */ -} csi_hmac_context_t; - -/****** HMAC Ctrl ******/ -typedef struct csi_hmac { - csi_dev_t dev; - void *priv; -}csi_hmac_t; - -/** - \brief Initialize MAC Interface. Initializes the resources needed for the MAC interface - \param[in] mac operate handle. - \param[in] idx index of mac - \return error code \ref csi_error_t -*/ -csi_error_t csi_hmac_init(csi_hmac_t *mac, uint32_t idx); - -/** - \brief De-initialize MAC Interface. stops operation and releases the software resources used by the interface - \param[in] mac mac handle to operate. - \return none -*/ -void csi_hmac_uninit(csi_hmac_t *mac); - -/** - \brief MAC set key function. - \param[in] mac mac handle to operate. - \param[in] key Pointer to the mac key. - \param[in] key_len Length of key. - \return error code \ref csi_error_t -*/ -csi_error_t csi_hmac_set_key(csi_hmac_t *mac, uint8_t *key, uint32_t key_len); - -/** - \brief MAC start operation function. - \param[in] mac mac handle to operate. - \param[in] context mac context pointer. - \param[in] mode sc_sha_mode_t. - \return error code \ref csi_error_t -*/ -csi_error_t csi_hmac_start(csi_hmac_t *mac, csi_hmac_context_t *context, csi_sha_mode_t mode); - -/** - \brief MAC start operation function. - \param[in] mac mac handle to operate. - \param[in] msg Pointer to the mac input message. - \param[in] msg_len Length of msg. - \return error code \ref csi_error_t -*/ -csi_error_t csi_hmac_update(csi_hmac_t *mac, csi_hmac_context_t *context, uint8_t *msg, uint32_t msg_len); - -/** - \brief MAC start operation function. - \param[in] mac mac handle to operate. - \param[out] out mac buffer, malloc by caller. - \param[out] out_len out mac length, - \return error code \ref csi_error_t -*/ -csi_error_t csi_hmac_finish(csi_hmac_t *mac, csi_hmac_context_t *context, uint8_t *out, uint32_t *out_len); - -/** - \brief MAC cacl operation function. - \param[in] mac mac handle to operate. - \param[in] mode sc_sha_mode_t. - \param[in] msg Pointer to the mac input message. - \param[in] msg_len Length of msg. - \param[out] out mac buffer, malloc by caller. - \param[out] out_len out mac length, - \return error code \ref csi_error_t -*/ -csi_error_t csi_hmac_calc(csi_hmac_t *mac, csi_sha_mode_t mode, uint8_t *msg, - uint32_t msg_len, uint8_t *out, uint32_t *out_len); -#ifdef __cplusplus -} -#endif - -#endif /* _SC_MAC_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/i2s.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/i2s.h deleted file mode 100755 index f783d21d..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/i2s.h +++ /dev/null @@ -1,397 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/i2s.h - * @brief header file for i2s driver - * @version V1.0 - * @date 16. Mar 2020 - * @model i2s - ******************************************************************************/ - -#ifndef _DRV_I2S_H_ -#define _DRV_I2S_H_ - -#include -#include -#include -#include -#include "drv/ringbuf.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - I2S_MODE_MASTER, ///< I2s transmitter master mode - I2S_MODE_SLAVE, ///< I2s transmitter slave mode -} csi_i2s_mode_t; - -typedef enum { - I2S_PROTOCOL_I2S, ///< I2S protocol - I2S_PROTOCOL_MSB_JUSTIFIED, ///< MSB (left) justified protocol - I2S_PROTOCOL_LSB_JUSTIFIED, ///< LSB (right) justified protocol - I2S_PROTOCOL_PCM, ///< PCM protocol -} csi_i2s_protocol_t; - -typedef enum { - I2S_LEFT_POLARITY_LOW, ///< Low level represents the left channel - I2S_LEFT_POLARITY_HIGH, ///< High level represents the left channel -} csi_i2s_ws_left_polarity_t; - -typedef enum { - I2S_SAMPLE_RATE_8000 = 8000U, ///< I2S sample rate is 8000 - I2S_SAMPLE_RATE_11025 = 11025U, - I2S_SAMPLE_RATE_12000 = 12000U, - I2S_SAMPLE_RATE_16000 = 16000U, - I2S_SAMPLE_RATE_22050 = 22050U, - I2S_SAMPLE_RATE_24000 = 24000U, - I2S_SAMPLE_RATE_32000 = 32000U, - I2S_SAMPLE_RATE_44100 = 44100U, - I2S_SAMPLE_RATE_48000 = 48000U, - I2S_SAMPLE_RATE_96000 = 96000U, - I2S_SAMPLE_RATE_192000 = 192000U, - I2S_SAMPLE_RATE_256000 = 256000U, -} csi_i2s_sample_rate_t; - -typedef enum { - I2S_SAMPLE_WIDTH_16BIT = 16U, ///< I2S sample width is 16bit - I2S_SAMPLE_WIDTH_24BIT = 24U, - I2S_SAMPLE_WIDTH_32BIT = 32U, -} csi_i2s_sample_width_t; - -typedef enum { - I2S_SCLK_16FS = 16U, ///< SCLK frequency is 16 times that of I2S sample rate - I2S_SCLK_32FS = 32U, - I2S_SCLK_48FS = 48U, - I2S_SCLK_64FS = 64U, -} csi_i2s_sclk_freq_t; - -typedef enum { - I2S_MCLK_256FS = 256U, ///< MCLK frequency is 256 times that of I2S sample rate - I2S_MCLK_384FS = 384U, -} csi_i2s_mclk_freq_t; - -typedef struct { - csi_i2s_mode_t mode; ///< I2S work mode - csi_i2s_protocol_t protocol; ///< Protocols used by I2S - csi_i2s_ws_left_polarity_t polarity; ///< left channel polarity - csi_i2s_sample_rate_t rate; ///< I2S sample rate - csi_i2s_sample_width_t width; ///< I2S sample width - csi_i2s_sclk_freq_t sclk_nfs; ///< SCLK frequency is N times that of I2S sample rate - csi_i2s_mclk_freq_t mclk_nfs; ///< MCLK frequency is N times that of I2S sample rate -} csi_i2s_format_t; - -typedef enum { - I2S_LEFT_CHANNEL, - I2S_RIGHT_CHANNEL, - I2S_LEFT_RIGHT_CHANNEL, -} csi_i2s_sound_channel_t; - -typedef enum { - I2S_EVENT_SEND_COMPLETE, - I2S_EVENT_RECEIVE_COMPLETE, - I2S_EVENT_TX_BUFFER_EMPTY, - I2S_EVENT_RX_BUFFER_FULL, - I2S_EVENT_ERROR_OVERFLOW, - I2S_EVENT_ERROR_UNDERFLOW, - I2S_EVENT_ERROR, -} csi_i2s_event_t; - -typedef struct csi_i2s csi_i2s_t; - -struct csi_i2s { - csi_dev_t dev; ///< I2S hw-device info - void (*callback)(csi_i2s_t *i2s, csi_i2s_event_t event, void *arg); ///< I2S event callback for user - void *arg; ///< user private param passed to user callback - csi_ringbuf_t *tx_buf; ///< I2S send buffer - csi_ringbuf_t *rx_buf; ///< I2S receive buffer - csi_dma_ch_t *tx_dma; ///< send dma channel handle - csi_dma_ch_t *rx_dma; ///< receive dma channel handle - uint32_t tx_period; ///< I2S send period num data will callback - uint32_t rx_period; ///< I2S receive period num data will callback - csi_state_t state; ///< I2S communication state - void *priv; -}; - -/** - \brief Init i2s - \param[in] i2s I2s handle to operate - \param[in] idx I2s interface idx - \return error code \ref csi_error_t -*/ -csi_error_t csi_i2s_init(csi_i2s_t *i2s, uint32_t idx); - -/** - \brief Uninit i2s - \param[in] i2s I2s handle to operate - \return none -*/ -void csi_i2s_uninit(csi_i2s_t *i2s); - -/** - \brief Enable i2s - \param[in] i2s I2s handle to operate - \param[in] en True enable, False disable - \return None -*/ -void csi_i2s_enable(csi_i2s_t *i2s, bool enable); - -/** - \brief I2s config format - \param[in] i2s I2s handle to operate - \param[in] format I2s config param \ref csi_i2s_format_t - \return error code \ref csi_error_t -*/ -csi_error_t csi_i2s_format(csi_i2s_t *i2s, csi_i2s_format_t *format); - -/** - \brief Set the i2s tx mono - \param[in] i2s I2s handle to operate - \param[in] ch Mono channel selection - \return error code \ref csi_error_t -*/ -csi_error_t csi_i2s_tx_select_sound_channel(csi_i2s_t *i2s, csi_i2s_sound_channel_t ch); - -/** - \brief Set the i2s rx mono - \param[in] i2s I2s handle to operate - \param[in] ch Mono channel selection - \return error code \ref csi_error_t -*/ -csi_error_t csi_i2s_rx_select_sound_channel(csi_i2s_t *i2s, csi_i2s_sound_channel_t ch); - -/** - \brief Link DMA channel to i2s device - \param[in] i2s I2s handle to operate - \param[in] rx_dma The DMA channel for receive, when it is NULL means to unused dma - \return error code \ref csi_error_t -*/ -csi_error_t csi_i2s_rx_link_dma(csi_i2s_t *i2s, csi_dma_ch_t *rx_dma); - -/** - \brief Link DMA channel to i2s device - \param[in] i2s I2s handle to operate - \param[in] tx_dma The DMA channel for send, when it is NULL means to unused dma - \return error code \ref csi_error_t -*/ -csi_error_t csi_i2s_tx_link_dma(csi_i2s_t *i2s, csi_dma_ch_t *tx_dma); - -/** - \brief I2s rx buffer config - \param[in] i2s I2s handle to operate - \param[in] buffer I2s rx buffer - \return None -*/ -void csi_i2s_rx_set_buffer(csi_i2s_t *i2s, csi_ringbuf_t *buffer); - -/** - \brief I2s tx buffer config - \param[in] i2s I2s handle to operate - \param[in] buffer I2s tx buffer - \return None -*/ -void csi_i2s_tx_set_buffer(csi_i2s_t *i2s, csi_ringbuf_t *buffer); - -/** - \brief I2s rx set period.The value of period is to report a receive completion event - after each period value data is received - \param[in] i2s I2s handle to operate - \param[in] period I2s rx period - \return error code \ref csi_error_t -*/ -csi_error_t csi_i2s_rx_set_period(csi_i2s_t *i2s, uint32_t period); - -/** - \brief I2s tx set period.The value of period is to report a receive completion event - after each period value data is send - \param[in] i2s I2s handle to operate - \param[in] period I2s tx period - \return error code \ref csi_error_t -*/ -csi_error_t csi_i2s_tx_set_period(csi_i2s_t *i2s, uint32_t period); - -/** - \brief Get rx csi_ringbuf buffer free space - \param[in] i2s I2s handle to operate - \return Buffer free space (bytes) -*/ -uint32_t csi_i2s_rx_buffer_avail(csi_i2s_t *i2s); - -/** - \brief Get rx csi_ringbuf buffer used space - \param[in] i2s I2s handle to operate - \return Buffer used space (bytes) -*/ -uint32_t csi_i2s_rx_buffer_remain(csi_i2s_t *i2s); - -/** - \brief Reset the rx csi_ringbuf, discard all data in the buffer - \param[in] i2s I2s handle to operate - \return error code \ref csi_error_t -*/ -csi_error_t csi_i2s_rx_buffer_reset(csi_i2s_t *i2s); - -/** - \brief Get tx csi_ringbuf buffer free space - \param[in] i2s I2s handle to operate - \return Buffer free space (bytes) -*/ -uint32_t csi_i2s_tx_buffer_avail(csi_i2s_t *i2s); - -/** - \brief Get tx csi_ringbuf buffer used space - \param[in] i2s I2s handle to operate - \return Buffer used space (bytes) -*/ -uint32_t csi_i2s_tx_buffer_remain(csi_i2s_t *i2s); - -/** - \brief Reset the tx csi_ringbuf, discard all data in the buffer - \param[in] i2s Handle to operate - \return error code \ref csi_error_t -*/ -csi_error_t csi_i2s_tx_buffer_reset(csi_i2s_t *i2s); - -/** - \brief Send an amount of data to buffer in blocking mode - \param[in] i2s Operate handle - \param[in] data Pointer to send data buffer - \param[in] size Send data size - \return The num of data witch is send successful -*/ -int32_t csi_i2s_send(csi_i2s_t *i2s, const void *data, uint32_t size); - -/** - \brief Receive an amount of data to buffer in blocking mode - \param[in] i2s Operate handle - \param[out] data Pointer to receive data buffer - \param[in] size Receive data size - \return The size of data receive successfully -*/ -int32_t csi_i2s_receive(csi_i2s_t *i2s, void *data, uint32_t size); - -/** - \brief Write data to the buffer - With asynchronous sending - The data is first written to the buffer and then output through the i2s interface - Return value is the number of data that was successfully written to the buffer - \param[in] i2s Operate handle - \param[in] data Pointer to send data buffer - \param[in] size Send data size - \return The data size that write to buffer -*/ -uint32_t csi_i2s_send_async(csi_i2s_t *i2s, const void *data, uint32_t size); - -/** - \brief Read data from the buffer - Using asynchronous receive, i2s writes the received data to the buffer - This function reads data from the buffer, returns the number of successful reads - Returns 0 if there is no data in the buffer - \param[in] i2s Operate handle - \param[out] data Pointer to receive data buffer - \param[in] size Receive data size - \return The size of data read successfully -*/ -uint32_t csi_i2s_receive_async(csi_i2s_t *i2s, void *data, uint32_t size); - -/** - \brief Start i2s pause asynchronous send - \param[in] i2s Operate handle - \return error code \ref csi_error_t -*/ -csi_error_t csi_i2s_send_pause(csi_i2s_t *i2s); - -/** - \brief Start i2s resume asynchronous send - \param[in] i2s Operate handle - \return error code \ref csi_error_t -*/ -csi_error_t csi_i2s_send_resume(csi_i2s_t *i2s); - -/** - \brief Start i2s asynchronous send - \param[in] i2s Operate handle - \return error code \ref csi_error_t -*/ -csi_error_t csi_i2s_send_start(csi_i2s_t *i2s); - -/** - \brief Start i2s asynchronous receive - \param[in] i2s Operate handle - \return error code \ref csi_error_t -*/ -csi_error_t csi_i2s_receive_start(csi_i2s_t *i2s); - -/** - \brief Stop i2s asynchronous send - \param[in] i2s Operate handle - \return None -*/ -void csi_i2s_send_stop(csi_i2s_t *i2s); - -/** - \brief Stop i2s asynchronous receive - \param[in] i2s Operate handle - \return None -*/ -void csi_i2s_receive_stop(csi_i2s_t *i2s); - -/** - \brief Attach the callback handler to i2s - \param[in] i2s Operate handle - \param[in] cb Callback function - \param[in] arg User private param - \return error code \ref csi_error_t -*/ -csi_error_t csi_i2s_attach_callback(csi_i2s_t *i2s, void *callback, void *arg); - -/** - \brief Detach the callback handler - \param[in] i2s Operate handle - \return None -*/ -void csi_i2s_detach_callback(csi_i2s_t *i2s); - -/** - \brief Get i2s status - \param[in] i2s I2s handle to operate - \param[out] state I2s state - \return error code \ref csi_error_t -*/ -csi_error_t csi_i2s_get_state(csi_i2s_t *i2s, csi_state_t *state); - -/** - \brief Enable i2s power manage - \param[in] i2s I2s handle to operate - \return error code \ref csi_error_t -*/ -csi_error_t csi_i2s_enable_pm(csi_i2s_t *i2s); - -/** - \brief Disable i2s power manage - \param[in] i2s I2s handle to operate - \return None -*/ -void csi_i2s_disable_pm(csi_i2s_t *i2s); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_I2S_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/iic.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/iic.h deleted file mode 100755 index ee46ea22..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/iic.h +++ /dev/null @@ -1,338 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file iic.h - * @brief header file for iic driver - * @version V1.0 - * @date 08. Apr 2020 - * @model iic - ******************************************************************************/ - -#ifndef _DRV_IIC_H_ -#define _DRV_IIC_H_ - -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \enum csi_iic_mode_t - \brief iic work in master/slave mode - */ -typedef enum { - IIC_MODE_MASTER = 0U, ///< IIC master - IIC_MODE_SLAVE ///< IIC slave -} csi_iic_mode_t; - -/** - \enum csi_iic_speed_t - \brief iic speed mode - */ -typedef enum { - IIC_BUS_SPEED_STANDARD = 0U, ///< Standard Speed (<=100kHz) - IIC_BUS_SPEED_FAST, ///< Fast Speed (<=400kHz) - IIC_BUS_SPEED_FAST_PLUS, ///< Fast plus Speed (<= 1MHz) - IIC_BUS_SPEED_HIGH ///< High Speed (<=3.4MHz) -} csi_iic_speed_t; - -/** - \enum csi_iic_address_mode_t - \brief iic address mode - */ -typedef enum { - IIC_ADDRESS_7BIT = 0U, ///< 7-bit address mode - IIC_ADDRESS_10BIT ///< 10-bit address mode -} csi_iic_addr_mode_t; - -/** - \enum csi_iic_mem_addr_size_t - \brief iic memory address size - */ -typedef enum { - IIC_MEM_ADDR_SIZE_8BIT = 0U, ///< IIC e2prom 8bit address mode - IIC_MEM_ADDR_SIZE_16BIT ///< IIC e2prom 16bit address mode -} csi_iic_mem_addr_size_t; - -/** - \enum csi_iic_event_t - \brief iic event signaled by iic driver - */ -typedef enum { - IIC_EVENT_SEND_COMPLETE = 0U, ///< Master/slave Send finished - IIC_EVENT_RECEIVE_COMPLETE, ///< Master/slave Receive finished - IIC_EVENT_ERROR_OVERFLOW, ///< Master/slave fifo overflow error - IIC_EVENT_ERROR_UNDERFLOW, ///< Master/slave fifo underflow error - IIC_EVENT_ERROR ///< The receive buffer was completely filled to FIFO and more data arrived. That data is lost -} csi_iic_event_t; - -/** - \struct csi_iic_t - \brief iic ctrl block - */ -typedef struct csi_iic csi_iic_t; -struct csi_iic { - csi_dev_t dev; ///< IIC hw-device info - void (*callback)(csi_iic_t *iic, csi_iic_event_t event, void *arg); ///< IIC event callback for user - void *arg; ///< User private param passed to user callback - uint8_t *data; ///< IIC transfer-data buffer - uint32_t size; ///< IIC transfer-data size - csi_iic_mode_t mode; ///< IIC mode - csi_dma_ch_t *tx_dma; ///< Send dma channel handle - csi_dma_ch_t *rx_dma; ///< Receive dma channel handle - void *send; ///< Send function pointer asynchronously - void *receive; ///< Receive function pointer asynchronously - csi_state_t state; ///< IIC current state - void *priv; -}; - -typedef csi_error_t (*csi_iic_master_send_async_t)(csi_iic_t *iic, uint32_t devaddr, const void *data, uint32_t size); -typedef csi_error_t (*csi_iic_master_receive_async_t)(csi_iic_t *iic, uint32_t devaddr, void *data, uint32_t size); -typedef csi_error_t (*csi_iic_slave_send_async_t)(csi_iic_t *iic, const void *data, uint32_t size); -typedef csi_error_t (*csi_iic_slave_receive_async_t)(csi_iic_t *iic, void *data, uint32_t size); - -/** - \brief Init iic ctrl block - Initializes the resources needed for the iic instance - \param[in] iic Handle of iic instance - \param[in] idx Index of instance - \return error code \ref csi_error_t -*/ -csi_error_t csi_iic_init(csi_iic_t *iic, uint32_t idx); - -/** - \brief Uninit iic ctrl block - Stops operation and releases the software resources used by the instance - \param[in] iic Handle of iic instance - \return None -*/ -void csi_iic_uninit(csi_iic_t *iic); - -/** - \brief Config iic master or slave mode - \param[in] iic Handle of iic instance - \param[in] mode iic mode \ref csi_iic_mode_t - \return error code \ref csi_error_t -*/ -csi_error_t csi_iic_mode(csi_iic_t *iic, csi_iic_mode_t mode); - -/** - \brief Config iic addr mode - \param[in] iic Handle of iic instance - \param[in] addr_mode iic addr mode \ref csi_iic_addr_mode_t - \return error code \ref csi_error_t -*/ -csi_error_t csi_iic_addr_mode(csi_iic_t *iic, csi_iic_addr_mode_t addr_mode); - -/** - \brief Config iic speed - \param[in] iic Handle of iic instance - \param[in] speed iic speed mode \ref csi_iic_speed_t - \return error code \ref csi_error_t -*/ -csi_error_t csi_iic_speed(csi_iic_t *iic, csi_iic_speed_t speed); - -/** - \brief Config iic own addr - \param[in] iic Handle of iic instance - \param[in] own_addr iic set own addr at slave mode - \return error code \ref csi_error_t -*/ -csi_error_t csi_iic_own_addr(csi_iic_t *iic, uint32_t own_addr); - -/** - \brief Start sending data as iic master - This function is blocking - \param[in] iic Handle of iic instance - \param[in] devaddr Addrress of slave device - \param[in] data Pointer to send data buffer - \param[in] size Size of data items to send - \param[in] timout Unit of time delay(ms) - \return The amount of real data sent or error code -*/ -int32_t csi_iic_master_send(csi_iic_t *iic, uint32_t devaddr, const void *data, uint32_t size, uint32_t timeout); - -/** - \brief Start receiving data as iic master - This function is blocking - \param[in] iic Handle to operate - \param[in] devaddr iic addrress of slave device - \param[out] data Pointer to buffer for data to receive from iic receiver - \param[in] size Size of data items to receive - \param[in] timeout Unit of time delay(ms) - \return The amount of real data received or error code -*/ -int32_t csi_iic_master_receive(csi_iic_t *iic, uint32_t devaddr, void *data, uint32_t size, uint32_t timeout); - -/** - \brief Start sending data as iic master - This function is non-blocking,\ref csi_iic_event_t is signaled when transfer completes or error happens - \param[in] iic Handle to operate - \param[in] devaddr iic addrress of slave device - \param[in] data Pointer to send data buffer - \param[in] size Size of data items to send - \return error code \ref csi_error_t -*/ -csi_error_t csi_iic_master_send_async(csi_iic_t *iic, uint32_t devaddr, const void *data, uint32_t size); - -/** - \brief Start receiving data as iic master. - This function is non-blocking.\ref csi_iic_event_t is signaled when transfer completes or error happens - \param[in] iic Handle to operate - \param[in] devaddr iic addrress of slave device - \param[out] data Pointer to buffer for data to receive from iic receiver - \param[in] size Size of data items to receive - \return error code \ref csi_error_t -*/ -csi_error_t csi_iic_master_receive_async(csi_iic_t *iic, uint32_t devaddr, void *data, uint32_t size); - -/** - \brief Start sending data as iic master - This function is blocking - \param[in] iic Handle of iic instance - \param[in] devaddr Addrress of slave device - \param[in] memaddr Internal addr of device - \param[in] memaddr_size Internal addr mode of device - \param[in] data Pointer to send data buffer - \param[in] size Size of data items to send - \param[in] timout Unit of time delay(ms) - \return The amount of real data sent or error code -*/ -int32_t csi_iic_mem_send(csi_iic_t *iic, uint32_t devaddr, uint16_t memaddr, csi_iic_mem_addr_size_t memaddr_size, const void *data, uint32_t size, uint32_t timeout); - -/** - \brief Start receiving data as iic master - This function is blocking - \param[in] iic Handle to operate - \param[in] devaddr iic addrress of slave device - \param[in] memaddr Internal addr of device - \param[in] memaddr_mode Internal addr mode of device - \param[out] data Pointer to buffer for data to receive from eeprom device - \param[in] size Size of data items to receive - \param[in] timeout Unit of time delay(ms) - \return The amount of real data received or error code -*/ -int32_t csi_iic_mem_receive(csi_iic_t *iic, uint32_t devaddr, uint16_t memaddr, csi_iic_mem_addr_size_t memaddr_size, void *data, uint32_t size, uint32_t timeout); - -/** - \brief Start sending data as iic slave - This function is blocking - \param[in] iic Handle to operate - \param[in] data Pointer to buffer with data to send to iic master - \param[in] size Size of data items to send - \param[in] timeout Unit of time delay(ms) - \return The amount of real data sent or error code -*/ -int32_t csi_iic_slave_send(csi_iic_t *iic, const void *data, uint32_t size, uint32_t timeout); - -/** - \brief Start receiving data as iic slave - This function is blocking - \param[in] iic Handle to operate - \param[out] data Pointer to buffer for data to receive from iic master - \param[in] size Size of data items to receive - \param[in] timeout Unit of time delay(ms) - \return The amount of real data received or error code -*/ -int32_t csi_iic_slave_receive(csi_iic_t *iic, void *data, uint32_t size, uint32_t timeout); - -/** - \brief Start sending data as iic slave - This function is non-blocking,\ref csi_iic_event_t is signaled when transfer completes or error happens - \param[in] iic Handle to operate - \param[in] data Pointer to buffer with data to send to iic master - \param[in] size Size of data items to send - \return error code \ref csi_error_t -*/ -csi_error_t csi_iic_slave_send_async(csi_iic_t *iic, const void *data, uint32_t size); - -/** - \brief Start receiving data as iic slave - This function is non-blocking,\ref csi_iic_event_t is signaled when transfer completes or error happens - \param[in] handle iic handle to operate - \param[out] data Pointer to buffer for data to receive from iic master - \param[in] size Size of data items to receive - \return error code \ref csi_error_t -*/ -csi_error_t csi_iic_slave_receive_async(csi_iic_t *iic, void *data, uint32_t size); - -/** - \brief Attach callback to the iic - \param[in] iic iic handle to operate - \param[in] cb Event callback function \ref csi_iic_callback_t - \param[in] arg User private param for event callback - \return error code \ref csi_error_t -*/ -csi_error_t csi_iic_attach_callback(csi_iic_t *iic, void *callback, void *arg); - -/** - \brief Detach callback from the iic - \param[in] iic iic handle to operate - \return None -*/ -void csi_iic_detach_callback(csi_iic_t *iic); - -/** - \brief Config iic stop to generate - \param[in] iic iic handle to operate - \param[in] enable Transfer operation is pending - stop condition will not be generated - \return error code \ref csi_error_t -*/ -csi_error_t csi_iic_xfer_pending(csi_iic_t *iic, bool enable); - -/** - \brief Link DMA channel to iic device - \param[in] iic Handle to operate - \param[in] tx_dma The DMA channel handle for send, when it is NULL means to unlink the channel - \param[in] rx_dma The DMA channel handle for receive, when it is NULL means to unlink the channel - \return error code \ref csi_error_t -*/ -csi_error_t csi_iic_link_dma(csi_iic_t *iic, csi_dma_ch_t *tx_dma, csi_dma_ch_t *rx_dma); - -/** - \brief Get iic state - \param[in] iic Handle to operate - \param[out] state iic state \ref csi_state_t - \return error code \ref csi_error_t -*/ -csi_error_t csi_iic_get_state(csi_iic_t *iic, csi_state_t *state); - -/** - \brief Enable iic power manage - \param[in] iic iic handle to operate - \return error code \ref csi_error_t -*/ -csi_error_t csi_iic_enable_pm(csi_iic_t *iic); - -/** - \brief Disable iic power manage - \param[in] iic iic handle to operate - \return None -*/ -void csi_iic_disable_pm(csi_iic_t *iic); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_IIC_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/intc.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/intc.h deleted file mode 100755 index 573f33eb..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/intc.h +++ /dev/null @@ -1,178 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/intc.h - * @brief Header File for INTC Driver - * @version V1.0 - * @date 02. June 2020 - * @model intc - ******************************************************************************/ - -#ifndef _DRV_INTC_H_ -#define _DRV_INTC_H_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif -typedef enum int_trigger_mode_t { - INT_MODE_LOW_LEVEL, - INT_MODE_HIGH_LEVEL, - INT_MODE_RISING_EDGE, - INT_MODE_FALLING_EDGE, - INT_MODE_DOUBLE_EDGE, -} int_trigger_mode_t; - -/** - \brief Initialize the INTC interrupt controller - */ -void csi_intc_init(void); - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the INTC interrupt controller. - \param[in] IRQn External interrupt number. Value cannot be negative. - */ -void csi_intc_enable_irq(int32_t IRQn); - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the INTC interrupt controller. - \param[in] IRQn External interrupt number. Value cannot be negative. - */ -void csi_intc_disable_irq(int32_t IRQn); - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the INTC and returns the pending bit for the specified interrupt. - \param[in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -uint32_t csi_intc_get_pending_irq(int32_t IRQn); - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param[in] IRQn Interrupt number. Value cannot be negative. - */ -void csi_intc_set_pending_irq(int32_t IRQn); - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param[in] IRQn External interrupt number. Value cannot be negative. - */ -void csi_intc_clear_pending_irq(int32_t IRQn); - -/** - \brief Get Wake up Interrupt - \details Reads the wake up register in the INTC and returns the pending bit for the specified interrupt. - \param[in] IRQn Interrupt number. - \return 0 Interrupt is not set as wake up interrupt. - \return 1 Interrupt is set as wake up interrupt. - */ -uint32_t csi_intc_get_wakeup_irq(int32_t IRQn); - -/** - \brief Set Wake up Interrupt - \details Sets the wake up bit of an external interrupt. - \param[in] IRQn Interrupt number. Value cannot be negative. - */ -void csi_intc_set_wakeup_irq(int32_t IRQn); - -/** - \brief Clear Wake up Interrupt - \details Clears the wake up bit of an external interrupt. - \param[in] IRQn External interrupt number. Value cannot be negative. - */ -void csi_intc_clear_wakeup_irq(int32_t IRQn); - -/** - \brief Get Active Interrupt - \details Reads the active register in the INTC and returns the active bit for the device specific interrupt. - \param[in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -uint32_t csi_intc_get_active(int32_t IRQn); - -/** - \brief Set Threshold register - \details set the threshold register in the INTC. - \param[in] VectThreshold specific vecter threshold. - \param[in] PrioThreshold specific priority threshold. - */ -void csi_intc_set_threshold(uint32_t VectThreshold, uint32_t PrioThreshold); - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param[in] IRQn Interrupt number. - \param[in] priority Priority to set. - */ -void csi_intc_set_prio(int32_t IRQn, uint32_t priority); - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param[in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -uint32_t csi_intc_get_prio(int32_t IRQn); - -/** - \brief funciton is acknowledge the IRQ. this interface is internally used by irq system - \param[in] irq irq number to operate - \return 0 on success; -1 on failure - */ -int csi_intc_ack_irq(int32_t IRQn); - -/** - \brief This function is set the attributes of an IRQ. - \param[in] irq irq number to operate - \param[in] priority interrupt priority - \param[in] trigger_mode interrupt trigger_mode - \return 0 on success; -1 on failure -*/ -int csi_intc_set_attribute(int32_t IRQn, uint32_t priority, int_trigger_mode_t trigger_mode); - -/** - \brief Set interrupt handler - \details Set the interrupt handler according to the interrupt num, the handler will be filled in g_irqvector[]. - \param[in] IRQn Interrupt number. - \param[in] handler Interrupt handler. - */ -void csi_intc_set_vector(int32_t IRQn, uint32_t handler); - -/** - \brief Get interrupt handler - \details Get the address of interrupt handler function. - \param[in] IRQn Interrupt number. - */ -uint32_t csi_intc_get_vector(int32_t IRQn); - -#endif /* _DRV_INTC_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/io.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/io.h deleted file mode 100755 index 5b970c33..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/io.h +++ /dev/null @@ -1,131 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/io.h - * @brief Header File for register bits operation - * @version V1.0 - * @date 9. Oct 2020 - * @model io - ******************************************************************************/ - -#ifndef _DRV_IO_H_ -#define _DRV_IO_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* Bit field operate*/ -#define REG64(addr) (*(volatile uint64_t *)(addr)) -#define REG32(addr) (*(volatile uint32_t *)(addr)) -#define REG16(addr) (*(volatile uint16_t *)(addr)) -#define REG8(addr) (*(volatile uint8_t *)(addr)) - -/* Insert value to some field in reg, other field is set to 0(the field make macro) */ -#define HAL_FMK(PER_REG_FIELD, val) \ - (((val) << PER_REG_FIELD##_SHIFT) & PER_REG_FIELD##_MASK) - -/* Get value of some field in reg(the field extract macro) */ -#define HAL_FEXT(reg, PER_REG_FIELD) \ - (((reg) & PER_REG_FIELD##_MASK) >> PER_REG_FIELD##_SHIFT) - -/* Insert value to some field in reg, other field don't change(the field insert macro) */ -#define HAL_FINS(reg, PER_REG_FIELD, val) \ - ((reg) = ((reg) & ~PER_REG_FIELD##_MASK) \ - | HAL_FMK(PER_REG_FIELD, val)) - - -/* Bit operate */ -/* Set one value to 1, other bit don't change*/ -#define HAL_BIT_SET(reg, bit) ((reg) = ((reg) | (1U << (bit)))) - -/* Set one value to 0, other bit don't change*/ -#define HAL_BIT_CLR(reg, bit) ((reg) = ((reg) & (~(1U << (bit))))) - -/* Get value of one bit(0/1) */ -#define HAL_GET_BIT_VAL(reg, bit) (((reg)>> (bit)) & 1U) - -/* Judge one bit is 1 or not */ -#define HAL_IS_BIT_SET(reg, pos) (((reg) & (1U << (pos))) != 0x0U) - -/* Judge one bit is 0 or not */ -#define HAL_IS_BIT_CLR(reg, pos) (((reg) & (1U << (pos))) == 0x0U) - -/* Set one value to bit, other bit don't change*/ -#define HAL_BIT_INSR(reg, bit, val) \ - ((reg) = (((reg) & (~(1U << (bit)))) | (((val) & 1U) << (bit)))) - - -static inline uint8_t getreg8(volatile void *addr) -{ - return *(volatile uint8_t *)addr; -} - -static inline void putreg8(uint8_t val, volatile void *addr) -{ - *(volatile uint8_t *)addr = val; -} - -static inline uint16_t getreg16(volatile void *addr) -{ - return *(volatile uint16_t *)addr; -} - -static inline void putreg16(uint16_t val, volatile void *addr) -{ - *(volatile uint16_t *)addr = val; -} - -static inline uint32_t getreg32(volatile void *addr) -{ - return *(volatile uint32_t *)addr; -} - -static inline void putreg32(uint32_t val, volatile void *addr) -{ - *(volatile uint32_t *)addr = val; -} - -static inline uint64_t getreg64(volatile void *addr) -{ - return *(volatile uint64_t *)addr; -} - -static inline void putreg64(uint32_t val, volatile void *addr) -{ - *(volatile uint64_t *)addr = val; -} - -static inline uint32_t inl(void *addr) -{ - return *(volatile uint32_t *)addr; -} - -static inline void outl(uint32_t val, void *addr) -{ - *(volatile uint32_t *)addr = val; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_IO_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/iso7816.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/iso7816.h deleted file mode 100755 index 706d4fa6..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/iso7816.h +++ /dev/null @@ -1,409 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/iso7816.h - * @brief Header File for ISO7816 Driver - * @version V1.0 - * @date 9. Oct 2020 - * @model iso7816 - ******************************************************************************/ - -#ifndef _DRV_ISO7816_H_ -#define _DRV_ISO7816_H_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - A_5V, - B_3_3V, - C_1_8V, -} dcd_vclass_t; - -typedef enum { - T0, - T1, -} iso7816_tprotocol_t; - -typedef enum { - ISO7816_EVENT_CARD_DETECTED, - ISO7816_EVENT_READ_COMPLETE, - ISO7816_EVENT_WRITE_COMPLETE, - ISO7816_EVENT_READ_ERROR, - ISO7816_EVENT_WRITE_ERROR, - ISO7816_EVENT_ACTIVATE_SUCCESS, - ISO7816_EVENT_ACTIVATE_FAILED, - ISO7816_EVENT_CARD_ERROR_DEACTIVATE, - ISO7816_EVENT_CARD_SESSION_CLOSED, - ISO7816_EVENT_RX_FULL, - ISO7816_EVENT_CWT_TIME_OUT, - ISO7816_EVENT_RX_OVER, - ISO7816_EVENT_CRC_ERR, - ISO7816_EVENT_PARITY_ERR, - ISO7816_EVENT_SLAVE_ATR_DETECTED, - ISO7816_EVENT_SLAVE_ATR_DONE, -} iso7816_event_t; - -typedef void (*iso7816_event_cb_t)(iso7816_event_t event, void *arg); - -typedef enum { - ISO7816_SLAVE, - ISO7816_MASTER, -} iso7816_mode_t; - -typedef struct { - uint8_t clk_div; - dcd_vclass_t vclass; - iso7816_mode_t mode; - int32_t card_detected_en; -} iso7816_config_t; - -typedef enum { - ISO7816_A_ONLY = 1U, - ISO7816_B_ONLY, - ISO7816_C_ONLY, - ISO7816_AB, - ISO7816_AC, - ISO7816_BC, - ISO7816_ABC, -} iso7816_voltage_class_t; - -typedef struct { - iso7816_voltage_class_t support_voltage_class; - int32_t proto_t; - int32_t clk_stop_is_support; - int32_t history_byte_num; - uint8_t history_data[15]; -} iso7816_atr_info_t; - -typedef enum { - EVEN_PARITY, - ODD_PARITY, -} iso7816_parity_type_t; - -typedef enum { - ISO7816_DRIECT, - ISO7816_INVERSE, -} iso7816_convention_t; - -typedef enum { - INVCTIVE, - ACTIVATEING, - PSS_TRF, - PSS_RECV, - ACTIVATE, -} iso7816_card_sta_t; - -/** - \brief Initialize ISO7816 master interface - \param[in] idx Master index - \param[in] cb_event Pointer to \ref iso7816_event_cb_t - \param[in] cb_arg Event callback arg - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_master_init(int idx, iso7816_event_cb_t cb_event, void *cb_arg); - -/** - \brief Uninit ISO7816 master interface - \param[in] idx Master index - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_master_uninit(int idx); - -/** - \brief Config ISO7816 master attributes - \param[in] idx Master index - \param[in] config master config \ref iso7816_config_t - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_master_config(int idx, iso7816_config_t *config); - -/** - \brief Receiving data from ISO7816 master receiver, used polling mode - \param[in] idx Master index - \param[in] buf Pointer to buffer for data to receive from i2s receiver - \param[in] len Size of receiver data - \param[in] time_out Receive time out value - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_master_receive(int idx, uint8_t *buf, uint32_t len, uint32_t time_out); - -/** - \brief Receiving data from ISO7816 master receiver, used interrupt mode - \param[in] idx Master index - \param[in] buf Pointer to buffer for data to receive from i2s receiver - \param[in] len Size of receiver data - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_master_receive_it(int idx, uint8_t *buf, uint32_t len); - -/** - \brief Sending data to ISO7816 master transmitter, used polling mode - \param[in] idx Master index - \param[in] buf Pointer to buffer for data to send - \param[in] len Size of tranmitter data - \param[in] time_out Send time out value - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_master_send(int idx, uint8_t *buf, uint32_t len, uint32_t time_out); - -/** - \brief Sending data to ISO7816 master transmitter, used interrupt mode - \param[in] idx Master index - \param[in] buf Pointer to buffer for data to send - \param[in] len Size of tranmitter data - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_master_send_it(int idx, uint8_t *buf, uint32_t len); - -/** - \brief ISO7816 master performs the activation smart card process, this process - is non-blocking,should monitor callback event or read card status to check card is activate - \param[in] idx Master index - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_master_card_activate(int idx); - -/** - \brief ISO7816 master performs the deactivation smart card process, this process - is non-blocking,should monitor callback event or read card status to check card is activate - \param[in] idx Master index - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_master_card_deactivate(int idx); - -/** - \brief The smard card session status - \param[in] idx Master index - \return smart card status. -*/ -iso7816_card_sta_t csi_iso7816_master_card_status(int idx); - -/** - \brief ISO7816 master performs the warm reset smart card process - \param[in] idx Master index - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_master_card_warm_reset(int idx); - -/** - \brief ISO7816 master performs clock stop - \param[in] idx Master index - \param[in] en The clk last state when power down - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_master_card_clk_stop_enable(int idx, int en); - -/** - \brief ISO7816 master performs pwoer down - \param[in] idx Master index - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_master_power_down(int idx); - -/** - \brief Get atr analytical results - \param[in] idx Master index - \param[out] info The result of atr information - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_master_atr_info(int idx, iso7816_atr_info_t *info); - -/** - \brief Initialize ISO7816 slave interface - \param[in] idx Slave index - \param[in] cb Pointer to \ref iso7816_event_cb_t - \param[in] cb_arg Event callback arg - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_slave_init(int idx, iso7816_event_cb_t cb, void *cb_arg); - -/** - \brief Uninit ISO7816 slave interface - \param[in] idx Slave index - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_slave_uninit(int idx); - -/** - \brief Enable ISO7816 slave interface - \param[in] idx Slave index - \param[in] en Slave enable - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_slave_enable(int idx, int en); - -/** - \brief Enable ISO7816 slave receive parity - \param[in] idx Slave index - \param[in] en Enable receive parity - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_slave_receive_parity_enable(int idx, int en); - -/** - \brief Set ISO7816 slave receive parity attributes - \param[in] idx Slave index - \param[in] type Set receiver parity type - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_slave_set_receive_parity(int idx, iso7816_parity_type_t type); - -/** - \brief Enable ISO7816 slave send parity - \param[in] idx Slave index - \param[in] en Enable send parity - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_slave_send_parity_enable(int idx, int en); - -/** - \brief Set ISO7816 slave send parity attributes - \param[in] idx Slave index - \param[in] type Set send parity attributes - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_slave_set_send_parity(int idx, iso7816_parity_type_t type); - -/** - \brief Set the number of ISO7816 slave receive retry - \param[in] idx Slave index - \param[in] val Set the number retry - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_slave_set_receive_retry(int idx, uint8_t val); - -/** - \brief Set the number of ISO7816 send send retry - \param[in] idx Slave index - \param[in] val Set the number retry - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_slave_set_send_retry(int idx, uint8_t val); - -/** - \brief Set the ISO7816 slave GT - \param[in] idx Slave index - \param[in] val Set the slave GT - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_slave_set_gt(int idx, uint8_t val); - -/** - \brief Set the ISO7816 slave WT - \param[in] idx Slave index - \param[in] val Set the slave WT - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_slave_set_wt(int idx, uint16_t val); - -/** - \brief Set the ISO7816 slave baud, baud = F/D - \param[in] idx Slave index - \param[in] val Set the slave baud - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_slave_set_baud(int idx, uint16_t val); - -/** - \brief Set the ISO7816 slave convention - \param[in] idx Slave index - \param[in] convention Set the slave convention \ref iso7816_convention_t - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_slave_set_convention(int idx, iso7816_convention_t convention); - -/** - \brief Set the ISO7816 slave art response time, val range is 400~40000 - \param[in] idx Slave index - \param[in] val Set the slave art response time - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_slave_set_atr_ack_time(int idx, int val); - -/** - \brief Set the ISO7816 slave send atr data - \param[in] idx Slave index - \param[in] buf Pointer to buffer for data to send - \param[in] len Size of tranmitter data - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_slave_send_atr(int idx, uint8_t *buf, int len); - -/** - \brief Receiving data from ISO7816 slave receiver, used polling mode - \param[in] idx Master index - \param[in] buf Pointer to buffer for data to receive from i2s receiver - \param[in] len Size of receiver data - \param[in] timer_out receive time out value - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_slave_receive(int idx, uint8_t *buf, uint32_t len, uint32_t time_out); - -/** - \brief Flushed the ISO7816 slave receive fifo - \param[in] idx Master index - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_slave_flushed_receive_fifo(int idx); - -/** - \brief Receiving data from ISO7816 slave receiver, used interrupt mode - \param[in] idx Master index - \param[in] buf Pointer to buffer for data to receive from i2s receiver - \param[in] len Size of receiver data - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_slave_receive_it(int idx, uint8_t *buf, uint32_t len); - -/** - \brief Sending data to ISO7816 slave transmitter, used polling mode - \param[in] idx Slave index - \param[in] buf Pointer to buffer for data to send - \param[in] len Size of tranmitter data - \param[in] timer_out Send time out value - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_slave_send(int idx, uint8_t *buf, uint32_t len, uint32_t time_out); - -/** - \brief Flushed the ISO7816 slave send fifo. - \param[in] idx Master index - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_slave_flushed_send_fifo(int idx); - -/** - \brief Sending data to ISO7816 slave transmitter, used interrupt mode - \param[in] idx Slave index - \param[in] buf Pointer to buffer for data to send - \param[in] len Size of tranmitter data - \return 0 for success, negative for error code -*/ -int32_t csi_iso7816_slave_send_it(int idx, uint8_t *buf, uint32_t len); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_ISO7816_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/mbox.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/mbox.h deleted file mode 100755 index c5090425..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/mbox.h +++ /dev/null @@ -1,104 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/mbox.h - * @brief Header File for MBOX Driver - * @version V1.0 - * @date 5. Apr 2020 - * @model mbox - ******************************************************************************/ - -#ifndef _DRV_MBOX_H_ -#define _DRV_MBOX_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - MBOX_EVENT_SEND_COMPLETE = 0U, ///< Send completed; however mbox may still transmit data - MBOX_EVENT_RECEIVED = 1U, ///< Data Received, only in mbox buf, call memcpy() get the data - MBOX_EVENT_ERROR = 2U, ///< Mbox transmit error occurred -} csi_mbox_event_t; - -typedef struct csi_mbox csi_mbox_t; -struct csi_mbox { - csi_dev_t dev; - void (*callback)(csi_mbox_t *mbox, csi_mbox_event_t event, uint32_t channel_id, uint32_t received_len, void *arg); - void *arg; - void *priv; -}; - -/** - \brief Initialize mbox Interface. - Initializes the resources needed for the mbox interface. - \param[in] mbox Operate handle. - \param[in] idx The device idx. - \return Error code \ref csi_error_t. -*/ -csi_error_t csi_mbox_init(csi_mbox_t *mbox, uint32_t idx); - -/** - \brief Uninitialize mbox interface. stops operation and releases the software resources used by the interface. - \param[in] mbox Operate handle. -*/ -void csi_mbox_uninit(csi_mbox_t *mbox); - -/** - \brief Start sending data to mbox transmitter. - \param[in] mbox Operate handle. - \param[in] channel_id Index of channel. - \param[in] data Pointer to buffer with data to send to mbox transmitter. - \param[in] size Number of data items to send. - \return sent Number of data or error code. -*/ -int32_t csi_mbox_send(csi_mbox_t *mbox, uint32_t channel_id, const void *data, uint32_t size); - -/** - \brief Start receiving data from mbox receiver. - \param[in] mbox Operate handle. - \param[in] channel_id Index of channel. - \param[out] data Pointer to buffer with data to receive from mailbox. - \param[in] size Number of data items to receive. - \return received Number or error code. -*/ -int32_t csi_mbox_receive(csi_mbox_t *mbox, uint32_t channel_id, void *data, uint32_t size); - -/** - \brief Attach callback to the mbox. - \param[in] mbox Operate handle. - \param[in] cb Event callback function. - \param[in] arg User private param for event callback. - \return Error code \ref csi_error_t. -*/ -csi_error_t csi_mbox_attach_callback(csi_mbox_t *mbox, void *callback, void *arg); - -/** - \brief Detach callback from the mbox - \param[in] mbox Operate handle. -*/ -void csi_mbox_detach_callback(csi_mbox_t *mbox); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_MBOX_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/pm.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/pm.h deleted file mode 100755 index 1894f206..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/pm.h +++ /dev/null @@ -1,122 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/pm.h - * @brief Header File for PM Driver - * @version V1.0 - * @date 10. Oct 2020 - * @model pm - ******************************************************************************/ - -#ifndef _DRV_PM_H_ -#define _DRV_PM_H_ - -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \brief Initialize PM module - \return Error code \ref csi_error_t -*/ -csi_error_t csi_pm_init(void); - -/** - \brief De-initialize PM module - \return None -*/ -void csi_pm_uninit(void); - -/** - \brief Set the retention memory used to save registers - \param[in] mem Retention memory(word align) - \param[in] num Number of memory(1: 1 word) - \return Error code \ref csi_error_t -*/ -csi_error_t csi_pm_set_reten_mem(uint32_t *mem, uint32_t num); - -/** - \brief Config the wakeup source - \param[in] wakeup_num Wakeup source num - \param[in] enable Flag control the wakeup source is enable or not - \return Error code \ref csi_error_t -*/ -csi_error_t csi_pm_config_wakeup_source(uint32_t wakeup_num, bool enable); - -/** - \brief System enter low-power mode - \param[in] mode Low-power mode, \ref csi_pm_mode_t - \return Error code \ref csi_error_t -*/ -csi_error_t csi_pm_enter_sleep(csi_pm_mode_t mode); - -/** - \brief Register device to the PM list - \param[in] dev Csi dev - \param[in] pm_action PM action function - \param[in] mem_size Size of memory for saving registers - \param[in] priority PM dev priority(0-3), The smaller the value, - the last execution before entering low power consumption, - the first execution after exiting low power consumption - \return Error code \ref csi_error_t -*/ -csi_error_t csi_pm_dev_register(csi_dev_t *dev, void *pm_action, uint32_t mem_size, uint8_t priority); - -/** - \brief Deregister device to the PM list - \param[in] dev Csi dev - \return None -*/ -void csi_pm_dev_unregister(csi_dev_t *dev); - -/** - \brief Save registers to memory - \param[in] mem Mem to store registers - \param[in] addr Registers address - \param[in] num Number of memory(1: 1 word) - \return None -*/ -void csi_pm_dev_save_regs(uint32_t *mem, uint32_t *addr, uint32_t num); - -/** - \brief Save registers to memory - \param[in] mem Mem to store registers - \param[in] addr Registers address - \param[in] num Number of memory(1: 1 word) - \return None -*/ -void csi_pm_dev_restore_regs(uint32_t *mem, uint32_t *addr, uint32_t num); - -/** - \brief Notify devices enter low-power states - \param[in] action Device low-power action - \return Error code \ref csi_error_t -*/ -csi_error_t csi_pm_dev_notify(csi_pm_dev_action_t action); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_PM_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/pmu.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/pmu.h deleted file mode 100755 index ac5bbadf..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/pmu.h +++ /dev/null @@ -1,118 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv_pmu.h - * @brief header file for pmu driver - * @version V1.0 - * @date 02. June 2017 - * @model pmu - ******************************************************************************/ - -#ifndef _DRV_PMU_H_ -#define _DRV_PMU_H_ - - -#include - -#ifdef __cplusplus -extern "C" { -#endif -/// definition for pmu handle. -typedef void *pmu_handle_t; - -/****** PMU specific error codes *****/ -typedef enum { - EDRV_PMU_MODE = (1), ///< Specified Mode not supported -} pmu_error_e; - -/*----- PMU Control Codes: Mode -----*/ -typedef enum { - PMU_MODE_RUN = 0, ///< Running mode - PMU_MODE_SLEEP, ///< Sleep mode - PMU_MODE_DOZE, ///< Doze mode - PMU_MODE_DORMANT, ///< Dormant mode - PMU_MODE_STANDBY, ///< Standby mode - PMU_MODE_SHUTDOWN ///< Shutdown mode -} pmu_mode_e; - -/*----- PMU Control Codes: Wakeup type -----*/ -typedef enum { - PMU_WAKEUP_TYPE_PULSE = 0, ///< Pulse interrupt - PMU_WAKEUP_TYPE_LEVEL ///< Level interrupt -} pmu_wakeup_type_e; - -/*----- PMU Control Codes: Wakeup polarity -----*/ -typedef enum { - PMU_WAKEUP_POL_LOW = 0, ///< Low or negedge - PMU_WAKEUP_POL_HIGH ///< High or posedge -} pmu_wakeup_pol_e; - -/****** PMU Event *****/ -typedef enum { - PMU_EVENT_SLEEP_DONE = 0, ///< Send completed; however PMU may still transmit data - PMU_EVENT_PREPARE_SLEEP = 1 -} pmu_event_e; - -typedef void (*pmu_event_cb_t)(int32_t idx, pmu_event_e event, pmu_mode_e mode); ///< Pointer to \ref pmu_event_cb_t : PMU Event call back. - -/** - \brief Initialize PMU Interface. 1. Initializes the resources needed for the PMU interface 2.registers event callback function - \param[in] idx the id of the pmu - \param[in] cb_event Pointer to \ref pmu_event_cb_t - \return return pmu handle if success -*/ -pmu_handle_t csi_pmu_initialize(int32_t idx, pmu_event_cb_t cb_event); - -/** - \brief De-initialize PMU Interface. stops operation and releases the software resources used by the interface - \param[in] handle pmu handle to operate. - \return error code -*/ -int32_t csi_pmu_uninitialize(pmu_handle_t handle); - -/** - \brief choose the pmu mode to enter - \param[in] handle pmu handle to operate. - \param[in] mode \ref pmu_mode_e - \return error code -*/ -int32_t csi_pmu_enter_sleep(pmu_handle_t handle, pmu_mode_e mode); - -/** - \brief control pmu power. - \param[in] handle pmu handle to operate. - \param[in] state power state.\ref csi_power_stat_e. - \return error code -*/ -/** - \brief Config the wakeup source. - \param[in] handle pmu handle to operate - \param[in] wakeup_num wakeup source num - \param[in] type \ref pmu_wakeup_type - \param[in] pol \ref pmu_wakeup_pol - \param[in] enable flag control the wakeup source is enable or not - \return error code -*/ -int32_t csi_pmu_config_wakeup_source(pmu_handle_t handle, uint32_t wakeup_num, pmu_wakeup_type_e type, pmu_wakeup_pol_e pol, uint8_t enable); - -#ifdef __cplusplus -} -#endif - -#endif /* _CSI_PMU_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/pwm.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/pwm.h deleted file mode 100755 index 0db71e97..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/pwm.h +++ /dev/null @@ -1,172 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/pwm.h - * @brief Header File for PWM Driver - * @version V1.0 - * @date 9. Oct 2020 - * @model pwm - ******************************************************************************/ - -#ifndef _DRV_PWM_H_ -#define _DRV_PWM_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PWM_POLARITY_HIGH = 0U, ///< High level - PWM_POLARITY_LOW ///< Low level -} csi_pwm_polarity_t; - -typedef enum { - PWM_CAPTURE_POLARITY_POSEDGE = 0U, ///< Posedge Edge - PWM_CAPTURE_POLARITY_NEGEDGE, ///< Negedge Edge - PWM_CAPTURE_POLARITY_BOTHEDGE ///< Both Edge -} csi_pwm_capture_polarity_t; - -typedef enum { - PWM_EVENT_CAPTURE_POSEDGE = 0U, ///< Capture Posedge Event - PWM_EVENT_CAPTURE_NEGEDGE, ///< Capture Negedge Event - PWM_EVENT_CAPTURE_BOTHEDGE, ///< Capture Bothedge Event - PWM_EVENT_ERROR, ///< Error -} csi_pwm_event_t; - -typedef struct csi_pwm csi_pwm_t; - -struct csi_pwm { - csi_dev_t dev; - void (*callback)(csi_pwm_t *pwm, csi_pwm_event_t event, uint32_t ch, uint32_t time_us, void *arg); - void *arg; - void *priv; -}; - -/** - \brief Initialize PWM interface. Initializes the resources needed for the PWM interface - \param[in] pwm Handle to operate - \param[in] idx PWM idx - \return Error code \ref csi_error_t -*/ -csi_error_t csi_pwm_init(csi_pwm_t *pwm, uint32_t idx); - -/** - \brief De-initialize PWM interface. Stops operation and releases the software resources used by the interface - \param[in] pwm Handle to operate - \return None -*/ -void csi_pwm_uninit(csi_pwm_t *pwm); - -/** - \brief Config PWM out mode - \param[in] pwm Handle to operate - \param[in] channel Channel num - \param[in] period_us The PWM period in us - \param[in] pulse_width_us The PMW pulse width in us - \param[in] polarity The PWM polarity \ref csi_pwm_polarity_t - \return Error code \ref csi_error_t -*/ -csi_error_t csi_pwm_out_config(csi_pwm_t *pwm, - uint32_t channel, - uint32_t period_us, - uint32_t pulse_width_us, - csi_pwm_polarity_t polarity); - -/** - \brief Start generate PWM signal - \param[in] pwm Handle to operate - \param[in] channel Channel num - \return Error code \ref csi_error_t -*/ -csi_error_t csi_pwm_out_start(csi_pwm_t *pwm, uint32_t channel); - -/** - \brief Stop generate PWM signal - \param[in] pwm Handle to operate - \param[in] channel Channel num - \return None -*/ -void csi_pwm_out_stop(csi_pwm_t *pwm, uint32_t channel); - -/** - \brief Config PWM capture mode - \param[in] pwm Handle to operate - \param[in] channel Channel num - \param[in] polarity PWM capture polarity \ref csi_pwm_capture_polarity_t - \param[in] count PWM capture polarity count - \return Error code \ref csi_error_t -*/ -csi_error_t csi_pwm_capture_config(csi_pwm_t *pwm, - uint32_t channel, - csi_pwm_capture_polarity_t polarity, - uint32_t count); - -/** - \brief Start PWM capture - \param[in] pwm Handle to operate - \param[in] channel Channel num - \return Error code \ref csi_error_t -*/ -csi_error_t csi_pwm_capture_start(csi_pwm_t *pwm, uint32_t channel); - -/** - \brief Stop PWM capture - \param[in] pwm Handle to operate - \param[in] channel Channel num - \return None -*/ -void csi_pwm_capture_stop(csi_pwm_t *pwm, uint32_t channel); - -/** - \brief Attach PWM callback - \param[in] pwm Handle to operate - \param[in] callback Callback func - \param[in] arg Callback's param - \return Error code \ref csi_error_t -*/ -csi_error_t csi_pwm_attach_callback(csi_pwm_t *pwm, void *callback, void *arg); - -/** - \brief Detach PWM callback - \param[in] pwm Handle to operate - \return None -*/ -void csi_pwm_detach_callback(csi_pwm_t *pwm); - -/** - \brief Enable PWM power manage - \param[in] pwm Handle to operate - \return Error code \ref csi_error_t -*/ -csi_error_t csi_pwm_enable_pm(csi_pwm_t *pwm); - -/** - \brief Disable PWM power manage - \param[in] pwm Handle to operate - \return None -*/ -void csi_pwm_disable_pm(csi_pwm_t *pwm); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_PWM_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/qspi.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/qspi.h deleted file mode 100755 index e8f33312..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/qspi.h +++ /dev/null @@ -1,304 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/qspi.h - * @brief Header File for QSPI Driver - * @version V1.0 - * @date 8. Apr 2020 - * @model qspi - ******************************************************************************/ - -#ifndef _DRV_QSPI_H_ -#define _DRV_QSPI_H_ - -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \enum csi_qspi_clock_mode_t - * \brief QSPI clock mode - */ -typedef enum { - QSPI_CLOCK_MODE_0 = 0, ///< Clock Polarity 0, Clock Phase 0 - QSPI_CLOCK_MODE_1, ///< Clock Polarity 0, Clock Phase 1 - QSPI_CLOCK_MODE_2, ///< Clock Polarity 1, Clock Phase 0 - QSPI_CLOCK_MODE_3, ///< Clock Polarity 1, Clock Phase 1 -} csi_qspi_mode_t; - -/** - * \enum csi_qspi_bus_width_t - * \brief QSPI bus width - */ -typedef enum { - QSPI_CFG_BUS_SINGLE = 0, ///< Single line - QSPI_CFG_BUS_DUAL, ///< Two line - QSPI_CFG_BUS_QUAD, ///< Four line -} csi_qspi_bus_width_t; - -/** - * \enum csi_qspi_address_size_t - * \brief Address size in bits - */ -typedef enum { - QSPI_ADDRESS_8_BITS = 0, - QSPI_ADDRESS_16_BITS, - QSPI_ADDRESS_24_BITS, - QSPI_ADDRESS_32_BITS, -} csi_qspi_address_size_t; - -/** - * \enum csi_qspi_alternate_bytes_size_t - * rief QSPI alternate bytes - */ -typedef enum { - QSPI_ALTERNATE_8_BITS = 0, - QSPI_ALTERNATE_16_BITS, - QSPI_ALTERNATE_24_BITS, - QSPI_ALTERNATE_32_BITS, -} csi_qspi_alt_size_t; - -/** QSPI command - * - * Defines a frame format. It consists of instruction, address, alternative, dummy count and data - */ -typedef struct { - struct { - csi_qspi_bus_width_t bus_width; ///< Bus width for the instruction - uint8_t value; ///< Instruction value - bool disabled; ///< Instruction phase skipped if disabled is set to true - } instruction; - struct { - csi_qspi_bus_width_t bus_width; ///< Bus width for the address - csi_qspi_address_size_t size; ///< Address size - uint32_t value; ///< Address value - bool disabled; ///< Address phase skipped if disabled is set to true - } address; - struct { - csi_qspi_bus_width_t bus_width; ///< Bus width for alternative - csi_qspi_alt_size_t size; ///< Alternative size - uint32_t value; ///< Alternative value - bool disabled; ///< Alternative phase skipped if disabled is set to true - } alt; - uint8_t dummy_count; ///< Dummy cycles count - struct { - csi_qspi_bus_width_t bus_width; ///< Bus width for data - } data; - uint8_t ddr_enable; -} csi_qspi_command_t; - -/** - * \enum csi_qspi_event_t - * \brief QSPI event - */ -typedef enum { - QSPI_EVENT_COMMAND_COMPLETE = 0, ///< Command completed - QSPI_EVENT_ERROR, ///< An error has occurred -} csi_qspi_event_t; - -/** - * \struct csi_qspi_t - * \brief QSPI Handle Structure definition - */ - -typedef struct csi_qspi csi_qspi_t; -struct csi_qspi { - csi_dev_t dev; ///< QSPI hw-device info - void (*callback)(csi_qspi_t *qspi, csi_qspi_event_t event, void *arg); ///< User callback function - void *arg; ///< QSPI custom designed param passed to evt_cb - uint8_t *tx_data; ///< Pointer to QSPI Tx transfer Buffer - uint32_t tx_size; ///< QSPI Tx Transfer size - uint8_t *rx_data; ///< Pointer to QSPI Rx transfer Buffer - uint32_t rx_size; ///< QSPI Rx Transfer size - void *send; ///< The send_async func - void *receive; ///< The receive_async func - void *send_receive; ///< The send_receive_async func - csi_state_t state; ///< Peripheral state - csi_dma_ch_t *tx_dma; - csi_dma_ch_t *rx_dma; - void *priv; -}; - -/** - \brief Init QSPI ctrl block - 1. Initializes the QSPI mode according to the specified parameters in the csi_qspi_init_t - 2. Registers event callback function and user param for the callback - \param[in] qspi Handle of QSPI instance - \param[in] idx Index of instance - \return Error code -*/ -csi_error_t csi_qspi_init(csi_qspi_t *qspi, uint32_t idx); - - -/** - \brief De-initialize QSPI Instance - stops operation and releases the software resources used by the Instance - \param[in] qspi Handle of QSPI instance -*/ -void csi_qspi_uninit(csi_qspi_t *qspi); - -/** - \brief Attach the callback handler to QSPI - \param[in] qspi Operate handle - \param[in] callback Callback function - \param[in] arg User can define it by himself as callback's param - \return Error code -*/ -csi_error_t csi_qspi_attach_callback(csi_qspi_t *qspi, void *callback, void *arg); - -/** - \brief Detach the callback handler - \param[in] qspi Operate handle - \return None -*/ -void csi_qspi_detach_callback(csi_qspi_t *qspi); - -/** - \brief Config qspi frequence - \param[in] qspi Handle of qspi instance - \param[in] hz QSPI frequence - \return The actual config frequency -*/ -uint32_t csi_qspi_frequence(csi_qspi_t *qspi, uint32_t hz); - -/** - \brief Config qspi mode - \param[in] qspi Handle of qspi instance - \param[in] mode QSPI mode - \return Error code -*/ -csi_error_t csi_qspi_mode(csi_qspi_t *qspi, csi_qspi_mode_t mode); - -/** - \brief Send an amount of data in blocking mode - \param[in] qspi QSPI handle - \param[in] cmd Structure that contains the command configuration information - \param[in] data Pointer to data buffer - \param[in] size Size of data to send - \param[in] timeout Time out duration - \return If send successful, this function shall return the num of data witch is sent successful - otherwise, the function shall return error code - */ -int32_t csi_qspi_send(csi_qspi_t *qspi, csi_qspi_command_t *cmd, const void *data, uint32_t size, uint32_t timeout); - -/** - \brief Receive an amount of data in blocking mode - \param[in] qspi QSPI handle - \param[in] cmd Structure that contains the command configuration information - \param[out] data Pointer to data buffer - \param[in] size Size of data items to receive - \param[in] timeout Time out duration - \return If receive successful, this function shall return the num of data witch is received successfulful - otherwise, the function shall return error code - */ -int32_t csi_qspi_receive(csi_qspi_t *qspi, csi_qspi_command_t *cmd, void *data, uint32_t size, uint32_t timeout); - -/** - \brief Transfer an amount of data in blocking mode - \param[in] qspi QSPI handle - \param[in] cmd Structure that contains the command configuration information - \param[in] tx_data Pointer to send data buffer - \param[out] rx_data Pointer to receive data buffer - \param[in] size Size of data to transfer - \param[in] timeout Time out duration - \return If transfer successful, this function shall return the num of data witch is transfer successfulful - otherwise, the function shall return error code - */ -int32_t csi_qspi_send_receive(csi_qspi_t *qspi, csi_qspi_command_t *cmd, const void *tx_data, void *rx_data, uint32_t size, uint32_t timeout); - -/** - \brief Send an amount of data in async mode - \param[in] qspi QSPI handle - \param[in] cmd Structure that contains the command configuration information - \param[in] data Pointer to data buffer - \param[in] size Size of data to send - \return Data number send - */ -csi_error_t csi_qspi_send_async(csi_qspi_t *qspi, csi_qspi_command_t *cmd, const void *data, uint32_t size); - -/** - \brief Receive an amount of data in async mode - \param[in] qspi QSPI handle - \param[in] cmd Structure that contains the command configuration information - \param[out] data Pointer to data buffer - \param[in] size Size of data items to receive - \return Data number received - */ -csi_error_t csi_qspi_receive_async(csi_qspi_t *qspi, csi_qspi_command_t *cmd, void *data, uint32_t size); - -/** - \brief Transfer an amount of data in async mode - \param[in] qspi QSPI handle - \param[in] cmd Structure that contains the command configuration information - \param[in] tx_data Pointer to send data buffer - \param[out] rx_data Pointer to receive data buffer - \param[in] size Size of data to transfer - \return Data number transfered - */ -csi_error_t csi_qspi_send_receive_async(csi_qspi_t *qspi, csi_qspi_command_t *cmd, const void *tx_data, void *rx_data, uint32_t size); - -/** - \brief Link DMA channel to qspi device - \param[in] qspi QSPI handle to operate - \param[in] tx_dma The DMA channel handle for send, when it is NULL means to unlink the channel - \param[in] rx_dma The DMA channel handle for receive, when it is NULL means to unlink the channel - \return Error code -*/ -csi_error_t csi_qspi_link_dma(csi_qspi_t *qspi, csi_dma_ch_t *tx_dma, csi_dma_ch_t *rx_dma); - -/** - \brief Get the state of qspi device - \param[in] qspi QSPI handle - \param[in] state QSPI state \ref csi_state_t - \return Error code - */ -csi_error_t csi_qspi_get_state(csi_qspi_t *qspi, csi_state_t *state); - -/** - \brief Comfigure the memory mapped mode - \param[in] qspi QSPI handle - \param[in] cmd Structure that contains the command configuration information - \return Error code - */ -csi_error_t csi_qspi_memory_mapped(csi_qspi_t *qspi, csi_qspi_command_t *cmd); - -/** - \brief Enable qspi power manage - \param[in] qspi QSPI handle to operate - \return Error code -*/ -csi_error_t csi_qspi_enable_pm(csi_qspi_t *qspi); - -/** - \brief Disable qspi power manage - \param[in] qspi QSPI handle to operate - \return None -*/ -void csi_qspi_disable_pm(csi_qspi_t *qspi); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_QSPI_H_*/ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/ringbuf.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/ringbuf.h deleted file mode 100755 index e5006e16..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/ringbuf.h +++ /dev/null @@ -1,62 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** -* @file ringbuffer.h -* @brief header file for ringbuffer Driver -* @version V1.0 -* @date August 15. 2019 -******************************************************************************/ -#ifndef _RING_BUFFER_H_ -#define _RING_BUFFER_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "stdint.h" -#include - -typedef struct ringbuffer { - uint8_t *buffer; - uint32_t size; - uint32_t write; - uint32_t read; - uint32_t data_len; -} csi_ringbuf_t; - -void csi_ringbuf_reset(csi_ringbuf_t *fifo); -uint32_t csi_ringbuf_len(csi_ringbuf_t *fifo); -uint32_t csi_ringbuf_avail(csi_ringbuf_t *fifo); -bool csi_ringbuf_is_empty(csi_ringbuf_t *fifo); -bool csi_ringbuf_is_full(csi_ringbuf_t *fifo); - -/*write to ringbuffer*/ -uint32_t csi_ringbuf_in(csi_ringbuf_t *fifo, const void *in, uint32_t len); - -/*read to ringbuffer*/ -uint32_t csi_ringbuf_out(csi_ringbuf_t *fifo, void *out, uint32_t len); - -/*move to another ringbuffer*/ -uint32_t csi_ringbuf_move(csi_ringbuf_t *fifo_in, csi_ringbuf_t *fifo_out); - -#ifdef __cplusplus -} -#endif - -#endif /* _RING_BUFFER_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/rng.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/rng.h deleted file mode 100755 index 11e03f44..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/rng.h +++ /dev/null @@ -1,54 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/tng.h - * @brief Header File for RNG Driver - * @version V1.0 - * @date 22. Apr 2020 - * @model tng - ******************************************************************************/ -#ifndef _DRV_TNG_H_ -#define _DRV_TNG_H_ - -#include "drv/common.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \brief Get data from the TNG engine - \param[out] Data Pointer to buffer with data get from TNG - \param[in] Num Number of data items,uinit in uint32 - \return Error code \ref csi_error_t -*/ -csi_error_t csi_rng_get_multi_word(uint32_t *data, uint32_t num); - -/** - \brief Get data from the TNG engine - \return Error code \ref csi_error_t -*/ -csi_error_t csi_rng_get_single_word(uint32_t* data); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_TNG_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/rsa.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/rsa.h deleted file mode 100755 index ea5b005d..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/rsa.h +++ /dev/null @@ -1,198 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -/****************************************************************************** - * @file drv/rsa.h - * @brief Header File for RSA Driver - * @version V1.0 - * @date 02. June 2020 - * @model rsa - ******************************************************************************/ -#ifndef _DRV_RSA_H_ -#define _DRV_RSA_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -/*----- RSA Control Codes: Mode Parameters: Key Bits -----*/ -/****** RSA Key bits Type *****/ -typedef enum { - RSA_KEY_BITS_192 = 0U, /* 192 Key bits */ - RSA_KEY_BITS_256, /* 256 Key bits */ - RSA_KEY_BITS_512, /* 512 Key bits */ - RSA_KEY_BITS_1024, /* 1024 Key bits */ - RSA_KEY_BITS_2048, /* 2048 Key bits */ - RSA_KEY_BITS_3072, /* 3072 Key bits */ - RSA_KEY_BITS_4096 /* 4096 Key bits */ -} csi_rsa_key_bits_t; - -/****** RSA Padding Type *****/ -typedef enum { - RSA_PADDING_MODE_NO = 0, /* RSA NO Padding Mode */ - RSA_PADDING_MODE_PKCS1, /* RSA PKCS1 Padding Mode */ - RSA_PADDING_MODE_PKCS1_OAEP, /* RSA PKCS1 OAEP Padding Mode */ - RSA_PADDING_MODE_SSLV23, /* RSA SSLV23 Padding Mode */ - RSA_PADDING_MODE_X931, /* RSA X931 Padding Mode */ - RSA_PADDING_MODE_PSS /* RSA PSS Padding Mode */ -} csi_rsa_padding_type_t; - -/****** RSA Hash Type *****/ -typedef enum { - RSA_HASH_TYPE_MD5 = 0, - RSA_HASH_TYPE_SHA1, - RSA_HASH_TYPE_SHA224, - RSA_HASH_TYPE_SHA256, - RSA_HASH_TYPE_SHA384, - RSA_HASH_TYPE_SHA512 -} csi_rsa_hash_type_t; - -/****** RSA Context *****/ -typedef struct { - void *n; /* Pointer to the public modulus */ - void *e; /* Pointer to the public exponent */ - void *d; /* Pointer to the private exponent */ - csi_rsa_key_bits_t key_bits; /* RSA KEY BITS */ - csi_rsa_padding_type_t padding_type; /* RSA PADDING TYPE */ -} csi_rsa_context_t; - -/****** RSA State *****/ -typedef struct { - uint8_t busy : 1; /* Calculate busy flag */ - uint8_t error : 1; /* Calculate error flag */ -} csi_rsa_state_t; - -/****** RSA Ctrl *****/ -typedef struct { - csi_dev_t dev; - void *cb; - void *arg; - csi_rsa_state_t state; - void *prim; -} csi_rsa_t; - -/****** RSA Moddle *****/ -typedef struct { - uint32_t pout[64]; - uint8_t *pouts; - uint32_t *pout_size; - uint32_t u32keywords; - uint8_t *pdst; - uint32_t u32padding; - uint32_t u32dst_words; - uint32_t u32type; - uint32_t rsa_state; -}rsa_middle_t; - -/****** RSA Event *****/ -typedef enum { - RSA_EVENT_COMPLETE = 0, /* rsa event completed */ - RSA_EVENT_VERIFY_SUCCESS, /* rsa event verify success */ - RSA_EVENT_VERIFY_FAILED, /* rsa event verify failed */ - RSA_EVENT_ERROR, /* rsa event error */ -} csi_rsa_event_t; - -typedef void (*csi_rsa_callback_t)(csi_rsa_t *rsa, csi_rsa_event_t event, void *arg); ///< Pointer to \ref csi_rsa_callback_t : RSA Event call back. - -/** - \brief Initialize RSA Interface. 1. Initializes the resources needed for the RSA interface 2.registers event callback function - \param[in] rsa RSA handle to operate. - \param[in] idx Device id - \return Error code \ref csi_error_t -*/ -csi_error_t csi_rsa_init(csi_rsa_t *rsa, uint32_t idx); - -/** - \brief De-initialize RSA Interface. stops operation and releases the software resources used by the interface - \param[in] rsa RSA handle to operate. - \return none -*/ -void csi_rsa_uninit(csi_rsa_t *rsa); - -/** - \brief Generate rsa key pair. - \param[in] rsa RSA handle to operate. - \param[out] context Pointer to the rsa context - \return Error code \ref csi_error_t -*/ -csi_error_t csi_rsa_gen_key(csi_rsa_t *rsa, csi_rsa_context_t *context); - -/** - \brief Encrypt - \param[in] rsa RSA handle to operate. - \param[in] context Pointer to the rsa context - \param[in] src Pointer to the source data. - \param[in] src_size The source data len - \param[out] out Pointer to the result buffer - \return Error code \ref csi_error_t -*/ -csi_error_t csi_rsa_encrypt(csi_rsa_t *rsa, csi_rsa_context_t *context, void *src, uint32_t src_size, void *out); - -/** - \brief decrypt - \param[in] rsa RSA handle to operate. - \param[in] context Pointer to the rsa context - \param[in] src Pointer to the source data. - \param[in] src_size The source data len - \param[out] out Pointer to the result buffer - \param[out] out_size The result size - \return Error code \ref csi_error_t -*/ -csi_error_t csi_rsa_decrypt(csi_rsa_t *rsa, csi_rsa_context_t *context, void *src, uint32_t src_size, void *out, uint32_t *out_size); - -/** - \brief RSA sign - \param[in] rsa RSA handle to operate. - \param[in] context Pointer to the rsa context - \param[in] src Pointer to the source data. - \param[in] src_size The source data len - \param[out] signature Pointer to the signature - \param[in] hash_type The source data hash type - \return Error code \ref csi_error_t -*/ -csi_error_t csi_rsa_sign(csi_rsa_t *rsa, csi_rsa_context_t *context, void *src, uint32_t src_size, void *signature, csi_rsa_hash_type_t hash_type); - -/** - \brief RSA verify - \param[in] rsa RSA handle to operate. - \param[in] context Pointer to the rsa context - \param[in] src Pointer to the source data. - \param[in] src_size The source data len - \param[in] signature Pointer to the signature - \param[in] sig_size The signature size - \param[in] hash_type The source data hash type - \return Verify result -*/ -bool csi_rsa_verify(csi_rsa_t *rsa, csi_rsa_context_t *context, void *src, uint32_t src_size, void *signature, uint32_t sig_size, csi_rsa_hash_type_t hash_type); - -/** - \brief Get big prime data - \param[in] rsa RSA handle to operate. - \param[in] p Pointer to the prime - \param[in] bit_length Pointer to the prime bit length - \return Error code \ref csi_error_t -*/ -csi_error_t csi_rsa_get_prime(csi_rsa_t *rsa, void *p, uint32_t bit_length); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_RSA_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/rtc.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/rtc.h deleted file mode 100755 index 29742f3c..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/rtc.h +++ /dev/null @@ -1,148 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/rtc.h - * @brief Header File for RTC Driver - * @version V1.0 - * @date 9. Oct 2020 - * @model rtc - ******************************************************************************/ - -#ifndef _DRV_RTC_H_ -#define _DRV_RTC_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/****** RTC time ******/ -typedef struct { - int tm_sec; ///< Second. [0-59] - int tm_min; ///< Minute. [0-59] - int tm_hour; ///< Hour. [0-23] - int tm_mday; ///< Day. [1-31] - int tm_mon; ///< Month. [0-11] - int tm_year; ///< Year-1900. [70- ] !NOTE:Set 100 mean 2000 - int tm_wday; ///< Day of week. [0-6 ] !NOTE:Set 0 mean Sunday - int tm_yday; ///< Days in year.[0-365] !NOTE:Set 0 mean January 1st -} csi_rtc_time_t; - -/****** definition for RTC ******/ -typedef struct csi_rtc csi_rtc_t; - -struct csi_rtc { - csi_dev_t dev; - void (*callback)(csi_rtc_t *rtc, void *arg); - void *arg; - void *priv; -}; - -/** - \brief Initialize RTC interface. Initializes the resources needed for the RTC interface - \param[in] rtc Handle to operate - \param[in] idx RTC index - \return Error code \ref csi_error_t -*/ -csi_error_t csi_rtc_init(csi_rtc_t *rtc, uint32_t idx); - -/** - \brief De-initialize RTC interface. Stops operation and releases the software resources used by the interface - \param[in] rtc Handle to operate - \return None -*/ -void csi_rtc_uninit(csi_rtc_t *rtc); - -/** - \brief Set system date and wait for synchro - \param[in] rtc Handle to operate - \param[in] rtctime Pointer to RTC time - \return Error code \ref csi_error_t -*/ -csi_error_t csi_rtc_set_time(csi_rtc_t *rtc, const csi_rtc_time_t *rtctime); - -/** - \brief Set system date but no wait - \param[in] rtc Handle to operate - \param[in] rtctime Pointer to RTC time - \return Error code \ref csi_error_t -*/ -csi_error_t csi_rtc_set_time_no_wait(csi_rtc_t *rtc, const csi_rtc_time_t *rtctime); - -/** - \brief Get system date - \param[in] rtc Handle to operate - \param[out] rtctime Pointer to RTC time - \return Error code \ref csi_error_t -*/ -csi_error_t csi_rtc_get_time(csi_rtc_t *rtc, csi_rtc_time_t *rtctime); - -/** - \brief Get alarm remaining time - \param[in] rtc Handle to operate - \return The remaining time(s) -*/ -uint32_t csi_rtc_get_alarm_remaining_time(csi_rtc_t *rtc); - -/** - \brief Config RTC alarm timer - \param[in] rtc Handle to operate - \param[in] rtctime Time to wake up - \param[in] callback Callback function - \param[in] arg Callback's param - \return Error code \ref csi_error_t -*/ -csi_error_t csi_rtc_set_alarm(csi_rtc_t *rtc, const csi_rtc_time_t *rtctime, void *callback, void *arg); - -/** - \brief Cancel the RTC alarm - \param[in] rtc Handle to operate - \return Error code \ref csi_error_t -*/ -csi_error_t csi_rtc_cancel_alarm(csi_rtc_t *rtc); - -/** - \brief Judge RTC is running - \param[in] rtc Handle to operate - \return - true - RTC is running - false - RTC is not running -*/ -bool csi_rtc_is_running(csi_rtc_t *rtc); - -/** - \brief Enable RTC power manage - \param[in] rtc Handle to operate - \return Error code \ref csi_error_t -*/ -csi_error_t csi_rtc_enable_pm(csi_rtc_t *rtc); - -/** - \brief Disable RTC power manage - \param[in] rtc Handle to operate - \return None -*/ -void csi_rtc_disable_pm(csi_rtc_t *rtc); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_RTC_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/sasc.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/sasc.h deleted file mode 100755 index 6a7f6a04..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/sasc.h +++ /dev/null @@ -1,144 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/sasc.h - * @brief Header File for SASC driver - * @version V1.0 - * @date 02. June 2020 - * @model sasc - ******************************************************************************/ -#ifndef _DRV_SASC_H_ -#define _DRV_SASC_H_ - - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif -typedef enum { - SASC_RW = 0, - SASC_RO = 1, - SASC_WO = 2, - SASC_AP_DENY = 3 -} csi_sasc_ap_t; - -typedef enum { - SASC_DI = 0, - SASC_DO = 1, - SASC_IO = 2, - SASC_DI_DENY = 3 -} csi_sasc_di_t; - -typedef enum { - SASC_RAM_4B = 5, - SASC_RAM_8B = 6, - SASC_RAM_16B = 7, - SASC_RAM_32B = 8, - SASC_RAM_64B = 9, - SASC_RAM_128B = 10, - SASC_RAM_256B = 11, - SASC_RAM_512B = 12, - SASC_RAM_1KB = 13, - SASC_RAM_2KB = 14, - SASC_RAM_4KB = 15, - SASC_RAM_8KB = 16, - SASC_RAM_16KB = 17, - SASC_RAM_32KB = 18, - SASC_RAM_64KB = 19, - SASC_RAM_128KB = 20, -} csi_sasc_ram_size_t; - -typedef enum { - SASC_FLASH_1S = 0, - SASC_FLASH_2S, - SASC_FLASH_4S, - SASC_FLASH_8S, - SASC_FLASH_16S, - SASC_FLASH_32S, - SASC_FLASH_64S, - SASC_FLASH_128S, - SASC_FLASH_256S, - SASC_FLASH_512S, - SASC_FLASH_1024S, - SASC_FLASH_2048S -} csi_sasc_flash_size_t; - -typedef struct { - csi_sasc_ap_t super_ap; - csi_sasc_ap_t user_ap; - csi_sasc_di_t super_di; - csi_sasc_di_t user_di; - bool is_secure; -} csi_sasc_attr_t; - -/** - \brief Config the sasc ram region attribute. - \param[in] region_id Config region index - \param[in] base_addr Config region base address. - \param[in] size config region size. - \param[in] attr Region attr. - \return Error code -*/ -csi_error_t csi_sasc_ram_config(uint8_t region_id, uint32_t base_addr, csi_sasc_ram_size_t size, csi_sasc_attr_t attr); - -/** - \brief Config the sasc flash region attribute. - \param[in] region_id Config region index - \param[in] base_addr Config region base address. - \param[in] size Config region size. - \param[in] attr Region attr. - \return Error code -*/ -csi_error_t csi_sasc_flash_config(uint8_t region_id, uint32_t base_addr, csi_sasc_flash_size_t size, csi_sasc_attr_t attr); - -/** - \brief Enable sasc ram config. - \param[in] region_id Region index - \return error code -*/ -csi_error_t csi_sasc_ram_enable(uint8_t region_id); - -/** - \brief Enable sasc flash config - \param[in] region_id Config region index - \return error code -*/ -csi_error_t csi_sasc_flash_enable(uint8_t region_id); - -/** - \brief Disable sasc ram config. - \param[in] region_id Region index - \return error code -*/ -csi_error_t csi_sasc_ram_disable(uint8_t region_id); - -/** - \brief Disable sasc flash config - \param[in] region_id Region index - \return error code -*/ -csi_error_t csi_sasc_flash_disable(uint8_t region_id); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_SASC_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/sdif.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/sdif.h deleted file mode 100755 index 0508912b..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/sdif.h +++ /dev/null @@ -1,441 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/sdif.h - * @brief Header File for SDIF Driver - * @version V1.0 - * @date 28. June 2020 - * @model sdif - ******************************************************************************/ -#ifndef _DRV_SDIF_H_ -#define _DRV_SDIF_H_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -typedef void *sdif_handle_t; - -/*! @brief Construct a status code value from a group and code number. */ -#define MAKE_STATUS(group, code) ((((group)*100) + (code))) - -/*! @brief Status group numbers. */ -enum _status_groups { - kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ - kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ - kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ - kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ -}; - -/*! @brief Generic status return codes. */ -enum _generic_status { - kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), - kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), - kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), - kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), - kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), - kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), - kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), -}; - -/*! @brief SDIF status */ -enum _sdif_status { - kStatus_SDIF_DescriptorBufferLenError = MAKE_STATUS(kStatusGroup_SDIF, 0U), /*!< Set DMA descriptor failed */ - kStatus_SDIF_InvalidArgument = MAKE_STATUS(kStatusGroup_SDIF, 1U), /*!< invalid argument status */ - kStatus_SDIF_SyncCmdTimeout = MAKE_STATUS(kStatusGroup_SDIF, 2U), /*!< sync command to CIU timeout status */ - kStatus_SDIF_SendCmdFail = MAKE_STATUS(kStatusGroup_SDIF, 3U), /*!< send command to card fail */ - kStatus_SDIF_SendCmdErrorBufferFull = - MAKE_STATUS(kStatusGroup_SDIF, 4U), /*!< send command to card fail, due to command buffer full - user need to resend this command */ - kStatus_SDIF_DMATransferFailWithFBE = - MAKE_STATUS(kStatusGroup_SDIF, 5U), /*!< DMA transfer data fail with fatal bus error , - to do with this error :issue a hard reset/controller reset*/ - kStatus_SDIF_DMATransferDescriptorUnavailable = - MAKE_STATUS(kStatusGroup_SDIF, 6U), /*!< DMA descriptor unavailable */ - kStatus_SDIF_DataTransferFail = MAKE_STATUS(kStatusGroup_SDIF, 6U), /*!< transfer data fail */ - kStatus_SDIF_ResponseError = MAKE_STATUS(kStatusGroup_SDIF, 7U), /*!< response error */ - kStatus_SDIF_DMAAddrNotAlign = MAKE_STATUS(kStatusGroup_SDIF, 8U), /*!< DMA address not align */ -}; - -/*! @brief Type used for all status and error return values. */ -typedef int32_t status_t; - -/*! @brief Computes the number of elements in an array. */ -#if !defined(ARRAY_SIZE) -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) -#endif - -/*! Macro to change a value to a given size aligned value */ -#define SDK_SIZEALIGN(var, alignbytes) \ - ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1))) - -///< #define assert(__e) ((void)0) -/*! @name Min/max macros */ -#if !defined(MIN) -#define MIN(a, b) ((a) < (b) ? (a) : (b)) -#endif - -#if !defined(MAX) -#define MAX(a, b) ((a) > (b) ? (a) : (b)) -#endif - -#define SDK_ALIGN(var, alignbytes) var - -static inline unsigned long cpu_to_dma(unsigned long addr) -{ - return addr; -} - -static inline unsigned long *ptr_cpu_to_dma(unsigned long *addr) -{ - return (unsigned long *)cpu_to_dma((unsigned long)addr); -} - -typedef enum { - SDIF_ERROR_CMD_CRC_FAIL = (1), ///< Command response received (but CRC check failed) - SDIF_ERROR_DATA_CRC_FAIL, ///< Data block sent/received (CRC check failed) - SDIF_ERROR_CMD_RSP_TIMEOUT, ///< Command response timeout - SDIF_ERROR_DATA_TIMEOUT, ///< Data timeout - SDIF_ERROR_TX_UNDERRUN, ///< Transmit FIFO underrun - SDIF_ERROR_RX_OVERRUN, ///< Receive FIFO overrun - SDIF_ERROR_ADDR_MISALIGNED, ///< Misaligned address - SDIF_ERROR_BLOCK_LEN_ERR, ///< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length - SDIF_ERROR_ERASE_SEQ_ERR, ///< An error in the sequence of erase command occurs - SDIF_ERROR_BAD_ERASE_PARAM, ///< An invalid selection for erase groups - SDIF_ERROR_WRITE_PROT_VIOLATION, ///< Attempt to program a write protect block - SDIF_ERROR_LOCK_UNLOCK_FAILED, ///< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card - SDIF_ERROR_COM_CRC_FAILED, ///< CRC check of the previous command failed - SDIF_ERROR_ILLEGAL_CMD, ///< Command is not legal for the card state - SDIF_ERROR_CARD_ECC_FAILED, ///< Card internal ECC was applied but failed to correct the data - SDIF_ERROR_CC_ERR, ///< Internal card controller error - SDIF_ERROR_GENERAL_UNKNOWN_ERR, ///< General or unknown error - SDIF_ERROR_STREAM_READ_UNDERRUN, ///< The card could not sustain data reading in stream rmode - SDIF_ERROR_STREAM_WRITE_OVERRUN, ///< The card could not sustain data programming in stream mode - SDIF_ERROR_CID_CSD_OVERWRITE, ///< CID/CSD overwrite error - SDIF_ERROR_WP_ERASE_SKIP, ///< Only partial address space was erased - SDIF_ERROR_CARD_ECC_DISABLED, ///< Command has been executed without using internal ECC - SDIF_ERROR_ERASE_RESET, ///< Erase sequence was cleared before executing because an out - SDIF_ERROR_AKE_SEQ_ERR, ///< Error in sequence of authentication - SDIF_ERROR_INVALID_VOLTRANGE, ///< Error in case of invalid voltage range - SDIF_ERROR_ADDR_OUT_OF_RANGE, ///< Error when addressed block is out of range - SDIF_ERROR_REQUEST_NOT_APPLICABLE, ///< Error when command request is not applicable - SDIF_ERROR_UNSUPPORTED_FEATURE, ///< Error when feature is not insupported -} sdif_error_e; - -/* Host controller capabilities flag mask */ -typedef enum { - SDIF_SUPPORT_HIGH_SPEED = 0x1U, ///< Support high-speed - SDIF_SUPPORT_DMA_SPEED = 0x2U, ///< Support DMA - SDIF_SUPPORT_USPEND_RESUME = 0x4U, ///< Support suspend/resume - SDIF_SUPPORT_V330 = 0x8U, ///< Support voltage 3.3V - SDIF_SUPPORT_4BIT = 0x10U, ///< Support 4 bit mode - SDIF_SUPPORT_8BIT = 0x20U, ///< Support 8 bit mode -} sdif_capability_flag_e; - -/* \brief define the internal DMA mode */ -typedef enum { - SDIF_CHAIN_DMA_MODE = 0x01U, ///< one descriptor with one buffer,but one descriptor point to another - SDIF_DUAL_DMA_MODE = 0x02U, ///< dual mode is one descriptor with two buffer -} sdif_dma_mode_e; - -/* The command type */ -typedef enum { - SDIF_CARD_COMMAND_NORMAL = 0U, ///< Normal command - SDIF_CARD_COMMAND_SUSPEND = 1U, ///< Suspend command - SDIF_CARD_COMMAND_RESUME = 2U, ///< Resume command - SDIF_CARD_COMMAND_ABORT = 3U, ///< Abort command -} sdif_card_command_type_e; - -/* The command response type */ -typedef enum { - SDIF_CARD_RESPONSE_NONE = 0U, ///< Response type: none - SDIF_CARD_RESPONSE_R1 = 1U, ///< Response type: R1 - SDIF_CARD_RESPONSE_R1b = 2U, ///< Response type: R1b - SDIF_CARD_RESPONSE_R2 = 3U, ///< Response type: R2 - SDIF_CARD_RESPONSE_R3 = 4U, ///< Response type: R3 - SDIF_CARD_RESPONSE_R4 = 5U, ///< Response type: R4 - SDIF_CARD_RESPONSE_R5 = 6U, ///< Response type: R5 - SDIF_CARD_RESPONSE_R5b = 7U, ///< Response type: R5b - SDIF_CARD_RESPONSE_R6 = 8U, ///< Response type: R6 - SDIF_CARD_RESPONSE_R7 = 9U, ///< Response type: R7 -} sdif_card_response_type_e; - -/* \brief define the card bus width type */ -typedef enum { - SDIF_BUS_1BIT_WIDTH = 0U, ///< 1bit bus width, 1bit mode and 4bit mode share one register bit - SDIF_BUS_4BIT_WIDTH = 1U, ///< 4bit mode mask - SDIF_BUS_8BIT_WIDTH = 2U, ///< support 8 bit mode -} sdif_bus_width_e; - -/* \brief Defines the internal DMA configure structure. */ -typedef struct { - bool enable_fix_burst_len; ///< fix burst len enable/disable flag,When set, the AHB will - ///< use only SINGLE, INCR4, INCR8 or INCR16 during start of - ///< normal burst transfers. When reset, the AHB will use SINGLE - ///< and INCR burst transfer operations - - sdif_dma_mode_e mode; ///< define the DMA mode */ - - - uint32_t *dma_des_buffer_start_addr; ///< internal DMA descriptor start address - uint32_t dma_des_buffer_len; ///< internal DMA buffer descriptor buffer len ,user need to pay attention to the - ///< dma descriptor buffer length if it is bigger enough for your transfer - uint8_t dma_dws_skip_len; ///< define the descriptor skip length ,the length between two descriptor - ///< this field is special for dual DMA mode -} sdif_dma_config_t; - -/* \brief sdif callback functions. */ -typedef struct { - void (*card_inserted)(uint32_t idx, void *user_data); ///< card insert call back - void (*card_removed)(uint32_t idx, void *user_data); ///< card remove call back - void (*sdif_interrupt)(uint32_t idx, void *user_data); ///< SDIF card interrupt occurs - void (*dma_des_unavailable)(uint32_t idx, void *user_data);///< DMA descriptor unavailable - void (*command_reload)(uint32_t idx, void *user_data); ///< command buffer full,need re-load - void (*transfer_complete)(uint32_t idx, - void *state, - int32_t status, - void *user_data); /// -#include -#include - - -typedef enum { - SENSOR_VDS_3V3_3V3 = 1, - SENSOR_VDS_2V5_3V3, - SENSOR_VDS_1V8_1V8, - SENSOR_VDS_1V5_1V8, - SENSOR_VDS_1V2_1V2, - SENSOR_VDS_1V1_1V2 -}drv_sensor_vds_t; - -typedef enum { - SENSOR_VHS_RANGE_15 = 0, - SENSOR_VHS_RANGE_12, - SENSOR_VHS_RANGE_9, - SENSOR_VHS_RANGE_6, -}drv_sensor_vhs_t; - -typedef enum { - SENSOR_VLS_RANGE_6 = 0, - SENSOR_VLS_RANGE_9, - SENSOR_VLS_RANGE_12, - SENSOR_VLS_RANGE_15, -}drv_sensor_vls_t; - -typedef enum { - SENSOR_TDHS_NEG_55 = 0, ///< -55 - SENSOR_TDHS_NEG_50, - SENSOR_TDHS_NEG_45, - SENSOR_TDHS_NEG_40, - SENSOR_TDHS_NEG_35, - SENSOR_TDHS_NEG_30, - SENSOR_TDHS_NEG_25, - SENSOR_TDHS_NEG_20, - SENSOR_TDHS_NEG_15, - SENSOR_TDHS_NEG_10, - SENSOR_TDHS_NEG_5, - SENSOR_TDHS_NEG_0, - SENSOR_TDHS_POS_5, ///< +5 - SENSOR_TDHS_POS_10, - SENSOR_TDHS_POS_15, - SENSOR_TDHS_POS_20, - SENSOR_TDHS_POS_25, - SENSOR_TDHS_POS_30, - SENSOR_TDHS_POS_35, - SENSOR_TDHS_POS_40, - SENSOR_TDHS_POS_45, - SENSOR_TDHS_POS_50, - SENSOR_TDHS_POS_55, - SENSOR_TDHS_POS_60, - SENSOR_TDHS_POS_65, - SENSOR_TDHS_POS_70, - SENSOR_TDHS_POS_75, - SENSOR_TDHS_POS_80, - SENSOR_TDHS_POS_85, - SENSOR_TDHS_POS_90, - SENSOR_TDHS_POS_95, - SENSOR_TDHS_POS_100, - SENSOR_TDHS_POS_105, - SENSOR_TDHS_POS_110, - SENSOR_TDHS_POS_115, - SENSOR_TDHS_POS_120, - SENSOR_TDHS_POS_125 -}drv_sensor_tdhs_t; - -typedef enum { - SENSOR_TDLS_NEG_55 = 0, ///< -55 - SENSOR_TDLS_NEG_50, - SENSOR_TDLS_NEG_45, - SENSOR_TDLS_NEG_40, - SENSOR_TDLS_NEG_35, - SENSOR_TDLS_NEG_30, - SENSOR_TDLS_NEG_25, - SENSOR_TDLS_NEG_20, - SENSOR_TDLS_NEG_15, - SENSOR_TDLS_NEG_10, - SENSOR_TDLS_NEG_5, - SENSOR_TDLS_NEG_0, - SENSOR_TDLS_POS_5, ///< +5 - SENSOR_TDLS_POS_10, - SENSOR_TDLS_POS_15, - SENSOR_TDLS_POS_20, -}drv_sensor_tdls_t; - -typedef enum { - SENSOR_FHS_RANGE_50 = 0, - SENSOR_FHS_RANGE_30, - SENSOR_FHS_RANGE_10, - SENSOR_FHS_RANGE_5, -}drv_sensor_fhs_t; - -typedef enum { - SENSOR_FLS_RANGE_50 = 0, - SENSOR_FLS_RANGE_30, - SENSOR_FLS_RANGE_10, - SENSOR_FLS_RANGE_5, -}drv_sensor_fls_t; - -typedef enum { - SENSOR_FHS_FREQ_33M = 0, - SENSOR_FHS_FREQ_66M, - SENSOR_FHS_FREQ_24M, - SENSOR_FHS_FREQ_12M, - SENSOR_FHS_FREQ_99M, - SENSOR_FHS_FREQ_198M, - SENSOR_FHS_FREQ_72M, - SENSOR_FHS_FREQ_36M, -}drv_sensor_freq_t; - -typedef enum { - SENSOR_WARN_H = 0, - SENSOR_WARN_L, - SENSOR_WARN_RST, -}drv_sensor_warn_t; - -/** - \brief Initialize Sensor VD - \param[in] vds Voltage range - \param[in] vhs Voltage high threshold - \param[in] vls Voltage low threshold - \param[in] vtm Used to modify the threshold value of the voltage detection point - \return Error code -*/ -csi_error_t drv_sensor_vd_init(drv_sensor_vds_t vds,drv_sensor_vhs_t vhs,drv_sensor_vls_t vls,uint8_t vtm); - -/** - \brief Get vd warn - \param[in] warn Vd warn select - \return Vd warn code -*/ -uint32_t drv_sensor_vd_get_warn(drv_sensor_warn_t warn); - -/** - \brief Initialize Sensor td - \param[in] hs Temp high threshold - \param[in] ls Temp low threshold - \return Error code -*/ -csi_error_t drv_sensor_td_init(drv_sensor_tdhs_t hs,drv_sensor_tdls_t ls); - -/** - \brief Get td warn - \param[in] warn Td warn select - \return Td warn code -*/ -uint32_t drv_sensor_td_get_warn(drv_sensor_warn_t warn); - -/** - \brief Initialize Sensor FD - \param[in] hs Temp high threshold - \param[in] ls Temp low threshold - \return Error code -*/ -csi_error_t drv_sensor_fd_init(drv_sensor_freq_t freq,drv_sensor_fhs_t fhs,drv_sensor_fls_t fls); - -/** - \brief Get fd warn - \param[in] warn Fd warn select - \return FD warn code -*/ -uint32_t drv_sensor_fd_get_warn(drv_sensor_warn_t warn); - -#endif /* _DRV_SENSOR_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/sha.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/sha.h deleted file mode 100755 index 668b9dcc..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/sha.h +++ /dev/null @@ -1,128 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/sha.h - * @brief Header File for SHA Driver - * @version V1.0 - * @date 9. Oct 2020 - * @model sha - ******************************************************************************/ - -#ifndef _DRV_SHA_H_ -#define _DRV_SHA_H_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/****** SHA mode ******/ -typedef enum { - SHA_MODE_1 = 1U, /* SHA_1 mode */ - SHA_MODE_256, /* SHA_256 mode */ - SHA_MODE_224, /* SHA_224 mode */ - SHA_MODE_512, /* SHA_512 mode */ - SHA_MODE_384, /* SHA_384 mode */ - SHA_MODE_512_256, /* SHA_512_256 mode */ - SHA_MODE_512_224, /* SHA_512_224 mode */ - SHA_MODE_MD5 /* MD5 mode */ -} csi_sha_mode_t; - -/****** SHA State ******/ -typedef struct { - uint32_t busy : 1; /* Calculate busy flag */ - uint32_t error : 1; /* Calculate error flag */ -} csi_sha_state_t; - -/****** SHA Context ******/ -typedef struct { - csi_sha_mode_t mode; /* SHA mode */ - uint32_t total[2]; /* Number of bytes processed */ - uint32_t state[16]; /* Intermediate digest state */ - uint8_t buffer[128]; /* Data block being processed */ -} csi_sha_context_t; - -/****** SHA Event ******/ -typedef enum { - SHA_EVENT_COMPLETE = 0U, /*Calculate completed*/ - SHA_EVENT_ERROR /*Calculate error*/ -} csi_sha_event_t; - -/****** SHA Ctrl ******/ -typedef struct csi_sha csi_sha_t; -struct csi_sha{ - csi_dev_t dev; - void (*callback)(csi_sha_t *sha, csi_sha_event_t event, void *arg); /* SHA event callback for user */ - void *arg; /* SHA custom designed param passed to evt_cb */ - csi_dma_ch_t *dma_in; /* SHA in dma handle param */ - csi_sha_state_t state; /* SHA state */ - void *priv; -}; - -/** - \brief Initialize SHA Interface. Initializes the resources needed for the SHA interface - \param[in] sha Operate handle - \param[in] idx Index of SHA - \return Error code \ref csi_error_t -*/ -csi_error_t csi_sha_init(csi_sha_t *sha, uint32_t idx); - -/** - \brief De-initialize SHA Interface. Stops operation and releases the software resources used by the interface - \param[in] sha SHA handle to operate - \return None -*/ -void csi_sha_uninit(csi_sha_t *sha); - -/** - \brief Start the engine - \param[in] sha Handle to operate - \param[in] context Pointer to the SHA context \ref csi_sha_context_t - \param[in] mode SHA mode \ref csi_sha_mode_t - \return Error code \ref csi_error_t -*/ -csi_error_t csi_sha_start(csi_sha_t *sha, csi_sha_context_t *context, csi_sha_mode_t mode); - -/** - \brief Update the engine - \param[in] sha Handle to operate - \param[in] context Pointer to the SHA context \ref csi_sha_context_t - \param[in] input Pointer to the Source data - \param[in] size The data size - \return Error code \ref csi_error_t -*/ -csi_error_t csi_sha_update(csi_sha_t *sha, csi_sha_context_t *context, const void *input, uint32_t size); - -/** - \brief Finish the engine - \param[in] sha Handle to operate - \param[in] context Pointer to the SHA context \ref csi_sha_context_t - \param[out] output Pointer to the result data - \param[out] out_size Pointer to the result data size(bytes) - \return Error code \ref csi_error_t -*/ -csi_error_t csi_sha_finish(csi_sha_t *sha, csi_sha_context_t *context, void *output, uint32_t *out_size); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_SHA_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/spi.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/spi.h deleted file mode 100755 index 80f7e4d3..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/spi.h +++ /dev/null @@ -1,293 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/spi.h - * @brief Header File for SPI Driver - * @version V1.0 - * @date 08. Apr 2020 - * @model spi - ******************************************************************************/ - -#ifndef _DRV_SPI_H_ -#define _DRV_SPI_H_ - -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \enum csi_spi_mode_t - * \brief Function mode of spi - */ -typedef enum { - SPI_MASTER, ///< SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps - SPI_SLAVE, ///< SPI Slave (Output on MISO, Input on MOSI) -} csi_spi_mode_t; - -/** - * \enum csi_spi_frame_len_t - * \brief SPI data width (4bit ~ 16bit) - */ -typedef enum { - SPI_FRAME_LEN_4 = 4, - SPI_FRAME_LEN_5, - SPI_FRAME_LEN_6, - SPI_FRAME_LEN_7, - SPI_FRAME_LEN_8, - SPI_FRAME_LEN_9, - SPI_FRAME_LEN_10, - SPI_FRAME_LEN_11, - SPI_FRAME_LEN_12, - SPI_FRAME_LEN_13, - SPI_FRAME_LEN_14, - SPI_FRAME_LEN_15, - SPI_FRAME_LEN_16 -} csi_spi_frame_len_t; - -/** - * \enum csi_spi_format_t - * \brief Timing format of spi - */ -typedef enum { - SPI_FORMAT_CPOL0_CPHA0 = 0, ///< Clock Polarity 0, Clock Phase 0 - SPI_FORMAT_CPOL0_CPHA1, ///< Clock Polarity 0, Clock Phase 1 - SPI_FORMAT_CPOL1_CPHA0, ///< Clock Polarity 1, Clock Phase 0 - SPI_FORMAT_CPOL1_CPHA1, ///< Clock Polarity 1, Clock Phase 1 -} csi_spi_cp_format_t; - -/** - * \enum csi_spi_event_t - * \brief Signaled event for user by driver - */ -typedef enum { - SPI_EVENT_SEND_COMPLETE, ///< Data Send completed. Occurs after call to csi_spi_send_async to indicate that all the data has been send over - SPI_EVENT_RECEIVE_COMPLETE, ///< Data Receive completed. Occurs after call to csi_spi_receive_async to indicate that all the data has been received - SPI_EVENT_SEND_RECEIVE_COMPLETE, ///< Data Send_receive completed. Occurs after call to csi_spi_send_receive_async to indicate that all the data has been send_received - SPI_EVENT_ERROR_OVERFLOW, ///< Data overflow: Receive overflow - SPI_EVENT_ERROR_UNDERFLOW, ///< Data underflow: Transmit underflow - SPI_EVENT_ERROR ///< Master Mode Fault (SS deactivated when Master).Occurs in master mode when Slave Select is deactivated and indicates Master Mode Fault -} csi_spi_event_t; - -/** - * \struct csi_spi_t - * \brief Ctrl block of spi instance - */ -typedef struct csi_spi csi_spi_t; -struct csi_spi { - csi_dev_t dev; ///< Hw-device info - void (*callback)(csi_spi_t *spi, csi_spi_event_t event, void *arg); ///< User callback ,signaled by driver event - void *arg; ///< User private param ,passed to user callback - uint8_t *tx_data; ///< Output data buf - uint32_t tx_size; ///< Output data size specified by user - uint8_t *rx_data; ///< Input data buf - uint32_t rx_size; ///< Input data size specified by user - csi_error_t (*send)(csi_spi_t *spi, const void *data, uint32_t size); ///< The send_async func - csi_error_t (*receive)(csi_spi_t *spi, void *data, uint32_t size); ///< The receive_async func - csi_error_t (*send_receive)(csi_spi_t *spi, const void *data_out, void *data_in, uint32_t size); ///< The send_receive_async func - csi_state_t state; ///< Peripheral state - csi_dma_ch_t *tx_dma; - csi_dma_ch_t *rx_dma; - void *priv; -}; - -/** - \brief Initialize SPI Interface - Initialize the resources needed for the SPI instance - \param[in] spi SPI handle - \param[in] idx SPI instance index - \return Error code -*/ -csi_error_t csi_spi_init(csi_spi_t *spi, uint32_t idx); - -/** - \brief De-initialize SPI Interface - stops Operation and releases the software resources used by the spi instance - \param[in] spi Handle - \return None -*/ -void csi_spi_uninit(csi_spi_t *spi); - -/** - \brief Attach the callback handler to SPI - \param[in] spi Operate handle - \param[in] callback Callback function - \param[in] arg User can define it by himself as callback's param - \return Error code -*/ -csi_error_t csi_spi_attach_callback(csi_spi_t *spi, void *callback, void *arg); - -/** - \brief Detach the callback handler - \param[in] spi Operate handle - \return None -*/ -void csi_spi_detach_callback(csi_spi_t *spi); - -/** - \brief Config spi mode (master or slave) - \param[in] spi SPI handle - \param[in] mode The mode of spi (master or slave) - \return Error code -*/ -csi_error_t csi_spi_mode(csi_spi_t *spi, csi_spi_mode_t mode); - -/** - \brief Config spi cp format - \param[in] spi SPI handle - \param[in] format SPI cp format - \return Error code -*/ -csi_error_t csi_spi_cp_format(csi_spi_t *spi, csi_spi_cp_format_t format); - -/** - \brief Config spi frame len - \param[in] spi SPI handle - \param[in] length SPI frame len - \return Error code -*/ -csi_error_t csi_spi_frame_len(csi_spi_t *spi, csi_spi_frame_len_t length); - -/** - \brief Config spi work frequence - \param[in] spi SPI handle - \param[in] baud SPI work baud - \return the actual config frequency -*/ -uint32_t csi_spi_baud(csi_spi_t *spi, uint32_t baud); - -/** - \brief Sending data to SPI transmitter,(received data is ignored) - blocking mode ,return unti all data has been sent or err happened - \param[in] spi Handle to operate - \param[in] data Pointer to buffer with data to send to SPI transmitter - \param[in] size Number of data to send(byte) - \param[in] timeout Unit in mini-second - \return If send successful, this function shall return the num of data witch is sent successful - otherwise, the function shall return Error code -*/ -int32_t csi_spi_send(csi_spi_t *spi, const void *data, uint32_t size, uint32_t timeout); - -/** - \brief Sending data to SPI transmitter,(received data is ignored) - non-blocking mode,transfer done event will be signaled by driver - \param[in] spi Handle to operate - \param[in] data Pointer to buffer with data to send to SPI transmitter - \param[in] size Number of data items to send(byte) - \return Error code -*/ -csi_error_t csi_spi_send_async(csi_spi_t *spi, const void *data, uint32_t size); - -/** - \brief Receiving data from SPI receiver - blocking mode, return untill curtain data items are readed - \param[in] spi Handle to operate - \param[out] data Pointer to buffer for data to receive from SPI receiver - \param[in] size Number of data items to receive(byte) - \param[in] timeout Unit in mini-second - \return If receive successful, this function shall return the num of data witch is received successful - otherwise, the function shall return Error code -*/ -int32_t csi_spi_receive(csi_spi_t *spi, void *data, uint32_t size, uint32_t timeout); - -/** - \brief Receiving data from SPI receiver - not-blocking mode, event will be signaled when receive done or err happend - \param[in] spi Handle to operate - \param[out] data Pointer to buffer for data to receive from SPI receiver - \param[in] size Number of data items to receive(byte) - \return Error code -*/ -csi_error_t csi_spi_receive_async(csi_spi_t *spi, void *data, uint32_t size); - -/** - \brief Dulplex,sending and receiving data at the same time - \ref csi_spi_event_t is signaled when operation completes or error happens - \ref csi_spi_get_state can get operation status - blocking mode, this function returns after operation completes or error happens - \param[in] spi SPI handle to operate - \param[in] data_out Pointer to buffer with data to send to SPI transmitter - \param[out] data_in Pointer to buffer for data to receive from SPI receiver - \param[in] size Data size(byte) - \return If transfer successful, this function shall return the num of data witch is transfer successful, - otherwise, the function shall return Error code -*/ -int32_t csi_spi_send_receive(csi_spi_t *spi, const void *data_out, void *data_in, uint32_t size, uint32_t timeout); - -/** - \brief Transmit first then receive ,receive will begin after transmit is done - if non-blocking mode, this function only starts the transfer, - \ref csi_spi_event_t is signaled when operation completes or error happens - \ref csi_spi_get_state can get operation status - \param[in] spi SPI handle to operate - \param[in] data_out Pointer to buffer with data to send to SPI transmitter - \param[out] data_in Pointer to buffer for data to receive from SPI receiver - \param[in] size Data size(byte) - \return Error code -*/ -csi_error_t csi_spi_send_receive_async(csi_spi_t *spi, const void *data_out, void *data_in, uint32_t size); - -/* - \brief Set slave select num. Only valid for master - \param[in] handle SPI handle to operate - \param[in] slave_num SPI slave num - \return None - */ -void csi_spi_select_slave(csi_spi_t *spi, uint32_t slave_num); - -/** - \brief Link DMA channel to spi device - \param[in] spi SPI handle to operate - \param[in] tx_dma The DMA channel handle for send, when it is NULL means to unlink the channel - \param[in] rx_dma The DMA channel handle for receive, when it is NULL means to unlink the channel - \return Error code -*/ -csi_error_t csi_spi_link_dma(csi_spi_t *spi, csi_dma_ch_t *tx_dma, csi_dma_ch_t *rx_dma); - -/** - \brief Get the state of spi device - \param[in] spi SPI handle to operate - \param[out] state The state of spi device - \return Error code -*/ -csi_error_t csi_spi_get_state(csi_spi_t *spi, csi_state_t *state); - -/** - \brief Enable spi power manage - \param[in] spi SPI handle to operate - \return Error code -*/ -csi_error_t csi_spi_enable_pm(csi_spi_t *spi); - -/** - \brief Disable spi power manage - \param[in] spi SPI handle to operate - \return Error code -*/ -void csi_spi_disable_pm(csi_spi_t *spi); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_SPI_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/spiflash.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/spiflash.h deleted file mode 100755 index 64a24ca9..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/spiflash.h +++ /dev/null @@ -1,303 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/spiflash.h - * @brief Header File for SPIFLASH Driver - * @version V1.0 - * @date 02. June 2020 - * @model spiflash - ******************************************************************************/ -#ifndef _DRV_SPIFLASH_H_ -#define _DRV_SPIFLASH_H_ - -#include -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** -* \brief Build a flash ID -* \param [in] vendor_id Vendor id(8bit) -* \param [in] device_id Flash device id (ID15~ID0) 16bit -* \return 24bit flash id -*/ -#define FLASH_ID_BUILD(VENDOR_ID,DEVICE_ID) - -/** -* \struct csi_spiflash_lock_info_t -* \ flash use status register 1 to protect data in memory array -* \ different flash vendor support different protect region (top/bottom/none) -* also support different protect number -* status1 register bif field show as follow -* 7 |6 |5 |4 |3 |2 |1 |0 -* --------------------------------------------------------------------- -* vensor def | vendor def | vendor def | BP2 | BP1 | BP0 | WEL | BUSY -* \ Protect type -* \ Protect block size : Vendor define ,user should check flash datasheet of vendor -* : Use w25q64fw as example , min protect block size is 128 KB -* \ TOP : Protect address from flash top address -* \ BOTTOM : Protect address from flash bottom address -* \ SEC : Protect addres base on sector unit and protect region only must not exceed one block -* \ BPx : Protect start addres base on TOP/BOTTOM feature,and BPx value denote protect number -* \ BP[x..0]'s value : 2^(n-1) protect block unit, ex, BP[x..0] = 5, protect block number = 2^(5-1) = 16 -* \ If BP[x..0] = 0 denote protect none -* \ If BP[x..0]'s all bis is 1 ,denote protect all flash -* \ -* \ NOTE: -* \ only support SEC = 0 -* \ only support CMP = 0 -* \ -* -* Sample table portion for 8MB flash (Winbond w25q64fw): -* -* SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion -* -------------------------------------------------------------------------- -* X | X | 0 | 0 | 0 | NONE | NONE -* 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64 -* 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32 -* 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16 -* 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8 -* 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 -* 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 -* X | X | 1 | 1 | 1 | 8 MB | ALL -* ------|-------|-------|-------|-------|---------------|------------------- -* 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64 -* 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32 -* 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16 -* 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8 -* 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4 -* 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2 -* -*/ -typedef enum { - LOCK_TP_NONE, - LOCK_TP_TOP, - LOCK_TP_BOTTOM, - LOCK_TP_DUAL -} csi_spiflash_lock_region_t; -typedef enum { - SPIFLASH_DATA_1_LINE = 1, - SPIFLASH_DATA_2_LINES = 2, - SPIFLASH_DATA_4_LINES = 4 -} csi_spiflash_data_line_t; -typedef union { - csi_spi_t spi; - csi_qspi_t qspi; -} csi_spi_qspi_t; - -/** -\brief Flash information -*/ -typedef struct { - char *flash_name; ///< Name string of spiflash - uint32_t flash_id; ///< JEDEC ID = manufature ID <<16 | device ID (ID15~ID0) - uint32_t flash_size; ///< Flash chip size - uint32_t xip_addr; ///< If use qspi controler to access flash ,code can be ececuted on flash ,the addr is xip addr - uint32_t sector_size; ///< Sector size - uint32_t page_size; ///< Page size for read or program -} csi_spiflash_info_t; - -typedef struct{ - struct{ - uint8_t buswidth; ///< cmd buswidth - }cmd; - struct { - uint8_t buswidth; ///< addr buswidth - }addr; - struct { - uint8_t nbytes; ///< dummy bytes - }dummy; - struct { - uint8_t buswidth; ///< data buswidth - }data; -} csi_spiflash_cmd_t; - -/** -\brief Flash control block -*/ -typedef struct { - csi_spi_qspi_t spi_qspi; ///< Spi/qspi handle - void (*spi_cs_callback)(csi_gpio_pin_state_t value); - void *flash_prv_info; ///< Point to vendor private feature struct - int32_t (*spi_send)(void *spi, uint8_t cmd, uint32_t addr, uint32_t addr_size, const void *data, uint32_t size); - int32_t (*spi_receive)(void *spi, uint8_t cmd, uint32_t addr, uint32_t addr_size, void *data, uint32_t size); - csi_error_t (*set_cmd)(void *spi, csi_spiflash_cmd_t *cmd); - void *priv; ///< User private param -} csi_spiflash_t; - -/** - \brief Initialize SPIFLASH with spi controler and probe flash device - \param[in] spiflash SPIFLASH handle - \param[in] spi_idx SPI controler index - \param[in] spi_cs GPIO info for chip select,if NULL, not use gpio cs - \return Error code -*/ -csi_error_t csi_spiflash_spi_init(csi_spiflash_t *spiflash, uint32_t spi_idx, void *spi_cs_callback); - -/** - \brief Initialize SPIFLASH with qspi controler and probe flash device - \param[in] spiflash SPIFLASH handle - \param[in] qspi_idx QSPI controler index - \return Error code -*/ -csi_error_t csi_spiflash_qspi_init(csi_spiflash_t *spiflash, uint32_t qspi_idx, void *qspi_cs_callback); - -/** - \brief De-initialize SPIFLASH Interface based on spi controler. stops operation and releases the software resources used by the interface - \param[in] spiflash SPIFLASH handle to operate - \return Error code -*/ -void csi_spiflash_spi_uninit(csi_spiflash_t *spiflash); - -/** - \brief De-initialize SPIFLASH Interface based on qspi controler. stops operation and releases the software resources used by the interface - \param[in] spiflash SPIFLASH handle to operate - \return Error code -*/ -void csi_spiflash_qspi_uninit(csi_spiflash_t *spiflash); - - -/** - \brief Get flash device infomation - \param[in] spiflash SPIFLASH handle to operate - \param[in] flash_info User storage to get flash vendor info after flash init - \return spiflash_info_t -*/ -csi_error_t csi_spiflash_get_flash_info(csi_spiflash_t *spiflash, csi_spiflash_info_t *flash_info); - - -/** - \brief Read data from Flash - \param[in] spiflash SPIFLASH handle to operate - \param[in] offset Data address, offset address relative to zero - \param[out] data Pointer to a buffer storing the data read from Flash - \param[in] size Number of data items to read - \return If receive successful, this function shall return the num of data witch is received successful - otherwise, the function shall return Error code -*/ -int32_t csi_spiflash_read(csi_spiflash_t *spiflash, uint32_t offset, void *data, uint32_t size); - -/** - \brief Program data to Flash - \param[in] spiflash SPIFLASH handle to operate - \param[in] offset Data address, offset address relative to zero - \param[in] data Pointer to a buffer containing the data to be programmed to Flash. - \param[in] size Number of data items to program - \return If program successful, this function shall return the num of data witch is program successful, - otherwise, the function shall return Error code -*/ -int32_t csi_spiflash_program(csi_spiflash_t *spiflash, uint32_t offset, const void *data, uint32_t size); - -/** - \brief Erase Flash Sector - \param[in] spiflash SPIFLASH handle to operate - \param[in] offset Data address, offset address relative to zero - \param[in] size Length to be erased - \return Error code -*/ -csi_error_t csi_spiflash_erase(csi_spiflash_t *spiflash, uint32_t offset, uint32_t size); - -/** - \brief Read flash status register - \param[in] spiflash SPIFLASH handle to operate - \param[in] cmd_code Cmd code - \param[out] data Data buf to save flash status register - \param[in] size Register length in byte - \return Error code -*/ -csi_error_t csi_spiflash_read_reg(csi_spiflash_t *spiflash, uint8_t cmd_code, uint8_t *data, uint32_t size); - -/** - \brief Write status register - \param[in] spiflash SPIFLASH handle to operate - \param[in] cmd Cmd code - \param[out] data Data buf to save flash status register - \param[in] size Register length in byte - \return Error code -*/ -csi_error_t csi_spiflash_write_reg(csi_spiflash_t *spiflash, uint8_t cmd_code, uint8_t *data, uint32_t size); - - -/** - \brief Enable spiflash write protection - \param[in] spiflash SPIFLASH handle to operate - \param[in] offset Protect flash offset,offset need protect block size aligned - \param[in] size Lock size(byte) - \return Error code -*/ -csi_error_t csi_spiflash_lock(csi_spiflash_t *spiflash, uint32_t offset, uint32_t size); - -/** - \brief Enable spiflash write protection - \param[in] spiflash SPIFLASH handle to operate - \param[in] offset Protect flash offset,offset need protect block size aligned - \param[in] size Unlock size(byte) - \return Error code -*/ -csi_error_t csi_spiflash_unlock(csi_spiflash_t *spiflash, uint32_t offset, uint32_t size); - -/** - \brief check flash is locked(write protect) - \param[in] spiflash SPIFLASH handle to operate - \param[in] offset Protect flash offset,offset need protect block size aligned - \param[in] size Locked size(byte) - \return 0:unlocked if query region overlay with locked region 1: locked if query reigon is fully in locked region -*/ -int csi_spiflash_is_locked(csi_spiflash_t *spiflash, uint32_t offset, uint32_t size); - -/** - \brief Set QSPI data line - \param[in] spiflash SPIFLASH handle to operate - \param[in] line SPIFLASH data line mode - \return Error code -*/ -csi_error_t csi_spiflash_config_data_line(csi_spiflash_t *spiflash, csi_spiflash_data_line_t line); - -/** - \brief Set QSPI frequence - \param[in] spiflash SPIFLASH handle to operate - \param[in] hz SPIFLASH frequence - \return The actual config frequency -*/ -uint32_t csi_spiflash_frequence(csi_spiflash_t *spiflash, uint32_t hz); - -/** - \brief Flash power down. - \param[in] spiflash SPIFLASH handle to operate. - \return error code -*/ -csi_error_t csi_spiflash_release_power_down(csi_spiflash_t *spiflash); - -/** - \brief Flash power release. - \param[in] spiflash SPIFLASH handle to operate. - \return none -*/ -void csi_spiflash_power_down(csi_spiflash_t *spiflash); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_SPIFLASH_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/spinand.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/spinand.h deleted file mode 100644 index 8a011987..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/spinand.h +++ /dev/null @@ -1,321 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file spinand.h - * @brief header file for spinand driver - * @version V1.0 - * @date 17. Aug 2017 - * @model spinand - ******************************************************************************/ -#ifndef _DRV_NANDFLASH_H_ -#define _DRV_NANDFLASH_H_ - - -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#define SPINAND_DEF_SPEED (1000000) -#define SPIANND_DEF_MAX_WAIT_TIME (1000) ///< max wait time in ms - -typedef union { - csi_qspi_t qspi; ///< hold qspi object -} csi_nand_spi_qspi_t; - - -typedef struct { -uint32_t target; ///< target in chip -uint32_t lun; ///< lun in target -uint32_t plane; ///< plane number in lun -uint32_t block; ///< block index in lun -uint32_t page; ///< page index in lun -uint32_t offset; ///< column offset within page -}csi_nand_pos_t; - -typedef enum{ - SPI_MEM_NODATA, ///< no data portion - SPI_MEM_DATA_IN, ///< read data - SPI_MEM_DATA_OUT ///< write data -}csi_spi_mem_dir_t; - -typedef struct{ - - struct{ - uint8_t buswidth; ///< cmd buswidth - uint8_t opcode; ///< cmd code - }cmd; - - struct { - uint8_t buswidth; ///< addr buswidth - uint8_t nbytes; ///< bytes of addr - uint64_t val; ///< addr value - }addr; - - struct { - uint8_t nbytes; ///< dummy bytes - uint8_t buswidth; ///< bus width - }dummy; - - - struct { - uint8_t buswidth; ///< data buswidth - uint32_t nbytes; ///< data len - csi_spi_mem_dir_t dir; ///< data xfer dir - union{ - void* in; ///< read data buf ptr - void* out; ///< write datat buf ptr - }buf; - }data; - -}spi_mem_op_t; - -typedef struct { - const uint8_t *id; ///< point to chip id array - const uint8_t len; ///< id length -}csi_spinand_id_t; - -typedef struct { - uint8_t id[4]; ///< id data - uint8_t len; ///< id length -}csi_nand_id_t; - - -typedef struct{ - uint16_t strength; ///< number of hw-ecc engine bits - uint16_t step_size; ///< corect size by ecc per-step -}csi_nand_ecc_req_t; - -typedef struct { - uint32_t bits_per_cell; ///< bit per-cell - uint32_t pagesize; ///< page size - uint32_t oobsize; ///< spare area size - uint32_t pages_per_eraseblock; ///< pages per block - uint32_t eraseblocks_per_lun; ///< blocks per lun(logic unit number== max block index ) - uint32_t max_bad_eraseblocks_per_lun; ///< max bad blocks per lun - uint32_t planes_per_lun; ///< planes per-lun - uint32_t luns_per_target; ///< luns per die - uint32_t ntargets; ///< target index -}csi_nand_mem_layout_t; - - - -typedef struct { - char *model; ///< chip name of vendor - uint32_t flags; ///< chip-specific feature bits group - csi_spinand_id_t devid; ///< devid of chip - csi_nand_mem_layout_t memorg; ///< mem layout of chip - csi_nand_ecc_req_t eccreq; ///< ecc capabilty of chip - csi_error_t (*select_target)(void *spinand, uint32_t target); ///< select target - csi_error_t (*check_ecc_status)(void *spinand,uint8_t status); ///< check vendor specific ecc status -}csi_spinand_info_t; - - -typedef struct { - csi_error_t (*init) (void *spinand); ///< vendor chip inition - void (*uninit) (void *spinand); ///< vendor chip uninition -}csi_spinand_manufacturer_ops_t; - -typedef struct { - uint8_t id; ///< vendor id - char *name; ///< vendor name - const csi_spinand_info_t *chips; ///< vendor chip param - uint32_t nchips; ///< chips number supported - const csi_spinand_manufacturer_ops_t *ops; ///< vendor specific operations -}csi_spinand_manufacturer_t; - - -typedef struct { - char *model_name; ///< name of nand-device module - uint16_t page_size; ///< page-size of nand-device - uint16_t oob_size; ///< oob-size(spare size) of nand-device - uint16_t pages_per_block; ///< pages-per-block - uint16_t max_bad_blocks; ///< max possible bad blocks of nand-device - uint32_t total_blocks; ///< total blocks of nand-device -}csi_spinand_dev_params_t; - -typedef struct -{ - void *xfer_buf; ///< point to xfer data buf - uint32_t xfer_buf_len; ///< length of xfer buf ,count in byte - uint16_t rxfer_copy_offset; ///< copy offset from word-aligned buf - uint16_t rxfer_origin_len; ///< copy length from word-aligned buf -}csi_xfer_data_buf_t; - - -/** -\brief Flash control block -*/ -typedef struct { - #define SPINAND_SCRAT_BUF_LEN 4 ///< scratch buf len - csi_nand_spi_qspi_t spi_qspi; ///< Spi/qspi handle - uint8_t scractbuf[SPINAND_SCRAT_BUF_LEN]; ///< scracthbuf for read/write id or reg - uint8_t cur_target; ///< current target - uint16_t max_tx_size; ///< max tx op size - uint16_t max_rx_size; ///< max rx op size - csi_xfer_data_buf_t xfer; ///< xfer buf - csi_spinand_info_t *chip_info; ///< Point to vendor private feature struct - csi_spinand_manufacturer_t *maf; ///< point to manufacture - void (*spi_cs_callback)(csi_gpio_pin_state_t value); ///< gpio chip select for spi or qspi - csi_error_t (*spi_mem)(void *spinand,spi_mem_op_t *op); ///< spi-mem op function - void *priv; ///< User private param -} csi_spinand_t; - -typedef enum { - XFER_CPU_POLLING, ///< transfer by qspi with cpu polling mode - XFER_DMA, ///< transfer by qspi with external dma engine - XFER_INTR, ///< transfer by qspi with cpu-interrut -}csi_spinand_xfer_t; - -/** - \brief Initialize NANDFLASH with qspi controler and probe flash device - \param[in] spinand NANDFLASH handle - \param[in] qspi_idx QSPI controler index - \param[in] spi_cs_callback GPIO info for chip select,if NULL, not use gpio cs - \return Error code -*/ -csi_error_t csi_spinand_qspi_init(csi_spinand_t *spinand, uint32_t qspi_idx,void *gpio_cs_callback); - -/** - \brief De-initialize NANDFLASH Interface based on spi controler. stops operation and releases the software resources used by the interface - \param[in] spinand NANDFLASH handle to operate - \return Error code -*/ -void csi_spinand_qspi_uninit(csi_spinand_t *spinand); - -/** - \brief set xfer mode - \param[in] spinand NANDFLASH handle to operate - \param[in] xfer_mode please ref csi_spinand_xfer_t - \return Error code -*/ -csi_error_t csi_spinand_set_xfer_mode(csi_spinand_t *spinand,csi_spinand_xfer_t xfer_mode); - - -/** - \brief get flash device infomation - \param[in] spinand NANDFLASH handle to operate - \param[in] flash_info User storage to get flash vendor info after flash init - \return spinand_info_t -*/ - -csi_error_t csi_spinand_get_flash_info(csi_spinand_t *spinand, csi_spinand_dev_params_t *flash_info); - -/** - \brief Read data from Flash - \param[in] spinand NANDFLASH handle to operate - \param[in] offset Data address, offset address relative to zero - \param[out] data Pointer to a buffer storing the data read from Flash - \param[in] cnt Number of data items to read - \return If receive successful, this function shall return the num of data witch is received successfulful - otherwise, the function shall return Error code -*/ -int32_t csi_spinand_read(csi_spinand_t *spinand, uint64_t offset, void *data, uint32_t size); - - -/** - \brief Read spare data from specific page - \param[in] spinand NANDFLASH handle to operate - \param[in] page_addr page addr, address relative to zero, addr need page size aligned - \param[in] spare_offset offset address within the spare area of the page - \param[out] data Pointer to a buffer storing the data read from Flash - \param[in] size Number of data items to read - \return If receive successful, this function shall return the num of data witch is received successfully - otherwise, the function shall return Error code -*/ -int32_t csi_spinand_read_spare_data(csi_spinand_t *spinand,uint64_t page_addr,uint32_t spare_offset,void *data, uint32_t size); - -/** - \brief write data to Flash - \param[in] spinand NANDFLASH handle to operate - \param[in] offset Data address, offset address relative to zero - \param[in] data Pointer to a buffer containing the data to be programmed to Flash. - \param[in] size Number of data items to program - \return If program successful, this function shall return the num of data witch is programed successfully - otherwise, the function shall return Error code -*/ -int32_t csi_spinand_write(csi_spinand_t *spinand, uint64_t offset, const void *data, uint64_t size); - -/** - \brief write spare data to specific page - \param[in] spinand NANDFLASH handle to operate - \param[in] page_addr page addr, address relative to zero, addr need page size aligned - \param[in] spare_offset offset address within the spare area of the page - \param[out] data Pointer to a buffer storing the data write to Flash - \param[in] size Number of data items to write - \return If program successful, this function shall return the num of data witch is programed successfully - otherwise, the function shall return Error code -*/ -int32_t csi_spinand_write_spare_data(csi_spinand_t *spinand,uint64_t page_addr,uint32_t spare_offset,void *data, uint32_t size); - - -/** - \brief Erase Flash Sector - \param[in] spinand NANDFLASH handle to operate - \param[in] offset Data address, offset address relative to zero - \param[in] size Length to be erased - \param[out] last erased block addr - \return Error code -*/ -csi_error_t csi_spinand_erase(csi_spinand_t *spinand, uint64_t offset, uint64_t size, uint64_t *last_fail_addr); - -/** - \brief check whether the block is bad - \param[in] spinand NANDFLASH handle to operate - \param[in] block_addr block addr (count in bytes) - \return 1: bad 0: not bad <0 err code -*/ - - -int32_t csi_spinand_block_is_bad(csi_spinand_t *spinand,uint64_t block_addr); - -/** - \brief mark block as a bad block - \param[in] spinand NANDFLASH handle to operate - \param[in] block_addr block addr (count in bytes) - \return Error code -*/ -csi_error_t csi_spinand_block_mark_bad(csi_spinand_t *spinand, uint64_t block_addr); - -/** - \brief reset spinand device - \param[in] spinand NANDFLASH handle to operate - \return Error code -*/ -int32_t csi_spinand_reset(csi_spinand_t *spinand); - -/** - \brief Set QSPI frequence - \param[in] spinand NANDFLASH handle to operate - \param[in] hz NANDFLASH frequence - \return The actual config frequency -*/ -uint32_t csi_spinand_frequence(csi_spinand_t *spinand, uint32_t hz); - - - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_NANDFLASH_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/tee.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/tee.h deleted file mode 100755 index dc85c7b9..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/tee.h +++ /dev/null @@ -1,643 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -/****************************************************************************** - * @file drv/tee.h - * @brief Header File for TEE Driver - * @version V1.0 - * @date 12 Sep 2020 - * @model tee - ******************************************************************************/ -#ifndef _DRV_TEE_H_ -#define _DRV_TEE_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif -/****** TEE AES mode *****/ -typedef enum { - TEE_AES_MODE_ECB = 0, ///< TEE AES ECB mode - TEE_AES_MODE_CBC = 1, ///< TEE AES CBC mode - TEE_AES_MODE_MAX, ///< invaild mode -} -tee_aes_mode_e; - -/** - \brief TEE AES encrypt - \note Length should be a multiple of the block size (16 bytes) - After calling this function, the content of iv is updated. - \param[in] in Pointer to plaintext buffer - \param[in] in_len Plaintext buffer length - \param[in] key Pointer to secret key - \param[in] key_len Secret key size,must be 16 bytes for AES128,24 bytes for AES192 or 32byes for AES256 - \param[out] out Pointer to ciphertext buffer - \param[in] mode \ref tee_aes_mode_e - \return Return 0 if successful,otherwise error code -*/ -int32_t csi_tee_aes_encrypt(const uint8_t *in, uint32_t in_len, - const uint8_t *key, uint32_t key_len, - uint8_t iv[16], - uint8_t *out, - tee_aes_mode_e mode); - -/** - \brief TEE AES decrypt - \note Length should be a multiple of the block size (16 bytes) - After calling this function, the content of iv is updated. - \param[in] in Pointer to ciphertext buffer - \param[in] in_len Ciphertext buffer length - \param[in] key Pointer to secret key - \param[in] key_len Secret key size,must be 16 bytes for AES128,24 bytes for AES192 or 32byes for AES256 - \param[out] out Pointer to plaintext buffer - \param[in] mode \ref tee_aes_mode_e - \return Return 0 if successful,otherwise error code -*/ -int32_t csi_tee_aes_decrypt(const uint8_t *in, uint32_t in_len, - const uint8_t *key, uint32_t key_len, - uint8_t iv[16], - uint8_t *out, - uint32_t mode); - -/** - \brief TEE AES ECB encrypt - \note Length should be a multiple of the block size (16 bytes) - After calling this function, the content of iv is updated. - \param[in] in Pointer to plaintext buffer - \param[in] in_len Plaintext buffer length - \param[in] key Pointer to secret key - \param[in] key_len Secret key size,must be 16 bytes for AES128,24 bytes for AES192 or 32byes for AES256 - \param[out] out Pointer to ciphertext buffer - \return Return 0 if successful,otherwise error code -*/ -#define csi_tee_aes_encrypt_ecb(in, in_len, key, key_len, out) \ - csi_tee_aes_encrypt(in, in_len, key, key_len, NULL, out, TEE_AES_MODE_ECB) - -/** - \brief TEE AES ECB decrypt - \note Length should be a multiple of the block size (16 bytes) - After calling this function, the content of iv is updated. - \param[in] in Pointer to ciphertext buffer - \param[in] in_len Ciphertext buffer length - \param[in] key Pointer to secret key - \param[in] key_len Secret key size,must be 16 bytes for AES128,24 bytes for AES192 or 32byes for AES256 - \param[out] out Pointer to plaintext buffer - \return Return 0 if successful,otherwise error code -*/ -#define csi_tee_aes_decrypt_ecb(in, in_len, key, key_len, out) \ - csi_tee_aes_decrypt(in, in_len, key, key_len, NULL, out, TEE_AES_MODE_ECB) - -/** - \brief TEE AES CBC encrypt - \note Length should be a multiple of the block size (16 bytes) - After calling this function, the content of iv is updated. - \param[in] in Pointer to ciphertext buffer - \param[in] in_len Ciphertext buffer length - \param[in] key Pointer to secret key - \param[in] key_len Secret key size,must be 16 bytes for AES128,24 bytes for AES192 or 32byes for AES256 - \param[out] out Pointer to plaintext buffer - \return Return 0 if successful,otherwise error code -*/ -#define csi_tee_aes_encrypt_cbc(in, in_len, key, key_len, iv, out) \ - csi_tee_aes_encrypt(in, in_len, key, key_len, iv, out, TEE_AES_MODE_CBC) - -/** - \brief TEE AES CBC decrypt - \note Length should be a multiple of the block size (16 bytes) - After calling this function, the content of iv is updated. - \param[in] in Pointer to ciphertext buffer - \param[in] in_len Ciphertext buffer length - \param[in] key Pointer to secret key - \param[in] key_len Secret key size,must be 16 bytes for AES128,24 bytes for AES192 or 32byes for AES256 - \param[out] out Pointer to plaintext buffer - \return Return 0 if successful,otherwise error code -*/ -#define csi_tee_aes_decrypt_cbc(in, in_len, key, key_len, iv, out) \ - csi_tee_aes_decrypt(in, in_len, key, key_len, iv, out, TEE_AES_MODE_CBC) - -/** - \brief TEE BASE64 encode/decode - \param[in] in Pointer to input data buffer - \param[in] in_len Input data buffer length - \param[out] out Pointer to output data buffer - \param[out] out_len Output data buffer length - \param[in] is_encode 1 encode 0 decode - \param[in] wsafe Base64 websafe feature,set 1, replace "+/" with "-_" - \return Return 0 if successful,otherwise error code -*/ -int32_t csi_tee_base64(const uint8_t *in, uint32_t in_len, - uint8_t *out, uint32_t *out_len, - uint32_t is_encode, - uint32_t wsafe); - -/** - \brief TEE BASE64 encode - \param[in] in Pointer to input data buffer - \param[in] in_len Input data buffer length - \param[out] out Pointer to output data buffer - \param[out] out_len Output data buffer length - \return Return 0 if successful,otherwise error code -*/ -#define csi_tee_base64_encode(in,in_len,out,out_len) \ - csi_tee_base64(in,in_len,out,out_len,1,0) - -/** - \brief TEE BASE64 decode - \param[in] in Pointer to input data buffer - \param[in] in_len Input data buffer length - \param[out] out Pointer to output data buffer - \param[out] out_len Output data buffer length - \return Return 0 if successful,otherwise error code -*/ -#define csi_tee_base64_decode(in,in_len,out,out_len) \ - csi_tee_base64(in,in_len,out,out_len,0,0) - -/** - \brief TEE BASE64 web safe encode - \param[in] in Pointer to input data buffer - \param[in] in_len Input data buffer length - \param[out] out Pointer to output data buffer - \param[out] out_len Output data buffer length - \return Return 0 if successful,otherwise error code -*/ -#define csi_tee_base64_websafe_encode(in,in_len,out,out_len) \ - csi_tee_base64(in,in_len,out,out_len,1,1) - -/** - \brief TEE BASE64 web safe decode - \param[in] in Pointer to input data buffer - \param[in] in_len Input data buffer length - \param[out] out Pointer to output data buffer - \param[out] out_len Output data buffer length - \return Return 0 if successful,otherwise error code -*/ -#define csi_tee_base64_websafe_decode(in,in_len,out,out_len) \ - csi_tee_base64(in,in_len,out,out_len,0,1) - -/** - \brief TEE obtain CID from Key Provisioning - \param[out] out Pointer to cid buffer - \param[out] out_len CID buffer length,if cid obtain successfully, - out_len is updated to actual cid sizes - \return Return 0 if successful,otherwise error code -*/ -int32_t csi_tee_get_cid(uint8_t *out, uint32_t *out_len); - -/****** lpm mode *****/ -typedef enum { - TEE_LPM_MODE_WAIT = 0, ///< lpm wait - TEE_LPM_MODE_DOZE = 1, ///< lpm doze - TEE_LPM_MODE_STOP = 2, ///< lpm stop - TEE_LPM_MODE_STANDBY = 3, ///< lpm standby - TEE_LPM_MODE_CLOCK = 4, ///< lpm clock gate - TEE_LPM_MODE_MAX, -} tee_lpm_mode_e; - -/** - \brief TEE set low power mode - \param[in] gate Not use for now - \param[in] irqid Not use for now - \param[in] mode \ref tee_lpm_mode_e - \return Return 0 if successful,otherwise error code -*/ -int32_t csi_tee_enter_lpm(uint32_t gate, uint32_t irqid, tee_lpm_mode_e mode); - -/** - \brief TEE obtain manifest info from manifest table - \note call csi_tee_get_sys_img_info, csi_tee_get_sys_os_version or csi_tee_get_sys_partition is better - \param[out] out Pointer to info buffer - \param[out] out_len Info buffer length,if info obtain successfully, - out_len is updated to actual sizes - \param[in] name info name - \return Return 0 if successful,otherwise error code -*/ -int32_t csi_tee_get_manifest_info(uint8_t *out, uint32_t *out_len, char *name); - -/** - \brief TEE obtain image buffer from manifest table - \param[out] out Pointer to image buffer - \param[out] out_len Image buffer length,if info obtain successfully, - out_len is updated to actual image buffer sizes - \param[in] img_name Image name - \return Return 0 if successful,otherwise error code -*/ -#define csi_tee_get_sys_img_info(out,out_len,img_name) \ - csi_tee_get_manifest_info(out,out_len,img_name) - -/** - \brief TEE obtain os version from manifest table - \param[out] out Pointer to os version buffer - \param[out] out_len OS version buffer length,if info obtain successfully, - out_len is updated to actual os version buffer sizes - \return Return 0 if successful,otherwise error code -*/ -#define csi_tee_get_sys_os_version(out,out_len) \ - csi_tee_get_manifest_info(out,out_len,"os_v") - -/** - \brief TEE obtain partition buffer from manifest table - \param[out] out Pointer to partition buffer - \param[out] out_len Partition buffer length,if info obtain successfully, - out_len is updated to actual partition buffer sizes - \return Return 0 if successful,otherwise error code -*/ -#define csi_tee_get_sys_partition(out,out_len) \ - csi_tee_get_manifest_info(out,out_len,"sys_p") - -/** - \brief TEE set random seed - \param[in] Seed random sedd - \return Return 0 if successful,otherwise error code -*/ -int32_t csi_tee_rand_seed(uint32_t seed); - -/** - \brief TEE ramdom date generation - \param[out] out Pointer to random data buffer - \param[in] out_len Data buffer length - \return Return 0 if successful,otherwise error code -*/ -int32_t csi_tee_rand_generate(uint8_t *out, uint32_t out_len); - -/****** TEE RSA sign type *****/ -typedef enum { - TEE_RSA_MD5 = 0, ///< MD5 - TEE_RSA_SHA1 = 1, ///< SHA1 - TEE_RSA_SHA256 = 3, ///< SHA256 - TEE_RSA_SIGN_TYPE_MAX, ///< invailed type -} tee_rsa_sign_type_e; - -/** - \brief TEE RSA sign with private key - \param[in] in Pointer to digest buffer - \param[in] in_len Digest buffer length - \param[in] key Pointer to private key,key contains n, e, d - \param[in] key_len Private key size,must be 128*3 = 384 bytes for RSA1024, 256*3 = 768 bytes for RSA2048 - \param[out] sign Pointer to sign buffer - \param[out] sign_len Sign buffer length - \param[in] type \ref tee_rsa_sign_type_e - \return Return 0 if successful,otherwise error code -*/ -int32_t csi_tee_rsa_sign(const uint8_t *in, uint32_t in_len, - const uint8_t *key, uint32_t key_len, - uint8_t *sign, uint32_t *sign_len, - tee_rsa_sign_type_e type); - -/** - \brief TEE RSA verify with public key - \param[in] in Pointer to digest buffer - \param[in] in_len Digest buffer length - \param[in] key Pointer to public key,key contains n, e - \param[in] key_len Public key size,must be 128*2 = 256 bytes for RSA1024, 256*2 = 512 bytes for RSA2048 - \param[in] sign Pointer to sign buffer - \param[in] sign_len Sign buffer length - \param[in] type \ref tee_rsa_sign_type_e - \return Return 0 if verify successful,otherwise error code -*/ -int32_t csi_tee_rsa_verify(const uint8_t *in, uint32_t in_len, - const uint8_t *key, uint32_t key_len, - uint8_t *sign, uint32_t sign_len, - tee_rsa_sign_type_e type); - -/****** TEE RSA padding mode *****/ -typedef enum { - TEE_RSA_PKCS1_PADDING = 0x01, ///< RSA PKCS padding mode - TEE_RSA_NO_PADDING = 0x02, ///< RSA no padding mode -} tee_rsa_padding_mode_e; - -/** - \brief TEE RSA encrypt with public key - \param[in] in Pointer to plaintext buffer - \param[in] in_len Plaintext buffer length - \param[in] key Pointer to public key,key contains n, e - \param[in] key_len Public key size, must be 128*2 = 256 bytes for RSA1024, 256*2 = 512 bytes for RSA2048 - \param[in] out Pointer to ciphertext buffer - \param[in] out_len Ciphertext buffer length - \param[in] padding \ref tee_rsa_padding_mode_e - \return Return 0 if successful,otherwise error code -*/ -int32_t csi_tee_rsa_encrypt(const uint8_t *in, uint32_t in_len, - const uint8_t *key, uint32_t key_len, - uint8_t *out, uint32_t *out_len, - tee_rsa_padding_mode_e padding); -/** - \brief TEE RSA decrypt with private key - \param[in] in Pointer to ciphertext buffer - \param[in] in_len Ciphertext buffer length - \param[in] key Pointer to private key,key contains n, e, d - \param[in] key_len Private key size,must be 128*3 = 384 bytes for RSA1024, 256*3 = 768 bytes for RSA2048 - \param[in] out Pointer to plaintext buffer - \param[in] out_len Plaintext buffer length - \param[in] padding \ref tee_rsa_padding_mode_e - \return Return 0 if successful,otherwise error code -*/ -int32_t csi_tee_rsa_decrypt(const uint8_t *in, uint32_t in_len, - const uint8_t *key, uint32_t key_len, - uint8_t *out, uint32_t *out_len, - tee_rsa_padding_mode_e padding); - -/** - \brief TEE RSA sign with internal private key - \note Only use if key provisioning exist - \param[in] in Pointer to digest buffer - \param[in] in_len Digest buffer length - \param[out] sign Pointer to sign buffer - \param[out] sign_len Sign buffer length - \param[in] type \ref tee_rsa_sign_type_e - \return Return 0 if successful,otherwise error code -*/ -#define csi_tee_cid_rsa_sign(in,in_len,sign,sign_len,type) \ - csi_tee_rsa_sign(in,in_len,NULL,0,sign,sign_len,type) - -/** - \brief TEE RSA verify with internal public key - \note Only use if key provisioning exist - \param[in] in Pointer to digest buffer - \param[in] in_len Digest buffer length - \param[in] sign Pointer to sign buffer - \param[in] sign_len Sign buffer length - \param[in] type \ref tee_rsa_sign_type_e - \return Return 0 if verify successful,otherwise error code -*/ -#define csi_tee_cid_rsa_verify(in,in_len,sign,sign_len,type) \ - csi_tee_rsa_verify(in,in_len,NULL,0,sign,sign_len,type) - -/** - \brief TEE RSA encrypt with internal public key - \note Only use if key provisioning exist - \param[in] in Pointer to plaintext buffer - \param[in] in_len Plaintext buffer length - \param[in] out Pointer to ciphertext buffer - \param[in] out_len Ciphertext buffer length - \param[in] padding \ref tee_rsa_padding_mode_e - \return Return 0 if successful,otherwise error code -*/ -#define csi_tee_cid_rsa_encrypt(in,in_len,out,out_len,padding) \ - csi_tee_rsa_encrypt(in,in_len,NULL,0,out,out_len,padding) - -/** - \brief TEE RSA decrypt with internal private key - \note Only use if key provisioning exist - \param[in] in Pointer to ciphertext buffer - \param[in] in_len Ciphertext buffer length - \param[in] key Pointer to private key,key contains n, e, d - \param[in] key_len Private key size,must be 128*3 = 384 bytes for RSA1024, 256*3 = 768 bytes for RSA2048 - \param[in] out Pointer to plaintext buffer - \param[in] out_len Plaintext buffer length - \param[in] padding \ref tee_rsa_padding_mode_e - \return Return 0 if successful,otherwise error code -*/ -#define csi_tee_cid_rsa_decrypt(in,in_len,out,out_len,padding) \ - csi_tee_rsa_decrypt(in,in_len,NULL,0,out,out_len,padding) - -/** - \brief verify boot image with boot public key - \note Only use if key provisioning exist - \param[in] in Pointer to digest buffer - \param[in] in_len Digest buffer length - \param[in] sign Pointer to sign buffer - \param[in] sign_len Sign buffer length - \param[in] type \ref tee_rsa_sign_type_e - \return Return 0 if verify successful,otherwise error code -*/ -int32_t csi_tee_img_rsa_verify(const uint8_t *in, uint32_t in_len, - uint8_t *sign, uint32_t sign_len, - tee_rsa_sign_type_e type); - -/****** TEE HASH operation mode *****/ -typedef enum { - TEE_HASH_OP_NONE = 0, ///< No operation - TEE_HASH_OP_START = 1, ///< HASH init - TEE_HASH_OP_UPDATA = 2, ///< HASH update - TEE_HASH_OP_FINISH = 3, ///< HASH finish - TEE_HASH_OP_MAX, ///< invailed operation -} tee_hash_op_e; - -/****** TEE HMAC type *****/ -typedef enum { - TEE_HMAC_SHA1 = 1, ///< HMAC with SHA1 -} tee_hmac_type_e; - -/** - \brief TEE HAMC - \note Call csi_tee_hmac_digest is better - out buffer size must be large enough according to type, eg. 20 bytes for TEE_HMAC_SHA1 - \param[in] in Pointer to input data buffer - \param[in] in_len Input data buffer length - \param[in] key Pointer to key buffer - \param[in] key_len Key buffer size - \param[out] out Pointer to output date buffer - \param[in] type \ref tee_hmac_type_e - \param[in] hash_op \ref tee_hash_op_e - \param[in] ctx Pointer to context of hmac - \return Return 0 if successful,otherwise error code -*/ -int32_t csi_tee_hmac(const uint8_t *in, uint32_t in_len, - const uint8_t *key, uint32_t key_len, - uint8_t *out, - tee_hmac_type_e type, - tee_hash_op_e hash_op, - uint32_t *ctx); - -/** - \brief TEE HAMC digest - \note out buffer size must be large enough according to type, eg. 20 bytes for TEE_HMAC_SHA1 - \param[in] in Pointer to input data buffer - \param[in] in_len Input data buffer length - \param[in] key Pointer to key buffer - \param[in] key_len Key buffer size - \param[out] out Pointer to output date buffer - \param[in] type \ref tee_hmac_type_e - \return Return 0 if successful,otherwise error code -*/ -#define csi_tee_hmac_digest(in,in_len,key,key_len,out,type) \ - csi_tee_hmac(in,in_len,key,key_len,out,type,TEE_HASH_OP_NONE,NULL) - -/****** TEE SHA type *****/ -typedef enum { - TEE_SHA1 = 0, ///< SHA1 - TEE_SHA256 = 1, ///< SHA256 - TEE_SHA224 = 2, ///< SHA224 - TEE_SHA384 = 3, ///< SHA384 - TEE_SHA512 = 4, ///< SHA512 - TEE_SHA_MAX, ///< invaild sha type -} tee_sha_type_t; - -/** - \brief TEE SHA - \note Call csi_tee_sha_digest, csi_tee_sha_start, csi_tee_sha_update or csi_tee_sha_finish is better - out buffer size must be large enough according to type, eg. 20 bytes for TEE_SHA1, 32 bytes for TEE_SHA256 - \param[in] in Pointer to input data buffer - \param[in] in_len Input data buffer length - \param[out] out Pointer to output date buffer - \param[in] type \ref tee_sha_type_t - \param[in] hash_op \ref tee_hash_op_e - \param[in] ctx Pointer to context of sha - \return Return 0 if successful,otherwise error code -*/ -int32_t csi_tee_sha(const uint8_t *in, uint32_t in_len, - uint8_t *out, - tee_sha_type_t type, - tee_hash_op_e hash_op, - void *ctx); - -/** - \brief TEE SHA digest - \note out buffer size must be large enough according to type, eg. 20 bytes for TEE_SHA1, 32 bytes for TEE_SHA256 - \param[in] in Pointer to input data buffer - \param[in] in_len Input data buffer length - \param[out] out Pointer to output date buffer - \param[in] type \ref tee_sha_type_t - \return Return 0 if successful,otherwise error code -*/ -#define csi_tee_sha_digest(in,in_len,out,type) \ - csi_tee_sha(in,in_len,out,type,TEE_HASH_OP_NONE,NULL); - -/** - \brief TEE SHA start, initial sha - \param[in] type \ref tee_sha_type_t - \param[in] ctx Pointer to context of sha - \return Return 0 if successful,otherwise error code -*/ -#define csi_tee_sha_start(type,ctx) \ - csi_tee_sha(NULL,0,NULL,type,TEE_HASH_OP_START,ctx); - -/** - \brief TEE SHA update, update data - \param[in] in Pointer to input data buffer - \param[in] in_len Input data buffer length - \param[in] ctx Pointer to context of sha - \return Return 0 if successful,otherwise error code -*/ -#define csi_tee_sha_update(in,in_len,ctx) \ - csi_tee_sha(in,in_len,NULL,0,TEE_HASH_OP_UPDATA,ctx); - -/** - \brief TEE SHA digest, get sha digest - \note out buffer size must be large enough according to type, eg. 20 bytes for TEE_SHA1, 32 bytes for TEE_SHA256 - \param[out] out Pointer to output date buffer - \param[in] ctx Pointer to context of sha - \return Return 0 if successful,otherwise error code -*/ -#define csi_tee_sha_finish(out,ctx) \ - csi_tee_sha(NULL,0,out,0,TEE_HASH_OP_FINISH,ctx); - -/** - \brief TEE get device name and product key - \param[in] name_encrypted Pointer to device name ciphertext - \param[in] name_encrypted_len device name ciphertext length - \param[in] product_key_encrypted Pointer to device product key ciphertext - \param[in] product_key_encrypted_len Device product key ciphertext length - \param[out] name Pointer to device name - \param[out] name_len Device name length - \param[out] product_key Pointer to device product key - \param[out] product_key_len Device product key length - \return Return 0 if successful,otherwise error code -*/ -int32_t csi_tee_dev_info_get(const uint8_t *name_encrypted, uint32_t name_encrypted_len, - const uint8_t *product_key_encrypted, uint32_t product_key_encrypted_len, - const uint8_t *name, uint32_t *name_len, - const uint8_t *product_key, uint32_t *product_key_len); - -/** - \brief TEE device info sign - \param[in] in Pointer to input date buffer - \param[in] in_len Input data buffer length - \param[in] device_secret Pointer to device secret ciphertext - \param[in] device_secret_len Device secret ciphertext length - \param[out] sign Pointer to signed buffer - \param[out] sign_len Signed buffer length - \return Return 0 if successful,otherwise error code -*/ -int32_t csi_tee_dev_info_sign(const uint8_t *in, uint32_t in_len, - const uint8_t *device_secret, uint32_t device_secret_len, - const uint8_t *sign, uint32_t *sign_len); - -/** - \brief TEE device info encrypt/decrypt - \param[in] in Pointer to input date buffer - \param[in] in_len Input data buffer length - \param[in] out Pointer to output date buffer - \param[in] out_len Onput data buffer length - \param[in] is_enc 1 incrypt 0 decrypt - \return Return 0 if successful,otherwise error code -*/ -int32_t csi_tee_dev_info_crypt(const uint8_t *in, uint32_t in_len, - uint8_t *out, uint32_t *out_len, - uint8_t is_enc); - -/** - \brief TEE device info encrypt - \param[in] in Pointer to input date buffer - \param[in] in_len Input data buffer length - \param[in] out Pointer to output date buffer - \param[in] out_len Onput data buffer length - \return Return 0 if successful,otherwise error code -*/ -#define csi_tee_dev_info_encrypt(in, in_len, out, out_len) \ - csi_tee_dev_info_crypt(in, in_len, out, out_len, 1) - -/** - \brief TEE device info decrypt - \param[in] in Pointer to input date buffer - \param[in] in_len Input data buffer length - \param[in] out Pointer to output date buffer - \param[in] out_len Onput data buffer length - \return Return 0 if successful,otherwise error code -*/ -#define csi_tee_dev_info_decrypt(in, in_len, out, out_len) \ - csi_tee_dev_info_crypt(in, in_len, out, out_len, 0) - -/** - \brief Set system frequence - \param[in] clk_src Indicate clock source type - \param[in] clk_val System freqence to be set - \return Return 0 if successful,otherwise error code -*/ -int32_t csi_tee_set_sys_freq(uint32_t clk_src, uint32_t clk_val); - -/** - \brief Get system frequence - \param[in] clk_val Value address to store system freqence - \return Return 0 if successful,otherwise error code -*/ -int32_t csi_tee_get_sys_freq(uint32_t *clk_val); - -/** - \brief Read system register - \param[in] addr Indicate register address - \param[out] val Value to read from the address - \return Return 0 if successful,otherwise error code -*/ -int32_t csi_tee_read_reg(uint32_t addr, uint32_t *val); - -/** - \brief Wrte system register - \param[in] addr Indicate register address - \param[in] val Value to be written into the address - \return Return 0 if successful,otherwise error code -*/ -int32_t csi_tee_write_reg(uint32_t addr, uint32_t val); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_TEE_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/tipc.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/tipc.h deleted file mode 100755 index da117ebc..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/tipc.h +++ /dev/null @@ -1,56 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/tipc.h - * @brief Header File for TIPC Driver - * @version V1.0 - * @date 08. Mar 2020 - * @model tipc - ******************************************************************************/ - -#ifndef _DRV_TIPC_H_ -#define _DRV_TIPC_H_ - -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - uint32_t ip; - uint16_t dev_tag; - uint8_t idx; -} csi_tipcmap_t; - -/** - \brief Config the tipc module properity - \param[in] dev Dev handle \ref csi_dev_t - \param[in] is_secure is secure or not -*/ -csi_error_t csi_dev_secure_config(csi_dev_t *dev, bool is_secure); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_TIPC_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/usi.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/usi.h deleted file mode 100755 index 8e8cb1d3..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/usi.h +++ /dev/null @@ -1,42 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/usi.h - * @brief Header File for USI Driver - * @version V1.0 - * @date 02. June 2020 - * @model usi - ******************************************************************************/ - -#ifndef _DRV_USI_H_ -#define _DRV_USI_H_ - -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_USI_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/usi_iic.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/usi_iic.h deleted file mode 100755 index 257b534a..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/usi_iic.h +++ /dev/null @@ -1,260 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/drv_usi_iic.h - * @brief Header File for IIC driver - * @version V1.0 - * @date 02. June 2020 - * @model usi_iic - ******************************************************************************/ - -#ifndef _DRV_USI_IIC_H_ -#define _DRV_USI_IIC_H_ - -#include -#include -#include -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** - \brief Init iic ctrl block. - Initializes the resources needed for the iic instance. - \param[in] iic Handle of iic instance. - \param[in] idx Index of instance. - \return \ref csi_error_t. -*/ -csi_error_t csi_usi_iic_init(csi_iic_t *iic, uint32_t idx); - -/** - \brief Uninit iic ctrl block. - Stops operation and releases the software resources used by the instance. - \param[in] iic Handle of iic instance. -*/ -void csi_usi_iic_uninit(csi_iic_t *iic); - -/** - \brief Config iic master or slave mode. - \param[in] iic Handle of iic instance. - \param[in] mode IIC mode \ref csi_iic_mode_t. - \return \ref csi_error_t. -*/ -csi_error_t csi_usi_iic_mode(csi_iic_t *iic, csi_iic_mode_t mode); - -/** - \brief Config iic addr mode. - \param[in] iic Handle of iic instance. - \param[in] addr_mode IIC addr mode \ref csi_iic_addr_mode_t. - \return \ref csi_error_t. -*/ -csi_error_t csi_usi_iic_addr_mode(csi_iic_t *iic, csi_iic_addr_mode_t addr_mode); - -/** - \brief Config iic speed. - \param[in] iic Handle of iic instance. - \param[in] speed iic speed mode \ref csi_iic_speed_t. - \return \ref csi_error_t. -*/ -csi_error_t csi_usi_iic_speed(csi_iic_t *iic, csi_iic_speed_t speed); - -/** - \brief Config iic own addr. - \param[in] iic Handle of iic instance. - \param[in] own_addr IIC set own addr at slave mode. - \return \ref csi_error_t. -*/ -csi_error_t csi_usi_iic_own_addr(csi_iic_t *iic, uint32_t own_addr); - -/** - \brief Start sending data as iic master. - This function is blocking. - \param[in] iic Handle of iic instance. - \param[in] devaddr Addrress of slave device. - \param[in] data Pointer to send data buffer. - \param[in] size Size of data items to send. - \param[in] timout Unit of time delay(ms). - \return The amount of real data sent. -*/ -int32_t csi_usi_iic_master_send(csi_iic_t *iic, uint32_t devaddr, const void *data, uint32_t size, uint32_t timeout); - -/** - \brief Start receiving data as iic master. - This function is blocking. - \param[in] iic Handle to operate. - \param[in] devaddr IIC addrress of slave device. - \param[out] data Pointer to buffer for data to receive from iic receiver. - \param[in] size Size of data items to receive. - \param[in] timeout Unit of time delay(ms). - \return The amount of real data received. -*/ -int32_t csi_usi_iic_master_receive(csi_iic_t *iic, uint32_t devaddr, void *data, uint32_t size, uint32_t timeout); - -/** - \brief Start sending data as iic master. - This function is non-blocking,\ref csi_usi_iic_event_t is signaled when transfer completes or error happens. - \param[in] iic Handle to operate. - \param[in] devaddr IIC addrress of slave device. - \param[in] data Pointer to send data buffer. - \param[in] size Size of data items to send. - \return \ref csi_error_t. -*/ -csi_error_t csi_usi_iic_master_send_async(csi_iic_t *iic, uint32_t devaddr, const void *data, uint32_t size); - -/** - \brief Start receiving data as iic master. - This function is non-blocking.\ref csi_usi_iic_event_t is signaled when transfer completes or error happens. - \param[in] iic Handle to operate. - \param[in] devaddr IIC addrress of slave device. - \param[out] data Pointer to buffer for data to receive from iic receiver. - \param[in] size Size of data items to receive. - \return \ref csi_error_t. -*/ -csi_error_t csi_usi_iic_master_receive_async(csi_iic_t *iic, uint32_t devaddr, void *data, uint32_t size); - -/** - \brief Start sending data as iic master. - This function is blocking. - \param[in] iic Handle of iic instance. - \param[in] devaddr Addrress of slave device. - \param[in] memaddr Internal addr of device. - \param[in] memaddr_size Internal addr mode of device. - \param[in] data Pointer to send data buffer. - \param[in] size Size of data items to send. - \param[in] timout Unit of time delay(ms). - \return The amount of real data sent. -*/ -int32_t csi_usi_iic_mem_send(csi_iic_t *iic, uint32_t devaddr, uint16_t memaddr, csi_iic_mem_addr_size_t memaddr_size, const void *data, uint32_t size, uint32_t timeout); - -/** - \brief Start receiving data as iic master. - This function is blocking. - \param[in] iic Handle to operate. - \param[in] devaddr IIC addrress of slave device. - \param[in] memaddr Internal addr of device. - \param[in] memaddr_mode Internal addr mode of device. - \param[out] data Pointer to buffer for data to receive from eeprom device. - \param[in] size Size of data items to receive. - \param[in] timeout Unit of time delay(ms). - \return The amount of real data received. -*/ -int32_t csi_usi_iic_mem_receive(csi_iic_t *iic, uint32_t devaddr, uint16_t memaddr, csi_iic_mem_addr_size_t memaddr_size, void *data, uint32_t size, uint32_t timeout); - -/** - \brief Start sending data as iic slave. - This function is blocking. - \param[in] iic Handle to operate. - \param[in] data Pointer to buffer with data to send to iic master. - \param[in] size Size of data items to send. - \param[in] timeout Unit of time delay(ms). - \return The amount of real data sent. -*/ -int32_t csi_usi_iic_slave_send(csi_iic_t *iic, const void *data, uint32_t size, uint32_t timeout); - -/** - \brief Start receiving data as iic slave. - This function is blocking. - \param[in] iic Handle to operate. - \param[out] data Pointer to buffer for data to receive from iic master. - \param[in] size Size of data items to receive. - \param[in] timeout Unit of time delay(ms). - \return The amount of real data received. -*/ -int32_t csi_usi_iic_slave_receive(csi_iic_t *iic, void *data, uint32_t size, uint32_t timeout); - -/** - \brief Start sending data as iic slave. - This function is non-blocking,\ref csi_usi_iic_event_t is signaled when transfer completes or error happens. - \param[in] iic Handle to operate. - \param[in] data Pointer to buffer with data to send to iic master. - \param[in] size size of data items to send. - \return \ref csi_error_t. -*/ -csi_error_t csi_usi_iic_slave_send_async(csi_iic_t *iic, const void *data, uint32_t size); - -/** - \brief Start receiving data as iic slave. - This function is non-blocking,\ref csi_usi_iic_event_t is signaled when transfer completes or error happens. - \param[in] handle IIC handle to operate. - \param[out] data Pointer to buffer for data to receive from iic master. - \param[in] size Size of data items to receive. - \return \ref csi_error_t. -*/ -csi_error_t csi_usi_iic_slave_receive_async(csi_iic_t *iic, void *data, uint32_t size); - -/** - \brief Attach callback to the iic. - \param[in] iic IIC handle to operate. - \param[in] cb Event callback function \ref csi_usi_iic_callback_t. - \param[in] arg User private param for event callback. - \return \ref csi_error_t. -*/ -csi_error_t csi_usi_iic_attach_callback(csi_iic_t *iic, void *callback, void *arg); - -/** - \brief Detach callback from the iic. - \param[in] iic IIC handle to operate. - \return \ref csi_error_t. -*/ -void csi_usi_iic_detach_callback(csi_iic_t *iic); - -/** - \brief Config iic stop to generate. - \param[in] iic IIC handle to operate. - \param[in] enable Transfer operation is pending - stop condition will not be generated. - \return \ref csi_error_t. -*/ -csi_error_t csi_usi_iic_xfer_pending(csi_iic_t *iic, bool enable); - -/** - \brief Link DMA channel to iic device. - \param[in] iic Handle to operate. - \param[in] tx_dma The DMA channel handle for send, when it is NULL means to unlink the channel. - \param[in] rx_dma The DMA channel handle for receive, when it is NULL means to unlink the channel. - \return \ref csi_error_t. -*/ -csi_error_t csi_usi_iic_link_dma(csi_iic_t *iic, csi_dma_ch_t *tx_dma, csi_dma_ch_t *rx_dma); - -/** - \brief Get iic state. - \param[in] iic Handle to operate. - \param[out] state IIC state \ref csi_state_t. - \return \ref csi_error_t. -*/ -csi_error_t csi_usi_iic_get_state(csi_iic_t *iic, csi_state_t *state); - -/** - \brief Enable iic power manage. - \param[in] iic IIC handle to operate. - \return \ref csi_error_t. -*/ -csi_error_t csi_usi_iic_enable_pm(csi_iic_t *iic); - -/** - \brief Disable iic power manage. - \param[in] iic IIC handle to operate. -*/ -void csi_usi_iic_disable_pm(csi_iic_t *iic); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_USI_IIC_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/usi_spi.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/usi_spi.h deleted file mode 100755 index eaa1f3e3..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/usi_spi.h +++ /dev/null @@ -1,229 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/usi_spi.h - * @brief Header File for SPI Driver - * @version V1.0 - * @date 02. June 2020 - * @model usi_spi - ******************************************************************************/ - -#ifndef _DRV_SPI_USI_H_ -#define _DRV_SPI_USI_H_ - -#include -#include -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** - \brief Initialize SPI Interface. - Initializes the resources needed for the SPI instance - \param[in] spi SPI handle - \param[in] idx SPI instance index - \return Error code -*/ -csi_error_t csi_usi_spi_init(csi_spi_t *spi, uint32_t idx); - -/** - \brief De-initialize SPI Interface - Stops operation and releases the software resources used by the spi instance - \param[in] spi SPI handle - \return None -*/ -void csi_usi_spi_uninit(csi_spi_t *spi); - -/** - \brief Attach the callback handler to SPI - \param[in] spi Operate handle. - \param[in] callback Callback function - \param[in] arg User can define it by himself as callback's param - \return Error code -*/ -csi_error_t csi_usi_spi_attach_callback(csi_spi_t *spi, void *callback, void *arg); - -/** - \brief Detach the callback handler - \param[in] spi Operate handle. - \return None -*/ -void csi_usi_spi_detach_callback(csi_spi_t *spi); - - -/** - \brief Config spi mode (master or slave). - \param[in] spi SPI handle - \param[in] mode The mode of spi (master or slave) - \return Error code -*/ -csi_error_t csi_usi_spi_mode(csi_spi_t *spi, csi_spi_mode_t mode); - -/** - \brief Config spi cp format. - \param[in] spi SPI handle - \param[in] format SPI cp format - \return Error code -*/ -csi_error_t csi_usi_spi_cp_format(csi_spi_t *spi, csi_spi_cp_format_t format); - -/** - \brief Config spi frame len. - \param[in] spi SPI handle - \param[in] length spi frame len - \return error code -*/ -csi_error_t csi_usi_spi_frame_len(csi_spi_t *spi, csi_spi_frame_len_t length); - -/** - \brief Config spi work frequence. - \param[in] spi SPI handle - \param[in] baud SPI work baud - \return The actual config frequency -*/ -uint32_t csi_usi_spi_baud(csi_spi_t *spi, uint32_t baud); - -/** - \brief Config spi mode. - \param[in] Handle spi handle to operate. - \param[in] baud SPI baud rate. If negative, then this attribute not changed - \param[in] mode \ref spi_mode_e . If negative, then this attribute not changed - \param[in] format \ref spi_format_e . If negative, then this attribute not changed - \param[in] order \ref spi_bit_order_e . If negative, then this attribute not changed - \param[in] ss_mode \ref spi_ss_mode_t . If negative, then this attribute not changed - \param[in] bit_width SPI data bitwidth: (1 ~ SPI_DATAWIDTH_MAX) . If negative, then this attribute not changed - \return Error code -*/ -csi_error_t drv_usi_spi_config(csi_spi_t *spi, csi_spi_mode_t mode, csi_spi_frame_len_t width, csi_spi_cp_format_t format); - -/** - \brief Sending data to SPI transmitter,(received data is ignored). - Blocking mode ,return unti all data has been sent or err happened - \param[in] spi Handle to operate. - \param[in] data Pointer to buffer with data to send to SPI transmitter. - \param[in] size Number of data to send(byte) - \param[in] timeout Unit in mini-second - \return If send success, this function shall return the num of data witch is sent successful - otherwise, the function shall return error code -*/ -int32_t csi_usi_spi_send(csi_spi_t *spi, const void *data, uint32_t size, uint32_t timeout); - -/** - \brief Sending data to SPI transmitter,(received data is ignored). - non-blocking mode,transfer done event will be signaled by driver - \param[in] spi Handle to operate. - \param[in] data Pointer to buffer with data to send to SPI transmitter. - \param[in] size Number of data items to send(byte) - \return Error code -*/ -csi_error_t csi_usi_spi_send_async(csi_spi_t *spi, const void *data, uint32_t size); - -/** - \brief Receiving data from SPI receiver. - Blocking mode, return untill curtain data items are readed - \param[in] spi Handle to operate. - \param[out] data Pointer to buffer for data to receive from SPI receiver - \param[in] size Number of data items to receive(byte) - \param[in] timeout Unit in mini-second - \return If receive success, this function shall return the num of data witch is received successful - Otherwise, the function shall return error code -*/ -int32_t csi_usi_spi_receive(csi_spi_t *spi, void *data, uint32_t size, uint32_t timeout); - -/** - \brief Receiving data from SPI receiver. - Not-blocking mode, event will be signaled when receive done or err happend - \param[in] spi Handle to operate. - \param[out] data Pointer to buffer for data to receive from SPI receiver - \param[in] size Number of data items to receive(byte) - \return Error code -*/ -csi_error_t csi_usi_spi_receive_async(csi_spi_t *spi, void *data, uint32_t size); - -/** - \brief Dulplex,sending and receiving data at the same time - \ref csi_spi_event_t is signaled when operation completes or error happens. - \ref csi_spi_get_state can get operation status. - Blocking mode, this function returns after operation completes or error happens. - \param[in] Handle spi handle to operate. - \param[in] data_out Pointer to buffer with data to send to SPI transmitter - \param[out] data_in Pointer to buffer for data to receive from SPI receiver - \param[in] size Data size(byte) - \return If transfer success, this function shall return the num of data witch is transfer successful - otherwise, the function shall return error code -*/ -int32_t csi_usi_spi_send_receive(csi_spi_t *spi, const void *data_out, void *data_in, uint32_t size, uint32_t timeout); - -/** - \brief Transmit first then receive ,receive will begin after transmit is done - if non-blocking mode, this function only starts the transfer, - \ref csi_spi_event_t is signaled when operation completes or error happens. - \ref csi_spi_get_state can get operation status. - \param[in] handle spi Handle to operate. - \param[in] data_out Pointer to buffer with data to send to SPI transmitter - \param[out] data_in Pointer to buffer for data to receive from SPI receiver - \param[in] size Data size(byte) - \return Error code -*/ -csi_error_t csi_usi_spi_send_receive_async(csi_spi_t *spi, const void *data_out, void *data_in, uint32_t size); - -/* - \brief Set slave select num. Only valid for master - \param[in] Handle spi handle to operate. - \param[in] slave_num SPI slave num. - \return None - */ -void csi_usi_spi_select_slave(csi_spi_t *spi, uint32_t slave_num); - -/** - \brief Link DMA channel to spi device - \param[in] spi SPI handle to operate. - \param[in] tx_dma The DMA channel handle for send, when it is NULL means to unlink the channel - \param[in] rx_dma The DMA channel handle for receive, when it is NULL means to unlink the channel - \return Error code -*/ -csi_error_t csi_usi_spi_link_dma(csi_spi_t *spi, csi_dma_ch_t *tx_dma, csi_dma_ch_t *rx_dma); - -/** - \brief Get the state of spi device - \param[in] spi SPI handle to operate. - \param[out] state The state of spi device - \return Error code -*/ -csi_error_t csi_usi_spi_get_state(csi_spi_t *spi, csi_state_t *state); - -/** - \brief Enable spi power manage - \param[in] spi SPI handle to operate. - \return Error code -*/ -csi_error_t csi_usi_spi_enable_pm(csi_spi_t *spi); - -/** - \brief Disable spi power manage - \param[in] spi SPI handle to operate. - \return Error code -*/ -void csi_spi_disable_pm(csi_spi_t *spi); -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_SPI_USI_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/usi_usart.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/usi_usart.h deleted file mode 100755 index 59bfe554..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/usi_usart.h +++ /dev/null @@ -1,192 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/usi_usart.h - * @brief Header File for USART Driver - * @version V1.0 - * @date 02. June 2020 - * @model usi_usart - ******************************************************************************/ - -#ifndef _DRV_USI_USART_H_ -#define _DRV_USI_USART_H_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \brief Initialize UART Interface. 1. Initializes the resources needed for the UART interface 2.registers event callback function - \param[in] uart Operate handle. - \param[in] idx The device idx - \param[in] cb_event Event call back function \ref uart_event_cb_t - \param[in] arg User can define it by himself - \return error code -*/ -csi_error_t csi_usi_uart_init(csi_uart_t *uart, uint32_t idx); - -/** - \brief De-initialize UART Interface. stops operation and releases the software resources used by the interface - \param[in] uart Operate handle. - \return Error code -*/ -void csi_usi_uart_uninit(csi_uart_t *uart); - -/** - \brief Attach the callback handler to UART - \param[in] uart Operate handle. - \param[in] cb Callback function - \param[in] arg User can define it by himself as callback's param - \return Error code -*/ -csi_error_t csi_usi_uart_attach_callback(csi_uart_t *uart, void * cb, void *arg); - -/** - \brief Detach the callback handler - \param[in] uart Operate handle. -*/ -void csi_usi_uart_detach_callback(csi_uart_t *uart); - -/** - \brief Config the baudrate. - \param[in] uart UART handle to operate. - \param[in] baud UART baudrate - \return Error code -*/ -csi_error_t csi_usi_uart_baud(csi_uart_t *uart, uint32_t baud); - -/** - \brief Config the uart format. - \param[in] uart UART handle to operate. - \param[in] data_bit UART data bits - \param[in] parity UART data parity - \param[in] stop_bit UART stop bits - \return Error code -*/ -csi_error_t csi_usi_uart_format(csi_uart_t *uart, csi_uart_data_bits_t data_bits, - csi_uart_parity_t parity, csi_uart_stop_bits_t stop_bits); - -/** - \brief Config the uart flow control. - \param[in] uart UART handle to operate. - \param[in] flowctrl UART flow control - \return Error code -*/ -csi_error_t csi_usi_uart_flowctrl(csi_uart_t *uart, csi_uart_flowctrl_t flowctrl); - -/** - \brief Start sending data to UART transmitter. - \param[in] uart UART handle to operate. - \param[in] data Pointer to buffer with data to send to UART transmitter. data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits - \param[in] num Number of data items to send (byte) - \param[in] Timeout is the number of queries, not time - \return The num of data witch is send successful -*/ -int32_t csi_usi_uart_send(csi_uart_t *uart, const void *data, uint32_t size, uint32_t timeout); - -/** - \brief Start sending data to UART transmitter (interrupt mode). - \param[in] uart UART handle to operate. - \param[in] data Pointer to buffer with data to send to UART transmitter. data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits - \param[in] num Number of data items to send - \return The status of send func -*/ -csi_error_t csi_usi_uart_send_async(csi_uart_t *uart, const void *data, uint32_t size); - -/** - \brief Get the num of data in RX_FIFO. - \param[in] uart UART handle to operate. - \return The num of data in RX_FIFO -*/ -uint32_t csi_usi_uart_get_recvfifo_waiting_num(csi_uart_t *uart); - -/** - \brief Start receiving data from UART receiver. \n - This function is non-blocking,\ref uart_event_e is signaled when operation completes or error happens. - \ref csi_uart_get_status can get operation status. - \param[in] uart UART handle to operate. - \param[out] data Pointer to buffer for data to receive from UART receiver.data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits - \param[in] num Number of data items to receive - \return Error code -*/ -csi_error_t csi_usi_uart_receive_async(csi_uart_t *uart, void *data, uint32_t size); - -/** - \brief Query data from UART receiver FIFO. - \param[in] uart UART handle to operate. - \param[out] data Pointer to buffer for data to receive from UART receiver - \param[in] num Number of data items to receive - \param[in] Timeout is the number of queries, not time - \return FIFO data num to receive -*/ -int32_t csi_usi_uart_receive(csi_uart_t *uart, void *data, uint32_t size, uint32_t timeout); - -/** - \brief Get character in query mode. - \param[in] uart UART handle to operate. - \param[out] ch The pointer to the received character. - \return Error code -*/ -uint8_t csi_usi_uart_getchar(csi_uart_t *uart); - -/** - \brief Transmit character in query mode. - \param[in] uart UART handle to operate. - \param[in] ch The input character - \return Error code -*/ -void csi_usi_uart_putchar(csi_uart_t *uart, uint8_t ch); - -/** - \brief Link DMA channel to uart device - \param[in] uart UART handle to operate. - \param[in] tx_dma The DMA channel handle for send, when it is NULL means to unlink the channel - \param[in] rx_dma The DMA channel handle for receive, when it is NULL means to unlink the channel - \return Error code -*/ -csi_error_t csi_usi_uart_link_dma(csi_uart_t *uart, csi_dma_ch_t *tx_dma, csi_dma_ch_t *rx_dma); - -/** - \brief Get the state of uart device. - \param[in] uart UART handle to operate. - \param[out] state The state of uart device. - \return Error code. -*/ -csi_error_t csi_usi_uart_get_state(csi_uart_t *uart, csi_state_t *state); - -/** - \brief Enable uart power manage. - \param[in] uart UART handle to operate. - \return Error code. -*/ -csi_error_t csi_usi_uart_enable_pm(csi_uart_t *uart); - -/** - \brief Disable uart power manage. - \param[in] uart UART handle to operate. -*/ -void csi_usi_uart_disable_pm(csi_uart_t *uart); -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_USI_USART_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/wdt.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/wdt.h deleted file mode 100755 index d7a824ec..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/drv/wdt.h +++ /dev/null @@ -1,139 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file drv/wdt.h - * @brief Header File for WDT Driver - * @version V1.0 - * @date 9. Oct 2020 - * @model wdt - ******************************************************************************/ - -#ifndef _DRV_WDT_H_ -#define _DRV_WDT_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct csi_wdt csi_wdt_t; - -struct csi_wdt { - csi_dev_t dev; - void (*callback)(csi_wdt_t *wdt, void *arg); - void *arg; - void *priv; -}; - -/** - \brief Initialize WDT interface. Initializes the resources needed for the WDT interface - \param[in] wdt Handle to operate - \param[in] idx WDT index - \return Error code \ref csi_error_t -*/ -csi_error_t csi_wdt_init(csi_wdt_t *wdt, uint32_t idx); - -/** - \brief De-initialize WDT interface. Stops operation and releases the software resources used by the interface - \param[in] wdt Handle to operate - \return None -*/ -void csi_wdt_uninit(csi_wdt_t *wdt); - -/** - \brief Set the WDT value - \param[in] wdt Handle to operate - \param[in] ms The timeout value(ms) - \return Error code \ref csi_error_t -*/ -csi_error_t csi_wdt_set_timeout(csi_wdt_t *wdt, uint32_t ms); - -/** - \brief Start the WDT - \param[in] wdt Handle to operate - \return Error code \ref csi_error_t -*/ -csi_error_t csi_wdt_start(csi_wdt_t *wdt); - -/** - \brief Stop the WDT - \param[in] wdt Handle to operate - \return None -*/ -void csi_wdt_stop(csi_wdt_t *wdt); - -/** - \brief Feed the WDT - \param[in] wdt Handle to operate - \return Error code \ref csi_error_t -*/ -csi_error_t csi_wdt_feed(csi_wdt_t *wdt); - -/** - \brief Get the remaining time to timeout - \param[in] wdt Handle to operate - \return The remaining time of WDT(ms) -*/ -uint32_t csi_wdt_get_remaining_time(csi_wdt_t *wdt); - -/** - \brief Check WDT is running - \param[in] wdt Handle to operate - \return - true - WDT is running - false - WDT is stopped -*/ -bool csi_wdt_is_running(csi_wdt_t *wdt); - -/** - \brief Attach the callback handler to WDT - \param[in] wdt Handle to operate - \param[in] callback Callback function - \param[in] arg Callback's param - \return Error code \ref csi_error_t -*/ -csi_error_t csi_wdt_attach_callback(csi_wdt_t *wdt, void *callback, void *arg); - -/** - \brief Detach the callback handler - \param[in] wdt Handle to operate - \return None -*/ -void csi_wdt_detach_callback(csi_wdt_t *wdt); - -/** - \brief Enable WDT power manage - \param[in] wdt Handle to operate - \return Error code \ref csi_error_t -*/ -csi_error_t csi_wdt_enable_pm(csi_wdt_t *wdt); - -/** - \brief Disable WDT power manage - \param[in] wdt Handle to operate - \return None -*/ -void csi_wdt_disable_pm(csi_wdt_t *wdt); - -#ifdef __cplusplus -} -#endif - -#endif /* _DRV_WDT_H_ */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csi_common_tables.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csi_common_tables.h deleted file mode 100644 index 7d5e4028..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csi_common_tables.h +++ /dev/null @@ -1,316 +0,0 @@ -/* - * Copyright (C) 2016-2019 C-SKY Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file csi_common_tables.h - * @brief This file has extern declaration for common tables like - * Bitreverse, reciprocal etc which are used across different functions. - * @version V1.0 - * @date 20. Dec 2016 - ******************************************************************************/ - -#ifndef _CSI_COMMON_TABLES_H -#define _CSI_COMMON_TABLES_H - -#include "csi_math.h" - -extern const uint16_t csiBitRevTable[1024]; -extern const q15_t csiRecipTableQ15[64]; -extern const q31_t csiRecipTableQ31[64]; -extern const uint32_t twiddleCoef_16[32]; -extern const uint32_t twiddleCoef_32[64]; -extern const uint32_t twiddleCoef_64[128]; -extern const uint32_t twiddleCoef_128[256]; -extern const uint32_t twiddleCoef_256[512]; -extern const uint32_t twiddleCoef_512[1024]; -extern const uint32_t twiddleCoef_1024[2048]; -extern const uint32_t twiddleCoef_2048[4096]; -extern const uint32_t twiddleCoef_4096[8192]; -extern const q31_t twiddleCoef_16_q31[24]; -extern const q31_t twiddleCoef_32_q31[48]; -extern const q31_t twiddleCoef_64_q31[96]; -extern const q31_t twiddleCoef_128_q31[192]; -extern const q31_t twiddleCoef_256_q31[384]; -extern const q31_t twiddleCoef_512_q31[768]; -extern const q31_t twiddleCoef_1024_q31[1536]; -extern const q31_t twiddleCoef_2048_q31[3072]; -extern const q31_t twiddleCoef_4096_q31[6144]; -extern const q15_t twiddleCoef_16_q15[24]; -extern const q15_t twiddleCoef_32_q15[48]; -extern const q15_t twiddleCoef_64_q15[96]; -extern const q15_t twiddleCoef_128_q15[192]; -extern const q15_t twiddleCoef_256_q15[384]; -extern const q15_t twiddleCoef_512_q15[768]; -extern const q15_t twiddleCoef_1024_q15[1536]; -extern const q15_t twiddleCoef_2048_q15[3072]; -extern const q15_t twiddleCoef_4096_q15[6144]; -extern const float32_t twiddleCoef_rfft_32[32]; -extern const float32_t twiddleCoef_rfft_64[64]; -extern const float32_t twiddleCoef_rfft_128[128]; -extern const float32_t twiddleCoef_rfft_256[256]; -extern const float32_t twiddleCoef_rfft_512[512]; -extern const float32_t twiddleCoef_rfft_1024[1024]; -extern const float32_t twiddleCoef_rfft_2048[2048]; -extern const float32_t twiddleCoef_rfft_4096[4096]; -extern const float32_t twiddleCoef_rfft_8192[8192]; - -extern const q15_t twiddleCoef_fast_16_q15[24]; -extern const q15_t twiddleCoef_fast_32_q15[56]; -extern const q15_t twiddleCoef_fast_64_q15[120]; -extern const q15_t twiddleCoef_fast_128_q15[248]; -extern const q15_t twiddleCoef_fast_256_q15[504]; -extern const q15_t twiddleCoef_fast_512_q15[1016]; -extern const q15_t twiddleCoef_fast_1024_q15[2040]; -extern const q15_t twiddleCoef_fast_2048_q15[4088]; -extern const q15_t twiddleCoef_fast_4096_q15[8184]; - -extern const q31_t twiddleCoef_fast_16_q31[24]; -extern const q31_t twiddleCoef_fast_32_q31[56]; -extern const q31_t twiddleCoef_fast_64_q31[120]; -extern const q31_t twiddleCoef_fast_128_q31[248]; -extern const q31_t twiddleCoef_fast_256_q31[504]; -extern const q31_t twiddleCoef_fast_512_q31[1016]; -extern const q31_t twiddleCoef_fast_1024_q31[2040]; -extern const q31_t twiddleCoef_fast_2048_q31[4088]; -extern const q31_t twiddleCoef_fast_4096_q31[8184]; - -extern const uint32_t twiddleCoef_fast_16[24]; -extern const uint32_t twiddleCoef_fast_32[56]; -extern const uint32_t twiddleCoef_fast_64[120]; -extern const uint32_t twiddleCoef_fast_128[248]; -extern const uint32_t twiddleCoef_fast_256[504]; -extern const uint32_t twiddleCoef_fast_512[1016]; -extern const uint32_t twiddleCoef_fast_1024[2040]; -extern const uint32_t twiddleCoef_fast_2048[4088]; -extern const uint32_t twiddleCoef_fast_4096[8184]; - -extern const q15_t realCoefAQ15_8192[8192]; -extern const q31_t realCoefAQ31_8192[8192]; -extern const q15_t realCoefBQ15_8192[8192]; -extern const q31_t realCoefBQ31_8192[8192]; - -/*Tables for RFFT.*/ -extern const q15_t ALIGN4 realCoefAQ15_32[32]; -extern const q15_t ALIGN4 realCoefAQ15_64[64]; -extern const q15_t ALIGN4 realCoefAQ15_128[128]; -extern const q15_t ALIGN4 realCoefAQ15_256[256]; -extern const q15_t ALIGN4 realCoefAQ15_512[512]; -extern const q15_t ALIGN4 realCoefAQ15_1024[1024]; -extern const q15_t ALIGN4 realCoefAQ15_2048[2048]; -extern const q15_t ALIGN4 realCoefAQ15_4096[4096]; - -extern const q15_t ALIGN4 realCoefBQ15_32[32]; -extern const q15_t ALIGN4 realCoefBQ15_64[64]; -extern const q15_t ALIGN4 realCoefBQ15_128[128]; -extern const q15_t ALIGN4 realCoefBQ15_256[256]; -extern const q15_t ALIGN4 realCoefBQ15_512[512]; -extern const q15_t ALIGN4 realCoefBQ15_1024[1024]; -extern const q15_t ALIGN4 realCoefBQ15_2048[2048]; -extern const q15_t ALIGN4 realCoefBQ15_4096[4096]; - -extern const q31_t realCoefAQ31_32[32]; -extern const q31_t realCoefAQ31_64[64]; -extern const q31_t realCoefAQ31_128[128]; -extern const q31_t realCoefAQ31_256[256]; -extern const q31_t realCoefAQ31_512[512]; -extern const q31_t realCoefAQ31_1024[1024]; -extern const q31_t realCoefAQ31_2048[2048]; -extern const q31_t realCoefAQ31_4096[4096]; - -extern const q31_t realCoefBQ31_32[32]; -extern const q31_t realCoefBQ31_64[64]; -extern const q31_t realCoefBQ31_128[128]; -extern const q31_t realCoefBQ31_256[256]; -extern const q31_t realCoefBQ31_512[512]; -extern const q31_t realCoefBQ31_1024[1024]; -extern const q31_t realCoefBQ31_2048[2048]; -extern const q31_t realCoefBQ31_4096[4096]; - - -extern const float32_t realCoefA[8192]; -extern const float32_t realCoefB[8192]; - -extern const csi_cfft_instance_q15 csi_cfft_fast_sR_q15_len16; -extern const csi_cfft_instance_q15 csi_cfft_fast_sR_q15_len32; -extern const csi_cfft_instance_q15 csi_cfft_fast_sR_q15_len64; -extern const csi_cfft_instance_q15 csi_cfft_fast_sR_q15_len128; -extern const csi_cfft_instance_q15 csi_cfft_fast_sR_q15_len256; -extern const csi_cfft_instance_q15 csi_cfft_fast_sR_q15_len512; -extern const csi_cfft_instance_q15 csi_cfft_fast_sR_q15_len1024; -extern const csi_cfft_instance_q15 csi_cfft_fast_sR_q15_len2048; -extern const csi_cfft_instance_q15 csi_cfft_fast_sR_q15_len4096; - -extern const csi_cfft_instance_q31 csi_cfft_fast_sR_q31_len16; -extern const csi_cfft_instance_q31 csi_cfft_fast_sR_q31_len32; -extern const csi_cfft_instance_q31 csi_cfft_fast_sR_q31_len64; -extern const csi_cfft_instance_q31 csi_cfft_fast_sR_q31_len128; -extern const csi_cfft_instance_q31 csi_cfft_fast_sR_q31_len256; -extern const csi_cfft_instance_q31 csi_cfft_fast_sR_q31_len512; -extern const csi_cfft_instance_q31 csi_cfft_fast_sR_q31_len1024; -extern const csi_cfft_instance_q31 csi_cfft_fast_sR_q31_len2048; -extern const csi_cfft_instance_q31 csi_cfft_fast_sR_q31_len4096; - -extern csi_rfft_fast_instance_q15 csi_rfft_fast_sR_q15_len32; -extern csi_rfft_fast_instance_q15 csi_rfft_fast_sR_q15_len64; -extern csi_rfft_fast_instance_q15 csi_rfft_fast_sR_q15_len128; -extern csi_rfft_fast_instance_q15 csi_rfft_fast_sR_q15_len256; -extern csi_rfft_fast_instance_q15 csi_rfft_fast_sR_q15_len512; -extern csi_rfft_fast_instance_q15 csi_rfft_fast_sR_q15_len1024; -extern csi_rfft_fast_instance_q15 csi_rfft_fast_sR_q15_len2048; -extern csi_rfft_fast_instance_q15 csi_rfft_fast_sR_q15_len4096; -extern csi_rfft_fast_instance_q15 csi_rfft_fast_sR_q15_len8192; - -extern csi_rfft_fast_instance_q15 csi_inv_rfft_fast_sR_q15_len32; -extern csi_rfft_fast_instance_q15 csi_inv_rfft_fast_sR_q15_len64; -extern csi_rfft_fast_instance_q15 csi_inv_rfft_fast_sR_q15_len128; -extern csi_rfft_fast_instance_q15 csi_inv_rfft_fast_sR_q15_len256; -extern csi_rfft_fast_instance_q15 csi_inv_rfft_fast_sR_q15_len512; -extern csi_rfft_fast_instance_q15 csi_inv_rfft_fast_sR_q15_len1024; -extern csi_rfft_fast_instance_q15 csi_inv_rfft_fast_sR_q15_len2048; -extern csi_rfft_fast_instance_q15 csi_inv_rfft_fast_sR_q15_len4096; -extern csi_rfft_fast_instance_q15 csi_inv_rfft_fast_sR_q15_len8192; - -extern csi_rfft_fast_instance_q31 csi_rfft_fast_sR_q31_len32; -extern csi_rfft_fast_instance_q31 csi_rfft_fast_sR_q31_len64; -extern csi_rfft_fast_instance_q31 csi_rfft_fast_sR_q31_len128; -extern csi_rfft_fast_instance_q31 csi_rfft_fast_sR_q31_len256; -extern csi_rfft_fast_instance_q31 csi_rfft_fast_sR_q31_len512; -extern csi_rfft_fast_instance_q31 csi_rfft_fast_sR_q31_len1024; -extern csi_rfft_fast_instance_q31 csi_rfft_fast_sR_q31_len2048; -extern csi_rfft_fast_instance_q31 csi_rfft_fast_sR_q31_len4096; -extern csi_rfft_fast_instance_q31 csi_rfft_fast_sR_q31_len8192; - -extern csi_rfft_fast_instance_q31 csi_inv_rfft_fast_sR_q31_len32; -extern csi_rfft_fast_instance_q31 csi_inv_rfft_fast_sR_q31_len64; -extern csi_rfft_fast_instance_q31 csi_inv_rfft_fast_sR_q31_len128; -extern csi_rfft_fast_instance_q31 csi_inv_rfft_fast_sR_q31_len256; -extern csi_rfft_fast_instance_q31 csi_inv_rfft_fast_sR_q31_len512; -extern csi_rfft_fast_instance_q31 csi_inv_rfft_fast_sR_q31_len1024; -extern csi_rfft_fast_instance_q31 csi_inv_rfft_fast_sR_q31_len2048; -extern csi_rfft_fast_instance_q31 csi_inv_rfft_fast_sR_q31_len4096; -extern csi_rfft_fast_instance_q31 csi_inv_rfft_fast_sR_q31_len8192; - -extern csi_dct4_fast_instance_q15 csi_dct4_fast_sR_q15_len128; -extern csi_dct4_fast_instance_q15 csi_dct4_fast_sR_q15_len512; -extern csi_dct4_fast_instance_q15 csi_dct4_fast_sR_q15_len2048; -extern csi_dct4_fast_instance_q15 csi_dct4_fast_sR_q15_len8192; - -extern csi_dct4_fast_instance_q31 csi_dct4_fast_sR_q31_len128; -extern csi_dct4_fast_instance_q31 csi_dct4_fast_sR_q31_len512; -extern csi_dct4_fast_instance_q31 csi_dct4_fast_sR_q31_len2048; -extern csi_dct4_fast_instance_q31 csi_dct4_fast_sR_q31_len8192; - -/*Tables for DCT4*/ -#ifndef CSI_OPT_WEIGHT -extern const q15_t ALIGN4 WeightsQ15_128[256]; -extern const q15_t ALIGN4 WeightsQ15_512[1024]; -extern const q15_t ALIGN4 WeightsQ15_2048[4096]; -extern const q15_t ALIGN4 WeightsQ15_8192[16384]; -#else -extern const q15_t ALIGN4 WeightsQ15_128[128+2]; -extern const q15_t ALIGN4 WeightsQ15_512[512+2]; -extern const q15_t ALIGN4 WeightsQ15_2048[2048+2]; -extern const q15_t ALIGN4 WeightsQ15_8192[8192+2]; -#endif -extern const q15_t ALIGN4 cos_factorsQ15_128[128]; -extern const q15_t ALIGN4 cos_factorsQ15_512[512]; -extern const q15_t ALIGN4 cos_factorsQ15_2048[2048]; -extern const q15_t ALIGN4 cos_factorsQ15_8192[8192]; - -#ifndef CSI_OPT_WEIGHT -extern const q31_t WeightsQ31_128[256]; -extern const q31_t WeightsQ31_512[1024]; -extern const q31_t WeightsQ31_2048[4096]; -extern const q31_t WeightsQ31_8192[16384]; -#else -extern const q31_t WeightsQ31_128[128+2]; -extern const q31_t WeightsQ31_512[512+2]; -extern const q31_t WeightsQ31_2048[2048+2]; -extern const q31_t WeightsQ31_8192[8192+2]; -#endif - -extern const q31_t cos_factorsQ31_128[128]; -extern const q31_t cos_factorsQ31_512[512]; -extern const q31_t cos_factorsQ31_2048[2048]; -extern const q31_t cos_factorsQ31_8192[8192]; - -#ifndef CSI_OPT_WEIGHT -extern const float32_t Weights_128[256]; -extern const float32_t Weights_512[1024]; -extern const float32_t Weights_2048[4096]; -extern const float32_t Weights_8192[16384]; - -#else -extern const float32_t Weights_128[128+2]; -extern const float32_t Weights_512[512+2]; -extern const float32_t Weights_2048[2048+2]; -extern const float32_t Weights_8192[8192+2]; -#endif -extern const float32_t cos_factors_128[128]; -extern const float32_t cos_factors_512[512]; -extern const float32_t cos_factors_2048[2048]; -extern const float32_t cos_factors_8192[8192]; - -/* floating-point bit reversal tables */ -#define CSIBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20 ) -#define CSIBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48 ) -#define CSIBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56 ) -#define CSIBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) -#define CSIBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) -#define CSIBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) -#define CSIBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) -#define CSIBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) -#define CSIBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t csiBitRevIndexTable16[CSIBITREVINDEXTABLE_16_TABLE_LENGTH]; -extern const uint16_t csiBitRevIndexTable32[CSIBITREVINDEXTABLE_32_TABLE_LENGTH]; -extern const uint16_t csiBitRevIndexTable64[CSIBITREVINDEXTABLE_64_TABLE_LENGTH]; -extern const uint16_t csiBitRevIndexTable128[CSIBITREVINDEXTABLE_128_TABLE_LENGTH]; -extern const uint16_t csiBitRevIndexTable256[CSIBITREVINDEXTABLE_256_TABLE_LENGTH]; -extern const uint16_t csiBitRevIndexTable512[CSIBITREVINDEXTABLE_512_TABLE_LENGTH]; -extern const uint16_t csiBitRevIndexTable1024[CSIBITREVINDEXTABLE_1024_TABLE_LENGTH]; -extern const uint16_t csiBitRevIndexTable2048[CSIBITREVINDEXTABLE_2048_TABLE_LENGTH]; -extern const uint16_t csiBitRevIndexTable4096[CSIBITREVINDEXTABLE_4096_TABLE_LENGTH]; - -/* fixed-point bit reversal tables */ -#define CSIBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12 ) -#define CSIBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24 ) -#define CSIBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56 ) -#define CSIBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112 ) -#define CSIBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240 ) -#define CSIBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480 ) -#define CSIBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) -#define CSIBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) -#define CSIBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t csiBitRevIndexTable_fixed_16[CSIBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; -extern const uint16_t csiBitRevIndexTable_fixed_32[CSIBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; -extern const uint16_t csiBitRevIndexTable_fixed_64[CSIBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; -extern const uint16_t csiBitRevIndexTable_fixed_128[CSIBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; -extern const uint16_t csiBitRevIndexTable_fixed_256[CSIBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; -extern const uint16_t csiBitRevIndexTable_fixed_512[CSIBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; -extern const uint16_t csiBitRevIndexTable_fixed_1024[CSIBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; -extern const uint16_t csiBitRevIndexTable_fixed_2048[CSIBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; -extern const uint16_t csiBitRevIndexTable_fixed_4096[CSIBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; - -/* Tables for Fast Math Sine and Cosine */ -extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; -extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; -extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; - -#endif /* CSI_COMMON_TABLES_H */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csi_const_structs.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csi_const_structs.h deleted file mode 100644 index 09f8f367..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csi_const_structs.h +++ /dev/null @@ -1,157 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file csi_const_structs.h - * @brief Constant structs that are initialized for user convenience. - * @version V1.0 - * @date Feb. 2020 - ******************************************************************************/ - - -#ifndef _RISCV_CONST_STRUCTS_H -#define _RISCV_CONST_STRUCTS_H - -#include "csi_math.h" -#include "csi_common_tables.h" - -extern const csi_cfft_instance_f32 csi_cfft_radix4_fast_sR_f32_len16; -extern const csi_cfft_instance_f32 csi_cfft_radix4_fast_sR_f32_len32; -extern const csi_cfft_instance_f32 csi_cfft_radix4_fast_sR_f32_len64; -extern const csi_cfft_instance_f32 csi_cfft_radix4_fast_sR_f32_len128; -extern const csi_cfft_instance_f32 csi_cfft_radix4_fast_sR_f32_len256; -extern const csi_cfft_instance_f32 csi_cfft_radix4_fast_sR_f32_len512; -extern const csi_cfft_instance_f32 csi_cfft_radix4_fast_sR_f32_len1024; -extern const csi_cfft_instance_f32 csi_cfft_radix4_fast_sR_f32_len2048; -extern const csi_cfft_instance_f32 csi_cfft_radix4_fast_sR_f32_len4096; - -extern const csi_cfft_instance_f32 csi_cfft_radix2_sR_f32_len16; -extern const csi_cfft_instance_f32 csi_cfft_radix2_sR_f32_len32; -extern const csi_cfft_instance_f32 csi_cfft_radix2_sR_f32_len64; -extern const csi_cfft_instance_f32 csi_cfft_radix2_sR_f32_len128; -extern const csi_cfft_instance_f32 csi_cfft_radix2_sR_f32_len256; -extern const csi_cfft_instance_f32 csi_cfft_radix2_sR_f32_len512; -extern const csi_cfft_instance_f32 csi_cfft_radix2_sR_f32_len1024; -extern const csi_cfft_instance_f32 csi_cfft_radix2_sR_f32_len2048; -extern const csi_cfft_instance_f32 csi_cfft_radix2_sR_f32_len4096; - -extern const csi_cfft_instance_f32 csi_cfft_radix4_sR_f32_len16; -extern const csi_cfft_instance_f32 csi_cfft_radix4_sR_f32_len32; -extern const csi_cfft_instance_f32 csi_cfft_radix4_sR_f32_len64; -extern const csi_cfft_instance_f32 csi_cfft_radix4_sR_f32_len128; -extern const csi_cfft_instance_f32 csi_cfft_radix4_sR_f32_len256; -extern const csi_cfft_instance_f32 csi_cfft_radix4_sR_f32_len512; -extern const csi_cfft_instance_f32 csi_cfft_radix4_sR_f32_len1024; -extern const csi_cfft_instance_f32 csi_cfft_radix4_sR_f32_len2048; -extern const csi_cfft_instance_f32 csi_cfft_radix4_sR_f32_len4096; - -extern const csi_cfft_instance_f32 csi_cfft_sR_f32_len16 ; -extern const csi_cfft_instance_f32 csi_cfft_sR_f32_len32 ; -extern const csi_cfft_instance_f32 csi_cfft_sR_f32_len64 ; -extern const csi_cfft_instance_f32 csi_cfft_sR_f32_len128 ; -extern const csi_cfft_instance_f32 csi_cfft_sR_f32_len256 ; -extern const csi_cfft_instance_f32 csi_cfft_sR_f32_len512 ; -extern const csi_cfft_instance_f32 csi_cfft_sR_f32_len1024 ; -extern const csi_cfft_instance_f32 csi_cfft_sR_f32_len2048 ; -extern const csi_cfft_instance_f32 csi_cfft_sR_f32_len4096 ; -extern const csi_cfft_instance_q31 csi_cfft_sR_q31_len16 ; -extern const csi_cfft_instance_q31 csi_cfft_sR_q31_len32 ; -extern const csi_cfft_instance_q31 csi_cfft_sR_q31_len64 ; -extern const csi_cfft_instance_q31 csi_cfft_sR_q31_len128 ; -extern const csi_cfft_instance_q31 csi_cfft_sR_q31_len256 ; -extern const csi_cfft_instance_q31 csi_cfft_sR_q31_len512 ; -extern const csi_cfft_instance_q31 csi_cfft_sR_q31_len1024 ; -extern const csi_cfft_instance_q31 csi_cfft_sR_q31_len2048 ; -extern const csi_cfft_instance_q31 csi_cfft_sR_q31_len4096 ; -extern const csi_cfft_instance_q15 csi_cfft_sR_q15_len16 ; -extern const csi_cfft_instance_q15 csi_cfft_sR_q15_len32 ; -extern const csi_cfft_instance_q15 csi_cfft_sR_q15_len64 ; -extern const csi_cfft_instance_q15 csi_cfft_sR_q15_len128 ; -extern const csi_cfft_instance_q15 csi_cfft_sR_q15_len256 ; -extern const csi_cfft_instance_q15 csi_cfft_sR_q15_len512 ; -extern const csi_cfft_instance_q15 csi_cfft_sR_q15_len1024 ; -extern const csi_cfft_instance_q15 csi_cfft_sR_q15_len2048 ; -extern const csi_cfft_instance_q15 csi_cfft_sR_q15_len4096 ; -extern const csi_rfft_fast_instance_f32 csi_rfft_sR_f32_len32 ; -extern const csi_rfft_fast_instance_f32 csi_rfft_sR_f32_len64 ; -extern const csi_rfft_fast_instance_f32 csi_rfft_sR_f32_len128 ; -extern const csi_rfft_fast_instance_f32 csi_rfft_sR_f32_len256 ; -extern const csi_rfft_fast_instance_f32 csi_rfft_sR_f32_len512 ; -extern const csi_rfft_fast_instance_f32 csi_rfft_sR_f32_len1024 ; -extern const csi_rfft_fast_instance_f32 csi_rfft_sR_f32_len2048 ; -extern const csi_rfft_fast_instance_f32 csi_rfft_sR_f32_len4096 ; -extern const csi_rfft_fast_instance_f32 csi_rfft_sR_f32_len8192 ; -extern const csi_rfft_instance_q31 csi_rfft_sR_q31_len32 ; -extern const csi_rfft_instance_q31 csi_rfft_sR_q31_len64 ; -extern const csi_rfft_instance_q31 csi_rfft_sR_q31_len128 ; -extern const csi_rfft_instance_q31 csi_rfft_sR_q31_len256 ; -extern const csi_rfft_instance_q31 csi_rfft_sR_q31_len512 ; -extern const csi_rfft_instance_q31 csi_rfft_sR_q31_len1024 ; -extern const csi_rfft_instance_q31 csi_rfft_sR_q31_len2048 ; -extern const csi_rfft_instance_q31 csi_rfft_sR_q31_len4096 ; -extern const csi_rfft_instance_q31 csi_rfft_sR_q31_len8192 ; -extern const csi_rfft_instance_q15 csi_rfft_sR_q15_len32 ; -extern const csi_rfft_instance_q15 csi_rfft_sR_q15_len64 ; -extern const csi_rfft_instance_q15 csi_rfft_sR_q15_len128 ; -extern const csi_rfft_instance_q15 csi_rfft_sR_q15_len256 ; -extern const csi_rfft_instance_q15 csi_rfft_sR_q15_len512 ; -extern const csi_rfft_instance_q15 csi_rfft_sR_q15_len1024 ; -extern const csi_rfft_instance_q15 csi_rfft_sR_q15_len2048 ; -extern const csi_rfft_instance_q15 csi_rfft_sR_q15_len4096 ; -extern const csi_rfft_instance_q15 csi_rfft_sR_q15_len8192 ; -extern const csi_rfft_instance_f32 csi_inv_rfft_sR_f32_len32; -extern const csi_rfft_instance_f32 csi_inv_rfft_sR_f32_len64; -extern const csi_rfft_instance_f32 csi_inv_rfft_sR_f32_len128; -extern const csi_rfft_instance_f32 csi_inv_rfft_sR_f32_len256; -extern const csi_rfft_instance_f32 csi_inv_rfft_sR_f32_len512; -extern const csi_rfft_instance_f32 csi_inv_rfft_sR_f32_len1024; -extern const csi_rfft_instance_f32 csi_inv_rfft_sR_f32_len2048; -extern const csi_rfft_instance_f32 csi_inv_rfft_sR_f32_len4096; -extern const csi_rfft_instance_f32 csi_inv_rfft_sR_f32_len8192; -extern const csi_rfft_instance_q31 csi_inv_rfft_sR_q31_len32; -extern const csi_rfft_instance_q31 csi_inv_rfft_sR_q31_len64; -extern const csi_rfft_instance_q31 csi_inv_rfft_sR_q31_len128; -extern const csi_rfft_instance_q31 csi_inv_rfft_sR_q31_len256; -extern const csi_rfft_instance_q31 csi_inv_rfft_sR_q31_len512; -extern const csi_rfft_instance_q31 csi_inv_rfft_sR_q31_len1024; -extern const csi_rfft_instance_q31 csi_inv_rfft_sR_q31_len2048; -extern const csi_rfft_instance_q31 csi_inv_rfft_sR_q31_len4096; -extern const csi_rfft_instance_q31 csi_inv_rfft_sR_q31_len8192; -extern const csi_rfft_instance_q15 csi_inv_rfft_sR_q15_len32; -extern const csi_rfft_instance_q15 csi_inv_rfft_sR_q15_len64; -extern const csi_rfft_instance_q15 csi_inv_rfft_sR_q15_len128; -extern const csi_rfft_instance_q15 csi_inv_rfft_sR_q15_len256; -extern const csi_rfft_instance_q15 csi_inv_rfft_sR_q15_len512; -extern const csi_rfft_instance_q15 csi_inv_rfft_sR_q15_len1024; -extern const csi_rfft_instance_q15 csi_inv_rfft_sR_q15_len2048; -extern const csi_rfft_instance_q15 csi_inv_rfft_sR_q15_len4096; -extern const csi_rfft_instance_q15 csi_inv_rfft_sR_q15_len8192; -extern const csi_dct4_instance_q31 csi_dct4_sR_q31_len128; -extern const csi_dct4_instance_q31 csi_dct4_sR_q31_len512; -extern const csi_dct4_instance_q31 csi_dct4_sR_q31_len2048; -extern const csi_dct4_instance_q31 csi_dct4_sR_q31_len8192; -extern const csi_dct4_instance_q15 csi_dct4_sR_q15_len128; -extern const csi_dct4_instance_q15 csi_dct4_sR_q15_len512; -extern const csi_dct4_instance_q15 csi_dct4_sR_q15_len2048; -extern const csi_dct4_instance_q15 csi_dct4_sR_q15_len8192; -extern const csi_dct4_instance_f32 csi_dct4_sR_f32_len128; -extern const csi_dct4_instance_f32 csi_dct4_sR_f32_len512; -extern const csi_dct4_instance_f32 csi_dct4_sR_f32_len2048; -extern const csi_dct4_instance_f32 csi_dct4_sR_f32_len8192; - -#endif diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csi_instance.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csi_instance.h deleted file mode 100644 index a1aa7131..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csi_instance.h +++ /dev/null @@ -1,1879 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file csi_instance.h - * @brief Some common define - * @version V1.0 - * @date Feb. 2020 - ******************************************************************************/ - - -#ifndef _CSI_INSTANCE_H -#define _CSI_INSTANCE_H - -#ifdef __cplusplus -extern "C" -{ -#endif - - -#include -#include -#include -#include -#include -#ifndef __CK860__ -#include "csi_core.h" -#else -#include -#endif - -#define LOW_OPTIMIZATION_ENTER -#define LOW_OPTIMIZATION_EXIT - -#define F64_MAX ((float64_t)DBL_MAX) -#define F32_MAX ((float32_t)FLT_MAX) - -#define F64_MIN (-DBL_MAX) -#define F32_MIN (-FLT_MAX) - -#define F64_ABSMAX ((float64_t)DBL_MAX) -#define F32_ABSMAX ((float32_t)FLT_MAX) - -#define F64_ABSMIN ((float64_t)0.0) -#define F32_ABSMIN ((float32_t)0.0) - -#define Q31_MAX ((q31_t)(0x7FFFFFFFL)) -#define Q15_MAX ((q15_t)(0x7FFF)) -#define Q7_MAX ((q7_t)(0x7F)) -#define Q31_MIN ((q31_t)(0x80000000L)) -#define Q15_MIN ((q15_t)(0x8000)) -#define Q7_MIN ((q7_t)(0x80)) - -#define Q31_ABSMAX ((q31_t)(0x7FFFFFFFL)) -#define Q15_ABSMAX ((q15_t)(0x7FFF)) -#define Q7_ABSMAX ((q7_t)(0x7F)) -#define Q31_ABSMIN ((q31_t)0) -#define Q15_ABSMIN ((q15_t)0) -#define Q7_ABSMIN ((q7_t)0) - -/** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 ((q31_t)(0x100)) -#define DELTA_Q15 ((q15_t)0x5) -#define INDEX_MASK 0x0000003F -#ifndef PI -#define PI 3.14159265358979f -#endif - -#ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 -#else - #define ALIGN4 __attribute__((aligned(4))) -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - -/** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define FAST_MATH_TABLE_SIZE 512 -#define FAST_MATH_Q31_SHIFT (32 - 10) -#define FAST_MATH_Q15_SHIFT (16 - 10) -#define CONTROLLER_Q31_SHIFT (32 - 9) -#define TABLE_SPACING_Q31 0x400000 -#define TABLE_SPACING_Q15 0x80 - -#define __STATIC_FORCEINLINE static inline __attribute__((unused)) -#define CSI_NEWTON_SQRTF -#ifdef __CK860__ -#define __STATIC_INLINE static inline __attribute__((unused)) - -#define __ALWAYS_STATIC_INLINE __attribute__((always_inline)) static inline - -#endif - - -/** - * @brief Macros required for SINE and COSINE Controller functions - */ -/* 1.31(q31) Fixed value of 2/360 */ -/* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - -/** - * @brief Macros for complex numbers - */ - -/* Dimension C vector space */ -#define CMPLX_DIM 2 - -/** - * @brief Error status returned by some functions in the library. - */ - -typedef enum { - CSI_MATH_SUCCESS = 0, /**< No error */ - CSI_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - CSI_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - CSI_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation */ - CSI_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - CSI_MATH_SINGULAR = -5, /**< Input matrix is singular and cannot be inverted */ - CSI_MATH_TEST_FAILURE = -6 /**< Test Failed */ -} csi_status; - -/** - * @brief 8-bit fractional data type in 1.7 format. - */ -typedef int8_t q7_t; - -/** - * @brief 16-bit fractional data type in 1.15 format. - */ -typedef int16_t q15_t; - -/** - * @brief 32-bit fractional data type in 1.31 format. - */ -typedef int32_t q31_t; - -/** - * @brief 64-bit fractional data type in 1.63 format. - */ -typedef int64_t q63_t; - -/** - * @brief 32-bit floating-point type definition. - */ -typedef float float32_t; - -/** - * @brief 64-bit floating-point type definition. - */ -typedef double float64_t; - -/** - @brief definition to read/write two 16 bit values. - @deprecated - */ -#define __SIMD32_TYPE int32_t -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr)) -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr)) -#define __SIMD64(addr) (*( int64_t **) & (addr)) - -#define STEP(x) (x) <= 0 ? 0 : 1 -#define SQ(x) ((x) * (x)) - -__ALWAYS_STATIC_INLINE int32_t __SSAT_31(int32_t x) -{ - int32_t res = x; - if (x > 0x3fffffff) { - res = 0x3fffffff; - } else if (x < -1073741824) { - res = -1073741824; - } - - return res; -} - -__ALWAYS_STATIC_INLINE int32_t __SSAT_16(int32_t x) -{ - int32_t res = x; - if (x > 0x7fff) { - res = 0x7fff; - } else if (x < -32768) { - res = -32768; - } - - return res; -} - -__ALWAYS_STATIC_INLINE int32_t __SSAT_8(int32_t x) -{ - int32_t res = x; - if (x > 0x7f) { - res = 0x7f; - } else if (x < -128) { - res = -128; - } - - return res; -} - -/** - @brief Read 2 Q15 from Q15 pointer. - @param[in] pQ15 points to input value - @return Q31 value - */ -__STATIC_FORCEINLINE q31_t read_q15x2 ( - q15_t * pQ15) -{ - q31_t val; - memcpy (&val, pQ15, 4); - return (val); -} - -/** - @brief Read 2 Q15 from Q15 pointer and increment pointer afterwards. - @param[in] pQ15 points to input value - @return Q31 value - */ -__STATIC_FORCEINLINE q31_t read_q15x2_ia ( - q15_t ** pQ15) -{ - q31_t val; - memcpy (&val, *pQ15, 4); - *pQ15 += 2; - return (val); -} - -/** - @brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards. - @param[in] pQ15 points to input value - @return Q31 value - */ -__STATIC_FORCEINLINE q31_t read_q15x2_da ( - q15_t ** pQ15) -{ - q31_t val; - memcpy (&val, *pQ15, 4); - *pQ15 -= 2; - return (val); -} - -/** - @brief Write 2 Q15 to Q15 pointer and increment pointer afterwards. - @param[in] pQ15 points to input value - @param[in] value Q31 value - @return none - */ -__STATIC_FORCEINLINE void write_q15x2_ia ( - q15_t ** pQ15, - q31_t value) -{ - q31_t val = value; - memcpy (*pQ15, &val, 4); - *pQ15 += 2; -} - -/** - @brief Write 2 Q15 to Q15 pointer. - @param[in] pQ15 points to input value - @param[in] value Q31 value - @return none - */ -__STATIC_FORCEINLINE void write_q15x2 ( - q15_t * pQ15, - q31_t value) -{ - q31_t val = value; - memcpy (pQ15, &val, 4); -} - - -/** - @brief Read 4 Q7 from Q7 pointer and increment pointer afterwards. - @param[in] pQ7 points to input value - @return Q31 value - */ -__STATIC_FORCEINLINE q31_t read_q7x4_ia ( - q7_t ** pQ7) -{ - q31_t val; - memcpy (&val, *pQ7, 4); - *pQ7 += 4; - return (val); -} - -/** - @brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards. - @param[in] pQ7 points to input value - @return Q31 value - */ -__STATIC_FORCEINLINE q31_t read_q7x4_da ( - q7_t ** pQ7) -{ - q31_t val; - memcpy (&val, *pQ7, 4); - *pQ7 -= 4; - return (val); -} - -/** - @brief Write 4 Q7 to Q7 pointer and increment pointer afterwards. - @param[in] pQ7 points to input value - @param[in] value Q31 value - @return none - */ -__STATIC_FORCEINLINE void write_q7x4_ia ( - q7_t ** pQ7, - q31_t value) -{ - q31_t val = value; - memcpy (*pQ7, &val, 4); - *pQ7 += 4; -} - -#ifdef __CK860__ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data) -{ - if (data == 0U) { - return 32U; - } - - uint32_t count = 0U; - uint32_t mask = 0x80000000U; - - while ((data & mask) == 0U) { - count += 1U; - mask = mask >> 1U; - } - - return count; -} - -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - - if (val > max) { - return max; - - } else if (val < min) { - return min; - } - } - - return val; -} - -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) { - const uint32_t max = ((1U << sat) - 1U); - - if (val > (int32_t)max) { - return max; - - } else if (val < 0) { - return 0U; - } - } - - return (uint32_t)val; -} -#endif -/** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - - -/** -* @brief definition to pack four 8 bit values. -*/ -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) - -/** - * @brief Clips Q63 to Q31 values. - */ -__STATIC_FORCEINLINE q31_t clip_q63_to_q31( - q63_t x) -{ - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; -} - -/** - * @brief Clips Q63 to Q15 values. - */ -__STATIC_FORCEINLINE q15_t clip_q63_to_q15( - q63_t x) -{ - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); -} - -/** - * @brief Clips Q31 to Q7 values. - */ -__STATIC_FORCEINLINE q7_t clip_q31_to_q7( - q31_t x) -{ - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; -} - -/** - * @brief Clips Q31 to Q15 values. - */ -__STATIC_FORCEINLINE q15_t clip_q31_to_q15( - q31_t x) -{ - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; -} - -/** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ -__STATIC_FORCEINLINE q63_t mult32x64( - q63_t x, - q31_t y) -{ - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y) ) ); -} - -/** - * @brief Integer exponentiation - * @param[in] x value - * @param[in] nb integer exponent >= 1 - * @return x^nb - * - */ -__STATIC_INLINE float32_t csi_exponent_f32(float32_t x, int32_t nb) -{ - float32_t r = x; - nb --; - - while(nb > 0) { - r = r * x; - nb--; - } - - return(r); -} - -/** - * @brief 64-bit to 32-bit unsigned normalization - * @param[in] in is input unsigned long long value - * @param[out] normalized is the 32-bit normalized value - * @param[out] norm is norm scale - */ -__STATIC_INLINE void csi_norm_64_to_32u(uint64_t in, int32_t * normalized, int32_t *norm) -{ - int32_t n1; - int32_t hi = (int32_t) (in >> 32); - int32_t lo = (int32_t) ((in << 32) >> 32); - n1 = __CLZ(hi) - 32; - - if (!n1) { - /* - * input fits in 32-bit - */ - n1 = __CLZ(lo); - - if (!n1) { - /* - * MSB set, need to scale down by 1 - */ - *norm = -1; - *normalized = (((uint32_t) lo) >> 1); - - } else { - if (n1 == 32) { - /* - * input is zero - */ - *norm = 0; - *normalized = 0; - - } else { - /* - * 32-bit normalization - */ - *norm = n1 - 1; - *normalized = lo << *norm; - } - } - - } else { - /* - * input fits in 64-bit - */ - n1 = 1 - n1; - *norm = -n1; - /* - * 64 bit normalization - */ - *normalized = (((uint32_t) lo) >> n1) | (hi << (32 - n1)); - } -} - -__STATIC_INLINE q31_t csi_div_q63_to_q31(q63_t num, q31_t den) -{ - q31_t result; - uint64_t absNum; - int32_t normalized; - int32_t norm; - /* - * if sum fits in 32bits - * avoid costly 64-bit division - */ - absNum = num > 0 ? num : -num; - csi_norm_64_to_32u(absNum, &normalized, &norm); - - if (norm > 0) - /* - * 32-bit division - */ - result = (q31_t) num / den; - - else - /* - * 64-bit division - */ - result = (q31_t) (num / den); - - return result; -} - -/* - * @brief C custom defined intrinsic functions - */ -#ifdef __CK860__ -/* - * @brief C custom defined QADD8 - */ -__STATIC_FORCEINLINE uint32_t __QADD8( - uint32_t x, - uint32_t y) -{ - q31_t r, s, t, u; - r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); -} - - -/* - * @brief C custom defined QSUB8 - */ -__STATIC_FORCEINLINE uint32_t __QSUB8( - uint32_t x, - uint32_t y) -{ - q31_t r, s, t, u; - r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); -} - - -/* - * @brief C custom defined QADD16 - */ -__STATIC_FORCEINLINE uint32_t __QADD16( - uint32_t x, - uint32_t y) -{ - /* q31_t r, s; without initialisation 'csi_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ - q31_t r = 0, s = 0; - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - return ((uint32_t)((s << 16) | (r ))); -} - - -/* - * @brief C custom defined SHADD16 - */ -__STATIC_FORCEINLINE uint32_t __SHADD16( - uint32_t x, - uint32_t y) -{ - q31_t r, s; - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - return ((uint32_t)((s << 16) | (r ))); -} - - -/* - * @brief C custom defined QSUB16 - */ -__STATIC_FORCEINLINE uint32_t __QSUB16( - uint32_t x, - uint32_t y) -{ - q31_t r, s; - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - return ((uint32_t)((s << 16) | (r ))); -} - - -/* - * @brief C custom defined SHSUB16 - */ -__STATIC_FORCEINLINE uint32_t __SHSUB16( - uint32_t x, - uint32_t y) -{ - q31_t r, s; - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - return ((uint32_t)((s << 16) | (r ))); -} - - -/* - * @brief C custom defined QASX - */ -__STATIC_FORCEINLINE uint32_t __QASX( - uint32_t x, - uint32_t y) -{ - q31_t r, s; - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - return ((uint32_t)((s << 16) | (r ))); -} - - -/* - * @brief C custom defined SHASX - */ -__STATIC_FORCEINLINE uint32_t __SHASX( - uint32_t x, - uint32_t y) -{ - q31_t r, s; - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - return ((uint32_t)((s << 16) | (r ))); -} - - -/* - * @brief C custom defined QSAX - */ -__STATIC_FORCEINLINE uint32_t __QSAX( - uint32_t x, - uint32_t y) -{ - q31_t r, s; - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - return ((uint32_t)((s << 16) | (r ))); -} - - -/* - * @brief C custom defined SHSAX - */ -__STATIC_FORCEINLINE uint32_t __SHSAX( - uint32_t x, - uint32_t y) -{ - q31_t r, s; - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - return ((uint32_t)((s << 16) | (r ))); -} - - -/* - * @brief C custom defined SMUSDX - */ -__STATIC_FORCEINLINE uint32_t __SMUSDX( - uint32_t x, - uint32_t y) -{ - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); -} - -/* - * @brief C custom defined SMUADX - */ -__STATIC_FORCEINLINE uint32_t __SMUADX( - uint32_t x, - uint32_t y) -{ - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); -} - - -/* - * @brief C custom defined QADD - */ -__STATIC_FORCEINLINE int32_t __QADD( - int32_t x, - int32_t y) -{ - return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); -} - - -/* - * @brief C custom defined QSUB - */ -__STATIC_FORCEINLINE int32_t __QSUB( - int32_t x, - int32_t y) -{ - return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); -} - - -/* - * @brief C custom defined SMLAD - */ -__STATIC_FORCEINLINE uint32_t __SMLAD( - uint32_t x, - uint32_t y, - uint32_t sum) -{ - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q31_t)sum ) ) )); -} - - -/* - * @brief C custom defined SMLADX - */ -__STATIC_FORCEINLINE uint32_t __SMLADX( - uint32_t x, - uint32_t y, - uint32_t sum) -{ - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); -} - - -/* - * @brief C custom defined SMLSDX - */ -__STATIC_FORCEINLINE uint32_t __SMLSDX( - uint32_t x, - uint32_t y, - uint32_t sum) -{ - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); -} - - -/* - * @brief C custom defined SMLALD - */ -__STATIC_FORCEINLINE uint64_t __SMLALD( - uint32_t x, - uint32_t y, - uint64_t sum) -{ - /* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q63_t)sum ) ) )); -} - - -/* - * @brief C custom defined SMLALDX - */ -__STATIC_FORCEINLINE uint64_t __SMLALDX( - uint32_t x, - uint32_t y, - uint64_t sum) -{ - /* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q63_t)sum ) ) )); -} - - -/* - * @brief C custom defined SMUAD - */ -__STATIC_FORCEINLINE uint32_t __SMUAD( - uint32_t x, - uint32_t y) -{ - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); -} - - -/* - * @brief C custom defined SMUSD - */ -__STATIC_FORCEINLINE uint32_t __SMUSD( - uint32_t x, - uint32_t y) -{ - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); -} - - -/* - * @brief C custom defined SXTB16 - */ -__STATIC_FORCEINLINE uint32_t __SXTB16( - uint32_t x) -{ - return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | - ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); -} -/* - * @brief C custom defined SMMLA - */ -__STATIC_FORCEINLINE int32_t __SMMLA( - int32_t x, - int32_t y, - int32_t sum) -{ - return (sum + (int32_t) (((int64_t) x * y) >> 32)); -} -#endif -/** - * @brief Instance structure for the Q7 FIR filter. - */ -typedef struct { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ -} csi_fir_instance_q7; - -/** - * @brief Instance structure for the Q15 FIR filter. - */ -typedef struct { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ -} csi_fir_instance_q15; - -/** - * @brief Instance structure for the Q31 FIR filter. - */ -typedef struct { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ -} csi_fir_instance_q31; - -/** - * @brief Instance structure for the floating-point FIR filter. - */ -typedef struct { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ -} csi_fir_instance_f32; - -/** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ -typedef struct { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - const q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ -} csi_biquad_casd_df1_inst_q15; - -/** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ -typedef struct { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - const q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ -} csi_biquad_casd_df1_inst_q31; - -/** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ -typedef struct { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - const float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ -} csi_biquad_casd_df1_inst_f32; - -/** - * @brief Instance structure for the floating-point matrix structure. - */ -typedef struct { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ -} csi_matrix_instance_f32; - - -/** - * @brief Instance structure for the floating-point matrix structure. - */ -typedef struct { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float64_t *pData; /**< points to the data of the matrix. */ -} csi_matrix_instance_f64; - -/** - * @brief Instance structure for the Q15 matrix structure. - */ -typedef struct { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ -} csi_matrix_instance_q15; - -/** - * @brief Instance structure for the Q31 matrix structure. - */ -typedef struct { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ -} csi_matrix_instance_q31; - -/** - * @brief Instance structure for the Q15 PID Control. - */ -typedef struct { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q15_t A1; - q15_t A2; - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ -} csi_pid_instance_q15; - -/** - * @brief Instance structure for the Q31 PID Control. - */ -typedef struct { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ -} csi_pid_instance_q31; - -/** - * @brief Instance structure for the floating-point PID Control. - */ -typedef struct { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ -} csi_pid_instance_f32; - -/** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ -typedef struct { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ -} csi_linear_interp_instance_f32; - -/** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ -typedef struct { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ -} csi_bilinear_interp_instance_f32; - -/** -* @brief Instance structure for the Q31 bilinear interpolation function. -*/ -typedef struct { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ -} csi_bilinear_interp_instance_q31; - -/** -* @brief Instance structure for the Q15 bilinear interpolation function. -*/ -typedef struct { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ -} csi_bilinear_interp_instance_q15; - -/** -* @brief Instance structure for the Q15 bilinear interpolation function. -*/ -typedef struct { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ -} csi_bilinear_interp_instance_q7; - -/** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ -typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - const q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ -} csi_cfft_radix2_instance_q15; - -/** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ -typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - const q15_t *pTwiddle; /**< points to the twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ -} csi_cfft_radix4_instance_q15; - -/** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ -typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ -} csi_cfft_radix2_instance_q31; - - -/** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ -typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - const q31_t *pTwiddle; /**< points to the twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ -} csi_cfft_radix4_instance_q31; - -/** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ -typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ -} csi_cfft_radix2_instance_f32; - -/** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ -typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ -} csi_cfft_radix4_instance_f32; - -/** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ -typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ -} csi_cfft_instance_q15; - -/** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ -typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ -} csi_cfft_instance_q31; - - -/** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ -typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ -} csi_cfft_instance_f32; - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - q31_t *pTwiddleAReal; /**< points to the A real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the B real twiddle factor table. */ - const csi_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } csi_rfft_fast_instance_q31; - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - q15_t *pTwiddleAReal; /**< points to the A real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the B real twiddle factor table. */ - const csi_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } csi_rfft_fast_instance_q15; - -/** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ -typedef struct { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ -#if (!defined __riscv_xthead) && (defined __riscv) - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ -#endif - const csi_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ -} csi_rfft_instance_q15; - - -/** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ -typedef struct { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ -#if (!defined __riscv_xthead) && (defined __riscv) - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ -#endif - const csi_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ -} csi_rfft_instance_q31; - - -/** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ -typedef struct { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - csi_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ -} csi_rfft_instance_f32; - -/** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ -typedef struct { - csi_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - const float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ -} csi_rfft_fast_instance_f32 ; - -/** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ -typedef struct { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - const float32_t *pTwiddle; /**< points to the twiddle factor table. */ - const float32_t *pCosFactor; /**< points to the cosFactor table. */ - csi_rfft_fast_instance_f32 *pRfft; /**< points to the real FFT instance. */ - csi_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ -} csi_dct4_instance_f32; - - -/** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ -typedef struct { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - const q31_t *pTwiddle; /**< points to the twiddle factor table. */ - const q31_t *pCosFactor; /**< points to the cosFactor table. */ - csi_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - csi_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ -} csi_dct4_instance_q31; - - -/** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ -typedef struct { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - const q15_t *pTwiddle; /**< points to the twiddle factor table. */ - const q15_t *pCosFactor; /**< points to the cosFactor table. */ - csi_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - csi_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ -} csi_dct4_instance_q15; - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - csi_rfft_fast_instance_q15 *pRfft; /**< points to the real FFT instance. */ - csi_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } csi_dct4_fast_instance_q15; - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - csi_rfft_fast_instance_q31 *pRfft; /**< points to the real FFT instance. */ - csi_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } csi_dct4_fast_instance_q31; - - csi_status csi_dct4_init_q31( - csi_dct4_instance_q31 * S, - csi_rfft_instance_q31 * S_RFFT, - csi_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - void csi_dct4_q31( - const csi_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - void csi_dct4_fast_q31( - const csi_dct4_fast_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - -/** - * @brief Instance structure for the Q15 FIR decimator. - */ -typedef struct { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ -} csi_fir_decimate_instance_q15; - -/** - * @brief Instance structure for the Q31 FIR decimator. - */ -typedef struct { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ -} csi_fir_decimate_instance_q31; - -/** - @brief Instance structure for floating-point FIR decimator. - */ -typedef struct { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ -} csi_fir_decimate_instance_f32; - -/** - * @brief Instance structure for the Q15 FIR interpolator. - */ -typedef struct { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ -} csi_fir_interpolate_instance_q15; - -/** - * @brief Instance structure for the Q31 FIR interpolator. - */ -typedef struct { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ -} csi_fir_interpolate_instance_q31; - -/** - * @brief Instance structure for the floating-point FIR interpolator. - */ -typedef struct { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ -} csi_fir_interpolate_instance_f32; - - -/** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ -typedef struct { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - const q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ -} csi_biquad_cas_df1_32x64_ins_q31; - -/** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ -typedef struct { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ -} csi_biquad_cascade_df2T_instance_f32; - -/** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ -typedef struct { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ -} csi_biquad_cascade_stereo_df2T_instance_f32; - -/** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ -typedef struct { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ -} csi_biquad_cascade_df2T_instance_f64; - -/** - * @brief Instance structure for the Q15 FIR lattice filter. - */ -typedef struct { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ -} csi_fir_lattice_instance_q15; - -/** - * @brief Instance structure for the Q31 FIR lattice filter. - */ -typedef struct { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ -} csi_fir_lattice_instance_q31; - -/** - * @brief Instance structure for the floating-point FIR lattice filter. - */ -typedef struct { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ -} csi_fir_lattice_instance_f32; - - -/** - * @brief Instance structure for the Q15 IIR lattice filter. - */ -typedef struct { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ -} csi_iir_lattice_instance_q15; - -/** - * @brief Instance structure for the Q31 IIR lattice filter. - */ -typedef struct { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ -} csi_iir_lattice_instance_q31; - -/** - * @brief Instance structure for the floating-point IIR lattice filter. - */ -typedef struct { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ -} csi_iir_lattice_instance_f32; - - -/** - * @brief Instance structure for the floating-point LMS filter. - */ -typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ -} csi_lms_instance_f32; - - -/** - * @brief Instance structure for the Q15 LMS filter. - */ -typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ -} csi_lms_instance_q15; - - -/** - * @brief Instance structure for the Q31 LMS filter. - */ -typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ -} csi_lms_instance_q31; - - -/** - * @brief Instance structure for the floating-point normalized LMS filter. - */ -typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ -} csi_lms_norm_instance_f32; - -/** - * @brief Instance structure for the Q31 normalized LMS filter. - */ -typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - const q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ -} csi_lms_norm_instance_q31; - - -/** - * @brief Instance structure for the Q15 normalized LMS filter. - */ -typedef struct { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - const q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ -} csi_lms_norm_instance_q15; - -/** - * @brief Instance structure for the floating-point sparse FIR filter. - */ -typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ -} csi_fir_sparse_instance_f32; - -/** - * @brief Instance structure for the Q31 sparse FIR filter. - */ -typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ -} csi_fir_sparse_instance_q31; - -/** - * @brief Instance structure for the Q15 sparse FIR filter. - */ -typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ -} csi_fir_sparse_instance_q15; - -/** - * @brief Instance structure for the Q7 sparse FIR filter. - */ -typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ -} csi_fir_sparse_instance_q7; - - -/** -* @brief Struct for specifying SVM Kernel -* -*/ -typedef enum { - CSI_ML_KERNEL_LINEAR = 0, - /**< Linear kernel */ - CSI_ML_KERNEL_POLYNOMIAL = 1, - /**< Polynomial kernel */ - CSI_ML_KERNEL_RBF = 2, - /**< Radial Basis Function kernel */ - CSI_ML_KERNEL_SIGMOID = 3 - /**< Sigmoid kernel */ -} csi_ml_kernel_type; - - - -/** - * @brief Instance structure for linear SVM prediction function. - */ -typedef struct { - uint32_t nbOfSupportVectors; /**< Number of support vectors */ - uint32_t vectorDimension; /**< Dimension of vector space */ - float32_t intercept; /**< Intercept */ - const float32_t *dualCoefficients; /**< Dual coefficients */ - const float32_t *supportVectors; /**< Support vectors */ - const int32_t *classes; /**< The two SVM classes */ -} csi_svm_linear_instance_f32; - - -/** - * @brief Instance structure for polynomial SVM prediction function. - */ -typedef struct { - uint32_t nbOfSupportVectors; /**< Number of support vectors */ - uint32_t vectorDimension; /**< Dimension of vector space */ - float32_t intercept; /**< Intercept */ - const float32_t *dualCoefficients; /**< Dual coefficients */ - const float32_t *supportVectors; /**< Support vectors */ - const int32_t *classes; /**< The two SVM classes */ - int32_t degree; /**< Polynomial degree */ - float32_t coef0; /**< Polynomial constant */ - float32_t gamma; /**< Gamma factor */ -} csi_svm_polynomial_instance_f32; - -/** - * @brief Instance structure for rbf SVM prediction function. - */ -typedef struct { - uint32_t nbOfSupportVectors; /**< Number of support vectors */ - uint32_t vectorDimension; /**< Dimension of vector space */ - float32_t intercept; /**< Intercept */ - const float32_t *dualCoefficients; /**< Dual coefficients */ - const float32_t *supportVectors; /**< Support vectors */ - const int32_t *classes; /**< The two SVM classes */ - float32_t gamma; /**< Gamma factor */ -} csi_svm_rbf_instance_f32; - -/** - * @brief Instance structure for sigmoid SVM prediction function. - */ -typedef struct { - uint32_t nbOfSupportVectors; /**< Number of support vectors */ - uint32_t vectorDimension; /**< Dimension of vector space */ - float32_t intercept; /**< Intercept */ - const float32_t *dualCoefficients; /**< Dual coefficients */ - const float32_t *supportVectors; /**< Support vectors */ - const int32_t *classes; /**< The two SVM classes */ - float32_t coef0; /**< Independant constant */ - float32_t gamma; /**< Gamma factor */ -} csi_svm_sigmoid_instance_f32; - -/** - * @brief Instance structure for Naive Gaussian Bayesian estimator. - */ -typedef struct { - uint32_t vectorDimension; /**< Dimension of vector space */ - uint32_t numberOfClasses; /**< Number of different classes */ - const float32_t *theta; /**< Mean values for the Gaussians */ - const float32_t *sigma; /**< Variances for the Gaussians */ - const float32_t *classPriors; /**< Class prior probabilities */ - float32_t epsilon; /**< Additive value to variances */ -} csi_gaussian_naive_bayes_instance_f32; - -#ifdef CSI_SIMD -/* SMMLAR */ -__ALWAYS_STATIC_INLINE int32_t multAcc_32x32_keep32_R(int32_t a, int32_t x, int32_t y) -{ - __ASM volatile("mula.s32.rhs %0, %1, %2\n\t" - :"=r" (a), "=r" (x), "=r" (y) : "0" (a), "1" (x), "2" (y)); - return a; -} - -/* SMMLSR */ -__ALWAYS_STATIC_INLINE int32_t multSub_32x32_keep32_R(int32_t a, int32_t x, int32_t y) -{ - __ASM volatile("muls.s32.rhs %0, %1, %2\n\t" - :"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y)); - return a; -} - -/* SMMULR */ -__ALWAYS_STATIC_INLINE int32_t mult_32x32_keep32_R(int32_t x, int32_t y) -{ - int32_t a; - __ASM volatile("mul.s32.rh %0, %1, %2\n\t" - :"=r" (a), "=r" (x), "=r" (y): "1" (x), "2" (y)); - return a; -} - -/* SMMLA */ -__ALWAYS_STATIC_INLINE int32_t multAcc_32x32_keep32(int32_t a, int32_t x, int32_t y) -{ - __ASM volatile("mula.s32.hs %0, %1, %2\n\t" - :"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y)); - return a; -} - -/* SMMLS */ -__ALWAYS_STATIC_INLINE int32_t multSub_32x32_keep32(int32_t a, int32_t x, int32_t y) -{ - __ASM volatile("muls.s32.hs %0, %1, %2\n\t" - :"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y)); - return a; -} - -/* SMMUL */ -__ALWAYS_STATIC_INLINE int32_t mult_32x32_keep32(int32_t x, int32_t y) -{ - int32_t a; - __ASM volatile("mul.s32.h %0, %1, %2\n\t" - :"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y)); - return a; -} - -__ALWAYS_STATIC_INLINE int32_t multAcc_16x16_keep32(int32_t a, int16_t x, int16_t y) -{ - __ASM volatile("mulall.s16 %0, %1, %2\n\t" - :"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y)); - return a; -} - -__ALWAYS_STATIC_INLINE int64_t multAcc_16x16_keep64(int64_t a, int16_t x, int16_t y) -{ - __ASM volatile("mulall.s16.e %0, %1, %2\n\t" - :"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y)); - return a; -} - -__ALWAYS_STATIC_INLINE int64_t mult_32x32_keep64(int32_t x, int32_t y) -{ - int64_t a; - __ASM volatile("mul.s32 %0, %1, %2\n\t" - :"=r" (a), "=r" (x), "=r" (y): "1" (x), "2" (y)); - return a; -} - -__ALWAYS_STATIC_INLINE int64_t multAcc_32x32_keep64(int64_t a, int32_t x, int32_t y) -{ - __ASM volatile("mula.s32 %0, %1, %2\n\t" - :"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y)); - return a; -} - -__ALWAYS_STATIC_INLINE int32_t mult_32x32_dext_31(int32_t x, int32_t y) -{ - int64_t tmp1; - int32_t tmp2; - __ASM volatile("mul.s32 %0, %1, %2\n\t" - "dexti %3, %0, %R0, 31" - :"=r" (tmp1), "=r" (x), "=r" (y), "=r" (tmp2): "1" (x), "2" (y)); - return tmp2; -} - -__ALWAYS_STATIC_INLINE int32_t mult_32x32_dext_30(int32_t x, int32_t y) -{ - int64_t tmp1; - int32_t tmp2; - __ASM volatile("mul.s32 %0, %1, %2\n\t" - "dexti %3, %0, %R0, 30" - :"=r" (tmp1), "=r" (x), "=r" (y), "=r" (tmp2): "1" (x), "2" (y)); - return tmp2; -} - -__ALWAYS_STATIC_INLINE int32_t mult_32x32_dext_4(int32_t x, int32_t y) -{ - int64_t tmp1; - int32_t tmp2; - __ASM volatile("mul.s32 %0, %1, %2\n\t" - "dexti %3, %0, %R0, 4" - :"=r" (tmp1), "=r" (x), "=r" (y), "=r" (tmp2): "1" (x), "2" (y)); - return tmp2; -} - -__ALWAYS_STATIC_INLINE int32_t mult_32x32_dext_33(int32_t x, int32_t y) -{ - int64_t tmp1; - int32_t tmp2; - __ASM volatile("mul.s32 %0, %1, %2\n\t" - "asri %3, %R0, 1" - :"=r" (tmp1), "=r" (x), "=r" (y), "=r" (tmp2): "1" (x), "2" (y)); - return tmp2; -} - -__ALWAYS_STATIC_INLINE int32_t dext_31(int64_t x) -{ - int32_t tmp1; - __ASM volatile( - "dexti %0, %1, %R1, 31" - :"=r" (tmp1), "=r" (x) : "1" (x)); - return tmp1; -} - -__ALWAYS_STATIC_INLINE int32_t mult_l16xl16_keep32(int32_t x, int32_t y) -{ - int32_t a; - __ASM volatile("mulll.s16 %0, %1, %2\n\t" - :"=r" (a), "=r" (x), "=r" (y): "1" (x), "2" (y)); - return a; -} - -__ALWAYS_STATIC_INLINE int32_t mult_h16xl16_keep32(int32_t x, int32_t y) -{ - int32_t a; - __ASM volatile("mulhl.s16 %0, %1, %2\n\t" - :"=r" (a), "=r" (x), "=r" (y): "1" (x), "2" (y)); - return a; -} - -__ALWAYS_STATIC_INLINE int32_t mult_h16xh16_keep32(int32_t x, int32_t y) -{ - int32_t a; - __ASM volatile("mulhh.s16 %0, %1, %2\n\t" - :"=r" (a), "=r" (x), "=r" (y): "1" (x), "2" (y)); - return a; -} - -#else - -/* SMMLAR */ -#define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMLSR */ -#define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMULR */ -#define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) - -/* SMMLA */ -#define multAcc_32x32_keep32(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - -/* SMMLS */ -#define multSub_32x32_keep32(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -/* SMMUL */ -#define mult_32x32_keep32(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) -#endif -#ifdef __cplusplus -} -#endif - - -#endif /* _CSI_MATH_H */ - -/** - * - * End of file. - */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csi_math.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csi_math.h deleted file mode 100644 index 24eb063a..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csi_math.h +++ /dev/null @@ -1,5739 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file csi_math.h - * @brief Some common define - * @version V1.0 - * @date Feb. 2020 - ******************************************************************************/ - - -#ifndef _CSI_MATH_H -#define _CSI_MATH_H - -#ifdef __cplusplus -extern "C" -{ -#endif - - -#include -#include -#include -#include -#include -#include "csi_instance.h" - - -/** - * @brief Processing function for the Q7 FIR filter. - * @param[in] S points to an instance of the Q7 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void csi_fir_q7( - const csi_fir_instance_q7 * S, - const q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - -/** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - */ -void csi_fir_init_q7( - csi_fir_instance_q7 * S, - uint16_t numTaps, - const q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - -/** - * @brief Processing function for the Q15 FIR filter. - * @param[in] S points to an instance of the Q15 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void csi_fir_q15( - const csi_fir_instance_q15 * S, - const q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - -/** - * @brief Processing function for the fast Q15 FIR filter (fast version). - * @param[in] S points to an instance of the Q15 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void csi_fir_fast_q15( - const csi_fir_instance_q15 * S, - const q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - -/** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns either - * CSI_MATH_SUCCESS if initialization was successful or - * CSI_MATH_ARGUMENT_ERROR if numTaps is not a supported value. - */ -csi_status csi_fir_init_q15( - csi_fir_instance_q15 * S, - uint16_t numTaps, - const q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - -/** - * @brief Processing function for the Q31 FIR filter. - * @param[in] S points to an instance of the Q31 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void csi_fir_q31( - const csi_fir_instance_q31 * S, - const q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Processing function for the fast Q31 FIR filter (fast version). - * @param[in] S points to an instance of the Q31 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void csi_fir_fast_q31( - const csi_fir_instance_q31 * S, - const q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ -void csi_fir_init_q31( - csi_fir_instance_q31 * S, - uint16_t numTaps, - const q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - -/** - * @brief Processing function for the floating-point FIR filter. - * @param[in] S points to an instance of the floating-point FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void csi_fir_f32( - const csi_fir_instance_f32 * S, - const float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - -/** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ -void csi_fir_init_f32( - csi_fir_instance_f32 * S, - uint16_t numTaps, - const float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void csi_biquad_cascade_df1_q15( - const csi_biquad_casd_df1_inst_q15 * S, - const q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - -/** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ -void csi_biquad_cascade_df1_init_q15( - csi_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - const q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - -/** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void csi_biquad_cascade_df1_fast_q15( - const csi_biquad_casd_df1_inst_q15 * S, - const q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - -/** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void csi_biquad_cascade_df1_q31( - const csi_biquad_casd_df1_inst_q31 * S, - const q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void csi_biquad_cascade_df1_fast_q31( - const csi_biquad_casd_df1_inst_q31 * S, - const q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ -void csi_biquad_cascade_df1_init_q31( - csi_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - const q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - -/** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void csi_biquad_cascade_df1_f32( - const csi_biquad_casd_df1_inst_f32 * S, - const float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - -/** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ -void csi_biquad_cascade_df1_init_f32( - csi_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - const float32_t * pCoeffs, - float32_t * pState); - -/** - * @brief Floating-point matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. - */ -csi_status csi_mat_add_f32( - const csi_matrix_instance_f32 * pSrcA, - const csi_matrix_instance_f32 * pSrcB, - csi_matrix_instance_f32 * pDst); - -/** - * @brief Q15 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. - */ -csi_status csi_mat_add_q15( - const csi_matrix_instance_q15 * pSrcA, - const csi_matrix_instance_q15 * pSrcB, - csi_matrix_instance_q15 * pDst); - -/** - * @brief Q31 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. - */ -csi_status csi_mat_add_q31( - const csi_matrix_instance_q31 * pSrcA, - const csi_matrix_instance_q31 * pSrcB, - csi_matrix_instance_q31 * pDst); - -/** - * @brief Floating-point, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. - */ -csi_status csi_mat_cmplx_mult_f32( - const csi_matrix_instance_f32 * pSrcA, - const csi_matrix_instance_f32 * pSrcB, - csi_matrix_instance_f32 * pDst); - -/** - * @brief Q15, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. - */ -csi_status csi_mat_cmplx_mult_q15( - const csi_matrix_instance_q15 * pSrcA, - const csi_matrix_instance_q15 * pSrcB, - csi_matrix_instance_q15 * pDst); - -void csi_mult_q15xq31_sht( - q15_t * pSrcA, - q31_t * pSrcB, - uint32_t shiftValue, - uint32_t blockSize); - -/** - * @brief Q31, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. - */ -csi_status csi_mat_cmplx_mult_q31( - const csi_matrix_instance_q31 * pSrcA, - const csi_matrix_instance_q31 * pSrcB, - csi_matrix_instance_q31 * pDst); - -/** - * @brief Floating-point matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either CSI_MATH_SIZE_MISMATCH - * or CSI_MATH_SUCCESS based on the outcome of size checking. - */ -csi_status csi_mat_trans_f32( - const csi_matrix_instance_f32 * pSrc, - csi_matrix_instance_f32 * pDst); - -/** - * @brief Q15 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either CSI_MATH_SIZE_MISMATCH - * or CSI_MATH_SUCCESS based on the outcome of size checking. - */ -csi_status csi_mat_trans_q15( - const csi_matrix_instance_q15 * pSrc, - csi_matrix_instance_q15 * pDst); - -/** - * @brief Q31 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either CSI_MATH_SIZE_MISMATCH - * or CSI_MATH_SUCCESS based on the outcome of size checking. - */ -csi_status csi_mat_trans_q31( - const csi_matrix_instance_q31 * pSrc, - csi_matrix_instance_q31 * pDst); - -/** - * @brief Floating-point matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. - */ -csi_status csi_mat_mult_f32( - const csi_matrix_instance_f32 * pSrcA, - const csi_matrix_instance_f32 * pSrcB, - csi_matrix_instance_f32 * pDst); - -/** - * @brief Q15 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. - */ -csi_status csi_mat_mult_q15( - const csi_matrix_instance_q15 * pSrcA, - const csi_matrix_instance_q15 * pSrcB, - csi_matrix_instance_q15 * pDst); - - csi_status csi_mat_mult_trans_q15( - const csi_matrix_instance_q15 * pSrcA, - const csi_matrix_instance_q15 * pSrcB, - csi_matrix_instance_q15 * pDst); - -/** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. - */ -csi_status csi_mat_mult_fast_q15( - const csi_matrix_instance_q15 * pSrcA, - const csi_matrix_instance_q15 * pSrcB, - csi_matrix_instance_q15 * pDst); - -/** - * @brief Q31 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. - */ -csi_status csi_mat_mult_q31( - const csi_matrix_instance_q31 * pSrcA, - const csi_matrix_instance_q31 * pSrcB, - csi_matrix_instance_q31 * pDst); - -csi_status csi_mat_mult_trans_q31( - const csi_matrix_instance_q31 * pSrcA, - const csi_matrix_instance_q31 * pSrcB, - csi_matrix_instance_q31 * pDst); - -/** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. - */ -csi_status csi_mat_mult_fast_q31( - const csi_matrix_instance_q31 * pSrcA, - const csi_matrix_instance_q31 * pSrcB, - csi_matrix_instance_q31 * pDst); - -/** - * @brief Floating-point matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. - */ -csi_status csi_mat_sub_f32( - const csi_matrix_instance_f32 * pSrcA, - const csi_matrix_instance_f32 * pSrcB, - csi_matrix_instance_f32 * pDst); - -/** - * @brief Q15 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. - */ -csi_status csi_mat_sub_q15( - const csi_matrix_instance_q15 * pSrcA, - const csi_matrix_instance_q15 * pSrcB, - csi_matrix_instance_q15 * pDst); - -/** - * @brief Q31 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. - */ -csi_status csi_mat_sub_q31( - const csi_matrix_instance_q31 * pSrcA, - const csi_matrix_instance_q31 * pSrcB, - csi_matrix_instance_q31 * pDst); - -void csi_sum_q15( - q15_t * pSrcA, - q63_t * pDst, - uint32_t blockSize); - -/** - * @brief Floating-point matrix scaling. - * @param[in] pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] pDst points to the output matrix - * @return The function returns either - * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. - */ -csi_status csi_mat_scale_f32( - const csi_matrix_instance_f32 * pSrc, - float32_t scale, - csi_matrix_instance_f32 * pDst); - -/** - * @brief Q15 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix - * @return The function returns either - * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. - */ -csi_status csi_mat_scale_q15( - const csi_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - csi_matrix_instance_q15 * pDst); - -/** - * @brief Q31 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix structure - * @return The function returns either - * CSI_MATH_SIZE_MISMATCH or CSI_MATH_SUCCESS based on the outcome of size checking. - */ -csi_status csi_mat_scale_q31( - const csi_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - csi_matrix_instance_q31 * pDst); - -/** - * @brief Q31 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ -void csi_mat_init_q31( - csi_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - -/** - * @brief Q15 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ -void csi_mat_init_q15( - csi_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - -/** - * @brief Floating-point matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ -void csi_mat_init_f32( - csi_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - - -/** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ -void csi_pid_init_f32( - csi_pid_instance_f32 * S, - int32_t resetStateFlag); - - -/** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - */ -void csi_pid_reset_f32( - csi_pid_instance_f32 * S); - - -/** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ -void csi_pid_init_q31( - csi_pid_instance_q31 * S, - int32_t resetStateFlag); - - -/** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - */ - -void csi_pid_reset_q31( - csi_pid_instance_q31 * S); - - -/** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ -void csi_pid_init_q15( - csi_pid_instance_q15 * S, - int32_t resetStateFlag); - - -/** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] S points to an instance of the q15 PID Control structure - */ -void csi_pid_reset_q15( - csi_pid_instance_q15 * S); - -/** - * @brief Q7 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void csi_mult_q7( - const q7_t * pSrcA, - const q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - -/** - * @brief Q15 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void csi_mult_q15( - const q15_t * pSrcA, - const q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - -void csi_mult_rnd_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Q31 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void csi_mult_q31( - const q31_t * pSrcA, - const q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Floating-point vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void csi_mult_f32( - const float32_t * pSrcA, - const float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - -/* Deprecated */ -csi_status csi_cfft_radix2_init_q15( - csi_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ -void csi_cfft_radix2_q15( - const csi_cfft_radix2_instance_q15 * S, - q15_t * pSrc); - - -/* Deprecated */ -csi_status csi_cfft_radix4_init_q15( - csi_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ -void csi_cfft_radix4_q15( - const csi_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - -/* Deprecated */ -csi_status csi_cfft_radix2_init_q31( - csi_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ -void csi_cfft_radix2_q31( - const csi_cfft_radix2_instance_q31 * S, - q31_t * pSrc); - - -/* Deprecated */ -void csi_cfft_radix4_q31( - const csi_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - -/* Deprecated */ -csi_status csi_cfft_radix4_init_q31( - csi_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - -/* Deprecated */ -csi_status csi_cfft_radix2_init_f32( - csi_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void csi_cfft_radix2_f32( - const csi_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag, - float32_t onebyfftLen); - - -/* Deprecated */ -csi_status csi_cfft_radix4_init_f32( - csi_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void csi_cfft_radix4_f32( - const csi_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag, - float32_t onebyfftLen); - - void csi_cfft_fast_radix4_f32( - const csi_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag, - float32_t onebyfftLen); - - -void csi_cfft_q15( - const csi_cfft_instance_q15 * S, - q15_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -void csi_cfft_fast_q15( - const csi_cfft_instance_q15 * S, - q15_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -void csi_cfft_q31( - const csi_cfft_instance_q31 * S, - q31_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -void csi_cfft_fast_q31( - const csi_cfft_instance_q31 * S, - q31_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - -void csi_cfft_f32( - const csi_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - -csi_status csi_rfft_init_q15( - csi_rfft_instance_q15 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - -void csi_rfft_q15( - const csi_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - -void csi_rfft_fast_q15( - const csi_rfft_fast_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - -csi_status csi_rfft_init_q31( - csi_rfft_instance_q31 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - -void csi_rfft_q31( - const csi_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - -void csi_rfft_fast_q31( - const csi_rfft_fast_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - -csi_status csi_rfft_init_f32( - csi_rfft_instance_f32 * S, - csi_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - -void csi_rfft_f32( - const csi_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - -csi_status csi_rfft_fast_init_f32 ( - csi_rfft_fast_instance_f32 * S, - uint16_t fftLen); - -csi_status csi_rfft_32_fast_init_f32 ( csi_rfft_fast_instance_f32 * S ); - -csi_status csi_rfft_64_fast_init_f32 ( csi_rfft_fast_instance_f32 * S ); - -csi_status csi_rfft_128_fast_init_f32 ( csi_rfft_fast_instance_f32 * S ); - -csi_status csi_rfft_256_fast_init_f32 ( csi_rfft_fast_instance_f32 * S ); - -csi_status csi_rfft_512_fast_init_f32 ( csi_rfft_fast_instance_f32 * S ); - -csi_status csi_rfft_1024_fast_init_f32 ( csi_rfft_fast_instance_f32 * S ); - -csi_status csi_rfft_2048_fast_init_f32 ( csi_rfft_fast_instance_f32 * S ); - -csi_status csi_rfft_4096_fast_init_f32 ( csi_rfft_fast_instance_f32 * S ); - - -void csi_rfft_fast_f32( - csi_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); - - -/** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return csi_status function returns CSI_MATH_SUCCESS if initialization is successful or CSI_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ -csi_status csi_dct4_init_f32( - csi_dct4_instance_f32 * S, - csi_rfft_fast_instance_f32 * S_RFFT, - csi_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - -/** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ -void csi_dct4_f32( - const csi_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - - -/** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return csi_status function returns CSI_MATH_SUCCESS if initialization is successful or CSI_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ -csi_status csi_dct4_init_q31( - csi_dct4_instance_q31 * S, - csi_rfft_instance_q31 * S_RFFT, - csi_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - -/** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] S points to an instance of the Q31 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ -void csi_dct4_q31( - const csi_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - -void csi_dct4_fast_q31( - const csi_dct4_fast_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - -/** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return csi_status function returns CSI_MATH_SUCCESS if initialization is successful or CSI_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ -csi_status csi_dct4_init_q15( - csi_dct4_instance_q15 * S, - csi_rfft_instance_q15 * S_RFFT, - csi_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - -/** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] S points to an instance of the Q15 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ -void csi_dct4_q15( - const csi_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - -void csi_dct4_fast_q15( - const csi_dct4_fast_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - -/** - * @brief Floating-point vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void csi_add_f32( - const float32_t * pSrcA, - const float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - -/** - * @brief Q7 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void csi_add_q7( - const q7_t * pSrcA, - const q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - -/** - * @brief Q15 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void csi_add_q15( - const q15_t * pSrcA, - const q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Q31 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void csi_add_q31( - const q31_t * pSrcA, - const q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Floating-point vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void csi_sub_f32( - const float32_t * pSrcA, - const float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - -/** - * @brief Q7 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void csi_sub_q7( - const q7_t * pSrcA, - const q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - -/** - * @brief Q15 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void csi_sub_q15( - const q15_t * pSrcA, - const q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Q31 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void csi_sub_q31( - const q31_t * pSrcA, - const q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void csi_scale_f32( - const float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - -/** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void csi_scale_q7( - const q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - -/** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void csi_scale_q15( - const q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void csi_scale_q31( - const q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Q7 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ -void csi_abs_q7( - const q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - -/** - * @brief Floating-point vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ -void csi_abs_f32( - const float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - -/** - * @brief Q15 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ -void csi_abs_q15( - const q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Q31 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ -void csi_abs_q31( - const q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - void csi_abs_max_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - void csi_abs_max_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Dot product of floating-point vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ -void csi_dot_prod_f32( - const float32_t * pSrcA, - const float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - -/** - * @brief Dot product of Q7 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ -void csi_dot_prod_q7( - const q7_t * pSrcA, - const q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - -/** - * @brief Dot product of Q15 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ -void csi_dot_prod_q15( - const q15_t * pSrcA, - const q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - -/** - * @brief Dot product of Q31 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ -void csi_dot_prod_q31( - const q31_t * pSrcA, - const q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - -/** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void csi_shift_q7( - const q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - -/** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void csi_shift_q15( - const q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void csi_shift_q31( - const q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void csi_offset_f32( - const float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - -/** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void csi_offset_q7( - const q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - -/** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void csi_offset_q15( - const q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void csi_offset_q31( - const q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Negates the elements of a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void csi_negate_f32( - const float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - -/** - * @brief Negates the elements of a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void csi_negate_q7( - const q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - -/** - * @brief Negates the elements of a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void csi_negate_q15( - const q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Negates the elements of a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void csi_negate_q31( - const q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Copies the elements of a floating-point vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void csi_copy_f32( - const float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - -/** - * @brief Copies the elements of a Q7 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void csi_copy_q7( - const q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - -/** - * @brief Copies the elements of a Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void csi_copy_q15( - const q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Copies the elements of a Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void csi_copy_q31( - const q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void csi_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - -/** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void csi_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - -/** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void csi_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void csi_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ -void csi_conv_f32( - const float32_t * pSrcA, - uint32_t srcALen, - const float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ -void csi_conv_opt_q15( - const q15_t * pSrcA, - uint32_t srcALen, - const q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ -void csi_conv_q15( - const q15_t * pSrcA, - uint32_t srcALen, - const q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - -/** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ -void csi_conv_fast_q15( - const q15_t * pSrcA, - uint32_t srcALen, - const q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - -/** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ -void csi_conv_fast_opt_q15( - const q15_t * pSrcA, - uint32_t srcALen, - const q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ -void csi_conv_q31( - const q31_t * pSrcA, - uint32_t srcALen, - const q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - -/** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ -void csi_conv_fast_q31( - const q31_t * pSrcA, - uint32_t srcALen, - const q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - -/** -* @brief Convolution of Q7 sequences. -* @param[in] pSrcA points to the first input sequence. -* @param[in] srcALen length of the first input sequence. -* @param[in] pSrcB points to the second input sequence. -* @param[in] srcBLen length of the second input sequence. -* @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. -* @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. -* @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). -*/ -void csi_conv_opt_q7( - const q7_t * pSrcA, - uint32_t srcALen, - const q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ -void csi_conv_q7( - const q7_t * pSrcA, - uint32_t srcALen, - const q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - -/** - * @brief Partial convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either CSI_MATH_SUCCESS if the function completed correctly or CSI_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ -csi_status csi_conv_partial_f32( - const float32_t * pSrcA, - uint32_t srcALen, - const float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - -/** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either CSI_MATH_SUCCESS if the function completed correctly or CSI_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ -csi_status csi_conv_partial_opt_q15( - const q15_t * pSrcA, - uint32_t srcALen, - const q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either CSI_MATH_SUCCESS if the function completed correctly or CSI_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ -csi_status csi_conv_partial_q15( - const q15_t * pSrcA, - uint32_t srcALen, - const q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - -/** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either CSI_MATH_SUCCESS if the function completed correctly or CSI_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ -csi_status csi_conv_partial_fast_q15( - const q15_t * pSrcA, - uint32_t srcALen, - const q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - -/** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either CSI_MATH_SUCCESS if the function completed correctly or CSI_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ -csi_status csi_conv_partial_fast_opt_q15( - const q15_t * pSrcA, - uint32_t srcALen, - const q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either CSI_MATH_SUCCESS if the function completed correctly or CSI_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ -csi_status csi_conv_partial_q31( - const q31_t * pSrcA, - uint32_t srcALen, - const q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - -/** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either CSI_MATH_SUCCESS if the function completed correctly or CSI_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ -csi_status csi_conv_partial_fast_q31( - const q31_t * pSrcA, - uint32_t srcALen, - const q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - -/** - * @brief Partial convolution of Q7 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either CSI_MATH_SUCCESS if the function completed correctly or CSI_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ -csi_status csi_conv_partial_opt_q7( - const q7_t * pSrcA, - uint32_t srcALen, - const q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either CSI_MATH_SUCCESS if the function completed correctly or CSI_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ -csi_status csi_conv_partial_q7( - const q7_t * pSrcA, - uint32_t srcALen, - const q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - -/** - @brief Processing function for floating-point FIR decimator. - @param[in] S points to an instance of the floating-point FIR decimator structure - @param[in] pSrc points to the block of input data - @param[out] pDst points to the block of output data - @param[in] blockSize number of samples to process - */ -void csi_fir_decimate_f32( - const csi_fir_decimate_instance_f32 * S, - const float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - -/** - @brief Initialization function for the floating-point FIR decimator. - @param[in,out] S points to an instance of the floating-point FIR decimator structure - @param[in] numTaps number of coefficients in the filter - @param[in] M decimation factor - @param[in] pCoeffs points to the filter coefficients - @param[in] pState points to the state buffer - @param[in] blockSize number of input samples to process per call - @return execution status - - \ref CSI_MATH_SUCCESS : Operation successful - - \ref CSI_MATH_LENGTH_ERROR : blockSize is not a multiple of M - */ -csi_status csi_fir_decimate_init_f32( - csi_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - const float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ -void csi_fir_decimate_q15( - const csi_fir_decimate_instance_q15 * S, - const q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ -void csi_fir_decimate_fast_q15( - const csi_fir_decimate_instance_q15 * S, - const q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns CSI_MATH_SUCCESS if initialization is successful or CSI_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ -csi_status csi_fir_decimate_init_q15( - csi_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - const q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ -void csi_fir_decimate_q31( - const csi_fir_decimate_instance_q31 * S, - const q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ -void csi_fir_decimate_fast_q31( - const csi_fir_decimate_instance_q31 * S, - const q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns CSI_MATH_SUCCESS if initialization is successful or CSI_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ -csi_status csi_fir_decimate_init_q31( - csi_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - const q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - -/** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ -void csi_fir_interpolate_q15( - const csi_fir_interpolate_instance_q15 * S, - const q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns CSI_MATH_SUCCESS if initialization is successful or CSI_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ -csi_status csi_fir_interpolate_init_q15( - csi_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - const q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ -void csi_fir_interpolate_q31( - const csi_fir_interpolate_instance_q31 * S, - const q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns CSI_MATH_SUCCESS if initialization is successful or CSI_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ -csi_status csi_fir_interpolate_init_q31( - csi_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - const q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - -/** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ -void csi_fir_interpolate_f32( - const csi_fir_interpolate_instance_f32 * S, - const float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns CSI_MATH_SUCCESS if initialization is successful or CSI_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ -csi_status csi_fir_interpolate_init_f32( - csi_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - const float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - -/** - * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ -void csi_biquad_cas_df1_32x64_q31( - const csi_biquad_cas_df1_32x64_ins_q31 * S, - const q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - */ -void csi_biquad_cas_df1_32x64_init_q31( - csi_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - const q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - -/** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ -void csi_biquad_cascade_df2T_f32( - const csi_biquad_cascade_df2T_instance_f32 * S, - const float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - -/** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ -void csi_biquad_cascade_stereo_df2T_f32( - const csi_biquad_cascade_stereo_df2T_instance_f32 * S, - const float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - -/** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ -void csi_biquad_cascade_df2T_f64( - const csi_biquad_cascade_df2T_instance_f64 * S, - float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); - - -#if defined(CSI_MATH_NEON) -void csi_biquad_cascade_df2T_compute_coefs_f32( - csi_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs); -#endif -/** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ -void csi_biquad_cascade_df2T_init_f32( - csi_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - const float32_t * pCoeffs, - float32_t * pState); - - -/** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ -void csi_biquad_cascade_stereo_df2T_init_f32( - csi_biquad_cascade_stereo_df2T_instance_f32 * S, - uint8_t numStages, - const float32_t * pCoeffs, - float32_t * pState); - - -/** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ -void csi_biquad_cascade_df2T_init_f64( - csi_biquad_cascade_df2T_instance_f64 * S, - uint8_t numStages, - float64_t * pCoeffs, - float64_t * pState); - - -/** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ -void csi_fir_lattice_init_q15( - csi_fir_lattice_instance_q15 * S, - uint16_t numStages, - const q15_t * pCoeffs, - q15_t * pState); - - -/** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void csi_fir_lattice_q15( - const csi_fir_lattice_instance_q15 * S, - const q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ -void csi_fir_lattice_init_q31( - csi_fir_lattice_instance_q31 * S, - uint16_t numStages, - const q31_t * pCoeffs, - q31_t * pState); - - -/** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ -void csi_fir_lattice_q31( - const csi_fir_lattice_instance_q31 * S, - const q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ -void csi_fir_lattice_init_f32( - csi_fir_lattice_instance_f32 * S, - uint16_t numStages, - const float32_t * pCoeffs, - float32_t * pState); - - -/** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ -void csi_fir_lattice_f32( - const csi_fir_lattice_instance_f32 * S, - const float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - -/** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void csi_iir_lattice_f32( - const csi_iir_lattice_instance_f32 * S, - const float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - */ -void csi_iir_lattice_init_f32( - csi_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void csi_iir_lattice_q31( - const csi_iir_lattice_instance_q31 * S, - const q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - */ -void csi_iir_lattice_init_q31( - csi_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the Q15 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void csi_iir_lattice_q15( - const csi_iir_lattice_instance_q15 * S, - const q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - */ -void csi_iir_lattice_init_q15( - csi_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - - -/** - * @brief Processing function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ -void csi_lms_f32( - const csi_lms_instance_f32 * S, - const float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - -/** - * @brief Initialization function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ -void csi_lms_init_f32( - csi_lms_instance_f32 * S, - uint16_t numTaps, - const float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ -void csi_lms_init_q15( - csi_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - -/** - * @brief Processing function for Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ -void csi_lms_q15( - const csi_lms_instance_q15 * S, - const q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - -/** - * @brief Processing function for Q31 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ -void csi_lms_q31( - const csi_lms_instance_q31 * S, - const q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - -/** - * @brief Initialization function for Q31 LMS filter. - * @param[in] S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ -void csi_lms_init_q31( - csi_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - -/** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ -void csi_lms_norm_f32( - csi_lms_norm_instance_f32 * S, - const float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - -/** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ -void csi_lms_norm_init_f32( - csi_lms_norm_instance_f32 * S, - uint16_t numTaps, - const float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - -/** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ -void csi_lms_norm_q31( - csi_lms_norm_instance_q31 * S, - const q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - -/** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ -void csi_lms_norm_init_q31( - csi_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - -/** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ -void csi_lms_norm_q15( - csi_lms_norm_instance_q15 * S, - const q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - -/** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ -void csi_lms_norm_init_q15( - csi_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - -/** - * @brief Correlation of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ -void csi_correlate_f32( - const float32_t * pSrcA, - uint32_t srcALen, - const float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - -/** - @brief Correlation of Q15 sequences - @param[in] pSrcA points to the first input sequence - @param[in] srcALen length of the first input sequence - @param[in] pSrcB points to the second input sequence - @param[in] srcBLen length of the second input sequence - @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. -*/ -void csi_correlate_opt_q15( - const q15_t * pSrcA, - uint32_t srcALen, - const q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - -/** - @brief Correlation of Q15 sequences. - @param[in] pSrcA points to the first input sequence - @param[in] srcALen length of the first input sequence - @param[in] pSrcB points to the second input sequence - @param[in] srcBLen length of the second input sequence - @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ -void csi_correlate_q15( - const q15_t * pSrcA, - uint32_t srcALen, - const q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - -/** - @brief Correlation of Q15 sequences (fast version). - @param[in] pSrcA points to the first input sequence - @param[in] srcALen length of the first input sequence - @param[in] pSrcB points to the second input sequence - @param[in] srcBLen length of the second input sequence - @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. - @return none - */ -void csi_correlate_fast_q15( - const q15_t * pSrcA, - uint32_t srcALen, - const q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - -/** - @brief Correlation of Q15 sequences (fast version). - @param[in] pSrcA points to the first input sequence. - @param[in] srcALen length of the first input sequence. - @param[in] pSrcB points to the second input sequence. - @param[in] srcBLen length of the second input sequence. - @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ -void csi_correlate_fast_opt_q15( - const q15_t * pSrcA, - uint32_t srcALen, - const q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - -/** - * @brief Correlation of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ -void csi_correlate_q31( - const q31_t * pSrcA, - uint32_t srcALen, - const q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - -/** - @brief Correlation of Q31 sequences (fast version). - @param[in] pSrcA points to the first input sequence - @param[in] srcALen length of the first input sequence - @param[in] pSrcB points to the second input sequence - @param[in] srcBLen length of the second input sequence - @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ -void csi_correlate_fast_q31( - const q31_t * pSrcA, - uint32_t srcALen, - const q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - -/** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ -void csi_correlate_opt_q7( - const q7_t * pSrcA, - uint32_t srcALen, - const q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ -void csi_correlate_q7( - const q7_t * pSrcA, - uint32_t srcALen, - const q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - -/** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] S points to an instance of the floating-point sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ -void csi_fir_sparse_f32( - csi_fir_sparse_instance_f32 * S, - const float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ -void csi_fir_sparse_init_f32( - csi_fir_sparse_instance_f32 * S, - uint16_t numTaps, - const float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] S points to an instance of the Q31 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ -void csi_fir_sparse_q31( - csi_fir_sparse_instance_q31 * S, - const q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ -void csi_fir_sparse_init_q31( - csi_fir_sparse_instance_q31 * S, - uint16_t numTaps, - const q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] S points to an instance of the Q15 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ -void csi_fir_sparse_q15( - csi_fir_sparse_instance_q15 * S, - const q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ -void csi_fir_sparse_init_q15( - csi_fir_sparse_instance_q15 * S, - uint16_t numTaps, - const q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] S points to an instance of the Q7 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ -void csi_fir_sparse_q7( - csi_fir_sparse_instance_q7 * S, - const q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ -void csi_fir_sparse_init_q7( - csi_fir_sparse_instance_q7 * S, - uint16_t numTaps, - const q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - -/** - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cos output. - */ -void csi_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCosVal); - - -/** - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cosine output. - */ -void csi_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - - -/** - * @brief Floating-point complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ -void csi_cmplx_conj_f32( - const float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - -/** - * @brief Q31 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ -void csi_cmplx_conj_q31( - const q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - -/** - * @brief Q15 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ -void csi_cmplx_conj_q15( - const q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - -/** - * @brief Floating-point complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ -void csi_cmplx_mag_squared_f32( - const float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - -/** - * @brief Q31 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ -void csi_cmplx_mag_squared_q31( - const q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - -void csi_cmplx_mag_squared_q31_basic( - q31_t * pSrc, - q63_t * pDst, - uint32_t numSamples); - - -/** - * @brief Q15 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ -void csi_cmplx_mag_squared_q15( - const q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - -/** - * @ingroup groupController - */ - -/** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
- *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
- *    A0 = Kp + Ki + Kd
- *    A1 = (-Kp ) - (2 * Kd )
- *    A2 = Kd
- *
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - -/** - * @addtogroup PID - * @{ - */ - -/** - * @brief Process function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return processed output sample. - */ -__STATIC_FORCEINLINE float32_t csi_pid_f32( - csi_pid_instance_f32 * S, - float32_t in) -{ - float32_t out; - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - /* return to application */ - return (out); -} - -/** - @brief Process function for the Q31 PID Control. - @param[in,out] S points to an instance of the Q31 PID Control structure - @param[in] in input sample to process - @return processed output sample. - - \par Scaling and Overflow Behavior - The function is implemented using an internal 64-bit accumulator. - The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - Thus, if the accumulator result overflows it wraps around rather than clip. - In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ -__STATIC_FORCEINLINE q31_t csi_pid_q31( - csi_pid_instance_q31 * S, - q31_t in) -{ - q63_t acc; - q31_t out; - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31U); - /* out += y[n-1] */ - out += S->state[2]; - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - /* return to application */ - return (out); -} - - -/** - @brief Process function for the Q15 PID Control. - @param[in,out] S points to an instance of the Q15 PID Control structure - @param[in] in input sample to process - @return processed output sample. - - \par Scaling and Overflow Behavior - The function is implemented using a 64-bit internal accumulator. - Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ -__STATIC_FORCEINLINE q15_t csi_pid_q15( - csi_pid_instance_q15 * S, - q15_t in) -{ - q63_t acc; - q15_t out; -#if defined (CSI_MATH_DSP) - /* Implementation of PID controller */ - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)read_q15x2 (S->state), (uint64_t)acc); -#else - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; -#endif - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - /* saturate the output */ - out = (q15_t) (__SSAT((q31_t)(acc >> 15), 16)); - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - /* return to application */ - return (out); -} - -/** - * @} end of PID group - */ - - -/** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns CSI_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status CSI_MATH_SINGULAR. - */ -csi_status csi_mat_inverse_f32( - const csi_matrix_instance_f32 * src, - csi_matrix_instance_f32 * dst); - - -/** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns CSI_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status CSI_MATH_SINGULAR. - */ -csi_status csi_mat_inverse_f64( - const csi_matrix_instance_f64 * src, - csi_matrix_instance_f64 * dst); - - - -/** - * @ingroup groupController - */ - -/** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - -/** - * @addtogroup clarke - * @{ - */ - -/** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @return none - */ -__STATIC_FORCEINLINE void csi_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) -{ - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); -} - - -/** - @brief Clarke transform for Q31 version - @param[in] Ia input three-phase coordinate a - @param[in] Ib input three-phase coordinate b - @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - @param[out] pIbeta points to output two-phase orthogonal vector axis beta - @return none - - \par Scaling and Overflow Behavior - The function is implemented using an internal 32-bit accumulator. - The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - There is saturation on the addition, hence there is no risk of overflow. - */ -__STATIC_FORCEINLINE void csi_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) -{ - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); -} - -/** - * @} end of clarke group - */ - - -/** - * @ingroup groupController - */ - -/** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - -/** - * @addtogroup inv_clarke - * @{ - */ - -/** -* @brief Floating-point Inverse Clarke transform -* @param[in] Ialpha input two-phase orthogonal vector axis alpha -* @param[in] Ibeta input two-phase orthogonal vector axis beta -* @param[out] pIa points to output three-phase coordinate a -* @param[out] pIb points to output three-phase coordinate b -* @return none -*/ -__STATIC_FORCEINLINE void csi_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) -{ - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; -} - - -/** - @brief Inverse Clarke transform for Q31 version - @param[in] Ialpha input two-phase orthogonal vector axis alpha - @param[in] Ibeta input two-phase orthogonal vector axis beta - @param[out] pIa points to output three-phase coordinate a - @param[out] pIb points to output three-phase coordinate b - @return none - - \par Scaling and Overflow Behavior - The function is implemented using an internal 32-bit accumulator. - The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - There is saturation on the subtraction, hence there is no risk of overflow. - */ -__STATIC_FORCEINLINE void csi_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) -{ - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); -} - -/** - * @} end of inv_clarke group - */ - - - -/** - * @ingroup groupController - */ - -/** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - -/** - * @addtogroup park - * @{ - */ - -/** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none - * - * The function implements the forward Park transform. - * - */ -__STATIC_FORCEINLINE void csi_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) -{ - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; -} - - -/** - @brief Park transform for Q31 version - @param[in] Ialpha input two-phase vector coordinate alpha - @param[in] Ibeta input two-phase vector coordinate beta - @param[out] pId points to output rotor reference frame d - @param[out] pIq points to output rotor reference frame q - @param[in] sinVal sine value of rotation angle theta - @param[in] cosVal cosine value of rotation angle theta - @return none - - \par Scaling and Overflow Behavior - The function is implemented using an internal 32-bit accumulator. - The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ -__STATIC_FORCEINLINE void csi_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) -{ -#ifdef CSI_SIMD - asm volatile( - "rmul.s32.h t0, %0, %3\n\t" - "rmul.s32.h t1, %1, %2\n\t" - "add.s32.s t0, t0, t1\n\t" - "st.w t0, (%4, 0x0)\n\t" - "rmul.s32.h t0, %0, %2\n\t" - "rmul.s32.h t1, %1, %3\n\t" - "sub.s32.s t1, t1, t0\n\t" - "st.w t1, (%5, 0x0)\n\t" - ::"r"(Ialpha),"r"(Ibeta),"r"(sinVal),"r"(cosVal),"r"(pId),"r"(pIq) - :"t0","t1", "memory"); -#else - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); -#endif -} - -/** - * @} end of park group - */ - - -/** - * @ingroup groupController - */ - -/** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - -/** - * @addtogroup inv_park - * @{ - */ - -/** -* @brief Floating-point Inverse Park transform -* @param[in] Id input coordinate of rotor reference frame d -* @param[in] Iq input coordinate of rotor reference frame q -* @param[out] pIalpha points to output two-phase orthogonal vector axis alpha -* @param[out] pIbeta points to output two-phase orthogonal vector axis beta -* @param[in] sinVal sine value of rotation angle theta -* @param[in] cosVal cosine value of rotation angle theta -* @return none -*/ -__STATIC_FORCEINLINE void csi_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) -{ - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; -} - - -/** - @brief Inverse Park transform for Q31 version - @param[in] Id input coordinate of rotor reference frame d - @param[in] Iq input coordinate of rotor reference frame q - @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - @param[out] pIbeta points to output two-phase orthogonal vector axis beta - @param[in] sinVal sine value of rotation angle theta - @param[in] cosVal cosine value of rotation angle theta - @return none - - @par Scaling and Overflow Behavior - The function is implemented using an internal 32-bit accumulator. - The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - There is saturation on the addition, hence there is no risk of overflow. - */ -__STATIC_FORCEINLINE void csi_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) -{ -#ifdef CSI_SIMD - asm volatile( - "rmul.s32.h t0, %0, %3\n\t" - "rmul.s32.h t1, %1, %2\n\t" - "sub.s32.s t0, t0, t1\n\t" - "st.w t0, (%4, 0x0)\n\t" - "rmul.s32.h t0, %0, %2\n\t" - "rmul.s32.h t1, %1, %3\n\t" - "add.s32.s t0, t0, t1\n\t" - "st.w t0, (%5, 0x0)\n\t" - ::"r"(Id),"r"(Iq),"r"(sinVal),"r"(cosVal),"r"(pIalpha),"r"(pIbeta) - :"t0","t1", "memory"); -#else - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); -#endif -} - -/** - * @} end of Inverse park group - */ - - -/** - * @ingroup groupInterpolation - */ - -/** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
- *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
- *       where x0, x1 are nearest values of input x
- *             y0, y1 are nearest values to output y
- *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - -/** - * @addtogroup LinearInterpolate - * @{ - */ - -/** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ -__STATIC_FORCEINLINE float32_t csi_linear_interp_f32( - csi_linear_interp_instance_f32 * S, - float32_t x) -{ - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - - if (i < 0) { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - - } else if ((uint32_t)i >= (S->nValues - 1)) { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - - } else { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - } - - /* returns output value */ - return (y); -} - - -/** -* -* @brief Process function for the Q31 Linear Interpolation Function. -* @param[in] pYData pointer to Q31 Linear Interpolation table -* @param[in] x input sample to process -* @param[in] nValues number of table values -* @return y processed output sample. -* -* \par -* Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. -* This function can support maximum of table size 2^12. -* -*/ -__STATIC_FORCEINLINE q31_t csi_linear_interp_q31( - q31_t * pYData, - q31_t x, - uint32_t nValues) -{ - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (q31_t)0xFFF00000) >> 20); - - if (index >= (int32_t)(nValues - 1)) { - return (pYData[nValues - 1]); - - } else if (index < 0) { - return (pYData[0]); - - } else { - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - /* Convert y to 1.31 format */ - return (y << 1U); - } -} - - -/** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ -__STATIC_FORCEINLINE q15_t csi_linear_interp_q15( - q15_t * pYData, - q31_t x, - uint32_t nValues) -{ - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (int32_t)0xFFF00000) >> 20); - - if (index >= (int32_t)(nValues - 1)) { - return (pYData[nValues - 1]); - - } else if (index < 0) { - return (pYData[0]); - - } else { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - /* convert y to 1.15 format */ - return (q15_t) (y >> 20); - } -} - - -/** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ -__STATIC_FORCEINLINE q7_t csi_linear_interp_q7( - q7_t * pYData, - q31_t x, - uint32_t nValues) -{ - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) { - return (pYData[0]); - } - - index = (x >> 20) & 0xfff; - - if (index >= (nValues - 1)) { - return (pYData[nValues - 1]); - - } else { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - /* convert y to 1.7(q7) format */ - return (q7_t) (y >> 20); - } -} - -/** - * @} end of LinearInterpolate group - */ - -/** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ -float32_t csi_sin_f32( - float32_t x); - - -/** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ -q31_t csi_sin_q31( - q31_t x); - - -/** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ -q15_t csi_sin_q15( - q15_t x); - - -/** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ -float32_t csi_cos_f32( - float32_t x); - - -/** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ -q31_t csi_cos_q31( - q31_t x); - - -/** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ -q15_t csi_cos_q15( - q15_t x); - - -/** - @brief Floating-point vector of log values. - @param[in] pSrc points to the input vector - @param[out] pDst points to the output vector - @param[in] blockSize number of samples in each vector - @return none - */ -void csi_vlog_f32( - const float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - -/** - @brief Floating-point vector of exp values. - @param[in] pSrc points to the input vector - @param[out] pDst points to the output vector - @param[in] blockSize number of samples in each vector - @return none - */ -void csi_vexp_f32( - const float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - -/** - * @ingroup groupFastMath - */ - - -/** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
- *      x1 = x0 - f(x0)/f'(x0)
- *
- * where x1 is the current estimate, - * x0 is the previous estimate, and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
- *     x0 = in/2                         [initial guess]
- *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
- *
- */ - - -/** - * @addtogroup SQRT - * @{ - */ - -/** - @brief Q15 square root function. - @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF - @param[out] pOut points to square root of input value - @return execution status - - \ref CSI_MATH_SUCCESS : input value is positive - - \ref CSI_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 - */ -csi_status csi_sqrt_q15( - q15_t in, - q15_t * pOut); - -/** - @brief Floating-point square root function. - @param[in] in input value - @param[out] pOut square root of input value - @return execution status - - \ref CSI_MATH_SUCCESS : input value is positive - - \ref CSI_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 - */ -#ifdef __riscv -__STATIC_FORCEINLINE csi_status csi_sqrt_f32( - float32_t in, - float32_t * pOut) -{ - if (in >= 0.0f) { -#ifdef CSI_NEWTON_SQRTF - float32_t eps = 0.000000011; - float32_t val = in / 2; - float32_t last; - - if (in <= eps) { - *pOut = 0.0f; - } else { - do { - last = val; - val = (val + in / val) / 2; - } while (fabsf(val - last) > eps); - *pOut = val; - } -#else - *pOut = sqrtf(in); -#endif - return (CSI_MATH_SUCCESS); - } else { - *pOut = 0.0f; - return (CSI_MATH_ARGUMENT_ERROR); - } -} -#else -csi_status csi_sqrt_f32( - float32_t in, - float32_t * pOut); -#endif - - -/** - @brief Q31 square root function. - @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF - @param[out] pOut points to square root of input value - @return execution status - - \ref CSI_MATH_SUCCESS : input value is positive - - \ref CSI_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 - */ -csi_status csi_sqrt_q31( - q31_t in, - q31_t * pOut); - -/** - * @brief Vector Floating-point square root function. - * @param[in] pIn input vector. - * @param[out] pOut vector of square roots of input elements. - * @param[in] len length of input vector. - * @return The function returns CSI_MATH_SUCCESS if input value is positive value or CSI_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ -#ifdef __csky__ - -void csi_vsqrt_f32( - float32_t * pIn, - float32_t * pOut, - uint16_t len); - - void csi_vsqrt_q15( - q15_t * pIn, - q15_t * pOut, - uint16_t len); - -void csi_vsqrt_q31( - q31_t * pIn, - q31_t * pOut, - uint16_t len); - -void csi_vsqrt_q7( - q7_t * pIn, - q7_t * pOut, - uint16_t len); - - -#else -__STATIC_FORCEINLINE void csi_vsqrt_f32( - float32_t * pIn, - float32_t * pOut, - uint16_t len) -{ - for (int i = 0; i < len; i++) { - csi_sqrt_f32(pIn[i], pOut + i); - } -} - -__STATIC_FORCEINLINE void csi_vsqrt_q15( - q15_t * pIn, - q15_t * pOut, - uint16_t len -) -{ - for (int i = 0; i < len; i++) { - csi_sqrt_q15(pIn[i], pOut + i); - } -} -__STATIC_FORCEINLINE void csi_vsqrt_q31( - q31_t * pIn, - q31_t * pOut, - uint16_t len -) -{ - for (int i = 0; i < len; i++) { - csi_sqrt_q31(pIn[i], pOut + i); - } -} -#endif -/** - * @} end of SQRT group - */ - -/** - * @brief floating-point Circular write function. - a*/ -#ifndef __csky__ -__STATIC_FORCEINLINE void csi_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) -{ - uint32_t i = 0U; - int32_t wOffset; - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0U) { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - /* Update the input pointer */ - src += srcInc; - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - - if (wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; -} - - - -/** - * @brief floating-point Circular Read function. - */ -__STATIC_FORCEINLINE void csi_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) -{ - uint32_t i = 0U; - int32_t rOffset; - int32_t* dst_end; - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = dst_base + dst_length; - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0U) { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - /* Update the input pointer */ - dst += dstInc; - - if (dst == dst_end) { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if (rOffset >= L) { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; -} -#endif -/** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void csi_power_q31( - const q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - -void csi_power_int32( - int32_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - -/** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void csi_power_f32( - const float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - -/** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void csi_power_q15( - const q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - -/** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void csi_power_q7( - const q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - -/** - * @brief Mean value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void csi_mean_q7( - const q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - -/** - * @brief Mean value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void csi_mean_q15( - const q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - -/** - * @brief Mean value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void csi_mean_q31( - const q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - -/** - * @brief Mean value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void csi_mean_f32( - const float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - -/** - * @brief Variance of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void csi_var_f32( - const float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - -/** - * @brief Variance of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void csi_var_q31( - const q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - -/** - * @brief Variance of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void csi_var_q15( - const q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - -/** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void csi_rms_f32( - const float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - -/** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void csi_rms_q31( - const q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - -/** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void csi_rms_q15( - const q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - -/** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void csi_std_f32( - const float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - -/** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void csi_std_q31( - const q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - -/** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void csi_std_q15( - const q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - -/** - * @brief Floating-point complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ -void csi_cmplx_mag_f32( - const float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - -/** - * @brief Q31 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ -void csi_cmplx_mag_q31( - const q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - -/** - * @brief Q15 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ -void csi_cmplx_mag_q15( - const q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - -/** - * @brief Q15 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ -void csi_cmplx_dot_prod_q15( - const q15_t * pSrcA, - const q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - -/** - * @brief Q31 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ -void csi_cmplx_dot_prod_q31( - const q31_t * pSrcA, - const q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - void csi_dot_prod_u64xu8( - uint8_t * pSrcA, - uint64_t * pSrcB, - uint32_t blockSize, - uint64_t * result); - -/** - * @brief Floating-point complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ -void csi_cmplx_dot_prod_f32( - const float32_t * pSrcA, - const float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - -/** - * @brief Q15 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ -void csi_cmplx_mult_real_q15( - const q15_t * pSrcCmplx, - const q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - -/** - * @brief Q31 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ -void csi_cmplx_mult_real_q31( - const q31_t * pSrcCmplx, - const q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - -/** - * @brief Floating-point complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ -void csi_cmplx_mult_real_f32( - const float32_t * pSrcCmplx, - const float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - -/** - * @brief Minimum value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - */ -void csi_min_q7( - const q7_t * pSrc, - uint16_t blockSize, - q7_t * result, - uint16_t * index); - - -/** - * @brief Minimum value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[in] pIndex is the array index of the minimum value in the input buffer. - */ -void csi_min_q15( - const q15_t * pSrc, - uint16_t blockSize, - q15_t * pResult, - uint16_t * pIndex); - - -/** - * @brief Minimum value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ -void csi_min_q31( - const q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Minimum value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ -void csi_min_f32( - const float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ -void csi_max_q7( - const q7_t * pSrc, - uint16_t blockSize, - q7_t * pResult, - uint16_t * pIndex); - - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ -void csi_max_q15( - const q15_t * pSrc, - uint16_t blockSize, - q15_t * pResult, - uint16_t * pIndex); - - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ -void csi_max_q31( - const q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ -void csi_max_f32( - const float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - -/** - @brief Maximum value of a floating-point vector. - @param[in] pSrc points to the input vector - @param[in] blockSize number of samples in input vector - @param[out] pResult maximum value returned here - @return none - */ -void csi_max_no_idx_f32( - const float32_t *pSrc, - uint32_t blockSize, - float32_t *pResult); - -/** - * @brief Q15 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ -void csi_cmplx_mult_cmplx_q15( - const q15_t * pSrcA, - const q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - -/** - * @brief Q31 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ -void csi_cmplx_mult_cmplx_q31( - const q31_t * pSrcA, - const q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - -/** - * @brief Floating-point complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ -void csi_cmplx_mult_cmplx_f32( - const float32_t * pSrcA, - const float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - -void csi_cmplx_mult_cmplx_re_f32( - const float32_t * pSrcA, - const float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - -/** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - */ -void csi_float_to_q31( - const float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - */ -void csi_float_to_q15( - const float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - */ -void csi_float_to_q7( - const float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - -/** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ -void csi_q31_to_float( - const q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - -/** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ -void csi_q31_to_q15( - const q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - -void csi_q31_to_q7_rs( - q31_t * pSrc, - q7_t * pDst, - uint32_t shiftValue, - uint32_t blockSize); - -void csi_q63_to_q31_rs( - q63_t * pSrc, - q31_t * pDst, - uint32_t shiftValue, - uint32_t blockSize); - - -/** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ -void csi_q31_to_q7( - const q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - -/** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ -void csi_q15_to_float( - const q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - -/** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ -void csi_q15_to_q31( - const q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ -void csi_q15_to_q7( - const q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - -/** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ -void csi_q7_to_float( - const q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - -/** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void csi_q7_to_q31( - const q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void csi_q7_to_q15( - const q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief SVM linear instance init function - * @param[in] S Parameters for SVM functions - * @param[in] nbOfSupportVectors Number of support vectors - * @param[in] vectorDimension Dimension of vector space - * @param[in] intercept Intercept - * @param[in] dualCoefficients Array of dual coefficients - * @param[in] supportVectors Array of support vectors - * @param[in] classes Array of 2 classes ID - * @return none. - * - */ - - -void csi_svm_linear_init_f32(csi_svm_linear_instance_f32 *S, - uint32_t nbOfSupportVectors, - uint32_t vectorDimension, - float32_t intercept, - const float32_t *dualCoefficients, - const float32_t *supportVectors, - const int32_t *classes); - -/** - * @brief SVM linear prediction - * @param[in] S Pointer to an instance of the linear SVM structure. - * @param[in] in Pointer to input vector - * @param[out] pResult Decision value - * @return none. - * - */ - -void csi_svm_linear_predict_f32(const csi_svm_linear_instance_f32 *S, - const float32_t * in, - int32_t * pResult); - - -/** - * @brief SVM polynomial instance init function - * @param[in] S points to an instance of the polynomial SVM structure. - * @param[in] nbOfSupportVectors Number of support vectors - * @param[in] vectorDimension Dimension of vector space - * @param[in] intercept Intercept - * @param[in] dualCoefficients Array of dual coefficients - * @param[in] supportVectors Array of support vectors - * @param[in] classes Array of 2 classes ID - * @param[in] degree Polynomial degree - * @param[in] coef0 coeff0 (scikit-learn terminology) - * @param[in] gamma gamma (scikit-learn terminology) - * @return none. - * - */ - - -void csi_svm_polynomial_init_f32(csi_svm_polynomial_instance_f32 *S, - uint32_t nbOfSupportVectors, - uint32_t vectorDimension, - float32_t intercept, - const float32_t *dualCoefficients, - const float32_t *supportVectors, - const int32_t *classes, - int32_t degree, - float32_t coef0, - float32_t gamma - ); - -/** - * @brief SVM polynomial prediction - * @param[in] S Pointer to an instance of the polynomial SVM structure. - * @param[in] in Pointer to input vector - * @param[out] pResult Decision value - * @return none. - * - */ -void csi_svm_polynomial_predict_f32(const csi_svm_polynomial_instance_f32 *S, - const float32_t * in, - int32_t * pResult); - - -/** - * @brief SVM radial basis function instance init function - * @param[in] S points to an instance of the polynomial SVM structure. - * @param[in] nbOfSupportVectors Number of support vectors - * @param[in] vectorDimension Dimension of vector space - * @param[in] intercept Intercept - * @param[in] dualCoefficients Array of dual coefficients - * @param[in] supportVectors Array of support vectors - * @param[in] classes Array of 2 classes ID - * @param[in] gamma gamma (scikit-learn terminology) - * @return none. - * - */ - -void csi_svm_rbf_init_f32(csi_svm_rbf_instance_f32 *S, - uint32_t nbOfSupportVectors, - uint32_t vectorDimension, - float32_t intercept, - const float32_t *dualCoefficients, - const float32_t *supportVectors, - const int32_t *classes, - float32_t gamma - ); - -/** - * @brief SVM rbf prediction - * @param[in] S Pointer to an instance of the rbf SVM structure. - * @param[in] in Pointer to input vector - * @param[out] pResult decision value - * @return none. - * - */ -void csi_svm_rbf_predict_f32(const csi_svm_rbf_instance_f32 *S, - const float32_t * in, - int32_t * pResult); - -/** - * @brief SVM sigmoid instance init function - * @param[in] S points to an instance of the rbf SVM structure. - * @param[in] nbOfSupportVectors Number of support vectors - * @param[in] vectorDimension Dimension of vector space - * @param[in] intercept Intercept - * @param[in] dualCoefficients Array of dual coefficients - * @param[in] supportVectors Array of support vectors - * @param[in] classes Array of 2 classes ID - * @param[in] coef0 coeff0 (scikit-learn terminology) - * @param[in] gamma gamma (scikit-learn terminology) - * @return none. - * - */ - -void csi_svm_sigmoid_init_f32(csi_svm_sigmoid_instance_f32 *S, - uint32_t nbOfSupportVectors, - uint32_t vectorDimension, - float32_t intercept, - const float32_t *dualCoefficients, - const float32_t *supportVectors, - const int32_t *classes, - float32_t coef0, - float32_t gamma - ); - -/** - * @brief SVM sigmoid prediction - * @param[in] S Pointer to an instance of the rbf SVM structure. - * @param[in] in Pointer to input vector - * @param[out] pResult Decision value - * @return none. - * - */ -void csi_svm_sigmoid_predict_f32(const csi_svm_sigmoid_instance_f32 *S, - const float32_t * in, - int32_t * pResult); - - -/** - * @brief Naive Gaussian Bayesian Estimator - * - * @param[in] S points to a naive bayes instance structure - * @param[in] in points to the elements of the input vector. - * @param[in] pBuffer points to a buffer of length numberOfClasses - * @return The predicted class - * - */ - - -uint32_t csi_gaussian_naive_bayes_predict_f32(const csi_gaussian_naive_bayes_instance_f32 *S, - const float32_t * in, - float32_t *pBuffer); - -/** - * @brief Computation of the LogSumExp - * - * In probabilistic computations, the dynamic of the probability values can be very - * wide because they come from gaussian functions. - * To avoid underflow and overflow issues, the values are represented by their log. - * In this representation, multiplying the original exp values is easy : their logs are added. - * But adding the original exp values is requiring some special handling and it is the - * goal of the LogSumExp function. - * - * If the values are x1...xn, the function is computing: - * - * ln(exp(x1) + ... + exp(xn)) and the computation is done in such a way that - * rounding issues are minimised. - * - * The max xm of the values is extracted and the function is computing: - * xm + ln(exp(x1 - xm) + ... + exp(xn - xm)) - * - * @param[in] *in Pointer to an array of input values. - * @param[in] blockSize Number of samples in the input array. - * @return LogSumExp - * - */ - - -float32_t csi_logsumexp_f32(const float32_t *in, uint32_t blockSize); - -/** - * @brief Dot product with log arithmetic - * - * Vectors are containing the log of the samples - * - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[in] pTmpBuffer temporary buffer of length blockSize - * @return The log of the dot product . - * - */ - - -float32_t csi_logsumexp_dot_prod_f32(const float32_t * pSrcA, - const float32_t * pSrcB, - uint32_t blockSize, - float32_t *pTmpBuffer); - -/** - * @brief Entropy - * - * @param[in] pSrcA Array of input values. - * @param[in] blockSize Number of samples in the input array. - * @return Entropy -Sum(p ln p) - * - */ - - -float32_t csi_entropy_f32(const float32_t * pSrcA,uint32_t blockSize); - - -/** - * @brief Kullback-Leibler - * - * @param[in] pSrcA Pointer to an array of input values for probability distribution A. - * @param[in] pSrcB Pointer to an array of input values for probability distribution B. - * @param[in] blockSize Number of samples in the input array. - * @return Kullback-Leibler Divergence D(A || B) - * - */ -float32_t csi_kullback_leibler_f32(const float32_t * pSrcA - ,const float32_t * pSrcB - ,uint32_t blockSize); - - -/** - * @brief Weighted sum - * - * - * @param[in] *in Array of input values. - * @param[in] *weigths Weights - * @param[in] blockSize Number of samples in the input array. - * @return Weighted sum - * - */ -float32_t csi_weighted_sum_f32(const float32_t *in - , const float32_t *weigths - , uint32_t blockSize); - - -/** - * @brief Barycenter - * - * - * @param[in] in List of vectors - * @param[in] weights Weights of the vectors - * @param[out] out Barycenter - * @param[in] nbVectors Number of vectors - * @param[in] vecDim Dimension of space (vector dimension) - * @return None - * - */ -void csi_barycenter_f32(const float32_t *in - , const float32_t *weights - , float32_t *out - , uint32_t nbVectors - , uint32_t vecDim); - -/** - * @brief Euclidean distance between two vectors - * @param[in] pA First vector - * @param[in] pB Second vector - * @param[in] blockSize vector length - * @return distance - * - */ - -float32_t csi_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); - -/** - * @brief Bray-Curtis distance between two vectors - * @param[in] pA First vector - * @param[in] pB Second vector - * @param[in] blockSize vector length - * @return distance - * - */ -float32_t csi_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); - -/** - * @brief Canberra distance between two vectors - * - * This function may divide by zero when samples pA[i] and pB[i] are both zero. - * The result of the computation will be correct. So the division per zero may be - * ignored. - * - * @param[in] pA First vector - * @param[in] pB Second vector - * @param[in] blockSize vector length - * @return distance - * - */ -float32_t csi_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); - - -/** - * @brief Chebyshev distance between two vectors - * @param[in] pA First vector - * @param[in] pB Second vector - * @param[in] blockSize vector length - * @return distance - * - */ -float32_t csi_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); - - -/** - * @brief Cityblock (Manhattan) distance between two vectors - * @param[in] pA First vector - * @param[in] pB Second vector - * @param[in] blockSize vector length - * @return distance - * - */ -float32_t csi_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); - -/** - * @brief Correlation distance between two vectors - * - * The input vectors are modified in place ! - * - * @param[in] pA First vector - * @param[in] pB Second vector - * @param[in] blockSize vector length - * @return distance - * - */ -float32_t csi_correlation_distance_f32(float32_t *pA,float32_t *pB, uint32_t blockSize); - -/** - * @brief Cosine distance between two vectors - * - * @param[in] pA First vector - * @param[in] pB Second vector - * @param[in] blockSize vector length - * @return distance - * - */ - -float32_t csi_cosine_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); - -/** - * @brief Jensen-Shannon distance between two vectors - * - * This function is assuming that elements of second vector are > 0 - * and 0 only when the corresponding element of first vector is 0. - * Otherwise the result of the computation does not make sense - * and for speed reasons, the cases returning NaN or Infinity are not - * managed. - * - * When the function is computing x log (x / y) with x 0 and y 0, - * it will compute the right value (0) but a division per zero will occur - * and shoudl be ignored in client code. - * - * @param[in] pA First vector - * @param[in] pB Second vector - * @param[in] blockSize vector length - * @return distance - * - */ - -float32_t csi_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB,uint32_t blockSize); - -/** - * @brief Minkowski distance between two vectors - * - * @param[in] pA First vector - * @param[in] pB Second vector - * @param[in] n Norm order (>= 2) - * @param[in] blockSize vector length - * @return distance - * - */ - - - -float32_t csi_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize); - -/** - * @brief Dice distance between two vectors - * - * @param[in] pA First vector of packed booleans - * @param[in] pB Second vector of packed booleans - * @param[in] order Distance order - * @param[in] blockSize Number of samples - * @return distance - * - */ - - -float32_t csi_dice_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); - -/** - * @brief Hamming distance between two vectors - * - * @param[in] pA First vector of packed booleans - * @param[in] pB Second vector of packed booleans - * @param[in] numberOfBools Number of booleans - * @return distance - * - */ - -float32_t csi_hamming_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); - -/** - * @brief Jaccard distance between two vectors - * - * @param[in] pA First vector of packed booleans - * @param[in] pB Second vector of packed booleans - * @param[in] numberOfBools Number of booleans - * @return distance - * - */ - -float32_t csi_jaccard_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); - -/** - * @brief Kulsinski distance between two vectors - * - * @param[in] pA First vector of packed booleans - * @param[in] pB Second vector of packed booleans - * @param[in] numberOfBools Number of booleans - * @return distance - * - */ - -float32_t csi_kulsinski_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); - -/** - * @brief Roger Stanimoto distance between two vectors - * - * @param[in] pA First vector of packed booleans - * @param[in] pB Second vector of packed booleans - * @param[in] numberOfBools Number of booleans - * @return distance - * - */ - -float32_t csi_rogerstanimoto_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); - -/** - * @brief Russell-Rao distance between two vectors - * - * @param[in] pA First vector of packed booleans - * @param[in] pB Second vector of packed booleans - * @param[in] numberOfBools Number of booleans - * @return distance - * - */ - -float32_t csi_russellrao_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); - -/** - * @brief Sokal-Michener distance between two vectors - * - * @param[in] pA First vector of packed booleans - * @param[in] pB Second vector of packed booleans - * @param[in] numberOfBools Number of booleans - * @return distance - * - */ - -float32_t csi_sokalmichener_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); - -/** - * @brief Sokal-Sneath distance between two vectors - * - * @param[in] pA First vector of packed booleans - * @param[in] pB Second vector of packed booleans - * @param[in] numberOfBools Number of booleans - * @return distance - * - */ - -float32_t csi_sokalsneath_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); - -/** - * @brief Yule distance between two vectors - * - * @param[in] pA First vector of packed booleans - * @param[in] pB Second vector of packed booleans - * @param[in] numberOfBools Number of booleans - * @return distance - * - */ - -float32_t csi_yule_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); - - -/** - * @ingroup groupInterpolation - */ - -/** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
- *   typedef struct
- *   {
- *     uint16_t numRows;
- *     uint16_t numCols;
- *     float32_t *pData;
- * } csi_bilinear_interp_instance_f32;
- *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
- *     XF = floor(x)
- *     YF = floor(y)
- *
- * \par - * The interpolated output point is computed as: - * 
- *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
- *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
- *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
- *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
- *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - -/** - * @addtogroup BilinearInterpolate - * @{ - */ - -/** -* @brief Floating-point bilinear interpolation. -* @param[in,out] S points to an instance of the interpolation structure. -* @param[in] X interpolation coordinate. -* @param[in] Y interpolation coordinate. -* @return out interpolated value. -*/ -__STATIC_FORCEINLINE float32_t csi_bilinear_interp_f32( - const csi_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) -{ - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) { - return (0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - /* return to application */ - return (out); -} - - -/** -* @brief Q31 bilinear interpolation. -* @param[in,out] S points to an instance of the interpolation structure. -* @param[in] X interpolation coordinate in 12.20 format. -* @param[in] Y interpolation coordinate in 12.20 format. -* @return out interpolated value. -*/ -__STATIC_FORCEINLINE q31_t csi_bilinear_interp_q31( - csi_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) -{ - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { - return (0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11U; - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; - x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11U; - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; - y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - /* Convert acc to 1.31(q31) format */ - return ((q31_t)(acc << 2)); -} - - -/** -* @brief Q15 bilinear interpolation. -* @param[in,out] S points to an instance of the interpolation structure. -* @param[in] X interpolation coordinate in 12.20 format. -* @param[in] Y interpolation coordinate in 12.20 format. -* @return out interpolated value. -*/ -__STATIC_FORCEINLINE q15_t csi_bilinear_interp_q15( - csi_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) -{ - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U); - acc = ((q63_t) out * (0xFFFFF - yfract)); - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U); - acc += ((q63_t) out * (xfract)); - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U); - acc += ((q63_t) out * (yfract)); - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); - acc += ((q63_t) out * (yfract)); - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return ((q15_t)(acc >> 36)); -} - - -/** -* @brief Q7 bilinear interpolation. -* @param[in,out] S points to an instance of the interpolation structure. -* @param[in] X interpolation coordinate in 12.20 format. -* @param[in] Y interpolation coordinate in 12.20 format. -* @return out interpolated value. -*/ -__STATIC_FORCEINLINE q7_t csi_bilinear_interp_q7( - csi_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) -{ - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & (q31_t)0x000FFFFF); - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & (q31_t)0x000FFFFF); - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return ((q7_t)(acc >> 40)); -} - -/** - * @} end of BilinearInterpolate group - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* _CSI_MATH_H */ - -/** - * - * End of file. - */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_common_tables.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_common_tables.h deleted file mode 100644 index 13a96dca..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_common_tables.h +++ /dev/null @@ -1,229 +0,0 @@ -/* - * Copyright (C) 2016-2019 C-SKY Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file csky_common_tables.h - * @brief This file has extern declaration for common tables like - * Bitreverse, reciprocal etc which are used across different functions. - * @version V1.0 - * @date 20. Dec 2016 - ******************************************************************************/ - -#ifndef _CSKY_COMMON_TABLES_H -#define _CSKY_COMMON_TABLES_H - -#include "csky_math.h" - -extern const uint16_t cskyBitRevTable[1024]; -extern const q15_t cskyRecipTableQ15[64]; -extern const q31_t cskyRecipTableQ31[64]; -extern const uint32_t twiddleCoef_16[32]; -extern const uint32_t twiddleCoef_32[64]; -extern const uint32_t twiddleCoef_64[128]; -extern const uint32_t twiddleCoef_128[256]; -extern const uint32_t twiddleCoef_256[512]; -extern const uint32_t twiddleCoef_512[1024]; -extern const uint32_t twiddleCoef_1024[2048]; -extern const uint32_t twiddleCoef_2048[4096]; -extern const uint32_t twiddleCoef_4096[8192]; -extern const q31_t twiddleCoef_16_q31[24]; -extern const q31_t twiddleCoef_32_q31[48]; -extern const q31_t twiddleCoef_64_q31[96]; -extern const q31_t twiddleCoef_128_q31[192]; -extern const q31_t twiddleCoef_256_q31[384]; -extern const q31_t twiddleCoef_512_q31[768]; -extern const q31_t twiddleCoef_1024_q31[1536]; -extern const q31_t twiddleCoef_2048_q31[3072]; -extern const q31_t twiddleCoef_4096_q31[6144]; -extern const q15_t twiddleCoef_16_q15[24]; -extern const q15_t twiddleCoef_32_q15[48]; -extern const q15_t twiddleCoef_64_q15[96]; -extern const q15_t twiddleCoef_128_q15[192]; -extern const q15_t twiddleCoef_256_q15[384]; -extern const q15_t twiddleCoef_512_q15[768]; -extern const q15_t twiddleCoef_1024_q15[1536]; -extern const q15_t twiddleCoef_2048_q15[3072]; -extern const q15_t twiddleCoef_4096_q15[6144]; -extern const float32_t twiddleCoef_rfft_32[32]; -extern const float32_t twiddleCoef_rfft_64[64]; -extern const float32_t twiddleCoef_rfft_128[128]; -extern const float32_t twiddleCoef_rfft_256[256]; -extern const float32_t twiddleCoef_rfft_512[512]; -extern const float32_t twiddleCoef_rfft_1024[1024]; -extern const float32_t twiddleCoef_rfft_2048[2048]; -extern const float32_t twiddleCoef_rfft_4096[4096]; -extern const float32_t twiddleCoef_rfft_8192[8192]; - -extern const q15_t twiddleCoef_fast_16_q15[24]; -extern const q15_t twiddleCoef_fast_32_q15[56]; -extern const q15_t twiddleCoef_fast_64_q15[120]; -extern const q15_t twiddleCoef_fast_128_q15[248]; -extern const q15_t twiddleCoef_fast_256_q15[504]; -extern const q15_t twiddleCoef_fast_512_q15[1016]; -extern const q15_t twiddleCoef_fast_1024_q15[2040]; -extern const q15_t twiddleCoef_fast_2048_q15[4088]; -extern const q15_t twiddleCoef_fast_4096_q15[8184]; - -extern const q31_t twiddleCoef_fast_16_q31[24]; -extern const q31_t twiddleCoef_fast_32_q31[56]; -extern const q31_t twiddleCoef_fast_64_q31[120]; -extern const q31_t twiddleCoef_fast_128_q31[248]; -extern const q31_t twiddleCoef_fast_256_q31[504]; -extern const q31_t twiddleCoef_fast_512_q31[1016]; -extern const q31_t twiddleCoef_fast_1024_q31[2040]; -extern const q31_t twiddleCoef_fast_2048_q31[4088]; -extern const q31_t twiddleCoef_fast_4096_q31[8184]; - -extern const uint32_t twiddleCoef_fast_16[24]; -extern const uint32_t twiddleCoef_fast_32[56]; -extern const uint32_t twiddleCoef_fast_64[120]; -extern const uint32_t twiddleCoef_fast_128[248]; -extern const uint32_t twiddleCoef_fast_256[504]; -extern const uint32_t twiddleCoef_fast_512[1016]; -extern const uint32_t twiddleCoef_fast_1024[2040]; -extern const uint32_t twiddleCoef_fast_2048[4088]; -extern const uint32_t twiddleCoef_fast_4096[8184]; - -extern const q15_t realCoefAQ15_8192[8192]; -extern const q31_t realCoefAQ31_8192[8192]; -extern const q15_t realCoefBQ15_8192[8192]; -extern const q31_t realCoefBQ31_8192[8192]; - -/*Tables for RFFT.*/ -extern const q15_t ALIGN4 realCoefAQ15_32[32]; -extern const q15_t ALIGN4 realCoefAQ15_64[64]; -extern const q15_t ALIGN4 realCoefAQ15_128[128]; -extern const q15_t ALIGN4 realCoefAQ15_256[256]; -extern const q15_t ALIGN4 realCoefAQ15_512[512]; -extern const q15_t ALIGN4 realCoefAQ15_1024[1024]; -extern const q15_t ALIGN4 realCoefAQ15_2048[2048]; -extern const q15_t ALIGN4 realCoefAQ15_4096[4096]; - -extern const q15_t ALIGN4 realCoefBQ15_32[32]; -extern const q15_t ALIGN4 realCoefBQ15_64[64]; -extern const q15_t ALIGN4 realCoefBQ15_128[128]; -extern const q15_t ALIGN4 realCoefBQ15_256[256]; -extern const q15_t ALIGN4 realCoefBQ15_512[512]; -extern const q15_t ALIGN4 realCoefBQ15_1024[1024]; -extern const q15_t ALIGN4 realCoefBQ15_2048[2048]; -extern const q15_t ALIGN4 realCoefBQ15_4096[4096]; - -extern const q31_t realCoefAQ31_32[32]; -extern const q31_t realCoefAQ31_64[64]; -extern const q31_t realCoefAQ31_128[128]; -extern const q31_t realCoefAQ31_256[256]; -extern const q31_t realCoefAQ31_512[512]; -extern const q31_t realCoefAQ31_1024[1024]; -extern const q31_t realCoefAQ31_2048[2048]; -extern const q31_t realCoefAQ31_4096[4096]; - -extern const q31_t realCoefBQ31_32[32]; -extern const q31_t realCoefBQ31_64[64]; -extern const q31_t realCoefBQ31_128[128]; -extern const q31_t realCoefBQ31_256[256]; -extern const q31_t realCoefBQ31_512[512]; -extern const q31_t realCoefBQ31_1024[1024]; -extern const q31_t realCoefBQ31_2048[2048]; -extern const q31_t realCoefBQ31_4096[4096]; - - -extern const float32_t realCoefA[8192]; -extern const float32_t realCoefB[8192]; - - -/*Tables for DCT4*/ -extern const q15_t ALIGN4 WeightsQ15_128[128+2]; -extern const q15_t ALIGN4 WeightsQ15_512[512+2]; -extern const q15_t ALIGN4 WeightsQ15_2048[2048+2]; -extern const q15_t ALIGN4 WeightsQ15_8192[8192+2]; - -extern const q15_t ALIGN4 cos_factorsQ15_128[128]; -extern const q15_t ALIGN4 cos_factorsQ15_512[512]; -extern const q15_t ALIGN4 cos_factorsQ15_2048[2048]; -extern const q15_t ALIGN4 cos_factorsQ15_8192[8192]; - - -extern const q31_t WeightsQ31_128[128+2]; -extern const q31_t WeightsQ31_512[512+2]; -extern const q31_t WeightsQ31_2048[2048+2]; -extern const q31_t WeightsQ31_8192[8192+2]; - -extern const q31_t cos_factorsQ31_128[128]; -extern const q31_t cos_factorsQ31_512[512]; -extern const q31_t cos_factorsQ31_2048[2048]; -extern const q31_t cos_factorsQ31_8192[8192]; - - -extern const float32_t Weights_128[128+2]; -extern const float32_t Weights_512[512+2]; -extern const float32_t Weights_2048[2048+2]; -extern const float32_t Weights_8192[8192+2]; - -extern const float32_t cos_factors_128[128]; -extern const float32_t cos_factors_512[512]; -extern const float32_t cos_factors_2048[2048]; -extern const float32_t cos_factors_8192[8192]; - -/* floating-point bit reversal tables */ -#define CSKYBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) -#define CSKYBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) -#define CSKYBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) -#define CSKYBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) -#define CSKYBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) -#define CSKYBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) -#define CSKYBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) -#define CSKYBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) -#define CSKYBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t cskyBitRevIndexTable16[CSKYBITREVINDEXTABLE__16_TABLE_LENGTH]; -extern const uint16_t cskyBitRevIndexTable32[CSKYBITREVINDEXTABLE__32_TABLE_LENGTH]; -extern const uint16_t cskyBitRevIndexTable64[CSKYBITREVINDEXTABLE__64_TABLE_LENGTH]; -extern const uint16_t cskyBitRevIndexTable128[CSKYBITREVINDEXTABLE_128_TABLE_LENGTH]; -extern const uint16_t cskyBitRevIndexTable256[CSKYBITREVINDEXTABLE_256_TABLE_LENGTH]; -extern const uint16_t cskyBitRevIndexTable512[CSKYBITREVINDEXTABLE_512_TABLE_LENGTH]; -extern const uint16_t cskyBitRevIndexTable1024[CSKYBITREVINDEXTABLE1024_TABLE_LENGTH]; -extern const uint16_t cskyBitRevIndexTable2048[CSKYBITREVINDEXTABLE2048_TABLE_LENGTH]; -extern const uint16_t cskyBitRevIndexTable4096[CSKYBITREVINDEXTABLE4096_TABLE_LENGTH]; - -/* fixed-point bit reversal tables */ -#define CSKYBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) -#define CSKYBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) -#define CSKYBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) -#define CSKYBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) -#define CSKYBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) -#define CSKYBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) -#define CSKYBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) -#define CSKYBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) -#define CSKYBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t cskyBitRevIndexTable_fixed_16[CSKYBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; -extern const uint16_t cskyBitRevIndexTable_fixed_32[CSKYBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; -extern const uint16_t cskyBitRevIndexTable_fixed_64[CSKYBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; -extern const uint16_t cskyBitRevIndexTable_fixed_128[CSKYBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; -extern const uint16_t cskyBitRevIndexTable_fixed_256[CSKYBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; -extern const uint16_t cskyBitRevIndexTable_fixed_512[CSKYBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; -extern const uint16_t cskyBitRevIndexTable_fixed_1024[CSKYBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; -extern const uint16_t cskyBitRevIndexTable_fixed_2048[CSKYBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; -extern const uint16_t cskyBitRevIndexTable_fixed_4096[CSKYBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; - -/* Tables for Fast Math Sine and Cosine */ -extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; -extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; -extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; - -#endif /* CSKY_COMMON_TABLES_H */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_const_structs.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_const_structs.h deleted file mode 100644 index 1f5b5409..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_const_structs.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (C) 2016-2019 C-SKY Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file csky_const_structs.h - * @brief This file has constant structs that are initialized for - * user convenience. For example, some can be given as - * arguments to the csky_cfft_f32() function. - * @version V1.0 - * @date 20. Dec 2016 - ******************************************************************************/ - -#ifndef _CSKY_CONST_STRUCTS_H -#define _CSKY_CONST_STRUCTS_H - -#include "csky_math.h" -#include "csky_common_tables.h" - - extern const csky_cfft_instance_f32 csky_cfft_sR_f32_len16; - extern const csky_cfft_instance_f32 csky_cfft_sR_f32_len32; - extern const csky_cfft_instance_f32 csky_cfft_sR_f32_len64; - extern const csky_cfft_instance_f32 csky_cfft_sR_f32_len128; - extern const csky_cfft_instance_f32 csky_cfft_sR_f32_len256; - extern const csky_cfft_instance_f32 csky_cfft_sR_f32_len512; - extern const csky_cfft_instance_f32 csky_cfft_sR_f32_len1024; - extern const csky_cfft_instance_f32 csky_cfft_sR_f32_len2048; - extern const csky_cfft_instance_f32 csky_cfft_sR_f32_len4096; - - extern const csky_cfft_instance_q31 csky_cfft_sR_q31_len16; - extern const csky_cfft_instance_q31 csky_cfft_sR_q31_len32; - extern const csky_cfft_instance_q31 csky_cfft_sR_q31_len64; - extern const csky_cfft_instance_q31 csky_cfft_sR_q31_len128; - extern const csky_cfft_instance_q31 csky_cfft_sR_q31_len256; - extern const csky_cfft_instance_q31 csky_cfft_sR_q31_len512; - extern const csky_cfft_instance_q31 csky_cfft_sR_q31_len1024; - extern const csky_cfft_instance_q31 csky_cfft_sR_q31_len2048; - extern const csky_cfft_instance_q31 csky_cfft_sR_q31_len4096; - - extern const csky_cfft_instance_q15 csky_cfft_sR_q15_len16; - extern const csky_cfft_instance_q15 csky_cfft_sR_q15_len32; - extern const csky_cfft_instance_q15 csky_cfft_sR_q15_len64; - extern const csky_cfft_instance_q15 csky_cfft_sR_q15_len128; - extern const csky_cfft_instance_q15 csky_cfft_sR_q15_len256; - extern const csky_cfft_instance_q15 csky_cfft_sR_q15_len512; - extern const csky_cfft_instance_q15 csky_cfft_sR_q15_len1024; - extern const csky_cfft_instance_q15 csky_cfft_sR_q15_len2048; - extern const csky_cfft_instance_q15 csky_cfft_sR_q15_len4096; - - extern csky_rfft_instance_q15 csky_rfft_sR_q15_len32; - extern csky_rfft_instance_q15 csky_rfft_sR_q15_len64; - extern csky_rfft_instance_q15 csky_rfft_sR_q15_len128; - extern csky_rfft_instance_q15 csky_rfft_sR_q15_len256; - extern csky_rfft_instance_q15 csky_rfft_sR_q15_len512; - extern csky_rfft_instance_q15 csky_rfft_sR_q15_len1024; - extern csky_rfft_instance_q15 csky_rfft_sR_q15_len2048; - extern csky_rfft_instance_q15 csky_rfft_sR_q15_len4096; - extern csky_rfft_instance_q15 csky_rfft_sR_q15_len8192; - - - extern csky_rfft_instance_q15 csky_inv_rfft_sR_q15_len32; - extern csky_rfft_instance_q15 csky_inv_rfft_sR_q15_len64; - extern csky_rfft_instance_q15 csky_inv_rfft_sR_q15_len128; - extern csky_rfft_instance_q15 csky_inv_rfft_sR_q15_len256; - extern csky_rfft_instance_q15 csky_inv_rfft_sR_q15_len512; - extern csky_rfft_instance_q15 csky_inv_rfft_sR_q15_len1024; - extern csky_rfft_instance_q15 csky_inv_rfft_sR_q15_len2048; - extern csky_rfft_instance_q15 csky_inv_rfft_sR_q15_len4096; - extern csky_rfft_instance_q15 csky_inv_rfft_sR_q15_len8192; - - - extern csky_rfft_instance_q31 csky_rfft_sR_q31_len32; - extern csky_rfft_instance_q31 csky_rfft_sR_q31_len64; - extern csky_rfft_instance_q31 csky_rfft_sR_q31_len128; - extern csky_rfft_instance_q31 csky_rfft_sR_q31_len256; - extern csky_rfft_instance_q31 csky_rfft_sR_q31_len512; - extern csky_rfft_instance_q31 csky_rfft_sR_q31_len1024; - extern csky_rfft_instance_q31 csky_rfft_sR_q31_len2048; - extern csky_rfft_instance_q31 csky_rfft_sR_q31_len4096; - extern csky_rfft_instance_q31 csky_rfft_sR_q31_len8192; - - extern csky_rfft_instance_q31 csky_inv_rfft_sR_q31_len32; - extern csky_rfft_instance_q31 csky_inv_rfft_sR_q31_len64; - extern csky_rfft_instance_q31 csky_inv_rfft_sR_q31_len128; - extern csky_rfft_instance_q31 csky_inv_rfft_sR_q31_len256; - extern csky_rfft_instance_q31 csky_inv_rfft_sR_q31_len512; - extern csky_rfft_instance_q31 csky_inv_rfft_sR_q31_len1024; - extern csky_rfft_instance_q31 csky_inv_rfft_sR_q31_len2048; - extern csky_rfft_instance_q31 csky_inv_rfft_sR_q31_len4096; - extern csky_rfft_instance_q31 csky_inv_rfft_sR_q31_len8192; - - - extern csky_rfft_fast_instance_f32 csky_rfft_sR_f32_len32; - extern csky_rfft_fast_instance_f32 csky_rfft_sR_f32_len64; - extern csky_rfft_fast_instance_f32 csky_rfft_sR_f32_len128; - extern csky_rfft_fast_instance_f32 csky_rfft_sR_f32_len256; - extern csky_rfft_fast_instance_f32 csky_rfft_sR_f32_len512; - extern csky_rfft_fast_instance_f32 csky_rfft_sR_f32_len1024; - extern csky_rfft_fast_instance_f32 csky_rfft_sR_f32_len2048; - extern csky_rfft_fast_instance_f32 csky_rfft_sR_f32_len4096; - extern csky_rfft_fast_instance_f32 csky_rfft_sR_f32_len8192; - - extern csky_dct4_instance_q15 csky_dct4_sR_q15_len128; - extern csky_dct4_instance_q15 csky_dct4_sR_q15_len512; - extern csky_dct4_instance_q15 csky_dct4_sR_q15_len2048; - extern csky_dct4_instance_q15 csky_dct4_sR_q15_len8192; - - extern csky_dct4_instance_q31 csky_dct4_sR_q31_len128; - extern csky_dct4_instance_q31 csky_dct4_sR_q31_len512; - extern csky_dct4_instance_q31 csky_dct4_sR_q31_len2048; - extern csky_dct4_instance_q31 csky_dct4_sR_q31_len8192; - - extern csky_dct4_instance_f32 csky_dct4_sR_f32_len128; - extern csky_dct4_instance_f32 csky_dct4_sR_f32_len512; - extern csky_dct4_instance_f32 csky_dct4_sR_f32_len2048; - extern csky_dct4_instance_f32 csky_dct4_sR_f32_len8192; -#endif diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_math.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_math.h deleted file mode 100644 index d7adfecb..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_math.h +++ /dev/null @@ -1,4637 +0,0 @@ -/* - * Copyright (C) 2016-2019 C-SKY Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file csky_math.h - * @brief Public header file for CSI DSP Library. - * @version V1.0 - * @date 20. Dec 2016 - ******************************************************************************/ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CSI math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } csky_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function csky_mat_init_f32(), csky_mat_init_q31() - * and csky_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * csky_matrix_instance_f32 S = {nRows, nColumns, pData};
- * csky_matrix_instance_q31 S = {nRows, nColumns, pData};
- * csky_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     CSKY_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     CSKY_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - * 
- *     CSKY_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return CSKY_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - - -/** - * @defgroup groupYunvoice Yunvoice Functions - * These functions are designed for Yunvoice project, which are modified - * according to the CEVA DSP functions. So, one can porting the software - * from CEVA to CSKY straightforwardly. - */ - -/** - * @defgroup groupExamples Examples - */ - - -#ifndef _CSKY_MATH_H -#define _CSKY_MATH_H - -#define __CSI_GENERIC /* disable NVIC and Systick functions */ - -#include "csi_core.h" - -#include -#undef __CSI_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" -#include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#ifndef PI -#define PI 3.14159265358979f -#endif - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define FAST_MATH_TABLE_SIZE 512 -#define FAST_MATH_Q31_SHIFT (32 - 10) -#define FAST_MATH_Q15_SHIFT (16 - 10) -#define CONTROLLER_Q31_SHIFT (32 - 9) -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x400000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - /** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 -#else - #define ALIGN4 __attribute__((aligned(4))) -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - -__ALWAYS_STATIC_INLINE int32_t __SSAT_31(int32_t x) -{ - int32_t res = x; - if (x > 0x3fffffff) { - res = 0x3fffffff; - } else if (x < -1073741824) { - res = -1073741824; - } - - return res; -} - -__ALWAYS_STATIC_INLINE int32_t __SSAT_16(int32_t x) -{ - int32_t res = x; - if (x > 0x7fff) { - res = 0x7fff; - } else if (x < -32768) { - res = -32768; - } - - return res; -} - -__ALWAYS_STATIC_INLINE int32_t __SSAT_8(int32_t x) -{ - int32_t res = x; - if (x > 0x7f) { - res = 0x7f; - } else if (x < -128) { - res = -128; - } - - return res; -} - -#ifdef CSKY_SIMD -/* SMMLAR */ -__ALWAYS_STATIC_INLINE int32_t multAcc_32x32_keep32_R(int32_t a, int32_t x, int32_t y) -{ - __ASM volatile("mula.s32.rhs %0, %1, %2\n\t" - :"=r" (a), "=r" (x), "=r" (y) : "0" (a), "1" (x), "2" (y)); - return a; -} - -/* SMMLSR */ -__ALWAYS_STATIC_INLINE int32_t multSub_32x32_keep32_R(int32_t a, int32_t x, int32_t y) -{ - __ASM volatile("muls.s32.rhs %0, %1, %2\n\t" - :"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y)); - return a; -} - -/* SMMULR */ -__ALWAYS_STATIC_INLINE int32_t mult_32x32_keep32_R(int32_t x, int32_t y) -{ - int32_t a; - __ASM volatile("mul.s32.rh %0, %1, %2\n\t" - :"=r" (a), "=r" (x), "=r" (y): "1" (x), "2" (y)); - return a; -} - -/* SMMLA */ -__ALWAYS_STATIC_INLINE int32_t multAcc_32x32_keep32(int32_t a, int32_t x, int32_t y) -{ - __ASM volatile("mula.s32.hs %0, %1, %2\n\t" - :"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y)); - return a; -} - -/* SMMLS */ -__ALWAYS_STATIC_INLINE int32_t multSub_32x32_keep32(int32_t a, int32_t x, int32_t y) -{ - __ASM volatile("muls.s32.hs %0, %1, %2\n\t" - :"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y)); - return a; -} - -/* SMMUL */ -__ALWAYS_STATIC_INLINE int32_t mult_32x32_keep32(int32_t x, int32_t y) -{ - int32_t a; - __ASM volatile("mul.s32.h %0, %1, %2\n\t" - :"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y)); - return a; -} - -__ALWAYS_STATIC_INLINE int32_t multAcc_16x16_keep32(int32_t a, int16_t x, int16_t y) -{ - __ASM volatile("mulall.s16 %0, %1, %2\n\t" - :"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y)); - return a; -} - -__ALWAYS_STATIC_INLINE int64_t multAcc_16x16_keep64(int64_t a, int16_t x, int16_t y) -{ - __ASM volatile("mulall.s16.e %0, %1, %2\n\t" - :"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y)); - return a; -} - -__ALWAYS_STATIC_INLINE int64_t mult_32x32_keep64(int32_t x, int32_t y) -{ - int64_t a; - __ASM volatile("mul.s32 %0, %1, %2\n\t" - :"=r" (a), "=r" (x), "=r" (y): "1" (x), "2" (y)); - return a; -} - -__ALWAYS_STATIC_INLINE int64_t multAcc_32x32_keep64(int64_t a, int32_t x, int32_t y) -{ - __ASM volatile("mula.s32 %0, %1, %2\n\t" - :"=r" (a), "=r" (x), "=r" (y): "0" (a), "1" (x), "2" (y)); - return a; -} - -__ALWAYS_STATIC_INLINE int32_t mult_32x32_dext_31(int32_t x, int32_t y) -{ - int64_t tmp1; - int32_t tmp2; - __ASM volatile("mul.s32 %0, %1, %2\n\t" - "dexti %3, %0, %R0, 31" - :"=r" (tmp1), "=r" (x), "=r" (y), "=r" (tmp2): "1" (x), "2" (y)); - return tmp2; -} - -__ALWAYS_STATIC_INLINE int32_t mult_32x32_dext_30(int32_t x, int32_t y) -{ - int64_t tmp1; - int32_t tmp2; - __ASM volatile("mul.s32 %0, %1, %2\n\t" - "dexti %3, %0, %R0, 30" - :"=r" (tmp1), "=r" (x), "=r" (y), "=r" (tmp2): "1" (x), "2" (y)); - return tmp2; -} - -__ALWAYS_STATIC_INLINE int32_t mult_32x32_dext_4(int32_t x, int32_t y) -{ - int64_t tmp1; - int32_t tmp2; - __ASM volatile("mul.s32 %0, %1, %2\n\t" - "dexti %3, %0, %R0, 4" - :"=r" (tmp1), "=r" (x), "=r" (y), "=r" (tmp2): "1" (x), "2" (y)); - return tmp2; -} - -__ALWAYS_STATIC_INLINE int32_t mult_32x32_dext_33(int32_t x, int32_t y) -{ - int64_t tmp1; - int32_t tmp2; - __ASM volatile("mul.s32 %0, %1, %2\n\t" - "asri %3, %R0, 1" - :"=r" (tmp1), "=r" (x), "=r" (y), "=r" (tmp2): "1" (x), "2" (y)); - return tmp2; -} - -__ALWAYS_STATIC_INLINE int32_t dext_31(int64_t x) -{ - int32_t tmp1; - __ASM volatile( - "dexti %0, %1, %R1, 31" - :"=r" (tmp1), "=r" (x) : "1" (x)); - return tmp1; -} - -__ALWAYS_STATIC_INLINE int32_t mult_l16xl16_keep32(int32_t x, int32_t y) -{ - int32_t a; - __ASM volatile("mulll.s16 %0, %1, %2\n\t" - :"=r" (a), "=r" (x), "=r" (y): "1" (x), "2" (y)); - return a; -} - -__ALWAYS_STATIC_INLINE int32_t mult_h16xl16_keep32(int32_t x, int32_t y) -{ - int32_t a; - __ASM volatile("mulhl.s16 %0, %1, %2\n\t" - :"=r" (a), "=r" (x), "=r" (y): "1" (x), "2" (y)); - return a; -} - -__ALWAYS_STATIC_INLINE int32_t mult_h16xh16_keep32(int32_t x, int32_t y) -{ - int32_t a; - __ASM volatile("mulhh.s16 %0, %1, %2\n\t" - :"=r" (a), "=r" (x), "=r" (y): "1" (x), "2" (y)); - return a; -} - -#endif - - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - CSKY_MATH_SUCCESS = 0, /**< No error */ - CSKY_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - CSKY_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - CSKY_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - CSKY_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - CSKY_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - CSKY_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } csky_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief 32-bit fractional complex data type in 1.31 format. - */ - typedef struct - { - q31_t re; - q31_t im; - } cq31_t; - /** - * @brief 16-bit fractional complex data type in 1.15 format. - */ - typedef struct - { - q15_t re; - q15_t im; - } cq15_t; - /** - * @brief definition to read/write two 16 bit values. - */ - #define __SIMD32_TYPE int32_t - #define CSI_UNUSED __attribute__((unused)) - -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) -#define __SIMD64(addr) (*(int64_t **) & (addr)) - -#if defined (CSKY_MATH_NO_SIMD) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -#endif - - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef CSKY_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - /** - * @brief Clips Q63 to Q31 values. - */ - static __INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } csky_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } csky_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } csky_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } csky_fir_instance_f32; - - void csky_fir_q7( - const csky_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - void csky_fir_init_q7( - csky_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - void csky_fir_q15( - const csky_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - void csky_fir_fast_q15( - const csky_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - csky_status csky_fir_init_q15( - csky_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - void csky_fir_q31( - const csky_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - void csky_fir_fast_q31( - const csky_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - void csky_fir_init_q31( - csky_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - void csky_fir_f32( - const csky_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - void csky_fir_init_f32( - csky_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } csky_biquad_casd_df1_inst_q15; - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } csky_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - } csky_biquad_casd_df1_inst_f32; - - void csky_biquad_cascade_df1_q15( - const csky_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - void csky_biquad_cascade_df1_init_q15( - csky_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - void csky_biquad_cascade_df1_fast_q15( - const csky_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - void csky_biquad_cascade_df1_q31( - const csky_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - void csky_biquad_cascade_df1_fast_q31( - const csky_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - void csky_biquad_cascade_df1_init_q31( - csky_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - void csky_biquad_cascade_df1_f32( - const csky_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - void csky_biquad_cascade_df1_init_f32( - csky_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } csky_matrix_instance_f32; - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float64_t *pData; /**< points to the data of the matrix. */ - } csky_matrix_instance_f64; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - } csky_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - } csky_matrix_instance_q31; - - csky_status csky_mat_add_f32( - const csky_matrix_instance_f32 * pSrcA, - const csky_matrix_instance_f32 * pSrcB, - csky_matrix_instance_f32 * pDst); - - csky_status csky_mat_add_q15( - const csky_matrix_instance_q15 * pSrcA, - const csky_matrix_instance_q15 * pSrcB, - csky_matrix_instance_q15 * pDst); - - csky_status csky_mat_add_q31( - const csky_matrix_instance_q31 * pSrcA, - const csky_matrix_instance_q31 * pSrcB, - csky_matrix_instance_q31 * pDst); - - csky_status csky_mat_cmplx_mult_f32( - const csky_matrix_instance_f32 * pSrcA, - const csky_matrix_instance_f32 * pSrcB, - csky_matrix_instance_f32 * pDst); - - csky_status csky_mat_cmplx_mult_q15( - const csky_matrix_instance_q15 * pSrcA, - const csky_matrix_instance_q15 * pSrcB, - csky_matrix_instance_q15 * pDst); - - csky_status csky_mat_cmplx_mult_q31( - const csky_matrix_instance_q31 * pSrcA, - const csky_matrix_instance_q31 * pSrcB, - csky_matrix_instance_q31 * pDst); - - csky_status csky_mat_trans_f32( - const csky_matrix_instance_f32 * pSrc, - csky_matrix_instance_f32 * pDst); - - csky_status csky_mat_trans_q15( - const csky_matrix_instance_q15 * pSrc, - csky_matrix_instance_q15 * pDst); - - csky_status csky_mat_trans_q31( - const csky_matrix_instance_q31 * pSrc, - csky_matrix_instance_q31 * pDst); - - csky_status csky_mat_mult_f32( - const csky_matrix_instance_f32 * pSrcA, - const csky_matrix_instance_f32 * pSrcB, - csky_matrix_instance_f32 * pDst); - - csky_status csky_mat_mult_q15( - const csky_matrix_instance_q15 * pSrcA, - const csky_matrix_instance_q15 * pSrcB, - csky_matrix_instance_q15 * pDst); - - csky_status csky_mat_mult_fast_q15( - const csky_matrix_instance_q15 * pSrcA, - const csky_matrix_instance_q15 * pSrcB, - csky_matrix_instance_q15 * pDst); - - csky_status csky_mat_mult_q31( - const csky_matrix_instance_q31 * pSrcA, - const csky_matrix_instance_q31 * pSrcB, - csky_matrix_instance_q31 * pDst); - - csky_status csky_mat_mult_trans_q31( - const csky_matrix_instance_q31 * pSrcA, - const csky_matrix_instance_q31 * pSrcB, - csky_matrix_instance_q31 * pDst); - - csky_status csky_mat_mult_fast_q31( - const csky_matrix_instance_q31 * pSrcA, - const csky_matrix_instance_q31 * pSrcB, - csky_matrix_instance_q31 * pDst); - - csky_status csky_mat_sub_f32( - const csky_matrix_instance_f32 * pSrcA, - const csky_matrix_instance_f32 * pSrcB, - csky_matrix_instance_f32 * pDst); - - csky_status csky_mat_sub_q15( - const csky_matrix_instance_q15 * pSrcA, - const csky_matrix_instance_q15 * pSrcB, - csky_matrix_instance_q15 * pDst); - - csky_status csky_mat_sub_q31( - const csky_matrix_instance_q31 * pSrcA, - const csky_matrix_instance_q31 * pSrcB, - csky_matrix_instance_q31 * pDst); - - csky_status csky_mat_scale_f32( - const csky_matrix_instance_f32 * pSrc, - float32_t scale, - csky_matrix_instance_f32 * pDst); - - csky_status csky_mat_scale_q15( - const csky_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - csky_matrix_instance_q15 * pDst); - - csky_status csky_mat_scale_q31( - const csky_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - csky_matrix_instance_q31 * pDst); - - void csky_mat_init_q31( - csky_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - - void csky_mat_init_q15( - csky_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - - void csky_mat_init_f32( - csky_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q15_t A1; - q15_t A2; - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } csky_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - } csky_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } csky_pid_instance_f32; - - void csky_pid_init_f32( - csky_pid_instance_f32 * S, - int32_t resetStateFlag); - - void csky_pid_reset_f32( - csky_pid_instance_f32 * S); - - void csky_pid_init_q31( - csky_pid_instance_q31 * S, - int32_t resetStateFlag); - - void csky_pid_reset_q31( - csky_pid_instance_q31 * S); - - void csky_pid_init_q15( - csky_pid_instance_q15 * S, - int32_t resetStateFlag); - - void csky_pid_reset_q15( - csky_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } csky_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } csky_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } csky_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } csky_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } csky_bilinear_interp_instance_q7; - - void csky_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - void csky_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - void csky_mult_rnd_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - void csky_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - void csky_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } csky_cfft_radix2_instance_q15; - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } csky_cfft_radix4_instance_q15; - - /** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } csky_cfft_radix2_instance_q31; - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } csky_cfft_radix4_instance_q31; - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } csky_cfft_radix2_instance_f32; - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } csky_cfft_radix4_instance_f32; - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } csky_cfft_instance_q15; - -void csky_cfft_q15( - const csky_cfft_instance_q15 * S, - q15_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } csky_cfft_instance_q31; - -void csky_cfft_q31( - const csky_cfft_instance_q31 * S, - q31_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } csky_cfft_instance_f32; - - void csky_cfft_f32( - const csky_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - const csky_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } csky_rfft_instance_q15; - - csky_status csky_rfft_init_q15( - csky_rfft_instance_q15 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void csky_rfft_q15( - const csky_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - const csky_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } csky_rfft_instance_q31; - - csky_status csky_rfft_init_q31( - csky_rfft_instance_q31 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void csky_rfft_q31( - const csky_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - csky_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } csky_rfft_instance_f32; - - csky_status csky_rfft_init_f32( - csky_rfft_instance_f32 * S, - csky_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void csky_rfft_f32( - const csky_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ -typedef struct - { - csky_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } csky_rfft_fast_instance_f32 ; - -csky_status csky_rfft_fast_init_f32 ( - csky_rfft_fast_instance_f32 * S, - uint16_t fftLen); - -void csky_rfft_fast_f32( - csky_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - csky_rfft_fast_instance_f32 *pRfft; /**< points to the real FFT fast instance. */ - csky_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } csky_dct4_instance_f32; - - csky_status csky_dct4_init_f32( - csky_dct4_instance_f32 * S, - csky_rfft_fast_instance_f32 * S_RFFT, - csky_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - void csky_dct4_f32( - const csky_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - csky_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - csky_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } csky_dct4_instance_q31; - - csky_status csky_dct4_init_q31( - csky_dct4_instance_q31 * S, - csky_rfft_instance_q31 * S_RFFT, - csky_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - void csky_dct4_q31( - const csky_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - csky_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - csky_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } csky_dct4_instance_q15; - - csky_status csky_dct4_init_q15( - csky_dct4_instance_q15 * S, - csky_rfft_instance_q15 * S_RFFT, - csky_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - void csky_dct4_q15( - const csky_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - void csky_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - void csky_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - void csky_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - void csky_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - void csky_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - void csky_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - void csky_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - void csky_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - void csky_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - void csky_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - void csky_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - void csky_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - void csky_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - void csky_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - void csky_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - void csky_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - void csky_abs_max_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - void csky_abs_max_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - void csky_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - void csky_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - void csky_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - void csky_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - void csky_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - void csky_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - void csky_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - void csky_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - void csky_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - void csky_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - void csky_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - void csky_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - void csky_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - void csky_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - void csky_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - void csky_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - void csky_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - void csky_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - void csky_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - void csky_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - void csky_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - void csky_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - void csky_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - - void csky_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - void csky_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - void csky_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - void csky_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - void csky_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - void csky_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - void csky_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - void csky_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - void csky_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - csky_status csky_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - csky_status csky_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - csky_status csky_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - csky_status csky_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - csky_status csky_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - csky_status csky_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - csky_status csky_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - csky_status csky_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - csky_status csky_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * functions for the yunVoice functions. - */ - q15_t csky_dsp_lib_vec_max_abs16( - q15_t * A, - uint32_t N); - - q31_t csky_dsp_lib_vec_max_abs32( - q31_t * A, - uint32_t N); - - void csky_dsp_lib_vec_abs16( - q15_t * A, - uint32_t N, - q15_t * C); - - void csky_dsp_lib_vec_abs32( - q31_t * A, - uint32_t N, - q31_t * C); - - void csky_dsp_lib_vec_add16( - q15_t * A, - q15_t * B, - uint32_t N, - q15_t * C); - - void csky_dsp_lib_vec_add32( - q31_t * A, - q31_t * B, - uint32_t N, - q31_t * C); - - void csky_dsp_lib_vec_cx_conj_q15( - q15_t * A, - uint32_t N, - q15_t * B); - - void csky_dsp_lib_vec_cx_conj_q31( - q31_t * A, - uint32_t N, - q31_t * C); - - q31_t csky_dsp_lib_vec_dot_q15( - q15_t * A, - q15_t * B, - uint32_t N); - - q31_t csky_dsp_lib_vec_dot_q31( - q31_t * A, - q31_t * B, - uint32_t N); - - void csky_dsp_lib_mat_cx_add16( - cq15_t * A, - cq15_t * B, - uint32_t N, - uint32_t M, - cq15_t * C); - - void csky_dsp_lib_mat_cx_add32( - cq31_t * A, - cq31_t * B, - uint32_t N, - uint32_t M, - cq31_t * C); - - void csky_dsp_lib_mat_cx_mul_q15( - cq15_t * A, - cq15_t * B, - uint32_t N, - uint32_t M, - uint32_t L, - cq15_t * C); - - void csky_dsp_lib_mat_cx_mul_q31( - cq31_t * A, - cq31_t * B, - uint32_t N, - uint32_t M, - uint32_t L, - cq31_t * C); - - void csky_dsp_lib_mat_cx_sub16( - cq15_t * A, - cq15_t * B, - uint32_t N, - uint32_t M, - cq15_t * C); - - void csky_dsp_lib_mat_cx_sub32( - cq31_t * A, - cq31_t * B, - uint32_t N, - uint32_t M, - cq31_t * C); - - void csky_dsp_lib_vec_mul_q15( - q15_t * A, - q15_t * B, - uint32_t N, - q15_t * C); - - void csky_dsp_lib_vec_mul_q31( - q31_t * A, - q31_t * B, - uint32_t N, - q31_t * C); - - q31_t csky_dsp_lib_pow_int32( - q31_t arg_in_x, - q15_t arg_exp_in_x, - q31_t arg_in_y, - q15_t arg_exp_in_y, - q31_t *arg_exp_out); - - void csky_dsp_lib_vec_scale_q15( - q15_t * A, - q15_t scaleFract, - int8_t shift, - q15_t * B, - uint32_t N); - - void csky_dsp_lib_vec_scale_q31( - q31_t * A, - q31_t scaleFract, - int8_t shift, - q31_t * B, - uint32_t N); - - void csky_dsp_lib_vec_shf16( - q15_t * A, - int8_t shift_val, - uint32_t N, - q15_t * C); - - void csky_dsp_lib_vec_shf32( - q31_t * A, - q31_t shift_val, - uint32_t N, - q31_t * C); - - q15_t csky_dsp_lib_sqrt_int32( - q31_t x, - uint32_t rnd_flag); - - void csky_dsp_lib_vec_sub16( - q15_t * A, - q15_t * B, - uint32_t N, - q15_t * C); - - void csky_dsp_lib_vec_sub32( - q31_t * A, - q31_t * B, - uint32_t N, - q31_t * C); - - q63_t csky_dsp_lib_vec_sum16( - q15_t * A, - uint32_t N); - - q63_t csky_dsp_lib_vec_sum32( - q31_t * A, - uint32_t N); - - void csky_fft_lib_cx16_fft( - q31_t log2_buf_len, - q15_t * in_buf, - q15_t * out_buf, - const q15_t * twi_table, - const uint16_t * bitrev_tbl, - q15_t * temp_buf, - q7_t * ScaleShift, - q31_t br); - - void csky_fft_lib_cx32_fft( - q31_t log2_buf_len, - q31_t * in_buf, - q31_t * out_buf, - const q31_t * twi_table, - const uint16_t * bitrev_tbl, - q31_t * temp_buf, - q31_t br); - - void csky_fft_lib_cx16_ifft( - q31_t log2_buf_len, - q15_t * in_buf, - q15_t * out_buf, - const q15_t * twi_table, - const uint16_t * bitrev_tbl, - q15_t * temp_buf, - q7_t * ScaleShift, - q31_t br); - - void csky_fft_lib_cx32_ifft( - q31_t log2_buf_len, - q31_t * in_buf, - q31_t * out_buf, - const q31_t * twi_table, - const uint16_t * bitrev_tbl, - q31_t * temp_buf, - q31_t br); - - void csky_fft_lib_int16_fft( - q31_t log2_buf_len, - q15_t * in_buf, - q15_t * out_buf, - const q15_t * twi_table, - const q15_t * last_stage_twi_table, - const uint16_t * bitrev_tbl, - q15_t * temp_buf, - q7_t * ScaleShift, - q31_t br); - - void csky_fft_lib_int32_fft( - q31_t log2_buf_len, - q31_t * in_buf, - q31_t * out_buf, - const q31_t * twi_table, - const q31_t * last_stage_twi_table, - const uint16_t * bitrev_tbl, - q31_t * temp_buf, - q31_t br); - - void csky_fft_lib_int16_ifft( - q31_t log2_buf_len, - q15_t * in_buf, - q15_t * out_buf, - const q15_t * twi_table, - const q15_t * last_stage_twi_table, - const uint16_t * bitrev_tbl, - q15_t * temp_buf, - q7_t * ScaleShift, - q31_t br); - - void csky_fft_lib_int32_ifft( - q31_t log2_buf_len, - q31_t * in_buf, - q31_t * out_buf, - const q31_t * twi_table, - const q31_t * last_stage_twi_table, - const uint16_t * bitrev_tbl, - q31_t * temp_buf, - q31_t br); - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } csky_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } csky_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } csky_fir_decimate_instance_f32; - - void csky_fir_decimate_f32( - const csky_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - csky_status csky_fir_decimate_init_f32( - csky_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - void csky_fir_decimate_q15( - const csky_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - void csky_fir_decimate_fast_q15( - const csky_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - csky_status csky_fir_decimate_init_q15( - csky_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - void csky_fir_decimate_q31( - const csky_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - void csky_fir_decimate_fast_q31( - csky_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - csky_status csky_fir_decimate_init_q31( - csky_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } csky_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } csky_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } csky_fir_interpolate_instance_f32; - - void csky_fir_interpolate_q15( - const csky_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - csky_status csky_fir_interpolate_init_q15( - csky_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - void csky_fir_interpolate_q31( - const csky_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - csky_status csky_fir_interpolate_init_q31( - csky_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - void csky_fir_interpolate_f32( - const csky_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - csky_status csky_fir_interpolate_init_f32( - csky_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - } csky_biquad_cas_df1_32x64_ins_q31; - - void csky_biquad_cas_df1_32x64_q31( - const csky_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - void csky_biquad_cas_df1_32x64_init_q31( - csky_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } csky_biquad_cascade_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } csky_biquad_cascade_stereo_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } csky_biquad_cascade_df2T_instance_f64; - - void csky_biquad_cascade_df2T_f32( - const csky_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - void csky_biquad_cascade_stereo_df2T_f32( - const csky_biquad_cascade_stereo_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - void csky_biquad_cascade_df2T_f64( - const csky_biquad_cascade_df2T_instance_f64 * S, - float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); - - void csky_biquad_cascade_df2T_init_f32( - csky_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - void csky_biquad_cascade_stereo_df2T_init_f32( - csky_biquad_cascade_stereo_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - void csky_biquad_cascade_df2T_init_f64( - csky_biquad_cascade_df2T_instance_f64 * S, - uint8_t numStages, - float64_t * pCoeffs, - float64_t * pState); - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } csky_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } csky_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } csky_fir_lattice_instance_f32; - - void csky_fir_lattice_init_q15( - csky_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - void csky_fir_lattice_q15( - const csky_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - void csky_fir_lattice_init_q31( - csky_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - void csky_fir_lattice_q31( - const csky_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - void csky_fir_lattice_init_f32( - csky_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - void csky_fir_lattice_f32( - const csky_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } csky_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } csky_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } csky_iir_lattice_instance_f32; - - void csky_iir_lattice_f32( - const csky_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - void csky_iir_lattice_init_f32( - csky_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - - void csky_iir_lattice_q31( - const csky_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - void csky_iir_lattice_init_q31( - csky_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); - - void csky_iir_lattice_q15( - const csky_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - void csky_iir_lattice_init_q15( - csky_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } csky_lms_instance_f32; - - void csky_lms_f32( - const csky_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - void csky_lms_init_f32( - csky_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } csky_lms_instance_q15; - - void csky_lms_init_q15( - csky_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - void csky_lms_q15( - const csky_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } csky_lms_instance_q31; - - void csky_lms_q31( - const csky_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - void csky_lms_init_q31( - csky_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } csky_lms_norm_instance_f32; - - void csky_lms_norm_f32( - csky_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - void csky_lms_norm_init_f32( - csky_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } csky_lms_norm_instance_q31; - - void csky_lms_norm_q31( - csky_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - void csky_lms_norm_init_q31( - csky_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } csky_lms_norm_instance_q15; - - void csky_lms_norm_q15( - csky_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - void csky_lms_norm_init_q15( - csky_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - void csky_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - void csky_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - void csky_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - void csky_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - void csky_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - void csky_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - void csky_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - void csky_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - void csky_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } csky_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } csky_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } csky_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } csky_fir_sparse_instance_q7; - - void csky_fir_sparse_f32( - csky_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - void csky_fir_sparse_init_f32( - csky_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - void csky_fir_sparse_q31( - csky_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - void csky_fir_sparse_init_q31( - csky_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - void csky_fir_sparse_q15( - csky_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - void csky_fir_sparse_init_q15( - csky_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - void csky_fir_sparse_q7( - csky_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - void csky_fir_sparse_init_q7( - csky_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - void csky_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCosVal); - - void csky_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - - void csky_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - void csky_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - void csky_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - void csky_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - void csky_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - void csky_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - void csky_vsqrt_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - void csky_vsqrt_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - void csky_vsqrt_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t numSamples); - -/** - * @ingroup groupController - */ - -/** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
- *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
- *    A0 = Kp + Ki + Kd
- *    A1 = (-Kp ) - (2 * Kd )
- *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - -/** - * @addtogroup PID - * @{ - */ - -/** - * @brief Process function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - __ALWAYS_STATIC_INLINE float32_t csky_pid_f32( - csky_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - -/** - * @} -*/ // end of PID group - - -/** - * @addtogroup PID - * @{ - */ - -/** - * @brief Process function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - __ALWAYS_STATIC_INLINE q31_t csky_pid_q31( - csky_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - #ifdef CSKY_SIMD - /* acc = A0 * x[n] */ - acc = mult_32x32_keep64(S->A0, in); - - /* acc += A1 * x[n-1] */ - acc = multAcc_32x32_keep64(acc, S->A1, S->state[0]); - - /* acc += A2 * x[n-2] */ - acc = multAcc_32x32_keep64(acc, S->A2, S->state[1]); - - /* convert output to 1.31 format to add y[n-1] */ - out = dext_31(acc); - #else - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - #endif - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - -/** - * @} - */ // end of PID group - -/** - * @addtogroup PID - * @{ - */ -/** - * @brief Process function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - __ALWAYS_STATIC_INLINE q15_t csky_pid_q15( - csky_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT_16((acc >> 15))); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } -/** - * @} - */ // end of PID group - - csky_status csky_mat_inverse_f32( - const csky_matrix_instance_f32 * src, - csky_matrix_instance_f32 * dst); - - csky_status csky_mat_inverse_f64( - const csky_matrix_instance_f64 * src, - csky_matrix_instance_f64 * dst); - -/** - * @ingroup groupController - */ - -/** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - -/** - * @addtogroup clarke - * @{ - */ - -/** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - */ - __ALWAYS_STATIC_INLINE void csky_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - } - -/** - * @} - */ // end of clarke group - - -/** - * @addtogroup clarke - * @{ - */ - -/** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - __ALWAYS_STATIC_INLINE void csky_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - #ifdef CSKY_SIMD - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = mult_32x32_dext_30(Ia, 0x24F34E8B); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = mult_32x32_dext_30(Ib, 0x49E69D16); - #else - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - #endif - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - -/** - * @} - */ // end of clarke group - - void csky_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - -/** - * @ingroup groupController - */ -/** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - -/** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - */ - __ALWAYS_STATIC_INLINE void csky_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; - } - - -/** - * @} - */ // end of inv_clarke group - -/** - * @addtogroup inv_clarke - * @{ - */ - -/** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - __ALWAYS_STATIC_INLINE void csky_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - #ifdef CSKY_SIMD - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = mult_32x32_dext_31(Ialpha, 0x40000000); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = mult_32x32_dext_31(Ibeta, 0x6ED9EBA1); - #else - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - #endif - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - } - -/** - * @} - */ // end of inv_clarke group - - void csky_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - -/** - * @ingroup groupController - */ -/** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ -/** - * @addtogroup park - * @{ - */ -/** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * The function implements the forward Park transform. - * - */ - __ALWAYS_STATIC_INLINE void csky_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) -{ - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; -} -/** - * @} - */ // end of park group - -/** - * @addtogroup park - * @{ - */ -/** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - __ALWAYS_STATIC_INLINE void csky_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) -{ -#ifdef CSKY_SIMD - __ASM volatile( - "rmul.s32.h t0, %0, %3\n\t" - "rmul.s32.h t1, %1, %2\n\t" - "add.s32.s t0, t0, t1\n\t" - "st.w t0, (%4, 0x0)\n\t" - "rmul.s32.h t0, %0, %2\n\t" - "rmul.s32.h t1, %1, %3\n\t" - "sub.s32.s t1, t1, t0\n\t" - "st.w t1, (%5, 0x0)\n\t" - ::"r"(Ialpha),"r"(Ibeta),"r"(sinVal),"r"(cosVal),"r"(pId),"r"(pIq) - :"t0","t1", "memory"); -#else - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = clip_q63_to_q31 (((q63_t) (Ialpha) * (cosVal)) >> 31); - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = clip_q63_to_q31 (((q63_t) (Ibeta) * (sinVal)) >> 31); - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = clip_q63_to_q31 (((q63_t) (Ialpha) * (sinVal)) >> 31); - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = clip_q63_to_q31 (((q63_t) (Ibeta) * (cosVal)) >> 31); - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); -#endif -} -/** - * @} - */ // end of park group - - void csky_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - -/** - * @ingroup groupController - */ -/** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ -/** - * @addtogroup inv_park - * @{ - */ - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - */ - __ALWAYS_STATIC_INLINE void csky_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) -{ - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; -} -/** - * @} - */ // end of inv_park group - -/** - * @addtogroup inv_park - * @{ - */ -/** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - __ALWAYS_STATIC_INLINE void csky_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) -{ -#ifdef CSKY_SIMD - __ASM volatile( - "rmul.s32.h t0, %0, %3\n\t" - "rmul.s32.h t1, %1, %2\n\t" - "sub.s32.s t0, t0, t1\n\t" - "st.w t0, (%4, 0x0)\n\t" - "rmul.s32.h t0, %0, %2\n\t" - "rmul.s32.h t1, %1, %3\n\t" - "add.s32.s t0, t0, t1\n\t" - "st.w t0, (%5, 0x0)\n\t" - ::"r"(Id),"r"(Iq),"r"(sinVal),"r"(cosVal),"r"(pIalpha),"r"(pIbeta) - :"t0","t1", "memory"); - -#else - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = clip_q63_to_q31 (((q63_t) (Id) * (cosVal)) >> 31); - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = clip_q63_to_q31 (((q63_t) (Iq) * (sinVal)) >> 31); - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = clip_q63_to_q31 (((q63_t) (Id) * (sinVal)) >> 31); - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = clip_q63_to_q31 (((q63_t) (Iq) * (cosVal)) >> 31); - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); -#endif -} - -/** - * @} - */ // end of inv_park group - - void csky_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - -/** - * @ingroup groupInterpolation - */ -/** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
- *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
- *       where x0, x1 are nearest values of input x
- *             y0, y1 are nearest values to output y
- *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ -/** - * @addtogroup LinearInterpolate - * @{ - */ -/** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ -__ALWAYS_STATIC_INLINE float32_t csky_linear_interp_f32( -csky_linear_interp_instance_f32 * S, -float32_t x) -{ - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - if(i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if((uint32_t)i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - } - /* returns output value */ - return (y); -} -/** - * @} - */ // end of LinearInterpolate group - -/** - * @addtogroup LinearInterpolate - * @{ - */ - -/** - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ -__ALWAYS_STATIC_INLINE q31_t csky_linear_interp_q31( -q31_t * pYData, -q31_t x, -uint32_t nValues) -{ - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (q31_t)0xFFF00000) >> 20); - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; -#ifdef CSKY_SIMD - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = mult_32x32_keep32(y0, (0x7FFFFFFF - fract)); - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y = multAcc_32x32_keep32(y, y1, fract); -#else - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); -#endif - /* Convert y to 1.31 format */ - return (y << 1u); - } -} -/** - * @} - */ // end of LinearInterpolate group - -/** - * @addtogroup LinearInterpolate - * @{ - */ -/** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ -__ALWAYS_STATIC_INLINE q15_t csky_linear_interp_q15( -q15_t * pYData, -q31_t x, -uint32_t nValues) -{ - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (int32_t)0xFFF00000) >> 20); - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1]; -#ifdef CSKY_SIMD - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = mult_32x32_keep64(y0, (0xFFFFF - fract)); - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y = multAcc_32x32_keep64(y, y1, (fract)); -#else - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); -#endif - /* convert y to 1.15 format */ - return (q15_t) (y >> 20); - } -} -/** - * @} - */ // end of LinearInterpolate group - -/** - * @addtogroup LinearInterpolate - * @{ - */ -/** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ -__ALWAYS_STATIC_INLINE q7_t csky_linear_interp_q7( -q7_t * pYData, -q31_t x, -uint32_t nValues) -{ - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) - { - return (pYData[0]); - } - index = (x >> 20) & 0xfff; - if(index >= (nValues - 1)) - { - return (pYData[nValues - 1]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - /* convert y to 1.7(q7) format */ - return (q7_t) (y >> 20); - } -} -/** - * @} - */ // end of LinearInterpolate group - - float32_t csky_sin_f32( - float32_t x); - - q31_t csky_sin_q31( - q31_t x); - - q15_t csky_sin_q15( - q15_t x); - - float32_t csky_cos_f32( - float32_t x); - - q31_t csky_cos_q31( - q31_t x); - - q15_t csky_cos_q15( - q15_t x); - - csky_status csky_sqrt_f32( - float32_t in, - float32_t * pOut); - - csky_status csky_sqrt_q31( - q31_t in, - q31_t * pOut); - - csky_status csky_sqrt_q15( - q15_t in, - q15_t * pOut); - - void csky_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - void csky_power_int32( - int32_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - void csky_power_int32( - int32_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - void csky_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - void csky_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - void csky_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - void csky_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - void csky_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - void csky_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - void csky_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - void csky_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - void csky_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - void csky_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - void csky_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - void csky_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - void csky_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - void csky_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - void csky_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - void csky_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - void csky_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - void csky_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - void csky_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - void csky_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - void csky_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - void csky_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - void csky_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - void csky_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - void csky_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - void csky_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - void csky_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - void csky_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - void csky_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - void csky_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - - void csky_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - void csky_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - void csky_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - void csky_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - void csky_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - void csky_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - void csky_cmplx_mult_cmplx_re_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - void csky_cmplx_mult_cmplx_re_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - void csky_cmplx_mult_cmplx_re_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - - void csky_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - void csky_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - void csky_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - void csky_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - void csky_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - void csky_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - void csky_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - void csky_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - -/** - * @ingroup groupInterpolation - */ -/** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CSI DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
- *   typedef struct
- *   {
- *     uint16_t numRows;
- *     uint16_t numCols;
- *     float32_t *pData;
- * } csky_bilinear_interp_instance_f32;
- *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
- *     XF = floor(x)
- *     YF = floor(y)
- *
- * \par - * The interpolated output point is computed as: - * 
- *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
- *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
- *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
- *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
- *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ -/** - * @addtogroup BilinearInterpolate - * @{ - */ -/** -* -* @brief Floating-point bilinear interpolation. -* @param[in,out] S points to an instance of the interpolation structure. -* @param[in] X interpolation coordinate. -* @param[in] Y interpolation coordinate. -* @return out interpolated value. -*/ -__ALWAYS_STATIC_INLINE float32_t csky_bilinear_interp_f32( -const csky_bilinear_interp_instance_f32 * S, -float32_t X, -float32_t Y) -{ - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) - { - return (0); - } - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - /* return to application */ - return (out); -} -/** - * @} - */ // end of BilinearInterpolate group - -/** - * @addtogroup BilinearInterpolate - * @{ - */ -/** -* -* @brief Q31 bilinear interpolation. -* @param[in,out] S points to an instance of the interpolation structure. -* @param[in] X interpolation coordinate in 12.20 format. -* @param[in] Y interpolation coordinate in 12.20 format. -* @return out interpolated value. -*/ -__ALWAYS_STATIC_INLINE q31_t csky_bilinear_interp_q31( -csky_bilinear_interp_instance_q31 * S, -q31_t X, -q31_t Y) -{ - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; - x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; - y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; -#ifdef CSKY_SIMD - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = mult_32x32_keep32(x1, (0x7FFFFFFF - xfract)); - acc = mult_32x32_keep32(out, (0x7FFFFFFF - yfract)); - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = mult_32x32_keep32(x2, (0x7FFFFFFF - yfract)); - acc = multAcc_32x32_keep32(acc, out, xfract); - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = mult_32x32_keep32(y1, (0x7FFFFFFF - xfract)); - acc = multAcc_32x32_keep32(acc, out, yfract); - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = mult_32x32_keep32(y2, xfract); - acc = multAcc_32x32_keep32(acc, out, yfract); -#else - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); -#endif - /* Convert acc to 1.31(q31) format */ - return ((q31_t)(acc << 2)); -} -/** - * @} - */ // end of BilinearInterpolate group - -/** - * @addtogroup BilinearInterpolate - * @{ - */ -/** -* @brief Q15 bilinear interpolation. -* @param[in,out] S points to an instance of the interpolation structure. -* @param[in] X interpolation coordinate in 12.20 format. -* @param[in] Y interpolation coordinate in 12.20 format. -* @return out interpolated value. -*/ -__ALWAYS_STATIC_INLINE q15_t csky_bilinear_interp_q15( -csky_bilinear_interp_instance_q15 * S, -q31_t X, -q31_t Y) -{ - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ -#ifdef CSKY_SIMD - out = mult_32x32_dext_4(x1, (0xFFFFF - xfract)); - acc = mult_32x32_keep64(out, (0xFFFFF - yfract)); - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = mult_32x32_dext_4(x2, (0xFFFFF - yfract)); - acc = multAcc_32x32_keep64(acc, out, (xfract)); - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = mult_32x32_dext_4(y1, (0xFFFFF - xfract)); - acc = multAcc_32x32_keep64(acc, out, (yfract)); - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = mult_32x32_dext_4(y2, (xfract)); - acc = multAcc_32x32_keep64(acc, out, (yfract)); -#else - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); -#endif - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return ((q15_t)(acc >> 36)); -} -/** - * @} - */ // end of BilinearInterpolate group - -/** - * @addtogroup BilinearInterpolate - * @{ - */ -/** -* @brief Q7 bilinear interpolation. -* @param[in,out] S points to an instance of the interpolation structure. -* @param[in] X interpolation coordinate in 12.20 format. -* @param[in] Y interpolation coordinate in 12.20 format. -* @return out interpolated value. -*/ -__ALWAYS_STATIC_INLINE q7_t csky_bilinear_interp_q7( -csky_bilinear_interp_instance_q7 * S, -q31_t X, -q31_t Y) -{ - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & (q31_t)0x000FFFFF); - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & (q31_t)0x000FFFFF); - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); -#ifdef CSKY_SIMD - acc = multAcc_32x32_keep64(acc, out, (0xFFFFF - yfract)); - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc = multAcc_32x32_keep64(acc, out, xfract); - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc = multAcc_32x32_keep64(acc, out, yfract); - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc = multAcc_32x32_keep64(acc, out, xfract); -#else - acc = (((q63_t) out * (0xFFFFF - yfract))); - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); -#endif - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return ((q7_t)(acc >> 40)); -} -/** - * @} - */ // end of BilinearInterpolate group - -/** - * @ingroup groupMath - */ - -/** - * @defgroup ShiftRight Right Shift - * - * Shift the input value to right with appointed bits, its basic format is: - * 
- *     a = (a) >> (shift),   1 =< shift <= bitof(a) - 1.
- *
- * The basic format is only designed for q31. - * - * and the extended format should be rounding to +inf: - * 
- *     a = (a + (1<<(shift - 1)) >> (shift),   1 =< shift <= bitof(a) - 1.
- *
- * - * which are designed for q31, q31 positive and q63. - */ - -/** - * @addtogroup ShiftRight - * @{ - */ -/** - * @brief right shift Q31 version - * @param[in] a input value to be shift. - * @param[in] shift input positive value, the number of bits to be shift. - * @param[out] result the shifted a. - * - * Scaling and Overflow Behavior: - * \par - * The function is only used for right shift. So, the value of shift is - * between[1,31]. - */ - __ALWAYS_STATIC_INLINE q31_t csky_shr_q31( - q31_t a, - q31_t shift) -{ - q31_t res; -#ifdef CSKY_SIMD - __ASM volatile( - "asr %0, %1, %2\n\t" - :"=r"(res), "=r"(a),"=r"(shift):"0"(res), "1"(a), "2"(shift)); -#else - res = ((a) >> (shift)); -#endif - return res; -} - -#define SHR(a, shift) csky_shr_q31(a, shift) - -/** - * @} - */ // end of ShiftRight group - - -/** - * @addtogroup ShiftRight - * @{ - */ -/** - * @brief right shift Q31 version - * @param[in] a input value to be shift. - * @param[in] shift input positive value, the number of bits to be shift. - * @param[out] result the shifted a. - * - * Scaling and Overflow Behavior: - * \par - * The function is only used for right shift. So, the value of shift is - * between[1,31]. And the output value is rounding to +inf. - */ - __ALWAYS_STATIC_INLINE q31_t csky_pshr_q31( - q31_t a, - q31_t shift) -{ - q31_t res; -#ifdef CSKY_SIMD - __ASM volatile( - "asr.s32.r %0, %1, %2\n\t" - :"=r"(res), "=r"(a),"=r"(shift):"0"(res), "1"(a), "2"(shift)); -#else - res = (a >= 0?(SHR((a) + (1<<(shift - 1)), shift))\ - :(SHR((a) + ((1<>1) -1, shift))); -#endif - return res; -} - -/** - * @} - */ // end of ShiftRight group - - -/** - * @addtogroup ShiftRight - * @{ - */ -/** - * @brief right shift Q31 version - * @param[in] a input positive value to be shift. - * @param[in] shift input positive value, the number of bits to be shift. - * @param[out] result the shifted a. - * - * Scaling and Overflow Behavior: - * \par - * The function is only used for right shift. So, the value of shift is - * between[1,31]. And the output value is rounding to +inf. - */ - __ALWAYS_STATIC_INLINE q31_t csky_pshr_pos_q31( - q31_t a, - q31_t shift) -{ - q31_t res; -#ifdef CSKY_SIMD - __ASM volatile( - "asr.s32.r %0, %1, %2\n\t" - :"=r"(res), "=r"(a),"=r"(shift):"0"(res), "1"(a), "2"(shift)); -#else - res = SHR((a) + (1<<(shift - 1)), shift); -#endif - return res; -} - -/** - * @} - */ // end of ShiftRight group - - -/** - * @addtogroup ShiftRight - * @{ - */ -/** - * @brief right shift Q63 version - * @param[in] a input value to be shift. - * @param[in] shift input positive value, the number of bits to be shift. - * @param[out] result the shifted a. - * - * Scaling and Overflow Behavior: - * \par - * The function is only used for right shift. So, the value of shift is - * between[1,63]. And the output value is rounding to +inf. - */ - __ALWAYS_STATIC_INLINE q63_t csky_pshr_q63( - q63_t a, - q31_t shift) -{ - q63_t res; -#ifdef CSKY_SIMD - __ASM volatile( - "subi t0, %2, 1\n\t" - "cmphsi t0, 32\n\t" - "bt 1f\n\t" - "movi t1, 1\n\t" - "lsl t0, t1, t0\n\t" - "movi t1, 0\n\t" - "add.s64.s %1, %1, t0\n\t" - "dext %0, %1, %R1, %2\n\t" - "asr %R0, %R1, %2\n\t" - "br 2f\n\t" - "1:\n\t" - "subi %2, %2, 32\n\t" - "subi t0, t0, 32\n\t" - "movi t1, 1\n\t" - "lsl t1, t1, t0\n\t" - "add.s32.s %R1, %R1, t1\n\t" - "asr %0, %R1, %2\n\t" - "asri %R0, %R1, 31\n\t" - "2:\n\t" - :"=r"(res), "=r"(a),"=r"(shift):"0"(res), "1"(a), "2"(shift):"t0", "t1"); -#else - res = (a >= 0?(SHR((a) + ((q63_t)1<<(shift - 1)), shift))\ - :(SHR((a) + (((q63_t)1<>1) -1, shift))); -#endif - return res; -} - -/** - * @} - */ // end of ShiftRight group - -//#define SHR(a, shift) csky_shr_q31(a, shift) -#define PSHR(a, shift) csky_pshr_q31(a, shift) -#define PSHR_POSITIVE(a, shift) csky_pshr_pos_q31(a, shift) -#define PSHR64(a, shift) csky_pshr_q63(a, shift) - - -#ifdef CSKY_SIMD -#else -/* SMMLAR */ -#define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMLSR */ -#define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMULR */ -#define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) - -/* SMMLA */ -#define multAcc_32x32_keep32(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - -/* SMMLS */ -#define multSub_32x32_keep32(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -/* SMMUL */ -#define mult_32x32_keep32(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* _CSKY_MATH_H */ - -/** - * - * End of file. - */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_vdsp2_const_structs.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_vdsp2_const_structs.h deleted file mode 100644 index 618f5f92..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_vdsp2_const_structs.h +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Copyright (C) 2016-2019 C-SKY Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file csky_vdsp2_const_structs.h - * @brief This file has constant structs that are initialized for - * user convenience. For example, some can be given as - * arguments to the csky_vdsp2_cfft_f32() function. - * @version V1.0 - * @date 20. Dec 2016 - ******************************************************************************/ - -#ifndef _CSKY_CONST_STRUCTS_H -#define _CSKY_CONST_STRUCTS_H - -#include "csky_vdsp2_math.h" -#include "csky_common_tables.h" - - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_sR_f32_len16; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_sR_f32_len32; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_sR_f32_len64; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_sR_f32_len128; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_sR_f32_len256; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_sR_f32_len512; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_sR_f32_len1024; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_sR_f32_len2048; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_sR_f32_len4096; - - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_sR_f32_len16; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_sR_f32_len32; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_sR_f32_len64; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_sR_f32_len128; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_sR_f32_len256; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_sR_f32_len512; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_sR_f32_len1024; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_sR_f32_len2048; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_sR_f32_len4096; - - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_fast_sR_f32_len16; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_fast_sR_f32_len32; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_fast_sR_f32_len64; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_fast_sR_f32_len128; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_fast_sR_f32_len256; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_fast_sR_f32_len512; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_fast_sR_f32_len1024; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_fast_sR_f32_len2048; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix4_fast_sR_f32_len4096; - - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix2_sR_f32_len16; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix2_sR_f32_len32; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix2_sR_f32_len64; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix2_sR_f32_len128; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix2_sR_f32_len256; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix2_sR_f32_len512; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix2_sR_f32_len1024; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix2_sR_f32_len2048; - extern const csky_vdsp2_cfft_instance_f32 csky_vdsp2_cfft_radix2_sR_f32_len4096; - - extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_sR_q31_len16; - extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_sR_q31_len32; - extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_sR_q31_len64; - extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_sR_q31_len128; - extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_sR_q31_len256; - extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_sR_q31_len512; - extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_sR_q31_len1024; - extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_sR_q31_len2048; - extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_sR_q31_len4096; - - extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_sR_q15_len16; - extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_sR_q15_len32; - extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_sR_q15_len64; - extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_sR_q15_len128; - extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_sR_q15_len256; - extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_sR_q15_len512; - extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_sR_q15_len1024; - extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_sR_q15_len2048; - extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_sR_q15_len4096; - - extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_fast_sR_q15_len16; - extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_fast_sR_q15_len32; - extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_fast_sR_q15_len64; - extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_fast_sR_q15_len128; - extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_fast_sR_q15_len256; - extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_fast_sR_q15_len512; - extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_fast_sR_q15_len1024; - extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_fast_sR_q15_len2048; - extern const csky_vdsp2_cfft_instance_q15 csky_vdsp2_cfft_fast_sR_q15_len4096; - - extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_fast_sR_q31_len16; - extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_fast_sR_q31_len32; - extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_fast_sR_q31_len64; - extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_fast_sR_q31_len128; - extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_fast_sR_q31_len256; - extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_fast_sR_q31_len512; - extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_fast_sR_q31_len1024; - extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_fast_sR_q31_len2048; - extern const csky_vdsp2_cfft_instance_q31 csky_vdsp2_cfft_fast_sR_q31_len4096; - - extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_rfft_sR_q15_len32; - extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_rfft_sR_q15_len64; - extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_rfft_sR_q15_len128; - extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_rfft_sR_q15_len256; - extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_rfft_sR_q15_len512; - extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_rfft_sR_q15_len1024; - extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_rfft_sR_q15_len2048; - extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_rfft_sR_q15_len4096; - extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_rfft_sR_q15_len8192; - - - extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_inv_rfft_sR_q15_len32; - extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_inv_rfft_sR_q15_len64; - extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_inv_rfft_sR_q15_len128; - extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_inv_rfft_sR_q15_len256; - extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_inv_rfft_sR_q15_len512; - extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_inv_rfft_sR_q15_len1024; - extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_inv_rfft_sR_q15_len2048; - extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_inv_rfft_sR_q15_len4096; - extern csky_vdsp2_rfft_instance_q15 csky_vdsp2_inv_rfft_sR_q15_len8192; - - extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_rfft_fast_sR_q15_len32; - extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_rfft_fast_sR_q15_len64; - extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_rfft_fast_sR_q15_len128; - extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_rfft_fast_sR_q15_len256; - extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_rfft_fast_sR_q15_len512; - extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_rfft_fast_sR_q15_len1024; - extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_rfft_fast_sR_q15_len2048; - extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_rfft_fast_sR_q15_len4096; - extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_rfft_fast_sR_q15_len8192; - - - extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_inv_rfft_fast_sR_q15_len32; - extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_inv_rfft_fast_sR_q15_len64; - extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_inv_rfft_fast_sR_q15_len128; - extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_inv_rfft_fast_sR_q15_len256; - extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_inv_rfft_fast_sR_q15_len512; - extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_inv_rfft_fast_sR_q15_len1024; - extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_inv_rfft_fast_sR_q15_len2048; - extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_inv_rfft_fast_sR_q15_len4096; - extern csky_vdsp2_rfft_fast_instance_q15 csky_vdsp2_inv_rfft_fast_sR_q15_len8192; - - - extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_rfft_sR_q31_len32; - extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_rfft_sR_q31_len64; - extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_rfft_sR_q31_len128; - extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_rfft_sR_q31_len256; - extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_rfft_sR_q31_len512; - extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_rfft_sR_q31_len1024; - extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_rfft_sR_q31_len2048; - extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_rfft_sR_q31_len4096; - extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_rfft_sR_q31_len8192; - - extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_inv_rfft_sR_q31_len32; - extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_inv_rfft_sR_q31_len64; - extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_inv_rfft_sR_q31_len128; - extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_inv_rfft_sR_q31_len256; - extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_inv_rfft_sR_q31_len512; - extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_inv_rfft_sR_q31_len1024; - extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_inv_rfft_sR_q31_len2048; - extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_inv_rfft_sR_q31_len4096; - extern csky_vdsp2_rfft_instance_q31 csky_vdsp2_inv_rfft_sR_q31_len8192; - - extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_rfft_fast_sR_q31_len32; - extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_rfft_fast_sR_q31_len64; - extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_rfft_fast_sR_q31_len128; - extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_rfft_fast_sR_q31_len256; - extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_rfft_fast_sR_q31_len512; - extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_rfft_fast_sR_q31_len1024; - extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_rfft_fast_sR_q31_len2048; - extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_rfft_fast_sR_q31_len4096; - extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_rfft_fast_sR_q31_len8192; - - extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_inv_rfft_fast_sR_q31_len32; - extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_inv_rfft_fast_sR_q31_len64; - extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_inv_rfft_fast_sR_q31_len128; - extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_inv_rfft_fast_sR_q31_len256; - extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_inv_rfft_fast_sR_q31_len512; - extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_inv_rfft_fast_sR_q31_len1024; - extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_inv_rfft_fast_sR_q31_len2048; - extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_inv_rfft_fast_sR_q31_len4096; - extern csky_vdsp2_rfft_fast_instance_q31 csky_vdsp2_inv_rfft_fast_sR_q31_len8192; - - - extern csky_vdsp2_rfft_fast_instance_f32 csky_vdsp2_rfft_sR_f32_len32; - extern csky_vdsp2_rfft_fast_instance_f32 csky_vdsp2_rfft_sR_f32_len64; - extern csky_vdsp2_rfft_fast_instance_f32 csky_vdsp2_rfft_sR_f32_len128; - extern csky_vdsp2_rfft_fast_instance_f32 csky_vdsp2_rfft_sR_f32_len256; - extern csky_vdsp2_rfft_fast_instance_f32 csky_vdsp2_rfft_sR_f32_len512; - extern csky_vdsp2_rfft_fast_instance_f32 csky_vdsp2_rfft_sR_f32_len1024; - extern csky_vdsp2_rfft_fast_instance_f32 csky_vdsp2_rfft_sR_f32_len2048; - extern csky_vdsp2_rfft_fast_instance_f32 csky_vdsp2_rfft_sR_f32_len4096; - extern csky_vdsp2_rfft_fast_instance_f32 csky_vdsp2_rfft_sR_f32_len8192; - - extern csky_vdsp2_dct4_instance_q15 csky_vdsp2_dct4_sR_q15_len128; - extern csky_vdsp2_dct4_instance_q15 csky_vdsp2_dct4_sR_q15_len512; - extern csky_vdsp2_dct4_instance_q15 csky_vdsp2_dct4_sR_q15_len2048; - extern csky_vdsp2_dct4_instance_q15 csky_vdsp2_dct4_sR_q15_len8192; - - extern csky_vdsp2_dct4_instance_q31 csky_vdsp2_dct4_sR_q31_len128; - extern csky_vdsp2_dct4_instance_q31 csky_vdsp2_dct4_sR_q31_len512; - extern csky_vdsp2_dct4_instance_q31 csky_vdsp2_dct4_sR_q31_len2048; - extern csky_vdsp2_dct4_instance_q31 csky_vdsp2_dct4_sR_q31_len8192; - - extern csky_vdsp2_dct4_fast_instance_q15 csky_vdsp2_dct4_fast_sR_q15_len128; - extern csky_vdsp2_dct4_fast_instance_q15 csky_vdsp2_dct4_fast_sR_q15_len512; - extern csky_vdsp2_dct4_fast_instance_q15 csky_vdsp2_dct4_fast_sR_q15_len2048; - extern csky_vdsp2_dct4_fast_instance_q15 csky_vdsp2_dct4_fast_sR_q15_len8192; - - extern csky_vdsp2_dct4_fast_instance_q31 csky_vdsp2_dct4_fast_sR_q31_len128; - extern csky_vdsp2_dct4_fast_instance_q31 csky_vdsp2_dct4_fast_sR_q31_len512; - extern csky_vdsp2_dct4_fast_instance_q31 csky_vdsp2_dct4_fast_sR_q31_len2048; - extern csky_vdsp2_dct4_fast_instance_q31 csky_vdsp2_dct4_fast_sR_q31_len8192; - - extern csky_vdsp2_dct4_instance_f32 csky_vdsp2_dct4_sR_f32_len128; - extern csky_vdsp2_dct4_instance_f32 csky_vdsp2_dct4_sR_f32_len512; - extern csky_vdsp2_dct4_instance_f32 csky_vdsp2_dct4_sR_f32_len2048; - extern csky_vdsp2_dct4_instance_f32 csky_vdsp2_dct4_sR_f32_len8192; -#endif diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_vdsp2_math.h b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_vdsp2_math.h deleted file mode 100644 index 55ced0f4..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/include/dsp/csky_vdsp2_math.h +++ /dev/null @@ -1,2378 +0,0 @@ -/* - * Copyright (C) 2016-2019 C-SKY Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/****************************************************************************** - * @file csky_vdsp2_math.h - * @brief Public header file for CSI DSP Library. - * @version V1.0 - * @date 20. Dec 2016 - ******************************************************************************/ - -#ifndef _CSKY_VDSP2_MATH_H -#define _CSKY_VDSP2_MATH_H - -#include -#include - -#ifdef CSKY_VDSP2_MATH_DSP -#include "csi_core.h" -#endif - -#ifdef __cplusplus -extern "C" -{ -#endif - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - CSKY_VDSP2_MATH_SUCCESS = 0, /**< No error */ - CSKY_VDSP2_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - CSKY_VDSP2_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - CSKY_VDSP2_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - CSKY_VDSP2_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - CSKY_VDSP2_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - CSKY_VDSP2_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } csky_vdsp2_status; - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } csky_vdsp2_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } csky_vdsp2_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } csky_vdsp2_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } csky_vdsp2_fir_instance_f32; - - void csky_vdsp2_fir_q7( - const csky_vdsp2_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_fir_init_q7( - csky_vdsp2_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - void csky_vdsp2_fir_q15( - const csky_vdsp2_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_fir_fast_q15( - const csky_vdsp2_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - csky_vdsp2_status csky_vdsp2_fir_init_q15( - csky_vdsp2_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - void csky_vdsp2_fir_q31( - const csky_vdsp2_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_fir_fast_q31( - const csky_vdsp2_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_fir_init_q31( - csky_vdsp2_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - void csky_vdsp2_fir_f32( - const csky_vdsp2_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_fir_init_f32( - csky_vdsp2_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } csky_vdsp2_biquad_casd_df1_inst_q15; - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } csky_vdsp2_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - } csky_vdsp2_biquad_casd_df1_inst_f32; - - void csky_vdsp2_biquad_cascade_df1_q15( - const csky_vdsp2_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_biquad_cascade_df1_init_q15( - csky_vdsp2_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - void csky_vdsp2_biquad_cascade_df1_fast_q15( - const csky_vdsp2_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_biquad_cascade_df1_q31( - const csky_vdsp2_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_biquad_cascade_df1_fast_q31( - const csky_vdsp2_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_biquad_cascade_df1_init_q31( - csky_vdsp2_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - void csky_vdsp2_biquad_cascade_df1_f32( - const csky_vdsp2_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_biquad_cascade_df1_init_f32( - csky_vdsp2_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } csky_vdsp2_matrix_instance_f32; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - } csky_vdsp2_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - } csky_vdsp2_matrix_instance_q31; - - csky_vdsp2_status csky_vdsp2_mat_add_f32( - const csky_vdsp2_matrix_instance_f32 * pSrcA, - const csky_vdsp2_matrix_instance_f32 * pSrcB, - csky_vdsp2_matrix_instance_f32 * pDst); - - csky_vdsp2_status csky_vdsp2_mat_add_q15( - const csky_vdsp2_matrix_instance_q15 * pSrcA, - const csky_vdsp2_matrix_instance_q15 * pSrcB, - csky_vdsp2_matrix_instance_q15 * pDst); - - csky_vdsp2_status csky_vdsp2_mat_add_q31( - const csky_vdsp2_matrix_instance_q31 * pSrcA, - const csky_vdsp2_matrix_instance_q31 * pSrcB, - csky_vdsp2_matrix_instance_q31 * pDst); - - csky_vdsp2_status csky_vdsp2_mat_cmplx_mult_f32( - const csky_vdsp2_matrix_instance_f32 * pSrcA, - const csky_vdsp2_matrix_instance_f32 * pSrcB, - csky_vdsp2_matrix_instance_f32 * pDst); - - csky_vdsp2_status csky_vdsp2_mat_cmplx_mult_q15( - const csky_vdsp2_matrix_instance_q15 * pSrcA, - const csky_vdsp2_matrix_instance_q15 * pSrcB, - csky_vdsp2_matrix_instance_q15 * pDst); - - csky_vdsp2_status csky_vdsp2_mat_cmplx_mult_q31( - const csky_vdsp2_matrix_instance_q31 * pSrcA, - const csky_vdsp2_matrix_instance_q31 * pSrcB, - csky_vdsp2_matrix_instance_q31 * pDst); - - csky_vdsp2_status csky_vdsp2_mat_trans_f32( - const csky_vdsp2_matrix_instance_f32 * pSrc, - csky_vdsp2_matrix_instance_f32 * pDst); - - csky_vdsp2_status csky_vdsp2_mat_trans_q15( - const csky_vdsp2_matrix_instance_q15 * pSrc, - csky_vdsp2_matrix_instance_q15 * pDst); - - csky_vdsp2_status csky_vdsp2_mat_trans_q31( - const csky_vdsp2_matrix_instance_q31 * pSrc, - csky_vdsp2_matrix_instance_q31 * pDst); - - csky_vdsp2_status csky_vdsp2_mat_mult_f32( - const csky_vdsp2_matrix_instance_f32 * pSrcA, - const csky_vdsp2_matrix_instance_f32 * pSrcB, - csky_vdsp2_matrix_instance_f32 * pDst); - - csky_vdsp2_status csky_vdsp2_mat_mult_trans_f32( - const csky_vdsp2_matrix_instance_f32 * pSrcA, - const csky_vdsp2_matrix_instance_f32 * pSrcB, - csky_vdsp2_matrix_instance_f32 * pDst); - - csky_vdsp2_status csky_vdsp2_mat_mult_q15( - const csky_vdsp2_matrix_instance_q15 * pSrcA, - const csky_vdsp2_matrix_instance_q15 * pSrcB, - csky_vdsp2_matrix_instance_q15 * pDst); - - csky_vdsp2_status csky_vdsp2_mat_mult_trans_q15( - const csky_vdsp2_matrix_instance_q15 * pSrcA, - const csky_vdsp2_matrix_instance_q15 * pSrcB, - csky_vdsp2_matrix_instance_q15 * pDst); - - csky_vdsp2_status csky_vdsp2_mat_mult_q31( - const csky_vdsp2_matrix_instance_q31 * pSrcA, - const csky_vdsp2_matrix_instance_q31 * pSrcB, - csky_vdsp2_matrix_instance_q31 * pDst); - - csky_vdsp2_status csky_vdsp2_mat_mult_trans_q31( - const csky_vdsp2_matrix_instance_q31 * pSrcA, - const csky_vdsp2_matrix_instance_q31 * pSrcB, - csky_vdsp2_matrix_instance_q31 * pDst); - - csky_vdsp2_status csky_vdsp2_mat_sub_f32( - const csky_vdsp2_matrix_instance_f32 * pSrcA, - const csky_vdsp2_matrix_instance_f32 * pSrcB, - csky_vdsp2_matrix_instance_f32 * pDst); - - csky_vdsp2_status csky_vdsp2_mat_sub_q15( - const csky_vdsp2_matrix_instance_q15 * pSrcA, - const csky_vdsp2_matrix_instance_q15 * pSrcB, - csky_vdsp2_matrix_instance_q15 * pDst); - - csky_vdsp2_status csky_vdsp2_mat_sub_q31( - const csky_vdsp2_matrix_instance_q31 * pSrcA, - const csky_vdsp2_matrix_instance_q31 * pSrcB, - csky_vdsp2_matrix_instance_q31 * pDst); - - csky_vdsp2_status csky_vdsp2_mat_scale_f32( - const csky_vdsp2_matrix_instance_f32 * pSrc, - float32_t scale, - csky_vdsp2_matrix_instance_f32 * pDst); - - csky_vdsp2_status csky_vdsp2_mat_scale_q15( - const csky_vdsp2_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - csky_vdsp2_matrix_instance_q15 * pDst); - - csky_vdsp2_status csky_vdsp2_mat_scale_q31( - const csky_vdsp2_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - csky_vdsp2_matrix_instance_q31 * pDst); - - void csky_vdsp2_mat_init_q31( - csky_vdsp2_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - - void csky_vdsp2_mat_init_q15( - csky_vdsp2_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - - void csky_vdsp2_mat_init_f32( - csky_vdsp2_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - - void csky_vdsp2_mult_q15xq31_sht( - q15_t * pSrcA, - q31_t * pSrcB, - uint32_t shiftValue, - uint32_t blockSize); - - void csky_vdsp2_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_mult_rnd_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } csky_vdsp2_cfft_radix2_instance_q15; - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } csky_vdsp2_cfft_radix4_instance_q15; - - /** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } csky_vdsp2_cfft_radix2_instance_q31; - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } csky_vdsp2_cfft_radix4_instance_q31; - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } csky_vdsp2_cfft_radix2_instance_f32; - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } csky_vdsp2_cfft_radix4_instance_f32; - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } csky_vdsp2_cfft_instance_q15; - -void csky_vdsp2_cfft_q15( - const csky_vdsp2_cfft_instance_q15 * S, - q15_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -void csky_vdsp2_cfft_fast_q15( - const csky_vdsp2_cfft_instance_q15 * S, - q15_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } csky_vdsp2_cfft_instance_q31; - -void csky_vdsp2_cfft_q31( - const csky_vdsp2_cfft_instance_q31 * S, - q31_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -void csky_vdsp2_cfft_fast_q31( - const csky_vdsp2_cfft_instance_q31 * S, - q31_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } csky_vdsp2_cfft_instance_f32; - - void csky_vdsp2_cfft_f32( - const csky_vdsp2_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - const csky_vdsp2_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } csky_vdsp2_rfft_instance_q15; - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - q15_t *pTwiddleAReal; /**< points to the A real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the B real twiddle factor table. */ - const csky_vdsp2_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } csky_vdsp2_rfft_fast_instance_q15; - - csky_vdsp2_status csky_vdsp2_rfft_init_q15( - csky_vdsp2_rfft_instance_q15 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void csky_vdsp2_rfft_q15( - const csky_vdsp2_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - void csky_vdsp2_rfft_fast_q15( - const csky_vdsp2_rfft_fast_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - const csky_vdsp2_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } csky_vdsp2_rfft_instance_q31; - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - q31_t *pTwiddleAReal; /**< points to the A real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the B real twiddle factor table. */ - const csky_vdsp2_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } csky_vdsp2_rfft_fast_instance_q31; - - csky_vdsp2_status csky_vdsp2_rfft_init_q31( - csky_vdsp2_rfft_instance_q31 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void csky_vdsp2_rfft_q31( - const csky_vdsp2_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - void csky_vdsp2_rfft_fast_q31( - const csky_vdsp2_rfft_fast_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - csky_vdsp2_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } csky_vdsp2_rfft_instance_f32; - - csky_vdsp2_status csky_vdsp2_rfft_init_f32( - csky_vdsp2_rfft_instance_f32 * S, - csky_vdsp2_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void csky_vdsp2_cfft_radix4_f32( - const csky_vdsp2_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag, - float32_t onebyfftLen); - - void csky_vdsp2_cfft_fast_radix4_f32( - const csky_vdsp2_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag, - float32_t onebyfftLen); - - void csky_vdsp2_cfft_radix2_f32( - const csky_vdsp2_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag, - float32_t onebyfftLen); - - void csky_vdsp2_rfft_f32( - const csky_vdsp2_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ -typedef struct - { - csky_vdsp2_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } csky_vdsp2_rfft_fast_instance_f32 ; - -csky_vdsp2_status csky_vdsp2_rfft_fast_init_f32 ( - csky_vdsp2_rfft_fast_instance_f32 * S, - uint16_t fftLen); - -void csky_vdsp2_rfft_fast_f32( - csky_vdsp2_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - csky_vdsp2_rfft_fast_instance_f32 *pRfft; /**< points to the real FFT fast instance. */ - csky_vdsp2_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } csky_vdsp2_dct4_instance_f32; - - csky_vdsp2_status csky_vdsp2_dct4_init_f32( - csky_vdsp2_dct4_instance_f32 * S, - csky_vdsp2_rfft_fast_instance_f32 * S_RFFT, - csky_vdsp2_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - void csky_vdsp2_dct4_f32( - const csky_vdsp2_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - csky_vdsp2_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - csky_vdsp2_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } csky_vdsp2_dct4_instance_q31; - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - csky_vdsp2_rfft_fast_instance_q31 *pRfft; /**< points to the real FFT instance. */ - csky_vdsp2_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } csky_vdsp2_dct4_fast_instance_q31; - - csky_vdsp2_status csky_vdsp2_dct4_init_q31( - csky_vdsp2_dct4_instance_q31 * S, - csky_vdsp2_rfft_instance_q31 * S_RFFT, - csky_vdsp2_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - void csky_vdsp2_dct4_q31( - const csky_vdsp2_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - void csky_vdsp2_dct4_fast_q31( - const csky_vdsp2_dct4_fast_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - csky_vdsp2_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - csky_vdsp2_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } csky_vdsp2_dct4_instance_q15; - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - csky_vdsp2_rfft_fast_instance_q15 *pRfft; /**< points to the real FFT instance. */ - csky_vdsp2_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } csky_vdsp2_dct4_fast_instance_q15; - - csky_vdsp2_status csky_vdsp2_dct4_init_q15( - csky_vdsp2_dct4_instance_q15 * S, - csky_vdsp2_rfft_instance_q15 * S_RFFT, - csky_vdsp2_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - void csky_vdsp2_dct4_q15( - const csky_vdsp2_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - void csky_vdsp2_dct4_fast_q15( - const csky_vdsp2_dct4_fast_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - void csky_vdsp2_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_sum_q15( - q15_t * pSrcA, - q63_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_abs_max_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_abs_max_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - void csky_vdsp2_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - void csky_vdsp2_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - void csky_vdsp2_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - void csky_vdsp2_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - void csky_vdsp2_dot_prod_u64xu8( - uint8_t * pSrcA, - uint64_t * pSrcB, - uint32_t blockSize, - uint64_t * result); - - void csky_vdsp2_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - void csky_vdsp2_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - void csky_vdsp2_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - void csky_vdsp2_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - void csky_vdsp2_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - void csky_vdsp2_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - void csky_vdsp2_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - void csky_vdsp2_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - void csky_vdsp2_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - csky_vdsp2_status csky_vdsp2_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - csky_vdsp2_status csky_vdsp2_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - csky_vdsp2_status csky_vdsp2_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - csky_vdsp2_status csky_vdsp2_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - csky_vdsp2_status csky_vdsp2_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - csky_vdsp2_status csky_vdsp2_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - csky_vdsp2_status csky_vdsp2_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - csky_vdsp2_status csky_vdsp2_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - csky_vdsp2_status csky_vdsp2_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } csky_vdsp2_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } csky_vdsp2_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } csky_vdsp2_fir_decimate_instance_f32; - - void csky_vdsp2_fir_decimate_f32( - const csky_vdsp2_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - csky_vdsp2_status csky_vdsp2_fir_decimate_init_f32( - csky_vdsp2_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - void csky_vdsp2_fir_decimate_q15( - const csky_vdsp2_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_fir_decimate_fast_q15( - const csky_vdsp2_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - csky_vdsp2_status csky_vdsp2_fir_decimate_init_q15( - csky_vdsp2_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - void csky_vdsp2_fir_decimate_q31( - const csky_vdsp2_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_fir_decimate_fast_q31( - csky_vdsp2_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - csky_vdsp2_status csky_vdsp2_fir_decimate_init_q31( - csky_vdsp2_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } csky_vdsp2_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } csky_vdsp2_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } csky_vdsp2_fir_interpolate_instance_f32; - - void csky_vdsp2_fir_interpolate_q15( - const csky_vdsp2_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - csky_vdsp2_status csky_vdsp2_fir_interpolate_init_q15( - csky_vdsp2_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - void csky_vdsp2_fir_interpolate_q31( - const csky_vdsp2_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - csky_vdsp2_status csky_vdsp2_fir_interpolate_init_q31( - csky_vdsp2_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - void csky_vdsp2_fir_interpolate_f32( - const csky_vdsp2_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - csky_vdsp2_status csky_vdsp2_fir_interpolate_init_f32( - csky_vdsp2_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } csky_vdsp2_biquad_cascade_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } csky_vdsp2_biquad_cascade_stereo_df2T_instance_f32; - - void csky_vdsp2_biquad_cascade_df2T_f32( - const csky_vdsp2_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_biquad_cascade_stereo_df2T_f32( - const csky_vdsp2_biquad_cascade_stereo_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_biquad_cascade_df2T_init_f32( - csky_vdsp2_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - void csky_vdsp2_biquad_cascade_stereo_df2T_init_f32( - csky_vdsp2_biquad_cascade_stereo_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } csky_vdsp2_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } csky_vdsp2_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } csky_vdsp2_fir_lattice_instance_f32; - - void csky_vdsp2_fir_lattice_init_q15( - csky_vdsp2_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - void csky_vdsp2_fir_lattice_q15( - const csky_vdsp2_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_fir_lattice_init_q31( - csky_vdsp2_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - void csky_vdsp2_fir_lattice_q31( - const csky_vdsp2_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_fir_lattice_init_f32( - csky_vdsp2_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - void csky_vdsp2_fir_lattice_f32( - const csky_vdsp2_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } csky_vdsp2_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } csky_vdsp2_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } csky_vdsp2_iir_lattice_instance_f32; - - void csky_vdsp2_iir_lattice_f32( - const csky_vdsp2_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_iir_lattice_init_f32( - csky_vdsp2_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - - void csky_vdsp2_iir_lattice_q31( - const csky_vdsp2_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_iir_lattice_init_q31( - csky_vdsp2_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); - - void csky_vdsp2_iir_lattice_q15( - const csky_vdsp2_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_iir_lattice_init_q15( - csky_vdsp2_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } csky_vdsp2_lms_instance_f32; - - void csky_vdsp2_lms_f32( - const csky_vdsp2_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - void csky_vdsp2_lms_init_f32( - csky_vdsp2_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } csky_vdsp2_lms_instance_q15; - - void csky_vdsp2_lms_init_q15( - csky_vdsp2_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - void csky_vdsp2_lms_q15( - const csky_vdsp2_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } csky_vdsp2_lms_instance_q31; - - void csky_vdsp2_lms_q31( - const csky_vdsp2_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - void csky_vdsp2_lms_init_q31( - csky_vdsp2_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } csky_vdsp2_lms_norm_instance_f32; - - void csky_vdsp2_lms_norm_f32( - csky_vdsp2_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - void csky_vdsp2_lms_norm_init_f32( - csky_vdsp2_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } csky_vdsp2_lms_norm_instance_q31; - - void csky_vdsp2_lms_norm_q31( - csky_vdsp2_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - void csky_vdsp2_lms_norm_init_q31( - csky_vdsp2_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } csky_vdsp2_lms_norm_instance_q15; - - void csky_vdsp2_lms_norm_q15( - csky_vdsp2_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - void csky_vdsp2_lms_norm_init_q15( - csky_vdsp2_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - void csky_vdsp2_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - void csky_vdsp2_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - void csky_vdsp2_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - void csky_vdsp2_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - void csky_vdsp2_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - void csky_vdsp2_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - void csky_vdsp2_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - void csky_vdsp2_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - void csky_vdsp2_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } csky_vdsp2_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } csky_vdsp2_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } csky_vdsp2_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } csky_vdsp2_fir_sparse_instance_q7; - - void csky_vdsp2_fir_sparse_f32( - csky_vdsp2_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - void csky_vdsp2_fir_sparse_init_f32( - csky_vdsp2_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - void csky_vdsp2_fir_sparse_q31( - csky_vdsp2_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - void csky_vdsp2_fir_sparse_init_q31( - csky_vdsp2_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - void csky_vdsp2_fir_sparse_q15( - csky_vdsp2_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - void csky_vdsp2_fir_sparse_init_q15( - csky_vdsp2_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - void csky_vdsp2_fir_sparse_q7( - csky_vdsp2_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - void csky_vdsp2_fir_sparse_init_q7( - csky_vdsp2_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - void csky_vdsp2_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCosVal); - - void csky_vdsp2_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - - void csky_vdsp2_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - void csky_vdsp2_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - void csky_vdsp2_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - void csky_vdsp2_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - void csky_vdsp2_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - void csky_vdsp2_cmplx_mag_squared_q31_basic( - q31_t * pSrc, - q63_t * pDst, - uint32_t numSamples); - - void csky_vdsp2_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - void csky_vdsp2_vsqrt_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - void csky_vdsp2_vsqrt_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - void csky_vdsp2_vsqrt_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - void csky_vdsp2_vsqrt_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t numSamples); - - void csky_vdsp2_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - csky_vdsp2_status csky_vdsp2_sqrt_f32( - float32_t in, - float32_t * pOut); - - csky_vdsp2_status csky_vdsp2_sqrt_q31( - q31_t in, - q31_t * pOut); - - csky_vdsp2_status csky_vdsp2_sqrt_q15( - q15_t in, - q15_t * pOut); - - void csky_vdsp2_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - void csky_vdsp2_power_int32( - int32_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - void csky_vdsp2_power_int32( - int32_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - void csky_vdsp2_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - void csky_vdsp2_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - void csky_vdsp2_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - void csky_vdsp2_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - void csky_vdsp2_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - void csky_vdsp2_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - void csky_vdsp2_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - void csky_vdsp2_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - void csky_vdsp2_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - void csky_vdsp2_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - void csky_vdsp2_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - void csky_vdsp2_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - void csky_vdsp2_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - void csky_vdsp2_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - void csky_vdsp2_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - void csky_vdsp2_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - void csky_vdsp2_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - void csky_vdsp2_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - void csky_vdsp2_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - void csky_vdsp2_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - void csky_vdsp2_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - void csky_vdsp2_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - void csky_vdsp2_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - void csky_vdsp2_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - void csky_vdsp2_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - void csky_vdsp2_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - void csky_vdsp2_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - void csky_vdsp2_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - void csky_vdsp2_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - void csky_vdsp2_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - - void csky_vdsp2_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - void csky_vdsp2_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - void csky_vdsp2_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - void csky_vdsp2_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - void csky_vdsp2_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - void csky_vdsp2_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - void csky_vdsp2_cmplx_mult_cmplx_re_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - void csky_vdsp2_cmplx_mult_cmplx_re_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - void csky_vdsp2_cmplx_mult_cmplx_re_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - - void csky_vdsp2_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_q31_to_q7_rs( - q31_t * pSrc, - q7_t * pDst, - uint32_t shiftValue, - uint32_t blockSize); - - void csky_vdsp2_q63_to_q31_rs( - q63_t * pSrc, - q31_t * pDst, - uint32_t shiftValue, - uint32_t blockSize); - - void csky_vdsp2_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - void csky_vdsp2_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - -#ifdef __cplusplus -} -#endif -#endif /* _CSKY_VDSP2_MATH_H */ - -/** - * - * End of file. - */ diff --git a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/src/csi_ringbuf.c b/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/src/csi_ringbuf.c deleted file mode 100644 index 364b682c..00000000 --- a/ports/xuantie/e906/gnu/example_build/smartl_fpga/components/csi/csi2/src/csi_ringbuf.c +++ /dev/null @@ -1,184 +0,0 @@ -#include -#include -#include -#include -#include "drv/ringbuf.h" - -#define min(a, b) (((a) < (b)) ? (a) : (b)) - -/** - * \brief Removes the entire FIFO contents. - * \param [in] fifo: The fifo to be emptied. - * \return None. - */ -void csi_ringbuf_reset(csi_ringbuf_t *fifo) -{ - uint32_t stat = csi_irq_save(); - fifo->write = fifo->read = 0; - fifo->data_len = 0; - csi_irq_restore(stat); -} - -/** - * \brief Returns the size of the FIFO in bytes. - * \param [in] fifo: The fifo to be used. - * \return The size of the FIFO. - */ -static inline uint32_t csi_ringbuf_size(csi_ringbuf_t *fifo) -{ - return fifo->size; -} - -/** - * \brief Returns the number of used bytes in the FIFO. - * \param [in] fifo: The fifo to be used. - * \return The number of used bytes. - */ -uint32_t csi_ringbuf_len(csi_ringbuf_t *fifo) -{ - return fifo->data_len; -} - -/** - * \brief Returns the number of bytes available in the FIFO. - * \param [in] fifo: The fifo to be used. - * \return The number of bytes available. - */ -uint32_t csi_ringbuf_avail(csi_ringbuf_t *fifo) -{ - return csi_ringbuf_size(fifo) - csi_ringbuf_len(fifo); -} - -/** - * \brief Is the FIFO empty? - * \param [in] fifo: The fifo to be used. - * \retval true: Yes. - * \retval false: No. - */ -bool csi_ringbuf_is_empty(csi_ringbuf_t *fifo) -{ - return csi_ringbuf_len(fifo) == 0; -} - -/** - * \brief Is the FIFO full? - * \param [in] fifo: The fifo to be used. - * \retval true: Yes. - * \retval false: No. - */ -bool csi_ringbuf_is_full(csi_ringbuf_t *fifo) -{ - return csi_ringbuf_avail(fifo) == 0; -} - -/** - * \brief Puts some data into the FIFO. - * \param [in] fifo: The fifo to be used. - * \param [in] in: The data to be added. - * \param [in] len: The length of the data to be added. - * \return The number of bytes copied. - * \note This function copies at most @len bytes from the @in into - * the FIFO depending on the free space, and returns the number - * of bytes copied. - */ -uint32_t csi_ringbuf_in(csi_ringbuf_t *fifo, const void *datptr, uint32_t len) -{ - uint32_t writelen = 0, tmplen = 0; - - if(csi_ringbuf_is_full(fifo)) - return 0; - - tmplen = fifo->size - fifo->data_len; - writelen = tmplen > len ? len : tmplen; - - if(fifo->write < fifo->read) { - memcpy((void*)&fifo->buffer[fifo->write], (void*)datptr, writelen); - } else { - tmplen = fifo->size - fifo->write; - if(writelen <= tmplen) { - memcpy((void*)&fifo->buffer[fifo->write], (void*)datptr, writelen); - } else { - memcpy((void*)&fifo->buffer[fifo->write], (void*)datptr, tmplen); - memcpy((void*)fifo->buffer, (uint8_t*)datptr + tmplen, writelen - tmplen); - } - } - - uint32_t stat = csi_irq_save(); - fifo->write = (fifo->write + writelen) % fifo->size; - fifo->data_len += writelen; - csi_irq_restore(stat); - - return writelen; -} - -/** - * \brief Gets some data from the FIFO. - * \param [in] fifo: The fifo to be used. - * \param [in] out: Where the data must be copied. - * \param [in] len: The size of the destination buffer. - * \return The number of copied bytes. - * \note This function copies at most @len bytes from the FIFO into - * the @out and returns the number of copied bytes. - */ -uint32_t csi_ringbuf_out(csi_ringbuf_t *fifo, void *outbuf, uint32_t len) -{ - uint32_t readlen = 0, tmplen = 0; - if(csi_ringbuf_is_empty(fifo)) - return 0; - - uint32_t data_len = fifo->data_len; - readlen = len > data_len ? data_len : len; - tmplen = fifo->size - fifo->read; - - if(NULL != outbuf) { - if(readlen <= tmplen) { - memcpy((void*)outbuf, (void*)&fifo->buffer[fifo->read], readlen); - } else { - memcpy((void*)outbuf,(void*)&fifo->buffer[fifo->read], tmplen); - memcpy((uint8_t*)outbuf + tmplen,(void*)fifo->buffer,readlen - tmplen); - } - } - - uint32_t stat = csi_irq_save(); - fifo->read = (fifo->read + readlen) % fifo->size; - fifo->data_len -= readlen; - csi_irq_restore(stat); - - return readlen; -} - -/** - * \brief Move FIFO buffer to another FIFO. - * \param [in] fifo_in: The fifo to be used. - * \param [in] fifo_out: The fifo to be used. - * \return The number of copied bytes. - * \note This function copies at most @len bytes from the FIFO into - * the @out and returns the number of copied bytes. - */ -uint32_t csi_ringbuf_move(csi_ringbuf_t *fifo_in, csi_ringbuf_t *fifo_out) -{ - uint32_t readlen = 0, tmplen_out = 0; - if(csi_ringbuf_is_empty(fifo_out)) - return 0; - - uint32_t len = csi_ringbuf_avail(fifo_in); - - uint32_t data_len = fifo_out->data_len; - readlen = len > data_len ? data_len : len; - tmplen_out = fifo_out->size - fifo_out->read; - - if(readlen <= tmplen_out) { - csi_ringbuf_in(fifo_in, (void*)&fifo_out->buffer[fifo_out->read], readlen); - } else { - csi_ringbuf_in(fifo_in, (void*)&fifo_out->buffer[fifo_out->read], tmplen_out); - csi_ringbuf_in(fifo_in, (void*)fifo_out->buffer, readlen - tmplen_out); - } - - uint32_t stat = csi_irq_save(); - fifo_out->read = (fifo_out->read + readlen) % fifo_out->size; - fifo_out->data_len -= readlen; - csi_irq_restore(stat); - - return readlen; -} - diff --git a/ports/xuantie/e906/gnu/inc/tx_port.h b/ports/xuantie/e906/gnu/inc/tx_port.h deleted file mode 100644 index 50f87587..00000000 --- a/ports/xuantie/e906/gnu/inc/tx_port.h +++ /dev/null @@ -1,361 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Port Specific */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h RISC-V64/GNU */ -/* 6.2.1 */ -/* */ -/* AUTHOR */ -/* */ -/* Scott Larson, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ -/**************************************************************************/ - -#ifndef TX_PORT_H -#define TX_PORT_H - -#include -#include - -/* Determine if the optional ThreadX user define file should be used. */ - -#ifdef TX_INCLUDE_USER_DEFINE_FILE - - -/* Yes, include the user defines in tx_user.h. The defines in this file may - alternately be defined on the command line. */ - -#include "tx_user.h" -#endif - - -/* Define compiler library include files. */ - - -/* Define ThreadX basic types for this port. */ - -#define VOID void -typedef char CHAR; -typedef unsigned char UCHAR; -typedef int INT; -typedef unsigned int UINT; -typedef long LONG; -typedef unsigned long ULONG; -typedef unsigned long long ULONG64; -typedef short SHORT; -typedef unsigned short USHORT; -#define ULONG64_DEFINED - -#define ALIGN_TYPE_DEFINED -#define ALIGN_TYPE ULONG - - -typedef struct thread_stack_frame { - unsigned long epc; /* epc - epc - program counter */ - unsigned long ra; /* x1 - ra - return address for jumps */ - unsigned long t0; /* x5 - t0 - temporary register 0 */ - unsigned long t1; /* x6 - t1 - temporary register 1 */ - unsigned long t2; /* x7 - t2 - temporary register 2 */ - unsigned long s0_fp; /* x8 - s0/fp - saved register 0 or frame pointer */ - unsigned long s1; /* x9 - s1 - saved register 1 */ - unsigned long a0; /* x10 - a0 - return value or function argument 0 */ - unsigned long a1; /* x11 - a1 - return value or function argument 1 */ - unsigned long a2; /* x12 - a2 - function argument 2 */ - unsigned long a3; /* x13 - a3 - function argument 3 */ - unsigned long a4; /* x14 - a4 - function argument 4 */ - unsigned long a5; /* x15 - a5 - function argument 5 */ - unsigned long a6; /* x16 - a6 - function argument 6 */ - unsigned long a7; /* x17 - s7 - function argument 7 */ - unsigned long s2; /* x18 - s2 - saved register 2 */ - unsigned long s3; /* x19 - s3 - saved register 3 */ - unsigned long s4; /* x20 - s4 - saved register 4 */ - unsigned long s5; /* x21 - s5 - saved register 5 */ - unsigned long s6; /* x22 - s6 - saved register 6 */ - unsigned long s7; /* x23 - s7 - saved register 7 */ - unsigned long s8; /* x24 - s8 - saved register 8 */ - unsigned long s9; /* x25 - s9 - saved register 9 */ - unsigned long s10; /* x26 - s10 - saved register 10 */ - unsigned long s11; /* x27 - s11 - saved register 11 */ - unsigned long t3; /* x28 - t3 - temporary register 3 */ - unsigned long t4; /* x29 - t4 - temporary register 4 */ - unsigned long t5; /* x30 - t5 - temporary register 5 */ - unsigned long t6; /* x31 - t6 - temporary register 6 */ - unsigned long mstatus; /* - machine status register */ -} tx_stack_frame_t; - -typedef struct __attribute__((packed)) { - unsigned long fcsr; -#if __riscv_float_abi_single - unsigned long f[32]; /* f0~f31 */ -#elif __riscv_float_abi_double - unsigned long long f[32]; /* f0~f31 */ -#endif -} tx_stack_f_frame_t; - -typedef struct { - unsigned long vxsat; -} tx_stack_p_frame_t; - -/* Define the priority levels for ThreadX. Legal values range - from 32 to 1024 and MUST be evenly divisible by 32. */ - -#ifndef TX_MAX_PRIORITIES -#define TX_MAX_PRIORITIES 32 -#endif - - -/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during - thread creation is less than this value, the thread create call will return an error. */ - -#ifndef TX_MINIMUM_STACK -#define TX_MINIMUM_STACK 1024 /* Minimum stack size for this port */ -#endif - - -/* Define the system timer thread's default stack size and priority. These are only applicable - if TX_TIMER_PROCESS_IN_ISR is not defined. */ - -#ifndef TX_TIMER_THREAD_STACK_SIZE -#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ -#endif - -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ -#endif - - -/* Define various constants for the ThreadX RISC-V port. */ - -#define TX_INT_DISABLE 0x00000000 /* Disable interrupts value */ -#define TX_INT_ENABLE 0x00000008 /* Enable interrupt value */ - - -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock - source constants would be: - -#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) -#define TX_TRACE_TIME_MASK 0x0000FFFFUL - -*/ - -#ifndef TX_TRACE_TIME_SOURCE -#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time -#endif -#ifndef TX_TRACE_TIME_MASK -#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL -#endif - - -/* Define the port specific options for the _tx_build_options variable. This variable indicates - how the ThreadX library was built. */ - -#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 - - -/* Define the in-line initialization constant so that modules with in-line - initialization capabilities can prevent their initialization from being - a function call. */ - -#define TX_INLINE_INITIALIZATION - - -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is - disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack - checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING - define is negated, thereby forcing the stack fill which is necessary for the stack checking - logic. */ - -#ifdef TX_ENABLE_STACK_CHECKING -#undef TX_DISABLE_STACK_FILLING -#endif - - - -/* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with - existing ThreadX kernel awareness modules. */ - -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ - VOID *tx_thread_module_entry_info_ptr; \ - ULONG tx_thread_module_current_user_mode; \ - ULONG tx_thread_module_user_mode; \ - ULONG tx_thread_module_saved_lr; \ - VOID *tx_thread_module_kernel_stack_start; \ - VOID *tx_thread_module_kernel_stack_end; \ - ULONG tx_thread_module_kernel_stack_size; \ - VOID *tx_thread_module_stack_ptr; \ - VOID *tx_thread_module_stack_start; \ - VOID *tx_thread_module_stack_end; \ - ULONG tx_thread_module_stack_size; \ - VOID *tx_thread_module_reserved; \ - VOID *tx_thread_iar_tls_pointer; -#else -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ - VOID *tx_thread_module_entry_info_ptr; \ - ULONG tx_thread_module_current_user_mode; \ - ULONG tx_thread_module_user_mode; \ - ULONG tx_thread_module_saved_lr; \ - VOID *tx_thread_module_kernel_stack_start; \ - VOID *tx_thread_module_kernel_stack_end; \ - ULONG tx_thread_module_kernel_stack_size; \ - VOID *tx_thread_module_stack_ptr; \ - VOID *tx_thread_module_stack_start; \ - VOID *tx_thread_module_stack_end; \ - ULONG tx_thread_module_stack_size; \ - VOID *tx_thread_module_reserved; -#endif -#ifndef TX_ENABLE_EXECUTION_CHANGE_NOTIFY -#define TX_THREAD_EXTENSION_3 -#else -#define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; -#endif - - -/* Define the port extensions of the remaining ThreadX objects. */ - -#define TX_BLOCK_POOL_EXTENSION -#define TX_BYTE_POOL_EXTENSION -#define TX_MUTEX_EXTENSION -#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ - VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); - -#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ - VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); - -#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ - VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); - -#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ - VOID (*tx_timer_module_expiration_function)(ULONG id); - - -/* Define the user extension field of the thread control block. Nothing - additional is needed for this port so it is defined as white space. */ - -#ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION -#endif - - - -/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, - tx_thread_shell_entry, and tx_thread_terminate. */ - -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) -#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) -#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) - - -/* Define the ThreadX object creation extensions for the remaining objects. */ - -#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) -#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) -#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) -#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) -#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) -#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) -#define TX_TIMER_CREATE_EXTENSION(timer_ptr) - - -/* Define the ThreadX object deletion extensions for the remaining objects. */ - -#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) -#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) -#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) -#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) -#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) -#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) -#define TX_TIMER_DELETE_EXTENSION(timer_ptr) - - -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value - present prior to the disable macro. In most cases, the save area macro - is used to define a local function save area for the disable and restore - macros. */ - -#ifdef TX_DISABLE_INLINE - -#define TX_INTERRUPT_SAVE_AREA register ULONG interrupt_save; - -#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); -#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); - -#else - -#define TX_INTERRUPT_SAVE_AREA ULONG interrupt_save; -/* Atomically read mstatus into interrupt_save and clear bit 3 of mstatus. */ -#define TX_DISABLE {__asm__ volatile ("csrrci %0, mstatus, 0x08" : "=r" (interrupt_save) : : "memory");}; -/* We only care about mstatus.mie (bit 3), so mask interrupt_save and write to mstatus. */ -#define TX_RESTORE {register ULONG __tempmask = interrupt_save & 0x08; \ - __asm__ volatile ("csrrs x0, mstatus, %0 \n\t" : : "r" (__tempmask) : "memory");}; - -#endif - - -/* Define the interrupt lockout macros for each ThreadX object. */ - -#define TX_BLOCK_POOL_DISABLE TX_DISABLE -#define TX_BYTE_POOL_DISABLE TX_DISABLE -#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE -#define TX_MUTEX_DISABLE TX_DISABLE -#define TX_QUEUE_DISABLE TX_DISABLE -#define TX_SEMAPHORE_DISABLE TX_DISABLE - - -/* Define the version ID of ThreadX. This may be utilized by the application. */ - -#ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX RISC-V32/GNU Version 6.4.2 *"; -#else -extern CHAR _tx_version_id[]; -#endif - -#endif diff --git a/ports/xuantie/e906/gnu/src/tx_port.c b/ports/xuantie/e906/gnu/src/tx_port.c deleted file mode 100644 index 1fee892a..00000000 --- a/ports/xuantie/e906/gnu/src/tx_port.c +++ /dev/null @@ -1,110 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "tx_api.h" -#include "tx_timer.h" -#include "tx_thread.h" -#include "tx_initialize.h" - -void thread_switch_ext(void) -{ -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - _tx_execution_thread_exit(); -#endif - - if(!_tx_thread_execute_ptr) { - unsigned long mcause; - __asm__ volatile( - "csrr %0, mcause\n\t" - "csrsi mstatus, 0x8" - : "=r"(mcause) - : - : "memory" - ); - while (!_tx_thread_execute_ptr) { - __asm__ volatile("wfi"); - } - __asm__ volatile( - "csrci mstatus, 0x8\n\t" - "csrw mcause, %0" - : - : "r"(mcause) - : "memory" - ); - } - /* Determine if the time-slice is active. */ - if (_tx_timer_time_slice && _tx_thread_current_ptr) { - /* Preserve current remaining time-slice for the thread and clear the current time-slice. */ - _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; - _tx_timer_time_slice = 0; - } - _tx_thread_current_ptr = _tx_thread_execute_ptr; -} - -VOID _tx_initialize_low_level(VOID) -{ - _tx_initialize_unused_memory = NULL; - _tx_thread_interrupt_control(0); -} - -VOID _tx_thread_exit(VOID) -{ - while (1) { - __asm__ volatile("wfi"); - } -} - -VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) -{ - int i; - uint8_t *stk; - tx_stack_frame_t *frame; - - stk = thread_ptr -> tx_thread_stack_end; - stk = (uint8_t *)(((unsigned long)stk) & (~(unsigned long)(sizeof(ALIGN_TYPE) - 1))); - stk -= sizeof(tx_stack_frame_t); - - frame = (tx_stack_frame_t *)stk; - - for (i = 0; i < sizeof(tx_stack_frame_t) / sizeof(unsigned long); i++) { - ((unsigned long*)frame)[i] = 0; - } - - frame->epc = (unsigned long)function_ptr; - frame->ra = (unsigned long)_tx_thread_exit; - frame->mstatus = (3UL << 11) | (1UL << 7); // mstatus.MPP=3, MPIE=1 - -#if __riscv_flen - frame->mstatus |= (1UL << 13); // mstatus.FS=1 - stk -= sizeof(tx_stack_f_frame_t); - tx_stack_f_frame_t *f_frame = (tx_stack_f_frame_t *)stk; - f_frame->fcsr = 0; - for (int i = 0; i < 32; i++) { - f_frame->f[i] = 0; - } -#endif - -#if __riscv_dsp - stk -= sizeof(tx_stack_p_frame_t); - tx_stack_p_frame_t *p_frame = (tx_stack_p_frame_t *)stk; - p_frame->vxsat = 0; -#endif - - thread_ptr -> tx_thread_stack_ptr = stk; -} - diff --git a/ports/xuantie/e906/gnu/src/tx_thread_context.S b/ports/xuantie/e906/gnu/src/tx_thread_context.S deleted file mode 100644 index 220520bb..00000000 --- a/ports/xuantie/e906/gnu/src/tx_thread_context.S +++ /dev/null @@ -1,283 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -.section .text - - .align 3 - .global tspend_handler - .type tspend_handler, @function -tspend_handler: - addi sp, sp, -(30 * 4) - sw x1, 1 * 4(sp) /* RA */ - sw x5, 2 * 4(sp) - sw x6, 3 * 4(sp) - sw x7, 4 * 4(sp) - sw x8, 5 * 4(sp) - sw x9, 6 * 4(sp) - sw x10, 7 * 4(sp) - sw x11, 8 * 4(sp) - sw x12, 9 * 4(sp) - sw x13, 10 * 4(sp) - sw x14, 11 * 4(sp) - sw x15, 12 * 4(sp) - sw x16, 13 * 4(sp) - sw x17, 14 * 4(sp) - sw x18, 15 * 4(sp) - sw x19, 16 * 4(sp) - sw x20, 17 * 4(sp) - sw x21, 18 * 4(sp) - sw x22, 19 * 4(sp) - sw x23, 20 * 4(sp) - sw x24, 21 * 4(sp) - sw x25, 22 * 4(sp) - sw x26, 23 * 4(sp) - sw x27, 24 * 4(sp) - sw x28, 25 * 4(sp) - sw x29, 26 * 4(sp) - sw x30, 27 * 4(sp) - sw x31, 28 * 4(sp) - - csrr t0, mepc - sw t0, 0(sp) - - csrr t3, mstatus - sw t3, 29 * 4(sp) - -#if __riscv_flen - addi sp, sp, -4 - frcsr t0 - sw t0, 0(sp) -#if __riscv_float_abi_single - addi sp, sp, -(32 * 4) - fsw f0, 0 * 4(sp) - fsw f1, 1 * 4(sp) - fsw f2, 2 * 4(sp) - fsw f3, 3 * 4(sp) - fsw f4, 4 * 4(sp) - fsw f5, 5 * 4(sp) - fsw f6, 6 * 4(sp) - fsw f7, 7 * 4(sp) - fsw f8, 8 * 4(sp) - fsw f9, 9 * 4(sp) - fsw f10, 10 * 4(sp) - fsw f11, 11 * 4(sp) - fsw f12, 12 * 4(sp) - fsw f13, 13 * 4(sp) - fsw f14, 14 * 4(sp) - fsw f15, 15 * 4(sp) - fsw f16, 16 * 4(sp) - fsw f17, 17 * 4(sp) - fsw f18, 18 * 4(sp) - fsw f19, 19 * 4(sp) - fsw f20, 20 * 4(sp) - fsw f21, 21 * 4(sp) - fsw f22, 22 * 4(sp) - fsw f23, 23 * 4(sp) - fsw f24, 24 * 4(sp) - fsw f25, 25 * 4(sp) - fsw f26, 26 * 4(sp) - fsw f27, 27 * 4(sp) - fsw f28, 28 * 4(sp) - fsw f29, 29 * 4(sp) - fsw f30, 30 * 4(sp) - fsw f31, 31 * 4(sp) -#elif __riscv_float_abi_double - addi sp, sp, -(32 * 8) - fsw f0, 0 * 8(sp) - fsw f1, 1 * 8(sp) - fsw f2, 2 * 8(sp) - fsw f3, 3 * 8(sp) - fsw f4, 4 * 8(sp) - fsw f5, 5 * 8(sp) - fsw f6, 6 * 8(sp) - fsw f7, 7 * 8(sp) - fsw f8, 8 * 8(sp) - fsw f9, 9 * 8(sp) - fsw f10, 10 * 8(sp) - fsw f11, 11 * 8(sp) - fsw f12, 12 * 8(sp) - fsw f13, 13 * 8(sp) - fsw f14, 14 * 8(sp) - fsw f15, 15 * 8(sp) - fsw f16, 16 * 8(sp) - fsw f17, 17 * 8(sp) - fsw f18, 18 * 8(sp) - fsw f19, 19 * 8(sp) - fsw f20, 20 * 8(sp) - fsw f21, 21 * 8(sp) - fsw f22, 22 * 8(sp) - fsw f23, 23 * 8(sp) - fsw f24, 24 * 8(sp) - fsw f25, 25 * 8(sp) - fsw f26, 26 * 8(sp) - fsw f27, 27 * 8(sp) - fsw f28, 28 * 8(sp) - fsw f29, 29 * 8(sp) - fsw f30, 30 * 8(sp) - fsw f31, 31 * 8(sp) -#endif -#endif /* __riscv_flen */ - -#if __riscv_dsp - addi sp, sp, -4 - csrr t0, vxsat - sw t0, 0(sp) -#endif /*__riscv_dsp */ - - /* If _tx_thread_current_ptr is null, no sp need to be saved */ - la t0, _tx_thread_current_ptr - lw t0, 0(t0) - beqz t0, _tx_thread_switch - /* Store sp to task stack to _tx_thread_current_ptr -> tx_thread_stack_ptr */ - sw sp, 2 * 4(t0) - -_tx_thread_switch: - jal thread_switch_ext - /*clear software interrupt*/ - /* Edge-triggered vector interrupts do not require software to clear the pending bit. */ - - /* Switch task context to _tx_thread_execute_ptr */ - la t0, _tx_thread_execute_ptr - lw t0, 0(t0) - lw sp, 2 * 4(t0) - - /* Pop additional registers */ -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - -#if __riscv_flen -#if __riscv_float_abi_single - flw f0, 0 * 4(sp) - flw f1, 1 * 4(sp) - flw f2, 2 * 4(sp) - flw f3, 3 * 4(sp) - flw f4, 4 * 4(sp) - flw f5, 5 * 4(sp) - flw f6, 6 * 4(sp) - flw f7, 7 * 4(sp) - flw f8, 8 * 4(sp) - flw f9, 9 * 4(sp) - flw f10, 10 * 4(sp) - flw f11, 11 * 4(sp) - flw f12, 12 * 4(sp) - flw f13, 13 * 4(sp) - flw f14, 14 * 4(sp) - flw f15, 15 * 4(sp) - flw f16, 16 * 4(sp) - flw f17, 17 * 4(sp) - flw f18, 18 * 4(sp) - flw f19, 19 * 4(sp) - flw f20, 20 * 4(sp) - flw f21, 21 * 4(sp) - flw f22, 22 * 4(sp) - flw f23, 23 * 4(sp) - flw f24, 24 * 4(sp) - flw f25, 25 * 4(sp) - flw f26, 26 * 4(sp) - flw f27, 27 * 4(sp) - flw f28, 28 * 4(sp) - flw f29, 29 * 4(sp) - flw f30, 30 * 4(sp) - flw f31, 31 * 4(sp) - addi sp, sp, (32 * 4) -#elif __riscv_float_abi_double - flw f0, 0 * 8(sp) - flw f1, 1 * 8(sp) - flw f2, 2 * 8(sp) - flw f3, 3 * 8(sp) - flw f4, 4 * 8(sp) - flw f5, 5 * 8(sp) - flw f6, 6 * 8(sp) - flw f7, 7 * 8(sp) - flw f8, 8 * 8(sp) - flw f9, 9 * 8(sp) - flw f10, 10 * 8(sp) - flw f11, 11 * 8(sp) - flw f12, 12 * 8(sp) - flw f13, 13 * 8(sp) - flw f14, 14 * 8(sp) - flw f15, 15 * 8(sp) - flw f16, 16 * 8(sp) - flw f17, 17 * 8(sp) - flw f18, 18 * 8(sp) - flw f19, 19 * 8(sp) - flw f20, 20 * 8(sp) - flw f21, 21 * 8(sp) - flw f22, 22 * 8(sp) - flw f23, 23 * 8(sp) - flw f24, 24 * 8(sp) - flw f25, 25 * 8(sp) - flw f26, 26 * 8(sp) - flw f27, 27 * 8(sp) - flw f28, 28 * 8(sp) - flw f29, 29 * 8(sp) - flw f30, 30 * 8(sp) - flw f31, 31 * 8(sp) - addi sp, sp, (32 * 8) -#endif - - lw t0, 0(sp) - fscsr t0 - addi sp, sp, 4 -#endif /* __riscv_flen */ - - /* Pop PC from stack and set MEPC */ - lw t0, 0 * 4(sp) - csrw mepc, t0 - - /* Pop mstatus from stack and set it */ - lw t0, 29 * 4(sp) - csrw mstatus, t0 - - /* Interrupt still disable here */ - /* Restore Registers from Stack */ - lw x1, 1 * 4(sp) /* RA */ - lw x5, 2 * 4(sp) - lw x6, 3 * 4(sp) - lw x7, 4 * 4(sp) - lw x8, 5 * 4(sp) - lw x9, 6 * 4(sp) - lw x10, 7 * 4(sp) - lw x11, 8 * 4(sp) - lw x12, 9 * 4(sp) - lw x13, 10 * 4(sp) - lw x14, 11 * 4(sp) - lw x15, 12 * 4(sp) - lw x16, 13 * 4(sp) - lw x17, 14 * 4(sp) - lw x18, 15 * 4(sp) - lw x19, 16 * 4(sp) - lw x20, 17 * 4(sp) - lw x21, 18 * 4(sp) - lw x22, 19 * 4(sp) - lw x23, 20 * 4(sp) - lw x24, 21 * 4(sp) - lw x25, 22 * 4(sp) - lw x26, 23 * 4(sp) - lw x27, 24 * 4(sp) - lw x28, 25 * 4(sp) - lw x29, 26 * 4(sp) - lw x30, 27 * 4(sp) - lw x31, 28 * 4(sp) - addi sp, sp, (30 * 4) - - mret - - .size tspend_handler, . - tspend_handler diff --git a/ports/xuantie/e906/gnu/src/tx_thread_interrupt_control.S b/ports/xuantie/e906/gnu/src/tx_thread_interrupt_control.S deleted file mode 100644 index f5b538e8..00000000 --- a/ports/xuantie/e906/gnu/src/tx_thread_interrupt_control.S +++ /dev/null @@ -1,83 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Thread */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - - .section .text -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_interrupt_control RISC-V64/GNU */ -/* 6.2.1 */ -/* AUTHOR */ -/* */ -/* Scott Larson, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function is responsible for changing the interrupt lockout */ -/* posture of the system. */ -/* */ -/* INPUT */ -/* */ -/* new_posture New interrupt lockout posture */ -/* */ -/* OUTPUT */ -/* */ -/* old_posture Old interrupt lockout posture */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ -/**************************************************************************/ -/* UINT _tx_thread_interrupt_control(UINT new_posture) -{ */ - .global _tx_thread_interrupt_control -_tx_thread_interrupt_control: - /* Pickup current interrupt lockout posture. */ - /* old_mstatus = mstatus; */ - - csrr t0, mstatus - mv t1, t0 // Save original mstatus for return - - /* Apply the new interrupt posture while preserving unrelated mstatus bits. */ - /* Only modify the MIE bit (bit 3) */ - /* mstatus = (mstatus & ~MIE) | (new_posture & MIE); */ - - li t2, ~0x08 // Build mask to clear MIE - and t0, t0, t2 // Clear MIE bit - and a0, a0, 0x08 // Mask incoming to only MIE bit - or t0, t0, a0 // Set requested MIE state - csrw mstatus, t0 - andi a0, t1, 0x08 // Return original MIE bit - ret -/* } */ diff --git a/ports/xuantie/e906/gnu/src/tx_thread_schedule.S b/ports/xuantie/e906/gnu/src/tx_thread_schedule.S deleted file mode 100644 index 09d67ec2..00000000 --- a/ports/xuantie/e906/gnu/src/tx_thread_schedule.S +++ /dev/null @@ -1,234 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Thread */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - .section .text -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_schedule RISC-V64/GNU */ -/* 6.2.1 */ -/* AUTHOR */ -/* */ -/* Scott Larson, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function waits for a thread control block pointer to appear in */ -/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -/* in the variable, the corresponding thread is resumed. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_initialize_kernel_enter ThreadX entry function */ -/* _tx_thread_system_return Return to system from thread */ -/* _tx_thread_context_restore Restore thread's context */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ -/**************************************************************************/ -/* VOID _tx_thread_schedule(VOID) -{ */ - .align 3 - .global _tx_thread_schedule - .type _tx_thread_schedule, @function -_tx_thread_schedule: - /* Enable interrupts. */ - csrsi mstatus, 0x08 // Enable interrupts - - /* Wait for a thread to execute. */ - /* do - { */ - la t0, _tx_thread_execute_ptr // Pickup address of execute ptr -_tx_thread_schedule_loop: - lw t1, 0(t0) // Pickup next thread to execute - beqz t1, _tx_thread_schedule_loop // If NULL, wait for thread to execute - /* } - while(_tx_thread_execute_ptr == TX_NULL); */ - - /* Yes! We have a thread to execute. Lockout interrupts and - transfer control to it. */ - csrci mstatus, 0x08 // Lockout interrupts - - /* Setup the current thread pointer. */ - /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ - la t0, _tx_thread_current_ptr // Pickup current thread pointer address - sw t1, 0(t0) // Set current thread pointer - - /* Increment the run count for this thread. */ - /* _tx_thread_current_ptr -> tx_thread_run_count++; */ - lw t2, 1 * 4(t1) // Pickup run count - lw t3, 6 * 4(t1) // Pickup time slice value - addi t2, t2, 1 // Increment run count - sw t2, 1 * 4(t1) // Store new run count - - /* Setup time-slice, if present. */ - /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ - la t2, _tx_timer_time_slice // Pickup time-slice variable address - - /* Switch to the thread's stack. */ - /* SP = _tx_thread_execute_ptr -> tx_thread_stack_ptr; */ - lw sp, 2 * 4(t1) // Switch to thread's stack - sw t3, 0(t2) // Store new time-slice*/ - -#if __riscv_dsp - lw t0, 0(sp) - csrw vxsat, t0 - addi sp, sp, 4 -#endif /*__riscv_dsp */ - -#if __riscv_flen -#if __riscv_float_abi_single - flw f0, 0 * 4(sp) - flw f1, 1 * 4(sp) - flw f2, 2 * 4(sp) - flw f3, 3 * 4(sp) - flw f4, 4 * 4(sp) - flw f5, 5 * 4(sp) - flw f6, 6 * 4(sp) - flw f7, 7 * 4(sp) - flw f8, 8 * 4(sp) - flw f9, 9 * 4(sp) - flw f10, 10 * 4(sp) - flw f11, 11 * 4(sp) - flw f12, 12 * 4(sp) - flw f13, 13 * 4(sp) - flw f14, 14 * 4(sp) - flw f15, 15 * 4(sp) - flw f16, 16 * 4(sp) - flw f17, 17 * 4(sp) - flw f18, 18 * 4(sp) - flw f19, 19 * 4(sp) - flw f20, 20 * 4(sp) - flw f21, 21 * 4(sp) - flw f22, 22 * 4(sp) - flw f23, 23 * 4(sp) - flw f24, 24 * 4(sp) - flw f25, 25 * 4(sp) - flw f26, 26 * 4(sp) - flw f27, 27 * 4(sp) - flw f28, 28 * 4(sp) - flw f29, 29 * 4(sp) - flw f30, 30 * 4(sp) - flw f31, 31 * 4(sp) - addi sp, sp, (32 * 4) -#elif __riscv_float_abi_double - flw f0, 0 * 8(sp) - flw f1, 1 * 8(sp) - flw f2, 2 * 8(sp) - flw f3, 3 * 8(sp) - flw f4, 4 * 8(sp) - flw f5, 5 * 8(sp) - flw f6, 6 * 8(sp) - flw f7, 7 * 8(sp) - flw f8, 8 * 8(sp) - flw f9, 9 * 8(sp) - flw f10, 10 * 8(sp) - flw f11, 11 * 8(sp) - flw f12, 12 * 8(sp) - flw f13, 13 * 8(sp) - flw f14, 14 * 8(sp) - flw f15, 15 * 8(sp) - flw f16, 16 * 8(sp) - flw f17, 17 * 8(sp) - flw f18, 18 * 8(sp) - flw f19, 19 * 8(sp) - flw f20, 20 * 8(sp) - flw f21, 21 * 8(sp) - flw f22, 22 * 8(sp) - flw f23, 23 * 8(sp) - flw f24, 24 * 8(sp) - flw f25, 25 * 8(sp) - flw f26, 26 * 8(sp) - flw f27, 27 * 8(sp) - flw f28, 28 * 8(sp) - flw f29, 29 * 8(sp) - flw f30, 30 * 8(sp) - flw f31, 31 * 8(sp) - addi sp, sp, (32 * 8) -#endif - - lw t0, 0(sp) - fscsr t0 - addi sp, sp, 4 -#endif /* __riscv_flen */ - - /* Pop PC from stack and set MEPC */ - lw t0, 0 * 4(sp) - csrw mepc, t0 - - /* Pop mstatus from stack and set it */ - lw t0, 29 * 4(sp) - csrw mstatus, t0 - - /* Interrupt still disable here */ - /* Restore Registers from Stack */ - lw x1, 1 * 4(sp) /* RA */ - lw x5, 2 * 4(sp) - lw x6, 3 * 4(sp) - lw x7, 4 * 4(sp) - lw x8, 5 * 4(sp) - lw x9, 6 * 4(sp) - lw x10, 7 * 4(sp) - lw x11, 8 * 4(sp) - lw x12, 9 * 4(sp) - lw x13, 10 * 4(sp) - lw x14, 11 * 4(sp) - lw x15, 12 * 4(sp) - lw x16, 13 * 4(sp) - lw x17, 14 * 4(sp) - lw x18, 15 * 4(sp) - lw x19, 16 * 4(sp) - lw x20, 17 * 4(sp) - lw x21, 18 * 4(sp) - lw x22, 19 * 4(sp) - lw x23, 20 * 4(sp) - lw x24, 21 * 4(sp) - lw x25, 22 * 4(sp) - lw x26, 23 * 4(sp) - lw x27, 24 * 4(sp) - lw x28, 25 * 4(sp) - lw x29, 26 * 4(sp) - lw x30, 27 * 4(sp) - lw x31, 28 * 4(sp) - addi sp, sp, (30 * 4) - - mret - - .size _tx_thread_schedule, . - _tx_thread_schedule - -/* } */ diff --git a/ports/xuantie/e906/gnu/src/tx_thread_system_return.S b/ports/xuantie/e906/gnu/src/tx_thread_system_return.S deleted file mode 100644 index 598bc283..00000000 --- a/ports/xuantie/e906/gnu/src/tx_thread_system_return.S +++ /dev/null @@ -1,78 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Thread */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - .section .text -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_system_return RISC-V64/GNU */ -/* 6.2.1 */ -/* AUTHOR */ -/* */ -/* Scott Larson, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function is target processor specific. It is used to transfer */ -/* control from a thread back to the system. Only a minimal context */ -/* is saved since the compiler assumes temp registers are going to get */ -/* slicked by a function call anyway. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_thread_schedule Thread scheduling loop */ -/* */ -/* CALLED BY */ -/* */ -/* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ -/**************************************************************************/ -/* VOID _tx_thread_system_return(VOID) -{ */ - .align 3 - .global _tx_thread_system_return - .type _tx_thread_system_return, @function -_tx_thread_system_return: - li t0, 0xE080100C - lb t1, (t0) - li t2, 0x01 - or t1, t1, t2 - sb t1, (t0) - - fence - ret - .size _tx_thread_system_return, . - _tx_thread_system_return - -/* } */ diff --git a/ports/xuantie/e906/gnu/src/tx_timer_interrupt.c b/ports/xuantie/e906/gnu/src/tx_timer_interrupt.c deleted file mode 100644 index aea1119b..00000000 --- a/ports/xuantie/e906/gnu/src/tx_timer_interrupt.c +++ /dev/null @@ -1,125 +0,0 @@ -/*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * - * This program and the accompanying materials are made available under the - * terms of the MIT License which is available at - * https://opensource.org/licenses/MIT. - * - * SPDX-License-Identifier: MIT - **************************************************************************/ - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Timer */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - -#define TX_SOURCE_CODE - -/* Include necessary system files. */ - -#include "tx_api.h" -#include "tx_timer.h" -#include "tx_thread.h" - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_timer_interrupt RISC-V64/GNU */ -/* 6.2.1 */ -/* AUTHOR */ -/* */ -/* Scott Larson, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function processes the hardware timer interrupt. This */ -/* processing includes incrementing the system clock and checking for */ -/* time slice and/or timer expiration. If either is found, the */ -/* interrupt context save/restore functions are called along with the */ -/* expiration functions. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_timer_expiration_process Timer expiration processing */ -/* _tx_thread_time_slice Time slice interrupted thread */ -/* */ -/* CALLED BY */ -/* */ -/* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ -/**************************************************************************/ -VOID _tx_timer_interrupt(VOID) -{ - /* Increment system clock. */ - _tx_timer_system_clock++; - - /* Test for time-slice expiration. */ - if (_tx_timer_time_slice) - { - /* Decrement the time_slice. */ - _tx_timer_time_slice--; - /* Check for expiration. */ - if (_tx_timer_time_slice == 0) - { - /* Set the time-slice expired flag. */ - _tx_timer_expired_time_slice = TX_TRUE; - } - } - - /* Test for timer expiration. */ - if (*_tx_timer_current_ptr) - { - /* Set expiration flag. */ - _tx_timer_expired = TX_TRUE; - } - else - { - /* No timer expired, increment the timer pointer. */ - _tx_timer_current_ptr++; - /* Check for wrap-around. */ - if (_tx_timer_current_ptr == _tx_timer_list_end) - { - /* Wrap to beginning of list. */ - _tx_timer_current_ptr = _tx_timer_list_start; - } - } - - /* See if anything has expired. */ - if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) - { - /* Did a timer expire? */ - if (_tx_timer_expired) - { - /* Process timer expiration. */ - _tx_timer_expiration_process(); - } - - /* Did time slice expire? */ - if (_tx_timer_expired_time_slice) - { - /* Time slice interrupted thread. */ - _tx_thread_time_slice(); - } - } -} From 888f7a42b08187720cd356a3cf95caf119dbdf3c Mon Sep 17 00:00:00 2001 From: Francisco Manuel Merino Torres Date: Thu, 26 Feb 2026 10:49:23 +0100 Subject: [PATCH 12/19] Added a RISC-V32 architecture port layer for Clang. --- cmake/riscv32-clang-unknown-elf.cmake | 29 ++ cmake/riscv32_clang.cmake | 18 + ports/risc-v32/clang/CMakeLists.txt | 19 + ports/risc-v32/clang/README.md | 58 +++ .../clang/example_build/qemu_virt/board.c | 42 ++ .../qemu_virt/build_libthreadx.sh | 7 + .../qemu_virt/build_threadx_sample.sh | 19 + .../clang/example_build/qemu_virt/csr.h | 343 ++++++++++++++ .../example_build/qemu_virt/demo_threadx.c | 393 ++++++++++++++++ .../clang/example_build/qemu_virt/entry.s | 58 +++ .../clang/example_build/qemu_virt/hwtimer.c | 35 ++ .../clang/example_build/qemu_virt/hwtimer.h | 23 + .../clang/example_build/qemu_virt/link.lds | 49 ++ .../clang/example_build/qemu_virt/plic.c | 72 +++ .../clang/example_build/qemu_virt/plic.h | 49 ++ .../clang/example_build/qemu_virt/trap.c | 67 +++ .../qemu_virt/tx_initialize_low_level.S | 177 +++++++ .../clang/example_build/qemu_virt/uart.c | 102 ++++ .../clang/example_build/qemu_virt/uart.h | 22 + ports/risc-v32/clang/inc/tx_port.h | 309 +++++++++++++ ports/risc-v32/clang/readme_threadx.txt | 436 ++++++++++++++++++ .../clang/src/tx_initialize_low_level.S | 118 +++++ .../clang/src/tx_thread_context_restore.S | 416 +++++++++++++++++ .../clang/src/tx_thread_context_save.S | 277 +++++++++++ .../clang/src/tx_thread_interrupt_control.S | 94 ++++ ports/risc-v32/clang/src/tx_thread_schedule.S | 324 +++++++++++++ .../clang/src/tx_thread_stack_build.S | 227 +++++++++ .../clang/src/tx_thread_system_return.S | 174 +++++++ ports/risc-v32/clang/src/tx_timer_interrupt.S | 210 +++++++++ 29 files changed, 4167 insertions(+) create mode 100644 cmake/riscv32-clang-unknown-elf.cmake create mode 100644 cmake/riscv32_clang.cmake create mode 100644 ports/risc-v32/clang/CMakeLists.txt create mode 100644 ports/risc-v32/clang/README.md create mode 100644 ports/risc-v32/clang/example_build/qemu_virt/board.c create mode 100755 ports/risc-v32/clang/example_build/qemu_virt/build_libthreadx.sh create mode 100755 ports/risc-v32/clang/example_build/qemu_virt/build_threadx_sample.sh create mode 100644 ports/risc-v32/clang/example_build/qemu_virt/csr.h create mode 100644 ports/risc-v32/clang/example_build/qemu_virt/demo_threadx.c create mode 100644 ports/risc-v32/clang/example_build/qemu_virt/entry.s create mode 100644 ports/risc-v32/clang/example_build/qemu_virt/hwtimer.c create mode 100644 ports/risc-v32/clang/example_build/qemu_virt/hwtimer.h create mode 100644 ports/risc-v32/clang/example_build/qemu_virt/link.lds create mode 100644 ports/risc-v32/clang/example_build/qemu_virt/plic.c create mode 100644 ports/risc-v32/clang/example_build/qemu_virt/plic.h create mode 100644 ports/risc-v32/clang/example_build/qemu_virt/trap.c create mode 100644 ports/risc-v32/clang/example_build/qemu_virt/tx_initialize_low_level.S create mode 100644 ports/risc-v32/clang/example_build/qemu_virt/uart.c create mode 100644 ports/risc-v32/clang/example_build/qemu_virt/uart.h create mode 100644 ports/risc-v32/clang/inc/tx_port.h create mode 100644 ports/risc-v32/clang/readme_threadx.txt create mode 100644 ports/risc-v32/clang/src/tx_initialize_low_level.S create mode 100644 ports/risc-v32/clang/src/tx_thread_context_restore.S create mode 100644 ports/risc-v32/clang/src/tx_thread_context_save.S create mode 100644 ports/risc-v32/clang/src/tx_thread_interrupt_control.S create mode 100644 ports/risc-v32/clang/src/tx_thread_schedule.S create mode 100644 ports/risc-v32/clang/src/tx_thread_stack_build.S create mode 100644 ports/risc-v32/clang/src/tx_thread_system_return.S create mode 100644 ports/risc-v32/clang/src/tx_timer_interrupt.S diff --git a/cmake/riscv32-clang-unknown-elf.cmake b/cmake/riscv32-clang-unknown-elf.cmake new file mode 100644 index 00000000..eb520962 --- /dev/null +++ b/cmake/riscv32-clang-unknown-elf.cmake @@ -0,0 +1,29 @@ +# Toolchain settings +set(CMAKE_C_COMPILER clang-18) +set(CMAKE_CXX_COMPILER clang++-18) +#set(AS llvm-as) +#set(AR llvm-ar) +#set(OBJCOPY llvm-objcopy) +#set(OBJDUMP llvm-objdump-18) +#set(SIZE llvm-size) + +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY) + +# this makes the test compiles use static library option so that we don't need to pre-set linker flags and scripts +set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) + +set(CMAKE_C_FLAGS "${CFLAGS}" CACHE INTERNAL "c compiler flags") +set(CMAKE_CXX_FLAGS "${CXXFLAGS}" CACHE INTERNAL "cxx compiler flags") +set(CMAKE_ASM_FLAGS "${ASFLAGS} -D__ASSEMBLER__" CACHE INTERNAL "asm compiler flags") +set(CMAKE_EXE_LINKER_FLAGS "${LDFLAGS}" CACHE INTERNAL "exe link flags") + +SET(CMAKE_C_FLAGS_DEBUG "--target=riscv32 -march=rv32im_zicsr_zicntr -mabi=ilp32 -g" CACHE INTERNAL "c debug compiler flags") +SET(CMAKE_CXX_FLAGS_DEBUG "--target=riscv32 -march=rv32im_zicsr_zicntr -mabi=ilp32 -g" CACHE INTERNAL "cxx debug compiler flags") +SET(CMAKE_ASM_FLAGS_DEBUG "--target=riscv32 -march=rv32im_zicsr_zicntr -mabi=ilp32 -g" CACHE INTERNAL "asm debug compiler flags") + +SET(CMAKE_C_FLAGS_RELEASE "--target=riscv32 -march=rv32im_zicsr_zicntr -mabi=ilp32 -O3" CACHE INTERNAL "c release compiler flags") +SET(CMAKE_CXX_FLAGS_RELEASE "--target=riscv32 -march=rv32im_zicsr_zicntr -mabi=ilp32 -O3" CACHE INTERNAL "cxx release compiler flags") +SET(CMAKE_ASM_FLAGS_RELEASE "--target=riscv32 -march=rv32im_zicsr_zicntr -mabi=ilp32" CACHE INTERNAL "asm release compiler flags") diff --git a/cmake/riscv32_clang.cmake b/cmake/riscv32_clang.cmake new file mode 100644 index 00000000..97acd832 --- /dev/null +++ b/cmake/riscv32_clang.cmake @@ -0,0 +1,18 @@ +# Name of the target +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_PROCESSOR risc-v32) + +IF(DEFINED $ENV{GCC_INSTALL_PREFIX}) + SET(GCC_INSTALL_PREFIX "$ENV{GCC_INSTALL_PREFIX}" CACHE INTERNAL "" FORCE) +ELSE() + SET(GCC_INSTALL_PREFIX "/opt/riscv_rv32ima" CACHE INTERNAL "" FORCE) +ENDIF() + +set(THREADX_ARCH "risc-v32") +set(THREADX_TOOLCHAIN "clang") +set(ARCH_FLAGS "--sysroot=${GCC_INSTALL_PREFIX}/riscv32-unknown-elf --target=riscv32 -g -march=rv32ima_zicsr -mabi=ilp32") +set(CFLAGS "${ARCH_FLAGS}") +set(ASFLAGS "${ARCH_FLAGS}") +set(LDFLAGS "--no-dynamic-linker -m elf32lriscv -static -nostdlib") + +include(${CMAKE_CURRENT_LIST_DIR}/riscv32-clang-unknown-elf.cmake) diff --git a/ports/risc-v32/clang/CMakeLists.txt b/ports/risc-v32/clang/CMakeLists.txt new file mode 100644 index 00000000..9b725103 --- /dev/null +++ b/ports/risc-v32/clang/CMakeLists.txt @@ -0,0 +1,19 @@ + +target_sources(${PROJECT_NAME} + PRIVATE + # {{BEGIN_TARGET_SOURCES}} + ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S + # {{END_TARGET_SOURCES}} +) + +target_include_directories(${PROJECT_NAME} + PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/inc +) diff --git a/ports/risc-v32/clang/README.md b/ports/risc-v32/clang/README.md new file mode 100644 index 00000000..7a4d495c --- /dev/null +++ b/ports/risc-v32/clang/README.md @@ -0,0 +1,58 @@ +# RISCV32 clang port + +This is basically a copy of the RISC64 gnu port. +The only major modification was changing the load double word (ld) +and store double double (sd) word with load word (ld) and store word (sd). + +I also added support for semihosting so the example can be executed on QEMU. + +## How to build + +cd to the folder where this repo is cloned and run the following commands: + +``` +cd /threadx/ports/risc-v32/clang/example_build/qemu_virt +./build_libthreadx.sh +./build_threadx_sample.sh +``` + +The first script will build the ThreadX libraries. +You can find the library in /build/libthreadx.a. + +The second script will build the demo application. +You can find the demo application in /ports/risc-v32/clang/example_build/qemu_virt/build/demo_threadx.elf + +## How to run using QEMU + +cd to the folder where this repo is cloned and run the following command: + +``` +docker run --rm -it -p 1234:1234 -v $(pwd):/threadx -w /threadx ghcr.io/quintauris-tech/qemu-system-riscv32-v10:latest bash +``` + +The commands assumes that this repo is clone into a folder named "threadx" + +``` +cd /threadx/ports/risc-v32/clang/example_build/qemu_virt + +qemu-system-riscv32 -machine virt -m 16M -bios ./build/demo_threadx.elf -display none -chardev stdio,id=stdio0 -semihosting-config enable=on,userspace=on,chardev=stdio0 -gdb tcp::1234 +``` + +This should print output from different threads. In the QEMU output you should see output like the following: + +``` +[Thread] : thread_xxxx_entry is here! +``` + +You can use option -S with qemu-system-riscv32 to debug. + +In this case run debugger as /opt/riscv_rv32ima_zicsr/bin/riscv32-unknown-elf-gdb /ports/risc-v32/gnu/example_build/qemu_virt/build/demo_threadx.elf + +``` +target remote :1234 +``` + +to connect to the target. Enter 'c' to continue execution. + + + \ No newline at end of file diff --git a/ports/risc-v32/clang/example_build/qemu_virt/board.c b/ports/risc-v32/clang/example_build/qemu_virt/board.c new file mode 100644 index 00000000..47f828d4 --- /dev/null +++ b/ports/risc-v32/clang/example_build/qemu_virt/board.c @@ -0,0 +1,42 @@ +/*************************************************************************** + * Copyright (c) 2026 Quintauris + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#include "plic.h" +#include "hwtimer.h" +#include "uart.h" +#include +#include + +void *memset(void *des, int c,size_t n) +{ + if((des == NULL) || n <=0) + return (void*)des; + char* t = (char*)des; + int i; + for(i=0;i + +static inline uint32_t riscv_get_core() +{ + uint32_t x; + asm volatile("csrr %0, mhartid" : "=r" (x) ); + return x; +} + +static inline uint32_t riscv_get_mstatus() +{ + uint32_t x; + asm volatile("csrr %0, mstatus" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_mstatus(uint32_t x) +{ + asm volatile("csrw mstatus, %0" : : "r" (x)); +} + +static inline void riscv_writ_mepc(uint32_t x) +{ + asm volatile("csrw mepc, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_sstatus() +{ + uint32_t x; + asm volatile("csrr %0, sstatus" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_sstatus(uint32_t x) +{ + asm volatile("csrw sstatus, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_sip() +{ + uint32_t x; + asm volatile("csrr %0, sip" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_sip(uint32_t x) +{ + asm volatile("csrw sip, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_sie() +{ + uint32_t x; + asm volatile("csrr %0, sie" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_sie(uint32_t x) +{ + asm volatile("csrw sie, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_mie() +{ + uint32_t x; + asm volatile("csrr %0, mie" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_mie(uint32_t x) +{ + asm volatile("csrw mie, %0" : : "r" (x)); +} + +static inline void riscv_writ_sepc(uint32_t x) +{ + asm volatile("csrw sepc, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_sepc() +{ + uint32_t x; + asm volatile("csrr %0, sepc" : "=r" (x) ); + return x; +} + +static inline uint32_t riscv_get_medeleg() +{ + uint32_t x; + asm volatile("csrr %0, medeleg" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_medeleg(uint32_t x) +{ + asm volatile("csrw medeleg, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_mideleg() +{ + uint32_t x; + asm volatile("csrr %0, mideleg" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_mideleg(uint32_t x) +{ + asm volatile("csrw mideleg, %0" : : "r" (x)); +} + +static inline void riscv_writ_stvec(uint32_t x) +{ + asm volatile("csrw stvec, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_stvec() +{ + uint32_t x; + asm volatile("csrr %0, stvec" : "=r" (x) ); + return x; +} + +static inline uint32_t riscv_get_stimecmp() +{ + uint32_t x; + asm volatile("csrr %0, 0x14d" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_stimecmp(uint32_t x) +{ + asm volatile("csrw 0x14d, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_menvcfg() +{ + uint32_t x; + asm volatile("csrr %0, 0x30a" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_menvcfg(uint32_t x) +{ + asm volatile("csrw 0x30a, %0" : : "r" (x)); +} + +static inline void riscv_writ_pmpcfg0(uint32_t x) +{ + asm volatile("csrw pmpcfg0, %0" : : "r" (x)); +} + +static inline void riscv_writ_pmpaddr0(uint32_t x) +{ + asm volatile("csrw pmpaddr0, %0" : : "r" (x)); +} + +static inline void riscv_writ_satp(uint32_t x) +{ + asm volatile("csrw satp, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_satp() +{ + uint32_t x; + asm volatile("csrr %0, satp" : "=r" (x) ); + return x; +} + +static inline uint32_t riscv_get_scause() +{ + uint32_t x; + asm volatile("csrr %0, scause" : "=r" (x) ); + return x; +} + +static inline uint32_t riscv_get_stval() +{ + uint32_t x; + asm volatile("csrr %0, stval" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_mcounteren(uint32_t x) +{ + asm volatile("csrw mcounteren, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_mcounteren() +{ + uint32_t x; + asm volatile("csrr %0, mcounteren" : "=r" (x) ); + return x; +} + +static inline uint32_t riscv_get_time() +{ + uint32_t x; + asm volatile("csrr %0, time" : "=r" (x) ); + return x; +} + +static inline void riscv_sintr_on() +{ + uint32_t sstatus = riscv_get_sstatus(); + sstatus |= SSTATUS_SIE; + riscv_writ_sstatus(sstatus); +} + +static inline void riscv_sintr_off() +{ + uint32_t sstatus = riscv_get_sstatus(); + sstatus &= (~SSTATUS_SIE); + riscv_writ_sstatus(sstatus); +} + +static inline int riscv_sintr_get() +{ + uint32_t x = riscv_get_sstatus(); + return (x & SSTATUS_SIE) != 0; +} + +static inline void riscv_sintr_restore(int x) +{ + if(x) + riscv_sintr_on(); + else + riscv_sintr_off(); +} + +static inline void riscv_mintr_on() +{ + uint32_t mstatus = riscv_get_mstatus(); + mstatus |= MSTATUS_MIE; + riscv_writ_mstatus(mstatus); +} + +static inline void riscv_mintr_off() +{ + uint32_t mstatus = riscv_get_mstatus(); + mstatus &= (~MSTATUS_MIE); + riscv_writ_mstatus(mstatus); +} + +static inline int riscv_mintr_get() +{ + uint32_t x = riscv_get_mstatus(); + return (x & MSTATUS_MIE) != 0; +} + +static inline void riscv_mintr_restore(int x) +{ + if(x) + riscv_mintr_on(); + else + riscv_mintr_off(); +} + +static inline uint32_t riscv_get_sp() +{ + uint32_t x; + asm volatile("mv %0, sp" : "=r" (x) ); + return x; +} + +// read and write tp, the thread pointer, which xv6 uses to hold +// this core's hartid (core number), the index into cpus[]. +static inline uint32_t riscv_get_tp() +{ + uint32_t x; + asm volatile("mv %0, tp" : "=r" (x) ); + return x; +} + +static inline void riscv_writ_tp(uint32_t x) +{ + asm volatile("mv tp, %0" : : "r" (x)); +} + +static inline uint32_t riscv_get_ra() +{ + uint32_t x; + asm volatile("mv %0, ra" : "=r" (x) ); + return x; +} + +// flush the TLB. +static inline void sfence_vma() +{ + // the zero, zero means flush all TLB entries. + asm volatile("sfence.vma zero, zero"); +} + +#endif // __ASSEMBLER__ + +#endif diff --git a/ports/risc-v32/clang/example_build/qemu_virt/demo_threadx.c b/ports/risc-v32/clang/example_build/qemu_virt/demo_threadx.c new file mode 100644 index 00000000..59aa1640 --- /dev/null +++ b/ports/risc-v32/clang/example_build/qemu_virt/demo_threadx.c @@ -0,0 +1,393 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" +#include "uart.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + +char *_to_str(ULONG val) +{ + static char buf[11]; /* 10 digits max + '\0' */ + char *p = buf + sizeof(buf) - 1; + + *p = '\0'; + do { + *--p = '0' + (val % 10); + val /= 10; + } while (val); + + return p; +} + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + CHAR *pointer = TX_NULL; + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + puts("[Thread] : thread_0_entry is here!"); + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + puts("[Thread] : thread_1_entry is here!"); + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) { + puts("[Thread 1] ERROR: Failed to send message!"); + break; + } + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + puts("[Thread] : thread_2_entry is here!"); + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)){ + puts("[Thread 2] ERROR: Failed to receive message ! Expected # "); + uart_puts(_to_str(thread_2_messages_received)); + puts(", but got # "); + uart_puts(_to_str(received_message)); + break; + } + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + puts("[Thread] : thread_3_and_4_entry is here!"); + + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + puts("[Thread] : thread_5_entry is here!"); + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + puts("[Thread] : thread_6_and_7_entry is here!"); + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/risc-v32/clang/example_build/qemu_virt/entry.s b/ports/risc-v32/clang/example_build/qemu_virt/entry.s new file mode 100644 index 00000000..9b202ca1 --- /dev/null +++ b/ports/risc-v32/clang/example_build/qemu_virt/entry.s @@ -0,0 +1,58 @@ + +.section .text +.align 4 +.global _start +.extern main +.extern _sysstack_start +.extern _bss_start +.extern _bss_end +_start: + csrr t0, mhartid + bne t0, zero, 1f + li x1, 0 + li x2, 0 + li x3, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10, 0 + li x11, 0 + li x12, 0 + li x13, 0 + li x14, 0 + li x15, 0 + li x16, 0 + li x17, 0 + li x18, 0 + li x19, 0 + li x20, 0 + li x21, 0 + li x22, 0 + li x23, 0 + li x24, 0 + li x25, 0 + li x26, 0 + li x27, 0 + li x28, 0 + li x29, 0 + li x30, 0 + li x31, 0 + la t0, _sysstack_start + li t1, 0x1000 + add sp, t0, t1 + la t0, _bss_start + la t1, _bss_end +_bss_clean_start: + bgeu t0, t1, _bss_clean_end + sb zero, 0(t0) + addi t0, t0, 1 + j _bss_clean_start +_bss_clean_end: + call main +1: + /* todo smp */ + wfi + j 1b diff --git a/ports/risc-v32/clang/example_build/qemu_virt/hwtimer.c b/ports/risc-v32/clang/example_build/qemu_virt/hwtimer.c new file mode 100644 index 00000000..b5335cf3 --- /dev/null +++ b/ports/risc-v32/clang/example_build/qemu_virt/hwtimer.c @@ -0,0 +1,35 @@ +/*************************************************************************** + * Copyright (c) 2026 Quintauris + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#include "tx_port.h" +#include "csr.h" +#include "hwtimer.h" + +#define CLINT (0x02000000L) +#define CLINT_TIME (CLINT+0xBFF8) +#define CLINT_TIMECMP(hart_id) (CLINT+0x4000+8*(hart_id)) + + +int hwtimer_init(void) +{ + int hart = riscv_get_core(); + uint64_t time = *((uint64_t*)CLINT_TIME); + *((uint64_t*)CLINT_TIMECMP(hart)) = time + TICKNUM_PER_TIMER; + return 0; +} + +int hwtimer_handler(void) +{ + int hart = riscv_get_core(); + uint64_t time = *((uint64_t*)CLINT_TIME); + *((uint64_t*)CLINT_TIMECMP(hart)) = time + TICKNUM_PER_TIMER; + return 0; +} + diff --git a/ports/risc-v32/clang/example_build/qemu_virt/hwtimer.h b/ports/risc-v32/clang/example_build/qemu_virt/hwtimer.h new file mode 100644 index 00000000..e27a7578 --- /dev/null +++ b/ports/risc-v32/clang/example_build/qemu_virt/hwtimer.h @@ -0,0 +1,23 @@ + +/*************************************************************************** + * Copyright (c) 2026 Quintauris + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#ifndef RISCV_HWTIMER_H +#define RISCV_HWTIMER_H + +#include + +#define TICKNUM_PER_SECOND 10000000 +#define TICKNUM_PER_TIMER (TICKNUM_PER_SECOND / 10) + +int hwtimer_init(void); +int hwtimer_handler(void); + +#endif diff --git a/ports/risc-v32/clang/example_build/qemu_virt/link.lds b/ports/risc-v32/clang/example_build/qemu_virt/link.lds new file mode 100644 index 00000000..522f90d9 --- /dev/null +++ b/ports/risc-v32/clang/example_build/qemu_virt/link.lds @@ -0,0 +1,49 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY( _start ) + +SECTIONS +{ + /* + * ensure that entry.S / _entry is at 0x80000000, + * where qemu's -kernel jumps. + */ + . = 0x80000000; + + .text : { + *(.text .text.*) + . = ALIGN(0x1000); + PROVIDE(etext = .); + } + + .rodata : { + . = ALIGN(16); + *(.srodata .srodata.*) /* do not need to distinguish this from .rodata */ + . = ALIGN(16); + *(.rodata .rodata.*) + } + + .data : { + . = ALIGN(16); + *(.sdata .sdata.*) /* do not need to distinguish this from .data */ + . = ALIGN(16); + *(.data .data.*) + } + + .bss : { + . = ALIGN(16); + _bss_start = .; + *(.sbss .sbss.*) /* do not need to distinguish this from .bss */ + . = ALIGN(16); + *(.bss .bss.*) + _bss_end = .; + } + + .stack : { + . = ALIGN(4096); + _sysstack_start = .; + . += 0x1000; + _sysstack_end = .; + } + + PROVIDE(_end = .); +} diff --git a/ports/risc-v32/clang/example_build/qemu_virt/plic.c b/ports/risc-v32/clang/example_build/qemu_virt/plic.c new file mode 100644 index 00000000..01e5c71a --- /dev/null +++ b/ports/risc-v32/clang/example_build/qemu_virt/plic.c @@ -0,0 +1,72 @@ +#include "plic.h" +#include +irq_callback callbacks[MAX_CALLBACK_NUM]; + +void plic_irq_enable(int irqno) +{ + int hart = riscv_get_core(); + *(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) | (1 << irqno)); + return; +} + +void plic_irq_disable(int irqno) +{ + int hart = riscv_get_core(); + *(uint32_t*)PLIC_MENABLE(hart) = (*(uint32_t*)PLIC_MENABLE(hart) & (~(1 << irqno))); + return; +} + +void plic_prio_set(int irqno, int prio) +{ + PLIC_SET_PRIO(irqno, prio); +} + +int plic_prio_get(int irqno) +{ + return PLIC_GET_PRIO(irqno); +} + +int plic_register_callback(int irqno, irq_callback callback) +{ + if(!(irqno >=0 && irqno < MAX_CALLBACK_NUM)) + return -1; + callbacks[irqno] = callback; + return 0; +} + +int plic_unregister_callback(int irqno) +{ + return plic_register_callback(irqno, NULL); +} + +int plic_init(void) +{ + for(int i=0;i + +#define PLIC 0x0c000000L +#define PLIC_PRIORITY (PLIC + 0x0) +#define PLIC_PENDING (PLIC + 0x1000) +#define PLIC_MENABLE(hart) (PLIC + 0x2000 + (hart)*0x100) +#define PLIC_SENABLE(hart) (PLIC + 0x2080 + (hart)*0x100) +#define PLIC_MPRIORITY(hart) (PLIC + 0x200000 + (hart)*0x2000) +#define PLIC_SPRIORITY(hart) (PLIC + 0x201000 + (hart)*0x2000) +#define PLIC_MCLAIM(hart) (PLIC + 0x200004 + (hart)*0x2000) +#define PLIC_SCLAIM(hart) (PLIC + 0x201004 + (hart)*0x2000) +#define PLIC_MCOMPLETE(hart) (PLIC + 0x200004 + (hart)*0x2000) +#define PLIC_SCOMPLETE(hart) (PLIC + 0x201004 + (hart)*0x2000) + + +#define PLIC_GET_PRIO(irqno) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4)) +#define PLIC_SET_PRIO(irqno, prio) (*(uint32_t *)(PLIC_PRIORITY + (irqno)*4) = (prio)) + +#define MAX_CALLBACK_NUM 128 +typedef int (*irq_callback)(int irqno); + +void plic_irq_enable(int irqno); +void plic_irq_disable(int irqno); +int plic_prio_get(int irqno); +void plic_prio_set(int irqno, int prio); +int plic_register_callback(int irqno, irq_callback callback); +int plic_unregister_callback(int irqno); +int plic_init(void); +int plic_claim(void); +void plic_complete(int irqno); + +int plic_irq_intr(void); + +#endif + diff --git a/ports/risc-v32/clang/example_build/qemu_virt/trap.c b/ports/risc-v32/clang/example_build/qemu_virt/trap.c new file mode 100644 index 00000000..a2733e02 --- /dev/null +++ b/ports/risc-v32/clang/example_build/qemu_virt/trap.c @@ -0,0 +1,67 @@ +#include "csr.h" +#include +#include "uart.h" +#include "hwtimer.h" +#include "plic.h" +#include +#include + +#define OS_IS_INTERUPT(mcause) (mcause & 0x80000000u) +#define OS_IS_EXCEPTION(mcause) (~(OS_IS_INTERUPT)) +#define OS_IS_TICK_INT(mcause) (mcause == 0x80000007u) +#define OS_IS_SOFT_INT(mcause) (mcause == 0x80000003u) +#define OS_IS_EXT_INT(mcause) (mcause == 0x8000000bu) +#define OS_IS_TRAP_USER(mcause) (mcause == 0x0000000bu) +extern void _tx_timer_interrupt(void); + +extern int uart_putc(int ch); + +static void print_hex(uintptr_t val) +{ + char digits[] = "0123456789ABCDEF"; + uart_putc('0'); + uart_putc('x'); + for(int i = (sizeof(uintptr_t)*2) - 1; i >= 0; i--) { + int d = (val >> (i*4)) & 0xF; + uart_putc(digits[d]); + } + uart_putc('\n'); +} + +void trap_handler(uintptr_t mcause, uintptr_t mepc, uintptr_t mtval) +{ + // uart_puts("DEBUG : threadx/ports/risc-v32/gnu/example_build/qemu_virt/trap.c, trap_handler\n"); + if(OS_IS_INTERUPT(mcause)) + { + if(OS_IS_TICK_INT(mcause)) + { + hwtimer_handler(); + _tx_timer_interrupt(); + } + else if(OS_IS_EXT_INT(mcause)) + { + int ret = plic_irq_intr(); + if(ret) + { + puts("[INTERRUPT]: handler irq error!"); + while(1) ; + } + } + else + { + puts("[INTERRUPT]: now can't deal with the interrupt!"); + while(1) ; + } + } + else + { + puts("[EXCEPTION] : Unkown Error!!"); + puts("mcause:"); + print_hex(mcause); + puts("mepc:"); + print_hex(mepc); + puts("mtval:"); + print_hex(mtval); + while(1) ; + } +} diff --git a/ports/risc-v32/clang/example_build/qemu_virt/tx_initialize_low_level.S b/ports/risc-v32/clang/example_build/qemu_virt/tx_initialize_low_level.S new file mode 100644 index 00000000..a207d0ae --- /dev/null +++ b/ports/risc-v32/clang/example_build/qemu_virt/tx_initialize_low_level.S @@ -0,0 +1,177 @@ +/*************************************************************************** + * Copyright (c) 2026 Quintauris + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#include "csr.h" +#include "tx_port.h" + + .section .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* trap_entry RISC-V32/GNU */ +/* 6.4.x */ +/* AUTHOR */ +/* */ +/* Francisco Merino, Quintauris */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for riscv processor trap handle */ +/* It will do the contex save and call c trap_handler and do contex */ +/* load */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* trap_handler */ +/* */ +/* CALLED BY */ +/* */ +/* hardware exception */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 02-02-2026 Francisco Merino Adapted for RV32 Clang */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + .global trap_entry + .extern trap_handler + .extern _tx_thread_context_restore + trap_entry: +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, -65*REGBYTES // Allocate space for all registers - with floating point enabled +#else + addi sp, sp, -32*REGBYTES // Allocate space for all registers - without floating point enabled +#endif + + STORE x1, 28*REGBYTES(sp) // Store RA, 28*REGBYTES(because call will override ra [ra is a calle register in riscv]) + + call _tx_thread_context_save + + csrr a0, mcause + csrr a1, mepc + csrr a2, mtval + addi sp, sp, -4 + sw ra, 0(sp) + call trap_handler + lw ra, 0(sp) + addi sp, sp, 4 + call _tx_thread_context_restore + // it will nerver return +_err: + wfi + j _err + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level RISC-V32/GNU */ +/* 6.4.x */ +/* AUTHOR */ +/* */ +/* Francisco Merino, Quintauris */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 26-02-2026 Francisco Merino Adapted for RV32 Clang */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ +// .global _tx_initialize_low_level + .weak _tx_initialize_low_level + .extern _end + .extern board_init +_tx_initialize_low_level: + +/* debug print + .section .rodata +debug_str_init: + .string "DEBUG : threadx/ports/risc-v32/gnu/example_build/qemu_virt/tx_initialize_low_level.S, _tx_initialize_low_level\n" +*/ + .section .text + + la t0, _tx_thread_system_stack_ptr + sw sp, 0(t0) // Save system stack pointer + + la t0, _end // Pickup first free address + la t1, _tx_initialize_unused_memory + sw t0, 0(t1) // Save unused memory address + li t0, MSTATUS_MIE + csrrc zero, mstatus, t0 // clear MSTATUS_MIE bit + li t0, (MSTATUS_MPP_M | MSTATUS_MPIE ) + csrrs zero, mstatus, t0 // set MSTATUS_MPP, MPIE bit + li t0, (MIE_MTIE | MIE_MSIE | MIE_MEIE) + csrrs zero, mie, t0 // set mie +#ifdef __riscv_flen + li t0, MSTATUS_FS + csrrs zero, mstatus, t0 // set MSTATUS_FS bit to open f/d isa in riscv + fscsr x0 +#endif + addi sp, sp, -4 + sw ra, 0(sp) + call board_init +/* debug print + la a0, debug_str_init + call uart_puts +*/ + lw ra, 0(sp) + addi sp, sp, 4 + la t0, trap_entry + csrw mtvec, t0 + ret diff --git a/ports/risc-v32/clang/example_build/qemu_virt/uart.c b/ports/risc-v32/clang/example_build/qemu_virt/uart.c new file mode 100644 index 00000000..a175b7d2 --- /dev/null +++ b/ports/risc-v32/clang/example_build/qemu_virt/uart.c @@ -0,0 +1,102 @@ +#include "uart.h" +#include "csr.h" +#include "plic.h" +#include + +// the UART control registers are memory-mapped +// at address UART0. this macro returns the +// address of one of the registers. +#define Reg(reg) ((volatile unsigned char *)(UART0 + (reg))) + +// the UART control registers. +// some have different meanings for +// read vs write. +// see http://byterunner.com/16550.html +#define RHR 0 // receive holding register (for input bytes) +#define THR 0 // transmit holding register (for output bytes) +#define IER 1 // interrupt enable register +#define IER_RX_ENABLE (1<<0) +#define IER_TX_ENABLE (1<<1) +#define FCR 2 // FIFO control register +#define FCR_FIFO_ENABLE (1<<0) +#define FCR_FIFO_CLEAR (3<<1) // clear the content of the two FIFOs +#define ISR 2 // interrupt status register +#define LCR 3 // line control register +#define LCR_EIGHT_BITS (3<<0) +#define LCR_BAUD_LATCH (1<<7) // special mode to set baud rate +#define LSR 5 // line status register +#define LSR_RX_READY (1<<0) // input is waiting to be read from RHR +#define LSR_TX_IDLE (1<<5) // THR can accept another character to send + +#define ReadReg(reg) (*(Reg(reg))) +#define WriteReg(reg, v) (*(Reg(reg)) = (v)) + +int uart_init(void) +{ + // disable interrupts. + WriteReg(IER, 0x00); + + // special mode to set baud rate. + WriteReg(LCR, LCR_BAUD_LATCH); + + // LSB for baud rate of 38.4K. + WriteReg(0, 0x03); + + // MSB for baud rate of 38.4K. + WriteReg(1, 0x00); + + // leave set-baud mode, + // and set word length to 8 bits, no parity. + WriteReg(LCR, LCR_EIGHT_BITS); + + // reset and enable FIFOs. + WriteReg(FCR, FCR_FIFO_ENABLE | FCR_FIFO_CLEAR); + + // enable transmit and receive interrupts. + // WriteReg(IER, IER_TX_ENABLE | IER_RX_ENABLE); + + //enable UART0 in PLIC + plic_irq_enable(UART0_IRQ); + + //set UART0 priority in PLIC + plic_prio_set(UART0_IRQ, 1); + + //register callback for UART0 + //plic_register_callback(UART0_IRQ, uart_intr); + puts("[UART0] : Uart Init Done, this is Test output!"); + return 0; +} + +void uart_putc_nolock(int ch) +{ + // wait for Transmit Holding Empty to be set in LSR. + while((ReadReg(LSR) & LSR_TX_IDLE) == 0) + ; + WriteReg(THR, ch); + return; +} + +int uart_putc(int ch) +{ + int intr_enable = riscv_mintr_get(); + riscv_mintr_off(); + uart_putc_nolock(ch); + riscv_mintr_restore(intr_enable); + return 1; +} + +int uart_puts(const char* str) +{ + int i; + int intr_enable = riscv_mintr_get(); + riscv_mintr_off(); + for(i=0;str[i]!=0;i++) + { + uart_putc_nolock(str[i]); + } + uart_putc_nolock('\n'); + riscv_mintr_restore(intr_enable); + return i; +} + + diff --git a/ports/risc-v32/clang/example_build/qemu_virt/uart.h b/ports/risc-v32/clang/example_build/qemu_virt/uart.h new file mode 100644 index 00000000..19e8f73d --- /dev/null +++ b/ports/risc-v32/clang/example_build/qemu_virt/uart.h @@ -0,0 +1,22 @@ +/*************************************************************************** + * Copyright (c) 2024 Microsoft Corporation + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + +#ifndef RISCV_UART_H +#define RISCV_UART_H + +#define UART0 0x10000000L +#define UART0_IRQ 10 + +#define puts uart_puts +int uart_init(void); +int uart_putc(int ch); +void uart_putc_nolock(int ch); +int uart_puts(const char* str); +#endif diff --git a/ports/risc-v32/clang/inc/tx_port.h b/ports/risc-v32/clang/inc/tx_port.h new file mode 100644 index 00000000..81dcdcf7 --- /dev/null +++ b/ports/risc-v32/clang/inc/tx_port.h @@ -0,0 +1,309 @@ +/*************************************************************************** + * Copyright (c) 2025 Quintauris + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h RISC-V32/GNU */ +/* 6.4.x */ +/* */ +/* AUTHOR */ +/* */ +/* Francisco Merino, Quintauris */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 02-26-2026 Francisco Merino Initial Version 6.4.x */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + +#ifdef __ASSEMBLER__ + + +#if __riscv_xlen == 64 +# define SLL32 sllw +# define STORE sd +# define LOAD ld +# define LWU lwu +# define LOG_REGBYTES 3 +#else +# define SLL32 sll +# define STORE sw +# define LOAD lw +# define LWU lw +# define LOG_REGBYTES 2 +#endif +#define REGBYTES (1 << LOG_REGBYTES) + +#else /*not __ASSEMBLER__ */ + +/* Include for memset. */ +#include + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif /* TX_INCLUDE_USER_DEFINE_FILE */ + +#endif /* __ASSEMBLER__ */ + + +/* Define ThreadX basic types for this port. */ + +#define VOID void + +#ifndef __ASSEMBLER__ +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long long ULONG64; +typedef short SHORT; +typedef unsigned short USHORT; +#define ULONG64_DEFINED +#endif /* __ASSEMBLER__ */ + + + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 1024 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX RISC-V port. */ + +#define TX_INT_DISABLE 0x00000000 /* Disable interrupts value */ +#define TX_INT_ENABLE 0x00000008 /* Enable interrupt value */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +/* Expose helper used to perform an atomic read/modify/write of mstatus. + The helper composes and returns the posture per ThreadX contract. */ +#ifndef __ASSEMBLER__ +UINT _tx_thread_interrupt_control(UINT new_posture); +#endif + +#ifdef TX_DISABLE_INLINE + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE __asm__ volatile("csrrci %0, mstatus, 8" : "=r" (interrupt_save) :: "memory"); +#define TX_RESTORE { \ + unsigned long _temp_mstatus; \ + __asm__ volatile( \ + "csrc mstatus, 8\n" \ + "andi %0, %1, 8\n" \ + "csrs mstatus, %0" \ + : "=&r" (_temp_mstatus) \ + : "r" (interrupt_save) \ + : "memory"); \ + } + +#else + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); +#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); + +#endif /* TX_DISABLE_INLINE */ + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifndef __ASSEMBLER__ +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) 2024 Microsoft Corporation. * ThreadX RISC-V32/GNU Version 6.4.2 *"; +#else +extern CHAR _tx_version_id[]; +#endif /* TX_THREAD_INIT */ +#endif /* __ASSEMBLER__ */ + +#endif /* TX_PORT_H */ \ No newline at end of file diff --git a/ports/risc-v32/clang/readme_threadx.txt b/ports/risc-v32/clang/readme_threadx.txt new file mode 100644 index 00000000..caa60986 --- /dev/null +++ b/ports/risc-v32/clang/readme_threadx.txt @@ -0,0 +1,436 @@ + Eclipse Foundation's RTOS, ThreadX for RISC-V32 + + Using the Clang Tools + + +1. Building the ThreadX run-time Library + +Prerequisites +- Install a RISC-V32 bare-metal Clang toolchain +- Install a RISC-V32 bare-metal GNU toolchain with riscv32-unknown-elf prefix +- Common source: https://github.com/riscv-collab/riscv-gnu-toolchain + +Verify the Clang toolchaing: + clang --version + +Verify the GCC toolchain: + riscv32-unknown-elf-gcc --version + riscv32-unknown-elf-objdump --version + +CMake-based build (recommended) + +From the ThreadX top-level directory: + + cmake -Bbuild -GNinja -DCMAKE_TOOLCHAIN_FILE=cmake/riscv32_clang.cmake . + cmake --build ./build/ + +This uses cmake/riscv32_clang.cmake and ports/risc-v32/clang/CMakeLists.txt to +configure the cross-compiler flags and produce the ThreadX run-time library +and example binaries. + +Example build script + +The example demonstration contains a build script. See: + + ports/risc-v32/clang/example_build/qemu_virt/build_libthreadx.sh + +This script builds the library and the demo application kernel.elf. + + +2. Demonstration System (QEMU) + +The provided example is targeted at QEMU's virt platform. After building the +example, the produced kernel.elf can be executed in QEMU: + + qemu-system-riscv32 -nographic -smp 1 -bios none -m 128M -machine virt -kernel kernel.elf + +Typical QEMU features used: +- Single-core CPU +- UART serial console +- PLIC (Platform-Level Interrupt Controller) +- CLINT (Core-Local Interruptor) for timer + + +3. System Initialization + +Entry Point + +The example startup code begins at the _start label in entry.s. This startup +code performs hardware initialization including: +- Check hart ID (only hart 0 continues; others enter WFI loop) +- Zero general-purpose registers +- Set up initial stack pointer +- Clear BSS section +- Jump to main() + +Low-Level Port Initialization (tx_initialize_low_level.S) + +The _tx_initialize_low_level function: +- Saves the system stack pointer to _tx_thread_system_stack_ptr +- Records first free RAM address from __tx_free_memory_start symbol +- Initializes floating-point control/status register (FCSR) if floating point enabled + +Board Initialization (board.c) + +After tx_initialize_low_level returns, main() calls board_init() to: +- Initialize PLIC (Platform-Level Interrupt Controller) +- Initialize UART +- Initialize hardware timer (CLINT) +- Set trap vector (mtvec) to point to trap handler + + +4. Register Usage and Stack Frames + +The RISC-V32 ABI defines t0-t6 and a0-a7 as caller-saved (scratch) registers. +All other registers used by a function must be preserved by the function. + +ThreadX takes advantage of this: when a context switch happens during a +function call, only the non-scratch registers need to be saved. + +Stack Frame Types + +Two types of stack frames exist: + +A. Interrupt Frame (stack type = 1) + Created when an interrupt occurs during thread execution. + Saves all registers including caller-saved registers. + Size: 65*4 = 260 bytes (with FP), or 32*4 = 128 bytes (without FP) + +B. Solicited Frame (stack type = 0) + Created when a thread voluntarily yields via ThreadX service calls. + Saves only callee-saved registers (s0-s11) and mstatus. + Size: 29*4 = 116 bytes (with FP), or 16*4 = 64 bytes (without FP) + + +Stack Layout for Interrupt Frame (with FP enabled): + + Index Offset Register Description + ───────────────────────────────────────────────── + 0 0x00 -- Stack type (1 = interrupt) + 1 0x04 s11 Preserved register + 2 0x08 s10 Preserved register + 3 0x0C s9 Preserved register + 4 0x10 s8 Preserved register + 5 0x14 s7 Preserved register + 6 0x18 s6 Preserved register + 7 0x1C s5 Preserved register + 8 0x20 s4 Preserved register + 9 0x24 s3 Preserved register + 10 0x28 s2 Preserved register + 11 0x2C s1 Preserved register + 12 0x30 s0 Preserved register + 13 0x34 t6 Scratch register + 14 0x38 t5 Scratch register + 15 0x3C t4 Scratch register + 16 0x40 t3 Scratch register + 17 0x44 t2 Scratch register + 18 0x48 t1 Scratch register + 19 0x4C t0 Scratch register + 20 0x50 a7 Argument register + 21 0x54 a6 Argument register + 22 0x58 a5 Argument register + 23 0x5C a4 Argument register + 24 0x60 a3 Argument register + 25 0x64 a2 Argument register + 26 0x68 a1 Argument register + 27 0x6C a0 Argument register + 28 0x70 ra Return address + 29 0x74 -- Reserved + 30 0x78 mepc Machine exception PC + 31-46 0x7C-0xB8 fs0-fs7 Preserved FP registers* + 47-62 0xBC-0xF8 ft0-ft11 Scratch FP registers* + 63 0xFC fcsr FP control/status register + ───────────────────────────────────────────────── + *Note: In ilp32d ABI, FP registers are 8 bytes each, but current + port implementation uses 4-byte indexing which may cause + overlap if fsd/fld are used. + + +5. Interrupt Handling + +Machine Mode Operation + +ThreadX operates in machine mode (M-mode), the highest privilege level. +All interrupts and exceptions trap to machine mode. + +Interrupt Sources + +1. Machine Timer Interrupt (MTI): + - Triggered by CLINT when mtime >= mtimecmp + - Handled by _tx_timer_interrupt (src/tx_timer_interrupt.S) + - Called from trap handler in trap.c + +2. External Interrupts (MEI): + - Routed through PLIC + - Handler in trap.c calls registered ISR callbacks + +3. Software Interrupts (MSI): + - Supported but not actively used in this port + +Interrupt Flow + +1. Hardware trap entry (automatic): + - mepc <- PC (address of interrupted instruction) + - mcause <- exception/interrupt code + - mstatus.MPIE <- mstatus.MIE (save interrupt-enable state) + - mstatus.MIE <- 0 (disable interrupts) + - mstatus.MPP <- Machine mode + - PC <- mtvec (points to trap_entry in entry.s) + +2. Trap entry (entry.s): + - Allocates interrupt stack frame (32*4 or 65*4 bytes depending on FP) + - Saves RA (x1) on stack + - Calls _tx_thread_context_save + +3. Context save (_tx_thread_context_save.S): + - Increments _tx_thread_system_state (nested interrupt counter) + - If nested interrupt: saves remaining registers and returns to ISR + - If first interrupt: saves full context, switches to system stack + +4. Trap handler (trap.c): + - Examines mcause to determine interrupt type + - Dispatches to appropriate handler (_tx_timer_interrupt or PLIC handler) + - Returns to context restore + +5. Context restore (_tx_thread_context_restore.S): + - Decrements _tx_thread_system_state + - Checks if preemption needed + - Restores thread context or switches to next ready thread via scheduler + - Returns to interrupted thread or executes new thread + + +Interrupt Control Macros + +TX_DISABLE and TX_RESTORE macros atomically manage the MIE bit in mstatus: + + TX_DISABLE: Saves and clears MIE bit via csrrci (CSR read-clear immediate) + TX_RESTORE: Restores only MIE bit via csrrs (CSR read-set) + Other mstatus bits remain unchanged + +These are defined in ports/risc-v32/gnu/inc/tx_port.h and use the +_tx_thread_interrupt_control() function. + + +6. Thread Scheduling and Context Switching + +Thread Scheduler (src/tx_thread_schedule.S) + +The scheduler: +1. Enables interrupts while waiting for next thread +2. Spins until _tx_thread_execute_ptr becomes non-NULL +3. Disables interrupts (critical section) +4. Sets _tx_thread_current_ptr = _tx_thread_execute_ptr +5. Increments thread's run count +6. Switches to thread's stack +7. Determines stack frame type and restores context: + - Interrupt frame: full context restored, returns via mret + - Solicited frame: minimal context restored, returns via ret + +Initial Thread Stack Frame (src/tx_thread_stack_build.S) + +New threads start with a fake interrupt frame containing: +- All registers initialized to 0 +- ra (x1) = 0 +- mepc = entry function pointer +- Stack type = 1 (interrupt frame) +- Floating-point registers initialized based on ABI + + +7. Port Configuration and Macros + +Default Configurations (in ports/risc-v32/gnu/inc/tx_port.h): + + TX_MINIMUM_STACK 1024 /* Minimum thread stack size */ + TX_TIMER_THREAD_STACK_SIZE 1024 /* Timer thread stack size */ + TX_TIMER_THREAD_PRIORITY 0 /* Timer thread priority */ + TX_MAX_PRIORITIES 32 /* Must be multiple of 32 */ + +These can be overridden in tx_user.h or on the compiler command line. + + +8. Build Configuration + +CMake Toolchain File: cmake/riscv32_gnu.cmake + +Compiler Flags: + -march=rv32gc RV32 with IMAFD+C extensions + -mabi=ilp32d 32-bit integers/pointers, double-precision FP in registers + -mcmodel=medany ±2GB addressability + -D__ASSEMBLER__ For assembly files + +ABI Selection + +The port uses ilp32d ABI which includes: +- 32-bit integers and pointers +- Double-precision floating-point arguments in registers +- Floating-point registers f0-f31 + +When building with floating-point ABI: +- FP registers and FCSR are saved/restored in context switches +- Stack frames expand from 32*REGBYTES to 65*REGBYTES +- Conditional compilation uses __riscv_float_abi_double / __riscv_float_abi_single + + +9. File Organization + +Port-specific files (ports/risc-v32/gnu/): + +Core assembly files (src/): + - tx_initialize_low_level.S Initial setup and system state + - tx_thread_context_save.S Save context on interrupt entry + - tx_thread_context_restore.S Restore context on interrupt exit + - tx_thread_schedule.S Thread scheduler + - tx_thread_system_return.S Solicited context save for voluntary yield + - tx_thread_stack_build.S Build initial stack frame for new thread + - tx_thread_interrupt_control.S Interrupt enable/disable control + - tx_timer_interrupt.S Timer interrupt handler + +Header file (inc/): + - tx_port.h Port-specific defines and macros + +Example files (example_build/qemu_virt/): + - entry.s Startup code, trap entry point + - board.c, uart.c, hwtimer.c Platform-specific initialization + - plic.c PLIC interrupt controller driver + - trap.c Trap/exception dispatcher + - link.lds Linker script for QEMU virt + - build_libthreadx.sh Build script + + +10. Linker Script Requirements + +The linker script must provide: + +1. Entry point: + ENTRY(_start) + +2. Memory layout: + - .text section (code) + - .rodata section (read-only data) + - .data section (initialized data) + - .bss section (uninitialized data) + +3. Symbols: + - _end: First free memory address (used by ThreadX allocation) + - _bss_start, _bss_end: For zero initialization + - Initial stack space (example: 4KB) + +4. Alignment: + - 16-byte alignment throughout (RISC-V requirement) + +Example from QEMU virt build: + + SECTIONS + { + . = 0x80000000; /* QEMU virt base address */ + + .text : { *(.text .text.*) } + .rodata : { *(.rodata .rodata.*) } + .data : { *(.data .data.*) } + .bss : { *(.bss .bss.*) } + + .stack : { + . = ALIGN(4096); + _sysstack_start = .; + . += 0x1000; /* 4KB initial stack */ + _sysstack_end = .; + } + + PROVIDE(_end = .); + } + + +11. Floating-Point Support + +When building with ilp32d ABI and FP enabled: + +- FP registers f0-f31 and FCSR are saved/restored during context switches +- Stack frames increase from 32*REGBYTES to 65*REGBYTES (128 to 260 bytes) +- MSTATUS.FS (floating-point state) field is set to indicate dirty FP state + +Stack frame differences: +- Without FP: 32*4 = 128 bytes (interrupt), 16*4 = 64 bytes (solicited) +- With FP: 65*4 = 260 bytes (interrupt), 29*4 = 116 bytes (solicited) + + +12. Performance and Debugging + +Performance Optimization + +Build optimizations: +- Use -O2 or -O3 for production (example uses -O0 for debugging) +- Enable -Wl,--gc-sections to remove unused code +- Define TX_DISABLE_ERROR_CHECKING to remove parameter checks +- Consider -flto for link-time optimization + +Debugging with QEMU and GDB + +Start QEMU in debug mode: + qemu-system-riscv32 -nographic -smp 1 -bios none -m 128M \ + -machine virt -kernel kernel.elf -s -S + + -s: Enable GDB server on TCP port 1234 + -S: Pause at startup waiting for GDB + +Connect GDB: + riscv32-unknown-elf-gdb kernel.elf + (gdb) target remote :1234 + (gdb) break main + (gdb) continue + +Useful GDB commands: + (gdb) info registers # View general registers + (gdb) info all-registers # Include CSR and FP registers + (gdb) p/x $mstatus # View machine status register + (gdb) x/32xw $sp # Examine stack memory + (gdb) p *_tx_thread_current_ptr # View current thread control block + + +13. Platform-Specific Notes (QEMU virt) + +PLIC Configuration + +The PLIC (Platform-Level Interrupt Controller) is memory-mapped at 0x0C000000: + +- Enables up to 1024 interrupt sources +- Supports priority levels 0-7 (0 = disabled) +- Requires per-hart priority threshold and enable register configuration + +Example PLIC usage (from plic.c): + plic_irq_enable(irq_number); # Enable specific interrupt + plic_prio_set(irq_number, priority);# Set priority level + +CLINT Configuration + +The CLINT (Core-Local Interruptor) is memory-mapped at 0x02000000: + +- CLINT_MSIP(hartid): 0x0000 + 4*hartid (software interrupt) +- CLINT_MTIMECMP(hartid): 0x4000 + 8*hartid (timer compare) +- CLINT_MTIME: 0xBFF8 (timer value, read-only) + +Timer frequency is platform-dependent (example uses 10MHz). + +Multi-Core Considerations + +The current port is single-core focused: +- Only hart 0 continues from reset; others enter WFI loop +- _tx_thread_system_state is a global variable +- No per-hart data structures + + +14. Revision History + +For generic code revision information, refer to readme_threadx_generic.txt. + +The following details the revision history for this RISC-V32 GNU port: + +01-26-2026 Akif Ejaz Brief rewrite with accurate + technical details matching implementation, + register naming per RISC-V ABI, and + complete interrupt flow documentation + (Adapted from RISC-V64 port) + + +Copyright (c) 1996-2026 Microsoft Corporation + +https://azure.com/rtos diff --git a/ports/risc-v32/clang/src/tx_initialize_low_level.S b/ports/risc-v32/clang/src/tx_initialize_low_level.S new file mode 100644 index 00000000..6414e1be --- /dev/null +++ b/ports/risc-v32/clang/src/tx_initialize_low_level.S @@ -0,0 +1,118 @@ +/*************************************************************************** + * Copyright (c) 2026 Quintauris + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .section .data + .global __tx_free_memory_start +__tx_free_memory_start: + + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level RISC-V32/GNU */ +/* 6.4.x */ +/* AUTHOR */ +/* */ +/* Francisco Merino, Quintauris */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 26-02-2026 Francisco Merino Initial Version 6.4.x */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ +// .global _tx_initialize_low_level + .weak _tx_initialize_low_level +_tx_initialize_low_level: + + /* Save the system stack pointer. */ + /* _tx_thread_system_stack_ptr = sp; */ + + la t0, _tx_thread_system_stack_ptr // Pickup address of system stack ptr + sw sp, 0(t0) // Save system stack pointer + + /* Pickup first free address. */ + /* _tx_initialize_unused_memory(__tx_free_memory_start); */ + + la t0, __tx_free_memory_start // Pickup first free address + la t1, _tx_initialize_unused_memory // Pickup address of unused memory + sw t0, 0(t1) // Save unused memory address + + /* Initialize floating point control/status register if floating point is enabled. */ +#ifdef __riscv_flen + li t0, 0 + csrw fcsr, t0 // Clear FP control/status register +#endif + + ret + +/* Timer Interrupt Handler Note: + Platform-specific implementations must provide their own timer ISR. + The timer interrupt handler should follow this execution flow: + + 1. Disable interrupts (if not done by hardware exception entry) + 2. Allocate interrupt stack frame (65*4 bytes with FP, 32*4 bytes without) + 3. Save RA (x1) on the stack at offset 28*4 + 4. Call _tx_thread_context_save to save thread context + 5. Call _tx_timer_interrupt to process the timer tick + 6. Call _tx_thread_context_restore to resume execution (does not return) + + Example (for CLINT timer): + + _tx_timer_interrupt_handler: + addi sp, sp, -32*4 + sw ra, 28*4(sp) + call _tx_thread_context_save + call _tx_timer_interrupt + j _tx_thread_context_restore + + The port assumes Machine mode (M-mode) execution. + For Supervisor mode (S-mode), use sstatus and SIE/SPIE instead of mstatus. + See the RISC-V Privileged Specification for more details. */ \ No newline at end of file diff --git a/ports/risc-v32/clang/src/tx_thread_context_restore.S b/ports/risc-v32/clang/src/tx_thread_context_restore.S new file mode 100644 index 00000000..8fa108b4 --- /dev/null +++ b/ports/risc-v32/clang/src/tx_thread_context_restore.S @@ -0,0 +1,416 @@ +/*************************************************************************** + * Copyright (c) 2025 Quintauris + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore RISC-V32/GNU */ +/* 6.4.x */ +/* AUTHOR */ +/* */ +/* Francisco Merino, Quintauris */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 26-02-2026 Francisco Merino Initial Version 6.4.x */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_restore(VOID) +{ */ + .global _tx_thread_context_restore +_tx_thread_context_restore: + + /* Lockout interrupts. */ + + csrci mstatus, 0x08 // Disable interrupts (MIE bit 3) + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + call _tx_execution_isr_exit // Call the ISR execution exit function +#endif + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) + { */ + + la t0, _tx_thread_system_state // Pickup addr of nested interrupt count + lw t1, 0(t0) // Pickup nested interrupt count + addi t1, t1, -1 // Decrement the nested interrupt counter + sw t1, 0(t0) // Store new nested count + beqz t1, _tx_thread_not_nested_restore // If 0, not nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + /* Recover floating point registers. */ +#if defined(__riscv_float_abi_single) + flw f0, 31*4(sp) // Recover ft0 + flw f1, 32*4(sp) // Recover ft1 + flw f2, 33*4(sp) // Recover ft2 + flw f3, 34*4(sp) // Recover ft3 + flw f4, 35*4(sp) // Recover ft4 + flw f5, 36*4(sp) // Recover ft5 + flw f6, 37*4(sp) // Recover ft6 + flw f7, 38*4(sp) // Recover ft7 + flw f10, 41*4(sp) // Recover fa0 + flw f11, 42*4(sp) // Recover fa1 + flw f12, 43*4(sp) // Recover fa2 + flw f13, 44*4(sp) // Recover fa3 + flw f14, 45*4(sp) // Recover fa4 + flw f15, 46*4(sp) // Recover fa5 + flw f16, 47*4(sp) // Recover fa6 + flw f17, 48*4(sp) // Recover fa7 + flw f28, 59*4(sp) // Recover ft8 + flw f29, 60*4(sp) // Recover ft9 + flw f30, 61*4(sp) // Recover ft10 + flw f31, 62*4(sp) // Recover ft11 + lw t0, 63*4(sp) // Recover fcsr + csrw fcsr, t0 // Restore fcsr +#elif defined(__riscv_float_abi_double) + fld f0, 31*4(sp) // Recover ft0 + fld f1, 32*4(sp) // Recover ft1 + fld f2, 33*4(sp) // Recover ft2 + fld f3, 34*4(sp) // Recover ft3 + fld f4, 35*4(sp) // Recover ft4 + fld f5, 36*4(sp) // Recover ft5 + fld f6, 37*4(sp) // Recover ft6 + fld f7, 38*4(sp) // Recover ft7 + fld f10, 41*4(sp) // Recover fa0 + fld f11, 42*4(sp) // Recover fa1 + fld f12, 43*4(sp) // Recover fa2 + fld f13, 44*4(sp) // Recover fa3 + fld f14, 45*4(sp) // Recover fa4 + fld f15, 46*4(sp) // Recover fa5 + fld f16, 47*4(sp) // Recover fa6 + fld f17, 48*4(sp) // Recover fa7 + fld f28, 59*4(sp) // Recover ft8 + fld f29, 60*4(sp) // Recover ft9 + fld f30, 61*4(sp) // Recover ft10 + fld f31, 62*4(sp) // Recover ft11 + lw t0, 63*4(sp) // Recover fcsr + csrw fcsr, t0 // Restore fcsr +#endif + + /* Recover standard registers. */ + + /* Restore registers, + Skip global pointer because that does not change. + Also skip the saved registers since they have been restored by any function we called, + except s0 since we use it ourselves. */ + + lw t0, 30*4(sp) // Recover mepc + csrw mepc, t0 // Setup mepc + + /* Compose mstatus via read/modify/write to avoid clobbering unrelated bits. + Set MPIE and restore MPP to Machine, preserve other fields. */ + + csrr t1, mstatus + + /* Clear MPP/MPIE/MIE bits in t1 then set desired values. */ + + li t2, 0x1888 // MPP(0x1800) | MPIE(0x80) | MIE(0x08) + li t3, 0x1800 // Set MPP to Machine mode (bits 12:11) + + /* Construct new mstatus in t1: clear mask bits, set MPP/MPIE and optionally FP bit, + preserve everything except the bits we will modify. */ + + li t4, ~0x1888 // Clear mask for MPP/MPIE/MIE + and t1, t1, t4 + or t1, t1, t3 + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + li t0, 0x2000 // Set FS bits (bits 14:13 to 01) for FP state + or t1, t1, t0 +#endif + csrw mstatus, t1 // Update mstatus safely + + lw ra, 28*4(sp) // Recover return address + lw t0, 19*4(sp) // Recover t0 + lw t1, 18*4(sp) // Recover t1 + lw t2, 17*4(sp) // Recover t2 + lw s0, 12*4(sp) // Recover s0 + lw a0, 27*4(sp) // Recover a0 + lw a1, 26*4(sp) // Recover a1 + lw a2, 25*4(sp) // Recover a2 + lw a3, 24*4(sp) // Recover a3 + lw a4, 23*4(sp) // Recover a4 + lw a5, 22*4(sp) // Recover a5 + lw a6, 21*4(sp) // Recover a6 + lw a7, 20*4(sp) // Recover a7 + lw t3, 16*4(sp) // Recover t3 + lw t4, 15*4(sp) // Recover t4 + lw t5, 14*4(sp) // Recover t5 + lw t6, 13*4(sp) // Recover t6 + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, 65*4 // Recover stack frame - with floating point enabled +#else + addi sp, sp, 32*4 // Recover stack frame - without floating point enabled +#endif + mret // Return to point of interrupt + + /* } */ +_tx_thread_not_nested_restore: + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + || (_tx_thread_preempt_disable)) + { */ + + la t0, _tx_thread_current_ptr // Pickup current thread pointer address + lw t1, 0(t0) // Pickup current thread pointer + + beqz t1, _tx_thread_idle_system_restore // If NULL, idle system restore + + + la t0, _tx_thread_preempt_disable // Pickup preempt disable flag address + lw t2, 0(t0) // Pickup preempt disable flag (UINT) + + bgtz t2, _tx_thread_no_preempt_restore // If set, restore interrupted thread + + + la t0, _tx_thread_execute_ptr // Pickup thread execute pointer address + lw t2, 0(t0) // Pickup thread execute pointer + + bne t1, t2, _tx_thread_preempt_restore // If higher-priority thread is ready, preempt + + +_tx_thread_no_preempt_restore: + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* sp = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + lw sp, 8(t1) // Switch back to thread's stack + + /* Recover floating point registers. */ +#if defined(__riscv_float_abi_single) + flw f0, 31*4(sp) // Recover ft0 + flw f1, 32*4(sp) // Recover ft1 + flw f2, 33*4(sp) // Recover ft2 + flw f3, 34*4(sp) // Recover ft3 + flw f4, 35*4(sp) // Recover ft4 + flw f5, 36*4(sp) // Recover ft5 + flw f6, 37*4(sp) // Recover ft6 + flw f7, 38*4(sp) // Recover ft7 + flw f10, 41*4(sp) // Recover fa0 + flw f11, 42*4(sp) // Recover fa1 + flw f12, 43*4(sp) // Recover fa2 + flw f13, 44*4(sp) // Recover fa3 + flw f14, 45*4(sp) // Recover fa4 + flw f15, 46*4(sp) // Recover fa5 + flw f16, 47*4(sp) // Recover fa6 + flw f17, 48*4(sp) // Recover fa7 + flw f28, 59*4(sp) // Recover ft8 + flw f29, 60*4(sp) // Recover ft9 + flw f30, 61*4(sp) // Recover ft10 + flw f31, 62*4(sp) // Recover ft11 + lw t0, 63*4(sp) // Recover fcsr + csrw fcsr, t0 // Restore fcsr +#elif defined(__riscv_float_abi_double) + fld f0, 31*4(sp) // Recover ft0 + fld f1, 32*4(sp) // Recover ft1 + fld f2, 33*4(sp) // Recover ft2 + fld f3, 34*4(sp) // Recover ft3 + fld f4, 35*4(sp) // Recover ft4 + fld f5, 36*4(sp) // Recover ft5 + fld f6, 37*4(sp) // Recover ft6 + fld f7, 38*4(sp) // Recover ft7 + fld f10, 41*4(sp) // Recover fa0 + fld f11, 42*4(sp) // Recover fa1 + fld f12, 43*4(sp) // Recover fa2 + fld f13, 44*4(sp) // Recover fa3 + fld f14, 45*4(sp) // Recover fa4 + fld f15, 46*4(sp) // Recover fa5 + fld f16, 47*4(sp) // Recover fa6 + fld f17, 48*4(sp) // Recover fa7 + fld f28, 59*4(sp) // Recover ft8 + fld f29, 60*4(sp) // Recover ft9 + fld f30, 61*4(sp) // Recover ft10 + fld f31, 62*4(sp) // Recover ft11 + lw t0, 63*4(sp) // Recover fcsr + csrw fcsr, t0 // Restore fcsr +#endif + + /* Recover the saved context and return to the point of interrupt. */ + + /* Recover standard registers. */ + /* Restore registers, + Skip global pointer because that does not change */ + + lw t0, 30*4(sp) // Recover mepc + csrw mepc, t0 // Setup mepc + + /* Compose mstatus via read/modify/write to avoid clobbering unrelated bits. */ + + csrr t1, mstatus + li t2, 0x1888 // MPP(0x1800) | MPIE(0x80) | MIE(0x08) + li t3, 0x1800 // Set MPP to Machine mode + li t4, ~0x1888 // Clear mask for MPP/MPIE/MIE + and t1, t1, t4 + or t1, t1, t3 + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + li t0, 0x2000 // Set FS bits for FP state + or t1, t1, t0 +#endif + csrw mstatus, t1 // Update mstatus safely + + lw ra, 28*4(sp) // Recover return address + lw t0, 19*4(sp) // Recover t0 + lw t1, 18*4(sp) // Recover t1 + lw t2, 17*4(sp) // Recover t2 + lw s0, 12*4(sp) // Recover s0 + lw a0, 27*4(sp) // Recover a0 + lw a1, 26*4(sp) // Recover a1 + lw a2, 25*4(sp) // Recover a2 + lw a3, 24*4(sp) // Recover a3 + lw a4, 23*4(sp) // Recover a4 + lw a5, 22*4(sp) // Recover a5 + lw a6, 21*4(sp) // Recover a6 + lw a7, 20*4(sp) // Recover a7 + lw t3, 16*4(sp) // Recover t3 + lw t4, 15*4(sp) // Recover t4 + lw t5, 14*4(sp) // Recover t5 + lw t6, 13*4(sp) // Recover t6 + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, 65*4 // Recover stack frame - with floating point enabled +#else + addi sp, sp, 32*4 // Recover stack frame - without floating point enabled +#endif + mret // Return to point of interrupt + + /* } + else + { */ +_tx_thread_preempt_restore: + /* Instead of directly activating the thread again, ensure we save the + entire stack frame by saving the remaining registers. */ + + lw t0, 8(t1) // Pickup thread's stack pointer + ori t3, zero, 1 // Build interrupt stack type + sw t3, 0(t0) // Store stack type + + /* Store floating point preserved registers. */ +#ifdef __riscv_float_abi_single + fsw f8, 39*4(t0) // Store fs0 + fsw f9, 40*4(t0) // Store fs1 + fsw f18, 49*4(t0) // Store fs2 + fsw f19, 50*4(t0) // Store fs3 + fsw f20, 51*4(t0) // Store fs4 + fsw f21, 52*4(t0) // Store fs5 + fsw f22, 53*4(t0) // Store fs6 + fsw f23, 54*4(t0) // Store fs7 + fsw f24, 55*4(t0) // Store fs8 + fsw f25, 56*4(t0) // Store fs9 + fsw f26, 57*4(t0) // Store fs10 + fsw f27, 58*4(t0) // Store fs11 +#elif defined(__riscv_float_abi_double) + fsd f8, 39*4(t0) // Store fs0 + fsd f9, 40*4(t0) // Store fs1 + fsd f18, 49*4(t0) // Store fs2 + fsd f19, 50*4(t0) // Store fs3 + fsd f20, 51*4(t0) // Store fs4 + fsd f21, 52*4(t0) // Store fs5 + fsd f22, 53*4(t0) // Store fs6 + fsd f23, 54*4(t0) // Store fs7 + fsd f24, 55*4(t0) // Store fs8 + fsd f25, 56*4(t0) // Store fs9 + fsd f26, 57*4(t0) // Store fs10 + fsd f27, 58*4(t0) // Store fs11 +#endif + + /* Store standard preserved registers. */ + + sw x9, 11*4(t0) // Store s1 + sw x18, 10*4(t0) // Store s2 + sw x19, 9*4(t0) // Store s3 + sw x20, 8*4(t0) // Store s4 + sw x21, 7*4(t0) // Store s5 + sw x22, 6*4(t0) // Store s6 + sw x23, 5*4(t0) // Store s7 + sw x24, 4*4(t0) // Store s8 + sw x25, 3*4(t0) // Store s9 + sw x26, 2*4(t0) // Store s10 + sw x27, 1*4(t0) // Store s11 + // Note: s0 is already stored! + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) + { */ + + la t0, _tx_timer_time_slice // Pickup time slice variable address + lw t2, 0(t0) // Pickup time slice + beqz t2, _tx_thread_dont_save_ts // If 0, skip time slice processing + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice + _tx_timer_time_slice = 0; */ + + sw t2, 24(t1) // Save current time slice + sw x0, 0(t0) // Clear global time slice + + + /* } */ +_tx_thread_dont_save_ts: + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + la t0, _tx_thread_current_ptr // Pickup current thread pointer address + sw x0, 0(t0) // Clear current thread pointer + + /* } */ + +_tx_thread_idle_system_restore: + /* Just return back to the scheduler! */ + j _tx_thread_schedule // Return to scheduler + +/* } */ diff --git a/ports/risc-v32/clang/src/tx_thread_context_save.S b/ports/risc-v32/clang/src/tx_thread_context_save.S new file mode 100644 index 00000000..8801374e --- /dev/null +++ b/ports/risc-v32/clang/src/tx_thread_context_save.S @@ -0,0 +1,277 @@ +/*************************************************************************** + * Copyright (c) 2026 Quintauris + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save RISC-V32/GNU */ +/* 6.4.x */ +/* AUTHOR */ +/* */ +/* Francisco Merino, Quintauris */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 26-02-2026 Francisco Merino Initial Version 6.4.x */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_save(VOID) +{ */ + .global _tx_thread_context_save +_tx_thread_context_save: + + /* Upon entry to this routine, RA/x1 has been saved on the stack + and the stack has been already allocated for the entire context: + addi sp, sp, -32*4 (or -65*4) + sw ra, 28*4(sp) + */ + + sw t0, 19*4(sp) // Store t0 + sw t1, 18*4(sp) // Store t1 + + /* Check for a nested interrupt. */ + /* if (_tx_thread_system_state++) + { */ + + la t0, _tx_thread_system_state // Pickup addr of system state var + lw t1, 0(t0) // Pickup system state + addi t1, t1, 1 // Increment system state + sw t1, 0(t0) // Store system state + li t0, 1 + bgt t1, t0, _tx_thread_nested_save // If it's more than 1, nested interrupt + + /* First level interrupt, save the rest of the scratch registers and + check for a thread to preempt. */ + + sw t2, 17*4(sp) // Store t2 + sw s0, 12*4(sp) // Store s0 + sw a0, 27*4(sp) // Store a0 + sw a1, 26*4(sp) // Store a1 + sw a2, 25*4(sp) // Store a2 + sw a3, 24*4(sp) // Store a3 + sw a4, 23*4(sp) // Store a4 + sw a5, 22*4(sp) // Store a5 + sw a6, 21*4(sp) // Store a6 + sw a7, 20*4(sp) // Store a7 + sw t3, 16*4(sp) // Store t3 + sw t4, 15*4(sp) // Store t4 + sw t5, 14*4(sp) // Store t5 + sw t6, 13*4(sp) // Store t6 + + /* Save floating point registers. */ +#if defined(__riscv_float_abi_single) + fsw f0, 31*4(sp) // Store ft0 + fsw f1, 32*4(sp) // Store ft1 + fsw f2, 33*4(sp) // Store ft2 + fsw f3, 34*4(sp) // Store ft3 + fsw f4, 35*4(sp) // Store ft4 + fsw f5, 36*4(sp) // Store ft5 + fsw f6, 37*4(sp) // Store ft6 + fsw f7, 38*4(sp) // Store ft7 + fsw f10, 41*4(sp) // Store fa0 + fsw f11, 42*4(sp) // Store fa1 + fsw f12, 43*4(sp) // Store fa2 + fsw f13, 44*4(sp) // Store fa3 + fsw f14, 45*4(sp) // Store fa4 + fsw f15, 46*4(sp) // Store fa5 + fsw f16, 47*4(sp) // Store fa6 + fsw f17, 48*4(sp) // Store fa7 + fsw f28, 59*4(sp) // Store ft8 + fsw f29, 60*4(sp) // Store ft9 + fsw f30, 61*4(sp) // Store ft10 + fsw f31, 62*4(sp) // Store ft11 + csrr t0, fcsr + sw t0, 63*4(sp) // Store fcsr +#elif defined(__riscv_float_abi_double) + fsd f0, 31*4(sp) // Store ft0 + fsd f1, 32*4(sp) // Store ft1 + fsd f2, 33*4(sp) // Store ft2 + fsd f3, 34*4(sp) // Store ft3 + fsd f4, 35*4(sp) // Store ft4 + fsd f5, 36*4(sp) // Store ft5 + fsd f6, 37*4(sp) // Store ft6 + fsd f7, 38*4(sp) // Store ft7 + fsd f10, 41*4(sp) // Store fa0 + fsd f11, 42*4(sp) // Store fa1 + fsd f12, 43*4(sp) // Store fa2 + fsd f13, 44*4(sp) // Store fa3 + fsd f14, 45*4(sp) // Store fa4 + fsd f15, 46*4(sp) // Store fa5 + fsd f16, 47*4(sp) // Store fa6 + fsd f17, 48*4(sp) // Store fa7 + fsd f28, 59*4(sp) // Store ft8 + fsd f29, 60*4(sp) // Store ft9 + fsd f30, 61*4(sp) // Store ft10 + fsd f31, 62*4(sp) // Store ft11 + csrr t0, fcsr + sw t0, 63*4(sp) // Store fcsr +#endif + + csrr t0, mepc + sw t0, 30*4(sp) // Save it on the stack + + /* Save mstatus. */ + csrr t0, mstatus + sw t0, 29*4(sp) + + la t1, _tx_thread_current_ptr // Pickup address of current thread ptr + lw t2, 0(t1) // Pickup current thread pointer + beqz t2, _tx_thread_idle_system_save // If NULL, idle system was interrupted + + /* Save the current thread's stack pointer and switch to the system stack. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; + sp = _tx_thread_system_stack_ptr; */ + + sw sp, 8(t2) // Save stack pointer + la t0, _tx_thread_system_stack_ptr + lw sp, 0(t0) // Switch to system stack + + /* Call the ISR execution exit function if enabled. */ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + call _tx_execution_isr_enter // Call the ISR execution enter function +#endif + + ret // Return to ISR + +_tx_thread_nested_save: + + /* Nested interrupt! Just save the scratch registers and return to the ISR. */ + + sw t2, 17*4(sp) // Store t2 + sw s0, 12*4(sp) // Store s0 + sw a0, 27*4(sp) // Store a0 + sw a1, 26*4(sp) // Store a1 + sw a2, 25*4(sp) // Store a2 + sw a3, 24*4(sp) // Store a3 + sw a4, 23*4(sp) // Store a4 + sw a5, 22*4(sp) // Store a5 + sw a6, 21*4(sp) // Store a6 + sw a7, 20*4(sp) // Store a7 + sw t3, 16*4(sp) // Store t3 + sw t4, 15*4(sp) // Store t4 + sw t5, 14*4(sp) // Store t5 + sw t6, 13*4(sp) // Store t6 + + /* Save floating point registers. */ +#if defined(__riscv_float_abi_single) + fsw f0, 31*4(sp) // Store ft0 + fsw f1, 32*4(sp) // Store ft1 + fsw f2, 33*4(sp) // Store ft2 + fsw f3, 34*4(sp) // Store ft3 + fsw f4, 35*4(sp) // Store ft4 + fsw f5, 36*4(sp) // Store ft5 + fsw f6, 37*4(sp) // Store ft6 + fsw f7, 38*4(sp) // Store ft7 + fsw f10, 41*4(sp) // Store fa0 + fsw f11, 42*4(sp) // Store fa1 + fsw f12, 43*4(sp) // Store fa2 + fsw f13, 44*4(sp) // Store fa3 + fsw f14, 45*4(sp) // Store fa4 + fsw f15, 46*4(sp) // Store fa5 + fsw f16, 47*4(sp) // Store fa6 + fsw f17, 48*4(sp) // Store fa7 + fsw f28, 59*4(sp) // Store ft8 + fsw f29, 60*4(sp) // Store ft9 + fsw f30, 61*4(sp) // Store ft10 + fsw f31, 62*4(sp) // Store ft11 + csrr t0, fcsr + sw t0, 63*4(sp) // Store fcsr +#elif defined(__riscv_float_abi_double) + fsd f0, 31*4(sp) // Store ft0 + fsd f1, 32*4(sp) // Store ft1 + fsd f2, 33*4(sp) // Store ft2 + fsd f3, 34*4(sp) // Store ft3 + fsd f4, 35*4(sp) // Store ft4 + fsd f5, 36*4(sp) // Store ft5 + fsd f6, 37*4(sp) // Store ft6 + fsd f7, 38*4(sp) // Store ft7 + fsd f10, 41*4(sp) // Store fa0 + fsd f11, 42*4(sp) // Store fa1 + fsd f12, 43*4(sp) // Store fa2 + fsd f13, 44*4(sp) // Store fa3 + fsd f14, 45*4(sp) // Store fa4 + fsd f15, 46*4(sp) // Store fa5 + fsd f16, 47*4(sp) // Store fa6 + fsd f17, 48*4(sp) // Store fa7 + fsd f28, 59*4(sp) // Store ft8 + fsd f29, 60*4(sp) // Store ft9 + fsd f30, 61*4(sp) // Store ft10 + fsd f31, 62*4(sp) // Store ft11 + csrr t0, fcsr + sw t0, 63*4(sp) // Store fcsr +#endif + + csrr t0, mepc + sw t0, 30*4(sp) // Save it on stack + + csrr t0, mstatus + sw t0, 29*4(sp) + + /* Call the ISR execution exit function if enabled. */ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + call _tx_execution_isr_enter // Call the ISR execution enter function +#endif + + ret // Return to ISR + +_tx_thread_idle_system_save: + + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + call _tx_execution_isr_enter // Call the ISR execution enter function +#endif + + /* Interrupt occurred in the scheduling loop. */ + + /* } +} */ +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, 65*4 // Recover stack frame - with floating point enabled +#else + addi sp, sp, 32*4 // Recover the reserved stack space +#endif + ret // Return to calling ISR diff --git a/ports/risc-v32/clang/src/tx_thread_interrupt_control.S b/ports/risc-v32/clang/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..867174ad --- /dev/null +++ b/ports/risc-v32/clang/src/tx_thread_interrupt_control.S @@ -0,0 +1,94 @@ +/*************************************************************************** + * Copyright (c) 2026 Quintauris + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control RISC-V32/GNU */ +/* 6.4.x */ +/* AUTHOR */ +/* */ +/* Francisco Merino, Quintauris */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 26-02-2026 Francisco Merino Initial Version 6.4.x */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_control(UINT new_posture) +{ */ + .global _tx_thread_interrupt_control +_tx_thread_interrupt_control: + + /* Pickup current interrupt posture. */ + + csrr a1, mstatus // Pickup mstatus + andi a1, a1, 0x08 // Mask out all but MIE + + /* Check for the new posture. */ + + beqz a0, _tx_thread_interrupt_disable // If 0, disable interrupts + + /* Enable interrupts. */ + + csrsi mstatus, 0x08 // Enable interrupts (MIE bit 3) + j _tx_thread_interrupt_control_exit // Return to caller + +_tx_thread_interrupt_disable: + + /* Disable interrupts. */ + + csrci mstatus, 0x08 // Disable interrupts (MIE bit 3) + +_tx_thread_interrupt_control_exit: + + /* Return the old interrupt posture. */ + + mv a0, a1 // Setup return value + ret // Return to caller + +/* } */ diff --git a/ports/risc-v32/clang/src/tx_thread_schedule.S b/ports/risc-v32/clang/src/tx_thread_schedule.S new file mode 100644 index 00000000..3e6d3506 --- /dev/null +++ b/ports/risc-v32/clang/src/tx_thread_schedule.S @@ -0,0 +1,324 @@ +/*************************************************************************** + * Copyright (c) 2026 Quintauris + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule RISC-V32/GNU */ +/* 6.4.x */ +/* AUTHOR */ +/* */ +/* Francisco Merino, Quintauris */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_schedule(VOID) +{ */ + .global _tx_thread_schedule +_tx_thread_schedule: + + /* Enable interrupts. */ + + csrsi mstatus, 0x08 // Enable interrupts (MIE bit 3) + + /* Wait for a thread to execute. */ + /* do + { */ +_tx_thread_schedule_loop: + + la t0, _tx_thread_execute_ptr // Pickup address of execute ptr + lw t1, 0(t0) // Pickup execute pointer + bnez t1, _tx_thread_ready_to_run // If non-NULL, a thread is ready to run + +#ifndef TX_NO_WFI + wfi // Wait for interrupt +#endif + j _tx_thread_schedule_loop // Check again + + /* } + while (_tx_thread_execute_ptr == TX_NULL); */ + +_tx_thread_ready_to_run: + + /* At this point, t1 contains the pointer to the thread to execute. + Lockout interrupts. */ + + csrci mstatus, 0x08 // Disable interrupts (MIE bit 3) + + /* Check _tx_thread_execute_ptr again, in case an interrupt occurred + between the check and the disable. */ + + lw t1, 0(t0) // Pickup execute pointer + beqz t1, _tx_thread_schedule_loop // If NULL, go back to wait loop + + /* Yes! We have a thread to execute. */ + /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ + + la t0, _tx_thread_current_ptr // Pickup address of current thread + sw t1, 0(t0) // Setup current thread pointer + + /* Increment the run count for this thread. */ + /* _tx_thread_current_ptr -> tx_thread_run_count++; */ + + lw t2, 4(t1) // Pickup run count + addi t2, t2, 1 // Increment run count + sw t2, 4(t1) // Store run count + + /* Setup time-slice values. */ + /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ + + lw t2, 24(t1) // Pickup thread time-slice + la t3, _tx_timer_time_slice // Pickup address of time-slice + sw t2, 0(t3) // Setup time-slice + + /* Call the thread execution enter function if enabled. */ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + call _tx_execution_thread_enter // Call the thread execution enter function +#endif + + /* Switch to the thread's stack. */ + /* sp = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + lw sp, 8(t1) // Switch to thread stack + + /* Determine the type of stack frame. */ + /* if (*sp) + { */ + + lw t0, 0(sp) // Pickup stack type + beqz t0, _tx_thread_solicited_return // If 0, solicited return + + /* Recover floating point registers. */ +#if defined(__riscv_float_abi_single) + flw f0, 31*4(sp) // Recover ft0 + flw f1, 32*4(sp) // Recover ft1 + flw f2, 33*4(sp) // Recover ft2 + flw f3, 34*4(sp) // Recover ft3 + flw f4, 35*4(sp) // Recover ft4 + flw f5, 36*4(sp) // Recover ft5 + flw f6, 37*4(sp) // Recover ft6 + flw f7, 38*4(sp) // Recover ft7 + flw f8, 39*4(sp) // Recover fs0 + flw f9, 40*4(sp) // Recover fs1 + flw f10, 41*4(sp) // Recover fa0 + flw f11, 42*4(sp) // Recover fa1 + flw f12, 43*4(sp) // Recover fa2 + flw f13, 44*4(sp) // Recover fa3 + flw f14, 45*4(sp) // Recover fa4 + flw f15, 46*4(sp) // Recover fa5 + flw f16, 47*4(sp) // Recover fa6 + flw f17, 48*4(sp) // Recover fa7 + flw f18, 49*4(sp) // Recover fs2 + flw f19, 50*4(sp) // Recover fs3 + flw f20, 51*4(sp) // Recover fs4 + flw f21, 52*4(sp) // Recover fs5 + flw f22, 53*4(sp) // Recover fs6 + flw f23, 54*4(sp) // Recover fs7 + flw f24, 55*4(sp) // Recover fs8 + flw f25, 56*4(sp) // Recover fs9 + flw f26, 57*4(sp) // Recover fs10 + flw f27, 58*4(sp) // Recover fs11 + flw f28, 59*4(sp) // Recover ft8 + flw f29, 60*4(sp) // Recover ft9 + flw f30, 61*4(sp) // Recover ft10 + flw f31, 62*4(sp) // Recover ft11 + lw t0, 63*4(sp) // Recover fcsr + csrw fcsr, t0 // Restore fcsr +#elif defined(__riscv_float_abi_double) + fld f0, 31*4(sp) // Recover ft0 + fld f1, 32*4(sp) // Recover ft1 + fld f2, 33*4(sp) // Recover ft2 + fld f3, 34*4(sp) // Recover ft3 + fld f4, 35*4(sp) // Recover ft4 + fld f5, 36*4(sp) // Recover ft5 + fld f6, 37*4(sp) // Recover ft6 + fld f7, 38*4(sp) // Recover ft7 + fld f8, 39*4(sp) // Recover fs0 + fld f9, 40*4(sp) // Recover fs1 + fld f10, 41*4(sp) // Recover fa0 + fld f11, 42*4(sp) // Recover fa1 + fld f12, 43*4(sp) // Recover fa2 + fld f13, 44*4(sp) // Recover fa3 + fld f14, 45*4(sp) // Recover fa4 + fld f15, 46*4(sp) // Recover fa5 + fld f16, 47*4(sp) // Recover fa6 + fld f17, 48*4(sp) // Recover fa7 + fld f18, 49*4(sp) // Recover fs2 + fld f19, 50*4(sp) // Recover fs3 + fld f20, 51*4(sp) // Recover fs4 + fld f21, 52*4(sp) // Recover fs5 + fld f22, 53*4(sp) // Recover fs6 + fld f23, 54*4(sp) // Recover fs7 + fld f24, 55*4(sp) // Recover fs8 + fld f25, 56*4(sp) // Recover fs9 + fld f26, 57*4(sp) // Recover fs10 + fld f27, 58*4(sp) // Recover fs11 + fld f28, 59*4(sp) // Recover ft8 + fld f29, 60*4(sp) // Recover ft9 + fld f30, 61*4(sp) // Recover ft10 + fld f31, 62*4(sp) // Recover ft11 + lw t0, 63*4(sp) // Recover fcsr + csrw fcsr, t0 // Restore fcsr +#endif + + /* Recover standard registers. */ + + lw t0, 30*4(sp) // Recover mepc + csrw mepc, t0 // Setup mepc + + li t0, 0x1880 // Prepare mstatus: MPP=Machine(0x1800) | MPIE(0x80) +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + li t1, 0x2000 // Set FS bits for FP state + or t0, t0, t1 +#endif + csrw mstatus, t0 // Set mstatus + + lw ra, 28*4(sp) // Recover return address + lw t0, 19*4(sp) // Recover t0 + lw t1, 18*4(sp) // Recover t1 + lw t2, 17*4(sp) // Recover t2 + lw s0, 12*4(sp) // Recover s0 + lw x9, 11*4(sp) // Recover s1 + lw a0, 27*4(sp) // Recover a0 + lw a1, 26*4(sp) // Recover a1 + lw a2, 25*4(sp) // Recover a2 + lw a3, 24*4(sp) // Recover a3 + lw a4, 23*4(sp) // Recover a4 + lw a5, 22*4(sp) // Recover a5 + lw a6, 21*4(sp) // Recover a6 + lw a7, 20*4(sp) // Recover a7 + lw t3, 16*4(sp) // Recover t3 + lw t4, 15*4(sp) // Recover t4 + lw t5, 14*4(sp) // Recover t5 + lw t6, 13*4(sp) // Recover t6 + lw x18, 10*4(sp) // Recover s2 + lw x19, 9*4(sp) // Recover s3 + lw x20, 8*4(sp) // Recover s4 + lw x21, 7*4(sp) // Recover s5 + lw x22, 6*4(sp) // Recover s6 + lw x23, 5*4(sp) // Recover s7 + lw x24, 4*4(sp) // Recover s8 + lw x25, 3*4(sp) // Recover s9 + lw x26, 2*4(sp) // Recover s10 + lw x27, 1*4(sp) // Recover s11 + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, 65*4 // Recover stack frame - with floating point enabled +#else + addi sp, sp, 32*4 // Recover stack frame - without floating point enabled +#endif + mret // Return to thread + +_tx_thread_solicited_return: + + /* Recover floating point registers. */ +#if defined(__riscv_float_abi_single) + flw f8, 15*4(sp) // Recover fs0 + flw f9, 16*4(sp) // Recover fs1 + flw f18, 17*4(sp) // Recover fs2 + flw f19, 18*4(sp) // Recover fs3 + flw f20, 19*4(sp) // Recover fs4 + flw f21, 20*4(sp) // Recover fs5 + flw f22, 21*4(sp) // Recover fs6 + flw f23, 22*4(sp) // Recover fs7 + flw f24, 23*4(sp) // Recover fs8 + flw f25, 24*4(sp) // Recover fs9 + flw f26, 25*4(sp) // Recover fs10 + flw f27, 26*4(sp) // Recover fs11 + lw t0, 27*4(sp) // Recover fcsr + csrw fcsr, t0 // Restore fcsr +#elif defined(__riscv_float_abi_double) + fld f8, 15*4(sp) // Recover fs0 + fld f9, 16*4(sp) // Recover fs1 + fld f18, 17*4(sp) // Recover fs2 + fld f19, 18*4(sp) // Recover fs3 + fld f20, 19*4(sp) // Recover fs4 + fld f21, 20*4(sp) // Recover fs5 + fld f22, 21*4(sp) // Recover fs6 + fld f23, 22*4(sp) // Recover fs7 + fld f24, 23*4(sp) // Recover fs8 + fld f25, 24*4(sp) // Recover fs9 + fld f26, 25*4(sp) // Recover fs10 + fld f27, 26*4(sp) // Recover fs11 + lw t0, 27*4(sp) // Recover fcsr + csrw fcsr, t0 // Restore fcsr +#endif + + /* Recover standard registers. */ + + lw t0, 14*4(sp) // Recover mstatus + csrw mstatus, t0 // Restore mstatus + + lw ra, 13*4(sp) // Recover return address + lw s0, 12*4(sp) // Recover s0 + lw s1, 11*4(sp) // Recover s1 + lw x18, 10*4(sp) // Recover s2 + lw x19, 9*4(sp) // Recover s3 + lw x20, 8*4(sp) // Recover s4 + lw x21, 7*4(sp) // Recover s5 + lw x22, 6*4(sp) // Recover s6 + lw x23, 5*4(sp) // Recover s7 + lw x24, 4*4(sp) // Recover s8 + lw x25, 3*4(sp) // Recover s9 + lw x26, 2*4(sp) // Recover s10 + lw x27, 1*4(sp) // Recover s11 + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, 29*4 // Recover stack frame - with floating point enabled +#else + addi sp, sp, 16*4 // Recover stack frame - without floating point enabled +#endif + ret // Return to thread + +/* } */ diff --git a/ports/risc-v32/clang/src/tx_thread_stack_build.S b/ports/risc-v32/clang/src/tx_thread_stack_build.S new file mode 100644 index 00000000..20ceed2f --- /dev/null +++ b/ports/risc-v32/clang/src/tx_thread_stack_build.S @@ -0,0 +1,227 @@ +/*************************************************************************** + * Copyright (c) 2026 Quintauris + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build RISC-V32/GNU */ +/* 6.4.x */ +/* AUTHOR */ +/* */ +/* Francisco Merino, Quintauris */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 26-02-2026 Francisco Merino Initial Version 6.4.x */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +{ */ + .global _tx_thread_stack_build +_tx_thread_stack_build: + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the RISC-V should look like the following after it is built: + Reg Index + Stack Top: 1 0 Interrupt stack frame type + x27 1 Initial s11 + x26 2 Initial s10 + x25 3 Initial s9 + x24 4 Initial s8 + x23 5 Initial s7 + x22 6 Initial s6 + x21 7 Initial s5 + x20 8 Initial s4 + x19 9 Initial s3 + x18 10 Initial s2 + x9 11 Initial s1 + x8 12 Initial s0 + x31 13 Initial t6 + x30 14 Initial t5 + x29 15 Initial t4 + x28 16 Initial t3 + x7 17 Initial t2 + x6 18 Initial t1 + x5 19 Initial t0 + x17 20 Initial a7 + x16 21 Initial a6 + x15 22 Initial a5 + x14 23 Initial a4 + x13 24 Initial a3 + x12 25 Initial a2 + x11 26 Initial a1 + x10 27 Initial a0 + x1 28 Initial ra + -- 29 reserved + mepc 30 Initial mepc +If floating point support: + f0 31 Initial ft0 + f1 32 Initial ft1 + f2 33 Initial ft2 + f3 34 Initial ft3 + f4 35 Initial ft4 + f5 36 Initial ft5 + f6 37 Initial ft6 + f7 38 Initial ft7 + f8 39 Initial fs0 + f9 40 Initial fs1 + f10 41 Initial fa0 + f11 42 Initial fa1 + f12 43 Initial fa2 + f13 44 Initial fa3 + f14 45 Initial fa4 + f15 46 Initial fa5 + f16 47 Initial fa6 + f17 48 Initial fa7 + f18 49 Initial fs2 + f19 50 Initial fs3 + f20 51 Initial fs4 + f21 52 Initial fs5 + f22 53 Initial fs6 + f23 54 Initial fs7 + f24 55 Initial fs8 + f25 56 Initial fs9 + f26 57 Initial fs10 + f27 58 Initial fs11 + f28 59 Initial ft8 + f29 60 Initial ft9 + f30 61 Initial ft10 + f31 62 Initial ft11 + fscr 63 Initial fscr + + Stack Bottom: (higher memory address) */ + + lw t0, 16(a0) // Pickup end of stack area + li t1, ~15 // Build 16-byte alignment mask + and t0, t0, t1 // Make sure 16-byte alignment + + /* Actually build the stack frame. */ + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi t0, t0, -65*4 +#else + addi t0, t0, -32*4 // Allocate space for the stack frame +#endif + li t1, 1 // Build stack type + sw t1, 0*4(t0) // Place stack type on the top + sw zero, 1*4(t0) // Initial s11 + sw zero, 2*4(t0) // Initial s10 + sw zero, 3*4(t0) // Initial s9 + sw zero, 4*4(t0) // Initial s8 + sw zero, 5*4(t0) // Initial s7 + sw zero, 6*4(t0) // Initial s6 + sw zero, 7*4(t0) // Initial s5 + sw zero, 8*4(t0) // Initial s4 + sw zero, 9*4(t0) // Initial s3 + sw zero, 10*4(t0) // Initial s2 + sw zero, 11*4(t0) // Initial s1 + sw zero, 12*4(t0) // Initial s0 + sw zero, 13*4(t0) // Initial t6 + sw zero, 14*4(t0) // Initial t5 + sw zero, 15*4(t0) // Initial t4 + sw zero, 16*4(t0) // Initial t3 + sw zero, 17*4(t0) // Initial t2 + sw zero, 18*4(t0) // Initial t1 + sw zero, 19*4(t0) // Initial t0 + sw zero, 20*4(t0) // Initial a7 + sw zero, 21*4(t0) // Initial a6 + sw zero, 22*4(t0) // Initial a5 + sw zero, 23*4(t0) // Initial a4 + sw zero, 24*4(t0) // Initial a3 + sw zero, 25*4(t0) // Initial a2 + sw zero, 26*4(t0) // Initial a1 + sw zero, 27*4(t0) // Initial a0 + sw zero, 28*4(t0) // Initial ra + sw a1, 30*4(t0) // Initial mepc (thread entry point) +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + sw zero, 31*4(t0) // Initial ft0 + sw zero, 32*4(t0) // Initial ft1 + sw zero, 33*4(t0) // Initial ft2 + sw zero, 34*4(t0) // Initial ft3 + sw zero, 35*4(t0) // Initial ft4 + sw zero, 36*4(t0) // Initial ft5 + sw zero, 37*4(t0) // Initial ft6 + sw zero, 38*4(t0) // Initial ft7 + sw zero, 39*4(t0) // Initial fs0 + sw zero, 40*4(t0) // Initial fs1 + sw zero, 41*4(t0) // Initial fa0 + sw zero, 42*4(t0) // Initial fa1 + sw zero, 43*4(t0) // Initial fa2 + sw zero, 44*4(t0) // Initial fa3 + sw zero, 45*4(t0) // Initial fa4 + sw zero, 46*4(t0) // Initial fa5 + sw zero, 47*4(t0) // Initial fa6 + sw zero, 48*4(t0) // Initial fa7 + sw zero, 49*4(t0) // Initial fs2 + sw zero, 50*4(t0) // Initial fs3 + sw zero, 51*4(t0) // Initial fs4 + sw zero, 52*4(t0) // Initial fs5 + sw zero, 53*4(t0) // Initial fs6 + sw zero, 54*4(t0) // Initial fs7 + sw zero, 55*4(t0) // Initial fs8 + sw zero, 56*4(t0) // Initial fs9 + sw zero, 57*4(t0) // Initial fs10 + sw zero, 58*4(t0) // Initial fs11 + sw zero, 59*4(t0) // Initial ft8 + sw zero, 60*4(t0) // Initial ft9 + sw zero, 61*4(t0) // Initial ft10 + sw zero, 62*4(t0) // Initial ft11 + csrr a1, fcsr // Read fcsr for initial value + sw a1, 63*4(t0) // Initial fcsr + sw zero, 64*4(t0) // Reserved word (0) +#else + sw zero, 31*4(t0) // Reserved word (0) +#endif + + /* Setup stack pointer. */ + /* thread_ptr -> tx_thread_stack_ptr = t0; */ + + sw t0, 8(a0) // Save stack pointer in thread's + ret // control block and return +/* } */ diff --git a/ports/risc-v32/clang/src/tx_thread_system_return.S b/ports/risc-v32/clang/src/tx_thread_system_return.S new file mode 100644 index 00000000..e8fe5617 --- /dev/null +++ b/ports/risc-v32/clang/src/tx_thread_system_return.S @@ -0,0 +1,174 @@ +/*************************************************************************** + * Copyright (c) 2026 Quintauris + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .section .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return RISC-V32/GNU */ +/* 6.4.x */ +/* AUTHOR */ +/* */ +/* Francisco Merino, Quintauris */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the system. Only a minimal context */ +/* is saved since the compiler assumes temp registers are going to get */ +/* slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 26-02-2026 Francisco Merino Initial Version 6.4.x */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_system_return(VOID) +{ */ + .global _tx_thread_system_return +_tx_thread_system_return: + + /* Save minimal context on the stack. */ + /* sp -= sizeof(stack_frame); */ + +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, -29*4 // Allocate space on the stack - with floating point enabled +#else + addi sp, sp, -16*4 // Allocate space on the stack - without floating point enabled +#endif + + /* Store floating point preserved registers. */ +#if defined(__riscv_float_abi_single) + fsw f8, 15*4(sp) // Store fs0 + fsw f9, 16*4(sp) // Store fs1 + fsw f18, 17*4(sp) // Store fs2 + fsw f19, 18*4(sp) // Store fs3 + fsw f20, 19*4(sp) // Store fs4 + fsw f21, 20*4(sp) // Store fs5 + fsw f22, 21*4(sp) // Store fs6 + fsw f23, 22*4(sp) // Store fs7 + fsw f24, 23*4(sp) // Store fs8 + fsw f25, 24*4(sp) // Store fs9 + fsw f26, 25*4(sp) // Store fs10 + fsw f27, 26*4(sp) // Store fs11 + csrr t0, fcsr + sw t0, 27*4(sp) // Store fcsr +#elif defined(__riscv_float_abi_double) + fsd f8, 15*4(sp) // Store fs0 + fsd f9, 16*4(sp) // Store fs1 + fsd f18, 17*4(sp) // Store fs2 + fsd f19, 18*4(sp) // Store fs3 + fsd f20, 19*4(sp) // Store fs4 + fsd f21, 20*4(sp) // Store fs5 + fsd f22, 21*4(sp) // Store fs6 + fsd f23, 22*4(sp) // Store fs7 + fsd f24, 23*4(sp) // Store fs8 + fsd f25, 24*4(sp) // Store fs9 + fsd f26, 25*4(sp) // Store fs10 + fsd f27, 26*4(sp) // Store fs11 + csrr t0, fcsr + sw t0, 27*4(sp) // Store fcsr +#endif + + sw zero, 0(sp) // Solicited stack type + sw ra, 13*4(sp) // Save return address + sw s0, 12*4(sp) // Save s0 + sw s1, 11*4(sp) // Save s1 + sw s2, 10*4(sp) // Save s2 + sw s3, 9*4(sp) // Save s3 + sw s4, 8*4(sp) // Save s4 + sw s5, 7*4(sp) // Save s5 + sw s6, 6*4(sp) // Save s6 + sw s7, 5*4(sp) // Save s7 + sw s8, 4*4(sp) // Save s8 + sw s9, 3*4(sp) // Save s9 + sw s10, 2*4(sp) // Save s10 + sw s11, 1*4(sp) // Save s11 + csrr t0, mstatus // Pickup mstatus + sw t0, 14*4(sp) // Save mstatus + + + /* Lockout interrupts. will be enabled in _tx_thread_schedule */ + + csrci mstatus, 0x08 // Disable interrupts (MIE bit 3) + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + call _tx_execution_thread_exit // Call the thread execution exit function +#endif + + la t0, _tx_thread_current_ptr // Pickup address of pointer + lw t1, 0(t0) // Pickup current thread pointer + la t2, _tx_thread_system_stack_ptr // Pickup stack pointer address + + /* Save current stack and switch to system stack. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = SP; + SP = _tx_thread_system_stack_ptr; */ + + sw sp, 8(t1) // Save stack pointer + lw sp, 0(t2) // Switch to system stack + + /* Determine if the time-slice is active. */ + /* if (_tx_timer_time_slice) + { */ + + la t4, _tx_timer_time_slice // Pickup time slice variable addr + lw t3, 0(t4) // Pickup time slice value + la t2, _tx_thread_schedule // Pickup address of scheduling loop + beqz t3, _tx_thread_dont_save_ts // If no time-slice, don't save it + + /* Save time-slice for the thread and clear the current time-slice. */ + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + sw t3, 24(t1) // Save current time-slice for thread + sw zero, 0(t4) // Clear time-slice variable + + /* } */ +_tx_thread_dont_save_ts: + + /* Clear the current thread pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + sw x0, 0(t0) // Clear current thread pointer + jr t2 // Return to thread scheduler + +/* } */ diff --git a/ports/risc-v32/clang/src/tx_timer_interrupt.S b/ports/risc-v32/clang/src/tx_timer_interrupt.S new file mode 100644 index 00000000..b32256ba --- /dev/null +++ b/ports/risc-v32/clang/src/tx_timer_interrupt.S @@ -0,0 +1,210 @@ +/*************************************************************************** + * Copyright (c) 2026 Quintauris + * + * This program and the accompanying materials are made available under the + * terms of the MIT License which is available at + * https://opensource.org/licenses/MIT. + * + * SPDX-License-Identifier: MIT + **************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .section .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt RISC-V32/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Francisco Merino, Quintauris */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 01-20-2023 Akif Ejaz Initial Version 6.2.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_timer_interrupt(VOID) +{ */ + .global _tx_timer_interrupt +_tx_timer_interrupt: + + /* Increment the system clock. */ + /* _tx_timer_system_clock++; */ + + la t0, _tx_timer_system_clock // Pickup address of system clock + lw t1, 0(t0) // Pickup system clock + la t2, _tx_timer_time_slice // Pickup address of time slice + lw t3, 0(t2) // Pickup time slice + addi t1, t1, 1 // Increment system clock + sw t1, 0(t0) // Store new system clock + li t6, 0 // Clear local expired flag + + /* Test for time-slice expiration. */ + /* if (_tx_timer_time_slice) + { */ + + beqz t3, _tx_timer_no_time_slice // If 0, skip time slice processing + addi t3, t3, -1 // Decrement the time slice + + /* Decrement the time_slice. */ + /* _tx_timer_time_slice--; */ + + sw t3, 0(t2) // Store new time slice + + /* Check for expiration. */ + /* if (_tx_timer_time_slice == 0) */ + + bgtz t3, _tx_timer_no_time_slice // If not 0, has not expired yet + li t1, 1 // Build expired flag + + /* Set the time-slice expired flag. */ + /* _tx_timer_expired_time_slice = TX_TRUE; */ + + la t4, _tx_timer_expired_time_slice // Get address of expired flag + sw t1, 0(t4) // Set expired flag (UINT) + ori t6, t6, 1 // Set local expired flag + + /* } */ + +_tx_timer_no_time_slice: + + /* Test for timer expiration. */ + /* if (*_tx_timer_current_ptr) + { */ + + la t0, _tx_timer_current_ptr // Pickup address of current ptr + lw t1, 0(t0) // Pickup current pointer (word) + lw t3, 0(t1) // Pickup the current timer entry (word) + la t2, _tx_timer_expired // Pickup address of timer expired flag + li t4, 1 // Build TX_TRUE flag + beqz t3, _tx_timer_no_timer // If NULL, no timer has expired + + /* Set expiration flag. */ + /* _tx_timer_expired = TX_TRUE; */ + + ori t6, t6, 2 // Set local expired flag + sw t4, 0(t2) // Set expired flag in memory (UINT) + j _tx_timer_done // Finished timer processing + + + /* } + else + { */ +_tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + /* _tx_timer_current_ptr++; */ + + /* Check for wrap-around. */ + /* if (_tx_timer_current_ptr == _tx_timer_list_end) */ + + la t2, _tx_timer_list_end // Pickup address of list end pointer + lw t3, 0(t2) // Pickup actual list end + addi t1, t1, 4 // Point to next timer entry + sw t1, 0(t0) // Store new timer pointer + bne t1, t3, _tx_timer_skip_wrap // If not same, good pointer + + /* Wrap to beginning of list. */ + /* _tx_timer_current_ptr = _tx_timer_list_start; */ + + la t2, _tx_timer_list_start // Pickup address of list start pointer + lw t4, 0(t2) // Pickup start of the list + sw t4, 0(t0) // Store new timer pointer + + +_tx_timer_skip_wrap: + /* } */ + +_tx_timer_done: + + + /* See if anything has expired. */ + /* if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + { */ + + beqz t6, _tx_timer_nothing_expired // If nothing expired skip the rest + addi sp, sp, -16 // Allocate some storage on the stack + sw t6, 0(sp) // Save local expired flag + sw ra, 4(sp) // Save ra + + /* Did a timer expire? */ + /* if (_tx_timer_expired) + { */ + + andi t2, t6, 2 // Isolate the timer expired bit + beqz t2, _tx_timer_dont_activate // No, timer not expired + + /* Call the timer expiration processing. */ + /* _tx_timer_expiration_process(void); */ + + call _tx_timer_expiration_process // Call _tx_timer_expiration_process + lw t6, 0(sp) // Recover local expired flag + + /* } */ +_tx_timer_dont_activate: + + /* Did time slice expire? */ + /* if (_tx_timer_expired_time_slice) + { */ + + andi t2, t6, 1 // Is the timer expired bit set? + beqz t2, _tx_timer_not_ts_expiration // If not, skip time slice processing + + /* Time slice interrupted thread. */ + /* _tx_thread_time_slice(); */ + + call _tx_thread_time_slice // Call time slice + + /* } */ + +_tx_timer_not_ts_expiration: + + lw ra, 4(sp) // Recover ra + addi sp, sp, 16 // Recover stack space + /* } */ + +_tx_timer_nothing_expired: + + ret + +/* } */ \ No newline at end of file From 49439bfa9c67fee51852a0e55df3a96aad785a8f Mon Sep 17 00:00:00 2001 From: Francisco Manuel Merino Torres Date: Thu, 26 Feb 2026 11:54:26 +0100 Subject: [PATCH 13/19] Fixes to the RISC-V32 architecture port layer for Clang. --- ports/risc-v32/clang/README.md | 58 ------------------- .../example_build/qemu_virt/demo_threadx.c | 4 ++ .../qemu_virt/tx_initialize_low_level.S | 6 +- ports/risc-v32/clang/inc/tx_port.h | 20 +------ ports/risc-v32/clang/readme_threadx.txt | 12 +++- 5 files changed, 17 insertions(+), 83 deletions(-) delete mode 100644 ports/risc-v32/clang/README.md diff --git a/ports/risc-v32/clang/README.md b/ports/risc-v32/clang/README.md deleted file mode 100644 index 7a4d495c..00000000 --- a/ports/risc-v32/clang/README.md +++ /dev/null @@ -1,58 +0,0 @@ -# RISCV32 clang port - -This is basically a copy of the RISC64 gnu port. -The only major modification was changing the load double word (ld) -and store double double (sd) word with load word (ld) and store word (sd). - -I also added support for semihosting so the example can be executed on QEMU. - -## How to build - -cd to the folder where this repo is cloned and run the following commands: - -``` -cd /threadx/ports/risc-v32/clang/example_build/qemu_virt -./build_libthreadx.sh -./build_threadx_sample.sh -``` - -The first script will build the ThreadX libraries. -You can find the library in /build/libthreadx.a. - -The second script will build the demo application. -You can find the demo application in /ports/risc-v32/clang/example_build/qemu_virt/build/demo_threadx.elf - -## How to run using QEMU - -cd to the folder where this repo is cloned and run the following command: - -``` -docker run --rm -it -p 1234:1234 -v $(pwd):/threadx -w /threadx ghcr.io/quintauris-tech/qemu-system-riscv32-v10:latest bash -``` - -The commands assumes that this repo is clone into a folder named "threadx" - -``` -cd /threadx/ports/risc-v32/clang/example_build/qemu_virt - -qemu-system-riscv32 -machine virt -m 16M -bios ./build/demo_threadx.elf -display none -chardev stdio,id=stdio0 -semihosting-config enable=on,userspace=on,chardev=stdio0 -gdb tcp::1234 -``` - -This should print output from different threads. In the QEMU output you should see output like the following: - -``` -[Thread] : thread_xxxx_entry is here! -``` - -You can use option -S with qemu-system-riscv32 to debug. - -In this case run debugger as /opt/riscv_rv32ima_zicsr/bin/riscv32-unknown-elf-gdb /ports/risc-v32/gnu/example_build/qemu_virt/build/demo_threadx.elf - -``` -target remote :1234 -``` - -to connect to the target. Enter 'c' to continue execution. - - - \ No newline at end of file diff --git a/ports/risc-v32/clang/example_build/qemu_virt/demo_threadx.c b/ports/risc-v32/clang/example_build/qemu_virt/demo_threadx.c index 59aa1640..a5955b29 100644 --- a/ports/risc-v32/clang/example_build/qemu_virt/demo_threadx.c +++ b/ports/risc-v32/clang/example_build/qemu_virt/demo_threadx.c @@ -228,6 +228,8 @@ UINT status; /* Send message to queue 0. */ status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + tx_thread_sleep(2); + /* Check completion status. */ if (status != TX_SUCCESS) { puts("[Thread 1] ERROR: Failed to send message!"); @@ -257,6 +259,8 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + tx_thread_sleep(2); + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)){ diff --git a/ports/risc-v32/clang/example_build/qemu_virt/tx_initialize_low_level.S b/ports/risc-v32/clang/example_build/qemu_virt/tx_initialize_low_level.S index a207d0ae..4cbfcf65 100644 --- a/ports/risc-v32/clang/example_build/qemu_virt/tx_initialize_low_level.S +++ b/ports/risc-v32/clang/example_build/qemu_virt/tx_initialize_low_level.S @@ -67,12 +67,12 @@ .extern _tx_thread_context_restore trap_entry: #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - addi sp, sp, -65*REGBYTES // Allocate space for all registers - with floating point enabled + addi sp, sp, -65*4 // Allocate space for all registers - with floating point enabled #else - addi sp, sp, -32*REGBYTES // Allocate space for all registers - without floating point enabled + addi sp, sp, -32*4 // Allocate space for all registers - without floating point enabled #endif - STORE x1, 28*REGBYTES(sp) // Store RA, 28*REGBYTES(because call will override ra [ra is a calle register in riscv]) + sw x1, 28*4(sp) // Store RA, 28*4(because call will override ra [ra is a calle register in riscv]) call _tx_thread_context_save diff --git a/ports/risc-v32/clang/inc/tx_port.h b/ports/risc-v32/clang/inc/tx_port.h index 81dcdcf7..ece70953 100644 --- a/ports/risc-v32/clang/inc/tx_port.h +++ b/ports/risc-v32/clang/inc/tx_port.h @@ -53,25 +53,7 @@ #ifndef TX_PORT_H #define TX_PORT_H -#ifdef __ASSEMBLER__ - - -#if __riscv_xlen == 64 -# define SLL32 sllw -# define STORE sd -# define LOAD ld -# define LWU lwu -# define LOG_REGBYTES 3 -#else -# define SLL32 sll -# define STORE sw -# define LOAD lw -# define LWU lw -# define LOG_REGBYTES 2 -#endif -#define REGBYTES (1 << LOG_REGBYTES) - -#else /*not __ASSEMBLER__ */ +#ifndef __ASSEMBLER__ /* Include for memset. */ #include diff --git a/ports/risc-v32/clang/readme_threadx.txt b/ports/risc-v32/clang/readme_threadx.txt index caa60986..53ffcf23 100644 --- a/ports/risc-v32/clang/readme_threadx.txt +++ b/ports/risc-v32/clang/readme_threadx.txt @@ -7,10 +7,13 @@ Prerequisites - Install a RISC-V32 bare-metal Clang toolchain -- Install a RISC-V32 bare-metal GNU toolchain with riscv32-unknown-elf prefix -- Common source: https://github.com/riscv-collab/riscv-gnu-toolchain +- Install a RISC-V32 bare-metal GNU toolchain with riscv32-unknown-elf prefix. + Common source: https://github.com/riscv-collab/riscv-gnu-toolchain -Verify the Clang toolchaing: +The GNU toolchain is needed because the Clang toolchain does not include some +standard headers and libraries, i.e. "string.h". + +Verify the Clang toolchain: clang --version Verify the GCC toolchain: @@ -21,6 +24,9 @@ CMake-based build (recommended) From the ThreadX top-level directory: + Set environment variable "GCC_INSTALL_PREFIX" with the location of the + GNU toolchain, i.e., export GCC_INSTALL_PREFIX=/opt/riscv_rv32ima + cmake -Bbuild -GNinja -DCMAKE_TOOLCHAIN_FILE=cmake/riscv32_clang.cmake . cmake --build ./build/ From c62ed82b1a6348c12546c612bf1caab22f82cbee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Desbiens?= Date: Thu, 26 Feb 2026 17:22:25 -0500 Subject: [PATCH 14/19] Added a missing symbol to tx_api.h for TX SMP. --- common_smp/inc/tx_api.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/common_smp/inc/tx_api.h b/common_smp/inc/tx_api.h index ae5ffc8f..cc378f16 100644 --- a/common_smp/inc/tx_api.h +++ b/common_smp/inc/tx_api.h @@ -334,6 +334,14 @@ extern "C" { #endif +/* Define the default maximum message size in a queue. The default value is TX_16_ULONG, but may + be customized in tx_user.h or as a compilation option. */ + +#ifndef TX_QUEUE_MESSAGE_MAX_SIZE +#define TX_QUEUE_MESSAGE_MAX_SIZE TX_16_ULONG +#endif + + /* Event numbers 0 through 4095 are reserved by Azure RTOS. Specific event assignments are: ThreadX events: 1-199 From f4051070dbd788aeebb064d5a5f83b218a6a6686 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Desbiens?= Date: Fri, 27 Feb 2026 10:25:05 -0500 Subject: [PATCH 15/19] Added ax attribute to ThreadX module example build preamble.S files --- .../example_build/sample_threadx_module/txm_module_preamble.S | 2 +- .../example_build/sample_threadx_module/txm_module_preamble.S | 2 +- ports_module/cortex_a7/gnu/example_build/txm_module_preamble.s | 2 +- .../example_build/sample_threadx_module/txm_module_preamble.S | 2 +- ports_module/cortex_m23/gnu/example_build/txm_module_preamble.S | 1 + ports_module/cortex_m3/gnu/example_build/txm_module_preamble.S | 2 +- ports_module/cortex_m33/gnu/example_build/txm_module_preamble.S | 1 + ports_module/cortex_m4/gnu/example_build/txm_module_preamble.S | 2 +- ports_module/cortex_m7/gnu/example_build/txm_module_preamble.S | 2 +- 9 files changed, 9 insertions(+), 7 deletions(-) diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/txm_module_preamble.S index cce29ef8..616d4165 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/txm_module_preamble.S @@ -1,4 +1,4 @@ - .section .txm_module_preamble + .section .txm_module_preamble, "ax" .align 4 // External references diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/txm_module_preamble.S index e41ac007..bb0acb6f 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/txm_module_preamble.S @@ -1,4 +1,4 @@ - .section .txm_module_preamble + .section .txm_module_preamble, "ax" .align 4 // External references diff --git a/ports_module/cortex_a7/gnu/example_build/txm_module_preamble.s b/ports_module/cortex_a7/gnu/example_build/txm_module_preamble.s index 7678628b..0e35f8f0 100644 --- a/ports_module/cortex_a7/gnu/example_build/txm_module_preamble.s +++ b/ports_module/cortex_a7/gnu/example_build/txm_module_preamble.s @@ -1,4 +1,4 @@ - .section .txm_module_preamble + .section .txm_module_preamble, "ax" .align 4 /* Define common external references. */ diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/txm_module_preamble.S index dec92093..b296ed2a 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/txm_module_preamble.S @@ -1,7 +1,7 @@ .text .align 4 .syntax unified - .section .preamble + .section .preamble, "ax" // Define public symbols .global __txm_module_preamble diff --git a/ports_module/cortex_m23/gnu/example_build/txm_module_preamble.S b/ports_module/cortex_m23/gnu/example_build/txm_module_preamble.S index a9413251..ded31277 100644 --- a/ports_module/cortex_m23/gnu/example_build/txm_module_preamble.S +++ b/ports_module/cortex_m23/gnu/example_build/txm_module_preamble.S @@ -1,6 +1,7 @@ .text .align 4 .syntax unified + .section .preamble, "ax" /* Define public symbols. */ .global __txm_module_preamble diff --git a/ports_module/cortex_m3/gnu/example_build/txm_module_preamble.S b/ports_module/cortex_m3/gnu/example_build/txm_module_preamble.S index 590991a6..50814cc8 100644 --- a/ports_module/cortex_m3/gnu/example_build/txm_module_preamble.S +++ b/ports_module/cortex_m3/gnu/example_build/txm_module_preamble.S @@ -1,7 +1,7 @@ .text .align 4 .syntax unified - .section .preamble + .section .preamble, "ax" /* Define public symbols. */ .global __txm_module_preamble diff --git a/ports_module/cortex_m33/gnu/example_build/txm_module_preamble.S b/ports_module/cortex_m33/gnu/example_build/txm_module_preamble.S index a9413251..ded31277 100644 --- a/ports_module/cortex_m33/gnu/example_build/txm_module_preamble.S +++ b/ports_module/cortex_m33/gnu/example_build/txm_module_preamble.S @@ -1,6 +1,7 @@ .text .align 4 .syntax unified + .section .preamble, "ax" /* Define public symbols. */ .global __txm_module_preamble diff --git a/ports_module/cortex_m4/gnu/example_build/txm_module_preamble.S b/ports_module/cortex_m4/gnu/example_build/txm_module_preamble.S index 41ea3d71..ded31277 100644 --- a/ports_module/cortex_m4/gnu/example_build/txm_module_preamble.S +++ b/ports_module/cortex_m4/gnu/example_build/txm_module_preamble.S @@ -1,7 +1,7 @@ .text .align 4 .syntax unified - .section .preamble + .section .preamble, "ax" /* Define public symbols. */ .global __txm_module_preamble diff --git a/ports_module/cortex_m7/gnu/example_build/txm_module_preamble.S b/ports_module/cortex_m7/gnu/example_build/txm_module_preamble.S index 41ea3d71..ded31277 100644 --- a/ports_module/cortex_m7/gnu/example_build/txm_module_preamble.S +++ b/ports_module/cortex_m7/gnu/example_build/txm_module_preamble.S @@ -1,7 +1,7 @@ .text .align 4 .syntax unified - .section .preamble + .section .preamble, "ax" /* Define public symbols. */ .global __txm_module_preamble From ff287cce979e23aa4866edb6ab17e69e3de30a9c Mon Sep 17 00:00:00 2001 From: Akif Ejaz Date: Sun, 1 Mar 2026 14:14:19 +0500 Subject: [PATCH 16/19] update qemu examples as per new rv port format - removed the REGBYTES, STORE/LOAD macros Signed-off-by: Akif Ejaz --- .../qemu_virt/tx_initialize_low_level.S | 16 +++---------- .../example_build/qemu_virt/demo_threadx.c | 2 +- .../qemu_virt/tx_initialize_low_level.S | 23 ++++++++++--------- 3 files changed, 16 insertions(+), 25 deletions(-) diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/tx_initialize_low_level.S b/ports/risc-v32/gnu/example_build/qemu_virt/tx_initialize_low_level.S index 62bb9abb..f4f4a750 100644 --- a/ports/risc-v32/gnu/example_build/qemu_virt/tx_initialize_low_level.S +++ b/ports/risc-v32/gnu/example_build/qemu_virt/tx_initialize_low_level.S @@ -9,7 +9,6 @@ **************************************************************************/ #include "csr.h" -#include "tx_port.h" .section .text .align 4 @@ -67,12 +66,12 @@ .extern _tx_thread_context_restore trap_entry: #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - addi sp, sp, -65*REGBYTES // Allocate space for all registers - with floating point enabled + addi sp, sp, -260 // Allocate space for all registers - with floating point enabled #else - addi sp, sp, -32*REGBYTES // Allocate space for all registers - without floating point enabled + addi sp, sp, -128 // Allocate space for all registers - without floating point enabled #endif - STORE x1, 28*REGBYTES(sp) // Store RA, 28*REGBYTES(because call will override ra [ra is a calle register in riscv]) + sw x1, 112(sp) // Store RA (28*4 = 112, because call will override ra [ra is a callee register in riscv]) call _tx_thread_context_save @@ -139,11 +138,6 @@ _err: .extern board_init _tx_initialize_low_level: -/* debug print - .section .rodata -debug_str_init: - .string "DEBUG : threadx/ports/risc-v32/gnu/example_build/qemu_virt/tx_initialize_low_level.S, _tx_initialize_low_level\n" -*/ .section .text la t0, _tx_thread_system_stack_ptr @@ -166,10 +160,6 @@ debug_str_init: addi sp, sp, -4 sw ra, 0(sp) call board_init -/* debug print - la a0, debug_str_init - call uart_puts -*/ lw ra, 0(sp) addi sp, sp, 4 la t0, trap_entry diff --git a/ports/risc-v64/gnu/example_build/qemu_virt/demo_threadx.c b/ports/risc-v64/gnu/example_build/qemu_virt/demo_threadx.c index dfd8b599..aff197db 100644 --- a/ports/risc-v64/gnu/example_build/qemu_virt/demo_threadx.c +++ b/ports/risc-v64/gnu/example_build/qemu_virt/demo_threadx.c @@ -5,7 +5,7 @@ #include "tx_api.h" #include "uart.h" #define DEMO_STACK_SIZE 1024 -#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BYTE_POOL_SIZE 9180 #define DEMO_BLOCK_POOL_SIZE 100 #define DEMO_QUEUE_SIZE 100 diff --git a/ports/risc-v64/gnu/example_build/qemu_virt/tx_initialize_low_level.S b/ports/risc-v64/gnu/example_build/qemu_virt/tx_initialize_low_level.S index 04d664a2..3c4a00af 100644 --- a/ports/risc-v64/gnu/example_build/qemu_virt/tx_initialize_low_level.S +++ b/ports/risc-v64/gnu/example_build/qemu_virt/tx_initialize_low_level.S @@ -9,7 +9,6 @@ **************************************************************************/ #include "csr.h" -#include "tx_port.h" .section .text .align 4 @@ -67,12 +66,12 @@ .extern _tx_thread_context_restore trap_entry: #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - addi sp, sp, -65*REGBYTES // Allocate space for all registers - with floating point enabled + addi sp, sp, -520 // Allocate space for all registers - with floating point enabled (65*8) #else - addi sp, sp, -32*REGBYTES // Allocate space for all registers - without floating point enabled + addi sp, sp, -256 // Allocate space for all registers - without floating point enabled (32*8) #endif - STORE x1, 28*REGBYTES(sp) // Store RA, 28*REGBYTES(because call will override ra [ra is a calle register in riscv]) + sd x1, 224(sp) // Store RA (28*8 = 224, because call will override ra [ra is a callee register in riscv]) call _tx_thread_context_save @@ -138,19 +137,21 @@ _err: .extern _end .extern board_init _tx_initialize_low_level: - sd sp, _tx_thread_system_stack_ptr, t0 // Save system stack pointer + la t0, _tx_thread_system_stack_ptr + sd sp, 0(t0) // Save system stack pointer - la t0, _end // Pickup first free address - sd t0, _tx_initialize_unused_memory, t1 // Save unused memory address + la t0, _end // Pickup first free address + la t1, _tx_initialize_unused_memory + sd t0, 0(t1) // Save unused memory address li t0, MSTATUS_MIE - csrrc zero, mstatus, t0 // clear MSTATUS_MIE bit + csrrc zero, mstatus, t0 // clear MSTATUS_MIE bit li t0, (MSTATUS_MPP_M | MSTATUS_MPIE ) - csrrs zero, mstatus, t0 // set MSTATUS_MPP, MPIE bit + csrrs zero, mstatus, t0 // set MSTATUS_MPP, MPIE bit li t0, (MIE_MTIE | MIE_MSIE | MIE_MEIE) - csrrs zero, mie, t0 // set mie + csrrs zero, mie, t0 // set mie #ifdef __riscv_flen li t0, MSTATUS_FS - csrrs zero, mstatus, t0 // set MSTATUS_FS bit to open f/d isa in riscv + csrrs zero, mstatus, t0 // set MSTATUS_FS bit to open f/d isa in riscv fscsr x0 #endif addi sp, sp, -8 From cd101d9ab4d4581d978a4bf8befe9af8de173335 Mon Sep 17 00:00:00 2001 From: Akif Ejaz Date: Sun, 1 Mar 2026 15:13:28 +0500 Subject: [PATCH 17/19] update comments Signed-off-by: Akif Ejaz --- .../gnu/example_build/qemu_virt/tx_initialize_low_level.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/tx_initialize_low_level.S b/ports/risc-v32/gnu/example_build/qemu_virt/tx_initialize_low_level.S index f4f4a750..d7108c27 100644 --- a/ports/risc-v32/gnu/example_build/qemu_virt/tx_initialize_low_level.S +++ b/ports/risc-v32/gnu/example_build/qemu_virt/tx_initialize_low_level.S @@ -66,9 +66,9 @@ .extern _tx_thread_context_restore trap_entry: #if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) - addi sp, sp, -260 // Allocate space for all registers - with floating point enabled + addi sp, sp, -260 // Allocate space for all registers - with floating point enabled (65*4) #else - addi sp, sp, -128 // Allocate space for all registers - without floating point enabled + addi sp, sp, -128 // Allocate space for all registers - without floating point enabled (32*4) #endif sw x1, 112(sp) // Store RA (28*4 = 112, because call will override ra [ra is a callee register in riscv]) From da5093f84b2bbe2aa6050b9521a7d8a818dbc96f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Desbiens?= Date: Mon, 2 Mar 2026 14:24:07 +0100 Subject: [PATCH 18/19] Proposed changes to the original PR --- ports/cortex_a12/ac6/src/tx_thread_schedule.S | 6 ++++-- ports/cortex_a12/gnu/src/tx_thread_schedule.S | 6 ++++-- ports/cortex_a15/ac6/src/tx_thread_schedule.S | 6 ++++-- ports/cortex_a15/gnu/src/tx_thread_schedule.S | 6 ++++-- ports/cortex_a15/iar/src/tx_thread_schedule.s | 2 ++ ports/cortex_a17/ac6/src/tx_thread_schedule.S | 6 ++++-- ports/cortex_a17/gnu/src/tx_thread_schedule.S | 6 ++++-- ports/cortex_a34/ac6/src/tx_thread_schedule.S | 2 ++ ports/cortex_a34/gnu/src/tx_thread_schedule.S | 2 ++ ports/cortex_a35/ac6/src/tx_thread_schedule.S | 2 ++ ports/cortex_a35/gnu/src/tx_thread_schedule.S | 2 ++ ports/cortex_a5/ac5/src/tx_thread_schedule.s | 2 ++ ports/cortex_a5/ac6/src/tx_thread_schedule.S | 6 ++++-- ports/cortex_a5/gnu/src/tx_thread_schedule.S | 6 ++++-- ports/cortex_a5/iar/src/tx_thread_schedule.s | 2 ++ ports/cortex_a53/ac6/src/tx_thread_schedule.S | 2 ++ ports/cortex_a53/gnu/src/tx_thread_schedule.S | 2 ++ ports/cortex_a55/ac6/src/tx_thread_schedule.S | 2 ++ ports/cortex_a55/gnu/src/tx_thread_schedule.S | 2 ++ ports/cortex_a57/ac6/src/tx_thread_schedule.S | 2 ++ ports/cortex_a57/gnu/src/tx_thread_schedule.S | 2 ++ ports/cortex_a5x/ac6/src/tx_thread_schedule.S | 2 ++ ports/cortex_a65/ac6/src/tx_thread_schedule.S | 2 ++ ports/cortex_a65/gnu/src/tx_thread_schedule.S | 2 ++ ports/cortex_a65ae/ac6/src/tx_thread_schedule.S | 2 ++ ports/cortex_a65ae/gnu/src/tx_thread_schedule.S | 2 ++ ports/cortex_a7/ac5/src/tx_thread_schedule.s | 2 ++ ports/cortex_a7/ac6/src/tx_thread_schedule.S | 6 ++++-- ports/cortex_a7/gnu/src/tx_thread_schedule.S | 6 ++++-- ports/cortex_a7/iar/src/tx_thread_schedule.s | 2 ++ ports/cortex_a72/ac6/src/tx_thread_schedule.S | 2 ++ ports/cortex_a72/gnu/src/tx_thread_schedule.S | 2 ++ ports/cortex_a73/ac6/src/tx_thread_schedule.S | 2 ++ ports/cortex_a73/gnu/src/tx_thread_schedule.S | 2 ++ ports/cortex_a75/ac6/src/tx_thread_schedule.S | 2 ++ ports/cortex_a75/gnu/src/tx_thread_schedule.S | 2 ++ ports/cortex_a76/ac6/src/tx_thread_schedule.S | 2 ++ ports/cortex_a76/gnu/src/tx_thread_schedule.S | 2 ++ ports/cortex_a76ae/ac6/src/tx_thread_schedule.S | 2 ++ ports/cortex_a76ae/gnu/src/tx_thread_schedule.S | 2 ++ ports/cortex_a77/ac6/src/tx_thread_schedule.S | 2 ++ ports/cortex_a77/gnu/src/tx_thread_schedule.S | 2 ++ ports/cortex_a8/ac5/src/tx_thread_schedule.s | 2 ++ ports/cortex_a8/ac6/src/tx_thread_schedule.S | 6 ++++-- ports/cortex_a8/gnu/src/tx_thread_schedule.S | 6 ++++-- ports/cortex_a8/iar/src/tx_thread_schedule.s | 2 ++ ports/cortex_a9/ac5/src/tx_thread_schedule.s | 2 ++ ports/cortex_a9/ac6/src/tx_thread_schedule.S | 6 ++++-- ports/cortex_a9/gnu/src/tx_thread_schedule.S | 6 ++++-- ports/cortex_a9/iar/src/tx_thread_schedule.s | 2 ++ .../ARMv7-A/threadx/common/src/tx_thread_schedule.S | 9 +++++++++ 51 files changed, 137 insertions(+), 28 deletions(-) diff --git a/ports/cortex_a12/ac6/src/tx_thread_schedule.S b/ports/cortex_a12/ac6/src/tx_thread_schedule.S index 54127015..f46a339b 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a12/ac6/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -40,11 +41,11 @@ #define SVC_MODE 0x13 // SVC mode #ifdef TX_ENABLE_VFP_SUPPORT -IRQ_MASK = 0x080 +#define IRQ_MASK 0x80 #endif #ifdef TX_ENABLE_FIQ_SUPPORT -FIQ_MASK = 0x040 +#define FIQ_MASK 0x40 #endif /**************************************************************************/ @@ -267,3 +268,4 @@ no_fiq: BX lr #endif + diff --git a/ports/cortex_a12/gnu/src/tx_thread_schedule.S b/ports/cortex_a12/gnu/src/tx_thread_schedule.S index 54127015..f46a339b 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a12/gnu/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -40,11 +41,11 @@ #define SVC_MODE 0x13 // SVC mode #ifdef TX_ENABLE_VFP_SUPPORT -IRQ_MASK = 0x080 +#define IRQ_MASK 0x80 #endif #ifdef TX_ENABLE_FIQ_SUPPORT -FIQ_MASK = 0x040 +#define FIQ_MASK 0x40 #endif /**************************************************************************/ @@ -267,3 +268,4 @@ no_fiq: BX lr #endif + diff --git a/ports/cortex_a15/ac6/src/tx_thread_schedule.S b/ports/cortex_a15/ac6/src/tx_thread_schedule.S index 54127015..f46a339b 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a15/ac6/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -40,11 +41,11 @@ #define SVC_MODE 0x13 // SVC mode #ifdef TX_ENABLE_VFP_SUPPORT -IRQ_MASK = 0x080 +#define IRQ_MASK 0x80 #endif #ifdef TX_ENABLE_FIQ_SUPPORT -FIQ_MASK = 0x040 +#define FIQ_MASK 0x40 #endif /**************************************************************************/ @@ -267,3 +268,4 @@ no_fiq: BX lr #endif + diff --git a/ports/cortex_a15/gnu/src/tx_thread_schedule.S b/ports/cortex_a15/gnu/src/tx_thread_schedule.S index 54127015..f46a339b 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a15/gnu/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -40,11 +41,11 @@ #define SVC_MODE 0x13 // SVC mode #ifdef TX_ENABLE_VFP_SUPPORT -IRQ_MASK = 0x080 +#define IRQ_MASK 0x80 #endif #ifdef TX_ENABLE_FIQ_SUPPORT -FIQ_MASK = 0x040 +#define FIQ_MASK 0x40 #endif /**************************************************************************/ @@ -267,3 +268,4 @@ no_fiq: BX lr #endif + diff --git a/ports/cortex_a15/iar/src/tx_thread_schedule.s b/ports/cortex_a15/iar/src/tx_thread_schedule.s index c98087aa..0d2fd007 100644 --- a/ports/cortex_a15/iar/src/tx_thread_schedule.s +++ b/ports/cortex_a15/iar/src/tx_thread_schedule.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -239,3 +240,4 @@ __tx_no_thread_to_disable END + diff --git a/ports/cortex_a17/ac6/src/tx_thread_schedule.S b/ports/cortex_a17/ac6/src/tx_thread_schedule.S index 54127015..f46a339b 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a17/ac6/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -40,11 +41,11 @@ #define SVC_MODE 0x13 // SVC mode #ifdef TX_ENABLE_VFP_SUPPORT -IRQ_MASK = 0x080 +#define IRQ_MASK 0x80 #endif #ifdef TX_ENABLE_FIQ_SUPPORT -FIQ_MASK = 0x040 +#define FIQ_MASK 0x40 #endif /**************************************************************************/ @@ -267,3 +268,4 @@ no_fiq: BX lr #endif + diff --git a/ports/cortex_a17/gnu/src/tx_thread_schedule.S b/ports/cortex_a17/gnu/src/tx_thread_schedule.S index 54127015..f46a339b 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a17/gnu/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -40,11 +41,11 @@ #define SVC_MODE 0x13 // SVC mode #ifdef TX_ENABLE_VFP_SUPPORT -IRQ_MASK = 0x080 +#define IRQ_MASK 0x80 #endif #ifdef TX_ENABLE_FIQ_SUPPORT -FIQ_MASK = 0x040 +#define FIQ_MASK 0x40 #endif /**************************************************************************/ @@ -267,3 +268,4 @@ no_fiq: BX lr #endif + diff --git a/ports/cortex_a34/ac6/src/tx_thread_schedule.S b/ports/cortex_a34/ac6/src/tx_thread_schedule.S index 4612d4b5..8dcc8220 100644 --- a/ports/cortex_a34/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a34/ac6/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -225,3 +226,4 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } + diff --git a/ports/cortex_a34/gnu/src/tx_thread_schedule.S b/ports/cortex_a34/gnu/src/tx_thread_schedule.S index 8b1bbee2..95eb7d5d 100644 --- a/ports/cortex_a34/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a34/gnu/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -231,3 +232,4 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } + diff --git a/ports/cortex_a35/ac6/src/tx_thread_schedule.S b/ports/cortex_a35/ac6/src/tx_thread_schedule.S index 009a0d5b..4cce4a62 100644 --- a/ports/cortex_a35/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a35/ac6/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -230,3 +231,4 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } + diff --git a/ports/cortex_a35/gnu/src/tx_thread_schedule.S b/ports/cortex_a35/gnu/src/tx_thread_schedule.S index 009a0d5b..4cce4a62 100644 --- a/ports/cortex_a35/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a35/gnu/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -230,3 +231,4 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } + diff --git a/ports/cortex_a5/ac5/src/tx_thread_schedule.s b/ports/cortex_a5/ac5/src/tx_thread_schedule.s index 4ff4083c..b75c6836 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_a5/ac5/src/tx_thread_schedule.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -233,3 +234,4 @@ __tx_no_thread_to_disable END + diff --git a/ports/cortex_a5/ac6/src/tx_thread_schedule.S b/ports/cortex_a5/ac6/src/tx_thread_schedule.S index 54127015..f46a339b 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a5/ac6/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -40,11 +41,11 @@ #define SVC_MODE 0x13 // SVC mode #ifdef TX_ENABLE_VFP_SUPPORT -IRQ_MASK = 0x080 +#define IRQ_MASK 0x80 #endif #ifdef TX_ENABLE_FIQ_SUPPORT -FIQ_MASK = 0x040 +#define FIQ_MASK 0x40 #endif /**************************************************************************/ @@ -267,3 +268,4 @@ no_fiq: BX lr #endif + diff --git a/ports/cortex_a5/gnu/src/tx_thread_schedule.S b/ports/cortex_a5/gnu/src/tx_thread_schedule.S index 54127015..19627892 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a5/gnu/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -40,11 +41,11 @@ #define SVC_MODE 0x13 // SVC mode #ifdef TX_ENABLE_VFP_SUPPORT -IRQ_MASK = 0x080 +#define IRQ_MASK 0x80 #endif #ifdef TX_ENABLE_FIQ_SUPPORT -FIQ_MASK = 0x040 +#define FIQ_MASK 0x40 #endif /**************************************************************************/ @@ -267,3 +268,4 @@ no_fiq: BX lr #endif + diff --git a/ports/cortex_a5/iar/src/tx_thread_schedule.s b/ports/cortex_a5/iar/src/tx_thread_schedule.s index 7565b57a..2390c450 100644 --- a/ports/cortex_a5/iar/src/tx_thread_schedule.s +++ b/ports/cortex_a5/iar/src/tx_thread_schedule.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -243,3 +244,4 @@ __tx_no_thread_to_disable: END + diff --git a/ports/cortex_a53/ac6/src/tx_thread_schedule.S b/ports/cortex_a53/ac6/src/tx_thread_schedule.S index 009a0d5b..4cce4a62 100644 --- a/ports/cortex_a53/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a53/ac6/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -230,3 +231,4 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } + diff --git a/ports/cortex_a53/gnu/src/tx_thread_schedule.S b/ports/cortex_a53/gnu/src/tx_thread_schedule.S index 009a0d5b..4cce4a62 100644 --- a/ports/cortex_a53/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a53/gnu/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -230,3 +231,4 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } + diff --git a/ports/cortex_a55/ac6/src/tx_thread_schedule.S b/ports/cortex_a55/ac6/src/tx_thread_schedule.S index 009a0d5b..4cce4a62 100644 --- a/ports/cortex_a55/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a55/ac6/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -230,3 +231,4 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } + diff --git a/ports/cortex_a55/gnu/src/tx_thread_schedule.S b/ports/cortex_a55/gnu/src/tx_thread_schedule.S index 009a0d5b..4cce4a62 100644 --- a/ports/cortex_a55/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a55/gnu/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -230,3 +231,4 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } + diff --git a/ports/cortex_a57/ac6/src/tx_thread_schedule.S b/ports/cortex_a57/ac6/src/tx_thread_schedule.S index 009a0d5b..4cce4a62 100644 --- a/ports/cortex_a57/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a57/ac6/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -230,3 +231,4 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } + diff --git a/ports/cortex_a57/gnu/src/tx_thread_schedule.S b/ports/cortex_a57/gnu/src/tx_thread_schedule.S index 009a0d5b..4cce4a62 100644 --- a/ports/cortex_a57/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a57/gnu/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -230,3 +231,4 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } + diff --git a/ports/cortex_a5x/ac6/src/tx_thread_schedule.S b/ports/cortex_a5x/ac6/src/tx_thread_schedule.S index 42bd0e4f..37778ce8 100644 --- a/ports/cortex_a5x/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a5x/ac6/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -237,3 +238,4 @@ _skip_solicited_fp_restore: /* } */ + diff --git a/ports/cortex_a65/ac6/src/tx_thread_schedule.S b/ports/cortex_a65/ac6/src/tx_thread_schedule.S index 009a0d5b..4cce4a62 100644 --- a/ports/cortex_a65/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a65/ac6/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -230,3 +231,4 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } + diff --git a/ports/cortex_a65/gnu/src/tx_thread_schedule.S b/ports/cortex_a65/gnu/src/tx_thread_schedule.S index 009a0d5b..4cce4a62 100644 --- a/ports/cortex_a65/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a65/gnu/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -230,3 +231,4 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } + diff --git a/ports/cortex_a65ae/ac6/src/tx_thread_schedule.S b/ports/cortex_a65ae/ac6/src/tx_thread_schedule.S index 009a0d5b..4cce4a62 100644 --- a/ports/cortex_a65ae/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a65ae/ac6/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -230,3 +231,4 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } + diff --git a/ports/cortex_a65ae/gnu/src/tx_thread_schedule.S b/ports/cortex_a65ae/gnu/src/tx_thread_schedule.S index 009a0d5b..4cce4a62 100644 --- a/ports/cortex_a65ae/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a65ae/gnu/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -230,3 +231,4 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } + diff --git a/ports/cortex_a7/ac5/src/tx_thread_schedule.s b/ports/cortex_a7/ac5/src/tx_thread_schedule.s index 0f10a537..a0f10476 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_a7/ac5/src/tx_thread_schedule.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -233,3 +234,4 @@ __tx_no_thread_to_disable END + diff --git a/ports/cortex_a7/ac6/src/tx_thread_schedule.S b/ports/cortex_a7/ac6/src/tx_thread_schedule.S index 54127015..f46a339b 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a7/ac6/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -40,11 +41,11 @@ #define SVC_MODE 0x13 // SVC mode #ifdef TX_ENABLE_VFP_SUPPORT -IRQ_MASK = 0x080 +#define IRQ_MASK 0x80 #endif #ifdef TX_ENABLE_FIQ_SUPPORT -FIQ_MASK = 0x040 +#define FIQ_MASK 0x40 #endif /**************************************************************************/ @@ -267,3 +268,4 @@ no_fiq: BX lr #endif + diff --git a/ports/cortex_a7/gnu/src/tx_thread_schedule.S b/ports/cortex_a7/gnu/src/tx_thread_schedule.S index 54127015..f46a339b 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a7/gnu/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -40,11 +41,11 @@ #define SVC_MODE 0x13 // SVC mode #ifdef TX_ENABLE_VFP_SUPPORT -IRQ_MASK = 0x080 +#define IRQ_MASK 0x80 #endif #ifdef TX_ENABLE_FIQ_SUPPORT -FIQ_MASK = 0x040 +#define FIQ_MASK 0x40 #endif /**************************************************************************/ @@ -267,3 +268,4 @@ no_fiq: BX lr #endif + diff --git a/ports/cortex_a7/iar/src/tx_thread_schedule.s b/ports/cortex_a7/iar/src/tx_thread_schedule.s index 985da38e..0486e767 100644 --- a/ports/cortex_a7/iar/src/tx_thread_schedule.s +++ b/ports/cortex_a7/iar/src/tx_thread_schedule.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -239,3 +240,4 @@ __tx_no_thread_to_disable: END + diff --git a/ports/cortex_a72/ac6/src/tx_thread_schedule.S b/ports/cortex_a72/ac6/src/tx_thread_schedule.S index 009a0d5b..4cce4a62 100644 --- a/ports/cortex_a72/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a72/ac6/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -230,3 +231,4 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } + diff --git a/ports/cortex_a72/gnu/src/tx_thread_schedule.S b/ports/cortex_a72/gnu/src/tx_thread_schedule.S index 009a0d5b..4cce4a62 100644 --- a/ports/cortex_a72/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a72/gnu/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -230,3 +231,4 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } + diff --git a/ports/cortex_a73/ac6/src/tx_thread_schedule.S b/ports/cortex_a73/ac6/src/tx_thread_schedule.S index 009a0d5b..4cce4a62 100644 --- a/ports/cortex_a73/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a73/ac6/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -230,3 +231,4 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } + diff --git a/ports/cortex_a73/gnu/src/tx_thread_schedule.S b/ports/cortex_a73/gnu/src/tx_thread_schedule.S index 009a0d5b..4cce4a62 100644 --- a/ports/cortex_a73/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a73/gnu/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -230,3 +231,4 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } + diff --git a/ports/cortex_a75/ac6/src/tx_thread_schedule.S b/ports/cortex_a75/ac6/src/tx_thread_schedule.S index 009a0d5b..4cce4a62 100644 --- a/ports/cortex_a75/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a75/ac6/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -230,3 +231,4 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } + diff --git a/ports/cortex_a75/gnu/src/tx_thread_schedule.S b/ports/cortex_a75/gnu/src/tx_thread_schedule.S index 009a0d5b..4cce4a62 100644 --- a/ports/cortex_a75/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a75/gnu/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -230,3 +231,4 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } + diff --git a/ports/cortex_a76/ac6/src/tx_thread_schedule.S b/ports/cortex_a76/ac6/src/tx_thread_schedule.S index 009a0d5b..4cce4a62 100644 --- a/ports/cortex_a76/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a76/ac6/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -230,3 +231,4 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } + diff --git a/ports/cortex_a76/gnu/src/tx_thread_schedule.S b/ports/cortex_a76/gnu/src/tx_thread_schedule.S index 009a0d5b..4cce4a62 100644 --- a/ports/cortex_a76/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a76/gnu/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -230,3 +231,4 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } + diff --git a/ports/cortex_a76ae/ac6/src/tx_thread_schedule.S b/ports/cortex_a76ae/ac6/src/tx_thread_schedule.S index 009a0d5b..4cce4a62 100644 --- a/ports/cortex_a76ae/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a76ae/ac6/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -230,3 +231,4 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } + diff --git a/ports/cortex_a76ae/gnu/src/tx_thread_schedule.S b/ports/cortex_a76ae/gnu/src/tx_thread_schedule.S index 009a0d5b..4cce4a62 100644 --- a/ports/cortex_a76ae/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a76ae/gnu/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -230,3 +231,4 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } + diff --git a/ports/cortex_a77/ac6/src/tx_thread_schedule.S b/ports/cortex_a77/ac6/src/tx_thread_schedule.S index 009a0d5b..4cce4a62 100644 --- a/ports/cortex_a77/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a77/ac6/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -230,3 +231,4 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } + diff --git a/ports/cortex_a77/gnu/src/tx_thread_schedule.S b/ports/cortex_a77/gnu/src/tx_thread_schedule.S index 009a0d5b..4cce4a62 100644 --- a/ports/cortex_a77/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a77/gnu/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -230,3 +231,4 @@ _skip_solicited_fp_restore: MSR DAIF, x4 // Recover DAIF RET // Return to caller // } + diff --git a/ports/cortex_a8/ac5/src/tx_thread_schedule.s b/ports/cortex_a8/ac5/src/tx_thread_schedule.s index f5982192..42645b44 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_a8/ac5/src/tx_thread_schedule.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -233,3 +234,4 @@ __tx_no_thread_to_disable END + diff --git a/ports/cortex_a8/ac6/src/tx_thread_schedule.S b/ports/cortex_a8/ac6/src/tx_thread_schedule.S index 54127015..f46a339b 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a8/ac6/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -40,11 +41,11 @@ #define SVC_MODE 0x13 // SVC mode #ifdef TX_ENABLE_VFP_SUPPORT -IRQ_MASK = 0x080 +#define IRQ_MASK 0x80 #endif #ifdef TX_ENABLE_FIQ_SUPPORT -FIQ_MASK = 0x040 +#define FIQ_MASK 0x40 #endif /**************************************************************************/ @@ -267,3 +268,4 @@ no_fiq: BX lr #endif + diff --git a/ports/cortex_a8/gnu/src/tx_thread_schedule.S b/ports/cortex_a8/gnu/src/tx_thread_schedule.S index 54127015..f46a339b 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a8/gnu/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -40,11 +41,11 @@ #define SVC_MODE 0x13 // SVC mode #ifdef TX_ENABLE_VFP_SUPPORT -IRQ_MASK = 0x080 +#define IRQ_MASK 0x80 #endif #ifdef TX_ENABLE_FIQ_SUPPORT -FIQ_MASK = 0x040 +#define FIQ_MASK 0x40 #endif /**************************************************************************/ @@ -267,3 +268,4 @@ no_fiq: BX lr #endif + diff --git a/ports/cortex_a8/iar/src/tx_thread_schedule.s b/ports/cortex_a8/iar/src/tx_thread_schedule.s index 0688152e..c7a4f3f8 100644 --- a/ports/cortex_a8/iar/src/tx_thread_schedule.s +++ b/ports/cortex_a8/iar/src/tx_thread_schedule.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -239,3 +240,4 @@ __tx_no_thread_to_disable: END + diff --git a/ports/cortex_a9/ac5/src/tx_thread_schedule.s b/ports/cortex_a9/ac5/src/tx_thread_schedule.s index 664bc10e..2b986ee5 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_a9/ac5/src/tx_thread_schedule.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -233,3 +234,4 @@ __tx_no_thread_to_disable END + diff --git a/ports/cortex_a9/ac6/src/tx_thread_schedule.S b/ports/cortex_a9/ac6/src/tx_thread_schedule.S index 54127015..f46a339b 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a9/ac6/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -40,11 +41,11 @@ #define SVC_MODE 0x13 // SVC mode #ifdef TX_ENABLE_VFP_SUPPORT -IRQ_MASK = 0x080 +#define IRQ_MASK 0x80 #endif #ifdef TX_ENABLE_FIQ_SUPPORT -FIQ_MASK = 0x040 +#define FIQ_MASK 0x40 #endif /**************************************************************************/ @@ -267,3 +268,4 @@ no_fiq: BX lr #endif + diff --git a/ports/cortex_a9/gnu/src/tx_thread_schedule.S b/ports/cortex_a9/gnu/src/tx_thread_schedule.S index 54127015..f46a339b 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a9/gnu/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -40,11 +41,11 @@ #define SVC_MODE 0x13 // SVC mode #ifdef TX_ENABLE_VFP_SUPPORT -IRQ_MASK = 0x080 +#define IRQ_MASK 0x80 #endif #ifdef TX_ENABLE_FIQ_SUPPORT -FIQ_MASK = 0x040 +#define FIQ_MASK 0x40 #endif /**************************************************************************/ @@ -267,3 +268,4 @@ no_fiq: BX lr #endif + diff --git a/ports/cortex_a9/iar/src/tx_thread_schedule.s b/ports/cortex_a9/iar/src/tx_thread_schedule.s index 8f221f16..a2367096 100644 --- a/ports/cortex_a9/iar/src/tx_thread_schedule.s +++ b/ports/cortex_a9/iar/src/tx_thread_schedule.s @@ -1,5 +1,6 @@ ;/*************************************************************************** ; * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors ; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at @@ -240,3 +241,4 @@ __tx_no_thread_to_disable: END + diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_schedule.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_schedule.S index 07dd6f7f..5be10faa 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_schedule.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_schedule.S @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (C) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -39,6 +40,14 @@ #define IRQ_MODE 0x12 // IRQ mode #define SVC_MODE 0x13 // SVC mode +#ifdef TX_ENABLE_VFP_SUPPORT +#define IRQ_MASK 0x80 +#endif + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define FIQ_MASK 0x40 +#endif + /**************************************************************************/ /* */ /* FUNCTION RELEASE */ From c3259a216026372e3833dd8996a68f77e8595fbd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Desbiens?= Date: Thu, 5 Mar 2026 10:46:30 +0100 Subject: [PATCH 19/19] Updated copyright headers and version number constants (#509) * Updated version number constants * Removed revision history from all files * Added Eclipse ThreadX contributors' copyright header --- .github/workflows/ci_cortex_m.yml | 2 +- .github/workflows/regression_template.yml | 16 +- .gitignore | 1 + CHANGELOG.md | 2 +- CMakeLists.txt | 6 +- CONTRIBUTING.md | 10 +- README.md | 14 +- common/CMakeLists.txt | 4 +- common/inc/tx_api.h | 85 +- common/inc/tx_block_pool.h | 15 +- common/inc/tx_byte_pool.h | 15 +- common/inc/tx_event_flags.h | 15 +- common/inc/tx_initialize.h | 15 +- common/inc/tx_mutex.h | 15 +- common/inc/tx_queue.h | 15 +- common/inc/tx_semaphore.h | 15 +- common/inc/tx_thread.h | 22 +- common/inc/tx_timer.h | 15 +- common/inc/tx_trace.h | 15 +- common/inc/tx_user_sample.h | 36 +- common/src/tx_block_allocate.c | 15 +- common/src/tx_block_pool_cleanup.c | 15 +- common/src/tx_block_pool_create.c | 15 +- common/src/tx_block_pool_delete.c | 15 +- common/src/tx_block_pool_info_get.c | 15 +- common/src/tx_block_pool_initialize.c | 18 +- .../src/tx_block_pool_performance_info_get.c | 15 +- ...x_block_pool_performance_system_info_get.c | 15 +- common/src/tx_block_pool_prioritize.c | 15 +- common/src/tx_block_release.c | 15 +- common/src/tx_byte_allocate.c | 15 +- common/src/tx_byte_pool_cleanup.c | 15 +- common/src/tx_byte_pool_create.c | 15 +- common/src/tx_byte_pool_delete.c | 15 +- common/src/tx_byte_pool_info_get.c | 15 +- common/src/tx_byte_pool_initialize.c | 18 +- .../src/tx_byte_pool_performance_info_get.c | 15 +- ...tx_byte_pool_performance_system_info_get.c | 15 +- common/src/tx_byte_pool_prioritize.c | 15 +- common/src/tx_byte_pool_search.c | 18 +- common/src/tx_byte_release.c | 15 +- common/src/tx_event_flags_cleanup.c | 15 +- common/src/tx_event_flags_create.c | 15 +- common/src/tx_event_flags_delete.c | 15 +- common/src/tx_event_flags_get.c | 21 +- common/src/tx_event_flags_info_get.c | 15 +- common/src/tx_event_flags_initialize.c | 18 +- .../src/tx_event_flags_performance_info_get.c | 15 +- ..._event_flags_performance_system_info_get.c | 15 +- common/src/tx_event_flags_set.c | 23 +- common/src/tx_event_flags_set_notify.c | 15 +- common/src/tx_initialize_high_level.c | 15 +- common/src/tx_initialize_kernel_enter.c | 22 +- common/src/tx_initialize_kernel_setup.c | 15 +- common/src/tx_misra.c | 9 +- common/src/tx_mutex_cleanup.c | 15 +- common/src/tx_mutex_create.c | 15 +- common/src/tx_mutex_delete.c | 15 +- common/src/tx_mutex_get.c | 15 +- common/src/tx_mutex_info_get.c | 15 +- common/src/tx_mutex_initialize.c | 18 +- common/src/tx_mutex_performance_info_get.c | 15 +- .../tx_mutex_performance_system_info_get.c | 15 +- common/src/tx_mutex_prioritize.c | 15 +- common/src/tx_mutex_priority_change.c | 24 +- common/src/tx_mutex_put.c | 15 +- common/src/tx_queue_cleanup.c | 15 +- common/src/tx_queue_create.c | 15 +- common/src/tx_queue_delete.c | 15 +- common/src/tx_queue_flush.c | 15 +- common/src/tx_queue_front_send.c | 15 +- common/src/tx_queue_info_get.c | 15 +- common/src/tx_queue_initialize.c | 18 +- common/src/tx_queue_performance_info_get.c | 15 +- .../tx_queue_performance_system_info_get.c | 15 +- common/src/tx_queue_prioritize.c | 15 +- common/src/tx_queue_receive.c | 15 +- common/src/tx_queue_send.c | 15 +- common/src/tx_queue_send_notify.c | 15 +- common/src/tx_semaphore_ceiling_put.c | 15 +- common/src/tx_semaphore_cleanup.c | 15 +- common/src/tx_semaphore_create.c | 15 +- common/src/tx_semaphore_delete.c | 15 +- common/src/tx_semaphore_get.c | 15 +- common/src/tx_semaphore_info_get.c | 15 +- common/src/tx_semaphore_initialize.c | 18 +- .../src/tx_semaphore_performance_info_get.c | 15 +- ...tx_semaphore_performance_system_info_get.c | 15 +- common/src/tx_semaphore_prioritize.c | 15 +- common/src/tx_semaphore_put.c | 15 +- common/src/tx_semaphore_put_notify.c | 15 +- common/src/tx_thread_create.c | 25 +- common/src/tx_thread_delete.c | 15 +- common/src/tx_thread_entry_exit_notify.c | 15 +- common/src/tx_thread_identify.c | 15 +- common/src/tx_thread_info_get.c | 15 +- common/src/tx_thread_initialize.c | 87 +- common/src/tx_thread_performance_info_get.c | 15 +- .../tx_thread_performance_system_info_get.c | 15 +- common/src/tx_thread_preemption_change.c | 15 +- common/src/tx_thread_priority_change.c | 20 +- common/src/tx_thread_relinquish.c | 15 +- common/src/tx_thread_reset.c | 15 +- common/src/tx_thread_resume.c | 15 +- common/src/tx_thread_shell_entry.c | 15 +- common/src/tx_thread_sleep.c | 15 +- common/src/tx_thread_stack_analyze.c | 15 +- common/src/tx_thread_stack_error_handler.c | 27 +- common/src/tx_thread_stack_error_notify.c | 22 +- common/src/tx_thread_suspend.c | 19 +- common/src/tx_thread_system_preempt_check.c | 15 +- common/src/tx_thread_system_resume.c | 15 +- common/src/tx_thread_system_suspend.c | 15 +- common/src/tx_thread_terminate.c | 15 +- common/src/tx_thread_time_slice.c | 17 +- common/src/tx_thread_time_slice_change.c | 15 +- common/src/tx_thread_timeout.c | 15 +- common/src/tx_thread_wait_abort.c | 18 +- common/src/tx_time_get.c | 17 +- common/src/tx_time_set.c | 15 +- common/src/tx_timer_activate.c | 15 +- common/src/tx_timer_change.c | 15 +- common/src/tx_timer_create.c | 15 +- common/src/tx_timer_deactivate.c | 15 +- common/src/tx_timer_delete.c | 15 +- common/src/tx_timer_expiration_process.c | 17 +- common/src/tx_timer_info_get.c | 15 +- common/src/tx_timer_initialize.c | 15 +- common/src/tx_timer_performance_info_get.c | 15 +- .../tx_timer_performance_system_info_get.c | 15 +- common/src/tx_timer_system_activate.c | 17 +- common/src/tx_timer_system_deactivate.c | 15 +- common/src/tx_timer_thread_entry.c | 15 +- common/src/tx_trace_buffer_full_notify.c | 15 +- common/src/tx_trace_disable.c | 15 +- common/src/tx_trace_enable.c | 15 +- common/src/tx_trace_event_filter.c | 15 +- common/src/tx_trace_event_unfilter.c | 15 +- common/src/tx_trace_initialize.c | 15 +- common/src/tx_trace_interrupt_control.c | 15 +- common/src/tx_trace_isr_enter_insert.c | 15 +- common/src/tx_trace_isr_exit_insert.c | 15 +- common/src/tx_trace_object_register.c | 18 +- common/src/tx_trace_object_unregister.c | 15 +- common/src/tx_trace_user_event_insert.c | 15 +- common/src/txe_block_allocate.c | 15 +- common/src/txe_block_pool_create.c | 15 +- common/src/txe_block_pool_delete.c | 15 +- common/src/txe_block_pool_info_get.c | 15 +- common/src/txe_block_pool_prioritize.c | 15 +- common/src/txe_block_release.c | 15 +- common/src/txe_byte_allocate.c | 15 +- common/src/txe_byte_pool_create.c | 15 +- common/src/txe_byte_pool_delete.c | 15 +- common/src/txe_byte_pool_info_get.c | 15 +- common/src/txe_byte_pool_prioritize.c | 15 +- common/src/txe_byte_release.c | 15 +- common/src/txe_event_flags_create.c | 15 +- common/src/txe_event_flags_delete.c | 15 +- common/src/txe_event_flags_get.c | 15 +- common/src/txe_event_flags_info_get.c | 15 +- common/src/txe_event_flags_set.c | 15 +- common/src/txe_event_flags_set_notify.c | 15 +- common/src/txe_mutex_create.c | 15 +- common/src/txe_mutex_delete.c | 15 +- common/src/txe_mutex_get.c | 15 +- common/src/txe_mutex_info_get.c | 15 +- common/src/txe_mutex_prioritize.c | 15 +- common/src/txe_mutex_put.c | 15 +- common/src/txe_queue_create.c | 15 +- common/src/txe_queue_delete.c | 15 +- common/src/txe_queue_flush.c | 15 +- common/src/txe_queue_front_send.c | 15 +- common/src/txe_queue_info_get.c | 15 +- common/src/txe_queue_prioritize.c | 15 +- common/src/txe_queue_receive.c | 15 +- common/src/txe_queue_send.c | 15 +- common/src/txe_queue_send_notify.c | 15 +- common/src/txe_semaphore_ceiling_put.c | 15 +- common/src/txe_semaphore_create.c | 15 +- common/src/txe_semaphore_delete.c | 15 +- common/src/txe_semaphore_get.c | 15 +- common/src/txe_semaphore_info_get.c | 15 +- common/src/txe_semaphore_prioritize.c | 15 +- common/src/txe_semaphore_put.c | 15 +- common/src/txe_semaphore_put_notify.c | 15 +- common/src/txe_thread_create.c | 15 +- common/src/txe_thread_delete.c | 15 +- common/src/txe_thread_entry_exit_notify.c | 15 +- common/src/txe_thread_info_get.c | 15 +- common/src/txe_thread_preemption_change.c | 15 +- common/src/txe_thread_priority_change.c | 15 +- common/src/txe_thread_relinquish.c | 15 +- common/src/txe_thread_reset.c | 15 +- common/src/txe_thread_resume.c | 15 +- common/src/txe_thread_suspend.c | 15 +- common/src/txe_thread_terminate.c | 15 +- common/src/txe_thread_time_slice_change.c | 15 +- common/src/txe_thread_wait_abort.c | 15 +- common/src/txe_timer_activate.c | 15 +- common/src/txe_timer_change.c | 15 +- common/src/txe_timer_create.c | 15 +- common/src/txe_timer_deactivate.c | 15 +- common/src/txe_timer_delete.c | 15 +- common/src/txe_timer_info_get.c | 15 +- common_modules/inc/txm_module.h | 19 +- common_modules/inc/txm_module_user_sample.h | 16 +- .../module_lib/src/txm_block_allocate.c | 16 +- .../module_lib/src/txm_block_pool_create.c | 16 +- .../module_lib/src/txm_block_pool_delete.c | 16 +- .../module_lib/src/txm_block_pool_info_get.c | 16 +- .../src/txm_block_pool_performance_info_get.c | 16 +- ...m_block_pool_performance_system_info_get.c | 16 +- .../src/txm_block_pool_prioritize.c | 16 +- .../module_lib/src/txm_block_release.c | 16 +- .../module_lib/src/txm_byte_allocate.c | 16 +- .../module_lib/src/txm_byte_pool_create.c | 16 +- .../module_lib/src/txm_byte_pool_delete.c | 16 +- .../module_lib/src/txm_byte_pool_info_get.c | 16 +- .../src/txm_byte_pool_performance_info_get.c | 16 +- ...xm_byte_pool_performance_system_info_get.c | 16 +- .../module_lib/src/txm_byte_pool_prioritize.c | 16 +- .../module_lib/src/txm_byte_release.c | 16 +- .../module_lib/src/txm_event_flags_create.c | 16 +- .../module_lib/src/txm_event_flags_delete.c | 16 +- .../module_lib/src/txm_event_flags_get.c | 16 +- .../module_lib/src/txm_event_flags_info_get.c | 16 +- .../txm_event_flags_performance_info_get.c | 16 +- ..._event_flags_performance_system_info_get.c | 16 +- .../module_lib/src/txm_event_flags_set.c | 16 +- .../src/txm_event_flags_set_notify.c | 16 +- .../src/txm_module_application_request.c | 16 +- ...txm_module_callback_request_thread_entry.c | 16 +- .../src/txm_module_object_allocate.c | 16 +- .../src/txm_module_object_deallocate.c | 16 +- .../src/txm_module_object_pointer_get.c | 16 +- .../txm_module_object_pointer_get_extended.c | 16 +- .../src/txm_module_thread_system_suspend.c | 16 +- .../module_lib/src/txm_mutex_create.c | 16 +- .../module_lib/src/txm_mutex_delete.c | 16 +- common_modules/module_lib/src/txm_mutex_get.c | 16 +- .../module_lib/src/txm_mutex_info_get.c | 16 +- .../src/txm_mutex_performance_info_get.c | 16 +- .../txm_mutex_performance_system_info_get.c | 16 +- .../module_lib/src/txm_mutex_prioritize.c | 16 +- common_modules/module_lib/src/txm_mutex_put.c | 16 +- .../module_lib/src/txm_queue_create.c | 16 +- .../module_lib/src/txm_queue_delete.c | 16 +- .../module_lib/src/txm_queue_flush.c | 16 +- .../module_lib/src/txm_queue_front_send.c | 16 +- .../module_lib/src/txm_queue_info_get.c | 16 +- .../src/txm_queue_performance_info_get.c | 16 +- .../txm_queue_performance_system_info_get.c | 16 +- .../module_lib/src/txm_queue_prioritize.c | 16 +- .../module_lib/src/txm_queue_receive.c | 16 +- .../module_lib/src/txm_queue_send.c | 16 +- .../module_lib/src/txm_queue_send_notify.c | 16 +- .../src/txm_semaphore_ceiling_put.c | 16 +- .../module_lib/src/txm_semaphore_create.c | 16 +- .../module_lib/src/txm_semaphore_delete.c | 16 +- .../module_lib/src/txm_semaphore_get.c | 16 +- .../module_lib/src/txm_semaphore_info_get.c | 16 +- .../src/txm_semaphore_performance_info_get.c | 16 +- ...xm_semaphore_performance_system_info_get.c | 16 +- .../module_lib/src/txm_semaphore_prioritize.c | 16 +- .../module_lib/src/txm_semaphore_put.c | 16 +- .../module_lib/src/txm_semaphore_put_notify.c | 16 +- .../module_lib/src/txm_thread_create.c | 16 +- .../module_lib/src/txm_thread_delete.c | 16 +- .../src/txm_thread_entry_exit_notify.c | 16 +- .../module_lib/src/txm_thread_identify.c | 16 +- .../module_lib/src/txm_thread_info_get.c | 16 +- .../src/txm_thread_interrupt_control.c | 16 +- .../src/txm_thread_performance_info_get.c | 16 +- .../txm_thread_performance_system_info_get.c | 16 +- .../src/txm_thread_preemption_change.c | 16 +- .../src/txm_thread_priority_change.c | 16 +- .../module_lib/src/txm_thread_relinquish.c | 16 +- .../module_lib/src/txm_thread_reset.c | 16 +- .../module_lib/src/txm_thread_resume.c | 16 +- .../module_lib/src/txm_thread_sleep.c | 16 +- .../src/txm_thread_stack_error_notify.c | 16 +- .../module_lib/src/txm_thread_suspend.c | 16 +- .../module_lib/src/txm_thread_terminate.c | 16 +- .../src/txm_thread_time_slice_change.c | 16 +- .../module_lib/src/txm_thread_wait_abort.c | 16 +- common_modules/module_lib/src/txm_time_get.c | 16 +- common_modules/module_lib/src/txm_time_set.c | 16 +- .../module_lib/src/txm_timer_activate.c | 16 +- .../module_lib/src/txm_timer_change.c | 16 +- .../module_lib/src/txm_timer_create.c | 16 +- .../module_lib/src/txm_timer_deactivate.c | 16 +- .../module_lib/src/txm_timer_delete.c | 16 +- .../module_lib/src/txm_timer_info_get.c | 16 +- .../src/txm_timer_performance_info_get.c | 16 +- .../txm_timer_performance_system_info_get.c | 16 +- .../src/txm_trace_buffer_full_notify.c | 16 +- .../module_lib/src/txm_trace_disable.c | 16 +- .../module_lib/src/txm_trace_enable.c | 16 +- .../module_lib/src/txm_trace_event_filter.c | 16 +- .../module_lib/src/txm_trace_event_unfilter.c | 16 +- .../src/txm_trace_interrupt_control.c | 16 +- .../src/txm_trace_isr_enter_insert.c | 16 +- .../src/txm_trace_isr_exit_insert.c | 16 +- .../src/txm_trace_user_event_insert.c | 16 +- .../inc/txm_module_manager_dispatch.h | 8 +- .../inc/txm_module_manager_util.h | 23 +- .../src/txm_module_manager_absolute_load.c | 13 +- .../txm_module_manager_application_request.c | 16 +- .../src/txm_module_manager_callback_request.c | 13 +- ...le_manager_event_flags_notify_trampoline.c | 13 +- .../src/txm_module_manager_file_load.c | 13 +- .../src/txm_module_manager_in_place_load.c | 13 +- .../src/txm_module_manager_initialize.c | 13 +- .../src/txm_module_manager_internal_load.c | 13 +- .../src/txm_module_manager_kernel_dispatch.c | 25 +- ...dule_manager_maximum_module_priority_set.c | 13 +- .../src/txm_module_manager_memory_load.c | 13 +- .../src/txm_module_manager_object_allocate.c | 13 +- .../txm_module_manager_object_deallocate.c | 13 +- .../txm_module_manager_object_pointer_get.c | 13 +- ...dule_manager_object_pointer_get_extended.c | 13 +- .../txm_module_manager_object_pool_create.c | 13 +- .../src/txm_module_manager_properties_get.c | 13 +- ...m_module_manager_queue_notify_trampoline.c | 13 +- ...dule_manager_semaphore_notify_trampoline.c | 13 +- .../src/txm_module_manager_start.c | 15 +- .../src/txm_module_manager_stop.c | 18 +- .../src/txm_module_manager_thread_create.c | 27 +- ..._module_manager_thread_notify_trampoline.c | 13 +- .../src/txm_module_manager_thread_reset.c | 13 +- ...m_module_manager_timer_notify_trampoline.c | 13 +- .../src/txm_module_manager_unload.c | 13 +- .../src/txm_module_manager_util.c | 43 +- .../utilities/module_binary_to_c_array.c | 6 +- .../utilities/module_to_binary.c | 18 +- .../utilities/module_to_c_array.c | 22 +- common_smp/inc/tx_api.h | 67 +- common_smp/inc/tx_block_pool.h | 15 +- common_smp/inc/tx_byte_pool.h | 15 +- common_smp/inc/tx_event_flags.h | 15 +- common_smp/inc/tx_initialize.h | 15 +- common_smp/inc/tx_mutex.h | 15 +- common_smp/inc/tx_queue.h | 15 +- common_smp/inc/tx_semaphore.h | 15 +- common_smp/inc/tx_thread.h | 15 +- common_smp/inc/tx_timer.h | 13 +- common_smp/inc/tx_trace.h | 15 +- common_smp/inc/tx_user_sample.h | 36 +- common_smp/src/tx_block_allocate.c | 15 +- common_smp/src/tx_block_pool_cleanup.c | 15 +- common_smp/src/tx_block_pool_create.c | 15 +- common_smp/src/tx_block_pool_delete.c | 15 +- common_smp/src/tx_block_pool_info_get.c | 15 +- common_smp/src/tx_block_pool_initialize.c | 18 +- .../src/tx_block_pool_performance_info_get.c | 15 +- ...x_block_pool_performance_system_info_get.c | 15 +- common_smp/src/tx_block_pool_prioritize.c | 15 +- common_smp/src/tx_block_release.c | 15 +- common_smp/src/tx_byte_allocate.c | 15 +- common_smp/src/tx_byte_pool_cleanup.c | 15 +- common_smp/src/tx_byte_pool_create.c | 15 +- common_smp/src/tx_byte_pool_delete.c | 15 +- common_smp/src/tx_byte_pool_info_get.c | 15 +- common_smp/src/tx_byte_pool_initialize.c | 18 +- .../src/tx_byte_pool_performance_info_get.c | 15 +- ...tx_byte_pool_performance_system_info_get.c | 15 +- common_smp/src/tx_byte_pool_prioritize.c | 15 +- common_smp/src/tx_byte_pool_search.c | 19 +- common_smp/src/tx_byte_release.c | 15 +- common_smp/src/tx_event_flags_cleanup.c | 15 +- common_smp/src/tx_event_flags_create.c | 15 +- common_smp/src/tx_event_flags_delete.c | 15 +- common_smp/src/tx_event_flags_get.c | 21 +- common_smp/src/tx_event_flags_info_get.c | 15 +- common_smp/src/tx_event_flags_initialize.c | 18 +- .../src/tx_event_flags_performance_info_get.c | 15 +- ..._event_flags_performance_system_info_get.c | 15 +- common_smp/src/tx_event_flags_set.c | 23 +- common_smp/src/tx_event_flags_set_notify.c | 15 +- common_smp/src/tx_initialize_high_level.c | 15 +- common_smp/src/tx_initialize_kernel_enter.c | 17 +- common_smp/src/tx_initialize_kernel_setup.c | 13 +- common_smp/src/tx_misra.c | 9 +- common_smp/src/tx_mutex_cleanup.c | 15 +- common_smp/src/tx_mutex_create.c | 15 +- common_smp/src/tx_mutex_delete.c | 15 +- common_smp/src/tx_mutex_get.c | 15 +- common_smp/src/tx_mutex_info_get.c | 15 +- common_smp/src/tx_mutex_initialize.c | 18 +- .../src/tx_mutex_performance_info_get.c | 15 +- .../tx_mutex_performance_system_info_get.c | 15 +- common_smp/src/tx_mutex_prioritize.c | 15 +- common_smp/src/tx_mutex_priority_change.c | 13 +- common_smp/src/tx_mutex_put.c | 15 +- common_smp/src/tx_queue_cleanup.c | 15 +- common_smp/src/tx_queue_create.c | 15 +- common_smp/src/tx_queue_delete.c | 15 +- common_smp/src/tx_queue_flush.c | 15 +- common_smp/src/tx_queue_front_send.c | 15 +- common_smp/src/tx_queue_info_get.c | 15 +- common_smp/src/tx_queue_initialize.c | 18 +- .../src/tx_queue_performance_info_get.c | 15 +- .../tx_queue_performance_system_info_get.c | 15 +- common_smp/src/tx_queue_prioritize.c | 15 +- common_smp/src/tx_queue_receive.c | 15 +- common_smp/src/tx_queue_send.c | 15 +- common_smp/src/tx_queue_send_notify.c | 15 +- common_smp/src/tx_semaphore_ceiling_put.c | 15 +- common_smp/src/tx_semaphore_cleanup.c | 15 +- common_smp/src/tx_semaphore_create.c | 15 +- common_smp/src/tx_semaphore_delete.c | 15 +- common_smp/src/tx_semaphore_get.c | 15 +- common_smp/src/tx_semaphore_info_get.c | 15 +- common_smp/src/tx_semaphore_initialize.c | 18 +- .../src/tx_semaphore_performance_info_get.c | 15 +- ...tx_semaphore_performance_system_info_get.c | 15 +- common_smp/src/tx_semaphore_prioritize.c | 15 +- common_smp/src/tx_semaphore_put.c | 15 +- common_smp/src/tx_semaphore_put_notify.c | 15 +- common_smp/src/tx_thread_create.c | 25 +- common_smp/src/tx_thread_delete.c | 15 +- common_smp/src/tx_thread_entry_exit_notify.c | 15 +- common_smp/src/tx_thread_identify.c | 15 +- common_smp/src/tx_thread_info_get.c | 15 +- common_smp/src/tx_thread_initialize.c | 13 +- .../src/tx_thread_performance_info_get.c | 15 +- .../tx_thread_performance_system_info_get.c | 15 +- common_smp/src/tx_thread_preemption_change.c | 13 +- common_smp/src/tx_thread_priority_change.c | 13 +- common_smp/src/tx_thread_relinquish.c | 13 +- common_smp/src/tx_thread_reset.c | 15 +- common_smp/src/tx_thread_resume.c | 13 +- common_smp/src/tx_thread_shell_entry.c | 15 +- common_smp/src/tx_thread_sleep.c | 15 +- common_smp/src/tx_thread_smp_core_exclude.c | 13 +- .../src/tx_thread_smp_core_exclude_get.c | 13 +- .../src/tx_thread_smp_current_state_set.c | 13 +- .../src/tx_thread_smp_debug_entry_insert.c | 13 +- .../src/tx_thread_smp_high_level_initialize.c | 17 +- .../tx_thread_smp_rebalance_execute_list.c | 13 +- common_smp/src/tx_thread_smp_utilities.c | 7 +- common_smp/src/tx_thread_stack_analyze.c | 15 +- .../src/tx_thread_stack_error_handler.c | 16 +- common_smp/src/tx_thread_stack_error_notify.c | 13 +- common_smp/src/tx_thread_suspend.c | 13 +- .../src/tx_thread_system_preempt_check.c | 13 +- common_smp/src/tx_thread_system_resume.c | 13 +- common_smp/src/tx_thread_system_suspend.c | 18 +- common_smp/src/tx_thread_terminate.c | 15 +- common_smp/src/tx_thread_time_slice.c | 13 +- common_smp/src/tx_thread_time_slice_change.c | 13 +- common_smp/src/tx_thread_timeout.c | 15 +- common_smp/src/tx_thread_wait_abort.c | 18 +- common_smp/src/tx_time_get.c | 17 +- common_smp/src/tx_time_set.c | 15 +- common_smp/src/tx_timer_activate.c | 15 +- common_smp/src/tx_timer_change.c | 15 +- common_smp/src/tx_timer_create.c | 13 +- common_smp/src/tx_timer_deactivate.c | 15 +- common_smp/src/tx_timer_delete.c | 15 +- common_smp/src/tx_timer_expiration_process.c | 13 +- common_smp/src/tx_timer_info_get.c | 15 +- common_smp/src/tx_timer_initialize.c | 13 +- .../src/tx_timer_performance_info_get.c | 15 +- .../tx_timer_performance_system_info_get.c | 15 +- common_smp/src/tx_timer_smp_core_exclude.c | 13 +- .../src/tx_timer_smp_core_exclude_get.c | 13 +- common_smp/src/tx_timer_system_activate.c | 13 +- common_smp/src/tx_timer_system_deactivate.c | 15 +- common_smp/src/tx_timer_thread_entry.c | 13 +- common_smp/src/tx_trace_buffer_full_notify.c | 15 +- common_smp/src/tx_trace_disable.c | 15 +- common_smp/src/tx_trace_enable.c | 15 +- common_smp/src/tx_trace_event_filter.c | 15 +- common_smp/src/tx_trace_event_unfilter.c | 15 +- common_smp/src/tx_trace_initialize.c | 15 +- common_smp/src/tx_trace_interrupt_control.c | 15 +- common_smp/src/tx_trace_isr_enter_insert.c | 15 +- common_smp/src/tx_trace_isr_exit_insert.c | 15 +- common_smp/src/tx_trace_object_register.c | 18 +- common_smp/src/tx_trace_object_unregister.c | 15 +- common_smp/src/tx_trace_user_event_insert.c | 15 +- common_smp/src/txe_block_allocate.c | 15 +- common_smp/src/txe_block_pool_create.c | 15 +- common_smp/src/txe_block_pool_delete.c | 15 +- common_smp/src/txe_block_pool_info_get.c | 15 +- common_smp/src/txe_block_pool_prioritize.c | 15 +- common_smp/src/txe_block_release.c | 15 +- common_smp/src/txe_byte_allocate.c | 15 +- common_smp/src/txe_byte_pool_create.c | 15 +- common_smp/src/txe_byte_pool_delete.c | 15 +- common_smp/src/txe_byte_pool_info_get.c | 15 +- common_smp/src/txe_byte_pool_prioritize.c | 15 +- common_smp/src/txe_byte_release.c | 15 +- common_smp/src/txe_event_flags_create.c | 15 +- common_smp/src/txe_event_flags_delete.c | 15 +- common_smp/src/txe_event_flags_get.c | 15 +- common_smp/src/txe_event_flags_info_get.c | 15 +- common_smp/src/txe_event_flags_set.c | 15 +- common_smp/src/txe_event_flags_set_notify.c | 15 +- common_smp/src/txe_mutex_create.c | 15 +- common_smp/src/txe_mutex_delete.c | 15 +- common_smp/src/txe_mutex_get.c | 15 +- common_smp/src/txe_mutex_info_get.c | 15 +- common_smp/src/txe_mutex_prioritize.c | 15 +- common_smp/src/txe_mutex_put.c | 15 +- common_smp/src/txe_queue_create.c | 15 +- common_smp/src/txe_queue_delete.c | 15 +- common_smp/src/txe_queue_flush.c | 15 +- common_smp/src/txe_queue_front_send.c | 15 +- common_smp/src/txe_queue_info_get.c | 15 +- common_smp/src/txe_queue_prioritize.c | 15 +- common_smp/src/txe_queue_receive.c | 15 +- common_smp/src/txe_queue_send.c | 15 +- common_smp/src/txe_queue_send_notify.c | 15 +- common_smp/src/txe_semaphore_ceiling_put.c | 15 +- common_smp/src/txe_semaphore_create.c | 15 +- common_smp/src/txe_semaphore_delete.c | 15 +- common_smp/src/txe_semaphore_get.c | 15 +- common_smp/src/txe_semaphore_info_get.c | 15 +- common_smp/src/txe_semaphore_prioritize.c | 15 +- common_smp/src/txe_semaphore_put.c | 15 +- common_smp/src/txe_semaphore_put_notify.c | 15 +- common_smp/src/txe_thread_create.c | 15 +- common_smp/src/txe_thread_delete.c | 15 +- common_smp/src/txe_thread_entry_exit_notify.c | 15 +- common_smp/src/txe_thread_info_get.c | 15 +- common_smp/src/txe_thread_preemption_change.c | 15 +- common_smp/src/txe_thread_priority_change.c | 15 +- common_smp/src/txe_thread_relinquish.c | 15 +- common_smp/src/txe_thread_reset.c | 15 +- common_smp/src/txe_thread_resume.c | 15 +- common_smp/src/txe_thread_suspend.c | 15 +- common_smp/src/txe_thread_terminate.c | 15 +- common_smp/src/txe_thread_time_slice_change.c | 15 +- common_smp/src/txe_thread_wait_abort.c | 15 +- common_smp/src/txe_timer_activate.c | 15 +- common_smp/src/txe_timer_change.c | 15 +- common_smp/src/txe_timer_create.c | 15 +- common_smp/src/txe_timer_deactivate.c | 15 +- common_smp/src/txe_timer_delete.c | 15 +- common_smp/src/txe_timer_info_get.c | 15 +- .../sample_threadx/sample_threadx.c | 44 +- .../sample_threadx/sample_threadx.cmd | 16 +- .../sample_threadx/tx_initialize_low_level.s | 20 +- .../example_build/sample_threadx/vectors.s | 2 +- ports/arc_em/metaware/inc/tx_port.h | 79 +- ports/arc_em/metaware/readme_threadx.txt | 102 +- .../metaware/src/tx_thread_context_restore.s | 22 +- .../metaware/src/tx_thread_context_save.s | 18 +- .../src/tx_thread_interrupt_control.s | 17 +- .../arc_em/metaware/src/tx_thread_schedule.s | 23 +- .../metaware/src/tx_thread_stack_build.s | 17 +- .../metaware/src/tx_thread_system_return.s | 20 +- .../arc_em/metaware/src/tx_timer_interrupt.s | 23 +- .../sample_threadx/sample_threadx.c | 42 +- .../sample_threadx/sample_threadx.cmd | 16 +- .../sample_threadx/tx_initialize_low_level.s | 20 +- .../example_build/sample_threadx/vectors.s | 2 +- ports/arc_hs/metaware/inc/tx_port.h | 79 +- ports/arc_hs/metaware/readme_threadx.txt | 108 +- .../src/tx_initialize_fast_interrupt_setup.s | 67 +- .../src/tx_thread_context_fast_restore.s | 79 +- .../src/tx_thread_context_fast_save.s | 77 +- .../metaware/src/tx_thread_context_restore.s | 21 +- .../metaware/src/tx_thread_context_save.s | 18 +- .../src/tx_thread_interrupt_control.s | 17 +- .../src/tx_thread_register_bank_assign.s | 67 +- .../arc_hs/metaware/src/tx_thread_schedule.s | 30 +- .../metaware/src/tx_thread_stack_build.s | 17 +- .../metaware/src/tx_thread_system_return.s | 22 +- .../arc_hs/metaware/src/tx_timer_interrupt.s | 23 +- .../arm11/ac5/example_build/sample_threadx.c | 46 +- .../example_build/tx_initialize_low_level.s | 122 +- ports/arm11/ac5/inc/tx_port.h | 100 +- ports/arm11/ac5/readme_threadx.txt | 320 +++--- .../arm11/ac5/src/tx_thread_context_restore.s | 72 +- ports/arm11/ac5/src/tx_thread_context_save.s | 80 +- .../ac5/src/tx_thread_fiq_context_restore.s | 76 +- .../ac5/src/tx_thread_fiq_context_save.s | 102 +- .../arm11/ac5/src/tx_thread_fiq_nesting_end.s | 84 +- .../ac5/src/tx_thread_fiq_nesting_start.s | 74 +- .../ac5/src/tx_thread_interrupt_control.s | 62 +- .../ac5/src/tx_thread_interrupt_disable.s | 60 +- .../ac5/src/tx_thread_interrupt_restore.s | 58 +- .../arm11/ac5/src/tx_thread_irq_nesting_end.s | 84 +- .../ac5/src/tx_thread_irq_nesting_start.s | 74 +- ports/arm11/ac5/src/tx_thread_schedule.s | 74 +- ports/arm11/ac5/src/tx_thread_stack_build.s | 62 +- ports/arm11/ac5/src/tx_thread_system_return.s | 72 +- .../ac5/src/tx_thread_vectored_context_save.s | 68 +- ports/arm11/ac5/src/tx_timer_interrupt.s | 76 +- ports/arm11/gnu/example_build/crt0.S | 20 +- ports/arm11/gnu/example_build/reset.S | 16 +- .../arm11/gnu/example_build/sample_threadx.c | 46 +- .../arm11/gnu/example_build/sample_threadx.ld | 14 +- .../example_build/tx_initialize_low_level.S | 114 +- ports/arm11/gnu/inc/tx_port.h | 96 +- ports/arm11/gnu/readme_threadx.txt | 312 ++--- .../arm11/gnu/src/tx_thread_context_restore.S | 75 +- ports/arm11/gnu/src/tx_thread_context_save.S | 85 +- .../gnu/src/tx_thread_fiq_context_restore.S | 77 +- .../gnu/src/tx_thread_fiq_context_save.S | 105 +- .../arm11/gnu/src/tx_thread_fiq_nesting_end.S | 87 +- .../gnu/src/tx_thread_fiq_nesting_start.S | 77 +- .../gnu/src/tx_thread_interrupt_control.S | 67 +- .../gnu/src/tx_thread_interrupt_disable.S | 65 +- .../gnu/src/tx_thread_interrupt_restore.S | 63 +- .../arm11/gnu/src/tx_thread_irq_nesting_end.S | 87 +- .../gnu/src/tx_thread_irq_nesting_start.S | 77 +- ports/arm11/gnu/src/tx_thread_schedule.S | 79 +- ports/arm11/gnu/src/tx_thread_stack_build.S | 67 +- ports/arm11/gnu/src/tx_thread_system_return.S | 75 +- .../gnu/src/tx_thread_vectored_context_save.S | 73 +- ports/arm11/gnu/src/tx_timer_interrupt.S | 79 +- ports/arm11/iar/example_build/cstartup.s | 10 +- .../arm11/iar/example_build/sample_threadx.c | 46 +- .../example_build/tx_initialize_low_level.s | 128 +-- ports/arm11/iar/inc/tx_port.h | 124 +- ports/arm11/iar/readme_threadx.txt | 322 +++--- ports/arm11/iar/src/tx_iar.c | 239 ++-- .../arm11/iar/src/tx_thread_context_restore.s | 90 +- ports/arm11/iar/src/tx_thread_context_save.s | 98 +- .../iar/src/tx_thread_fiq_context_restore.s | 94 +- .../iar/src/tx_thread_fiq_context_save.s | 120 +- .../arm11/iar/src/tx_thread_fiq_nesting_end.s | 100 +- .../iar/src/tx_thread_fiq_nesting_start.s | 92 +- .../iar/src/tx_thread_interrupt_control.s | 80 +- .../iar/src/tx_thread_interrupt_disable.s | 78 +- .../iar/src/tx_thread_interrupt_restore.s | 76 +- .../arm11/iar/src/tx_thread_irq_nesting_end.s | 100 +- .../iar/src/tx_thread_irq_nesting_start.s | 92 +- ports/arm11/iar/src/tx_thread_schedule.s | 88 +- ports/arm11/iar/src/tx_thread_stack_build.s | 76 +- ports/arm11/iar/src/tx_thread_system_return.s | 86 +- .../iar/src/tx_thread_vectored_context_save.s | 86 +- ports/arm11/iar/src/tx_timer_interrupt.s | 94 +- ports/arm9/ac5/example_build/sample_threadx.c | 46 +- .../example_build/tx_initialize_low_level.s | 122 +- ports/arm9/ac5/inc/tx_port.h | 100 +- ports/arm9/ac5/readme_threadx.txt | 322 +++--- .../arm9/ac5/src/tx_thread_context_restore.s | 72 +- ports/arm9/ac5/src/tx_thread_context_save.s | 80 +- .../ac5/src/tx_thread_fiq_context_restore.s | 76 +- .../arm9/ac5/src/tx_thread_fiq_context_save.s | 102 +- .../arm9/ac5/src/tx_thread_fiq_nesting_end.s | 84 +- .../ac5/src/tx_thread_fiq_nesting_start.s | 74 +- .../ac5/src/tx_thread_interrupt_control.s | 62 +- .../ac5/src/tx_thread_interrupt_disable.s | 60 +- .../ac5/src/tx_thread_interrupt_restore.s | 58 +- .../arm9/ac5/src/tx_thread_irq_nesting_end.s | 84 +- .../ac5/src/tx_thread_irq_nesting_start.s | 74 +- ports/arm9/ac5/src/tx_thread_schedule.s | 74 +- ports/arm9/ac5/src/tx_thread_stack_build.s | 62 +- ports/arm9/ac5/src/tx_thread_system_return.s | 70 +- .../ac5/src/tx_thread_vectored_context_save.s | 68 +- ports/arm9/ac5/src/tx_timer_interrupt.s | 76 +- ports/arm9/gnu/example_build/crt0.S | 20 +- ports/arm9/gnu/example_build/reset.S | 16 +- ports/arm9/gnu/example_build/sample_threadx.c | 46 +- .../arm9/gnu/example_build/sample_threadx.ld | 14 +- .../example_build/tx_initialize_low_level.S | 114 +- ports/arm9/gnu/inc/tx_port.h | 96 +- ports/arm9/gnu/readme_threadx.txt | 312 ++--- .../arm9/gnu/src/tx_thread_context_restore.S | 75 +- ports/arm9/gnu/src/tx_thread_context_save.S | 85 +- .../gnu/src/tx_thread_fiq_context_restore.S | 77 +- .../arm9/gnu/src/tx_thread_fiq_context_save.S | 105 +- .../arm9/gnu/src/tx_thread_fiq_nesting_end.S | 87 +- .../gnu/src/tx_thread_fiq_nesting_start.S | 77 +- .../gnu/src/tx_thread_interrupt_control.S | 67 +- .../gnu/src/tx_thread_interrupt_disable.S | 65 +- .../gnu/src/tx_thread_interrupt_restore.S | 63 +- .../arm9/gnu/src/tx_thread_irq_nesting_end.S | 87 +- .../gnu/src/tx_thread_irq_nesting_start.S | 77 +- ports/arm9/gnu/src/tx_thread_schedule.S | 79 +- ports/arm9/gnu/src/tx_thread_stack_build.S | 67 +- ports/arm9/gnu/src/tx_thread_system_return.S | 75 +- .../gnu/src/tx_thread_vectored_context_save.S | 73 +- ports/arm9/gnu/src/tx_timer_interrupt.S | 79 +- ports/arm9/iar/example_build/cstartup.s | 10 +- ports/arm9/iar/example_build/sample_threadx.c | 46 +- .../example_build/tx_initialize_low_level.s | 110 +- ports/arm9/iar/inc/tx_port.h | 106 +- ports/arm9/iar/readme_threadx.txt | 320 +++--- ports/arm9/iar/src/tx_iar.c | 239 ++-- .../arm9/iar/src/tx_thread_context_restore.s | 72 +- ports/arm9/iar/src/tx_thread_context_save.s | 80 +- .../iar/src/tx_thread_fiq_context_restore.s | 76 +- .../arm9/iar/src/tx_thread_fiq_context_save.s | 102 +- .../arm9/iar/src/tx_thread_fiq_nesting_end.s | 82 +- .../iar/src/tx_thread_fiq_nesting_start.s | 74 +- .../iar/src/tx_thread_interrupt_control.s | 62 +- .../iar/src/tx_thread_interrupt_disable.s | 60 +- .../iar/src/tx_thread_interrupt_restore.s | 58 +- .../arm9/iar/src/tx_thread_irq_nesting_end.s | 82 +- .../iar/src/tx_thread_irq_nesting_start.s | 74 +- ports/arm9/iar/src/tx_thread_schedule.s | 74 +- ports/arm9/iar/src/tx_thread_stack_build.s | 64 +- ports/arm9/iar/src/tx_thread_system_return.s | 68 +- .../iar/src/tx_thread_vectored_context_save.s | 68 +- ports/arm9/iar/src/tx_timer_interrupt.s | 76 +- ports/c667x/ccs/example_build/include/C66XX.h | 2 +- .../ccs/example_build/include/C66XX_DEF.hxx | 46 +- .../example_build/include/C66XX_FUNCTIONS.hxx | 6 +- .../example_build/include/C66XX_MACROS.hxx | 2 +- .../ccs/example_build/include/TA66XX_DSP.h | 2 +- .../ccs/example_build/include/TA66XX_DSP_BC.h | 2 +- .../include/TA66XX_DSP_BC_FUNCTIONS.hxx | 12 +- .../ccs/example_build/include/TA66XX_OSAL.h | 2 +- .../sample_threadx_c6678evm/sample_threadx.c | 32 +- .../sample_threadx.cmd | 10 +- .../targetConfigs/TMS320C6678.ccxml | 2 +- .../tx_initialize_low_level.asm | 76 +- .../sample_threadx_ta6678fmc/sample_threadx.c | 32 +- .../sample_threadx.cmd | 8 +- .../targetConfigs/TMS320C6678.ccxml | 2 +- .../tx_initialize_low_level.asm | 76 +- .../ccs/example_build/tx/Release/ccsObjs.opt | 2 +- .../ccs/example_build/tx/Release/makefile | 30 +- .../ccs/example_build/tx/Release/sources.mk | 202 ++-- .../example_build/tx/Release/subdir_vars.mk | 22 +- ports/c667x/ccs/inc/tx_port.h | 90 +- ports/c667x/ccs/readme_threadx.txt | 110 +- .../ccs/src/tx_thread_context_restore.asm | 82 +- .../c667x/ccs/src/tx_thread_context_save.asm | 72 +- .../ccs/src/tx_thread_interrupt_control.asm | 64 +- ports/c667x/ccs/src/tx_thread_schedule.asm | 74 +- ports/c667x/ccs/src/tx_thread_stack_build.asm | 62 +- .../c667x/ccs/src/tx_thread_system_return.asm | 80 +- ports/c667x/ccs/src/tx_timer_interrupt.asm | 110 +- .../example_build/sample_threadx/.cproject | 174 +-- .../sample_threadx/sample_threadx.scat | 2 +- .../sample_threadx/tx_initialize_low_level.S | 15 +- .../cortex_a12/ac6/example_build/tx/.cproject | 144 +-- ports/cortex_a12/ac6/inc/tx_port.h | 23 +- .../ac6/src/tx_thread_context_restore.S | 24 +- .../ac6/src/tx_thread_context_save.S | 24 +- .../ac6/src/tx_thread_fiq_context_restore.S | 21 +- .../ac6/src/tx_thread_fiq_context_save.S | 21 +- .../ac6/src/tx_thread_fiq_nesting_end.S | 21 +- .../ac6/src/tx_thread_fiq_nesting_start.S | 21 +- .../ac6/src/tx_thread_interrupt_control.S | 21 +- .../ac6/src/tx_thread_interrupt_disable.S | 21 +- .../ac6/src/tx_thread_interrupt_restore.S | 21 +- .../ac6/src/tx_thread_irq_nesting_end.S | 21 +- .../ac6/src/tx_thread_irq_nesting_start.S | 21 +- ports/cortex_a12/ac6/src/tx_thread_schedule.S | 25 +- .../ac6/src/tx_thread_stack_build.S | 21 +- .../ac6/src/tx_thread_system_return.S | 24 +- .../ac6/src/tx_thread_vectored_context_save.S | 21 +- ports/cortex_a12/ac6/src/tx_timer_interrupt.S | 21 +- ports/cortex_a12/gnu/example_build/reset.S | 7 +- .../gnu/example_build/sample_threadx.ld | 14 +- .../example_build/tx_initialize_low_level.S | 18 +- ports/cortex_a12/gnu/example_build/v7.h | 2 +- ports/cortex_a12/gnu/example_build/v7.s | 48 +- ports/cortex_a12/gnu/inc/tx_port.h | 23 +- .../gnu/src/tx_thread_context_restore.S | 24 +- .../gnu/src/tx_thread_context_save.S | 24 +- .../gnu/src/tx_thread_fiq_context_restore.S | 21 +- .../gnu/src/tx_thread_fiq_context_save.S | 21 +- .../gnu/src/tx_thread_fiq_nesting_end.S | 21 +- .../gnu/src/tx_thread_fiq_nesting_start.S | 21 +- .../gnu/src/tx_thread_interrupt_control.S | 21 +- .../gnu/src/tx_thread_interrupt_disable.S | 21 +- .../gnu/src/tx_thread_interrupt_restore.S | 21 +- .../gnu/src/tx_thread_irq_nesting_end.S | 21 +- .../gnu/src/tx_thread_irq_nesting_start.S | 21 +- ports/cortex_a12/gnu/src/tx_thread_schedule.S | 25 +- .../gnu/src/tx_thread_stack_build.S | 21 +- .../gnu/src/tx_thread_system_return.S | 24 +- .../gnu/src/tx_thread_vectored_context_save.S | 21 +- ports/cortex_a12/gnu/src/tx_timer_interrupt.S | 21 +- .../example_build/sample_threadx/.cproject | 174 +-- .../sample_threadx/sample_threadx.scat | 2 +- .../sample_threadx/tx_initialize_low_level.S | 15 +- .../cortex_a15/ac6/example_build/tx/.cproject | 144 +-- ports/cortex_a15/ac6/inc/tx_port.h | 23 +- ports/cortex_a15/ac6/readme_threadx.txt | 146 +-- .../ac6/src/tx_thread_context_restore.S | 24 +- .../ac6/src/tx_thread_context_save.S | 24 +- .../ac6/src/tx_thread_fiq_context_restore.S | 21 +- .../ac6/src/tx_thread_fiq_context_save.S | 21 +- .../ac6/src/tx_thread_fiq_nesting_end.S | 21 +- .../ac6/src/tx_thread_fiq_nesting_start.S | 21 +- .../ac6/src/tx_thread_interrupt_control.S | 21 +- .../ac6/src/tx_thread_interrupt_disable.S | 21 +- .../ac6/src/tx_thread_interrupt_restore.S | 21 +- .../ac6/src/tx_thread_irq_nesting_end.S | 21 +- .../ac6/src/tx_thread_irq_nesting_start.S | 21 +- ports/cortex_a15/ac6/src/tx_thread_schedule.S | 25 +- .../ac6/src/tx_thread_stack_build.S | 21 +- .../ac6/src/tx_thread_system_return.S | 24 +- .../ac6/src/tx_thread_vectored_context_save.S | 21 +- ports/cortex_a15/ac6/src/tx_timer_interrupt.S | 21 +- ports/cortex_a15/gnu/example_build/reset.S | 7 +- .../gnu/example_build/sample_threadx.ld | 14 +- .../example_build/tx_initialize_low_level.S | 18 +- ports/cortex_a15/gnu/example_build/v7.h | 2 +- ports/cortex_a15/gnu/example_build/v7.s | 48 +- ports/cortex_a15/gnu/inc/tx_port.h | 23 +- ports/cortex_a15/gnu/readme_threadx.txt | 314 ++--- .../gnu/src/tx_thread_context_restore.S | 24 +- .../gnu/src/tx_thread_context_save.S | 24 +- .../gnu/src/tx_thread_fiq_context_restore.S | 21 +- .../gnu/src/tx_thread_fiq_context_save.S | 21 +- .../gnu/src/tx_thread_fiq_nesting_end.S | 21 +- .../gnu/src/tx_thread_fiq_nesting_start.S | 21 +- .../gnu/src/tx_thread_interrupt_control.S | 21 +- .../gnu/src/tx_thread_interrupt_disable.S | 21 +- .../gnu/src/tx_thread_interrupt_restore.S | 21 +- .../gnu/src/tx_thread_irq_nesting_end.S | 21 +- .../gnu/src/tx_thread_irq_nesting_start.S | 21 +- ports/cortex_a15/gnu/src/tx_thread_schedule.S | 25 +- .../gnu/src/tx_thread_stack_build.S | 21 +- .../gnu/src/tx_thread_system_return.S | 24 +- .../gnu/src/tx_thread_vectored_context_save.S | 21 +- ports/cortex_a15/gnu/src/tx_timer_interrupt.S | 21 +- ports/cortex_a15/iar/example_build/cstartup.s | 10 +- .../iar/example_build/sample_threadx.c | 46 +- .../example_build/tx_initialize_low_level.s | 110 +- ports/cortex_a15/iar/inc/tx_port.h | 104 +- ports/cortex_a15/iar/readme_threadx.txt | 322 +++--- ports/cortex_a15/iar/src/tx_iar.c | 239 ++-- .../iar/src/tx_thread_context_restore.s | 73 +- .../iar/src/tx_thread_context_save.s | 83 +- .../iar/src/tx_thread_fiq_context_restore.s | 77 +- .../iar/src/tx_thread_fiq_context_save.s | 105 +- .../iar/src/tx_thread_fiq_nesting_end.s | 84 +- .../iar/src/tx_thread_fiq_nesting_start.s | 74 +- .../iar/src/tx_thread_interrupt_control.s | 62 +- .../iar/src/tx_thread_interrupt_disable.s | 62 +- .../iar/src/tx_thread_interrupt_restore.s | 58 +- .../iar/src/tx_thread_irq_nesting_end.s | 84 +- .../iar/src/tx_thread_irq_nesting_start.s | 74 +- ports/cortex_a15/iar/src/tx_thread_schedule.s | 79 +- .../iar/src/tx_thread_stack_build.s | 62 +- .../iar/src/tx_thread_system_return.s | 75 +- .../iar/src/tx_thread_vectored_context_save.s | 71 +- ports/cortex_a15/iar/src/tx_timer_interrupt.s | 74 +- .../example_build/sample_threadx/.cproject | 174 +-- .../sample_threadx/sample_threadx.scat | 2 +- .../sample_threadx/tx_initialize_low_level.S | 15 +- .../cortex_a17/ac6/example_build/tx/.cproject | 144 +-- ports/cortex_a17/ac6/inc/tx_port.h | 23 +- .../ac6/src/tx_thread_context_restore.S | 24 +- .../ac6/src/tx_thread_context_save.S | 24 +- .../ac6/src/tx_thread_fiq_context_restore.S | 21 +- .../ac6/src/tx_thread_fiq_context_save.S | 21 +- .../ac6/src/tx_thread_fiq_nesting_end.S | 21 +- .../ac6/src/tx_thread_fiq_nesting_start.S | 21 +- .../ac6/src/tx_thread_interrupt_control.S | 21 +- .../ac6/src/tx_thread_interrupt_disable.S | 21 +- .../ac6/src/tx_thread_interrupt_restore.S | 21 +- .../ac6/src/tx_thread_irq_nesting_end.S | 21 +- .../ac6/src/tx_thread_irq_nesting_start.S | 21 +- ports/cortex_a17/ac6/src/tx_thread_schedule.S | 25 +- .../ac6/src/tx_thread_stack_build.S | 21 +- .../ac6/src/tx_thread_system_return.S | 24 +- .../ac6/src/tx_thread_vectored_context_save.S | 21 +- ports/cortex_a17/ac6/src/tx_timer_interrupt.S | 21 +- ports/cortex_a17/gnu/example_build/reset.S | 7 +- .../gnu/example_build/sample_threadx.ld | 14 +- .../example_build/tx_initialize_low_level.S | 18 +- ports/cortex_a17/gnu/example_build/v7.h | 2 +- ports/cortex_a17/gnu/example_build/v7.s | 48 +- ports/cortex_a17/gnu/inc/tx_port.h | 23 +- .../gnu/src/tx_thread_context_restore.S | 24 +- .../gnu/src/tx_thread_context_save.S | 24 +- .../gnu/src/tx_thread_fiq_context_restore.S | 21 +- .../gnu/src/tx_thread_fiq_context_save.S | 21 +- .../gnu/src/tx_thread_fiq_nesting_end.S | 21 +- .../gnu/src/tx_thread_fiq_nesting_start.S | 21 +- .../gnu/src/tx_thread_interrupt_control.S | 21 +- .../gnu/src/tx_thread_interrupt_disable.S | 21 +- .../gnu/src/tx_thread_interrupt_restore.S | 21 +- .../gnu/src/tx_thread_irq_nesting_end.S | 21 +- .../gnu/src/tx_thread_irq_nesting_start.S | 21 +- ports/cortex_a17/gnu/src/tx_thread_schedule.S | 25 +- .../gnu/src/tx_thread_stack_build.S | 21 +- .../gnu/src/tx_thread_system_return.S | 24 +- .../gnu/src/tx_thread_vectored_context_save.S | 21 +- ports/cortex_a17/gnu/src/tx_timer_interrupt.S | 21 +- .../example_build/sample_threadx/.cproject | 156 +-- .../ac6/example_build/sample_threadx/GICv3.h | 2 +- .../example_build/sample_threadx/GICv3_gicc.h | 2 +- .../example_build/sample_threadx/GICv3_gicd.c | 2 +- .../example_build/sample_threadx/GICv3_gicr.c | 2 +- .../example_build/sample_threadx/MP_Mutexes.S | 4 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../example_build/sample_threadx/PPM_AEM.h | 2 +- .../sample_threadx/sample_threadx.scat | 4 +- .../sample_threadx/sp804_timer.c | 2 +- .../sample_threadx/sp804_timer.h | 2 +- .../example_build/sample_threadx/startup.S | 4 +- .../example_build/sample_threadx/v8_aarch64.S | 2 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../ac6/example_build/sample_threadx/v8_mmu.h | 4 +- .../example_build/sample_threadx/v8_system.h | 2 +- .../example_build/sample_threadx/v8_utils.S | 2 +- .../example_build/sample_threadx/vectors.S | 2 +- .../cortex_a34/ac6/example_build/tx/.cproject | 146 +-- ports/cortex_a34/ac6/inc/tx_port.h | 18 +- .../ac6/src/tx_initialize_low_level.S | 13 +- .../ac6/src/tx_thread_context_restore.S | 13 +- .../ac6/src/tx_thread_context_save.S | 13 +- .../cortex_a34/ac6/src/tx_thread_fp_disable.c | 15 +- .../cortex_a34/ac6/src/tx_thread_fp_enable.c | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 15 +- .../ac6/src/tx_thread_interrupt_disable.S | 15 +- .../ac6/src/tx_thread_interrupt_restore.S | 15 +- ports/cortex_a34/ac6/src/tx_thread_schedule.S | 17 +- .../ac6/src/tx_thread_stack_build.S | 15 +- .../ac6/src/tx_thread_system_return.S | 13 +- ports/cortex_a34/ac6/src/tx_timer_interrupt.S | 13 +- .../example_build/sample_threadx/.cproject | 240 ++-- .../gnu/example_build/sample_threadx/GICv3.h | 2 +- .../sample_threadx/GICv3_aliases.h | 2 +- .../example_build/sample_threadx/GICv3_gicc.h | 2 +- .../example_build/sample_threadx/GICv3_gicd.c | 2 +- .../example_build/sample_threadx/GICv3_gicr.c | 2 +- .../example_build/sample_threadx/MP_Mutexes.S | 4 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../example_build/sample_threadx/PPM_AEM.h | 2 +- .../sample_threadx/sample_threadx.ld | 2 +- .../sample_threadx/sp804_timer.c | 2 +- .../sample_threadx/sp804_timer.h | 2 +- .../example_build/sample_threadx/startup.S | 4 +- .../example_build/sample_threadx/v8_aarch64.S | 2 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../gnu/example_build/sample_threadx/v8_mmu.h | 4 +- .../example_build/sample_threadx/v8_system.h | 2 +- .../example_build/sample_threadx/v8_utils.S | 2 +- .../example_build/sample_threadx/vectors.S | 2 +- .../cortex_a34/gnu/example_build/tx/.cproject | 232 ++-- ports/cortex_a34/gnu/inc/tx_port.h | 18 +- .../gnu/src/tx_initialize_low_level.S | 22 +- .../gnu/src/tx_thread_context_restore.S | 16 +- .../gnu/src/tx_thread_context_save.S | 16 +- .../cortex_a34/gnu/src/tx_thread_fp_disable.c | 15 +- .../cortex_a34/gnu/src/tx_thread_fp_enable.c | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 18 +- .../gnu/src/tx_thread_interrupt_disable.S | 18 +- .../gnu/src/tx_thread_interrupt_restore.S | 18 +- ports/cortex_a34/gnu/src/tx_thread_schedule.S | 20 +- .../gnu/src/tx_thread_stack_build.S | 18 +- .../gnu/src/tx_thread_system_return.S | 16 +- ports/cortex_a34/gnu/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 156 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.scat | 4 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../ac6/example_build/sample_threadx/v8_mmu.h | 2 +- .../cortex_a35/ac6/example_build/tx/.cproject | 146 +-- ports/cortex_a35/ac6/inc/tx_port.h | 18 +- ports/cortex_a35/ac6/readme_threadx.txt | 94 +- .../ac6/src/tx_initialize_low_level.S | 18 +- .../ac6/src/tx_thread_context_restore.S | 16 +- .../ac6/src/tx_thread_context_save.S | 16 +- .../cortex_a35/ac6/src/tx_thread_fp_disable.c | 15 +- .../cortex_a35/ac6/src/tx_thread_fp_enable.c | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 18 +- .../ac6/src/tx_thread_interrupt_disable.S | 18 +- .../ac6/src/tx_thread_interrupt_restore.S | 18 +- ports/cortex_a35/ac6/src/tx_thread_schedule.S | 20 +- .../ac6/src/tx_thread_stack_build.S | 18 +- .../ac6/src/tx_thread_system_return.S | 16 +- ports/cortex_a35/ac6/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 168 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.ld | 2 +- .../example_build/sample_threadx/startup.S | 2 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../gnu/example_build/sample_threadx/v8_mmu.h | 2 +- .../cortex_a35/gnu/example_build/tx/.cproject | 160 +-- ports/cortex_a35/gnu/inc/tx_port.h | 18 +- ports/cortex_a35/gnu/readme_threadx.txt | 94 +- .../gnu/src/tx_initialize_low_level.S | 20 +- .../gnu/src/tx_thread_context_restore.S | 16 +- .../gnu/src/tx_thread_context_save.S | 16 +- .../cortex_a35/gnu/src/tx_thread_fp_disable.c | 15 +- .../cortex_a35/gnu/src/tx_thread_fp_enable.c | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 18 +- .../gnu/src/tx_thread_interrupt_disable.S | 18 +- .../gnu/src/tx_thread_interrupt_restore.S | 18 +- ports/cortex_a35/gnu/src/tx_thread_schedule.S | 20 +- .../gnu/src/tx_thread_stack_build.S | 18 +- .../gnu/src/tx_thread_system_return.S | 16 +- ports/cortex_a35/gnu/src/tx_timer_interrupt.S | 16 +- .../ac5/example_build/sample_threadx.c | 46 +- .../example_build/tx_initialize_low_level.s | 112 +- ports/cortex_a5/ac5/inc/tx_port.h | 98 +- ports/cortex_a5/ac5/readme_threadx.txt | 334 +++--- .../ac5/src/tx_thread_context_restore.s | 70 +- .../ac5/src/tx_thread_context_save.s | 80 +- .../ac5/src/tx_thread_fiq_context_restore.s | 78 +- .../ac5/src/tx_thread_fiq_context_save.s | 102 +- .../ac5/src/tx_thread_fiq_nesting_end.s | 84 +- .../ac5/src/tx_thread_fiq_nesting_start.s | 74 +- .../ac5/src/tx_thread_interrupt_control.s | 62 +- .../ac5/src/tx_thread_interrupt_disable.s | 62 +- .../ac5/src/tx_thread_interrupt_restore.s | 58 +- .../ac5/src/tx_thread_irq_nesting_end.s | 84 +- .../ac5/src/tx_thread_irq_nesting_start.s | 74 +- ports/cortex_a5/ac5/src/tx_thread_schedule.s | 76 +- .../cortex_a5/ac5/src/tx_thread_stack_build.s | 62 +- .../ac5/src/tx_thread_system_return.s | 70 +- .../ac5/src/tx_thread_vectored_context_save.s | 68 +- ports/cortex_a5/ac5/src/tx_timer_interrupt.s | 76 +- .../example_build/sample_threadx/.cproject | 174 +-- .../sample_threadx/sample_threadx.scat | 2 +- .../sample_threadx/tx_initialize_low_level.S | 15 +- .../cortex_a5/ac6/example_build/tx/.cproject | 144 +-- ports/cortex_a5/ac6/inc/tx_port.h | 23 +- .../ac6/src/tx_thread_context_restore.S | 24 +- .../ac6/src/tx_thread_context_save.S | 24 +- .../ac6/src/tx_thread_fiq_context_restore.S | 21 +- .../ac6/src/tx_thread_fiq_context_save.S | 21 +- .../ac6/src/tx_thread_fiq_nesting_end.S | 21 +- .../ac6/src/tx_thread_fiq_nesting_start.S | 21 +- .../ac6/src/tx_thread_interrupt_control.S | 21 +- .../ac6/src/tx_thread_interrupt_disable.S | 21 +- .../ac6/src/tx_thread_interrupt_restore.S | 21 +- .../ac6/src/tx_thread_irq_nesting_end.S | 21 +- .../ac6/src/tx_thread_irq_nesting_start.S | 21 +- ports/cortex_a5/ac6/src/tx_thread_schedule.S | 25 +- .../cortex_a5/ac6/src/tx_thread_stack_build.S | 21 +- .../ac6/src/tx_thread_system_return.S | 24 +- .../ac6/src/tx_thread_vectored_context_save.S | 21 +- ports/cortex_a5/ac6/src/tx_timer_interrupt.S | 21 +- .../example_build/tx_initialize_low_level.arm | 6 +- ports/cortex_a5/ghs/inc/tx_el.h | 13 +- ports/cortex_a5/ghs/inc/tx_port.h | 18 +- ports/cortex_a5/ghs/readme_threadx.txt | 316 ++--- ports/cortex_a5/ghs/src/tx_el.c | 13 +- .../ghs/src/tx_thread_context_restore.arm | 6 +- .../ghs/src/tx_thread_context_save.arm | 6 +- .../ghs/src/tx_thread_fiq_context_restore.arm | 6 +- .../ghs/src/tx_thread_fiq_context_save.arm | 6 +- .../ghs/src/tx_thread_fiq_nesting_end.arm | 6 +- .../ghs/src/tx_thread_fiq_nesting_start.arm | 6 +- .../ghs/src/tx_thread_interrupt_control.arm | 6 +- .../ghs/src/tx_thread_interrupt_disable.arm | 6 +- .../ghs/src/tx_thread_interrupt_restore.arm | 6 +- .../ghs/src/tx_thread_irq_nesting_end.arm | 6 +- .../ghs/src/tx_thread_irq_nesting_start.arm | 6 +- .../cortex_a5/ghs/src/tx_thread_schedule.arm | 6 +- .../ghs/src/tx_thread_stack_build.arm | 6 +- .../ghs/src/tx_thread_system_return.arm | 6 +- .../src/tx_thread_vectored_context_save.arm | 6 +- .../cortex_a5/ghs/src/tx_timer_interrupt.arm | 6 +- ports/cortex_a5/gnu/example_build/MP_GIC.S | 2 +- ports/cortex_a5/gnu/example_build/MP_GIC.h | 2 +- .../gnu/example_build/MP_PrivateTimer.S | 2 +- ports/cortex_a5/gnu/example_build/reset.S | 7 +- .../gnu/example_build/sample_threadx.ld | 14 +- .../example_build/tx_initialize_low_level.S | 22 +- ports/cortex_a5/gnu/example_build/v7.h | 2 +- ports/cortex_a5/gnu/example_build/v7.s | 48 +- ports/cortex_a5/gnu/inc/tx_port.h | 23 +- ports/cortex_a5/gnu/readme_threadx.txt | 314 ++--- .../gnu/src/tx_thread_context_restore.S | 24 +- .../gnu/src/tx_thread_context_save.S | 24 +- .../gnu/src/tx_thread_fiq_context_restore.S | 21 +- .../gnu/src/tx_thread_fiq_context_save.S | 21 +- .../gnu/src/tx_thread_fiq_nesting_end.S | 21 +- .../gnu/src/tx_thread_fiq_nesting_start.S | 21 +- .../gnu/src/tx_thread_interrupt_control.S | 21 +- .../gnu/src/tx_thread_interrupt_disable.S | 21 +- .../gnu/src/tx_thread_interrupt_restore.S | 21 +- .../gnu/src/tx_thread_irq_nesting_end.S | 21 +- .../gnu/src/tx_thread_irq_nesting_start.S | 21 +- ports/cortex_a5/gnu/src/tx_thread_schedule.S | 25 +- .../cortex_a5/gnu/src/tx_thread_stack_build.S | 21 +- .../gnu/src/tx_thread_system_return.S | 24 +- .../gnu/src/tx_thread_vectored_context_save.S | 21 +- ports/cortex_a5/gnu/src/tx_timer_interrupt.S | 21 +- ports/cortex_a5/iar/example_build/cstartup.s | 10 +- .../iar/example_build/sample_threadx.c | 46 +- .../example_build/tx_initialize_low_level.s | 110 +- ports/cortex_a5/iar/inc/tx_port.h | 104 +- ports/cortex_a5/iar/readme_threadx.txt | 322 +++--- ports/cortex_a5/iar/src/tx_iar.c | 239 ++-- .../iar/src/tx_thread_context_restore.s | 79 +- .../iar/src/tx_thread_context_save.s | 83 +- .../iar/src/tx_thread_fiq_context_restore.s | 79 +- .../iar/src/tx_thread_fiq_context_save.s | 105 +- .../iar/src/tx_thread_fiq_nesting_end.s | 82 +- .../iar/src/tx_thread_fiq_nesting_start.s | 74 +- .../iar/src/tx_thread_interrupt_control.s | 62 +- .../iar/src/tx_thread_interrupt_disable.s | 60 +- .../iar/src/tx_thread_interrupt_restore.s | 58 +- .../iar/src/tx_thread_irq_nesting_end.s | 82 +- .../iar/src/tx_thread_irq_nesting_start.s | 74 +- ports/cortex_a5/iar/src/tx_thread_schedule.s | 83 +- .../cortex_a5/iar/src/tx_thread_stack_build.s | 64 +- .../iar/src/tx_thread_system_return.s | 71 +- .../iar/src/tx_thread_vectored_context_save.s | 71 +- ports/cortex_a5/iar/src/tx_timer_interrupt.s | 76 +- .../example_build/sample_threadx/.cproject | 156 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.scat | 4 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../ac6/example_build/sample_threadx/v8_mmu.h | 2 +- .../cortex_a53/ac6/example_build/tx/.cproject | 146 +-- ports/cortex_a53/ac6/inc/tx_port.h | 18 +- .../ac6/src/tx_initialize_low_level.S | 18 +- .../ac6/src/tx_thread_context_restore.S | 16 +- .../ac6/src/tx_thread_context_save.S | 16 +- .../cortex_a53/ac6/src/tx_thread_fp_disable.c | 15 +- .../cortex_a53/ac6/src/tx_thread_fp_enable.c | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 18 +- .../ac6/src/tx_thread_interrupt_disable.S | 18 +- .../ac6/src/tx_thread_interrupt_restore.S | 18 +- ports/cortex_a53/ac6/src/tx_thread_schedule.S | 20 +- .../ac6/src/tx_thread_stack_build.S | 18 +- .../ac6/src/tx_thread_system_return.S | 16 +- ports/cortex_a53/ac6/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 168 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.ld | 2 +- .../example_build/sample_threadx/startup.S | 2 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../gnu/example_build/sample_threadx/v8_mmu.h | 2 +- .../cortex_a53/gnu/example_build/tx/.cproject | 160 +-- ports/cortex_a53/gnu/inc/tx_port.h | 18 +- .../gnu/src/tx_initialize_low_level.S | 20 +- .../gnu/src/tx_thread_context_restore.S | 16 +- .../gnu/src/tx_thread_context_save.S | 16 +- .../cortex_a53/gnu/src/tx_thread_fp_disable.c | 15 +- .../cortex_a53/gnu/src/tx_thread_fp_enable.c | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 18 +- .../gnu/src/tx_thread_interrupt_disable.S | 18 +- .../gnu/src/tx_thread_interrupt_restore.S | 18 +- ports/cortex_a53/gnu/src/tx_thread_schedule.S | 20 +- .../gnu/src/tx_thread_stack_build.S | 18 +- .../gnu/src/tx_thread_system_return.S | 16 +- ports/cortex_a53/gnu/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 156 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.scat | 4 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../ac6/example_build/sample_threadx/v8_mmu.h | 2 +- .../cortex_a55/ac6/example_build/tx/.cproject | 146 +-- ports/cortex_a55/ac6/inc/tx_port.h | 18 +- .../ac6/src/tx_initialize_low_level.S | 18 +- .../ac6/src/tx_thread_context_restore.S | 16 +- .../ac6/src/tx_thread_context_save.S | 16 +- .../cortex_a55/ac6/src/tx_thread_fp_disable.c | 15 +- .../cortex_a55/ac6/src/tx_thread_fp_enable.c | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 18 +- .../ac6/src/tx_thread_interrupt_disable.S | 18 +- .../ac6/src/tx_thread_interrupt_restore.S | 18 +- ports/cortex_a55/ac6/src/tx_thread_schedule.S | 20 +- .../ac6/src/tx_thread_stack_build.S | 18 +- .../ac6/src/tx_thread_system_return.S | 16 +- ports/cortex_a55/ac6/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 168 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.ld | 2 +- .../example_build/sample_threadx/startup.S | 2 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../gnu/example_build/sample_threadx/v8_mmu.h | 2 +- .../cortex_a55/gnu/example_build/tx/.cproject | 160 +-- ports/cortex_a55/gnu/inc/tx_port.h | 18 +- .../gnu/src/tx_initialize_low_level.S | 20 +- .../gnu/src/tx_thread_context_restore.S | 16 +- .../gnu/src/tx_thread_context_save.S | 16 +- .../cortex_a55/gnu/src/tx_thread_fp_disable.c | 15 +- .../cortex_a55/gnu/src/tx_thread_fp_enable.c | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 18 +- .../gnu/src/tx_thread_interrupt_disable.S | 18 +- .../gnu/src/tx_thread_interrupt_restore.S | 18 +- ports/cortex_a55/gnu/src/tx_thread_schedule.S | 20 +- .../gnu/src/tx_thread_stack_build.S | 18 +- .../gnu/src/tx_thread_system_return.S | 16 +- ports/cortex_a55/gnu/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 156 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.scat | 4 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../ac6/example_build/sample_threadx/v8_mmu.h | 2 +- .../cortex_a57/ac6/example_build/tx/.cproject | 146 +-- ports/cortex_a57/ac6/inc/tx_port.h | 18 +- .../ac6/src/tx_initialize_low_level.S | 18 +- .../ac6/src/tx_thread_context_restore.S | 16 +- .../ac6/src/tx_thread_context_save.S | 16 +- .../cortex_a57/ac6/src/tx_thread_fp_disable.c | 15 +- .../cortex_a57/ac6/src/tx_thread_fp_enable.c | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 18 +- .../ac6/src/tx_thread_interrupt_disable.S | 18 +- .../ac6/src/tx_thread_interrupt_restore.S | 18 +- ports/cortex_a57/ac6/src/tx_thread_schedule.S | 20 +- .../ac6/src/tx_thread_stack_build.S | 18 +- .../ac6/src/tx_thread_system_return.S | 16 +- ports/cortex_a57/ac6/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 168 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.ld | 2 +- .../example_build/sample_threadx/startup.S | 2 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../gnu/example_build/sample_threadx/v8_mmu.h | 2 +- .../cortex_a57/gnu/example_build/tx/.cproject | 160 +-- ports/cortex_a57/gnu/inc/tx_port.h | 18 +- .../gnu/src/tx_initialize_low_level.S | 20 +- .../gnu/src/tx_thread_context_restore.S | 16 +- .../gnu/src/tx_thread_context_save.S | 16 +- .../cortex_a57/gnu/src/tx_thread_fp_disable.c | 15 +- .../cortex_a57/gnu/src/tx_thread_fp_enable.c | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 18 +- .../gnu/src/tx_thread_interrupt_disable.S | 18 +- .../gnu/src/tx_thread_interrupt_restore.S | 18 +- ports/cortex_a57/gnu/src/tx_thread_schedule.S | 20 +- .../gnu/src/tx_thread_stack_build.S | 18 +- .../gnu/src/tx_thread_system_return.S | 16 +- ports/cortex_a57/gnu/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 152 +-- .../armv8_aarch64_SystemTimer.S | 144 +-- .../sample_threadx/el3_vectors.S | 8 +- .../example_build/sample_threadx/gic400_gic.c | 4 +- .../example_build/sample_threadx/hw_setup.c | 2 +- .../sample_threadx/sample_threadx.c | 46 +- .../sample_threadx/sample_threadx.txt | 2 +- .../example_build/sample_threadx/startup.S | 10 +- .../cortex_a5x/ac6/example_build/tx/.cproject | 138 +-- ports/cortex_a5x/ac6/inc/tx_port.h | 92 +- ports/cortex_a5x/ac6/readme_threadx.txt | 104 +- .../ac6/src/tx_initialize_low_level.S | 69 +- .../ac6/src/tx_thread_context_restore.S | 73 +- .../ac6/src/tx_thread_context_save.S | 75 +- .../cortex_a5x/ac6/src/tx_thread_fp_disable.c | 67 +- .../cortex_a5x/ac6/src/tx_thread_fp_enable.c | 67 +- .../ac6/src/tx_thread_interrupt_control.S | 63 +- .../ac6/src/tx_thread_interrupt_disable.S | 61 +- .../ac6/src/tx_thread_interrupt_restore.S | 59 +- ports/cortex_a5x/ac6/src/tx_thread_schedule.S | 84 +- .../ac6/src/tx_thread_stack_build.S | 65 +- .../ac6/src/tx_thread_system_return.S | 67 +- ports/cortex_a5x/ac6/src/tx_timer_interrupt.S | 75 +- .../example_build/sample_threadx/.cproject | 156 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.scat | 4 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../ac6/example_build/sample_threadx/v8_mmu.h | 2 +- .../cortex_a65/ac6/example_build/tx/.cproject | 146 +-- ports/cortex_a65/ac6/inc/tx_port.h | 18 +- .../ac6/src/tx_initialize_low_level.S | 18 +- .../ac6/src/tx_thread_context_restore.S | 16 +- .../ac6/src/tx_thread_context_save.S | 16 +- .../cortex_a65/ac6/src/tx_thread_fp_disable.c | 15 +- .../cortex_a65/ac6/src/tx_thread_fp_enable.c | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 18 +- .../ac6/src/tx_thread_interrupt_disable.S | 18 +- .../ac6/src/tx_thread_interrupt_restore.S | 18 +- ports/cortex_a65/ac6/src/tx_thread_schedule.S | 20 +- .../ac6/src/tx_thread_stack_build.S | 18 +- .../ac6/src/tx_thread_system_return.S | 16 +- ports/cortex_a65/ac6/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 168 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.ld | 2 +- .../example_build/sample_threadx/startup.S | 2 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../gnu/example_build/sample_threadx/v8_mmu.h | 2 +- .../cortex_a65/gnu/example_build/tx/.cproject | 160 +-- ports/cortex_a65/gnu/inc/tx_port.h | 18 +- .../gnu/src/tx_initialize_low_level.S | 20 +- .../gnu/src/tx_thread_context_restore.S | 16 +- .../gnu/src/tx_thread_context_save.S | 16 +- .../cortex_a65/gnu/src/tx_thread_fp_disable.c | 15 +- .../cortex_a65/gnu/src/tx_thread_fp_enable.c | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 18 +- .../gnu/src/tx_thread_interrupt_disable.S | 18 +- .../gnu/src/tx_thread_interrupt_restore.S | 18 +- ports/cortex_a65/gnu/src/tx_thread_schedule.S | 20 +- .../gnu/src/tx_thread_stack_build.S | 18 +- .../gnu/src/tx_thread_system_return.S | 16 +- ports/cortex_a65/gnu/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 156 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.scat | 4 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../ac6/example_build/sample_threadx/v8_mmu.h | 2 +- .../ac6/example_build/tx/.cproject | 146 +-- ports/cortex_a65ae/ac6/inc/tx_port.h | 18 +- .../ac6/src/tx_initialize_low_level.S | 18 +- .../ac6/src/tx_thread_context_restore.S | 16 +- .../ac6/src/tx_thread_context_save.S | 16 +- .../ac6/src/tx_thread_fp_disable.c | 15 +- .../ac6/src/tx_thread_fp_enable.c | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 18 +- .../ac6/src/tx_thread_interrupt_disable.S | 18 +- .../ac6/src/tx_thread_interrupt_restore.S | 18 +- .../cortex_a65ae/ac6/src/tx_thread_schedule.S | 20 +- .../ac6/src/tx_thread_stack_build.S | 18 +- .../ac6/src/tx_thread_system_return.S | 16 +- .../cortex_a65ae/ac6/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 168 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.ld | 2 +- .../example_build/sample_threadx/startup.S | 2 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../gnu/example_build/sample_threadx/v8_mmu.h | 2 +- .../gnu/example_build/tx/.cproject | 160 +-- ports/cortex_a65ae/gnu/inc/tx_port.h | 18 +- .../gnu/src/tx_initialize_low_level.S | 20 +- .../gnu/src/tx_thread_context_restore.S | 16 +- .../gnu/src/tx_thread_context_save.S | 16 +- .../gnu/src/tx_thread_fp_disable.c | 15 +- .../gnu/src/tx_thread_fp_enable.c | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 18 +- .../gnu/src/tx_thread_interrupt_disable.S | 18 +- .../gnu/src/tx_thread_interrupt_restore.S | 18 +- .../cortex_a65ae/gnu/src/tx_thread_schedule.S | 20 +- .../gnu/src/tx_thread_stack_build.S | 18 +- .../gnu/src/tx_thread_system_return.S | 16 +- .../cortex_a65ae/gnu/src/tx_timer_interrupt.S | 16 +- .../ac5/example_build/sample_threadx.c | 46 +- .../example_build/tx_initialize_low_level.s | 112 +- ports/cortex_a7/ac5/inc/tx_port.h | 98 +- ports/cortex_a7/ac5/readme_threadx.txt | 332 +++--- .../ac5/src/tx_thread_context_restore.s | 70 +- .../ac5/src/tx_thread_context_save.s | 80 +- .../ac5/src/tx_thread_fiq_context_restore.s | 78 +- .../ac5/src/tx_thread_fiq_context_save.s | 102 +- .../ac5/src/tx_thread_fiq_nesting_end.s | 84 +- .../ac5/src/tx_thread_fiq_nesting_start.s | 74 +- .../ac5/src/tx_thread_interrupt_control.s | 62 +- .../ac5/src/tx_thread_interrupt_disable.s | 62 +- .../ac5/src/tx_thread_interrupt_restore.s | 58 +- .../ac5/src/tx_thread_irq_nesting_end.s | 84 +- .../ac5/src/tx_thread_irq_nesting_start.s | 74 +- ports/cortex_a7/ac5/src/tx_thread_schedule.s | 76 +- .../cortex_a7/ac5/src/tx_thread_stack_build.s | 62 +- .../ac5/src/tx_thread_system_return.s | 70 +- .../ac5/src/tx_thread_vectored_context_save.s | 68 +- ports/cortex_a7/ac5/src/tx_timer_interrupt.s | 76 +- .../example_build/sample_threadx/.cproject | 174 +-- .../sample_threadx/sample_threadx.scat | 2 +- .../sample_threadx/tx_initialize_low_level.S | 15 +- .../cortex_a7/ac6/example_build/tx/.cproject | 144 +-- ports/cortex_a7/ac6/inc/tx_port.h | 23 +- ports/cortex_a7/ac6/readme_threadx.txt | 146 +-- .../ac6/src/tx_thread_context_restore.S | 24 +- .../ac6/src/tx_thread_context_save.S | 24 +- .../ac6/src/tx_thread_fiq_context_restore.S | 21 +- .../ac6/src/tx_thread_fiq_context_save.S | 21 +- .../ac6/src/tx_thread_fiq_nesting_end.S | 21 +- .../ac6/src/tx_thread_fiq_nesting_start.S | 21 +- .../ac6/src/tx_thread_interrupt_control.S | 21 +- .../ac6/src/tx_thread_interrupt_disable.S | 21 +- .../ac6/src/tx_thread_interrupt_restore.S | 21 +- .../ac6/src/tx_thread_irq_nesting_end.S | 21 +- .../ac6/src/tx_thread_irq_nesting_start.S | 21 +- ports/cortex_a7/ac6/src/tx_thread_schedule.S | 25 +- .../cortex_a7/ac6/src/tx_thread_stack_build.S | 21 +- .../ac6/src/tx_thread_system_return.S | 24 +- .../ac6/src/tx_thread_vectored_context_save.S | 21 +- ports/cortex_a7/ac6/src/tx_timer_interrupt.S | 21 +- .../example_build/tx_initialize_low_level.arm | 6 +- ports/cortex_a7/ghs/inc/tx_el.h | 13 +- ports/cortex_a7/ghs/inc/tx_port.h | 18 +- ports/cortex_a7/ghs/readme_threadx.txt | 316 ++--- ports/cortex_a7/ghs/src/tx_el.c | 13 +- .../ghs/src/tx_thread_context_restore.arm | 6 +- .../ghs/src/tx_thread_context_save.arm | 6 +- .../ghs/src/tx_thread_fiq_context_restore.arm | 6 +- .../ghs/src/tx_thread_fiq_context_save.arm | 6 +- .../ghs/src/tx_thread_fiq_nesting_end.arm | 6 +- .../ghs/src/tx_thread_fiq_nesting_start.arm | 6 +- .../ghs/src/tx_thread_interrupt_control.arm | 6 +- .../ghs/src/tx_thread_interrupt_disable.arm | 6 +- .../ghs/src/tx_thread_interrupt_restore.arm | 6 +- .../ghs/src/tx_thread_irq_nesting_end.arm | 6 +- .../ghs/src/tx_thread_irq_nesting_start.arm | 6 +- .../cortex_a7/ghs/src/tx_thread_schedule.arm | 6 +- .../ghs/src/tx_thread_stack_build.arm | 6 +- .../ghs/src/tx_thread_system_return.arm | 6 +- .../src/tx_thread_vectored_context_save.arm | 6 +- .../cortex_a7/ghs/src/tx_timer_interrupt.arm | 6 +- ports/cortex_a7/gnu/example_build/MP_GIC.h | 2 +- ports/cortex_a7/gnu/example_build/MP_GIC.s | 32 +- .../gnu/example_build/MP_PrivateTimer.S | 2 +- ports/cortex_a7/gnu/example_build/reset.S | 7 +- .../gnu/example_build/sample_threadx.ld | 14 +- .../example_build/tx_initialize_low_level.S | 20 +- ports/cortex_a7/gnu/example_build/v7.h | 2 +- ports/cortex_a7/gnu/example_build/v7.s | 48 +- ports/cortex_a7/gnu/inc/tx_port.h | 23 +- ports/cortex_a7/gnu/readme_threadx.txt | 314 ++--- .../gnu/src/tx_thread_context_restore.S | 24 +- .../gnu/src/tx_thread_context_save.S | 24 +- .../gnu/src/tx_thread_fiq_context_restore.S | 21 +- .../gnu/src/tx_thread_fiq_context_save.S | 21 +- .../gnu/src/tx_thread_fiq_nesting_end.S | 21 +- .../gnu/src/tx_thread_fiq_nesting_start.S | 21 +- .../gnu/src/tx_thread_interrupt_control.S | 21 +- .../gnu/src/tx_thread_interrupt_disable.S | 21 +- .../gnu/src/tx_thread_interrupt_restore.S | 21 +- .../gnu/src/tx_thread_irq_nesting_end.S | 21 +- .../gnu/src/tx_thread_irq_nesting_start.S | 21 +- ports/cortex_a7/gnu/src/tx_thread_schedule.S | 25 +- .../cortex_a7/gnu/src/tx_thread_stack_build.S | 21 +- .../gnu/src/tx_thread_system_return.S | 24 +- .../gnu/src/tx_thread_vectored_context_save.S | 21 +- ports/cortex_a7/gnu/src/tx_timer_interrupt.S | 21 +- ports/cortex_a7/iar/example_build/cstartup.s | 10 +- .../iar/example_build/sample_threadx.c | 46 +- .../example_build/tx_initialize_low_level.s | 110 +- ports/cortex_a7/iar/inc/tx_port.h | 104 +- ports/cortex_a7/iar/readme_threadx.txt | 322 +++--- ports/cortex_a7/iar/src/tx_iar.c | 239 ++-- .../iar/src/tx_thread_context_restore.s | 79 +- .../iar/src/tx_thread_context_save.s | 83 +- .../iar/src/tx_thread_fiq_context_restore.s | 79 +- .../iar/src/tx_thread_fiq_context_save.s | 105 +- .../iar/src/tx_thread_fiq_nesting_end.s | 82 +- .../iar/src/tx_thread_fiq_nesting_start.s | 74 +- .../iar/src/tx_thread_interrupt_control.s | 62 +- .../iar/src/tx_thread_interrupt_disable.s | 60 +- .../iar/src/tx_thread_interrupt_restore.s | 58 +- .../iar/src/tx_thread_irq_nesting_end.s | 82 +- .../iar/src/tx_thread_irq_nesting_start.s | 74 +- ports/cortex_a7/iar/src/tx_thread_schedule.s | 83 +- .../cortex_a7/iar/src/tx_thread_stack_build.s | 64 +- .../iar/src/tx_thread_system_return.s | 71 +- .../iar/src/tx_thread_vectored_context_save.s | 71 +- ports/cortex_a7/iar/src/tx_timer_interrupt.s | 76 +- .../example_build/sample_threadx/.cproject | 156 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.scat | 4 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../ac6/example_build/sample_threadx/v8_mmu.h | 2 +- .../cortex_a72/ac6/example_build/tx/.cproject | 146 +-- ports/cortex_a72/ac6/inc/tx_port.h | 18 +- .../ac6/src/tx_initialize_low_level.S | 18 +- .../ac6/src/tx_thread_context_restore.S | 16 +- .../ac6/src/tx_thread_context_save.S | 16 +- .../cortex_a72/ac6/src/tx_thread_fp_disable.c | 15 +- .../cortex_a72/ac6/src/tx_thread_fp_enable.c | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 18 +- .../ac6/src/tx_thread_interrupt_disable.S | 18 +- .../ac6/src/tx_thread_interrupt_restore.S | 18 +- ports/cortex_a72/ac6/src/tx_thread_schedule.S | 20 +- .../ac6/src/tx_thread_stack_build.S | 18 +- .../ac6/src/tx_thread_system_return.S | 16 +- ports/cortex_a72/ac6/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 168 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.ld | 2 +- .../example_build/sample_threadx/startup.S | 2 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../gnu/example_build/sample_threadx/v8_mmu.h | 2 +- .../cortex_a72/gnu/example_build/tx/.cproject | 160 +-- ports/cortex_a72/gnu/inc/tx_port.h | 18 +- .../gnu/src/tx_initialize_low_level.S | 20 +- .../gnu/src/tx_thread_context_restore.S | 16 +- .../gnu/src/tx_thread_context_save.S | 16 +- .../cortex_a72/gnu/src/tx_thread_fp_disable.c | 15 +- .../cortex_a72/gnu/src/tx_thread_fp_enable.c | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 18 +- .../gnu/src/tx_thread_interrupt_disable.S | 18 +- .../gnu/src/tx_thread_interrupt_restore.S | 18 +- ports/cortex_a72/gnu/src/tx_thread_schedule.S | 20 +- .../gnu/src/tx_thread_stack_build.S | 18 +- .../gnu/src/tx_thread_system_return.S | 16 +- ports/cortex_a72/gnu/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 156 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.scat | 4 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../ac6/example_build/sample_threadx/v8_mmu.h | 2 +- .../cortex_a73/ac6/example_build/tx/.cproject | 146 +-- ports/cortex_a73/ac6/inc/tx_port.h | 18 +- .../ac6/src/tx_initialize_low_level.S | 18 +- .../ac6/src/tx_thread_context_restore.S | 16 +- .../ac6/src/tx_thread_context_save.S | 16 +- .../cortex_a73/ac6/src/tx_thread_fp_disable.c | 15 +- .../cortex_a73/ac6/src/tx_thread_fp_enable.c | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 18 +- .../ac6/src/tx_thread_interrupt_disable.S | 18 +- .../ac6/src/tx_thread_interrupt_restore.S | 18 +- ports/cortex_a73/ac6/src/tx_thread_schedule.S | 20 +- .../ac6/src/tx_thread_stack_build.S | 18 +- .../ac6/src/tx_thread_system_return.S | 16 +- ports/cortex_a73/ac6/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 168 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.ld | 2 +- .../example_build/sample_threadx/startup.S | 2 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../gnu/example_build/sample_threadx/v8_mmu.h | 2 +- .../cortex_a73/gnu/example_build/tx/.cproject | 160 +-- ports/cortex_a73/gnu/inc/tx_port.h | 18 +- .../gnu/src/tx_initialize_low_level.S | 20 +- .../gnu/src/tx_thread_context_restore.S | 16 +- .../gnu/src/tx_thread_context_save.S | 16 +- .../cortex_a73/gnu/src/tx_thread_fp_disable.c | 15 +- .../cortex_a73/gnu/src/tx_thread_fp_enable.c | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 18 +- .../gnu/src/tx_thread_interrupt_disable.S | 18 +- .../gnu/src/tx_thread_interrupt_restore.S | 18 +- ports/cortex_a73/gnu/src/tx_thread_schedule.S | 20 +- .../gnu/src/tx_thread_stack_build.S | 18 +- .../gnu/src/tx_thread_system_return.S | 16 +- ports/cortex_a73/gnu/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 156 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.scat | 4 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../ac6/example_build/sample_threadx/v8_mmu.h | 2 +- .../cortex_a75/ac6/example_build/tx/.cproject | 146 +-- ports/cortex_a75/ac6/inc/tx_port.h | 18 +- .../ac6/src/tx_initialize_low_level.S | 18 +- .../ac6/src/tx_thread_context_restore.S | 16 +- .../ac6/src/tx_thread_context_save.S | 16 +- .../cortex_a75/ac6/src/tx_thread_fp_disable.c | 15 +- .../cortex_a75/ac6/src/tx_thread_fp_enable.c | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 18 +- .../ac6/src/tx_thread_interrupt_disable.S | 18 +- .../ac6/src/tx_thread_interrupt_restore.S | 18 +- ports/cortex_a75/ac6/src/tx_thread_schedule.S | 20 +- .../ac6/src/tx_thread_stack_build.S | 18 +- .../ac6/src/tx_thread_system_return.S | 16 +- ports/cortex_a75/ac6/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 168 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.ld | 2 +- .../example_build/sample_threadx/startup.S | 2 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../gnu/example_build/sample_threadx/v8_mmu.h | 2 +- .../cortex_a75/gnu/example_build/tx/.cproject | 160 +-- ports/cortex_a75/gnu/inc/tx_port.h | 18 +- .../gnu/src/tx_initialize_low_level.S | 20 +- .../gnu/src/tx_thread_context_restore.S | 16 +- .../gnu/src/tx_thread_context_save.S | 16 +- .../cortex_a75/gnu/src/tx_thread_fp_disable.c | 15 +- .../cortex_a75/gnu/src/tx_thread_fp_enable.c | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 18 +- .../gnu/src/tx_thread_interrupt_disable.S | 18 +- .../gnu/src/tx_thread_interrupt_restore.S | 18 +- ports/cortex_a75/gnu/src/tx_thread_schedule.S | 20 +- .../gnu/src/tx_thread_stack_build.S | 18 +- .../gnu/src/tx_thread_system_return.S | 16 +- ports/cortex_a75/gnu/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 156 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.scat | 4 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../ac6/example_build/sample_threadx/v8_mmu.h | 2 +- .../cortex_a76/ac6/example_build/tx/.cproject | 146 +-- ports/cortex_a76/ac6/inc/tx_port.h | 18 +- .../ac6/src/tx_initialize_low_level.S | 18 +- .../ac6/src/tx_thread_context_restore.S | 16 +- .../ac6/src/tx_thread_context_save.S | 16 +- .../cortex_a76/ac6/src/tx_thread_fp_disable.c | 15 +- .../cortex_a76/ac6/src/tx_thread_fp_enable.c | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 18 +- .../ac6/src/tx_thread_interrupt_disable.S | 18 +- .../ac6/src/tx_thread_interrupt_restore.S | 18 +- ports/cortex_a76/ac6/src/tx_thread_schedule.S | 20 +- .../ac6/src/tx_thread_stack_build.S | 18 +- .../ac6/src/tx_thread_system_return.S | 16 +- ports/cortex_a76/ac6/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 168 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.ld | 2 +- .../example_build/sample_threadx/startup.S | 2 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../gnu/example_build/sample_threadx/v8_mmu.h | 2 +- .../cortex_a76/gnu/example_build/tx/.cproject | 160 +-- ports/cortex_a76/gnu/inc/tx_port.h | 18 +- .../gnu/src/tx_initialize_low_level.S | 20 +- .../gnu/src/tx_thread_context_restore.S | 16 +- .../gnu/src/tx_thread_context_save.S | 16 +- .../cortex_a76/gnu/src/tx_thread_fp_disable.c | 15 +- .../cortex_a76/gnu/src/tx_thread_fp_enable.c | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 18 +- .../gnu/src/tx_thread_interrupt_disable.S | 18 +- .../gnu/src/tx_thread_interrupt_restore.S | 18 +- ports/cortex_a76/gnu/src/tx_thread_schedule.S | 20 +- .../gnu/src/tx_thread_stack_build.S | 18 +- .../gnu/src/tx_thread_system_return.S | 16 +- ports/cortex_a76/gnu/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 156 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.scat | 4 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../ac6/example_build/sample_threadx/v8_mmu.h | 2 +- .../ac6/example_build/tx/.cproject | 146 +-- ports/cortex_a76ae/ac6/inc/tx_port.h | 18 +- .../ac6/src/tx_initialize_low_level.S | 18 +- .../ac6/src/tx_thread_context_restore.S | 16 +- .../ac6/src/tx_thread_context_save.S | 16 +- .../ac6/src/tx_thread_fp_disable.c | 15 +- .../ac6/src/tx_thread_fp_enable.c | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 18 +- .../ac6/src/tx_thread_interrupt_disable.S | 18 +- .../ac6/src/tx_thread_interrupt_restore.S | 18 +- .../cortex_a76ae/ac6/src/tx_thread_schedule.S | 20 +- .../ac6/src/tx_thread_stack_build.S | 18 +- .../ac6/src/tx_thread_system_return.S | 16 +- .../cortex_a76ae/ac6/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 168 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.ld | 2 +- .../example_build/sample_threadx/startup.S | 2 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../gnu/example_build/sample_threadx/v8_mmu.h | 2 +- .../gnu/example_build/tx/.cproject | 160 +-- ports/cortex_a76ae/gnu/inc/tx_port.h | 18 +- .../gnu/src/tx_initialize_low_level.S | 20 +- .../gnu/src/tx_thread_context_restore.S | 16 +- .../gnu/src/tx_thread_context_save.S | 16 +- .../gnu/src/tx_thread_fp_disable.c | 15 +- .../gnu/src/tx_thread_fp_enable.c | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 18 +- .../gnu/src/tx_thread_interrupt_disable.S | 18 +- .../gnu/src/tx_thread_interrupt_restore.S | 18 +- .../cortex_a76ae/gnu/src/tx_thread_schedule.S | 20 +- .../gnu/src/tx_thread_stack_build.S | 18 +- .../gnu/src/tx_thread_system_return.S | 16 +- .../cortex_a76ae/gnu/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 156 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.scat | 4 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../ac6/example_build/sample_threadx/v8_mmu.h | 2 +- .../cortex_a77/ac6/example_build/tx/.cproject | 146 +-- ports/cortex_a77/ac6/inc/tx_port.h | 18 +- .../ac6/src/tx_initialize_low_level.S | 18 +- .../ac6/src/tx_thread_context_restore.S | 16 +- .../ac6/src/tx_thread_context_save.S | 16 +- .../cortex_a77/ac6/src/tx_thread_fp_disable.c | 15 +- .../cortex_a77/ac6/src/tx_thread_fp_enable.c | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 18 +- .../ac6/src/tx_thread_interrupt_disable.S | 18 +- .../ac6/src/tx_thread_interrupt_restore.S | 18 +- ports/cortex_a77/ac6/src/tx_thread_schedule.S | 20 +- .../ac6/src/tx_thread_stack_build.S | 18 +- .../ac6/src/tx_thread_system_return.S | 16 +- ports/cortex_a77/ac6/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 168 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.ld | 2 +- .../example_build/sample_threadx/startup.S | 2 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../gnu/example_build/sample_threadx/v8_mmu.h | 2 +- .../cortex_a77/gnu/example_build/tx/.cproject | 160 +-- ports/cortex_a77/gnu/inc/tx_port.h | 18 +- .../gnu/src/tx_initialize_low_level.S | 20 +- .../gnu/src/tx_thread_context_restore.S | 16 +- .../gnu/src/tx_thread_context_save.S | 16 +- .../cortex_a77/gnu/src/tx_thread_fp_disable.c | 15 +- .../cortex_a77/gnu/src/tx_thread_fp_enable.c | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 18 +- .../gnu/src/tx_thread_interrupt_disable.S | 18 +- .../gnu/src/tx_thread_interrupt_restore.S | 18 +- ports/cortex_a77/gnu/src/tx_thread_schedule.S | 20 +- .../gnu/src/tx_thread_stack_build.S | 18 +- .../gnu/src/tx_thread_system_return.S | 16 +- ports/cortex_a77/gnu/src/tx_timer_interrupt.S | 16 +- .../ac5/example_build/sample_threadx.c | 46 +- .../example_build/tx_initialize_low_level.s | 112 +- ports/cortex_a8/ac5/inc/tx_port.h | 98 +- ports/cortex_a8/ac5/readme_threadx.txt | 334 +++--- .../ac5/src/tx_thread_context_restore.s | 70 +- .../ac5/src/tx_thread_context_save.s | 80 +- .../ac5/src/tx_thread_fiq_context_restore.s | 78 +- .../ac5/src/tx_thread_fiq_context_save.s | 102 +- .../ac5/src/tx_thread_fiq_nesting_end.s | 84 +- .../ac5/src/tx_thread_fiq_nesting_start.s | 74 +- .../ac5/src/tx_thread_interrupt_control.s | 62 +- .../ac5/src/tx_thread_interrupt_disable.s | 62 +- .../ac5/src/tx_thread_interrupt_restore.s | 58 +- .../ac5/src/tx_thread_irq_nesting_end.s | 84 +- .../ac5/src/tx_thread_irq_nesting_start.s | 74 +- ports/cortex_a8/ac5/src/tx_thread_schedule.s | 76 +- .../cortex_a8/ac5/src/tx_thread_stack_build.s | 62 +- .../ac5/src/tx_thread_system_return.s | 70 +- .../ac5/src/tx_thread_vectored_context_save.s | 68 +- ports/cortex_a8/ac5/src/tx_timer_interrupt.s | 76 +- .../example_build/sample_threadx/.cproject | 174 +-- .../sample_threadx/sample_threadx.scat | 2 +- .../sample_threadx/tx_initialize_low_level.S | 15 +- .../cortex_a8/ac6/example_build/tx/.cproject | 144 +-- ports/cortex_a8/ac6/inc/tx_port.h | 23 +- ports/cortex_a8/ac6/readme_threadx.txt | 142 +-- .../ac6/src/tx_thread_context_restore.S | 24 +- .../ac6/src/tx_thread_context_save.S | 24 +- .../ac6/src/tx_thread_fiq_context_restore.S | 21 +- .../ac6/src/tx_thread_fiq_context_save.S | 21 +- .../ac6/src/tx_thread_fiq_nesting_end.S | 21 +- .../ac6/src/tx_thread_fiq_nesting_start.S | 21 +- .../ac6/src/tx_thread_interrupt_control.S | 21 +- .../ac6/src/tx_thread_interrupt_disable.S | 21 +- .../ac6/src/tx_thread_interrupt_restore.S | 21 +- .../ac6/src/tx_thread_irq_nesting_end.S | 21 +- .../ac6/src/tx_thread_irq_nesting_start.S | 21 +- ports/cortex_a8/ac6/src/tx_thread_schedule.S | 25 +- .../cortex_a8/ac6/src/tx_thread_stack_build.S | 21 +- .../ac6/src/tx_thread_system_return.S | 24 +- .../ac6/src/tx_thread_vectored_context_save.S | 21 +- ports/cortex_a8/ac6/src/tx_timer_interrupt.S | 21 +- .../example_build/tx_initialize_low_level.arm | 6 +- ports/cortex_a8/ghs/inc/tx_el.h | 13 +- ports/cortex_a8/ghs/inc/tx_port.h | 18 +- ports/cortex_a8/ghs/readme_threadx.txt | 316 ++--- ports/cortex_a8/ghs/src/tx_el.c | 13 +- .../ghs/src/tx_thread_context_restore.arm | 6 +- .../ghs/src/tx_thread_context_save.arm | 6 +- .../ghs/src/tx_thread_fiq_context_restore.arm | 6 +- .../ghs/src/tx_thread_fiq_context_save.arm | 6 +- .../ghs/src/tx_thread_fiq_nesting_end.arm | 6 +- .../ghs/src/tx_thread_fiq_nesting_start.arm | 6 +- .../ghs/src/tx_thread_interrupt_control.arm | 6 +- .../ghs/src/tx_thread_interrupt_disable.arm | 6 +- .../ghs/src/tx_thread_interrupt_restore.arm | 6 +- .../ghs/src/tx_thread_irq_nesting_end.arm | 6 +- .../ghs/src/tx_thread_irq_nesting_start.arm | 6 +- .../cortex_a8/ghs/src/tx_thread_schedule.arm | 6 +- .../ghs/src/tx_thread_stack_build.arm | 6 +- .../ghs/src/tx_thread_system_return.arm | 6 +- .../src/tx_thread_vectored_context_save.arm | 6 +- .../cortex_a8/ghs/src/tx_timer_interrupt.arm | 6 +- ports/cortex_a8/gnu/example_build/MP_GIC.h | 2 +- ports/cortex_a8/gnu/example_build/MP_GIC.s | 32 +- .../gnu/example_build/MP_PrivateTimer.S | 2 +- ports/cortex_a8/gnu/example_build/reset.S | 7 +- .../gnu/example_build/sample_threadx.ld | 14 +- .../example_build/tx_initialize_low_level.S | 20 +- ports/cortex_a8/gnu/example_build/v7.h | 2 +- ports/cortex_a8/gnu/example_build/v7.s | 48 +- ports/cortex_a8/gnu/inc/tx_port.h | 23 +- ports/cortex_a8/gnu/readme_threadx.txt | 314 ++--- .../gnu/src/tx_thread_context_restore.S | 24 +- .../gnu/src/tx_thread_context_save.S | 24 +- .../gnu/src/tx_thread_fiq_context_restore.S | 21 +- .../gnu/src/tx_thread_fiq_context_save.S | 21 +- .../gnu/src/tx_thread_fiq_nesting_end.S | 21 +- .../gnu/src/tx_thread_fiq_nesting_start.S | 21 +- .../gnu/src/tx_thread_interrupt_control.S | 21 +- .../gnu/src/tx_thread_interrupt_disable.S | 21 +- .../gnu/src/tx_thread_interrupt_restore.S | 21 +- .../gnu/src/tx_thread_irq_nesting_end.S | 21 +- .../gnu/src/tx_thread_irq_nesting_start.S | 21 +- ports/cortex_a8/gnu/src/tx_thread_schedule.S | 25 +- .../cortex_a8/gnu/src/tx_thread_stack_build.S | 21 +- .../gnu/src/tx_thread_system_return.S | 24 +- .../gnu/src/tx_thread_vectored_context_save.S | 21 +- ports/cortex_a8/gnu/src/tx_timer_interrupt.S | 21 +- ports/cortex_a8/iar/example_build/cstartup.s | 10 +- .../iar/example_build/sample_threadx.c | 46 +- .../example_build/tx_initialize_low_level.s | 110 +- ports/cortex_a8/iar/inc/tx_port.h | 104 +- ports/cortex_a8/iar/readme_threadx.txt | 322 +++--- ports/cortex_a8/iar/src/tx_iar.c | 239 ++-- .../iar/src/tx_thread_context_restore.s | 77 +- .../iar/src/tx_thread_context_save.s | 83 +- .../iar/src/tx_thread_fiq_context_restore.s | 79 +- .../iar/src/tx_thread_fiq_context_save.s | 105 +- .../iar/src/tx_thread_fiq_nesting_end.s | 82 +- .../iar/src/tx_thread_fiq_nesting_start.s | 74 +- .../iar/src/tx_thread_interrupt_control.s | 62 +- .../iar/src/tx_thread_interrupt_disable.s | 60 +- .../iar/src/tx_thread_interrupt_restore.s | 58 +- .../iar/src/tx_thread_irq_nesting_end.s | 82 +- .../iar/src/tx_thread_irq_nesting_start.s | 74 +- ports/cortex_a8/iar/src/tx_thread_schedule.s | 83 +- .../cortex_a8/iar/src/tx_thread_stack_build.s | 64 +- .../iar/src/tx_thread_system_return.s | 71 +- .../iar/src/tx_thread_vectored_context_save.s | 71 +- ports/cortex_a8/iar/src/tx_timer_interrupt.s | 76 +- .../ac5/example_build/sample_threadx.c | 46 +- .../example_build/tx_initialize_low_level.s | 112 +- ports/cortex_a9/ac5/inc/tx_port.h | 98 +- ports/cortex_a9/ac5/readme_threadx.txt | 334 +++--- .../ac5/src/tx_thread_context_restore.s | 70 +- .../ac5/src/tx_thread_context_save.s | 80 +- .../ac5/src/tx_thread_fiq_context_restore.s | 78 +- .../ac5/src/tx_thread_fiq_context_save.s | 102 +- .../ac5/src/tx_thread_fiq_nesting_end.s | 84 +- .../ac5/src/tx_thread_fiq_nesting_start.s | 74 +- .../ac5/src/tx_thread_interrupt_control.s | 62 +- .../ac5/src/tx_thread_interrupt_disable.s | 62 +- .../ac5/src/tx_thread_interrupt_restore.s | 58 +- .../ac5/src/tx_thread_irq_nesting_end.s | 84 +- .../ac5/src/tx_thread_irq_nesting_start.s | 74 +- ports/cortex_a9/ac5/src/tx_thread_schedule.s | 76 +- .../cortex_a9/ac5/src/tx_thread_stack_build.s | 62 +- .../ac5/src/tx_thread_system_return.s | 70 +- .../ac5/src/tx_thread_vectored_context_save.s | 68 +- ports/cortex_a9/ac5/src/tx_timer_interrupt.s | 76 +- .../example_build/sample_threadx/.cproject | 174 +-- .../sample_threadx/sample_threadx.scat | 2 +- .../sample_threadx/tx_initialize_low_level.S | 15 +- .../cortex_a9/ac6/example_build/tx/.cproject | 144 +-- ports/cortex_a9/ac6/inc/tx_port.h | 23 +- ports/cortex_a9/ac6/readme_threadx.txt | 146 +-- .../ac6/src/tx_thread_context_restore.S | 24 +- .../ac6/src/tx_thread_context_save.S | 24 +- .../ac6/src/tx_thread_fiq_context_restore.S | 21 +- .../ac6/src/tx_thread_fiq_context_save.S | 21 +- .../ac6/src/tx_thread_fiq_nesting_end.S | 21 +- .../ac6/src/tx_thread_fiq_nesting_start.S | 21 +- .../ac6/src/tx_thread_interrupt_control.S | 21 +- .../ac6/src/tx_thread_interrupt_disable.S | 21 +- .../ac6/src/tx_thread_interrupt_restore.S | 21 +- .../ac6/src/tx_thread_irq_nesting_end.S | 21 +- .../ac6/src/tx_thread_irq_nesting_start.S | 21 +- ports/cortex_a9/ac6/src/tx_thread_schedule.S | 25 +- .../cortex_a9/ac6/src/tx_thread_stack_build.S | 21 +- .../ac6/src/tx_thread_system_return.S | 24 +- .../ac6/src/tx_thread_vectored_context_save.S | 21 +- ports/cortex_a9/ac6/src/tx_timer_interrupt.S | 21 +- .../example_build/tx_initialize_low_level.arm | 6 +- ports/cortex_a9/ghs/inc/tx_el.h | 13 +- ports/cortex_a9/ghs/inc/tx_port.h | 18 +- ports/cortex_a9/ghs/readme_threadx.txt | 316 ++--- ports/cortex_a9/ghs/src/tx_el.c | 13 +- .../ghs/src/tx_thread_context_restore.arm | 6 +- .../ghs/src/tx_thread_context_save.arm | 6 +- .../ghs/src/tx_thread_fiq_context_restore.arm | 6 +- .../ghs/src/tx_thread_fiq_context_save.arm | 6 +- .../ghs/src/tx_thread_fiq_nesting_end.arm | 6 +- .../ghs/src/tx_thread_fiq_nesting_start.arm | 6 +- .../ghs/src/tx_thread_interrupt_control.arm | 6 +- .../ghs/src/tx_thread_interrupt_disable.arm | 6 +- .../ghs/src/tx_thread_interrupt_restore.arm | 6 +- .../ghs/src/tx_thread_irq_nesting_end.arm | 6 +- .../ghs/src/tx_thread_irq_nesting_start.arm | 6 +- .../cortex_a9/ghs/src/tx_thread_schedule.arm | 6 +- .../ghs/src/tx_thread_stack_build.arm | 6 +- .../ghs/src/tx_thread_system_return.arm | 6 +- .../src/tx_thread_vectored_context_save.arm | 6 +- .../cortex_a9/ghs/src/tx_timer_interrupt.arm | 6 +- ports/cortex_a9/gnu/example_build/MP_GIC.S | 2 +- ports/cortex_a9/gnu/example_build/MP_GIC.h | 2 +- .../gnu/example_build/MP_PrivateTimer.S | 2 +- ports/cortex_a9/gnu/example_build/reset.S | 7 +- .../gnu/example_build/sample_threadx.ld | 14 +- .../example_build/tx_initialize_low_level.S | 24 +- ports/cortex_a9/gnu/example_build/v7.h | 2 +- ports/cortex_a9/gnu/example_build/v7.s | 48 +- ports/cortex_a9/gnu/inc/tx_port.h | 23 +- ports/cortex_a9/gnu/readme_threadx.txt | 314 ++--- .../gnu/src/tx_thread_context_restore.S | 24 +- .../gnu/src/tx_thread_context_save.S | 24 +- .../gnu/src/tx_thread_fiq_context_restore.S | 21 +- .../gnu/src/tx_thread_fiq_context_save.S | 21 +- .../gnu/src/tx_thread_fiq_nesting_end.S | 21 +- .../gnu/src/tx_thread_fiq_nesting_start.S | 21 +- .../gnu/src/tx_thread_interrupt_control.S | 21 +- .../gnu/src/tx_thread_interrupt_disable.S | 21 +- .../gnu/src/tx_thread_interrupt_restore.S | 21 +- .../gnu/src/tx_thread_irq_nesting_end.S | 21 +- .../gnu/src/tx_thread_irq_nesting_start.S | 21 +- ports/cortex_a9/gnu/src/tx_thread_schedule.S | 25 +- .../cortex_a9/gnu/src/tx_thread_stack_build.S | 21 +- .../gnu/src/tx_thread_system_return.S | 24 +- .../gnu/src/tx_thread_vectored_context_save.S | 21 +- ports/cortex_a9/gnu/src/tx_timer_interrupt.S | 21 +- ports/cortex_a9/iar/example_build/cstartup.s | 10 +- .../iar/example_build/sample_threadx.c | 46 +- .../example_build/tx_initialize_low_level.s | 110 +- ports/cortex_a9/iar/inc/tx_port.h | 104 +- ports/cortex_a9/iar/readme_threadx.txt | 322 +++--- ports/cortex_a9/iar/src/tx_iar.c | 239 ++-- .../iar/src/tx_thread_context_restore.s | 79 +- .../iar/src/tx_thread_context_save.s | 83 +- .../iar/src/tx_thread_fiq_context_restore.s | 79 +- .../iar/src/tx_thread_fiq_context_save.s | 105 +- .../iar/src/tx_thread_fiq_nesting_end.s | 82 +- .../iar/src/tx_thread_fiq_nesting_start.s | 74 +- .../iar/src/tx_thread_interrupt_control.s | 62 +- .../iar/src/tx_thread_interrupt_disable.s | 60 +- .../iar/src/tx_thread_interrupt_restore.s | 58 +- .../iar/src/tx_thread_irq_nesting_end.s | 82 +- .../iar/src/tx_thread_irq_nesting_start.s | 74 +- ports/cortex_a9/iar/src/tx_thread_schedule.s | 83 +- .../cortex_a9/iar/src/tx_thread_stack_build.s | 64 +- .../iar/src/tx_thread_system_return.s | 71 +- .../iar/src/tx_thread_vectored_context_save.s | 71 +- ports/cortex_a9/iar/src/tx_timer_interrupt.s | 76 +- .../ac5/example_build/sample_threadx.c | 46 +- .../example_build/tx_initialize_low_level.s | 12 +- ports/cortex_m0/ac5/inc/tx_port.h | 67 +- ports/cortex_m0/ac5/readme_threadx.txt | 64 +- .../ac5/src/tx_thread_context_restore.s | 16 +- .../ac5/src/tx_thread_context_save.s | 16 +- .../ac5/src/tx_thread_interrupt_control.s | 12 +- .../ac5/src/tx_thread_interrupt_disable.s | 12 +- .../ac5/src/tx_thread_interrupt_restore.s | 12 +- ports/cortex_m0/ac5/src/tx_thread_schedule.s | 21 +- .../cortex_m0/ac5/src/tx_thread_stack_build.s | 12 +- .../ac5/src/tx_thread_system_return.s | 12 +- ports/cortex_m0/ac5/src/tx_timer_interrupt.s | 12 +- .../example_build/sample_threadx/.cproject | 164 +-- .../example_build/sample_threadx/exceptions.c | 2 +- .../sample_threadx/sample_threadx.c | 46 +- .../sample_threadx/sample_threadx.scat | 2 +- .../sample_threadx/tx_initialize_low_level.S | 12 +- .../cortex_m0/ac6/example_build/tx/.cproject | 144 +-- ports/cortex_m0/ac6/inc/tx_port.h | 59 +- ports/cortex_m0/ac6/readme_threadx.txt | 64 +- .../ac6/src/tx_thread_context_restore.S | 16 +- .../ac6/src/tx_thread_context_save.S | 18 +- .../ac6/src/tx_thread_interrupt_control.S | 14 +- .../ac6/src/tx_thread_interrupt_disable.S | 14 +- .../ac6/src/tx_thread_interrupt_restore.S | 14 +- ports/cortex_m0/ac6/src/tx_thread_schedule.S | 23 +- .../cortex_m0/ac6/src/tx_thread_stack_build.S | 14 +- .../ac6/src/tx_thread_system_return.S | 14 +- ports/cortex_m0/ac6/src/tx_timer_interrupt.S | 14 +- .../gnu/example_build/cortexm0_crt0.S | 5 +- .../gnu/example_build/cortexm0_vectors.S | 12 +- .../gnu/example_build/sample_threadx.c | 46 +- .../gnu/example_build/sample_threadx.ld | 10 +- .../example_build/tx_initialize_low_level.S | 38 +- ports/cortex_m0/gnu/inc/tx_port.h | 61 +- ports/cortex_m0/gnu/readme_threadx.txt | 72 +- .../gnu/src/tx_thread_context_restore.S | 19 +- .../gnu/src/tx_thread_context_save.S | 21 +- .../gnu/src/tx_thread_interrupt_control.S | 16 +- .../gnu/src/tx_thread_interrupt_disable.S | 16 +- .../gnu/src/tx_thread_interrupt_restore.S | 16 +- ports/cortex_m0/gnu/src/tx_thread_schedule.S | 23 +- .../cortex_m0/gnu/src/tx_thread_stack_build.S | 20 +- .../gnu/src/tx_thread_system_return.S | 16 +- ports/cortex_m0/gnu/src/tx_timer_interrupt.S | 16 +- ports/cortex_m0/iar/CMakeLists.txt | 2 +- .../cortex_m0/iar/example_build/cstartup_M.s | 10 +- .../iar/example_build/sample_threadx.c | 48 +- .../example_build/tx_initialize_low_level.s | 12 +- ports/cortex_m0/iar/inc/tx_port.h | 75 +- ports/cortex_m0/iar/readme_threadx.txt | 88 +- ports/cortex_m0/iar/src/tx_iar.c | 235 ++-- .../iar/src/tx_thread_context_restore.s | 14 +- .../iar/src/tx_thread_context_save.s | 14 +- .../iar/src/tx_thread_interrupt_control.s | 12 +- .../iar/src/tx_thread_interrupt_disable.s | 12 +- .../iar/src/tx_thread_interrupt_restore.s | 12 +- ports/cortex_m0/iar/src/tx_thread_schedule.s | 19 +- .../cortex_m0/iar/src/tx_thread_stack_build.s | 12 +- .../iar/src/tx_thread_system_return.s | 12 +- ports/cortex_m0/iar/src/tx_timer_interrupt.s | 12 +- .../keil/example_build/sample_threadx.c | 46 +- .../example_build/tx_initialize_low_level.s | 12 +- ports/cortex_m0/keil/inc/tx_port.h | 67 +- ports/cortex_m0/keil/readme_threadx.txt | 60 +- .../keil/src/tx_thread_context_restore.s | 18 +- .../keil/src/tx_thread_context_save.s | 16 +- .../keil/src/tx_thread_interrupt_control.s | 12 +- .../keil/src/tx_thread_interrupt_disable.s | 12 +- .../keil/src/tx_thread_interrupt_restore.s | 12 +- ports/cortex_m0/keil/src/tx_thread_schedule.s | 21 +- .../keil/src/tx_thread_stack_build.s | 12 +- .../keil/src/tx_thread_system_return.s | 12 +- ports/cortex_m0/keil/src/tx_timer_interrupt.s | 12 +- .../ac6/example_build/ARMCM23_TZ_config.txt | 2 +- .../_ThreadX_Library_Project/RTE_Components.h | 6 +- .../demo_secure_zone/Abstract.txt | 8 +- .../RTE/Device/ARMCM23_TZ/partition_ARMCM23.h | 2 +- .../RTE/Device/ARMCM23_TZ/system_ARMCM23.c | 2 +- .../_FVP_Simulation_Model/RTE_Components.h | 6 +- .../demo_secure_zone/interface.c | 10 +- .../example_build/demo_secure_zone/main_ns.c | 2 +- .../example_build/demo_secure_zone/main_s.c | 18 +- .../demo_secure_zone/tx_secure_interface.h | 13 +- .../demo_secure_zone/tz_context.c | 2 +- .../RTE/CMSIS/RTX_Config.c | 6 +- .../RTE/CMSIS/RTX_Config.h | 220 ++-- .../RTE/Device/ARMCM23_TZ/partition_ARMCM23.h | 2 +- .../_FVP_Simulation_Model/RTE_Components.h | 6 +- .../_ThreadX_Library_Project/RTE_Components.h | 6 +- .../demo_threadx.c | 78 +- .../example_build/tx_initialize_low_level.S | 31 +- ports/cortex_m23/ac6/inc/tx_port.h | 71 +- .../cortex_m23/ac6/inc/tx_secure_interface.h | 13 +- ports/cortex_m23/ac6/readme_threadx.txt | 58 +- ports/cortex_m23/ac6/src/tx_misra.S | 19 +- .../ac6/src/tx_thread_context_restore.S | 15 +- .../ac6/src/tx_thread_context_save.S | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 15 +- .../ac6/src/tx_thread_interrupt_disable.S | 15 +- .../ac6/src/tx_thread_interrupt_restore.S | 15 +- ports/cortex_m23/ac6/src/tx_thread_schedule.S | 23 +- .../ac6/src/tx_thread_secure_stack.c | 22 +- .../ac6/src/tx_thread_secure_stack_allocate.S | 15 +- .../ac6/src/tx_thread_secure_stack_free.S | 15 +- .../src/tx_thread_secure_stack_initialize.S | 19 +- .../ac6/src/tx_thread_stack_build.S | 17 +- .../ac6/src/tx_thread_system_return.S | 15 +- ports/cortex_m23/ac6/src/tx_timer_interrupt.S | 15 +- .../src/txe_thread_secure_stack_allocate.c | 21 +- .../ac6/src/txe_thread_secure_stack_free.c | 21 +- ports/cortex_m23/gnu/inc/tx_port.h | 72 +- .../cortex_m23/gnu/inc/tx_secure_interface.h | 13 +- ports/cortex_m23/gnu/readme_threadx.txt | 54 +- .../gnu/src/tx_initialize_low_level.S | 35 +- ports/cortex_m23/gnu/src/tx_misra.S | 19 +- .../gnu/src/tx_thread_context_restore.S | 15 +- .../gnu/src/tx_thread_context_save.S | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 15 +- .../gnu/src/tx_thread_interrupt_disable.S | 15 +- .../gnu/src/tx_thread_interrupt_restore.S | 15 +- ports/cortex_m23/gnu/src/tx_thread_schedule.S | 23 +- .../gnu/src/tx_thread_secure_stack.c | 22 +- .../gnu/src/tx_thread_secure_stack_allocate.S | 15 +- .../gnu/src/tx_thread_secure_stack_free.S | 15 +- .../src/tx_thread_secure_stack_initialize.S | 19 +- .../gnu/src/tx_thread_stack_build.S | 17 +- .../gnu/src/tx_thread_system_return.S | 15 +- ports/cortex_m23/gnu/src/tx_timer_interrupt.S | 15 +- .../src/txe_thread_secure_stack_allocate.c | 21 +- .../gnu/src/txe_thread_secure_stack_free.c | 21 +- ports/cortex_m23/iar/inc/tx_port.h | 72 +- .../cortex_m23/iar/inc/tx_secure_interface.h | 13 +- ports/cortex_m23/iar/readme_threadx.txt | 48 +- ports/cortex_m23/iar/src/tx_iar.c | 235 ++-- .../iar/src/tx_initialize_low_level.s | 28 +- ports/cortex_m23/iar/src/tx_misra.s | 23 +- .../iar/src/tx_thread_context_restore.s | 14 +- .../iar/src/tx_thread_context_save.s | 14 +- .../iar/src/tx_thread_interrupt_control.s | 14 +- .../iar/src/tx_thread_interrupt_disable.s | 14 +- .../iar/src/tx_thread_interrupt_restore.s | 14 +- ports/cortex_m23/iar/src/tx_thread_schedule.s | 22 +- .../iar/src/tx_thread_secure_stack.c | 22 +- .../iar/src/tx_thread_secure_stack_allocate.s | 14 +- .../iar/src/tx_thread_secure_stack_free.s | 14 +- .../src/tx_thread_secure_stack_initialize.s | 18 +- .../iar/src/tx_thread_stack_build.s | 16 +- .../iar/src/tx_thread_system_return.s | 14 +- ports/cortex_m23/iar/src/tx_timer_interrupt.s | 14 +- .../src/txe_thread_secure_stack_allocate.c | 21 +- .../iar/src/txe_thread_secure_stack_free.c | 21 +- .../ac5/example_build/sample_threadx.c | 46 +- .../example_build/tx_initialize_low_level.s | 12 +- ports/cortex_m3/ac5/inc/tx_port.h | 30 +- ports/cortex_m3/ac5/readme_threadx.txt | 56 +- .../ac5/src/tx_thread_context_restore.s | 16 +- .../ac5/src/tx_thread_context_save.s | 16 +- .../ac5/src/tx_thread_interrupt_control.s | 16 +- .../ac5/src/tx_thread_interrupt_disable.s | 16 +- .../ac5/src/tx_thread_interrupt_restore.s | 16 +- ports/cortex_m3/ac5/src/tx_thread_schedule.s | 18 +- .../cortex_m3/ac5/src/tx_thread_stack_build.s | 16 +- .../ac5/src/tx_thread_system_return.s | 16 +- ports/cortex_m3/ac5/src/tx_timer_interrupt.s | 19 +- .../example_build/sample_threadx/.cproject | 168 +-- .../example_build/sample_threadx/exceptions.c | 2 +- .../sample_threadx/sample_threadx.c | 46 +- .../sample_threadx/sample_threadx.scat | 2 +- .../sample_threadx/tx_initialize_low_level.S | 12 +- .../cortex_m3/ac6/example_build/tx/.cproject | 144 +-- ports/cortex_m3/ac6/inc/tx_port.h | 30 +- ports/cortex_m3/ac6/readme_threadx.txt | 60 +- ports/cortex_m3/ac6/src/tx_misra.S | 19 +- .../ac6/src/tx_thread_context_restore.S | 15 +- .../ac6/src/tx_thread_context_save.S | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 15 +- .../ac6/src/tx_thread_interrupt_disable.S | 15 +- .../ac6/src/tx_thread_interrupt_restore.S | 15 +- ports/cortex_m3/ac6/src/tx_thread_schedule.S | 17 +- .../cortex_m3/ac6/src/tx_thread_stack_build.S | 15 +- .../ac6/src/tx_thread_system_return.S | 15 +- ports/cortex_m3/ac6/src/tx_timer_interrupt.S | 18 +- .../ghs/example_build/sample_threadx.c | 46 +- .../example_build/tx_initialize_low_level.arm | 6 +- ports/cortex_m3/ghs/inc/tx_el.h | 13 +- ports/cortex_m3/ghs/inc/tx_port.h | 18 +- ports/cortex_m3/ghs/readme_threadx.txt | 86 +- ports/cortex_m3/ghs/src/tx_el.c | 641 ++++++----- ports/cortex_m3/ghs/src/tx_ghs.c | 2 +- .../ghs/src/tx_thread_context_restore.arm | 6 +- .../ghs/src/tx_thread_context_save.arm | 6 +- .../ghs/src/tx_thread_interrupt_control.arm | 6 +- .../ghs/src/tx_thread_interrupt_disable.arm | 6 +- .../ghs/src/tx_thread_interrupt_restore.arm | 6 +- .../cortex_m3/ghs/src/tx_thread_schedule.arm | 6 +- .../ghs/src/tx_thread_stack_build.arm | 6 +- .../ghs/src/tx_thread_system_return.arm | 6 +- .../cortex_m3/ghs/src/tx_timer_interrupt.arm | 6 +- .../gnu/example_build/cortexm3_crt0.S | 3 +- .../gnu/example_build/cortexm3_vectors.S | 12 +- .../gnu/example_build/sample_threadx.c | 46 +- .../gnu/example_build/sample_threadx.ld | 10 +- .../example_build/tx_initialize_low_level.S | 17 +- ports/cortex_m3/gnu/inc/tx_port.h | 30 +- ports/cortex_m3/gnu/readme_threadx.txt | 68 +- ports/cortex_m3/gnu/src/tx_misra.S | 19 +- .../gnu/src/tx_thread_context_restore.S | 15 +- .../gnu/src/tx_thread_context_save.S | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 15 +- .../gnu/src/tx_thread_interrupt_disable.S | 15 +- .../gnu/src/tx_thread_interrupt_restore.S | 15 +- ports/cortex_m3/gnu/src/tx_thread_schedule.S | 19 +- .../cortex_m3/gnu/src/tx_thread_stack_build.S | 15 +- .../gnu/src/tx_thread_system_return.S | 15 +- ports/cortex_m3/gnu/src/tx_timer_interrupt.S | 18 +- ports/cortex_m3/iar/CMakeLists.txt | 2 +- .../cortex_m3/iar/example_build/cstartup_M.s | 8 +- .../iar/example_build/sample_threadx.c | 48 +- .../example_build/tx_initialize_low_level.s | 12 +- ports/cortex_m3/iar/inc/tx_port.h | 30 +- ports/cortex_m3/iar/readme_threadx.txt | 60 +- ports/cortex_m3/iar/src/tx_iar.c | 235 ++-- ports/cortex_m3/iar/src/tx_misra.s | 23 +- .../iar/src/tx_thread_context_restore.s | 16 +- .../iar/src/tx_thread_context_save.s | 16 +- .../iar/src/tx_thread_interrupt_control.s | 16 +- .../iar/src/tx_thread_interrupt_disable.s | 16 +- .../iar/src/tx_thread_interrupt_restore.s | 16 +- ports/cortex_m3/iar/src/tx_thread_schedule.s | 18 +- .../cortex_m3/iar/src/tx_thread_stack_build.s | 16 +- .../iar/src/tx_thread_system_return.s | 16 +- ports/cortex_m3/iar/src/tx_timer_interrupt.s | 19 +- .../keil/example_build/sample_threadx.c | 34 +- .../example_build/tx_initialize_low_level.s | 12 +- ports/cortex_m3/keil/inc/tx_port.h | 30 +- ports/cortex_m3/keil/readme_threadx.txt | 62 +- .../keil/src/tx_thread_context_restore.s | 12 +- .../keil/src/tx_thread_context_save.s | 12 +- .../keil/src/tx_thread_interrupt_control.s | 12 +- .../keil/src/tx_thread_interrupt_disable.s | 12 +- .../keil/src/tx_thread_interrupt_restore.s | 12 +- ports/cortex_m3/keil/src/tx_thread_schedule.s | 15 +- .../keil/src/tx_thread_stack_build.s | 12 +- .../keil/src/tx_thread_system_return.s | 12 +- ports/cortex_m3/keil/src/tx_timer_interrupt.s | 12 +- .../ARMCM33_DSP_FP_TZ_config.txt | 2 +- .../_ThreadX_Library_Project/RTE_Components.h | 6 +- .../demo_secure_zone/Abstract.txt | 8 +- .../Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c | 2 +- .../_FVP_Simulation_Model/RTE_Components.h | 6 +- .../demo_secure_zone/interface.c | 10 +- .../example_build/demo_secure_zone/main_ns.c | 2 +- .../example_build/demo_secure_zone/main_s.c | 18 +- .../demo_secure_zone/tz_context.c | 2 +- .../RTE/CMSIS/RTX_Config.c | 6 +- .../RTE/CMSIS/RTX_Config.h | 220 ++-- .../_FVP_Simulation_Model/RTE_Components.h | 6 +- .../_ThreadX_Library_Project/RTE_Components.h | 6 +- .../demo_threadx.c | 68 +- .../example_build/tx_initialize_low_level.S | 13 +- ports/cortex_m33/ac6/inc/tx_port.h | 42 +- .../cortex_m33/ac6/inc/tx_secure_interface.h | 13 +- ports/cortex_m33/ac6/readme_threadx.txt | 58 +- .../ac6/src/tx_initialize_low_level.S | 15 +- ports/cortex_m33/ac6/src/tx_misra.S | 19 +- .../ac6/src/tx_thread_context_restore.S | 15 +- .../ac6/src/tx_thread_context_save.S | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 15 +- .../ac6/src/tx_thread_interrupt_disable.S | 15 +- .../ac6/src/tx_thread_interrupt_restore.S | 15 +- ports/cortex_m33/ac6/src/tx_thread_schedule.S | 26 +- .../ac6/src/tx_thread_secure_stack.c | 22 +- .../ac6/src/tx_thread_secure_stack_allocate.S | 15 +- .../ac6/src/tx_thread_secure_stack_free.S | 15 +- .../src/tx_thread_secure_stack_initialize.S | 19 +- .../ac6/src/tx_thread_stack_build.S | 15 +- .../ac6/src/tx_thread_system_return.S | 15 +- ports/cortex_m33/ac6/src/tx_timer_interrupt.S | 15 +- .../src/txe_thread_secure_stack_allocate.c | 21 +- .../ac6/src/txe_thread_secure_stack_free.c | 21 +- ports/cortex_m33/gnu/inc/tx_port.h | 42 +- .../cortex_m33/gnu/inc/tx_secure_interface.h | 13 +- ports/cortex_m33/gnu/readme_threadx.txt | 50 +- .../gnu/src/tx_initialize_low_level.S | 17 +- ports/cortex_m33/gnu/src/tx_misra.S | 19 +- .../gnu/src/tx_thread_context_restore.S | 15 +- .../gnu/src/tx_thread_context_save.S | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 15 +- .../gnu/src/tx_thread_interrupt_disable.S | 15 +- .../gnu/src/tx_thread_interrupt_restore.S | 15 +- ports/cortex_m33/gnu/src/tx_thread_schedule.S | 27 +- .../gnu/src/tx_thread_secure_stack.c | 22 +- .../gnu/src/tx_thread_secure_stack_allocate.S | 15 +- .../gnu/src/tx_thread_secure_stack_free.S | 15 +- .../src/tx_thread_secure_stack_initialize.S | 19 +- .../gnu/src/tx_thread_stack_build.S | 15 +- .../gnu/src/tx_thread_system_return.S | 15 +- ports/cortex_m33/gnu/src/tx_timer_interrupt.S | 15 +- .../src/txe_thread_secure_stack_allocate.c | 21 +- .../gnu/src/txe_thread_secure_stack_free.c | 21 +- ports/cortex_m33/iar/inc/tx_port.h | 42 +- .../cortex_m33/iar/inc/tx_secure_interface.h | 13 +- ports/cortex_m33/iar/readme_threadx.txt | 50 +- ports/cortex_m33/iar/src/tx_iar.c | 235 ++-- .../iar/src/tx_initialize_low_level.s | 14 +- ports/cortex_m33/iar/src/tx_misra.s | 23 +- .../iar/src/tx_thread_context_restore.s | 14 +- .../iar/src/tx_thread_context_save.s | 14 +- .../iar/src/tx_thread_interrupt_control.s | 14 +- .../iar/src/tx_thread_interrupt_disable.s | 14 +- .../iar/src/tx_thread_interrupt_restore.s | 14 +- ports/cortex_m33/iar/src/tx_thread_schedule.s | 26 +- .../iar/src/tx_thread_secure_stack.c | 21 +- .../iar/src/tx_thread_secure_stack_allocate.s | 14 +- .../iar/src/tx_thread_secure_stack_free.s | 14 +- .../src/tx_thread_secure_stack_initialize.s | 18 +- .../iar/src/tx_thread_stack_build.s | 14 +- .../iar/src/tx_thread_system_return.s | 14 +- ports/cortex_m33/iar/src/tx_timer_interrupt.s | 14 +- .../src/txe_thread_secure_stack_allocate.c | 21 +- .../iar/src/txe_thread_secure_stack_free.c | 21 +- .../ac5/example_build/sample_threadx.c | 46 +- .../example_build/tx_initialize_low_level.s | 6 - ports/cortex_m4/ac5/inc/tx_port.h | 30 +- ports/cortex_m4/ac5/readme_threadx.txt | 56 +- .../ac5/src/tx_thread_context_restore.s | 16 +- .../ac5/src/tx_thread_context_save.s | 16 +- .../ac5/src/tx_thread_interrupt_control.s | 16 +- .../ac5/src/tx_thread_interrupt_disable.s | 16 +- .../ac5/src/tx_thread_interrupt_restore.s | 16 +- ports/cortex_m4/ac5/src/tx_thread_schedule.s | 18 +- .../cortex_m4/ac5/src/tx_thread_stack_build.s | 16 +- .../ac5/src/tx_thread_system_return.s | 16 +- ports/cortex_m4/ac5/src/tx_timer_interrupt.s | 19 +- .../example_build/sample_threadx/.cproject | 168 +-- .../example_build/sample_threadx/exceptions.c | 2 +- .../sample_threadx/sample_threadx.c | 46 +- .../sample_threadx/sample_threadx.scat | 2 +- .../sample_threadx/tx_initialize_low_level.S | 12 +- .../cortex_m4/ac6/example_build/tx/.cproject | 144 +-- ports/cortex_m4/ac6/inc/tx_port.h | 30 +- ports/cortex_m4/ac6/readme_threadx.txt | 60 +- ports/cortex_m4/ac6/src/tx_misra.S | 19 +- .../ac6/src/tx_thread_context_restore.S | 15 +- .../ac6/src/tx_thread_context_save.S | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 15 +- .../ac6/src/tx_thread_interrupt_disable.S | 15 +- .../ac6/src/tx_thread_interrupt_restore.S | 15 +- ports/cortex_m4/ac6/src/tx_thread_schedule.S | 17 +- .../cortex_m4/ac6/src/tx_thread_stack_build.S | 15 +- .../ac6/src/tx_thread_system_return.S | 15 +- ports/cortex_m4/ac6/src/tx_timer_interrupt.S | 18 +- .../ghs/example_build/sample_threadx.c | 46 +- .../example_build/tx_initialize_low_level.arm | 90 +- ports/cortex_m4/ghs/inc/tx_el.h | 49 +- ports/cortex_m4/ghs/inc/tx_port.h | 74 +- ports/cortex_m4/ghs/readme_threadx.txt | 86 +- ports/cortex_m4/ghs/src/tx_el.c | 641 ++++++----- ports/cortex_m4/ghs/src/tx_ghs.c | 2 +- .../ghs/src/tx_thread_context_restore.arm | 6 +- .../ghs/src/tx_thread_context_save.arm | 6 +- .../ghs/src/tx_thread_interrupt_control.arm | 6 +- .../ghs/src/tx_thread_interrupt_disable.arm | 8 +- .../ghs/src/tx_thread_interrupt_restore.arm | 8 +- .../cortex_m4/ghs/src/tx_thread_schedule.arm | 30 +- .../ghs/src/tx_thread_stack_build.arm | 6 +- .../ghs/src/tx_thread_system_return.arm | 8 +- .../cortex_m4/ghs/src/tx_timer_interrupt.arm | 12 +- .../gnu/example_build/cortexm4_crt0.S | 5 +- .../gnu/example_build/cortexm4_vectors.S | 12 +- .../gnu/example_build/sample_threadx.c | 46 +- .../gnu/example_build/sample_threadx.ld | 10 +- .../example_build/tx_initialize_low_level.S | 16 +- ports/cortex_m4/gnu/inc/tx_port.h | 30 +- ports/cortex_m4/gnu/readme_threadx.txt | 68 +- ports/cortex_m4/gnu/src/tx_misra.S | 19 +- .../gnu/src/tx_thread_context_restore.S | 15 +- .../gnu/src/tx_thread_context_save.S | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 15 +- .../gnu/src/tx_thread_interrupt_disable.S | 15 +- .../gnu/src/tx_thread_interrupt_restore.S | 15 +- ports/cortex_m4/gnu/src/tx_thread_schedule.S | 19 +- .../cortex_m4/gnu/src/tx_thread_stack_build.S | 15 +- .../gnu/src/tx_thread_system_return.S | 15 +- ports/cortex_m4/gnu/src/tx_timer_interrupt.S | 18 +- ports/cortex_m4/iar/CMakeLists.txt | 2 +- .../cortex_m4/iar/example_build/cstartup_M.s | 8 +- .../iar/example_build/sample_threadx.c | 48 +- .../example_build/tx_initialize_low_level.s | 12 +- ports/cortex_m4/iar/inc/tx_port.h | 30 +- ports/cortex_m4/iar/readme_threadx.txt | 60 +- ports/cortex_m4/iar/src/tx_iar.c | 235 ++-- ports/cortex_m4/iar/src/tx_misra.s | 23 +- .../iar/src/tx_thread_context_restore.s | 16 +- .../iar/src/tx_thread_context_save.s | 16 +- .../iar/src/tx_thread_interrupt_control.s | 16 +- .../iar/src/tx_thread_interrupt_disable.s | 16 +- .../iar/src/tx_thread_interrupt_restore.s | 16 +- ports/cortex_m4/iar/src/tx_thread_schedule.s | 18 +- .../cortex_m4/iar/src/tx_thread_stack_build.s | 16 +- .../iar/src/tx_thread_system_return.s | 16 +- ports/cortex_m4/iar/src/tx_timer_interrupt.s | 19 +- .../keil/example_build/demo_threadx.c | 34 +- .../example_build/tx_initialize_low_level.s | 12 +- ports/cortex_m4/keil/inc/tx_port.h | 30 +- ports/cortex_m4/keil/readme_threadx.txt | 64 +- .../keil/src/tx_thread_context_restore.s | 12 +- .../keil/src/tx_thread_context_save.s | 12 +- .../keil/src/tx_thread_interrupt_control.s | 12 +- .../keil/src/tx_thread_interrupt_disable.s | 12 +- .../keil/src/tx_thread_interrupt_restore.s | 12 +- ports/cortex_m4/keil/src/tx_thread_schedule.s | 15 +- .../keil/src/tx_thread_stack_build.s | 12 +- .../keil/src/tx_thread_system_return.s | 12 +- ports/cortex_m4/keil/src/tx_timer_interrupt.s | 12 +- .../_ThreadX_Library_Project/RTE_Components.h | 6 +- .../Device/SSE-300-MPS3/system_SSE300MPS3.c | 8 +- .../_FVP_Simulation_Model/RTE_Components.h | 6 +- .../demo_secure_zone/interface.c | 10 +- .../example_build/demo_secure_zone/main_s.c | 18 +- .../demo_secure_zone/tz_context.c | 2 +- .../_FVP_Simulation_Model/RTE_Components.h | 6 +- .../demo_threadx.c | 68 +- .../example_build/tx_initialize_low_level.S | 13 +- ports/cortex_m55/ac6/inc/tx_port.h | 42 +- .../cortex_m55/ac6/inc/tx_secure_interface.h | 13 +- ports/cortex_m55/ac6/readme_threadx.txt | 58 +- .../ac6/src/tx_initialize_low_level.S | 15 +- ports/cortex_m55/ac6/src/tx_misra.S | 19 +- .../ac6/src/tx_thread_context_restore.S | 15 +- .../ac6/src/tx_thread_context_save.S | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 15 +- .../ac6/src/tx_thread_interrupt_disable.S | 15 +- .../ac6/src/tx_thread_interrupt_restore.S | 15 +- ports/cortex_m55/ac6/src/tx_thread_schedule.S | 26 +- .../ac6/src/tx_thread_secure_stack.c | 22 +- .../ac6/src/tx_thread_secure_stack_allocate.S | 15 +- .../ac6/src/tx_thread_secure_stack_free.S | 15 +- .../src/tx_thread_secure_stack_initialize.S | 19 +- .../ac6/src/tx_thread_stack_build.S | 15 +- .../ac6/src/tx_thread_system_return.S | 15 +- ports/cortex_m55/ac6/src/tx_timer_interrupt.S | 15 +- .../src/txe_thread_secure_stack_allocate.c | 21 +- .../ac6/src/txe_thread_secure_stack_free.c | 21 +- ports/cortex_m55/gnu/inc/tx_port.h | 42 +- .../cortex_m55/gnu/inc/tx_secure_interface.h | 13 +- ports/cortex_m55/gnu/readme_threadx.txt | 50 +- .../gnu/src/tx_initialize_low_level.S | 17 +- ports/cortex_m55/gnu/src/tx_misra.S | 19 +- .../gnu/src/tx_thread_context_restore.S | 15 +- .../gnu/src/tx_thread_context_save.S | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 15 +- .../gnu/src/tx_thread_interrupt_disable.S | 15 +- .../gnu/src/tx_thread_interrupt_restore.S | 15 +- ports/cortex_m55/gnu/src/tx_thread_schedule.S | 27 +- .../gnu/src/tx_thread_secure_stack.c | 22 +- .../gnu/src/tx_thread_secure_stack_allocate.S | 15 +- .../gnu/src/tx_thread_secure_stack_free.S | 15 +- .../src/tx_thread_secure_stack_initialize.S | 19 +- .../gnu/src/tx_thread_stack_build.S | 15 +- .../gnu/src/tx_thread_system_return.S | 15 +- ports/cortex_m55/gnu/src/tx_timer_interrupt.S | 15 +- .../src/txe_thread_secure_stack_allocate.c | 21 +- .../gnu/src/txe_thread_secure_stack_free.c | 21 +- ports/cortex_m55/iar/inc/tx_port.h | 42 +- .../cortex_m55/iar/inc/tx_secure_interface.h | 13 +- ports/cortex_m55/iar/readme_threadx.txt | 50 +- ports/cortex_m55/iar/src/tx_iar.c | 235 ++-- .../iar/src/tx_initialize_low_level.s | 14 +- ports/cortex_m55/iar/src/tx_misra.s | 23 +- .../iar/src/tx_thread_context_restore.s | 14 +- .../iar/src/tx_thread_context_save.s | 14 +- .../iar/src/tx_thread_interrupt_control.s | 14 +- .../iar/src/tx_thread_interrupt_disable.s | 14 +- .../iar/src/tx_thread_interrupt_restore.s | 14 +- ports/cortex_m55/iar/src/tx_thread_schedule.s | 26 +- .../iar/src/tx_thread_secure_stack.c | 21 +- .../iar/src/tx_thread_secure_stack_allocate.s | 14 +- .../iar/src/tx_thread_secure_stack_free.s | 14 +- .../src/tx_thread_secure_stack_initialize.s | 18 +- .../iar/src/tx_thread_stack_build.s | 14 +- .../iar/src/tx_thread_system_return.s | 14 +- ports/cortex_m55/iar/src/tx_timer_interrupt.s | 14 +- .../src/txe_thread_secure_stack_allocate.c | 21 +- .../iar/src/txe_thread_secure_stack_free.c | 21 +- .../ac5/example_build/sample_threadx.c | 46 +- .../example_build/tx_initialize_low_level.s | 12 +- ports/cortex_m7/ac5/inc/tx_port.h | 30 +- ports/cortex_m7/ac5/readme_threadx.txt | 56 +- .../ac5/src/tx_thread_context_restore.s | 16 +- .../ac5/src/tx_thread_context_save.s | 16 +- .../ac5/src/tx_thread_interrupt_control.s | 16 +- .../ac5/src/tx_thread_interrupt_disable.s | 16 +- .../ac5/src/tx_thread_interrupt_restore.s | 16 +- ports/cortex_m7/ac5/src/tx_thread_schedule.s | 18 +- .../cortex_m7/ac5/src/tx_thread_stack_build.s | 16 +- .../ac5/src/tx_thread_system_return.s | 16 +- ports/cortex_m7/ac5/src/tx_timer_interrupt.s | 19 +- .../example_build/sample_threadx/.cproject | 168 +-- .../example_build/sample_threadx/exceptions.c | 2 +- .../sample_threadx/sample_threadx.c | 46 +- .../sample_threadx/sample_threadx.scat | 2 +- .../sample_threadx/tx_initialize_low_level.S | 12 +- .../cortex_m7/ac6/example_build/tx/.cproject | 144 +-- ports/cortex_m7/ac6/inc/tx_port.h | 30 +- ports/cortex_m7/ac6/readme_threadx.txt | 60 +- ports/cortex_m7/ac6/src/tx_misra.S | 19 +- .../ac6/src/tx_thread_context_restore.S | 15 +- .../ac6/src/tx_thread_context_save.S | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 15 +- .../ac6/src/tx_thread_interrupt_disable.S | 15 +- .../ac6/src/tx_thread_interrupt_restore.S | 15 +- ports/cortex_m7/ac6/src/tx_thread_schedule.S | 17 +- .../cortex_m7/ac6/src/tx_thread_stack_build.S | 15 +- .../ac6/src/tx_thread_system_return.S | 15 +- ports/cortex_m7/ac6/src/tx_timer_interrupt.S | 18 +- .../ghs/example_build/sample_threadx.c | 46 +- .../example_build/tx_initialize_low_level.arm | 90 +- ports/cortex_m7/ghs/inc/tx_el.h | 49 +- ports/cortex_m7/ghs/inc/tx_port.h | 74 +- ports/cortex_m7/ghs/readme_threadx.txt | 86 +- ports/cortex_m7/ghs/src/tx_el.c | 641 ++++++----- ports/cortex_m7/ghs/src/tx_ghs.c | 2 +- .../ghs/src/tx_thread_context_restore.arm | 6 +- .../ghs/src/tx_thread_context_save.arm | 6 +- .../ghs/src/tx_thread_interrupt_control.arm | 6 +- .../ghs/src/tx_thread_interrupt_disable.arm | 8 +- .../ghs/src/tx_thread_interrupt_restore.arm | 8 +- .../cortex_m7/ghs/src/tx_thread_schedule.arm | 30 +- .../ghs/src/tx_thread_stack_build.arm | 6 +- .../ghs/src/tx_thread_system_return.arm | 8 +- .../cortex_m7/ghs/src/tx_timer_interrupt.arm | 12 +- .../gnu/example_build/cortexm7_crt0.S | 3 +- .../gnu/example_build/cortexm7_vectors.S | 12 +- .../gnu/example_build/sample_threadx.c | 46 +- .../gnu/example_build/sample_threadx.ld | 10 +- .../example_build/tx_initialize_low_level.S | 17 +- ports/cortex_m7/gnu/inc/tx_port.h | 30 +- ports/cortex_m7/gnu/readme_threadx.txt | 68 +- ports/cortex_m7/gnu/src/tx_misra.S | 19 +- .../gnu/src/tx_thread_context_restore.S | 15 +- .../gnu/src/tx_thread_context_save.S | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 15 +- .../gnu/src/tx_thread_interrupt_disable.S | 15 +- .../gnu/src/tx_thread_interrupt_restore.S | 15 +- ports/cortex_m7/gnu/src/tx_thread_schedule.S | 19 +- .../cortex_m7/gnu/src/tx_thread_stack_build.S | 15 +- .../gnu/src/tx_thread_system_return.S | 15 +- ports/cortex_m7/gnu/src/tx_timer_interrupt.S | 18 +- ports/cortex_m7/iar/CMakeLists.txt | 2 +- .../cortex_m7/iar/example_build/cstartup_M.s | 8 +- .../iar/example_build/sample_threadx.c | 48 +- .../example_build/tx_initialize_low_level.s | 12 +- ports/cortex_m7/iar/inc/tx_port.h | 30 +- ports/cortex_m7/iar/readme_threadx.txt | 60 +- ports/cortex_m7/iar/src/tx_iar.c | 235 ++-- ports/cortex_m7/iar/src/tx_misra.s | 23 +- .../iar/src/tx_thread_context_restore.s | 16 +- .../iar/src/tx_thread_context_save.s | 16 +- .../iar/src/tx_thread_interrupt_control.s | 16 +- .../iar/src/tx_thread_interrupt_disable.s | 16 +- .../iar/src/tx_thread_interrupt_restore.s | 16 +- ports/cortex_m7/iar/src/tx_thread_schedule.s | 18 +- .../cortex_m7/iar/src/tx_thread_stack_build.s | 16 +- .../iar/src/tx_thread_system_return.s | 16 +- ports/cortex_m7/iar/src/tx_timer_interrupt.s | 19 +- ports/cortex_m85/ac6/inc/tx_port.h | 42 +- .../cortex_m85/ac6/inc/tx_secure_interface.h | 13 +- ports/cortex_m85/ac6/readme_threadx.txt | 58 +- .../ac6/src/tx_initialize_low_level.S | 15 +- ports/cortex_m85/ac6/src/tx_misra.S | 19 +- .../ac6/src/tx_thread_context_restore.S | 15 +- .../ac6/src/tx_thread_context_save.S | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 15 +- .../ac6/src/tx_thread_interrupt_disable.S | 15 +- .../ac6/src/tx_thread_interrupt_restore.S | 15 +- ports/cortex_m85/ac6/src/tx_thread_schedule.S | 26 +- .../ac6/src/tx_thread_secure_stack.c | 22 +- .../ac6/src/tx_thread_secure_stack_allocate.S | 15 +- .../ac6/src/tx_thread_secure_stack_free.S | 15 +- .../src/tx_thread_secure_stack_initialize.S | 19 +- .../ac6/src/tx_thread_stack_build.S | 15 +- .../ac6/src/tx_thread_system_return.S | 15 +- ports/cortex_m85/ac6/src/tx_timer_interrupt.S | 15 +- .../src/txe_thread_secure_stack_allocate.c | 21 +- .../ac6/src/txe_thread_secure_stack_free.c | 21 +- ports/cortex_m85/gnu/inc/tx_port.h | 42 +- .../cortex_m85/gnu/inc/tx_secure_interface.h | 13 +- ports/cortex_m85/gnu/readme_threadx.txt | 50 +- .../gnu/src/tx_initialize_low_level.S | 17 +- ports/cortex_m85/gnu/src/tx_misra.S | 19 +- .../gnu/src/tx_thread_context_restore.S | 15 +- .../gnu/src/tx_thread_context_save.S | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 15 +- .../gnu/src/tx_thread_interrupt_disable.S | 15 +- .../gnu/src/tx_thread_interrupt_restore.S | 15 +- ports/cortex_m85/gnu/src/tx_thread_schedule.S | 27 +- .../gnu/src/tx_thread_secure_stack.c | 22 +- .../gnu/src/tx_thread_secure_stack_allocate.S | 15 +- .../gnu/src/tx_thread_secure_stack_free.S | 15 +- .../src/tx_thread_secure_stack_initialize.S | 19 +- .../gnu/src/tx_thread_stack_build.S | 15 +- .../gnu/src/tx_thread_system_return.S | 15 +- ports/cortex_m85/gnu/src/tx_timer_interrupt.S | 15 +- .../src/txe_thread_secure_stack_allocate.c | 21 +- .../gnu/src/txe_thread_secure_stack_free.c | 21 +- ports/cortex_m85/iar/inc/tx_port.h | 42 +- .../cortex_m85/iar/inc/tx_secure_interface.h | 13 +- ports/cortex_m85/iar/readme_threadx.txt | 50 +- ports/cortex_m85/iar/src/tx_iar.c | 235 ++-- .../iar/src/tx_initialize_low_level.s | 14 +- ports/cortex_m85/iar/src/tx_misra.s | 23 +- .../iar/src/tx_thread_context_restore.s | 14 +- .../iar/src/tx_thread_context_save.s | 14 +- .../iar/src/tx_thread_interrupt_control.s | 14 +- .../iar/src/tx_thread_interrupt_disable.s | 14 +- .../iar/src/tx_thread_interrupt_restore.s | 14 +- ports/cortex_m85/iar/src/tx_thread_schedule.s | 26 +- .../iar/src/tx_thread_secure_stack.c | 21 +- .../iar/src/tx_thread_secure_stack_allocate.s | 14 +- .../iar/src/tx_thread_secure_stack_free.s | 14 +- .../src/tx_thread_secure_stack_initialize.s | 18 +- .../iar/src/tx_thread_stack_build.s | 14 +- .../iar/src/tx_thread_system_return.s | 14 +- ports/cortex_m85/iar/src/tx_timer_interrupt.s | 14 +- .../src/txe_thread_secure_stack_allocate.c | 21 +- .../iar/src/txe_thread_secure_stack_free.c | 21 +- .../ac5/example_build/sample_threadx.c | 46 +- .../example_build/tx_initialize_low_level.s | 112 +- ports/cortex_r4/ac5/inc/tx_port.h | 96 +- ports/cortex_r4/ac5/readme_threadx.txt | 334 +++--- .../ac5/src/tx_thread_context_restore.s | 70 +- .../ac5/src/tx_thread_context_save.s | 80 +- .../ac5/src/tx_thread_fiq_context_restore.s | 78 +- .../ac5/src/tx_thread_fiq_context_save.s | 102 +- .../ac5/src/tx_thread_fiq_nesting_end.s | 84 +- .../ac5/src/tx_thread_fiq_nesting_start.s | 74 +- .../ac5/src/tx_thread_interrupt_control.s | 62 +- .../ac5/src/tx_thread_interrupt_disable.s | 62 +- .../ac5/src/tx_thread_interrupt_restore.s | 58 +- .../ac5/src/tx_thread_irq_nesting_end.s | 84 +- .../ac5/src/tx_thread_irq_nesting_start.s | 74 +- ports/cortex_r4/ac5/src/tx_thread_schedule.s | 74 +- .../cortex_r4/ac5/src/tx_thread_stack_build.s | 62 +- .../ac5/src/tx_thread_system_return.s | 70 +- .../ac5/src/tx_thread_vectored_context_save.s | 70 +- ports/cortex_r4/ac5/src/tx_timer_interrupt.s | 76 +- .../example_build/sample_threadx/.cproject | 156 +-- .../sample_threadx/sample_threadx.c | 36 +- .../sample_threadx/sample_threadx.scat | 12 +- .../example_build/sample_threadx/startup.S | 4 +- .../cortex_r4/ac6/example_build/tx/.cproject | 160 +-- ports/cortex_r4/ac6/inc/tx_port.h | 96 +- ports/cortex_r4/ac6/readme_threadx.txt | 140 +-- .../ac6/src/tx_initialize_low_level.S | 13 +- .../ac6/src/tx_thread_context_restore.S | 21 +- .../ac6/src/tx_thread_context_save.S | 13 +- .../ac6/src/tx_thread_fiq_context_restore.S | 19 +- .../ac6/src/tx_thread_fiq_context_save.S | 15 +- .../ac6/src/tx_thread_fiq_nesting_end.S | 17 +- .../ac6/src/tx_thread_fiq_nesting_start.S | 13 +- .../ac6/src/tx_thread_interrupt_control.S | 13 +- .../ac6/src/tx_thread_interrupt_disable.S | 13 +- .../ac6/src/tx_thread_interrupt_restore.S | 13 +- .../ac6/src/tx_thread_irq_nesting_end.S | 15 +- .../ac6/src/tx_thread_irq_nesting_start.S | 13 +- ports/cortex_r4/ac6/src/tx_thread_schedule.S | 13 +- .../cortex_r4/ac6/src/tx_thread_stack_build.S | 13 +- .../ac6/src/tx_thread_system_return.S | 13 +- .../ac6/src/tx_thread_vectored_context_save.S | 13 +- ports/cortex_r4/ac6/src/tx_timer_interrupt.S | 13 +- .../example_build/tx_initialize_low_level.arm | 6 +- ports/cortex_r4/ghs/inc/tx_el.h | 13 +- ports/cortex_r4/ghs/inc/tx_port.h | 18 +- ports/cortex_r4/ghs/readme_threadx.txt | 314 ++--- ports/cortex_r4/ghs/src/tx_el.c | 13 +- .../ghs/src/tx_thread_context_restore.arm | 6 +- .../ghs/src/tx_thread_context_save.arm | 6 +- .../ghs/src/tx_thread_fiq_context_restore.arm | 6 +- .../ghs/src/tx_thread_fiq_context_save.arm | 6 +- .../ghs/src/tx_thread_fiq_nesting_end.arm | 6 +- .../ghs/src/tx_thread_fiq_nesting_start.arm | 6 +- .../ghs/src/tx_thread_interrupt_control.arm | 6 +- .../ghs/src/tx_thread_interrupt_disable.arm | 6 +- .../ghs/src/tx_thread_interrupt_restore.arm | 6 +- .../ghs/src/tx_thread_irq_nesting_end.arm | 6 +- .../ghs/src/tx_thread_irq_nesting_start.arm | 6 +- .../cortex_r4/ghs/src/tx_thread_schedule.arm | 6 +- .../ghs/src/tx_thread_stack_build.arm | 6 +- .../ghs/src/tx_thread_system_return.arm | 6 +- .../src/tx_thread_vectored_context_save.arm | 6 +- .../cortex_r4/ghs/src/tx_timer_interrupt.arm | 6 +- ports/cortex_r4/gnu/example_build/crt0.S | 20 +- ports/cortex_r4/gnu/example_build/reset.S | 16 +- .../gnu/example_build/sample_threadx.c | 46 +- .../gnu/example_build/sample_threadx.ld | 14 +- .../example_build/tx_initialize_low_level.S | 114 +- ports/cortex_r4/gnu/inc/tx_port.h | 99 +- ports/cortex_r4/gnu/readme_threadx.txt | 312 ++--- .../gnu/src/tx_thread_context_restore.S | 72 +- .../gnu/src/tx_thread_context_save.S | 82 +- .../gnu/src/tx_thread_fiq_context_restore.S | 74 +- .../gnu/src/tx_thread_fiq_context_save.S | 102 +- .../gnu/src/tx_thread_fiq_nesting_end.S | 84 +- .../gnu/src/tx_thread_fiq_nesting_start.S | 74 +- .../gnu/src/tx_thread_interrupt_control.S | 64 +- .../gnu/src/tx_thread_interrupt_disable.S | 64 +- .../gnu/src/tx_thread_interrupt_restore.S | 60 +- .../gnu/src/tx_thread_irq_nesting_end.S | 84 +- .../gnu/src/tx_thread_irq_nesting_start.S | 74 +- ports/cortex_r4/gnu/src/tx_thread_schedule.S | 76 +- .../cortex_r4/gnu/src/tx_thread_stack_build.S | 64 +- .../gnu/src/tx_thread_system_return.S | 70 +- .../gnu/src/tx_thread_vectored_context_save.S | 70 +- ports/cortex_r4/gnu/src/tx_timer_interrupt.S | 76 +- .../iar/example_build/sample_threadx.c | 48 +- .../example_build/tx_initialize_low_level.s | 116 +- ports/cortex_r4/iar/inc/tx_port.h | 104 +- ports/cortex_r4/iar/readme_threadx.txt | 288 ++--- ports/cortex_r4/iar/src/tx_iar.c | 239 ++-- .../iar/src/tx_thread_context_restore.s | 90 +- .../iar/src/tx_thread_context_save.s | 94 +- .../iar/src/tx_thread_interrupt_control.s | 78 +- .../iar/src/tx_thread_interrupt_disable.s | 74 +- .../iar/src/tx_thread_interrupt_restore.s | 76 +- .../iar/src/tx_thread_irq_nesting_end.s | 94 +- .../iar/src/tx_thread_irq_nesting_start.s | 88 +- ports/cortex_r4/iar/src/tx_thread_schedule.s | 92 +- .../cortex_r4/iar/src/tx_thread_stack_build.s | 86 +- .../iar/src/tx_thread_system_return.s | 82 +- .../iar/src/tx_thread_vectored_context_save.s | 82 +- ports/cortex_r4/iar/src/tx_timer_interrupt.s | 90 +- .../ac5/example_build/sample_threadx.c | 46 +- .../example_build/tx_initialize_low_level.s | 112 +- ports/cortex_r5/ac5/inc/tx_port.h | 98 +- ports/cortex_r5/ac5/readme_threadx.txt | 332 +++--- .../ac5/src/tx_thread_context_restore.s | 72 +- .../ac5/src/tx_thread_context_save.s | 80 +- .../ac5/src/tx_thread_fiq_context_restore.s | 78 +- .../ac5/src/tx_thread_fiq_context_save.s | 102 +- .../ac5/src/tx_thread_fiq_nesting_end.s | 84 +- .../ac5/src/tx_thread_fiq_nesting_start.s | 74 +- .../ac5/src/tx_thread_interrupt_control.s | 62 +- .../ac5/src/tx_thread_interrupt_disable.s | 62 +- .../ac5/src/tx_thread_interrupt_restore.s | 58 +- .../ac5/src/tx_thread_irq_nesting_end.s | 84 +- .../ac5/src/tx_thread_irq_nesting_start.s | 74 +- ports/cortex_r5/ac5/src/tx_thread_schedule.s | 74 +- .../cortex_r5/ac5/src/tx_thread_stack_build.s | 62 +- .../ac5/src/tx_thread_system_return.s | 70 +- .../ac5/src/tx_thread_vectored_context_save.s | 70 +- ports/cortex_r5/ac5/src/tx_timer_interrupt.s | 76 +- .../example_build/sample_threadx/.cproject | 168 +-- .../sample_threadx/sample_threadx.c | 46 +- .../sample_threadx/sample_threadx.scat | 2 +- .../example_build/sample_threadx/startup.S | 4 +- .../sample_threadx/tx_initialize_low_level.S | 112 +- .../cortex_r5/ac6/example_build/tx/.cproject | 148 +-- ports/cortex_r5/ac6/inc/tx_port.h | 99 +- ports/cortex_r5/ac6/readme_threadx.txt | 144 +-- .../ac6/src/tx_thread_context_restore.S | 72 +- .../ac6/src/tx_thread_context_save.S | 82 +- .../ac6/src/tx_thread_fiq_context_restore.S | 74 +- .../ac6/src/tx_thread_fiq_context_save.S | 102 +- .../ac6/src/tx_thread_fiq_nesting_end.S | 84 +- .../ac6/src/tx_thread_fiq_nesting_start.S | 74 +- .../ac6/src/tx_thread_interrupt_control.S | 64 +- .../ac6/src/tx_thread_interrupt_disable.S | 64 +- .../ac6/src/tx_thread_interrupt_restore.S | 60 +- .../ac6/src/tx_thread_irq_nesting_end.S | 84 +- .../ac6/src/tx_thread_irq_nesting_start.S | 74 +- ports/cortex_r5/ac6/src/tx_thread_schedule.S | 76 +- .../cortex_r5/ac6/src/tx_thread_stack_build.S | 64 +- .../ac6/src/tx_thread_system_return.S | 70 +- .../ac6/src/tx_thread_vectored_context_save.S | 70 +- ports/cortex_r5/ac6/src/tx_timer_interrupt.S | 76 +- .../example_build/tx_initialize_low_level.arm | 6 +- ports/cortex_r5/ghs/inc/tx_el.h | 13 +- ports/cortex_r5/ghs/inc/tx_port.h | 18 +- ports/cortex_r5/ghs/readme_threadx.txt | 316 ++--- ports/cortex_r5/ghs/src/tx_el.c | 13 +- .../ghs/src/tx_thread_context_restore.arm | 6 +- .../ghs/src/tx_thread_context_save.arm | 6 +- .../ghs/src/tx_thread_fiq_context_restore.arm | 6 +- .../ghs/src/tx_thread_fiq_context_save.arm | 6 +- .../ghs/src/tx_thread_fiq_nesting_end.arm | 6 +- .../ghs/src/tx_thread_fiq_nesting_start.arm | 6 +- .../ghs/src/tx_thread_interrupt_control.arm | 6 +- .../ghs/src/tx_thread_interrupt_disable.arm | 6 +- .../ghs/src/tx_thread_interrupt_restore.arm | 6 +- .../ghs/src/tx_thread_irq_nesting_end.arm | 6 +- .../ghs/src/tx_thread_irq_nesting_start.arm | 6 +- .../cortex_r5/ghs/src/tx_thread_schedule.arm | 6 +- .../ghs/src/tx_thread_stack_build.arm | 6 +- .../ghs/src/tx_thread_system_return.arm | 6 +- .../src/tx_thread_vectored_context_save.arm | 6 +- .../cortex_r5/ghs/src/tx_timer_interrupt.arm | 6 +- ports/cortex_r5/gnu/example_build/crt0.S | 20 +- ports/cortex_r5/gnu/example_build/reset.S | 16 +- .../gnu/example_build/sample_threadx.c | 46 +- .../gnu/example_build/sample_threadx.ld | 14 +- .../example_build/tx_initialize_low_level.S | 114 +- ports/cortex_r5/gnu/inc/tx_port.h | 99 +- ports/cortex_r5/gnu/readme_threadx.txt | 312 ++--- .../gnu/src/tx_thread_context_restore.S | 72 +- .../gnu/src/tx_thread_context_save.S | 82 +- .../gnu/src/tx_thread_fiq_context_restore.S | 74 +- .../gnu/src/tx_thread_fiq_context_save.S | 102 +- .../gnu/src/tx_thread_fiq_nesting_end.S | 84 +- .../gnu/src/tx_thread_fiq_nesting_start.S | 74 +- .../gnu/src/tx_thread_interrupt_control.S | 64 +- .../gnu/src/tx_thread_interrupt_disable.S | 64 +- .../gnu/src/tx_thread_interrupt_restore.S | 60 +- .../gnu/src/tx_thread_irq_nesting_end.S | 84 +- .../gnu/src/tx_thread_irq_nesting_start.S | 74 +- ports/cortex_r5/gnu/src/tx_thread_schedule.S | 76 +- .../cortex_r5/gnu/src/tx_thread_stack_build.S | 64 +- .../gnu/src/tx_thread_system_return.S | 70 +- .../gnu/src/tx_thread_vectored_context_save.S | 70 +- ports/cortex_r5/gnu/src/tx_timer_interrupt.S | 76 +- .../iar/example_build/sample_threadx.c | 48 +- .../example_build/tx_initialize_low_level.s | 116 +- ports/cortex_r5/iar/inc/tx_port.h | 104 +- ports/cortex_r5/iar/readme_threadx.txt | 288 ++--- ports/cortex_r5/iar/src/tx_iar.c | 239 ++-- .../iar/src/tx_thread_context_restore.s | 90 +- .../iar/src/tx_thread_context_save.s | 94 +- .../iar/src/tx_thread_interrupt_control.s | 78 +- .../iar/src/tx_thread_interrupt_disable.s | 74 +- .../iar/src/tx_thread_interrupt_restore.s | 76 +- .../iar/src/tx_thread_irq_nesting_end.s | 94 +- .../iar/src/tx_thread_irq_nesting_start.s | 88 +- ports/cortex_r5/iar/src/tx_thread_schedule.s | 92 +- .../cortex_r5/iar/src/tx_thread_stack_build.s | 86 +- .../iar/src/tx_thread_system_return.s | 82 +- .../iar/src/tx_thread_vectored_context_save.s | 82 +- ports/cortex_r5/iar/src/tx_timer_interrupt.s | 90 +- .../example_build/tx_initialize_low_level.arm | 6 +- ports/cortex_r7/ghs/inc/tx_el.h | 13 +- ports/cortex_r7/ghs/inc/tx_port.h | 18 +- ports/cortex_r7/ghs/readme_threadx.txt | 316 ++--- ports/cortex_r7/ghs/src/tx_el.c | 13 +- .../ghs/src/tx_thread_context_restore.arm | 6 +- .../ghs/src/tx_thread_context_save.arm | 6 +- .../ghs/src/tx_thread_fiq_context_restore.arm | 6 +- .../ghs/src/tx_thread_fiq_context_save.arm | 6 +- .../ghs/src/tx_thread_fiq_nesting_end.arm | 6 +- .../ghs/src/tx_thread_fiq_nesting_start.arm | 6 +- .../ghs/src/tx_thread_interrupt_control.arm | 6 +- .../ghs/src/tx_thread_interrupt_disable.arm | 6 +- .../ghs/src/tx_thread_interrupt_restore.arm | 6 +- .../ghs/src/tx_thread_irq_nesting_end.arm | 6 +- .../ghs/src/tx_thread_irq_nesting_start.arm | 6 +- .../cortex_r7/ghs/src/tx_thread_schedule.arm | 6 +- .../ghs/src/tx_thread_stack_build.arm | 6 +- .../ghs/src/tx_thread_system_return.arm | 6 +- .../src/tx_thread_vectored_context_save.arm | 6 +- .../cortex_r7/ghs/src/tx_timer_interrupt.arm | 6 +- ports/linux/gnu/example_build/Makefile | 6 +- .../linux/gnu/example_build/sample_threadx.c | 46 +- ports/linux/gnu/inc/tx_port.h | 50 +- ports/linux/gnu/readme_threadx.txt | 58 +- ports/linux/gnu/src/tx_initialize_low_level.c | 113 +- .../linux/gnu/src/tx_thread_context_restore.c | 81 +- ports/linux/gnu/src/tx_thread_context_save.c | 71 +- .../gnu/src/tx_thread_interrupt_control.c | 87 +- ports/linux/gnu/src/tx_thread_schedule.c | 19 +- ports/linux/gnu/src/tx_thread_stack_build.c | 75 +- ports/linux/gnu/src/tx_thread_system_return.c | 109 +- ports/linux/gnu/src/tx_timer_interrupt.c | 77 +- .../clang/example_build/qemu_virt/csr.h | 2 +- .../qemu_virt/tx_initialize_low_level.S | 5 - .../clang/example_build/qemu_virt/uart.h | 1 + ports/risc-v32/clang/inc/tx_port.h | 8 +- ports/risc-v32/clang/readme_threadx.txt | 14 +- .../clang/src/tx_initialize_low_level.S | 8 +- .../clang/src/tx_thread_context_restore.S | 12 +- .../clang/src/tx_thread_context_save.S | 6 - .../clang/src/tx_thread_interrupt_control.S | 8 +- ports/risc-v32/clang/src/tx_thread_schedule.S | 10 +- .../clang/src/tx_thread_stack_build.S | 8 +- .../clang/src/tx_thread_system_return.S | 10 +- ports/risc-v32/clang/src/tx_timer_interrupt.S | 6 - .../qemu_virt/tx_initialize_low_level.S | 5 - .../gnu/example_build/qemu_virt/uart.h | 1 + .../chip_riscv_dummy/gcc_flash_smartl.ld | 2 +- .../include/asm/riscv_asm_macro.h | 2 +- .../chip_riscv_dummy/include/asm/riscv_csr.h | 2 +- .../chip_riscv_dummy/src/sys/feature.c | 2 +- .../csi/csi2/include/core/csi_rv64_gcc.h | 4 +- .../components/csi/csi2/include/drv/gpio.h | 4 +- .../components/csi/csi2/include/drv/irq.h | 2 +- .../components/csi/csi2/include/drv/pin.h | 2 +- .../components/csi/csi2/include/syslog.h | 2 +- .../include/serf/minilibc_stdio.h | 2 +- .../xuantie_smartl_fpga/demo_threadx.c | 46 +- .../xuantie_smartl_fpga/readme_e906.txt | 2 +- .../xuantie_smartl_fpga/tx_user.h | 36 +- ports/risc-v32/gnu/inc/tx_port.h | 8 +- ports/risc-v32/gnu/readme_threadx.txt | 12 +- .../gnu/src/tx_initialize_low_level.S | 6 - .../gnu/src/tx_thread_context_restore.S | 12 +- .../risc-v32/gnu/src/tx_thread_context_save.S | 6 - .../gnu/src/tx_thread_interrupt_control.S | 6 - ports/risc-v32/gnu/src/tx_thread_schedule.S | 6 - .../risc-v32/gnu/src/tx_thread_stack_build.S | 6 - .../gnu/src/tx_thread_system_return.S | 6 - ports/risc-v32/gnu/src/tx_timer_interrupt.S | 6 - .../iar/example_build/sample_threadx.c | 48 +- ports/risc-v32/iar/inc/tx_port.h | 96 +- ports/risc-v32/iar/readme_threadx.txt | 92 +- .../iar/src/tx_initialize_low_level.s | 93 +- .../iar/src/tx_thread_context_restore.s | 102 +- .../risc-v32/iar/src/tx_thread_context_save.s | 89 +- .../iar/src/tx_thread_interrupt_control.s | 79 +- ports/risc-v32/iar/src/tx_thread_schedule.s | 96 +- .../risc-v32/iar/src/tx_thread_stack_build.s | 76 +- .../iar/src/tx_thread_system_return.s | 95 +- ports/risc-v32/iar/src/tx_timer_interrupt.s | 85 +- .../gnu/example_build/qemu_virt/board.c | 2 +- .../gnu/example_build/qemu_virt/csr.h | 3 +- .../example_build/qemu_virt/demo_threadx.c | 46 +- .../gnu/example_build/qemu_virt/link.lds | 2 +- .../gnu/example_build/qemu_virt/plic.h | 1 + .../qemu_virt/tx_initialize_low_level.S | 18 +- .../gnu/example_build/qemu_virt/uart.c | 4 +- .../gnu/example_build/qemu_virt/uart.h | 1 + ports/risc-v64/gnu/inc/tx_port.h | 9 +- ports/risc-v64/gnu/readme_threadx.txt | 8 +- .../gnu/src/tx_initialize_low_level.S | 7 +- .../gnu/src/tx_thread_context_restore.S | 7 +- .../risc-v64/gnu/src/tx_thread_context_save.S | 7 +- .../gnu/src/tx_thread_interrupt_control.S | 7 +- ports/risc-v64/gnu/src/tx_thread_schedule.S | 7 +- .../risc-v64/gnu/src/tx_thread_stack_build.S | 7 +- .../gnu/src/tx_thread_system_return.S | 7 +- ports/risc-v64/gnu/src/tx_timer_interrupt.S | 6 - ports/rxv1/ccrx/CMakeLists.txt | 2 +- ports/rxv1/ccrx/inc/tx_port.h | 64 +- ports/rxv1/ccrx/readme_threadx.txt | 70 +- .../rxv1/ccrx/src/tx_initialize_low_level.src | 10 +- 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+- ports/xtensa/xcc/example_build/demo_threadx.c | 46 +- ports/xtensa/xcc/inc/tx_api_asm.h | 12 +- ports/xtensa/xcc/inc/tx_port.h | 20 +- ports/xtensa/xcc/inc/tx_user.h | 93 +- ports/xtensa/xcc/inc/xtensa_api.h | 2 +- ports/xtensa/xcc/inc/xtensa_context.h | 24 +- ports/xtensa/xcc/inc/xtensa_rtos.h | 14 +- ports/xtensa/xcc/inc/xtensa_timer.h | 6 +- ports/xtensa/xcc/readme_threadx.txt | 140 +-- ports/xtensa/xcc/src/tx_clib_lock.c | 12 +- .../xtensa/xcc/src/tx_initialize_low_level.c | 13 +- .../xcc/src/tx_thread_context_restore.S | 12 +- ports/xtensa/xcc/src/tx_thread_context_save.S | 53 +- .../xcc/src/tx_thread_interrupt_control.c | 35 +- ports/xtensa/xcc/src/tx_thread_schedule.S | 15 +- ports/xtensa/xcc/src/tx_thread_stack_build.S | 31 +- .../xtensa/xcc/src/tx_thread_system_return.S | 14 +- ports/xtensa/xcc/src/tx_timer_interrupt.S | 50 +- .../xcc/src/tx_xtensa_stack_error_handler.c | 31 +- ports/xtensa/xcc/src/xtensa_context.S | 34 +- ports/xtensa/xcc/src/xtensa_coproc_handler.S | 14 +- ports/xtensa/xcc/src/xtensa_init.c | 8 +- ports/xtensa/xcc/src/xtensa_intr_asm.S | 6 - ports/xtensa/xcc/src/xtensa_intr_wrapper.c | 6 - ports/xtensa/xcc/src/xtensa_overlay_os_hook.c | 10 +- ports/xtensa/xcc/src/xtensa_vectors.S | 28 +- ports/xtensa/xcc/src/xtensa_vectors_xea3.S | 6 - .../ARMv7-A/threadx/common/inc/tx_port.h | 23 +- .../common/src/tx_thread_context_restore.S | 24 +- .../common/src/tx_thread_context_save.S | 24 +- .../src/tx_thread_fiq_context_restore.S | 21 +- .../common/src/tx_thread_fiq_context_save.S | 21 +- .../common/src/tx_thread_fiq_nesting_end.S | 21 +- .../common/src/tx_thread_fiq_nesting_start.S | 21 +- .../common/src/tx_thread_interrupt_control.S | 21 +- .../common/src/tx_thread_interrupt_disable.S | 21 +- .../common/src/tx_thread_interrupt_restore.S | 21 +- .../common/src/tx_thread_irq_nesting_end.S | 21 +- .../common/src/tx_thread_irq_nesting_start.S | 21 +- .../threadx/common/src/tx_thread_schedule.S | 25 +- .../common/src/tx_thread_stack_build.S | 21 +- .../common/src/tx_thread_system_return.S | 24 +- .../src/tx_thread_vectored_context_save.S | 21 +- .../threadx/common/src/tx_timer_interrupt.S | 21 +- .../example_build/tx_initialize_low_level.s | 16 +- .../example_build/sample_threadx/.cproject | 174 +-- .../sample_threadx/sample_threadx.scat | 2 +- .../sample_threadx/tx_initialize_low_level.S | 15 +- .../ports/ac6/example_build/tx/.cproject | 144 +-- .../threadx/ports/gnu/example_build/reset.S | 7 +- .../ports/gnu/example_build/sample_threadx.ld | 14 +- .../threadx/ports/gnu/example_build/v7.h | 2 +- .../threadx/ports/gnu/example_build/v7.s | 48 +- .../example_build/tx_initialize_low_level.s | 17 +- ports_arch/ARMv7-A/update.ps1 | 8 +- .../ac5/example_build/sample_threadx.c | 46 +- .../example_build/tx_initialize_low_level.s | 17 +- .../ARMv7-M/threadx/ac5/readme_threadx.txt | 56 +- .../ac5/src/tx_thread_context_restore.s | 16 +- .../threadx/ac5/src/tx_thread_context_save.s | 16 +- .../ac5/src/tx_thread_interrupt_control.s | 16 +- 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+- .../common/src/tx_thread_smp_time_get.S | 18 +- .../common/src/tx_thread_smp_unprotect.S | 22 +- .../common/src/tx_thread_stack_build.S | 18 +- .../common/src/tx_thread_system_return.S | 20 +- .../common/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 146 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.scat | 26 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../ac6/example_build/sample_threadx/v8_mmu.h | 2 +- .../ports/ac6/example_build/tx/.cproject | 186 +-- .../ports/ac6/src/tx_initialize_low_level.S | 15 +- .../example_build/sample_threadx/.cproject | 162 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.ld | 4 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../gnu/example_build/sample_threadx/v8_mmu.h | 2 +- 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4 +- .../example_build/sample_threadx/v8_system.h | 2 +- .../example_build/sample_threadx/v8_utils.S | 2 +- .../example_build/sample_threadx/vectors.S | 2 +- .../sample_threadx_module/.cproject | 218 ++-- .../sample_threadx_module.c | 42 +- .../txm_module_preamble.S | 2 +- .../sample_threadx_module_manager/.cproject | 236 ++-- .../sample_threadx_module_manager/GICv3.h | 2 +- .../GICv3_gicc.h | 2 +- .../GICv3_gicd.c | 2 +- .../GICv3_gicr.c | 2 +- .../MP_Mutexes.S | 4 +- .../MP_Mutexes.h | 2 +- .../sample_threadx_module_manager/PPM_AEM.h | 2 +- .../sample_threadx.scat | 4 +- .../sample_threadx_module_manager.c | 10 +- .../sp804_timer.c | 2 +- .../sp804_timer.h | 2 +- .../sample_threadx_module_manager/startup.S | 4 +- .../tx_initialize_low_level.S | 69 +- .../v8_aarch64.S | 2 +- .../v8_aarch64.h | 2 +- .../sample_threadx_module_manager/v8_mmu.h | 4 +- .../sample_threadx_module_manager/v8_system.h | 2 +- .../sample_threadx_module_manager/v8_utils.S | 2 +- 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.../example_build/sample_threadx/v8_utils.S | 2 +- .../example_build/sample_threadx/vectors.S | 2 +- .../sample_threadx_module/.cproject | 182 +-- .../sample_threadx_module/gcc_setup.s | 14 +- .../sample_threadx_module.c | 42 +- .../sample_threadx_module.ld | 4 +- .../txm_module_preamble.S | 2 +- .../sample_threadx_module_manager/.cproject | 262 ++--- .../sample_threadx_module_manager/GICv3.h | 2 +- .../GICv3_aliases.h | 2 +- .../GICv3_gicc.h | 2 +- .../GICv3_gicd.c | 2 +- .../GICv3_gicr.c | 2 +- .../MP_Mutexes.S | 4 +- .../MP_Mutexes.h | 2 +- .../sample_threadx_module_manager/PPM_AEM.h | 2 +- .../sample_threadx_module_manager.c | 10 +- .../sample_threadx_module_manager.ld | 2 +- .../sp804_timer.c | 2 +- .../sp804_timer.h | 2 +- .../sample_threadx_module_manager/startup.S | 4 +- .../tx_initialize_low_level.S | 69 +- .../v8_aarch64.S | 2 +- .../v8_aarch64.h | 2 +- .../sample_threadx_module_manager/v8_mmu.h | 4 +- .../sample_threadx_module_manager/v8_system.h | 2 +- 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| 37 +- .../src/tx_thread_smp_low_level_initialize.S | 13 +- .../src/tx_thread_smp_protect.S | 24 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../src/tx_thread_smp_time_get.S | 13 +- .../src/tx_thread_smp_unprotect.S | 19 +- .../src/tx_thread_stack_build.S | 13 +- .../src/tx_thread_system_return.S | 23 +- .../module_manager/src/tx_timer_interrupt.S | 17 +- .../src/txm_module_manager_port_dispatch.c | 15 +- .../txm_module_manager_thread_stack_build.S | 13 +- .../cortex_a35_smp/gnu/readme_threadx.txt | 54 +- .../ac5/example_build/sample_threadx_module.c | 40 +- .../sample_threadx_module_manager.c | 36 +- .../cortex_a7/ac5/example_build/scatter.scat | 2 +- .../example_build/tx_initialize_low_level.s | 204 ++-- .../ac5/example_build/txm_module_preamble.s | 2 +- ports_module/cortex_a7/ac5/inc/tx_port.h | 98 +- .../cortex_a7/ac5/inc/txm_module_port.h | 61 +- .../module_lib/src/txm_module_initialize.s | 84 +- .../src/txm_module_thread_shell_entry.c | 13 +- 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++- .../txm_module_manager_mm_register_setup.c | 13 +- .../txm_module_manager_thread_stack_build.s | 84 +- .../src/txm_module_manager_user_mode_entry.s | 86 +- .../build_threadx_module_sample.bat | 2 +- .../cortex_a7/gnu/example_build/gcc_setup.S | 15 +- .../cortex_a7/gnu/example_build/module_code.c | 2 +- .../cortex_a7/gnu/example_build/reset.S | 7 +- .../gnu/example_build/sample_threadx.ld | 14 +- .../gnu/example_build/sample_threadx_module.c | 40 +- .../example_build/sample_threadx_module.ld | 4 +- .../sample_threadx_module_manager.c | 36 +- .../example_build/tx_initialize_low_level.s | 19 +- .../gnu/example_build/txm_module_preamble.s | 2 +- ports_module/cortex_a7/gnu/inc/tx_port.h | 26 +- .../cortex_a7/gnu/inc/txm_module_port.h | 64 +- .../src/txm_module_thread_shell_entry.c | 13 +- .../src/tx_thread_context_restore.s | 22 +- .../src/tx_thread_context_save.s | 22 +- .../src/tx_thread_fiq_context_restore.s | 22 +- .../src/tx_thread_fiq_context_save.s | 22 +- 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87 +- .../src/tx_thread_irq_nesting_start.s | 77 +- .../module_manager/src/tx_thread_schedule.s | 125 +- .../src/tx_thread_stack_build.s | 89 +- .../src/tx_thread_system_return.s | 71 +- .../src/tx_thread_vectored_context_save.s | 73 +- .../module_manager/src/tx_timer_interrupt.s | 79 +- .../src/txm_module_manager_alignment_adjust.c | 85 +- ...xm_module_manager_external_memory_enable.c | 13 +- .../txm_module_manager_memory_fault_handler.c | 13 +- .../txm_module_manager_memory_fault_notify.c | 85 +- .../src/txm_module_manager_mm_initialize.c | 167 ++- .../txm_module_manager_mm_register_setup.c | 13 +- .../txm_module_manager_thread_stack_build.s | 87 +- .../src/txm_module_manager_user_mode_entry.s | 89 +- .../example_build/sample_threadx/.cproject | 168 +-- .../example_build/sample_threadx/exceptions.c | 2 +- .../sample_threadx/sample_threadx.c | 46 +- .../sample_threadx/sample_threadx.scat | 2 +- .../sample_threadx/tx_initialize_low_level.S | 13 +- .../sample_threadx_module/.cproject | 216 ++-- .../sample_threadx_module.c | 60 +- .../txm_module_preamble.S | 2 +- .../sample_threadx_module_manager/.cproject | 170 +-- .../exceptions.c | 2 +- .../sample_threadx.scat | 2 +- .../sample_threadx_module_manager.c | 18 +- .../tx_initialize_low_level.S | 13 +- .../cortex_m0+/ac6/example_build/tx/.cproject | 164 +-- .../ac6/example_build/txm/.cproject | 182 +-- ports_module/cortex_m0+/ac6/inc/tx_port.h | 64 +- .../cortex_m0+/ac6/inc/txm_module_port.h | 15 +- .../module_lib/src/txm_module_initialize.S | 13 +- .../src/txm_module_thread_shell_entry.c | 21 +- .../src/tx_thread_context_restore.S | 13 +- .../src/tx_thread_context_save.S | 13 +- .../src/tx_thread_interrupt_control.S | 13 +- .../src/tx_thread_interrupt_disable.S | 13 +- .../src/tx_thread_interrupt_restore.S | 13 +- .../module_manager/src/tx_thread_schedule.S | 20 +- .../src/tx_thread_stack_build.S | 13 +- .../src/tx_thread_system_return.S | 13 +- .../module_manager/src/tx_timer_interrupt.S | 13 +- .../src/txm_module_manager_alignment_adjust.c | 33 +- ...xm_module_manager_external_memory_enable.c | 77 +- .../txm_module_manager_memory_fault_handler.c | 17 +- .../txm_module_manager_memory_fault_notify.c | 15 +- .../txm_module_manager_mm_register_setup.c | 155 ++- .../txm_module_manager_thread_stack_build.S | 13 +- .../example_build/sample_threadx/.cproject | 164 +-- .../sample_threadx/cortexm_crt0.s | 5 +- .../sample_threadx/sample_threadx.c | 46 +- .../sample_threadx/tx_initialize_low_level.S | 13 +- .../sample_threadx/tx_simulator_startup.s | 8 +- .../sample_threadx_module/.cproject | 176 +-- .../sample_threadx_module/gcc_setup.s | 16 +- .../sample_threadx_module.c | 60 +- .../sample_threadx_module.ld | 4 +- .../txm_module_preamble.S | 2 +- .../sample_threadx_module_manager/.cproject | 172 +-- .../cortexm_crt0.s | 5 +- .../sample_threadx_module_manager.c | 18 +- .../tx_initialize_low_level.S | 13 +- .../tx_simulator_startup.s | 8 +- .../cortex_m0+/gnu/example_build/tx/.cproject | 162 +-- .../gnu/example_build/txm/.cproject | 166 +-- ports_module/cortex_m0+/gnu/inc/tx_port.h | 64 +- .../cortex_m0+/gnu/inc/txm_module_port.h | 15 +- .../src/txm_module_thread_shell_entry.c | 21 +- .../src/tx_thread_context_restore.S | 13 +- .../src/tx_thread_context_save.S | 13 +- .../src/tx_thread_interrupt_control.S | 13 +- .../src/tx_thread_interrupt_disable.S | 13 +- .../src/tx_thread_interrupt_restore.S | 13 +- .../module_manager/src/tx_thread_schedule.S | 20 +- .../src/tx_thread_stack_build.S | 13 +- .../src/tx_thread_system_return.S | 13 +- .../module_manager/src/tx_timer_interrupt.S | 13 +- .../src/txm_module_manager_alignment_adjust.c | 33 +- ...xm_module_manager_external_memory_enable.c | 77 +- .../txm_module_manager_memory_fault_handler.c | 17 +- .../txm_module_manager_memory_fault_notify.c | 15 +- .../txm_module_manager_mm_register_setup.c | 155 ++- .../txm_module_manager_thread_stack_build.S | 13 +- .../cortex_m0+/iar/example_build/cstartup_M.s | 8 +- .../iar/example_build/sample_threadx.c | 48 +- .../iar/example_build/sample_threadx_module.c | 62 +- .../example_build/sample_threadx_module.icf | 8 +- .../sample_threadx_module_manager.c | 20 +- .../sample_threadx_module_manager.icf | 4 +- .../cortex_m0+/iar/example_build/startup.s | 430 +++---- .../example_build/tx_initialize_low_level.s | 22 +- ports_module/cortex_m0+/iar/inc/tx_port.h | 74 +- .../cortex_m0+/iar/inc/txm_module_port.h | 15 +- .../src/txm_module_thread_shell_entry.c | 21 +- .../iar/module_manager/src/tx_iar.c | 235 ++-- .../iar/module_manager/src/tx_misra.s | 23 +- .../src/tx_thread_context_restore.S | 13 +- .../src/tx_thread_context_save.S | 13 +- .../src/tx_thread_interrupt_control.S | 13 +- .../src/tx_thread_interrupt_disable.S | 13 +- .../src/tx_thread_interrupt_restore.S | 13 +- .../module_manager/src/tx_thread_schedule.S | 21 +- .../src/tx_thread_stack_build.S | 13 +- .../src/tx_thread_system_return.S | 13 +- .../module_manager/src/tx_timer_interrupt.S | 13 +- .../src/txm_module_manager_alignment_adjust.c | 33 +- ...xm_module_manager_external_memory_enable.c | 77 +- .../txm_module_manager_memory_fault_handler.c | 17 +- .../txm_module_manager_memory_fault_notify.c | 15 +- .../txm_module_manager_mm_register_setup.c | 155 ++- .../txm_module_manager_thread_stack_build.S | 13 +- .../ac6/example_build/ARMCM23_TZ_config.txt | 2 +- .../_ThreadX_Library_Project/RTE_Components.h | 6 +- .../RTE/Device/ARMCM23_TZ/partition_ARMCM23.h | 2 +- .../RTE/Device/ARMCM23_TZ/system_ARMCM23.c | 2 +- .../_FVP_Simulation_Model/RTE_Components.h | 6 +- .../demo_secure_zone/interface.c | 10 +- .../example_build/demo_secure_zone/main_ns.c | 2 +- .../example_build/demo_secure_zone/main_s.c | 18 +- .../demo_secure_zone/tz_context.c | 2 +- .../RTE/CMSIS/RTX_Config.c | 6 +- .../RTE/CMSIS/RTX_Config.h | 220 ++-- .../RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct | 2 +- .../_FVP_Simulation_Model/RTE_Components.h | 6 +- .../_ThreadX_Library_Project/RTE_Components.h | 6 +- .../sample_threadx_module_manager.c | 22 +- .../_FVP_Simulation_Model/RTE_Components.h | 6 +- .../sample_threadx_module.c | 64 +- .../txm_module_preamble.S | 2 +- .../example_build/tx_initialize_low_level.S | 35 +- .../_ThreadX_Module_Library/RTE_Components.h | 6 +- ports_module/cortex_m23/ac6/inc/tx_port.h | 44 +- .../cortex_m23/ac6/inc/tx_secure_interface.h | 13 +- .../cortex_m23/ac6/inc/txm_module_port.h | 18 +- .../module_lib/src/txm_module_initialize.S | 19 +- .../src/txm_module_thread_shell_entry.c | 25 +- .../src/txm_thread_secure_stack_allocate.c | 13 +- .../src/txm_thread_secure_stack_free.c | 13 +- .../inc/txm_module_manager_dispatch_port.h | 7 +- .../src/tx_thread_context_restore.S | 13 +- .../src/tx_thread_context_save.S | 13 +- .../src/tx_thread_interrupt_control.S | 13 +- .../src/tx_thread_interrupt_disable.S | 13 +- .../src/tx_thread_interrupt_restore.S | 13 +- .../module_manager/src/tx_thread_schedule.S | 28 +- .../src/tx_thread_secure_stack.c | 22 +- .../src/tx_thread_secure_stack_allocate.S | 13 +- .../src/tx_thread_secure_stack_free.S | 13 +- .../src/tx_thread_secure_stack_initialize.S | 17 +- .../src/tx_thread_stack_build.S | 15 +- .../src/tx_thread_system_return.S | 13 +- .../module_manager/src/tx_timer_interrupt.S | 13 +- .../src/txe_thread_secure_stack_allocate.c | 21 +- .../src/txe_thread_secure_stack_free.c | 21 +- .../src/txm_module_manager_alignment_adjust.c | 15 +- ...xm_module_manager_external_memory_enable.c | 39 +- .../txm_module_manager_memory_fault_handler.c | 17 +- .../txm_module_manager_memory_fault_notify.c | 15 +- .../txm_module_manager_mm_register_setup.c | 25 +- .../src/txm_module_manager_port_dispatch.c | 19 +- .../txm_module_manager_thread_stack_build.S | 15 +- .../gnu/example_build/sample_threadx_module.c | 62 +- .../gnu/example_build/txm_module_preamble.S | 2 +- ports_module/cortex_m23/gnu/inc/tx_port.h | 50 +- .../cortex_m23/gnu/inc/tx_secure_interface.h | 13 +- .../cortex_m23/gnu/inc/txm_module_port.h | 15 +- .../src/txm_module_thread_shell_entry.c | 21 +- .../src/txm_thread_secure_stack_allocate.c | 13 +- .../src/txm_thread_secure_stack_free.c | 13 +- .../inc/txm_module_manager_dispatch_port.h | 7 +- .../src/tx_initialize_low_level.S | 35 +- .../src/tx_thread_context_restore.S | 13 +- .../src/tx_thread_context_save.S | 13 +- .../src/tx_thread_interrupt_control.S | 13 +- .../src/tx_thread_interrupt_disable.S | 13 +- .../src/tx_thread_interrupt_restore.S | 13 +- .../module_manager/src/tx_thread_schedule.S | 28 +- .../src/tx_thread_secure_stack.c | 22 +- .../src/tx_thread_secure_stack_allocate.S | 13 +- .../src/tx_thread_secure_stack_free.S | 13 +- .../src/tx_thread_secure_stack_initialize.S | 17 +- .../src/tx_thread_stack_build.S | 15 +- .../src/tx_thread_system_return.S | 13 +- .../module_manager/src/tx_timer_interrupt.S | 13 +- .../src/txe_thread_secure_stack_allocate.c | 21 +- .../src/txe_thread_secure_stack_free.c | 21 +- .../src/txm_module_manager_alignment_adjust.c | 15 +- ...xm_module_manager_external_memory_enable.c | 39 +- .../txm_module_manager_memory_fault_handler.c | 17 +- .../txm_module_manager_memory_fault_notify.c | 15 +- .../txm_module_manager_mm_register_setup.c | 25 +- .../src/txm_module_manager_port_dispatch.c | 19 +- .../txm_module_manager_thread_stack_build.S | 15 +- .../iar/example_build/sample_threadx_module.c | 62 +- .../example_build/sample_threadx_module.icf | 8 +- .../sample_threadx_module_manager.c | 16 +- .../example_build/tx_initialize_low_level.s | 30 +- ports_module/cortex_m23/iar/inc/tx_port.h | 36 +- .../cortex_m23/iar/inc/tx_secure_interface.h | 13 +- .../cortex_m23/iar/inc/txm_module_port.h | 15 +- .../src/txm_module_thread_shell_entry.c | 21 +- .../src/txm_thread_secure_stack_allocate.c | 13 +- .../src/txm_thread_secure_stack_free.c | 13 +- .../inc/txm_module_manager_dispatch_port.h | 7 +- .../src/tx_thread_context_restore.s | 14 +- .../src/tx_thread_context_save.s | 14 +- .../src/tx_thread_interrupt_control.s | 14 +- .../src/tx_thread_interrupt_disable.s | 14 +- .../src/tx_thread_interrupt_restore.s | 14 +- .../module_manager/src/tx_thread_schedule.s | 29 +- .../src/tx_thread_secure_stack.c | 22 +- .../src/tx_thread_secure_stack_allocate.s | 14 +- .../src/tx_thread_secure_stack_free.s | 14 +- .../src/tx_thread_secure_stack_initialize.s | 18 +- .../src/tx_thread_stack_build.s | 16 +- .../src/tx_thread_system_return.s | 14 +- .../module_manager/src/tx_timer_interrupt.s | 14 +- .../src/txe_thread_secure_stack_allocate.c | 21 +- .../src/txe_thread_secure_stack_free.c | 21 +- .../src/txm_module_manager_alignment_adjust.c | 15 +- ...xm_module_manager_external_memory_enable.c | 39 +- .../txm_module_manager_memory_fault_handler.c | 17 +- .../txm_module_manager_memory_fault_notify.c | 15 +- .../txm_module_manager_mm_register_setup.c | 25 +- .../src/txm_module_manager_port_dispatch.c | 19 +- .../txm_module_manager_thread_stack_build.s | 16 +- .../ac5/example_build/sample_threadx.c | 46 +- .../ac5/example_build/sample_threadx_module.c | 60 +- .../sample_threadx_module_manager.c | 18 +- .../example_build/tx_initialize_low_level.S | 98 +- ports_module/cortex_m3/ac5/inc/tx_port.h | 24 +- .../cortex_m3/ac5/inc/txm_module_port.h | 27 +- .../module_lib/src/txm_module_initialize.s | 14 +- .../src/txm_module_thread_shell_entry.c | 21 +- .../src/tx_thread_context_restore.s | 16 +- .../src/tx_thread_context_save.s | 16 +- .../src/tx_thread_interrupt_control.s | 16 +- .../src/tx_thread_interrupt_disable.s | 16 +- .../src/tx_thread_interrupt_restore.s | 16 +- .../module_manager/src/tx_thread_schedule.s | 24 +- .../src/tx_thread_stack_build.s | 16 +- .../src/tx_thread_system_return.s | 16 +- .../module_manager/src/tx_timer_interrupt.s | 19 +- .../src/txm_module_manager_alignment_adjust.c | 33 +- ...xm_module_manager_external_memory_enable.c | 79 +- .../txm_module_manager_memory_fault_handler.c | 17 +- .../txm_module_manager_memory_fault_notify.c | 15 +- .../txm_module_manager_mm_register_setup.c | 17 +- .../txm_module_manager_thread_stack_build.s | 14 +- .../src/txm_module_manager_user_mode_entry.s | 14 +- .../example_build/sample_threadx/.cproject | 190 +-- .../example_build/sample_threadx/exceptions.c | 2 +- .../sample_threadx/sample_threadx.c | 46 +- .../sample_threadx/sample_threadx.scat | 2 +- .../sample_threadx/tx_initialize_low_level.S | 13 +- .../sample_threadx_module/.cproject | 216 ++-- .../sample_threadx_module.c | 60 +- .../txm_module_preamble.S | 2 +- .../sample_threadx_module_manager/.cproject | 170 +-- .../exceptions.c | 2 +- .../sample_threadx.scat | 2 +- .../sample_threadx_module_manager.c | 18 +- .../tx_initialize_low_level.S | 13 +- .../cortex_m3/ac6/example_build/tx/.cproject | 160 +-- .../cortex_m3/ac6/example_build/txm/.cproject | 182 +-- ports_module/cortex_m3/ac6/inc/tx_port.h | 24 +- .../cortex_m3/ac6/inc/txm_module_port.h | 27 +- .../module_lib/src/txm_module_initialize.S | 16 +- .../src/txm_module_thread_shell_entry.c | 24 +- .../src/tx_thread_context_restore.S | 15 +- .../src/tx_thread_context_save.S | 15 +- .../src/tx_thread_interrupt_control.S | 15 +- .../src/tx_thread_interrupt_disable.S | 15 +- .../src/tx_thread_interrupt_restore.S | 15 +- .../module_manager/src/tx_thread_schedule.S | 22 +- .../src/tx_thread_stack_build.S | 15 +- .../src/tx_thread_system_return.S | 15 +- .../module_manager/src/tx_timer_interrupt.S | 18 +- .../src/txm_module_manager_alignment_adjust.c | 33 +- ...xm_module_manager_external_memory_enable.c | 79 +- .../txm_module_manager_memory_fault_handler.c | 17 +- .../txm_module_manager_memory_fault_notify.c | 15 +- .../txm_module_manager_mm_register_setup.c | 17 +- .../txm_module_manager_thread_stack_build.S | 13 +- .../gnu/example_build/cortexm_crt0.s | 5 +- .../cortex_m3/gnu/example_build/gcc_setup.s | 15 +- .../gnu/example_build/sample_threadx_module.c | 62 +- .../example_build/sample_threadx_module.ld | 4 +- .../sample_threadx_module_manager.c | 18 +- .../example_build/tx_initialize_low_level.S | 31 +- .../gnu/example_build/tx_simulator_startup.s | 8 +- .../gnu/example_build/txm_module_preamble.S | 2 +- ports_module/cortex_m3/gnu/inc/tx_port.h | 24 +- .../cortex_m3/gnu/inc/txm_module_port.h | 27 +- .../src/txm_module_thread_shell_entry.c | 21 +- .../src/tx_thread_context_restore.S | 15 +- .../src/tx_thread_context_save.S | 15 +- .../src/tx_thread_interrupt_control.S | 15 +- .../src/tx_thread_interrupt_disable.S | 15 +- .../src/tx_thread_interrupt_restore.S | 15 +- .../module_manager/src/tx_thread_schedule.S | 24 +- .../src/tx_thread_stack_build.S | 15 +- .../src/tx_thread_system_return.S | 15 +- .../module_manager/src/tx_timer_interrupt.S | 18 +- .../src/txm_module_manager_alignment_adjust.c | 33 +- ...xm_module_manager_external_memory_enable.c | 79 +- .../txm_module_manager_memory_fault_handler.c | 17 +- .../txm_module_manager_memory_fault_notify.c | 15 +- .../txm_module_manager_mm_register_setup.c | 17 +- .../txm_module_manager_thread_stack_build.s | 14 +- .../cortex_m3/iar/example_build/cstartup_M.s | 8 +- .../iar/example_build/sample_threadx.c | 48 +- .../iar/example_build/sample_threadx_module.c | 62 +- .../example_build/sample_threadx_module.icf | 8 +- .../sample_threadx_module_manager.c | 18 +- .../sample_threadx_module_manager.icf | 4 +- .../cortex_m3/iar/example_build/startup.s | 430 +++---- .../example_build/tx_initialize_low_level.s | 34 +- ports_module/cortex_m3/iar/inc/tx_port.h | 24 +- .../cortex_m3/iar/inc/txm_module_port.h | 27 +- .../src/txm_module_thread_shell_entry.c | 21 +- .../cortex_m3/iar/module_manager/src/tx_iar.c | 235 ++-- .../iar/module_manager/src/tx_misra.s | 23 +- .../src/tx_thread_context_restore.s | 16 +- .../src/tx_thread_context_save.s | 16 +- .../src/tx_thread_interrupt_control.s | 16 +- .../src/tx_thread_interrupt_disable.s | 16 +- .../src/tx_thread_interrupt_restore.s | 16 +- .../module_manager/src/tx_thread_schedule.s | 23 +- .../src/tx_thread_stack_build.s | 16 +- .../src/tx_thread_system_return.s | 16 +- .../module_manager/src/tx_timer_interrupt.s | 19 +- .../src/txm_module_manager_alignment_adjust.c | 33 +- ...xm_module_manager_external_memory_enable.c | 79 +- .../txm_module_manager_memory_fault_handler.c | 17 +- .../txm_module_manager_memory_fault_notify.c | 15 +- .../txm_module_manager_mm_register_setup.c | 17 +- .../txm_module_manager_thread_stack_build.s | 14 +- .../ARMCM33_DSP_FP_TZ_config.txt | 2 +- .../_ThreadX_Library_Project/RTE_Components.h | 6 +- .../Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c | 2 +- .../_FVP_Simulation_Model/RTE_Components.h | 6 +- .../demo_secure_zone/interface.c | 10 +- .../example_build/demo_secure_zone/main_ns.c | 2 +- .../example_build/demo_secure_zone/main_s.c | 18 +- .../RTE/CMSIS/RTX_Config.c | 6 +- .../RTE/CMSIS/RTX_Config.h | 220 ++-- .../_FVP_Simulation_Model/RTE_Components.h | 6 +- .../_ThreadX_Library_Project/RTE_Components.h | 6 +- .../sample_threadx_module_manager.c | 22 +- .../_FVP_Simulation_Model/RTE_Components.h | 6 +- .../sample_threadx_module.c | 64 +- .../txm_module_preamble.S | 2 +- .../example_build/tx_initialize_low_level.S | 13 +- .../_ThreadX_Module_Library/RTE_Components.h | 6 +- ports_module/cortex_m33/ac6/inc/tx_port.h | 40 +- .../cortex_m33/ac6/inc/tx_secure_interface.h | 13 +- .../cortex_m33/ac6/inc/txm_module_port.h | 18 +- .../module_lib/src/txm_module_initialize.S | 17 +- .../src/txm_module_thread_shell_entry.c | 25 +- .../src/txm_thread_secure_stack_allocate.c | 13 +- .../src/txm_thread_secure_stack_free.c | 13 +- .../inc/txm_module_manager_dispatch_port.h | 7 +- .../src/tx_thread_context_restore.S | 13 +- .../src/tx_thread_context_save.S | 13 +- .../src/tx_thread_interrupt_control.S | 13 +- .../src/tx_thread_interrupt_disable.S | 13 +- .../src/tx_thread_interrupt_restore.S | 13 +- .../module_manager/src/tx_thread_schedule.S | 37 +- .../src/tx_thread_secure_stack.c | 22 +- .../src/tx_thread_secure_stack_allocate.S | 13 +- .../src/tx_thread_secure_stack_free.S | 13 +- .../src/tx_thread_secure_stack_initialize.S | 17 +- .../src/tx_thread_stack_build.S | 13 +- .../src/tx_thread_system_return.S | 13 +- .../module_manager/src/tx_timer_interrupt.S | 13 +- .../src/txe_thread_secure_stack_allocate.c | 21 +- .../src/txe_thread_secure_stack_free.c | 21 +- .../src/txm_module_manager_alignment_adjust.c | 15 +- ...xm_module_manager_external_memory_enable.c | 39 +- .../txm_module_manager_memory_fault_handler.c | 17 +- .../txm_module_manager_memory_fault_notify.c | 15 +- .../txm_module_manager_mm_register_setup.c | 28 +- .../src/txm_module_manager_port_dispatch.c | 19 +- .../txm_module_manager_thread_stack_build.S | 13 +- .../cortex_m33/gnu/example_build/gcc_setup.s | 15 +- .../gnu/example_build/sample_threadx_module.c | 62 +- .../sample_threadx_module_manager.c | 18 +- .../gnu/example_build/txm_module_preamble.S | 2 +- ports_module/cortex_m33/gnu/inc/tx_port.h | 40 +- .../cortex_m33/gnu/inc/tx_secure_interface.h | 13 +- .../cortex_m33/gnu/inc/txm_module_port.h | 17 +- .../src/txm_module_thread_shell_entry.c | 21 +- .../src/txm_thread_secure_stack_allocate.c | 13 +- .../src/txm_thread_secure_stack_free.c | 13 +- .../inc/txm_module_manager_dispatch_port.h | 7 +- .../src/tx_initialize_low_level.S | 15 +- .../src/tx_thread_context_restore.s | 14 +- .../src/tx_thread_context_save.s | 14 +- .../src/tx_thread_interrupt_control.s | 14 +- .../src/tx_thread_interrupt_disable.s | 14 +- .../src/tx_thread_interrupt_restore.s | 14 +- .../module_manager/src/tx_thread_schedule.S | 37 +- .../src/tx_thread_secure_stack.c | 22 +- .../src/tx_thread_secure_stack_allocate.S | 13 +- .../src/tx_thread_secure_stack_free.S | 13 +- .../src/tx_thread_secure_stack_initialize.S | 17 +- .../src/tx_thread_stack_build.s | 14 +- .../src/tx_thread_system_return.s | 14 +- .../module_manager/src/tx_timer_interrupt.s | 14 +- .../src/txe_thread_secure_stack_allocate.c | 21 +- .../src/txe_thread_secure_stack_free.c | 21 +- .../src/txm_module_manager_alignment_adjust.c | 15 +- ...xm_module_manager_external_memory_enable.c | 39 +- .../txm_module_manager_memory_fault_handler.c | 17 +- .../txm_module_manager_memory_fault_notify.c | 15 +- .../txm_module_manager_mm_register_setup.c | 28 +- .../src/txm_module_manager_port_dispatch.c | 19 +- .../txm_module_manager_thread_stack_build.s | 14 +- .../iar/example_build/sample_threadx_module.c | 62 +- .../example_build/sample_threadx_module.icf | 8 +- .../sample_threadx_module_manager.c | 16 +- .../example_build/tx_initialize_low_level.s | 14 +- ports_module/cortex_m33/iar/inc/tx_port.h | 40 +- .../cortex_m33/iar/inc/tx_secure_interface.h | 13 +- .../cortex_m33/iar/inc/txm_module_port.h | 17 +- .../src/txm_module_thread_shell_entry.c | 21 +- .../src/txm_thread_secure_stack_allocate.c | 13 +- .../src/txm_thread_secure_stack_free.c | 13 +- .../inc/txm_module_manager_dispatch_port.h | 7 +- .../src/tx_thread_context_restore.s | 14 +- .../src/tx_thread_context_save.s | 14 +- .../src/tx_thread_interrupt_control.s | 14 +- .../src/tx_thread_interrupt_disable.s | 14 +- .../src/tx_thread_interrupt_restore.s | 14 +- .../module_manager/src/tx_thread_schedule.s | 38 +- .../src/tx_thread_secure_stack.c | 21 +- .../src/tx_thread_secure_stack_allocate.s | 16 +- .../src/tx_thread_secure_stack_free.s | 16 +- .../src/tx_thread_secure_stack_initialize.s | 18 +- .../src/tx_thread_stack_build.s | 14 +- .../src/tx_thread_system_return.s | 14 +- .../module_manager/src/tx_timer_interrupt.s | 14 +- .../src/txe_thread_secure_stack_allocate.c | 21 +- .../src/txe_thread_secure_stack_free.c | 21 +- .../src/txm_module_manager_alignment_adjust.c | 15 +- ...xm_module_manager_external_memory_enable.c | 39 +- .../txm_module_manager_memory_fault_handler.c | 17 +- .../txm_module_manager_memory_fault_notify.c | 15 +- .../txm_module_manager_mm_register_setup.c | 28 +- .../src/txm_module_manager_port_dispatch.c | 19 +- .../txm_module_manager_thread_stack_build.s | 14 +- .../ac5/example_build/sample_threadx.c | 46 +- .../ac5/example_build/sample_threadx_module.c | 60 +- .../sample_threadx_module_manager.c | 18 +- .../example_build/tx_initialize_low_level.S | 29 +- ports_module/cortex_m4/ac5/inc/tx_port.h | 24 +- .../cortex_m4/ac5/inc/txm_module_port.h | 27 +- .../module_lib/src/txm_module_initialize.s | 14 +- .../src/txm_module_thread_shell_entry.c | 21 +- .../src/tx_thread_context_restore.s | 16 +- .../src/tx_thread_context_save.s | 16 +- .../src/tx_thread_interrupt_control.s | 16 +- .../src/tx_thread_interrupt_disable.s | 16 +- .../src/tx_thread_interrupt_restore.s | 16 +- .../module_manager/src/tx_thread_schedule.s | 24 +- .../src/tx_thread_stack_build.s | 16 +- .../src/tx_thread_system_return.s | 16 +- .../module_manager/src/tx_timer_interrupt.s | 19 +- .../src/txm_module_manager_alignment_adjust.c | 33 +- ...xm_module_manager_external_memory_enable.c | 79 +- .../txm_module_manager_memory_fault_handler.c | 17 +- .../txm_module_manager_memory_fault_notify.c | 15 +- .../txm_module_manager_mm_register_setup.c | 17 +- .../txm_module_manager_thread_stack_build.s | 14 +- .../src/txm_module_manager_user_mode_entry.s | 14 +- .../example_build/sample_threadx/.cproject | 168 +-- .../example_build/sample_threadx/exceptions.c | 2 +- .../sample_threadx/sample_threadx.c | 46 +- .../sample_threadx/sample_threadx.scat | 2 +- .../sample_threadx/tx_initialize_low_level.S | 13 +- .../sample_threadx_module/.cproject | 216 ++-- .../sample_threadx_module.c | 60 +- .../txm_module_preamble.S | 2 +- .../sample_threadx_module_manager/.cproject | 170 +-- .../exceptions.c | 2 +- .../sample_threadx.scat | 2 +- .../sample_threadx_module_manager.c | 18 +- .../tx_initialize_low_level.S | 17 +- .../cortex_m4/ac6/example_build/tx/.cproject | 160 +-- .../cortex_m4/ac6/example_build/txm/.cproject | 182 +-- ports_module/cortex_m4/ac6/inc/tx_port.h | 24 +- .../cortex_m4/ac6/inc/txm_module_port.h | 27 +- .../module_lib/src/txm_module_initialize.S | 16 +- .../src/txm_module_thread_shell_entry.c | 24 +- .../src/tx_thread_context_restore.S | 15 +- .../src/tx_thread_context_save.S | 15 +- .../src/tx_thread_interrupt_control.S | 15 +- .../src/tx_thread_interrupt_disable.S | 15 +- .../src/tx_thread_interrupt_restore.S | 15 +- .../module_manager/src/tx_thread_schedule.S | 22 +- .../src/tx_thread_stack_build.S | 15 +- .../src/tx_thread_system_return.S | 15 +- .../module_manager/src/tx_timer_interrupt.S | 18 +- .../src/txm_module_manager_alignment_adjust.c | 33 +- ...xm_module_manager_external_memory_enable.c | 79 +- .../txm_module_manager_memory_fault_handler.c | 17 +- .../txm_module_manager_memory_fault_notify.c | 15 +- .../txm_module_manager_mm_register_setup.c | 17 +- .../txm_module_manager_thread_stack_build.S | 13 +- .../gnu/example_build/cortexm_vectors.S | 12 +- .../cortex_m4/gnu/example_build/gcc_setup.s | 15 +- .../gnu/example_build/sample_threadx_module.c | 62 +- .../example_build/sample_threadx_module.ld | 4 +- .../sample_threadx_module_manager.c | 18 +- .../example_build/tx_initialize_low_level.S | 29 +- .../gnu/example_build/txm_module_preamble.S | 2 +- ports_module/cortex_m4/gnu/inc/tx_port.h | 24 +- .../cortex_m4/gnu/inc/txm_module_port.h | 27 +- .../src/txm_module_thread_shell_entry.c | 21 +- .../src/tx_thread_context_restore.S | 15 +- .../src/tx_thread_context_save.S | 15 +- .../src/tx_thread_interrupt_control.S | 15 +- .../src/tx_thread_interrupt_disable.S | 15 +- .../src/tx_thread_interrupt_restore.S | 15 +- .../module_manager/src/tx_thread_schedule.S | 24 +- .../src/tx_thread_stack_build.S | 15 +- .../src/tx_thread_system_return.S | 15 +- .../module_manager/src/tx_timer_interrupt.S | 18 +- .../src/txm_module_manager_alignment_adjust.c | 33 +- ...xm_module_manager_external_memory_enable.c | 79 +- .../txm_module_manager_memory_fault_handler.c | 17 +- .../txm_module_manager_memory_fault_notify.c | 15 +- .../txm_module_manager_mm_register_setup.c | 17 +- .../txm_module_manager_thread_stack_build.s | 14 +- .../cortex_m4/iar/example_build/cstartup_M.s | 8 +- .../iar/example_build/sample_threadx.c | 48 +- .../iar/example_build/sample_threadx_module.c | 62 +- .../example_build/sample_threadx_module.icf | 8 +- .../sample_threadx_module_manager.c | 16 +- .../cortex_m4/iar/example_build/startup.s | 430 +++---- .../example_build/tx_initialize_low_level.s | 28 +- ports_module/cortex_m4/iar/inc/tx_port.h | 24 +- .../cortex_m4/iar/inc/txm_module_port.h | 27 +- .../src/txm_module_thread_shell_entry.c | 21 +- .../cortex_m4/iar/module_manager/src/tx_iar.c | 235 ++-- .../iar/module_manager/src/tx_misra.s | 23 +- .../src/tx_thread_context_restore.s | 16 +- .../src/tx_thread_context_save.s | 16 +- .../src/tx_thread_interrupt_control.s | 16 +- .../src/tx_thread_interrupt_disable.s | 16 +- .../src/tx_thread_interrupt_restore.s | 16 +- .../module_manager/src/tx_thread_schedule.s | 23 +- .../src/tx_thread_stack_build.s | 16 +- .../src/tx_thread_system_return.s | 16 +- .../module_manager/src/tx_timer_interrupt.s | 19 +- .../src/txm_module_manager_alignment_adjust.c | 33 +- ...xm_module_manager_external_memory_enable.c | 79 +- .../txm_module_manager_memory_fault_handler.c | 17 +- .../txm_module_manager_memory_fault_notify.c | 15 +- .../txm_module_manager_mm_register_setup.c | 17 +- .../txm_module_manager_thread_stack_build.s | 14 +- .../ac5/example_build/sample_threadx.c | 46 +- .../ac5/example_build/sample_threadx_module.c | 60 +- .../sample_threadx_module_manager.c | 18 +- .../example_build/tx_initialize_low_level.S | 29 +- ports_module/cortex_m7/ac5/inc/tx_port.h | 24 +- .../cortex_m7/ac5/inc/txm_module_port.h | 27 +- .../module_lib/src/txm_module_initialize.s | 14 +- .../src/txm_module_thread_shell_entry.c | 21 +- .../src/tx_thread_context_restore.s | 16 +- .../src/tx_thread_context_save.s | 16 +- .../src/tx_thread_interrupt_control.s | 16 +- .../src/tx_thread_interrupt_disable.s | 16 +- .../src/tx_thread_interrupt_restore.s | 16 +- .../module_manager/src/tx_thread_schedule.s | 24 +- .../src/tx_thread_stack_build.s | 16 +- .../src/tx_thread_system_return.s | 16 +- .../module_manager/src/tx_timer_interrupt.s | 19 +- .../src/txm_module_manager_alignment_adjust.c | 33 +- ...xm_module_manager_external_memory_enable.c | 79 +- .../txm_module_manager_memory_fault_handler.c | 17 +- .../txm_module_manager_memory_fault_notify.c | 15 +- .../txm_module_manager_mm_register_setup.c | 17 +- .../txm_module_manager_thread_stack_build.s | 14 +- .../src/txm_module_manager_user_mode_entry.s | 14 +- .../example_build/sample_threadx/.cproject | 168 +-- .../example_build/sample_threadx/exceptions.c | 2 +- .../sample_threadx/sample_threadx.c | 46 +- .../sample_threadx/sample_threadx.scat | 2 +- .../sample_threadx/tx_initialize_low_level.S | 13 +- .../sample_threadx_module/.cproject | 216 ++-- .../sample_threadx_module.c | 60 +- .../txm_module_preamble.S | 2 +- .../sample_threadx_module_manager/.cproject | 172 +-- .../exceptions.c | 2 +- .../sample_threadx.scat | 2 +- .../sample_threadx_module_manager.c | 18 +- .../tx_initialize_low_level.S | 17 +- .../cortex_m7/ac6/example_build/tx/.cproject | 160 +-- .../cortex_m7/ac6/example_build/txm/.cproject | 182 +-- ports_module/cortex_m7/ac6/inc/tx_port.h | 24 +- .../cortex_m7/ac6/inc/txm_module_port.h | 27 +- .../module_lib/src/txm_module_initialize.S | 16 +- .../src/txm_module_thread_shell_entry.c | 24 +- .../src/tx_thread_context_restore.S | 15 +- .../src/tx_thread_context_save.S | 15 +- .../src/tx_thread_interrupt_control.S | 15 +- .../src/tx_thread_interrupt_disable.S | 15 +- .../src/tx_thread_interrupt_restore.S | 15 +- .../module_manager/src/tx_thread_schedule.S | 22 +- .../src/tx_thread_stack_build.S | 15 +- .../src/tx_thread_system_return.S | 15 +- .../module_manager/src/tx_timer_interrupt.S | 18 +- .../src/txm_module_manager_alignment_adjust.c | 33 +- ...xm_module_manager_external_memory_enable.c | 79 +- .../txm_module_manager_memory_fault_handler.c | 17 +- .../txm_module_manager_memory_fault_notify.c | 15 +- .../txm_module_manager_mm_register_setup.c | 17 +- .../txm_module_manager_thread_stack_build.S | 13 +- .../gnu/example_build/cortexm_crt0.s | 5 +- .../cortex_m7/gnu/example_build/gcc_setup.s | 15 +- .../gnu/example_build/sample_threadx_module.c | 62 +- .../example_build/sample_threadx_module.ld | 4 +- .../sample_threadx_module_manager.c | 18 +- .../example_build/tx_initialize_low_level.S | 29 +- .../gnu/example_build/tx_simulator_startup.s | 8 +- .../gnu/example_build/txm_module_preamble.S | 2 +- ports_module/cortex_m7/gnu/inc/tx_port.h | 24 +- .../cortex_m7/gnu/inc/txm_module_port.h | 27 +- .../src/txm_module_thread_shell_entry.c | 21 +- .../src/tx_thread_context_restore.S | 15 +- .../src/tx_thread_context_save.S | 15 +- .../src/tx_thread_interrupt_control.S | 15 +- .../src/tx_thread_interrupt_disable.S | 15 +- .../src/tx_thread_interrupt_restore.S | 15 +- .../module_manager/src/tx_thread_schedule.S | 24 +- .../src/tx_thread_stack_build.S | 15 +- .../src/tx_thread_system_return.S | 15 +- .../module_manager/src/tx_timer_interrupt.S | 18 +- .../src/txm_module_manager_alignment_adjust.c | 33 +- ...xm_module_manager_external_memory_enable.c | 79 +- .../txm_module_manager_memory_fault_handler.c | 17 +- .../txm_module_manager_memory_fault_notify.c | 15 +- .../txm_module_manager_mm_register_setup.c | 17 +- .../txm_module_manager_thread_stack_build.s | 14 +- .../cortex_m7/iar/example_build/cstartup_M.s | 8 +- .../iar/example_build/sample_threadx.c | 48 +- .../iar/example_build/sample_threadx_module.c | 60 +- .../example_build/sample_threadx_module.icf | 8 +- .../sample_threadx_module_manager.c | 16 +- .../cortex_m7/iar/example_build/startup.s | 538 ++++----- .../example_build/tx_initialize_low_level.s | 28 +- ports_module/cortex_m7/iar/inc/tx_port.h | 24 +- .../cortex_m7/iar/inc/txm_module_port.h | 27 +- .../src/txm_module_thread_shell_entry.c | 21 +- .../cortex_m7/iar/module_manager/src/tx_iar.c | 235 ++-- .../iar/module_manager/src/tx_misra.s | 23 +- .../src/tx_thread_context_restore.s | 16 +- .../src/tx_thread_context_save.s | 16 +- .../src/tx_thread_interrupt_control.s | 16 +- .../src/tx_thread_interrupt_disable.s | 16 +- .../src/tx_thread_interrupt_restore.s | 16 +- .../module_manager/src/tx_thread_schedule.s | 23 +- .../src/tx_thread_stack_build.s | 16 +- .../src/tx_thread_system_return.s | 16 +- .../module_manager/src/tx_timer_interrupt.s | 19 +- .../src/txm_module_manager_alignment_adjust.c | 33 +- ...xm_module_manager_external_memory_enable.c | 79 +- .../txm_module_manager_memory_fault_handler.c | 17 +- .../txm_module_manager_memory_fault_notify.c | 15 +- .../txm_module_manager_mm_register_setup.c | 17 +- .../txm_module_manager_thread_stack_build.s | 14 +- .../example_build/sample_threadx/.cproject | 168 +-- .../sample_threadx/sample_threadx.c | 48 +- .../sample_threadx/tx_initialize_low_level.S | 13 +- .../sample_threadx_module/.cproject | 182 +-- .../sample_threadx_module.c | 36 +- .../sample_threadx_module/semihosting.c | 6 +- .../sample_threadx_module_manager/.cproject | 168 +-- .../module_code.c | 2 +- .../sample_threadx.scat | 12 +- .../sample_threadx_module_manager.c | 28 +- .../sample_threadx_module_manager/startup.S | 6 +- .../tx_initialize_low_level.S | 13 +- .../cortex_r4/ac6/example_build/tx/.cproject | 162 +-- .../cortex_r4/ac6/example_build/txm/.cproject | 174 +-- ports_module/cortex_r4/ac6/inc/tx_port.h | 96 +- .../cortex_r4/ac6/inc/txm_module_port.h | 63 +- .../module_lib/src/txm_module_initialize.S | 74 +- .../src/txm_module_thread_shell_entry.c | 13 +- .../src/tx_thread_context_restore.S | 21 +- .../src/tx_thread_context_save.S | 13 +- .../src/tx_thread_fiq_context_restore.S | 19 +- .../src/tx_thread_fiq_context_save.S | 15 +- .../src/tx_thread_fiq_nesting_end.S | 17 +- .../src/tx_thread_fiq_nesting_start.S | 13 +- .../src/tx_thread_interrupt_control.S | 13 +- .../src/tx_thread_interrupt_disable.S | 13 +- .../src/tx_thread_interrupt_restore.S | 13 +- .../src/tx_thread_irq_nesting_end.S | 15 +- .../src/tx_thread_irq_nesting_start.S | 13 +- .../module_manager/src/tx_thread_schedule.S | 13 +- .../src/tx_thread_stack_build.S | 13 +- .../src/tx_thread_system_return.S | 13 +- .../src/tx_thread_vectored_context_save.S | 13 +- .../module_manager/src/tx_timer_interrupt.S | 13 +- .../src/txm_module_manager_alignment_adjust.c | 13 +- ...xm_module_manager_external_memory_enable.c | 13 +- .../txm_module_manager_memory_fault_handler.c | 13 +- .../txm_module_manager_memory_fault_notify.c | 13 +- .../txm_module_manager_mm_register_setup.c | 15 +- .../txm_module_manager_thread_stack_build.S | 13 +- .../src/txm_module_manager_user_mode_entry.S | 15 +- .../cortex_r4/iar/example_build/cstartup.s | 6 +- .../iar/example_build/sample_threadx.c | 48 +- .../iar/example_build/sample_threadx_module.c | 64 +- .../example_build/sample_threadx_module.icf | 8 +- .../sample_threadx_module_manager.c | 24 +- .../example_build/tx_initialize_low_level.s | 198 ++-- .../iar/example_build/txm_module_preamble.s | 18 +- ports_module/cortex_r4/iar/inc/tx_port.h | 102 +- .../cortex_r4/iar/inc/txm_module_port.h | 57 +- .../src/txm_module_thread_shell_entry.c | 13 +- .../cortex_r4/iar/module_manager/src/tx_iar.c | 239 ++-- .../src/tx_thread_context_restore.s | 92 +- .../src/tx_thread_context_save.s | 94 +- .../src/tx_thread_interrupt_control.s | 78 +- .../src/tx_thread_interrupt_disable.s | 74 +- .../src/tx_thread_interrupt_restore.s | 76 +- .../src/tx_thread_irq_nesting_end.s | 94 +- .../src/tx_thread_irq_nesting_start.s | 88 +- .../module_manager/src/tx_thread_schedule.s | 142 ++- .../src/tx_thread_stack_build.s | 88 +- .../src/tx_thread_system_return.s | 82 +- .../src/tx_thread_vectored_context_save.s | 82 +- .../module_manager/src/tx_timer_interrupt.s | 90 +- .../src/txm_module_manager_alignment_adjust.c | 163 ++- ...xm_module_manager_external_memory_enable.c | 13 +- .../txm_module_manager_memory_fault_handler.c | 13 +- .../txm_module_manager_memory_fault_notify.c | 85 +- .../txm_module_manager_mm_register_setup.c | 15 +- .../txm_module_manager_thread_stack_build.s | 84 +- .../src/txm_module_manager_user_mode_entry.s | 84 +- ports_module/rxv2/iar/example_build/hwsetup.c | 62 +- ports_module/rxv2/iar/example_build/hwsetup.h | 24 +- .../rxv2/iar/example_build/low_level_init.c | 2 +- .../example_build/sample_module_linker.icf | 6 +- .../iar/example_build/sample_threadx_module.c | 62 +- .../sample_threadx_module_manager.c | 26 +- .../example_build/tx_initialize_low_level.s | 14 +- .../iar/example_build/txm_module_preamble.s | 22 +- ports_module/rxv2/iar/inc/tx_port.h | 58 +- ports_module/rxv2/iar/inc/txm_module_port.h | 19 +- .../src/txm_module_thread_shell_entry.c | 21 +- .../src/tx_initialize_low_level.s | 18 +- .../src/tx_thread_context_restore.s | 30 +- .../src/tx_thread_context_save.s | 22 +- .../src/tx_thread_interrupt_control.s | 30 +- .../module_manager/src/tx_thread_schedule.s | 68 +- .../src/tx_thread_stack_build.s | 26 +- .../src/tx_thread_system_return.s | 16 +- .../module_manager/src/tx_timer_interrupt.s | 32 +- .../src/txm_module_manager_alignment_adjust.c | 13 +- ...xm_module_manager_external_memory_enable.c | 35 +- .../txm_module_manager_memory_fault_handler.c | 17 +- .../txm_module_manager_memory_fault_notify.c | 15 +- .../txm_module_manager_setup_mpu_registers.c | 35 +- .../txm_module_manager_thread_stack_build.s | 20 +- .../example_build/sample_threadx/arc.c | 4 +- .../sample_threadx/sample_threadx.c | 42 +- .../sample_threadx/sample_threadx.cmd | 18 +- .../sample_threadx/tx_initialize_low_level.s | 110 +- .../example_build/sample_threadx/vectors.s | 2 +- ports_smp/arc_hs_smp/metaware/inc/tx_port.h | 116 +- .../arc_hs_smp/metaware/readme_threadx.txt | 90 +- .../metaware/src/tx_thread_context_restore.s | 88 +- .../metaware/src/tx_thread_context_save.s | 74 +- .../src/tx_thread_interrupt_control.s | 62 +- .../metaware/src/tx_thread_schedule.s | 104 +- .../metaware/src/tx_thread_smp_core_get.s | 66 +- .../metaware/src/tx_thread_smp_core_preempt.s | 72 +- .../src/tx_thread_smp_current_state_get.s | 64 +- .../src/tx_thread_smp_current_thread_get.s | 64 +- .../src/tx_thread_smp_initialize_wait.s | 78 +- .../src/tx_thread_smp_low_level_initialize.s | 64 +- .../metaware/src/tx_thread_smp_protect.s | 64 +- .../metaware/src/tx_thread_smp_time_get.s | 64 +- .../metaware/src/tx_thread_smp_unprotect.s | 74 +- .../metaware/src/tx_thread_stack_build.s | 82 +- .../metaware/src/tx_thread_system_return.s | 74 +- .../metaware/src/tx_timer_interrupt.s | 84 +- .../example_build/sample_threadx/.cproject | 146 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.scat | 26 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../ac6/example_build/sample_threadx/v8_mmu.h | 2 +- .../ac6/example_build/tx/.cproject | 158 +-- ports_smp/cortex_a34_smp/ac6/inc/tx_port.h | 18 +- .../ac6/src/tx_initialize_low_level.S | 15 +- .../ac6/src/tx_thread_context_restore.S | 19 +- .../ac6/src/tx_thread_context_save.S | 16 +- .../ac6/src/tx_thread_fp_disable.c | 15 +- .../ac6/src/tx_thread_fp_enable.c | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 15 +- .../ac6/src/tx_thread_interrupt_disable.S | 15 +- .../ac6/src/tx_thread_interrupt_restore.S | 15 +- .../ac6/src/tx_thread_schedule.S | 16 +- .../ac6/src/tx_thread_smp_core_get.S | 16 +- .../ac6/src/tx_thread_smp_core_preempt.S | 16 +- .../ac6/src/tx_thread_smp_current_state_get.S | 16 +- .../src/tx_thread_smp_current_thread_get.S | 16 +- .../ac6/src/tx_thread_smp_initialize_wait.S | 16 +- .../src/tx_thread_smp_low_level_initialize.S | 15 +- .../ac6/src/tx_thread_smp_protect.S | 24 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../ac6/src/tx_thread_smp_time_get.S | 15 +- .../ac6/src/tx_thread_smp_unprotect.S | 19 +- .../ac6/src/tx_thread_stack_build.S | 15 +- .../ac6/src/tx_thread_system_return.S | 16 +- .../ac6/src/tx_timer_interrupt.S | 13 +- .../example_build/sample_threadx/.cproject | 162 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.ld | 4 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../gnu/example_build/sample_threadx/v8_mmu.h | 2 +- .../gnu/example_build/tx/.cproject | 192 ++-- ports_smp/cortex_a34_smp/gnu/inc/tx_port.h | 18 +- .../gnu/src/tx_initialize_low_level.S | 15 +- .../gnu/src/tx_thread_context_restore.S | 19 +- .../gnu/src/tx_thread_context_save.S | 16 +- .../gnu/src/tx_thread_fp_disable.c | 15 +- .../gnu/src/tx_thread_fp_enable.c | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 15 +- .../gnu/src/tx_thread_interrupt_disable.S | 15 +- .../gnu/src/tx_thread_interrupt_restore.S | 15 +- .../gnu/src/tx_thread_schedule.S | 16 +- .../gnu/src/tx_thread_smp_core_get.S | 16 +- .../gnu/src/tx_thread_smp_core_preempt.S | 16 +- .../gnu/src/tx_thread_smp_current_state_get.S | 16 +- .../src/tx_thread_smp_current_thread_get.S | 16 +- .../gnu/src/tx_thread_smp_initialize_wait.S | 16 +- .../src/tx_thread_smp_low_level_initialize.S | 15 +- .../gnu/src/tx_thread_smp_protect.S | 24 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../gnu/src/tx_thread_smp_time_get.S | 15 +- .../gnu/src/tx_thread_smp_unprotect.S | 19 +- .../gnu/src/tx_thread_stack_build.S | 15 +- .../gnu/src/tx_thread_system_return.S | 16 +- .../gnu/src/tx_timer_interrupt.S | 13 +- .../example_build/sample_threadx/.cproject | 146 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.scat | 26 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../ac6/example_build/sample_threadx/v8_mmu.h | 2 +- .../ac6/example_build/tx/.cproject | 186 +-- ports_smp/cortex_a35_smp/ac6/inc/tx_port.h | 18 +- .../cortex_a35_smp/ac6/readme_threadx.txt | 94 +- .../ac6/src/tx_initialize_low_level.S | 15 +- .../ac6/src/tx_thread_context_restore.S | 23 +- .../ac6/src/tx_thread_context_save.S | 19 +- .../ac6/src/tx_thread_fp_disable.c | 15 +- .../ac6/src/tx_thread_fp_enable.c | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 18 +- .../ac6/src/tx_thread_interrupt_disable.S | 18 +- .../ac6/src/tx_thread_interrupt_restore.S | 18 +- .../ac6/src/tx_thread_schedule.S | 20 +- .../ac6/src/tx_thread_smp_core_get.S | 19 +- .../ac6/src/tx_thread_smp_core_preempt.S | 19 +- .../ac6/src/tx_thread_smp_current_state_get.S | 19 +- .../src/tx_thread_smp_current_thread_get.S | 19 +- .../ac6/src/tx_thread_smp_initialize_wait.S | 19 +- .../src/tx_thread_smp_low_level_initialize.S | 18 +- .../ac6/src/tx_thread_smp_protect.S | 27 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../ac6/src/tx_thread_smp_time_get.S | 18 +- .../ac6/src/tx_thread_smp_unprotect.S | 22 +- .../ac6/src/tx_thread_stack_build.S | 18 +- .../ac6/src/tx_thread_system_return.S | 20 +- .../ac6/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 162 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.ld | 4 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../gnu/example_build/sample_threadx/v8_mmu.h | 2 +- .../gnu/example_build/tx/.cproject | 198 ++-- ports_smp/cortex_a35_smp/gnu/inc/tx_port.h | 18 +- .../cortex_a35_smp/gnu/readme_threadx.txt | 92 +- .../gnu/src/tx_initialize_low_level.S | 18 +- .../gnu/src/tx_thread_context_restore.S | 23 +- .../gnu/src/tx_thread_context_save.S | 19 +- .../gnu/src/tx_thread_fp_disable.c | 15 +- .../gnu/src/tx_thread_fp_enable.c | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 18 +- .../gnu/src/tx_thread_interrupt_disable.S | 18 +- .../gnu/src/tx_thread_interrupt_restore.S | 18 +- .../gnu/src/tx_thread_schedule.S | 20 +- .../gnu/src/tx_thread_smp_core_get.S | 19 +- .../gnu/src/tx_thread_smp_core_preempt.S | 19 +- .../gnu/src/tx_thread_smp_current_state_get.S | 19 +- .../src/tx_thread_smp_current_thread_get.S | 19 +- .../gnu/src/tx_thread_smp_initialize_wait.S | 19 +- .../src/tx_thread_smp_low_level_initialize.S | 18 +- .../gnu/src/tx_thread_smp_protect.S | 27 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../gnu/src/tx_thread_smp_time_get.S | 18 +- .../gnu/src/tx_thread_smp_unprotect.S | 22 +- .../gnu/src/tx_thread_stack_build.S | 18 +- .../gnu/src/tx_thread_system_return.S | 20 +- .../gnu/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 146 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.scat | 26 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../ac6/example_build/sample_threadx/v8_mmu.h | 2 +- .../ac6/example_build/tx/.cproject | 186 +-- ports_smp/cortex_a53_smp/ac6/inc/tx_port.h | 18 +- .../ac6/src/tx_initialize_low_level.S | 15 +- .../ac6/src/tx_thread_context_restore.S | 23 +- .../ac6/src/tx_thread_context_save.S | 19 +- .../ac6/src/tx_thread_fp_disable.c | 15 +- .../ac6/src/tx_thread_fp_enable.c | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 18 +- .../ac6/src/tx_thread_interrupt_disable.S | 18 +- .../ac6/src/tx_thread_interrupt_restore.S | 18 +- .../ac6/src/tx_thread_schedule.S | 20 +- .../ac6/src/tx_thread_smp_core_get.S | 19 +- .../ac6/src/tx_thread_smp_core_preempt.S | 19 +- .../ac6/src/tx_thread_smp_current_state_get.S | 19 +- .../src/tx_thread_smp_current_thread_get.S | 19 +- .../ac6/src/tx_thread_smp_initialize_wait.S | 19 +- .../src/tx_thread_smp_low_level_initialize.S | 18 +- .../ac6/src/tx_thread_smp_protect.S | 27 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../ac6/src/tx_thread_smp_time_get.S | 18 +- .../ac6/src/tx_thread_smp_unprotect.S | 22 +- .../ac6/src/tx_thread_stack_build.S | 18 +- .../ac6/src/tx_thread_system_return.S | 20 +- .../ac6/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 162 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.ld | 4 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../gnu/example_build/sample_threadx/v8_mmu.h | 2 +- .../gnu/example_build/tx/.cproject | 198 ++-- ports_smp/cortex_a53_smp/gnu/inc/tx_port.h | 18 +- .../gnu/src/tx_initialize_low_level.S | 18 +- .../gnu/src/tx_thread_context_restore.S | 23 +- .../gnu/src/tx_thread_context_save.S | 19 +- .../gnu/src/tx_thread_fp_disable.c | 15 +- .../gnu/src/tx_thread_fp_enable.c | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 18 +- .../gnu/src/tx_thread_interrupt_disable.S | 18 +- .../gnu/src/tx_thread_interrupt_restore.S | 18 +- .../gnu/src/tx_thread_schedule.S | 20 +- .../gnu/src/tx_thread_smp_core_get.S | 19 +- .../gnu/src/tx_thread_smp_core_preempt.S | 19 +- .../gnu/src/tx_thread_smp_current_state_get.S | 19 +- .../src/tx_thread_smp_current_thread_get.S | 19 +- .../gnu/src/tx_thread_smp_initialize_wait.S | 19 +- .../src/tx_thread_smp_low_level_initialize.S | 18 +- .../gnu/src/tx_thread_smp_protect.S | 27 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../gnu/src/tx_thread_smp_time_get.S | 18 +- .../gnu/src/tx_thread_smp_unprotect.S | 22 +- .../gnu/src/tx_thread_stack_build.S | 18 +- .../gnu/src/tx_thread_system_return.S | 20 +- .../gnu/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 146 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.scat | 26 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../ac6/example_build/sample_threadx/v8_mmu.h | 2 +- .../ac6/example_build/tx/.cproject | 186 +-- ports_smp/cortex_a55_smp/ac6/inc/tx_port.h | 18 +- .../ac6/src/tx_initialize_low_level.S | 15 +- .../ac6/src/tx_thread_context_restore.S | 23 +- .../ac6/src/tx_thread_context_save.S | 19 +- .../ac6/src/tx_thread_fp_disable.c | 15 +- .../ac6/src/tx_thread_fp_enable.c | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 18 +- .../ac6/src/tx_thread_interrupt_disable.S | 18 +- .../ac6/src/tx_thread_interrupt_restore.S | 18 +- .../ac6/src/tx_thread_schedule.S | 20 +- .../ac6/src/tx_thread_smp_core_get.S | 19 +- .../ac6/src/tx_thread_smp_core_preempt.S | 19 +- .../ac6/src/tx_thread_smp_current_state_get.S | 19 +- .../src/tx_thread_smp_current_thread_get.S | 19 +- .../ac6/src/tx_thread_smp_initialize_wait.S | 19 +- .../src/tx_thread_smp_low_level_initialize.S | 18 +- .../ac6/src/tx_thread_smp_protect.S | 27 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../ac6/src/tx_thread_smp_time_get.S | 18 +- .../ac6/src/tx_thread_smp_unprotect.S | 22 +- .../ac6/src/tx_thread_stack_build.S | 18 +- .../ac6/src/tx_thread_system_return.S | 20 +- .../ac6/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 162 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.ld | 4 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../gnu/example_build/sample_threadx/v8_mmu.h | 2 +- .../gnu/example_build/tx/.cproject | 198 ++-- ports_smp/cortex_a55_smp/gnu/inc/tx_port.h | 18 +- .../gnu/src/tx_initialize_low_level.S | 18 +- .../gnu/src/tx_thread_context_restore.S | 23 +- .../gnu/src/tx_thread_context_save.S | 19 +- .../gnu/src/tx_thread_fp_disable.c | 15 +- .../gnu/src/tx_thread_fp_enable.c | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 18 +- .../gnu/src/tx_thread_interrupt_disable.S | 18 +- .../gnu/src/tx_thread_interrupt_restore.S | 18 +- .../gnu/src/tx_thread_schedule.S | 20 +- .../gnu/src/tx_thread_smp_core_get.S | 19 +- .../gnu/src/tx_thread_smp_core_preempt.S | 19 +- .../gnu/src/tx_thread_smp_current_state_get.S | 19 +- .../src/tx_thread_smp_current_thread_get.S | 19 +- .../gnu/src/tx_thread_smp_initialize_wait.S | 19 +- .../src/tx_thread_smp_low_level_initialize.S | 18 +- .../gnu/src/tx_thread_smp_protect.S | 27 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../gnu/src/tx_thread_smp_time_get.S | 18 +- .../gnu/src/tx_thread_smp_unprotect.S | 22 +- .../gnu/src/tx_thread_stack_build.S | 18 +- .../gnu/src/tx_thread_system_return.S | 20 +- .../gnu/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 146 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.scat | 26 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../ac6/example_build/sample_threadx/v8_mmu.h | 2 +- .../ac6/example_build/tx/.cproject | 186 +-- ports_smp/cortex_a57_smp/ac6/inc/tx_port.h | 18 +- .../ac6/src/tx_initialize_low_level.S | 15 +- .../ac6/src/tx_thread_context_restore.S | 23 +- .../ac6/src/tx_thread_context_save.S | 19 +- .../ac6/src/tx_thread_fp_disable.c | 15 +- .../ac6/src/tx_thread_fp_enable.c | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 18 +- .../ac6/src/tx_thread_interrupt_disable.S | 18 +- .../ac6/src/tx_thread_interrupt_restore.S | 18 +- .../ac6/src/tx_thread_schedule.S | 20 +- .../ac6/src/tx_thread_smp_core_get.S | 19 +- .../ac6/src/tx_thread_smp_core_preempt.S | 19 +- .../ac6/src/tx_thread_smp_current_state_get.S | 19 +- .../src/tx_thread_smp_current_thread_get.S | 19 +- .../ac6/src/tx_thread_smp_initialize_wait.S | 19 +- .../src/tx_thread_smp_low_level_initialize.S | 18 +- .../ac6/src/tx_thread_smp_protect.S | 27 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../ac6/src/tx_thread_smp_time_get.S | 18 +- .../ac6/src/tx_thread_smp_unprotect.S | 22 +- .../ac6/src/tx_thread_stack_build.S | 18 +- .../ac6/src/tx_thread_system_return.S | 20 +- .../ac6/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 162 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.ld | 4 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../gnu/example_build/sample_threadx/v8_mmu.h | 2 +- .../gnu/example_build/tx/.cproject | 198 ++-- ports_smp/cortex_a57_smp/gnu/inc/tx_port.h | 18 +- .../gnu/src/tx_initialize_low_level.S | 18 +- .../gnu/src/tx_thread_context_restore.S | 23 +- .../gnu/src/tx_thread_context_save.S | 19 +- .../gnu/src/tx_thread_fp_disable.c | 15 +- .../gnu/src/tx_thread_fp_enable.c | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 18 +- .../gnu/src/tx_thread_interrupt_disable.S | 18 +- .../gnu/src/tx_thread_interrupt_restore.S | 18 +- .../gnu/src/tx_thread_schedule.S | 20 +- .../gnu/src/tx_thread_smp_core_get.S | 19 +- .../gnu/src/tx_thread_smp_core_preempt.S | 19 +- .../gnu/src/tx_thread_smp_current_state_get.S | 19 +- .../src/tx_thread_smp_current_thread_get.S | 19 +- .../gnu/src/tx_thread_smp_initialize_wait.S | 19 +- .../src/tx_thread_smp_low_level_initialize.S | 18 +- .../gnu/src/tx_thread_smp_protect.S | 27 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../gnu/src/tx_thread_smp_time_get.S | 18 +- .../gnu/src/tx_thread_smp_unprotect.S | 22 +- .../gnu/src/tx_thread_stack_build.S | 18 +- .../gnu/src/tx_thread_system_return.S | 20 +- .../gnu/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 226 ++-- .../.settings/language.settings.xml | 504 ++++---- .../ac5/example_build/sample_threadx/MP_GIC.h | 2 +- .../ac5/example_build/sample_threadx/MP_GIC.s | 14 +- .../sample_threadx/MP_GlobalTimer.h | 2 +- .../sample_threadx/MP_GlobalTimer.s | 10 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../example_build/sample_threadx/MP_Mutexes.s | 4 +- .../sample_threadx/MP_PrivateTimer.s | 2 +- .../ac5/example_build/sample_threadx/MP_SCU.h | 2 +- .../ac5/example_build/sample_threadx/MP_SCU.s | 8 +- .../sample_threadx/sample_threadx.c | 52 +- .../sample_threadx/sample_threadx.sct | 2 +- .../example_build/sample_threadx/startup.s | 12 +- .../sample_threadx/tx_initialize_low_level.s | 66 +- .../ac5/example_build/sample_threadx/v7.h | 2 +- .../ac5/example_build/sample_threadx/v7.s | 4 +- .../ac5/example_build/tx/.cproject | 200 ++-- .../tx/.settings/language.settings.xml | 504 ++++---- ports_smp/cortex_a5_smp/ac5/inc/tx_port.h | 106 +- .../cortex_a5_smp/ac5/readme_threadx.txt | 156 +-- .../ac5/src/tx_thread_context_restore.s | 72 +- .../ac5/src/tx_thread_context_save.s | 76 +- .../ac5/src/tx_thread_interrupt_control.s | 60 +- .../ac5/src/tx_thread_interrupt_disable.s | 60 +- .../ac5/src/tx_thread_interrupt_restore.s | 56 +- .../ac5/src/tx_thread_irq_nesting_end.s | 82 +- .../ac5/src/tx_thread_irq_nesting_start.s | 72 +- .../ac5/src/tx_thread_schedule.s | 76 +- .../ac5/src/tx_thread_smp_core_get.s | 60 +- .../ac5/src/tx_thread_smp_core_preempt.s | 80 +- .../ac5/src/tx_thread_smp_current_state_get.s | 60 +- .../src/tx_thread_smp_current_thread_get.s | 60 +- .../ac5/src/tx_thread_smp_initialize_wait.s | 70 +- .../src/tx_thread_smp_low_level_initialize.s | 60 +- .../ac5/src/tx_thread_smp_protect.s | 64 +- ...x_thread_smp_protection_wait_list_macros.h | 6 +- .../ac5/src/tx_thread_smp_time_get.s | 62 +- .../ac5/src/tx_thread_smp_unprotect.s | 66 +- .../ac5/src/tx_thread_stack_build.s | 60 +- .../ac5/src/tx_thread_system_return.s | 72 +- .../ac5/src/tx_thread_vectored_context_save.s | 66 +- .../ac5/src/tx_timer_interrupt.s | 74 +- .../cortex_a5_smp/gnu/example_build/MP_GIC.S | 2 +- .../cortex_a5_smp/gnu/example_build/MP_GIC.h | 2 +- .../gnu/example_build/MP_Mutexes.S | 4 +- .../gnu/example_build/MP_Mutexes.h | 2 +- .../gnu/example_build/MP_PrivateTimer.S | 2 +- .../cortex_a5_smp/gnu/example_build/MP_SCU.S | 2 +- .../cortex_a5_smp/gnu/example_build/MP_SCU.h | 2 +- .../gnu/example_build/sample_threadx.c | 52 +- .../gnu/example_build/sample_threadx.ld | 4 +- .../cortex_a5_smp/gnu/example_build/startup.S | 6 +- .../example_build/tx_initialize_low_level.s | 68 +- .../cortex_a5_smp/gnu/example_build/v7.S | 10 +- .../cortex_a5_smp/gnu/example_build/v7.h | 2 +- ports_smp/cortex_a5_smp/gnu/inc/tx_port.h | 106 +- .../cortex_a5_smp/gnu/readme_threadx.txt | 154 +-- .../gnu/src/tx_thread_context_restore.S | 94 +- .../gnu/src/tx_thread_context_save.S | 82 +- .../gnu/src/tx_thread_interrupt_control.S | 62 +- .../gnu/src/tx_thread_interrupt_disable.S | 62 +- .../gnu/src/tx_thread_interrupt_restore.S | 58 +- .../gnu/src/tx_thread_irq_nesting_end.S | 84 +- .../gnu/src/tx_thread_irq_nesting_start.S | 74 +- .../gnu/src/tx_thread_schedule.S | 96 +- .../gnu/src/tx_thread_smp_core_get.S | 62 +- .../gnu/src/tx_thread_smp_core_preempt.S | 82 +- .../gnu/src/tx_thread_smp_current_state_get.S | 62 +- .../src/tx_thread_smp_current_thread_get.S | 62 +- .../gnu/src/tx_thread_smp_initialize_wait.S | 78 +- .../src/tx_thread_smp_low_level_initialize.S | 62 +- .../gnu/src/tx_thread_smp_protect.S | 84 +- ...x_thread_smp_protection_wait_list_macros.h | 34 +- .../gnu/src/tx_thread_smp_time_get.S | 64 +- .../gnu/src/tx_thread_smp_unprotect.S | 70 +- .../gnu/src/tx_thread_stack_build.S | 62 +- .../gnu/src/tx_thread_system_return.S | 80 +- .../gnu/src/tx_thread_vectored_context_save.S | 72 +- .../gnu/src/tx_timer_interrupt.S | 86 +- .../example_build/sample_threadx/.cproject | 140 +-- .../sample_threadx/sample_threadx.sct | 26 +- .../ac6/example_build/tx/.cproject | 152 +-- ports_smp/cortex_a5x_smp/ac6/inc/tx_port.h | 21 +- .../cortex_a5x_smp/ac6/readme_threadx.txt | 94 +- .../ac6/src/tx_initialize_low_level.S | 15 +- .../ac6/src/tx_thread_context_restore.S | 19 +- .../ac6/src/tx_thread_context_save.S | 16 +- .../ac6/src/tx_thread_fp_disable.c | 15 +- .../ac6/src/tx_thread_fp_enable.c | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 15 +- .../ac6/src/tx_thread_interrupt_disable.S | 15 +- .../ac6/src/tx_thread_interrupt_restore.S | 15 +- .../ac6/src/tx_thread_schedule.S | 16 +- .../ac6/src/tx_thread_smp_core_get.S | 16 +- .../ac6/src/tx_thread_smp_core_preempt.S | 16 +- .../ac6/src/tx_thread_smp_current_state_get.S | 16 +- .../src/tx_thread_smp_current_thread_get.S | 16 +- .../ac6/src/tx_thread_smp_initialize_wait.S | 16 +- .../src/tx_thread_smp_low_level_initialize.S | 15 +- .../ac6/src/tx_thread_smp_protect.S | 24 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../ac6/src/tx_thread_smp_time_get.S | 15 +- .../ac6/src/tx_thread_smp_unprotect.S | 19 +- .../ac6/src/tx_thread_stack_build.S | 15 +- .../ac6/src/tx_thread_system_return.S | 16 +- .../ac6/src/tx_timer_interrupt.S | 15 +- .../example_build/sample_threadx/.cproject | 162 +-- .../sample_threadx/sample_threadx.ld | 4 +- .../gnu/example_build/tx/.cproject | 186 +-- ports_smp/cortex_a5x_smp/gnu/inc/tx_port.h | 18 +- .../cortex_a5x_smp/gnu/readme_threadx.txt | 92 +- .../gnu/src/tx_initialize_low_level.S | 15 +- .../gnu/src/tx_thread_context_restore.S | 19 +- .../gnu/src/tx_thread_context_save.S | 16 +- .../gnu/src/tx_thread_fp_disable.c | 15 +- .../gnu/src/tx_thread_fp_enable.c | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 15 +- .../gnu/src/tx_thread_interrupt_disable.S | 15 +- .../gnu/src/tx_thread_interrupt_restore.S | 15 +- .../gnu/src/tx_thread_schedule.S | 16 +- .../gnu/src/tx_thread_smp_core_get.S | 15 +- .../gnu/src/tx_thread_smp_core_preempt.S | 16 +- .../gnu/src/tx_thread_smp_current_state_get.S | 15 +- .../src/tx_thread_smp_current_thread_get.S | 15 +- .../gnu/src/tx_thread_smp_initialize_wait.S | 15 +- .../src/tx_thread_smp_low_level_initialize.S | 15 +- .../gnu/src/tx_thread_smp_protect.S | 24 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../gnu/src/tx_thread_smp_time_get.S | 15 +- .../gnu/src/tx_thread_smp_unprotect.S | 18 +- .../gnu/src/tx_thread_stack_build.S | 15 +- .../gnu/src/tx_thread_system_return.S | 16 +- .../gnu/src/tx_timer_interrupt.S | 15 +- .../example_build/sample_threadx/tx_boot.a64 | 6 +- .../example_build/sample_threadx/tx_zynqmp.h | 7 +- .../sample_threadx/tx_zynqmp_low_level.c | 13 +- .../green/example_build/tgt/release.gpc | 2 +- .../example_build/tgt/resource_readme.txt | 10 +- .../green/example_build/tgt/standalone_ram.ld | 2 +- .../example_build/tgt/standalone_romcopy.ld | 6 +- .../example_build/tgt/standalone_romrun.ld | 4 +- ports_smp/cortex_a5x_smp/green/inc/tx_el.h | 13 +- ports_smp/cortex_a5x_smp/green/inc/tx_port.h | 101 +- .../cortex_a5x_smp/green/readme_threadx.txt | 118 +- ports_smp/cortex_a5x_smp/green/src/tx_el.c | 13 +- .../green/src/tx_initialize_low_level.a64 | 6 +- .../green/src/tx_thread_context_restore.a64 | 82 +- .../green/src/tx_thread_context_save.a64 | 78 +- .../green/src/tx_thread_fp_disable.c | 13 +- .../green/src/tx_thread_fp_enable.c | 13 +- .../green/src/tx_thread_interrupt_control.a64 | 64 +- .../green/src/tx_thread_interrupt_disable.a64 | 62 +- .../green/src/tx_thread_interrupt_restore.a64 | 60 +- .../green/src/tx_thread_schedule.a64 | 84 +- .../green/src/tx_thread_smp_core_get.a64 | 60 +- .../green/src/tx_thread_smp_core_preempt.a64 | 6 +- .../src/tx_thread_smp_current_state_get.a64 | 56 +- .../src/tx_thread_smp_current_thread_get.a64 | 56 +- .../src/tx_thread_smp_initialize_wait.a64 | 86 +- .../tx_thread_smp_low_level_initialize.a64 | 60 +- .../green/src/tx_thread_smp_protect.a64 | 74 +- .../green/src/tx_thread_smp_time_get.a64 | 62 +- .../green/src/tx_thread_smp_unprotect.a64 | 66 +- .../green/src/tx_thread_stack_build.a64 | 62 +- .../green/src/tx_thread_system_return.a64 | 78 +- .../green/src/tx_timer_interrupt.a64 | 76 +- ports_smp/cortex_a5x_smp/iar/inc/tx_port.h | 15 +- .../cortex_a5x_smp/iar/readme_threadx.txt | 96 +- .../iar/src/tx_initialize_low_level.S | 13 +- .../iar/src/tx_thread_context_restore.S | 16 +- .../iar/src/tx_thread_context_save.S | 13 +- .../iar/src/tx_thread_fp_disable.c | 13 +- .../iar/src/tx_thread_fp_enable.c | 13 +- .../iar/src/tx_thread_interrupt_control.S | 13 +- .../iar/src/tx_thread_interrupt_disable.S | 13 +- .../iar/src/tx_thread_interrupt_restore.S | 13 +- .../iar/src/tx_thread_schedule.S | 13 +- .../iar/src/tx_thread_smp_core_get.S | 13 +- .../iar/src/tx_thread_smp_core_preempt.S | 13 +- .../iar/src/tx_thread_smp_current_state_get.S | 13 +- .../src/tx_thread_smp_current_thread_get.S | 13 +- .../iar/src/tx_thread_smp_initialize_wait.S | 13 +- .../src/tx_thread_smp_low_level_initialize.S | 13 +- .../iar/src/tx_thread_smp_protect.S | 20 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../iar/src/tx_thread_smp_time_get.S | 13 +- .../iar/src/tx_thread_smp_unprotect.S | 16 +- .../iar/src/tx_thread_stack_build.S | 13 +- .../iar/src/tx_thread_system_return.S | 13 +- .../iar/src/tx_timer_interrupt.S | 13 +- .../example_build/sample_threadx/.cproject | 146 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.scat | 26 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../ac6/example_build/sample_threadx/v8_mmu.h | 2 +- .../ac6/example_build/tx/.cproject | 186 +-- ports_smp/cortex_a65_smp/ac6/inc/tx_port.h | 18 +- .../ac6/src/tx_initialize_low_level.S | 15 +- .../ac6/src/tx_thread_context_restore.S | 23 +- .../ac6/src/tx_thread_context_save.S | 19 +- .../ac6/src/tx_thread_fp_disable.c | 15 +- .../ac6/src/tx_thread_fp_enable.c | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 18 +- .../ac6/src/tx_thread_interrupt_disable.S | 18 +- .../ac6/src/tx_thread_interrupt_restore.S | 18 +- .../ac6/src/tx_thread_schedule.S | 20 +- .../ac6/src/tx_thread_smp_core_get.S | 19 +- .../ac6/src/tx_thread_smp_core_preempt.S | 19 +- .../ac6/src/tx_thread_smp_current_state_get.S | 19 +- .../src/tx_thread_smp_current_thread_get.S | 19 +- .../ac6/src/tx_thread_smp_initialize_wait.S | 19 +- .../src/tx_thread_smp_low_level_initialize.S | 18 +- .../ac6/src/tx_thread_smp_protect.S | 27 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../ac6/src/tx_thread_smp_time_get.S | 18 +- .../ac6/src/tx_thread_smp_unprotect.S | 22 +- .../ac6/src/tx_thread_stack_build.S | 18 +- .../ac6/src/tx_thread_system_return.S | 20 +- .../ac6/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 162 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.ld | 4 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../gnu/example_build/sample_threadx/v8_mmu.h | 2 +- .../gnu/example_build/tx/.cproject | 198 ++-- ports_smp/cortex_a65_smp/gnu/inc/tx_port.h | 18 +- .../gnu/src/tx_initialize_low_level.S | 18 +- .../gnu/src/tx_thread_context_restore.S | 23 +- .../gnu/src/tx_thread_context_save.S | 19 +- .../gnu/src/tx_thread_fp_disable.c | 15 +- .../gnu/src/tx_thread_fp_enable.c | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 18 +- .../gnu/src/tx_thread_interrupt_disable.S | 18 +- .../gnu/src/tx_thread_interrupt_restore.S | 18 +- .../gnu/src/tx_thread_schedule.S | 20 +- .../gnu/src/tx_thread_smp_core_get.S | 19 +- .../gnu/src/tx_thread_smp_core_preempt.S | 19 +- .../gnu/src/tx_thread_smp_current_state_get.S | 19 +- .../src/tx_thread_smp_current_thread_get.S | 19 +- .../gnu/src/tx_thread_smp_initialize_wait.S | 19 +- .../src/tx_thread_smp_low_level_initialize.S | 18 +- .../gnu/src/tx_thread_smp_protect.S | 27 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../gnu/src/tx_thread_smp_time_get.S | 18 +- .../gnu/src/tx_thread_smp_unprotect.S | 22 +- .../gnu/src/tx_thread_stack_build.S | 18 +- .../gnu/src/tx_thread_system_return.S | 20 +- .../gnu/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 146 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.scat | 26 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../ac6/example_build/sample_threadx/v8_mmu.h | 2 +- .../ac6/example_build/tx/.cproject | 186 +-- ports_smp/cortex_a65ae_smp/ac6/inc/tx_port.h | 18 +- .../ac6/src/tx_initialize_low_level.S | 15 +- .../ac6/src/tx_thread_context_restore.S | 23 +- .../ac6/src/tx_thread_context_save.S | 19 +- .../ac6/src/tx_thread_fp_disable.c | 15 +- .../ac6/src/tx_thread_fp_enable.c | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 18 +- .../ac6/src/tx_thread_interrupt_disable.S | 18 +- .../ac6/src/tx_thread_interrupt_restore.S | 18 +- .../ac6/src/tx_thread_schedule.S | 20 +- .../ac6/src/tx_thread_smp_core_get.S | 19 +- .../ac6/src/tx_thread_smp_core_preempt.S | 19 +- .../ac6/src/tx_thread_smp_current_state_get.S | 19 +- .../src/tx_thread_smp_current_thread_get.S | 19 +- .../ac6/src/tx_thread_smp_initialize_wait.S | 19 +- .../src/tx_thread_smp_low_level_initialize.S | 18 +- .../ac6/src/tx_thread_smp_protect.S | 27 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../ac6/src/tx_thread_smp_time_get.S | 18 +- .../ac6/src/tx_thread_smp_unprotect.S | 22 +- .../ac6/src/tx_thread_stack_build.S | 18 +- .../ac6/src/tx_thread_system_return.S | 20 +- .../ac6/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 162 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.ld | 4 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../gnu/example_build/sample_threadx/v8_mmu.h | 2 +- .../gnu/example_build/tx/.cproject | 198 ++-- ports_smp/cortex_a65ae_smp/gnu/inc/tx_port.h | 18 +- .../gnu/src/tx_initialize_low_level.S | 18 +- .../gnu/src/tx_thread_context_restore.S | 23 +- .../gnu/src/tx_thread_context_save.S | 19 +- .../gnu/src/tx_thread_fp_disable.c | 15 +- .../gnu/src/tx_thread_fp_enable.c | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 18 +- .../gnu/src/tx_thread_interrupt_disable.S | 18 +- .../gnu/src/tx_thread_interrupt_restore.S | 18 +- .../gnu/src/tx_thread_schedule.S | 20 +- .../gnu/src/tx_thread_smp_core_get.S | 19 +- .../gnu/src/tx_thread_smp_core_preempt.S | 19 +- .../gnu/src/tx_thread_smp_current_state_get.S | 19 +- .../src/tx_thread_smp_current_thread_get.S | 19 +- .../gnu/src/tx_thread_smp_initialize_wait.S | 19 +- .../src/tx_thread_smp_low_level_initialize.S | 18 +- .../gnu/src/tx_thread_smp_protect.S | 27 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../gnu/src/tx_thread_smp_time_get.S | 18 +- .../gnu/src/tx_thread_smp_unprotect.S | 22 +- .../gnu/src/tx_thread_stack_build.S | 18 +- .../gnu/src/tx_thread_system_return.S | 20 +- .../gnu/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 146 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.scat | 26 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../ac6/example_build/sample_threadx/v8_mmu.h | 2 +- .../ac6/example_build/tx/.cproject | 186 +-- ports_smp/cortex_a72_smp/ac6/inc/tx_port.h | 18 +- .../ac6/src/tx_initialize_low_level.S | 15 +- .../ac6/src/tx_thread_context_restore.S | 23 +- .../ac6/src/tx_thread_context_save.S | 19 +- .../ac6/src/tx_thread_fp_disable.c | 15 +- .../ac6/src/tx_thread_fp_enable.c | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 18 +- .../ac6/src/tx_thread_interrupt_disable.S | 18 +- .../ac6/src/tx_thread_interrupt_restore.S | 18 +- .../ac6/src/tx_thread_schedule.S | 20 +- .../ac6/src/tx_thread_smp_core_get.S | 19 +- .../ac6/src/tx_thread_smp_core_preempt.S | 19 +- .../ac6/src/tx_thread_smp_current_state_get.S | 19 +- .../src/tx_thread_smp_current_thread_get.S | 19 +- .../ac6/src/tx_thread_smp_initialize_wait.S | 19 +- .../src/tx_thread_smp_low_level_initialize.S | 18 +- .../ac6/src/tx_thread_smp_protect.S | 27 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../ac6/src/tx_thread_smp_time_get.S | 18 +- .../ac6/src/tx_thread_smp_unprotect.S | 22 +- .../ac6/src/tx_thread_stack_build.S | 18 +- .../ac6/src/tx_thread_system_return.S | 20 +- .../ac6/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 162 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.ld | 4 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../gnu/example_build/sample_threadx/v8_mmu.h | 2 +- .../gnu/example_build/tx/.cproject | 198 ++-- ports_smp/cortex_a72_smp/gnu/inc/tx_port.h | 18 +- .../gnu/src/tx_initialize_low_level.S | 18 +- .../gnu/src/tx_thread_context_restore.S | 23 +- .../gnu/src/tx_thread_context_save.S | 19 +- .../gnu/src/tx_thread_fp_disable.c | 15 +- .../gnu/src/tx_thread_fp_enable.c | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 18 +- .../gnu/src/tx_thread_interrupt_disable.S | 18 +- .../gnu/src/tx_thread_interrupt_restore.S | 18 +- .../gnu/src/tx_thread_schedule.S | 20 +- .../gnu/src/tx_thread_smp_core_get.S | 19 +- .../gnu/src/tx_thread_smp_core_preempt.S | 19 +- .../gnu/src/tx_thread_smp_current_state_get.S | 19 +- .../src/tx_thread_smp_current_thread_get.S | 19 +- .../gnu/src/tx_thread_smp_initialize_wait.S | 19 +- .../src/tx_thread_smp_low_level_initialize.S | 18 +- .../gnu/src/tx_thread_smp_protect.S | 27 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../gnu/src/tx_thread_smp_time_get.S | 18 +- .../gnu/src/tx_thread_smp_unprotect.S | 22 +- .../gnu/src/tx_thread_stack_build.S | 18 +- .../gnu/src/tx_thread_system_return.S | 20 +- .../gnu/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 146 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.scat | 26 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../ac6/example_build/sample_threadx/v8_mmu.h | 2 +- .../ac6/example_build/tx/.cproject | 186 +-- ports_smp/cortex_a73_smp/ac6/inc/tx_port.h | 18 +- .../ac6/src/tx_initialize_low_level.S | 15 +- .../ac6/src/tx_thread_context_restore.S | 23 +- .../ac6/src/tx_thread_context_save.S | 19 +- .../ac6/src/tx_thread_fp_disable.c | 15 +- .../ac6/src/tx_thread_fp_enable.c | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 18 +- .../ac6/src/tx_thread_interrupt_disable.S | 18 +- .../ac6/src/tx_thread_interrupt_restore.S | 18 +- .../ac6/src/tx_thread_schedule.S | 20 +- .../ac6/src/tx_thread_smp_core_get.S | 19 +- .../ac6/src/tx_thread_smp_core_preempt.S | 19 +- .../ac6/src/tx_thread_smp_current_state_get.S | 19 +- .../src/tx_thread_smp_current_thread_get.S | 19 +- .../ac6/src/tx_thread_smp_initialize_wait.S | 19 +- .../src/tx_thread_smp_low_level_initialize.S | 18 +- .../ac6/src/tx_thread_smp_protect.S | 27 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../ac6/src/tx_thread_smp_time_get.S | 18 +- .../ac6/src/tx_thread_smp_unprotect.S | 22 +- .../ac6/src/tx_thread_stack_build.S | 18 +- .../ac6/src/tx_thread_system_return.S | 20 +- .../ac6/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 162 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.ld | 4 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../gnu/example_build/sample_threadx/v8_mmu.h | 2 +- .../gnu/example_build/tx/.cproject | 198 ++-- ports_smp/cortex_a73_smp/gnu/inc/tx_port.h | 18 +- .../gnu/src/tx_initialize_low_level.S | 18 +- .../gnu/src/tx_thread_context_restore.S | 23 +- .../gnu/src/tx_thread_context_save.S | 19 +- .../gnu/src/tx_thread_fp_disable.c | 15 +- .../gnu/src/tx_thread_fp_enable.c | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 18 +- .../gnu/src/tx_thread_interrupt_disable.S | 18 +- .../gnu/src/tx_thread_interrupt_restore.S | 18 +- .../gnu/src/tx_thread_schedule.S | 20 +- .../gnu/src/tx_thread_smp_core_get.S | 19 +- .../gnu/src/tx_thread_smp_core_preempt.S | 19 +- .../gnu/src/tx_thread_smp_current_state_get.S | 19 +- .../src/tx_thread_smp_current_thread_get.S | 19 +- .../gnu/src/tx_thread_smp_initialize_wait.S | 19 +- .../src/tx_thread_smp_low_level_initialize.S | 18 +- .../gnu/src/tx_thread_smp_protect.S | 27 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../gnu/src/tx_thread_smp_time_get.S | 18 +- .../gnu/src/tx_thread_smp_unprotect.S | 22 +- .../gnu/src/tx_thread_stack_build.S | 18 +- .../gnu/src/tx_thread_system_return.S | 20 +- .../gnu/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 146 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.scat | 26 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../ac6/example_build/sample_threadx/v8_mmu.h | 2 +- .../ac6/example_build/tx/.cproject | 186 +-- ports_smp/cortex_a75_smp/ac6/inc/tx_port.h | 18 +- .../ac6/src/tx_initialize_low_level.S | 15 +- .../ac6/src/tx_thread_context_restore.S | 23 +- .../ac6/src/tx_thread_context_save.S | 19 +- .../ac6/src/tx_thread_fp_disable.c | 15 +- .../ac6/src/tx_thread_fp_enable.c | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 18 +- .../ac6/src/tx_thread_interrupt_disable.S | 18 +- .../ac6/src/tx_thread_interrupt_restore.S | 18 +- .../ac6/src/tx_thread_schedule.S | 20 +- .../ac6/src/tx_thread_smp_core_get.S | 19 +- .../ac6/src/tx_thread_smp_core_preempt.S | 19 +- .../ac6/src/tx_thread_smp_current_state_get.S | 19 +- .../src/tx_thread_smp_current_thread_get.S | 19 +- .../ac6/src/tx_thread_smp_initialize_wait.S | 19 +- .../src/tx_thread_smp_low_level_initialize.S | 18 +- .../ac6/src/tx_thread_smp_protect.S | 27 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../ac6/src/tx_thread_smp_time_get.S | 18 +- .../ac6/src/tx_thread_smp_unprotect.S | 22 +- .../ac6/src/tx_thread_stack_build.S | 18 +- .../ac6/src/tx_thread_system_return.S | 20 +- .../ac6/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 162 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.ld | 4 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../gnu/example_build/sample_threadx/v8_mmu.h | 2 +- .../gnu/example_build/tx/.cproject | 198 ++-- ports_smp/cortex_a75_smp/gnu/inc/tx_port.h | 18 +- .../gnu/src/tx_initialize_low_level.S | 18 +- .../gnu/src/tx_thread_context_restore.S | 23 +- .../gnu/src/tx_thread_context_save.S | 19 +- .../gnu/src/tx_thread_fp_disable.c | 15 +- .../gnu/src/tx_thread_fp_enable.c | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 18 +- .../gnu/src/tx_thread_interrupt_disable.S | 18 +- .../gnu/src/tx_thread_interrupt_restore.S | 18 +- .../gnu/src/tx_thread_schedule.S | 20 +- .../gnu/src/tx_thread_smp_core_get.S | 19 +- .../gnu/src/tx_thread_smp_core_preempt.S | 19 +- .../gnu/src/tx_thread_smp_current_state_get.S | 19 +- .../src/tx_thread_smp_current_thread_get.S | 19 +- .../gnu/src/tx_thread_smp_initialize_wait.S | 19 +- .../src/tx_thread_smp_low_level_initialize.S | 18 +- .../gnu/src/tx_thread_smp_protect.S | 27 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../gnu/src/tx_thread_smp_time_get.S | 18 +- .../gnu/src/tx_thread_smp_unprotect.S | 22 +- .../gnu/src/tx_thread_stack_build.S | 18 +- .../gnu/src/tx_thread_system_return.S | 20 +- .../gnu/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 146 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.scat | 26 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../ac6/example_build/sample_threadx/v8_mmu.h | 2 +- .../ac6/example_build/tx/.cproject | 186 +-- ports_smp/cortex_a76_smp/ac6/inc/tx_port.h | 18 +- .../ac6/src/tx_initialize_low_level.S | 15 +- .../ac6/src/tx_thread_context_restore.S | 23 +- .../ac6/src/tx_thread_context_save.S | 19 +- .../ac6/src/tx_thread_fp_disable.c | 15 +- .../ac6/src/tx_thread_fp_enable.c | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 18 +- .../ac6/src/tx_thread_interrupt_disable.S | 18 +- .../ac6/src/tx_thread_interrupt_restore.S | 18 +- .../ac6/src/tx_thread_schedule.S | 20 +- .../ac6/src/tx_thread_smp_core_get.S | 19 +- .../ac6/src/tx_thread_smp_core_preempt.S | 19 +- .../ac6/src/tx_thread_smp_current_state_get.S | 19 +- .../src/tx_thread_smp_current_thread_get.S | 19 +- .../ac6/src/tx_thread_smp_initialize_wait.S | 19 +- .../src/tx_thread_smp_low_level_initialize.S | 18 +- .../ac6/src/tx_thread_smp_protect.S | 27 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../ac6/src/tx_thread_smp_time_get.S | 18 +- .../ac6/src/tx_thread_smp_unprotect.S | 22 +- .../ac6/src/tx_thread_stack_build.S | 18 +- .../ac6/src/tx_thread_system_return.S | 20 +- .../ac6/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 162 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.ld | 4 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../gnu/example_build/sample_threadx/v8_mmu.h | 2 +- .../gnu/example_build/tx/.cproject | 198 ++-- ports_smp/cortex_a76_smp/gnu/inc/tx_port.h | 18 +- .../gnu/src/tx_initialize_low_level.S | 18 +- .../gnu/src/tx_thread_context_restore.S | 23 +- .../gnu/src/tx_thread_context_save.S | 19 +- .../gnu/src/tx_thread_fp_disable.c | 15 +- .../gnu/src/tx_thread_fp_enable.c | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 18 +- .../gnu/src/tx_thread_interrupt_disable.S | 18 +- .../gnu/src/tx_thread_interrupt_restore.S | 18 +- .../gnu/src/tx_thread_schedule.S | 20 +- .../gnu/src/tx_thread_smp_core_get.S | 19 +- .../gnu/src/tx_thread_smp_core_preempt.S | 19 +- .../gnu/src/tx_thread_smp_current_state_get.S | 19 +- .../src/tx_thread_smp_current_thread_get.S | 19 +- .../gnu/src/tx_thread_smp_initialize_wait.S | 19 +- .../src/tx_thread_smp_low_level_initialize.S | 18 +- .../gnu/src/tx_thread_smp_protect.S | 27 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../gnu/src/tx_thread_smp_time_get.S | 18 +- .../gnu/src/tx_thread_smp_unprotect.S | 22 +- .../gnu/src/tx_thread_stack_build.S | 18 +- .../gnu/src/tx_thread_system_return.S | 20 +- .../gnu/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 146 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.scat | 26 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../ac6/example_build/sample_threadx/v8_mmu.h | 2 +- .../ac6/example_build/tx/.cproject | 186 +-- ports_smp/cortex_a76ae_smp/ac6/inc/tx_port.h | 18 +- .../ac6/src/tx_initialize_low_level.S | 15 +- .../ac6/src/tx_thread_context_restore.S | 23 +- .../ac6/src/tx_thread_context_save.S | 19 +- .../ac6/src/tx_thread_fp_disable.c | 15 +- .../ac6/src/tx_thread_fp_enable.c | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 18 +- .../ac6/src/tx_thread_interrupt_disable.S | 18 +- .../ac6/src/tx_thread_interrupt_restore.S | 18 +- .../ac6/src/tx_thread_schedule.S | 20 +- .../ac6/src/tx_thread_smp_core_get.S | 19 +- .../ac6/src/tx_thread_smp_core_preempt.S | 19 +- .../ac6/src/tx_thread_smp_current_state_get.S | 19 +- .../src/tx_thread_smp_current_thread_get.S | 19 +- .../ac6/src/tx_thread_smp_initialize_wait.S | 19 +- .../src/tx_thread_smp_low_level_initialize.S | 18 +- .../ac6/src/tx_thread_smp_protect.S | 27 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../ac6/src/tx_thread_smp_time_get.S | 18 +- .../ac6/src/tx_thread_smp_unprotect.S | 22 +- .../ac6/src/tx_thread_stack_build.S | 18 +- .../ac6/src/tx_thread_system_return.S | 20 +- .../ac6/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 162 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.ld | 4 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../gnu/example_build/sample_threadx/v8_mmu.h | 2 +- .../gnu/example_build/tx/.cproject | 198 ++-- ports_smp/cortex_a76ae_smp/gnu/inc/tx_port.h | 18 +- .../gnu/src/tx_initialize_low_level.S | 18 +- .../gnu/src/tx_thread_context_restore.S | 23 +- .../gnu/src/tx_thread_context_save.S | 19 +- .../gnu/src/tx_thread_fp_disable.c | 15 +- .../gnu/src/tx_thread_fp_enable.c | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 18 +- .../gnu/src/tx_thread_interrupt_disable.S | 18 +- .../gnu/src/tx_thread_interrupt_restore.S | 18 +- .../gnu/src/tx_thread_schedule.S | 20 +- .../gnu/src/tx_thread_smp_core_get.S | 19 +- .../gnu/src/tx_thread_smp_core_preempt.S | 19 +- .../gnu/src/tx_thread_smp_current_state_get.S | 19 +- .../src/tx_thread_smp_current_thread_get.S | 19 +- .../gnu/src/tx_thread_smp_initialize_wait.S | 19 +- .../src/tx_thread_smp_low_level_initialize.S | 18 +- .../gnu/src/tx_thread_smp_protect.S | 27 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../gnu/src/tx_thread_smp_time_get.S | 18 +- .../gnu/src/tx_thread_smp_unprotect.S | 22 +- .../gnu/src/tx_thread_stack_build.S | 18 +- .../gnu/src/tx_thread_system_return.S | 20 +- .../gnu/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 146 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.scat | 26 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../ac6/example_build/sample_threadx/v8_mmu.h | 2 +- .../ac6/example_build/tx/.cproject | 186 +-- ports_smp/cortex_a77_smp/ac6/inc/tx_port.h | 18 +- .../ac6/src/tx_initialize_low_level.S | 15 +- .../ac6/src/tx_thread_context_restore.S | 23 +- .../ac6/src/tx_thread_context_save.S | 19 +- .../ac6/src/tx_thread_fp_disable.c | 15 +- .../ac6/src/tx_thread_fp_enable.c | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 18 +- .../ac6/src/tx_thread_interrupt_disable.S | 18 +- .../ac6/src/tx_thread_interrupt_restore.S | 18 +- .../ac6/src/tx_thread_schedule.S | 20 +- .../ac6/src/tx_thread_smp_core_get.S | 19 +- .../ac6/src/tx_thread_smp_core_preempt.S | 19 +- .../ac6/src/tx_thread_smp_current_state_get.S | 19 +- .../src/tx_thread_smp_current_thread_get.S | 19 +- .../ac6/src/tx_thread_smp_initialize_wait.S | 19 +- .../src/tx_thread_smp_low_level_initialize.S | 18 +- .../ac6/src/tx_thread_smp_protect.S | 27 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../ac6/src/tx_thread_smp_time_get.S | 18 +- .../ac6/src/tx_thread_smp_unprotect.S | 22 +- .../ac6/src/tx_thread_stack_build.S | 18 +- .../ac6/src/tx_thread_system_return.S | 20 +- .../ac6/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 162 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.ld | 4 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../gnu/example_build/sample_threadx/v8_mmu.h | 2 +- .../gnu/example_build/tx/.cproject | 198 ++-- ports_smp/cortex_a77_smp/gnu/inc/tx_port.h | 18 +- .../gnu/src/tx_initialize_low_level.S | 18 +- .../gnu/src/tx_thread_context_restore.S | 23 +- .../gnu/src/tx_thread_context_save.S | 19 +- .../gnu/src/tx_thread_fp_disable.c | 15 +- .../gnu/src/tx_thread_fp_enable.c | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 18 +- .../gnu/src/tx_thread_interrupt_disable.S | 18 +- .../gnu/src/tx_thread_interrupt_restore.S | 18 +- .../gnu/src/tx_thread_schedule.S | 20 +- .../gnu/src/tx_thread_smp_core_get.S | 19 +- .../gnu/src/tx_thread_smp_core_preempt.S | 19 +- .../gnu/src/tx_thread_smp_current_state_get.S | 19 +- .../src/tx_thread_smp_current_thread_get.S | 19 +- .../gnu/src/tx_thread_smp_initialize_wait.S | 19 +- .../src/tx_thread_smp_low_level_initialize.S | 18 +- .../gnu/src/tx_thread_smp_protect.S | 27 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../gnu/src/tx_thread_smp_time_get.S | 18 +- .../gnu/src/tx_thread_smp_unprotect.S | 22 +- .../gnu/src/tx_thread_stack_build.S | 18 +- .../gnu/src/tx_thread_system_return.S | 20 +- .../gnu/src/tx_timer_interrupt.S | 16 +- .../example_build/sample_threadx/.cproject | 146 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.scat | 26 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../ac6/example_build/sample_threadx/v8_mmu.h | 2 +- .../ac6/example_build/tx/.cproject | 158 +-- ports_smp/cortex_a78_smp/ac6/inc/tx_port.h | 18 +- .../ac6/src/tx_initialize_low_level.S | 15 +- .../ac6/src/tx_thread_context_restore.S | 16 +- .../ac6/src/tx_thread_context_save.S | 16 +- .../ac6/src/tx_thread_fp_disable.c | 15 +- .../ac6/src/tx_thread_fp_enable.c | 15 +- .../ac6/src/tx_thread_interrupt_control.S | 15 +- .../ac6/src/tx_thread_interrupt_disable.S | 15 +- .../ac6/src/tx_thread_interrupt_restore.S | 15 +- .../ac6/src/tx_thread_schedule.S | 16 +- .../ac6/src/tx_thread_smp_core_get.S | 16 +- .../ac6/src/tx_thread_smp_core_preempt.S | 16 +- .../ac6/src/tx_thread_smp_current_state_get.S | 16 +- .../src/tx_thread_smp_current_thread_get.S | 16 +- .../ac6/src/tx_thread_smp_initialize_wait.S | 16 +- .../src/tx_thread_smp_low_level_initialize.S | 15 +- .../ac6/src/tx_thread_smp_protect.S | 17 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../ac6/src/tx_thread_smp_time_get.S | 15 +- .../ac6/src/tx_thread_smp_unprotect.S | 16 +- .../ac6/src/tx_thread_stack_build.S | 15 +- .../ac6/src/tx_thread_system_return.S | 16 +- .../ac6/src/tx_timer_interrupt.S | 13 +- .../example_build/sample_threadx/.cproject | 162 +-- .../example_build/sample_threadx/MP_Mutexes.S | 2 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- .../sample_threadx/sample_threadx.ld | 4 +- .../example_build/sample_threadx/v8_aarch64.h | 2 +- .../gnu/example_build/sample_threadx/v8_mmu.h | 2 +- .../gnu/example_build/tx/.cproject | 192 ++-- ports_smp/cortex_a78_smp/gnu/inc/tx_port.h | 18 +- .../gnu/src/tx_initialize_low_level.S | 15 +- .../gnu/src/tx_thread_context_restore.S | 16 +- .../gnu/src/tx_thread_context_save.S | 16 +- .../gnu/src/tx_thread_fp_disable.c | 15 +- .../gnu/src/tx_thread_fp_enable.c | 15 +- .../gnu/src/tx_thread_interrupt_control.S | 15 +- .../gnu/src/tx_thread_interrupt_disable.S | 15 +- .../gnu/src/tx_thread_interrupt_restore.S | 15 +- .../gnu/src/tx_thread_schedule.S | 16 +- .../gnu/src/tx_thread_smp_core_get.S | 16 +- .../gnu/src/tx_thread_smp_core_preempt.S | 16 +- .../gnu/src/tx_thread_smp_current_state_get.S | 16 +- .../src/tx_thread_smp_current_thread_get.S | 16 +- .../gnu/src/tx_thread_smp_initialize_wait.S | 16 +- .../src/tx_thread_smp_low_level_initialize.S | 15 +- .../gnu/src/tx_thread_smp_protect.S | 17 +- ...x_thread_smp_protection_wait_list_macros.h | 7 +- .../gnu/src/tx_thread_smp_time_get.S | 15 +- .../gnu/src/tx_thread_smp_unprotect.S | 16 +- .../gnu/src/tx_thread_stack_build.S | 15 +- .../gnu/src/tx_thread_system_return.S | 16 +- .../gnu/src/tx_timer_interrupt.S | 13 +- .../example_build/sample_threadx/.cproject | 226 ++-- .../.settings/language.settings.xml | 510 ++++----- .../ac5/example_build/sample_threadx/MP_GIC.h | 2 +- .../ac5/example_build/sample_threadx/MP_GIC.s | 14 +- .../example_build/sample_threadx/MP_Mutexes.h | 2 +- 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| 136 +-- .../threadx_byte_memory_information_test.c | 62 +- .../threadx_byte_memory_prioritize_test.c | 40 +- .../threadx_byte_memory_suspension_test.c | 56 +- ...eadx_byte_memory_suspension_timeout_test.c | 18 +- ...readx_byte_memory_thread_contention_test.c | 26 +- ...hreadx_byte_memory_thread_terminate_test.c | 14 +- .../threadx_event_flag_basic_test.c | 44 +- .../threadx_event_flag_information_test.c | 26 +- .../threadx_event_flag_isr_set_clear_test.c | 34 +- .../threadx_event_flag_isr_wait_abort_test.c | 32 +- ..._event_flag_single_thread_terminate_test.c | 24 +- ...readx_event_flag_suspension_consume_test.c | 18 +- ...g_suspension_different_bits_consume_test.c | 18 +- ...vent_flag_suspension_different_bits_test.c | 16 +- .../threadx_event_flag_suspension_test.c | 28 +- ...readx_event_flag_suspension_timeout_test.c | 22 +- ...threadx_event_flag_thread_terminate_test.c | 14 +- .../threadx_initialize_kernel_setup_test.c | 4 +- .../threadx_interrupt_control_test.c | 6 +- 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102 +- .../threadx_queue_full_suspension_test.c | 38 +- .../threadx_queue_information_test.c | 70 +- .../smp/regression/threadx_queue_prioritize.c | 46 +- .../threadx_queue_suspension_timeout_test.c | 20 +- .../threadx_queue_thread_terminate_test.c | 12 +- .../regression/threadx_semaphore_basic_test.c | 20 +- .../threadx_semaphore_ceiling_put_test.c | 40 +- .../threadx_semaphore_delete_test.c | 14 +- .../threadx_semaphore_information_test.c | 22 +- .../threadx_semaphore_non_preemption_test.c | 26 +- .../threadx_semaphore_preemption_test.c | 10 +- .../regression/threadx_semaphore_prioritize.c | 44 +- .../threadx_semaphore_thread_terminate_test.c | 16 +- .../threadx_semaphore_timeout_test.c | 8 +- ...readx_smp_multiple_threads_one_core_test.c | 50 +- .../threadx_smp_non_trivial_scheduling_test.c | 52 +- ...dx_smp_one_thread_dynamic_exclusion_test.c | 6 +- .../threadx_smp_preemption_threshold_test.c | 116 +- ..._random_resume_suspend_exclusion_pt_test.c | 112 +- ...smp_random_resume_suspend_exclusion_test.c | 72 +- .../threadx_smp_random_resume_suspend_test.c | 60 +- .../threadx_smp_rebalance_exclusion_test.c | 28 +- .../regression/threadx_smp_relinquish_test.c | 74 +- ..._smp_resume_suspend_accending_order_test.c | 276 ++--- ..._smp_resume_suspend_decending_order_test.c | 276 ++--- .../regression/threadx_smp_time_slice_test.c | 70 +- .../threadx_smp_two_threads_one_core_test.c | 54 +- .../threadx_thread_basic_execution_test.c | 156 +-- .../threadx_thread_basic_time_slice_test.c | 16 +- .../threadx_thread_completed_test.c | 48 +- ..._thread_create_preemption_threshold_test.c | 12 +- .../threadx_thread_delayed_suspension_test.c | 54 +- .../threadx_thread_information_test.c | 112 +- ...ad_multi_level_preemption_threshold_test.c | 174 +-- ...threadx_thread_multiple_non_current_test.c | 26 +- .../threadx_thread_multiple_sleep_test.c | 16 +- .../threadx_thread_multiple_suspension_test.c | 48 +- .../threadx_thread_multiple_time_slice_test.c | 38 +- ...readx_thread_preemptable_suspension_test.c | 46 +- .../threadx_thread_preemption_change_test.c | 70 +- .../threadx_thread_priority_change.c | 90 +- .../threadx_thread_relinquish_test.c | 66 +- .../regression/threadx_thread_reset_test.c | 32 +- ...readx_thread_simple_sleep_non_clear_test.c | 8 +- .../threadx_thread_simple_sleep_test.c | 4 +- .../threadx_thread_simple_suspend_test.c | 10 +- .../threadx_thread_sleep_for_100ticks_test.c | 54 +- .../threadx_thread_sleep_terminate_test.c | 16 +- .../threadx_thread_stack_checking_test.c | 24 +- .../threadx_thread_terminate_delete_test.c | 24 +- .../threadx_thread_time_slice_change_test.c | 10 +- .../threadx_thread_wait_abort_and_isr_test.c | 22 +- .../threadx_thread_wait_abort_test.c | 8 +- .../regression/threadx_time_get_set_test.c | 6 +- .../threadx_timer_activate_deactivate_test.c | 28 +- .../threadx_timer_deactivate_accuracy_test.c | 6 +- .../threadx_timer_information_test.c | 84 +- .../threadx_timer_large_timer_accuracy_test.c | 6 +- .../threadx_timer_multiple_accuracy_test.c | 4 +- .../regression/threadx_timer_multiple_test.c | 6 +- .../regression/threadx_timer_simple_test.c | 180 +-- .../smp/regression/threadx_trace_basic_test.c | 78 +- test/tx/regression/testcontrol.c | 196 ++-- .../threadx_block_memory_basic_test.c | 38 +- ...hreadx_block_memory_error_detection_test.c | 10 +- .../threadx_block_memory_information_test.c | 84 +- .../threadx_block_memory_prioritize_test.c | 50 +- .../threadx_block_memory_suspension_test.c | 26 +- ...adx_block_memory_suspension_timeout_test.c | 16 +- ...readx_block_memory_thread_terminate_test.c | 12 +- .../threadx_byte_memory_basic_test.c | 136 +-- .../threadx_byte_memory_information_test.c | 62 +- .../threadx_byte_memory_prioritize_test.c | 40 +- .../threadx_byte_memory_suspension_test.c | 56 +- ...eadx_byte_memory_suspension_timeout_test.c | 18 +- ...readx_byte_memory_thread_contention_test.c | 26 +- ...hreadx_byte_memory_thread_terminate_test.c | 14 +- .../threadx_event_flag_basic_test.c | 44 +- .../threadx_event_flag_information_test.c | 26 +- .../threadx_event_flag_isr_set_clear_test.c | 34 +- .../threadx_event_flag_isr_wait_abort_test.c | 32 +- ..._event_flag_single_thread_terminate_test.c | 24 +- ...readx_event_flag_suspension_consume_test.c | 18 +- ...g_suspension_different_bits_consume_test.c | 18 +- ...vent_flag_suspension_different_bits_test.c | 16 +- .../threadx_event_flag_suspension_test.c | 28 +- ...readx_event_flag_suspension_timeout_test.c | 22 +- ...threadx_event_flag_thread_terminate_test.c | 14 +- .../threadx_initialize_kernel_setup_test.c | 2 +- .../threadx_interrupt_control_test.c | 6 +- test/tx/regression/threadx_mutex_basic_test.c | 68 +- .../tx/regression/threadx_mutex_delete_test.c | 12 +- .../threadx_mutex_information_test.c | 22 +- ...x_mutex_nested_priority_inheritance_test.c | 116 +- .../threadx_mutex_no_preemption_test.c | 8 +- .../threadx_mutex_preemption_test.c | 8 +- .../threadx_mutex_priority_inheritance_test.c | 100 +- .../regression/threadx_mutex_proritize_test.c | 76 +- .../threadx_mutex_suspension_timeout_test.c | 56 +- .../threadx_mutex_thread_terminate_test.c | 12 +- .../threadx_queue_basic_eight_word_test.c | 24 +- .../threadx_queue_basic_four_word_test.c | 24 +- ...hreadx_queue_basic_max_message_size_test.c | 24 +- .../threadx_queue_basic_one_word_test.c | 80 +- .../threadx_queue_basic_sixteen_word_test.c | 24 +- .../threadx_queue_basic_two_word_test.c | 26 +- .../threadx_queue_empty_suspension_test.c | 22 +- .../threadx_queue_flush_no_suspension_test.c | 6 +- test/tx/regression/threadx_queue_flush_test.c | 16 +- .../threadx_queue_front_send_test.c | 102 +- .../threadx_queue_full_suspension_test.c | 38 +- .../threadx_queue_information_test.c | 70 +- test/tx/regression/threadx_queue_prioritize.c | 46 +- .../threadx_queue_suspension_timeout_test.c | 20 +- .../threadx_queue_thread_terminate_test.c | 12 +- .../regression/threadx_semaphore_basic_test.c | 20 +- .../threadx_semaphore_ceiling_put_test.c | 40 +- .../threadx_semaphore_delete_test.c | 14 +- .../threadx_semaphore_information_test.c | 22 +- .../threadx_semaphore_non_preemption_test.c | 26 +- .../threadx_semaphore_preemption_test.c | 10 +- .../regression/threadx_semaphore_prioritize.c | 44 +- .../threadx_semaphore_thread_terminate_test.c | 16 +- .../threadx_semaphore_timeout_test.c | 8 +- .../threadx_thread_basic_execution_test.c | 212 ++-- .../threadx_thread_basic_time_slice_test.c | 6 +- .../threadx_thread_completed_test.c | 48 +- ..._thread_create_preemption_threshold_test.c | 12 +- .../threadx_thread_delayed_suspension_test.c | 54 +- .../threadx_thread_information_test.c | 112 +- ...ad_multi_level_preemption_threshold_test.c | 174 +-- ...threadx_thread_multiple_non_current_test.c | 26 +- .../threadx_thread_multiple_sleep_test.c | 16 +- .../threadx_thread_multiple_suspension_test.c | 48 +- .../threadx_thread_multiple_time_slice_test.c | 38 +- ...readx_thread_preemptable_suspension_test.c | 46 +- .../threadx_thread_preemption_change_test.c | 72 +- .../threadx_thread_priority_change.c | 52 +- .../threadx_thread_relinquish_test.c | 18 +- .../tx/regression/threadx_thread_reset_test.c | 32 +- ...readx_thread_simple_sleep_non_clear_test.c | 8 +- .../threadx_thread_simple_sleep_test.c | 4 +- .../threadx_thread_simple_suspend_test.c | 10 +- .../threadx_thread_sleep_for_100ticks_test.c | 54 +- .../threadx_thread_sleep_terminate_test.c | 16 +- .../threadx_thread_stack_checking_test.c | 24 +- .../threadx_thread_terminate_delete_test.c | 24 +- .../threadx_thread_time_slice_change_test.c | 10 +- .../threadx_thread_wait_abort_and_isr_test.c | 22 +- .../threadx_thread_wait_abort_test.c | 8 +- .../tx/regression/threadx_time_get_set_test.c | 6 +- .../threadx_timer_activate_deactivate_test.c | 28 +- .../threadx_timer_deactivate_accuracy_test.c | 6 +- .../threadx_timer_information_test.c | 84 +- .../threadx_timer_large_timer_accuracy_test.c | 6 +- .../threadx_timer_multiple_accuracy_test.c | 4 +- .../regression/threadx_timer_multiple_test.c | 6 +- .../tx/regression/threadx_timer_simple_test.c | 108 +- test/tx/regression/threadx_trace_basic_test.c | 74 +- .../thread_metric/thread_metric_readme.txt | 138 +-- .../tm_porting_layer_threadx.c | 35 +- utility/benchmarks/thread_metric/tm_api.h | 49 +- .../thread_metric/tm_basic_processing_test.c | 53 +- .../tm_cooperative_scheduling_test.c | 59 +- .../tm_interrupt_preemption_processing_test.c | 57 +- .../tm_interrupt_processing_test.c | 55 +- .../thread_metric/tm_memory_allocation_test.c | 45 +- .../tm_message_processing_test.c | 47 +- .../thread_metric/tm_porting_layer.h | 13 +- .../thread_metric/tm_porting_layer_template.c | 29 +- .../tm_preemptive_scheduling_test.c | 55 +- .../tm_synchronization_processing_test.c | 45 +- .../smp_version/tx_execution_profile.c | 195 ++-- .../smp_version/tx_execution_profile.h | 25 +- .../tx_execution_profile.c | 137 ++- .../tx_execution_profile.h | 21 +- utility/low_power/tx_low_power.c | 24 +- utility/low_power/tx_low_power.h | 13 +- .../FreeRTOS/FreeRTOS.h | 17 +- .../FreeRTOS/config_template/FreeRTOSConfig.h | 16 +- .../FreeRTOS/event_groups.h | 13 +- .../FreeRTOS/queue.h | 13 +- .../FreeRTOS/readme.md | 182 +-- .../FreeRTOS/revision_history.txt | 6 +- .../FreeRTOS/semphr.h | 13 +- .../rtos_compatibility_layers/FreeRTOS/task.h | 13 +- .../FreeRTOS/timers.h | 13 +- .../FreeRTOS/tx_freertos.c | 27 +- .../OSEK/demo_osek.c | 16 +- utility/rtos_compatibility_layers/OSEK/os.h | 14 +- .../OSEK/osek_user.h | 13 +- .../OSEK/threadx_osek_readme.txt | 106 +- .../rtos_compatibility_layers/OSEK/tx_osek.c | 13 +- .../rtos_compatibility_layers/posix/errno.h | 16 +- .../rtos_compatibility_layers/posix/fcntl.h | 62 +- .../posix/posix_demo.c | 44 +- .../posix/posix_signal_nested_test.c | 30 +- .../posix/posix_signal_resume_thread_test.c | 48 +- .../posix/posix_signal_self_send_test.c | 54 +- .../posix/posix_signal_sigmask_test.c | 84 +- .../posix/posix_signal_sigwait_test.c | 58 +- .../posix_signal_suspended_thread_test.c | 44 +- .../rtos_compatibility_layers/posix/pthread.h | 14 +- .../posix/px_abs_time_to_rel_ticks.c | 19 +- .../posix/px_clock_getres.c | 51 +- .../posix/px_clock_gettime.c | 55 +- .../posix/px_clock_settime.c | 51 +- .../posix/px_cond_broadcast.c | 57 +- .../posix/px_cond_destroy.c | 55 +- .../posix/px_cond_init.c | 55 +- .../posix/px_cond_signal.c | 47 +- .../posix/px_cond_timedwait.c | 63 +- .../posix/px_cond_wait.c | 61 +- .../posix/px_error.c | 73 +- .../posix/px_in_thread_context.c | 23 +- .../rtos_compatibility_layers/posix/px_int.h | 26 +- .../posix/px_internal_signal_dispatch.c | 45 +- .../posix/px_memory_allocate.c | 21 +- .../posix/px_memory_release.c | 29 +- .../posix/px_mq_arrange_msg.c | 22 +- .../posix/px_mq_attr_init.c | 19 +- .../posix/px_mq_close.c | 27 +- .../posix/px_mq_create.c | 31 +- .../posix/px_mq_find_queue.c | 17 +- .../posix/px_mq_get_new_queue.c | 37 +- .../posix/px_mq_get_queue_desc.c | 17 +- .../posix/px_mq_open.c | 27 +- .../posix/px_mq_priority_search.c | 15 +- .../posix/px_mq_putback_queue.c | 17 +- .../posix/px_mq_queue_delete.c | 17 +- .../posix/px_mq_queue_init.c | 17 +- .../posix/px_mq_receive.c | 45 +- .../posix/px_mq_reset_queue.c | 17 +- .../posix/px_mq_send.c | 45 +- .../posix/px_mq_unlink.c | 17 +- .../posix/px_mx_attr_destroy.c | 63 +- .../posix/px_mx_attr_getprotocol.c | 57 +- .../posix/px_mx_attr_getpshared.c | 57 +- .../posix/px_mx_attr_gettype.c | 57 +- .../posix/px_mx_attr_initi.c | 61 +- .../posix/px_mx_attr_setprotocol.c | 61 +- .../posix/px_mx_attr_setpshared.c | 61 +- .../posix/px_mx_attr_settype.c | 61 +- .../posix/px_mx_destroy.c | 61 +- .../posix/px_mx_init.c | 77 +- .../posix/px_mx_lock.c | 61 +- .../posix/px_mx_set_default_mutexattr.c | 63 +- .../posix/px_mx_timedlock.c | 57 +- .../posix/px_mx_trylock.c | 63 +- .../posix/px_mx_unlock.c | 61 +- .../posix/px_nanosleep.c | 19 +- .../posix/px_pth_attr_destroy.c | 63 +- .../posix/px_pth_attr_getdetachstate.c | 65 +- .../posix/px_pth_attr_getinheritsched.c | 63 +- .../posix/px_pth_attr_getschedparam.c | 63 +- .../posix/px_pth_attr_getschedpolicy.c | 63 +- .../posix/px_pth_attr_getstack.c | 77 +- .../posix/px_pth_attr_getstackaddr.c | 65 +- .../posix/px_pth_attr_getstacksize.c | 63 +- .../posix/px_pth_attr_init.c | 61 +- .../posix/px_pth_attr_setdetachstate.c | 65 +- .../posix/px_pth_attr_setinheritsched.c | 61 +- .../posix/px_pth_attr_setschedparam.c | 63 +- .../posix/px_pth_attr_setschedpolicyl.c | 63 +- .../posix/px_pth_attr_setstack.c | 77 +- .../posix/px_pth_attr_setstackaddr.c | 65 +- .../posix/px_pth_attr_setstacksize.c | 59 +- .../posix/px_pth_cancel.c | 37 +- .../posix/px_pth_create.c | 100 +- .../posix/px_pth_detach.c | 25 +- .../posix/px_pth_equal.c | 21 +- .../posix/px_pth_exit.c | 37 +- .../posix/px_pth_getcanceltype.c | 77 +- .../posix/px_pth_getschedparam.c | 63 +- .../posix/px_pth_init.c | 1015 ++++++++--------- .../posix/px_pth_join.c | 35 +- .../posix/px_pth_kill.c | 86 +- .../posix/px_pth_once.c | 21 +- .../posix/px_pth_self.c | 39 +- .../posix/px_pth_set_default_pthread_attr.c | 63 +- .../posix/px_pth_setcancelstate.c | 73 +- .../posix/px_pth_setcanceltype.c | 77 +- .../posix/px_pth_setschedparam.c | 59 +- .../posix/px_pth_sigmask.c | 58 +- .../posix/px_pth_testcancel.c | 27 +- .../posix/px_pth_yield.c | 51 +- .../posix/px_px_initialize.c | 49 +- .../posix/px_sched_get_prio.c | 17 +- .../posix/px_sched_yield.c | 17 +- .../posix/px_sem_close.c | 17 +- .../posix/px_sem_destroy.c | 19 +- .../posix/px_sem_find_sem.c | 19 +- .../posix/px_sem_get_new_sem.c | 19 +- .../posix/px_sem_getvalue.c | 19 +- .../posix/px_sem_init.c | 19 +- .../posix/px_sem_open.c | 27 +- .../posix/px_sem_post.c | 17 +- .../posix/px_sem_reset.c | 17 +- .../posix/px_sem_set_sem_name.c | 17 +- .../posix/px_sem_trywait.c | 17 +- .../posix/px_sem_unlink.c | 21 +- .../posix/px_sem_wait.c | 17 +- .../posix/px_sig_addset.c | 21 +- .../posix/px_sig_delset.c | 21 +- .../posix/px_sig_emptyset.c | 19 +- .../posix/px_sig_fillset.c | 19 +- .../posix/px_sig_signal.c | 23 +- .../posix/px_sig_wait.c | 51 +- .../posix/px_sleep.c | 49 +- .../posix/px_system_manager.c | 67 +- .../posix/readme_release_history.txt | 12 +- .../posix/readme_threadx_posix.txt | 62 +- .../rtos_compatibility_layers/posix/sched.h | 16 +- .../rtos_compatibility_layers/posix/signal.h | 35 +- .../rtos_compatibility_layers/posix/time.h | 18 +- .../posix/tx_posix.h | 101 +- .../posix/tx_px_time.h | 16 +- 5970 files changed, 90237 insertions(+), 124072 deletions(-) diff --git a/.github/workflows/ci_cortex_m.yml b/.github/workflows/ci_cortex_m.yml index 57e1149b..149490be 100644 --- a/.github/workflows/ci_cortex_m.yml +++ b/.github/workflows/ci_cortex_m.yml @@ -47,7 +47,7 @@ jobs: path: $HOME/arm-none-eabi-gcc-9-2019-q4 key: ${{ runner.os }}-arm-gcc-9-2019-q4 - # Get the arm-non-eabi-gcc toolchain + # Get the arm-non-eabi-gcc toolchain - name: Install arm-none-eabi-gcc uses: fiam/arm-none-eabi-gcc@v1 if: steps.cache-arm-gcc.outputs.cache-hit != 'true' diff --git a/.github/workflows/regression_template.yml b/.github/workflows/regression_template.yml index f2b529f6..205eb5a8 100644 --- a/.github/workflows/regression_template.yml +++ b/.github/workflows/regression_template.yml @@ -56,7 +56,7 @@ jobs: issues: read checks: write pull-requests: write - + # The type of runner that the job will run on runs-on: ubuntu-latest @@ -66,7 +66,7 @@ jobs: uses: actions/checkout@v4.2.2 with: submodules: true - + - name: Install softwares run: ${{ inputs.install_script }} @@ -75,7 +75,7 @@ jobs: - name: Test run: ${{ inputs.test_script }} - + - name: Publish Test Results uses: EnricoMi/publish-unit-test-result-action@v2.11.0 if: always() @@ -83,7 +83,7 @@ jobs: check_name: Test Results ${{ inputs.result_affix }} files: | ${{ inputs.cmake_path }}/build/*/*.xml - + - name: Upload Test Results if: success() || failure() uses: actions/upload-artifact@v4.6.2 @@ -93,7 +93,7 @@ jobs: ${{ inputs.cmake_path }}/build/*.txt ${{ inputs.cmake_path }}/build/*/Testing/**/*.xml ${{ inputs.cmake_path }}/build/**/regression/output_files/*.bin - + - name: Configure GitHub Pages uses: actions/configure-pages@v5.0.0 @@ -158,7 +158,7 @@ jobs: if: (!inputs.skip_deploy && !inputs.skip_coverage) with: path: ${{ inputs.cmake_path }}/coverage_report/${{ inputs.coverage_name }} - + deploy_code_coverage: runs-on: ubuntu-latest if: ((github.event_name == 'push') || (github.event_name == 'workflow_dispatch')) && !inputs.skip_coverage && !inputs.skip_deploy && !failure() && !cancelled() @@ -183,7 +183,7 @@ jobs: with: path: . - - name: Delete Duplicate Code Coverage Artifact + - name: Delete Duplicate Code Coverage Artifact uses: geekyeggo/delete-artifact@v5.1.0 with: name: coverage_report @@ -195,7 +195,7 @@ jobs: - name: Write Code Coverage Report URL run: >- if [ "${{ inputs.deploy_list }}" != "" ]; then - for i in ${{ inputs.deploy_list }}; do + for i in ${{ inputs.deploy_list }}; do echo 'Coverage report for ' $i ':${{ steps.deployment.outputs.page_url }}'$i >> $GITHUB_STEP_SUMMARY done else diff --git a/.gitignore b/.gitignore index 16aa71ad..d2216ddb 100644 --- a/.gitignore +++ b/.gitignore @@ -1,6 +1,7 @@ .vscode/ .settings/ .metadata/ +.tmp/ _deps/ build/ Debug/ diff --git a/CHANGELOG.md b/CHANGELOG.md index 2d63cb0d..f3c5e5d2 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -200,7 +200,7 @@ | Cleanup | Closed | 6.1.3 | Updates to use builtins/inline assembler | ports/cortex_m23/gnu/inc/tx_port.h
ports/cortex_m23/gnu/src/tx_thread_secure_stack.c | 08/01/2021 | Scott Larson | | Cleanup | Closed | 6.1.3 | Remove unnecessary settings directories from example. | ports/cortex_a35/ac6/** | 08/01/2021 | Scott Larson | | Cleanup | Closed | 6.1.3 | Remove unneeded load of _tx_thread_preempt_disable. | ports/arc_em/metaware/src/tx_timer_interrupt.s
ports/arc_hs/metaware/src/tx_timer_interrupt.s | 08/01/2021 | Scott Larson | -| Enhancement | Closed | 6.1.3 | Update product constants.
MISRA compliance changes | common_smp/inc/tx_api.h
common_smp/src/tx_thread_create.c
common_smp/src/tx_time_get.c
common_smp/src/tx_thread_smp_high_level_initialize.c | 08/01/2021 | Scott Larson | +| Enhancement | Closed | 6.1.3 | Update product constants.
MISRA compliance changes | common_smp/inc/tx_api.h
common_smp/src/tx_thread_create.c
common_smp/src/tx_time_get.c
common_smp/src/tx_thread_smp_high_level_initialize.c | 08/01/2021 | Scott Larson | | New feature | Closed | 6.1.3 | Pre-execution module preamble validation and preparation | common_modules/module_manager/src/txm_module_manager_start.c
common_modules/module_manager/src/txm_module_manager_absolute_load.c | 08/01/2021 | Scott Larson | | Enhancement | Closed | 6.1.3 | Added port-specific dispathc. | common/inc/tx_api.h | 08/01/2021 | Scott Larson | | Enhancement | Closed | 6.1.3 | Fix stack overlap checking.
Added 64-bit & SMP support. | common_modules/module_manager/src/txm_module_manager_thread_create.c | 08/01/2021 | Scott Larson | diff --git a/CMakeLists.txt b/CMakeLists.txt index 42c328fd..9d348e68 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -49,10 +49,10 @@ if (NOT TX_USER_FILE) set(TX_USER_FILE ${CMAKE_CURRENT_LIST_DIR}/common/inc/tx_user_sample.h) else() message(STATUS "Using custom tx_user.h file from ${TX_USER_FILE}") -endif() +endif() configure_file(${TX_USER_FILE} ${CUSTOM_INC_DIR}/tx_user.h COPYONLY) -target_include_directories(${PROJECT_NAME} - PUBLIC +target_include_directories(${PROJECT_NAME} + PUBLIC ${CUSTOM_INC_DIR} ) target_compile_definitions(${PROJECT_NAME} PUBLIC "TX_INCLUDE_USER_DEFINE_FILE" ) diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index a327a0bc..7dfafcac 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -6,7 +6,7 @@ Thanks for your interest in this project. Eclipse ThreadX provides a vendor-neutral, open source, safety certified OS for real-time applications published on under a permissive license. The Eclipse -ThreadX suite encompasses: +ThreadX suite encompasses: * ThreadX - advanced real-time operating system (RTOS) designed specifically for deeply embedded applications * NetX Duo - advanced, industrial-grade TCP/IP network stack designed specifically for deeply embedded real-time and IoT applications * FileX - high-performance, FAT-compatible file system that’s fully integrated with ThreadX kernel @@ -20,7 +20,7 @@ Project site: https://projects.eclipse.org/projects/iot.threadx ## Terms of Use -This repository is subject to the Terms of Use of the Eclipse Foundation +This repository is subject to the Terms of Use of the Eclipse Foundation https://www.eclipse.org/legal/termsofuse.php ## Developer resources @@ -54,7 +54,7 @@ Development Process and operates under the terms of the Eclipse IP Policy. ## Eclipse Contributor Agreement -In order to be able to contribute to Eclipse Foundation projects you must electronically sign the Eclipse Contributor Agreement (ECA). +In order to be able to contribute to Eclipse Foundation projects you must electronically sign the Eclipse Contributor Agreement (ECA). https://www.eclipse.org/legal/ECA.php The ECA provides the Eclipse Foundation with a permanent record that you agree @@ -63,10 +63,10 @@ the Developer Certificate of Origin (DCO). Having an ECA on file associated with the email address matching the "Author" field of your contribution's Git commits fulfills the DCO's requirement that you sign-off on your contributions. -For more information, please see the Eclipse Committer Handbook: +For more information, please see the Eclipse Committer Handbook: https://www.eclipse.org/projects/handbook/#resources-commit ## Contact -Contact the project developers via the project's "dev" list. +Contact the project developers via the project's "dev" list. https://accounts.eclipse.org/mailing-list/threadx-dev diff --git a/README.md b/README.md index b3c3e456..260a77a3 100644 --- a/README.md +++ b/README.md @@ -12,7 +12,7 @@ Eclipse ThreadX has been integrated to the semiconductor's SDKs and development We also provide [getting started guide](https://github.com/eclipse-threadx/getting-started) and [samples](https://github.com/eclipse-threadx/samples) using development boards from semiconductors you can build and test with. -See [Overview of Eclipse ThreadX RTOS](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/threadx/overview-threadx.md) for the high-level overview. +See [Overview of Eclipse ThreadX RTOS](https://github.com/eclipse-threadx/rtos-docs/blob/main/rtos-docs/threadx/overview-threadx.md) for the high-level overview. ## Repository Structure and Usage ### Directory layout @@ -23,8 +23,8 @@ See [Overview of Eclipse ThreadX RTOS](https://github.com/eclipse-threadx/rtos-d ├── common_modules # Core ThreadX module files ├── common_smp # Core ThreadX SMP files ├── docs # Documentation supplements - ├── ports # Architecture and compiler specific files. See below for directory breakdown - │ ├── cortex_m7 + ├── ports # Architecture and compiler specific files. See below for directory breakdown + │ ├── cortex_m7 │ │ ├── iar # Example IAR compiler sample project │ │ │ ├── example build # IAR workspace and sample project files │ │ │ ├── inc # tx_port.h for this architecture @@ -32,7 +32,7 @@ See [Overview of Eclipse ThreadX RTOS](https://github.com/eclipse-threadx/rtos-d │ │ ├── ac6 # Example ac6/Keil sample project │ │ ├── gnu # Example gnu sample project │ │ └── ... - │ └── ... + │ └── ... ├── ports_modules # Architecture and compiler specific files for threadX modules ├── ports_smp # Architecture and compiler specific files for threadX SMP ├── samples # demo_threadx.c @@ -87,7 +87,7 @@ The master branch has the most recent code with all new features and bug fixes. /* xx-xx-xxxx Scott Larson Include tx_user.h, */ /* resulting in version 6.x */ /* */ -/**************************************************************************/ +/**************************************************************************/ ``` ## Supported Architecture Ports @@ -97,8 +97,8 @@ The master branch has the most recent code with all new features and bug fixes. arc_em cortex_a12 cortex_m0 cortex_r4 arc_hs cortex_a15 cortex_m23 cortex_r5 arm11 cortex_a17 cortex_m3 cortex_r7 -arm9 cortex_a34 cortex_m33 -c667x cortex_a35 cortex_m4 +arm9 cortex_a34 cortex_m33 +c667x cortex_a35 cortex_m4 linux cortex_a5 cortex_m55 risc-v32 cortex_a53 cortex_m7 rxv1 cortex_a55 cortex_m85 diff --git a/common/CMakeLists.txt b/common/CMakeLists.txt index 715e64c7..51314c95 100644 --- a/common/CMakeLists.txt +++ b/common/CMakeLists.txt @@ -201,9 +201,9 @@ target_sources(${PROJECT_NAME} ) # Add the Common/inc directory to the project include list -target_include_directories(${PROJECT_NAME} +target_include_directories(${PROJECT_NAME} SYSTEM - PUBLIC + PUBLIC ${CMAKE_CURRENT_LIST_DIR}/inc ) diff --git a/common/inc/tx_api.h b/common/inc/tx_api.h index 4224c7e6..7527c413 100644 --- a/common/inc/tx_api.h +++ b/common/inc/tx_api.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -38,78 +39,6 @@ /* Please note that basic data type definitions and other architecture-*/ /* specific information is contained in the file tx_port.h. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 William E. Lamie Modified comment(s), and */ -/* updated product constants, */ -/* added new thread execution */ -/* state TX_PRIORITY_CHANGE, */ -/* added macros for casting */ -/* pointers to ALIGN_TYPE, */ -/* resulting in version 6.1 */ -/* 10-16-2020 William E. Lamie Modified comment(s), and */ -/* increased patch version, */ -/* resulting in version 6.1.1 */ -/* 11-09-2020 Yuxin Zhou Modified comment(s), and */ -/* moved TX_THREAD_GET_SYSTEM_ */ -/* STATE to tx_api.h, */ -/* resulting in version 6.1.2 */ -/* 12-31-2020 William E. Lamie Modified comment(s), and */ -/* increased patch version, */ -/* resulting in version 6.1.3 */ -/* 03-02-2021 Scott Larson Modified comment(s), and */ -/* order defines numerically, */ -/* add option to remove FileX */ -/* pointer, */ -/* resulting in version 6.1.5 */ -/* 04-02-2021 Scott Larson Modified comment(s), and */ -/* update patch number, */ -/* resulting in version 6.1.6 */ -/* 06-02-2021 Yuxin Zhou Modified comment(s), added */ -/* Execution Profile support, */ -/* resulting in version 6.1.7 */ -/* 08-02-2021 Scott Larson Modified comment(s), and */ -/* update patch number, */ -/* resulting in version 6.1.8 */ -/* 10-15-2021 Yuxin Zhou Modified comment(s), */ -/* update patch number, */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), */ -/* add unused parameter macro, */ -/* update patch number, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Wenhui Xie Modified comment(s), */ -/* optimized the definition of */ -/* TX_TIMER_TICKS_PER_SECOND, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comment(s), */ -/* update patch number, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Modified comment(s), */ -/* add extension macros, */ -/* update EPK typedef, */ -/* update version numbers, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Tiejun Zhou Modified comment(s), */ -/* update patch number, */ -/* resulting in version 6.2.1 */ -/* 10-31-2023 Xiuwen Cai Modified comment(s), */ -/* added option for random */ -/* number stack filling, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Tiejun Zhou Modified comment(s), */ -/* update version number, */ -/* resulting in version 6.4.0 */ -/* 03-01-2024 Tiejun Zhou Modified comment(s), */ -/* update version number, */ -/* resulting in version 6.4.1 */ -/* 02-19-2025 Frédéric Desbiens Modified comment(s), */ -/* update version number, */ -/* resulting in version 6.4.2 */ -/* */ /**************************************************************************/ #ifndef TX_API_H @@ -147,9 +76,9 @@ extern "C" { #define AZURE_RTOS_THREADX #define THREADX_MAJOR_VERSION 6 -#define THREADX_MINOR_VERSION 4 -#define THREADX_PATCH_VERSION 5 -#define THREADX_BUILD_VERSION 202504 +#define THREADX_MINOR_VERSION 5 +#define THREADX_PATCH_VERSION 0 +#define THREADX_BUILD_VERSION 202601 #define THREADX_HOTFIX_VERSION ' ' /* Define the following symbol for backward compatibility */ diff --git a/common/inc/tx_block_pool.h b/common/inc/tx_block_pool.h index 2a8bb51e..89c9dfbe 100644 --- a/common/inc/tx_block_pool.h +++ b/common/inc/tx_block_pool.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,14 +37,6 @@ /* including all data types and external references. It is assumed */ /* that tx_api.h and tx_port.h have already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_BLOCK_POOL_H diff --git a/common/inc/tx_byte_pool.h b/common/inc/tx_byte_pool.h index 8f1050fa..b9f34311 100644 --- a/common/inc/tx_byte_pool.h +++ b/common/inc/tx_byte_pool.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,14 +37,6 @@ /* including all data types and external references. It is assumed */ /* that tx_api.h and tx_port.h have already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_BYTE_POOL_H diff --git a/common/inc/tx_event_flags.h b/common/inc/tx_event_flags.h index 51e99536..6506dd13 100644 --- a/common/inc/tx_event_flags.h +++ b/common/inc/tx_event_flags.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,14 +37,6 @@ /* including all data types and external references. It is assumed */ /* that tx_api.h and tx_port.h have already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_EVENT_FLAGS_H diff --git a/common/inc/tx_initialize.h b/common/inc/tx_initialize.h index 28c7251b..fd944965 100644 --- a/common/inc/tx_initialize.h +++ b/common/inc/tx_initialize.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,14 +37,6 @@ /* data types and external references. It is assumed that tx_api.h */ /* and tx_port.h have already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_INITIALIZE_H diff --git a/common/inc/tx_mutex.h b/common/inc/tx_mutex.h index a3b52386..b0b46c2f 100644 --- a/common/inc/tx_mutex.h +++ b/common/inc/tx_mutex.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,14 +37,6 @@ /* including all data types and external references. It is assumed */ /* that tx_api.h and tx_port.h have already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_MUTEX_H diff --git a/common/inc/tx_queue.h b/common/inc/tx_queue.h index 7074a91e..c8b4122c 100644 --- a/common/inc/tx_queue.h +++ b/common/inc/tx_queue.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,14 +37,6 @@ /* including all data types and external references. It is assumed */ /* that tx_api.h and tx_port.h have already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_QUEUE_H diff --git a/common/inc/tx_semaphore.h b/common/inc/tx_semaphore.h index 6784e58f..baf292bd 100644 --- a/common/inc/tx_semaphore.h +++ b/common/inc/tx_semaphore.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,14 +37,6 @@ /* including all data types and external references. It is assumed */ /* that tx_api.h and tx_port.h have already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_SEMAPHORE_H diff --git a/common/inc/tx_thread.h b/common/inc/tx_thread.h index 8729263d..5ba8b3f5 100644 --- a/common/inc/tx_thread.h +++ b/common/inc/tx_thread.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,21 +37,6 @@ /* data types and external references. It is assumed that tx_api.h */ /* and tx_port.h have already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* 11-09-2020 Yuxin Zhou Modified comment(s), and */ -/* moved TX_THREAD_GET_SYSTEM_ */ -/* STATE to tx_api.h, */ -/* resulting in version 6.1.2 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ -/* stack check error handling, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ #ifndef TX_THREAD_H diff --git a/common/inc/tx_timer.h b/common/inc/tx_timer.h index 4703b14d..b49c573e 100644 --- a/common/inc/tx_timer.h +++ b/common/inc/tx_timer.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,14 +37,6 @@ /* data types and external references. It is assumed that tx_api.h */ /* and tx_port.h have already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_TIMER_H diff --git a/common/inc/tx_trace.h b/common/inc/tx_trace.h index dd78580e..d85d5cc3 100644 --- a/common/inc/tx_trace.h +++ b/common/inc/tx_trace.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,14 +36,6 @@ /* and structure definitions as well as external references. It is */ /* assumed that tx_api.h and tx_port.h have already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ diff --git a/common/inc/tx_user_sample.h b/common/inc/tx_user_sample.h index f8d809b5..9621c30c 100644 --- a/common/inc/tx_user_sample.h +++ b/common/inc/tx_user_sample.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -39,33 +40,6 @@ /* Note that all the defines in this file may also be made on the */ /* command line when building ThreadX library and application objects. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* 03-02-2021 Scott Larson Modified comment(s), */ -/* added option to remove */ -/* FileX pointer, */ -/* resulting in version 6.1.5 */ -/* 06-02-2021 Scott Larson Added options for multiple */ -/* block pool search & delay, */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 Yuxin Zhou Modified comment(s), added */ -/* user-configurable symbol */ -/* TX_TIMER_TICKS_PER_SECOND */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Wenhui Xie Modified comment(s), */ -/* optimized the definition of */ -/* TX_TIMER_TICKS_PER_SECOND, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Xiuwen Cai Modified comment(s), */ -/* added option for random */ -/* number stack filling, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #ifndef TX_USER_H @@ -182,7 +156,7 @@ /* Determine if random number is used for stack filling. By default, ThreadX uses a fixed pattern for stack filling. When the following is defined, ThreadX uses a random number - for stack filling. This is effective only when TX_ENABLE_STACK_CHECKING is defined. */ + for stack filling. This is effective only when TX_ENABLE_STACK_CHECKING is defined. */ /* #define TX_ENABLE_RANDOM_NUMBER_STACK_FILLING diff --git a/common/src/tx_block_allocate.c b/common/src/tx_block_allocate.c index b2c7bef5..78619603 100644 --- a/common/src/tx_block_allocate.c +++ b/common/src/tx_block_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,14 +68,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_block_allocate(TX_BLOCK_POOL *pool_ptr, VOID **block_ptr, ULONG wait_option) { diff --git a/common/src/tx_block_pool_cleanup.c b/common/src/tx_block_pool_cleanup.c index 9bae546d..7bcfecd8 100644 --- a/common/src/tx_block_pool_cleanup.c +++ b/common/src/tx_block_pool_cleanup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* _tx_thread_terminate Thread terminate processing */ /* _tx_thread_wait_abort Thread wait abort processing */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_block_pool_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) { diff --git a/common/src/tx_block_pool_create.c b/common/src/tx_block_pool_create.c index 54612019..1d2c803c 100644 --- a/common/src/tx_block_pool_create.c +++ b/common/src/tx_block_pool_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_block_pool_create(TX_BLOCK_POOL *pool_ptr, CHAR *name_ptr, ULONG block_size, VOID *pool_start, ULONG pool_size) diff --git a/common/src/tx_block_pool_delete.c b/common/src/tx_block_pool_delete.c index da27ef57..19ecb055 100644 --- a/common/src/tx_block_pool_delete.c +++ b/common/src/tx_block_pool_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_block_pool_delete(TX_BLOCK_POOL *pool_ptr) { diff --git a/common/src/tx_block_pool_info_get.c b/common/src/tx_block_pool_info_get.c index aebd0db6..5998f1db 100644 --- a/common/src/tx_block_pool_info_get.c +++ b/common/src/tx_block_pool_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,14 +68,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_block_pool_info_get(TX_BLOCK_POOL *pool_ptr, CHAR **name, ULONG *available_blocks, ULONG *total_blocks, TX_THREAD **first_suspended, diff --git a/common/src/tx_block_pool_initialize.c b/common/src/tx_block_pool_initialize.c index 21132159..e01eba32 100644 --- a/common/src/tx_block_pool_initialize.c +++ b/common/src/tx_block_pool_initialize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -97,17 +98,6 @@ ULONG _tx_block_pool_performance_timeout_count; /* */ /* _tx_initialize_high_level High level initialization */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* opt out of function when */ -/* TX_INLINE_INITIALIZATION is */ -/* defined, */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_block_pool_initialize(VOID) { diff --git a/common/src/tx_block_pool_performance_info_get.c b/common/src/tx_block_pool_performance_info_get.c index 84f68026..aecf7851 100644 --- a/common/src/tx_block_pool_performance_info_get.c +++ b/common/src/tx_block_pool_performance_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,14 +71,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_block_pool_performance_info_get(TX_BLOCK_POOL *pool_ptr, ULONG *allocates, ULONG *releases, ULONG *suspensions, ULONG *timeouts) diff --git a/common/src/tx_block_pool_performance_system_info_get.c b/common/src/tx_block_pool_performance_system_info_get.c index 0707295d..86627dd0 100644 --- a/common/src/tx_block_pool_performance_system_info_get.c +++ b/common/src/tx_block_pool_performance_system_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,14 +68,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_block_pool_performance_system_info_get(ULONG *allocates, ULONG *releases, ULONG *suspensions, ULONG *timeouts) { diff --git a/common/src/tx_block_pool_prioritize.c b/common/src/tx_block_pool_prioritize.c index c4ee4e94..89c2d634 100644 --- a/common/src/tx_block_pool_prioritize.c +++ b/common/src/tx_block_pool_prioritize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_block_pool_prioritize(TX_BLOCK_POOL *pool_ptr) { diff --git a/common/src/tx_block_release.c b/common/src/tx_block_release.c index 3b94c1bb..4a11fe08 100644 --- a/common/src/tx_block_release.c +++ b/common/src/tx_block_release.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_block_release(VOID *block_ptr) { diff --git a/common/src/tx_byte_allocate.c b/common/src/tx_byte_allocate.c index 69e837e3..2e1a2e5e 100644 --- a/common/src/tx_byte_allocate.c +++ b/common/src/tx_byte_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -69,14 +70,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_byte_allocate(TX_BYTE_POOL *pool_ptr, VOID **memory_ptr, ULONG memory_size, ULONG wait_option) { diff --git a/common/src/tx_byte_pool_cleanup.c b/common/src/tx_byte_pool_cleanup.c index a1260c5b..3a7acd54 100644 --- a/common/src/tx_byte_pool_cleanup.c +++ b/common/src/tx_byte_pool_cleanup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* _tx_thread_terminate Thread terminate processing */ /* _tx_thread_wait_abort Thread wait abort processing */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_byte_pool_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) { diff --git a/common/src/tx_byte_pool_create.c b/common/src/tx_byte_pool_create.c index 439eed7c..21abbe35 100644 --- a/common/src/tx_byte_pool_create.c +++ b/common/src/tx_byte_pool_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_byte_pool_create(TX_BYTE_POOL *pool_ptr, CHAR *name_ptr, VOID *pool_start, ULONG pool_size) { diff --git a/common/src/tx_byte_pool_delete.c b/common/src/tx_byte_pool_delete.c index fc3d9be1..3a24705f 100644 --- a/common/src/tx_byte_pool_delete.c +++ b/common/src/tx_byte_pool_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,14 +69,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_byte_pool_delete(TX_BYTE_POOL *pool_ptr) { diff --git a/common/src/tx_byte_pool_info_get.c b/common/src/tx_byte_pool_info_get.c index 339aa771..bd096440 100644 --- a/common/src/tx_byte_pool_info_get.c +++ b/common/src/tx_byte_pool_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,14 +68,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_byte_pool_info_get(TX_BYTE_POOL *pool_ptr, CHAR **name, ULONG *available_bytes, ULONG *fragments, TX_THREAD **first_suspended, diff --git a/common/src/tx_byte_pool_initialize.c b/common/src/tx_byte_pool_initialize.c index 65514536..652ec829 100644 --- a/common/src/tx_byte_pool_initialize.c +++ b/common/src/tx_byte_pool_initialize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -112,17 +113,6 @@ ULONG _tx_byte_pool_performance_timeout_count; /* */ /* _tx_initialize_high_level High level initialization */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* opt out of function when */ -/* TX_INLINE_INITIALIZATION is */ -/* defined, */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_byte_pool_initialize(VOID) { diff --git a/common/src/tx_byte_pool_performance_info_get.c b/common/src/tx_byte_pool_performance_info_get.c index 400804a2..6c2fd615 100644 --- a/common/src/tx_byte_pool_performance_info_get.c +++ b/common/src/tx_byte_pool_performance_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -78,14 +79,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_byte_pool_performance_info_get(TX_BYTE_POOL *pool_ptr, ULONG *allocates, ULONG *releases, ULONG *fragments_searched, ULONG *merges, ULONG *splits, ULONG *suspensions, ULONG *timeouts) diff --git a/common/src/tx_byte_pool_performance_system_info_get.c b/common/src/tx_byte_pool_performance_system_info_get.c index 266e2767..23f41c47 100644 --- a/common/src/tx_byte_pool_performance_system_info_get.c +++ b/common/src/tx_byte_pool_performance_system_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -75,14 +76,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_byte_pool_performance_system_info_get(ULONG *allocates, ULONG *releases, ULONG *fragments_searched, ULONG *merges, ULONG *splits, ULONG *suspensions, ULONG *timeouts) diff --git a/common/src/tx_byte_pool_prioritize.c b/common/src/tx_byte_pool_prioritize.c index 0076e503..dc2ecc03 100644 --- a/common/src/tx_byte_pool_prioritize.c +++ b/common/src/tx_byte_pool_prioritize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_byte_pool_prioritize(TX_BYTE_POOL *pool_ptr) { diff --git a/common/src/tx_byte_pool_search.c b/common/src/tx_byte_pool_search.c index 504ad745..408f6587 100644 --- a/common/src/tx_byte_pool_search.c +++ b/common/src/tx_byte_pool_search.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,17 +72,6 @@ /* _tx_byte_allocate Allocate bytes of memory */ /* _tx_byte_release Release bytes of memory */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* 06-02-2021 Scott Larson Improve possible free bytes */ -/* calculation, */ -/* resulting in version 6.1.7 */ -/* */ /**************************************************************************/ UCHAR *_tx_byte_pool_search(TX_BYTE_POOL *pool_ptr, ULONG memory_size) { diff --git a/common/src/tx_byte_release.c b/common/src/tx_byte_release.c index 387320ba..b56665ed 100644 --- a/common/src/tx_byte_release.c +++ b/common/src/tx_byte_release.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_byte_release(VOID *memory_ptr) { diff --git a/common/src/tx_event_flags_cleanup.c b/common/src/tx_event_flags_cleanup.c index 3f870564..ac7bc68b 100644 --- a/common/src/tx_event_flags_cleanup.c +++ b/common/src/tx_event_flags_cleanup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* _tx_thread_terminate Thread terminate processing */ /* _tx_thread_wait_abort Thread wait abort processing */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_event_flags_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) { diff --git a/common/src/tx_event_flags_create.c b/common/src/tx_event_flags_create.c index 2195527a..2a9c042d 100644 --- a/common/src/tx_event_flags_create.c +++ b/common/src/tx_event_flags_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_event_flags_create(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR *name_ptr) { diff --git a/common/src/tx_event_flags_delete.c b/common/src/tx_event_flags_delete.c index 2b7c890a..777f2491 100644 --- a/common/src/tx_event_flags_delete.c +++ b/common/src/tx_event_flags_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_event_flags_delete(TX_EVENT_FLAGS_GROUP *group_ptr) { diff --git a/common/src/tx_event_flags_get.c b/common/src/tx_event_flags_get.c index 4e9abb80..3136d159 100644 --- a/common/src/tx_event_flags_get.c +++ b/common/src/tx_event_flags_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,20 +69,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* 04-25-2022 Scott Larson Modified comment(s), */ -/* handle 0 flags case, */ -/* resulting in version 6.1.11 */ -/* 10-31-2022 Scott Larson Modified comment(s), always */ -/* return actual flags, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ UINT _tx_event_flags_get(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG requested_flags, UINT get_option, ULONG *actual_flags_ptr, ULONG wait_option) diff --git a/common/src/tx_event_flags_info_get.c b/common/src/tx_event_flags_info_get.c index 9d409bc5..21e85c9a 100644 --- a/common/src/tx_event_flags_info_get.c +++ b/common/src/tx_event_flags_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -69,14 +70,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_event_flags_info_get(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR **name, ULONG *current_flags, TX_THREAD **first_suspended, ULONG *suspended_count, diff --git a/common/src/tx_event_flags_initialize.c b/common/src/tx_event_flags_initialize.c index f7b107c8..d5cd72b9 100644 --- a/common/src/tx_event_flags_initialize.c +++ b/common/src/tx_event_flags_initialize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -98,17 +99,6 @@ ULONG _tx_event_flags_performance_timeout_count; /* */ /* _tx_initialize_high_level High level initialization */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* opt out of function when */ -/* TX_INLINE_INITIALIZATION is */ -/* defined, */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_event_flags_initialize(VOID) { diff --git a/common/src/tx_event_flags_performance_info_get.c b/common/src/tx_event_flags_performance_info_get.c index c0529b03..213c2d2a 100644 --- a/common/src/tx_event_flags_performance_info_get.c +++ b/common/src/tx_event_flags_performance_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,14 +72,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_event_flags_performance_info_get(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG *sets, ULONG *gets, ULONG *suspensions, ULONG *timeouts) diff --git a/common/src/tx_event_flags_performance_system_info_get.c b/common/src/tx_event_flags_performance_system_info_get.c index 3f1570df..4902b0e1 100644 --- a/common/src/tx_event_flags_performance_system_info_get.c +++ b/common/src/tx_event_flags_performance_system_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,14 +69,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_event_flags_performance_system_info_get(ULONG *sets, ULONG *gets, ULONG *suspensions, ULONG *timeouts) { diff --git a/common/src/tx_event_flags_set.c b/common/src/tx_event_flags_set.c index 8309be14..749343c8 100644 --- a/common/src/tx_event_flags_set.c +++ b/common/src/tx_event_flags_set.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,18 +68,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* 04-25-2022 William E. Lamie Modified comment(s), and */ -/* added corrected preemption */ -/* check logic, resulting in */ -/* version 6.1.11 */ -/* */ /**************************************************************************/ UINT _tx_event_flags_set(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG flags_to_set, UINT set_option) { @@ -336,8 +325,8 @@ VOID (*events_set_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *notify_ /* Disable preemption while we process the suspended list. */ _tx_thread_preempt_disable++; - /* Since we have temporarily disabled preemption globally, set the preempt - check flag to check for any preemption condition - including from + /* Since we have temporarily disabled preemption globally, set the preempt + check flag to check for any preemption condition - including from unrelated ISR processing. */ preempt_check = TX_TRUE; diff --git a/common/src/tx_event_flags_set_notify.c b/common/src/tx_event_flags_set_notify.c index ab2b9a1c..4cafdd57 100644 --- a/common/src/tx_event_flags_set_notify.c +++ b/common/src/tx_event_flags_set_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_event_flags_set_notify(TX_EVENT_FLAGS_GROUP *group_ptr, VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)) { diff --git a/common/src/tx_initialize_high_level.c b/common/src/tx_initialize_high_level.c index b7224551..77bc3ed7 100644 --- a/common/src/tx_initialize_high_level.c +++ b/common/src/tx_initialize_high_level.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -100,14 +101,6 @@ VOID *_tx_initialize_unused_memory; /* is optionally called by */ /* compiler's startup code. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_initialize_high_level(VOID) { diff --git a/common/src/tx_initialize_kernel_enter.c b/common/src/tx_initialize_kernel_enter.c index e5eda61e..20dc3017 100644 --- a/common/src/tx_initialize_kernel_enter.c +++ b/common/src/tx_initialize_kernel_enter.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,21 +83,6 @@ TX_SAFETY_CRITICAL_EXCEPTION_HANDLER /* */ /* main Application main program */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* 04-25-2022 Scott Larson Modified comment(s), */ -/* added EPK initialization, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Xiuwen Cai Modified comment(s), */ -/* added random generator */ -/* initialization, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ VOID _tx_initialize_kernel_enter(VOID) { diff --git a/common/src/tx_initialize_kernel_setup.c b/common/src/tx_initialize_kernel_setup.c index d61e9318..7a698ba8 100644 --- a/common/src/tx_initialize_kernel_setup.c +++ b/common/src/tx_initialize_kernel_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* startup code Compiler startup code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_initialize_kernel_setup(VOID) { diff --git a/common/src/tx_misra.c b/common/src/tx_misra.c index 90533b96..9abf12f0 100644 --- a/common/src/tx_misra.c +++ b/common/src/tx_misra.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -32,7 +33,7 @@ #include "tx_api.h" #else #define TX_THREAD_INIT -//CHAR _tx_version_id[100] = "Copyright (c) 2024 Microsoft Corporation. * ThreadX 6.1 MISRA C Compliant *"; +//CHAR _tx_version_id[100] = "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX 6.1 MISRA C Compliant *"; #include "tx_api.h" #include "tx_thread.h" diff --git a/common/src/tx_mutex_cleanup.c b/common/src/tx_mutex_cleanup.c index 09acbf4d..d32f69fc 100644 --- a/common/src/tx_mutex_cleanup.c +++ b/common/src/tx_mutex_cleanup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* _tx_thread_terminate Thread terminate processing */ /* _tx_thread_wait_abort Thread wait abort processing */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_mutex_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) { diff --git a/common/src/tx_mutex_create.c b/common/src/tx_mutex_create.c index 993bf344..436c01f5 100644 --- a/common/src/tx_mutex_create.c +++ b/common/src/tx_mutex_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_mutex_create(TX_MUTEX *mutex_ptr, CHAR *name_ptr, UINT inherit) { diff --git a/common/src/tx_mutex_delete.c b/common/src/tx_mutex_delete.c index ca5aeca8..9c0a5aac 100644 --- a/common/src/tx_mutex_delete.c +++ b/common/src/tx_mutex_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_mutex_delete(TX_MUTEX *mutex_ptr) { diff --git a/common/src/tx_mutex_get.c b/common/src/tx_mutex_get.c index 91e97f14..402a0f0d 100644 --- a/common/src/tx_mutex_get.c +++ b/common/src/tx_mutex_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_mutex_get(TX_MUTEX *mutex_ptr, ULONG wait_option) { diff --git a/common/src/tx_mutex_info_get.c b/common/src/tx_mutex_info_get.c index 219bcc18..a24d1e30 100644 --- a/common/src/tx_mutex_info_get.c +++ b/common/src/tx_mutex_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,14 +69,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_mutex_info_get(TX_MUTEX *mutex_ptr, CHAR **name, ULONG *count, TX_THREAD **owner, TX_THREAD **first_suspended, ULONG *suspended_count, diff --git a/common/src/tx_mutex_initialize.c b/common/src/tx_mutex_initialize.c index ea2ca458..98460cd6 100644 --- a/common/src/tx_mutex_initialize.c +++ b/common/src/tx_mutex_initialize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -107,17 +108,6 @@ ULONG _tx_mutex_performance__priority_inheritance_count; /* */ /* _tx_initialize_high_level High level initialization */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* opt out of function when */ -/* TX_INLINE_INITIALIZATION is */ -/* defined, */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_mutex_initialize(VOID) { diff --git a/common/src/tx_mutex_performance_info_get.c b/common/src/tx_mutex_performance_info_get.c index 501a417a..0704c111 100644 --- a/common/src/tx_mutex_performance_info_get.c +++ b/common/src/tx_mutex_performance_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -73,14 +74,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_mutex_performance_info_get(TX_MUTEX *mutex_ptr, ULONG *puts, ULONG *gets, ULONG *suspensions, ULONG *timeouts, ULONG *inversions, ULONG *inheritances) diff --git a/common/src/tx_mutex_performance_system_info_get.c b/common/src/tx_mutex_performance_system_info_get.c index 9ca17197..458a5945 100644 --- a/common/src/tx_mutex_performance_system_info_get.c +++ b/common/src/tx_mutex_performance_system_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,14 +73,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_mutex_performance_system_info_get(ULONG *puts, ULONG *gets, ULONG *suspensions, ULONG *timeouts, ULONG *inversions, ULONG *inheritances) diff --git a/common/src/tx_mutex_prioritize.c b/common/src/tx_mutex_prioritize.c index 3006b7d0..6522307d 100644 --- a/common/src/tx_mutex_prioritize.c +++ b/common/src/tx_mutex_prioritize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_mutex_prioritize(TX_MUTEX *mutex_ptr) { diff --git a/common/src/tx_mutex_priority_change.c b/common/src/tx_mutex_priority_change.c index 4f9679ef..846e1a54 100644 --- a/common/src/tx_mutex_priority_change.c +++ b/common/src/tx_mutex_priority_change.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,23 +66,6 @@ /* _tx_mutex_get Inherit priority */ /* _tx_mutex_put Restore previous priority */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 William E. Lamie Modified comment(s), and */ -/* change thread state from */ -/* TX_SUSPENDED to */ -/* TX_PRIORITY_CHANGE before */ -/* calling */ -/* _tx_thread_system_suspend, */ -/* resulting in version 6.1 */ -/* 04-02-2021 Scott Larson Modified comments, fixed */ -/* mapping current thread's */ -/* priority rather than next, */ -/* resulting in version 6.1.6 */ -/* */ /**************************************************************************/ VOID _tx_mutex_priority_change(TX_THREAD *thread_ptr, UINT new_priority) { diff --git a/common/src/tx_mutex_put.c b/common/src/tx_mutex_put.c index 6ac5065d..062472a2 100644 --- a/common/src/tx_mutex_put.c +++ b/common/src/tx_mutex_put.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,14 +68,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_mutex_put(TX_MUTEX *mutex_ptr) { diff --git a/common/src/tx_queue_cleanup.c b/common/src/tx_queue_cleanup.c index 82d02f45..05a423b3 100644 --- a/common/src/tx_queue_cleanup.c +++ b/common/src/tx_queue_cleanup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* _tx_thread_terminate Thread terminate processing */ /* _tx_thread_wait_abort Thread wait abort processing */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_queue_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) { diff --git a/common/src/tx_queue_create.c b/common/src/tx_queue_create.c index 00edbad9..59ae154e 100644 --- a/common/src/tx_queue_create.c +++ b/common/src/tx_queue_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_queue_create(TX_QUEUE *queue_ptr, CHAR *name_ptr, UINT message_size, VOID *queue_start, ULONG queue_size) diff --git a/common/src/tx_queue_delete.c b/common/src/tx_queue_delete.c index 9887b160..6a2bcf6f 100644 --- a/common/src/tx_queue_delete.c +++ b/common/src/tx_queue_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_queue_delete(TX_QUEUE *queue_ptr) { diff --git a/common/src/tx_queue_flush.c b/common/src/tx_queue_flush.c index 5120c898..b721cf50 100644 --- a/common/src/tx_queue_flush.c +++ b/common/src/tx_queue_flush.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_queue_flush(TX_QUEUE *queue_ptr) { diff --git a/common/src/tx_queue_front_send.c b/common/src/tx_queue_front_send.c index 5e8b4104..bb39b970 100644 --- a/common/src/tx_queue_front_send.c +++ b/common/src/tx_queue_front_send.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,14 +68,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_queue_front_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option) { diff --git a/common/src/tx_queue_info_get.c b/common/src/tx_queue_info_get.c index 3b37b37f..d0ecb2b6 100644 --- a/common/src/tx_queue_info_get.c +++ b/common/src/tx_queue_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,14 +68,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_queue_info_get(TX_QUEUE *queue_ptr, CHAR **name, ULONG *enqueued, ULONG *available_storage, TX_THREAD **first_suspended, ULONG *suspended_count, TX_QUEUE **next_queue) diff --git a/common/src/tx_queue_initialize.c b/common/src/tx_queue_initialize.c index 7a811234..eb34f18b 100644 --- a/common/src/tx_queue_initialize.c +++ b/common/src/tx_queue_initialize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -105,17 +106,6 @@ ULONG _tx_queue_performance_timeout_count; /* */ /* _tx_initialize_high_level High level initialization */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* opt out of function when */ -/* TX_INLINE_INITIALIZATION is */ -/* defined, */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_queue_initialize(VOID) { diff --git a/common/src/tx_queue_performance_info_get.c b/common/src/tx_queue_performance_info_get.c index 721a7e5f..7c426515 100644 --- a/common/src/tx_queue_performance_info_get.c +++ b/common/src/tx_queue_performance_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,14 +73,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_queue_performance_info_get(TX_QUEUE *queue_ptr, ULONG *messages_sent, ULONG *messages_received, ULONG *empty_suspensions, ULONG *full_suspensions, ULONG *full_errors, ULONG *timeouts) diff --git a/common/src/tx_queue_performance_system_info_get.c b/common/src/tx_queue_performance_system_info_get.c index 87cfb4a6..306c97a2 100644 --- a/common/src/tx_queue_performance_system_info_get.c +++ b/common/src/tx_queue_performance_system_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,14 +73,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_queue_performance_system_info_get(ULONG *messages_sent, ULONG *messages_received, ULONG *empty_suspensions, ULONG *full_suspensions, ULONG *full_errors, ULONG *timeouts) diff --git a/common/src/tx_queue_prioritize.c b/common/src/tx_queue_prioritize.c index 4f875078..dbea0a6b 100644 --- a/common/src/tx_queue_prioritize.c +++ b/common/src/tx_queue_prioritize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_queue_prioritize(TX_QUEUE *queue_ptr) { diff --git a/common/src/tx_queue_receive.c b/common/src/tx_queue_receive.c index 31a22f94..a6ab0390 100644 --- a/common/src/tx_queue_receive.c +++ b/common/src/tx_queue_receive.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -69,14 +70,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_queue_receive(TX_QUEUE *queue_ptr, VOID *destination_ptr, ULONG wait_option) { diff --git a/common/src/tx_queue_send.c b/common/src/tx_queue_send.c index 3ca970a0..7d22f5b9 100644 --- a/common/src/tx_queue_send.c +++ b/common/src/tx_queue_send.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,14 +68,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_queue_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option) { diff --git a/common/src/tx_queue_send_notify.c b/common/src/tx_queue_send_notify.c index f46d153a..05af2f03 100644 --- a/common/src/tx_queue_send_notify.c +++ b/common/src/tx_queue_send_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_queue_send_notify(TX_QUEUE *queue_ptr, VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)) { diff --git a/common/src/tx_semaphore_ceiling_put.c b/common/src/tx_semaphore_ceiling_put.c index a72b094a..9b02e731 100644 --- a/common/src/tx_semaphore_ceiling_put.c +++ b/common/src/tx_semaphore_ceiling_put.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_semaphore_ceiling_put(TX_SEMAPHORE *semaphore_ptr, ULONG ceiling) { diff --git a/common/src/tx_semaphore_cleanup.c b/common/src/tx_semaphore_cleanup.c index 512f6c60..0e3cd965 100644 --- a/common/src/tx_semaphore_cleanup.c +++ b/common/src/tx_semaphore_cleanup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* _tx_thread_terminate Thread terminate processing */ /* _tx_thread_wait_abort Thread wait abort processing */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_semaphore_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) { diff --git a/common/src/tx_semaphore_create.c b/common/src/tx_semaphore_create.c index 3acf3f41..849f5d3b 100644 --- a/common/src/tx_semaphore_create.c +++ b/common/src/tx_semaphore_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_semaphore_create(TX_SEMAPHORE *semaphore_ptr, CHAR *name_ptr, ULONG initial_count) { diff --git a/common/src/tx_semaphore_delete.c b/common/src/tx_semaphore_delete.c index eee19755..8a0515a0 100644 --- a/common/src/tx_semaphore_delete.c +++ b/common/src/tx_semaphore_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_semaphore_delete(TX_SEMAPHORE *semaphore_ptr) { diff --git a/common/src/tx_semaphore_get.c b/common/src/tx_semaphore_get.c index 5a471997..52802da1 100644 --- a/common/src/tx_semaphore_get.c +++ b/common/src/tx_semaphore_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_semaphore_get(TX_SEMAPHORE *semaphore_ptr, ULONG wait_option) { diff --git a/common/src/tx_semaphore_info_get.c b/common/src/tx_semaphore_info_get.c index 70e98a71..89fd9423 100644 --- a/common/src/tx_semaphore_info_get.c +++ b/common/src/tx_semaphore_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,14 +68,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_semaphore_info_get(TX_SEMAPHORE *semaphore_ptr, CHAR **name, ULONG *current_value, TX_THREAD **first_suspended, ULONG *suspended_count, diff --git a/common/src/tx_semaphore_initialize.c b/common/src/tx_semaphore_initialize.c index 84358cc5..d2b169df 100644 --- a/common/src/tx_semaphore_initialize.c +++ b/common/src/tx_semaphore_initialize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -97,17 +98,6 @@ ULONG _tx_semaphore_performance_timeout_count; /* */ /* _tx_initialize_high_level High level initialization */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* opt out of function when */ -/* TX_INLINE_INITIALIZATION is */ -/* defined, */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_semaphore_initialize(VOID) { diff --git a/common/src/tx_semaphore_performance_info_get.c b/common/src/tx_semaphore_performance_info_get.c index a623705f..4c7ffa4e 100644 --- a/common/src/tx_semaphore_performance_info_get.c +++ b/common/src/tx_semaphore_performance_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,14 +71,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_semaphore_performance_info_get(TX_SEMAPHORE *semaphore_ptr, ULONG *puts, ULONG *gets, ULONG *suspensions, ULONG *timeouts) diff --git a/common/src/tx_semaphore_performance_system_info_get.c b/common/src/tx_semaphore_performance_system_info_get.c index 5245d00b..db17c937 100644 --- a/common/src/tx_semaphore_performance_system_info_get.c +++ b/common/src/tx_semaphore_performance_system_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,14 +69,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_semaphore_performance_system_info_get(ULONG *puts, ULONG *gets, ULONG *suspensions, ULONG *timeouts) { diff --git a/common/src/tx_semaphore_prioritize.c b/common/src/tx_semaphore_prioritize.c index 56245df8..eec5e7b7 100644 --- a/common/src/tx_semaphore_prioritize.c +++ b/common/src/tx_semaphore_prioritize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_semaphore_prioritize(TX_SEMAPHORE *semaphore_ptr) { diff --git a/common/src/tx_semaphore_put.c b/common/src/tx_semaphore_put.c index dacd0db0..1ce9d145 100644 --- a/common/src/tx_semaphore_put.c +++ b/common/src/tx_semaphore_put.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_semaphore_put(TX_SEMAPHORE *semaphore_ptr) { diff --git a/common/src/tx_semaphore_put_notify.c b/common/src/tx_semaphore_put_notify.c index b1abe3be..80894d6e 100644 --- a/common/src/tx_semaphore_put_notify.c +++ b/common/src/tx_semaphore_put_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_semaphore_put_notify(TX_SEMAPHORE *semaphore_ptr, VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)) { diff --git a/common/src/tx_thread_create.c b/common/src/tx_thread_create.c index 2f4d011d..026b0ada 100644 --- a/common/src/tx_thread_create.c +++ b/common/src/tx_thread_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,24 +75,6 @@ /* Application Code */ /* _tx_timer_initialize Create system timer thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 William E. Lamie Modified comment(s), and */ -/* changed stack calculations */ -/* to use ALIGN_TYPE integers, */ -/* resulting in version 6.1 */ -/* 06-02-2021 William E. Lamie Modified comment(s), and */ -/* supported TX_MISRA_ENABLE, */ -/* 08-02-2021 Scott Larson Removed unneeded cast, */ -/* resulting in version 6.1.8 */ -/* 10-31-2023 Xiuwen Cai Modified comment(s), */ -/* added option for random */ -/* number stack filling, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ UINT _tx_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr, VOID (*entry_function)(ULONG id), ULONG entry_input, VOID *stack_start, ULONG stack_size, UINT priority, UINT preempt_threshold, diff --git a/common/src/tx_thread_delete.c b/common/src/tx_thread_delete.c index 69626c50..510f6565 100644 --- a/common/src/tx_thread_delete.c +++ b/common/src/tx_thread_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_delete(TX_THREAD *thread_ptr) { diff --git a/common/src/tx_thread_entry_exit_notify.c b/common/src/tx_thread_entry_exit_notify.c index 7d5919de..fdce25ef 100644 --- a/common/src/tx_thread_entry_exit_notify.c +++ b/common/src/tx_thread_entry_exit_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_entry_exit_notify(TX_THREAD *thread_ptr, VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT id)) { diff --git a/common/src/tx_thread_identify.c b/common/src/tx_thread_identify.c index 7808d053..86f56194 100644 --- a/common/src/tx_thread_identify.c +++ b/common/src/tx_thread_identify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ TX_THREAD *_tx_thread_identify(VOID) { diff --git a/common/src/tx_thread_info_get.c b/common/src/tx_thread_info_get.c index d9069457..740a3b95 100644 --- a/common/src/tx_thread_info_get.c +++ b/common/src/tx_thread_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,14 +71,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_info_get(TX_THREAD *thread_ptr, CHAR **name, UINT *state, ULONG *run_count, UINT *priority, UINT *preemption_threshold, ULONG *time_slice, diff --git a/common/src/tx_thread_initialize.c b/common/src/tx_thread_initialize.c index 11ddcc67..c9cfea33 100644 --- a/common/src/tx_thread_initialize.c +++ b/common/src/tx_thread_initialize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -48,7 +49,7 @@ TX_THREAD * _tx_thread_current_ptr; /* Define the variable that holds the next thread to execute. It is important - to remember that this is not necessarily equal to the current thread + to remember that this is not necessarily equal to the current thread pointer. */ TX_THREAD * _tx_thread_execute_ptr; @@ -65,7 +66,7 @@ ULONG _tx_thread_created_count; /* Define the current state variable. When this value is 0, a thread - is executing or the system is idle. Other values indicate that + is executing or the system is idle. Other values indicate that interrupt or initialization processing is active. This variable is initialized to TX_INITIALIZE_IN_PROGRESS to indicate initialization is active. */ @@ -74,15 +75,15 @@ volatile ULONG _tx_thread_system_state = TX_INITIALIZE_IN_PROGRESS; /* Define the 32-bit priority bit-maps. There is one priority bit map for each - 32 priority levels supported. If only 32 priorities are supported there is - only one bit map. Each bit within a priority bit map represents that one + 32 priority levels supported. If only 32 priorities are supported there is + only one bit map. Each bit within a priority bit map represents that one or more threads at the associated thread priority are ready. */ ULONG _tx_thread_priority_maps[TX_MAX_PRIORITIES/32]; -/* Define the priority map active bit map that specifies which of the previously - defined priority maps have something set. This is only necessary if more than +/* Define the priority map active bit map that specifies which of the previously + defined priority maps have something set. This is only necessary if more than 32 priorities are supported. */ #if TX_MAX_PRIORITIES > 32 @@ -92,17 +93,17 @@ ULONG _tx_thread_priority_map_active; #ifndef TX_DISABLE_PREEMPTION_THRESHOLD -/* Define the 32-bit preempt priority bit maps. There is one preempt bit map - for each 32 priority levels supported. If only 32 priorities are supported - there is only one bit map. Each set set bit corresponds to a preempted priority - level that had preemption-threshold active to protect against preemption of a +/* Define the 32-bit preempt priority bit maps. There is one preempt bit map + for each 32 priority levels supported. If only 32 priorities are supported + there is only one bit map. Each set set bit corresponds to a preempted priority + level that had preemption-threshold active to protect against preemption of a range of relatively higher priority threads. */ ULONG _tx_thread_preempted_maps[TX_MAX_PRIORITIES/32]; -/* Define the preempt map active bit map that specifies which of the previously - defined preempt maps have something set. This is only necessary if more than +/* Define the preempt map active bit map that specifies which of the previously + defined preempt maps have something set. This is only necessary if more than 32 priorities are supported. */ #if TX_MAX_PRIORITIES > 32 @@ -110,7 +111,7 @@ ULONG _tx_thread_preempted_map_active; #endif #endif -/* Define the variable that holds the highest priority group ready for +/* Define the variable that holds the highest priority group ready for execution. It is important to note that this is not necessarily the same as the priority of the thread pointed to by _tx_execute_thread. */ @@ -126,13 +127,13 @@ TX_THREAD * _tx_thread_priority_list[TX_MAX_PRIORITIES]; /* Define the global preempt disable variable. If this is non-zero, preemption is - disabled. It is used internally by ThreadX to prevent preemption of a thread in + disabled. It is used internally by ThreadX to prevent preemption of a thread in the middle of a service that is resuming or suspending another thread. */ volatile UINT _tx_thread_preempt_disable; -/* Define the global function pointer for mutex cleanup on thread completion or +/* Define the global function pointer for mutex cleanup on thread completion or termination. This pointer is setup during mutex initialization. */ VOID (*_tx_thread_mutex_release)(TX_THREAD *thread_ptr); @@ -176,8 +177,8 @@ ULONG _tx_build_options; #if defined(TX_ENABLE_STACK_CHECKING) || defined(TX_PORT_THREAD_STACK_ERROR_HANDLING) -/* Define the global function pointer for stack error handling. If a stack error is - detected and the application has registered a stack error handler, it will be +/* Define the global function pointer for stack error handling. If a stack error is + detected and the application has registered a stack error handler, it will be called via this function pointer. */ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); @@ -192,20 +193,20 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ ULONG _tx_thread_performance_resume_count; -/* Define the total number of thread suspensions. Each time a thread enters a +/* Define the total number of thread suspensions. Each time a thread enters a suspended state this variable is incremented. */ ULONG _tx_thread_performance_suspend_count; -/* Define the total number of solicited thread preemptions. Each time a thread is +/* Define the total number of solicited thread preemptions. Each time a thread is preempted by directly calling a ThreadX service, this variable is incremented. */ ULONG _tx_thread_performance_solicited_preemption_count; -/* Define the total number of interrupt thread preemptions. Each time a thread is - preempted as a result of an ISR calling a ThreadX service, this variable is +/* Define the total number of interrupt thread preemptions. Each time a thread is + preempted as a result of an ISR calling a ThreadX service, this variable is incremented. */ ULONG _tx_thread_performance_interrupt_preemption_count; @@ -217,45 +218,45 @@ ULONG _tx_thread_performance_interrupt_preemption_count; ULONG _tx_thread_performance_priority_inversion_count; -/* Define the total number of time-slices. Each time a time-slice operation is - actually performed (another thread is setup for running) this variable is +/* Define the total number of time-slices. Each time a time-slice operation is + actually performed (another thread is setup for running) this variable is incremented. */ ULONG _tx_thread_performance_time_slice_count; -/* Define the total number of thread relinquish operations. Each time a thread +/* Define the total number of thread relinquish operations. Each time a thread relinquish operation is actually performed (another thread is setup for running) this variable is incremented. */ ULONG _tx_thread_performance_relinquish_count; -/* Define the total number of thread timeouts. Each time a thread has a +/* Define the total number of thread timeouts. Each time a thread has a timeout this variable is incremented. */ ULONG _tx_thread_performance_timeout_count; -/* Define the total number of thread wait aborts. Each time a thread's suspension +/* Define the total number of thread wait aborts. Each time a thread's suspension is lifted by the tx_thread_wait_abort call this variable is incremented. */ ULONG _tx_thread_performance_wait_abort_count; -/* Define the total number of idle system thread returns. Each time a thread returns to +/* Define the total number of idle system thread returns. Each time a thread returns to an idle system (no other thread is ready to run) this variable is incremented. */ ULONG _tx_thread_performance_idle_return_count; -/* Define the total number of non-idle system thread returns. Each time a thread returns to +/* Define the total number of non-idle system thread returns. Each time a thread returns to a non-idle system (another thread is ready to run) this variable is incremented. */ ULONG _tx_thread_performance_non_idle_return_count; -/* Define the last TX_THREAD_EXECUTE_LOG_SIZE threads scheduled in ThreadX. This +/* Define the last TX_THREAD_EXECUTE_LOG_SIZE threads scheduled in ThreadX. This is a circular list, where the index points to the oldest entry. */ ULONG _tx_thread_performance__execute_log_index; @@ -266,7 +267,7 @@ TX_THREAD * _tx_thread_performance_execute_log[TX_THREAD_EXECUTE_LOG_SIZE]; /* Define special string. */ #ifndef TX_MISRA_ENABLE -const CHAR _tx_thread_special_string[] = +const CHAR _tx_thread_special_string[] = "G-ML-EL-ML-BL-DL-BL-GB-GL-M-D-DL-GZ-KH-EL-CM-NH-HA-GF-DD-JC-YZ-CT-AT-DW-USA-CA-SD-SDSU"; #endif @@ -302,25 +303,11 @@ const CHAR _tx_thread_special_string[] = /* */ /* _tx_initialize_high_level High level initialization */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* 06-02-2021 Yuxin Zhou Modified comment(s), added */ -/* Execution Profile support, */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 Yuxin Zhou Modified comment(s), improved */ -/* stack check error handling, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ VOID _tx_thread_initialize(VOID) { - /* Note: the system stack pointer and the system state variables are + /* Note: the system stack pointer and the system state variables are initialized by the low and high-level initialization functions, respectively. */ @@ -388,8 +375,8 @@ VOID _tx_thread_initialize(VOID) #endif /* Setup the build options flag. This is used to identify how the ThreadX library was constructed. */ - _tx_build_options = _tx_build_options - | (((ULONG) (TX_MAX_PRIORITIES/32)) << 24) + _tx_build_options = _tx_build_options + | (((ULONG) (TX_MAX_PRIORITIES/32)) << 24) #ifdef TX_NOT_INTERRUPTABLE | (((ULONG) 1) << 31) #endif diff --git a/common/src/tx_thread_performance_info_get.c b/common/src/tx_thread_performance_info_get.c index 92c0e02b..79a8c7ee 100644 --- a/common/src/tx_thread_performance_info_get.c +++ b/common/src/tx_thread_performance_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -87,14 +88,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_performance_info_get(TX_THREAD *thread_ptr, ULONG *resumptions, ULONG *suspensions, ULONG *solicited_preemptions, ULONG *interrupt_preemptions, ULONG *priority_inversions, diff --git a/common/src/tx_thread_performance_system_info_get.c b/common/src/tx_thread_performance_system_info_get.c index a6c300aa..8ade15dd 100644 --- a/common/src/tx_thread_performance_system_info_get.c +++ b/common/src/tx_thread_performance_system_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -87,14 +88,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_performance_system_info_get(ULONG *resumptions, ULONG *suspensions, ULONG *solicited_preemptions, ULONG *interrupt_preemptions, ULONG *priority_inversions, diff --git a/common/src/tx_thread_preemption_change.c b/common/src/tx_thread_preemption_change.c index cafb5792..59a37514 100644 --- a/common/src/tx_thread_preemption_change.c +++ b/common/src/tx_thread_preemption_change.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_preemption_change(TX_THREAD *thread_ptr, UINT new_threshold, UINT *old_threshold) { diff --git a/common/src/tx_thread_priority_change.c b/common/src/tx_thread_priority_change.c index 9e8da188..bdf2a993 100644 --- a/common/src/tx_thread_priority_change.c +++ b/common/src/tx_thread_priority_change.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,19 +72,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 William E. Lamie Modified comment(s), and */ -/* change thread state from */ -/* TX_SUSPENDED to */ -/* TX_PRIORITY_CHANGE before */ -/* calling */ -/* _tx_thread_system_suspend, */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_priority_change(TX_THREAD *thread_ptr, UINT new_priority, UINT *old_priority) { diff --git a/common/src/tx_thread_relinquish.c b/common/src/tx_thread_relinquish.c index 6f3a33ab..c84e4d99 100644 --- a/common/src/tx_thread_relinquish.c +++ b/common/src/tx_thread_relinquish.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_thread_relinquish(VOID) { diff --git a/common/src/tx_thread_reset.c b/common/src/tx_thread_reset.c index 1fea78be..da56daf5 100644 --- a/common/src/tx_thread_reset.c +++ b/common/src/tx_thread_reset.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_reset(TX_THREAD *thread_ptr) { diff --git a/common/src/tx_thread_resume.c b/common/src/tx_thread_resume.c index b97bdb4b..f662be5a 100644 --- a/common/src/tx_thread_resume.c +++ b/common/src/tx_thread_resume.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_resume(TX_THREAD *thread_ptr) { diff --git a/common/src/tx_thread_shell_entry.c b/common/src/tx_thread_shell_entry.c index 161ea80e..45fe9d6d 100644 --- a/common/src/tx_thread_shell_entry.c +++ b/common/src/tx_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_thread_shell_entry(VOID) { diff --git a/common/src/tx_thread_sleep.c b/common/src/tx_thread_sleep.c index 6d6c92c4..fd986a0b 100644 --- a/common/src/tx_thread_sleep.c +++ b/common/src/tx_thread_sleep.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_sleep(ULONG timer_ticks) { diff --git a/common/src/tx_thread_stack_analyze.c b/common/src/tx_thread_stack_analyze.c index bdadab0d..080d0052 100644 --- a/common/src/tx_thread_stack_analyze.c +++ b/common/src/tx_thread_stack_analyze.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,14 +61,6 @@ /* */ /* ThreadX internal code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_thread_stack_analyze(TX_THREAD *thread_ptr) { diff --git a/common/src/tx_thread_stack_error_handler.c b/common/src/tx_thread_stack_error_handler.c index 6e2422ed..2a63fe4e 100644 --- a/common/src/tx_thread_stack_error_handler.c +++ b/common/src/tx_thread_stack_error_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,26 +61,6 @@ /* */ /* ThreadX internal code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* update misra support, */ -/* resulting in version 6.1 */ -/* 10-16-2020 William E. Lamie Modified comment(s), */ -/* fixed link issue, */ -/* resulting in version 6.1.1 */ -/* 06-02-2021 William E. Lamie Modified comment(s), */ -/* fixed link issue, added */ -/* conditional compilation */ -/* for ARMv8-M (Cortex M23/33) */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 Yuxin Zhou Modified comment(s), improved */ -/* stack check error handling, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) { diff --git a/common/src/tx_thread_stack_error_notify.c b/common/src/tx_thread_stack_error_notify.c index 796ff460..d1c76213 100644 --- a/common/src/tx_thread_stack_error_notify.c +++ b/common/src/tx_thread_stack_error_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,21 +67,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* 06-02-2021 Yuxin Zhou Modified comment(s), added */ -/* conditional compilation */ -/* for ARMv8-M (Cortex M23/33) */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 Yuxin Zhou Modified comment(s), improved */ -/* stack check error handling, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) { diff --git a/common/src/tx_thread_suspend.c b/common/src/tx_thread_suspend.c index ccf3ebc3..460944b6 100644 --- a/common/src/tx_thread_suspend.c +++ b/common/src/tx_thread_suspend.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,18 +63,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* 10-16-2020 Yuxin Zhou Modified comment(s), and */ -/* added type cast to address */ -/* a MISRA compliance issue, */ -/* resulting in version 6.1.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_suspend(TX_THREAD *thread_ptr) { diff --git a/common/src/tx_thread_system_preempt_check.c b/common/src/tx_thread_system_preempt_check.c index 7511a02c..9dd039de 100644 --- a/common/src/tx_thread_system_preempt_check.c +++ b/common/src/tx_thread_system_preempt_check.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,14 +61,6 @@ /* */ /* Other ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_thread_system_preempt_check(VOID) { diff --git a/common/src/tx_thread_system_resume.c b/common/src/tx_thread_system_resume.c index 7b9f557d..708e5e5e 100644 --- a/common/src/tx_thread_system_resume.c +++ b/common/src/tx_thread_system_resume.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,14 +69,6 @@ /* _tx_thread_wait_abort Thread wait abort */ /* Other ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_thread_system_resume(TX_THREAD *thread_ptr) #ifndef TX_NOT_INTERRUPTABLE diff --git a/common/src/tx_thread_system_suspend.c b/common/src/tx_thread_system_suspend.c index 33f8cac2..4cc14f5a 100644 --- a/common/src/tx_thread_system_suspend.c +++ b/common/src/tx_thread_system_suspend.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,14 +71,6 @@ /* _tx_thread_terminate Thread terminate */ /* Other ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_thread_system_suspend(TX_THREAD *thread_ptr) #ifndef TX_NOT_INTERRUPTABLE diff --git a/common/src/tx_thread_terminate.c b/common/src/tx_thread_terminate.c index 1e30687f..86e34bae 100644 --- a/common/src/tx_thread_terminate.c +++ b/common/src/tx_thread_terminate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,14 +68,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_terminate(TX_THREAD *thread_ptr) { diff --git a/common/src/tx_thread_time_slice.c b/common/src/tx_thread_time_slice.c index 31bc45ad..129ca322 100644 --- a/common/src/tx_thread_time_slice.c +++ b/common/src/tx_thread_time_slice.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,16 +65,6 @@ /* */ /* _tx_timer_interrupt Timer interrupt handling */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Scott Larson Modified comment(s), and */ -/* opt out of function when */ -/* TX_NO_TIMER is defined, */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_thread_time_slice(VOID) { diff --git a/common/src/tx_thread_time_slice_change.c b/common/src/tx_thread_time_slice_change.c index c15c9ae3..67a1c26b 100644 --- a/common/src/tx_thread_time_slice_change.c +++ b/common/src/tx_thread_time_slice_change.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_time_slice_change(TX_THREAD *thread_ptr, ULONG new_time_slice, ULONG *old_time_slice) { diff --git a/common/src/tx_thread_timeout.c b/common/src/tx_thread_timeout.c index 33ea5352..21b62e34 100644 --- a/common/src/tx_thread_timeout.c +++ b/common/src/tx_thread_timeout.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,14 +67,6 @@ /* _tx_timer_expiration_process Timer expiration function */ /* _tx_timer_thread_entry Timer thread function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_thread_timeout(ULONG timeout_input) { diff --git a/common/src/tx_thread_wait_abort.c b/common/src/tx_thread_wait_abort.c index 372a72b2..24bce69b 100644 --- a/common/src/tx_thread_wait_abort.c +++ b/common/src/tx_thread_wait_abort.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,17 +64,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* 03-08-2023 Scott Larson Check if thread is coming out */ -/* of suspension elsewhere, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_wait_abort(TX_THREAD *thread_ptr) { diff --git a/common/src/tx_time_get.c b/common/src/tx_time_get.c index 16361142..6ed7d731 100644 --- a/common/src/tx_time_get.c +++ b/common/src/tx_time_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,16 +61,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* 12-31-2020 Andres Mlinar Modified comment(s), */ -/* resulting in version 6.1.3 */ -/* */ /**************************************************************************/ ULONG _tx_time_get(VOID) { diff --git a/common/src/tx_time_set.c b/common/src/tx_time_set.c index 613274ac..97b42986 100644 --- a/common/src/tx_time_set.c +++ b/common/src/tx_time_set.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,14 +61,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_time_set(ULONG new_time) { diff --git a/common/src/tx_timer_activate.c b/common/src/tx_timer_activate.c index d8609573..5a59eade 100644 --- a/common/src/tx_timer_activate.c +++ b/common/src/tx_timer_activate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_timer_activate(TX_TIMER *timer_ptr) { diff --git a/common/src/tx_timer_change.c b/common/src/tx_timer_change.c index 420ff26a..24661d3d 100644 --- a/common/src/tx_timer_change.c +++ b/common/src/tx_timer_change.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_timer_change(TX_TIMER *timer_ptr, ULONG initial_ticks, ULONG reschedule_ticks) { diff --git a/common/src/tx_timer_create.c b/common/src/tx_timer_create.c index 707e743b..30dd4e11 100644 --- a/common/src/tx_timer_create.c +++ b/common/src/tx_timer_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_timer_create(TX_TIMER *timer_ptr, CHAR *name_ptr, VOID (*expiration_function)(ULONG id), ULONG expiration_input, diff --git a/common/src/tx_timer_deactivate.c b/common/src/tx_timer_deactivate.c index 97c786bf..98eacd4b 100644 --- a/common/src/tx_timer_deactivate.c +++ b/common/src/tx_timer_deactivate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_timer_deactivate(TX_TIMER *timer_ptr) { diff --git a/common/src/tx_timer_delete.c b/common/src/tx_timer_delete.c index 7baef6d4..60d425ec 100644 --- a/common/src/tx_timer_delete.c +++ b/common/src/tx_timer_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_timer_delete(TX_TIMER *timer_ptr) { diff --git a/common/src/tx_timer_expiration_process.c b/common/src/tx_timer_expiration_process.c index 72faed11..33923a93 100644 --- a/common/src/tx_timer_expiration_process.c +++ b/common/src/tx_timer_expiration_process.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,16 +68,6 @@ /* */ /* _tx_timer_interrupt Timer interrupt handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Scott Larson Modified comment(s), and */ -/* opt out of function when */ -/* TX_NO_TIMER is defined, */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_timer_expiration_process(VOID) { diff --git a/common/src/tx_timer_info_get.c b/common/src/tx_timer_info_get.c index ca04c4ea..31c801f9 100644 --- a/common/src/tx_timer_info_get.c +++ b/common/src/tx_timer_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,14 +67,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_timer_info_get(TX_TIMER *timer_ptr, CHAR **name, UINT *active, ULONG *remaining_ticks, ULONG *reschedule_ticks, TX_TIMER **next_timer) diff --git a/common/src/tx_timer_initialize.c b/common/src/tx_timer_initialize.c index 1ae442df..2172b4a6 100644 --- a/common/src/tx_timer_initialize.c +++ b/common/src/tx_timer_initialize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -192,14 +193,6 @@ ULONG _tx_timer_time_slice; /* */ /* _tx_initialize_high_level High level initialization */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_timer_initialize(VOID) { diff --git a/common/src/tx_timer_performance_info_get.c b/common/src/tx_timer_performance_info_get.c index 05e332c1..37cacee4 100644 --- a/common/src/tx_timer_performance_info_get.c +++ b/common/src/tx_timer_performance_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -73,14 +74,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_timer_performance_info_get(TX_TIMER *timer_ptr, ULONG *activates, ULONG *reactivates, ULONG *deactivates, ULONG *expirations, ULONG *expiration_adjusts) diff --git a/common/src/tx_timer_performance_system_info_get.c b/common/src/tx_timer_performance_system_info_get.c index 367e1149..9b6c3862 100644 --- a/common/src/tx_timer_performance_system_info_get.c +++ b/common/src/tx_timer_performance_system_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,14 +71,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_timer_performance_system_info_get(ULONG *activates, ULONG *reactivates, ULONG *deactivates, ULONG *expirations, ULONG *expiration_adjusts) diff --git a/common/src/tx_timer_system_activate.c b/common/src/tx_timer_system_activate.c index 4c6f7b04..af57fdf5 100644 --- a/common/src/tx_timer_system_activate.c +++ b/common/src/tx_timer_system_activate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,16 +65,6 @@ /* _tx_timer_thread_entry Timer thread processing */ /* _tx_timer_activate Application timer activate */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Scott Larson Modified comment(s), and */ -/* opt out of function when */ -/* TX_NO_TIMER is defined, */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_timer_system_activate(TX_TIMER_INTERNAL *timer_ptr) { diff --git a/common/src/tx_timer_system_deactivate.c b/common/src/tx_timer_system_deactivate.c index 487ead9d..ae955077 100644 --- a/common/src/tx_timer_system_deactivate.c +++ b/common/src/tx_timer_system_deactivate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* _tx_thread_system_resume Thread resume function */ /* _tx_timer_thread_entry Timer thread processing */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_timer_system_deactivate(TX_TIMER_INTERNAL *timer_ptr) { diff --git a/common/src/tx_timer_thread_entry.c b/common/src/tx_timer_thread_entry.c index 33074239..971a0703 100644 --- a/common/src/tx_timer_thread_entry.c +++ b/common/src/tx_timer_thread_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* ThreadX Scheduler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_TIMER_PROCESS_IN_ISR VOID _tx_timer_thread_entry(ULONG timer_thread_input) diff --git a/common/src/tx_trace_buffer_full_notify.c b/common/src/tx_trace_buffer_full_notify.c index 9e07c0a3..7253e8a4 100644 --- a/common/src/tx_trace_buffer_full_notify.c +++ b/common/src/tx_trace_buffer_full_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_trace_buffer_full_notify(VOID (*full_buffer_callback)(VOID *buffer)) { diff --git a/common/src/tx_trace_disable.c b/common/src/tx_trace_disable.c index 1ef211e0..96c28740 100644 --- a/common/src/tx_trace_disable.c +++ b/common/src/tx_trace_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_trace_disable(VOID) { diff --git a/common/src/tx_trace_enable.c b/common/src/tx_trace_enable.c index aa372e8d..2fb1252c 100644 --- a/common/src/tx_trace_enable.c +++ b/common/src/tx_trace_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -73,14 +74,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_trace_enable(VOID *trace_buffer_start, ULONG trace_buffer_size, ULONG registry_entries) { diff --git a/common/src/tx_trace_event_filter.c b/common/src/tx_trace_event_filter.c index 3afb8ed5..9caf18ae 100644 --- a/common/src/tx_trace_event_filter.c +++ b/common/src/tx_trace_event_filter.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_trace_event_filter(ULONG event_filter_bits) { diff --git a/common/src/tx_trace_event_unfilter.c b/common/src/tx_trace_event_unfilter.c index f9d054d7..652e4143 100644 --- a/common/src/tx_trace_event_unfilter.c +++ b/common/src/tx_trace_event_unfilter.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_trace_event_unfilter(ULONG event_unfilter_bits) { diff --git a/common/src/tx_trace_initialize.c b/common/src/tx_trace_initialize.c index 14877b9c..5cec8eae 100644 --- a/common/src/tx_trace_initialize.c +++ b/common/src/tx_trace_initialize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -125,14 +126,6 @@ ULONG _tx_trace_registry_search_start; /* */ /* _tx_initialize_high_level High level initialization */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_trace_initialize(VOID) { diff --git a/common/src/tx_trace_interrupt_control.c b/common/src/tx_trace_interrupt_control.c index 595dff77..2e35c62d 100644 --- a/common/src/tx_trace_interrupt_control.c +++ b/common/src/tx_trace_interrupt_control.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,14 +61,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_trace_interrupt_control(UINT new_posture) { diff --git a/common/src/tx_trace_isr_enter_insert.c b/common/src/tx_trace_isr_enter_insert.c index 628cc8ff..f9971cf2 100644 --- a/common/src/tx_trace_isr_enter_insert.c +++ b/common/src/tx_trace_isr_enter_insert.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_trace_isr_enter_insert(ULONG isr_id) { diff --git a/common/src/tx_trace_isr_exit_insert.c b/common/src/tx_trace_isr_exit_insert.c index 0d743c19..a4a8ade8 100644 --- a/common/src/tx_trace_isr_exit_insert.c +++ b/common/src/tx_trace_isr_exit_insert.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_trace_isr_exit_insert(ULONG isr_id) { diff --git a/common/src/tx_trace_object_register.c b/common/src/tx_trace_object_register.c index 0805063d..f7cd4a4a 100644 --- a/common/src/tx_trace_object_register.c +++ b/common/src/tx_trace_object_register.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,17 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* 07-29-2022 Scott Larson Modified comment(s), */ -/* check for null name, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ VOID _tx_trace_object_register(UCHAR object_type, VOID *object_ptr, CHAR *object_name, ULONG parameter_1, ULONG parameter_2) { diff --git a/common/src/tx_trace_object_unregister.c b/common/src/tx_trace_object_unregister.c index a7fef275..2166c973 100644 --- a/common/src/tx_trace_object_unregister.c +++ b/common/src/tx_trace_object_unregister.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_trace_object_unregister(VOID *object_ptr) { diff --git a/common/src/tx_trace_user_event_insert.c b/common/src/tx_trace_user_event_insert.c index fda09610..787a55f0 100644 --- a/common/src/tx_trace_user_event_insert.c +++ b/common/src/tx_trace_user_event_insert.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_trace_user_event_insert(ULONG event_id, ULONG info_field_1, ULONG info_field_2, ULONG info_field_3, ULONG info_field_4) { diff --git a/common/src/txe_block_allocate.c b/common/src/txe_block_allocate.c index 5564354b..c9c7a1a8 100644 --- a/common/src/txe_block_allocate.c +++ b/common/src/txe_block_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,14 +68,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_block_allocate(TX_BLOCK_POOL *pool_ptr, VOID **block_ptr, ULONG wait_option) { diff --git a/common/src/txe_block_pool_create.c b/common/src/txe_block_pool_create.c index 8cbeadbd..08ef7e69 100644 --- a/common/src/txe_block_pool_create.c +++ b/common/src/txe_block_pool_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,14 +73,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_block_pool_create(TX_BLOCK_POOL *pool_ptr, CHAR *name_ptr, ULONG block_size, VOID *pool_start, ULONG pool_size, UINT pool_control_block_size) diff --git a/common/src/txe_block_pool_delete.c b/common/src/txe_block_pool_delete.c index 844ff57a..f9af71cb 100644 --- a/common/src/txe_block_pool_delete.c +++ b/common/src/txe_block_pool_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_block_pool_delete(TX_BLOCK_POOL *pool_ptr) { diff --git a/common/src/txe_block_pool_info_get.c b/common/src/txe_block_pool_info_get.c index 77d9df4a..f91ca206 100644 --- a/common/src/txe_block_pool_info_get.c +++ b/common/src/txe_block_pool_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,14 +69,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_block_pool_info_get(TX_BLOCK_POOL *pool_ptr, CHAR **name, ULONG *available_blocks, ULONG *total_blocks, TX_THREAD **first_suspended, diff --git a/common/src/txe_block_pool_prioritize.c b/common/src/txe_block_pool_prioritize.c index 593ac6dc..87742011 100644 --- a/common/src/txe_block_pool_prioritize.c +++ b/common/src/txe_block_pool_prioritize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_block_pool_prioritize(TX_BLOCK_POOL *pool_ptr) { diff --git a/common/src/txe_block_release.c b/common/src/txe_block_release.c index e7eaed24..ba63d0b6 100644 --- a/common/src/txe_block_release.c +++ b/common/src/txe_block_release.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_block_release(VOID *block_ptr) { diff --git a/common/src/txe_byte_allocate.c b/common/src/txe_byte_allocate.c index dbb3937e..dacbede9 100644 --- a/common/src/txe_byte_allocate.c +++ b/common/src/txe_byte_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,14 +71,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_byte_allocate(TX_BYTE_POOL *pool_ptr, VOID **memory_ptr, ULONG memory_size, ULONG wait_option) diff --git a/common/src/txe_byte_pool_create.c b/common/src/txe_byte_pool_create.c index 2f37d063..99a89698 100644 --- a/common/src/txe_byte_pool_create.c +++ b/common/src/txe_byte_pool_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,14 +72,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_byte_pool_create(TX_BYTE_POOL *pool_ptr, CHAR *name_ptr, VOID *pool_start, ULONG pool_size, UINT pool_control_block_size) { diff --git a/common/src/txe_byte_pool_delete.c b/common/src/txe_byte_pool_delete.c index 2a6baad2..6bbeb8f0 100644 --- a/common/src/txe_byte_pool_delete.c +++ b/common/src/txe_byte_pool_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_byte_pool_delete(TX_BYTE_POOL *pool_ptr) { diff --git a/common/src/txe_byte_pool_info_get.c b/common/src/txe_byte_pool_info_get.c index 0a7536ef..85e7a233 100644 --- a/common/src/txe_byte_pool_info_get.c +++ b/common/src/txe_byte_pool_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,14 +69,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_byte_pool_info_get(TX_BYTE_POOL *pool_ptr, CHAR **name, ULONG *available_bytes, ULONG *fragments, TX_THREAD **first_suspended, diff --git a/common/src/txe_byte_pool_prioritize.c b/common/src/txe_byte_pool_prioritize.c index a0f0f1ae..9acec73c 100644 --- a/common/src/txe_byte_pool_prioritize.c +++ b/common/src/txe_byte_pool_prioritize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_byte_pool_prioritize(TX_BYTE_POOL *pool_ptr) { diff --git a/common/src/txe_byte_release.c b/common/src/txe_byte_release.c index 67f91907..89c3a82b 100644 --- a/common/src/txe_byte_release.c +++ b/common/src/txe_byte_release.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_byte_release(VOID *memory_ptr) { diff --git a/common/src/txe_event_flags_create.c b/common/src/txe_event_flags_create.c index 4c71bd95..4e3fed77 100644 --- a/common/src/txe_event_flags_create.c +++ b/common/src/txe_event_flags_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,14 +69,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_event_flags_create(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR *name_ptr, UINT event_control_block_size) { diff --git a/common/src/txe_event_flags_delete.c b/common/src/txe_event_flags_delete.c index 66066276..23c04807 100644 --- a/common/src/txe_event_flags_delete.c +++ b/common/src/txe_event_flags_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_event_flags_delete(TX_EVENT_FLAGS_GROUP *group_ptr) { diff --git a/common/src/txe_event_flags_get.c b/common/src/txe_event_flags_get.c index 23767630..1e9c6e0c 100644 --- a/common/src/txe_event_flags_get.c +++ b/common/src/txe_event_flags_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,14 +72,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_event_flags_get(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG requested_flags, UINT get_option, ULONG *actual_flags_ptr, ULONG wait_option) diff --git a/common/src/txe_event_flags_info_get.c b/common/src/txe_event_flags_info_get.c index 3400c55e..e551d025 100644 --- a/common/src/txe_event_flags_info_get.c +++ b/common/src/txe_event_flags_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,14 +71,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_event_flags_info_get(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR **name, ULONG *current_flags, TX_THREAD **first_suspended, ULONG *suspended_count, diff --git a/common/src/txe_event_flags_set.c b/common/src/txe_event_flags_set.c index 03d309ab..4df57fad 100644 --- a/common/src/txe_event_flags_set.c +++ b/common/src/txe_event_flags_set.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_event_flags_set(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG flags_to_set, UINT set_option) { diff --git a/common/src/txe_event_flags_set_notify.c b/common/src/txe_event_flags_set_notify.c index f93963d3..51887fd7 100644 --- a/common/src/txe_event_flags_set_notify.c +++ b/common/src/txe_event_flags_set_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_event_flags_set_notify(TX_EVENT_FLAGS_GROUP *group_ptr, VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)) { diff --git a/common/src/txe_mutex_create.c b/common/src/txe_mutex_create.c index fb65a5be..392f8b0e 100644 --- a/common/src/txe_mutex_create.c +++ b/common/src/txe_mutex_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -69,14 +70,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_mutex_create(TX_MUTEX *mutex_ptr, CHAR *name_ptr, UINT inherit, UINT mutex_control_block_size) { diff --git a/common/src/txe_mutex_delete.c b/common/src/txe_mutex_delete.c index b2a3fd2b..3692bf89 100644 --- a/common/src/txe_mutex_delete.c +++ b/common/src/txe_mutex_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_mutex_delete(TX_MUTEX *mutex_ptr) { diff --git a/common/src/txe_mutex_get.c b/common/src/txe_mutex_get.c index 7ef04eef..2d457c82 100644 --- a/common/src/txe_mutex_get.c +++ b/common/src/txe_mutex_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,14 +67,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_mutex_get(TX_MUTEX *mutex_ptr, ULONG wait_option) { diff --git a/common/src/txe_mutex_info_get.c b/common/src/txe_mutex_info_get.c index 826fead1..f4ef4168 100644 --- a/common/src/txe_mutex_info_get.c +++ b/common/src/txe_mutex_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -69,14 +70,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_mutex_info_get(TX_MUTEX *mutex_ptr, CHAR **name, ULONG *count, TX_THREAD **owner, TX_THREAD **first_suspended, ULONG *suspended_count, diff --git a/common/src/txe_mutex_prioritize.c b/common/src/txe_mutex_prioritize.c index 9ae4b868..d3302c1c 100644 --- a/common/src/txe_mutex_prioritize.c +++ b/common/src/txe_mutex_prioritize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_mutex_prioritize(TX_MUTEX *mutex_ptr) { diff --git a/common/src/txe_mutex_put.c b/common/src/txe_mutex_put.c index 85d5929f..8a085b7b 100644 --- a/common/src/txe_mutex_put.c +++ b/common/src/txe_mutex_put.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_mutex_put(TX_MUTEX *mutex_ptr) { diff --git a/common/src/txe_queue_create.c b/common/src/txe_queue_create.c index 2d91cc9f..185289fe 100644 --- a/common/src/txe_queue_create.c +++ b/common/src/txe_queue_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,14 +71,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_queue_create(TX_QUEUE *queue_ptr, CHAR *name_ptr, UINT message_size, VOID *queue_start, ULONG queue_size, UINT queue_control_block_size) diff --git a/common/src/txe_queue_delete.c b/common/src/txe_queue_delete.c index 3062edeb..43dc9d6f 100644 --- a/common/src/txe_queue_delete.c +++ b/common/src/txe_queue_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_queue_delete(TX_QUEUE *queue_ptr) { diff --git a/common/src/txe_queue_flush.c b/common/src/txe_queue_flush.c index 348de23e..b514db95 100644 --- a/common/src/txe_queue_flush.c +++ b/common/src/txe_queue_flush.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,14 +61,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_queue_flush(TX_QUEUE *queue_ptr) { diff --git a/common/src/txe_queue_front_send.c b/common/src/txe_queue_front_send.c index 21c254ab..798aada6 100644 --- a/common/src/txe_queue_front_send.c +++ b/common/src/txe_queue_front_send.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_queue_front_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option) { diff --git a/common/src/txe_queue_info_get.c b/common/src/txe_queue_info_get.c index b4507b01..78d98392 100644 --- a/common/src/txe_queue_info_get.c +++ b/common/src/txe_queue_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,14 +69,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_queue_info_get(TX_QUEUE *queue_ptr, CHAR **name, ULONG *enqueued, ULONG *available_storage, TX_THREAD **first_suspended, ULONG *suspended_count, TX_QUEUE **next_queue) diff --git a/common/src/txe_queue_prioritize.c b/common/src/txe_queue_prioritize.c index f74809a1..ba40b02a 100644 --- a/common/src/txe_queue_prioritize.c +++ b/common/src/txe_queue_prioritize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_queue_prioritize(TX_QUEUE *queue_ptr) { diff --git a/common/src/txe_queue_receive.c b/common/src/txe_queue_receive.c index b40e6a56..de6f4dcd 100644 --- a/common/src/txe_queue_receive.c +++ b/common/src/txe_queue_receive.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,14 +68,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_queue_receive(TX_QUEUE *queue_ptr, VOID *destination_ptr, ULONG wait_option) { diff --git a/common/src/txe_queue_send.c b/common/src/txe_queue_send.c index 5873f025..1b752e75 100644 --- a/common/src/txe_queue_send.c +++ b/common/src/txe_queue_send.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_queue_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option) { diff --git a/common/src/txe_queue_send_notify.c b/common/src/txe_queue_send_notify.c index 9ffb0a93..dd2beaf2 100644 --- a/common/src/txe_queue_send_notify.c +++ b/common/src/txe_queue_send_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_queue_send_notify(TX_QUEUE *queue_ptr, VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)) { diff --git a/common/src/txe_semaphore_ceiling_put.c b/common/src/txe_semaphore_ceiling_put.c index 51fee9d7..4c8b4603 100644 --- a/common/src/txe_semaphore_ceiling_put.c +++ b/common/src/txe_semaphore_ceiling_put.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_semaphore_ceiling_put(TX_SEMAPHORE *semaphore_ptr, ULONG ceiling) { diff --git a/common/src/txe_semaphore_create.c b/common/src/txe_semaphore_create.c index 3390491c..a190b03c 100644 --- a/common/src/txe_semaphore_create.c +++ b/common/src/txe_semaphore_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,14 +69,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_semaphore_create(TX_SEMAPHORE *semaphore_ptr, CHAR *name_ptr, ULONG initial_count, UINT semaphore_control_block_size) { diff --git a/common/src/txe_semaphore_delete.c b/common/src/txe_semaphore_delete.c index 2083a22a..3d9f366c 100644 --- a/common/src/txe_semaphore_delete.c +++ b/common/src/txe_semaphore_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_semaphore_delete(TX_SEMAPHORE *semaphore_ptr) { diff --git a/common/src/txe_semaphore_get.c b/common/src/txe_semaphore_get.c index 403d43b4..7b92d317 100644 --- a/common/src/txe_semaphore_get.c +++ b/common/src/txe_semaphore_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_semaphore_get(TX_SEMAPHORE *semaphore_ptr, ULONG wait_option) { diff --git a/common/src/txe_semaphore_info_get.c b/common/src/txe_semaphore_info_get.c index 142bad37..7695028e 100644 --- a/common/src/txe_semaphore_info_get.c +++ b/common/src/txe_semaphore_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,14 +69,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_semaphore_info_get(TX_SEMAPHORE *semaphore_ptr, CHAR **name, ULONG *current_value, TX_THREAD **first_suspended, ULONG *suspended_count, diff --git a/common/src/txe_semaphore_prioritize.c b/common/src/txe_semaphore_prioritize.c index 52525ded..cd873c5a 100644 --- a/common/src/txe_semaphore_prioritize.c +++ b/common/src/txe_semaphore_prioritize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_semaphore_prioritize(TX_SEMAPHORE *semaphore_ptr) { diff --git a/common/src/txe_semaphore_put.c b/common/src/txe_semaphore_put.c index 4a26fbd8..452c39bd 100644 --- a/common/src/txe_semaphore_put.c +++ b/common/src/txe_semaphore_put.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_semaphore_put(TX_SEMAPHORE *semaphore_ptr) { diff --git a/common/src/txe_semaphore_put_notify.c b/common/src/txe_semaphore_put_notify.c index 646c293a..33aa8d9a 100644 --- a/common/src/txe_semaphore_put_notify.c +++ b/common/src/txe_semaphore_put_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_semaphore_put_notify(TX_SEMAPHORE *semaphore_ptr, VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)) { diff --git a/common/src/txe_thread_create.c b/common/src/txe_thread_create.c index c3902cd1..d319bc9e 100644 --- a/common/src/txe_thread_create.c +++ b/common/src/txe_thread_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -77,14 +78,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr, VOID (*entry_function)(ULONG id), ULONG entry_input, diff --git a/common/src/txe_thread_delete.c b/common/src/txe_thread_delete.c index 6e2d1d2b..85cf31ca 100644 --- a/common/src/txe_thread_delete.c +++ b/common/src/txe_thread_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,14 +61,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_delete(TX_THREAD *thread_ptr) { diff --git a/common/src/txe_thread_entry_exit_notify.c b/common/src/txe_thread_entry_exit_notify.c index ab4e835d..33420683 100644 --- a/common/src/txe_thread_entry_exit_notify.c +++ b/common/src/txe_thread_entry_exit_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_entry_exit_notify(TX_THREAD *thread_ptr, VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT type)) { diff --git a/common/src/txe_thread_info_get.c b/common/src/txe_thread_info_get.c index 17f9155d..ad1db3f7 100644 --- a/common/src/txe_thread_info_get.c +++ b/common/src/txe_thread_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,14 +73,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_info_get(TX_THREAD *thread_ptr, CHAR **name, UINT *state, ULONG *run_count, UINT *priority, UINT *preemption_threshold, ULONG *time_slice, diff --git a/common/src/txe_thread_preemption_change.c b/common/src/txe_thread_preemption_change.c index c0cfa91e..e3de0a85 100644 --- a/common/src/txe_thread_preemption_change.c +++ b/common/src/txe_thread_preemption_change.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_preemption_change(TX_THREAD *thread_ptr, UINT new_threshold, UINT *old_threshold) { diff --git a/common/src/txe_thread_priority_change.c b/common/src/txe_thread_priority_change.c index b4a1224b..2bf0058b 100644 --- a/common/src/txe_thread_priority_change.c +++ b/common/src/txe_thread_priority_change.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_priority_change(TX_THREAD *thread_ptr, UINT new_priority, UINT *old_priority) { diff --git a/common/src/txe_thread_relinquish.c b/common/src/txe_thread_relinquish.c index 1c5ab21a..080bad47 100644 --- a/common/src/txe_thread_relinquish.c +++ b/common/src/txe_thread_relinquish.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _txe_thread_relinquish(VOID) { diff --git a/common/src/txe_thread_reset.c b/common/src/txe_thread_reset.c index 4fed5e7a..1815f5bb 100644 --- a/common/src/txe_thread_reset.c +++ b/common/src/txe_thread_reset.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_reset(TX_THREAD *thread_ptr) { diff --git a/common/src/txe_thread_resume.c b/common/src/txe_thread_resume.c index e8a341dd..ae356c6c 100644 --- a/common/src/txe_thread_resume.c +++ b/common/src/txe_thread_resume.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_resume(TX_THREAD *thread_ptr) { diff --git a/common/src/txe_thread_suspend.c b/common/src/txe_thread_suspend.c index 951d35eb..dab42db7 100644 --- a/common/src/txe_thread_suspend.c +++ b/common/src/txe_thread_suspend.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_suspend(TX_THREAD *thread_ptr) { diff --git a/common/src/txe_thread_terminate.c b/common/src/txe_thread_terminate.c index aa54501c..8e1f18f5 100644 --- a/common/src/txe_thread_terminate.c +++ b/common/src/txe_thread_terminate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_terminate(TX_THREAD *thread_ptr) { diff --git a/common/src/txe_thread_time_slice_change.c b/common/src/txe_thread_time_slice_change.c index d01137d8..456dbb2a 100644 --- a/common/src/txe_thread_time_slice_change.c +++ b/common/src/txe_thread_time_slice_change.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_time_slice_change(TX_THREAD *thread_ptr, ULONG new_time_slice, ULONG *old_time_slice) { diff --git a/common/src/txe_thread_wait_abort.c b/common/src/txe_thread_wait_abort.c index 8132c597..086fb33b 100644 --- a/common/src/txe_thread_wait_abort.c +++ b/common/src/txe_thread_wait_abort.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_wait_abort(TX_THREAD *thread_ptr) { diff --git a/common/src/txe_timer_activate.c b/common/src/txe_timer_activate.c index 9bd62341..094eda85 100644 --- a/common/src/txe_timer_activate.c +++ b/common/src/txe_timer_activate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_timer_activate(TX_TIMER *timer_ptr) { diff --git a/common/src/txe_timer_change.c b/common/src/txe_timer_change.c index 70a7ed0d..ef503ffa 100644 --- a/common/src/txe_timer_change.c +++ b/common/src/txe_timer_change.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,14 +67,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_timer_change(TX_TIMER *timer_ptr, ULONG initial_ticks, ULONG reschedule_ticks) { diff --git a/common/src/txe_timer_create.c b/common/src/txe_timer_create.c index 553418bf..02cf7c1a 100644 --- a/common/src/txe_timer_create.c +++ b/common/src/txe_timer_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,14 +73,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_timer_create(TX_TIMER *timer_ptr, CHAR *name_ptr, VOID (*expiration_function)(ULONG id), ULONG expiration_input, diff --git a/common/src/txe_timer_deactivate.c b/common/src/txe_timer_deactivate.c index a5736919..d44ba67b 100644 --- a/common/src/txe_timer_deactivate.c +++ b/common/src/txe_timer_deactivate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,14 +61,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_timer_deactivate(TX_TIMER *timer_ptr) { diff --git a/common/src/txe_timer_delete.c b/common/src/txe_timer_delete.c index 3a1bf33c..e94ba4d6 100644 --- a/common/src/txe_timer_delete.c +++ b/common/src/txe_timer_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_timer_delete(TX_TIMER *timer_ptr) { diff --git a/common/src/txe_timer_info_get.c b/common/src/txe_timer_info_get.c index a227f137..16ac5f64 100644 --- a/common/src/txe_timer_info_get.c +++ b/common/src/txe_timer_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,14 +68,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_timer_info_get(TX_TIMER *timer_ptr, CHAR **name, UINT *active, ULONG *remaining_ticks, ULONG *reschedule_ticks, TX_TIMER **next_timer) diff --git a/common_modules/inc/txm_module.h b/common_modules/inc/txm_module.h index d8c714f9..88f79d9e 100644 --- a/common_modules/inc/txm_module.h +++ b/common_modules/inc/txm_module.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,18 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 12-31-2020 Scott Larson Modified comment(s), added */ -/* port-specific extension, */ -/* resulting in version 6.1.3 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* callback thread prototype, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_H diff --git a/common_modules/inc/txm_module_user_sample.h b/common_modules/inc/txm_module_user_sample.h index e480fc1d..889e0b91 100644 --- a/common_modules/inc/txm_module_user_sample.h +++ b/common_modules/inc/txm_module_user_sample.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -39,15 +40,6 @@ /* the command line when building Modules library and application */ /* objects. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED defines, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_USER_H diff --git a/common_modules/module_lib/src/txm_block_allocate.c b/common_modules/module_lib/src/txm_block_allocate.c index 0a98d1b8..4ab3983f 100644 --- a/common_modules/module_lib/src/txm_block_allocate.c +++ b/common_modules/module_lib/src/txm_block_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_block_allocate(TX_BLOCK_POOL *pool_ptr, VOID **block_ptr, ULONG wait_option) { diff --git a/common_modules/module_lib/src/txm_block_pool_create.c b/common_modules/module_lib/src/txm_block_pool_create.c index d4b33e2b..90838e3b 100644 --- a/common_modules/module_lib/src/txm_block_pool_create.c +++ b/common_modules/module_lib/src/txm_block_pool_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,15 +63,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_block_pool_create(TX_BLOCK_POOL *pool_ptr, CHAR *name_ptr, ULONG block_size, VOID *pool_start, ULONG pool_size, UINT pool_control_block_size) { diff --git a/common_modules/module_lib/src/txm_block_pool_delete.c b/common_modules/module_lib/src/txm_block_pool_delete.c index b32f144e..aa146b8b 100644 --- a/common_modules/module_lib/src/txm_block_pool_delete.c +++ b/common_modules/module_lib/src/txm_block_pool_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_block_pool_delete(TX_BLOCK_POOL *pool_ptr) { diff --git a/common_modules/module_lib/src/txm_block_pool_info_get.c b/common_modules/module_lib/src/txm_block_pool_info_get.c index ef61b698..fa4ea686 100644 --- a/common_modules/module_lib/src/txm_block_pool_info_get.c +++ b/common_modules/module_lib/src/txm_block_pool_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,15 +63,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_block_pool_info_get(TX_BLOCK_POOL *pool_ptr, CHAR **name, ULONG *available_blocks, ULONG *total_blocks, TX_THREAD **first_suspended, ULONG *suspended_count, TX_BLOCK_POOL **next_pool) { diff --git a/common_modules/module_lib/src/txm_block_pool_performance_info_get.c b/common_modules/module_lib/src/txm_block_pool_performance_info_get.c index 8df0375b..2c2db6b1 100644 --- a/common_modules/module_lib/src/txm_block_pool_performance_info_get.c +++ b/common_modules/module_lib/src/txm_block_pool_performance_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,15 +62,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _tx_block_pool_performance_info_get(TX_BLOCK_POOL *pool_ptr, ULONG *allocates, ULONG *releases, ULONG *suspensions, ULONG *timeouts) { diff --git a/common_modules/module_lib/src/txm_block_pool_performance_system_info_get.c b/common_modules/module_lib/src/txm_block_pool_performance_system_info_get.c index 48c1771b..ca395c31 100644 --- a/common_modules/module_lib/src/txm_block_pool_performance_system_info_get.c +++ b/common_modules/module_lib/src/txm_block_pool_performance_system_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _tx_block_pool_performance_system_info_get(ULONG *allocates, ULONG *releases, ULONG *suspensions, ULONG *timeouts) { diff --git a/common_modules/module_lib/src/txm_block_pool_prioritize.c b/common_modules/module_lib/src/txm_block_pool_prioritize.c index 467b4574..1b3fc2b4 100644 --- a/common_modules/module_lib/src/txm_block_pool_prioritize.c +++ b/common_modules/module_lib/src/txm_block_pool_prioritize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,15 +53,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_block_pool_prioritize(TX_BLOCK_POOL *pool_ptr) { diff --git a/common_modules/module_lib/src/txm_block_release.c b/common_modules/module_lib/src/txm_block_release.c index 892257cb..0d02f83f 100644 --- a/common_modules/module_lib/src/txm_block_release.c +++ b/common_modules/module_lib/src/txm_block_release.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,15 +54,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_block_release(VOID *block_ptr) { diff --git a/common_modules/module_lib/src/txm_byte_allocate.c b/common_modules/module_lib/src/txm_byte_allocate.c index 7ce96bd7..acb88e9c 100644 --- a/common_modules/module_lib/src/txm_byte_allocate.c +++ b/common_modules/module_lib/src/txm_byte_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,15 +62,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_byte_allocate(TX_BYTE_POOL *pool_ptr, VOID **memory_ptr, ULONG memory_size, ULONG wait_option) { diff --git a/common_modules/module_lib/src/txm_byte_pool_create.c b/common_modules/module_lib/src/txm_byte_pool_create.c index d37d7aeb..d7775e3f 100644 --- a/common_modules/module_lib/src/txm_byte_pool_create.c +++ b/common_modules/module_lib/src/txm_byte_pool_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,15 +62,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_byte_pool_create(TX_BYTE_POOL *pool_ptr, CHAR *name_ptr, VOID *pool_start, ULONG pool_size, UINT pool_control_block_size) { diff --git a/common_modules/module_lib/src/txm_byte_pool_delete.c b/common_modules/module_lib/src/txm_byte_pool_delete.c index 5cd7237b..c7413635 100644 --- a/common_modules/module_lib/src/txm_byte_pool_delete.c +++ b/common_modules/module_lib/src/txm_byte_pool_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_byte_pool_delete(TX_BYTE_POOL *pool_ptr) { diff --git a/common_modules/module_lib/src/txm_byte_pool_info_get.c b/common_modules/module_lib/src/txm_byte_pool_info_get.c index f2d2bb81..1ad38f48 100644 --- a/common_modules/module_lib/src/txm_byte_pool_info_get.c +++ b/common_modules/module_lib/src/txm_byte_pool_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,15 +63,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_byte_pool_info_get(TX_BYTE_POOL *pool_ptr, CHAR **name, ULONG *available_bytes, ULONG *fragments, TX_THREAD **first_suspended, ULONG *suspended_count, TX_BYTE_POOL **next_pool) { diff --git a/common_modules/module_lib/src/txm_byte_pool_performance_info_get.c b/common_modules/module_lib/src/txm_byte_pool_performance_info_get.c index d0baf652..9c23d749 100644 --- a/common_modules/module_lib/src/txm_byte_pool_performance_info_get.c +++ b/common_modules/module_lib/src/txm_byte_pool_performance_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -69,15 +70,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _tx_byte_pool_performance_info_get(TX_BYTE_POOL *pool_ptr, ULONG *allocates, ULONG *releases, ULONG *fragments_searched, ULONG *merges, ULONG *splits, ULONG *suspensions, ULONG *timeouts) { diff --git a/common_modules/module_lib/src/txm_byte_pool_performance_system_info_get.c b/common_modules/module_lib/src/txm_byte_pool_performance_system_info_get.c index 806c283a..c9d92fa8 100644 --- a/common_modules/module_lib/src/txm_byte_pool_performance_system_info_get.c +++ b/common_modules/module_lib/src/txm_byte_pool_performance_system_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,15 +68,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _tx_byte_pool_performance_system_info_get(ULONG *allocates, ULONG *releases, ULONG *fragments_searched, ULONG *merges, ULONG *splits, ULONG *suspensions, ULONG *timeouts) { diff --git a/common_modules/module_lib/src/txm_byte_pool_prioritize.c b/common_modules/module_lib/src/txm_byte_pool_prioritize.c index 261679f7..6b1a47d4 100644 --- a/common_modules/module_lib/src/txm_byte_pool_prioritize.c +++ b/common_modules/module_lib/src/txm_byte_pool_prioritize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,15 +53,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_byte_pool_prioritize(TX_BYTE_POOL *pool_ptr) { diff --git a/common_modules/module_lib/src/txm_byte_release.c b/common_modules/module_lib/src/txm_byte_release.c index 54d57b95..aef10b3e 100644 --- a/common_modules/module_lib/src/txm_byte_release.c +++ b/common_modules/module_lib/src/txm_byte_release.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_byte_release(VOID *memory_ptr) { diff --git a/common_modules/module_lib/src/txm_event_flags_create.c b/common_modules/module_lib/src/txm_event_flags_create.c index 482cff18..76f1fe31 100644 --- a/common_modules/module_lib/src/txm_event_flags_create.c +++ b/common_modules/module_lib/src/txm_event_flags_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,15 +59,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_event_flags_create(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR *name_ptr, UINT event_control_block_size) { diff --git a/common_modules/module_lib/src/txm_event_flags_delete.c b/common_modules/module_lib/src/txm_event_flags_delete.c index 1b347c22..8ddbe611 100644 --- a/common_modules/module_lib/src/txm_event_flags_delete.c +++ b/common_modules/module_lib/src/txm_event_flags_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_event_flags_delete(TX_EVENT_FLAGS_GROUP *group_ptr) { diff --git a/common_modules/module_lib/src/txm_event_flags_get.c b/common_modules/module_lib/src/txm_event_flags_get.c index e8b0e5bf..5c1e2b6f 100644 --- a/common_modules/module_lib/src/txm_event_flags_get.c +++ b/common_modules/module_lib/src/txm_event_flags_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,15 +64,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_event_flags_get(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG requested_flags, UINT get_option, ULONG *actual_flags_ptr, ULONG wait_option) { diff --git a/common_modules/module_lib/src/txm_event_flags_info_get.c b/common_modules/module_lib/src/txm_event_flags_info_get.c index 3fac9791..eedcce1f 100644 --- a/common_modules/module_lib/src/txm_event_flags_info_get.c +++ b/common_modules/module_lib/src/txm_event_flags_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,15 +64,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_event_flags_info_get(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR **name, ULONG *current_flags, TX_THREAD **first_suspended, ULONG *suspended_count, TX_EVENT_FLAGS_GROUP **next_group) { diff --git a/common_modules/module_lib/src/txm_event_flags_performance_info_get.c b/common_modules/module_lib/src/txm_event_flags_performance_info_get.c index febcc5a6..1aac708c 100644 --- a/common_modules/module_lib/src/txm_event_flags_performance_info_get.c +++ b/common_modules/module_lib/src/txm_event_flags_performance_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,15 +63,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _tx_event_flags_performance_info_get(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG *sets, ULONG *gets, ULONG *suspensions, ULONG *timeouts) { diff --git a/common_modules/module_lib/src/txm_event_flags_performance_system_info_get.c b/common_modules/module_lib/src/txm_event_flags_performance_system_info_get.c index ff07989e..bb0230ee 100644 --- a/common_modules/module_lib/src/txm_event_flags_performance_system_info_get.c +++ b/common_modules/module_lib/src/txm_event_flags_performance_system_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _tx_event_flags_performance_system_info_get(ULONG *sets, ULONG *gets, ULONG *suspensions, ULONG *timeouts) { diff --git a/common_modules/module_lib/src/txm_event_flags_set.c b/common_modules/module_lib/src/txm_event_flags_set.c index 20999272..6c5e155e 100644 --- a/common_modules/module_lib/src/txm_event_flags_set.c +++ b/common_modules/module_lib/src/txm_event_flags_set.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,15 +59,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_event_flags_set(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG flags_to_set, UINT set_option) { diff --git a/common_modules/module_lib/src/txm_event_flags_set_notify.c b/common_modules/module_lib/src/txm_event_flags_set_notify.c index 8564c847..84c8b6ce 100644 --- a/common_modules/module_lib/src/txm_event_flags_set_notify.c +++ b/common_modules/module_lib/src/txm_event_flags_set_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_event_flags_set_notify(TX_EVENT_FLAGS_GROUP *group_ptr, VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *)) { diff --git a/common_modules/module_lib/src/txm_module_application_request.c b/common_modules/module_lib/src/txm_module_application_request.c index 1c452767..3c65c080 100644 --- a/common_modules/module_lib/src/txm_module_application_request.c +++ b/common_modules/module_lib/src/txm_module_application_request.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT txm_module_application_request(ULONG request, ALIGN_TYPE param_1, ALIGN_TYPE param_2, ALIGN_TYPE param_3) { diff --git a/common_modules/module_lib/src/txm_module_callback_request_thread_entry.c b/common_modules/module_lib/src/txm_module_callback_request_thread_entry.c index 16015755..cf030f92 100644 --- a/common_modules/module_lib/src/txm_module_callback_request_thread_entry.c +++ b/common_modules/module_lib/src/txm_module_callback_request_thread_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -73,15 +74,6 @@ extern TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_callback_request_thread_entry(ULONG id) { diff --git a/common_modules/module_lib/src/txm_module_object_allocate.c b/common_modules/module_lib/src/txm_module_object_allocate.c index 40d548fb..2cf169d5 100644 --- a/common_modules/module_lib/src/txm_module_object_allocate.c +++ b/common_modules/module_lib/src/txm_module_object_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,15 +59,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txm_module_object_allocate(VOID **object_ptr, ULONG object_size) { diff --git a/common_modules/module_lib/src/txm_module_object_deallocate.c b/common_modules/module_lib/src/txm_module_object_deallocate.c index 100c4e9f..c0ffb097 100644 --- a/common_modules/module_lib/src/txm_module_object_deallocate.c +++ b/common_modules/module_lib/src/txm_module_object_deallocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,15 +53,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txm_module_object_deallocate(VOID *object_ptr) { diff --git a/common_modules/module_lib/src/txm_module_object_pointer_get.c b/common_modules/module_lib/src/txm_module_object_pointer_get.c index 921d0fa9..6417457a 100644 --- a/common_modules/module_lib/src/txm_module_object_pointer_get.c +++ b/common_modules/module_lib/src/txm_module_object_pointer_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,15 +69,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txm_module_object_pointer_get(UINT object_type, CHAR *name, VOID **object_ptr) { diff --git a/common_modules/module_lib/src/txm_module_object_pointer_get_extended.c b/common_modules/module_lib/src/txm_module_object_pointer_get_extended.c index 87d986aa..b820cf1d 100644 --- a/common_modules/module_lib/src/txm_module_object_pointer_get_extended.c +++ b/common_modules/module_lib/src/txm_module_object_pointer_get_extended.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,15 +72,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txm_module_object_pointer_get_extended(UINT object_type, CHAR *name, UINT name_length, VOID **object_ptr) { diff --git a/common_modules/module_lib/src/txm_module_thread_system_suspend.c b/common_modules/module_lib/src/txm_module_thread_system_suspend.c index 46129074..ad8e8ea7 100644 --- a/common_modules/module_lib/src/txm_module_thread_system_suspend.c +++ b/common_modules/module_lib/src/txm_module_thread_system_suspend.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,15 +61,6 @@ /* _tx_thread_terminate Thread terminate */ /* Other ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txm_module_thread_system_suspend(TX_THREAD *thread_ptr) { diff --git a/common_modules/module_lib/src/txm_mutex_create.c b/common_modules/module_lib/src/txm_mutex_create.c index 19e8d03b..f50fd52f 100644 --- a/common_modules/module_lib/src/txm_mutex_create.c +++ b/common_modules/module_lib/src/txm_mutex_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_mutex_create(TX_MUTEX *mutex_ptr, CHAR *name_ptr, UINT inherit, UINT mutex_control_block_size) { diff --git a/common_modules/module_lib/src/txm_mutex_delete.c b/common_modules/module_lib/src/txm_mutex_delete.c index 9989ac8a..c487744e 100644 --- a/common_modules/module_lib/src/txm_mutex_delete.c +++ b/common_modules/module_lib/src/txm_mutex_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_mutex_delete(TX_MUTEX *mutex_ptr) { diff --git a/common_modules/module_lib/src/txm_mutex_get.c b/common_modules/module_lib/src/txm_mutex_get.c index 88da1ca3..fb6191e2 100644 --- a/common_modules/module_lib/src/txm_mutex_get.c +++ b/common_modules/module_lib/src/txm_mutex_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_mutex_get(TX_MUTEX *mutex_ptr, ULONG wait_option) { diff --git a/common_modules/module_lib/src/txm_mutex_info_get.c b/common_modules/module_lib/src/txm_mutex_info_get.c index 981b7959..8e63c779 100644 --- a/common_modules/module_lib/src/txm_mutex_info_get.c +++ b/common_modules/module_lib/src/txm_mutex_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,15 +64,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_mutex_info_get(TX_MUTEX *mutex_ptr, CHAR **name, ULONG *count, TX_THREAD **owner, TX_THREAD **first_suspended, ULONG *suspended_count, TX_MUTEX **next_mutex) { diff --git a/common_modules/module_lib/src/txm_mutex_performance_info_get.c b/common_modules/module_lib/src/txm_mutex_performance_info_get.c index 26bbde81..95e1045b 100644 --- a/common_modules/module_lib/src/txm_mutex_performance_info_get.c +++ b/common_modules/module_lib/src/txm_mutex_performance_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,15 +66,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _tx_mutex_performance_info_get(TX_MUTEX *mutex_ptr, ULONG *puts, ULONG *gets, ULONG *suspensions, ULONG *timeouts, ULONG *inversions, ULONG *inheritances) { diff --git a/common_modules/module_lib/src/txm_mutex_performance_system_info_get.c b/common_modules/module_lib/src/txm_mutex_performance_system_info_get.c index 29906c9f..1c899abd 100644 --- a/common_modules/module_lib/src/txm_mutex_performance_system_info_get.c +++ b/common_modules/module_lib/src/txm_mutex_performance_system_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,15 +64,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _tx_mutex_performance_system_info_get(ULONG *puts, ULONG *gets, ULONG *suspensions, ULONG *timeouts, ULONG *inversions, ULONG *inheritances) { diff --git a/common_modules/module_lib/src/txm_mutex_prioritize.c b/common_modules/module_lib/src/txm_mutex_prioritize.c index e0b596ec..32223b5f 100644 --- a/common_modules/module_lib/src/txm_mutex_prioritize.c +++ b/common_modules/module_lib/src/txm_mutex_prioritize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,15 +53,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_mutex_prioritize(TX_MUTEX *mutex_ptr) { diff --git a/common_modules/module_lib/src/txm_mutex_put.c b/common_modules/module_lib/src/txm_mutex_put.c index fc19b69b..d0e03d02 100644 --- a/common_modules/module_lib/src/txm_mutex_put.c +++ b/common_modules/module_lib/src/txm_mutex_put.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,15 +54,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_mutex_put(TX_MUTEX *mutex_ptr) { diff --git a/common_modules/module_lib/src/txm_queue_create.c b/common_modules/module_lib/src/txm_queue_create.c index 890abc43..a18b9f85 100644 --- a/common_modules/module_lib/src/txm_queue_create.c +++ b/common_modules/module_lib/src/txm_queue_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,15 +61,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_queue_create(TX_QUEUE *queue_ptr, CHAR *name_ptr, UINT message_size, VOID *queue_start, ULONG queue_size, UINT queue_control_block_size) { diff --git a/common_modules/module_lib/src/txm_queue_delete.c b/common_modules/module_lib/src/txm_queue_delete.c index 36377bfc..f39ddb99 100644 --- a/common_modules/module_lib/src/txm_queue_delete.c +++ b/common_modules/module_lib/src/txm_queue_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_queue_delete(TX_QUEUE *queue_ptr) { diff --git a/common_modules/module_lib/src/txm_queue_flush.c b/common_modules/module_lib/src/txm_queue_flush.c index 26a1c20d..5f33c111 100644 --- a/common_modules/module_lib/src/txm_queue_flush.c +++ b/common_modules/module_lib/src/txm_queue_flush.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_queue_flush(TX_QUEUE *queue_ptr) { diff --git a/common_modules/module_lib/src/txm_queue_front_send.c b/common_modules/module_lib/src/txm_queue_front_send.c index 09532f80..64555e83 100644 --- a/common_modules/module_lib/src/txm_queue_front_send.c +++ b/common_modules/module_lib/src/txm_queue_front_send.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_queue_front_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option) { diff --git a/common_modules/module_lib/src/txm_queue_info_get.c b/common_modules/module_lib/src/txm_queue_info_get.c index 67e814ea..c66a3d7e 100644 --- a/common_modules/module_lib/src/txm_queue_info_get.c +++ b/common_modules/module_lib/src/txm_queue_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,15 +63,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_queue_info_get(TX_QUEUE *queue_ptr, CHAR **name, ULONG *enqueued, ULONG *available_storage, TX_THREAD **first_suspended, ULONG *suspended_count, TX_QUEUE **next_queue) { diff --git a/common_modules/module_lib/src/txm_queue_performance_info_get.c b/common_modules/module_lib/src/txm_queue_performance_info_get.c index 6eb65642..a7c77eee 100644 --- a/common_modules/module_lib/src/txm_queue_performance_info_get.c +++ b/common_modules/module_lib/src/txm_queue_performance_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,15 +64,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _tx_queue_performance_info_get(TX_QUEUE *queue_ptr, ULONG *messages_sent, ULONG *messages_received, ULONG *empty_suspensions, ULONG *full_suspensions, ULONG *full_errors, ULONG *timeouts) { diff --git a/common_modules/module_lib/src/txm_queue_performance_system_info_get.c b/common_modules/module_lib/src/txm_queue_performance_system_info_get.c index 78bd22dd..9a09fd5a 100644 --- a/common_modules/module_lib/src/txm_queue_performance_system_info_get.c +++ b/common_modules/module_lib/src/txm_queue_performance_system_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,15 +64,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _tx_queue_performance_system_info_get(ULONG *messages_sent, ULONG *messages_received, ULONG *empty_suspensions, ULONG *full_suspensions, ULONG *full_errors, ULONG *timeouts) { diff --git a/common_modules/module_lib/src/txm_queue_prioritize.c b/common_modules/module_lib/src/txm_queue_prioritize.c index cc6badb7..417ad17a 100644 --- a/common_modules/module_lib/src/txm_queue_prioritize.c +++ b/common_modules/module_lib/src/txm_queue_prioritize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,15 +53,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_queue_prioritize(TX_QUEUE *queue_ptr) { diff --git a/common_modules/module_lib/src/txm_queue_receive.c b/common_modules/module_lib/src/txm_queue_receive.c index c7839127..07a9c8f3 100644 --- a/common_modules/module_lib/src/txm_queue_receive.c +++ b/common_modules/module_lib/src/txm_queue_receive.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_queue_receive(TX_QUEUE *queue_ptr, VOID *destination_ptr, ULONG wait_option) { diff --git a/common_modules/module_lib/src/txm_queue_send.c b/common_modules/module_lib/src/txm_queue_send.c index 0c5304b2..0fd522b2 100644 --- a/common_modules/module_lib/src/txm_queue_send.c +++ b/common_modules/module_lib/src/txm_queue_send.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_queue_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option) { diff --git a/common_modules/module_lib/src/txm_queue_send_notify.c b/common_modules/module_lib/src/txm_queue_send_notify.c index 5b8e782e..dab5d5b0 100644 --- a/common_modules/module_lib/src/txm_queue_send_notify.c +++ b/common_modules/module_lib/src/txm_queue_send_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_queue_send_notify(TX_QUEUE *queue_ptr, VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)) { diff --git a/common_modules/module_lib/src/txm_semaphore_ceiling_put.c b/common_modules/module_lib/src/txm_semaphore_ceiling_put.c index 55765072..10d76090 100644 --- a/common_modules/module_lib/src/txm_semaphore_ceiling_put.c +++ b/common_modules/module_lib/src/txm_semaphore_ceiling_put.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_semaphore_ceiling_put(TX_SEMAPHORE *semaphore_ptr, ULONG ceiling) { diff --git a/common_modules/module_lib/src/txm_semaphore_create.c b/common_modules/module_lib/src/txm_semaphore_create.c index 671892cb..229b46cd 100644 --- a/common_modules/module_lib/src/txm_semaphore_create.c +++ b/common_modules/module_lib/src/txm_semaphore_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,15 +59,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_semaphore_create(TX_SEMAPHORE *semaphore_ptr, CHAR *name_ptr, ULONG initial_count, UINT semaphore_control_block_size) { diff --git a/common_modules/module_lib/src/txm_semaphore_delete.c b/common_modules/module_lib/src/txm_semaphore_delete.c index 0229bf69..08dfebbf 100644 --- a/common_modules/module_lib/src/txm_semaphore_delete.c +++ b/common_modules/module_lib/src/txm_semaphore_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_semaphore_delete(TX_SEMAPHORE *semaphore_ptr) { diff --git a/common_modules/module_lib/src/txm_semaphore_get.c b/common_modules/module_lib/src/txm_semaphore_get.c index 2ab634de..9745da0b 100644 --- a/common_modules/module_lib/src/txm_semaphore_get.c +++ b/common_modules/module_lib/src/txm_semaphore_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_semaphore_get(TX_SEMAPHORE *semaphore_ptr, ULONG wait_option) { diff --git a/common_modules/module_lib/src/txm_semaphore_info_get.c b/common_modules/module_lib/src/txm_semaphore_info_get.c index 0627fe7c..2bdfa2c0 100644 --- a/common_modules/module_lib/src/txm_semaphore_info_get.c +++ b/common_modules/module_lib/src/txm_semaphore_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,15 +63,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_semaphore_info_get(TX_SEMAPHORE *semaphore_ptr, CHAR **name, ULONG *current_value, TX_THREAD **first_suspended, ULONG *suspended_count, TX_SEMAPHORE **next_semaphore) { diff --git a/common_modules/module_lib/src/txm_semaphore_performance_info_get.c b/common_modules/module_lib/src/txm_semaphore_performance_info_get.c index 1c09d2f1..13204bc9 100644 --- a/common_modules/module_lib/src/txm_semaphore_performance_info_get.c +++ b/common_modules/module_lib/src/txm_semaphore_performance_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,15 +62,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _tx_semaphore_performance_info_get(TX_SEMAPHORE *semaphore_ptr, ULONG *puts, ULONG *gets, ULONG *suspensions, ULONG *timeouts) { diff --git a/common_modules/module_lib/src/txm_semaphore_performance_system_info_get.c b/common_modules/module_lib/src/txm_semaphore_performance_system_info_get.c index 9a50edb9..7d196030 100644 --- a/common_modules/module_lib/src/txm_semaphore_performance_system_info_get.c +++ b/common_modules/module_lib/src/txm_semaphore_performance_system_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _tx_semaphore_performance_system_info_get(ULONG *puts, ULONG *gets, ULONG *suspensions, ULONG *timeouts) { diff --git a/common_modules/module_lib/src/txm_semaphore_prioritize.c b/common_modules/module_lib/src/txm_semaphore_prioritize.c index 02cd2a9f..2a72de20 100644 --- a/common_modules/module_lib/src/txm_semaphore_prioritize.c +++ b/common_modules/module_lib/src/txm_semaphore_prioritize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,15 +53,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_semaphore_prioritize(TX_SEMAPHORE *semaphore_ptr) { diff --git a/common_modules/module_lib/src/txm_semaphore_put.c b/common_modules/module_lib/src/txm_semaphore_put.c index 2ea4c04e..0e0831b3 100644 --- a/common_modules/module_lib/src/txm_semaphore_put.c +++ b/common_modules/module_lib/src/txm_semaphore_put.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,15 +54,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_semaphore_put(TX_SEMAPHORE *semaphore_ptr) { diff --git a/common_modules/module_lib/src/txm_semaphore_put_notify.c b/common_modules/module_lib/src/txm_semaphore_put_notify.c index db7dea85..05c916fd 100644 --- a/common_modules/module_lib/src/txm_semaphore_put_notify.c +++ b/common_modules/module_lib/src/txm_semaphore_put_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_semaphore_put_notify(TX_SEMAPHORE *semaphore_ptr, VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)) { diff --git a/common_modules/module_lib/src/txm_thread_create.c b/common_modules/module_lib/src/txm_thread_create.c index 62618314..8b1bc367 100644 --- a/common_modules/module_lib/src/txm_thread_create.c +++ b/common_modules/module_lib/src/txm_thread_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,15 +69,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr, VOID (*entry_function)(ULONG entry_input), ULONG entry_input, VOID *stack_start, ULONG stack_size, UINT priority, UINT preempt_threshold, ULONG time_slice, UINT auto_start, UINT thread_control_block_size) { diff --git a/common_modules/module_lib/src/txm_thread_delete.c b/common_modules/module_lib/src/txm_thread_delete.c index 641c220d..11a1bbd6 100644 --- a/common_modules/module_lib/src/txm_thread_delete.c +++ b/common_modules/module_lib/src/txm_thread_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_thread_delete(TX_THREAD *thread_ptr) { diff --git a/common_modules/module_lib/src/txm_thread_entry_exit_notify.c b/common_modules/module_lib/src/txm_thread_entry_exit_notify.c index 907840d6..db393071 100644 --- a/common_modules/module_lib/src/txm_thread_entry_exit_notify.c +++ b/common_modules/module_lib/src/txm_thread_entry_exit_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_thread_entry_exit_notify(TX_THREAD *thread_ptr, VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT type)) { diff --git a/common_modules/module_lib/src/txm_thread_identify.c b/common_modules/module_lib/src/txm_thread_identify.c index d18aaec1..6f83cb80 100644 --- a/common_modules/module_lib/src/txm_thread_identify.c +++ b/common_modules/module_lib/src/txm_thread_identify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ TX_THREAD *_tx_thread_identify(VOID) { diff --git a/common_modules/module_lib/src/txm_thread_info_get.c b/common_modules/module_lib/src/txm_thread_info_get.c index 6e2b921c..d956c031 100644 --- a/common_modules/module_lib/src/txm_thread_info_get.c +++ b/common_modules/module_lib/src/txm_thread_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,15 +66,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_thread_info_get(TX_THREAD *thread_ptr, CHAR **name, UINT *state, ULONG *run_count, UINT *priority, UINT *preemption_threshold, ULONG *time_slice, TX_THREAD **next_thread, TX_THREAD **next_suspended_thread) { diff --git a/common_modules/module_lib/src/txm_thread_interrupt_control.c b/common_modules/module_lib/src/txm_thread_interrupt_control.c index 915b56b9..7a4cf51f 100644 --- a/common_modules/module_lib/src/txm_thread_interrupt_control.c +++ b/common_modules/module_lib/src/txm_thread_interrupt_control.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _tx_thread_interrupt_control(UINT new_posture) { diff --git a/common_modules/module_lib/src/txm_thread_performance_info_get.c b/common_modules/module_lib/src/txm_thread_performance_info_get.c index 362c50e6..c6ab325b 100644 --- a/common_modules/module_lib/src/txm_thread_performance_info_get.c +++ b/common_modules/module_lib/src/txm_thread_performance_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -78,15 +79,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _tx_thread_performance_info_get(TX_THREAD *thread_ptr, ULONG *resumptions, ULONG *suspensions, ULONG *solicited_preemptions, ULONG *interrupt_preemptions, ULONG *priority_inversions, ULONG *time_slices, ULONG *relinquishes, ULONG *timeouts, ULONG *wait_aborts, TX_THREAD **last_preempted_by) { diff --git a/common_modules/module_lib/src/txm_thread_performance_system_info_get.c b/common_modules/module_lib/src/txm_thread_performance_system_info_get.c index 3bafa024..efe49868 100644 --- a/common_modules/module_lib/src/txm_thread_performance_system_info_get.c +++ b/common_modules/module_lib/src/txm_thread_performance_system_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -78,15 +79,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _tx_thread_performance_system_info_get(ULONG *resumptions, ULONG *suspensions, ULONG *solicited_preemptions, ULONG *interrupt_preemptions, ULONG *priority_inversions, ULONG *time_slices, ULONG *relinquishes, ULONG *timeouts, ULONG *wait_aborts, ULONG *non_idle_returns, ULONG *idle_returns) { diff --git a/common_modules/module_lib/src/txm_thread_preemption_change.c b/common_modules/module_lib/src/txm_thread_preemption_change.c index 617b99d1..8c956942 100644 --- a/common_modules/module_lib/src/txm_thread_preemption_change.c +++ b/common_modules/module_lib/src/txm_thread_preemption_change.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,15 +59,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_thread_preemption_change(TX_THREAD *thread_ptr, UINT new_threshold, UINT *old_threshold) { diff --git a/common_modules/module_lib/src/txm_thread_priority_change.c b/common_modules/module_lib/src/txm_thread_priority_change.c index 82193749..a31ad09f 100644 --- a/common_modules/module_lib/src/txm_thread_priority_change.c +++ b/common_modules/module_lib/src/txm_thread_priority_change.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,15 +59,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_thread_priority_change(TX_THREAD *thread_ptr, UINT new_priority, UINT *old_priority) { diff --git a/common_modules/module_lib/src/txm_thread_relinquish.c b/common_modules/module_lib/src/txm_thread_relinquish.c index c8cf6b3e..347ab163 100644 --- a/common_modules/module_lib/src/txm_thread_relinquish.c +++ b/common_modules/module_lib/src/txm_thread_relinquish.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,15 +54,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txe_thread_relinquish(VOID) { diff --git a/common_modules/module_lib/src/txm_thread_reset.c b/common_modules/module_lib/src/txm_thread_reset.c index f53506dd..b3c00290 100644 --- a/common_modules/module_lib/src/txm_thread_reset.c +++ b/common_modules/module_lib/src/txm_thread_reset.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_thread_reset(TX_THREAD *thread_ptr) { diff --git a/common_modules/module_lib/src/txm_thread_resume.c b/common_modules/module_lib/src/txm_thread_resume.c index a6023a62..a02100bc 100644 --- a/common_modules/module_lib/src/txm_thread_resume.c +++ b/common_modules/module_lib/src/txm_thread_resume.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,15 +54,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_thread_resume(TX_THREAD *thread_ptr) { diff --git a/common_modules/module_lib/src/txm_thread_sleep.c b/common_modules/module_lib/src/txm_thread_sleep.c index 8dccdab5..d5639af2 100644 --- a/common_modules/module_lib/src/txm_thread_sleep.c +++ b/common_modules/module_lib/src/txm_thread_sleep.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,15 +54,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _tx_thread_sleep(ULONG timer_ticks) { diff --git a/common_modules/module_lib/src/txm_thread_stack_error_notify.c b/common_modules/module_lib/src/txm_thread_stack_error_notify.c index 67fd4c79..eafb4b50 100644 --- a/common_modules/module_lib/src/txm_thread_stack_error_notify.c +++ b/common_modules/module_lib/src/txm_thread_stack_error_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) { diff --git a/common_modules/module_lib/src/txm_thread_suspend.c b/common_modules/module_lib/src/txm_thread_suspend.c index e0f6ab21..69a31b31 100644 --- a/common_modules/module_lib/src/txm_thread_suspend.c +++ b/common_modules/module_lib/src/txm_thread_suspend.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_thread_suspend(TX_THREAD *thread_ptr) { diff --git a/common_modules/module_lib/src/txm_thread_terminate.c b/common_modules/module_lib/src/txm_thread_terminate.c index 37b3fc92..65eb13ab 100644 --- a/common_modules/module_lib/src/txm_thread_terminate.c +++ b/common_modules/module_lib/src/txm_thread_terminate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_thread_terminate(TX_THREAD *thread_ptr) { diff --git a/common_modules/module_lib/src/txm_thread_time_slice_change.c b/common_modules/module_lib/src/txm_thread_time_slice_change.c index 581b13a9..bb7cc4eb 100644 --- a/common_modules/module_lib/src/txm_thread_time_slice_change.c +++ b/common_modules/module_lib/src/txm_thread_time_slice_change.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_thread_time_slice_change(TX_THREAD *thread_ptr, ULONG new_time_slice, ULONG *old_time_slice) { diff --git a/common_modules/module_lib/src/txm_thread_wait_abort.c b/common_modules/module_lib/src/txm_thread_wait_abort.c index fdf62e4c..e827946b 100644 --- a/common_modules/module_lib/src/txm_thread_wait_abort.c +++ b/common_modules/module_lib/src/txm_thread_wait_abort.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,15 +54,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_thread_wait_abort(TX_THREAD *thread_ptr) { diff --git a/common_modules/module_lib/src/txm_time_get.c b/common_modules/module_lib/src/txm_time_get.c index f31570c6..fd73e4bc 100644 --- a/common_modules/module_lib/src/txm_time_get.c +++ b/common_modules/module_lib/src/txm_time_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,15 +54,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ ULONG _tx_time_get(VOID) { diff --git a/common_modules/module_lib/src/txm_time_set.c b/common_modules/module_lib/src/txm_time_set.c index 87030665..8e36663d 100644 --- a/common_modules/module_lib/src/txm_time_set.c +++ b/common_modules/module_lib/src/txm_time_set.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,15 +54,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_time_set(ULONG new_time) { diff --git a/common_modules/module_lib/src/txm_timer_activate.c b/common_modules/module_lib/src/txm_timer_activate.c index 87bd6c9c..357be63e 100644 --- a/common_modules/module_lib/src/txm_timer_activate.c +++ b/common_modules/module_lib/src/txm_timer_activate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_timer_activate(TX_TIMER *timer_ptr) { diff --git a/common_modules/module_lib/src/txm_timer_change.c b/common_modules/module_lib/src/txm_timer_change.c index 3e694d4b..85bdff87 100644 --- a/common_modules/module_lib/src/txm_timer_change.c +++ b/common_modules/module_lib/src/txm_timer_change.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,15 +59,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_timer_change(TX_TIMER *timer_ptr, ULONG initial_ticks, ULONG reschedule_ticks) { diff --git a/common_modules/module_lib/src/txm_timer_create.c b/common_modules/module_lib/src/txm_timer_create.c index eca01d04..d65989eb 100644 --- a/common_modules/module_lib/src/txm_timer_create.c +++ b/common_modules/module_lib/src/txm_timer_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,15 +64,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_timer_create(TX_TIMER *timer_ptr, CHAR *name_ptr, VOID (*expiration_function)(ULONG), ULONG expiration_input, ULONG initial_ticks, ULONG reschedule_ticks, UINT auto_activate, UINT timer_control_block_size) { diff --git a/common_modules/module_lib/src/txm_timer_deactivate.c b/common_modules/module_lib/src/txm_timer_deactivate.c index 532dfe9d..5420ba5c 100644 --- a/common_modules/module_lib/src/txm_timer_deactivate.c +++ b/common_modules/module_lib/src/txm_timer_deactivate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_timer_deactivate(TX_TIMER *timer_ptr) { diff --git a/common_modules/module_lib/src/txm_timer_delete.c b/common_modules/module_lib/src/txm_timer_delete.c index 3a316278..a8b116a8 100644 --- a/common_modules/module_lib/src/txm_timer_delete.c +++ b/common_modules/module_lib/src/txm_timer_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_timer_delete(TX_TIMER *timer_ptr) { diff --git a/common_modules/module_lib/src/txm_timer_info_get.c b/common_modules/module_lib/src/txm_timer_info_get.c index 767012ab..f918ca67 100644 --- a/common_modules/module_lib/src/txm_timer_info_get.c +++ b/common_modules/module_lib/src/txm_timer_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,15 +62,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txe_timer_info_get(TX_TIMER *timer_ptr, CHAR **name, UINT *active, ULONG *remaining_ticks, ULONG *reschedule_ticks, TX_TIMER **next_timer) { diff --git a/common_modules/module_lib/src/txm_timer_performance_info_get.c b/common_modules/module_lib/src/txm_timer_performance_info_get.c index 620dbb9f..9e9c1ea4 100644 --- a/common_modules/module_lib/src/txm_timer_performance_info_get.c +++ b/common_modules/module_lib/src/txm_timer_performance_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,15 +65,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _tx_timer_performance_info_get(TX_TIMER *timer_ptr, ULONG *activates, ULONG *reactivates, ULONG *deactivates, ULONG *expirations, ULONG *expiration_adjusts) { diff --git a/common_modules/module_lib/src/txm_timer_performance_system_info_get.c b/common_modules/module_lib/src/txm_timer_performance_system_info_get.c index 02b98518..202ad1ad 100644 --- a/common_modules/module_lib/src/txm_timer_performance_system_info_get.c +++ b/common_modules/module_lib/src/txm_timer_performance_system_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,15 +62,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _tx_timer_performance_system_info_get(ULONG *activates, ULONG *reactivates, ULONG *deactivates, ULONG *expirations, ULONG *expiration_adjusts) { diff --git a/common_modules/module_lib/src/txm_trace_buffer_full_notify.c b/common_modules/module_lib/src/txm_trace_buffer_full_notify.c index 3e46bfe4..3494b741 100644 --- a/common_modules/module_lib/src/txm_trace_buffer_full_notify.c +++ b/common_modules/module_lib/src/txm_trace_buffer_full_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _tx_trace_buffer_full_notify(VOID (*full_buffer_callback)(VOID *buffer)) { diff --git a/common_modules/module_lib/src/txm_trace_disable.c b/common_modules/module_lib/src/txm_trace_disable.c index 569db575..9861533b 100644 --- a/common_modules/module_lib/src/txm_trace_disable.c +++ b/common_modules/module_lib/src/txm_trace_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,15 +53,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _tx_trace_disable(VOID) { diff --git a/common_modules/module_lib/src/txm_trace_enable.c b/common_modules/module_lib/src/txm_trace_enable.c index fd3532e3..3355520e 100644 --- a/common_modules/module_lib/src/txm_trace_enable.c +++ b/common_modules/module_lib/src/txm_trace_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _tx_trace_enable(VOID *trace_buffer_start, ULONG trace_buffer_size, ULONG registry_entries) { diff --git a/common_modules/module_lib/src/txm_trace_event_filter.c b/common_modules/module_lib/src/txm_trace_event_filter.c index 526fd690..1eeb9d4b 100644 --- a/common_modules/module_lib/src/txm_trace_event_filter.c +++ b/common_modules/module_lib/src/txm_trace_event_filter.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,15 +54,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _tx_trace_event_filter(ULONG event_filter_bits) { diff --git a/common_modules/module_lib/src/txm_trace_event_unfilter.c b/common_modules/module_lib/src/txm_trace_event_unfilter.c index e5ca5d69..66ec727e 100644 --- a/common_modules/module_lib/src/txm_trace_event_unfilter.c +++ b/common_modules/module_lib/src/txm_trace_event_unfilter.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,15 +54,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _tx_trace_event_unfilter(ULONG event_unfilter_bits) { diff --git a/common_modules/module_lib/src/txm_trace_interrupt_control.c b/common_modules/module_lib/src/txm_trace_interrupt_control.c index a26651f5..4bd9028c 100644 --- a/common_modules/module_lib/src/txm_trace_interrupt_control.c +++ b/common_modules/module_lib/src/txm_trace_interrupt_control.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,15 +54,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _tx_trace_interrupt_control(UINT new_posture) { diff --git a/common_modules/module_lib/src/txm_trace_isr_enter_insert.c b/common_modules/module_lib/src/txm_trace_isr_enter_insert.c index 9411443b..19a8ad18 100644 --- a/common_modules/module_lib/src/txm_trace_isr_enter_insert.c +++ b/common_modules/module_lib/src/txm_trace_isr_enter_insert.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,15 +54,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_trace_isr_enter_insert(ULONG isr_id) { diff --git a/common_modules/module_lib/src/txm_trace_isr_exit_insert.c b/common_modules/module_lib/src/txm_trace_isr_exit_insert.c index b686cb7c..3b60c0fb 100644 --- a/common_modules/module_lib/src/txm_trace_isr_exit_insert.c +++ b/common_modules/module_lib/src/txm_trace_isr_exit_insert.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,15 +54,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_trace_isr_exit_insert(ULONG isr_id) { diff --git a/common_modules/module_lib/src/txm_trace_user_event_insert.c b/common_modules/module_lib/src/txm_trace_user_event_insert.c index c3d0e0cb..dfe7dd23 100644 --- a/common_modules/module_lib/src/txm_trace_user_event_insert.c +++ b/common_modules/module_lib/src/txm_trace_user_event_insert.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _tx_trace_user_event_insert(ULONG event_id, ULONG info_field_1, ULONG info_field_2, ULONG info_field_3, ULONG info_field_4) { diff --git a/common_modules/module_manager/inc/txm_module_manager_dispatch.h b/common_modules/module_manager/inc/txm_module_manager_dispatch.h index 0ac2210d..03bd86eb 100644 --- a/common_modules/module_manager/inc/txm_module_manager_dispatch.h +++ b/common_modules/module_manager/inc/txm_module_manager_dispatch.h @@ -1,11 +1,11 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation * Copyright (c) 2025 Eclipse ThreadX Contributors - * + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -2393,7 +2393,7 @@ ALIGN_TYPE return_value; if (param_1 < module_instance -> txm_module_instance_maximum_priority) { return(TX_THRESH_ERROR); - } + } if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) { @@ -2427,7 +2427,7 @@ ALIGN_TYPE return_value; if (param_1 < module_instance -> txm_module_instance_maximum_priority) { return(TX_PRIORITY_ERROR); - } + } if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) { diff --git a/common_modules/module_manager/inc/txm_module_manager_util.h b/common_modules/module_manager/inc/txm_module_manager_util.h index 2dc49f77..45c7f409 100644 --- a/common_modules/module_manager/inc/txm_module_manager_util.h +++ b/common_modules/module_manager/inc/txm_module_manager_util.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,22 +36,6 @@ /* This file declares prototypes of utility functions used by the */ /* module manager. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 04-02-2021 Scott Larson Modified comment(s) and */ -/* optimized object checks, */ -/* resulting in version 6.1.6 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s) and */ -/* improved object check, */ -/* resulting in version 6.3.0 */ -/* xx-xx-2025 William E. Lamie Modified comment(s) and */ -/* improved object pointer use */ -/* and creation checking, */ -/* resulting in version 6.4.3 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_MANAGER_UTIL_H diff --git a/common_modules/module_manager/src/txm_module_manager_absolute_load.c b/common_modules/module_manager/src/txm_module_manager_absolute_load.c index d8a771f8..dee6efd2 100644 --- a/common_modules/module_manager/src/txm_module_manager_absolute_load.c +++ b/common_modules/module_manager/src/txm_module_manager_absolute_load.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,12 +67,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_absolute_load(TXM_MODULE_INSTANCE *module_instance, CHAR *module_name, VOID *module_location) { diff --git a/common_modules/module_manager/src/txm_module_manager_application_request.c b/common_modules/module_manager/src/txm_module_manager_application_request.c index 4682968a..111dbbdc 100644 --- a/common_modules/module_manager/src/txm_module_manager_application_request.c +++ b/common_modules/module_manager/src/txm_module_manager_application_request.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,15 +62,6 @@ /* */ /* _txm_module_manager_kernel_dispatch Kernel dispatch function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_application_request(ULONG request_id, ALIGN_TYPE param_1, ALIGN_TYPE param_2, ALIGN_TYPE param_3) { diff --git a/common_modules/module_manager/src/txm_module_manager_callback_request.c b/common_modules/module_manager/src/txm_module_manager_callback_request.c index 4d5211d6..bae5c00b 100644 --- a/common_modules/module_manager/src/txm_module_manager_callback_request.c +++ b/common_modules/module_manager/src/txm_module_manager_callback_request.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,12 +60,6 @@ /* */ /* ThreadX */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_callback_request(TX_QUEUE *module_callback_queue, TXM_MODULE_CALLBACK_MESSAGE *callback_message) { diff --git a/common_modules/module_manager/src/txm_module_manager_event_flags_notify_trampoline.c b/common_modules/module_manager/src/txm_module_manager_event_flags_notify_trampoline.c index 44dd1872..7510f36b 100644 --- a/common_modules/module_manager/src/txm_module_manager_event_flags_notify_trampoline.c +++ b/common_modules/module_manager/src/txm_module_manager_event_flags_notify_trampoline.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* ThreadX */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_event_flags_notify_trampoline(TX_EVENT_FLAGS_GROUP *group_ptr) { diff --git a/common_modules/module_manager/src/txm_module_manager_file_load.c b/common_modules/module_manager/src/txm_module_manager_file_load.c index 55ac57a2..c444c5c1 100644 --- a/common_modules/module_manager/src/txm_module_manager_file_load.c +++ b/common_modules/module_manager/src/txm_module_manager_file_load.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -75,12 +76,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_file_load(TXM_MODULE_INSTANCE *module_instance, CHAR *module_name, FX_MEDIA *media_ptr, CHAR *file_name) { diff --git a/common_modules/module_manager/src/txm_module_manager_in_place_load.c b/common_modules/module_manager/src/txm_module_manager_in_place_load.c index acc5828c..781ef628 100644 --- a/common_modules/module_manager/src/txm_module_manager_in_place_load.c +++ b/common_modules/module_manager/src/txm_module_manager_in_place_load.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,12 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_in_place_load(TXM_MODULE_INSTANCE *module_instance, CHAR *module_name, VOID *module_location) { diff --git a/common_modules/module_manager/src/txm_module_manager_initialize.c b/common_modules/module_manager/src/txm_module_manager_initialize.c index fba853f5..7626c19b 100644 --- a/common_modules/module_manager/src/txm_module_manager_initialize.c +++ b/common_modules/module_manager/src/txm_module_manager_initialize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -129,12 +130,6 @@ ULONG _txm_module_manager_callback_error_count; /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_initialize(VOID *module_memory_start, ULONG module_memory_size) { diff --git a/common_modules/module_manager/src/txm_module_manager_internal_load.c b/common_modules/module_manager/src/txm_module_manager_internal_load.c index 46416127..49d57354 100644 --- a/common_modules/module_manager/src/txm_module_manager_internal_load.c +++ b/common_modules/module_manager/src/txm_module_manager_internal_load.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,12 +69,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_internal_load(TXM_MODULE_INSTANCE *module_instance, CHAR *module_name, VOID *module_location, ULONG code_size, VOID *code_allocation_ptr, ULONG code_allocation_size) diff --git a/common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c b/common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c index 769ebcc5..aa377430 100644 --- a/common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c +++ b/common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -76,22 +77,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 12-31-2020 Scott Larson Modified comment(s), added */ -/* port-specific dispatch, */ -/* resulting in version 6.1.3 */ -/* 04-02-2021 Scott Larson Modified comment(s), */ -/* added optional defines to */ -/* remove unneeded functions, */ -/* resulting in version 6.1.6 */ -/* 01-31-2022 Scott Larson Modified comments and added */ -/* CALL_NOT_USED option, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ ALIGN_TYPE _txm_module_manager_kernel_dispatch(ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) { @@ -439,7 +424,7 @@ TXM_MODULE_INSTANCE *module_instance; break; } #endif - + #ifndef TXM_QUEUE_SEND_CALL_NOT_USED case TXM_QUEUE_SEND_CALL: { diff --git a/common_modules/module_manager/src/txm_module_manager_maximum_module_priority_set.c b/common_modules/module_manager/src/txm_module_manager_maximum_module_priority_set.c index a3b31c8e..35560eea 100644 --- a/common_modules/module_manager/src/txm_module_manager_maximum_module_priority_set.c +++ b/common_modules/module_manager/src/txm_module_manager_maximum_module_priority_set.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,12 +59,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_maximum_module_priority_set(TXM_MODULE_INSTANCE *module_instance, UINT priority) { diff --git a/common_modules/module_manager/src/txm_module_manager_memory_load.c b/common_modules/module_manager/src/txm_module_manager_memory_load.c index 88679544..e615e4f2 100644 --- a/common_modules/module_manager/src/txm_module_manager_memory_load.c +++ b/common_modules/module_manager/src/txm_module_manager_memory_load.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,12 +67,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_load(TXM_MODULE_INSTANCE *module_instance, CHAR *module_name, VOID *module_location) { diff --git a/common_modules/module_manager/src/txm_module_manager_object_allocate.c b/common_modules/module_manager/src/txm_module_manager_object_allocate.c index 49a6485e..92ae128c 100644 --- a/common_modules/module_manager/src/txm_module_manager_object_allocate.c +++ b/common_modules/module_manager/src/txm_module_manager_object_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_object_allocate(VOID **object_ptr_ptr, ULONG object_size, TXM_MODULE_INSTANCE *module_instance) { diff --git a/common_modules/module_manager/src/txm_module_manager_object_deallocate.c b/common_modules/module_manager/src/txm_module_manager_object_deallocate.c index b5deeb6b..2efc465b 100644 --- a/common_modules/module_manager/src/txm_module_manager_object_deallocate.c +++ b/common_modules/module_manager/src/txm_module_manager_object_deallocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,12 +59,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_object_deallocate(VOID *object_ptr) { diff --git a/common_modules/module_manager/src/txm_module_manager_object_pointer_get.c b/common_modules/module_manager/src/txm_module_manager_object_pointer_get.c index 198e8c70..84cf6c96 100644 --- a/common_modules/module_manager/src/txm_module_manager_object_pointer_get.c +++ b/common_modules/module_manager/src/txm_module_manager_object_pointer_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_object_pointer_get(UINT object_type, CHAR *name, VOID **object_ptr) { diff --git a/common_modules/module_manager/src/txm_module_manager_object_pointer_get_extended.c b/common_modules/module_manager/src/txm_module_manager_object_pointer_get_extended.c index 017ed364..1ddd987b 100644 --- a/common_modules/module_manager/src/txm_module_manager_object_pointer_get_extended.c +++ b/common_modules/module_manager/src/txm_module_manager_object_pointer_get_extended.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -88,12 +89,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_object_pointer_get_extended(UINT object_type, CHAR *search_name, UINT search_name_length, VOID **object_ptr) { diff --git a/common_modules/module_manager/src/txm_module_manager_object_pool_create.c b/common_modules/module_manager/src/txm_module_manager_object_pool_create.c index b9038a81..ad05aa95 100644 --- a/common_modules/module_manager/src/txm_module_manager_object_pool_create.c +++ b/common_modules/module_manager/src/txm_module_manager_object_pool_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,12 +60,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_object_pool_create(VOID *object_memory, ULONG object_memory_size) { diff --git a/common_modules/module_manager/src/txm_module_manager_properties_get.c b/common_modules/module_manager/src/txm_module_manager_properties_get.c index bab824fc..3705583f 100644 --- a/common_modules/module_manager/src/txm_module_manager_properties_get.c +++ b/common_modules/module_manager/src/txm_module_manager_properties_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_properties_get(TXM_MODULE_INSTANCE *module_instance, ULONG *module_properties_ptr) { diff --git a/common_modules/module_manager/src/txm_module_manager_queue_notify_trampoline.c b/common_modules/module_manager/src/txm_module_manager_queue_notify_trampoline.c index 94cb62e8..a6ffa56c 100644 --- a/common_modules/module_manager/src/txm_module_manager_queue_notify_trampoline.c +++ b/common_modules/module_manager/src/txm_module_manager_queue_notify_trampoline.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,12 +58,6 @@ /* */ /* ThreadX */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_queue_notify_trampoline(TX_QUEUE *queue_ptr) { diff --git a/common_modules/module_manager/src/txm_module_manager_semaphore_notify_trampoline.c b/common_modules/module_manager/src/txm_module_manager_semaphore_notify_trampoline.c index f070c26d..f1545cf6 100644 --- a/common_modules/module_manager/src/txm_module_manager_semaphore_notify_trampoline.c +++ b/common_modules/module_manager/src/txm_module_manager_semaphore_notify_trampoline.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,12 +59,6 @@ /* */ /* ThreadX */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_semaphore_notify_trampoline(TX_SEMAPHORE *semaphore_ptr) { diff --git a/common_modules/module_manager/src/txm_module_manager_start.c b/common_modules/module_manager/src/txm_module_manager_start.c index 4e2383bf..afad039f 100644 --- a/common_modules/module_manager/src/txm_module_manager_start.c +++ b/common_modules/module_manager/src/txm_module_manager_start.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 12-31-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.3 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_start(TXM_MODULE_INSTANCE *module_instance) { diff --git a/common_modules/module_manager/src/txm_module_manager_stop.c b/common_modules/module_manager/src/txm_module_manager_stop.c index c960dae1..69ab949b 100644 --- a/common_modules/module_manager/src/txm_module_manager_stop.c +++ b/common_modules/module_manager/src/txm_module_manager_stop.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -107,17 +108,6 @@ extern UINT _txm_module_manager_usbx_stop(TXM_MODULE_INSTANCE *module_instance) /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-02-2021 Scott Larson Modified comments, fix */ -/* object delete underflow, */ -/* resulting in version 6.1.5 */ -/* 03-08-2023 Scott Larson Added tx_trace.h include, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_stop(TXM_MODULE_INSTANCE *module_instance) { diff --git a/common_modules/module_manager/src/txm_module_manager_thread_create.c b/common_modules/module_manager/src/txm_module_manager_thread_create.c index d759a064..c14d8e4e 100644 --- a/common_modules/module_manager/src/txm_module_manager_thread_create.c +++ b/common_modules/module_manager/src/txm_module_manager_thread_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -80,26 +81,6 @@ /* _txm_module_manager_stop Initiate module's stop thread */ /* _txm_module_manager_kernel_dispatch Kernel dispatch function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 12-31-2020 Scott Larson Modified comment(s), */ -/* fix stack overlap checking, */ -/* added 64-bit support, */ -/* added SMP support, */ -/* resulting in version 6.1.3 */ -/* 03-08-2023 Scott Larson Check module stack for */ -/* overlap, */ -/* resulting in version 6.2.1 */ -/* 10-31-2023 Xiuwen Cai, Yajun xia Modified comment(s), */ -/* added option for random */ -/* number stack filling, */ -/* fixed the kernel stack */ -/* allocation issue, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr, VOID (*shell_function)(TX_THREAD *, TXM_MODULE_INSTANCE *), diff --git a/common_modules/module_manager/src/txm_module_manager_thread_notify_trampoline.c b/common_modules/module_manager/src/txm_module_manager_thread_notify_trampoline.c index 01ff1260..b7f2d552 100644 --- a/common_modules/module_manager/src/txm_module_manager_thread_notify_trampoline.c +++ b/common_modules/module_manager/src/txm_module_manager_thread_notify_trampoline.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,12 +60,6 @@ /* */ /* ThreadX */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_thread_notify_trampoline(TX_THREAD *thread_ptr, UINT type) { diff --git a/common_modules/module_manager/src/txm_module_manager_thread_reset.c b/common_modules/module_manager/src/txm_module_manager_thread_reset.c index 176f78e0..75dd4a49 100644 --- a/common_modules/module_manager/src/txm_module_manager_thread_reset.c +++ b/common_modules/module_manager/src/txm_module_manager_thread_reset.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* _txm_module_manager_kernel_dispatch Kernel dispatch function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_thread_reset(TX_THREAD *thread_ptr) { diff --git a/common_modules/module_manager/src/txm_module_manager_timer_notify_trampoline.c b/common_modules/module_manager/src/txm_module_manager_timer_notify_trampoline.c index 0d462d1e..b2df699b 100644 --- a/common_modules/module_manager/src/txm_module_manager_timer_notify_trampoline.c +++ b/common_modules/module_manager/src/txm_module_manager_timer_notify_trampoline.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,12 +59,6 @@ /* */ /* ThreadX */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_timer_notify_trampoline(ULONG id) { diff --git a/common_modules/module_manager/src/txm_module_manager_unload.c b/common_modules/module_manager/src/txm_module_manager_unload.c index 3f8b923a..5fe96f6f 100644 --- a/common_modules/module_manager/src/txm_module_manager_unload.c +++ b/common_modules/module_manager/src/txm_module_manager_unload.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_unload(TXM_MODULE_INSTANCE *module_instance) { diff --git a/common_modules/module_manager/src/txm_module_manager_util.c b/common_modules/module_manager/src/txm_module_manager_util.c index 0e5abe5e..78031b5f 100644 --- a/common_modules/module_manager/src/txm_module_manager_util.c +++ b/common_modules/module_manager/src/txm_module_manager_util.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* _txm_module_manager_kernel_dispatch Kernel dispatch function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_object_memory_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE object_ptr, ULONG object_size) { @@ -137,10 +132,10 @@ UINT _txm_module_manager_object_memory_check(TXM_MODULE_INSTANCE *module_instan /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* xx-xx-2025 William E. Lamie Modified comment(s), and */ -/* removed module local memory */ -/* check, resulting in */ -/* version 6.1x */ +/* xx-xx-2025 William E. Lamie Modified comment(s), and */ +/* removed module local memory */ +/* check, resulting in */ +/* version 6.1x */ /* */ /**************************************************************************/ UCHAR _txm_module_manager_created_object_check(TXM_MODULE_INSTANCE *module_instance, VOID *object_ptr) @@ -346,8 +341,8 @@ CHAR object_name_char; /* */ /* DESCRIPTION */ /* */ -/* This function checks to make sure the object pointer for one of the */ -/* creation APIs is valid. */ +/* This function checks to make sure the object pointer for one of the */ +/* creation APIs is valid. */ /* */ /* INPUT */ /* */ @@ -357,8 +352,8 @@ CHAR object_name_char; /* */ /* OUTPUT */ /* */ -/* TX_TRUE Valid object pointer */ -/* TX_FALSE Invalid object pointer */ +/* TX_TRUE Valid object pointer */ +/* TX_FALSE Invalid object pointer */ /* */ /* CALLS */ /* */ @@ -385,7 +380,7 @@ UINT _txm_module_manager_param_check_object_for_creation(TXM_MODULE_INSTANCE /* Object pointer is NULL, which is invalid. */ return(TX_FALSE); } - + /* Determine if the object pointer is inside the module object pool. */ if (TXM_MODULE_MANAGER_ENSURE_INSIDE_OBJ_POOL(module_instance, object_ptr, object_size) == TX_FALSE) { @@ -409,7 +404,7 @@ UINT _txm_module_manager_param_check_object_for_creation(TXM_MODULE_INSTANCE /* Object has already been created, which is invalid. */ return(TX_FALSE); } - + /* Everything is okay with the object, return TX_TRUE. */ return(TX_TRUE); } @@ -427,7 +422,7 @@ UINT _txm_module_manager_param_check_object_for_creation(TXM_MODULE_INSTANCE /* */ /* DESCRIPTION */ /* */ -/* This function checks to make sure the object pointer is valid. */ +/* This function checks to make sure the object pointer is valid. */ /* */ /* INPUT */ /* */ @@ -437,8 +432,8 @@ UINT _txm_module_manager_param_check_object_for_creation(TXM_MODULE_INSTANCE /* */ /* OUTPUT */ /* */ -/* TX_TRUE Valid object pointer */ -/* TX_FALSE Invalid object pointer */ +/* TX_TRUE Valid object pointer */ +/* TX_FALSE Invalid object pointer */ /* */ /* CALLS */ /* */ @@ -476,11 +471,11 @@ UINT _txm_module_manager_param_check_object_for_use(TXM_MODULE_INSTANCE *modu /* Define application-specific object memory check. */ #ifdef TXM_MODULE_MANGER_APPLICATION_VALID_OBJECT_MEMORY_CHECK - + /* Bring in the application-spefic objeft memory check, defined by the user. */ TXM_MODULE_MANGER_APPLICATION_VALID_OBJECT_MEMORY_CHECK #endif /* TXM_MODULE_MANGER_APPLICATION_VALID_OBJECT_MEMORY_ENABLE */ - + /* Everything is okay with the object, return TX_TRUE. */ return(TX_TRUE); } diff --git a/common_modules/module_manager/utilities/module_binary_to_c_array.c b/common_modules/module_manager/utilities/module_binary_to_c_array.c index b02fde6e..da0cf97c 100644 --- a/common_modules/module_manager/utilities/module_binary_to_c_array.c +++ b/common_modules/module_manager/utilities/module_binary_to_c_array.c @@ -21,7 +21,7 @@ unsigned long column; /* Determine if the proper number of files are provided. */ - if (argc != 3) + if (argc != 3) { /* Print an error message out and wait for user key hit. */ @@ -44,7 +44,7 @@ unsigned long column; printf(" File: %s ", argv[1]); return(2); } - + /* Determine if the binary file is a valid ThreadX module. */ alpha = fgetc(source_file); alpha1 = fgetc(source_file); @@ -94,7 +94,7 @@ unsigned long column; address = 0; column = 0; - do + do { /* Get character from the input file. */ diff --git a/common_modules/module_manager/utilities/module_to_binary.c b/common_modules/module_manager/utilities/module_to_binary.c index 77517e0d..a749c8a3 100644 --- a/common_modules/module_manager/utilities/module_to_binary.c +++ b/common_modules/module_manager/utilities/module_to_binary.c @@ -14,7 +14,7 @@ FILE *binary_file; #define ELF_EXECUTABLE 2 -typedef struct ELF_HEADER_STRUCT +typedef struct ELF_HEADER_STRUCT { unsigned char elf_header_id_string[ELF_ID_STRING_SIZE]; unsigned short elf_header_file_type; @@ -114,12 +114,12 @@ unsigned char *buffer; for (i = 0; i < object_size; i++) { alpha = fgetc(source_file); - + if (alpha == EOF) return(1); - + buffer[i] = (unsigned char) alpha; - } + } /* Return success. */ return(0); @@ -140,7 +140,7 @@ unsigned char zero_value; /* Determine if the proper number of files are provided. */ - if (argc != 3) + if (argc != 3) { /* Print an error message out and wait for user key hit. */ @@ -163,7 +163,7 @@ unsigned char zero_value; printf(" File: %s ", argv[1]); return(2); } - + /* Attempt to open the binary file for writing. */ binary_file = fopen(argv[2], "wb"); @@ -182,7 +182,7 @@ unsigned char zero_value; /* Allocate memory for the program header(s). */ program_header = malloc(sizeof(ELF_PROGRAM_HEADER)*header.elf_header_program_header_entries); - + /* Read the program header(s). */ elf_object_read(header.elf_header_program_header_offset, program_header, (sizeof(ELF_PROGRAM_HEADER)*header.elf_header_program_header_entries)); @@ -194,7 +194,7 @@ unsigned char zero_value; /* Alocate memory for the section string table. */ - section_string_table = malloc(section_header[header.elf_header_section_string_index].elf_section_header_size); + section_string_table = malloc(section_header[header.elf_header_section_string_index].elf_section_header_size); /* Read the section string table. */ elf_object_read(section_header[header.elf_header_section_string_index].elf_section_header_offset, section_string_table, section_header[header.elf_header_section_string_index].elf_section_header_size); @@ -315,7 +315,7 @@ unsigned char zero_value; /* Move address forward. */ address++; - + /* Decrement size. */ size--; diff --git a/common_modules/module_manager/utilities/module_to_c_array.c b/common_modules/module_manager/utilities/module_to_c_array.c index fc72092c..37d931f3 100644 --- a/common_modules/module_manager/utilities/module_to_c_array.c +++ b/common_modules/module_manager/utilities/module_to_c_array.c @@ -14,7 +14,7 @@ FILE *array_file; #define ELF_EXECUTABLE 2 -typedef struct ELF_HEADER_STRUCT +typedef struct ELF_HEADER_STRUCT { unsigned char elf_header_id_string[ELF_ID_STRING_SIZE]; unsigned short elf_header_file_type; @@ -114,12 +114,12 @@ unsigned char *buffer; for (i = 0; i < object_size; i++) { alpha = fgetc(source_file); - + if (alpha == EOF) return(1); - + buffer[i] = (unsigned char) alpha; - } + } /* Return success. */ return(0); @@ -140,7 +140,7 @@ CODE_SECTION_ENTRY code_section_temp; /* Determine if the proper number of files are provided. */ - if (argc != 3) + if (argc != 3) { /* Print an error message out and wait for user key hit. */ @@ -163,7 +163,7 @@ CODE_SECTION_ENTRY code_section_temp; printf(" File: %s ", argv[1]); return(2); } - + /* Attempt to open the dump file for writing. */ array_file = fopen(argv[2], "w"); @@ -192,7 +192,7 @@ CODE_SECTION_ENTRY code_section_temp; /* Allocate memory for the program header(s). */ program_header = malloc(sizeof(ELF_PROGRAM_HEADER)*header.elf_header_program_header_entries); - + /* Read the program header(s). */ elf_object_read(header.elf_header_program_header_offset, program_header, (sizeof(ELF_PROGRAM_HEADER)*header.elf_header_program_header_entries)); @@ -204,7 +204,7 @@ CODE_SECTION_ENTRY code_section_temp; /* Alocate memory for the section string table. */ - section_string_table = malloc(section_header[header.elf_header_section_string_index].elf_section_header_size); + section_string_table = malloc(section_header[header.elf_header_section_string_index].elf_section_header_size); /* Read the section string table. */ elf_object_read(section_header[header.elf_header_section_string_index].elf_section_header_offset, section_string_table, section_header[header.elf_header_section_string_index].elf_section_header_size); @@ -260,7 +260,7 @@ CODE_SECTION_ENTRY code_section_temp; printf("**** Error: No code sections found! **** \n"); fprintf(array_file, "unsigned char module_code[] = {0x00};\n\n"); - + /* Close files. */ fclose(source_file); fclose(array_file); @@ -337,7 +337,7 @@ CODE_SECTION_ENTRY code_section_temp; /* Write out the contents of this program area. */ size = code_section_array[i].code_section_size; - + j = 0; k = 0; while (size) @@ -372,7 +372,7 @@ CODE_SECTION_ENTRY code_section_temp; /* Move address forward. */ address++; - + /* Decrement size. */ size--; diff --git a/common_smp/inc/tx_api.h b/common_smp/inc/tx_api.h index cc378f16..7d0ccbe5 100644 --- a/common_smp/inc/tx_api.h +++ b/common_smp/inc/tx_api.h @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -38,66 +39,6 @@ /* Please note that basic data type definitions and other architecture-*/ /* specific information is contained in the file tx_port.h. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-16-2020 William E. Lamie Modified comment(s), and */ -/* increased patch version, */ -/* resulting in version 6.1.1 */ -/* 12-31-2020 William E. Lamie Modified comment(s), and */ -/* increased patch version, */ -/* resulting in version 6.1.3 */ -/* 03-02-2021 Scott Larson Modified comment(s), and */ -/* order defines numerically, */ -/* add option to remove FileX */ -/* pointer, fix whitespace, */ -/* resulting in version 6.1.5 */ -/* 04-02-2021 Scott Larson Modified comment(s), and */ -/* update patch number, */ -/* resulting in version 6.1.6 */ -/* 06-02-2021 Scott Larson Added options for multiple */ -/* block pool search & delay, */ -/* resulting in version 6.1.7 */ -/* 08-02-2021 Scott Larson Modified comment(s), and */ -/* update patch number, */ -/* resulting in version 6.1.8 */ -/* 10-15-2021 Yuxin Zhou Modified comment(s), */ -/* update patch number, */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), */ -/* add unused parameter macro, */ -/* update patch number, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Wenhui Xie Modified comment(s), */ -/* optimized the definition of */ -/* TX_TIMER_TICKS_PER_SECOND, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comment(s), */ -/* update patch number, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Modified comment(s), */ -/* add extension macros, */ -/* update version numbers, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Tiejun Zhou Modified comment(s), */ -/* update patch number, */ -/* resulting in version 6.2.1 */ -/* 10-31-2023 Xiuwen Cai Modified comment(s), */ -/* added option for random */ -/* number stack filling, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Tiejun Zhou Modified comment(s), */ -/* update version number, */ -/* resulting in version 6.4.0 */ -/* 03-01-2024 Tiejun Zhou Modified comment(s), */ -/* update version number, */ -/* resulting in version 6.4.1 */ -/* 02-19-2025 Frédéric Desbiens Modified comment(s), */ -/* update version number, */ -/* resulting in version 6.4.2 */ -/* */ /**************************************************************************/ #ifndef TX_API_H @@ -149,9 +90,9 @@ extern "C" { #define AZURE_RTOS_THREADX #define THREADX_MAJOR_VERSION 6 -#define THREADX_MINOR_VERSION 4 -#define THREADX_PATCH_VERSION 5 -#define THREADX_BUILD_VERSION 202504 +#define THREADX_MINOR_VERSION 5 +#define THREADX_PATCH_VERSION 0 +#define THREADX_BUILD_VERSION 202601 #define THREADX_HOTFIX_VERSION ' ' diff --git a/common_smp/inc/tx_block_pool.h b/common_smp/inc/tx_block_pool.h index 2a8bb51e..89c9dfbe 100644 --- a/common_smp/inc/tx_block_pool.h +++ b/common_smp/inc/tx_block_pool.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,14 +37,6 @@ /* including all data types and external references. It is assumed */ /* that tx_api.h and tx_port.h have already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_BLOCK_POOL_H diff --git a/common_smp/inc/tx_byte_pool.h b/common_smp/inc/tx_byte_pool.h index 8f1050fa..b9f34311 100644 --- a/common_smp/inc/tx_byte_pool.h +++ b/common_smp/inc/tx_byte_pool.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,14 +37,6 @@ /* including all data types and external references. It is assumed */ /* that tx_api.h and tx_port.h have already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_BYTE_POOL_H diff --git a/common_smp/inc/tx_event_flags.h b/common_smp/inc/tx_event_flags.h index 51e99536..6506dd13 100644 --- a/common_smp/inc/tx_event_flags.h +++ b/common_smp/inc/tx_event_flags.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,14 +37,6 @@ /* including all data types and external references. It is assumed */ /* that tx_api.h and tx_port.h have already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_EVENT_FLAGS_H diff --git a/common_smp/inc/tx_initialize.h b/common_smp/inc/tx_initialize.h index 28c7251b..fd944965 100644 --- a/common_smp/inc/tx_initialize.h +++ b/common_smp/inc/tx_initialize.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,14 +37,6 @@ /* data types and external references. It is assumed that tx_api.h */ /* and tx_port.h have already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_INITIALIZE_H diff --git a/common_smp/inc/tx_mutex.h b/common_smp/inc/tx_mutex.h index a3b52386..b0b46c2f 100644 --- a/common_smp/inc/tx_mutex.h +++ b/common_smp/inc/tx_mutex.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,14 +37,6 @@ /* including all data types and external references. It is assumed */ /* that tx_api.h and tx_port.h have already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_MUTEX_H diff --git a/common_smp/inc/tx_queue.h b/common_smp/inc/tx_queue.h index 7074a91e..c8b4122c 100644 --- a/common_smp/inc/tx_queue.h +++ b/common_smp/inc/tx_queue.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,14 +37,6 @@ /* including all data types and external references. It is assumed */ /* that tx_api.h and tx_port.h have already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_QUEUE_H diff --git a/common_smp/inc/tx_semaphore.h b/common_smp/inc/tx_semaphore.h index 6784e58f..baf292bd 100644 --- a/common_smp/inc/tx_semaphore.h +++ b/common_smp/inc/tx_semaphore.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,14 +37,6 @@ /* including all data types and external references. It is assumed */ /* that tx_api.h and tx_port.h have already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_SEMAPHORE_H diff --git a/common_smp/inc/tx_thread.h b/common_smp/inc/tx_thread.h index 8bd68438..7dc7801b 100644 --- a/common_smp/inc/tx_thread.h +++ b/common_smp/inc/tx_thread.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,14 +37,6 @@ /* data types and external references. It is assumed that tx_api.h */ /* and tx_port.h have already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Fixed MISRA2012 rule 8.3, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #ifndef TX_THREAD_H diff --git a/common_smp/inc/tx_timer.h b/common_smp/inc/tx_timer.h index d8277082..71a65b27 100644 --- a/common_smp/inc/tx_timer.h +++ b/common_smp/inc/tx_timer.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,12 +37,6 @@ /* data types and external references. It is assumed that tx_api.h */ /* and tx_port.h have already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_TIMER_H diff --git a/common_smp/inc/tx_trace.h b/common_smp/inc/tx_trace.h index 07da204b..ea0e59e5 100644 --- a/common_smp/inc/tx_trace.h +++ b/common_smp/inc/tx_trace.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,14 +36,6 @@ /* and structure definitions as well as external references. It is */ /* assumed that tx_api.h and tx_port.h have already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ diff --git a/common_smp/inc/tx_user_sample.h b/common_smp/inc/tx_user_sample.h index e7ecb56a..64ff9aed 100644 --- a/common_smp/inc/tx_user_sample.h +++ b/common_smp/inc/tx_user_sample.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -39,33 +40,6 @@ /* Note that all the defines in this file may also be made on the */ /* command line when building ThreadX library and application objects. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* 03-02-2021 Scott Larson Modified comment(s), */ -/* added option to remove */ -/* FileX pointer, */ -/* resulting in version 6.1.5 */ -/* 06-02-2021 Scott Larson Added options for multiple */ -/* block pool search & delay, */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 Yuxin Zhou Modified comment(s), added */ -/* user-configurable symbol */ -/* TX_TIMER_TICKS_PER_SECOND */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Wenhui Xie Modified comment(s), */ -/* optimized the definition of */ -/* TX_TIMER_TICKS_PER_SECOND, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Xiuwen Cai Modified comment(s), */ -/* added option for random */ -/* number stack filling, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #ifndef TX_USER_H @@ -175,7 +149,7 @@ /* Determine if random number is used for stack filling. By default, ThreadX uses a fixed pattern for stack filling. When the following is defined, ThreadX uses a random number - for stack filling. This is effective only when TX_ENABLE_STACK_CHECKING is defined. */ + for stack filling. This is effective only when TX_ENABLE_STACK_CHECKING is defined. */ /* #define TX_ENABLE_RANDOM_NUMBER_STACK_FILLING diff --git a/common_smp/src/tx_block_allocate.c b/common_smp/src/tx_block_allocate.c index b2c7bef5..78619603 100644 --- a/common_smp/src/tx_block_allocate.c +++ b/common_smp/src/tx_block_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,14 +68,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_block_allocate(TX_BLOCK_POOL *pool_ptr, VOID **block_ptr, ULONG wait_option) { diff --git a/common_smp/src/tx_block_pool_cleanup.c b/common_smp/src/tx_block_pool_cleanup.c index 9bae546d..7bcfecd8 100644 --- a/common_smp/src/tx_block_pool_cleanup.c +++ b/common_smp/src/tx_block_pool_cleanup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* _tx_thread_terminate Thread terminate processing */ /* _tx_thread_wait_abort Thread wait abort processing */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_block_pool_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) { diff --git a/common_smp/src/tx_block_pool_create.c b/common_smp/src/tx_block_pool_create.c index 54612019..1d2c803c 100644 --- a/common_smp/src/tx_block_pool_create.c +++ b/common_smp/src/tx_block_pool_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_block_pool_create(TX_BLOCK_POOL *pool_ptr, CHAR *name_ptr, ULONG block_size, VOID *pool_start, ULONG pool_size) diff --git a/common_smp/src/tx_block_pool_delete.c b/common_smp/src/tx_block_pool_delete.c index da27ef57..19ecb055 100644 --- a/common_smp/src/tx_block_pool_delete.c +++ b/common_smp/src/tx_block_pool_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_block_pool_delete(TX_BLOCK_POOL *pool_ptr) { diff --git a/common_smp/src/tx_block_pool_info_get.c b/common_smp/src/tx_block_pool_info_get.c index aebd0db6..5998f1db 100644 --- a/common_smp/src/tx_block_pool_info_get.c +++ b/common_smp/src/tx_block_pool_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,14 +68,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_block_pool_info_get(TX_BLOCK_POOL *pool_ptr, CHAR **name, ULONG *available_blocks, ULONG *total_blocks, TX_THREAD **first_suspended, diff --git a/common_smp/src/tx_block_pool_initialize.c b/common_smp/src/tx_block_pool_initialize.c index 21132159..e01eba32 100644 --- a/common_smp/src/tx_block_pool_initialize.c +++ b/common_smp/src/tx_block_pool_initialize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -97,17 +98,6 @@ ULONG _tx_block_pool_performance_timeout_count; /* */ /* _tx_initialize_high_level High level initialization */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* opt out of function when */ -/* TX_INLINE_INITIALIZATION is */ -/* defined, */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_block_pool_initialize(VOID) { diff --git a/common_smp/src/tx_block_pool_performance_info_get.c b/common_smp/src/tx_block_pool_performance_info_get.c index 84f68026..aecf7851 100644 --- a/common_smp/src/tx_block_pool_performance_info_get.c +++ b/common_smp/src/tx_block_pool_performance_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,14 +71,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_block_pool_performance_info_get(TX_BLOCK_POOL *pool_ptr, ULONG *allocates, ULONG *releases, ULONG *suspensions, ULONG *timeouts) diff --git a/common_smp/src/tx_block_pool_performance_system_info_get.c b/common_smp/src/tx_block_pool_performance_system_info_get.c index 0707295d..86627dd0 100644 --- a/common_smp/src/tx_block_pool_performance_system_info_get.c +++ b/common_smp/src/tx_block_pool_performance_system_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,14 +68,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_block_pool_performance_system_info_get(ULONG *allocates, ULONG *releases, ULONG *suspensions, ULONG *timeouts) { diff --git a/common_smp/src/tx_block_pool_prioritize.c b/common_smp/src/tx_block_pool_prioritize.c index c4ee4e94..89c2d634 100644 --- a/common_smp/src/tx_block_pool_prioritize.c +++ b/common_smp/src/tx_block_pool_prioritize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_block_pool_prioritize(TX_BLOCK_POOL *pool_ptr) { diff --git a/common_smp/src/tx_block_release.c b/common_smp/src/tx_block_release.c index 3b94c1bb..4a11fe08 100644 --- a/common_smp/src/tx_block_release.c +++ b/common_smp/src/tx_block_release.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_block_release(VOID *block_ptr) { diff --git a/common_smp/src/tx_byte_allocate.c b/common_smp/src/tx_byte_allocate.c index 69e837e3..2e1a2e5e 100644 --- a/common_smp/src/tx_byte_allocate.c +++ b/common_smp/src/tx_byte_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -69,14 +70,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_byte_allocate(TX_BYTE_POOL *pool_ptr, VOID **memory_ptr, ULONG memory_size, ULONG wait_option) { diff --git a/common_smp/src/tx_byte_pool_cleanup.c b/common_smp/src/tx_byte_pool_cleanup.c index a1260c5b..3a7acd54 100644 --- a/common_smp/src/tx_byte_pool_cleanup.c +++ b/common_smp/src/tx_byte_pool_cleanup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* _tx_thread_terminate Thread terminate processing */ /* _tx_thread_wait_abort Thread wait abort processing */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_byte_pool_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) { diff --git a/common_smp/src/tx_byte_pool_create.c b/common_smp/src/tx_byte_pool_create.c index 439eed7c..21abbe35 100644 --- a/common_smp/src/tx_byte_pool_create.c +++ b/common_smp/src/tx_byte_pool_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_byte_pool_create(TX_BYTE_POOL *pool_ptr, CHAR *name_ptr, VOID *pool_start, ULONG pool_size) { diff --git a/common_smp/src/tx_byte_pool_delete.c b/common_smp/src/tx_byte_pool_delete.c index fc3d9be1..3a24705f 100644 --- a/common_smp/src/tx_byte_pool_delete.c +++ b/common_smp/src/tx_byte_pool_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,14 +69,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_byte_pool_delete(TX_BYTE_POOL *pool_ptr) { diff --git a/common_smp/src/tx_byte_pool_info_get.c b/common_smp/src/tx_byte_pool_info_get.c index 339aa771..bd096440 100644 --- a/common_smp/src/tx_byte_pool_info_get.c +++ b/common_smp/src/tx_byte_pool_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,14 +68,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_byte_pool_info_get(TX_BYTE_POOL *pool_ptr, CHAR **name, ULONG *available_bytes, ULONG *fragments, TX_THREAD **first_suspended, diff --git a/common_smp/src/tx_byte_pool_initialize.c b/common_smp/src/tx_byte_pool_initialize.c index 65514536..652ec829 100644 --- a/common_smp/src/tx_byte_pool_initialize.c +++ b/common_smp/src/tx_byte_pool_initialize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -112,17 +113,6 @@ ULONG _tx_byte_pool_performance_timeout_count; /* */ /* _tx_initialize_high_level High level initialization */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* opt out of function when */ -/* TX_INLINE_INITIALIZATION is */ -/* defined, */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_byte_pool_initialize(VOID) { diff --git a/common_smp/src/tx_byte_pool_performance_info_get.c b/common_smp/src/tx_byte_pool_performance_info_get.c index 400804a2..6c2fd615 100644 --- a/common_smp/src/tx_byte_pool_performance_info_get.c +++ b/common_smp/src/tx_byte_pool_performance_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -78,14 +79,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_byte_pool_performance_info_get(TX_BYTE_POOL *pool_ptr, ULONG *allocates, ULONG *releases, ULONG *fragments_searched, ULONG *merges, ULONG *splits, ULONG *suspensions, ULONG *timeouts) diff --git a/common_smp/src/tx_byte_pool_performance_system_info_get.c b/common_smp/src/tx_byte_pool_performance_system_info_get.c index 266e2767..23f41c47 100644 --- a/common_smp/src/tx_byte_pool_performance_system_info_get.c +++ b/common_smp/src/tx_byte_pool_performance_system_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -75,14 +76,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_byte_pool_performance_system_info_get(ULONG *allocates, ULONG *releases, ULONG *fragments_searched, ULONG *merges, ULONG *splits, ULONG *suspensions, ULONG *timeouts) diff --git a/common_smp/src/tx_byte_pool_prioritize.c b/common_smp/src/tx_byte_pool_prioritize.c index 0076e503..dc2ecc03 100644 --- a/common_smp/src/tx_byte_pool_prioritize.c +++ b/common_smp/src/tx_byte_pool_prioritize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_byte_pool_prioritize(TX_BYTE_POOL *pool_ptr) { diff --git a/common_smp/src/tx_byte_pool_search.c b/common_smp/src/tx_byte_pool_search.c index 7f24ee69..712c9489 100644 --- a/common_smp/src/tx_byte_pool_search.c +++ b/common_smp/src/tx_byte_pool_search.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,18 +72,6 @@ /* _tx_byte_allocate Allocate bytes of memory */ /* _tx_byte_release Release bytes of memory */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 06-02-2021 Scott Larson Improve possible free bytes */ -/* calculation, and reduced */ -/* number of search resets, */ -/* resulting in version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Fixed MISRA2012 rule 10.4_a, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ UCHAR *_tx_byte_pool_search(TX_BYTE_POOL *pool_ptr, ULONG memory_size) { diff --git a/common_smp/src/tx_byte_release.c b/common_smp/src/tx_byte_release.c index 387320ba..b56665ed 100644 --- a/common_smp/src/tx_byte_release.c +++ b/common_smp/src/tx_byte_release.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_byte_release(VOID *memory_ptr) { diff --git a/common_smp/src/tx_event_flags_cleanup.c b/common_smp/src/tx_event_flags_cleanup.c index 3f870564..ac7bc68b 100644 --- a/common_smp/src/tx_event_flags_cleanup.c +++ b/common_smp/src/tx_event_flags_cleanup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* _tx_thread_terminate Thread terminate processing */ /* _tx_thread_wait_abort Thread wait abort processing */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_event_flags_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) { diff --git a/common_smp/src/tx_event_flags_create.c b/common_smp/src/tx_event_flags_create.c index 2195527a..2a9c042d 100644 --- a/common_smp/src/tx_event_flags_create.c +++ b/common_smp/src/tx_event_flags_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_event_flags_create(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR *name_ptr) { diff --git a/common_smp/src/tx_event_flags_delete.c b/common_smp/src/tx_event_flags_delete.c index 2b7c890a..777f2491 100644 --- a/common_smp/src/tx_event_flags_delete.c +++ b/common_smp/src/tx_event_flags_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_event_flags_delete(TX_EVENT_FLAGS_GROUP *group_ptr) { diff --git a/common_smp/src/tx_event_flags_get.c b/common_smp/src/tx_event_flags_get.c index 4e9abb80..3136d159 100644 --- a/common_smp/src/tx_event_flags_get.c +++ b/common_smp/src/tx_event_flags_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,20 +69,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* 04-25-2022 Scott Larson Modified comment(s), */ -/* handle 0 flags case, */ -/* resulting in version 6.1.11 */ -/* 10-31-2022 Scott Larson Modified comment(s), always */ -/* return actual flags, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ UINT _tx_event_flags_get(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG requested_flags, UINT get_option, ULONG *actual_flags_ptr, ULONG wait_option) diff --git a/common_smp/src/tx_event_flags_info_get.c b/common_smp/src/tx_event_flags_info_get.c index 9d409bc5..21e85c9a 100644 --- a/common_smp/src/tx_event_flags_info_get.c +++ b/common_smp/src/tx_event_flags_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -69,14 +70,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_event_flags_info_get(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR **name, ULONG *current_flags, TX_THREAD **first_suspended, ULONG *suspended_count, diff --git a/common_smp/src/tx_event_flags_initialize.c b/common_smp/src/tx_event_flags_initialize.c index f7b107c8..d5cd72b9 100644 --- a/common_smp/src/tx_event_flags_initialize.c +++ b/common_smp/src/tx_event_flags_initialize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -98,17 +99,6 @@ ULONG _tx_event_flags_performance_timeout_count; /* */ /* _tx_initialize_high_level High level initialization */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* opt out of function when */ -/* TX_INLINE_INITIALIZATION is */ -/* defined, */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_event_flags_initialize(VOID) { diff --git a/common_smp/src/tx_event_flags_performance_info_get.c b/common_smp/src/tx_event_flags_performance_info_get.c index c0529b03..213c2d2a 100644 --- a/common_smp/src/tx_event_flags_performance_info_get.c +++ b/common_smp/src/tx_event_flags_performance_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,14 +72,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_event_flags_performance_info_get(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG *sets, ULONG *gets, ULONG *suspensions, ULONG *timeouts) diff --git a/common_smp/src/tx_event_flags_performance_system_info_get.c b/common_smp/src/tx_event_flags_performance_system_info_get.c index 3f1570df..4902b0e1 100644 --- a/common_smp/src/tx_event_flags_performance_system_info_get.c +++ b/common_smp/src/tx_event_flags_performance_system_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,14 +69,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_event_flags_performance_system_info_get(ULONG *sets, ULONG *gets, ULONG *suspensions, ULONG *timeouts) { diff --git a/common_smp/src/tx_event_flags_set.c b/common_smp/src/tx_event_flags_set.c index 8309be14..749343c8 100644 --- a/common_smp/src/tx_event_flags_set.c +++ b/common_smp/src/tx_event_flags_set.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,18 +68,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* 04-25-2022 William E. Lamie Modified comment(s), and */ -/* added corrected preemption */ -/* check logic, resulting in */ -/* version 6.1.11 */ -/* */ /**************************************************************************/ UINT _tx_event_flags_set(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG flags_to_set, UINT set_option) { @@ -336,8 +325,8 @@ VOID (*events_set_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *notify_ /* Disable preemption while we process the suspended list. */ _tx_thread_preempt_disable++; - /* Since we have temporarily disabled preemption globally, set the preempt - check flag to check for any preemption condition - including from + /* Since we have temporarily disabled preemption globally, set the preempt + check flag to check for any preemption condition - including from unrelated ISR processing. */ preempt_check = TX_TRUE; diff --git a/common_smp/src/tx_event_flags_set_notify.c b/common_smp/src/tx_event_flags_set_notify.c index ab2b9a1c..4cafdd57 100644 --- a/common_smp/src/tx_event_flags_set_notify.c +++ b/common_smp/src/tx_event_flags_set_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_event_flags_set_notify(TX_EVENT_FLAGS_GROUP *group_ptr, VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)) { diff --git a/common_smp/src/tx_initialize_high_level.c b/common_smp/src/tx_initialize_high_level.c index b7224551..77bc3ed7 100644 --- a/common_smp/src/tx_initialize_high_level.c +++ b/common_smp/src/tx_initialize_high_level.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -100,14 +101,6 @@ VOID *_tx_initialize_unused_memory; /* is optionally called by */ /* compiler's startup code. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_initialize_high_level(VOID) { diff --git a/common_smp/src/tx_initialize_kernel_enter.c b/common_smp/src/tx_initialize_kernel_enter.c index 89c94dba..5fa71b8f 100644 --- a/common_smp/src/tx_initialize_kernel_enter.c +++ b/common_smp/src/tx_initialize_kernel_enter.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,16 +83,6 @@ TX_SAFETY_CRITICAL_EXCEPTION_HANDLER /* */ /* main Application main program */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Xiuwen Cai Modified comment(s), */ -/* added random generator */ -/* initialization, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ VOID _tx_initialize_kernel_enter(VOID) { diff --git a/common_smp/src/tx_initialize_kernel_setup.c b/common_smp/src/tx_initialize_kernel_setup.c index 2cc5e68e..1e750dbd 100644 --- a/common_smp/src/tx_initialize_kernel_setup.c +++ b/common_smp/src/tx_initialize_kernel_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,12 +67,6 @@ /* */ /* startup code Compiler startup code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_initialize_kernel_setup(VOID) { diff --git a/common_smp/src/tx_misra.c b/common_smp/src/tx_misra.c index 49b6cf65..f5dd5f53 100644 --- a/common_smp/src/tx_misra.c +++ b/common_smp/src/tx_misra.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -30,7 +31,7 @@ #ifdef TX_MISRA_ENABLE #define TX_THREAD_INIT -//CHAR _tx_version_id[100] = "Copyright (c) 2024 Microsoft Corporation. * ThreadX 6.1 MISRA C Compliant *"; +//CHAR _tx_version_id[100] = "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX 6.1 MISRA C Compliant *"; #include "tx_api.h" #include "tx_thread.h" diff --git a/common_smp/src/tx_mutex_cleanup.c b/common_smp/src/tx_mutex_cleanup.c index 09acbf4d..d32f69fc 100644 --- a/common_smp/src/tx_mutex_cleanup.c +++ b/common_smp/src/tx_mutex_cleanup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* _tx_thread_terminate Thread terminate processing */ /* _tx_thread_wait_abort Thread wait abort processing */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_mutex_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) { diff --git a/common_smp/src/tx_mutex_create.c b/common_smp/src/tx_mutex_create.c index 993bf344..436c01f5 100644 --- a/common_smp/src/tx_mutex_create.c +++ b/common_smp/src/tx_mutex_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_mutex_create(TX_MUTEX *mutex_ptr, CHAR *name_ptr, UINT inherit) { diff --git a/common_smp/src/tx_mutex_delete.c b/common_smp/src/tx_mutex_delete.c index ca5aeca8..9c0a5aac 100644 --- a/common_smp/src/tx_mutex_delete.c +++ b/common_smp/src/tx_mutex_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_mutex_delete(TX_MUTEX *mutex_ptr) { diff --git a/common_smp/src/tx_mutex_get.c b/common_smp/src/tx_mutex_get.c index 91e97f14..402a0f0d 100644 --- a/common_smp/src/tx_mutex_get.c +++ b/common_smp/src/tx_mutex_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_mutex_get(TX_MUTEX *mutex_ptr, ULONG wait_option) { diff --git a/common_smp/src/tx_mutex_info_get.c b/common_smp/src/tx_mutex_info_get.c index 219bcc18..a24d1e30 100644 --- a/common_smp/src/tx_mutex_info_get.c +++ b/common_smp/src/tx_mutex_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,14 +69,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_mutex_info_get(TX_MUTEX *mutex_ptr, CHAR **name, ULONG *count, TX_THREAD **owner, TX_THREAD **first_suspended, ULONG *suspended_count, diff --git a/common_smp/src/tx_mutex_initialize.c b/common_smp/src/tx_mutex_initialize.c index ea2ca458..98460cd6 100644 --- a/common_smp/src/tx_mutex_initialize.c +++ b/common_smp/src/tx_mutex_initialize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -107,17 +108,6 @@ ULONG _tx_mutex_performance__priority_inheritance_count; /* */ /* _tx_initialize_high_level High level initialization */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* opt out of function when */ -/* TX_INLINE_INITIALIZATION is */ -/* defined, */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_mutex_initialize(VOID) { diff --git a/common_smp/src/tx_mutex_performance_info_get.c b/common_smp/src/tx_mutex_performance_info_get.c index 501a417a..0704c111 100644 --- a/common_smp/src/tx_mutex_performance_info_get.c +++ b/common_smp/src/tx_mutex_performance_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -73,14 +74,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_mutex_performance_info_get(TX_MUTEX *mutex_ptr, ULONG *puts, ULONG *gets, ULONG *suspensions, ULONG *timeouts, ULONG *inversions, ULONG *inheritances) diff --git a/common_smp/src/tx_mutex_performance_system_info_get.c b/common_smp/src/tx_mutex_performance_system_info_get.c index 9ca17197..458a5945 100644 --- a/common_smp/src/tx_mutex_performance_system_info_get.c +++ b/common_smp/src/tx_mutex_performance_system_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,14 +73,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_mutex_performance_system_info_get(ULONG *puts, ULONG *gets, ULONG *suspensions, ULONG *timeouts, ULONG *inversions, ULONG *inheritances) diff --git a/common_smp/src/tx_mutex_prioritize.c b/common_smp/src/tx_mutex_prioritize.c index 3006b7d0..6522307d 100644 --- a/common_smp/src/tx_mutex_prioritize.c +++ b/common_smp/src/tx_mutex_prioritize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_mutex_prioritize(TX_MUTEX *mutex_ptr) { diff --git a/common_smp/src/tx_mutex_priority_change.c b/common_smp/src/tx_mutex_priority_change.c index e7d2eeaf..8722a8fb 100644 --- a/common_smp/src/tx_mutex_priority_change.c +++ b/common_smp/src/tx_mutex_priority_change.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ /* _tx_mutex_get Inherit priority */ /* _tx_mutex_put Restore previous priority */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_mutex_priority_change(TX_THREAD *thread_ptr, UINT new_priority) { diff --git a/common_smp/src/tx_mutex_put.c b/common_smp/src/tx_mutex_put.c index 6ac5065d..062472a2 100644 --- a/common_smp/src/tx_mutex_put.c +++ b/common_smp/src/tx_mutex_put.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,14 +68,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_mutex_put(TX_MUTEX *mutex_ptr) { diff --git a/common_smp/src/tx_queue_cleanup.c b/common_smp/src/tx_queue_cleanup.c index 82d02f45..05a423b3 100644 --- a/common_smp/src/tx_queue_cleanup.c +++ b/common_smp/src/tx_queue_cleanup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* _tx_thread_terminate Thread terminate processing */ /* _tx_thread_wait_abort Thread wait abort processing */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_queue_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) { diff --git a/common_smp/src/tx_queue_create.c b/common_smp/src/tx_queue_create.c index 00edbad9..59ae154e 100644 --- a/common_smp/src/tx_queue_create.c +++ b/common_smp/src/tx_queue_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_queue_create(TX_QUEUE *queue_ptr, CHAR *name_ptr, UINT message_size, VOID *queue_start, ULONG queue_size) diff --git a/common_smp/src/tx_queue_delete.c b/common_smp/src/tx_queue_delete.c index 9887b160..6a2bcf6f 100644 --- a/common_smp/src/tx_queue_delete.c +++ b/common_smp/src/tx_queue_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_queue_delete(TX_QUEUE *queue_ptr) { diff --git a/common_smp/src/tx_queue_flush.c b/common_smp/src/tx_queue_flush.c index 5120c898..b721cf50 100644 --- a/common_smp/src/tx_queue_flush.c +++ b/common_smp/src/tx_queue_flush.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_queue_flush(TX_QUEUE *queue_ptr) { diff --git a/common_smp/src/tx_queue_front_send.c b/common_smp/src/tx_queue_front_send.c index 5e8b4104..bb39b970 100644 --- a/common_smp/src/tx_queue_front_send.c +++ b/common_smp/src/tx_queue_front_send.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,14 +68,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_queue_front_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option) { diff --git a/common_smp/src/tx_queue_info_get.c b/common_smp/src/tx_queue_info_get.c index 3b37b37f..d0ecb2b6 100644 --- a/common_smp/src/tx_queue_info_get.c +++ b/common_smp/src/tx_queue_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,14 +68,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_queue_info_get(TX_QUEUE *queue_ptr, CHAR **name, ULONG *enqueued, ULONG *available_storage, TX_THREAD **first_suspended, ULONG *suspended_count, TX_QUEUE **next_queue) diff --git a/common_smp/src/tx_queue_initialize.c b/common_smp/src/tx_queue_initialize.c index 7a811234..eb34f18b 100644 --- a/common_smp/src/tx_queue_initialize.c +++ b/common_smp/src/tx_queue_initialize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -105,17 +106,6 @@ ULONG _tx_queue_performance_timeout_count; /* */ /* _tx_initialize_high_level High level initialization */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* opt out of function when */ -/* TX_INLINE_INITIALIZATION is */ -/* defined, */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_queue_initialize(VOID) { diff --git a/common_smp/src/tx_queue_performance_info_get.c b/common_smp/src/tx_queue_performance_info_get.c index 721a7e5f..7c426515 100644 --- a/common_smp/src/tx_queue_performance_info_get.c +++ b/common_smp/src/tx_queue_performance_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,14 +73,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_queue_performance_info_get(TX_QUEUE *queue_ptr, ULONG *messages_sent, ULONG *messages_received, ULONG *empty_suspensions, ULONG *full_suspensions, ULONG *full_errors, ULONG *timeouts) diff --git a/common_smp/src/tx_queue_performance_system_info_get.c b/common_smp/src/tx_queue_performance_system_info_get.c index 87cfb4a6..306c97a2 100644 --- a/common_smp/src/tx_queue_performance_system_info_get.c +++ b/common_smp/src/tx_queue_performance_system_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,14 +73,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_queue_performance_system_info_get(ULONG *messages_sent, ULONG *messages_received, ULONG *empty_suspensions, ULONG *full_suspensions, ULONG *full_errors, ULONG *timeouts) diff --git a/common_smp/src/tx_queue_prioritize.c b/common_smp/src/tx_queue_prioritize.c index 4f875078..dbea0a6b 100644 --- a/common_smp/src/tx_queue_prioritize.c +++ b/common_smp/src/tx_queue_prioritize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_queue_prioritize(TX_QUEUE *queue_ptr) { diff --git a/common_smp/src/tx_queue_receive.c b/common_smp/src/tx_queue_receive.c index 31a22f94..a6ab0390 100644 --- a/common_smp/src/tx_queue_receive.c +++ b/common_smp/src/tx_queue_receive.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -69,14 +70,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_queue_receive(TX_QUEUE *queue_ptr, VOID *destination_ptr, ULONG wait_option) { diff --git a/common_smp/src/tx_queue_send.c b/common_smp/src/tx_queue_send.c index 3ca970a0..7d22f5b9 100644 --- a/common_smp/src/tx_queue_send.c +++ b/common_smp/src/tx_queue_send.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,14 +68,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_queue_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option) { diff --git a/common_smp/src/tx_queue_send_notify.c b/common_smp/src/tx_queue_send_notify.c index f46d153a..05af2f03 100644 --- a/common_smp/src/tx_queue_send_notify.c +++ b/common_smp/src/tx_queue_send_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_queue_send_notify(TX_QUEUE *queue_ptr, VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)) { diff --git a/common_smp/src/tx_semaphore_ceiling_put.c b/common_smp/src/tx_semaphore_ceiling_put.c index a72b094a..9b02e731 100644 --- a/common_smp/src/tx_semaphore_ceiling_put.c +++ b/common_smp/src/tx_semaphore_ceiling_put.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_semaphore_ceiling_put(TX_SEMAPHORE *semaphore_ptr, ULONG ceiling) { diff --git a/common_smp/src/tx_semaphore_cleanup.c b/common_smp/src/tx_semaphore_cleanup.c index 512f6c60..0e3cd965 100644 --- a/common_smp/src/tx_semaphore_cleanup.c +++ b/common_smp/src/tx_semaphore_cleanup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* _tx_thread_terminate Thread terminate processing */ /* _tx_thread_wait_abort Thread wait abort processing */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_semaphore_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) { diff --git a/common_smp/src/tx_semaphore_create.c b/common_smp/src/tx_semaphore_create.c index 3acf3f41..849f5d3b 100644 --- a/common_smp/src/tx_semaphore_create.c +++ b/common_smp/src/tx_semaphore_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_semaphore_create(TX_SEMAPHORE *semaphore_ptr, CHAR *name_ptr, ULONG initial_count) { diff --git a/common_smp/src/tx_semaphore_delete.c b/common_smp/src/tx_semaphore_delete.c index eee19755..8a0515a0 100644 --- a/common_smp/src/tx_semaphore_delete.c +++ b/common_smp/src/tx_semaphore_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_semaphore_delete(TX_SEMAPHORE *semaphore_ptr) { diff --git a/common_smp/src/tx_semaphore_get.c b/common_smp/src/tx_semaphore_get.c index 5a471997..52802da1 100644 --- a/common_smp/src/tx_semaphore_get.c +++ b/common_smp/src/tx_semaphore_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_semaphore_get(TX_SEMAPHORE *semaphore_ptr, ULONG wait_option) { diff --git a/common_smp/src/tx_semaphore_info_get.c b/common_smp/src/tx_semaphore_info_get.c index 70e98a71..89fd9423 100644 --- a/common_smp/src/tx_semaphore_info_get.c +++ b/common_smp/src/tx_semaphore_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,14 +68,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_semaphore_info_get(TX_SEMAPHORE *semaphore_ptr, CHAR **name, ULONG *current_value, TX_THREAD **first_suspended, ULONG *suspended_count, diff --git a/common_smp/src/tx_semaphore_initialize.c b/common_smp/src/tx_semaphore_initialize.c index 84358cc5..d2b169df 100644 --- a/common_smp/src/tx_semaphore_initialize.c +++ b/common_smp/src/tx_semaphore_initialize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -97,17 +98,6 @@ ULONG _tx_semaphore_performance_timeout_count; /* */ /* _tx_initialize_high_level High level initialization */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* opt out of function when */ -/* TX_INLINE_INITIALIZATION is */ -/* defined, */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_semaphore_initialize(VOID) { diff --git a/common_smp/src/tx_semaphore_performance_info_get.c b/common_smp/src/tx_semaphore_performance_info_get.c index a623705f..4c7ffa4e 100644 --- a/common_smp/src/tx_semaphore_performance_info_get.c +++ b/common_smp/src/tx_semaphore_performance_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,14 +71,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_semaphore_performance_info_get(TX_SEMAPHORE *semaphore_ptr, ULONG *puts, ULONG *gets, ULONG *suspensions, ULONG *timeouts) diff --git a/common_smp/src/tx_semaphore_performance_system_info_get.c b/common_smp/src/tx_semaphore_performance_system_info_get.c index 5245d00b..db17c937 100644 --- a/common_smp/src/tx_semaphore_performance_system_info_get.c +++ b/common_smp/src/tx_semaphore_performance_system_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,14 +69,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_semaphore_performance_system_info_get(ULONG *puts, ULONG *gets, ULONG *suspensions, ULONG *timeouts) { diff --git a/common_smp/src/tx_semaphore_prioritize.c b/common_smp/src/tx_semaphore_prioritize.c index 56245df8..eec5e7b7 100644 --- a/common_smp/src/tx_semaphore_prioritize.c +++ b/common_smp/src/tx_semaphore_prioritize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_semaphore_prioritize(TX_SEMAPHORE *semaphore_ptr) { diff --git a/common_smp/src/tx_semaphore_put.c b/common_smp/src/tx_semaphore_put.c index dacd0db0..1ce9d145 100644 --- a/common_smp/src/tx_semaphore_put.c +++ b/common_smp/src/tx_semaphore_put.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_semaphore_put(TX_SEMAPHORE *semaphore_ptr) { diff --git a/common_smp/src/tx_semaphore_put_notify.c b/common_smp/src/tx_semaphore_put_notify.c index b1abe3be..80894d6e 100644 --- a/common_smp/src/tx_semaphore_put_notify.c +++ b/common_smp/src/tx_semaphore_put_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_semaphore_put_notify(TX_SEMAPHORE *semaphore_ptr, VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)) { diff --git a/common_smp/src/tx_thread_create.c b/common_smp/src/tx_thread_create.c index f66e393c..28a1dae1 100644 --- a/common_smp/src/tx_thread_create.c +++ b/common_smp/src/tx_thread_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -75,24 +76,6 @@ /* Application Code */ /* _tx_timer_initialize Create system timer thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 12-31-2020 Andres Mlinar Modified comment(s), */ -/* resulting in version 6.1.3 */ -/* 08-02-2021 Scott Larson Removed unneeded cast, */ -/* resulting in version 6.1.8 */ -/* 10-31-2022 Scott Larson Removed ifdef block to always */ -/* restore interrupts at end */ -/* of if block, */ -/* resulting in version 6.2.0 */ -/* 10-31-2023 Xiuwen Cai Modified comment(s), */ -/* added option for random */ -/* number stack filling, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ UINT _tx_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr, VOID (*entry_function)(ULONG id), ULONG entry_input, diff --git a/common_smp/src/tx_thread_delete.c b/common_smp/src/tx_thread_delete.c index 69626c50..510f6565 100644 --- a/common_smp/src/tx_thread_delete.c +++ b/common_smp/src/tx_thread_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_delete(TX_THREAD *thread_ptr) { diff --git a/common_smp/src/tx_thread_entry_exit_notify.c b/common_smp/src/tx_thread_entry_exit_notify.c index 7d5919de..fdce25ef 100644 --- a/common_smp/src/tx_thread_entry_exit_notify.c +++ b/common_smp/src/tx_thread_entry_exit_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_entry_exit_notify(TX_THREAD *thread_ptr, VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT id)) { diff --git a/common_smp/src/tx_thread_identify.c b/common_smp/src/tx_thread_identify.c index 7808d053..86f56194 100644 --- a/common_smp/src/tx_thread_identify.c +++ b/common_smp/src/tx_thread_identify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ TX_THREAD *_tx_thread_identify(VOID) { diff --git a/common_smp/src/tx_thread_info_get.c b/common_smp/src/tx_thread_info_get.c index d9069457..740a3b95 100644 --- a/common_smp/src/tx_thread_info_get.c +++ b/common_smp/src/tx_thread_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,14 +71,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_info_get(TX_THREAD *thread_ptr, CHAR **name, UINT *state, ULONG *run_count, UINT *priority, UINT *preemption_threshold, ULONG *time_slice, diff --git a/common_smp/src/tx_thread_initialize.c b/common_smp/src/tx_thread_initialize.c index eb0fc059..f3793109 100644 --- a/common_smp/src/tx_thread_initialize.c +++ b/common_smp/src/tx_thread_initialize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -341,12 +342,6 @@ const CHAR _tx_thread_special_string[] = /* */ /* _tx_initialize_high_level High level initialization */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_thread_initialize(VOID) { diff --git a/common_smp/src/tx_thread_performance_info_get.c b/common_smp/src/tx_thread_performance_info_get.c index 92c0e02b..79a8c7ee 100644 --- a/common_smp/src/tx_thread_performance_info_get.c +++ b/common_smp/src/tx_thread_performance_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -87,14 +88,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_performance_info_get(TX_THREAD *thread_ptr, ULONG *resumptions, ULONG *suspensions, ULONG *solicited_preemptions, ULONG *interrupt_preemptions, ULONG *priority_inversions, diff --git a/common_smp/src/tx_thread_performance_system_info_get.c b/common_smp/src/tx_thread_performance_system_info_get.c index a6c300aa..8ade15dd 100644 --- a/common_smp/src/tx_thread_performance_system_info_get.c +++ b/common_smp/src/tx_thread_performance_system_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -87,14 +88,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_performance_system_info_get(ULONG *resumptions, ULONG *suspensions, ULONG *solicited_preemptions, ULONG *interrupt_preemptions, ULONG *priority_inversions, diff --git a/common_smp/src/tx_thread_preemption_change.c b/common_smp/src/tx_thread_preemption_change.c index eac39d6f..b309308c 100644 --- a/common_smp/src/tx_thread_preemption_change.c +++ b/common_smp/src/tx_thread_preemption_change.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,12 +68,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_preemption_change(TX_THREAD *thread_ptr, UINT new_threshold, UINT *old_threshold) { diff --git a/common_smp/src/tx_thread_priority_change.c b/common_smp/src/tx_thread_priority_change.c index 6436a292..57d6eda7 100644 --- a/common_smp/src/tx_thread_priority_change.c +++ b/common_smp/src/tx_thread_priority_change.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,12 +75,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_priority_change(TX_THREAD *thread_ptr, UINT new_priority, UINT *old_priority) { diff --git a/common_smp/src/tx_thread_relinquish.c b/common_smp/src/tx_thread_relinquish.c index ea160b50..10982b26 100644 --- a/common_smp/src/tx_thread_relinquish.c +++ b/common_smp/src/tx_thread_relinquish.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,12 +66,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_thread_relinquish(VOID) { diff --git a/common_smp/src/tx_thread_reset.c b/common_smp/src/tx_thread_reset.c index 1fea78be..da56daf5 100644 --- a/common_smp/src/tx_thread_reset.c +++ b/common_smp/src/tx_thread_reset.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_reset(TX_THREAD *thread_ptr) { diff --git a/common_smp/src/tx_thread_resume.c b/common_smp/src/tx_thread_resume.c index 1537c730..e2da7d23 100644 --- a/common_smp/src/tx_thread_resume.c +++ b/common_smp/src/tx_thread_resume.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,12 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_resume(TX_THREAD *thread_ptr) { diff --git a/common_smp/src/tx_thread_shell_entry.c b/common_smp/src/tx_thread_shell_entry.c index 161ea80e..45fe9d6d 100644 --- a/common_smp/src/tx_thread_shell_entry.c +++ b/common_smp/src/tx_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_thread_shell_entry(VOID) { diff --git a/common_smp/src/tx_thread_sleep.c b/common_smp/src/tx_thread_sleep.c index 6d6c92c4..fd986a0b 100644 --- a/common_smp/src/tx_thread_sleep.c +++ b/common_smp/src/tx_thread_sleep.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_sleep(ULONG timer_ticks) { diff --git a/common_smp/src/tx_thread_smp_core_exclude.c b/common_smp/src/tx_thread_smp_core_exclude.c index 477c99f1..ee67cfce 100644 --- a/common_smp/src/tx_thread_smp_core_exclude.c +++ b/common_smp/src/tx_thread_smp_core_exclude.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,12 +68,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_smp_core_exclude(TX_THREAD *thread_ptr, ULONG exclusion_map) { diff --git a/common_smp/src/tx_thread_smp_core_exclude_get.c b/common_smp/src/tx_thread_smp_core_exclude_get.c index 962f45e3..bc517f5d 100644 --- a/common_smp/src/tx_thread_smp_core_exclude_get.c +++ b/common_smp/src/tx_thread_smp_core_exclude_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_smp_core_exclude_get(TX_THREAD *thread_ptr, ULONG *exclusion_map_ptr) { diff --git a/common_smp/src/tx_thread_smp_current_state_set.c b/common_smp/src/tx_thread_smp_current_state_set.c index 5491aa18..0187ac8c 100644 --- a/common_smp/src/tx_thread_smp_current_state_set.c +++ b/common_smp/src/tx_thread_smp_current_state_set.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,12 +63,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ void _tx_thread_smp_current_state_set(ULONG new_state) { diff --git a/common_smp/src/tx_thread_smp_debug_entry_insert.c b/common_smp/src/tx_thread_smp_debug_entry_insert.c index 70e86dc7..95148703 100644 --- a/common_smp/src/tx_thread_smp_debug_entry_insert.c +++ b/common_smp/src/tx_thread_smp_debug_entry_insert.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -118,12 +119,6 @@ ULONG _tx_thread_smp_debug_info_current_index; /* */ /* Internal routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ void _tx_thread_smp_debug_entry_insert(ULONG id, ULONG suspend, VOID *thread_void_ptr) { diff --git a/common_smp/src/tx_thread_smp_high_level_initialize.c b/common_smp/src/tx_thread_smp_high_level_initialize.c index 73c77ac6..a544b3de 100644 --- a/common_smp/src/tx_thread_smp_high_level_initialize.c +++ b/common_smp/src/tx_thread_smp_high_level_initialize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,16 +64,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 12-31-2020 William E. Lamie Modified comments, added */ -/* cast to address a MISRA */ -/* compliant issue, */ -/* resulting in version 6.1.3 */ -/* */ /**************************************************************************/ void _tx_thread_smp_high_level_initialize(void) { diff --git a/common_smp/src/tx_thread_smp_rebalance_execute_list.c b/common_smp/src/tx_thread_smp_rebalance_execute_list.c index 019c7209..6be7257a 100644 --- a/common_smp/src/tx_thread_smp_rebalance_execute_list.c +++ b/common_smp/src/tx_thread_smp_rebalance_execute_list.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,12 +83,6 @@ /* _tx_thread_system_suspend Thread suspend */ /* _tx_thread_time_slice Thread time-slice */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ void _tx_thread_smp_rebalance_execute_list(UINT core_index) { diff --git a/common_smp/src/tx_thread_smp_utilities.c b/common_smp/src/tx_thread_smp_utilities.c index 25e24df1..833a9aab 100644 --- a/common_smp/src/tx_thread_smp_utilities.c +++ b/common_smp/src/tx_thread_smp_utilities.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/common_smp/src/tx_thread_stack_analyze.c b/common_smp/src/tx_thread_stack_analyze.c index bdadab0d..080d0052 100644 --- a/common_smp/src/tx_thread_stack_analyze.c +++ b/common_smp/src/tx_thread_stack_analyze.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,14 +61,6 @@ /* */ /* ThreadX internal code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_thread_stack_analyze(TX_THREAD *thread_ptr) { diff --git a/common_smp/src/tx_thread_stack_error_handler.c b/common_smp/src/tx_thread_stack_error_handler.c index 1f8d89fa..d82005f0 100644 --- a/common_smp/src/tx_thread_stack_error_handler.c +++ b/common_smp/src/tx_thread_stack_error_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,15 +61,6 @@ /* */ /* ThreadX internal code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-16-2020 William E. Lamie Modified comment(s), */ -/* fixed link issue, */ -/* resulting in version 6.1.1 */ -/* */ /**************************************************************************/ VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) { diff --git a/common_smp/src/tx_thread_stack_error_notify.c b/common_smp/src/tx_thread_stack_error_notify.c index 4a257740..b300a131 100644 --- a/common_smp/src/tx_thread_stack_error_notify.c +++ b/common_smp/src/tx_thread_stack_error_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,12 +67,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) { diff --git a/common_smp/src/tx_thread_suspend.c b/common_smp/src/tx_thread_suspend.c index c600c3df..1ad3cd81 100644 --- a/common_smp/src/tx_thread_suspend.c +++ b/common_smp/src/tx_thread_suspend.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_suspend(TX_THREAD *thread_ptr) { diff --git a/common_smp/src/tx_thread_system_preempt_check.c b/common_smp/src/tx_thread_system_preempt_check.c index e9efa2fb..c70072c5 100644 --- a/common_smp/src/tx_thread_system_preempt_check.c +++ b/common_smp/src/tx_thread_system_preempt_check.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Other ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_thread_system_preempt_check(VOID) { diff --git a/common_smp/src/tx_thread_system_resume.c b/common_smp/src/tx_thread_system_resume.c index 77c09219..256c06f2 100644 --- a/common_smp/src/tx_thread_system_resume.c +++ b/common_smp/src/tx_thread_system_resume.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -90,12 +91,6 @@ /* _tx_thread_wait_abort Thread wait abort */ /* Other ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_thread_system_resume(TX_THREAD *thread_ptr) { diff --git a/common_smp/src/tx_thread_system_suspend.c b/common_smp/src/tx_thread_system_suspend.c index 63398999..d5bf5cc7 100644 --- a/common_smp/src/tx_thread_system_suspend.c +++ b/common_smp/src/tx_thread_system_suspend.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,17 +83,6 @@ /* _tx_thread_terminate Thread terminate */ /* Other ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Scott Larson Modified comments and fixed */ -/* loop to find next thread, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Fixed MISRA2012 rule 10.4_a, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ VOID _tx_thread_system_suspend(TX_THREAD *thread_ptr) { diff --git a/common_smp/src/tx_thread_terminate.c b/common_smp/src/tx_thread_terminate.c index 1e30687f..86e34bae 100644 --- a/common_smp/src/tx_thread_terminate.c +++ b/common_smp/src/tx_thread_terminate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,14 +68,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_terminate(TX_THREAD *thread_ptr) { diff --git a/common_smp/src/tx_thread_time_slice.c b/common_smp/src/tx_thread_time_slice.c index e48f68a6..8a45ab30 100644 --- a/common_smp/src/tx_thread_time_slice.c +++ b/common_smp/src/tx_thread_time_slice.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,12 +65,6 @@ /* */ /* _tx_timer_interrupt Timer interrupt handling */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_thread_time_slice(VOID) { diff --git a/common_smp/src/tx_thread_time_slice_change.c b/common_smp/src/tx_thread_time_slice_change.c index ba4f523c..b2204857 100644 --- a/common_smp/src/tx_thread_time_slice_change.c +++ b/common_smp/src/tx_thread_time_slice_change.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,12 +67,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_time_slice_change(TX_THREAD *thread_ptr, ULONG new_time_slice, ULONG *old_time_slice) { diff --git a/common_smp/src/tx_thread_timeout.c b/common_smp/src/tx_thread_timeout.c index 33ea5352..21b62e34 100644 --- a/common_smp/src/tx_thread_timeout.c +++ b/common_smp/src/tx_thread_timeout.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,14 +67,6 @@ /* _tx_timer_expiration_process Timer expiration function */ /* _tx_timer_thread_entry Timer thread function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_thread_timeout(ULONG timeout_input) { diff --git a/common_smp/src/tx_thread_wait_abort.c b/common_smp/src/tx_thread_wait_abort.c index 372a72b2..24bce69b 100644 --- a/common_smp/src/tx_thread_wait_abort.c +++ b/common_smp/src/tx_thread_wait_abort.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,17 +64,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* 03-08-2023 Scott Larson Check if thread is coming out */ -/* of suspension elsewhere, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_wait_abort(TX_THREAD *thread_ptr) { diff --git a/common_smp/src/tx_time_get.c b/common_smp/src/tx_time_get.c index 16361142..6ed7d731 100644 --- a/common_smp/src/tx_time_get.c +++ b/common_smp/src/tx_time_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,16 +61,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* 12-31-2020 Andres Mlinar Modified comment(s), */ -/* resulting in version 6.1.3 */ -/* */ /**************************************************************************/ ULONG _tx_time_get(VOID) { diff --git a/common_smp/src/tx_time_set.c b/common_smp/src/tx_time_set.c index 613274ac..97b42986 100644 --- a/common_smp/src/tx_time_set.c +++ b/common_smp/src/tx_time_set.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,14 +61,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_time_set(ULONG new_time) { diff --git a/common_smp/src/tx_timer_activate.c b/common_smp/src/tx_timer_activate.c index d8609573..5a59eade 100644 --- a/common_smp/src/tx_timer_activate.c +++ b/common_smp/src/tx_timer_activate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_timer_activate(TX_TIMER *timer_ptr) { diff --git a/common_smp/src/tx_timer_change.c b/common_smp/src/tx_timer_change.c index 420ff26a..24661d3d 100644 --- a/common_smp/src/tx_timer_change.c +++ b/common_smp/src/tx_timer_change.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_timer_change(TX_TIMER *timer_ptr, ULONG initial_ticks, ULONG reschedule_ticks) { diff --git a/common_smp/src/tx_timer_create.c b/common_smp/src/tx_timer_create.c index 7666724f..73fa67cd 100644 --- a/common_smp/src/tx_timer_create.c +++ b/common_smp/src/tx_timer_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,12 +67,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_timer_create(TX_TIMER *timer_ptr, CHAR *name_ptr, VOID (*expiration_function)(ULONG id), ULONG expiration_input, diff --git a/common_smp/src/tx_timer_deactivate.c b/common_smp/src/tx_timer_deactivate.c index 97c786bf..98eacd4b 100644 --- a/common_smp/src/tx_timer_deactivate.c +++ b/common_smp/src/tx_timer_deactivate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_timer_deactivate(TX_TIMER *timer_ptr) { diff --git a/common_smp/src/tx_timer_delete.c b/common_smp/src/tx_timer_delete.c index 7baef6d4..60d425ec 100644 --- a/common_smp/src/tx_timer_delete.c +++ b/common_smp/src/tx_timer_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_timer_delete(TX_TIMER *timer_ptr) { diff --git a/common_smp/src/tx_timer_expiration_process.c b/common_smp/src/tx_timer_expiration_process.c index f30c2d52..f54e982d 100644 --- a/common_smp/src/tx_timer_expiration_process.c +++ b/common_smp/src/tx_timer_expiration_process.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,12 +67,6 @@ /* */ /* _tx_timer_interrupt Timer interrupt handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_timer_expiration_process(VOID) { diff --git a/common_smp/src/tx_timer_info_get.c b/common_smp/src/tx_timer_info_get.c index ca04c4ea..31c801f9 100644 --- a/common_smp/src/tx_timer_info_get.c +++ b/common_smp/src/tx_timer_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,14 +67,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_timer_info_get(TX_TIMER *timer_ptr, CHAR **name, UINT *active, ULONG *remaining_ticks, ULONG *reschedule_ticks, TX_TIMER **next_timer) diff --git a/common_smp/src/tx_timer_initialize.c b/common_smp/src/tx_timer_initialize.c index 89a15926..327f2a65 100644 --- a/common_smp/src/tx_timer_initialize.c +++ b/common_smp/src/tx_timer_initialize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -199,12 +200,6 @@ ULONG _tx_timer_time_slice[TX_THREAD_SMP_MAX_CORES]; /* */ /* _tx_initialize_high_level High level initialization */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_timer_initialize(VOID) { diff --git a/common_smp/src/tx_timer_performance_info_get.c b/common_smp/src/tx_timer_performance_info_get.c index 05e332c1..37cacee4 100644 --- a/common_smp/src/tx_timer_performance_info_get.c +++ b/common_smp/src/tx_timer_performance_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -73,14 +74,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_timer_performance_info_get(TX_TIMER *timer_ptr, ULONG *activates, ULONG *reactivates, ULONG *deactivates, ULONG *expirations, ULONG *expiration_adjusts) diff --git a/common_smp/src/tx_timer_performance_system_info_get.c b/common_smp/src/tx_timer_performance_system_info_get.c index 367e1149..9b6c3862 100644 --- a/common_smp/src/tx_timer_performance_system_info_get.c +++ b/common_smp/src/tx_timer_performance_system_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,14 +71,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_timer_performance_system_info_get(ULONG *activates, ULONG *reactivates, ULONG *deactivates, ULONG *expirations, ULONG *expiration_adjusts) diff --git a/common_smp/src/tx_timer_smp_core_exclude.c b/common_smp/src/tx_timer_smp_core_exclude.c index 8600967f..9048c1e5 100644 --- a/common_smp/src/tx_timer_smp_core_exclude.c +++ b/common_smp/src/tx_timer_smp_core_exclude.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,12 +67,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_timer_smp_core_exclude(TX_TIMER *timer_ptr, ULONG exclusion_map) { diff --git a/common_smp/src/tx_timer_smp_core_exclude_get.c b/common_smp/src/tx_timer_smp_core_exclude_get.c index 52d5022f..0092e773 100644 --- a/common_smp/src/tx_timer_smp_core_exclude_get.c +++ b/common_smp/src/tx_timer_smp_core_exclude_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_timer_smp_core_exclude_get(TX_TIMER *timer_ptr, ULONG *exclusion_map_ptr) { diff --git a/common_smp/src/tx_timer_system_activate.c b/common_smp/src/tx_timer_system_activate.c index a27e8536..51cd107b 100644 --- a/common_smp/src/tx_timer_system_activate.c +++ b/common_smp/src/tx_timer_system_activate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* _tx_timer_thread_entry Timer thread processing */ /* _tx_timer_activate Application timer activate */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_timer_system_activate(TX_TIMER_INTERNAL *timer_ptr) { diff --git a/common_smp/src/tx_timer_system_deactivate.c b/common_smp/src/tx_timer_system_deactivate.c index 487ead9d..ae955077 100644 --- a/common_smp/src/tx_timer_system_deactivate.c +++ b/common_smp/src/tx_timer_system_deactivate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* _tx_thread_system_resume Thread resume function */ /* _tx_timer_thread_entry Timer thread processing */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_timer_system_deactivate(TX_TIMER_INTERNAL *timer_ptr) { diff --git a/common_smp/src/tx_timer_thread_entry.c b/common_smp/src/tx_timer_thread_entry.c index e8709c75..51b165b2 100644 --- a/common_smp/src/tx_timer_thread_entry.c +++ b/common_smp/src/tx_timer_thread_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,12 +66,6 @@ /* */ /* ThreadX Scheduler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_TIMER_PROCESS_IN_ISR VOID _tx_timer_thread_entry(ULONG timer_thread_input) diff --git a/common_smp/src/tx_trace_buffer_full_notify.c b/common_smp/src/tx_trace_buffer_full_notify.c index 9e07c0a3..7253e8a4 100644 --- a/common_smp/src/tx_trace_buffer_full_notify.c +++ b/common_smp/src/tx_trace_buffer_full_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_trace_buffer_full_notify(VOID (*full_buffer_callback)(VOID *buffer)) { diff --git a/common_smp/src/tx_trace_disable.c b/common_smp/src/tx_trace_disable.c index 1ef211e0..96c28740 100644 --- a/common_smp/src/tx_trace_disable.c +++ b/common_smp/src/tx_trace_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_trace_disable(VOID) { diff --git a/common_smp/src/tx_trace_enable.c b/common_smp/src/tx_trace_enable.c index aa372e8d..2fb1252c 100644 --- a/common_smp/src/tx_trace_enable.c +++ b/common_smp/src/tx_trace_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -73,14 +74,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_trace_enable(VOID *trace_buffer_start, ULONG trace_buffer_size, ULONG registry_entries) { diff --git a/common_smp/src/tx_trace_event_filter.c b/common_smp/src/tx_trace_event_filter.c index 3afb8ed5..9caf18ae 100644 --- a/common_smp/src/tx_trace_event_filter.c +++ b/common_smp/src/tx_trace_event_filter.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_trace_event_filter(ULONG event_filter_bits) { diff --git a/common_smp/src/tx_trace_event_unfilter.c b/common_smp/src/tx_trace_event_unfilter.c index f9d054d7..652e4143 100644 --- a/common_smp/src/tx_trace_event_unfilter.c +++ b/common_smp/src/tx_trace_event_unfilter.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_trace_event_unfilter(ULONG event_unfilter_bits) { diff --git a/common_smp/src/tx_trace_initialize.c b/common_smp/src/tx_trace_initialize.c index 14877b9c..5cec8eae 100644 --- a/common_smp/src/tx_trace_initialize.c +++ b/common_smp/src/tx_trace_initialize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -125,14 +126,6 @@ ULONG _tx_trace_registry_search_start; /* */ /* _tx_initialize_high_level High level initialization */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_trace_initialize(VOID) { diff --git a/common_smp/src/tx_trace_interrupt_control.c b/common_smp/src/tx_trace_interrupt_control.c index 595dff77..2e35c62d 100644 --- a/common_smp/src/tx_trace_interrupt_control.c +++ b/common_smp/src/tx_trace_interrupt_control.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,14 +61,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_trace_interrupt_control(UINT new_posture) { diff --git a/common_smp/src/tx_trace_isr_enter_insert.c b/common_smp/src/tx_trace_isr_enter_insert.c index 628cc8ff..f9971cf2 100644 --- a/common_smp/src/tx_trace_isr_enter_insert.c +++ b/common_smp/src/tx_trace_isr_enter_insert.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_trace_isr_enter_insert(ULONG isr_id) { diff --git a/common_smp/src/tx_trace_isr_exit_insert.c b/common_smp/src/tx_trace_isr_exit_insert.c index 0d743c19..a4a8ade8 100644 --- a/common_smp/src/tx_trace_isr_exit_insert.c +++ b/common_smp/src/tx_trace_isr_exit_insert.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_trace_isr_exit_insert(ULONG isr_id) { diff --git a/common_smp/src/tx_trace_object_register.c b/common_smp/src/tx_trace_object_register.c index 0805063d..f7cd4a4a 100644 --- a/common_smp/src/tx_trace_object_register.c +++ b/common_smp/src/tx_trace_object_register.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,17 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* 07-29-2022 Scott Larson Modified comment(s), */ -/* check for null name, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ VOID _tx_trace_object_register(UCHAR object_type, VOID *object_ptr, CHAR *object_name, ULONG parameter_1, ULONG parameter_2) { diff --git a/common_smp/src/tx_trace_object_unregister.c b/common_smp/src/tx_trace_object_unregister.c index a7fef275..2166c973 100644 --- a/common_smp/src/tx_trace_object_unregister.c +++ b/common_smp/src/tx_trace_object_unregister.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_trace_object_unregister(VOID *object_ptr) { diff --git a/common_smp/src/tx_trace_user_event_insert.c b/common_smp/src/tx_trace_user_event_insert.c index fda09610..787a55f0 100644 --- a/common_smp/src/tx_trace_user_event_insert.c +++ b/common_smp/src/tx_trace_user_event_insert.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_trace_user_event_insert(ULONG event_id, ULONG info_field_1, ULONG info_field_2, ULONG info_field_3, ULONG info_field_4) { diff --git a/common_smp/src/txe_block_allocate.c b/common_smp/src/txe_block_allocate.c index 5564354b..c9c7a1a8 100644 --- a/common_smp/src/txe_block_allocate.c +++ b/common_smp/src/txe_block_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,14 +68,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_block_allocate(TX_BLOCK_POOL *pool_ptr, VOID **block_ptr, ULONG wait_option) { diff --git a/common_smp/src/txe_block_pool_create.c b/common_smp/src/txe_block_pool_create.c index 8cbeadbd..08ef7e69 100644 --- a/common_smp/src/txe_block_pool_create.c +++ b/common_smp/src/txe_block_pool_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,14 +73,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_block_pool_create(TX_BLOCK_POOL *pool_ptr, CHAR *name_ptr, ULONG block_size, VOID *pool_start, ULONG pool_size, UINT pool_control_block_size) diff --git a/common_smp/src/txe_block_pool_delete.c b/common_smp/src/txe_block_pool_delete.c index 844ff57a..f9af71cb 100644 --- a/common_smp/src/txe_block_pool_delete.c +++ b/common_smp/src/txe_block_pool_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_block_pool_delete(TX_BLOCK_POOL *pool_ptr) { diff --git a/common_smp/src/txe_block_pool_info_get.c b/common_smp/src/txe_block_pool_info_get.c index 77d9df4a..f91ca206 100644 --- a/common_smp/src/txe_block_pool_info_get.c +++ b/common_smp/src/txe_block_pool_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,14 +69,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_block_pool_info_get(TX_BLOCK_POOL *pool_ptr, CHAR **name, ULONG *available_blocks, ULONG *total_blocks, TX_THREAD **first_suspended, diff --git a/common_smp/src/txe_block_pool_prioritize.c b/common_smp/src/txe_block_pool_prioritize.c index 593ac6dc..87742011 100644 --- a/common_smp/src/txe_block_pool_prioritize.c +++ b/common_smp/src/txe_block_pool_prioritize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_block_pool_prioritize(TX_BLOCK_POOL *pool_ptr) { diff --git a/common_smp/src/txe_block_release.c b/common_smp/src/txe_block_release.c index e7eaed24..ba63d0b6 100644 --- a/common_smp/src/txe_block_release.c +++ b/common_smp/src/txe_block_release.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_block_release(VOID *block_ptr) { diff --git a/common_smp/src/txe_byte_allocate.c b/common_smp/src/txe_byte_allocate.c index dbb3937e..dacbede9 100644 --- a/common_smp/src/txe_byte_allocate.c +++ b/common_smp/src/txe_byte_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,14 +71,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_byte_allocate(TX_BYTE_POOL *pool_ptr, VOID **memory_ptr, ULONG memory_size, ULONG wait_option) diff --git a/common_smp/src/txe_byte_pool_create.c b/common_smp/src/txe_byte_pool_create.c index 2f37d063..99a89698 100644 --- a/common_smp/src/txe_byte_pool_create.c +++ b/common_smp/src/txe_byte_pool_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,14 +72,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_byte_pool_create(TX_BYTE_POOL *pool_ptr, CHAR *name_ptr, VOID *pool_start, ULONG pool_size, UINT pool_control_block_size) { diff --git a/common_smp/src/txe_byte_pool_delete.c b/common_smp/src/txe_byte_pool_delete.c index 2a6baad2..6bbeb8f0 100644 --- a/common_smp/src/txe_byte_pool_delete.c +++ b/common_smp/src/txe_byte_pool_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_byte_pool_delete(TX_BYTE_POOL *pool_ptr) { diff --git a/common_smp/src/txe_byte_pool_info_get.c b/common_smp/src/txe_byte_pool_info_get.c index 0a7536ef..85e7a233 100644 --- a/common_smp/src/txe_byte_pool_info_get.c +++ b/common_smp/src/txe_byte_pool_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,14 +69,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_byte_pool_info_get(TX_BYTE_POOL *pool_ptr, CHAR **name, ULONG *available_bytes, ULONG *fragments, TX_THREAD **first_suspended, diff --git a/common_smp/src/txe_byte_pool_prioritize.c b/common_smp/src/txe_byte_pool_prioritize.c index a0f0f1ae..9acec73c 100644 --- a/common_smp/src/txe_byte_pool_prioritize.c +++ b/common_smp/src/txe_byte_pool_prioritize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_byte_pool_prioritize(TX_BYTE_POOL *pool_ptr) { diff --git a/common_smp/src/txe_byte_release.c b/common_smp/src/txe_byte_release.c index 67f91907..89c3a82b 100644 --- a/common_smp/src/txe_byte_release.c +++ b/common_smp/src/txe_byte_release.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_byte_release(VOID *memory_ptr) { diff --git a/common_smp/src/txe_event_flags_create.c b/common_smp/src/txe_event_flags_create.c index 4c71bd95..4e3fed77 100644 --- a/common_smp/src/txe_event_flags_create.c +++ b/common_smp/src/txe_event_flags_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,14 +69,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_event_flags_create(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR *name_ptr, UINT event_control_block_size) { diff --git a/common_smp/src/txe_event_flags_delete.c b/common_smp/src/txe_event_flags_delete.c index 66066276..23c04807 100644 --- a/common_smp/src/txe_event_flags_delete.c +++ b/common_smp/src/txe_event_flags_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_event_flags_delete(TX_EVENT_FLAGS_GROUP *group_ptr) { diff --git a/common_smp/src/txe_event_flags_get.c b/common_smp/src/txe_event_flags_get.c index 23767630..1e9c6e0c 100644 --- a/common_smp/src/txe_event_flags_get.c +++ b/common_smp/src/txe_event_flags_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,14 +72,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_event_flags_get(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG requested_flags, UINT get_option, ULONG *actual_flags_ptr, ULONG wait_option) diff --git a/common_smp/src/txe_event_flags_info_get.c b/common_smp/src/txe_event_flags_info_get.c index 3400c55e..e551d025 100644 --- a/common_smp/src/txe_event_flags_info_get.c +++ b/common_smp/src/txe_event_flags_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,14 +71,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_event_flags_info_get(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR **name, ULONG *current_flags, TX_THREAD **first_suspended, ULONG *suspended_count, diff --git a/common_smp/src/txe_event_flags_set.c b/common_smp/src/txe_event_flags_set.c index 03d309ab..4df57fad 100644 --- a/common_smp/src/txe_event_flags_set.c +++ b/common_smp/src/txe_event_flags_set.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_event_flags_set(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG flags_to_set, UINT set_option) { diff --git a/common_smp/src/txe_event_flags_set_notify.c b/common_smp/src/txe_event_flags_set_notify.c index f93963d3..51887fd7 100644 --- a/common_smp/src/txe_event_flags_set_notify.c +++ b/common_smp/src/txe_event_flags_set_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_event_flags_set_notify(TX_EVENT_FLAGS_GROUP *group_ptr, VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)) { diff --git a/common_smp/src/txe_mutex_create.c b/common_smp/src/txe_mutex_create.c index fb65a5be..392f8b0e 100644 --- a/common_smp/src/txe_mutex_create.c +++ b/common_smp/src/txe_mutex_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -69,14 +70,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_mutex_create(TX_MUTEX *mutex_ptr, CHAR *name_ptr, UINT inherit, UINT mutex_control_block_size) { diff --git a/common_smp/src/txe_mutex_delete.c b/common_smp/src/txe_mutex_delete.c index b2a3fd2b..3692bf89 100644 --- a/common_smp/src/txe_mutex_delete.c +++ b/common_smp/src/txe_mutex_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_mutex_delete(TX_MUTEX *mutex_ptr) { diff --git a/common_smp/src/txe_mutex_get.c b/common_smp/src/txe_mutex_get.c index 7ef04eef..2d457c82 100644 --- a/common_smp/src/txe_mutex_get.c +++ b/common_smp/src/txe_mutex_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,14 +67,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_mutex_get(TX_MUTEX *mutex_ptr, ULONG wait_option) { diff --git a/common_smp/src/txe_mutex_info_get.c b/common_smp/src/txe_mutex_info_get.c index 826fead1..f4ef4168 100644 --- a/common_smp/src/txe_mutex_info_get.c +++ b/common_smp/src/txe_mutex_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -69,14 +70,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_mutex_info_get(TX_MUTEX *mutex_ptr, CHAR **name, ULONG *count, TX_THREAD **owner, TX_THREAD **first_suspended, ULONG *suspended_count, diff --git a/common_smp/src/txe_mutex_prioritize.c b/common_smp/src/txe_mutex_prioritize.c index 9ae4b868..d3302c1c 100644 --- a/common_smp/src/txe_mutex_prioritize.c +++ b/common_smp/src/txe_mutex_prioritize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_mutex_prioritize(TX_MUTEX *mutex_ptr) { diff --git a/common_smp/src/txe_mutex_put.c b/common_smp/src/txe_mutex_put.c index 85d5929f..8a085b7b 100644 --- a/common_smp/src/txe_mutex_put.c +++ b/common_smp/src/txe_mutex_put.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_mutex_put(TX_MUTEX *mutex_ptr) { diff --git a/common_smp/src/txe_queue_create.c b/common_smp/src/txe_queue_create.c index 82a7b53c..387eacb6 100644 --- a/common_smp/src/txe_queue_create.c +++ b/common_smp/src/txe_queue_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,14 +71,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_queue_create(TX_QUEUE *queue_ptr, CHAR *name_ptr, UINT message_size, VOID *queue_start, ULONG queue_size, UINT queue_control_block_size) diff --git a/common_smp/src/txe_queue_delete.c b/common_smp/src/txe_queue_delete.c index 3062edeb..43dc9d6f 100644 --- a/common_smp/src/txe_queue_delete.c +++ b/common_smp/src/txe_queue_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_queue_delete(TX_QUEUE *queue_ptr) { diff --git a/common_smp/src/txe_queue_flush.c b/common_smp/src/txe_queue_flush.c index 348de23e..b514db95 100644 --- a/common_smp/src/txe_queue_flush.c +++ b/common_smp/src/txe_queue_flush.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,14 +61,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_queue_flush(TX_QUEUE *queue_ptr) { diff --git a/common_smp/src/txe_queue_front_send.c b/common_smp/src/txe_queue_front_send.c index 21c254ab..798aada6 100644 --- a/common_smp/src/txe_queue_front_send.c +++ b/common_smp/src/txe_queue_front_send.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_queue_front_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option) { diff --git a/common_smp/src/txe_queue_info_get.c b/common_smp/src/txe_queue_info_get.c index b4507b01..78d98392 100644 --- a/common_smp/src/txe_queue_info_get.c +++ b/common_smp/src/txe_queue_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,14 +69,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_queue_info_get(TX_QUEUE *queue_ptr, CHAR **name, ULONG *enqueued, ULONG *available_storage, TX_THREAD **first_suspended, ULONG *suspended_count, TX_QUEUE **next_queue) diff --git a/common_smp/src/txe_queue_prioritize.c b/common_smp/src/txe_queue_prioritize.c index f74809a1..ba40b02a 100644 --- a/common_smp/src/txe_queue_prioritize.c +++ b/common_smp/src/txe_queue_prioritize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_queue_prioritize(TX_QUEUE *queue_ptr) { diff --git a/common_smp/src/txe_queue_receive.c b/common_smp/src/txe_queue_receive.c index b40e6a56..de6f4dcd 100644 --- a/common_smp/src/txe_queue_receive.c +++ b/common_smp/src/txe_queue_receive.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,14 +68,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_queue_receive(TX_QUEUE *queue_ptr, VOID *destination_ptr, ULONG wait_option) { diff --git a/common_smp/src/txe_queue_send.c b/common_smp/src/txe_queue_send.c index 5873f025..1b752e75 100644 --- a/common_smp/src/txe_queue_send.c +++ b/common_smp/src/txe_queue_send.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_queue_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option) { diff --git a/common_smp/src/txe_queue_send_notify.c b/common_smp/src/txe_queue_send_notify.c index 9ffb0a93..dd2beaf2 100644 --- a/common_smp/src/txe_queue_send_notify.c +++ b/common_smp/src/txe_queue_send_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_queue_send_notify(TX_QUEUE *queue_ptr, VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)) { diff --git a/common_smp/src/txe_semaphore_ceiling_put.c b/common_smp/src/txe_semaphore_ceiling_put.c index 51fee9d7..4c8b4603 100644 --- a/common_smp/src/txe_semaphore_ceiling_put.c +++ b/common_smp/src/txe_semaphore_ceiling_put.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_semaphore_ceiling_put(TX_SEMAPHORE *semaphore_ptr, ULONG ceiling) { diff --git a/common_smp/src/txe_semaphore_create.c b/common_smp/src/txe_semaphore_create.c index 3390491c..a190b03c 100644 --- a/common_smp/src/txe_semaphore_create.c +++ b/common_smp/src/txe_semaphore_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,14 +69,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_semaphore_create(TX_SEMAPHORE *semaphore_ptr, CHAR *name_ptr, ULONG initial_count, UINT semaphore_control_block_size) { diff --git a/common_smp/src/txe_semaphore_delete.c b/common_smp/src/txe_semaphore_delete.c index 2083a22a..3d9f366c 100644 --- a/common_smp/src/txe_semaphore_delete.c +++ b/common_smp/src/txe_semaphore_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_semaphore_delete(TX_SEMAPHORE *semaphore_ptr) { diff --git a/common_smp/src/txe_semaphore_get.c b/common_smp/src/txe_semaphore_get.c index 403d43b4..7b92d317 100644 --- a/common_smp/src/txe_semaphore_get.c +++ b/common_smp/src/txe_semaphore_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,14 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_semaphore_get(TX_SEMAPHORE *semaphore_ptr, ULONG wait_option) { diff --git a/common_smp/src/txe_semaphore_info_get.c b/common_smp/src/txe_semaphore_info_get.c index 142bad37..7695028e 100644 --- a/common_smp/src/txe_semaphore_info_get.c +++ b/common_smp/src/txe_semaphore_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,14 +69,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_semaphore_info_get(TX_SEMAPHORE *semaphore_ptr, CHAR **name, ULONG *current_value, TX_THREAD **first_suspended, ULONG *suspended_count, diff --git a/common_smp/src/txe_semaphore_prioritize.c b/common_smp/src/txe_semaphore_prioritize.c index 52525ded..cd873c5a 100644 --- a/common_smp/src/txe_semaphore_prioritize.c +++ b/common_smp/src/txe_semaphore_prioritize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_semaphore_prioritize(TX_SEMAPHORE *semaphore_ptr) { diff --git a/common_smp/src/txe_semaphore_put.c b/common_smp/src/txe_semaphore_put.c index 4a26fbd8..452c39bd 100644 --- a/common_smp/src/txe_semaphore_put.c +++ b/common_smp/src/txe_semaphore_put.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_semaphore_put(TX_SEMAPHORE *semaphore_ptr) { diff --git a/common_smp/src/txe_semaphore_put_notify.c b/common_smp/src/txe_semaphore_put_notify.c index 646c293a..33aa8d9a 100644 --- a/common_smp/src/txe_semaphore_put_notify.c +++ b/common_smp/src/txe_semaphore_put_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_semaphore_put_notify(TX_SEMAPHORE *semaphore_ptr, VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)) { diff --git a/common_smp/src/txe_thread_create.c b/common_smp/src/txe_thread_create.c index c3902cd1..d319bc9e 100644 --- a/common_smp/src/txe_thread_create.c +++ b/common_smp/src/txe_thread_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -77,14 +78,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr, VOID (*entry_function)(ULONG id), ULONG entry_input, diff --git a/common_smp/src/txe_thread_delete.c b/common_smp/src/txe_thread_delete.c index 6e2d1d2b..85cf31ca 100644 --- a/common_smp/src/txe_thread_delete.c +++ b/common_smp/src/txe_thread_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,14 +61,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_delete(TX_THREAD *thread_ptr) { diff --git a/common_smp/src/txe_thread_entry_exit_notify.c b/common_smp/src/txe_thread_entry_exit_notify.c index ab4e835d..33420683 100644 --- a/common_smp/src/txe_thread_entry_exit_notify.c +++ b/common_smp/src/txe_thread_entry_exit_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_entry_exit_notify(TX_THREAD *thread_ptr, VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT type)) { diff --git a/common_smp/src/txe_thread_info_get.c b/common_smp/src/txe_thread_info_get.c index 17f9155d..ad1db3f7 100644 --- a/common_smp/src/txe_thread_info_get.c +++ b/common_smp/src/txe_thread_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,14 +73,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_info_get(TX_THREAD *thread_ptr, CHAR **name, UINT *state, ULONG *run_count, UINT *priority, UINT *preemption_threshold, ULONG *time_slice, diff --git a/common_smp/src/txe_thread_preemption_change.c b/common_smp/src/txe_thread_preemption_change.c index c0cfa91e..e3de0a85 100644 --- a/common_smp/src/txe_thread_preemption_change.c +++ b/common_smp/src/txe_thread_preemption_change.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_preemption_change(TX_THREAD *thread_ptr, UINT new_threshold, UINT *old_threshold) { diff --git a/common_smp/src/txe_thread_priority_change.c b/common_smp/src/txe_thread_priority_change.c index b4a1224b..2bf0058b 100644 --- a/common_smp/src/txe_thread_priority_change.c +++ b/common_smp/src/txe_thread_priority_change.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_priority_change(TX_THREAD *thread_ptr, UINT new_priority, UINT *old_priority) { diff --git a/common_smp/src/txe_thread_relinquish.c b/common_smp/src/txe_thread_relinquish.c index 1c5ab21a..080bad47 100644 --- a/common_smp/src/txe_thread_relinquish.c +++ b/common_smp/src/txe_thread_relinquish.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ VOID _txe_thread_relinquish(VOID) { diff --git a/common_smp/src/txe_thread_reset.c b/common_smp/src/txe_thread_reset.c index 4fed5e7a..1815f5bb 100644 --- a/common_smp/src/txe_thread_reset.c +++ b/common_smp/src/txe_thread_reset.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_reset(TX_THREAD *thread_ptr) { diff --git a/common_smp/src/txe_thread_resume.c b/common_smp/src/txe_thread_resume.c index e8a341dd..ae356c6c 100644 --- a/common_smp/src/txe_thread_resume.c +++ b/common_smp/src/txe_thread_resume.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_resume(TX_THREAD *thread_ptr) { diff --git a/common_smp/src/txe_thread_suspend.c b/common_smp/src/txe_thread_suspend.c index 951d35eb..dab42db7 100644 --- a/common_smp/src/txe_thread_suspend.c +++ b/common_smp/src/txe_thread_suspend.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_suspend(TX_THREAD *thread_ptr) { diff --git a/common_smp/src/txe_thread_terminate.c b/common_smp/src/txe_thread_terminate.c index aa54501c..8e1f18f5 100644 --- a/common_smp/src/txe_thread_terminate.c +++ b/common_smp/src/txe_thread_terminate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_terminate(TX_THREAD *thread_ptr) { diff --git a/common_smp/src/txe_thread_time_slice_change.c b/common_smp/src/txe_thread_time_slice_change.c index d01137d8..456dbb2a 100644 --- a/common_smp/src/txe_thread_time_slice_change.c +++ b/common_smp/src/txe_thread_time_slice_change.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,14 +65,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_time_slice_change(TX_THREAD *thread_ptr, ULONG new_time_slice, ULONG *old_time_slice) { diff --git a/common_smp/src/txe_thread_wait_abort.c b/common_smp/src/txe_thread_wait_abort.c index 8132c597..086fb33b 100644 --- a/common_smp/src/txe_thread_wait_abort.c +++ b/common_smp/src/txe_thread_wait_abort.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_wait_abort(TX_THREAD *thread_ptr) { diff --git a/common_smp/src/txe_timer_activate.c b/common_smp/src/txe_timer_activate.c index 9bd62341..094eda85 100644 --- a/common_smp/src/txe_timer_activate.c +++ b/common_smp/src/txe_timer_activate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_timer_activate(TX_TIMER *timer_ptr) { diff --git a/common_smp/src/txe_timer_change.c b/common_smp/src/txe_timer_change.c index 70a7ed0d..ef503ffa 100644 --- a/common_smp/src/txe_timer_change.c +++ b/common_smp/src/txe_timer_change.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,14 +67,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_timer_change(TX_TIMER *timer_ptr, ULONG initial_ticks, ULONG reschedule_ticks) { diff --git a/common_smp/src/txe_timer_create.c b/common_smp/src/txe_timer_create.c index 553418bf..02cf7c1a 100644 --- a/common_smp/src/txe_timer_create.c +++ b/common_smp/src/txe_timer_create.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,14 +73,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_timer_create(TX_TIMER *timer_ptr, CHAR *name_ptr, VOID (*expiration_function)(ULONG id), ULONG expiration_input, diff --git a/common_smp/src/txe_timer_deactivate.c b/common_smp/src/txe_timer_deactivate.c index a5736919..d44ba67b 100644 --- a/common_smp/src/txe_timer_deactivate.c +++ b/common_smp/src/txe_timer_deactivate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,14 +61,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_timer_deactivate(TX_TIMER *timer_ptr) { diff --git a/common_smp/src/txe_timer_delete.c b/common_smp/src/txe_timer_delete.c index 3a1bf33c..e94ba4d6 100644 --- a/common_smp/src/txe_timer_delete.c +++ b/common_smp/src/txe_timer_delete.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_timer_delete(TX_TIMER *timer_ptr) { diff --git a/common_smp/src/txe_timer_info_get.c b/common_smp/src/txe_timer_info_get.c index a227f137..16ac5f64 100644 --- a/common_smp/src/txe_timer_info_get.c +++ b/common_smp/src/txe_timer_info_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,14 +68,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_timer_info_get(TX_TIMER *timer_ptr, CHAR **name, UINT *active, ULONG *remaining_ticks, ULONG *reschedule_ticks, TX_TIMER **next_timer) diff --git a/ports/arc_em/metaware/example_build/sample_threadx/sample_threadx.c b/ports/arc_em/metaware/example_build/sample_threadx/sample_threadx.c index 5a03f35c..6ce6e0d4 100644 --- a/ports/arc_em/metaware/example_build/sample_threadx/sample_threadx.c +++ b/ports/arc_em/metaware/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -82,41 +82,41 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -124,23 +124,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -243,11 +243,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -306,7 +306,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -359,7 +359,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/arc_em/metaware/example_build/sample_threadx/sample_threadx.cmd b/ports/arc_em/metaware/example_build/sample_threadx/sample_threadx.cmd index 78dc1f6e..2f72e865 100644 --- a/ports/arc_em/metaware/example_build/sample_threadx/sample_threadx.cmd +++ b/ports/arc_em/metaware/example_build/sample_threadx/sample_threadx.cmd @@ -1,24 +1,24 @@ // // This is the linker script example (SRV3-style). // (c) Synopsys, 2013 -// +// // -//number of exceptions and interrupts +//number of exceptions and interrupts NUMBER_OF_EXCEPTIONS = 16;//it is fixed (16) NUMBER_OF_INTERRUPTS = 5;//depends on HW configuration //define Interrupt Vector Table size IVT_SIZE_ITEMS = (NUMBER_OF_EXCEPTIONS + NUMBER_OF_INTERRUPTS);//the total IVT size (in "items") -IVT_SIZE_BYTES = IVT_SIZE_ITEMS * 4;//in bytes +IVT_SIZE_BYTES = IVT_SIZE_ITEMS * 4;//in bytes //define ICCM and DCCM locations MEMORY { ICCM: ORIGIN = 0x00000000, LENGTH = 128K DCCM: ORIGIN = 0x80000000, LENGTH = 128K } - -//define sections and groups + +//define sections and groups SECTIONS { GROUP: { .ivt (TEXT) : # Interrupt table @@ -26,18 +26,18 @@ SECTIONS { ___ivt1 = .; * (.ivt) ___ivt2 = .; - // Make the IVT at least IVT_SIZE_BYTES + // Make the IVT at least IVT_SIZE_BYTES . += (___ivt2 - ___ivt1 < IVT_SIZE_BYTES) ? (IVT_SIZE_BYTES - (___ivt2 - ___ivt1)) : 0; } .ivh (TEXT) : // Interrupt handlers - + //TEXT sections .text? : { *('.text$crt*') } * (TEXT): {} //Literals * (LIT): {} } > ICCM - + GROUP: { //data sections .sdata?: {} diff --git a/ports/arc_em/metaware/example_build/sample_threadx/tx_initialize_low_level.s b/ports/arc_em/metaware/example_build/sample_threadx/tx_initialize_low_level.s index cf55e8db..07da0899 100644 --- a/ports/arc_em/metaware/example_build/sample_threadx/tx_initialize_low_level.s +++ b/ports/arc_em/metaware/example_build/sample_threadx/tx_initialize_low_level.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ @@ -88,20 +88,6 @@ _tx_system_stack_base_address: ;/* */ ;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 Andres Mlinar Modified comment(s), optimized*/ -;/* system stack usage, */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 Andres Mlinar Modified comments(s), */ -;/* initialize interrupts right */ -;/* before enabling the task */ -;/* scheduler, */ -;/* resulting in version 6.1.10 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) ;{ diff --git a/ports/arc_em/metaware/example_build/sample_threadx/vectors.s b/ports/arc_em/metaware/example_build/sample_threadx/vectors.s index c6cbc893..eeb9ba2a 100644 --- a/ports/arc_em/metaware/example_build/sample_threadx/vectors.s +++ b/ports/arc_em/metaware/example_build/sample_threadx/vectors.s @@ -1,4 +1,4 @@ - + .file "vectors.s" .section .ivt,text ;; This directive forces this section to stay resident even if stripped out by the -zpurgetext linker option diff --git a/ports/arc_em/metaware/inc/tx_port.h b/ports/arc_em/metaware/inc/tx_port.h index 63c90b6e..34ca8019 100644 --- a/ports/arc_em/metaware/inc/tx_port.h +++ b/ports/arc_em/metaware/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,29 +43,15 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s), updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 01-31-2022 Andres Mlinar Modified comments(s), */ -/* initialize interrupts right */ -/* before enabling the task */ -/* scheduler, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H #define TX_PORT_H -/* Remove volatile for ThreadX source on the ARC. This is because the ARC - compiler generates different non-cache r/w access when using volatile - that is different from the assembly language access of the same +/* Remove volatile for ThreadX source on the ARC. This is because the ARC + compiler generates different non-cache r/w access when using volatile + that is different from the assembly language access of the same global variables in ThreadX. */ #ifdef TX_SOURCE_CODE @@ -89,7 +76,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -102,7 +89,7 @@ #include -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -138,8 +125,8 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 2048 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -149,8 +136,8 @@ typedef unsigned short USHORT; #define TX_INT_DISABLE_MASK 0x00000000 /* Disable all interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -195,7 +182,7 @@ void _tx_initialize_start_interrupts(void); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION _tx_initialize_start_interrupts(); -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -209,15 +196,15 @@ void _tx_initialize_start_interrupts(void); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ #define TX_THREAD_EXTENSION_0 VOID *__mw_threadx_tls; \ int __mw_errnum; \ VOID (*__mw_thread_exit)(struct TX_THREAD_STRUCT *); -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -231,11 +218,11 @@ void _tx_initialize_start_interrupts(void); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -244,16 +231,16 @@ void _tx_initialize_start_interrupts(void); #if __HIGHC__ -/* The MetaWare thread safe C/C++ runtime library needs space to +/* The MetaWare thread safe C/C++ runtime library needs space to store thread specific information. In addition, a function pointer - is also supplied so that certain thread-specific resources may be + is also supplied so that certain thread-specific resources may be released upon thread termination and/or thread completion. */ #define TX_THREAD_CREATE_EXTENSION(thread_ptr) \ thread_ptr -> __mw_threadx_tls = 0; \ thread_ptr -> __mw_errnum = 0; \ - thread_ptr -> __mw_thread_exit = TX_NULL; -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) + thread_ptr -> __mw_thread_exit = TX_NULL; +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) \ if (thread_ptr -> __mw_thread_exit) \ (thread_ptr -> __mw_thread_exit) (thread_ptr); @@ -263,10 +250,10 @@ void _tx_initialize_start_interrupts(void); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) -#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) -#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) #endif @@ -293,9 +280,9 @@ void _tx_initialize_start_interrupts(void); #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -320,8 +307,8 @@ void _tx_initialize_start_interrupts(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARCv2_EM/MetaWare Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARCv2_EM/MetaWare Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/arc_em/metaware/readme_threadx.txt b/ports/arc_em/metaware/readme_threadx.txt index d622eeec..d14f7865 100644 --- a/ports/arc_em/metaware/readme_threadx.txt +++ b/ports/arc_em/metaware/readme_threadx.txt @@ -2,70 +2,70 @@ Using the MetaWare Tools -1. Open the Eclipse ThreadX RTOS Workspace +1. Open the Eclipse ThreadX RTOS Workspace -In order to build the ThreadX library and the ThreadX demonstration first load -the Eclipse ThreadX RTOS Workspace, which is located inside the "example_build" directory. +In order to build the ThreadX library and the ThreadX demonstration first load +the Eclipse ThreadX RTOS Workspace, which is located inside the "example_build" directory. 2. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply select the ThreadX library project -file "tx" and then select the build button. You should now observe the compilation -and assembly of the ThreadX library. This project build produces the ThreadX +Building the ThreadX library is easy; simply select the ThreadX library project +file "tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. 3. Demonstration System The ThreadX demonstration is designed to execute under the MetaWare ARCv2 EM -simulation. The instructions that follow describe how to get the ThreadX -demonstration running. +simulation. The instructions that follow describe how to get the ThreadX +demonstration running. -Building the demonstration is easy; simply select the demonstration project file -"sample_threadx." At this point, select the build button and observe the -compilation, assembly, and linkage of the ThreadX demonstration application. +Building the demonstration is easy; simply select the demonstration project file +"sample_threadx." At this point, select the build button and observe the +compilation, assembly, and linkage of the ThreadX demonstration application. After the demonstration is built, click on the "Debug" button and it will automatically launch a pre-configured connection to the ARCv2 EM simulator. -You are now ready to execute the ThreadX demonstration system. Select -breakpoints and data watches to observe the execution of the sample_threadx.c +You are now ready to execute the ThreadX demonstration system. Select +breakpoints and data watches to observe the execution of the sample_threadx.c application. 4. System Initialization -The system entry point using the MetaWare tools is at the label _start. -This is defined within the crt1.s file supplied by MetaWare. In addition, +The system entry point using the MetaWare tools is at the label _start. +This is defined within the crt1.s file supplied by MetaWare. In addition, this is where all static and global preset C variable initialization processing is called from. After the MetaWare startup function completes, ThreadX initialization is called. The main initialization function is _tx_initialize_low_level and -is located in the file tx_initialize_low_level.s. This function is -responsible for setting up various system data structures, and interrupt +is located in the file tx_initialize_low_level.s. This function is +responsible for setting up various system data structures, and interrupt vectors. -By default free memory is assumed to start at the section .free_memory -which is referenced in tx_initialize_low_level.s and located in the -linker control file after all the linker defined RAM addresses. This is +By default free memory is assumed to start at the section .free_memory +which is referenced in tx_initialize_low_level.s and located in the +linker control file after all the linker defined RAM addresses. This is the address passed to the application definition function, tx_application_define. 5. Register Usage and Stack Frames -The ARC compiler assumes that registers r0-r12 are scratch registers for -each function. All other registers used by a C function must be preserved -by the function. ThreadX takes advantage of this in situations where a -context switch happens as a result of making a ThreadX service call (which -is itself a C function). In such cases, the saved context of a thread is +The ARC compiler assumes that registers r0-r12 are scratch registers for +each function. All other registers used by a C function must be preserved +by the function. ThreadX takes advantage of this in situations where a +context switch happens as a result of making a ThreadX service call (which +is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -114,20 +114,20 @@ associated thread control block TX_THREAD. 0x9C bta 0xA0 point of interrupt 0xA4 STATUS32 - + 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make it run faster, you can change the build_threadx.bat -file to remove the -g option and enable all compiler optimizations. +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat +file to remove the -g option and enable all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling @@ -142,25 +142,25 @@ _tx_interrupt_x: st blink, [sp, 16] ; Save blink (blink must be saved before _tx_thread_context_save) bl _tx_thread_context_save ; Save interrupt context ; -; /* Application ISR processing goes here! Your ISR can be written in +; /* Application ISR processing goes here! Your ISR can be written in ; assembly language or in C. If it is written in C, you must allocate -; 16 bytes of stack space before it is called. This must also be -; recovered once your C ISR return. An example of this is shown below. +; 16 bytes of stack space before it is called. This must also be +; recovered once your C ISR return. An example of this is shown below. ; ; If the ISR is written in assembly language, only the compiler scratch -; registers are available for use without saving/restoring (r0-r12). +; registers are available for use without saving/restoring (r0-r12). ; If use of additional registers are required they must be saved and ; restored. */ ; bl.d your_ISR_written_in_C ; Call an ISR written in C sub sp, sp, 16 ; Allocate stack space (delay slot) add sp, sp, 16 ; Recover stack space - + ; b _tx_thread_context_restore ; Restore interrupt context -The application handles interrupts directly, which necessitates all register +The application handles interrupts directly, which necessitates all register preservation by the application's ISR. ISRs that do not use the ThreadX _tx_thread_context_save and _tx_thread_context_restore routines are not allowed access to the ThreadX API. In addition, custom application ISRs @@ -169,28 +169,28 @@ should be higher priority than all ThreadX-managed ISRs. 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer -interrupt source, these services are not functional but the remainder of +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of ThreadX will still run. By default, the ThreadX timer interrupt is mapped to the ARCv2 EM auxiliary timer 0, which generates low priority interrupts on interrupt vector 16. -It is easy to change the timer interrupt source and priority by changing the +It is easy to change the timer interrupt source and priority by changing the setup code in tx_initialize_low_level.s. 9. Hardware Stack Checking ThreadX optionally supports the ARCv2 EM hardware stack checking feature. When enabled, -the KSTACK_TOP and KSTACK_BASE registers are loaded with the stack top/bottom before +the KSTACK_TOP and KSTACK_BASE registers are loaded with the stack top/bottom before each thread's execution. In addition, the SC bit of STATUS32 is set to enable the stack checking feature. During initialization, idle, or interrupt processing, the hardware stack checking on the system stack is performed, when enabled. To enable ThreadX support for hardware stack checking, simply build the ThreadX library and application assembly code with TX_ENABLE_HW_STACK_CHECKING defined. This will enable -the stack checking logic in ThreadX. +the stack checking logic in ThreadX. For the system stack checking to function properly, there are two sections that must be located around the .stack section, which defines the system stack location and size. @@ -198,8 +198,8 @@ The new sections are .stack_top and .stack_base. The .stack_top section should b immediately BEFORE the .stack section and .stack_base should be placed immediately AFTER the .stack section. Please see the sample_threadx.cmd linker control file for an example. -When/if a stack exception occurs, the hardware will fetch the _tx_ev_protection_viol -exception defined in tx_initialize_low_level.s. Processing for this exception is +When/if a stack exception occurs, the hardware will fetch the _tx_ev_protection_viol +exception defined in tx_initialize_low_level.s. Processing for this exception is application specific. @@ -215,12 +215,12 @@ information associated with this specific port of ThreadX: tx_thread_context_restore.s r25/r30 are caller saved tx_thread_context_save.s r25/r30 are caller saved tx_thread_interrupt_control.s Modified comments - tx_thread_schedule.s fixed interrupt priority overwritting bug, + tx_thread_schedule.s fixed interrupt priority overwritting bug, and fixed hardware stack checker disable and reenable logic tx_thread_stack_build.s Modified comments tx_thread_system_return.s Modified comments tx_timer_interrupt.s remove unneeded load of _tx_thread_preempt_disable - + 09-30-2020 Initial ThreadX 6.1 for ARCv2 EM using MetaWare tools. diff --git a/ports/arc_em/metaware/src/tx_thread_context_restore.s b/ports/arc_em/metaware/src/tx_thread_context_restore.s index 7e1bb8bb..e39c3e2f 100644 --- a/ports/arc_em/metaware/src/tx_thread_context_restore.s +++ b/ports/arc_em/metaware/src/tx_thread_context_restore.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ @@ -59,22 +59,6 @@ ;/* */ ;/* ISRs Interrupt Service Routines */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 04-02-2021 Andres Mlinar Modified comment(s), and */ -;/* r25/r30 are caller saved, */ -;/* resulting in version 6.1.6 */ -;/* 10-15-2021 Andres Mlinar Modified comment(s), added */ -;/* support for disabling the */ -;/* loop control feature, */ -;/* resulting in version 6.1.9 */ -;/* 03-08-2023 Cindy Deng Modified comment(s), added */ -;/* #include tx_user.h, */ -;/* resulting in version 6.2.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) ;{ diff --git a/ports/arc_em/metaware/src/tx_thread_context_save.s b/ports/arc_em/metaware/src/tx_thread_context_save.s index 57013da2..fb2a280c 100644 --- a/ports/arc_em/metaware/src/tx_thread_context_save.s +++ b/ports/arc_em/metaware/src/tx_thread_context_save.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ @@ -58,18 +58,6 @@ ;/* */ ;/* ISRs */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 04-02-2021 Andres Mlinar Modified comment(s), and */ -;/* r25/r30 are caller saved, */ -;/* resulting in version 6.1.6 */ -;/* 03-08-2023 Cindy Deng Modified comment(s), added */ -;/* #include tx_user.h, */ -;/* resulting in version 6.2.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) ;{ diff --git a/ports/arc_em/metaware/src/tx_thread_interrupt_control.s b/ports/arc_em/metaware/src/tx_thread_interrupt_control.s index 6cca4ec7..b6d26148 100644 --- a/ports/arc_em/metaware/src/tx_thread_interrupt_control.s +++ b/ports/arc_em/metaware/src/tx_thread_interrupt_control.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ @@ -52,17 +52,6 @@ ;/* */ ;/* Application Code */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 04-02-2021 Andres Mlinar Modified comments, */ -;/* resulting in version 6.1.6 */ -;/* 03-08-2023 Cindy Deng Modified comment(s), added */ -;/* #include tx_user.h, */ -;/* resulting in version 6.2.1 */ -;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) ;{ diff --git a/ports/arc_em/metaware/src/tx_thread_schedule.s b/ports/arc_em/metaware/src/tx_thread_schedule.s index 583adae1..0e1a035c 100644 --- a/ports/arc_em/metaware/src/tx_thread_schedule.s +++ b/ports/arc_em/metaware/src/tx_thread_schedule.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ @@ -60,23 +60,6 @@ ;/* _tx_thread_system_return Return to system from thread */ ;/* _tx_thread_context_restore Restore thread's context */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 04-02-2021 Andres Mlinar Modified comment(s), and */ -;/* fixed interrupt priority */ -;/* overwritting bug, and */ -;/* fixed hardware stack checker*/ -;/* disable and reenable logic, */ -;/* resulting in version 6.1.6 */ -;/* 10-15-2021 Andres Mlinar Modified comment(s), added */ -;/* support for disabling the */ -;/* loop control feature, */ -;/* improved internal logic, */ -;/* resulting in version 6.1.9 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) ;{ diff --git a/ports/arc_em/metaware/src/tx_thread_stack_build.s b/ports/arc_em/metaware/src/tx_thread_stack_build.s index 9eaf86b5..3fc2e0e5 100644 --- a/ports/arc_em/metaware/src/tx_thread_stack_build.s +++ b/ports/arc_em/metaware/src/tx_thread_stack_build.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ @@ -57,17 +57,6 @@ ;/* */ ;/* _tx_thread_create Create thread service */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 04-02-2021 Andres Mlinar Modified comments, */ -;/* resulting in version 6.1.6 */ -;/* 03-08-2023 Cindy Deng Modified comment(s), added */ -;/* #include tx_user.h, */ -;/* resulting in version 6.2.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) ;{ diff --git a/ports/arc_em/metaware/src/tx_thread_system_return.s b/ports/arc_em/metaware/src/tx_thread_system_return.s index b08e87da..83321a45 100644 --- a/ports/arc_em/metaware/src/tx_thread_system_return.s +++ b/ports/arc_em/metaware/src/tx_thread_system_return.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ @@ -58,20 +58,6 @@ ;/* */ ;/* ThreadX components */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 04-02-2021 Andres Mlinar Modified comments, */ -;/* resulting in version 6.1.6 */ -;/* 10-15-2021 Andres Mlinar Modified comments, */ -;/* use schedule reenter, */ -;/* resulting in version 6.1.9 */ -;/* 03-08-2023 Cindy Deng Modified comment(s), added */ -;/* #include tx_user.h, */ -;/* resulting in version 6.2.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) ;{ diff --git a/ports/arc_em/metaware/src/tx_timer_interrupt.s b/ports/arc_em/metaware/src/tx_timer_interrupt.s index 003260a8..30941cb0 100644 --- a/ports/arc_em/metaware/src/tx_timer_interrupt.s +++ b/ports/arc_em/metaware/src/tx_timer_interrupt.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ @@ -58,23 +58,6 @@ ;/* */ ;/* interrupt vector */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 12-31-2020 Scott Larson Modified comment(s), remove */ -;/* unneeded load of */ -;/* _tx_thread_preempt_disable, */ -;/* resulting in version 6.1.3 */ -;/* 10-15-2021 Andres Mlinar Modified comment(s), and */ -;/* fixed possible race */ -;/* condition on preemption */ -;/* resulting in version 6.1.9 */ -;/* 03-08-2023 Cindy Deng Modified comment(s), added */ -;/* #include tx_user.h, */ -;/* resulting in version 6.2.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) ;{ diff --git a/ports/arc_hs/metaware/example_build/sample_threadx/sample_threadx.c b/ports/arc_hs/metaware/example_build/sample_threadx/sample_threadx.c index 81cca72b..6ce6e0d4 100644 --- a/ports/arc_hs/metaware/example_build/sample_threadx/sample_threadx.c +++ b/ports/arc_hs/metaware/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -83,40 +83,40 @@ CHAR *pointer = TX_NULL; /* Create the main thread. */ tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -124,23 +124,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -243,11 +243,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -306,7 +306,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -359,7 +359,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/arc_hs/metaware/example_build/sample_threadx/sample_threadx.cmd b/ports/arc_hs/metaware/example_build/sample_threadx/sample_threadx.cmd index 78dc1f6e..2f72e865 100644 --- a/ports/arc_hs/metaware/example_build/sample_threadx/sample_threadx.cmd +++ b/ports/arc_hs/metaware/example_build/sample_threadx/sample_threadx.cmd @@ -1,24 +1,24 @@ // // This is the linker script example (SRV3-style). // (c) Synopsys, 2013 -// +// // -//number of exceptions and interrupts +//number of exceptions and interrupts NUMBER_OF_EXCEPTIONS = 16;//it is fixed (16) NUMBER_OF_INTERRUPTS = 5;//depends on HW configuration //define Interrupt Vector Table size IVT_SIZE_ITEMS = (NUMBER_OF_EXCEPTIONS + NUMBER_OF_INTERRUPTS);//the total IVT size (in "items") -IVT_SIZE_BYTES = IVT_SIZE_ITEMS * 4;//in bytes +IVT_SIZE_BYTES = IVT_SIZE_ITEMS * 4;//in bytes //define ICCM and DCCM locations MEMORY { ICCM: ORIGIN = 0x00000000, LENGTH = 128K DCCM: ORIGIN = 0x80000000, LENGTH = 128K } - -//define sections and groups + +//define sections and groups SECTIONS { GROUP: { .ivt (TEXT) : # Interrupt table @@ -26,18 +26,18 @@ SECTIONS { ___ivt1 = .; * (.ivt) ___ivt2 = .; - // Make the IVT at least IVT_SIZE_BYTES + // Make the IVT at least IVT_SIZE_BYTES . += (___ivt2 - ___ivt1 < IVT_SIZE_BYTES) ? (IVT_SIZE_BYTES - (___ivt2 - ___ivt1)) : 0; } .ivh (TEXT) : // Interrupt handlers - + //TEXT sections .text? : { *('.text$crt*') } * (TEXT): {} //Literals * (LIT): {} } > ICCM - + GROUP: { //data sections .sdata?: {} diff --git a/ports/arc_hs/metaware/example_build/sample_threadx/tx_initialize_low_level.s b/ports/arc_hs/metaware/example_build/sample_threadx/tx_initialize_low_level.s index 56ef5840..9d583370 100644 --- a/ports/arc_hs/metaware/example_build/sample_threadx/tx_initialize_low_level.s +++ b/ports/arc_hs/metaware/example_build/sample_threadx/tx_initialize_low_level.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ @@ -67,20 +67,6 @@ _tx_first_free_address: ;/* */ ;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 Andres Mlinar Modified comment(s), optimized*/ -;/* system stack usage, */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 Andres Mlinar Modified comments(s), */ -;/* initialize interrupts right */ -;/* before enabling the task */ -;/* scheduler, */ -;/* resulting in version 6.1.10 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) ;{ diff --git a/ports/arc_hs/metaware/example_build/sample_threadx/vectors.s b/ports/arc_hs/metaware/example_build/sample_threadx/vectors.s index c6cbc893..eeb9ba2a 100644 --- a/ports/arc_hs/metaware/example_build/sample_threadx/vectors.s +++ b/ports/arc_hs/metaware/example_build/sample_threadx/vectors.s @@ -1,4 +1,4 @@ - + .file "vectors.s" .section .ivt,text ;; This directive forces this section to stay resident even if stripped out by the -zpurgetext linker option diff --git a/ports/arc_hs/metaware/inc/tx_port.h b/ports/arc_hs/metaware/inc/tx_port.h index 1400ded7..7c5dc6de 100644 --- a/ports/arc_hs/metaware/inc/tx_port.h +++ b/ports/arc_hs/metaware/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,29 +43,15 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s), updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 01-31-2022 Andres Mlinar Modified comments(s), */ -/* initialize interrupts right */ -/* before enabling the task */ -/* scheduler, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H #define TX_PORT_H -/* Remove volatile for ThreadX source on the ARC. This is because the ARC - compiler generates different non-cache r/w access when using volatile - that is different from the assembly language access of the same +/* Remove volatile for ThreadX source on the ARC. This is because the ARC + compiler generates different non-cache r/w access when using volatile + that is different from the assembly language access of the same global variables in ThreadX. */ #ifdef TX_SOURCE_CODE @@ -89,7 +76,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -102,7 +89,7 @@ #include -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -138,8 +125,8 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 2048 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -149,8 +136,8 @@ typedef unsigned short USHORT; #define TX_INT_DISABLE_MASK 0x00000000 /* Disable all interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -195,7 +182,7 @@ void _tx_initialize_start_interrupts(void); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION _tx_initialize_start_interrupts(); -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -209,15 +196,15 @@ void _tx_initialize_start_interrupts(void); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ #define TX_THREAD_EXTENSION_0 VOID *__mw_threadx_tls; \ int __mw_errnum; \ VOID (*__mw_thread_exit)(struct TX_THREAD_STRUCT *); -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -231,11 +218,11 @@ void _tx_initialize_start_interrupts(void); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -244,16 +231,16 @@ void _tx_initialize_start_interrupts(void); #if __HIGHC__ -/* The MetaWare thread safe C/C++ runtime library needs space to +/* The MetaWare thread safe C/C++ runtime library needs space to store thread specific information. In addition, a function pointer - is also supplied so that certain thread-specific resources may be + is also supplied so that certain thread-specific resources may be released upon thread termination and/or thread completion. */ #define TX_THREAD_CREATE_EXTENSION(thread_ptr) \ thread_ptr -> __mw_threadx_tls = 0; \ thread_ptr -> __mw_errnum = 0; \ - thread_ptr -> __mw_thread_exit = TX_NULL; -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) + thread_ptr -> __mw_thread_exit = TX_NULL; +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) \ if (thread_ptr -> __mw_thread_exit) \ (thread_ptr -> __mw_thread_exit) (thread_ptr); @@ -263,10 +250,10 @@ void _tx_initialize_start_interrupts(void); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) -#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) -#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) #endif @@ -293,9 +280,9 @@ void _tx_initialize_start_interrupts(void); #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -334,8 +321,8 @@ VOID tx_thread_register_bank_assign(VOID *thread_ptr, UINT register_bank); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARC_HS/MetaWare Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARC_HS/MetaWare Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/arc_hs/metaware/readme_threadx.txt b/ports/arc_hs/metaware/readme_threadx.txt index c763b850..506d89cc 100644 --- a/ports/arc_hs/metaware/readme_threadx.txt +++ b/ports/arc_hs/metaware/readme_threadx.txt @@ -2,70 +2,70 @@ Using the MetaWare Tools -1. Open the Azure RTOS Workspace +1. Open the Azure RTOS Workspace -In order to build the ThreadX library and the ThreadX demonstration first load -the Azure RTOS Workspace, which is located inside the "example_build" directory. +In order to build the ThreadX library and the ThreadX demonstration first load +the Azure RTOS Workspace, which is located inside the "example_build" directory. 2. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply select the ThreadX library project -file "tx" and then select the build button. You should now observe the compilation -and assembly of the ThreadX library. This project build produces the ThreadX +Building the ThreadX library is easy; simply select the ThreadX library project +file "tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. 3. Demonstration System The ThreadX demonstration is designed to execute under the MetaWare ARC HS -simulation. The instructions that follow describe how to get the ThreadX -demonstration running. +simulation. The instructions that follow describe how to get the ThreadX +demonstration running. -Building the demonstration is easy; simply select the demonstration project file -"sample_threadx." At this point, select the build button and observe the -compilation, assembly, and linkage of the ThreadX demonstration application. +Building the demonstration is easy; simply select the demonstration project file +"sample_threadx." At this point, select the build button and observe the +compilation, assembly, and linkage of the ThreadX demonstration application. After the demonstration is built, click on the "Debug" button and it will automatically launch a pre-configured connection to the ARC HS simulator. -You are now ready to execute the ThreadX demonstration system. Select -breakpoints and data watches to observe the execution of the sample_threadx.c +You are now ready to execute the ThreadX demonstration system. Select +breakpoints and data watches to observe the execution of the sample_threadx.c application. 4. System Initialization -The system entry point using the MetaWare tools is at the label _start. -This is defined within the crt1.s file supplied by MetaWare. In addition, +The system entry point using the MetaWare tools is at the label _start. +This is defined within the crt1.s file supplied by MetaWare. In addition, this is where all static and global preset C variable initialization processing is called from. After the MetaWare startup function completes, ThreadX initialization is called. The main initialization function is _tx_initialize_low_level and -is located in the file tx_initialize_low_level.s. This function is -responsible for setting up various system data structures, and interrupt +is located in the file tx_initialize_low_level.s. This function is +responsible for setting up various system data structures, and interrupt vectors. -By default free memory is assumed to start at the section .free_memory -which is referenced in tx_initialize_low_level.s and located in the -linker control file after all the linker defined RAM addresses. This is +By default free memory is assumed to start at the section .free_memory +which is referenced in tx_initialize_low_level.s and located in the +linker control file after all the linker defined RAM addresses. This is the address passed to the application definition function, tx_application_define. 5. Register Usage and Stack Frames -The ARC compiler assumes that registers r0-r12 are scratch registers for -each function. All other registers used by a C function must be preserved -by the function. ThreadX takes advantage of this in situations where a -context switch happens as a result of making a ThreadX service call (which -is itself a C function). In such cases, the saved context of a thread is +The ARC compiler assumes that registers r0-r12 are scratch registers for +each function. All other registers used by a C function must be preserved +by the function. ThreadX takes advantage of this in situations where a +context switch happens as a result of making a ThreadX service call (which +is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -114,26 +114,26 @@ associated thread control block TX_THREAD. 0x9C bta 0xA0 point of interrupt 0xA4 STATUS32 - + 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make it run faster, you can change the build_threadx.bat -file to remove the -g option and enable all compiler optimizations. +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat +file to remove the -g option and enable all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for the -ARC HS processor, including support for software interrupts and fast +ARC HS processor, including support for software interrupts and fast hardware interrupts. 7.1 Software Interrupt Handling @@ -147,25 +147,25 @@ _tx_interrupt_x: st blink, [sp, 16] ; Save blink (blink must be saved before _tx_thread_context_save) bl _tx_thread_context_save ; Save interrupt context ; -; /* Application ISR processing goes here! Your ISR can be written in +; /* Application ISR processing goes here! Your ISR can be written in ; assembly language or in C. If it is written in C, you must allocate -; 16 bytes of stack space before it is called. This must also be -; recovered once your C ISR return. An example of this is shown below. +; 16 bytes of stack space before it is called. This must also be +; recovered once your C ISR return. An example of this is shown below. ; ; If the ISR is written in assembly language, only the compiler scratch -; registers are available for use without saving/restoring (r0-r12). +; registers are available for use without saving/restoring (r0-r12). ; If use of additional registers are required they must be saved and ; restored. */ ; bl.d your_ISR_written_in_C ; Call an ISR written in C sub sp, sp, 16 ; Allocate stack space (delay slot) add sp, sp, 16 ; Recover stack space - + ; b _tx_thread_context_restore ; Restore interrupt context -The application handles interrupts directly, which necessitates all register +The application handles interrupts directly, which necessitates all register preservation by the application's ISR. ISRs that do not use the ThreadX _tx_thread_context_save and _tx_thread_context_restore routines are not allowed access to the ThreadX API. In addition, custom application ISRs @@ -173,11 +173,11 @@ should be higher priority than all ThreadX-managed ISRs. 7.2 Fast Interrupt Handling -ThreadX supports the ARC HS fast interrupt processing. It is assumed that +ThreadX supports the ARC HS fast interrupt processing. It is assumed that multiple register banks are available and the ARC HS processor automatically -uses register bank 1 as the fast interrupt register bank. +uses register bank 1 as the fast interrupt register bank. -In order to use fast interrupts with register bank 1, the interrupt desired +In order to use fast interrupts with register bank 1, the interrupt desired must have priority 0 and the application must call the following ThreadX API to setup register bank 1: @@ -190,7 +190,7 @@ look like: tx_initialize_fast_interrupt_setup(&fast_interrupt_stack[1020]); -As for the fast interrupt ISR, the following template should be used for +As for the fast interrupt ISR, the following template should be used for ARC HS fast interrupts managed by ThreadX: .global _tx_fast_interrupt_x @@ -207,28 +207,28 @@ _tx_fast_interrupt_x: 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer -interrupt source, these services are not functional but the remainder of +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of ThreadX will still run. By default, the ThreadX timer interrupt is mapped to the ARC HS auxiliary timer 0, which generates low priority interrupts on interrupt vector 16. -It is easy to change the timer interrupt source and priority by changing the +It is easy to change the timer interrupt source and priority by changing the setup code in tx_initialize_low_level.s. 9. Thread Hardware Register Bank Context -ThreadX supports the use of hardware register banks on the ARC HS. A hardware -register bank may be associated with a specific application thread via the +ThreadX supports the use of hardware register banks on the ARC HS. A hardware +register bank may be associated with a specific application thread via the following API: void tx_thread_register_bank_assign(TX_THREAD *thread_ptr, register_bank); This API is assumed to be called from initialization (interrupts are locked out -and execution is from register bank 0) and after the specified thread has been -created. This API assumes the register bank number is correct, i.e., a valid +and execution is from register bank 0) and after the specified thread has been +created. This API assumes the register bank number is correct, i.e., a valid register bank greater than 0 and one that hasn't been used for another thread. Note: if fast interrupts are used, register bank 1 must also not be used. In this diff --git a/ports/arc_hs/metaware/src/tx_initialize_fast_interrupt_setup.s b/ports/arc_hs/metaware/src/tx_initialize_fast_interrupt_setup.s index c4aa7114..c757508b 100644 --- a/ports/arc_hs/metaware/src/tx_initialize_fast_interrupt_setup.s +++ b/ports/arc_hs/metaware/src/tx_initialize_fast_interrupt_setup.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -22,10 +22,10 @@ #include "tx_user.h" #endif -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_initialize_fast_interrupt_setup ARC_HS/MetaWare */ ;/* 6.2.1 */ ;/* AUTHOR */ @@ -33,35 +33,26 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function initializes register bank 1 for fast interrupt use. */ -;/* The initialization includes setting the stack pointer to the value */ -;/* supplied by the caller. */ -;/* */ -;/* INPUT */ -;/* */ -;/* stack_ptr Pointer to stack for bank 1 */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 03-08-2023 Cindy Deng Modified comment(s), added */ -;/* #include tx_user.h, */ -;/* resulting in version 6.2.1 */ +;/* This function initializes register bank 1 for fast interrupt use. */ +;/* The initialization includes setting the stack pointer to the value */ +;/* supplied by the caller. */ +;/* */ +;/* INPUT */ +;/* */ +;/* stack_ptr Pointer to stack for bank 1 */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_fast_interrupt_setup(VOID *stack_ptr) @@ -71,7 +62,7 @@ _tx_initialize_fast_interrupt_setup: ; ; /* Assume this routine is being called from initialization, with interrupts -; disabled and from register bank 0. Also assume that the stack pointer +; disabled and from register bank 0. Also assume that the stack pointer ; input is valid, i.e., there is no error checking on the validity of ; register_bank. */ ; diff --git a/ports/arc_hs/metaware/src/tx_thread_context_fast_restore.s b/ports/arc_hs/metaware/src/tx_thread_context_fast_restore.s index 089f13de..d2f5284c 100644 --- a/ports/arc_hs/metaware/src/tx_thread_context_fast_restore.s +++ b/ports/arc_hs/metaware/src/tx_thread_context_fast_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -23,11 +23,11 @@ #endif .equ BTA, 0x412 - -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_context_fast_restore ARC_HS/MetaWare */ ;/* 6.2.1 */ ;/* AUTHOR */ @@ -35,43 +35,34 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the fast interrupt context, which can be a */ -;/* nesting condition on a non-fast ISR, an idle system restore, a */ -;/* restore of an interrupted thread, and a preemption of an interrupted*/ -;/* thread. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 03-08-2023 Cindy Deng Modified comment(s), added */ -;/* #include tx_user.h, */ -;/* resulting in version 6.2.1 */ +;/* This function restores the fast interrupt context, which can be a */ +;/* nesting condition on a non-fast ISR, an idle system restore, a */ +;/* restore of an interrupted thread, and a preemption of an interrupted*/ +;/* thread. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_fast_restore(VOID) ;{ .global _tx_thread_context_fast_restore - .type _tx_thread_context_fast_restore, @function + .type _tx_thread_context_fast_restore, @function _tx_thread_context_fast_restore: ; ; /* Note: it is assumed that the stack pointer is in the same position now as @@ -98,7 +89,7 @@ _tx_thread_context_fast_restore: ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; @@ -160,7 +151,7 @@ __tx_thread_preempt_restore: st r0, [sp, 132] ; Temporarily save r0 mov r0, 3 ; Build hardware interrupt stack type st r0, [sp, 0] ; Setup interrupt stack type - + .ifndef TX_DISABLE_LP lr r0, [LP_START] ; Pickup LP_START st r0, [sp, 4] ; Save LP_START @@ -186,7 +177,7 @@ __tx_thread_preempt_restore: kflag ilink ; Move back to register bank 0 b __tx_preempt_save_done ; Done, finished with preemption save -__tx_software_interrupt_context: +__tx_software_interrupt_context: st ilink, [sp, 0] ; Save ilink (point of interrupt) st r3, [sp, 4] ; Save status32 mov ilink, sp ; Pass the information back to the other register bank via ilink @@ -223,7 +214,7 @@ __tx_software_interrupt_context: st r1, [sp, 128] ; Save r1 st r0, [sp, 132] ; Save r0 st r30, [sp, 136] ; Save r30 - + .ifndef TX_DISABLE_LP lr r10, [LP_START] ; Pickup LP_START lr r9, [LP_END] ; Pickup LP_END diff --git a/ports/arc_hs/metaware/src/tx_thread_context_fast_save.s b/ports/arc_hs/metaware/src/tx_thread_context_fast_save.s index d9a80463..f54176d4 100644 --- a/ports/arc_hs/metaware/src/tx_thread_context_fast_save.s +++ b/ports/arc_hs/metaware/src/tx_thread_context_fast_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -22,10 +22,10 @@ #include "tx_user.h" #endif -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_context_fast_save ARC_HS/MetaWare */ ;/* 6.2.1 */ ;/* AUTHOR */ @@ -33,46 +33,37 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of fast interrupt processing. The function assumes that */ -;/* fast interrupts are enabled (priority 0) and multiple register */ -;/* banks are available. In this case, register bank 1 is reserved by */ -;/* hardware for fast interrupts. Additional assumptions include that */ -;/* there will be no nested fast interrupts and the LP_START, LP_END, */ -;/* and LP_COUNT registers are not used in the application's fast */ -;/* interrupt ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 03-08-2023 Cindy Deng Modified comment(s), added */ -;/* #include tx_user.h, */ -;/* resulting in version 6.2.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of fast interrupt processing. The function assumes that */ +;/* fast interrupts are enabled (priority 0) and multiple register */ +;/* banks are available. In this case, register bank 1 is reserved by */ +;/* hardware for fast interrupts. Additional assumptions include that */ +;/* there will be no nested fast interrupts and the LP_START, LP_END, */ +;/* and LP_COUNT registers are not used in the application's fast */ +;/* interrupt ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_fast_save(VOID) ;{ .global _tx_thread_context_fast_save - .type _tx_thread_context_fast_save, @function + .type _tx_thread_context_fast_save, @function _tx_thread_context_fast_save: ; ; /* Increment nested interrupt count. */ diff --git a/ports/arc_hs/metaware/src/tx_thread_context_restore.s b/ports/arc_hs/metaware/src/tx_thread_context_restore.s index 79a786c5..23d675a8 100644 --- a/ports/arc_hs/metaware/src/tx_thread_context_restore.s +++ b/ports/arc_hs/metaware/src/tx_thread_context_restore.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ @@ -56,19 +56,6 @@ ;/* */ ;/* ISRs Interrupt Service Routines */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 Andres Mlinar Modified comment(s), and */ -;/* r25/r30 are caller saved, */ -;/* use schedule_reenter, */ -;/* resulting in version 6.1.9 */ -;/* 03-08-2023 Cindy Deng Modified comment(s), added */ -;/* #include tx_user.h, */ -;/* resulting in version 6.2.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) ;{ @@ -249,7 +236,7 @@ __tx_thread_preempt_restore: b __tx_preempt_save_done ; Done, finished with preemption save nop -__tx_software_interrupt_context: +__tx_software_interrupt_context: mov r6, 1 ; Build interrupt stack type st r6, [r7, 0] ; Setup interrupt stack type st fp, [r7, 24] ; Save fp diff --git a/ports/arc_hs/metaware/src/tx_thread_context_save.s b/ports/arc_hs/metaware/src/tx_thread_context_save.s index 9fcc82e6..27ee25b5 100644 --- a/ports/arc_hs/metaware/src/tx_thread_context_save.s +++ b/ports/arc_hs/metaware/src/tx_thread_context_save.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ @@ -55,18 +55,6 @@ ;/* */ ;/* ISRs */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 Andres Mlinar Modified comment(s), and */ -;/* r25/r30 are caller saved, */ -;/* resulting in version 6.1.9 */ -;/* 03-08-2023 Cindy Deng Modified comment(s), added */ -;/* #include tx_user.h, */ -;/* resulting in version 6.2.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) ;{ diff --git a/ports/arc_hs/metaware/src/tx_thread_interrupt_control.s b/ports/arc_hs/metaware/src/tx_thread_interrupt_control.s index 9d3dacae..3d18b9a1 100644 --- a/ports/arc_hs/metaware/src/tx_thread_interrupt_control.s +++ b/ports/arc_hs/metaware/src/tx_thread_interrupt_control.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ @@ -52,17 +52,6 @@ ;/* */ ;/* Application Code */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 04-02-2021 Andres Mlinar Modified comments, */ -;/* resulting in version 6.1.6 */ -;/* 03-08-2023 Cindy Deng Modified comment(s), added */ -;/* #include tx_user.h, */ -;/* resulting in version 6.2.1 */ -;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) ;{ diff --git a/ports/arc_hs/metaware/src/tx_thread_register_bank_assign.s b/ports/arc_hs/metaware/src/tx_thread_register_bank_assign.s index 7b9d1114..f9876c89 100644 --- a/ports/arc_hs/metaware/src/tx_thread_register_bank_assign.s +++ b/ports/arc_hs/metaware/src/tx_thread_register_bank_assign.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -22,10 +22,10 @@ #include "tx_user.h" #endif -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_register_bank_assign ARC_HS/MetaWare */ ;/* 6.2.1 */ ;/* AUTHOR */ @@ -33,37 +33,28 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function builds a stack frame on the supplied thread's stack. */ ;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ ;/* thread_ptr Pointer to thread control blk */ ;/* register_bank Register bank number */ -;/* (1 through max-1) */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* (1 through max-1) */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 03-08-2023 Cindy Deng Modified comment(s), added */ -;/* #include tx_user.h, */ -;/* resulting in version 6.2.1 */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_register_bank_assign(VOID *thread_ptr, UINT register_bank) @@ -75,9 +66,9 @@ _tx_thread_register_bank_assign: ; /* Assume this routine is being called from initialization, with interrupts ; disabled and from register bank 0. Also assume that the thread pointer and ; register bank input is valid, i.e., there is no error checking on the validity of -; the thread pointer or the register_bank. +; the thread pointer or the register_bank. ; -; It is worth noting that if fast interrupts are being used, register bank 1 +; It is worth noting that if fast interrupts are being used, register bank 1 ; is reserved for the fast interrupt processing, so thread register bank assignments ; should begin at bank 2. */ ; @@ -101,7 +92,7 @@ _tx_thread_register_bank_assign: bclr r3, r3, 17 ; bclr r3, r3, 18 ; kflag r3 ; Move back to register bank 0 - mov r5, 3 ; Build type for hardware interrupt context + mov r5, 3 ; Build type for hardware interrupt context j_s.d [blink] ; Return to caller st r5, [r4, 0] ; Set stack frame type ;} diff --git a/ports/arc_hs/metaware/src/tx_thread_schedule.s b/ports/arc_hs/metaware/src/tx_thread_schedule.s index 954ec371..2651cb48 100644 --- a/ports/arc_hs/metaware/src/tx_thread_schedule.s +++ b/ports/arc_hs/metaware/src/tx_thread_schedule.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ @@ -57,18 +57,6 @@ ;/* _tx_thread_system_return Return to system from thread */ ;/* _tx_thread_context_restore Restore thread's context */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 Andres Mlinar Modified comment(s), */ -;/* use schedule reenter, */ -;/* resulting in version 6.1.9 */ -;/* 03-08-2023 Cindy Deng Modified comment(s), added */ -;/* #include tx_user.h, */ -;/* resulting in version 6.2.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) ;{ @@ -149,11 +137,11 @@ __tx_thread_schedule_loop: ld r2, [sp, 4] ; Pickup status32 kflag r2 ; Enter the proper register bank ld r3, [sp, 8] ; Pickup the saved interrupt posture - add sp, sp, 12 ; Recover small stack frame - j_s.d [blink] ; Return to thread and restore flags + add sp, sp, 12 ; Recover small stack frame + j_s.d [blink] ; Return to thread and restore flags seti r3 ; Recover STATUS32 -__tx_hw_interrupt_restore: +__tx_hw_interrupt_restore: mov r0, 0x2 ; Pretend level 1 interrupt is returning sr r0, [AUX_IRQ_ACT] ; @@ -163,10 +151,10 @@ __tx_hw_interrupt_restore: sr r0, [LP_START] ; Restore LP_START ld r1, [sp, 8] ; Recover LP_END sr r1, [LP_END] ; Restore LP_END - ld r2, [sp, 12] ; Recover LP_COUNT + ld r2, [sp, 12] ; Recover LP_COUNT mov LP_COUNT, r2 .endif - + .ifdef TX_ENABLE_ACC ld r58, [sp, 140] ; Recover r58 ld r59, [sp, 144] ; Recover r59 @@ -180,7 +168,7 @@ __tx_hw_interrupt_restore: kflag r0 ; Switch to the proper register bank add sp, sp, 160 ; Recover the interrupt stack frame rtie ; Return to point of interrupt - + __tx_restore_non_hw_context: ; ; /* Determine if an interrupt frame or a synchronous task suspension frame diff --git a/ports/arc_hs/metaware/src/tx_thread_stack_build.s b/ports/arc_hs/metaware/src/tx_thread_stack_build.s index 8ef5dc98..db4becfc 100644 --- a/ports/arc_hs/metaware/src/tx_thread_stack_build.s +++ b/ports/arc_hs/metaware/src/tx_thread_stack_build.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ @@ -57,17 +57,6 @@ ;/* */ ;/* _tx_thread_create Create thread service */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 04-02-2021 Andres Mlinar Modified comments, */ -;/* resulting in version 6.1.6 */ -;/* 03-08-2023 Cindy Deng Modified comment(s), added */ -;/* #include tx_user.h, */ -;/* resulting in version 6.2.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) ;{ diff --git a/ports/arc_hs/metaware/src/tx_thread_system_return.s b/ports/arc_hs/metaware/src/tx_thread_system_return.s index aec09bb4..453682e4 100644 --- a/ports/arc_hs/metaware/src/tx_thread_system_return.s +++ b/ports/arc_hs/metaware/src/tx_thread_system_return.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ @@ -54,18 +54,6 @@ ;/* */ ;/* ThreadX components */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 Andres Mlinar Modified comments, */ -;/* use schedule reenter, */ -;/* resulting in version 6.1.9 */ -;/* 03-08-2023 Cindy Deng Modified comment(s), added */ -;/* #include tx_user.h, */ -;/* resulting in version 6.2.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) ;{ @@ -87,7 +75,7 @@ _tx_thread_system_return: mov r4, 2 ; Build solicited hardward stack frame type st r4, [sp, 0] ; Set stack frame type st r3, [sp, 4] ; Save status32 - st r2, [sp, 8] ; Save interrupt posture + st r2, [sp, 8] ; Save interrupt posture st sp, [r0, 8] ; Save thread's stack pointer bclr r3, r3, 16 ; Build register bank 0 value bclr r3, r3, 17 ; @@ -120,7 +108,7 @@ __tx_software_context: st r30, [sp, 72] ; Save r30 st sp, [r0, 8] ; Save thread's stack pointer __tx_save_done: -; +; .ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; ; /* Call the thread exit function to indicate the thread is no longer executing. */ diff --git a/ports/arc_hs/metaware/src/tx_timer_interrupt.s b/ports/arc_hs/metaware/src/tx_timer_interrupt.s index 59410fdc..6f6aa521 100644 --- a/ports/arc_hs/metaware/src/tx_timer_interrupt.s +++ b/ports/arc_hs/metaware/src/tx_timer_interrupt.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ @@ -58,23 +58,6 @@ ;/* */ ;/* interrupt vector */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 12-31-2020 Scott Larson Modified comment(s), remove */ -;/* unneeded load of */ -;/* _tx_thread_preempt_disable, */ -;/* resulting in version 6.1.3 */ -;/* 10-15-2021 Yuxin Zhou Modified comment(s), and */ -;/* fixed possible race */ -;/* condition on preemption */ -;/* resulting in version 6.1.9 */ -;/* 03-08-2023 Cindy Deng Modified comment(s), added */ -;/* #include tx_user.h, */ -;/* resulting in version 6.2.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) ;{ diff --git a/ports/arm11/ac5/example_build/sample_threadx.c b/ports/arm11/ac5/example_build/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports/arm11/ac5/example_build/sample_threadx.c +++ b/ports/arm11/ac5/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/arm11/ac5/example_build/tx_initialize_low_level.s b/ports/arm11/ac5/example_build/tx_initialize_low_level.s index 541ddb1e..3badfc20 100644 --- a/ports/arm11/ac5/example_build/tx_initialize_low_level.s +++ b/ports/arm11/ac5/example_build/tx_initialize_low_level.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -41,7 +41,7 @@ SYS_STACK_SIZE EQU 1024 ; SYS stack size (used for neste IRQ_STACK_SIZE EQU 1024 ; IRQ stack size ; ; -;/* ARM11 ARMulator Timer and Interrupt controller information. This depends on +;/* ARM11 ARMulator Timer and Interrupt controller information. This depends on ; the ARMulator's Interrupt Controller and Timer being enabled in the default.ami. ; In addition, the addresses must match those specified in the peripherals.ami file. ; Please refer to section 2.10 and 4.16 of the Debug Target Guide, version 1.2. */ @@ -50,7 +50,7 @@ IRQStatus EQU 0x0a000000 ; IRQ Status Register IRQRawStatus EQU 0x0a000004 ; IRQ Raw Status Register IRQEnable EQU 0x0a000008 ; IRQ Enable Set Register IRQEnableClear EQU 0x0a00000C ; IRQ Enable Clear Register -IRQSoft EQU 0x0a000010 ; IRQ Soft +IRQSoft EQU 0x0a000010 ; IRQ Soft FIQStatus EQU 0x0a000100 ; FIQ Status Register FIQRawStatus EQU 0x0a000104 ; FIQ Raw Status Register FIQEnable EQU 0x0a000108 ; FIQ Enable Set Register @@ -113,45 +113,39 @@ __vectors ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -202,7 +196,7 @@ _tx_initialize_low_level ; _tx_thread_system_stack_ptr = (VOID_PTR) (sp); ; LDR r1, =_tx_thread_system_stack_ptr ; Pickup address of system stack ptr - LDR r0, [r1, #0] ; Pickup system stack + LDR r0, [r1, #0] ; Pickup system stack ADD r0, r0, #4 ; Increment to next free word ; ; /* Save the first available memory address. */ @@ -238,7 +232,7 @@ _tx_initialize_low_level ; ; ;/* Define initial heap/stack routine for the ARM RealView (and ADS) startup code. This -; routine will set the initial stack to use the ThreadX IRQ & FIQ & +; routine will set the initial stack to use the ThreadX IRQ & FIQ & ; (optionally SYS) stack areas. */ ; EXPORT __user_initial_stackheap @@ -290,7 +284,7 @@ __tx_reserved_handler ; ; EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -298,34 +292,34 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; ; ; /* Check for Timer1 interrupts on the ARMulator. */ LDR r1,=IRQStatus ; Pickup address of IRQStatus register - LDR r2, [r1] ; Read IRQStatus + LDR r2, [r1] ; Read IRQStatus LDR r0,=TIMER1_BIT ; Pickup Timer1 interrupt present bit AND r2, r2, r0 ; Is this a timer interrupt? - CMP r2, r0 ; + CMP r2, r0 ; BNE _tx_not_timer_interrupt ; If 0, not a timer interrupt LDR r1,=Timer1Clear ; Build address of Timer1 clear register - MOV r0,#0 ; + MOV r0,#0 ; STR r0, [r1] ; Clear timer 0 interrupt BL _tx_timer_interrupt ; Timer interrupt handler _tx_not_timer_interrupt ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ IF :DEF:TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -335,7 +329,7 @@ _tx_not_timer_interrupt ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ IF :DEF:TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -351,28 +345,28 @@ _tx_not_timer_interrupt __tx_example_vectored_irq_handler ; ; -; /* Save initial context and call context save to prepare for +; /* Save initial context and call context save to prepare for ; vectored ISR execution. */ ; ; STMDB sp!, {r0-r3} ; Save some scratch registers ; MRS r0, SPSR ; Pickup saved SPSR -; SUB lr, lr, #4 ; Adjust point of interrupt +; SUB lr, lr, #4 ; Adjust point of interrupt ; STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers ; BL _tx_thread_vectored_context_save ; Vectored context save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ; IF :DEF:TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_start @@ -381,7 +375,7 @@ __tx_example_vectored_irq_handler ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ; IF :DEF:TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_end @@ -403,11 +397,11 @@ __tx_fiq_processing_return ; /* At this point execution is still in the FIQ mode. The CPSR, point of ; interrupt, and all C scratch registers are available for use. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start ; from FIQ mode with interrupts disabled. This routine switches to the -; system mode and returns with FIQ interrupts enabled. +; system mode and returns with FIQ interrupts enabled. ; -; NOTE: It is very important to ensure all FIQ interrupts are cleared +; NOTE: It is very important to ensure all FIQ interrupts are cleared ; prior to enabling nested FIQ interrupts. */ IF :DEF:TX_ENABLE_FIQ_NESTING BL _tx_thread_fiq_nesting_start diff --git a/ports/arm11/ac5/inc/tx_port.h b/ports/arm11/ac5/inc/tx_port.h index eb74538b..b1bf6e36 100644 --- a/ports/arm11/ac5/inc/tx_port.h +++ b/ports/arm11/ac5/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h ARM11/AC5 */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h ARM11/AC5 */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -75,7 +67,7 @@ #include -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -111,12 +103,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -126,8 +118,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -174,7 +166,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -186,13 +178,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -206,11 +198,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -218,8 +210,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -246,21 +238,21 @@ typedef unsigned short USHORT; #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef __thumb - + #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (ULONG) __clz((unsigned int) m); \ - b = 31 - b; + b = 31 - b; #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -280,7 +272,7 @@ typedef unsigned short USHORT; { \ __enable_irq(); \ __enable_fiq(); \ - } + } #else @@ -289,7 +281,7 @@ typedef unsigned short USHORT; #define TX_RESTORE if (!interrupt_save_disabled) \ { \ __enable_irq(); \ - } + } #endif #else @@ -318,8 +310,8 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARM11/AC5 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARM11/AC5 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/arm11/ac5/readme_threadx.txt b/ports/arm11/ac5/readme_threadx.txt index 82a9dfa2..a89d79b5 100644 --- a/ports/arm11/ac5/readme_threadx.txt +++ b/ports/arm11/ac5/readme_threadx.txt @@ -6,15 +6,15 @@ 1. Building the ThreadX run-time Library -First make sure you are in the "example_build" directory. Also, make sure that -you have setup your path and other environment variables necessary for the ARM -AC5 development environment. At this point you may run the build_threadx.bat -batch file. This will build the ThreadX run-time environment in the -"example_build" directory. +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the ARM +AC5 development environment. At this point you may run the build_threadx.bat +batch file. This will build the ThreadX run-time environment in the +"example_build" directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. @@ -24,39 +24,39 @@ Since there is no ARM11 FVP, there are no instructions here for running the demonstration; users are expected to run the demonstration on their platform of choice. -Building the demonstration is easy; simply execute the build_threadx_sample.bat -batch file while inside the "example_build" directory. +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with tx.a. The resulting file sample_threadx.axf +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.axf is a binary file that can be downloaded and executed on the user's platform of choice. 3. System Initialization -The entry point in ThreadX for the Cortex-A5 using AC5 tools is at label +The entry point in ThreadX for the Cortex-A5 using AC5 tools is at label __main. This is defined within the AC5 compiler's startup code. In addition, this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. By default, the vector area is defined to be located in the Init area, -which is defined at the top of tx_initialize_low_level.s. This area is typically -located at 0. In situations where this is impossible, the vectors at the beginning +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. By default, the vector area is defined to be located in the Init area, +which is defined at the top of tx_initialize_low_level.s. This area is typically +located at 0. In situations where this is impossible, the vectors at the beginning of the Init area should be copied to address 0. This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 4. Assembler / Compiler Switches -The following are compiler switches used in building the demonstration +The following are compiler switches used in building the demonstration system: Compiler Switch Meaning @@ -72,10 +72,10 @@ Linker Switch Meaning -o demo.axf Specifies demo output file name --elf Specifies elf output file format --ro Specifies that Read-Only memory starts at address 0 - --first tx_initialize_low_level.o(Init) + --first tx_initialize_low_level.o(Init) Specifies that the first area loaded is Init --remove Remove unused areas - --list Specifies map file name + --list Specifies map file name --symbols Specifies symbols for map file --map Creates a map file @@ -86,161 +86,161 @@ Application Defines ThreadX assembly files. If used, it should be used on all assembly files and the generic C source of - ThreadX should be compiled with + ThreadX should be compiled with TX_ENABLE_FIQ_SUPPORT defined as well. --PD "TX_ENABLE_IRQ_NESTING SETL {TRUE}" This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. --PD "TX_ENABLE_FIQ_NESTING SETL {TRUE}" This assembler define enables FIQ - nested support. If FIQ nested + nested support. If FIQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. In addition, IRQ nesting should also be enabled. -DTX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ interrupt handling in the ThreadX - generic C source. This define + generic C source. This define should also be used in conjunction with the corresponding assembler - define. + define. -DTX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - -DTX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + -DTX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - -DTX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + -DTX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - -DTX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + -DTX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - -DTX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + -DTX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - -DTX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + -DTX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - -DTX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + -DTX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - -DTX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + -DTX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - -DTX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + -DTX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - -DTX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + -DTX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - -DTX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + -DTX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - -DTX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + -DTX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - -DTX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + -DTX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - -DTX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + -DTX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - -DTX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + -DTX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - -DTX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + -DTX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - -DTX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + -DTX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - -DTX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + -DTX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - -DTX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + -DTX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - -DTX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + -DTX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. -DTX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - -DTX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + -DTX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - -DTX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + -DTX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. 5. Register Usage and Stack Frames -The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -258,39 +258,39 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make it run faster, you can change the build_threadx.bat file to -remove the -g option and enable all compiler optimizations. +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A5 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-A5 vectors start at address zero. The demonstration system startup -Init area contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +Init area contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs @@ -301,12 +301,12 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.s: EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -314,7 +314,7 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -327,7 +327,7 @@ __tx_irq_processing_return 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.s: EXPORT __tx_irq_example_handler @@ -337,12 +337,12 @@ __tx_irq_example_handler STMDB sp!, {r0-r3} ; Save some scratch registers MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers BL _tx_thread_vectored_context_save ; Call the vectored IRQ context save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -359,22 +359,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.s. When nested IRQ interrupts are no longer required, calling the _tx_thread_irq_nesting_end service disables nesting by disabling -IRQ interrupts and switching back to IRQ mode in preparation for the IRQ +IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -382,10 +382,10 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* Enable nested IRQ interrupts. NOTE: Since this service returns -; with IRQ interrupts enabled, all IRQ interrupt sources must be +; with IRQ interrupts enabled, all IRQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start -; +; ; /* Application ISR call(s) go here! */ ; ; /* Disable nested IRQ interrupts. The mode is switched back to @@ -398,12 +398,12 @@ __tx_irq_processing_return 7.3 FIQ Interrupts -By default, Cortex-A5 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, Cortex-A5 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.s. @@ -412,7 +412,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.s. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.s: @@ -440,18 +440,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.s. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -467,7 +467,7 @@ __tx_fiq_processing_return ; interrupt, and all C scratch registers are available for use. */ ; ; /* Enable nested FIQ interrupts. NOTE: Since this service returns -; with FIQ interrupts enabled, all FIQ interrupt sources must be +; with FIQ interrupts enabled, all FIQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start ; @@ -483,28 +483,28 @@ __tx_fiq_processing_return 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.s in the Integrator sub-directories. 9. Thumb/Cortex-A5 Mixed Mode -By default, ThreadX is setup for running in Cortex-A5 32-bit mode. This is -also true for the demonstration system. It is possible to build any -ThreadX file and/or the application in Thumb mode. If any Thumb code -is used the entire ThreadX source- both C and assembly - should be built +By default, ThreadX is setup for running in Cortex-A5 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. If any Thumb code +is used the entire ThreadX source- both C and assembly - should be built with the "-apcs /interwork" option. 11. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); diff --git a/ports/arm11/ac5/src/tx_thread_context_restore.s b/ports/arm11/ac5/src/tx_thread_context_restore.s index e9dbf9e0..d7bce36c 100644 --- a/ports/arm11/ac5/src/tx_thread_context_restore.s +++ b/ports/arm11/ac5/src/tx_thread_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -37,7 +37,7 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask THUMB_MASK EQU 0x20 ; Thumb bit mask SVC_MODE_BITS EQU 0x13 ; SVC mode value ; @@ -55,44 +55,38 @@ SVC_MODE_BITS EQU 0x13 ; SVC mode value ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -120,13 +114,13 @@ _tx_thread_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3, #0] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3, #0] ; Store the counter + STR r2, [r3, #0] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs diff --git a/ports/arm11/ac5/src/tx_thread_context_save.s b/ports/arm11/ac5/src/tx_thread_context_save.s index 8c92eeb1..aa99af37 100644 --- a/ports/arm11/ac5/src/tx_thread_context_save.s +++ b/ports/arm11/ac5/src/tx_thread_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -45,43 +45,37 @@ DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -96,7 +90,7 @@ _tx_thread_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers IF :DEF:TX_ENABLE_FIQ_SUPPORT MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt CPSR @@ -116,7 +110,7 @@ _tx_thread_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -132,7 +126,7 @@ _tx_thread_context_save POP {lr} ; Recover ISR lr ENDIF - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; __tx_thread_not_nested_save ; } @@ -146,13 +140,13 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} ; Store other registers ; ; /* Save the current stack pointer in the thread's control block. */ @@ -172,7 +166,7 @@ __tx_thread_not_nested_save POP {lr} ; Recover ISR lr ENDIF - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ; else @@ -182,7 +176,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit @@ -197,7 +191,7 @@ __tx_thread_idle_system_save ENDIF ADD sp, sp, #16 ; Recover saved registers - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ;} diff --git a/ports/arm11/ac5/src/tx_thread_fiq_context_restore.s b/ports/arm11/ac5/src/tx_thread_fiq_context_restore.s index af516975..41fc0eac 100644 --- a/ports/arm11/ac5/src/tx_thread_fiq_context_restore.s +++ b/ports/arm11/ac5/src/tx_thread_fiq_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -37,7 +37,7 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask THUMB_MASK EQU 0x20 ; Thumb bit mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits SVC_MODE_BITS EQU 0x13 ; SVC mode value @@ -57,44 +57,38 @@ SVC_MODE_BITS EQU 0x13 ; SVC mode value ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_restore ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the fiq interrupt context when processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* FIQ ISR Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) @@ -122,13 +116,13 @@ _tx_thread_fiq_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3] ; Store the counter + STR r2, [r3] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -172,7 +166,7 @@ __tx_thread_fiq_no_preempt_restore ; /* Restore interrupted thread or ISR. */ ; ; /* Pickup the saved stack pointer. */ -; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; ; ; /* Recover the saved context and return to the point of interrupt. */ ; @@ -219,7 +213,7 @@ __tx_thread_fiq_preempt_restore BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it ; ; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; -; _tx_timer_time_slice = 0; +; _tx_timer_time_slice = 0; ; STR r2, [r0, #24] ; Save thread's time-slice MOV r2, #0 ; Clear value diff --git a/ports/arm11/ac5/src/tx_thread_fiq_context_save.s b/ports/arm11/ac5/src/tx_thread_fiq_context_save.s index 72bebd9d..7aa2c832 100644 --- a/ports/arm11/ac5/src/tx_thread_fiq_context_save.s +++ b/ports/arm11/ac5/src/tx_thread_fiq_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,43 +39,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_save ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) @@ -90,7 +84,7 @@ _tx_thread_fiq_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state CMP r2, #0 ; Is this the first interrupt? @@ -105,7 +99,7 @@ _tx_thread_fiq_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -121,38 +115,38 @@ _tx_thread_fiq_context_save POP {lr} ; Recover ISR lr ENDIF - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; __tx_thread_fiq_not_nested_save -; } +; } ; ; /* Otherwise, not nested, check to see if a thread was running. */ ; else if (_tx_thread_current_ptr) -; { +; { ; ADD r2, r2, #1 ; Increment the interrupt counter STR r2, [r3] ; Store it back in the variable LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in -; ; scheduling loop - nothing needs saving! + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, lr} ; Store other registers, Note that we don't -; ; need to save sl and ip since FIQ has -; ; copies of these registers. Nested +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested ; ; interrupt processing does need to save ; ; these registers. ; ; /* Save the current stack pointer in the thread's control block. */ -; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; ; ; /* Switch to the system stack. */ -; sp = _tx_thread_system_stack_ptr; +; sp = _tx_thread_system_stack_ptr; ; MOV r10, #0 ; Clear stack limit @@ -165,7 +159,7 @@ __tx_thread_fiq_not_nested_save POP {lr} ; Recover ISR lr ENDIF - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } ; else @@ -185,18 +179,18 @@ __tx_thread_fiq_idle_system_save ENDIF ; ; /* Not much to do here, save the current SPSR and LR for possible -; use in IRQ interrupted in idle system conditions, and return to +; use in IRQ interrupted in idle system conditions, and return to ; FIQ interrupt processing. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, lr} ; Store other registers that will get used -; ; or stripped off the stack in context -; ; restore - B __tx_fiq_processing_return ; Continue FIQ processing +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } -;} +;} ; END diff --git a/ports/arm11/ac5/src/tx_thread_fiq_nesting_end.s b/ports/arm11/ac5/src/tx_thread_fiq_nesting_end.s index 66b82422..69faffe0 100644 --- a/ports/arm11/ac5/src/tx_thread_fiq_nesting_end.s +++ b/ports/arm11/ac5/src/tx_thread_fiq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,56 +34,50 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_end ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ -;/* processing from system mode back to FIQ mode prior to the ISR */ -;/* calling _tx_thread_fiq_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with FIQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) @@ -94,7 +88,7 @@ _tx_thread_fiq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_cxsf, r0 ; Disable interrupts - LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports/arm11/ac5/src/tx_thread_fiq_nesting_start.s b/ports/arm11/ac5/src/tx_thread_fiq_nesting_start.s index fd36e17f..2bbd33e8 100644 --- a/ports/arm11/ac5/src/tx_thread_fiq_nesting_start.s +++ b/ports/arm11/ac5/src/tx_thread_fiq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_start ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ -;/* processing to the system mode so nested FIQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with FIQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/arm11/ac5/src/tx_thread_interrupt_control.s b/ports/arm11/ac5/src/tx_thread_interrupt_control.s index 7d3bddae..e51c993d 100644 --- a/ports/arm11/ac5/src/tx_thread_interrupt_control.s +++ b/ports/arm11/ac5/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,42 +36,36 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/arm11/ac5/src/tx_thread_interrupt_disable.s b/ports/arm11/ac5/src/tx_thread_interrupt_disable.s index e2c50cfd..6224b590 100644 --- a/ports/arm11/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/arm11/ac5/src/tx_thread_interrupt_disable.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,41 +36,35 @@ DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(void) diff --git a/ports/arm11/ac5/src/tx_thread_interrupt_restore.s b/ports/arm11/ac5/src/tx_thread_interrupt_restore.s index ad7fb5d2..a35c0621 100644 --- a/ports/arm11/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/arm11/ac5/src/tx_thread_interrupt_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,42 +29,36 @@ ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function is responsible for restoring interrupts to the state */ ;/* returned by a previous _tx_thread_interrupt_disable call. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/arm11/ac5/src/tx_thread_irq_nesting_end.s b/ports/arm11/ac5/src/tx_thread_irq_nesting_end.s index a8ee12ad..83e93891 100644 --- a/ports/arm11/ac5/src/tx_thread_irq_nesting_end.s +++ b/ports/arm11/ac5/src/tx_thread_irq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,56 +34,50 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_end ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -;/* processing from system mode back to IRQ mode prior to the ISR */ -;/* calling _tx_thread_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) @@ -94,7 +88,7 @@ _tx_thread_irq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_cxsf, r0 ; Disable interrupts - LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports/arm11/ac5/src/tx_thread_irq_nesting_start.s b/ports/arm11/ac5/src/tx_thread_irq_nesting_start.s index aea8bbf4..d658bf1c 100644 --- a/ports/arm11/ac5/src/tx_thread_irq_nesting_start.s +++ b/ports/arm11/ac5/src/tx_thread_irq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_start ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_context_save has been called and switches the IRQ */ -;/* processing to the system mode so nested IRQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/arm11/ac5/src/tx_thread_schedule.s b/ports/arm11/ac5/src/tx_thread_schedule.s index 17646482..b8bc01e6 100644 --- a/ports/arm11/ac5/src/tx_thread_schedule.s +++ b/ports/arm11/ac5/src/tx_thread_schedule.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -47,45 +47,39 @@ ENABLE_INTS EQU 0x80 ; IRQ Interrupts enabled mask ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -112,7 +106,7 @@ __tx_thread_schedule_loop ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Lockout interrupts and ; transfer control to it. */ ; @@ -121,7 +115,7 @@ __tx_thread_schedule_loop ; /* Setup the current thread pointer. */ ; _tx_thread_current_ptr = _tx_thread_execute_ptr; ; - LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread STR r0, [r1, #0] ; Setup current thread pointer ; ; /* Increment the run count for this thread. */ @@ -135,7 +129,7 @@ __tx_thread_schedule_loop ; /* Setup time-slice, if present. */ ; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; ; - LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice ; variable LDR sp, [r0, #8] ; Switch stack pointers STR r3, [r2, #0] ; Setup time-slice diff --git a/ports/arm11/ac5/src/tx_thread_stack_build.s b/ports/arm11/ac5/src/tx_thread_stack_build.s index 83821335..64482069 100644 --- a/ports/arm11/ac5/src/tx_thread_stack_build.s +++ b/ports/arm11/ac5/src/tx_thread_stack_build.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -38,44 +38,38 @@ CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints en ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function builds a stack frame on the supplied thread's stack. */ ;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ ;/* thread_ptr Pointer to thread control blk */ ;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -83,10 +77,10 @@ CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints en EXPORT _tx_thread_stack_build _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the ARM11 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; a1 (r0) Initial value for a1 diff --git a/ports/arm11/ac5/src/tx_thread_system_return.s b/ports/arm11/ac5/src/tx_thread_system_return.s index 82a1e0c4..37ce7066 100644 --- a/ports/arm11/ac5/src/tx_thread_system_return.s +++ b/ports/arm11/ac5/src/tx_thread_system_return.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -40,50 +40,44 @@ DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled IMPORT _tx_timer_time_slice IMPORT _tx_thread_schedule IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY - IMPORT _tx_execution_thread_exit + IMPORT _tx_execution_thread_exit ENDIF ; ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -96,12 +90,12 @@ _tx_thread_system_return MOV r0, #0 ; Build a solicited stack type MRS r1, CPSR ; Pickup the CPSR STMDB sp!, {r0-r1, r4-r11, lr} ; Save minimal context -; +; ; /* Lockout interrupts. */ ; ORR r2, r1, #DISABLE_INTS ; Build disable interrupt CPSR MSR CPSR_cxsf, r2 ; Disable interrupts - + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; ; /* Call the thread exit function to indicate the thread is no longer executing. */ diff --git a/ports/arm11/ac5/src/tx_thread_vectored_context_save.s b/ports/arm11/ac5/src/tx_thread_vectored_context_save.s index e9ae138a..ca013608 100644 --- a/ports/arm11/ac5/src/tx_thread_vectored_context_save.s +++ b/ports/arm11/ac5/src/tx_thread_vectored_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -45,43 +45,37 @@ DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_vectored_context_save ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) @@ -144,7 +138,7 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Note: Minimal context of interrupted thread is already saved. */ @@ -180,7 +174,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports/arm11/ac5/src/tx_timer_interrupt.s b/ports/arm11/ac5/src/tx_timer_interrupt.s index 9d745e0a..c5b7ee10 100644 --- a/ports/arm11/ac5/src/tx_timer_interrupt.s +++ b/ports/arm11/ac5/src/tx_timer_interrupt.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -44,46 +44,40 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt ARM11/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt ARM11/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -107,7 +101,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CMP r2, #0 ; Is it non-active? BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing @@ -225,13 +219,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CMP r2, #0 ; See if the flag is set BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing ; diff --git a/ports/arm11/gnu/example_build/crt0.S b/ports/arm11/gnu/example_build/crt0.S index aa0f3239..56b6c958 100644 --- a/ports/arm11/gnu/example_build/crt0.S +++ b/ports/arm11/gnu/example_build/crt0.S @@ -26,13 +26,13 @@ _mainCRTStartup: mov a2, #0 /* Second arg: fill value */ mov fp, a2 /* Null frame pointer */ mov r7, a2 /* Null frame pointer for Thumb */ - - ldr a1, .LC1 /* First arg: start of memory block */ - ldr a3, .LC2 - sub a3, a3, a1 /* Third arg: length of block */ - - + ldr a1, .LC1 /* First arg: start of memory block */ + ldr a3, .LC2 + sub a3, a3, a1 /* Third arg: length of block */ + + + bl memset mov r0, #0 /* no arguments */ mov r1, #0 /* no argv either */ @@ -48,15 +48,15 @@ _mainCRTStartup: /* bl init */ mov r0, r4 mov r1, r5 -#endif +#endif bl main bl exit /* Should not return. */ - - /* For Thumb, constants must be after the code since only + + /* For Thumb, constants must be after the code since only positive offsets are supported for PC relative addresses. */ - + .align 0 .LC0: .LC1: diff --git a/ports/arm11/gnu/example_build/reset.S b/ports/arm11/gnu/example_build/reset.S index a11c826a..5d05258b 100644 --- a/ports/arm11/gnu/example_build/reset.S +++ b/ports/arm11/gnu/example_build/reset.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Initialize */ @/** */ @@ -65,11 +65,11 @@ SWI: .word __tx_swi_interrupt @ Software interrupt handler PREFETCH: .word __tx_prefetch_handler @ Prefetch exception handler -ABORT: +ABORT: .word __tx_abort_handler @ Abort exception handler -RESERVED: +RESERVED: .word __tx_reserved_handler @ Reserved exception handler -IRQ: +IRQ: .word __tx_irq_handler @ IRQ interrupt handler FIQ: .word __tx_fiq_handler @ FIQ interrupt handler diff --git a/ports/arm11/gnu/example_build/sample_threadx.c b/ports/arm11/gnu/example_build/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports/arm11/gnu/example_build/sample_threadx.c +++ b/ports/arm11/gnu/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/arm11/gnu/example_build/sample_threadx.ld b/ports/arm11/gnu/example_build/sample_threadx.ld index 3dea4e1c..e940b2b8 100644 --- a/ports/arm11/gnu/example_build/sample_threadx.ld +++ b/ports/arm11/gnu/example_build/sample_threadx.ld @@ -7,7 +7,7 @@ OUTPUT_ARCH(arm) SECTIONS { . = 0x00000000; - + .vectors : {reset.o(.text) } /* Read-only sections, merged into text segment: */ @@ -94,8 +94,8 @@ SECTIONS *(.gnu.linkonce.t*) *(.glue_7t) *(.glue_7) } =0 - .init : - { + .init : + { KEEP (*(.init)) } =0 _etext = .; @@ -120,7 +120,7 @@ SECTIONS .data1 : { *(.data1) } .eh_frame : { KEEP (*(.eh_frame)) } .gcc_except_table : { *(.gcc_except_table) } - .ctors : + .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is @@ -153,9 +153,9 @@ SECTIONS /* We want the small data sections together, so single-instruction offsets can access them all, and initialized data all before uninitialized, so we can shorten the on-disk segment size. */ - .sdata : + .sdata : { - *(.sdata) + *(.sdata) *(.sdata.*) *(.gnu.linkonce.s.*) } @@ -191,7 +191,7 @@ SECTIONS _stack_bottom = ABSOLUTE(.) ; - /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and + /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and SYS stack if nested interrupts are enabled. */ . = ALIGN(8) ; . += 4096 ; diff --git a/ports/arm11/gnu/example_build/tx_initialize_low_level.S b/ports/arm11/gnu/example_build/tx_initialize_low_level.S index f7c4617a..887ae4e0 100644 --- a/ports/arm11/gnu/example_build/tx_initialize_low_level.S +++ b/ports/arm11/gnu/example_build/tx_initialize_low_level.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Initialize */ @/** */ @@ -62,7 +62,7 @@ SYS_STACK_SIZE = 1024 @ System stack size .type $_tx_initialize_low_level,function $_tx_initialize_low_level: BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_initialize_low_level @ Call _tx_initialize_low_level function @@ -72,45 +72,39 @@ $_tx_initialize_low_level: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_initialize_low_level ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level ARM11/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is responsible for any low-level processor */ -@/* initialization, including setting up interrupt vectors, setting */ -@/* up a periodic timer interrupt source, saving the system stack */ -@/* pointer for use in ISR processing later, and finding the first */ -@/* available RAM memory address for tx_application_define. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_initialize_kernel_enter ThreadX entry function */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) @@ -125,7 +119,7 @@ _tx_initialize_low_level: @ LDR r1, =_sp @ Get pointer to stack area -#ifdef TX_ENABLE_IRQ_NESTING +#ifdef TX_ENABLE_IRQ_NESTING @ @ /* Setup the system mode stack for nested interrupt support */ @ @@ -156,7 +150,7 @@ _tx_initialize_low_level: MSR CPSR, r0 @ Enter SVC mode LDR r2, =_stack_bottom @ Pickup stack bottom CMP r3, r2 @ Compare the current stack end with the bottom -_stack_error_loop: +_stack_error_loop: BLT _stack_error_loop @ If the IRQ stack exceeds the stack bottom, just sit here! @ @ /* Save the system stack pointer. */ @@ -208,7 +202,7 @@ __tx_reserved_handler: B __tx_reserved_handler @ Reserved exception handler @ .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -216,17 +210,17 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. In +@ interrupt, and all C scratch registers are available for use. In @ addition, IRQ interrupts may be re-enabled - with certain restrictions - @ if nested IRQ interrupts are desired. Interrupts may be re-enabled over -@ small code sequences where lr is saved before enabling interrupts and +@ small code sequences where lr is saved before enabling interrupts and @ restored after interrupts are again disabled. */ @ -@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start @ from IRQ mode with interrupts disabled. This routine switches to the -@ system mode and returns with IRQ interrupts enabled. -@ -@ NOTE: It is very important to ensure all IRQ interrupts are cleared +@ system mode and returns with IRQ interrupts enabled. +@ +@ NOTE: It is very important to ensure all IRQ interrupts are cleared @ prior to enabling nested IRQ interrupts. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -240,7 +234,7 @@ __tx_irq_processing_return: @ @ @ /* If interrupt nesting was started earlier, the end of interrupt nesting -@ service must be called before returning to _tx_thread_context_restore. +@ service must be called before returning to _tx_thread_context_restore. @ This routine returns in processing in IRQ mode with interrupts disabled. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -256,28 +250,28 @@ __tx_irq_processing_return: @__tx_example_vectored_irq_handler: @ @ -@ /* Save initial context and call context save to prepare for +@ /* Save initial context and call context save to prepare for @ vectored ISR execution. */ @ @ STMDB sp!, {r0-r3} @ Save some scratch registers @ MRS r0, SPSR @ Pickup saved SPSR -@ SUB lr, lr, #4 @ Adjust point of interrupt +@ SUB lr, lr, #4 @ Adjust point of interrupt @ STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers @ BL _tx_thread_vectored_context_save @ Vectored context save @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. In +@ interrupt, and all C scratch registers are available for use. In @ addition, IRQ interrupts may be re-enabled - with certain restrictions - @ if nested IRQ interrupts are desired. Interrupts may be re-enabled over -@ small code sequences where lr is saved before enabling interrupts and +@ small code sequences where lr is saved before enabling interrupts and @ restored after interrupts are again disabled. */ @ @ -@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start @ from IRQ mode with interrupts disabled. This routine switches to the -@ system mode and returns with IRQ interrupts enabled. -@ -@ NOTE: It is very important to ensure all IRQ interrupts are cleared +@ system mode and returns with IRQ interrupts enabled. +@ +@ NOTE: It is very important to ensure all IRQ interrupts are cleared @ prior to enabling nested IRQ interrupts. */ @#ifdef TX_ENABLE_IRQ_NESTING @ BL _tx_thread_irq_nesting_start @@ -286,7 +280,7 @@ __tx_irq_processing_return: @ /* Application IRQ handlers can be called here! */ @ @ /* If interrupt nesting was started earlier, the end of interrupt nesting -@ service must be called before returning to _tx_thread_context_restore. +@ service must be called before returning to _tx_thread_context_restore. @ This routine returns in processing in IRQ mode with interrupts disabled. */ @#ifdef TX_ENABLE_IRQ_NESTING @ BL _tx_thread_irq_nesting_end @@ -308,11 +302,11 @@ __tx_fiq_processing_return: @ /* At this point execution is still in the FIQ mode. The CPSR, point of @ interrupt, and all C scratch registers are available for use. */ @ -@ /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +@ /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start @ from FIQ mode with interrupts disabled. This routine switches to the -@ system mode and returns with FIQ interrupts enabled. +@ system mode and returns with FIQ interrupts enabled. @ -@ NOTE: It is very important to ensure all FIQ interrupts are cleared +@ NOTE: It is very important to ensure all FIQ interrupts are cleared @ prior to enabling nested FIQ interrupts. */ #ifdef TX_ENABLE_FIQ_NESTING BL _tx_thread_fiq_nesting_start diff --git a/ports/arm11/gnu/inc/tx_port.h b/ports/arm11/gnu/inc/tx_port.h index 65ffe076..259ad092 100644 --- a/ports/arm11/gnu/inc/tx_port.h +++ b/ports/arm11/gnu/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h ARM11/GNU */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h ARM11/GNU */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -75,7 +67,7 @@ #include -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -111,12 +103,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -126,8 +118,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -174,7 +166,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -186,13 +178,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -206,11 +198,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -218,8 +210,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -246,24 +238,24 @@ typedef unsigned short USHORT; #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ - + #if __TARGET_ARCH_ARM > 4 #ifndef __thumb__ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ asm volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); \ - b = 31 - b; + b = 31 - b; #endif #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -307,8 +299,8 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARM11/GNU Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARM11/GNU Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/arm11/gnu/readme_threadx.txt b/ports/arm11/gnu/readme_threadx.txt index d7300854..92a7c16d 100644 --- a/ports/arm11/gnu/readme_threadx.txt +++ b/ports/arm11/gnu/readme_threadx.txt @@ -1,55 +1,55 @@ - Microsoft's Azure RTOS ThreadX for ARM11 + Microsoft's Azure RTOS ThreadX for ARM11 Using the GNU Tools 1. Building the ThreadX run-time Library -First make sure you are in the "example_build" directory. Also, make sure that -you have setup your path and other environment variables necessary for the GNU -development environment. +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the GNU +development environment. -At this point you may run the build_threadx.bat batch file. This will build the -ThreadX run-time environment in the "example_build" directory. +At this point you may run the build_threadx.bat batch file. This will build the +ThreadX run-time environment in the "example_build" directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. 2. Demonstration System -Building the demonstration is easy; simply execute the build_threadx_sample.bat -batch file while inside the "example_build" directory. +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with TX.A. The resulting file DEMO is a binary file +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with TX.A. The resulting file DEMO is a binary file that can be downloaded and executed. 3. System Initialization -The entry point in ThreadX for the ARM11 using GNU tools is at label _start. +The entry point in ThreadX for the ARM11 using GNU tools is at label _start. This is defined within the modified version of the GNU startup code - crt0.S. -The ThreadX tx_initialize_low_level.S file is responsible for setting up various -system data structures, the interrupt vectors, and a periodic timer interrupt source. -By default, the vector area is defined to be located at the "__vectors" label, -which is defined in reset.S. This area is typically located at 0. In situations -where this is impossible, the vectors at the "__vectors" label should be copied +The ThreadX tx_initialize_low_level.S file is responsible for setting up various +system data structures, the interrupt vectors, and a periodic timer interrupt source. +By default, the vector area is defined to be located at the "__vectors" label, +which is defined in reset.S. This area is typically located at 0. In situations +where this is impossible, the vectors at the "__vectors" label should be copied to address 0. -This is also where initialization of a periodic timer interrupt source should take +This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level defines the first available address -for use by the application, which is supplied as the sole input parameter +In addition, _tx_initialize_low_level defines the first available address +for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 4. Assembler / Compiler Switches -The following are compiler switches used in building the demonstration +The following are compiler switches used in building the demonstration system: Compiler/Assembler Meaning @@ -73,164 +73,164 @@ Application Defines ( -D option) ThreadX assembly files. If used, it should be used on all assembly files and the generic C source of - ThreadX should be compiled with + ThreadX should be compiled with TX_ENABLE_FIQ_SUPPORT defined as well. TX_ENABLE_IRQ_NESTING This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.S. TX_ENABLE_FIQ_NESTING This assembler define enables FIQ - nested support. If FIQ nested + nested support. If FIQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.S. In addition, IRQ nesting should also be enabled. TX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ interrupt handling in the ThreadX - generic C source. This define + generic C source. This define should also be used in conjunction with the corresponding assembler - define. + define. TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - TX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. 5. Register Usage and Stack Frames -The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -248,52 +248,52 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for ARM11 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The ARM11 vectors start at address zero. The demonstration system startup -reset.S file contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +reset.S file contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs -ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -301,7 +301,7 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -314,7 +314,7 @@ __tx_irq_processing_return: 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_example_handler @@ -324,12 +324,12 @@ __tx_irq_example_handler: STMDB sp!, {r0-r3} @ Save some scratch registers MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers BL _tx_thread_vectored_context_save @ Call the vectored IRQ context save @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -346,22 +346,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.S. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables -nesting by disabling IRQ interrupts and switching back to IRQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -369,10 +369,10 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* Enable nested IRQ interrupts. NOTE: Since this service returns -@ with IRQ interrupts enabled, all IRQ interrupt sources must be +@ with IRQ interrupts enabled, all IRQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start -@ +@ @ /* Application ISR call(s) go here! */ @ @ /* Disable nested IRQ interrupts. The mode is switched back to @@ -385,12 +385,12 @@ __tx_irq_processing_return: 7.3 FIQ Interrupts -By default, ARM7 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, ARM7 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.S. @@ -399,7 +399,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.S. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.S: @@ -427,18 +427,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.S. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -454,7 +454,7 @@ __tx_fiq_processing_return: @ interrupt, and all C scratch registers are available for use. */ @ @ /* Enable nested FIQ interrupts. NOTE: Since this service returns -@ with FIQ interrupts enabled, all FIQ interrupt sources must be +@ with FIQ interrupts enabled, all FIQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start @ @@ -470,12 +470,12 @@ __tx_fiq_processing_return: 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer -interrupt source, these services are not functional but the remainder of +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of ThreadX will still run. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.S for the demonstration system. diff --git a/ports/arm11/gnu/src/tx_thread_context_restore.S b/ports/arm11/gnu/src/tx_thread_context_restore.S index 6a270b66..74fb495f 100644 --- a/ports/arm11/gnu/src/tx_thread_context_restore.S +++ b/ports/arm11/gnu/src/tx_thread_context_restore.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -43,51 +43,42 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @ @/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore @ since it will never be called 16-bit mode. */ -@ +@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_context_restore ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function restores the interrupt context if it is processing a */ -@/* nested interrupt. If not, it returns to the interrupt thread if no */ -@/* preemption is necessary. Otherwise, if preemption is necessary or */ -@/* if no thread was running, the function returns to the scheduler. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling routine */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs Interrupt Service Routines */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) @@ -115,13 +106,13 @@ _tx_thread_context_restore: LDR r3, =_tx_thread_system_state @ Pickup address of system state variable LDR r2, [r3] @ Pickup system state SUB r2, r2, #1 @ Decrement the counter - STR r2, [r3] @ Store the counter + STR r2, [r3] @ Store the counter CMP r2, #0 @ Was this the first interrupt? BEQ __tx_thread_not_nested_restore @ If so, not a nested restore @ @ /* Interrupts are nested. */ @ -@ /* Just recover the saved registers and return to the point of +@ /* Just recover the saved registers and return to the point of @ interrupt. */ @ LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs diff --git a/ports/arm11/gnu/src/tx_thread_context_save.S b/ports/arm11/gnu/src/tx_thread_context_save.S index 3fe539d2..c8d7e503 100644 --- a/ports/arm11/gnu/src/tx_thread_context_save.S +++ b/ports/arm11/gnu/src/tx_thread_context_save.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -36,50 +36,41 @@ DISABLE_INTS = 0x80 @ IRQ interrupts disabled @ @/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save @ since it will never be called 16-bit mode. */ -@ +@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_context_save ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function saves the context of an executing thread in the */ -@/* beginning of interrupt processing. The function also ensures that */ -@/* the system stack is used upon return to the calling ISR. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) @@ -95,7 +86,7 @@ _tx_thread_context_save: @ if (_tx_thread_system_state++) @ { @ - STMDB sp!, {r0-r3} @ Save some working registers + STMDB sp!, {r0-r3} @ Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT MRS r0, CPSR @ Pickup the CPSR ORR r0, r0, #DISABLE_INTS @ Build disable interrupt CPSR @@ -115,7 +106,7 @@ _tx_thread_context_save: @ calling ISR. */ @ MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other registers @ @ /* Return to the ISR. */ @@ -131,7 +122,7 @@ _tx_thread_context_save: POP {lr} @ Recover ISR lr #endif - B __tx_irq_processing_return @ Continue IRQ processing + B __tx_irq_processing_return @ Continue IRQ processing @ __tx_thread_not_nested_save: @ } @@ -145,13 +136,13 @@ __tx_thread_not_nested_save: LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr LDR r0, [r1] @ Pickup current thread pointer CMP r0, #0 @ Is it NULL? - BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in @ scheduling loop - nothing needs saving! @ @ /* Save minimal context of interrupted thread. */ @ MRS r2, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} @ Store other registers @ @ /* Save the current stack pointer in the thread's control block. */ @@ -171,7 +162,7 @@ __tx_thread_not_nested_save: POP {lr} @ Recover ISR lr #endif - B __tx_irq_processing_return @ Continue IRQ processing + B __tx_irq_processing_return @ Continue IRQ processing @ @ } @ else @@ -181,7 +172,7 @@ __tx_thread_idle_system_save: @ @ /* Interrupt occurred in the scheduling loop. */ @ -@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ @ processing. */ @ MOV r10, #0 @ Clear stack limit @@ -196,7 +187,7 @@ __tx_thread_idle_system_save: #endif ADD sp, sp, #16 @ Recover saved registers - B __tx_irq_processing_return @ Continue IRQ processing + B __tx_irq_processing_return @ Continue IRQ processing @ @ } @} diff --git a/ports/arm11/gnu/src/tx_thread_fiq_context_restore.S b/ports/arm11/gnu/src/tx_thread_fiq_context_restore.S index 3d3dd37a..5d6ed149 100644 --- a/ports/arm11/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/arm11/gnu/src/tx_thread_fiq_context_restore.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -25,7 +25,7 @@ SVC_MODE = 0xD3 @ SVC mode FIQ_MODE = 0xD1 @ FIQ mode DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts -MODE_MASK = 0x1F @ Mode mask +MODE_MASK = 0x1F @ Mode mask THUMB_MASK = 0x20 @ Thumb bit mask IRQ_MODE_BITS = 0x12 @ IRQ mode bits SVC_MODE_BITS = 0x13 @ SVC mode value @@ -47,47 +47,38 @@ SVC_MODE_BITS = 0x13 @ SVC mode value .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_fiq_context_restore ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_restore ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function restores the fiq interrupt context when processing a */ -@/* nested interrupt. If not, it returns to the interrupt thread if no */ -@/* preemption is necessary. Otherwise, if preemption is necessary or */ -@/* if no thread was running, the function returns to the scheduler. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling routine */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* FIQ ISR Interrupt Service Routines */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function restores the fiq interrupt context when processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* FIQ ISR Interrupt Service Routines */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_context_restore(VOID) @@ -116,13 +107,13 @@ _tx_thread_fiq_context_restore: LDR r3, =_tx_thread_system_state @ Pickup address of system state variable LDR r2, [r3] @ Pickup system state SUB r2, r2, #1 @ Decrement the counter - STR r2, [r3] @ Store the counter + STR r2, [r3] @ Store the counter CMP r2, #0 @ Was this the first interrupt? BEQ __tx_thread_fiq_not_nested_restore @ If so, not a nested restore @ @ /* Interrupts are nested. */ @ -@ /* Just recover the saved registers and return to the point of +@ /* Just recover the saved registers and return to the point of @ interrupt. */ @ LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs @@ -213,7 +204,7 @@ __tx_thread_fiq_preempt_restore: BEQ __tx_thread_fiq_dont_save_ts @ No, don't save it @ @ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; -@ _tx_timer_time_slice = 0; +@ _tx_timer_time_slice = 0; @ STR r2, [r0, #24] @ Save thread's time-slice MOV r2, #0 @ Clear value diff --git a/ports/arm11/gnu/src/tx_thread_fiq_context_save.S b/ports/arm11/gnu/src/tx_thread_fiq_context_save.S index 8dc69191..93b33309 100644 --- a/ports/arm11/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/arm11/gnu/src/tx_thread_fiq_context_save.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -34,46 +34,37 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_fiq_context_save ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_save ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function saves the context of an executing thread in the */ -@/* beginning of interrupt processing. The function also ensures that */ -@/* the system stack is used upon return to the calling ISR. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @ VOID _tx_thread_fiq_context_save(VOID) @@ -89,7 +80,7 @@ _tx_thread_fiq_context_save: @ if (_tx_thread_system_state++) @ { @ - STMDB sp!, {r0-r3} @ Save some working registers + STMDB sp!, {r0-r3} @ Save some working registers LDR r3, =_tx_thread_system_state @ Pickup address of system state variable LDR r2, [r3] @ Pickup system state CMP r2, #0 @ Is this the first interrupt? @@ -104,7 +95,7 @@ _tx_thread_fiq_context_save: @ calling ISR. */ @ MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other registers @ @ /* Return to the ISR. */ @@ -120,38 +111,38 @@ _tx_thread_fiq_context_save: POP {lr} @ Recover ISR lr #endif - B __tx_fiq_processing_return @ Continue FIQ processing + B __tx_fiq_processing_return @ Continue FIQ processing @ __tx_thread_fiq_not_nested_save: -@ } +@ } @ @ /* Otherwise, not nested, check to see if a thread was running. */ @ else if (_tx_thread_current_ptr) -@ { +@ { @ ADD r2, r2, #1 @ Increment the interrupt counter STR r2, [r3] @ Store it back in the variable LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr LDR r0, [r1] @ Pickup current thread pointer CMP r0, #0 @ Is it NULL? - BEQ __tx_thread_fiq_idle_system_save @ If so, interrupt occurred in -@ @ scheduling loop - nothing needs saving! + BEQ __tx_thread_fiq_idle_system_save @ If so, interrupt occurred in +@ @ scheduling loop - nothing needs saving! @ @ /* Save minimal context of interrupted thread. */ @ MRS r2, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r2, lr} @ Store other registers, Note that we don't -@ @ need to save sl and ip since FIQ has -@ @ copies of these registers. Nested +@ @ need to save sl and ip since FIQ has +@ @ copies of these registers. Nested @ @ interrupt processing does need to save @ @ these registers. @ @ /* Save the current stack pointer in the thread's control block. */ -@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; @ @ /* Switch to the system stack. */ -@ sp = _tx_thread_system_stack_ptr; +@ sp = _tx_thread_system_stack_ptr; @ MOV r10, #0 @ Clear stack limit @@ -164,7 +155,7 @@ __tx_thread_fiq_not_nested_save: POP {lr} @ Recover ISR lr #endif - B __tx_fiq_processing_return @ Continue FIQ processing + B __tx_fiq_processing_return @ Continue FIQ processing @ @ } @ else @@ -184,16 +175,16 @@ __tx_thread_fiq_idle_system_save: #endif @ @ /* Not much to do here, save the current SPSR and LR for possible -@ use in IRQ interrupted in idle system conditions, and return to +@ use in IRQ interrupted in idle system conditions, and return to @ FIQ interrupt processing. */ @ MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, lr} @ Store other registers that will get used -@ @ or stripped off the stack in context -@ @ restore - B __tx_fiq_processing_return @ Continue FIQ processing +@ @ or stripped off the stack in context +@ @ restore + B __tx_fiq_processing_return @ Continue FIQ processing @ @ } -@} +@} diff --git a/ports/arm11/gnu/src/tx_thread_fiq_nesting_end.S b/ports/arm11/gnu/src/tx_thread_fiq_nesting_end.S index 82362bbc..1e9ba513 100644 --- a/ports/arm11/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/arm11/gnu/src/tx_thread_fiq_nesting_end.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -27,7 +27,7 @@ DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts #else DISABLE_INTS = 0x80 @ Disable IRQ interrupts #endif -MODE_MASK = 0x1F @ Mode mask +MODE_MASK = 0x1F @ Mode mask FIQ_MODE_BITS = 0x11 @ FIQ mode bits @ @ @@ -37,54 +37,45 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_fiq_nesting_end ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_end ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from FIQ mode after */ -@/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ -@/* processing from system mode back to FIQ mode prior to the ISR */ -@/* calling _tx_thread_fiq_context_restore. Note that this function */ -@/* assumes the system stack pointer is in the same position after */ -@/* nesting start function was called. */ -@/* */ -@/* This function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with FIQ interrupts disabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +@/* processing from system mode back to FIQ mode prior to the ISR */ +@/* calling _tx_thread_fiq_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_end(VOID) @@ -96,7 +87,7 @@ _tx_thread_fiq_nesting_end: MRS r0, CPSR @ Pickup the CPSR ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value MSR CPSR_cxsf, r0 @ Disable interrupts - LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for @ 8-byte alignment logic) BIC r0, r0, #MODE_MASK @ Clear mode bits ORR r0, r0, #FIQ_MODE_BITS @ Build IRQ mode CPSR diff --git a/ports/arm11/gnu/src/tx_thread_fiq_nesting_start.S b/ports/arm11/gnu/src/tx_thread_fiq_nesting_start.S index 5a6b6e1b..2f7f4f52 100644 --- a/ports/arm11/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/arm11/gnu/src/tx_thread_fiq_nesting_start.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -33,51 +33,42 @@ SYS_MODE_BITS = 0x1F @ System mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_fiq_nesting_start ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_start ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from FIQ mode after */ -@/* _tx_thread_fiq_context_save has been called and switches the FIQ */ -@/* processing to the system mode so nested FIQ interrupt processing */ -@/* is possible (system mode has its own "lr" register). Note that */ -@/* this function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with FIQ interrupts enabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +@/* processing to the system mode so nested FIQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/arm11/gnu/src/tx_thread_interrupt_control.S b/ports/arm11/gnu/src/tx_thread_interrupt_control.S index ecc9326d..dd8b127c 100644 --- a/ports/arm11/gnu/src/tx_thread_interrupt_control.S +++ b/ports/arm11/gnu/src/tx_thread_interrupt_control.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -35,7 +35,7 @@ INT_MASK = 0x03F $_tx_thread_interrupt_control: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_interrupt_control @ Call _tx_thread_interrupt_control function @@ -45,45 +45,36 @@ $_tx_thread_interrupt_control: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_interrupt_control ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is responsible for changing the interrupt lockout */ -@/* posture of the system. */ -@/* */ -@/* INPUT */ -@/* */ -@/* new_posture New interrupt lockout posture */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/arm11/gnu/src/tx_thread_interrupt_disable.S b/ports/arm11/gnu/src/tx_thread_interrupt_disable.S index f51c2238..fb369d0b 100644 --- a/ports/arm11/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/arm11/gnu/src/tx_thread_interrupt_disable.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -38,7 +38,7 @@ DISABLE_INTS = 0x80 @ IRQ interrupts disabled $_tx_thread_interrupt_disable: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_interrupt_disable @ Call _tx_thread_interrupt_disable function @@ -48,44 +48,35 @@ $_tx_thread_interrupt_disable: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_interrupt_disable ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_disable ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is responsible for disabling interrupts */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function is responsible for disabling interrupts */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_disable(void) diff --git a/ports/arm11/gnu/src/tx_thread_interrupt_restore.S b/ports/arm11/gnu/src/tx_thread_interrupt_restore.S index 8506be1b..78c85f91 100644 --- a/ports/arm11/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/arm11/gnu/src/tx_thread_interrupt_restore.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -31,7 +31,7 @@ $_tx_thread_interrupt_restore: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_interrupt_restore @ Call _tx_thread_interrupt_restore function @@ -41,45 +41,36 @@ $_tx_thread_interrupt_restore: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_interrupt_restore ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_restore ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ +@/* */ @/* This function is responsible for restoring interrupts to the state */ @/* returned by a previous _tx_thread_interrupt_disable call. */ -@/* */ -@/* INPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* INPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/arm11/gnu/src/tx_thread_irq_nesting_end.S b/ports/arm11/gnu/src/tx_thread_irq_nesting_end.S index 649bbbb0..26504a38 100644 --- a/ports/arm11/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/arm11/gnu/src/tx_thread_irq_nesting_end.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -27,7 +27,7 @@ DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts #else DISABLE_INTS = 0x80 @ Disable IRQ interrupts #endif -MODE_MASK = 0x1F @ Mode mask +MODE_MASK = 0x1F @ Mode mask IRQ_MODE_BITS = 0x12 @ IRQ mode bits @ @ @@ -37,54 +37,45 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_irq_nesting_end ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_end ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from IRQ mode after */ -@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -@/* processing from system mode back to IRQ mode prior to the ISR */ -@/* calling _tx_thread_context_restore. Note that this function */ -@/* assumes the system stack pointer is in the same position after */ -@/* nesting start function was called. */ -@/* */ -@/* This function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with IRQ interrupts disabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +@/* processing from system mode back to IRQ mode prior to the ISR */ +@/* calling _tx_thread_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_end(VOID) @@ -96,7 +87,7 @@ _tx_thread_irq_nesting_end: MRS r0, CPSR @ Pickup the CPSR ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value MSR CPSR_cxsf, r0 @ Disable interrupts - LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for @ 8-byte alignment logic) BIC r0, r0, #MODE_MASK @ Clear mode bits ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR diff --git a/ports/arm11/gnu/src/tx_thread_irq_nesting_start.S b/ports/arm11/gnu/src/tx_thread_irq_nesting_start.S index ee949845..12bedd93 100644 --- a/ports/arm11/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/arm11/gnu/src/tx_thread_irq_nesting_start.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -33,51 +33,42 @@ SYS_MODE_BITS = 0x1F @ System mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_irq_nesting_start ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_start ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from IRQ mode after */ -@/* _tx_thread_context_save has been called and switches the IRQ */ -@/* processing to the system mode so nested IRQ interrupt processing */ -@/* is possible (system mode has its own "lr" register). Note that */ -@/* this function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with IRQ interrupts enabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_context_save has been called and switches the IRQ */ +@/* processing to the system mode so nested IRQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/arm11/gnu/src/tx_thread_schedule.S b/ports/arm11/gnu/src/tx_thread_schedule.S index 9350540c..2901fbef 100644 --- a/ports/arm11/gnu/src/tx_thread_schedule.S +++ b/ports/arm11/gnu/src/tx_thread_schedule.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -45,7 +45,7 @@ ENABLE_INTS = 0x80 @ IRQ Interrupts enabled mask $_tx_thread_schedule: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_schedule @ Call _tx_thread_schedule function @@ -55,48 +55,39 @@ $_tx_thread_schedule: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_schedule ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_schedule ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function waits for a thread control block pointer to appear in */ -@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -@/* in the variable, the corresponding thread is resumed. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_initialize_kernel_enter ThreadX entry function */ -@/* _tx_thread_system_return Return to system from thread */ -@/* _tx_thread_context_restore Restore thread's context */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function waits for a thread control block pointer to appear in */ +@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +@/* in the variable, the corresponding thread is resumed. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* _tx_thread_system_return Return to system from thread */ +@/* _tx_thread_context_restore Restore thread's context */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) @@ -124,7 +115,7 @@ __tx_thread_schedule_loop: @ @ } @ while(_tx_thread_execute_ptr == TX_NULL); -@ +@ @ /* Yes! We have a thread to execute. Lockout interrupts and @ transfer control to it. */ @ @@ -133,7 +124,7 @@ __tx_thread_schedule_loop: @ /* Setup the current thread pointer. */ @ _tx_thread_current_ptr = _tx_thread_execute_ptr; @ - LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread STR r0, [r1] @ Setup current thread pointer @ @ /* Increment the run count for this thread. */ @@ -147,7 +138,7 @@ __tx_thread_schedule_loop: @ /* Setup time-slice, if present. */ @ _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; @ - LDR r2, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r2, =_tx_timer_time_slice @ Pickup address of time-slice @ variable LDR sp, [r0, #8] @ Switch stack pointers STR r3, [r2] @ Setup time-slice diff --git a/ports/arm11/gnu/src/tx_thread_stack_build.S b/ports/arm11/gnu/src/tx_thread_stack_build.S index 7f156ee0..989916ca 100644 --- a/ports/arm11/gnu/src/tx_thread_stack_build.S +++ b/ports/arm11/gnu/src/tx_thread_stack_build.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -42,7 +42,7 @@ CPSR_MASK = 0x9F @ Mask initial CPSR, IRQ interru .type $_tx_thread_stack_build,function $_tx_thread_stack_build: BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_stack_build @ Call _tx_thread_stack_build function @@ -52,47 +52,38 @@ $_tx_thread_stack_build: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_stack_build ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ +@/* */ @/* This function builds a stack frame on the supplied thread's stack. */ @/* The stack frame results in a fake interrupt return to the supplied */ -@/* function pointer. */ -@/* */ -@/* INPUT */ -@/* */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ @/* thread_ptr Pointer to thread control blk */ @/* function_ptr Pointer to return function */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_thread_create Create thread service */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -101,10 +92,10 @@ $_tx_thread_stack_build: .type _tx_thread_stack_build,function _tx_thread_stack_build: @ -@ +@ @ /* Build a fake interrupt frame. The form of the fake interrupt stack @ on theARM11 should look like the following after it is built: -@ +@ @ Stack Top: 1 Interrupt stack frame type @ CPSR Initial value for CPSR @ a1 (r0) Initial value for a1 diff --git a/ports/arm11/gnu/src/tx_thread_system_return.S b/ports/arm11/gnu/src/tx_thread_system_return.S index 1c26a7a0..c15ae266 100644 --- a/ports/arm11/gnu/src/tx_thread_system_return.S +++ b/ports/arm11/gnu/src/tx_thread_system_return.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -48,7 +48,7 @@ DISABLE_INTS = 0x80 @ IRQ interrupts disabled $_tx_thread_system_return: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_system_return @ Call _tx_thread_system_return function @@ -58,47 +58,38 @@ $_tx_thread_system_return: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_system_return ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is target processor specific. It is used to transfer */ -@/* control from a thread back to the ThreadX system. Only a */ -@/* minimal context is saved since the compiler assumes temp registers */ -@/* are going to get slicked by a function call anyway. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling loop */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX components */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ @/* */ @/**************************************************************************/ @VOID _tx_thread_system_return(VOID) @@ -112,12 +103,12 @@ _tx_thread_system_return: MOV r0, #0 @ Build a solicited stack type MRS r1, CPSR @ Pickup the CPSR STMDB sp!, {r0-r1, r4-r11, lr} @ Save minimal context -@ +@ @ /* Lockout interrupts. */ @ ORR r2, r1, #DISABLE_INTS @ Build disable interrupt CPSR MSR CPSR_cxsf, r2 @ Disable interrupts - + #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY @ @ /* Call the thread exit function to indicate the thread is no longer executing. */ diff --git a/ports/arm11/gnu/src/tx_thread_vectored_context_save.S b/ports/arm11/gnu/src/tx_thread_vectored_context_save.S index 23f82007..391cf717 100644 --- a/ports/arm11/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/arm11/gnu/src/tx_thread_vectored_context_save.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -37,50 +37,41 @@ DISABLE_INTS = 0x80 @ IRQ interrupts disabled @ @/* No 16-bit Thumb mode veneer code is needed for _tx_thread_vectored_context_save @ since it will never be called 16-bit mode. */ -@ +@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_vectored_context_save ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_vectored_context_save ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function saves the context of an executing thread in the */ -@/* beginning of interrupt processing. The function also ensures that */ -@/* the system stack is used upon return to the calling ISR. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_vectored_context_save(VOID) @@ -140,7 +131,7 @@ __tx_thread_not_nested_save: LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr LDR r0, [r1, #0] @ Pickup current thread pointer CMP r0, #0 @ Is it NULL? - BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in @ scheduling loop - nothing needs saving! @ @ /* Note: Minimal context of interrupted thread is already saved. */ @@ -172,7 +163,7 @@ __tx_thread_idle_system_save: @ @ /* Interrupt occurred in the scheduling loop. */ @ -@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ @ processing. */ @ MOV r10, #0 @ Clear stack limit diff --git a/ports/arm11/gnu/src/tx_timer_interrupt.S b/ports/arm11/gnu/src/tx_timer_interrupt.S index 137c5883..1236ec49 100644 --- a/ports/arm11/gnu/src/tx_timer_interrupt.S +++ b/ports/arm11/gnu/src/tx_timer_interrupt.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Timer */ @/** */ @@ -48,7 +48,7 @@ .type $_tx_timer_interrupt,function $_tx_timer_interrupt: BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_timer_interrupt @ Call _tx_timer_interrupt function @@ -58,49 +58,40 @@ $_tx_timer_interrupt: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_timer_interrupt ARM11/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt ARM11/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function processes the hardware timer interrupt. This */ -@/* processing includes incrementing the system clock and checking for */ -@/* time slice and/or timer expiration. If either is found, the */ -@/* interrupt context save/restore functions are called along with the */ -@/* expiration functions. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_time_slice Time slice interrupted thread */ -@/* _tx_timer_expiration_process Timer expiration processing */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* interrupt vector */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) @@ -125,7 +116,7 @@ _tx_timer_interrupt: @ if (_tx_timer_time_slice) @ { @ - LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice LDR r2, [r3] @ Pickup time-slice CMP r2, #0 @ Is it non-active? BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing @@ -243,7 +234,7 @@ __tx_timer_dont_activate: @ if (_tx_timer_expired_time_slice) @ { @ - LDR r3, =_tx_timer_expired_time_slice @ Pickup address of time-slice expired + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of time-slice expired LDR r2, [r3] @ Pickup the actual flag CMP r2, #0 @ See if the flag is set BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing diff --git a/ports/arm11/iar/example_build/cstartup.s b/ports/arm11/iar/example_build/cstartup.s index b95efc0e..3da2b79d 100644 --- a/ports/arm11/iar/example_build/cstartup.s +++ b/ports/arm11/iar/example_build/cstartup.s @@ -1,7 +1,7 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; -;; Part one of the system initialization code, +;; Part one of the system initialization code, ;; contains low-level ;; initialization. ;; @@ -71,13 +71,13 @@ FIQ_Addr: DCD __tx_fiq_handler SECTION .text:CODE:NOROOT(2) -; PUBLIC ?cstartup +; PUBLIC ?cstartup EXTERN ?main REQUIRE __vector - ARM - -__iar_program_start: + ARM + +__iar_program_start: ?cstartup: ; diff --git a/ports/arm11/iar/example_build/sample_threadx.c b/ports/arm11/iar/example_build/sample_threadx.c index a57d908d..f9d0e94a 100644 --- a/ports/arm11/iar/example_build/sample_threadx.c +++ b/ports/arm11/iar/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -85,42 +85,42 @@ CHAR *pointer; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -128,23 +128,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -247,11 +247,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -310,7 +310,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -363,7 +363,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/arm11/iar/example_build/tx_initialize_low_level.s b/ports/arm11/iar/example_build/tx_initialize_low_level.s index 7242cfe4..61d554bc 100644 --- a/ports/arm11/iar/example_build/tx_initialize_low_level.s +++ b/ports/arm11/iar/example_build/tx_initialize_low_level.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -62,7 +62,7 @@ SYS_MODE DEFINE 0xDF ; Disable irq,fiq SYS mode ; ; ; -;/* Define the FREE_MEM segment that will specify where free memory is +;/* Define the FREE_MEM segment that will specify where free memory is ; defined. This must also be located in at the end of other RAM segments ; in the linker control file. The value of this segment is what is passed ; to tx_application_define. */ @@ -75,47 +75,41 @@ __tx_free_memory_start ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) ;{ RSEG .text:CODE:NOROOT(2) @@ -146,7 +140,7 @@ _tx_initialize_low_level ; LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address STR r0, [r2, #0] ; Save first free memory address -; +; ; /* Setup Timer for periodic interrupts. */ ; ; /* Done, return to caller. */ @@ -188,7 +182,7 @@ __tx_reserved_handler RSEG .text:CODE:NOROOT(2) PUBLIC __tx_irq_handler RSEG .text:CODE:NOROOT(2) - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -196,17 +190,17 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -221,7 +215,7 @@ __tx_irq_processing_return ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -240,22 +234,22 @@ __tx_irq_processing_return ; /* Jump to context save to save system context. */ ; STMDB sp!, {r0-r3} ; Save some scratch registers ; MRS r0, SPSR ; Pickup saved SPSR -; SUB lr, lr, #4 ; Adjust point of interrupt +; SUB lr, lr, #4 ; Adjust point of interrupt ; STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; BL _tx_thread_vectored_context_save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ;#ifdef TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_start @@ -264,7 +258,7 @@ __tx_irq_processing_return ; /* Application IRQ handler is called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ;#ifdef TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_end @@ -288,11 +282,11 @@ __tx_fiq_processing_return ; /* At this point execution is still in the FIQ mode. The CPSR, point of ; interrupt, and all C scratch registers are available for use. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start ; from FIQ mode with interrupts disabled. This routine switches to the -; system mode and returns with FIQ interrupts enabled. +; system mode and returns with FIQ interrupts enabled. ; -; NOTE: It is very important to ensure all FIQ interrupts are cleared +; NOTE: It is very important to ensure all FIQ interrupts are cleared ; prior to enabling nested FIQ interrupts. */ #ifdef TX_ENABLE_FIQ_NESTING BL _tx_thread_fiq_nesting_start diff --git a/ports/arm11/iar/inc/tx_port.h b/ports/arm11/iar/inc/tx_port.h index 3f965ba3..52b43a86 100644 --- a/ports/arm11/iar/inc/tx_port.h +++ b/ports/arm11/iar/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,38 +21,29 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h ARM11/IAR */ -/* 6.1.6 */ +/**************************************************************************/ /* */ -/* AUTHOR */ -/* */ -/* William E. Lamie, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* */ -/**************************************************************************/ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h ARM11/IAR */ +/* 6.1.6 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/**************************************************************************/ #ifndef TX_PORT_H #define TX_PORT_H @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -79,7 +71,7 @@ #endif -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -115,12 +107,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -130,8 +122,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -188,7 +180,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -202,17 +194,17 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -226,11 +218,11 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -240,23 +232,23 @@ ULONG _tx_misra_time_stamp_get(VOID); #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #if (__VER__ < 8000000) -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #endif #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -284,8 +276,8 @@ void __iar_Initlocks(void); #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -296,22 +288,22 @@ void __iar_Initlocks(void); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (UINT) __CLZ(m); \ - b = 31 - b; + b = 31 - b; #endif #endif #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ /* First, check and see what mode the file is being compiled in. The IAR compiler - defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode + defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode is present. If ARM 32-bit mode is present, the fast CPSR manipulation macros are available. Otherwise, if Thumb mode is present, we must use function calls. */ @@ -373,8 +365,8 @@ void _tx_thread_interrupt_restore(UINT old_posture); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARM11/IAR Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARM11/IAR Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/arm11/iar/readme_threadx.txt b/ports/arm11/iar/readme_threadx.txt index fbe7deeb..8a4ef703 100644 --- a/ports/arm11/iar/readme_threadx.txt +++ b/ports/arm11/iar/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for ARM11 + Microsoft's Azure RTOS ThreadX for ARM11 Thumb & 32-bit Mode @@ -7,10 +7,10 @@ 1. Building the ThreadX run-time Library Building the ThreadX library is easy. First, open the Azure RTOS workspace -azure_rtos.eww. Next, make the TX project the "active project" in the -IAR Embedded Workbench and select the "Make" button. You should observe -assembly and compilation of a series of ThreadX source files. This -results in the ThreadX run-time library file tx.a, which is needed by +azure_rtos.eww. Next, make the TX project the "active project" in the +IAR Embedded Workbench and select the "Make" button. You should observe +assembly and compilation of a series of ThreadX source files. This +results in the ThreadX run-time library file tx.a, which is needed by the application. @@ -20,52 +20,52 @@ The ThreadX demonstration is designed to execute under the IAR Windows-based ARM11 simulator. Building the demonstration is easy; simply make the sample_threadx.ewp project -the "active project" in the IAR Embedded Workbench and select the +the "active project" in the IAR Embedded Workbench and select the "Make" button. -You should observe the compilation of sample_threadx.c (which is the demonstration +You should observe the compilation of sample_threadx.c (which is the demonstration application) and linking with tx.a. The resulting file sample_threadx.out is a binary file that can be downloaded and executed on IAR's ARM11 simulator. A SPECIAL NOTE: The IAR ARM simulator does simulate interrupts. In order -for the ThreadX demonstration to run properly, a periodic IRQ interrupt must +for the ThreadX demonstration to run properly, a periodic IRQ interrupt must be setup in the IAR debugging environment. We recommend setting an IRQ interrupt to execute every 9999 cycles. 3. System Initialization -The entry point in ThreadX for the ARM11 using IAR tools is at label -?cstartup. This is defined within the IAR compiler's startup code. In -addition, this is where all static and global preset C variable +The entry point in ThreadX for the ARM11 using IAR tools is at label +?cstartup. This is defined within the IAR compiler's startup code. In +addition, this is where all static and global preset C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, and a periodic timer interrupt source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. By default, the vector area is defined at the top of cstartup.s, which is -a slightly modified from the base IAR file. +a slightly modified from the base IAR file. The _tx_initialize_low_level function inside of tx_initialize_low_level.s -also determines the first available address for use by the application, which -is supplied as the sole input parameter to your application definition function, -tx_application_define. To accomplish this, a section is created in -tx_initialize_low_level.s called FREE_MEM, which must be located after all +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all other RAM sections in memory. 4. Register Usage and Stack Frames -The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are -scratch registers for each function. All other registers used by a C function -must be preserved by the function. ThreadX takes advantage of this in -situations where a context switch happens as a result of making a ThreadX -service call (which is itself a C function). In such cases, the saved +The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are +scratch registers for each function. All other registers used by a C function +must be preserved by the function. ThreadX takes advantage of this in +situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -83,12 +83,12 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 5. Conditional Compilation Switches @@ -97,146 +97,146 @@ The following are conditional compilation options for building the ThreadX libra and application: - TX_ENABLE_FIQ_SUPPORT This assembler/compiler define enables + TX_ENABLE_FIQ_SUPPORT This assembler/compiler define enables FIQ interrupt handling support in the ThreadX assembly files. If used, it should be used on all assembly files and the generic C source of - ThreadX should be compiled with + ThreadX should be compiled with TX_ENABLE_FIQ_SUPPORT defined as well. TX_ENABLE_IRQ_NESTING This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. TX_ENABLE_FIQ_NESTING This assembler define enables FIQ - nested support. If FIQ nested + nested support. If FIQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. In addition, IRQ nesting should also be enabled. TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - TX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. TX_THUMB Defined, this option enables the BX LR calling return sequence @@ -250,29 +250,29 @@ and application: 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the ThreadX library -project to enable various compiler optimizations. +project to enable various compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for ARM11 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The ARM11 vectors start at address zero. The demonstration system startup -cstartup.s file contains the vectors and is loaded at address zero. -On actual hardware platforms, this area might have to be copied to address 0. +cstartup.s file contains the vectors and is loaded at address zero. +On actual hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs @@ -283,12 +283,12 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.s: PUBLIC __tx_irq_handler - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -296,7 +296,7 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -309,7 +309,7 @@ __tx_irq_processing_return 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.s: @@ -320,12 +320,12 @@ __tx_example_vectored_irq_handler ; /* Jump to context save to save system context. */ STMDB sp!, {r0-r3} ; Save some scratch registers MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers BL _tx_thread_vectored_context_save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -342,24 +342,24 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.s. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables -nesting by disabling IRQ interrupts and switching back to IRQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: RSEG .text:CODE:NOROOT(2) PUBLIC __tx_irq_handler RSEG .text:CODE:NOROOT(2) - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -367,15 +367,15 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ; BL _tx_thread_irq_nesting_start @@ -383,7 +383,7 @@ __tx_irq_processing_return ; /* Application ISR dispatch call goes here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ; BL _tx_thread_irq_nesting_end @@ -394,12 +394,12 @@ __tx_irq_processing_return 7.3 FIQ Interrupts -By default, ARM11 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, ARM11 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.s. @@ -408,7 +408,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.s. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.s: @@ -439,18 +439,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.s. When nested FIQ interrupts are no -longer required, calling the _tx_thread_fiq_nesting_end service disables -nesting by disabling FIQ interrupts and switching back to FIQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested FIQ interrupts are no +longer required, calling the _tx_thread_fiq_nesting_end service disables +nesting by disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -468,7 +468,7 @@ __tx_fiq_processing_return: ; interrupt, and all C scratch registers are available for use. */ ; ; /* Enable nested FIQ interrupts. NOTE: Since this service returns -; with FIQ interrupts enabled, all FIQ interrupt sources must be +; with FIQ interrupts enabled, all FIQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start ; @@ -484,22 +484,22 @@ __tx_fiq_processing_return: 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to _tx_timer_interrupt +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. 9. Thumb/ARM11 Mixed Mode -By default, ThreadX is setup for running in ARM11 32-bit mode. This is -also true for the demonstration system. It is possible to build any +By default, ThreadX is setup for running in ARM11 32-bit mode. This is +also true for the demonstration system. It is possible to build any ThreadX file and/or the application in Thumb mode. The only exception -to this is the file tx_thread_shell_entry.c. This file must always be -built in 32-bit mode. In addition, if any Thumb code is used the entire +to this is the file tx_thread_shell_entry.c. This file must always be +built in 32-bit mode. In addition, if any Thumb code is used the entire ThreadX assembly source should be built with TX_THUMB defined. @@ -511,7 +511,7 @@ should have the following line added (if not already in place): initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application -The project options "General Options -> Library Configuration" should also have the +The project options "General Options -> Library Configuration" should also have the "Enable thread support in library" box selected. diff --git a/ports/arm11/iar/src/tx_iar.c b/ports/arm11/iar/src/tx_iar.c index 158738ea..238b485e 100644 --- a/ports/arm11/iar/src/tx_iar.c +++ b/ports/arm11/iar/src/tx_iar.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** IAR Multithreaded Library Support */ /** */ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports/arm11/iar/src/tx_thread_context_restore.s b/ports/arm11/iar/src/tx_thread_context_restore.s index 211b81dd..addf7705 100644 --- a/ports/arm11/iar/src/tx_thread_context_restore.s +++ b/ports/arm11/iar/src/tx_thread_context_restore.s @@ -1,19 +1,19 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -37,7 +37,7 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask THUMB_MASK DEFINE 0x20 ; Thumb bit mask SVC_MODE_BITS DEFINE 0x13 ; SVC mode value @@ -52,46 +52,40 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) ;{ RSEG .text:CODE:NOROOT(2) @@ -119,13 +113,13 @@ _tx_thread_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3, #0] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3, #0] ; Store the counter + STR r2, [r3, #0] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs diff --git a/ports/arm11/iar/src/tx_thread_context_save.s b/ports/arm11/iar/src/tx_thread_context_save.s index c4d5b1b4..26a3b4d2 100644 --- a/ports/arm11/iar/src/tx_thread_context_save.s +++ b/ports/arm11/iar/src/tx_thread_context_save.s @@ -1,19 +1,19 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -44,45 +44,39 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled EXTERN _tx_execution_isr_enter ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) ;{ RSEG .text:CODE:NOROOT(2) @@ -97,7 +91,7 @@ _tx_thread_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt CPSR @@ -117,7 +111,7 @@ _tx_thread_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -133,7 +127,7 @@ _tx_thread_context_save POP {lr} ; Recover ISR lr #endif - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; __tx_thread_not_nested_save ; } @@ -147,13 +141,13 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} ; Store other registers ; ; /* Save the current stack pointer in the thread's control block. */ @@ -173,7 +167,7 @@ __tx_thread_not_nested_save POP {lr} ; Recover ISR lr #endif - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ; else @@ -183,7 +177,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit @@ -198,7 +192,7 @@ __tx_thread_idle_system_save #endif ADD sp, sp, #16 ; Recover saved registers - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ;} diff --git a/ports/arm11/iar/src/tx_thread_fiq_context_restore.s b/ports/arm11/iar/src/tx_thread_fiq_context_restore.s index 31824589..d9f8a37a 100644 --- a/ports/arm11/iar/src/tx_thread_fiq_context_restore.s +++ b/ports/arm11/iar/src/tx_thread_fiq_context_restore.s @@ -1,19 +1,19 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -38,7 +38,7 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask THUMB_MASK DEFINE 0x20 ; Thumb bit mask IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits SVC_MODE_BITS DEFINE 0x13 ; SVC mode value @@ -53,46 +53,40 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value EXTERN _tx_execution_isr_exit ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_restore ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function restores the fiq interrupt context when processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* FIQ ISR Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) ;{ RSEG .text:CODE:NOROOT(2) @@ -120,13 +114,13 @@ _tx_thread_fiq_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3] ; Store the counter + STR r2, [r3] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -170,7 +164,7 @@ __tx_thread_fiq_no_preempt_restore ; /* Restore interrupted thread or ISR. */ ; ; /* Pickup the saved stack pointer. */ -; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; ; ; /* Recover the saved context and return to the point of interrupt. */ ; @@ -217,7 +211,7 @@ __tx_thread_fiq_preempt_restore BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it ; ; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; -; _tx_timer_time_slice = 0; +; _tx_timer_time_slice = 0; ; STR r2, [r0, #24] ; Save thread's time-slice MOV r2, #0 ; Clear value diff --git a/ports/arm11/iar/src/tx_thread_fiq_context_save.s b/ports/arm11/iar/src/tx_thread_fiq_context_save.s index 17062581..55860011 100644 --- a/ports/arm11/iar/src/tx_thread_fiq_context_save.s +++ b/ports/arm11/iar/src/tx_thread_fiq_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,45 +36,39 @@ EXTERN _tx_execution_isr_enter ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_save ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) ;{ RSEG .text:CODE:NOROOT(2) @@ -89,7 +83,7 @@ _tx_thread_fiq_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state CMP r2, #0 ; Is this the first interrupt? @@ -104,7 +98,7 @@ _tx_thread_fiq_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -120,38 +114,38 @@ _tx_thread_fiq_context_save POP {lr} ; Recover ISR lr #endif - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; __tx_thread_fiq_not_nested_save -; } +; } ; ; /* Otherwise, not nested, check to see if a thread was running. */ ; else if (_tx_thread_current_ptr) -; { +; { ; ADD r2, r2, #1 ; Increment the interrupt counter STR r2, [r3] ; Store it back in the variable LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in -; ; scheduling loop - nothing needs saving! + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, lr} ; Store other registers, Note that we don't -; ; need to save sl and ip since FIQ has -; ; copies of these registers. Nested +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested ; ; interrupt processing does need to save ; ; these registers. ; ; /* Save the current stack pointer in the thread's control block. */ -; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; ; ; /* Switch to the system stack. */ -; sp = _tx_thread_system_stack_ptr; +; sp = _tx_thread_system_stack_ptr; ; MOV r10, #0 ; Clear stack limit @@ -164,7 +158,7 @@ __tx_thread_fiq_not_nested_save POP {lr} ; Recover ISR lr #endif - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } ; else @@ -184,18 +178,18 @@ __tx_thread_fiq_idle_system_save #endif ; ; /* Not much to do here, save the current SPSR and LR for possible -; use in IRQ interrupted in idle system conditions, and return to +; use in IRQ interrupted in idle system conditions, and return to ; FIQ interrupt processing. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, lr} ; Store other registers that will get used -; ; or stripped off the stack in context -; ; restore - B __tx_fiq_processing_return ; Continue FIQ processing +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } -;} +;} ; ; END diff --git a/ports/arm11/iar/src/tx_thread_fiq_nesting_end.s b/ports/arm11/iar/src/tx_thread_fiq_nesting_end.s index 0d71933a..2dbab8e5 100644 --- a/ports/arm11/iar/src/tx_thread_fiq_nesting_end.s +++ b/ports/arm11/iar/src/tx_thread_fiq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,57 +34,51 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_end ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ -;/* processing from system mode back to FIQ mode prior to the ISR */ -;/* calling _tx_thread_fiq_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s79). */ -;/* */ -;/* This function returns with FIQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) ;{ RSEG .text:CODE:NOROOT(2) diff --git a/ports/arm11/iar/src/tx_thread_fiq_nesting_start.s b/ports/arm11/iar/src/tx_thread_fiq_nesting_start.s index 7b2b36cb..2bbbe9b6 100644 --- a/ports/arm11/iar/src/tx_thread_fiq_nesting_start.s +++ b/ports/arm11/iar/src/tx_thread_fiq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,50 +35,44 @@ MODE_MASK DEFINE 0x1F ; Mode mask SYS_MODE_BITS DEFINE 0x1F ; System mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_start ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ -;/* processing to the system mode so nested FIQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s79). */ -;/* */ -;/* This function returns with FIQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) ;{ RSEG .text:CODE:NOROOT(2) diff --git a/ports/arm11/iar/src/tx_thread_interrupt_control.s b/ports/arm11/iar/src/tx_thread_interrupt_control.s index 4cf6b917..22f39ddf 100644 --- a/ports/arm11/iar/src/tx_thread_interrupt_control.s +++ b/ports/arm11/iar/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,44 +35,38 @@ INT_MASK DEFINE 0x80 ; Interrupt bit mask #endif ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) ;{ RSEG .text:CODE:NOROOT(2) diff --git a/ports/arm11/iar/src/tx_thread_interrupt_disable.s b/ports/arm11/iar/src/tx_thread_interrupt_disable.s index e1a61860..d963c895 100644 --- a/ports/arm11/iar/src/tx_thread_interrupt_disable.s +++ b/ports/arm11/iar/src/tx_thread_interrupt_disable.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,43 +36,37 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(VOID) ;{ RSEG .text:CODE:NOROOT(2) diff --git a/ports/arm11/iar/src/tx_thread_interrupt_restore.s b/ports/arm11/iar/src/tx_thread_interrupt_restore.s index 28856151..4bc8e9c2 100644 --- a/ports/arm11/iar/src/tx_thread_interrupt_restore.s +++ b/ports/arm11/iar/src/tx_thread_interrupt_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -28,44 +28,38 @@ ;#include "tx_thread.h" ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ ;/* This function is responsible for restoring interrupts to the state */ ;/* returned by a previous _tx_thread_interrupt_disable call. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/**************************************************************************/ ;void _tx_thread_interrupt_restore(UINT old_posture) ;{ RSEG .text:CODE:NOROOT(2) diff --git a/ports/arm11/iar/src/tx_thread_irq_nesting_end.s b/ports/arm11/iar/src/tx_thread_irq_nesting_end.s index 7a7a3585..3695a57f 100644 --- a/ports/arm11/iar/src/tx_thread_irq_nesting_end.s +++ b/ports/arm11/iar/src/tx_thread_irq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,57 +35,51 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_end ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -;/* processing from system mode back to IRQ mode prior to the ISR */ -;/* calling _tx_thread_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s79). */ -;/* */ -;/* This function returns with IRQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) ;{ RSEG .text:CODE:NOROOT(2) diff --git a/ports/arm11/iar/src/tx_thread_irq_nesting_start.s b/ports/arm11/iar/src/tx_thread_irq_nesting_start.s index b76d1ff6..e538ca1b 100644 --- a/ports/arm11/iar/src/tx_thread_irq_nesting_start.s +++ b/ports/arm11/iar/src/tx_thread_irq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,50 +35,44 @@ MODE_MASK DEFINE 0x1F ; Mode mask SYS_MODE_BITS DEFINE 0x1F ; System mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_start ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_context_save has been called and switches the IRQ */ -;/* processing to the system mode so nested IRQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s79). */ -;/* */ -;/* This function returns with IRQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) ;{ RSEG .text:CODE:NOROOT(2) diff --git a/ports/arm11/iar/src/tx_thread_schedule.s b/ports/arm11/iar/src/tx_thread_schedule.s index 761ec21c..e4a4da47 100644 --- a/ports/arm11/iar/src/tx_thread_schedule.s +++ b/ports/arm11/iar/src/tx_thread_schedule.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -43,47 +43,41 @@ ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLS */ -;/* */ +;/* */ +;/* OUTPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) ;{ RSEG .text:CODE:NOROOT(2) @@ -111,7 +105,7 @@ __tx_thread_schedule_loop ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Lockout interrupts and ; transfer control to it. */ ; @@ -120,7 +114,7 @@ __tx_thread_schedule_loop ; /* Setup the current thread pointer. */ ; _tx_thread_current_ptr = _tx_thread_execute_ptr; ; - LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread STR r0, [r1, #0] ; Setup current thread pointer ; ; /* Increment the run count for this thread. */ @@ -134,7 +128,7 @@ __tx_thread_schedule_loop ; /* Setup time-slice, if present. */ ; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; ; - LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice ; variable LDR sp, [r0, #8] ; Switch stack pointers STR r3, [r2, #0] ; Setup time-slice diff --git a/ports/arm11/iar/src/tx_thread_stack_build.s b/ports/arm11/iar/src/tx_thread_stack_build.s index 4e32e1fa..13981a6c 100644 --- a/ports/arm11/iar/src/tx_thread_stack_build.s +++ b/ports/arm11/iar/src/tx_thread_stack_build.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -37,58 +37,52 @@ CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints en #endif ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ ;/* This function builds a stack frame on the supplied thread's stack. */ ;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ ;/* thread_ptr Pointer to thread control blk */ ;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ +;/* */ +;/* OUTPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLS */ -;/* */ +;/* */ +;/* CALLS */ +;/* */ ;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ +;/* */ +;/* CALLED BY */ +;/* */ ;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) ;{ RSEG .text:CODE:NOROOT(2) PUBLIC _tx_thread_stack_build - + CODE32 _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the ARM9 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; a1 (r0) Initial value for a1 diff --git a/ports/arm11/iar/src/tx_thread_system_return.s b/ports/arm11/iar/src/tx_thread_system_return.s index c7042dfb..2bc395e0 100644 --- a/ports/arm11/iar/src/tx_thread_system_return.s +++ b/ports/arm11/iar/src/tx_thread_system_return.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -42,46 +42,40 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) ;{ RSEG .text:CODE:NOROOT(2) @@ -95,7 +89,7 @@ _tx_thread_system_return MOV r0, #0 ; Build a solicited stack type MRS r1, CPSR ; Pickup the CPSR STMDB sp!, {r0-r1, r4-r11, lr} ; Save minimal context -; +; ; /* Lockout interrupts. */ ; ORR r2, r1, #DISABLE_INTS ; Build disable interrupt CPSR diff --git a/ports/arm11/iar/src/tx_thread_vectored_context_save.s b/ports/arm11/iar/src/tx_thread_vectored_context_save.s index e287b8a5..15598036 100644 --- a/ports/arm11/iar/src/tx_thread_vectored_context_save.s +++ b/ports/arm11/iar/src/tx_thread_vectored_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -41,45 +41,39 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled EXTERN _tx_execution_isr_enter ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_vectored_context_save ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) ;{ RSEG .text:CODE:NOROOT(2) @@ -139,7 +133,7 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in ; scheduling loop - nothing needs saving! ; ; /* Note: Minimal context of interrupted thread is already saved. */ @@ -171,7 +165,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports/arm11/iar/src/tx_timer_interrupt.s b/ports/arm11/iar/src/tx_timer_interrupt.s index 550bc007..13c26851 100644 --- a/ports/arm11/iar/src/tx_timer_interrupt.s +++ b/ports/arm11/iar/src/tx_timer_interrupt.s @@ -1,20 +1,20 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -45,48 +45,42 @@ ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt ARM11/IAR */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time-slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt ARM11/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time-slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) ;{ RSEG .text:CODE:NOROOT(2) @@ -110,7 +104,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CMP r2, #0 ; Is it non-active? BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing @@ -228,13 +222,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CMP r2, #0 ; See if the flag is set BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing ; diff --git a/ports/arm9/ac5/example_build/sample_threadx.c b/ports/arm9/ac5/example_build/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports/arm9/ac5/example_build/sample_threadx.c +++ b/ports/arm9/ac5/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/arm9/ac5/example_build/tx_initialize_low_level.s b/ports/arm9/ac5/example_build/tx_initialize_low_level.s index f2420967..49dd2736 100644 --- a/ports/arm9/ac5/example_build/tx_initialize_low_level.s +++ b/ports/arm9/ac5/example_build/tx_initialize_low_level.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -41,7 +41,7 @@ SYS_STACK_SIZE EQU 1024 ; SYS stack size (used for neste IRQ_STACK_SIZE EQU 1024 ; IRQ stack size ; ; -;/* ARM9 ARMulator Timer and Interrupt controller information. This depends on +;/* ARM9 ARMulator Timer and Interrupt controller information. This depends on ; the ARMulator's Interrupt Controller and Timer being enabled in the default.ami. ; In addition, the addresses must match those specified in the peripherals.ami file. ; Please refer to section 2.10 and 4.16 of the Debug Target Guide, version 1.2. */ @@ -50,7 +50,7 @@ IRQStatus EQU 0x0a000000 ; IRQ Status Register IRQRawStatus EQU 0x0a000004 ; IRQ Raw Status Register IRQEnable EQU 0x0a000008 ; IRQ Enable Set Register IRQEnableClear EQU 0x0a00000C ; IRQ Enable Clear Register -IRQSoft EQU 0x0a000010 ; IRQ Soft +IRQSoft EQU 0x0a000010 ; IRQ Soft FIQStatus EQU 0x0a000100 ; FIQ Status Register FIQRawStatus EQU 0x0a000104 ; FIQ Raw Status Register FIQEnable EQU 0x0a000108 ; FIQ Enable Set Register @@ -113,45 +113,39 @@ __vectors ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level ARM9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level ARM9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -202,7 +196,7 @@ _tx_initialize_low_level ; _tx_thread_system_stack_ptr = (VOID_PTR) (sp); ; LDR r1, =_tx_thread_system_stack_ptr ; Pickup address of system stack ptr - LDR r0, [r1, #0] ; Pickup system stack + LDR r0, [r1, #0] ; Pickup system stack ADD r0, r0, #4 ; Increment to next free word ; ; /* Save the first available memory address. */ @@ -238,7 +232,7 @@ _tx_initialize_low_level ; ; ;/* Define initial heap/stack routine for the ARM RealView (and ADS) startup code. This -; routine will set the initial stack to use the ThreadX IRQ & FIQ & +; routine will set the initial stack to use the ThreadX IRQ & FIQ & ; (optionally SYS) stack areas. */ ; EXPORT __user_initial_stackheap @@ -290,7 +284,7 @@ __tx_reserved_handler ; ; EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -298,34 +292,34 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; ; ; /* Check for Timer1 interrupts on the ARMulator. */ LDR r1,=IRQStatus ; Pickup address of IRQStatus register - LDR r2, [r1] ; Read IRQStatus + LDR r2, [r1] ; Read IRQStatus LDR r0,=TIMER1_BIT ; Pickup Timer1 interrupt present bit AND r2, r2, r0 ; Is this a timer interrupt? - CMP r2, r0 ; + CMP r2, r0 ; BNE _tx_not_timer_interrupt ; If 0, not a timer interrupt LDR r1,=Timer1Clear ; Build address of Timer1 clear register - MOV r0,#0 ; + MOV r0,#0 ; STR r0, [r1] ; Clear timer 0 interrupt BL _tx_timer_interrupt ; Timer interrupt handler _tx_not_timer_interrupt ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ IF :DEF:TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -335,7 +329,7 @@ _tx_not_timer_interrupt ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ IF :DEF:TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -351,28 +345,28 @@ _tx_not_timer_interrupt __tx_example_vectored_irq_handler ; ; -; /* Save initial context and call context save to prepare for +; /* Save initial context and call context save to prepare for ; vectored ISR execution. */ ; ; STMDB sp!, {r0-r3} ; Save some scratch registers ; MRS r0, SPSR ; Pickup saved SPSR -; SUB lr, lr, #4 ; Adjust point of interrupt +; SUB lr, lr, #4 ; Adjust point of interrupt ; STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers ; BL _tx_thread_vectored_context_save ; Vectored context save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ; IF :DEF:TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_start @@ -381,7 +375,7 @@ __tx_example_vectored_irq_handler ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ; IF :DEF:TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_end @@ -403,11 +397,11 @@ __tx_fiq_processing_return ; /* At this point execution is still in the FIQ mode. The CPSR, point of ; interrupt, and all C scratch registers are available for use. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start ; from FIQ mode with interrupts disabled. This routine switches to the -; system mode and returns with FIQ interrupts enabled. +; system mode and returns with FIQ interrupts enabled. ; -; NOTE: It is very important to ensure all FIQ interrupts are cleared +; NOTE: It is very important to ensure all FIQ interrupts are cleared ; prior to enabling nested FIQ interrupts. */ IF :DEF:TX_ENABLE_FIQ_NESTING BL _tx_thread_fiq_nesting_start diff --git a/ports/arm9/ac5/inc/tx_port.h b/ports/arm9/ac5/inc/tx_port.h index 9741bb85..e9dc6430 100644 --- a/ports/arm9/ac5/inc/tx_port.h +++ b/ports/arm9/ac5/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h ARM9/AC5 */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h ARM9/AC5 */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -75,7 +67,7 @@ #include -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -111,12 +103,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -126,8 +118,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -174,7 +166,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -186,13 +178,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -206,11 +198,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -218,8 +210,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -246,24 +238,24 @@ typedef unsigned short USHORT; #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ - + #if __TARGET_ARCH_ARM > 4 #ifndef __thumb #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (ULONG) __clz((unsigned int) m); \ - b = 31 - b; + b = 31 - b; #endif #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -282,7 +274,7 @@ typedef unsigned short USHORT; { \ __enable_irq(); \ __enable_fiq(); \ - } + } #else @@ -291,7 +283,7 @@ typedef unsigned short USHORT; #define TX_RESTORE if (!interrupt_save_disabled) \ { \ __enable_irq(); \ - } + } #endif #else @@ -320,8 +312,8 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARM9/AC5 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARM9/AC5 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/arm9/ac5/readme_threadx.txt b/ports/arm9/ac5/readme_threadx.txt index f07ea494..4b455fa2 100644 --- a/ports/arm9/ac5/readme_threadx.txt +++ b/ports/arm9/ac5/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for ARM9 + Microsoft's Azure RTOS ThreadX for ARM9 Thumb & 32-bit Mode @@ -6,15 +6,15 @@ 1. Building the ThreadX run-time Library -First make sure you are in the "example_build" directory. Also, make sure that -you have setup your path and other environment variables necessary for the ARM -AC5 development environment. At this point you may run the build_threadx.bat -batch file. This will build the ThreadX run-time environment in the -"example_build" directory. +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the ARM +AC5 development environment. At this point you may run the build_threadx.bat +batch file. This will build the ThreadX run-time environment in the +"example_build" directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. @@ -23,39 +23,39 @@ application in order to use ThreadX. The ThreadX demonstration is designed to execute under the ARM Windows-based simulator. -Building the demonstration is easy; simply execute the build_threadx_demo.bat -batch file while inside the "example_build" directory. +Building the demonstration is easy; simply execute the build_threadx_demo.bat +batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with tx.a. The resulting file sample_threadx.axf +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.axf is a binary file that can be downloaded and executed on the ARM simulator. 3. System Initialization -The entry point in ThreadX for the ARM9 using AC5 tools is at label -__main. This is defined within the AC5 compiler's startup code. In -addition, this is where all static and global pre-set C variable +The entry point in ThreadX for the ARM9 using AC5 tools is at label +__main. This is defined within the AC5 compiler's startup code. In +addition, this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. By default, the vector area is defined to be located in the Init area, -which is defined at the top of tx_initialize_low_level.s. This area is typically -located at 0. In situations where this is impossible, the vectors at the beginning +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. By default, the vector area is defined to be located in the Init area, +which is defined at the top of tx_initialize_low_level.s. This area is typically +located at 0. In situations where this is impossible, the vectors at the beginning of the Init area should be copied to address 0. This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 4. Assembler / Compiler Switches -The following are compiler switches used in building the demonstration +The following are compiler switches used in building the demonstration system: Compiler Switch Meaning @@ -71,10 +71,10 @@ Linker Switch Meaning -o demo.axf Specifies demo output file name --elf Specifies elf output file format --ro Specifies that Read-Only memory starts at address 0 - --first tx_initialize_low_level.o(Init) + --first tx_initialize_low_level.o(Init) Specifies that the first area loaded is Init --remove Remove unused areas - --list Specifies map file name + --list Specifies map file name --symbols Specifies symbols for map file --map Creates a map file @@ -85,161 +85,161 @@ Application Defines ThreadX assembly files. If used, it should be used on all assembly files and the generic C source of - ThreadX should be compiled with + ThreadX should be compiled with TX_ENABLE_FIQ_SUPPORT defined as well. --PD "TX_ENABLE_IRQ_NESTING SETL {TRUE}" This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. --PD "TX_ENABLE_FIQ_NESTING SETL {TRUE}" This assembler define enables FIQ - nested support. If FIQ nested + nested support. If FIQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. In addition, IRQ nesting should also be enabled. -DTX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ interrupt handling in the ThreadX - generic C source. This define + generic C source. This define should also be used in conjunction with the corresponding assembler - define. + define. -DTX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - -DTX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + -DTX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - -DTX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + -DTX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - -DTX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + -DTX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - -DTX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + -DTX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - -DTX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + -DTX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - -DTX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + -DTX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - -DTX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + -DTX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - -DTX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + -DTX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - -DTX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + -DTX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - -DTX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + -DTX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - -DTX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + -DTX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - -DTX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + -DTX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - -DTX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + -DTX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - -DTX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + -DTX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - -DTX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + -DTX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - -DTX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + -DTX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - -DTX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + -DTX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - -DTX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + -DTX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - -DTX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + -DTX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. -DTX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - -DTX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + -DTX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - -DTX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + -DTX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. 5. Register Usage and Stack Frames -The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -257,39 +257,39 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make it run faster, you can change the build_threadx.bat file to -remove the -g option and enable all compiler optimizations. +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for ARM9 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The ARM9 vectors start at address zero. The demonstration system startup -Init area contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +Init area contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs @@ -300,12 +300,12 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.s: EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -313,7 +313,7 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -326,7 +326,7 @@ __tx_irq_processing_return 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.s: EXPORT __tx_irq_example_handler @@ -336,12 +336,12 @@ __tx_irq_example_handler STMDB sp!, {r0-r3} ; Save some scratch registers MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers BL _tx_thread_vectored_context_save ; Call the vectored IRQ context save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -358,22 +358,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.s. When nested IRQ interrupts are no longer required, calling the _tx_thread_irq_nesting_end service disables nesting by disabling -IRQ interrupts and switching back to IRQ mode in preparation for the IRQ +IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -381,10 +381,10 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* Enable nested IRQ interrupts. NOTE: Since this service returns -; with IRQ interrupts enabled, all IRQ interrupt sources must be +; with IRQ interrupts enabled, all IRQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start -; +; ; /* Application ISR call(s) go here! */ ; ; /* Disable nested IRQ interrupts. The mode is switched back to @@ -397,12 +397,12 @@ __tx_irq_processing_return 7.3 FIQ Interrupts -By default, ARM9 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, ARM9 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.s. @@ -411,7 +411,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.s. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.s: @@ -439,18 +439,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.s. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -466,7 +466,7 @@ __tx_fiq_processing_return ; interrupt, and all C scratch registers are available for use. */ ; ; /* Enable nested FIQ interrupts. NOTE: Since this service returns -; with FIQ interrupts enabled, all FIQ interrupt sources must be +; with FIQ interrupts enabled, all FIQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start ; @@ -482,22 +482,22 @@ __tx_fiq_processing_return 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.s in the Integrator sub-directories. 9. Thumb/ARM9 Mixed Mode -By default, ThreadX is setup for running in ARM9 32-bit mode. This is -also true for the demonstration system. It is possible to build any +By default, ThreadX is setup for running in ARM9 32-bit mode. This is +also true for the demonstration system. It is possible to build any ThreadX file and/or the application in Thumb mode. The only exception -to this is the file tx_thread_shell_entry.c. This file must always be built +to this is the file tx_thread_shell_entry.c. This file must always be built in 32-bit mode. In addition, if any Thumb code is used the entire ThreadX source- both C and assembly - should be built with the "-apcs /interwork" option. diff --git a/ports/arm9/ac5/src/tx_thread_context_restore.s b/ports/arm9/ac5/src/tx_thread_context_restore.s index ff4f3324..a1eaf668 100644 --- a/ports/arm9/ac5/src/tx_thread_context_restore.s +++ b/ports/arm9/ac5/src/tx_thread_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -37,7 +37,7 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask THUMB_MASK EQU 0x20 ; Thumb bit mask SVC_MODE_BITS EQU 0x13 ; SVC mode value ; @@ -55,44 +55,38 @@ SVC_MODE_BITS EQU 0x13 ; SVC mode value ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore ARM9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore ARM9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -120,13 +114,13 @@ _tx_thread_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3, #0] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3, #0] ; Store the counter + STR r2, [r3, #0] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs diff --git a/ports/arm9/ac5/src/tx_thread_context_save.s b/ports/arm9/ac5/src/tx_thread_context_save.s index 6e7963bf..d78110be 100644 --- a/ports/arm9/ac5/src/tx_thread_context_save.s +++ b/ports/arm9/ac5/src/tx_thread_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -45,43 +45,37 @@ DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save ARM9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save ARM9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -96,7 +90,7 @@ _tx_thread_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers IF :DEF:TX_ENABLE_FIQ_SUPPORT MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt CPSR @@ -116,7 +110,7 @@ _tx_thread_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -132,7 +126,7 @@ _tx_thread_context_save POP {lr} ; Recover ISR lr ENDIF - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; __tx_thread_not_nested_save ; } @@ -146,13 +140,13 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} ; Store other registers ; ; /* Save the current stack pointer in the thread's control block. */ @@ -172,7 +166,7 @@ __tx_thread_not_nested_save POP {lr} ; Recover ISR lr ENDIF - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ; else @@ -182,7 +176,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit @@ -197,7 +191,7 @@ __tx_thread_idle_system_save ENDIF ADD sp, sp, #16 ; Recover saved registers - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ;} diff --git a/ports/arm9/ac5/src/tx_thread_fiq_context_restore.s b/ports/arm9/ac5/src/tx_thread_fiq_context_restore.s index 906b9bd1..fc6e01bb 100644 --- a/ports/arm9/ac5/src/tx_thread_fiq_context_restore.s +++ b/ports/arm9/ac5/src/tx_thread_fiq_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -37,7 +37,7 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask THUMB_MASK EQU 0x20 ; Thumb bit mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits SVC_MODE_BITS EQU 0x13 ; SVC mode value @@ -57,44 +57,38 @@ SVC_MODE_BITS EQU 0x13 ; SVC mode value ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_restore ARM9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore ARM9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the fiq interrupt context when processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* FIQ ISR Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) @@ -122,13 +116,13 @@ _tx_thread_fiq_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3] ; Store the counter + STR r2, [r3] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -172,7 +166,7 @@ __tx_thread_fiq_no_preempt_restore ; /* Restore interrupted thread or ISR. */ ; ; /* Pickup the saved stack pointer. */ -; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; ; ; /* Recover the saved context and return to the point of interrupt. */ ; @@ -219,7 +213,7 @@ __tx_thread_fiq_preempt_restore BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it ; ; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; -; _tx_timer_time_slice = 0; +; _tx_timer_time_slice = 0; ; STR r2, [r0, #24] ; Save thread's time-slice MOV r2, #0 ; Clear value diff --git a/ports/arm9/ac5/src/tx_thread_fiq_context_save.s b/ports/arm9/ac5/src/tx_thread_fiq_context_save.s index 93be71d7..da963065 100644 --- a/ports/arm9/ac5/src/tx_thread_fiq_context_save.s +++ b/ports/arm9/ac5/src/tx_thread_fiq_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,43 +39,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_save ARM9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save ARM9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) @@ -90,7 +84,7 @@ _tx_thread_fiq_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state CMP r2, #0 ; Is this the first interrupt? @@ -105,7 +99,7 @@ _tx_thread_fiq_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -121,38 +115,38 @@ _tx_thread_fiq_context_save POP {lr} ; Recover ISR lr ENDIF - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; __tx_thread_fiq_not_nested_save -; } +; } ; ; /* Otherwise, not nested, check to see if a thread was running. */ ; else if (_tx_thread_current_ptr) -; { +; { ; ADD r2, r2, #1 ; Increment the interrupt counter STR r2, [r3] ; Store it back in the variable LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in -; ; scheduling loop - nothing needs saving! + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, lr} ; Store other registers, Note that we don't -; ; need to save sl and ip since FIQ has -; ; copies of these registers. Nested +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested ; ; interrupt processing does need to save ; ; these registers. ; ; /* Save the current stack pointer in the thread's control block. */ -; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; ; ; /* Switch to the system stack. */ -; sp = _tx_thread_system_stack_ptr; +; sp = _tx_thread_system_stack_ptr; ; MOV r10, #0 ; Clear stack limit @@ -165,7 +159,7 @@ __tx_thread_fiq_not_nested_save POP {lr} ; Recover ISR lr ENDIF - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } ; else @@ -185,18 +179,18 @@ __tx_thread_fiq_idle_system_save ENDIF ; ; /* Not much to do here, save the current SPSR and LR for possible -; use in IRQ interrupted in idle system conditions, and return to +; use in IRQ interrupted in idle system conditions, and return to ; FIQ interrupt processing. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, lr} ; Store other registers that will get used -; ; or stripped off the stack in context -; ; restore - B __tx_fiq_processing_return ; Continue FIQ processing +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } -;} +;} ; END diff --git a/ports/arm9/ac5/src/tx_thread_fiq_nesting_end.s b/ports/arm9/ac5/src/tx_thread_fiq_nesting_end.s index ee8484ce..e34c5be6 100644 --- a/ports/arm9/ac5/src/tx_thread_fiq_nesting_end.s +++ b/ports/arm9/ac5/src/tx_thread_fiq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,56 +34,50 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_end ARM9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end ARM9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ -;/* processing from system mode back to FIQ mode prior to the ISR */ -;/* calling _tx_thread_fiq_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with FIQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) @@ -94,7 +88,7 @@ _tx_thread_fiq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_cxsf, r0 ; Disable interrupts - LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports/arm9/ac5/src/tx_thread_fiq_nesting_start.s b/ports/arm9/ac5/src/tx_thread_fiq_nesting_start.s index e2e9435b..4b17fee9 100644 --- a/ports/arm9/ac5/src/tx_thread_fiq_nesting_start.s +++ b/ports/arm9/ac5/src/tx_thread_fiq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_start ARM9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start ARM9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ -;/* processing to the system mode so nested FIQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with FIQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/arm9/ac5/src/tx_thread_interrupt_control.s b/ports/arm9/ac5/src/tx_thread_interrupt_control.s index b9a99e0c..14c4e4f7 100644 --- a/ports/arm9/ac5/src/tx_thread_interrupt_control.s +++ b/ports/arm9/ac5/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,42 +36,36 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control ARM9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control ARM9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/arm9/ac5/src/tx_thread_interrupt_disable.s b/ports/arm9/ac5/src/tx_thread_interrupt_disable.s index 01e85f7f..a5d83435 100644 --- a/ports/arm9/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/arm9/ac5/src/tx_thread_interrupt_disable.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,41 +36,35 @@ DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable ARM9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable ARM9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(void) diff --git a/ports/arm9/ac5/src/tx_thread_interrupt_restore.s b/ports/arm9/ac5/src/tx_thread_interrupt_restore.s index 638d1d0d..d88578a8 100644 --- a/ports/arm9/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/arm9/ac5/src/tx_thread_interrupt_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,42 +29,36 @@ ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore ARM9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore ARM9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function is responsible for restoring interrupts to the state */ ;/* returned by a previous _tx_thread_interrupt_disable call. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/arm9/ac5/src/tx_thread_irq_nesting_end.s b/ports/arm9/ac5/src/tx_thread_irq_nesting_end.s index 032d4dcc..622288db 100644 --- a/ports/arm9/ac5/src/tx_thread_irq_nesting_end.s +++ b/ports/arm9/ac5/src/tx_thread_irq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,56 +34,50 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_end ARM9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end ARM9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -;/* processing from system mode back to IRQ mode prior to the ISR */ -;/* calling _tx_thread_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) @@ -94,7 +88,7 @@ _tx_thread_irq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_cxsf, r0 ; Disable interrupts - LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports/arm9/ac5/src/tx_thread_irq_nesting_start.s b/ports/arm9/ac5/src/tx_thread_irq_nesting_start.s index 3da96c71..7cd3cd98 100644 --- a/ports/arm9/ac5/src/tx_thread_irq_nesting_start.s +++ b/ports/arm9/ac5/src/tx_thread_irq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_start ARM9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start ARM9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_context_save has been called and switches the IRQ */ -;/* processing to the system mode so nested IRQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/arm9/ac5/src/tx_thread_schedule.s b/ports/arm9/ac5/src/tx_thread_schedule.s index 23b678e2..20fa4d41 100644 --- a/ports/arm9/ac5/src/tx_thread_schedule.s +++ b/ports/arm9/ac5/src/tx_thread_schedule.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -47,45 +47,39 @@ ENABLE_INTS EQU 0x80 ; IRQ Interrupts enabled mask ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule ARM9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule ARM9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -112,7 +106,7 @@ __tx_thread_schedule_loop ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Lockout interrupts and ; transfer control to it. */ ; @@ -121,7 +115,7 @@ __tx_thread_schedule_loop ; /* Setup the current thread pointer. */ ; _tx_thread_current_ptr = _tx_thread_execute_ptr; ; - LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread STR r0, [r1, #0] ; Setup current thread pointer ; ; /* Increment the run count for this thread. */ @@ -135,7 +129,7 @@ __tx_thread_schedule_loop ; /* Setup time-slice, if present. */ ; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; ; - LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice ; variable LDR sp, [r0, #8] ; Switch stack pointers STR r3, [r2, #0] ; Setup time-slice diff --git a/ports/arm9/ac5/src/tx_thread_stack_build.s b/ports/arm9/ac5/src/tx_thread_stack_build.s index 2ca47eb6..a286e896 100644 --- a/ports/arm9/ac5/src/tx_thread_stack_build.s +++ b/ports/arm9/ac5/src/tx_thread_stack_build.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -38,44 +38,38 @@ CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints en ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build ARM9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build ARM9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function builds a stack frame on the supplied thread's stack. */ ;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ ;/* thread_ptr Pointer to thread control blk */ ;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -83,10 +77,10 @@ CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints en EXPORT _tx_thread_stack_build _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the ARM9 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; a1 (r0) Initial value for a1 diff --git a/ports/arm9/ac5/src/tx_thread_system_return.s b/ports/arm9/ac5/src/tx_thread_system_return.s index bf9f1735..83a54a0f 100644 --- a/ports/arm9/ac5/src/tx_thread_system_return.s +++ b/ports/arm9/ac5/src/tx_thread_system_return.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -40,50 +40,44 @@ DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled IMPORT _tx_timer_time_slice IMPORT _tx_thread_schedule IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY - IMPORT _tx_execution_thread_exit + IMPORT _tx_execution_thread_exit ENDIF ; ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return ARM9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return ARM9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -96,7 +90,7 @@ _tx_thread_system_return MOV r0, #0 ; Build a solicited stack type MRS r1, CPSR ; Pickup the CPSR STMDB sp!, {r0-r1, r4-r11, lr} ; Save minimal context -; +; ; /* Lockout interrupts. */ ; ORR r2, r1, #DISABLE_INTS ; Build disable interrupt CPSR diff --git a/ports/arm9/ac5/src/tx_thread_vectored_context_save.s b/ports/arm9/ac5/src/tx_thread_vectored_context_save.s index ede3ec49..a9283702 100644 --- a/ports/arm9/ac5/src/tx_thread_vectored_context_save.s +++ b/ports/arm9/ac5/src/tx_thread_vectored_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -45,43 +45,37 @@ DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_vectored_context_save ARM9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save ARM9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) @@ -144,7 +138,7 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Note: Minimal context of interrupted thread is already saved. */ @@ -180,7 +174,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports/arm9/ac5/src/tx_timer_interrupt.s b/ports/arm9/ac5/src/tx_timer_interrupt.s index 061c5806..86ddba6f 100644 --- a/ports/arm9/ac5/src/tx_timer_interrupt.s +++ b/ports/arm9/ac5/src/tx_timer_interrupt.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -44,46 +44,40 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt ARM9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt ARM9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -107,7 +101,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CMP r2, #0 ; Is it non-active? BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing @@ -225,13 +219,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CMP r2, #0 ; See if the flag is set BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing ; diff --git a/ports/arm9/gnu/example_build/crt0.S b/ports/arm9/gnu/example_build/crt0.S index aa0f3239..56b6c958 100644 --- a/ports/arm9/gnu/example_build/crt0.S +++ b/ports/arm9/gnu/example_build/crt0.S @@ -26,13 +26,13 @@ _mainCRTStartup: mov a2, #0 /* Second arg: fill value */ mov fp, a2 /* Null frame pointer */ mov r7, a2 /* Null frame pointer for Thumb */ - - ldr a1, .LC1 /* First arg: start of memory block */ - ldr a3, .LC2 - sub a3, a3, a1 /* Third arg: length of block */ - - + ldr a1, .LC1 /* First arg: start of memory block */ + ldr a3, .LC2 + sub a3, a3, a1 /* Third arg: length of block */ + + + bl memset mov r0, #0 /* no arguments */ mov r1, #0 /* no argv either */ @@ -48,15 +48,15 @@ _mainCRTStartup: /* bl init */ mov r0, r4 mov r1, r5 -#endif +#endif bl main bl exit /* Should not return. */ - - /* For Thumb, constants must be after the code since only + + /* For Thumb, constants must be after the code since only positive offsets are supported for PC relative addresses. */ - + .align 0 .LC0: .LC1: diff --git a/ports/arm9/gnu/example_build/reset.S b/ports/arm9/gnu/example_build/reset.S index a11c826a..5d05258b 100644 --- a/ports/arm9/gnu/example_build/reset.S +++ b/ports/arm9/gnu/example_build/reset.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Initialize */ @/** */ @@ -65,11 +65,11 @@ SWI: .word __tx_swi_interrupt @ Software interrupt handler PREFETCH: .word __tx_prefetch_handler @ Prefetch exception handler -ABORT: +ABORT: .word __tx_abort_handler @ Abort exception handler -RESERVED: +RESERVED: .word __tx_reserved_handler @ Reserved exception handler -IRQ: +IRQ: .word __tx_irq_handler @ IRQ interrupt handler FIQ: .word __tx_fiq_handler @ FIQ interrupt handler diff --git a/ports/arm9/gnu/example_build/sample_threadx.c b/ports/arm9/gnu/example_build/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports/arm9/gnu/example_build/sample_threadx.c +++ b/ports/arm9/gnu/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/arm9/gnu/example_build/sample_threadx.ld b/ports/arm9/gnu/example_build/sample_threadx.ld index 3dea4e1c..e940b2b8 100644 --- a/ports/arm9/gnu/example_build/sample_threadx.ld +++ b/ports/arm9/gnu/example_build/sample_threadx.ld @@ -7,7 +7,7 @@ OUTPUT_ARCH(arm) SECTIONS { . = 0x00000000; - + .vectors : {reset.o(.text) } /* Read-only sections, merged into text segment: */ @@ -94,8 +94,8 @@ SECTIONS *(.gnu.linkonce.t*) *(.glue_7t) *(.glue_7) } =0 - .init : - { + .init : + { KEEP (*(.init)) } =0 _etext = .; @@ -120,7 +120,7 @@ SECTIONS .data1 : { *(.data1) } .eh_frame : { KEEP (*(.eh_frame)) } .gcc_except_table : { *(.gcc_except_table) } - .ctors : + .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is @@ -153,9 +153,9 @@ SECTIONS /* We want the small data sections together, so single-instruction offsets can access them all, and initialized data all before uninitialized, so we can shorten the on-disk segment size. */ - .sdata : + .sdata : { - *(.sdata) + *(.sdata) *(.sdata.*) *(.gnu.linkonce.s.*) } @@ -191,7 +191,7 @@ SECTIONS _stack_bottom = ABSOLUTE(.) ; - /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and + /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and SYS stack if nested interrupts are enabled. */ . = ALIGN(8) ; . += 4096 ; diff --git a/ports/arm9/gnu/example_build/tx_initialize_low_level.S b/ports/arm9/gnu/example_build/tx_initialize_low_level.S index 1f2207ec..6b6da2ab 100644 --- a/ports/arm9/gnu/example_build/tx_initialize_low_level.S +++ b/ports/arm9/gnu/example_build/tx_initialize_low_level.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Initialize */ @/** */ @@ -62,7 +62,7 @@ SYS_STACK_SIZE = 1024 @ System stack size .type $_tx_initialize_low_level,function $_tx_initialize_low_level: BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_initialize_low_level @ Call _tx_initialize_low_level function @@ -72,45 +72,39 @@ $_tx_initialize_low_level: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_initialize_low_level ARM9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level ARM9/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is responsible for any low-level processor */ -@/* initialization, including setting up interrupt vectors, setting */ -@/* up a periodic timer interrupt source, saving the system stack */ -@/* pointer for use in ISR processing later, and finding the first */ -@/* available RAM memory address for tx_application_define. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_initialize_kernel_enter ThreadX entry function */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) @@ -125,7 +119,7 @@ _tx_initialize_low_level: @ LDR r1, =_sp @ Get pointer to stack area -#ifdef TX_ENABLE_IRQ_NESTING +#ifdef TX_ENABLE_IRQ_NESTING @ @ /* Setup the system mode stack for nested interrupt support */ @ @@ -156,7 +150,7 @@ _tx_initialize_low_level: MSR CPSR, r0 @ Enter SVC mode LDR r2, =_stack_bottom @ Pickup stack bottom CMP r3, r2 @ Compare the current stack end with the bottom -_stack_error_loop: +_stack_error_loop: BLT _stack_error_loop @ If the IRQ stack exceeds the stack bottom, just sit here! @ @ /* Save the system stack pointer. */ @@ -208,7 +202,7 @@ __tx_reserved_handler: B __tx_reserved_handler @ Reserved exception handler @ .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -216,17 +210,17 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. In +@ interrupt, and all C scratch registers are available for use. In @ addition, IRQ interrupts may be re-enabled - with certain restrictions - @ if nested IRQ interrupts are desired. Interrupts may be re-enabled over -@ small code sequences where lr is saved before enabling interrupts and +@ small code sequences where lr is saved before enabling interrupts and @ restored after interrupts are again disabled. */ @ -@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start @ from IRQ mode with interrupts disabled. This routine switches to the -@ system mode and returns with IRQ interrupts enabled. -@ -@ NOTE: It is very important to ensure all IRQ interrupts are cleared +@ system mode and returns with IRQ interrupts enabled. +@ +@ NOTE: It is very important to ensure all IRQ interrupts are cleared @ prior to enabling nested IRQ interrupts. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -240,7 +234,7 @@ __tx_irq_processing_return: @ @ @ /* If interrupt nesting was started earlier, the end of interrupt nesting -@ service must be called before returning to _tx_thread_context_restore. +@ service must be called before returning to _tx_thread_context_restore. @ This routine returns in processing in IRQ mode with interrupts disabled. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -256,28 +250,28 @@ __tx_irq_processing_return: @__tx_example_vectored_irq_handler: @ @ -@ /* Save initial context and call context save to prepare for +@ /* Save initial context and call context save to prepare for @ vectored ISR execution. */ @ @ STMDB sp!, {r0-r3} @ Save some scratch registers @ MRS r0, SPSR @ Pickup saved SPSR -@ SUB lr, lr, #4 @ Adjust point of interrupt +@ SUB lr, lr, #4 @ Adjust point of interrupt @ STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers @ BL _tx_thread_vectored_context_save @ Vectored context save @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. In +@ interrupt, and all C scratch registers are available for use. In @ addition, IRQ interrupts may be re-enabled - with certain restrictions - @ if nested IRQ interrupts are desired. Interrupts may be re-enabled over -@ small code sequences where lr is saved before enabling interrupts and +@ small code sequences where lr is saved before enabling interrupts and @ restored after interrupts are again disabled. */ @ @ -@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start @ from IRQ mode with interrupts disabled. This routine switches to the -@ system mode and returns with IRQ interrupts enabled. -@ -@ NOTE: It is very important to ensure all IRQ interrupts are cleared +@ system mode and returns with IRQ interrupts enabled. +@ +@ NOTE: It is very important to ensure all IRQ interrupts are cleared @ prior to enabling nested IRQ interrupts. */ @#ifdef TX_ENABLE_IRQ_NESTING @ BL _tx_thread_irq_nesting_start @@ -286,7 +280,7 @@ __tx_irq_processing_return: @ /* Application IRQ handlers can be called here! */ @ @ /* If interrupt nesting was started earlier, the end of interrupt nesting -@ service must be called before returning to _tx_thread_context_restore. +@ service must be called before returning to _tx_thread_context_restore. @ This routine returns in processing in IRQ mode with interrupts disabled. */ @#ifdef TX_ENABLE_IRQ_NESTING @ BL _tx_thread_irq_nesting_end @@ -308,11 +302,11 @@ __tx_fiq_processing_return: @ /* At this point execution is still in the FIQ mode. The CPSR, point of @ interrupt, and all C scratch registers are available for use. */ @ -@ /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +@ /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start @ from FIQ mode with interrupts disabled. This routine switches to the -@ system mode and returns with FIQ interrupts enabled. +@ system mode and returns with FIQ interrupts enabled. @ -@ NOTE: It is very important to ensure all FIQ interrupts are cleared +@ NOTE: It is very important to ensure all FIQ interrupts are cleared @ prior to enabling nested FIQ interrupts. */ #ifdef TX_ENABLE_FIQ_NESTING BL _tx_thread_fiq_nesting_start diff --git a/ports/arm9/gnu/inc/tx_port.h b/ports/arm9/gnu/inc/tx_port.h index 5c83770f..4597b252 100644 --- a/ports/arm9/gnu/inc/tx_port.h +++ b/ports/arm9/gnu/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h ARM9/GNU */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h ARM9/GNU */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -75,7 +67,7 @@ #include -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -111,12 +103,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -126,8 +118,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -174,7 +166,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -186,13 +178,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -206,11 +198,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -218,8 +210,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -246,24 +238,24 @@ typedef unsigned short USHORT; #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ - + #if __TARGET_ARCH_ARM > 4 #ifndef __thumb__ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ asm volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); \ - b = 31 - b; + b = 31 - b; #endif #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -307,8 +299,8 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARM9/GNU Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARM9/GNU Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/arm9/gnu/readme_threadx.txt b/ports/arm9/gnu/readme_threadx.txt index 54046146..6f90b254 100644 --- a/ports/arm9/gnu/readme_threadx.txt +++ b/ports/arm9/gnu/readme_threadx.txt @@ -1,55 +1,55 @@ - Microsoft's Azure RTOS ThreadX for ARM9 + Microsoft's Azure RTOS ThreadX for ARM9 Using the GNU Tools 1. Building the ThreadX run-time Library -First make sure you are in the "example_build" directory. Also, make sure that -you have setup your path and other environment variables necessary for the GNU -development environment. +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the GNU +development environment. -At this point you may run the build_threadx.bat batch file. This will build the -ThreadX run-time environment in the "example_build" directory. +At this point you may run the build_threadx.bat batch file. This will build the +ThreadX run-time environment in the "example_build" directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: TX.A. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: TX.A. This file must be linked with your application in order to use ThreadX. 2. Demonstration System -Building the demonstration is easy; simply execute the build_threadx_sample.bat -batch file while inside the "example_build" directory. +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with TX.A. The resulting file DEMO is a binary file +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with TX.A. The resulting file DEMO is a binary file that can be downloaded and executed. 3. System Initialization -The entry point in ThreadX for the ARM9 using GNU tools is at label _start. +The entry point in ThreadX for the ARM9 using GNU tools is at label _start. This is defined within the modified version of the GNU startup code - crt0.S. -The ThreadX tx_initialize_low_level.S file is responsible for setting up various -system data structures, the interrupt vectors, and a periodic timer interrupt source. -By default, the vector area is defined to be located at the "__vectors" label, -which is defined in reset.S. This area is typically located at 0. In situations -where this is impossible, the vectors at the "__vectors" label should be copied +The ThreadX tx_initialize_low_level.S file is responsible for setting up various +system data structures, the interrupt vectors, and a periodic timer interrupt source. +By default, the vector area is defined to be located at the "__vectors" label, +which is defined in reset.S. This area is typically located at 0. In situations +where this is impossible, the vectors at the "__vectors" label should be copied to address 0. -This is also where initialization of a periodic timer interrupt source should take +This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level defines the first available address -for use by the application, which is supplied as the sole input parameter +In addition, _tx_initialize_low_level defines the first available address +for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 4. Assembler / Compiler Switches -The following are compiler switches used in building the demonstration +The following are compiler switches used in building the demonstration system: Compiler/Assembler Meaning @@ -73,164 +73,164 @@ Application Defines ( -D option) ThreadX assembly files. If used, it should be used on all assembly files and the generic C source of - ThreadX should be compiled with + ThreadX should be compiled with TX_ENABLE_FIQ_SUPPORT defined as well. TX_ENABLE_IRQ_NESTING This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.S. TX_ENABLE_FIQ_NESTING This assembler define enables FIQ - nested support. If FIQ nested + nested support. If FIQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.S. In addition, IRQ nesting should also be enabled. TX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ interrupt handling in the ThreadX - generic C source. This define + generic C source. This define should also be used in conjunction with the corresponding assembler - define. + define. TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - TX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. 5. Register Usage and Stack Frames -The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -248,52 +248,52 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for ARM9 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The ARM9 vectors start at address zero. The demonstration system startup -reset.S file contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +reset.S file contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs -ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -301,7 +301,7 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -314,7 +314,7 @@ __tx_irq_processing_return: 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_example_handler @@ -324,12 +324,12 @@ __tx_irq_example_handler: STMDB sp!, {r0-r3} @ Save some scratch registers MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers BL _tx_thread_vectored_context_save @ Call the vectored IRQ context save @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -346,22 +346,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.S. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables -nesting by disabling IRQ interrupts and switching back to IRQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -369,10 +369,10 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* Enable nested IRQ interrupts. NOTE: Since this service returns -@ with IRQ interrupts enabled, all IRQ interrupt sources must be +@ with IRQ interrupts enabled, all IRQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start -@ +@ @ /* Application ISR call(s) go here! */ @ @ /* Disable nested IRQ interrupts. The mode is switched back to @@ -385,12 +385,12 @@ __tx_irq_processing_return: 7.3 FIQ Interrupts -By default, ARM7 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, ARM7 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.S. @@ -399,7 +399,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.S. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.S: @@ -427,18 +427,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.S. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -454,7 +454,7 @@ __tx_fiq_processing_return: @ interrupt, and all C scratch registers are available for use. */ @ @ /* Enable nested FIQ interrupts. NOTE: Since this service returns -@ with FIQ interrupts enabled, all FIQ interrupt sources must be +@ with FIQ interrupts enabled, all FIQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start @ @@ -470,12 +470,12 @@ __tx_fiq_processing_return: 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer -interrupt source, these services are not functional but the remainder of +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of ThreadX will still run. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.S for the demonstration system. diff --git a/ports/arm9/gnu/src/tx_thread_context_restore.S b/ports/arm9/gnu/src/tx_thread_context_restore.S index 61087c84..3dcf8f82 100644 --- a/ports/arm9/gnu/src/tx_thread_context_restore.S +++ b/ports/arm9/gnu/src/tx_thread_context_restore.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -43,51 +43,42 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @ @/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore @ since it will never be called 16-bit mode. */ -@ +@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_context_restore ARM9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore ARM9/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function restores the interrupt context if it is processing a */ -@/* nested interrupt. If not, it returns to the interrupt thread if no */ -@/* preemption is necessary. Otherwise, if preemption is necessary or */ -@/* if no thread was running, the function returns to the scheduler. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling routine */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs Interrupt Service Routines */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) @@ -115,13 +106,13 @@ _tx_thread_context_restore: LDR r3, =_tx_thread_system_state @ Pickup address of system state variable LDR r2, [r3] @ Pickup system state SUB r2, r2, #1 @ Decrement the counter - STR r2, [r3] @ Store the counter + STR r2, [r3] @ Store the counter CMP r2, #0 @ Was this the first interrupt? BEQ __tx_thread_not_nested_restore @ If so, not a nested restore @ @ /* Interrupts are nested. */ @ -@ /* Just recover the saved registers and return to the point of +@ /* Just recover the saved registers and return to the point of @ interrupt. */ @ LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs diff --git a/ports/arm9/gnu/src/tx_thread_context_save.S b/ports/arm9/gnu/src/tx_thread_context_save.S index f2ef9712..712dc133 100644 --- a/ports/arm9/gnu/src/tx_thread_context_save.S +++ b/ports/arm9/gnu/src/tx_thread_context_save.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -36,50 +36,41 @@ DISABLE_INTS = 0x80 @ IRQ interrupts disabled @ @/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save @ since it will never be called 16-bit mode. */ -@ +@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_context_save ARM9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save ARM9/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function saves the context of an executing thread in the */ -@/* beginning of interrupt processing. The function also ensures that */ -@/* the system stack is used upon return to the calling ISR. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) @@ -95,7 +86,7 @@ _tx_thread_context_save: @ if (_tx_thread_system_state++) @ { @ - STMDB sp!, {r0-r3} @ Save some working registers + STMDB sp!, {r0-r3} @ Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT MRS r0, CPSR @ Pickup the CPSR ORR r0, r0, #DISABLE_INTS @ Build disable interrupt CPSR @@ -115,7 +106,7 @@ _tx_thread_context_save: @ calling ISR. */ @ MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other registers @ @ /* Return to the ISR. */ @@ -131,7 +122,7 @@ _tx_thread_context_save: POP {lr} @ Recover ISR lr #endif - B __tx_irq_processing_return @ Continue IRQ processing + B __tx_irq_processing_return @ Continue IRQ processing @ __tx_thread_not_nested_save: @ } @@ -145,13 +136,13 @@ __tx_thread_not_nested_save: LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr LDR r0, [r1] @ Pickup current thread pointer CMP r0, #0 @ Is it NULL? - BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in @ scheduling loop - nothing needs saving! @ @ /* Save minimal context of interrupted thread. */ @ MRS r2, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} @ Store other registers @ @ /* Save the current stack pointer in the thread's control block. */ @@ -171,7 +162,7 @@ __tx_thread_not_nested_save: POP {lr} @ Recover ISR lr #endif - B __tx_irq_processing_return @ Continue IRQ processing + B __tx_irq_processing_return @ Continue IRQ processing @ @ } @ else @@ -181,7 +172,7 @@ __tx_thread_idle_system_save: @ @ /* Interrupt occurred in the scheduling loop. */ @ -@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ @ processing. */ @ MOV r10, #0 @ Clear stack limit @@ -196,7 +187,7 @@ __tx_thread_idle_system_save: #endif ADD sp, sp, #16 @ Recover saved registers - B __tx_irq_processing_return @ Continue IRQ processing + B __tx_irq_processing_return @ Continue IRQ processing @ @ } @} diff --git a/ports/arm9/gnu/src/tx_thread_fiq_context_restore.S b/ports/arm9/gnu/src/tx_thread_fiq_context_restore.S index 5ac52543..c8dec5dc 100644 --- a/ports/arm9/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/arm9/gnu/src/tx_thread_fiq_context_restore.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -25,7 +25,7 @@ SVC_MODE = 0xD3 @ SVC mode FIQ_MODE = 0xD1 @ FIQ mode DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts -MODE_MASK = 0x1F @ Mode mask +MODE_MASK = 0x1F @ Mode mask THUMB_MASK = 0x20 @ Thumb bit mask IRQ_MODE_BITS = 0x12 @ IRQ mode bits SVC_MODE_BITS = 0x13 @ SVC mode value @@ -47,47 +47,38 @@ SVC_MODE_BITS = 0x13 @ SVC mode value .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_fiq_context_restore ARM9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_restore ARM9/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function restores the fiq interrupt context when processing a */ -@/* nested interrupt. If not, it returns to the interrupt thread if no */ -@/* preemption is necessary. Otherwise, if preemption is necessary or */ -@/* if no thread was running, the function returns to the scheduler. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling routine */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* FIQ ISR Interrupt Service Routines */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function restores the fiq interrupt context when processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* FIQ ISR Interrupt Service Routines */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_context_restore(VOID) @@ -116,13 +107,13 @@ _tx_thread_fiq_context_restore: LDR r3, =_tx_thread_system_state @ Pickup address of system state variable LDR r2, [r3] @ Pickup system state SUB r2, r2, #1 @ Decrement the counter - STR r2, [r3] @ Store the counter + STR r2, [r3] @ Store the counter CMP r2, #0 @ Was this the first interrupt? BEQ __tx_thread_fiq_not_nested_restore @ If so, not a nested restore @ @ /* Interrupts are nested. */ @ -@ /* Just recover the saved registers and return to the point of +@ /* Just recover the saved registers and return to the point of @ interrupt. */ @ LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs @@ -213,7 +204,7 @@ __tx_thread_fiq_preempt_restore: BEQ __tx_thread_fiq_dont_save_ts @ No, don't save it @ @ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; -@ _tx_timer_time_slice = 0; +@ _tx_timer_time_slice = 0; @ STR r2, [r0, #24] @ Save thread's time-slice MOV r2, #0 @ Clear value diff --git a/ports/arm9/gnu/src/tx_thread_fiq_context_save.S b/ports/arm9/gnu/src/tx_thread_fiq_context_save.S index 121dee2a..b7cc9ef8 100644 --- a/ports/arm9/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/arm9/gnu/src/tx_thread_fiq_context_save.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -34,46 +34,37 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_fiq_context_save ARM9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_save ARM9/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function saves the context of an executing thread in the */ -@/* beginning of interrupt processing. The function also ensures that */ -@/* the system stack is used upon return to the calling ISR. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @ VOID _tx_thread_fiq_context_save(VOID) @@ -89,7 +80,7 @@ _tx_thread_fiq_context_save: @ if (_tx_thread_system_state++) @ { @ - STMDB sp!, {r0-r3} @ Save some working registers + STMDB sp!, {r0-r3} @ Save some working registers LDR r3, =_tx_thread_system_state @ Pickup address of system state variable LDR r2, [r3] @ Pickup system state CMP r2, #0 @ Is this the first interrupt? @@ -104,7 +95,7 @@ _tx_thread_fiq_context_save: @ calling ISR. */ @ MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other registers @ @ /* Return to the ISR. */ @@ -120,38 +111,38 @@ _tx_thread_fiq_context_save: POP {lr} @ Recover ISR lr #endif - B __tx_fiq_processing_return @ Continue FIQ processing + B __tx_fiq_processing_return @ Continue FIQ processing @ __tx_thread_fiq_not_nested_save: -@ } +@ } @ @ /* Otherwise, not nested, check to see if a thread was running. */ @ else if (_tx_thread_current_ptr) -@ { +@ { @ ADD r2, r2, #1 @ Increment the interrupt counter STR r2, [r3] @ Store it back in the variable LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr LDR r0, [r1] @ Pickup current thread pointer CMP r0, #0 @ Is it NULL? - BEQ __tx_thread_fiq_idle_system_save @ If so, interrupt occurred in -@ @ scheduling loop - nothing needs saving! + BEQ __tx_thread_fiq_idle_system_save @ If so, interrupt occurred in +@ @ scheduling loop - nothing needs saving! @ @ /* Save minimal context of interrupted thread. */ @ MRS r2, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r2, lr} @ Store other registers, Note that we don't -@ @ need to save sl and ip since FIQ has -@ @ copies of these registers. Nested +@ @ need to save sl and ip since FIQ has +@ @ copies of these registers. Nested @ @ interrupt processing does need to save @ @ these registers. @ @ /* Save the current stack pointer in the thread's control block. */ -@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; @ @ /* Switch to the system stack. */ -@ sp = _tx_thread_system_stack_ptr; +@ sp = _tx_thread_system_stack_ptr; @ MOV r10, #0 @ Clear stack limit @@ -164,7 +155,7 @@ __tx_thread_fiq_not_nested_save: POP {lr} @ Recover ISR lr #endif - B __tx_fiq_processing_return @ Continue FIQ processing + B __tx_fiq_processing_return @ Continue FIQ processing @ @ } @ else @@ -184,16 +175,16 @@ __tx_thread_fiq_idle_system_save: #endif @ @ /* Not much to do here, save the current SPSR and LR for possible -@ use in IRQ interrupted in idle system conditions, and return to +@ use in IRQ interrupted in idle system conditions, and return to @ FIQ interrupt processing. */ @ MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, lr} @ Store other registers that will get used -@ @ or stripped off the stack in context -@ @ restore - B __tx_fiq_processing_return @ Continue FIQ processing +@ @ or stripped off the stack in context +@ @ restore + B __tx_fiq_processing_return @ Continue FIQ processing @ @ } -@} +@} diff --git a/ports/arm9/gnu/src/tx_thread_fiq_nesting_end.S b/ports/arm9/gnu/src/tx_thread_fiq_nesting_end.S index ded353be..1d7ebb34 100644 --- a/ports/arm9/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/arm9/gnu/src/tx_thread_fiq_nesting_end.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -27,7 +27,7 @@ DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts #else DISABLE_INTS = 0x80 @ Disable IRQ interrupts #endif -MODE_MASK = 0x1F @ Mode mask +MODE_MASK = 0x1F @ Mode mask FIQ_MODE_BITS = 0x11 @ FIQ mode bits @ @ @@ -37,54 +37,45 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_fiq_nesting_end ARM9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_end ARM9/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from FIQ mode after */ -@/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ -@/* processing from system mode back to FIQ mode prior to the ISR */ -@/* calling _tx_thread_fiq_context_restore. Note that this function */ -@/* assumes the system stack pointer is in the same position after */ -@/* nesting start function was called. */ -@/* */ -@/* This function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with FIQ interrupts disabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +@/* processing from system mode back to FIQ mode prior to the ISR */ +@/* calling _tx_thread_fiq_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_end(VOID) @@ -96,7 +87,7 @@ _tx_thread_fiq_nesting_end: MRS r0, CPSR @ Pickup the CPSR ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value MSR CPSR_cxsf, r0 @ Disable interrupts - LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for @ 8-byte alignment logic) BIC r0, r0, #MODE_MASK @ Clear mode bits ORR r0, r0, #FIQ_MODE_BITS @ Build IRQ mode CPSR diff --git a/ports/arm9/gnu/src/tx_thread_fiq_nesting_start.S b/ports/arm9/gnu/src/tx_thread_fiq_nesting_start.S index be12db77..d23b9fc0 100644 --- a/ports/arm9/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/arm9/gnu/src/tx_thread_fiq_nesting_start.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -33,51 +33,42 @@ SYS_MODE_BITS = 0x1F @ System mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_fiq_nesting_start ARM9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_start ARM9/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from FIQ mode after */ -@/* _tx_thread_fiq_context_save has been called and switches the FIQ */ -@/* processing to the system mode so nested FIQ interrupt processing */ -@/* is possible (system mode has its own "lr" register). Note that */ -@/* this function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with FIQ interrupts enabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +@/* processing to the system mode so nested FIQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/arm9/gnu/src/tx_thread_interrupt_control.S b/ports/arm9/gnu/src/tx_thread_interrupt_control.S index 2c72a853..9b0a2a0a 100644 --- a/ports/arm9/gnu/src/tx_thread_interrupt_control.S +++ b/ports/arm9/gnu/src/tx_thread_interrupt_control.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -35,7 +35,7 @@ INT_MASK = 0x03F $_tx_thread_interrupt_control: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_interrupt_control @ Call _tx_thread_interrupt_control function @@ -45,45 +45,36 @@ $_tx_thread_interrupt_control: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_interrupt_control ARM9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control ARM9/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is responsible for changing the interrupt lockout */ -@/* posture of the system. */ -@/* */ -@/* INPUT */ -@/* */ -@/* new_posture New interrupt lockout posture */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/arm9/gnu/src/tx_thread_interrupt_disable.S b/ports/arm9/gnu/src/tx_thread_interrupt_disable.S index dbd7a6db..cd4cf204 100644 --- a/ports/arm9/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/arm9/gnu/src/tx_thread_interrupt_disable.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -38,7 +38,7 @@ DISABLE_INTS = 0x80 @ IRQ interrupts disabled $_tx_thread_interrupt_disable: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_interrupt_disable @ Call _tx_thread_interrupt_disable function @@ -48,44 +48,35 @@ $_tx_thread_interrupt_disable: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_interrupt_disable ARM9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_disable ARM9/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is responsible for disabling interrupts */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function is responsible for disabling interrupts */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_disable(void) diff --git a/ports/arm9/gnu/src/tx_thread_interrupt_restore.S b/ports/arm9/gnu/src/tx_thread_interrupt_restore.S index e30d3577..4ae750f1 100644 --- a/ports/arm9/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/arm9/gnu/src/tx_thread_interrupt_restore.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -31,7 +31,7 @@ $_tx_thread_interrupt_restore: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_interrupt_restore @ Call _tx_thread_interrupt_restore function @@ -41,45 +41,36 @@ $_tx_thread_interrupt_restore: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_interrupt_restore ARM9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_restore ARM9/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ +@/* */ @/* This function is responsible for restoring interrupts to the state */ @/* returned by a previous _tx_thread_interrupt_disable call. */ -@/* */ -@/* INPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* INPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/arm9/gnu/src/tx_thread_irq_nesting_end.S b/ports/arm9/gnu/src/tx_thread_irq_nesting_end.S index afbca2cf..d26c93ff 100644 --- a/ports/arm9/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/arm9/gnu/src/tx_thread_irq_nesting_end.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -27,7 +27,7 @@ DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts #else DISABLE_INTS = 0x80 @ Disable IRQ interrupts #endif -MODE_MASK = 0x1F @ Mode mask +MODE_MASK = 0x1F @ Mode mask IRQ_MODE_BITS = 0x12 @ IRQ mode bits @ @ @@ -37,54 +37,45 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_irq_nesting_end ARM9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_end ARM9/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from IRQ mode after */ -@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -@/* processing from system mode back to IRQ mode prior to the ISR */ -@/* calling _tx_thread_context_restore. Note that this function */ -@/* assumes the system stack pointer is in the same position after */ -@/* nesting start function was called. */ -@/* */ -@/* This function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with IRQ interrupts disabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +@/* processing from system mode back to IRQ mode prior to the ISR */ +@/* calling _tx_thread_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_end(VOID) @@ -96,7 +87,7 @@ _tx_thread_irq_nesting_end: MRS r0, CPSR @ Pickup the CPSR ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value MSR CPSR_cxsf, r0 @ Disable interrupts - LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for @ 8-byte alignment logic) BIC r0, r0, #MODE_MASK @ Clear mode bits ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR diff --git a/ports/arm9/gnu/src/tx_thread_irq_nesting_start.S b/ports/arm9/gnu/src/tx_thread_irq_nesting_start.S index 060a471c..8c5d8642 100644 --- a/ports/arm9/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/arm9/gnu/src/tx_thread_irq_nesting_start.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -33,51 +33,42 @@ SYS_MODE_BITS = 0x1F @ System mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_irq_nesting_start ARM9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_start ARM9/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from IRQ mode after */ -@/* _tx_thread_context_save has been called and switches the IRQ */ -@/* processing to the system mode so nested IRQ interrupt processing */ -@/* is possible (system mode has its own "lr" register). Note that */ -@/* this function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with IRQ interrupts enabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_context_save has been called and switches the IRQ */ +@/* processing to the system mode so nested IRQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/arm9/gnu/src/tx_thread_schedule.S b/ports/arm9/gnu/src/tx_thread_schedule.S index 50affb8c..2cd8d04f 100644 --- a/ports/arm9/gnu/src/tx_thread_schedule.S +++ b/ports/arm9/gnu/src/tx_thread_schedule.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -45,7 +45,7 @@ ENABLE_INTS = 0x80 @ IRQ Interrupts enabled mask $_tx_thread_schedule: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_schedule @ Call _tx_thread_schedule function @@ -55,48 +55,39 @@ $_tx_thread_schedule: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_schedule ARM9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_schedule ARM9/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function waits for a thread control block pointer to appear in */ -@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -@/* in the variable, the corresponding thread is resumed. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_initialize_kernel_enter ThreadX entry function */ -@/* _tx_thread_system_return Return to system from thread */ -@/* _tx_thread_context_restore Restore thread's context */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function waits for a thread control block pointer to appear in */ +@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +@/* in the variable, the corresponding thread is resumed. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* _tx_thread_system_return Return to system from thread */ +@/* _tx_thread_context_restore Restore thread's context */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) @@ -124,7 +115,7 @@ __tx_thread_schedule_loop: @ @ } @ while(_tx_thread_execute_ptr == TX_NULL); -@ +@ @ /* Yes! We have a thread to execute. Lockout interrupts and @ transfer control to it. */ @ @@ -133,7 +124,7 @@ __tx_thread_schedule_loop: @ /* Setup the current thread pointer. */ @ _tx_thread_current_ptr = _tx_thread_execute_ptr; @ - LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread STR r0, [r1] @ Setup current thread pointer @ @ /* Increment the run count for this thread. */ @@ -147,7 +138,7 @@ __tx_thread_schedule_loop: @ /* Setup time-slice, if present. */ @ _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; @ - LDR r2, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r2, =_tx_timer_time_slice @ Pickup address of time-slice @ variable LDR sp, [r0, #8] @ Switch stack pointers STR r3, [r2] @ Setup time-slice diff --git a/ports/arm9/gnu/src/tx_thread_stack_build.S b/ports/arm9/gnu/src/tx_thread_stack_build.S index 675c1f4f..14ff4181 100644 --- a/ports/arm9/gnu/src/tx_thread_stack_build.S +++ b/ports/arm9/gnu/src/tx_thread_stack_build.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -42,7 +42,7 @@ CPSR_MASK = 0x9F @ Mask initial CPSR, IRQ interru .type $_tx_thread_stack_build,function $_tx_thread_stack_build: BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_stack_build @ Call _tx_thread_stack_build function @@ -52,47 +52,38 @@ $_tx_thread_stack_build: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_stack_build ARM9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build ARM9/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ +@/* */ @/* This function builds a stack frame on the supplied thread's stack. */ @/* The stack frame results in a fake interrupt return to the supplied */ -@/* function pointer. */ -@/* */ -@/* INPUT */ -@/* */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ @/* thread_ptr Pointer to thread control blk */ @/* function_ptr Pointer to return function */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_thread_create Create thread service */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -101,10 +92,10 @@ $_tx_thread_stack_build: .type _tx_thread_stack_build,function _tx_thread_stack_build: @ -@ +@ @ /* Build a fake interrupt frame. The form of the fake interrupt stack @ on the ARM9 should look like the following after it is built: -@ +@ @ Stack Top: 1 Interrupt stack frame type @ CPSR Initial value for CPSR @ a1 (r0) Initial value for a1 diff --git a/ports/arm9/gnu/src/tx_thread_system_return.S b/ports/arm9/gnu/src/tx_thread_system_return.S index ba0ed9bb..e551a18b 100644 --- a/ports/arm9/gnu/src/tx_thread_system_return.S +++ b/ports/arm9/gnu/src/tx_thread_system_return.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -48,7 +48,7 @@ DISABLE_INTS = 0x80 @ IRQ interrupts disabled $_tx_thread_system_return: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_system_return @ Call _tx_thread_system_return function @@ -58,47 +58,38 @@ $_tx_thread_system_return: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_system_return ARM9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return ARM9/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is target processor specific. It is used to transfer */ -@/* control from a thread back to the ThreadX system. Only a */ -@/* minimal context is saved since the compiler assumes temp registers */ -@/* are going to get slicked by a function call anyway. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling loop */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX components */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ @/* */ @/**************************************************************************/ @VOID _tx_thread_system_return(VOID) @@ -112,12 +103,12 @@ _tx_thread_system_return: MOV r0, #0 @ Build a solicited stack type MRS r1, CPSR @ Pickup the CPSR STMDB sp!, {r0-r1, r4-r11, lr} @ Save minimal context -@ +@ @ /* Lockout interrupts. */ @ ORR r2, r1, #DISABLE_INTS @ Build disable interrupt CPSR MSR CPSR_cxsf, r2 @ Disable interrupts - + #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY @ @ /* Call the thread exit function to indicate the thread is no longer executing. */ diff --git a/ports/arm9/gnu/src/tx_thread_vectored_context_save.S b/ports/arm9/gnu/src/tx_thread_vectored_context_save.S index d123e054..3f56304d 100644 --- a/ports/arm9/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/arm9/gnu/src/tx_thread_vectored_context_save.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -37,50 +37,41 @@ DISABLE_INTS = 0x80 @ IRQ interrupts disabled @ @/* No 16-bit Thumb mode veneer code is needed for _tx_thread_vectored_context_save @ since it will never be called 16-bit mode. */ -@ +@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_vectored_context_save ARM9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_vectored_context_save ARM9/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function saves the context of an executing thread in the */ -@/* beginning of interrupt processing. The function also ensures that */ -@/* the system stack is used upon return to the calling ISR. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_vectored_context_save(VOID) @@ -140,7 +131,7 @@ __tx_thread_not_nested_save: LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr LDR r0, [r1, #0] @ Pickup current thread pointer CMP r0, #0 @ Is it NULL? - BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in @ scheduling loop - nothing needs saving! @ @ /* Note: Minimal context of interrupted thread is already saved. */ @@ -172,7 +163,7 @@ __tx_thread_idle_system_save: @ @ /* Interrupt occurred in the scheduling loop. */ @ -@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ @ processing. */ @ MOV r10, #0 @ Clear stack limit diff --git a/ports/arm9/gnu/src/tx_timer_interrupt.S b/ports/arm9/gnu/src/tx_timer_interrupt.S index 48bee7f7..9ae148bf 100644 --- a/ports/arm9/gnu/src/tx_timer_interrupt.S +++ b/ports/arm9/gnu/src/tx_timer_interrupt.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Timer */ @/** */ @@ -48,7 +48,7 @@ .type $_tx_timer_interrupt,function $_tx_timer_interrupt: BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_timer_interrupt @ Call _tx_timer_interrupt function @@ -58,49 +58,40 @@ $_tx_timer_interrupt: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_timer_interrupt ARM9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt ARM9/GNU */ @/* 6.2.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function processes the hardware timer interrupt. This */ -@/* processing includes incrementing the system clock and checking for */ -@/* time slice and/or timer expiration. If either is found, the */ -@/* interrupt context save/restore functions are called along with the */ -@/* expiration functions. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_time_slice Time slice interrupted thread */ -@/* _tx_timer_expiration_process Timer expiration processing */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* interrupt vector */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Cindy Deng Modified comment(s), added */ -@/* #include tx_user.h, */ -@/* resulting in version 6.2.1 */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) @@ -125,7 +116,7 @@ _tx_timer_interrupt: @ if (_tx_timer_time_slice) @ { @ - LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice LDR r2, [r3] @ Pickup time-slice CMP r2, #0 @ Is it non-active? BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing @@ -243,7 +234,7 @@ __tx_timer_dont_activate: @ if (_tx_timer_expired_time_slice) @ { @ - LDR r3, =_tx_timer_expired_time_slice @ Pickup address of time-slice expired + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of time-slice expired LDR r2, [r3] @ Pickup the actual flag CMP r2, #0 @ See if the flag is set BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing diff --git a/ports/arm9/iar/example_build/cstartup.s b/ports/arm9/iar/example_build/cstartup.s index b95efc0e..3da2b79d 100644 --- a/ports/arm9/iar/example_build/cstartup.s +++ b/ports/arm9/iar/example_build/cstartup.s @@ -1,7 +1,7 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; -;; Part one of the system initialization code, +;; Part one of the system initialization code, ;; contains low-level ;; initialization. ;; @@ -71,13 +71,13 @@ FIQ_Addr: DCD __tx_fiq_handler SECTION .text:CODE:NOROOT(2) -; PUBLIC ?cstartup +; PUBLIC ?cstartup EXTERN ?main REQUIRE __vector - ARM - -__iar_program_start: + ARM + +__iar_program_start: ?cstartup: ; diff --git a/ports/arm9/iar/example_build/sample_threadx.c b/ports/arm9/iar/example_build/sample_threadx.c index 68cd97fe..56f7cd55 100644 --- a/ports/arm9/iar/example_build/sample_threadx.c +++ b/ports/arm9/iar/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -85,42 +85,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -128,23 +128,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -247,11 +247,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -310,7 +310,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -363,7 +363,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/arm9/iar/example_build/tx_initialize_low_level.s b/ports/arm9/iar/example_build/tx_initialize_low_level.s index 89024b8e..103d72d6 100644 --- a/ports/arm9/iar/example_build/tx_initialize_low_level.s +++ b/ports/arm9/iar/example_build/tx_initialize_low_level.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -62,7 +62,7 @@ SYS_MODE DEFINE 0xDF ; Disable irq,fiq SYS mode ; ; ; -;/* Define the FREE_MEM segment that will specify where free memory is +;/* Define the FREE_MEM segment that will specify where free memory is ; defined. This must also be located in at the end of other RAM segments ; in the linker control file. The value of this segment is what is passed ; to tx_application_define. */ @@ -75,45 +75,39 @@ __tx_free_memory_start ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level ARM9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level ARM9/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -146,7 +140,7 @@ _tx_initialize_low_level ; LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address STR r0, [r2, #0] ; Save first free memory address -; +; ; /* Setup Timer for periodic interrupts. */ ; ; /* Done, return to caller. */ @@ -188,7 +182,7 @@ __tx_reserved_handler RSEG .text:CODE:NOROOT(2) PUBLIC __tx_irq_handler RSEG .text:CODE:NOROOT(2) - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -196,17 +190,17 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -221,7 +215,7 @@ __tx_irq_processing_return ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -240,22 +234,22 @@ __tx_irq_processing_return ; /* Jump to context save to save system context. */ ; STMDB sp!, {r0-r3} ; Save some scratch registers ; MRS r0, SPSR ; Pickup saved SPSR -; SUB lr, lr, #4 ; Adjust point of interrupt +; SUB lr, lr, #4 ; Adjust point of interrupt ; STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; BL _tx_thread_vectored_context_save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ;#ifdef TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_start @@ -264,7 +258,7 @@ __tx_irq_processing_return ; /* Application IRQ handler is called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ;#ifdef TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_end @@ -288,11 +282,11 @@ __tx_fiq_processing_return ; /* At this point execution is still in the FIQ mode. The CPSR, point of ; interrupt, and all C scratch registers are available for use. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start ; from FIQ mode with interrupts disabled. This routine switches to the -; system mode and returns with FIQ interrupts enabled. +; system mode and returns with FIQ interrupts enabled. ; -; NOTE: It is very important to ensure all FIQ interrupts are cleared +; NOTE: It is very important to ensure all FIQ interrupts are cleared ; prior to enabling nested FIQ interrupts. */ #ifdef TX_ENABLE_FIQ_NESTING BL _tx_thread_fiq_nesting_start diff --git a/ports/arm9/iar/inc/tx_port.h b/ports/arm9/iar/inc/tx_port.h index f75d6048..e4411ae6 100644 --- a/ports/arm9/iar/inc/tx_port.h +++ b/ports/arm9/iar/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h ARM9/IAR */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h ARM9/IAR */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -79,7 +71,7 @@ #endif -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -115,12 +107,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -130,8 +122,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -188,7 +180,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -202,17 +194,17 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -226,11 +218,11 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -240,23 +232,23 @@ ULONG _tx_misra_time_stamp_get(VOID); #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #if (__VER__ < 8000000) -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #endif #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -284,8 +276,8 @@ void __iar_Initlocks(void); #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -296,22 +288,22 @@ void __iar_Initlocks(void); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (UINT) __CLZ(m); \ - b = 31 - b; + b = 31 - b; #endif #endif #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ /* First, check and see what mode the file is being compiled in. The IAR compiler - defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode + defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode is present. If ARM 32-bit mode is present, the fast CPSR manipulation macros are available. Otherwise, if Thumb mode is present, we must use function calls. */ @@ -373,8 +365,8 @@ void _tx_thread_interrupt_restore(UINT old_posture); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARM9/IAR Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARM9/IAR Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/arm9/iar/readme_threadx.txt b/ports/arm9/iar/readme_threadx.txt index 3f394604..7ce5c317 100644 --- a/ports/arm9/iar/readme_threadx.txt +++ b/ports/arm9/iar/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for ARM9 + Microsoft's Azure RTOS ThreadX for ARM9 Thumb & 32-bit Mode @@ -7,10 +7,10 @@ 1. Building the ThreadX run-time Library Building the ThreadX library is easy. First, open the Azure RTOS workspace -azure_rtos.eww. Next, make the TX project the "active project" in the -IAR Embedded Workbench and select the "Make" button. You should observe -assembly and compilation of a series of ThreadX source files. This -results in the ThreadX run-time library file tx.a, which is needed by +azure_rtos.eww. Next, make the TX project the "active project" in the +IAR Embedded Workbench and select the "Make" button. You should observe +assembly and compilation of a series of ThreadX source files. This +results in the ThreadX run-time library file tx.a, which is needed by the application. @@ -20,52 +20,52 @@ The ThreadX demonstration is designed to execute under the IAR Windows-based ARM9 simulator. Building the demonstration is easy; simply make the sample_threadx.ewp project -the "active project" in the IAR Embedded Workbench and select the +the "active project" in the IAR Embedded Workbench and select the "Make" button. -You should observe the compilation of sample_threadx.c (which is the demonstration +You should observe the compilation of sample_threadx.c (which is the demonstration application) and linking with tx.a. The resulting file sample_threadx.out is a binary file that can be downloaded and executed on IAR's ARM9 simulator. A SPECIAL NOTE: The IAR ARM simulator does simulate interrupts. In order -for the ThreadX demonstration to run properly, a periodic IRQ interrupt must +for the ThreadX demonstration to run properly, a periodic IRQ interrupt must be setup in the IAR debugging environment. We recommend setting an IRQ interrupt to execute every 9999 cycles. 3. System Initialization -The entry point in ThreadX for the ARM9 using IAR tools is at label -?cstartup. This is defined within the IAR compiler's startup code. In -addition, this is where all static and global preset C variable +The entry point in ThreadX for the ARM9 using IAR tools is at label +?cstartup. This is defined within the IAR compiler's startup code. In +addition, this is where all static and global preset C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, and a periodic timer interrupt source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. By default, the vector area is defined at the top of cstartup.s, which is -a slightly modified from the base IAR file. +a slightly modified from the base IAR file. The _tx_initialize_low_level function inside of tx_initialize_low_level.s -also determines the first available address for use by the application, which -is supplied as the sole input parameter to your application definition function, -tx_application_define. To accomplish this, a section is created in -tx_initialize_low_level.s called FREE_MEM, which must be located after all +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all other RAM sections in memory. 4. Register Usage and Stack Frames -The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are -scratch registers for each function. All other registers used by a C function -must be preserved by the function. ThreadX takes advantage of this in -situations where a context switch happens as a result of making a ThreadX -service call (which is itself a C function). In such cases, the saved +The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are +scratch registers for each function. All other registers used by a C function +must be preserved by the function. ThreadX takes advantage of this in +situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -83,12 +83,12 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 5. Conditional Compilation Switches @@ -97,146 +97,146 @@ The following are conditional compilation options for building the ThreadX libra and application: - TX_ENABLE_FIQ_SUPPORT This assembler/compiler define enables + TX_ENABLE_FIQ_SUPPORT This assembler/compiler define enables FIQ interrupt handling support in the ThreadX assembly files. If used, it should be used on all assembly files and the generic C source of - ThreadX should be compiled with + ThreadX should be compiled with TX_ENABLE_FIQ_SUPPORT defined as well. TX_ENABLE_IRQ_NESTING This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. TX_ENABLE_FIQ_NESTING This assembler define enables FIQ - nested support. If FIQ nested + nested support. If FIQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. In addition, IRQ nesting should also be enabled. TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - TX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. TX_THUMB Defined, this option enables the BX LR calling return sequence @@ -250,29 +250,29 @@ and application: 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the ThreadX library -project to enable various compiler optimizations. +project to enable various compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for ARM9 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The ARM9 vectors start at address zero. The demonstration system startup -cstartup.s file contains the vectors and is loaded at address zero. -On actual hardware platforms, this area might have to be copied to address 0. +cstartup.s file contains the vectors and is loaded at address zero. +On actual hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs @@ -283,12 +283,12 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.s: PUBLIC __tx_irq_handler - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -296,7 +296,7 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -309,7 +309,7 @@ __tx_irq_processing_return 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.s: @@ -320,12 +320,12 @@ __tx_example_vectored_irq_handler ; /* Jump to context save to save system context. */ STMDB sp!, {r0-r3} ; Save some scratch registers MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers BL _tx_thread_vectored_context_save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -342,24 +342,24 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.s. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables -nesting by disabling IRQ interrupts and switching back to IRQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: RSEG .text:CODE:NOROOT(2) PUBLIC __tx_irq_handler RSEG .text:CODE:NOROOT(2) - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -367,15 +367,15 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ; BL _tx_thread_irq_nesting_start @@ -383,7 +383,7 @@ __tx_irq_processing_return ; /* Application ISR dispatch call goes here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ; BL _tx_thread_irq_nesting_end @@ -394,12 +394,12 @@ __tx_irq_processing_return 7.3 FIQ Interrupts -By default, ARM9 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, ARM9 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.s. @@ -408,7 +408,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.s. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.s: @@ -439,18 +439,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.s. When nested FIQ interrupts are no -longer required, calling the _tx_thread_fiq_nesting_end service disables -nesting by disabling FIQ interrupts and switching back to FIQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested FIQ interrupts are no +longer required, calling the _tx_thread_fiq_nesting_end service disables +nesting by disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -468,7 +468,7 @@ __tx_fiq_processing_return: ; interrupt, and all C scratch registers are available for use. */ ; ; /* Enable nested FIQ interrupts. NOTE: Since this service returns -; with FIQ interrupts enabled, all FIQ interrupt sources must be +; with FIQ interrupts enabled, all FIQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start ; @@ -484,22 +484,22 @@ __tx_fiq_processing_return: 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to _tx_timer_interrupt +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. 9. Thumb/ARM9 Mixed Mode -By default, ThreadX is setup for running in ARM9 32-bit mode. This is -also true for the demonstration system. It is possible to build any +By default, ThreadX is setup for running in ARM9 32-bit mode. This is +also true for the demonstration system. It is possible to build any ThreadX file and/or the application in Thumb mode. The only exception -to this is the file tx_thread_shell_entry.c. This file must always be -built in 32-bit mode. In addition, if any Thumb code is used the entire +to this is the file tx_thread_shell_entry.c. This file must always be +built in 32-bit mode. In addition, if any Thumb code is used the entire ThreadX assembly source should be built with TX_THUMB defined. diff --git a/ports/arm9/iar/src/tx_iar.c b/ports/arm9/iar/src/tx_iar.c index 158738ea..238b485e 100644 --- a/ports/arm9/iar/src/tx_iar.c +++ b/ports/arm9/iar/src/tx_iar.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** IAR Multithreaded Library Support */ /** */ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports/arm9/iar/src/tx_thread_context_restore.s b/ports/arm9/iar/src/tx_thread_context_restore.s index ac57cd96..51450dd5 100644 --- a/ports/arm9/iar/src/tx_thread_context_restore.s +++ b/ports/arm9/iar/src/tx_thread_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,7 +36,7 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask THUMB_MASK DEFINE 0x20 ; Thumb bit mask SVC_MODE_BITS DEFINE 0x13 ; SVC mode value @@ -50,44 +50,38 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value EXTERN _tx_execution_isr_exit ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore ARM9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore ARM9/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -117,13 +111,13 @@ _tx_thread_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3, #0] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3, #0] ; Store the counter + STR r2, [r3, #0] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs diff --git a/ports/arm9/iar/src/tx_thread_context_save.s b/ports/arm9/iar/src/tx_thread_context_save.s index db77a17b..eeadaa24 100644 --- a/ports/arm9/iar/src/tx_thread_context_save.s +++ b/ports/arm9/iar/src/tx_thread_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -44,43 +44,37 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save ARM9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save ARM9/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -97,7 +91,7 @@ _tx_thread_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt CPSR @@ -117,7 +111,7 @@ _tx_thread_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -133,7 +127,7 @@ _tx_thread_context_save POP {lr} ; Recover ISR lr #endif - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; __tx_thread_not_nested_save ; } @@ -147,13 +141,13 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} ; Store other registers ; ; /* Save the current stack pointer in the thread's control block. */ @@ -173,7 +167,7 @@ __tx_thread_not_nested_save POP {lr} ; Recover ISR lr #endif - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ; else @@ -183,7 +177,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit @@ -198,7 +192,7 @@ __tx_thread_idle_system_save #endif ADD sp, sp, #16 ; Recover saved registers - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ;} diff --git a/ports/arm9/iar/src/tx_thread_fiq_context_restore.s b/ports/arm9/iar/src/tx_thread_fiq_context_restore.s index 137714b6..1fd57ad0 100644 --- a/ports/arm9/iar/src/tx_thread_fiq_context_restore.s +++ b/ports/arm9/iar/src/tx_thread_fiq_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -37,7 +37,7 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask THUMB_MASK DEFINE 0x20 ; Thumb bit mask IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits SVC_MODE_BITS DEFINE 0x13 ; SVC mode value @@ -52,44 +52,38 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value EXTERN _tx_execution_isr_exit ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_restore ARM9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore ARM9/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the fiq interrupt context when processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* FIQ ISR Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) @@ -119,13 +113,13 @@ _tx_thread_fiq_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3] ; Store the counter + STR r2, [r3] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -169,7 +163,7 @@ __tx_thread_fiq_no_preempt_restore ; /* Restore interrupted thread or ISR. */ ; ; /* Pickup the saved stack pointer. */ -; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; ; ; /* Recover the saved context and return to the point of interrupt. */ ; @@ -216,7 +210,7 @@ __tx_thread_fiq_preempt_restore BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it ; ; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; -; _tx_timer_time_slice = 0; +; _tx_timer_time_slice = 0; ; STR r2, [r0, #24] ; Save thread's time-slice MOV r2, #0 ; Clear value diff --git a/ports/arm9/iar/src/tx_thread_fiq_context_save.s b/ports/arm9/iar/src/tx_thread_fiq_context_save.s index 562d5132..38e7e568 100644 --- a/ports/arm9/iar/src/tx_thread_fiq_context_save.s +++ b/ports/arm9/iar/src/tx_thread_fiq_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,43 +36,37 @@ EXTERN _tx_execution_isr_enter ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_save ARM9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save ARM9/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) @@ -89,7 +83,7 @@ _tx_thread_fiq_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state CMP r2, #0 ; Is this the first interrupt? @@ -104,7 +98,7 @@ _tx_thread_fiq_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -120,38 +114,38 @@ _tx_thread_fiq_context_save POP {lr} ; Recover ISR lr #endif - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; __tx_thread_fiq_not_nested_save -; } +; } ; ; /* Otherwise, not nested, check to see if a thread was running. */ ; else if (_tx_thread_current_ptr) -; { +; { ; ADD r2, r2, #1 ; Increment the interrupt counter STR r2, [r3] ; Store it back in the variable LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in -; ; scheduling loop - nothing needs saving! + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, lr} ; Store other registers, Note that we don't -; ; need to save sl and ip since FIQ has -; ; copies of these registers. Nested +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested ; ; interrupt processing does need to save ; ; these registers. ; ; /* Save the current stack pointer in the thread's control block. */ -; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; ; ; /* Switch to the system stack. */ -; sp = _tx_thread_system_stack_ptr; +; sp = _tx_thread_system_stack_ptr; ; MOV r10, #0 ; Clear stack limit @@ -164,7 +158,7 @@ __tx_thread_fiq_not_nested_save POP {lr} ; Recover ISR lr #endif - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } ; else @@ -184,18 +178,18 @@ __tx_thread_fiq_idle_system_save #endif ; ; /* Not much to do here, save the current SPSR and LR for possible -; use in IRQ interrupted in idle system conditions, and return to +; use in IRQ interrupted in idle system conditions, and return to ; FIQ interrupt processing. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, lr} ; Store other registers that will get used -; ; or stripped off the stack in context -; ; restore - B __tx_fiq_processing_return ; Continue FIQ processing +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } -;} +;} ; ; END diff --git a/ports/arm9/iar/src/tx_thread_fiq_nesting_end.s b/ports/arm9/iar/src/tx_thread_fiq_nesting_end.s index e3897977..e71cea18 100644 --- a/ports/arm9/iar/src/tx_thread_fiq_nesting_end.s +++ b/ports/arm9/iar/src/tx_thread_fiq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,55 +34,49 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_end ARM9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end ARM9/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ -;/* processing from system mode back to FIQ mode prior to the ISR */ -;/* calling _tx_thread_fiq_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s79). */ -;/* */ -;/* This function returns with FIQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/arm9/iar/src/tx_thread_fiq_nesting_start.s b/ports/arm9/iar/src/tx_thread_fiq_nesting_start.s index 41867e49..d9d0fb14 100644 --- a/ports/arm9/iar/src/tx_thread_fiq_nesting_start.s +++ b/ports/arm9/iar/src/tx_thread_fiq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ MODE_MASK DEFINE 0x1F ; Mode mask SYS_MODE_BITS DEFINE 0x1F ; System mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_start ARM9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start ARM9/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ -;/* processing to the system mode so nested FIQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s79). */ -;/* */ -;/* This function returns with FIQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/arm9/iar/src/tx_thread_interrupt_control.s b/ports/arm9/iar/src/tx_thread_interrupt_control.s index a6d540a7..82ccae6e 100644 --- a/ports/arm9/iar/src/tx_thread_interrupt_control.s +++ b/ports/arm9/iar/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,42 +35,36 @@ INT_MASK DEFINE 0x80 ; Interrupt bit mask #endif ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control ARM9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control ARM9/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/arm9/iar/src/tx_thread_interrupt_disable.s b/ports/arm9/iar/src/tx_thread_interrupt_disable.s index 64c7508a..5a5cd20c 100644 --- a/ports/arm9/iar/src/tx_thread_interrupt_disable.s +++ b/ports/arm9/iar/src/tx_thread_interrupt_disable.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,41 +36,35 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable ARM9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable ARM9/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/arm9/iar/src/tx_thread_interrupt_restore.s b/ports/arm9/iar/src/tx_thread_interrupt_restore.s index deace508..945993e0 100644 --- a/ports/arm9/iar/src/tx_thread_interrupt_restore.s +++ b/ports/arm9/iar/src/tx_thread_interrupt_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -28,42 +28,36 @@ ;#include "tx_thread.h" ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore ARM9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore ARM9/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function is responsible for restoring interrupts to the state */ ;/* returned by a previous _tx_thread_interrupt_disable call. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;void _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/arm9/iar/src/tx_thread_irq_nesting_end.s b/ports/arm9/iar/src/tx_thread_irq_nesting_end.s index ff38c1ca..54003548 100644 --- a/ports/arm9/iar/src/tx_thread_irq_nesting_end.s +++ b/ports/arm9/iar/src/tx_thread_irq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,55 +35,49 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_end ARM9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end ARM9/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -;/* processing from system mode back to IRQ mode prior to the ISR */ -;/* calling _tx_thread_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s79). */ -;/* */ -;/* This function returns with IRQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/arm9/iar/src/tx_thread_irq_nesting_start.s b/ports/arm9/iar/src/tx_thread_irq_nesting_start.s index 5e08187c..5b13d528 100644 --- a/ports/arm9/iar/src/tx_thread_irq_nesting_start.s +++ b/ports/arm9/iar/src/tx_thread_irq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ MODE_MASK DEFINE 0x1F ; Mode mask SYS_MODE_BITS DEFINE 0x1F ; System mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_start ARM9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start ARM9/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_context_save has been called and switches the IRQ */ -;/* processing to the system mode so nested IRQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s79). */ -;/* */ -;/* This function returns with IRQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/arm9/iar/src/tx_thread_schedule.s b/ports/arm9/iar/src/tx_thread_schedule.s index 86a70a4f..89c875c9 100644 --- a/ports/arm9/iar/src/tx_thread_schedule.s +++ b/ports/arm9/iar/src/tx_thread_schedule.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -43,45 +43,39 @@ ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule ARM9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule ARM9/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -111,7 +105,7 @@ __tx_thread_schedule_loop ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Lockout interrupts and ; transfer control to it. */ ; @@ -120,7 +114,7 @@ __tx_thread_schedule_loop ; /* Setup the current thread pointer. */ ; _tx_thread_current_ptr = _tx_thread_execute_ptr; ; - LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread STR r0, [r1, #0] ; Setup current thread pointer ; ; /* Increment the run count for this thread. */ @@ -134,7 +128,7 @@ __tx_thread_schedule_loop ; /* Setup time-slice, if present. */ ; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; ; - LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice ; variable LDR sp, [r0, #8] ; Switch stack pointers STR r3, [r2, #0] ; Setup time-slice diff --git a/ports/arm9/iar/src/tx_thread_stack_build.s b/ports/arm9/iar/src/tx_thread_stack_build.s index c59c61f4..cd10adb1 100644 --- a/ports/arm9/iar/src/tx_thread_stack_build.s +++ b/ports/arm9/iar/src/tx_thread_stack_build.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -37,58 +37,52 @@ CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints en #endif ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build ARM9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build ARM9/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function builds a stack frame on the supplied thread's stack. */ ;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ ;/* thread_ptr Pointer to thread control blk */ ;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) ;{ RSEG .text:CODE:NOROOT(2) PUBLIC _tx_thread_stack_build - + CODE32 _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the ARM9 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; a1 (r0) Initial value for a1 diff --git a/ports/arm9/iar/src/tx_thread_system_return.s b/ports/arm9/iar/src/tx_thread_system_return.s index e8660d9b..d428d4a6 100644 --- a/ports/arm9/iar/src/tx_thread_system_return.s +++ b/ports/arm9/iar/src/tx_thread_system_return.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -42,44 +42,38 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return ARM9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return ARM9/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -95,7 +89,7 @@ _tx_thread_system_return MOV r0, #0 ; Build a solicited stack type MRS r1, CPSR ; Pickup the CPSR STMDB sp!, {r0-r1, r4-r11, lr} ; Save minimal context -; +; ; /* Lockout interrupts. */ ; ORR r2, r1, #DISABLE_INTS ; Build disable interrupt CPSR diff --git a/ports/arm9/iar/src/tx_thread_vectored_context_save.s b/ports/arm9/iar/src/tx_thread_vectored_context_save.s index 1aa26ae1..ce1b9d5b 100644 --- a/ports/arm9/iar/src/tx_thread_vectored_context_save.s +++ b/ports/arm9/iar/src/tx_thread_vectored_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -41,43 +41,37 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled EXTERN _tx_execution_isr_enter ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_vectored_context_save ARM9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save ARM9/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) @@ -139,7 +133,7 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in ; scheduling loop - nothing needs saving! ; ; /* Note: Minimal context of interrupted thread is already saved. */ @@ -171,7 +165,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports/arm9/iar/src/tx_timer_interrupt.s b/ports/arm9/iar/src/tx_timer_interrupt.s index 28bac145..367e629f 100644 --- a/ports/arm9/iar/src/tx_timer_interrupt.s +++ b/ports/arm9/iar/src/tx_timer_interrupt.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -43,46 +43,40 @@ ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt ARM9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt ARM9/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time-slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time-slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -108,7 +102,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CMP r2, #0 ; Is it non-active? BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing @@ -226,13 +220,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CMP r2, #0 ; See if the flag is set BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing ; diff --git a/ports/c667x/ccs/example_build/include/C66XX.h b/ports/c667x/ccs/example_build/include/C66XX.h index 581b563e..80507ca2 100644 --- a/ports/c667x/ccs/example_build/include/C66XX.h +++ b/ports/c667x/ccs/example_build/include/C66XX.h @@ -52,7 +52,7 @@ 3. This file is best viewed with the TAB setting set to '4'. - 4. This header file is externally controlled from user C-code by run-time + 4. This header file is externally controlled from user C-code by run-time compiler keys definitions in order to apply DSP-type specific definitions to refer to particular definitions included for different DSP type: diff --git a/ports/c667x/ccs/example_build/include/C66XX_DEF.hxx b/ports/c667x/ccs/example_build/include/C66XX_DEF.hxx index 9764a47f..0eb6a1d3 100644 --- a/ports/c667x/ccs/example_build/include/C66XX_DEF.hxx +++ b/ports/c667x/ccs/example_build/include/C66XX_DEF.hxx @@ -791,53 +791,53 @@ //============================================================================= //============ PLL controller registers ======================================= //============================================================================= -// PLL control register - r/w +// PLL control register - r/w #define C66XX_PLL_PLLCTL_RG_OFFSET 0x100 -// PLL secondary control register - r/w +// PLL secondary control register - r/w #define C66XX_PLL_SECCTL_RG_OFFSET 0x108 -// PLL multiplier control register - r/w +// PLL multiplier control register - r/w #define C66XX_PLL_PLLM_RG_OFFSET 0x110 -// PLL controller divider 1 register - r/w +// PLL controller divider 1 register - r/w #define C66XX_PLL_PLLDIV1_RG_OFFSET 0x118 -// PLL controller divider 2 register - r/w +// PLL controller divider 2 register - r/w #define C66XX_PLL_PLLDIV2_RG_OFFSET 0x11c -// PLL controller divider 3 register - r/w +// PLL controller divider 3 register - r/w #define C66XX_PLL_PLLDIV3_RG_OFFSET 0x120 -// PLL controller command register - r/w +// PLL controller command register - r/w #define C66XX_PLL_PLLCMD_RG_OFFSET 0x138 -// PLL controller status register - r/w +// PLL controller status register - r/w #define C66XX_PLL_PLLSTAT_RG_OFFSET 0x13c -// PLL controller clock align control register - r/w +// PLL controller clock align control register - r/w #define C66XX_PLL_ALNCTL_RG_OFFSET 0x140 -// PLL controller divider ratio change status register - r/w +// PLL controller divider ratio change status register - r/w #define C66XX_PLL_DCHANGE_RG_OFFSET 0x144 // SYSCLK status register - r-only #define C66XX_PLL_SYSTAT_RG_OFFSET 0x150 -// PLL controller divider 4 register - r/w +// PLL controller divider 4 register - r/w #define C66XX_PLL_PLLDIV4_RG_OFFSET 0x160 -// PLL controller divider 5 register - r/w +// PLL controller divider 5 register - r/w #define C66XX_PLL_PLLDIV5_RG_OFFSET 0x164 -// PLL controller divider 6 register - r/w +// PLL controller divider 6 register - r/w #define C66XX_PLL_PLLDIV6_RG_OFFSET 0x168 -// PLL controller divider 7 register - r/w +// PLL controller divider 7 register - r/w #define C66XX_PLL_PLLDIV7_RG_OFFSET 0x16c -// PLL controller divider 8 register - r/w +// PLL controller divider 8 register - r/w #define C66XX_PLL_PLLDIV8_RG_OFFSET 0x170 -// PLL controller divider 9 register - r/w +// PLL controller divider 9 register - r/w #define C66XX_PLL_PLLDIV9_RG_OFFSET 0x174 -// PLL controller divider 10 register - r/w +// PLL controller divider 10 register - r/w #define C66XX_PLL_PLLDIV10_RG_OFFSET 0x178 -// PLL controller divider 11 register - r/w +// PLL controller divider 11 register - r/w #define C66XX_PLL_PLLDIV11_RG_OFFSET 0x17c -// PLL controller divider 12 register - r/w +// PLL controller divider 12 register - r/w #define C66XX_PLL_PLLDIV12_RG_OFFSET 0x180 -// PLL controller divider 13 register - r/w +// PLL controller divider 13 register - r/w #define C66XX_PLL_PLLDIV13_RG_OFFSET 0x184 -// PLL controller divider 14 register - r/w +// PLL controller divider 14 register - r/w #define C66XX_PLL_PLLDIV14_RG_OFFSET 0x188 -// PLL controller divider 15 register - r/w +// PLL controller divider 15 register - r/w #define C66XX_PLL_PLLDIV15_RG_OFFSET 0x18c -// PLL controller divider 16 register - r/w +// PLL controller divider 16 register - r/w #define C66XX_PLL_PLLDIV16_RG_OFFSET 0x190 #define C66XX_PLL_PLLCTL_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLCTL_RG_OFFSET) diff --git a/ports/c667x/ccs/example_build/include/C66XX_FUNCTIONS.hxx b/ports/c667x/ccs/example_build/include/C66XX_FUNCTIONS.hxx index 8564e44d..8011bcac 100644 --- a/ports/c667x/ccs/example_build/include/C66XX_FUNCTIONS.hxx +++ b/ports/c667x/ccs/example_build/include/C66XX_FUNCTIONS.hxx @@ -775,7 +775,7 @@ uint32_t C66XX_INT_init_chip(uint32_t cpintc_id); * * System events are those events generated by a hardware module in the system. * These events are inputs into CPINTC. - * Host events are the output events of CPINTC, which act as event inputs to + * Host events are the output events of CPINTC, which act as event inputs to * C66x CorePac interrupt controllers (INTC). * * @param[in] cpintc_handle - chip interrupt controller handle returned by @@ -1372,7 +1372,7 @@ void C66XX_UART_transmit_string(char *s); * @brief Function receives a line ended with CR character, and stores * received characters into string with '\0' symbol. * - * Note that maximum received line length should not exceed + * Note that maximum received line length should not exceed * C66XX_UART_LINE_LEN_MAX value! * * @param[in] s - Pointer to a string to store received characters @@ -1626,7 +1626,7 @@ typedef struct * packets) and data streaming (Type11 packets) operations. * 2. Max MTU length is set to 256 bytes. * 3. SRIO 8-bit and 16-bit base device IDs are set to supplied parameters. - * 4. Available destination SRIO 8-bit and 16-bit device IDs are set + * 4. Available destination SRIO 8-bit and 16-bit device IDs are set * according to supplied parameters. * 5. Operation mode is set according to supplied parameter. * 6. Link rate and ports configuration (4 ports are available) are set diff --git a/ports/c667x/ccs/example_build/include/C66XX_MACROS.hxx b/ports/c667x/ccs/example_build/include/C66XX_MACROS.hxx index 54e7ef57..32b1e4ff 100644 --- a/ports/c667x/ccs/example_build/include/C66XX_MACROS.hxx +++ b/ports/c667x/ccs/example_build/include/C66XX_MACROS.hxx @@ -40,7 +40,7 @@ typedef volatile uint32_t __C66XX_IO_DATA_TYPE__; -// read-back data bitmask for DSP memory-mapped registers (32-bit wide) +// read-back data bitmask for DSP memory-mapped registers (32-bit wide) #define C66XX_RG_DATA_BITMASK 0xffffffff //============================================================================= diff --git a/ports/c667x/ccs/example_build/include/TA66XX_DSP.h b/ports/c667x/ccs/example_build/include/TA66XX_DSP.h index 04dfc4b7..ba3fa341 100644 --- a/ports/c667x/ccs/example_build/include/TA66XX_DSP.h +++ b/ports/c667x/ccs/example_build/include/TA66XX_DSP.h @@ -11,7 +11,7 @@ Description: ------------ - This file contains general definitions and API functions for TORNADO AMC + This file contains general definitions and API functions for TORNADO AMC modules SDK and must be included in the user C-application for TORNADO AMC modules. diff --git a/ports/c667x/ccs/example_build/include/TA66XX_DSP_BC.h b/ports/c667x/ccs/example_build/include/TA66XX_DSP_BC.h index dbc748e0..028ce336 100644 --- a/ports/c667x/ccs/example_build/include/TA66XX_DSP_BC.h +++ b/ports/c667x/ccs/example_build/include/TA66XX_DSP_BC.h @@ -11,7 +11,7 @@ Description: ------------ - This file contains definitions, macros and API functions for TORNADO AMC + This file contains definitions, macros and API functions for TORNADO AMC modules on-board DSP environment and must be included in the user C-application for TORNADO AMC modules. diff --git a/ports/c667x/ccs/example_build/include/TA66XX_DSP_BC_FUNCTIONS.hxx b/ports/c667x/ccs/example_build/include/TA66XX_DSP_BC_FUNCTIONS.hxx index 338a01ee..fcec18ce 100644 --- a/ports/c667x/ccs/example_build/include/TA66XX_DSP_BC_FUNCTIONS.hxx +++ b/ports/c667x/ccs/example_build/include/TA66XX_DSP_BC_FUNCTIONS.hxx @@ -7,7 +7,7 @@ Notes: ------ - 1. This C-header file contains TORNADO AMC modules SDK functions + 1. This C-header file contains TORNADO AMC modules SDK functions for DSP environment declarations and is an include file for TI C6xxx C/C++ Code Generation Tools, which must be invoked to compile for TORNADO AMC platform. @@ -1008,7 +1008,7 @@ int32_t TA66XX_BC_get_hw_cfg_info(TA66XX_BC_HW_CFG_INFO_DATA_DD *info_dd); /*------------ TA66XX_BC_get_fmc_info() function -------------------------*//** - * @brief Function returns FMC module device info: installed status, device + * @brief Function returns FMC module device info: installed status, device * name, serial number, manufacturing date, firmware revisions, etc. * * @param[out] info_dd - pointer to a buffer that receives FMC info data @@ -1081,7 +1081,7 @@ int32_t TA66XX_BC_set_mmc_power_down_notification(void); * @brief Function returns identification info about installed SFP * transceiver: 256-byte array read from address 0x50 (identification info * according to SFF-8472) and 256-byte array read from address 0x51 (digital - * diagnostic monitoring interface (DDMI) data) + * diagnostic monitoring interface (DDMI) data) * * @param[out] id_data - pointer to a buffer that receives 256-byte array read * from address 0x50 (identification info according to SFF-8472). @@ -1356,7 +1356,7 @@ uint32_t TA66XX_BC_get_flash_length(void); /*------------ TA66XX_BC_get_flash_hw_wp_enable_status() function --------*//** - * @brief Function returns enable status of on-board FLASH memory hardware + * @brief Function returns enable status of on-board FLASH memory hardware * (via on-board switch) write-protection * * @return On-board FLASH memory hardware write-protection enable state: @@ -1367,7 +1367,7 @@ uint32_t TA66XX_BC_get_flash_hw_wp_enable_status(void); /*------------ TA66XX_BC_get_flash_sw_wp_enable_status() function --------*//** - * @brief Function returns enable status of on-board FLASH memory software + * @brief Function returns enable status of on-board FLASH memory software * write-protection * * @return On-board FLASH memory software write-protection enable state: @@ -1507,7 +1507,7 @@ uint32_t TA66XX_BC_get_mram_length(void); /*------------ TA66XX_BC_get_mram_sw_wp_enable_status() function ---------*//** - * @brief Function returns enable status of on-board MRAM memory software + * @brief Function returns enable status of on-board MRAM memory software * write-protection * * @return On-board MRAM memory software write-protection enable state: diff --git a/ports/c667x/ccs/example_build/include/TA66XX_OSAL.h b/ports/c667x/ccs/example_build/include/TA66XX_OSAL.h index d61af0e9..360e9f3b 100644 --- a/ports/c667x/ccs/example_build/include/TA66XX_OSAL.h +++ b/ports/c667x/ccs/example_build/include/TA66XX_OSAL.h @@ -412,7 +412,7 @@ void *Osal_srioDataBufferMalloc(uint32_t numBytes); /*------------ Osal_srioDataBufferFree() function ------------------------*//** - * @brief Function is used to clean up a previously allocated data buffer + * @brief Function is used to clean up a previously allocated data buffer * block. All data buffers are in the global address space. * * @param[in] ptr - pointer to the memory block to be cleaned up diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/sample_threadx.c b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/sample_threadx.c index 18bad8de..a97ce125 100644 --- a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/sample_threadx.c +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -121,7 +121,7 @@ UINT status; /* Create the main thread. */ status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); if (status != TX_SUCCESS) { @@ -135,11 +135,11 @@ UINT status; while (1); } - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); if (status != TX_SUCCESS) { @@ -154,7 +154,7 @@ UINT status; } status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); if (status != TX_SUCCESS) { @@ -168,10 +168,10 @@ UINT status; while (1); } - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ status = tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); if (status != TX_SUCCESS) { @@ -186,7 +186,7 @@ UINT status; } status = tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); if (status != TX_SUCCESS) { @@ -203,7 +203,7 @@ UINT status; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); if (status != TX_SUCCESS) { @@ -219,7 +219,7 @@ UINT status; /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ status = tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); if (status != TX_SUCCESS) { @@ -234,7 +234,7 @@ UINT status; } status = tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); if (status != TX_SUCCESS) { @@ -328,7 +328,7 @@ UINT status; /* Increment the thread counter. */ thread_0_counter++; - + /* Sleep for 10 ticks. */ tx_thread_sleep(10); @@ -384,11 +384,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -447,7 +447,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -500,7 +500,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/sample_threadx.cmd b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/sample_threadx.cmd index a2267231..590da9dc 100644 --- a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/sample_threadx.cmd +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/sample_threadx.cmd @@ -4,18 +4,18 @@ -l C:\ti\pdk_C6678_1_1_2_6\packages\ti\csl\lib\ti.csl.ae66 -l C:\ti\pdk_C6678_1_1_2_6\packages\ti\csl\lib\ti.csl.intc.ae66 -l c:\ti\pdk_C6678_1_1_2_6\packages\ti\platform\evmc6678l\platform_lib\lib\release\ti.platform.evm6678l.ae66 - + /* Memory Map */ MEMORY { L1PSRAM (RWX) : org = 0x00E00000, len = 0x00008000 - L1DSRAM (RWX) : org = 0x00F00000, len = 0x00008000 + L1DSRAM (RWX) : org = 0x00F00000, len = 0x00008000 CODE_RAM (RWX) : org = 0x00800000, len = 0x00020000 DATA_RAM (RWX) : org = 0x00820000, len = 0x00060000 MSMCSRAM (RWX) : org = 0x0c000000, len = 0x00400000 DDR3 (RWX) : org = 0x80000000, len = 0x80000000 } - + SECTIONS { .text > CODE_RAM @@ -30,7 +30,7 @@ SECTIONS .ppinfo > CODE_RAM .ppdata > CODE_RAM .csl_vect > CODE_RAM - platform_lib > CODE_RAM + platform_lib > CODE_RAM GROUP { @@ -42,7 +42,7 @@ SECTIONS /* COFF sections */ .pinit > CODE_RAM .cinit > CODE_RAM - + /* EABI sections */ .binit > CODE_RAM .init_array > CODE_RAM diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/targetConfigs/TMS320C6678.ccxml b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/targetConfigs/TMS320C6678.ccxml index b7147d7f..d10a283a 100644 --- a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/targetConfigs/TMS320C6678.ccxml +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/targetConfigs/TMS320C6678.ccxml @@ -1,6 +1,6 @@ - + diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/tx_initialize_low_level.asm b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/tx_initialize_low_level.asm index 686220c5..1339dbf5 100644 --- a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/tx_initialize_low_level.asm +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/tx_initialize_low_level.asm @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -82,7 +82,7 @@ INTMUX1_TMR8_VAL .set 0x43 ; Tie in Event 67 (TINT8H) t .global _tx_first_free_memory .align 16 _tx_first_free_memory: - .space 4 + .space 4 ; Useful macro definitions ; Load 32-bit integer into register @@ -111,42 +111,42 @@ TX_INTERRUPT_EXIT .macro .sect ".text" -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level C667x/TI */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level C667x/TI */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -219,7 +219,7 @@ _tx_int4_vector: STW A4,*+SP(36) ; Save A4 NOP -;_tx_timer_interrupt_preamble: +;_tx_timer_interrupt_preamble: MVK_LH TMR8_INTCTLSTAT_ADDR,A0 ; Build address of Timer Interrupt Control Register MVK_LH INTCTLSTAT_VAL,A1 ; Build value of Timer Interrupt Control Register @@ -234,7 +234,7 @@ _tx_int4_vector: B A0 ; Branch ThreadX timer ISR routine NOP 5 ; Delay slots NOP - + .global _tx_int5_vector diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/sample_threadx.c b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/sample_threadx.c index 18bad8de..a97ce125 100644 --- a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/sample_threadx.c +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -121,7 +121,7 @@ UINT status; /* Create the main thread. */ status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); if (status != TX_SUCCESS) { @@ -135,11 +135,11 @@ UINT status; while (1); } - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); if (status != TX_SUCCESS) { @@ -154,7 +154,7 @@ UINT status; } status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); if (status != TX_SUCCESS) { @@ -168,10 +168,10 @@ UINT status; while (1); } - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ status = tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); if (status != TX_SUCCESS) { @@ -186,7 +186,7 @@ UINT status; } status = tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); if (status != TX_SUCCESS) { @@ -203,7 +203,7 @@ UINT status; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); if (status != TX_SUCCESS) { @@ -219,7 +219,7 @@ UINT status; /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ status = tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); if (status != TX_SUCCESS) { @@ -234,7 +234,7 @@ UINT status; } status = tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); if (status != TX_SUCCESS) { @@ -328,7 +328,7 @@ UINT status; /* Increment the thread counter. */ thread_0_counter++; - + /* Sleep for 10 ticks. */ tx_thread_sleep(10); @@ -384,11 +384,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -447,7 +447,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -500,7 +500,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/sample_threadx.cmd b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/sample_threadx.cmd index b03e87b5..f84bffc6 100644 --- a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/sample_threadx.cmd +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/sample_threadx.cmd @@ -3,18 +3,18 @@ -stack 0x1000 -l C:\ti\pdk_C6678_1_1_2_6\packages\ti\csl\lib\ti.csl.ae66 -l C:\ti\pdk_C6678_1_1_2_6\packages\ti\csl\lib\ti.csl.intc.ae66 - + /* Memory Map */ MEMORY { L1PSRAM (RWX) : org = 0x00E00000, len = 0x00008000 - L1DSRAM (RWX) : org = 0x00F00000, len = 0x00008000 + L1DSRAM (RWX) : org = 0x00F00000, len = 0x00008000 CODE_RAM (RWX) : org = 0x00800000, len = 0x00020000 DATA_RAM (RWX) : org = 0x00820000, len = 0x00060000 MSMCSRAM (RWX) : org = 0x0c000000, len = 0x00400000 DDR3 (RWX) : org = 0x80000000, len = 0x80000000 } - + SECTIONS { .text > CODE_RAM @@ -40,7 +40,7 @@ SECTIONS /* COFF sections */ .pinit > CODE_RAM .cinit > CODE_RAM - + /* EABI sections */ .binit > CODE_RAM .init_array > CODE_RAM diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/targetConfigs/TMS320C6678.ccxml b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/targetConfigs/TMS320C6678.ccxml index b7147d7f..d10a283a 100644 --- a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/targetConfigs/TMS320C6678.ccxml +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/targetConfigs/TMS320C6678.ccxml @@ -1,6 +1,6 @@ - + diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/tx_initialize_low_level.asm b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/tx_initialize_low_level.asm index 14591f59..ca59cb5d 100644 --- a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/tx_initialize_low_level.asm +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/tx_initialize_low_level.asm @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -82,7 +82,7 @@ INTMUX1_TMR8_VAL .set 0x43 ; Tie in Event 67 (TINT8H) t .global _tx_first_free_memory .align 16 _tx_first_free_memory: - .space 4 + .space 4 ; Useful macro definitions ; Load 32-bit integer into register @@ -111,42 +111,42 @@ TX_INTERRUPT_EXIT .macro .sect ".text" -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level C667x+/TI */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level C667x+/TI */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -219,7 +219,7 @@ _tx_int4_vector: STW A4,*+SP(36) ; Save A4 NOP -;_tx_timer_interrupt_preamble: +;_tx_timer_interrupt_preamble: MVK_LH TMR8_INTCTLSTAT_ADDR,A0 ; Build address of Timer Interrupt Control Register MVK_LH INTCTLSTAT_VAL,A1 ; Build value of Timer Interrupt Control Register @@ -235,7 +235,7 @@ _tx_int4_vector: B A0 ; Branch ThreadX timer ISR routine NOP 5 ; Delay slots NOP - + .global _tx_int5_vector diff --git a/ports/c667x/ccs/example_build/tx/Release/ccsObjs.opt b/ports/c667x/ccs/example_build/tx/Release/ccsObjs.opt index e954d96e..98982c10 100644 --- a/ports/c667x/ccs/example_build/tx/Release/ccsObjs.opt +++ b/ports/c667x/ccs/example_build/tx/Release/ccsObjs.opt @@ -1 +1 @@ -"./tx_block_allocate.obj" "./tx_block_pool_cleanup.obj" "./tx_block_pool_create.obj" "./tx_block_pool_delete.obj" "./tx_block_pool_info_get.obj" "./tx_block_pool_initialize.obj" "./tx_block_pool_performance_info_get.obj" "./tx_block_pool_performance_system_info_get.obj" "./tx_block_pool_prioritize.obj" "./tx_block_release.obj" "./tx_byte_allocate.obj" "./tx_byte_pool_cleanup.obj" "./tx_byte_pool_create.obj" "./tx_byte_pool_delete.obj" "./tx_byte_pool_info_get.obj" "./tx_byte_pool_initialize.obj" "./tx_byte_pool_performance_info_get.obj" "./tx_byte_pool_performance_system_info_get.obj" "./tx_byte_pool_prioritize.obj" "./tx_byte_pool_search.obj" "./tx_byte_release.obj" "./tx_event_flags_cleanup.obj" "./tx_event_flags_create.obj" "./tx_event_flags_delete.obj" "./tx_event_flags_get.obj" "./tx_event_flags_info_get.obj" "./tx_event_flags_initialize.obj" "./tx_event_flags_performance_info_get.obj" "./tx_event_flags_performance_system_info_get.obj" "./tx_event_flags_set.obj" "./tx_event_flags_set_notify.obj" "./tx_initialize_high_level.obj" "./tx_initialize_kernel_enter.obj" "./tx_initialize_kernel_setup.obj" "./tx_mutex_cleanup.obj" "./tx_mutex_create.obj" "./tx_mutex_delete.obj" "./tx_mutex_get.obj" "./tx_mutex_info_get.obj" "./tx_mutex_initialize.obj" "./tx_mutex_performance_info_get.obj" "./tx_mutex_performance_system_info_get.obj" "./tx_mutex_prioritize.obj" "./tx_mutex_priority_change.obj" "./tx_mutex_put.obj" "./tx_queue_cleanup.obj" "./tx_queue_create.obj" "./tx_queue_delete.obj" "./tx_queue_flush.obj" "./tx_queue_front_send.obj" "./tx_queue_info_get.obj" "./tx_queue_initialize.obj" "./tx_queue_performance_info_get.obj" "./tx_queue_performance_system_info_get.obj" "./tx_queue_prioritize.obj" "./tx_queue_receive.obj" "./tx_queue_send.obj" "./tx_queue_send_notify.obj" "./tx_semaphore_ceiling_put.obj" "./tx_semaphore_cleanup.obj" "./tx_semaphore_create.obj" "./tx_semaphore_delete.obj" "./tx_semaphore_get.obj" "./tx_semaphore_info_get.obj" "./tx_semaphore_initialize.obj" "./tx_semaphore_performance_info_get.obj" "./tx_semaphore_performance_system_info_get.obj" "./tx_semaphore_prioritize.obj" "./tx_semaphore_put.obj" "./tx_semaphore_put_notify.obj" "./tx_thread_context_restore.obj" "./tx_thread_context_save.obj" "./tx_thread_create.obj" "./tx_thread_delete.obj" "./tx_thread_entry_exit_notify.obj" "./tx_thread_identify.obj" "./tx_thread_info_get.obj" "./tx_thread_initialize.obj" "./tx_thread_interrupt_control.obj" "./tx_thread_performance_info_get.obj" "./tx_thread_performance_system_info_get.obj" "./tx_thread_preemption_change.obj" "./tx_thread_priority_change.obj" "./tx_thread_relinquish.obj" "./tx_thread_reset.obj" "./tx_thread_resume.obj" "./tx_thread_schedule.obj" "./tx_thread_shell_entry.obj" "./tx_thread_sleep.obj" "./tx_thread_stack_analyze.obj" "./tx_thread_stack_build.obj" "./tx_thread_stack_error_handler.obj" "./tx_thread_stack_error_notify.obj" "./tx_thread_suspend.obj" "./tx_thread_system_preempt_check.obj" "./tx_thread_system_resume.obj" "./tx_thread_system_return.obj" "./tx_thread_system_suspend.obj" "./tx_thread_terminate.obj" "./tx_thread_time_slice.obj" "./tx_thread_time_slice_change.obj" "./tx_thread_timeout.obj" "./tx_thread_wait_abort.obj" "./tx_time_get.obj" "./tx_time_set.obj" "./tx_timer_activate.obj" "./tx_timer_change.obj" "./tx_timer_create.obj" "./tx_timer_deactivate.obj" "./tx_timer_delete.obj" "./tx_timer_expiration_process.obj" "./tx_timer_info_get.obj" "./tx_timer_initialize.obj" "./tx_timer_interrupt.obj" "./tx_timer_performance_info_get.obj" "./tx_timer_performance_system_info_get.obj" "./tx_timer_system_activate.obj" "./tx_timer_system_deactivate.obj" "./tx_timer_thread_entry.obj" "./tx_trace_buffer_full_notify.obj" "./tx_trace_disable.obj" "./tx_trace_enable.obj" "./tx_trace_event_filter.obj" "./tx_trace_event_unfilter.obj" "./tx_trace_initialize.obj" "./tx_trace_interrupt_control.obj" "./tx_trace_isr_enter_insert.obj" "./tx_trace_isr_exit_insert.obj" "./tx_trace_object_register.obj" "./tx_trace_object_unregister.obj" "./tx_trace_user_event_insert.obj" "./txe_block_allocate.obj" "./txe_block_pool_create.obj" "./txe_block_pool_delete.obj" "./txe_block_pool_info_get.obj" "./txe_block_pool_prioritize.obj" "./txe_block_release.obj" "./txe_byte_allocate.obj" "./txe_byte_pool_create.obj" "./txe_byte_pool_delete.obj" "./txe_byte_pool_info_get.obj" "./txe_byte_pool_prioritize.obj" "./txe_byte_release.obj" "./txe_event_flags_create.obj" "./txe_event_flags_delete.obj" "./txe_event_flags_get.obj" "./txe_event_flags_info_get.obj" "./txe_event_flags_set.obj" "./txe_event_flags_set_notify.obj" "./txe_mutex_create.obj" "./txe_mutex_delete.obj" "./txe_mutex_get.obj" "./txe_mutex_info_get.obj" "./txe_mutex_prioritize.obj" "./txe_mutex_put.obj" "./txe_queue_create.obj" "./txe_queue_delete.obj" "./txe_queue_flush.obj" "./txe_queue_front_send.obj" "./txe_queue_info_get.obj" "./txe_queue_prioritize.obj" "./txe_queue_receive.obj" "./txe_queue_send.obj" "./txe_queue_send_notify.obj" "./txe_semaphore_ceiling_put.obj" "./txe_semaphore_create.obj" "./txe_semaphore_delete.obj" "./txe_semaphore_get.obj" "./txe_semaphore_info_get.obj" "./txe_semaphore_prioritize.obj" "./txe_semaphore_put.obj" "./txe_semaphore_put_notify.obj" "./txe_thread_create.obj" "./txe_thread_delete.obj" "./txe_thread_entry_exit_notify.obj" "./txe_thread_info_get.obj" "./txe_thread_preemption_change.obj" "./txe_thread_priority_change.obj" "./txe_thread_relinquish.obj" "./txe_thread_reset.obj" "./txe_thread_resume.obj" "./txe_thread_suspend.obj" "./txe_thread_terminate.obj" "./txe_thread_time_slice_change.obj" "./txe_thread_wait_abort.obj" "./txe_timer_activate.obj" "./txe_timer_change.obj" "./txe_timer_create.obj" "./txe_timer_deactivate.obj" "./txe_timer_delete.obj" "./txe_timer_info_get.obj" \ No newline at end of file +"./tx_block_allocate.obj" "./tx_block_pool_cleanup.obj" "./tx_block_pool_create.obj" "./tx_block_pool_delete.obj" "./tx_block_pool_info_get.obj" "./tx_block_pool_initialize.obj" "./tx_block_pool_performance_info_get.obj" "./tx_block_pool_performance_system_info_get.obj" "./tx_block_pool_prioritize.obj" "./tx_block_release.obj" "./tx_byte_allocate.obj" "./tx_byte_pool_cleanup.obj" "./tx_byte_pool_create.obj" "./tx_byte_pool_delete.obj" "./tx_byte_pool_info_get.obj" "./tx_byte_pool_initialize.obj" "./tx_byte_pool_performance_info_get.obj" "./tx_byte_pool_performance_system_info_get.obj" "./tx_byte_pool_prioritize.obj" "./tx_byte_pool_search.obj" "./tx_byte_release.obj" "./tx_event_flags_cleanup.obj" "./tx_event_flags_create.obj" "./tx_event_flags_delete.obj" "./tx_event_flags_get.obj" "./tx_event_flags_info_get.obj" "./tx_event_flags_initialize.obj" "./tx_event_flags_performance_info_get.obj" "./tx_event_flags_performance_system_info_get.obj" "./tx_event_flags_set.obj" "./tx_event_flags_set_notify.obj" "./tx_initialize_high_level.obj" "./tx_initialize_kernel_enter.obj" "./tx_initialize_kernel_setup.obj" "./tx_mutex_cleanup.obj" "./tx_mutex_create.obj" "./tx_mutex_delete.obj" "./tx_mutex_get.obj" "./tx_mutex_info_get.obj" "./tx_mutex_initialize.obj" "./tx_mutex_performance_info_get.obj" "./tx_mutex_performance_system_info_get.obj" "./tx_mutex_prioritize.obj" "./tx_mutex_priority_change.obj" "./tx_mutex_put.obj" "./tx_queue_cleanup.obj" "./tx_queue_create.obj" "./tx_queue_delete.obj" "./tx_queue_flush.obj" "./tx_queue_front_send.obj" "./tx_queue_info_get.obj" "./tx_queue_initialize.obj" "./tx_queue_performance_info_get.obj" "./tx_queue_performance_system_info_get.obj" "./tx_queue_prioritize.obj" "./tx_queue_receive.obj" "./tx_queue_send.obj" "./tx_queue_send_notify.obj" "./tx_semaphore_ceiling_put.obj" "./tx_semaphore_cleanup.obj" "./tx_semaphore_create.obj" "./tx_semaphore_delete.obj" "./tx_semaphore_get.obj" "./tx_semaphore_info_get.obj" "./tx_semaphore_initialize.obj" "./tx_semaphore_performance_info_get.obj" "./tx_semaphore_performance_system_info_get.obj" "./tx_semaphore_prioritize.obj" "./tx_semaphore_put.obj" "./tx_semaphore_put_notify.obj" "./tx_thread_context_restore.obj" "./tx_thread_context_save.obj" "./tx_thread_create.obj" "./tx_thread_delete.obj" "./tx_thread_entry_exit_notify.obj" "./tx_thread_identify.obj" "./tx_thread_info_get.obj" "./tx_thread_initialize.obj" "./tx_thread_interrupt_control.obj" "./tx_thread_performance_info_get.obj" "./tx_thread_performance_system_info_get.obj" "./tx_thread_preemption_change.obj" "./tx_thread_priority_change.obj" "./tx_thread_relinquish.obj" "./tx_thread_reset.obj" "./tx_thread_resume.obj" "./tx_thread_schedule.obj" "./tx_thread_shell_entry.obj" "./tx_thread_sleep.obj" "./tx_thread_stack_analyze.obj" "./tx_thread_stack_build.obj" "./tx_thread_stack_error_handler.obj" "./tx_thread_stack_error_notify.obj" "./tx_thread_suspend.obj" "./tx_thread_system_preempt_check.obj" "./tx_thread_system_resume.obj" "./tx_thread_system_return.obj" "./tx_thread_system_suspend.obj" "./tx_thread_terminate.obj" "./tx_thread_time_slice.obj" "./tx_thread_time_slice_change.obj" "./tx_thread_timeout.obj" "./tx_thread_wait_abort.obj" "./tx_time_get.obj" "./tx_time_set.obj" "./tx_timer_activate.obj" "./tx_timer_change.obj" "./tx_timer_create.obj" "./tx_timer_deactivate.obj" "./tx_timer_delete.obj" "./tx_timer_expiration_process.obj" "./tx_timer_info_get.obj" "./tx_timer_initialize.obj" "./tx_timer_interrupt.obj" "./tx_timer_performance_info_get.obj" "./tx_timer_performance_system_info_get.obj" "./tx_timer_system_activate.obj" "./tx_timer_system_deactivate.obj" "./tx_timer_thread_entry.obj" "./tx_trace_buffer_full_notify.obj" "./tx_trace_disable.obj" "./tx_trace_enable.obj" "./tx_trace_event_filter.obj" "./tx_trace_event_unfilter.obj" "./tx_trace_initialize.obj" "./tx_trace_interrupt_control.obj" "./tx_trace_isr_enter_insert.obj" "./tx_trace_isr_exit_insert.obj" "./tx_trace_object_register.obj" "./tx_trace_object_unregister.obj" "./tx_trace_user_event_insert.obj" "./txe_block_allocate.obj" "./txe_block_pool_create.obj" "./txe_block_pool_delete.obj" "./txe_block_pool_info_get.obj" "./txe_block_pool_prioritize.obj" "./txe_block_release.obj" "./txe_byte_allocate.obj" "./txe_byte_pool_create.obj" "./txe_byte_pool_delete.obj" "./txe_byte_pool_info_get.obj" "./txe_byte_pool_prioritize.obj" "./txe_byte_release.obj" "./txe_event_flags_create.obj" "./txe_event_flags_delete.obj" "./txe_event_flags_get.obj" "./txe_event_flags_info_get.obj" "./txe_event_flags_set.obj" "./txe_event_flags_set_notify.obj" "./txe_mutex_create.obj" "./txe_mutex_delete.obj" "./txe_mutex_get.obj" "./txe_mutex_info_get.obj" "./txe_mutex_prioritize.obj" "./txe_mutex_put.obj" "./txe_queue_create.obj" "./txe_queue_delete.obj" "./txe_queue_flush.obj" "./txe_queue_front_send.obj" "./txe_queue_info_get.obj" "./txe_queue_prioritize.obj" "./txe_queue_receive.obj" "./txe_queue_send.obj" "./txe_queue_send_notify.obj" "./txe_semaphore_ceiling_put.obj" "./txe_semaphore_create.obj" "./txe_semaphore_delete.obj" "./txe_semaphore_get.obj" "./txe_semaphore_info_get.obj" "./txe_semaphore_prioritize.obj" "./txe_semaphore_put.obj" "./txe_semaphore_put_notify.obj" "./txe_thread_create.obj" "./txe_thread_delete.obj" "./txe_thread_entry_exit_notify.obj" "./txe_thread_info_get.obj" "./txe_thread_preemption_change.obj" "./txe_thread_priority_change.obj" "./txe_thread_relinquish.obj" "./txe_thread_reset.obj" "./txe_thread_resume.obj" "./txe_thread_suspend.obj" "./txe_thread_terminate.obj" "./txe_thread_time_slice_change.obj" "./txe_thread_wait_abort.obj" "./txe_timer_activate.obj" "./txe_timer_change.obj" "./txe_timer_create.obj" "./txe_timer_deactivate.obj" "./txe_timer_delete.obj" "./txe_timer_info_get.obj" \ No newline at end of file diff --git a/ports/c667x/ccs/example_build/tx/Release/makefile b/ports/c667x/ccs/example_build/tx/Release/makefile index 45d27b35..10d8815d 100644 --- a/ports/c667x/ccs/example_build/tx/Release/makefile +++ b/ports/c667x/ccs/example_build/tx/Release/makefile @@ -6,8 +6,8 @@ SHELL = cmd.exe CG_TOOL_ROOT := C:/ti/ccsv8/tools/compiler/ti-cgt-c6000_8.2.4 -GEN_OPTS__FLAG := -GEN_CMDS__FLAG := +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := ORDERED_OBJS += \ "./tx_block_allocate.obj" \ @@ -305,7 +305,7 @@ endif -include ../makefile.defs -# Add inputs and outputs from these tool invocations to the build variables +# Add inputs and outputs from these tool invocations to the build variables LIB_OUTPUTS += \ tx.lib \ @@ -329,18 +329,18 @@ endif # Other Targets clean: -$(RM) $(LIB_OUTPUTS__QUOTED) - -$(RM) "tx_block_allocate.obj" "tx_block_pool_cleanup.obj" "tx_block_pool_create.obj" "tx_block_pool_delete.obj" "tx_block_pool_info_get.obj" "tx_block_pool_initialize.obj" "tx_block_pool_performance_info_get.obj" "tx_block_pool_performance_system_info_get.obj" "tx_block_pool_prioritize.obj" "tx_block_release.obj" "tx_byte_allocate.obj" "tx_byte_pool_cleanup.obj" "tx_byte_pool_create.obj" "tx_byte_pool_delete.obj" "tx_byte_pool_info_get.obj" "tx_byte_pool_initialize.obj" "tx_byte_pool_performance_info_get.obj" "tx_byte_pool_performance_system_info_get.obj" "tx_byte_pool_prioritize.obj" "tx_byte_pool_search.obj" "tx_byte_release.obj" "tx_event_flags_cleanup.obj" "tx_event_flags_create.obj" "tx_event_flags_delete.obj" "tx_event_flags_get.obj" "tx_event_flags_info_get.obj" "tx_event_flags_initialize.obj" "tx_event_flags_performance_info_get.obj" "tx_event_flags_performance_system_info_get.obj" "tx_event_flags_set.obj" "tx_event_flags_set_notify.obj" "tx_initialize_high_level.obj" "tx_initialize_kernel_enter.obj" - -$(RM) "tx_initialize_kernel_setup.obj" "tx_mutex_cleanup.obj" "tx_mutex_create.obj" "tx_mutex_delete.obj" "tx_mutex_get.obj" "tx_mutex_info_get.obj" "tx_mutex_initialize.obj" "tx_mutex_performance_info_get.obj" "tx_mutex_performance_system_info_get.obj" "tx_mutex_prioritize.obj" "tx_mutex_priority_change.obj" "tx_mutex_put.obj" "tx_queue_cleanup.obj" "tx_queue_create.obj" "tx_queue_delete.obj" "tx_queue_flush.obj" "tx_queue_front_send.obj" "tx_queue_info_get.obj" "tx_queue_initialize.obj" "tx_queue_performance_info_get.obj" "tx_queue_performance_system_info_get.obj" "tx_queue_prioritize.obj" "tx_queue_receive.obj" "tx_queue_send.obj" "tx_queue_send_notify.obj" "tx_semaphore_ceiling_put.obj" "tx_semaphore_cleanup.obj" "tx_semaphore_create.obj" "tx_semaphore_delete.obj" "tx_semaphore_get.obj" "tx_semaphore_info_get.obj" "tx_semaphore_initialize.obj" "tx_semaphore_performance_info_get.obj" "tx_semaphore_performance_system_info_get.obj" "tx_semaphore_prioritize.obj" "tx_semaphore_put.obj" "tx_semaphore_put_notify.obj" - -$(RM) "tx_thread_context_restore.obj" "tx_thread_context_save.obj" "tx_thread_create.obj" "tx_thread_delete.obj" "tx_thread_entry_exit_notify.obj" "tx_thread_identify.obj" "tx_thread_info_get.obj" "tx_thread_initialize.obj" "tx_thread_interrupt_control.obj" "tx_thread_performance_info_get.obj" "tx_thread_performance_system_info_get.obj" "tx_thread_preemption_change.obj" "tx_thread_priority_change.obj" "tx_thread_relinquish.obj" "tx_thread_reset.obj" "tx_thread_resume.obj" "tx_thread_schedule.obj" "tx_thread_shell_entry.obj" "tx_thread_sleep.obj" "tx_thread_stack_analyze.obj" "tx_thread_stack_build.obj" "tx_thread_stack_error_handler.obj" "tx_thread_stack_error_notify.obj" "tx_thread_suspend.obj" "tx_thread_system_preempt_check.obj" "tx_thread_system_resume.obj" "tx_thread_system_return.obj" "tx_thread_system_suspend.obj" "tx_thread_terminate.obj" "tx_thread_time_slice.obj" "tx_thread_time_slice_change.obj" "tx_thread_timeout.obj" "tx_thread_wait_abort.obj" "tx_time_get.obj" "tx_time_set.obj" - -$(RM) "tx_timer_activate.obj" "tx_timer_change.obj" "tx_timer_create.obj" "tx_timer_deactivate.obj" "tx_timer_delete.obj" "tx_timer_expiration_process.obj" "tx_timer_info_get.obj" "tx_timer_initialize.obj" "tx_timer_interrupt.obj" "tx_timer_performance_info_get.obj" "tx_timer_performance_system_info_get.obj" "tx_timer_system_activate.obj" "tx_timer_system_deactivate.obj" "tx_timer_thread_entry.obj" "tx_trace_buffer_full_notify.obj" "tx_trace_disable.obj" "tx_trace_enable.obj" "tx_trace_event_filter.obj" "tx_trace_event_unfilter.obj" "tx_trace_initialize.obj" "tx_trace_interrupt_control.obj" "tx_trace_isr_enter_insert.obj" "tx_trace_isr_exit_insert.obj" "tx_trace_object_register.obj" "tx_trace_object_unregister.obj" "tx_trace_user_event_insert.obj" "txe_block_allocate.obj" "txe_block_pool_create.obj" "txe_block_pool_delete.obj" "txe_block_pool_info_get.obj" "txe_block_pool_prioritize.obj" "txe_block_release.obj" "txe_byte_allocate.obj" "txe_byte_pool_create.obj" "txe_byte_pool_delete.obj" "txe_byte_pool_info_get.obj" - -$(RM) "txe_byte_pool_prioritize.obj" "txe_byte_release.obj" "txe_event_flags_create.obj" "txe_event_flags_delete.obj" "txe_event_flags_get.obj" "txe_event_flags_info_get.obj" "txe_event_flags_set.obj" "txe_event_flags_set_notify.obj" "txe_mutex_create.obj" "txe_mutex_delete.obj" "txe_mutex_get.obj" "txe_mutex_info_get.obj" "txe_mutex_prioritize.obj" "txe_mutex_put.obj" "txe_queue_create.obj" "txe_queue_delete.obj" "txe_queue_flush.obj" "txe_queue_front_send.obj" "txe_queue_info_get.obj" "txe_queue_prioritize.obj" "txe_queue_receive.obj" "txe_queue_send.obj" "txe_queue_send_notify.obj" "txe_semaphore_ceiling_put.obj" "txe_semaphore_create.obj" "txe_semaphore_delete.obj" "txe_semaphore_get.obj" "txe_semaphore_info_get.obj" "txe_semaphore_prioritize.obj" "txe_semaphore_put.obj" "txe_semaphore_put_notify.obj" "txe_thread_create.obj" "txe_thread_delete.obj" "txe_thread_entry_exit_notify.obj" "txe_thread_info_get.obj" "txe_thread_preemption_change.obj" "txe_thread_priority_change.obj" "txe_thread_relinquish.obj" - -$(RM) "txe_thread_reset.obj" "txe_thread_resume.obj" "txe_thread_suspend.obj" "txe_thread_terminate.obj" "txe_thread_time_slice_change.obj" "txe_thread_wait_abort.obj" "txe_timer_activate.obj" "txe_timer_change.obj" "txe_timer_create.obj" "txe_timer_deactivate.obj" "txe_timer_delete.obj" "txe_timer_info_get.obj" - -$(RM) "tx_block_allocate.d" "tx_block_pool_cleanup.d" "tx_block_pool_create.d" "tx_block_pool_delete.d" "tx_block_pool_info_get.d" "tx_block_pool_initialize.d" "tx_block_pool_performance_info_get.d" "tx_block_pool_performance_system_info_get.d" "tx_block_pool_prioritize.d" "tx_block_release.d" "tx_byte_allocate.d" "tx_byte_pool_cleanup.d" "tx_byte_pool_create.d" "tx_byte_pool_delete.d" "tx_byte_pool_info_get.d" "tx_byte_pool_initialize.d" "tx_byte_pool_performance_info_get.d" "tx_byte_pool_performance_system_info_get.d" "tx_byte_pool_prioritize.d" "tx_byte_pool_search.d" "tx_byte_release.d" "tx_event_flags_cleanup.d" "tx_event_flags_create.d" "tx_event_flags_delete.d" "tx_event_flags_get.d" "tx_event_flags_info_get.d" "tx_event_flags_initialize.d" "tx_event_flags_performance_info_get.d" "tx_event_flags_performance_system_info_get.d" "tx_event_flags_set.d" "tx_event_flags_set_notify.d" "tx_initialize_high_level.d" "tx_initialize_kernel_enter.d" "tx_initialize_kernel_setup.d" "tx_mutex_cleanup.d" - -$(RM) "tx_mutex_create.d" "tx_mutex_delete.d" "tx_mutex_get.d" "tx_mutex_info_get.d" "tx_mutex_initialize.d" "tx_mutex_performance_info_get.d" "tx_mutex_performance_system_info_get.d" "tx_mutex_prioritize.d" "tx_mutex_priority_change.d" "tx_mutex_put.d" "tx_queue_cleanup.d" "tx_queue_create.d" "tx_queue_delete.d" "tx_queue_flush.d" "tx_queue_front_send.d" "tx_queue_info_get.d" "tx_queue_initialize.d" "tx_queue_performance_info_get.d" "tx_queue_performance_system_info_get.d" "tx_queue_prioritize.d" "tx_queue_receive.d" "tx_queue_send.d" "tx_queue_send_notify.d" "tx_semaphore_ceiling_put.d" "tx_semaphore_cleanup.d" "tx_semaphore_create.d" "tx_semaphore_delete.d" "tx_semaphore_get.d" "tx_semaphore_info_get.d" "tx_semaphore_initialize.d" "tx_semaphore_performance_info_get.d" "tx_semaphore_performance_system_info_get.d" "tx_semaphore_prioritize.d" "tx_semaphore_put.d" "tx_semaphore_put_notify.d" "tx_thread_create.d" "tx_thread_delete.d" "tx_thread_entry_exit_notify.d" "tx_thread_identify.d" "tx_thread_info_get.d" - -$(RM) "tx_thread_initialize.d" "tx_thread_performance_info_get.d" "tx_thread_performance_system_info_get.d" "tx_thread_preemption_change.d" "tx_thread_priority_change.d" "tx_thread_relinquish.d" "tx_thread_reset.d" "tx_thread_resume.d" "tx_thread_shell_entry.d" "tx_thread_sleep.d" "tx_thread_stack_analyze.d" "tx_thread_stack_error_handler.d" "tx_thread_stack_error_notify.d" "tx_thread_suspend.d" "tx_thread_system_preempt_check.d" "tx_thread_system_resume.d" "tx_thread_system_suspend.d" "tx_thread_terminate.d" "tx_thread_time_slice.d" "tx_thread_time_slice_change.d" "tx_thread_timeout.d" "tx_thread_wait_abort.d" "tx_time_get.d" "tx_time_set.d" "tx_timer_activate.d" "tx_timer_change.d" "tx_timer_create.d" "tx_timer_deactivate.d" "tx_timer_delete.d" "tx_timer_expiration_process.d" "tx_timer_info_get.d" "tx_timer_initialize.d" "tx_timer_performance_info_get.d" "tx_timer_performance_system_info_get.d" "tx_timer_system_activate.d" "tx_timer_system_deactivate.d" "tx_timer_thread_entry.d" "tx_trace_buffer_full_notify.d" - -$(RM) "tx_trace_disable.d" "tx_trace_enable.d" "tx_trace_event_filter.d" "tx_trace_event_unfilter.d" "tx_trace_initialize.d" "tx_trace_interrupt_control.d" "tx_trace_isr_enter_insert.d" "tx_trace_isr_exit_insert.d" "tx_trace_object_register.d" "tx_trace_object_unregister.d" "tx_trace_user_event_insert.d" "txe_block_allocate.d" "txe_block_pool_create.d" "txe_block_pool_delete.d" "txe_block_pool_info_get.d" "txe_block_pool_prioritize.d" "txe_block_release.d" "txe_byte_allocate.d" "txe_byte_pool_create.d" "txe_byte_pool_delete.d" "txe_byte_pool_info_get.d" "txe_byte_pool_prioritize.d" "txe_byte_release.d" "txe_event_flags_create.d" "txe_event_flags_delete.d" "txe_event_flags_get.d" "txe_event_flags_info_get.d" "txe_event_flags_set.d" "txe_event_flags_set_notify.d" "txe_mutex_create.d" "txe_mutex_delete.d" "txe_mutex_get.d" "txe_mutex_info_get.d" "txe_mutex_prioritize.d" "txe_mutex_put.d" "txe_queue_create.d" "txe_queue_delete.d" "txe_queue_flush.d" "txe_queue_front_send.d" "txe_queue_info_get.d" - -$(RM) "txe_queue_prioritize.d" "txe_queue_receive.d" "txe_queue_send.d" "txe_queue_send_notify.d" "txe_semaphore_ceiling_put.d" "txe_semaphore_create.d" "txe_semaphore_delete.d" "txe_semaphore_get.d" "txe_semaphore_info_get.d" "txe_semaphore_prioritize.d" "txe_semaphore_put.d" "txe_semaphore_put_notify.d" "txe_thread_create.d" "txe_thread_delete.d" "txe_thread_entry_exit_notify.d" "txe_thread_info_get.d" "txe_thread_preemption_change.d" "txe_thread_priority_change.d" "txe_thread_relinquish.d" "txe_thread_reset.d" "txe_thread_resume.d" "txe_thread_suspend.d" "txe_thread_terminate.d" "txe_thread_time_slice_change.d" "txe_thread_wait_abort.d" "txe_timer_activate.d" "txe_timer_change.d" "txe_timer_create.d" "txe_timer_deactivate.d" "txe_timer_delete.d" "txe_timer_info_get.d" - -$(RM) "tx_thread_context_restore.d" "tx_thread_context_save.d" "tx_thread_interrupt_control.d" "tx_thread_schedule.d" "tx_thread_stack_build.d" "tx_thread_system_return.d" "tx_timer_interrupt.d" + -$(RM) "tx_block_allocate.obj" "tx_block_pool_cleanup.obj" "tx_block_pool_create.obj" "tx_block_pool_delete.obj" "tx_block_pool_info_get.obj" "tx_block_pool_initialize.obj" "tx_block_pool_performance_info_get.obj" "tx_block_pool_performance_system_info_get.obj" "tx_block_pool_prioritize.obj" "tx_block_release.obj" "tx_byte_allocate.obj" "tx_byte_pool_cleanup.obj" "tx_byte_pool_create.obj" "tx_byte_pool_delete.obj" "tx_byte_pool_info_get.obj" "tx_byte_pool_initialize.obj" "tx_byte_pool_performance_info_get.obj" "tx_byte_pool_performance_system_info_get.obj" "tx_byte_pool_prioritize.obj" "tx_byte_pool_search.obj" "tx_byte_release.obj" "tx_event_flags_cleanup.obj" "tx_event_flags_create.obj" "tx_event_flags_delete.obj" "tx_event_flags_get.obj" "tx_event_flags_info_get.obj" "tx_event_flags_initialize.obj" "tx_event_flags_performance_info_get.obj" "tx_event_flags_performance_system_info_get.obj" "tx_event_flags_set.obj" "tx_event_flags_set_notify.obj" "tx_initialize_high_level.obj" "tx_initialize_kernel_enter.obj" + -$(RM) "tx_initialize_kernel_setup.obj" "tx_mutex_cleanup.obj" "tx_mutex_create.obj" "tx_mutex_delete.obj" "tx_mutex_get.obj" "tx_mutex_info_get.obj" "tx_mutex_initialize.obj" "tx_mutex_performance_info_get.obj" "tx_mutex_performance_system_info_get.obj" "tx_mutex_prioritize.obj" "tx_mutex_priority_change.obj" "tx_mutex_put.obj" "tx_queue_cleanup.obj" "tx_queue_create.obj" "tx_queue_delete.obj" "tx_queue_flush.obj" "tx_queue_front_send.obj" "tx_queue_info_get.obj" "tx_queue_initialize.obj" "tx_queue_performance_info_get.obj" "tx_queue_performance_system_info_get.obj" "tx_queue_prioritize.obj" "tx_queue_receive.obj" "tx_queue_send.obj" "tx_queue_send_notify.obj" "tx_semaphore_ceiling_put.obj" "tx_semaphore_cleanup.obj" "tx_semaphore_create.obj" "tx_semaphore_delete.obj" "tx_semaphore_get.obj" "tx_semaphore_info_get.obj" "tx_semaphore_initialize.obj" "tx_semaphore_performance_info_get.obj" "tx_semaphore_performance_system_info_get.obj" "tx_semaphore_prioritize.obj" "tx_semaphore_put.obj" "tx_semaphore_put_notify.obj" + -$(RM) "tx_thread_context_restore.obj" "tx_thread_context_save.obj" "tx_thread_create.obj" "tx_thread_delete.obj" "tx_thread_entry_exit_notify.obj" "tx_thread_identify.obj" "tx_thread_info_get.obj" "tx_thread_initialize.obj" "tx_thread_interrupt_control.obj" "tx_thread_performance_info_get.obj" "tx_thread_performance_system_info_get.obj" "tx_thread_preemption_change.obj" "tx_thread_priority_change.obj" "tx_thread_relinquish.obj" "tx_thread_reset.obj" "tx_thread_resume.obj" "tx_thread_schedule.obj" "tx_thread_shell_entry.obj" "tx_thread_sleep.obj" "tx_thread_stack_analyze.obj" "tx_thread_stack_build.obj" "tx_thread_stack_error_handler.obj" "tx_thread_stack_error_notify.obj" "tx_thread_suspend.obj" "tx_thread_system_preempt_check.obj" "tx_thread_system_resume.obj" "tx_thread_system_return.obj" "tx_thread_system_suspend.obj" "tx_thread_terminate.obj" "tx_thread_time_slice.obj" "tx_thread_time_slice_change.obj" "tx_thread_timeout.obj" "tx_thread_wait_abort.obj" "tx_time_get.obj" "tx_time_set.obj" + -$(RM) "tx_timer_activate.obj" "tx_timer_change.obj" "tx_timer_create.obj" "tx_timer_deactivate.obj" "tx_timer_delete.obj" "tx_timer_expiration_process.obj" "tx_timer_info_get.obj" "tx_timer_initialize.obj" "tx_timer_interrupt.obj" "tx_timer_performance_info_get.obj" "tx_timer_performance_system_info_get.obj" "tx_timer_system_activate.obj" "tx_timer_system_deactivate.obj" "tx_timer_thread_entry.obj" "tx_trace_buffer_full_notify.obj" "tx_trace_disable.obj" "tx_trace_enable.obj" "tx_trace_event_filter.obj" "tx_trace_event_unfilter.obj" "tx_trace_initialize.obj" "tx_trace_interrupt_control.obj" "tx_trace_isr_enter_insert.obj" "tx_trace_isr_exit_insert.obj" "tx_trace_object_register.obj" "tx_trace_object_unregister.obj" "tx_trace_user_event_insert.obj" "txe_block_allocate.obj" "txe_block_pool_create.obj" "txe_block_pool_delete.obj" "txe_block_pool_info_get.obj" "txe_block_pool_prioritize.obj" "txe_block_release.obj" "txe_byte_allocate.obj" "txe_byte_pool_create.obj" "txe_byte_pool_delete.obj" "txe_byte_pool_info_get.obj" + -$(RM) "txe_byte_pool_prioritize.obj" "txe_byte_release.obj" "txe_event_flags_create.obj" "txe_event_flags_delete.obj" "txe_event_flags_get.obj" "txe_event_flags_info_get.obj" "txe_event_flags_set.obj" "txe_event_flags_set_notify.obj" "txe_mutex_create.obj" "txe_mutex_delete.obj" "txe_mutex_get.obj" "txe_mutex_info_get.obj" "txe_mutex_prioritize.obj" "txe_mutex_put.obj" "txe_queue_create.obj" "txe_queue_delete.obj" "txe_queue_flush.obj" "txe_queue_front_send.obj" "txe_queue_info_get.obj" "txe_queue_prioritize.obj" "txe_queue_receive.obj" "txe_queue_send.obj" "txe_queue_send_notify.obj" "txe_semaphore_ceiling_put.obj" "txe_semaphore_create.obj" "txe_semaphore_delete.obj" "txe_semaphore_get.obj" "txe_semaphore_info_get.obj" "txe_semaphore_prioritize.obj" "txe_semaphore_put.obj" "txe_semaphore_put_notify.obj" "txe_thread_create.obj" "txe_thread_delete.obj" "txe_thread_entry_exit_notify.obj" "txe_thread_info_get.obj" "txe_thread_preemption_change.obj" "txe_thread_priority_change.obj" "txe_thread_relinquish.obj" + -$(RM) "txe_thread_reset.obj" "txe_thread_resume.obj" "txe_thread_suspend.obj" "txe_thread_terminate.obj" "txe_thread_time_slice_change.obj" "txe_thread_wait_abort.obj" "txe_timer_activate.obj" "txe_timer_change.obj" "txe_timer_create.obj" "txe_timer_deactivate.obj" "txe_timer_delete.obj" "txe_timer_info_get.obj" + -$(RM) "tx_block_allocate.d" "tx_block_pool_cleanup.d" "tx_block_pool_create.d" "tx_block_pool_delete.d" "tx_block_pool_info_get.d" "tx_block_pool_initialize.d" "tx_block_pool_performance_info_get.d" "tx_block_pool_performance_system_info_get.d" "tx_block_pool_prioritize.d" "tx_block_release.d" "tx_byte_allocate.d" "tx_byte_pool_cleanup.d" "tx_byte_pool_create.d" "tx_byte_pool_delete.d" "tx_byte_pool_info_get.d" "tx_byte_pool_initialize.d" "tx_byte_pool_performance_info_get.d" "tx_byte_pool_performance_system_info_get.d" "tx_byte_pool_prioritize.d" "tx_byte_pool_search.d" "tx_byte_release.d" "tx_event_flags_cleanup.d" "tx_event_flags_create.d" "tx_event_flags_delete.d" "tx_event_flags_get.d" "tx_event_flags_info_get.d" "tx_event_flags_initialize.d" "tx_event_flags_performance_info_get.d" "tx_event_flags_performance_system_info_get.d" "tx_event_flags_set.d" "tx_event_flags_set_notify.d" "tx_initialize_high_level.d" "tx_initialize_kernel_enter.d" "tx_initialize_kernel_setup.d" "tx_mutex_cleanup.d" + -$(RM) "tx_mutex_create.d" "tx_mutex_delete.d" "tx_mutex_get.d" "tx_mutex_info_get.d" "tx_mutex_initialize.d" "tx_mutex_performance_info_get.d" "tx_mutex_performance_system_info_get.d" "tx_mutex_prioritize.d" "tx_mutex_priority_change.d" "tx_mutex_put.d" "tx_queue_cleanup.d" "tx_queue_create.d" "tx_queue_delete.d" "tx_queue_flush.d" "tx_queue_front_send.d" "tx_queue_info_get.d" "tx_queue_initialize.d" "tx_queue_performance_info_get.d" "tx_queue_performance_system_info_get.d" "tx_queue_prioritize.d" "tx_queue_receive.d" "tx_queue_send.d" "tx_queue_send_notify.d" "tx_semaphore_ceiling_put.d" "tx_semaphore_cleanup.d" "tx_semaphore_create.d" "tx_semaphore_delete.d" "tx_semaphore_get.d" "tx_semaphore_info_get.d" "tx_semaphore_initialize.d" "tx_semaphore_performance_info_get.d" "tx_semaphore_performance_system_info_get.d" "tx_semaphore_prioritize.d" "tx_semaphore_put.d" "tx_semaphore_put_notify.d" "tx_thread_create.d" "tx_thread_delete.d" "tx_thread_entry_exit_notify.d" "tx_thread_identify.d" "tx_thread_info_get.d" + -$(RM) "tx_thread_initialize.d" "tx_thread_performance_info_get.d" "tx_thread_performance_system_info_get.d" "tx_thread_preemption_change.d" "tx_thread_priority_change.d" "tx_thread_relinquish.d" "tx_thread_reset.d" "tx_thread_resume.d" "tx_thread_shell_entry.d" "tx_thread_sleep.d" "tx_thread_stack_analyze.d" "tx_thread_stack_error_handler.d" "tx_thread_stack_error_notify.d" "tx_thread_suspend.d" "tx_thread_system_preempt_check.d" "tx_thread_system_resume.d" "tx_thread_system_suspend.d" "tx_thread_terminate.d" "tx_thread_time_slice.d" "tx_thread_time_slice_change.d" "tx_thread_timeout.d" "tx_thread_wait_abort.d" "tx_time_get.d" "tx_time_set.d" "tx_timer_activate.d" "tx_timer_change.d" "tx_timer_create.d" "tx_timer_deactivate.d" "tx_timer_delete.d" "tx_timer_expiration_process.d" "tx_timer_info_get.d" "tx_timer_initialize.d" "tx_timer_performance_info_get.d" "tx_timer_performance_system_info_get.d" "tx_timer_system_activate.d" "tx_timer_system_deactivate.d" "tx_timer_thread_entry.d" "tx_trace_buffer_full_notify.d" + -$(RM) "tx_trace_disable.d" "tx_trace_enable.d" "tx_trace_event_filter.d" "tx_trace_event_unfilter.d" "tx_trace_initialize.d" "tx_trace_interrupt_control.d" "tx_trace_isr_enter_insert.d" "tx_trace_isr_exit_insert.d" "tx_trace_object_register.d" "tx_trace_object_unregister.d" "tx_trace_user_event_insert.d" "txe_block_allocate.d" "txe_block_pool_create.d" "txe_block_pool_delete.d" "txe_block_pool_info_get.d" "txe_block_pool_prioritize.d" "txe_block_release.d" "txe_byte_allocate.d" "txe_byte_pool_create.d" "txe_byte_pool_delete.d" "txe_byte_pool_info_get.d" "txe_byte_pool_prioritize.d" "txe_byte_release.d" "txe_event_flags_create.d" "txe_event_flags_delete.d" "txe_event_flags_get.d" "txe_event_flags_info_get.d" "txe_event_flags_set.d" "txe_event_flags_set_notify.d" "txe_mutex_create.d" "txe_mutex_delete.d" "txe_mutex_get.d" "txe_mutex_info_get.d" "txe_mutex_prioritize.d" "txe_mutex_put.d" "txe_queue_create.d" "txe_queue_delete.d" "txe_queue_flush.d" "txe_queue_front_send.d" "txe_queue_info_get.d" + -$(RM) "txe_queue_prioritize.d" "txe_queue_receive.d" "txe_queue_send.d" "txe_queue_send_notify.d" "txe_semaphore_ceiling_put.d" "txe_semaphore_create.d" "txe_semaphore_delete.d" "txe_semaphore_get.d" "txe_semaphore_info_get.d" "txe_semaphore_prioritize.d" "txe_semaphore_put.d" "txe_semaphore_put_notify.d" "txe_thread_create.d" "txe_thread_delete.d" "txe_thread_entry_exit_notify.d" "txe_thread_info_get.d" "txe_thread_preemption_change.d" "txe_thread_priority_change.d" "txe_thread_relinquish.d" "txe_thread_reset.d" "txe_thread_resume.d" "txe_thread_suspend.d" "txe_thread_terminate.d" "txe_thread_time_slice_change.d" "txe_thread_wait_abort.d" "txe_timer_activate.d" "txe_timer_change.d" "txe_timer_create.d" "txe_timer_deactivate.d" "txe_timer_delete.d" "txe_timer_info_get.d" + -$(RM) "tx_thread_context_restore.d" "tx_thread_context_save.d" "tx_thread_interrupt_control.d" "tx_thread_schedule.d" "tx_thread_stack_build.d" "tx_thread_system_return.d" "tx_timer_interrupt.d" -@echo 'Finished clean' -@echo ' ' diff --git a/ports/c667x/ccs/example_build/tx/Release/sources.mk b/ports/c667x/ccs/example_build/tx/Release/sources.mk index 9cbc2a26..95c7e8c3 100644 --- a/ports/c667x/ccs/example_build/tx/Release/sources.mk +++ b/ports/c667x/ccs/example_build/tx/Release/sources.mk @@ -2,107 +2,107 @@ # Automatically-generated file. Do not edit! ################################################################################ -C55_SRCS := -A_SRCS := -ASM_UPPER_SRCS := -LDS_UPPER_SRCS := -CPP_SRCS := -CMD_SRCS := -O_SRCS := -C??_SRCS := -C64_SRCS := -C67_SRCS := -SA_SRCS := -S64_SRCS := -OPT_SRCS := -CXX_SRCS := -S67_SRCS := -S??_SRCS := -PDE_SRCS := -SV7A_SRCS := -K_SRCS := -CLA_SRCS := -S55_SRCS := -LD_UPPER_SRCS := -INO_SRCS := -LIB_SRCS := -ASM_SRCS := -S_UPPER_SRCS := -S43_SRCS := -LD_SRCS := -CMD_UPPER_SRCS := -C_UPPER_SRCS := -C++_SRCS := -C43_SRCS := -OBJ_SRCS := -LDS_SRCS := -S_SRCS := -CC_SRCS := -S62_SRCS := -C62_SRCS := -C_SRCS := -C55_DEPS := -C_UPPER_DEPS := -S67_DEPS := -S62_DEPS := -S_DEPS := -OPT_DEPS := -C??_DEPS := -ASM_UPPER_DEPS := -S??_DEPS := -C64_DEPS := -CXX_DEPS := -S64_DEPS := -INO_DEPS := -CLA_DEPS := -S55_DEPS := -SV7A_DEPS := -C62_DEPS := -C67_DEPS := -PDE_DEPS := -K_DEPS := -C_DEPS := -LIB_OUTPUTS := -CC_DEPS := -C++_DEPS := -C43_DEPS := -S43_DEPS := -OBJS := -ASM_DEPS := -S_UPPER_DEPS := -CPP_DEPS := -SA_DEPS := -C++_DEPS__QUOTED := -OPT_DEPS__QUOTED := -S_UPPER_DEPS__QUOTED := -SA_DEPS__QUOTED := -C??_DEPS__QUOTED := -S67_DEPS__QUOTED := -C55_DEPS__QUOTED := -CC_DEPS__QUOTED := -ASM_UPPER_DEPS__QUOTED := -SV7A_DEPS__QUOTED := -S??_DEPS__QUOTED := -OBJS__QUOTED := -C67_DEPS__QUOTED := -LIB_OUTPUTS__QUOTED := -K_DEPS__QUOTED := -S55_DEPS__QUOTED := -INO_DEPS__QUOTED := -C62_DEPS__QUOTED := -C_DEPS__QUOTED := -C_UPPER_DEPS__QUOTED := -C43_DEPS__QUOTED := -CPP_DEPS__QUOTED := -C64_DEPS__QUOTED := -CXX_DEPS__QUOTED := -CLA_DEPS__QUOTED := -S_DEPS__QUOTED := -ASM_DEPS__QUOTED := -S43_DEPS__QUOTED := -S64_DEPS__QUOTED := -S62_DEPS__QUOTED := -PDE_DEPS__QUOTED := +C55_SRCS := +A_SRCS := +ASM_UPPER_SRCS := +LDS_UPPER_SRCS := +CPP_SRCS := +CMD_SRCS := +O_SRCS := +C??_SRCS := +C64_SRCS := +C67_SRCS := +SA_SRCS := +S64_SRCS := +OPT_SRCS := +CXX_SRCS := +S67_SRCS := +S??_SRCS := +PDE_SRCS := +SV7A_SRCS := +K_SRCS := +CLA_SRCS := +S55_SRCS := +LD_UPPER_SRCS := +INO_SRCS := +LIB_SRCS := +ASM_SRCS := +S_UPPER_SRCS := +S43_SRCS := +LD_SRCS := +CMD_UPPER_SRCS := +C_UPPER_SRCS := +C++_SRCS := +C43_SRCS := +OBJ_SRCS := +LDS_SRCS := +S_SRCS := +CC_SRCS := +S62_SRCS := +C62_SRCS := +C_SRCS := +C55_DEPS := +C_UPPER_DEPS := +S67_DEPS := +S62_DEPS := +S_DEPS := +OPT_DEPS := +C??_DEPS := +ASM_UPPER_DEPS := +S??_DEPS := +C64_DEPS := +CXX_DEPS := +S64_DEPS := +INO_DEPS := +CLA_DEPS := +S55_DEPS := +SV7A_DEPS := +C62_DEPS := +C67_DEPS := +PDE_DEPS := +K_DEPS := +C_DEPS := +LIB_OUTPUTS := +CC_DEPS := +C++_DEPS := +C43_DEPS := +S43_DEPS := +OBJS := +ASM_DEPS := +S_UPPER_DEPS := +CPP_DEPS := +SA_DEPS := +C++_DEPS__QUOTED := +OPT_DEPS__QUOTED := +S_UPPER_DEPS__QUOTED := +SA_DEPS__QUOTED := +C??_DEPS__QUOTED := +S67_DEPS__QUOTED := +C55_DEPS__QUOTED := +CC_DEPS__QUOTED := +ASM_UPPER_DEPS__QUOTED := +SV7A_DEPS__QUOTED := +S??_DEPS__QUOTED := +OBJS__QUOTED := +C67_DEPS__QUOTED := +LIB_OUTPUTS__QUOTED := +K_DEPS__QUOTED := +S55_DEPS__QUOTED := +INO_DEPS__QUOTED := +C62_DEPS__QUOTED := +C_DEPS__QUOTED := +C_UPPER_DEPS__QUOTED := +C43_DEPS__QUOTED := +CPP_DEPS__QUOTED := +C64_DEPS__QUOTED := +CXX_DEPS__QUOTED := +CLA_DEPS__QUOTED := +S_DEPS__QUOTED := +ASM_DEPS__QUOTED := +S43_DEPS__QUOTED := +S64_DEPS__QUOTED := +S62_DEPS__QUOTED := +PDE_DEPS__QUOTED := # Every subdirectory with source files must be described here SUBDIRS := \ diff --git a/ports/c667x/ccs/example_build/tx/Release/subdir_vars.mk b/ports/c667x/ccs/example_build/tx/Release/subdir_vars.mk index 6a6a3ffd..70ef8b01 100644 --- a/ports/c667x/ccs/example_build/tx/Release/subdir_vars.mk +++ b/ports/c667x/ccs/example_build/tx/Release/subdir_vars.mk @@ -4,7 +4,7 @@ SHELL = cmd.exe -# Add inputs and outputs from these tool invocations to the build variables +# Add inputs and outputs from these tool invocations to the build variables ASM_SRCS += \ ../tx_thread_context_restore.asm \ ../tx_thread_context_save.asm \ @@ -12,7 +12,7 @@ ASM_SRCS += \ ../tx_thread_schedule.asm \ ../tx_thread_stack_build.asm \ ../tx_thread_system_return.asm \ -../tx_timer_interrupt.asm +../tx_timer_interrupt.asm C_SRCS += \ ../tx_block_allocate.c \ @@ -198,7 +198,7 @@ C_SRCS += \ ../txe_timer_create.c \ ../txe_timer_deactivate.c \ ../txe_timer_delete.c \ -../txe_timer_info_get.c +../txe_timer_info_get.c C_DEPS += \ ./tx_block_allocate.d \ @@ -384,7 +384,7 @@ C_DEPS += \ ./txe_timer_create.d \ ./txe_timer_deactivate.d \ ./txe_timer_delete.d \ -./txe_timer_info_get.d +./txe_timer_info_get.d OBJS += \ ./tx_block_allocate.obj \ @@ -577,7 +577,7 @@ OBJS += \ ./txe_timer_create.obj \ ./txe_timer_deactivate.obj \ ./txe_timer_delete.obj \ -./txe_timer_info_get.obj +./txe_timer_info_get.obj ASM_DEPS += \ ./tx_thread_context_restore.d \ @@ -586,7 +586,7 @@ ASM_DEPS += \ ./tx_thread_schedule.d \ ./tx_thread_stack_build.d \ ./tx_thread_system_return.d \ -./tx_timer_interrupt.d +./tx_timer_interrupt.d OBJS__QUOTED += \ "tx_block_allocate.obj" \ @@ -779,7 +779,7 @@ OBJS__QUOTED += \ "txe_timer_create.obj" \ "txe_timer_deactivate.obj" \ "txe_timer_delete.obj" \ -"txe_timer_info_get.obj" +"txe_timer_info_get.obj" C_DEPS__QUOTED += \ "tx_block_allocate.d" \ @@ -965,7 +965,7 @@ C_DEPS__QUOTED += \ "txe_timer_create.d" \ "txe_timer_deactivate.d" \ "txe_timer_delete.d" \ -"txe_timer_info_get.d" +"txe_timer_info_get.d" ASM_DEPS__QUOTED += \ "tx_thread_context_restore.d" \ @@ -974,7 +974,7 @@ ASM_DEPS__QUOTED += \ "tx_thread_schedule.d" \ "tx_thread_stack_build.d" \ "tx_thread_system_return.d" \ -"tx_timer_interrupt.d" +"tx_timer_interrupt.d" C_SRCS__QUOTED += \ "../tx_block_allocate.c" \ @@ -1160,7 +1160,7 @@ C_SRCS__QUOTED += \ "../txe_timer_create.c" \ "../txe_timer_deactivate.c" \ "../txe_timer_delete.c" \ -"../txe_timer_info_get.c" +"../txe_timer_info_get.c" ASM_SRCS__QUOTED += \ "../tx_thread_context_restore.asm" \ @@ -1169,6 +1169,6 @@ ASM_SRCS__QUOTED += \ "../tx_thread_schedule.asm" \ "../tx_thread_stack_build.asm" \ "../tx_thread_system_return.asm" \ -"../tx_timer_interrupt.asm" +"../tx_timer_interrupt.asm" diff --git a/ports/c667x/ccs/inc/tx_port.h b/ports/c667x/ccs/inc/tx_port.h index 2cec57d3..6f5a9838 100644 --- a/ports/c667x/ccs/inc/tx_port.h +++ b/ports/c667x/ccs/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,10 +21,10 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ /* tx_port.h C667x/TI */ /* 6.1.11 */ /* */ @@ -32,28 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 04-25-2022 Wenhui Xie Modified comment(s), */ -/* optimized the definition of */ -/* TX_TIMER_TICKS_PER_SECOND, */ -/* resulting in version 6.1.11 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -66,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -80,7 +68,7 @@ #include -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -116,12 +104,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 2048 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX C6xxx port. */ +/* Define various constants for the ThreadX C6xxx port. */ #define TX_INT_DISABLE 0x00 /* Disable interrupts */ #define TX_INT_ENABLE 0x01 /* Enable interrupts */ @@ -132,8 +120,8 @@ typedef unsigned short USHORT; #endif -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -162,7 +150,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -174,13 +162,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -196,11 +184,11 @@ typedef unsigned short USHORT; #define TX_TIMER_INTERNAL_EXTENSION ULONG tx_timer_internal_padding; */ -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -208,8 +196,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -236,9 +224,9 @@ typedef unsigned short USHORT; #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -269,8 +257,8 @@ unsigned int _tx_thread_interrupt_control(unsigned int); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX C667x/TI Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX C667x/TI Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/c667x/ccs/readme_threadx.txt b/ports/c667x/ccs/readme_threadx.txt index 8826de45..989f0b49 100644 --- a/ports/c667x/ccs/readme_threadx.txt +++ b/ports/c667x/ccs/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for TMS320C667x + Microsoft's Azure RTOS ThreadX for TMS320C667x Using the TI Code Composer Tools @@ -17,73 +17,73 @@ It is assumed the tools are installed in the default directories: CCS path by default - c:\ti\ccsv(version number) MCSDK path by default - c:\ti -If the packages are installed in different directories, the ThreadX project +If the packages are installed in different directories, the ThreadX project settings must be adjusted. -2. Open the Azure RTOS Workspace +2. Open the Azure RTOS Workspace -In order to build the ThreadX library and the ThreadX demonstration first open -the Azure RTOS Workspace inside your ThreadX installation directory. +In order to build the ThreadX library and the ThreadX demonstration first open +the Azure RTOS Workspace inside your ThreadX installation directory. 3. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply import the CCS project file -"tx" and then select the build button. You should now observe the compilation -and assembly of the ThreadX library. This project build produces the ThreadX +Building the ThreadX library is easy; simply import the CCS project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX library file tx.lib. 4. Demonstration System -The ThreadX demonstration is designed to execute on the C6678EVM evaluation board. +The ThreadX demonstration is designed to execute on the C6678EVM evaluation board. Building the demonstration is easy; simply import the "sample_threadx_c6678evm" project. -Now select "Project -> Build Active Project" to build the ThreadX demonstration, -which produces the sample_threadx.out file in the "Debug" directory. You are now +Now select "Project -> Build Active Project" to build the ThreadX demonstration, +which produces the sample_threadx.out file in the "Debug" directory. You are now ready to run the ThreadX demonstration on the C6678EVM evaluation board. -Please refer to Chapter 6 of the ThreadX User Guide for a complete description -of this demonstration. +Please refer to Chapter 6 of the ThreadX User Guide for a complete description +of this demonstration. 5. System Initialization -The entry point in ThreadX for the TMS320C667x using the TI tools is at label -_c_int00. This is defined within the TI library. In addition, this is -where all static and global pre-set C variable initialization processing +The entry point in ThreadX for the TMS320C667x using the TI tools is at label +_c_int00. This is defined within the TI library. In addition, this is +where all static and global pre-set C variable initialization processing takes place. -The ThreadX initialization file tx_initialize_low_level.asm is responsible -for setting up various system data structures, the vector area, and a periodic -timer interrupt source. By default, the vector area is defined to be located in -the "vectors" section, which is defined at the top of tx_initialize_low_level.asm. -This area is located at address 0 for the demonstration. +The ThreadX initialization file tx_initialize_low_level.asm is responsible +for setting up various system data structures, the vector area, and a periodic +timer interrupt source. By default, the vector area is defined to be located in +the "vectors" section, which is defined at the top of tx_initialize_low_level.asm. +This area is located at address 0 for the demonstration. -tx_initialize_low_level.asm is also where initialization of a periodic timer +tx_initialize_low_level.asm is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level determines the first available address -for use by the application. By default, free memory is assumed to start after +In addition, _tx_initialize_low_level determines the first available address +for use by the application. By default, free memory is assumed to start after the .zend section in RAM (defined in tx_initialize_low_level). This section must be placed at the end of your other RAM sections. Please see sample_threadx.cmd -for an example. The address of this section is passed to the application definition +for an example. The address of this section is passed to the application definition function, tx_application_define. 6. Register Usage and Stack Frames -The TI TMS320C667x compiler assumes that registers A0-A9, A16-A31, B0-B9, and -B16-B31 are scratch registers for each function. All other registers used by -a C function must be preserved by the function. ThreadX takes advantage of this -in situations where a context switch happens as a result of making a ThreadX -service call (which is itself a C function). In such cases, the saved context +The TI TMS320C667x compiler assumes that registers A0-A9, A16-A31, B0-B9, and +B16-B31 are scratch registers for each function. All other registers used by +a C function must be preserved by the function. ThreadX takes advantage of this +in situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -101,10 +101,10 @@ associated thread control block TX_THREAD. 0x24 A4 A14 0x28 A5 A15 0x2C A6 B10 - 0x30 A7 B11 - 0x34 A8 B12 - 0x38 A9 B13 - 0x3C A10 ILC + 0x30 A7 B11 + 0x34 A8 B12 + 0x38 A9 B13 + 0x3C A10 ILC 0x40 A11 RILC 0x44 A12 0x48 A13 @@ -159,38 +159,38 @@ associated thread control block TX_THREAD. 0x10C ILC 0x110 RILC 0x114 ITSR - + 7. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some performance. +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make it run faster, you can replace the -g compiler option -to a -O3 in the ThreadX project file to enable all compiler optimizations. +to a -O3 in the ThreadX project file to enable all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 8. Interrupt Handling -ThreadX provides complete and high-performance interrupt handling for -TMS320C667x targets. There are a certain set of requirements that are +ThreadX provides complete and high-performance interrupt handling for +TMS320C667x targets. There are a certain set of requirements that are defined in the following sub-sections: 8.1 Vector Area -The TMS320C667x interrupt vectors at in the section "vectors" and is defined at -the top of tx_initialize_low_level.asm. Each interrupt vector entry contains -a jump to a template interrupt processing shell. +The TMS320C667x interrupt vectors at in the section "vectors" and is defined at +the top of tx_initialize_low_level.asm. Each interrupt vector entry contains +a jump to a template interrupt processing shell. 8.2 Interrupt Service Routine Shells -The following interrupt processing shells are defined at the bottom of +The following interrupt processing shells are defined at the bottom of tx_initialize_low_level.asm: @@ -207,18 +207,18 @@ tx_initialize_low_level.asm: __tx_int14_ISR __tx_int15_ISR -Each interrupt ISR is entered with B3, A0-A4 is available (these registers are -saved in the initial vector processing). The default interrupt handling +Each interrupt ISR is entered with B3, A0-A4 is available (these registers are +saved in the initial vector processing). The default interrupt handling includes calls to __tx_thread_context_save and __tx_thread_context_restore. -Application ISR processing can be added between the context save/restore +Application ISR processing can be added between the context save/restore calls. Note that only the compiler scratch registers are available for use after context save return to the ISR. -High-frequency interrupt handlers might not want to perform context -save/restore processing on each interrupt. If this is the case, any +High-frequency interrupt handlers might not want to perform context +save/restore processing on each interrupt. If this is the case, any additional registers used must be saved and restored by the ISR and the interrupt return processing must restore the registers saved by the -initial vector processing. This can be accomplished by adding the +initial vector processing. This can be accomplished by adding the following code to the end of the custom ISR handling: LDW *+SP(20),A0 ; Recover A0 diff --git a/ports/c667x/ccs/src/tx_thread_context_restore.asm b/ports/c667x/ccs/src/tx_thread_context_restore.asm index 593881ba..496e413e 100644 --- a/ports/c667x/ccs/src/tx_thread_context_restore.asm +++ b/ports/c667x/ccs/src/tx_thread_context_restore.asm @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -43,41 +43,41 @@ SP .set B15 ; ; .sect ".text" -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore C667x/TI */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore C667x/TI */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -99,20 +99,20 @@ _tx_thread_context_restore: ; { ; MVKL _tx_thread_system_state,A0 ; Build address of system state - MVKH _tx_thread_system_state,A0 ; + MVKH _tx_thread_system_state,A0 ; LDW *A0,A1 ; Pickup system state variable MVKL _tx_thread_current_ptr,A2 ; Build address of current thread ptr NOP 3 ; Delay slots SUB A1,1,A1 ; Decrement system state [!A1] B _tx_thread_not_nested_restore ; If 0, not a nested restore - MVKH _tx_thread_current_ptr,A2 ; + MVKH _tx_thread_current_ptr,A2 ; LDW *A2,A3 ; Pickup current thread pointer STW A1,*A0 ; Store system state NOP 2 ; Delay slots ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDW *+SP(8),B0 ; Recover saved CSR @@ -196,19 +196,19 @@ _tx_thread_not_nested_restore: MV A3,A1 ; Move thread pointer into A1 [!A1] B _tx_thread_schedule ; If null, idle system restore MVKL _tx_thread_preempt_disable,A0 ; Build preempt disable flag address - MVKH _tx_thread_preempt_disable,A0 ; + MVKH _tx_thread_preempt_disable,A0 ; MVKL _tx_thread_execute_ptr,A4 ; Build execute thread pointer - MVKH _tx_thread_execute_ptr,A4 ; + MVKH _tx_thread_execute_ptr,A4 ; LDW *A0,B1 ; Pickup preempt disable flag - LDW *A4,A6 ; Pickup next thread to execute + LDW *A4,A6 ; Pickup next thread to execute NOP 4 ; Delay slot CMPEQ A6,A1,A7 ; Determine if threads are the same? ADD A7,B1,B1 ; Add results together [B1] B _tx_thread_no_preempt_restore ; If set, skip preeemption LDW *+A1(8),A6 ; Recover thread's stack pointer MVKL _tx_timer_time_slice,A5 ; Build time slice address - MVKH _tx_timer_time_slice,A5 ; + MVKH _tx_timer_time_slice,A5 ; LDW *A5,B1 ; Pickup current time-slice NOP ; Delay slot ; diff --git a/ports/c667x/ccs/src/tx_thread_context_save.asm b/ports/c667x/ccs/src/tx_thread_context_save.asm index 795f720e..c6a6c307 100644 --- a/ports/c667x/ccs/src/tx_thread_context_save.asm +++ b/ports/c667x/ccs/src/tx_thread_context_save.asm @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,40 +39,40 @@ SP .set B15 ; ; .sect ".text" -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save C667x/TI */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save C667x/TI */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -93,7 +93,7 @@ _tx_thread_context_save: ; { ; MVKL _tx_thread_system_state,A0 ; Build address of system state - MVKH _tx_thread_system_state,A0 ; + MVKH _tx_thread_system_state,A0 ; LDW *A0,A1 ; Pickup current system state STW A5,*+SP(40) ; Save A5 STW A6,*+SP(44) ; Save A6 @@ -101,7 +101,7 @@ _tx_thread_context_save: STW A8,*+SP(52) ; Save A8 [!A1] B _tx_thread_not_nested_save ; If 0, not a nested save condition MVKL _tx_thread_current_ptr,A3 ; Build address of current thread ptr - MVKH _tx_thread_current_ptr,A3 ; + MVKH _tx_thread_current_ptr,A3 ; LDW *A3,A2 ; Pickup current thread pointer ADD 1,A1,A1 ; Increment the system state (nested) counter STW A1,*A0 ; Store system state @@ -261,7 +261,7 @@ _tx_thread_idle_system_save: ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to ISR +; /* Not much to do here, just adjust the stack pointer, and return to ISR ; processing. */ ; B B3 ; Return to ISR diff --git a/ports/c667x/ccs/src/tx_thread_interrupt_control.asm b/ports/c667x/ccs/src/tx_thread_interrupt_control.asm index ff39fe91..f43aee94 100644 --- a/ports/c667x/ccs/src/tx_thread_interrupt_control.asm +++ b/ports/c667x/ccs/src/tx_thread_interrupt_control.asm @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,39 +34,39 @@ SP .set B15 ; ; .sect ".text" -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control C667x/TI */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control C667x/TI */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ diff --git a/ports/c667x/ccs/src/tx_thread_schedule.asm b/ports/c667x/ccs/src/tx_thread_schedule.asm index 2b40fec1..10d0b3ad 100644 --- a/ports/c667x/ccs/src/tx_thread_schedule.asm +++ b/ports/c667x/ccs/src/tx_thread_schedule.asm @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -40,42 +40,42 @@ SP .set B15 ; ; .sect ".text" -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule C667x/TI */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule C667x/TI */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLS */ -;/* */ +;/* */ +;/* OUTPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -92,7 +92,7 @@ _tx_thread_schedule OR 1,B0,B0 ; Build interrupt enable value MVC B0,CSR ; Enable interrupts MVKL _tx_thread_execute_ptr,A0 ; Build address of execute pointer - MVKH _tx_thread_execute_ptr,A0 ; + MVKH _tx_thread_execute_ptr,A0 ; ; ; /* Wait for a thread to execute. */ ; do @@ -106,13 +106,13 @@ _tx_thread_schedule_loop: ; to become ready MV A1,A4 ; Move thread pointer to A4 MVKL _tx_thread_current_ptr,A1 ; Build address of current thread ptr - MVKH _tx_thread_current_ptr,A1 ; + MVKH _tx_thread_current_ptr,A1 ; MVKL _tx_timer_time_slice,A2 ; Build address of time-slice - MVKH _tx_timer_time_slice,A2 ; + MVKH _tx_timer_time_slice,A2 ; ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Lockout interrupts and ; transfer control to it. */ ; diff --git a/ports/c667x/ccs/src/tx_thread_stack_build.asm b/ports/c667x/ccs/src/tx_thread_stack_build.asm index dabfea41..d6521d09 100644 --- a/ports/c667x/ccs/src/tx_thread_stack_build.asm +++ b/ports/c667x/ccs/src/tx_thread_stack_build.asm @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,41 +34,41 @@ SP .set B15 ADDRESS_MSK .set 0xFFFFFFF0 ; .sect ".text" -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build C667x/TI */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build C667x/TI */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function builds a stack frame on the supplied thread's stack. */ ;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ ;/* thread_ptr Pointer to thread control blk */ ;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ +;/* */ +;/* OUTPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLS */ -;/* */ +;/* */ +;/* CALLS */ +;/* */ ;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ +;/* */ +;/* CALLED BY */ +;/* */ ;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -79,10 +79,10 @@ ADDRESS_MSK .set 0xFFFFFFF0 .global _tx_thread_stack_build _tx_thread_stack_build: ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the C667x should look like the following after it is built: -; +; ; Stack Top: N/A Available for use ; 1 Interrupt stack frame type 4 ; CSR Initial value for CSR 8 @@ -160,7 +160,7 @@ _tx_thread_stack_build: ; LDW *+A4(16),A0 ; Pickup end of stack area MVKL ADDRESS_MSK,A1 ; Build address mask - MVKH ADDRESS_MSK,A1 ; + MVKH ADDRESS_MSK,A1 ; MVC CSR,B0 ; Pickup current CSR AND -2,B0,B0 ; Clear GIE bit OR 2,B0,B0 ; Set PGIE bit for interrupt return @@ -171,7 +171,7 @@ _tx_thread_stack_build: ; /* Actually build the stack frame. */ ; MVKL 1,A2 ; Build stack type - ZERO A3 ; Clear value + ZERO A3 ; Clear value STW A2,*+A0(4) ; Interrupt stack type STW B0,*+A0(8) ; Initial CSR STW B4,*+A0(12) ; Thread shell entry point diff --git a/ports/c667x/ccs/src/tx_thread_system_return.asm b/ports/c667x/ccs/src/tx_thread_system_return.asm index bf4c5caf..5123958b 100644 --- a/ports/c667x/ccs/src/tx_thread_system_return.asm +++ b/ports/c667x/ccs/src/tx_thread_system_return.asm @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -40,41 +40,41 @@ SP .set B15 ; ; .sect ".text" -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return C667x/TI */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return C667x/TI */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -109,7 +109,7 @@ _tx_thread_system_return: MVC RILC,B1 ; Pickup RILC STW B0,*+SP(60) ; Save ILC STW B1,*+SP(64) ; Save RILC -; +; ; /* Lockout interrupts. */ ; AND -2,B0,B0 ; Build interrupt disable value @@ -120,13 +120,13 @@ _tx_thread_system_return: ; SP = _tx_thread_system_stack_ptr; ; MVKL _tx_timer_time_slice,A2 ; Pickup address of time slice - MVKH _tx_timer_time_slice,A2 ; + MVKH _tx_timer_time_slice,A2 ; LDW *A2,B0 ; Pickup time slice MVKL _tx_thread_current_ptr,A1 ; Pickup address of current thread - MVKH _tx_thread_current_ptr,A1 ; + MVKH _tx_thread_current_ptr,A1 ; LDW *A1,A4 ; Pickup current thread pointer MVKL _tx_thread_system_stack_ptr,A3 ; Pickup address of system stack - MVKH _tx_thread_system_stack_ptr,A3 ; + MVKH _tx_thread_system_stack_ptr,A3 ; ; ; /* Determine if the time-slice is active. */ ; if (_tx_timer_time_slice) @@ -134,14 +134,14 @@ _tx_thread_system_return: ; [!B0] B _tx_thread_dont_save_ts ; If no-time slice, skip save NOP ; Delay slot - STW SP,*+A4(8) ; Save thread's stack pointer + STW SP,*+A4(8) ; Save thread's stack pointer LDW *A3,SP ; Switch to system stack pointer NOP ; Delay slot ; ; /* Save time-slice for the thread and clear the current time-slice. */ ; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; ; _tx_timer_time_slice = 0; - NOP ; + NOP ; STW B2,*A2 ; Clear time-slice NOP 2 ; Delay slots STW B0,*+A4(24) ; Save time-slice diff --git a/ports/c667x/ccs/src/tx_timer_interrupt.asm b/ports/c667x/ccs/src/tx_timer_interrupt.asm index 60dd91b6..48df12d7 100644 --- a/ports/c667x/ccs/src/tx_timer_interrupt.asm +++ b/ports/c667x/ccs/src/tx_timer_interrupt.asm @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -48,45 +48,45 @@ SP .set B15 ; ; .sect ".text" -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt C667x/TI */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt C667x/TI */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_context_save Context save */ -;/* _tx_thread_context_restore Context restore */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_context_save Context save */ +;/* _tx_thread_context_restore Context restore */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -106,10 +106,10 @@ _tx_timer_interrupt: ; _tx_timer_system_clock++; ; MVKL _tx_timer_system_clock,A0 ; Build address of system clock - MVKH _tx_timer_system_clock,A0 ; + MVKH _tx_timer_system_clock,A0 ; LDW *A0,A2 ; Pickup system clock MVKL _tx_timer_time_slice,A3 ; Build address of time slice - MVKH _tx_timer_time_slice,A3 ; + MVKH _tx_timer_time_slice,A3 ; LDW *A3,A1 ; Pickup time slice NOP 2 ; Delay ADD 1,A2,A2 ; Increment the system clock @@ -120,7 +120,7 @@ _tx_timer_interrupt: ; { ; [!A1] B _tx_timer_no_time_slice ; If 0, skip time slice processing - SUB A1,1,A1 ; Decrement time-slice value + SUB A1,1,A1 ; Decrement time-slice value NOP 4 ; Delay slots ; ; /* Decrement the time_slice. */ @@ -130,9 +130,9 @@ _tx_timer_interrupt: ; if (_tx_timer_time_slice == 0) ; [A1] B _tx_timer_no_time_slice ; If non-zero, not expired yet - STW A1,*A3 ; Store new time-slice + STW A1,*A3 ; Store new time-slice MVKL _tx_timer_expired_time_slice,A0 ; Build address of expired flag - MVKH _tx_timer_expired_time_slice,A0 ; + MVKH _tx_timer_expired_time_slice,A0 ; MVKL 1,A4 ; Expired flag NOP ; Delay ; @@ -149,10 +149,10 @@ _tx_timer_no_time_slice: ; { ; MVKL _tx_timer_current_ptr,A2 ; Build address of current timer pointer - MVKH _tx_timer_current_ptr,A2 ; + MVKH _tx_timer_current_ptr,A2 ; LDW *A2,A0 ; Pickup timer list address MVKL _tx_timer_expired,A3 ; Build address of expired flag - MVKH _tx_timer_expired,A3 ; + MVKH _tx_timer_expired,A3 ; NOP 2 ; Delay slots LDW *A0,A1 ; Pickup current timer entry ADD 4,A0,A0 ; Increment the current pointer @@ -179,10 +179,10 @@ _tx_timer_no_timer: ; if (_tx_timer_current_ptr == _tx_timer_list_end) ; MVKL _tx_timer_list_end,A3 ; Build timer list end address - MVKH _tx_timer_list_end,A3 ; + MVKH _tx_timer_list_end,A3 ; LDW *A3,A4 ; Pickup list end address MVKL _tx_timer_list_start,A3 ; Build timer list start address - MVKH _tx_timer_list_start,A3 ; + MVKH _tx_timer_list_start,A3 ; NOP 2 ; Delay slots CMPEQ A4,A0,A1 ; Compare current pointer with end [A1] LDW *A3,A0 ; If at the end, pickup timer list start @@ -205,10 +205,10 @@ _tx_timer_done: ; { ; MVKL _tx_timer_expired_time_slice,A3 ; Build time-slice expired flag - MVKH _tx_timer_expired_time_slice,A3 ; + MVKH _tx_timer_expired_time_slice,A3 ; LDW *A3,A4 ; Pickup time-slice expired flag MVKL _tx_timer_expired,A0 ; Build timer expired flag - MVKH _tx_timer_expired,A0 ; + MVKH _tx_timer_expired,A0 ; LDW *A0,A2 ; Pickup timer expired flag NOP 4 ; Delay slots OR A2,A4,A1 ; Combine expired flags @@ -223,8 +223,8 @@ _tx_something_expired: ; B _tx_thread_context_save ; Call context save routine MVKL _tx_timer_ISR_return,B3 ; Build return address - MVKH _tx_timer_ISR_return,B3 ; - NOP 3 ; Delay slots + MVKH _tx_timer_ISR_return,B3 ; + NOP 3 ; Delay slots _tx_timer_ISR_return: ; ; /* Did a timer expire? */ @@ -232,7 +232,7 @@ _tx_timer_ISR_return: ; { ; MVKL _tx_timer_expired,A0 ; Build timer expired address - MVKH _tx_timer_expired,A0 ; + MVKH _tx_timer_expired,A0 ; LDW *A0,A1 ; Pickup expired flag NOP 4 ; Delay slots [!A1] B _tx_timer_dont_activate ; If not set, skip timer activation @@ -243,7 +243,7 @@ _tx_timer_ISR_return: ; B _tx_timer_expiration_process ; Process timer expiration MVKL _tx_timer_ISR_return_1,B3 ; Build return address - MVKH _tx_timer_ISR_return_1,B3 ; + MVKH _tx_timer_ISR_return_1,B3 ; NOP 3 ; Delay slots _tx_timer_ISR_return_1: ; @@ -255,7 +255,7 @@ _tx_timer_dont_activate: ; { ; MVKL _tx_timer_expired_time_slice,A0 ; Build address of expired flag - MVKH _tx_timer_expired_time_slice,A0 ; + MVKH _tx_timer_expired_time_slice,A0 ; LDW *A0,A1 ; Pickup expired flag NOP 4 ; Delay slots [!A1] B _tx_timer_not_ts_expiration ; If not set, skip time-slice processing @@ -266,7 +266,7 @@ _tx_timer_dont_activate: ; B _tx_thread_time_slice ; Call time-slice processing MVKL _tx_timer_ISR_return_2,B3 ; Build return address - MVKH _tx_timer_ISR_return_2,B3 ; + MVKH _tx_timer_ISR_return_2,B3 ; NOP 3 ; Delay slots _tx_timer_ISR_return_2: ; diff --git a/ports/cortex_a12/ac6/example_build/sample_threadx/.cproject b/ports/cortex_a12/ac6/example_build/sample_threadx/.cproject index e212b36d..7882693e 100644 --- a/ports/cortex_a12/ac6/example_build/sample_threadx/.cproject +++ b/ports/cortex_a12/ac6/example_build/sample_threadx/.cproject @@ -1,176 +1,176 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a12/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_a12/ac6/example_build/sample_threadx/sample_threadx.scat index d23881cd..66d0d95a 100644 --- a/ports/cortex_a12/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports/cortex_a12/ac6/example_build/sample_threadx/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports/cortex_a12/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_a12/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 083a57a7..76395459 100644 --- a/ports/cortex_a12/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_a12/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -91,14 +92,6 @@ $_tx_initialize_low_level: /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ .global _tx_initialize_low_level .type _tx_initialize_low_level,function diff --git a/ports/cortex_a12/ac6/example_build/tx/.cproject b/ports/cortex_a12/ac6/example_build/tx/.cproject index c6b251b2..7580a13f 100644 --- a/ports/cortex_a12/ac6/example_build/tx/.cproject +++ b/ports/cortex_a12/ac6/example_build/tx/.cproject @@ -1,146 +1,146 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a12/ac6/inc/tx_port.h b/ports/cortex_a12/ac6/inc/tx_port.h index f9b96956..f0153046 100644 --- a/ports/cortex_a12/ac6/inc/tx_port.h +++ b/ports/cortex_a12/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,20 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Updated comments, removed */ -/* unneeded temp variable, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -320,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv7-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a12/ac6/src/tx_thread_context_restore.S b/ports/cortex_a12/ac6/src/tx_thread_context_restore.S index 6b4a561d..41b0b0d0 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a12/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,23 +80,6 @@ IRQ_MODE = 0x12 // IRQ mode /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_restore .type _tx_thread_context_restore,function diff --git a/ports/cortex_a12/ac6/src/tx_thread_context_save.S b/ports/cortex_a12/ac6/src/tx_thread_context_save.S index eff06283..d2d29d34 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a12/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,23 +72,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_save .type _tx_thread_context_save,function diff --git a/ports/cortex_a12/ac6/src/tx_thread_fiq_context_restore.S b/ports/cortex_a12/ac6/src/tx_thread_fiq_context_restore.S index d2fbebe1..921c322c 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a12/ac6/src/tx_thread_fiq_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -78,20 +79,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* FIQ ISR Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_restore .type _tx_thread_fiq_context_restore,function diff --git a/ports/cortex_a12/ac6/src/tx_thread_fiq_context_save.S b/ports/cortex_a12/ac6/src/tx_thread_fiq_context_save.S index 88472a3d..2f1a6c40 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a12/ac6/src/tx_thread_fiq_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_save .type _tx_thread_fiq_context_save,function diff --git a/ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_end.S index fa3886b8..a7ce701e 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_start.S index dbed1cf2..4f095dde 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a12/ac6/src/tx_thread_fiq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a12/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a12/ac6/src/tx_thread_interrupt_control.S index d1223cb8..a5bc47f7 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a12/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,20 +69,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a12/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a12/ac6/src/tx_thread_interrupt_disable.S index a87d1a06..d7b53bc2 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a12/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,20 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a12/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a12/ac6/src/tx_thread_interrupt_restore.S index 53ff2813..3c31e94b 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a12/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,20 +68,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a12/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_a12/ac6/src/tx_thread_irq_nesting_end.S index 18aebc7c..cc4db3a7 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a12/ac6/src/tx_thread_irq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a12/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_a12/ac6/src/tx_thread_irq_nesting_start.S index a2ffd35d..3635874d 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a12/ac6/src/tx_thread_irq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a12/ac6/src/tx_thread_schedule.S b/ports/cortex_a12/ac6/src/tx_thread_schedule.S index f46a339b..a74e2050 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a12/ac6/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,23 +82,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a12/ac6/src/tx_thread_stack_build.S b/ports/cortex_a12/ac6/src/tx_thread_stack_build.S index 3876225a..827554a7 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a12/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,20 +75,6 @@ CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ int /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a12/ac6/src/tx_thread_system_return.S b/ports/cortex_a12/ac6/src/tx_thread_system_return.S index 0eed478d..1a17446b 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a12/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,23 +69,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a12/ac6/src/tx_thread_vectored_context_save.S b/ports/cortex_a12/ac6/src/tx_thread_vectored_context_save.S index fe8a98e8..91653b75 100644 --- a/ports/cortex_a12/ac6/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a12/ac6/src/tx_thread_vectored_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_vectored_context_save .type _tx_thread_vectored_context_save,function diff --git a/ports/cortex_a12/ac6/src/tx_timer_interrupt.S b/ports/cortex_a12/ac6/src/tx_timer_interrupt.S index cb0c1fa2..179ac894 100644 --- a/ports/cortex_a12/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a12/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -77,20 +78,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a12/gnu/example_build/reset.S b/ports/cortex_a12/gnu/example_build/reset.S index 3ce9efb7..f2e0522b 100644 --- a/ports/cortex_a12/gnu/example_build/reset.S +++ b/ports/cortex_a12/gnu/example_build/reset.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a12/gnu/example_build/sample_threadx.ld b/ports/cortex_a12/gnu/example_build/sample_threadx.ld index cb42c11c..d43e28f1 100644 --- a/ports/cortex_a12/gnu/example_build/sample_threadx.ld +++ b/ports/cortex_a12/gnu/example_build/sample_threadx.ld @@ -7,7 +7,7 @@ OUTPUT_ARCH(arm) SECTIONS { . = 0x00000000; - + .vectors : {reset.o(.text) } /* Read-only sections, merged into text segment: */ @@ -94,8 +94,8 @@ SECTIONS *(.gnu.linkonce.t*) *(.glue_7t) *(.glue_7) } =0 - .init : - { + .init : + { KEEP (*(.init)) } =0 _etext = .; @@ -120,7 +120,7 @@ SECTIONS .data1 : { *(.data1) } .eh_frame : { KEEP (*(.eh_frame)) } .gcc_except_table : { *(.gcc_except_table) } - .ctors : + .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is @@ -153,9 +153,9 @@ SECTIONS /* We want the small data sections together, so single-instruction offsets can access them all, and initialized data all before uninitialized, so we can shorten the on-disk segment size. */ - .sdata : + .sdata : { - *(.sdata) + *(.sdata) *(.sdata.*) *(.gnu.linkonce.s.*) } @@ -191,7 +191,7 @@ SECTIONS _stack_bottom = ABSOLUTE(.) ; - /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and + /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and SYS stack if nested interrupts are enabled. */ . = ALIGN(8) ; . += 4096 ; diff --git a/ports/cortex_a12/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_a12/gnu/example_build/tx_initialize_low_level.S index 88777dfd..f9a57216 100644 --- a/ports/cortex_a12/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_a12/gnu/example_build/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -95,17 +96,6 @@ $_tx_initialize_low_level: /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_initialize_low_level .type _tx_initialize_low_level,function diff --git a/ports/cortex_a12/gnu/example_build/v7.h b/ports/cortex_a12/gnu/example_build/v7.h index 5a08b43f..c18b945c 100644 --- a/ports/cortex_a12/gnu/example_build/v7.h +++ b/ports/cortex_a12/gnu/example_build/v7.h @@ -4,7 +4,7 @@ // // Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports/cortex_a12/gnu/example_build/v7.s b/ports/cortex_a12/gnu/example_build/v7.s index 82c9ab1e..9487ddde 100644 --- a/ports/cortex_a12/gnu/example_build/v7.s +++ b/ports/cortex_a12/gnu/example_build/v7.s @@ -3,7 +3,7 @@ // // Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ @@ -20,7 +20,7 @@ enableInterrupts: CPSIE i BX lr - + .global disableInterrupts .type disableInterrupts,function @@ -28,7 +28,7 @@ enableInterrupts: disableInterrupts: CPSID i BX lr - + // ------------------------------------------------------------ // Cache Maintenance @@ -44,7 +44,7 @@ enableCaches: MCR p15, 0, r0, c1, c0, 0 // Write System Control Register ISB BX lr - + .global disableCaches @@ -57,7 +57,7 @@ disableCaches: MCR p15, 0, r0, c1, c0, 0 // Write System Control Register ISB BX lr - + .global cleanDCache @@ -114,7 +114,7 @@ clean_dcache_finished: POP {r4-r12} BX lr - + .global cleanInvalidateDCache .type cleanInvalidateDCache,function @@ -170,7 +170,7 @@ clean_invalidate_dcache_finished: POP {r4-r12} BX lr - + .global invalidateCaches @@ -229,7 +229,7 @@ invalidate_caches_skip: invalidate_caches_finished: POP {r4-r12} BX lr - + .global invalidateCaches_IS @@ -284,7 +284,7 @@ invalidate_caches_is_skip: invalidate_caches_is_finished: POP {r4-r12} BX lr - + // ------------------------------------------------------------ // TLB @@ -297,7 +297,7 @@ invalidateUnifiedTLB: MOV r0, #0 MCR p15, 0, r0, c8, c7, 0 // TLBIALL - Invalidate entire unified TLB BX lr - + .global invalidateUnifiedTLB_IS .type invalidateUnifiedTLB_IS,function @@ -306,7 +306,7 @@ invalidateUnifiedTLB_IS: MOV r0, #1 MCR p15, 0, r0, c8, c3, 0 // TLBIALLIS - Invalidate entire unified TLB Inner Shareable BX lr - + // ------------------------------------------------------------ // Branch Prediction @@ -319,7 +319,7 @@ flushBranchTargetCache: MOV r0, #0 MCR p15, 0, r0, c7, c5, 6 // BPIALL - Invalidate entire branch predictor array BX lr - + .global flushBranchTargetCache_IS .type flushBranchTargetCache_IS,function @@ -328,7 +328,7 @@ flushBranchTargetCache_IS: MOV r0, #0 MCR p15, 0, r0, c7, c1, 6 // BPIALLIS - Invalidate entire branch predictor array Inner Shareable BX lr - + // ------------------------------------------------------------ // High Vecs @@ -343,7 +343,7 @@ enableHighVecs: MCR p15, 0, r0, c1, c0, 0 // Write Control Register ISB BX lr - + .global disableHighVecs .type disableHighVecs,function @@ -354,7 +354,7 @@ disableHighVecs: MCR p15, 0, r0, c1, c0, 0 // Write Control Register ISB BX lr - + // ------------------------------------------------------------ // Context ID @@ -366,7 +366,7 @@ disableHighVecs: getContextID: MRC p15, 0, r0, c13, c0, 1 // Read Context ID Register BX lr - + .global setContextID .type setContextID,function @@ -374,7 +374,7 @@ getContextID: setContextID: MCR p15, 0, r0, c13, c0, 1 // Write Context ID Register BX lr - + // ------------------------------------------------------------ // ID registers @@ -386,7 +386,7 @@ setContextID: getMIDR: MRC p15, 0, r0, c0, c0, 0 // Read Main ID Register (MIDR) BX lr - + .global getMPIDR .type getMPIDR,function @@ -394,7 +394,7 @@ getMIDR: getMPIDR: MRC p15, 0, r0, c0 ,c0, 5// Read Multiprocessor ID register (MPIDR) BX lr - + // ------------------------------------------------------------ // CP15 SMP related @@ -407,7 +407,7 @@ getMPIDR: getBaseAddr: MRC p15, 4, r0, c15, c0, 0 // Read peripheral base address BX lr - + // ------------------------------------------------------------ @@ -419,7 +419,7 @@ getCPUID: MRC p15, 0, r0, c0, c0, 5 // Read CPU ID register AND r0, r0, #0x03 // Mask off, leaving the CPU ID field BX lr - + // ------------------------------------------------------------ @@ -431,7 +431,7 @@ goToSleep: WFI // Go into standby B goToSleep // Catch in case of rogue events BX lr - + // ------------------------------------------------------------ @@ -451,7 +451,7 @@ joinSMP: ISB BX lr - + // ------------------------------------------------------------ @@ -469,7 +469,7 @@ leaveSMP: ISB BX lr - + // ------------------------------------------------------------ // End of v7.s diff --git a/ports/cortex_a12/gnu/inc/tx_port.h b/ports/cortex_a12/gnu/inc/tx_port.h index f9b96956..f0153046 100644 --- a/ports/cortex_a12/gnu/inc/tx_port.h +++ b/ports/cortex_a12/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,20 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Updated comments, removed */ -/* unneeded temp variable, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -320,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv7-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a12/gnu/src/tx_thread_context_restore.S b/ports/cortex_a12/gnu/src/tx_thread_context_restore.S index 6b4a561d..41b0b0d0 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a12/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,23 +80,6 @@ IRQ_MODE = 0x12 // IRQ mode /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_restore .type _tx_thread_context_restore,function diff --git a/ports/cortex_a12/gnu/src/tx_thread_context_save.S b/ports/cortex_a12/gnu/src/tx_thread_context_save.S index eff06283..d2d29d34 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a12/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,23 +72,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_save .type _tx_thread_context_save,function diff --git a/ports/cortex_a12/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_a12/gnu/src/tx_thread_fiq_context_restore.S index d2fbebe1..921c322c 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a12/gnu/src/tx_thread_fiq_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -78,20 +79,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* FIQ ISR Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_restore .type _tx_thread_fiq_context_restore,function diff --git a/ports/cortex_a12/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_a12/gnu/src/tx_thread_fiq_context_save.S index 88472a3d..2f1a6c40 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a12/gnu/src/tx_thread_fiq_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_save .type _tx_thread_fiq_context_save,function diff --git a/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_end.S index fa3886b8..a7ce701e 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_start.S index dbed1cf2..4f095dde 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a12/gnu/src/tx_thread_fiq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a12/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a12/gnu/src/tx_thread_interrupt_control.S index d1223cb8..a5bc47f7 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a12/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,20 +69,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a12/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a12/gnu/src/tx_thread_interrupt_disable.S index a87d1a06..d7b53bc2 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a12/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,20 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a12/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a12/gnu/src/tx_thread_interrupt_restore.S index 53ff2813..3c31e94b 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a12/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,20 +68,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_end.S index 18aebc7c..cc4db3a7 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_start.S index a2ffd35d..3635874d 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a12/gnu/src/tx_thread_irq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a12/gnu/src/tx_thread_schedule.S b/ports/cortex_a12/gnu/src/tx_thread_schedule.S index f46a339b..a74e2050 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a12/gnu/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,23 +82,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a12/gnu/src/tx_thread_stack_build.S b/ports/cortex_a12/gnu/src/tx_thread_stack_build.S index 3876225a..827554a7 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a12/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,20 +75,6 @@ CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ int /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a12/gnu/src/tx_thread_system_return.S b/ports/cortex_a12/gnu/src/tx_thread_system_return.S index 0eed478d..1a17446b 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a12/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,23 +69,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a12/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_a12/gnu/src/tx_thread_vectored_context_save.S index fe8a98e8..91653b75 100644 --- a/ports/cortex_a12/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a12/gnu/src/tx_thread_vectored_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_vectored_context_save .type _tx_thread_vectored_context_save,function diff --git a/ports/cortex_a12/gnu/src/tx_timer_interrupt.S b/ports/cortex_a12/gnu/src/tx_timer_interrupt.S index cb0c1fa2..179ac894 100644 --- a/ports/cortex_a12/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a12/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -77,20 +78,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a15/ac6/example_build/sample_threadx/.cproject b/ports/cortex_a15/ac6/example_build/sample_threadx/.cproject index 9a96fceb..abd7ce5b 100644 --- a/ports/cortex_a15/ac6/example_build/sample_threadx/.cproject +++ b/ports/cortex_a15/ac6/example_build/sample_threadx/.cproject @@ -1,176 +1,176 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a15/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_a15/ac6/example_build/sample_threadx/sample_threadx.scat index d23881cd..66d0d95a 100644 --- a/ports/cortex_a15/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports/cortex_a15/ac6/example_build/sample_threadx/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports/cortex_a15/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_a15/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 083a57a7..76395459 100644 --- a/ports/cortex_a15/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_a15/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -91,14 +92,6 @@ $_tx_initialize_low_level: /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ .global _tx_initialize_low_level .type _tx_initialize_low_level,function diff --git a/ports/cortex_a15/ac6/example_build/tx/.cproject b/ports/cortex_a15/ac6/example_build/tx/.cproject index e8ca6dd7..8b16e939 100644 --- a/ports/cortex_a15/ac6/example_build/tx/.cproject +++ b/ports/cortex_a15/ac6/example_build/tx/.cproject @@ -1,146 +1,146 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a15/ac6/inc/tx_port.h b/ports/cortex_a15/ac6/inc/tx_port.h index f9b96956..f0153046 100644 --- a/ports/cortex_a15/ac6/inc/tx_port.h +++ b/ports/cortex_a15/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,20 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Updated comments, removed */ -/* unneeded temp variable, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -320,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv7-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a15/ac6/readme_threadx.txt b/ports/cortex_a15/ac6/readme_threadx.txt index 8d81625a..dbe89478 100644 --- a/ports/cortex_a15/ac6/readme_threadx.txt +++ b/ports/cortex_a15/ac6/readme_threadx.txt @@ -1,18 +1,18 @@ - Microsoft's Azure RTOS ThreadX for Cortex-A15 + Microsoft's Azure RTOS ThreadX for Cortex-A15 Using the AC6 Tools 1. Import the ThreadX Projects -In order to build the ThreadX library and the ThreadX demonstration, first import -the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +In order to build the ThreadX library and the ThreadX demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) into your DS workspace. 2. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply right-click the Eclipse project -"tx" and then select the "Build Project" button. You should now observe the compilation +Building the ThreadX library is easy; simply right-click the Eclipse project +"tx" and then select the "Build Project" button. You should now observe the compilation and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. @@ -22,44 +22,44 @@ library file tx.a. The ThreadX demonstration is designed to execute under the DS debugger on the VE_Cortex-A15 Bare Metal simulator. -Building the demonstration is easy; simply right-click the Eclipse project -"sample_threadx" and then select the "Build Project" button. You should now observe -the compilation and assembly of the ThreadX demonstration. This project build produces -the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder +Building the demonstration is easy; simply right-click the Eclipse project +"sample_threadx" and then select the "Build Project" button. You should now observe +the compilation and assembly of the ThreadX demonstration. This project build produces +the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder in the Project Explorer window, right-click on the 'cortex-a15_tx.launch' file, click 'Debug As', and then click 'cortex-a15_tx' from the submenu. This will cause the -debugger to load the sample_threadx.axf ELF file and run to main. You are now ready +debugger to load the sample_threadx.axf ELF file and run to main. You are now ready to execute the ThreadX demonstration. 4. System Initialization -The entry point in ThreadX for the Cortex-A15 using ARM tools is at label -"Vectors". This is defined within startup.S in the sample_threadx project. In addition, -this is where all static and global pre-set C variable initialization processing +The entry point in ThreadX for the Cortex-A15 using ARM tools is at label +"Vectors". This is defined within startup.S in the sample_threadx project. In addition, +this is where all static and global pre-set C variable initialization processing takes place. -This is also where initialization of a periodic timer interrupt source should take +This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level defines the first available address -for use by the application, which is supplied as the sole input parameter +In addition, _tx_initialize_low_level defines the first available address +for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 5. Register Usage and Stack Frames -The AC6 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The AC6 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -77,52 +77,52 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A15 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-A15 vectors start at address zero. The demonstration system startup -reset.S file contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +reset.S file contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs -ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -130,7 +130,7 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -143,7 +143,7 @@ __tx_irq_processing_return: 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_example_handler @@ -153,12 +153,12 @@ __tx_irq_example_handler: STMDB sp!, {r0-r3} @ Save some scratch registers MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers BL _tx_thread_vectored_context_save @ Call the vectored IRQ context save @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -175,22 +175,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.S. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables -nesting by disabling IRQ interrupts and switching back to IRQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -198,10 +198,10 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* Enable nested IRQ interrupts. NOTE: Since this service returns -@ with IRQ interrupts enabled, all IRQ interrupt sources must be +@ with IRQ interrupts enabled, all IRQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start -@ +@ @ /* Application ISR call(s) go here! */ @ @ /* Disable nested IRQ interrupts. The mode is switched back to @@ -214,12 +214,12 @@ __tx_irq_processing_return: 7.3 FIQ Interrupts -By default, FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.S. @@ -228,7 +228,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.S. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.S: @@ -256,18 +256,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.S. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -283,7 +283,7 @@ __tx_fiq_processing_return: @ interrupt, and all C scratch registers are available for use. */ @ @ /* Enable nested FIQ interrupts. NOTE: Since this service returns -@ with FIQ interrupts enabled, all FIQ interrupt sources must be +@ with FIQ interrupts enabled, all FIQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start @ @@ -299,12 +299,12 @@ __tx_fiq_processing_return: 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer -interrupt source, these services are not functional but the remainder of +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of ThreadX will still run. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.S for the demonstration system. @@ -312,7 +312,7 @@ found in the file tx_initialize_low_level.S for the demonstration system. 9. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); diff --git a/ports/cortex_a15/ac6/src/tx_thread_context_restore.S b/ports/cortex_a15/ac6/src/tx_thread_context_restore.S index 6b4a561d..41b0b0d0 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a15/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,23 +80,6 @@ IRQ_MODE = 0x12 // IRQ mode /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_restore .type _tx_thread_context_restore,function diff --git a/ports/cortex_a15/ac6/src/tx_thread_context_save.S b/ports/cortex_a15/ac6/src/tx_thread_context_save.S index eff06283..d2d29d34 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a15/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,23 +72,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_save .type _tx_thread_context_save,function diff --git a/ports/cortex_a15/ac6/src/tx_thread_fiq_context_restore.S b/ports/cortex_a15/ac6/src/tx_thread_fiq_context_restore.S index d2fbebe1..921c322c 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a15/ac6/src/tx_thread_fiq_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -78,20 +79,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* FIQ ISR Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_restore .type _tx_thread_fiq_context_restore,function diff --git a/ports/cortex_a15/ac6/src/tx_thread_fiq_context_save.S b/ports/cortex_a15/ac6/src/tx_thread_fiq_context_save.S index 88472a3d..2f1a6c40 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a15/ac6/src/tx_thread_fiq_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_save .type _tx_thread_fiq_context_save,function diff --git a/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_end.S index fa3886b8..a7ce701e 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_start.S index dbed1cf2..4f095dde 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a15/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a15/ac6/src/tx_thread_interrupt_control.S index d1223cb8..a5bc47f7 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a15/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,20 +69,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a15/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a15/ac6/src/tx_thread_interrupt_disable.S index a87d1a06..d7b53bc2 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a15/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,20 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a15/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a15/ac6/src/tx_thread_interrupt_restore.S index 53ff2813..3c31e94b 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a15/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,20 +68,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_end.S index 18aebc7c..cc4db3a7 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_start.S index a2ffd35d..3635874d 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a15/ac6/src/tx_thread_schedule.S b/ports/cortex_a15/ac6/src/tx_thread_schedule.S index f46a339b..a74e2050 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a15/ac6/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,23 +82,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a15/ac6/src/tx_thread_stack_build.S b/ports/cortex_a15/ac6/src/tx_thread_stack_build.S index 3876225a..827554a7 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a15/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,20 +75,6 @@ CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ int /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a15/ac6/src/tx_thread_system_return.S b/ports/cortex_a15/ac6/src/tx_thread_system_return.S index 0eed478d..1a17446b 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a15/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,23 +69,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a15/ac6/src/tx_thread_vectored_context_save.S b/ports/cortex_a15/ac6/src/tx_thread_vectored_context_save.S index fe8a98e8..91653b75 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a15/ac6/src/tx_thread_vectored_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_vectored_context_save .type _tx_thread_vectored_context_save,function diff --git a/ports/cortex_a15/ac6/src/tx_timer_interrupt.S b/ports/cortex_a15/ac6/src/tx_timer_interrupt.S index cb0c1fa2..179ac894 100644 --- a/ports/cortex_a15/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a15/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -77,20 +78,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a15/gnu/example_build/reset.S b/ports/cortex_a15/gnu/example_build/reset.S index 3ce9efb7..f2e0522b 100644 --- a/ports/cortex_a15/gnu/example_build/reset.S +++ b/ports/cortex_a15/gnu/example_build/reset.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a15/gnu/example_build/sample_threadx.ld b/ports/cortex_a15/gnu/example_build/sample_threadx.ld index cb42c11c..d43e28f1 100644 --- a/ports/cortex_a15/gnu/example_build/sample_threadx.ld +++ b/ports/cortex_a15/gnu/example_build/sample_threadx.ld @@ -7,7 +7,7 @@ OUTPUT_ARCH(arm) SECTIONS { . = 0x00000000; - + .vectors : {reset.o(.text) } /* Read-only sections, merged into text segment: */ @@ -94,8 +94,8 @@ SECTIONS *(.gnu.linkonce.t*) *(.glue_7t) *(.glue_7) } =0 - .init : - { + .init : + { KEEP (*(.init)) } =0 _etext = .; @@ -120,7 +120,7 @@ SECTIONS .data1 : { *(.data1) } .eh_frame : { KEEP (*(.eh_frame)) } .gcc_except_table : { *(.gcc_except_table) } - .ctors : + .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is @@ -153,9 +153,9 @@ SECTIONS /* We want the small data sections together, so single-instruction offsets can access them all, and initialized data all before uninitialized, so we can shorten the on-disk segment size. */ - .sdata : + .sdata : { - *(.sdata) + *(.sdata) *(.sdata.*) *(.gnu.linkonce.s.*) } @@ -191,7 +191,7 @@ SECTIONS _stack_bottom = ABSOLUTE(.) ; - /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and + /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and SYS stack if nested interrupts are enabled. */ . = ALIGN(8) ; . += 4096 ; diff --git a/ports/cortex_a15/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_a15/gnu/example_build/tx_initialize_low_level.S index 88777dfd..f9a57216 100644 --- a/ports/cortex_a15/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_a15/gnu/example_build/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -95,17 +96,6 @@ $_tx_initialize_low_level: /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_initialize_low_level .type _tx_initialize_low_level,function diff --git a/ports/cortex_a15/gnu/example_build/v7.h b/ports/cortex_a15/gnu/example_build/v7.h index 5a08b43f..c18b945c 100644 --- a/ports/cortex_a15/gnu/example_build/v7.h +++ b/ports/cortex_a15/gnu/example_build/v7.h @@ -4,7 +4,7 @@ // // Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports/cortex_a15/gnu/example_build/v7.s b/ports/cortex_a15/gnu/example_build/v7.s index 82c9ab1e..9487ddde 100644 --- a/ports/cortex_a15/gnu/example_build/v7.s +++ b/ports/cortex_a15/gnu/example_build/v7.s @@ -3,7 +3,7 @@ // // Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ @@ -20,7 +20,7 @@ enableInterrupts: CPSIE i BX lr - + .global disableInterrupts .type disableInterrupts,function @@ -28,7 +28,7 @@ enableInterrupts: disableInterrupts: CPSID i BX lr - + // ------------------------------------------------------------ // Cache Maintenance @@ -44,7 +44,7 @@ enableCaches: MCR p15, 0, r0, c1, c0, 0 // Write System Control Register ISB BX lr - + .global disableCaches @@ -57,7 +57,7 @@ disableCaches: MCR p15, 0, r0, c1, c0, 0 // Write System Control Register ISB BX lr - + .global cleanDCache @@ -114,7 +114,7 @@ clean_dcache_finished: POP {r4-r12} BX lr - + .global cleanInvalidateDCache .type cleanInvalidateDCache,function @@ -170,7 +170,7 @@ clean_invalidate_dcache_finished: POP {r4-r12} BX lr - + .global invalidateCaches @@ -229,7 +229,7 @@ invalidate_caches_skip: invalidate_caches_finished: POP {r4-r12} BX lr - + .global invalidateCaches_IS @@ -284,7 +284,7 @@ invalidate_caches_is_skip: invalidate_caches_is_finished: POP {r4-r12} BX lr - + // ------------------------------------------------------------ // TLB @@ -297,7 +297,7 @@ invalidateUnifiedTLB: MOV r0, #0 MCR p15, 0, r0, c8, c7, 0 // TLBIALL - Invalidate entire unified TLB BX lr - + .global invalidateUnifiedTLB_IS .type invalidateUnifiedTLB_IS,function @@ -306,7 +306,7 @@ invalidateUnifiedTLB_IS: MOV r0, #1 MCR p15, 0, r0, c8, c3, 0 // TLBIALLIS - Invalidate entire unified TLB Inner Shareable BX lr - + // ------------------------------------------------------------ // Branch Prediction @@ -319,7 +319,7 @@ flushBranchTargetCache: MOV r0, #0 MCR p15, 0, r0, c7, c5, 6 // BPIALL - Invalidate entire branch predictor array BX lr - + .global flushBranchTargetCache_IS .type flushBranchTargetCache_IS,function @@ -328,7 +328,7 @@ flushBranchTargetCache_IS: MOV r0, #0 MCR p15, 0, r0, c7, c1, 6 // BPIALLIS - Invalidate entire branch predictor array Inner Shareable BX lr - + // ------------------------------------------------------------ // High Vecs @@ -343,7 +343,7 @@ enableHighVecs: MCR p15, 0, r0, c1, c0, 0 // Write Control Register ISB BX lr - + .global disableHighVecs .type disableHighVecs,function @@ -354,7 +354,7 @@ disableHighVecs: MCR p15, 0, r0, c1, c0, 0 // Write Control Register ISB BX lr - + // ------------------------------------------------------------ // Context ID @@ -366,7 +366,7 @@ disableHighVecs: getContextID: MRC p15, 0, r0, c13, c0, 1 // Read Context ID Register BX lr - + .global setContextID .type setContextID,function @@ -374,7 +374,7 @@ getContextID: setContextID: MCR p15, 0, r0, c13, c0, 1 // Write Context ID Register BX lr - + // ------------------------------------------------------------ // ID registers @@ -386,7 +386,7 @@ setContextID: getMIDR: MRC p15, 0, r0, c0, c0, 0 // Read Main ID Register (MIDR) BX lr - + .global getMPIDR .type getMPIDR,function @@ -394,7 +394,7 @@ getMIDR: getMPIDR: MRC p15, 0, r0, c0 ,c0, 5// Read Multiprocessor ID register (MPIDR) BX lr - + // ------------------------------------------------------------ // CP15 SMP related @@ -407,7 +407,7 @@ getMPIDR: getBaseAddr: MRC p15, 4, r0, c15, c0, 0 // Read peripheral base address BX lr - + // ------------------------------------------------------------ @@ -419,7 +419,7 @@ getCPUID: MRC p15, 0, r0, c0, c0, 5 // Read CPU ID register AND r0, r0, #0x03 // Mask off, leaving the CPU ID field BX lr - + // ------------------------------------------------------------ @@ -431,7 +431,7 @@ goToSleep: WFI // Go into standby B goToSleep // Catch in case of rogue events BX lr - + // ------------------------------------------------------------ @@ -451,7 +451,7 @@ joinSMP: ISB BX lr - + // ------------------------------------------------------------ @@ -469,7 +469,7 @@ leaveSMP: ISB BX lr - + // ------------------------------------------------------------ // End of v7.s diff --git a/ports/cortex_a15/gnu/inc/tx_port.h b/ports/cortex_a15/gnu/inc/tx_port.h index f9b96956..f0153046 100644 --- a/ports/cortex_a15/gnu/inc/tx_port.h +++ b/ports/cortex_a15/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,20 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Updated comments, removed */ -/* unneeded temp variable, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -320,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv7-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a15/gnu/readme_threadx.txt b/ports/cortex_a15/gnu/readme_threadx.txt index 5bd5eb7c..80a0cf6a 100644 --- a/ports/cortex_a15/gnu/readme_threadx.txt +++ b/ports/cortex_a15/gnu/readme_threadx.txt @@ -1,55 +1,55 @@ - Microsoft's Azure RTOS ThreadX for Cortex-A15 + Microsoft's Azure RTOS ThreadX for Cortex-A15 Using the GNU Tools 1. Building the ThreadX run-time Library -First make sure you are in the "example_build" directory. Also, make sure that -you have setup your path and other environment variables necessary for the GNU -development environment. +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the GNU +development environment. -At this point you may run the build_threadx.bat batch file. This will build the -ThreadX run-time environment in the "example_build" directory. +At this point you may run the build_threadx.bat batch file. This will build the +ThreadX run-time environment in the "example_build" directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. 2. Demonstration System -Building the demonstration is easy; simply execute the build_threadx_sample.bat -batch file while inside the "example_build" directory. +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with TX.A. The resulting file DEMO is a binary file +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with TX.A. The resulting file DEMO is a binary file that can be downloaded and executed. 3. System Initialization -The entry point in ThreadX for the Cortex-A15 using GNU tools is at label _start. +The entry point in ThreadX for the Cortex-A15 using GNU tools is at label _start. This is defined within the modified version of the GNU startup code - crt0.S. -The ThreadX tx_initialize_low_level.S file is responsible for setting up various -system data structures, the interrupt vectors, and a periodic timer interrupt source. -By default, the vector area is defined to be located at the "__vectors" label, -which is defined in reset.S. This area is typically located at 0. In situations -where this is impossible, the vectors at the "__vectors" label should be copied +The ThreadX tx_initialize_low_level.S file is responsible for setting up various +system data structures, the interrupt vectors, and a periodic timer interrupt source. +By default, the vector area is defined to be located at the "__vectors" label, +which is defined in reset.S. This area is typically located at 0. In situations +where this is impossible, the vectors at the "__vectors" label should be copied to address 0. -This is also where initialization of a periodic timer interrupt source should take +This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level defines the first available address -for use by the application, which is supplied as the sole input parameter +In addition, _tx_initialize_low_level defines the first available address +for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 4. Assembler / Compiler Switches -The following are compiler switches used in building the demonstration +The following are compiler switches used in building the demonstration system: Compiler/Assembler Meaning @@ -73,164 +73,164 @@ Application Defines ( -D option) ThreadX assembly files. If used, it should be used on all assembly files and the generic C source of - ThreadX should be compiled with + ThreadX should be compiled with TX_ENABLE_FIQ_SUPPORT defined as well. TX_ENABLE_IRQ_NESTING This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.S. TX_ENABLE_FIQ_NESTING This assembler define enables FIQ - nested support. If FIQ nested + nested support. If FIQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.S. In addition, IRQ nesting should also be enabled. TX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ interrupt handling in the ThreadX - generic C source. This define + generic C source. This define should also be used in conjunction with the corresponding assembler - define. + define. TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - TX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. 5. Register Usage and Stack Frames -The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -248,52 +248,52 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A15 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-A15 vectors start at address zero. The demonstration system startup -reset.S file contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +reset.S file contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs -ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -301,7 +301,7 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -314,7 +314,7 @@ __tx_irq_processing_return: 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_example_handler @@ -324,12 +324,12 @@ __tx_irq_example_handler: STMDB sp!, {r0-r3} @ Save some scratch registers MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers BL _tx_thread_vectored_context_save @ Call the vectored IRQ context save @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -346,22 +346,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.S. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables -nesting by disabling IRQ interrupts and switching back to IRQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -369,10 +369,10 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* Enable nested IRQ interrupts. NOTE: Since this service returns -@ with IRQ interrupts enabled, all IRQ interrupt sources must be +@ with IRQ interrupts enabled, all IRQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start -@ +@ @ /* Application ISR call(s) go here! */ @ @ /* Disable nested IRQ interrupts. The mode is switched back to @@ -385,12 +385,12 @@ __tx_irq_processing_return: 7.3 FIQ Interrupts -By default, FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.S. @@ -399,7 +399,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.S. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.S: @@ -427,18 +427,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.S. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -454,7 +454,7 @@ __tx_fiq_processing_return: @ interrupt, and all C scratch registers are available for use. */ @ @ /* Enable nested FIQ interrupts. NOTE: Since this service returns -@ with FIQ interrupts enabled, all FIQ interrupt sources must be +@ with FIQ interrupts enabled, all FIQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start @ @@ -470,12 +470,12 @@ __tx_fiq_processing_return: 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer -interrupt source, these services are not functional but the remainder of +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of ThreadX will still run. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.S for the demonstration system. @@ -483,7 +483,7 @@ found in the file tx_initialize_low_level.S for the demonstration system. 9. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); diff --git a/ports/cortex_a15/gnu/src/tx_thread_context_restore.S b/ports/cortex_a15/gnu/src/tx_thread_context_restore.S index 6b4a561d..41b0b0d0 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a15/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,23 +80,6 @@ IRQ_MODE = 0x12 // IRQ mode /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_restore .type _tx_thread_context_restore,function diff --git a/ports/cortex_a15/gnu/src/tx_thread_context_save.S b/ports/cortex_a15/gnu/src/tx_thread_context_save.S index eff06283..d2d29d34 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a15/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,23 +72,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_save .type _tx_thread_context_save,function diff --git a/ports/cortex_a15/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_a15/gnu/src/tx_thread_fiq_context_restore.S index d2fbebe1..921c322c 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a15/gnu/src/tx_thread_fiq_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -78,20 +79,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* FIQ ISR Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_restore .type _tx_thread_fiq_context_restore,function diff --git a/ports/cortex_a15/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_a15/gnu/src/tx_thread_fiq_context_save.S index 88472a3d..2f1a6c40 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a15/gnu/src/tx_thread_fiq_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_save .type _tx_thread_fiq_context_save,function diff --git a/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_end.S index fa3886b8..a7ce701e 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_start.S index dbed1cf2..4f095dde 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a15/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a15/gnu/src/tx_thread_interrupt_control.S index d1223cb8..a5bc47f7 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a15/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,20 +69,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a15/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a15/gnu/src/tx_thread_interrupt_disable.S index a87d1a06..d7b53bc2 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a15/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,20 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a15/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a15/gnu/src/tx_thread_interrupt_restore.S index 53ff2813..3c31e94b 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a15/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,20 +68,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_end.S index 18aebc7c..cc4db3a7 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_start.S index a2ffd35d..3635874d 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a15/gnu/src/tx_thread_schedule.S b/ports/cortex_a15/gnu/src/tx_thread_schedule.S index f46a339b..a74e2050 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a15/gnu/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,23 +82,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a15/gnu/src/tx_thread_stack_build.S b/ports/cortex_a15/gnu/src/tx_thread_stack_build.S index 3876225a..827554a7 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a15/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,20 +75,6 @@ CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ int /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a15/gnu/src/tx_thread_system_return.S b/ports/cortex_a15/gnu/src/tx_thread_system_return.S index 0eed478d..1a17446b 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a15/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,23 +69,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a15/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_a15/gnu/src/tx_thread_vectored_context_save.S index fe8a98e8..91653b75 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a15/gnu/src/tx_thread_vectored_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_vectored_context_save .type _tx_thread_vectored_context_save,function diff --git a/ports/cortex_a15/gnu/src/tx_timer_interrupt.S b/ports/cortex_a15/gnu/src/tx_timer_interrupt.S index cb0c1fa2..179ac894 100644 --- a/ports/cortex_a15/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a15/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -77,20 +78,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a15/iar/example_build/cstartup.s b/ports/cortex_a15/iar/example_build/cstartup.s index 647de2e8..b4ed8f87 100644 --- a/ports/cortex_a15/iar/example_build/cstartup.s +++ b/ports/cortex_a15/iar/example_build/cstartup.s @@ -1,7 +1,7 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; -;; Part one of the system initialization code, +;; Part one of the system initialization code, ;; contains low-level ;; initialization. ;; @@ -71,13 +71,13 @@ FIQ_Addr: DCD __tx_fiq_handler SECTION .text:CODE:NOROOT(2) -; PUBLIC ?cstartup +; PUBLIC ?cstartup EXTERN ?main REQUIRE __vector - ARM - -__iar_program_start: + ARM + +__iar_program_start: ?cstartup: ; diff --git a/ports/cortex_a15/iar/example_build/sample_threadx.c b/ports/cortex_a15/iar/example_build/sample_threadx.c index c7c300cb..afbd4ea8 100644 --- a/ports/cortex_a15/iar/example_build/sample_threadx.c +++ b/ports/cortex_a15/iar/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -83,42 +83,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -126,23 +126,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -245,11 +245,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -308,7 +308,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -361,7 +361,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_a15/iar/example_build/tx_initialize_low_level.s b/ports/cortex_a15/iar/example_build/tx_initialize_low_level.s index 6b32af58..13bb51f0 100644 --- a/ports/cortex_a15/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_a15/iar/example_build/tx_initialize_low_level.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -52,7 +52,7 @@ SYS_STACK_SIZE DEFINE 1024 ; System stack size ; ; ; -;/* Define the FREE_MEM segment that will specify where free memory is +;/* Define the FREE_MEM segment that will specify where free memory is ; defined. This must also be located in at the end of other RAM segments ; in the linker control file. The value of this segment is what is passed ; to tx_application_define. */ @@ -65,45 +65,39 @@ __tx_free_memory_start ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-A15/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-A15/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -136,7 +130,7 @@ _tx_initialize_low_level ; LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address STR r0, [r2, #0] ; Save first free memory address -; +; ; /* Setup Timer for periodic interrupts. */ ; ; /* Done, return to caller. */ @@ -187,17 +181,17 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -211,7 +205,7 @@ __tx_irq_processing_return ; ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -227,28 +221,28 @@ __tx_irq_processing_return ;__tx_example_vectored_irq_handler: ; ; -; /* Save initial context and call context save to prepare for +; /* Save initial context and call context save to prepare for ; vectored ISR execution. */ ; ; STMDB sp!, {r0-r3} ; Save some scratch registers ; MRS r0, SPSR ; Pickup saved SPSR -; SUB lr, lr, #4 ; Adjust point of interrupt +; SUB lr, lr, #4 ; Adjust point of interrupt ; STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers ; BL _tx_thread_vectored_context_save ; Vectored context save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ;#ifdef TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_start @@ -257,7 +251,7 @@ __tx_irq_processing_return ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ;#ifdef TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_end @@ -281,11 +275,11 @@ __tx_fiq_processing_return ; /* At this point execution is still in the FIQ mode. The CPSR, point of ; interrupt, and all C scratch registers are available for use. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start ; from FIQ mode with interrupts disabled. This routine switches to the -; system mode and returns with FIQ interrupts enabled. +; system mode and returns with FIQ interrupts enabled. ; -; NOTE: It is very important to ensure all FIQ interrupts are cleared +; NOTE: It is very important to ensure all FIQ interrupts are cleared ; prior to enabling nested FIQ interrupts. */ #ifdef TX_ENABLE_FIQ_NESTING BL _tx_thread_fiq_nesting_start diff --git a/ports/cortex_a15/iar/inc/tx_port.h b/ports/cortex_a15/iar/inc/tx_port.h index 719f0e72..ca868f64 100644 --- a/ports/cortex_a15/iar/inc/tx_port.h +++ b/ports/cortex_a15/iar/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Cortex-A15/IAR */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A15/IAR */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -79,7 +71,7 @@ #endif -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -115,12 +107,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -130,8 +122,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -189,7 +181,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -203,18 +195,18 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ - VOID *tx_thread_iar_tls_pointer; + VOID *tx_thread_iar_tls_pointer; #else #define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; #endif -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -228,11 +220,11 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -242,23 +234,23 @@ ULONG _tx_misra_time_stamp_get(VOID); #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #if (__VER__ < 8000000) -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #endif #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -286,8 +278,8 @@ void __iar_Initlocks(void); #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -298,22 +290,22 @@ void __iar_Initlocks(void); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (UINT) __CLZ(m); \ - b = 31 - b; + b = 31 - b; #endif #endif #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ /* First, check and see what mode the file is being compiled in. The IAR compiler - defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode + defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode is present. If ARM 32-bit mode is present, the fast CPSR manipulation macros are available. Otherwise, if Thumb mode is present, we must use function calls. */ @@ -383,8 +375,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-A15/IAR Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A15/IAR Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_a15/iar/readme_threadx.txt b/ports/cortex_a15/iar/readme_threadx.txt index 151c5253..e087351f 100644 --- a/ports/cortex_a15/iar/readme_threadx.txt +++ b/ports/cortex_a15/iar/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for Cortex-A15 + Microsoft's Azure RTOS ThreadX for Cortex-A15 Thumb & 32-bit Mode @@ -7,10 +7,10 @@ 1. Building the ThreadX run-time Library Building the ThreadX library is easy. First, open the Azure RTOS workspace -azure_rtos.eww. Next, make the TX project the "active project" in the -IAR Embedded Workbench and select the "Make" button. You should observe -assembly and compilation of a series of ThreadX source files. This -results in the ThreadX run-time library file tx.a, which is needed by +azure_rtos.eww. Next, make the TX project the "active project" in the +IAR Embedded Workbench and select the "Make" button. You should observe +assembly and compilation of a series of ThreadX source files. This +results in the ThreadX run-time library file tx.a, which is needed by the application. @@ -20,47 +20,47 @@ The ThreadX demonstration is designed to execute under the IAR Windows-based Cortex-A15 simulator. Building the demonstration is easy; simply make the sample_threadx.ewp project -the "active project" in the IAR Embedded Workbench and select the +the "active project" in the IAR Embedded Workbench and select the "Make" button. -You should observe the compilation of sample_threadx.c (which is the demonstration +You should observe the compilation of sample_threadx.c (which is the demonstration application) and linking with tx.a. The resulting file sample_threadx.out is a binary file that can be downloaded and executed on IAR's Cortex-A15 simulator. 3. System Initialization -The entry point in ThreadX for the Cortex-A15 using IAR tools is at label -?cstartup. This is defined within the IAR compiler's startup code. In -addition, this is where all static and global preset C variable +The entry point in ThreadX for the Cortex-A15 using IAR tools is at label +?cstartup. This is defined within the IAR compiler's startup code. In +addition, this is where all static and global preset C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, and a periodic timer interrupt source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. By default, the vector area is defined at the top of cstartup.s, which is -a slightly modified from the base IAR file. +a slightly modified from the base IAR file. The _tx_initialize_low_level function inside of tx_initialize_low_level.s -also determines the first available address for use by the application, which -is supplied as the sole input parameter to your application definition function, -tx_application_define. To accomplish this, a section is created in -tx_initialize_low_level.s called FREE_MEM, which must be located after all +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all other RAM sections in memory. 4. Register Usage and Stack Frames -The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are -scratch registers for each function. All other registers used by a C function -must be preserved by the function. ThreadX takes advantage of this in -situations where a context switch happens as a result of making a ThreadX -service call (which is itself a C function). In such cases, the saved +The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are +scratch registers for each function. All other registers used by a C function +must be preserved by the function. ThreadX takes advantage of this in +situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -78,12 +78,12 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 5. Conditional Compilation Switches @@ -92,146 +92,146 @@ The following are conditional compilation options for building the ThreadX libra and application: - TX_ENABLE_FIQ_SUPPORT This assembler/compiler define enables + TX_ENABLE_FIQ_SUPPORT This assembler/compiler define enables FIQ interrupt handling support in the ThreadX assembly files. If used, it should be used on all assembly files and the generic C source of - ThreadX should be compiled with + ThreadX should be compiled with TX_ENABLE_FIQ_SUPPORT defined as well. TX_ENABLE_IRQ_NESTING This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. TX_ENABLE_FIQ_NESTING This assembler define enables FIQ - nested support. If FIQ nested + nested support. If FIQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. In addition, IRQ nesting should also be enabled. TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - TX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. TX_THUMB Defined, this option enables the BX LR calling return sequence @@ -245,29 +245,29 @@ and application: 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the ThreadX library -project to enable various compiler optimizations. +project to enable various compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A15 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-A15 vectors start at address zero. The demonstration system startup -cstartup.s file contains the vectors and is loaded at address zero. -On actual hardware platforms, this area might have to be copied to address 0. +cstartup.s file contains the vectors and is loaded at address zero. +On actual hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs @@ -278,12 +278,12 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.s: PUBLIC __tx_irq_handler - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -291,7 +291,7 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -304,7 +304,7 @@ __tx_irq_processing_return 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.s: @@ -315,12 +315,12 @@ __tx_example_vectored_irq_handler ; /* Jump to context save to save system context. */ STMDB sp!, {r0-r3} ; Save some scratch registers MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers BL _tx_thread_vectored_context_save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -337,24 +337,24 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.s. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables -nesting by disabling IRQ interrupts and switching back to IRQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: RSEG .text:CODE:NOROOT(2) PUBLIC __tx_irq_handler RSEG .text:CODE:NOROOT(2) - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -362,15 +362,15 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ; BL _tx_thread_irq_nesting_start @@ -378,7 +378,7 @@ __tx_irq_processing_return ; /* Application ISR dispatch call goes here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ; BL _tx_thread_irq_nesting_end @@ -389,12 +389,12 @@ __tx_irq_processing_return 7.3 FIQ Interrupts -By default, Cortex-A15 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, Cortex-A15 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.s. @@ -403,7 +403,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.s. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.s: @@ -434,18 +434,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.s. When nested FIQ interrupts are no -longer required, calling the _tx_thread_fiq_nesting_end service disables -nesting by disabling FIQ interrupts and switching back to FIQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested FIQ interrupts are no +longer required, calling the _tx_thread_fiq_nesting_end service disables +nesting by disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -463,7 +463,7 @@ __tx_fiq_processing_return: ; interrupt, and all C scratch registers are available for use. */ ; ; /* Enable nested FIQ interrupts. NOTE: Since this service returns -; with FIQ interrupts enabled, all FIQ interrupt sources must be +; with FIQ interrupts enabled, all FIQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start ; @@ -479,22 +479,22 @@ __tx_fiq_processing_return: 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to _tx_timer_interrupt +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. 9. Thumb/Cortex-A15 Mixed Mode -By default, ThreadX is setup for running in Cortex-A15 32-bit mode. This is -also true for the demonstration system. It is possible to build any +By default, ThreadX is setup for running in Cortex-A15 32-bit mode. This is +also true for the demonstration system. It is possible to build any ThreadX file and/or the application in Thumb mode. The only exception -to this is the file tx_thread_shell_entry.c. This file must always be -built in 32-bit mode. In addition, if any Thumb code is used the entire +to this is the file tx_thread_shell_entry.c. This file must always be +built in 32-bit mode. In addition, if any Thumb code is used the entire ThreadX assembly source should be built with TX_THUMB defined. @@ -506,14 +506,14 @@ should have the following line added (if not already in place): initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application -The project options "General Options -> Library Configuration" should also have the +The project options "General Options -> Library Configuration" should also have the "Enable thread support in library" box selected. 11. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); diff --git a/ports/cortex_a15/iar/src/tx_iar.c b/ports/cortex_a15/iar/src/tx_iar.c index 158738ea..238b485e 100644 --- a/ports/cortex_a15/iar/src/tx_iar.c +++ b/ports/cortex_a15/iar/src/tx_iar.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** IAR Multithreaded Library Support */ /** */ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports/cortex_a15/iar/src/tx_thread_context_restore.s b/ports/cortex_a15/iar/src/tx_thread_context_restore.s index 64584101..d88b3e38 100644 --- a/ports/cortex_a15/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_a15/iar/src/tx_thread_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -47,47 +47,38 @@ IRQ_MODE DEFINE 0x92 ; Disable IRQ, IRQ mode ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore Cortex-A15/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-A15/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -119,13 +110,13 @@ _tx_thread_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state variable LDR r2, [r3, #0] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3, #0] ; Store the counter + STR r2, [r3, #0] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs diff --git a/ports/cortex_a15/iar/src/tx_thread_context_save.s b/ports/cortex_a15/iar/src/tx_thread_context_save.s index 09d94175..799cf55b 100644 --- a/ports/cortex_a15/iar/src/tx_thread_context_save.s +++ b/ports/cortex_a15/iar/src/tx_thread_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -37,46 +37,37 @@ ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save Cortex-A15/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-A15/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -93,7 +84,7 @@ _tx_thread_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if ; Disable FIQ interrupts #endif @@ -111,7 +102,7 @@ _tx_thread_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -127,7 +118,7 @@ _tx_thread_context_save POP {lr} ; Recover ISR lr #endif - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; __tx_thread_not_nested_save ; } @@ -141,13 +132,13 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} ; Store other registers ; ; /* Save the current stack pointer in the thread's control block. */ @@ -167,7 +158,7 @@ __tx_thread_not_nested_save POP {lr} ; Recover ISR lr #endif - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ; else @@ -177,7 +168,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit @@ -192,7 +183,7 @@ __tx_thread_idle_system_save #endif ADD sp, sp, #16 ; Recover saved registers - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ;} diff --git a/ports/cortex_a15/iar/src/tx_thread_fiq_context_restore.s b/ports/cortex_a15/iar/src/tx_thread_fiq_context_restore.s index bbbf8cf1..38259b01 100644 --- a/ports/cortex_a15/iar/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_a15/iar/src/tx_thread_fiq_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -32,7 +32,7 @@ ; SVC_MODE DEFINE 0xD3 ; SVC mode FIQ_MODE DEFINE 0xD1 ; FIQ mode -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask THUMB_MASK DEFINE 0x20 ; Thumb bit mask IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits ; @@ -48,47 +48,38 @@ IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_restore Cortex-A15/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore Cortex-A15/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the fiq interrupt context when processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* FIQ ISR Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) @@ -116,13 +107,13 @@ _tx_thread_fiq_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state variable LDR r2, [r3, #0] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3, #0] ; Store the counter + STR r2, [r3, #0] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -223,7 +214,7 @@ _tx_skip_fiq_vfp_save BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it ; ; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; -; _tx_timer_time_slice = 0; +; _tx_timer_time_slice = 0; ; STR r2, [r0, #24] ; Save thread's time-slice MOV r2, #0 ; Clear value diff --git a/ports/cortex_a15/iar/src/tx_thread_fiq_context_save.s b/ports/cortex_a15/iar/src/tx_thread_fiq_context_save.s index b8828834..8e205668 100644 --- a/ports/cortex_a15/iar/src/tx_thread_fiq_context_save.s +++ b/ports/cortex_a15/iar/src/tx_thread_fiq_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,46 +36,37 @@ ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_save Cortex-A15/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save Cortex-A15/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) @@ -92,7 +83,7 @@ _tx_thread_fiq_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers LDR r3, =_tx_thread_system_state ; Pickup address of system state variable LDR r2, [r3, #0] ; Pickup system state CMP r2, #0 ; Is this the first interrupt? @@ -107,7 +98,7 @@ _tx_thread_fiq_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -123,38 +114,38 @@ _tx_thread_fiq_context_save POP {lr} ; Recover ISR lr #endif - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; __tx_thread_fiq_not_nested_save -; } +; } ; ; /* Otherwise, not nested, check to see if a thread was running. */ ; else if (_tx_thread_current_ptr) -; { +; { ; ADD r2, r2, #1 ; Increment the interrupt counter STR r2, [r3, #0] ; Store it back in the variable LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in -; ; scheduling loop - nothing needs saving! + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, lr} ; Store other registers, Note that we don't -; ; need to save sl and ip since FIQ has -; ; copies of these registers. Nested +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested ; ; interrupt processing does need to save ; ; these registers. ; ; /* Save the current stack pointer in the thread's control block. */ -; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; ; ; /* Switch to the system stack. */ -; sp = _tx_thread_system_stack_ptr; +; sp = _tx_thread_system_stack_ptr; ; MOV r10, #0 ; Clear stack limit @@ -167,7 +158,7 @@ __tx_thread_fiq_not_nested_save POP {lr} ; Recover ISR lr #endif - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } ; else @@ -187,18 +178,18 @@ __tx_thread_fiq_idle_system_save #endif ; ; /* Not much to do here, save the current SPSR and LR for possible -; use in IRQ interrupted in idle system conditions, and return to +; use in IRQ interrupted in idle system conditions, and return to ; FIQ interrupt processing. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, lr} ; Store other registers that will get used -; ; or stripped off the stack in context -; ; restore - B __tx_fiq_processing_return ; Continue FIQ processing +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } -;} +;} END diff --git a/ports/cortex_a15/iar/src/tx_thread_fiq_nesting_end.s b/ports/cortex_a15/iar/src/tx_thread_fiq_nesting_end.s index f8a73cbc..272bb745 100644 --- a/ports/cortex_a15/iar/src/tx_thread_fiq_nesting_end.s +++ b/ports/cortex_a15/iar/src/tx_thread_fiq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,56 +34,50 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ/FIQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_end Cortex-A15/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end Cortex-A15/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ -;/* processing from system mode back to FIQ mode prior to the ISR */ -;/* calling _tx_thread_fiq_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with FIQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) @@ -96,7 +90,7 @@ _tx_thread_fiq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_c, r0 ; Disable interrupts - LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports/cortex_a15/iar/src/tx_thread_fiq_nesting_start.s b/ports/cortex_a15/iar/src/tx_thread_fiq_nesting_start.s index 497d7421..afa1ae05 100644 --- a/ports/cortex_a15/iar/src/tx_thread_fiq_nesting_start.s +++ b/ports/cortex_a15/iar/src/tx_thread_fiq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ SYS_MODE_BITS DEFINE 0x1F ; System mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_start Cortex-A15/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start Cortex-A15/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ -;/* processing to the system mode so nested FIQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with FIQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_a15/iar/src/tx_thread_interrupt_control.s b/ports/cortex_a15/iar/src/tx_thread_interrupt_control.s index ce9d08a7..c7432fcb 100644 --- a/ports/cortex_a15/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_a15/iar/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -30,42 +30,36 @@ INT_MASK = 0x03F -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control Cortex-A15/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-A15/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a15/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_a15/iar/src/tx_thread_interrupt_disable.s index 19c70c89..97b13aab 100644 --- a/ports/cortex_a15/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_a15/iar/src/tx_thread_interrupt_disable.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -27,41 +27,35 @@ ;#include "tx_api.h" ;#include "tx_thread.h" ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable Cortex-A15/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-A15/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(void) @@ -80,7 +74,7 @@ _tx_thread_interrupt_disable #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if ; Disable IRQ and FIQ #else - CPSID i ; Disable IRQ + CPSID i ; Disable IRQ #endif #ifdef TX_THUMB diff --git a/ports/cortex_a15/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_a15/iar/src/tx_thread_interrupt_restore.s index 70c949b3..b2765483 100644 --- a/ports/cortex_a15/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_a15/iar/src/tx_thread_interrupt_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -27,42 +27,36 @@ ;#include "tx_api.h" ;#include "tx_thread.h" ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore Cortex-A15/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-A15/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function is responsible for restoring interrupts to the state */ ;/* returned by a previous _tx_thread_interrupt_disable call. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a15/iar/src/tx_thread_irq_nesting_end.s b/ports/cortex_a15/iar/src/tx_thread_irq_nesting_end.s index f1662aba..33c018f4 100644 --- a/ports/cortex_a15/iar/src/tx_thread_irq_nesting_end.s +++ b/ports/cortex_a15/iar/src/tx_thread_irq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,56 +34,50 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ/FIQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_end Cortex-A15/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-A15/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -;/* processing from system mode back to IRQ mode prior to the ISR */ -;/* calling _tx_thread_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) @@ -96,7 +90,7 @@ _tx_thread_irq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_c, r0 ; Disable interrupts - LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports/cortex_a15/iar/src/tx_thread_irq_nesting_start.s b/ports/cortex_a15/iar/src/tx_thread_irq_nesting_start.s index 21151129..0cc03356 100644 --- a/ports/cortex_a15/iar/src/tx_thread_irq_nesting_start.s +++ b/ports/cortex_a15/iar/src/tx_thread_irq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ SYS_MODE_BITS DEFINE 0x1F ; System mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_start Cortex-A15/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-A15/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_context_save has been called and switches the IRQ */ -;/* processing to the system mode so nested IRQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_a15/iar/src/tx_thread_schedule.s b/ports/cortex_a15/iar/src/tx_thread_schedule.s index 0d2fd007..2a36cc42 100644 --- a/ports/cortex_a15/iar/src/tx_thread_schedule.s +++ b/ports/cortex_a15/iar/src/tx_thread_schedule.s @@ -1,19 +1,19 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors -; * +; * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,48 +36,39 @@ EXTERN _tx_timer_time_slice EXTERN _tx_execution_thread_enter ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule Cortex-A15/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-A15/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -108,7 +99,7 @@ __tx_thread_schedule_loop ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Lockout interrupts and ; transfer control to it. */ ; @@ -121,7 +112,7 @@ __tx_thread_schedule_loop ; /* Setup the current thread pointer. */ ; _tx_thread_current_ptr = _tx_thread_execute_ptr; ; - LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread STR r0, [r1, #0] ; Setup current thread pointer ; ; /* Increment the run count for this thread. */ @@ -135,7 +126,7 @@ __tx_thread_schedule_loop ; /* Setup time-slice, if present. */ ; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; ; - LDR r2, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r2, =_tx_timer_time_slice ; Pickup address of time-slice ; variable LDR sp, [r0, #8] ; Switch stack pointers STR r3, [r2, #0] ; Setup time-slice diff --git a/ports/cortex_a15/iar/src/tx_thread_stack_build.s b/ports/cortex_a15/iar/src/tx_thread_stack_build.s index 141a49bd..bfde0340 100644 --- a/ports/cortex_a15/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_a15/iar/src/tx_thread_stack_build.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -38,44 +38,38 @@ CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ interrupts ena EXTERN _tx_thread_schedule ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build Cortex-A15/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-A15/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function builds a stack frame on the supplied thread's stack. */ ;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ ;/* thread_ptr Pointer to thread control blk */ ;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -85,10 +79,10 @@ CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ interrupts ena CODE32 _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-A15 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; a1 (r0) Initial value for a1 diff --git a/ports/cortex_a15/iar/src/tx_thread_system_return.s b/ports/cortex_a15/iar/src/tx_thread_system_return.s index 3a1d2ba6..bd58b76c 100644 --- a/ports/cortex_a15/iar/src/tx_thread_system_return.s +++ b/ports/cortex_a15/iar/src/tx_thread_system_return.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,47 +36,38 @@ EXTERN _tx_execution_thread_exit ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return Cortex-A15/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-A15/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -92,7 +83,7 @@ _tx_thread_system_return LDR r4, =_tx_thread_current_ptr ; Pickup address of current ptr LDR r5, [r4, #0] ; Pickup current thread pointer - + #ifdef __ARMVFP__ LDR r1, [r5, #144] ; Pickup the VFP enabled flag CMP r1, #0 ; Is the VFP enabled? @@ -107,7 +98,7 @@ _tx_skip_solicited_vfp_save MOV r0, #0 ; Build a solicited stack type MRS r1, CPSR ; Pickup the CPSR STMDB sp!, {r0-r1} ; Save type and CPSR -; +; ; /* Lockout interrupts. */ ; #ifdef TX_ENABLE_FIQ_SUPPORT @@ -115,7 +106,7 @@ _tx_skip_solicited_vfp_save #else CPSID i ; Disable IRQ interrupts #endif - + #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) ; ; /* Call the thread exit function to indicate the thread is no longer executing. */ diff --git a/ports/cortex_a15/iar/src/tx_thread_vectored_context_save.s b/ports/cortex_a15/iar/src/tx_thread_vectored_context_save.s index 8d05bd80..67ffb6cd 100644 --- a/ports/cortex_a15/iar/src/tx_thread_vectored_context_save.s +++ b/ports/cortex_a15/iar/src/tx_thread_vectored_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,46 +36,37 @@ ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_vectored_context_save Cortex-A15/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-A15/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) @@ -134,7 +125,7 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Note: Minimal context of interrupted thread is already saved. */ @@ -166,7 +157,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports/cortex_a15/iar/src/tx_timer_interrupt.s b/ports/cortex_a15/iar/src/tx_timer_interrupt.s index 9a37d02a..b013cadd 100644 --- a/ports/cortex_a15/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_a15/iar/src/tx_timer_interrupt.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -43,46 +43,40 @@ EXTERN _tx_thread_time_slice ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt Cortex-A15/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-A15/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -108,7 +102,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CMP r2, #0 ; Is it non-active? BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing @@ -226,7 +220,7 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup address of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup address of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CMP r2, #0 ; See if the flag is set BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing diff --git a/ports/cortex_a17/ac6/example_build/sample_threadx/.cproject b/ports/cortex_a17/ac6/example_build/sample_threadx/.cproject index 6eef9a7b..80b9670c 100644 --- a/ports/cortex_a17/ac6/example_build/sample_threadx/.cproject +++ b/ports/cortex_a17/ac6/example_build/sample_threadx/.cproject @@ -1,176 +1,176 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a17/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_a17/ac6/example_build/sample_threadx/sample_threadx.scat index d23881cd..66d0d95a 100644 --- a/ports/cortex_a17/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports/cortex_a17/ac6/example_build/sample_threadx/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports/cortex_a17/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_a17/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 083a57a7..76395459 100644 --- a/ports/cortex_a17/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_a17/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -91,14 +92,6 @@ $_tx_initialize_low_level: /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ .global _tx_initialize_low_level .type _tx_initialize_low_level,function diff --git a/ports/cortex_a17/ac6/example_build/tx/.cproject b/ports/cortex_a17/ac6/example_build/tx/.cproject index 93fc2931..89a6951a 100644 --- a/ports/cortex_a17/ac6/example_build/tx/.cproject +++ b/ports/cortex_a17/ac6/example_build/tx/.cproject @@ -1,146 +1,146 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a17/ac6/inc/tx_port.h b/ports/cortex_a17/ac6/inc/tx_port.h index f9b96956..f0153046 100644 --- a/ports/cortex_a17/ac6/inc/tx_port.h +++ b/ports/cortex_a17/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,20 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Updated comments, removed */ -/* unneeded temp variable, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -320,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv7-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a17/ac6/src/tx_thread_context_restore.S b/ports/cortex_a17/ac6/src/tx_thread_context_restore.S index 6b4a561d..41b0b0d0 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a17/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,23 +80,6 @@ IRQ_MODE = 0x12 // IRQ mode /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_restore .type _tx_thread_context_restore,function diff --git a/ports/cortex_a17/ac6/src/tx_thread_context_save.S b/ports/cortex_a17/ac6/src/tx_thread_context_save.S index eff06283..d2d29d34 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a17/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,23 +72,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_save .type _tx_thread_context_save,function diff --git a/ports/cortex_a17/ac6/src/tx_thread_fiq_context_restore.S b/ports/cortex_a17/ac6/src/tx_thread_fiq_context_restore.S index d2fbebe1..921c322c 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a17/ac6/src/tx_thread_fiq_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -78,20 +79,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* FIQ ISR Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_restore .type _tx_thread_fiq_context_restore,function diff --git a/ports/cortex_a17/ac6/src/tx_thread_fiq_context_save.S b/ports/cortex_a17/ac6/src/tx_thread_fiq_context_save.S index 88472a3d..2f1a6c40 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a17/ac6/src/tx_thread_fiq_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_save .type _tx_thread_fiq_context_save,function diff --git a/ports/cortex_a17/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a17/ac6/src/tx_thread_fiq_nesting_end.S index fa3886b8..a7ce701e 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a17/ac6/src/tx_thread_fiq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a17/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a17/ac6/src/tx_thread_fiq_nesting_start.S index dbed1cf2..4f095dde 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a17/ac6/src/tx_thread_fiq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a17/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a17/ac6/src/tx_thread_interrupt_control.S index d1223cb8..a5bc47f7 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a17/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,20 +69,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a17/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a17/ac6/src/tx_thread_interrupt_disable.S index a87d1a06..d7b53bc2 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a17/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,20 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a17/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a17/ac6/src/tx_thread_interrupt_restore.S index 53ff2813..3c31e94b 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a17/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,20 +68,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a17/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_a17/ac6/src/tx_thread_irq_nesting_end.S index 18aebc7c..cc4db3a7 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a17/ac6/src/tx_thread_irq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a17/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_a17/ac6/src/tx_thread_irq_nesting_start.S index a2ffd35d..3635874d 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a17/ac6/src/tx_thread_irq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a17/ac6/src/tx_thread_schedule.S b/ports/cortex_a17/ac6/src/tx_thread_schedule.S index f46a339b..a74e2050 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a17/ac6/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,23 +82,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a17/ac6/src/tx_thread_stack_build.S b/ports/cortex_a17/ac6/src/tx_thread_stack_build.S index 3876225a..827554a7 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a17/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,20 +75,6 @@ CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ int /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a17/ac6/src/tx_thread_system_return.S b/ports/cortex_a17/ac6/src/tx_thread_system_return.S index 0eed478d..1a17446b 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a17/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,23 +69,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a17/ac6/src/tx_thread_vectored_context_save.S b/ports/cortex_a17/ac6/src/tx_thread_vectored_context_save.S index fe8a98e8..91653b75 100644 --- a/ports/cortex_a17/ac6/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a17/ac6/src/tx_thread_vectored_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_vectored_context_save .type _tx_thread_vectored_context_save,function diff --git a/ports/cortex_a17/ac6/src/tx_timer_interrupt.S b/ports/cortex_a17/ac6/src/tx_timer_interrupt.S index cb0c1fa2..179ac894 100644 --- a/ports/cortex_a17/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a17/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -77,20 +78,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a17/gnu/example_build/reset.S b/ports/cortex_a17/gnu/example_build/reset.S index 3ce9efb7..f2e0522b 100644 --- a/ports/cortex_a17/gnu/example_build/reset.S +++ b/ports/cortex_a17/gnu/example_build/reset.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a17/gnu/example_build/sample_threadx.ld b/ports/cortex_a17/gnu/example_build/sample_threadx.ld index cb42c11c..d43e28f1 100644 --- a/ports/cortex_a17/gnu/example_build/sample_threadx.ld +++ b/ports/cortex_a17/gnu/example_build/sample_threadx.ld @@ -7,7 +7,7 @@ OUTPUT_ARCH(arm) SECTIONS { . = 0x00000000; - + .vectors : {reset.o(.text) } /* Read-only sections, merged into text segment: */ @@ -94,8 +94,8 @@ SECTIONS *(.gnu.linkonce.t*) *(.glue_7t) *(.glue_7) } =0 - .init : - { + .init : + { KEEP (*(.init)) } =0 _etext = .; @@ -120,7 +120,7 @@ SECTIONS .data1 : { *(.data1) } .eh_frame : { KEEP (*(.eh_frame)) } .gcc_except_table : { *(.gcc_except_table) } - .ctors : + .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is @@ -153,9 +153,9 @@ SECTIONS /* We want the small data sections together, so single-instruction offsets can access them all, and initialized data all before uninitialized, so we can shorten the on-disk segment size. */ - .sdata : + .sdata : { - *(.sdata) + *(.sdata) *(.sdata.*) *(.gnu.linkonce.s.*) } @@ -191,7 +191,7 @@ SECTIONS _stack_bottom = ABSOLUTE(.) ; - /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and + /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and SYS stack if nested interrupts are enabled. */ . = ALIGN(8) ; . += 4096 ; diff --git a/ports/cortex_a17/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_a17/gnu/example_build/tx_initialize_low_level.S index 88777dfd..f9a57216 100644 --- a/ports/cortex_a17/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_a17/gnu/example_build/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -95,17 +96,6 @@ $_tx_initialize_low_level: /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_initialize_low_level .type _tx_initialize_low_level,function diff --git a/ports/cortex_a17/gnu/example_build/v7.h b/ports/cortex_a17/gnu/example_build/v7.h index 5a08b43f..c18b945c 100644 --- a/ports/cortex_a17/gnu/example_build/v7.h +++ b/ports/cortex_a17/gnu/example_build/v7.h @@ -4,7 +4,7 @@ // // Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports/cortex_a17/gnu/example_build/v7.s b/ports/cortex_a17/gnu/example_build/v7.s index 82c9ab1e..9487ddde 100644 --- a/ports/cortex_a17/gnu/example_build/v7.s +++ b/ports/cortex_a17/gnu/example_build/v7.s @@ -3,7 +3,7 @@ // // Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ @@ -20,7 +20,7 @@ enableInterrupts: CPSIE i BX lr - + .global disableInterrupts .type disableInterrupts,function @@ -28,7 +28,7 @@ enableInterrupts: disableInterrupts: CPSID i BX lr - + // ------------------------------------------------------------ // Cache Maintenance @@ -44,7 +44,7 @@ enableCaches: MCR p15, 0, r0, c1, c0, 0 // Write System Control Register ISB BX lr - + .global disableCaches @@ -57,7 +57,7 @@ disableCaches: MCR p15, 0, r0, c1, c0, 0 // Write System Control Register ISB BX lr - + .global cleanDCache @@ -114,7 +114,7 @@ clean_dcache_finished: POP {r4-r12} BX lr - + .global cleanInvalidateDCache .type cleanInvalidateDCache,function @@ -170,7 +170,7 @@ clean_invalidate_dcache_finished: POP {r4-r12} BX lr - + .global invalidateCaches @@ -229,7 +229,7 @@ invalidate_caches_skip: invalidate_caches_finished: POP {r4-r12} BX lr - + .global invalidateCaches_IS @@ -284,7 +284,7 @@ invalidate_caches_is_skip: invalidate_caches_is_finished: POP {r4-r12} BX lr - + // ------------------------------------------------------------ // TLB @@ -297,7 +297,7 @@ invalidateUnifiedTLB: MOV r0, #0 MCR p15, 0, r0, c8, c7, 0 // TLBIALL - Invalidate entire unified TLB BX lr - + .global invalidateUnifiedTLB_IS .type invalidateUnifiedTLB_IS,function @@ -306,7 +306,7 @@ invalidateUnifiedTLB_IS: MOV r0, #1 MCR p15, 0, r0, c8, c3, 0 // TLBIALLIS - Invalidate entire unified TLB Inner Shareable BX lr - + // ------------------------------------------------------------ // Branch Prediction @@ -319,7 +319,7 @@ flushBranchTargetCache: MOV r0, #0 MCR p15, 0, r0, c7, c5, 6 // BPIALL - Invalidate entire branch predictor array BX lr - + .global flushBranchTargetCache_IS .type flushBranchTargetCache_IS,function @@ -328,7 +328,7 @@ flushBranchTargetCache_IS: MOV r0, #0 MCR p15, 0, r0, c7, c1, 6 // BPIALLIS - Invalidate entire branch predictor array Inner Shareable BX lr - + // ------------------------------------------------------------ // High Vecs @@ -343,7 +343,7 @@ enableHighVecs: MCR p15, 0, r0, c1, c0, 0 // Write Control Register ISB BX lr - + .global disableHighVecs .type disableHighVecs,function @@ -354,7 +354,7 @@ disableHighVecs: MCR p15, 0, r0, c1, c0, 0 // Write Control Register ISB BX lr - + // ------------------------------------------------------------ // Context ID @@ -366,7 +366,7 @@ disableHighVecs: getContextID: MRC p15, 0, r0, c13, c0, 1 // Read Context ID Register BX lr - + .global setContextID .type setContextID,function @@ -374,7 +374,7 @@ getContextID: setContextID: MCR p15, 0, r0, c13, c0, 1 // Write Context ID Register BX lr - + // ------------------------------------------------------------ // ID registers @@ -386,7 +386,7 @@ setContextID: getMIDR: MRC p15, 0, r0, c0, c0, 0 // Read Main ID Register (MIDR) BX lr - + .global getMPIDR .type getMPIDR,function @@ -394,7 +394,7 @@ getMIDR: getMPIDR: MRC p15, 0, r0, c0 ,c0, 5// Read Multiprocessor ID register (MPIDR) BX lr - + // ------------------------------------------------------------ // CP15 SMP related @@ -407,7 +407,7 @@ getMPIDR: getBaseAddr: MRC p15, 4, r0, c15, c0, 0 // Read peripheral base address BX lr - + // ------------------------------------------------------------ @@ -419,7 +419,7 @@ getCPUID: MRC p15, 0, r0, c0, c0, 5 // Read CPU ID register AND r0, r0, #0x03 // Mask off, leaving the CPU ID field BX lr - + // ------------------------------------------------------------ @@ -431,7 +431,7 @@ goToSleep: WFI // Go into standby B goToSleep // Catch in case of rogue events BX lr - + // ------------------------------------------------------------ @@ -451,7 +451,7 @@ joinSMP: ISB BX lr - + // ------------------------------------------------------------ @@ -469,7 +469,7 @@ leaveSMP: ISB BX lr - + // ------------------------------------------------------------ // End of v7.s diff --git a/ports/cortex_a17/gnu/inc/tx_port.h b/ports/cortex_a17/gnu/inc/tx_port.h index f9b96956..f0153046 100644 --- a/ports/cortex_a17/gnu/inc/tx_port.h +++ b/ports/cortex_a17/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,20 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Updated comments, removed */ -/* unneeded temp variable, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -320,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv7-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a17/gnu/src/tx_thread_context_restore.S b/ports/cortex_a17/gnu/src/tx_thread_context_restore.S index 6b4a561d..41b0b0d0 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a17/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,23 +80,6 @@ IRQ_MODE = 0x12 // IRQ mode /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_restore .type _tx_thread_context_restore,function diff --git a/ports/cortex_a17/gnu/src/tx_thread_context_save.S b/ports/cortex_a17/gnu/src/tx_thread_context_save.S index eff06283..d2d29d34 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a17/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,23 +72,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_save .type _tx_thread_context_save,function diff --git a/ports/cortex_a17/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_a17/gnu/src/tx_thread_fiq_context_restore.S index d2fbebe1..921c322c 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a17/gnu/src/tx_thread_fiq_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -78,20 +79,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* FIQ ISR Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_restore .type _tx_thread_fiq_context_restore,function diff --git a/ports/cortex_a17/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_a17/gnu/src/tx_thread_fiq_context_save.S index 88472a3d..2f1a6c40 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a17/gnu/src/tx_thread_fiq_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_save .type _tx_thread_fiq_context_save,function diff --git a/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_end.S index fa3886b8..a7ce701e 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_start.S index dbed1cf2..4f095dde 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a17/gnu/src/tx_thread_fiq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a17/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a17/gnu/src/tx_thread_interrupt_control.S index d1223cb8..a5bc47f7 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a17/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,20 +69,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a17/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a17/gnu/src/tx_thread_interrupt_disable.S index a87d1a06..d7b53bc2 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a17/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,20 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a17/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a17/gnu/src/tx_thread_interrupt_restore.S index 53ff2813..3c31e94b 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a17/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,20 +68,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_end.S index 18aebc7c..cc4db3a7 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_start.S index a2ffd35d..3635874d 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a17/gnu/src/tx_thread_irq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a17/gnu/src/tx_thread_schedule.S b/ports/cortex_a17/gnu/src/tx_thread_schedule.S index f46a339b..a74e2050 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a17/gnu/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,23 +82,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a17/gnu/src/tx_thread_stack_build.S b/ports/cortex_a17/gnu/src/tx_thread_stack_build.S index 3876225a..827554a7 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a17/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,20 +75,6 @@ CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ int /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a17/gnu/src/tx_thread_system_return.S b/ports/cortex_a17/gnu/src/tx_thread_system_return.S index 0eed478d..1a17446b 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a17/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,23 +69,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a17/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_a17/gnu/src/tx_thread_vectored_context_save.S index fe8a98e8..91653b75 100644 --- a/ports/cortex_a17/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a17/gnu/src/tx_thread_vectored_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_vectored_context_save .type _tx_thread_vectored_context_save,function diff --git a/ports/cortex_a17/gnu/src/tx_timer_interrupt.S b/ports/cortex_a17/gnu/src/tx_timer_interrupt.S index cb0c1fa2..179ac894 100644 --- a/ports/cortex_a17/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a17/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -77,20 +78,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a34/ac6/example_build/sample_threadx/.cproject b/ports/cortex_a34/ac6/example_build/sample_threadx/.cproject index 587034cd..7310f92f 100644 --- a/ports/cortex_a34/ac6/example_build/sample_threadx/.cproject +++ b/ports/cortex_a34/ac6/example_build/sample_threadx/.cproject @@ -1,158 +1,158 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a34/ac6/example_build/sample_threadx/GICv3.h b/ports/cortex_a34/ac6/example_build/sample_threadx/GICv3.h index 23bc7fd8..dfe37586 100644 --- a/ports/cortex_a34/ac6/example_build/sample_threadx/GICv3.h +++ b/ports/cortex_a34/ac6/example_build/sample_threadx/GICv3.h @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef GICV3_h diff --git a/ports/cortex_a34/ac6/example_build/sample_threadx/GICv3_gicc.h b/ports/cortex_a34/ac6/example_build/sample_threadx/GICv3_gicc.h index 8e6f0acc..beaa9157 100644 --- a/ports/cortex_a34/ac6/example_build/sample_threadx/GICv3_gicc.h +++ b/ports/cortex_a34/ac6/example_build/sample_threadx/GICv3_gicc.h @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef GICV3_gicc_h diff --git a/ports/cortex_a34/ac6/example_build/sample_threadx/GICv3_gicd.c b/ports/cortex_a34/ac6/example_build/sample_threadx/GICv3_gicd.c index 3bfb4a93..2cf1553b 100644 --- a/ports/cortex_a34/ac6/example_build/sample_threadx/GICv3_gicd.c +++ b/ports/cortex_a34/ac6/example_build/sample_threadx/GICv3_gicd.c @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #include diff --git a/ports/cortex_a34/ac6/example_build/sample_threadx/GICv3_gicr.c b/ports/cortex_a34/ac6/example_build/sample_threadx/GICv3_gicr.c index 7b437b18..912ab2e4 100644 --- a/ports/cortex_a34/ac6/example_build/sample_threadx/GICv3_gicr.c +++ b/ports/cortex_a34/ac6/example_build/sample_threadx/GICv3_gicr.c @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #include "GICv3.h" diff --git a/ports/cortex_a34/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports/cortex_a34/ac6/example_build/sample_threadx/MP_Mutexes.S index e7f95aa7..e8a87f0b 100644 --- a/ports/cortex_a34/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports/cortex_a34/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -4,7 +4,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports/cortex_a34/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports/cortex_a34/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports/cortex_a34/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports/cortex_a34/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports/cortex_a34/ac6/example_build/sample_threadx/PPM_AEM.h b/ports/cortex_a34/ac6/example_build/sample_threadx/PPM_AEM.h index 52c9a0fe..f7501eeb 100644 --- a/ports/cortex_a34/ac6/example_build/sample_threadx/PPM_AEM.h +++ b/ports/cortex_a34/ac6/example_build/sample_threadx/PPM_AEM.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports/cortex_a34/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_a34/ac6/example_build/sample_threadx/sample_threadx.scat index e5783c7c..d8dfde69 100644 --- a/ports/cortex_a34/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports/cortex_a34/ac6/example_build/sample_threadx/sample_threadx.scat @@ -2,7 +2,7 @@ ; Scatter file for Armv8-A Startup code on FVP Base model ; Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************** @@ -25,7 +25,7 @@ LOAD 0x80000000 ; in source code for this to work correctly ; ARM_LIB_HEAP +0 ALIGN 64 EMPTY 0xA0000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary diff --git a/ports/cortex_a34/ac6/example_build/sample_threadx/sp804_timer.c b/ports/cortex_a34/ac6/example_build/sample_threadx/sp804_timer.c index 4dc009b2..c2ce6faa 100644 --- a/ports/cortex_a34/ac6/example_build/sample_threadx/sp804_timer.c +++ b/ports/cortex_a34/ac6/example_build/sample_threadx/sp804_timer.c @@ -3,7 +3,7 @@ // // Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports/cortex_a34/ac6/example_build/sample_threadx/sp804_timer.h b/ports/cortex_a34/ac6/example_build/sample_threadx/sp804_timer.h index 777062cc..4d423904 100644 --- a/ports/cortex_a34/ac6/example_build/sample_threadx/sp804_timer.h +++ b/ports/cortex_a34/ac6/example_build/sample_threadx/sp804_timer.h @@ -4,7 +4,7 @@ // // Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports/cortex_a34/ac6/example_build/sample_threadx/startup.S b/ports/cortex_a34/ac6/example_build/sample_threadx/startup.S index de100e56..9f0fc211 100644 --- a/ports/cortex_a34/ac6/example_build/sample_threadx/startup.S +++ b/ports/cortex_a34/ac6/example_build/sample_threadx/startup.S @@ -7,7 +7,7 @@ // // Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ @@ -328,7 +328,7 @@ el1_entry_aarch64: // // Cortex-A processors automatically invalidate their caches on reset // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). - // It is therefore not necessary for software to invalidate the caches + // It is therefore not necessary for software to invalidate the caches // on startup, however, this is done here in case of a warm reset. bl InvalidateUDCaches tlbi VMALLE1 diff --git a/ports/cortex_a34/ac6/example_build/sample_threadx/v8_aarch64.S b/ports/cortex_a34/ac6/example_build/sample_threadx/v8_aarch64.S index f8db3bfe..45445a98 100644 --- a/ports/cortex_a34/ac6/example_build/sample_threadx/v8_aarch64.S +++ b/ports/cortex_a34/ac6/example_build/sample_threadx/v8_aarch64.S @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports/cortex_a34/ac6/example_build/sample_threadx/v8_aarch64.h b/ports/cortex_a34/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports/cortex_a34/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports/cortex_a34/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_a34/ac6/example_build/sample_threadx/v8_mmu.h b/ports/cortex_a34/ac6/example_build/sample_threadx/v8_mmu.h index ee8834fa..d0c51601 100644 --- a/ports/cortex_a34/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports/cortex_a34/ac6/example_build/sample_threadx/v8_mmu.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports/cortex_a34/ac6/example_build/sample_threadx/v8_system.h b/ports/cortex_a34/ac6/example_build/sample_threadx/v8_system.h index ff96deff..a62d2a33 100644 --- a/ports/cortex_a34/ac6/example_build/sample_threadx/v8_system.h +++ b/ports/cortex_a34/ac6/example_build/sample_threadx/v8_system.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports/cortex_a34/ac6/example_build/sample_threadx/v8_utils.S b/ports/cortex_a34/ac6/example_build/sample_threadx/v8_utils.S index f0fcef26..888892a0 100644 --- a/ports/cortex_a34/ac6/example_build/sample_threadx/v8_utils.S +++ b/ports/cortex_a34/ac6/example_build/sample_threadx/v8_utils.S @@ -3,7 +3,7 @@ // // Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports/cortex_a34/ac6/example_build/sample_threadx/vectors.S b/ports/cortex_a34/ac6/example_build/sample_threadx/vectors.S index 9e60e001..7784f98e 100644 --- a/ports/cortex_a34/ac6/example_build/sample_threadx/vectors.S +++ b/ports/cortex_a34/ac6/example_build/sample_threadx/vectors.S @@ -3,7 +3,7 @@ // // Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports/cortex_a34/ac6/example_build/tx/.cproject b/ports/cortex_a34/ac6/example_build/tx/.cproject index 21675fd6..a7e80321 100644 --- a/ports/cortex_a34/ac6/example_build/tx/.cproject +++ b/ports/cortex_a34/ac6/example_build/tx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a34/ac6/inc/tx_port.h b/ports/cortex_a34/ac6/inc/tx_port.h index a8d3fd48..e5352338 100644 --- a/ports/cortex_a34/ac6/inc/tx_port.h +++ b/ports/cortex_a34/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -369,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a34/ac6/src/tx_initialize_low_level.S b/ports/cortex_a34/ac6/src/tx_initialize_low_level.S index da9e9467..55bcfaa8 100644 --- a/ports/cortex_a34/ac6/src/tx_initialize_low_level.S +++ b/ports/cortex_a34/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports/cortex_a34/ac6/src/tx_thread_context_restore.S b/ports/cortex_a34/ac6/src/tx_thread_context_restore.S index e5357e5c..3870de0d 100644 --- a/ports/cortex_a34/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a34/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_a34/ac6/src/tx_thread_context_save.S b/ports/cortex_a34/ac6/src/tx_thread_context_save.S index d292cce7..8bc7e21b 100644 --- a/ports/cortex_a34/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a34/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_a34/ac6/src/tx_thread_fp_disable.c b/ports/cortex_a34/ac6/src/tx_thread_fp_disable.c index cccf96c8..c69f6de5 100644 --- a/ports/cortex_a34/ac6/src/tx_thread_fp_disable.c +++ b/ports/cortex_a34/ac6/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports/cortex_a34/ac6/src/tx_thread_fp_enable.c b/ports/cortex_a34/ac6/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports/cortex_a34/ac6/src/tx_thread_fp_enable.c +++ b/ports/cortex_a34/ac6/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports/cortex_a34/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a34/ac6/src/tx_thread_interrupt_control.S index efc10724..d4235180 100644 --- a/ports/cortex_a34/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a34/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_a34/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a34/ac6/src/tx_thread_interrupt_disable.S index 508562ff..08f0e7e1 100644 --- a/ports/cortex_a34/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a34/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,14 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports/cortex_a34/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a34/ac6/src/tx_thread_interrupt_restore.S index 3572c1a2..69a859da 100644 --- a/ports/cortex_a34/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a34/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports/cortex_a34/ac6/src/tx_thread_schedule.S b/ports/cortex_a34/ac6/src/tx_thread_schedule.S index 8dcc8220..4d3763eb 100644 --- a/ports/cortex_a34/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a34/ac6/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +57,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_a34/ac6/src/tx_thread_stack_build.S b/ports/cortex_a34/ac6/src/tx_thread_stack_build.S index 9cd954f5..d1002b2c 100644 --- a/ports/cortex_a34/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a34/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,14 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_a34/ac6/src/tx_thread_system_return.S b/ports/cortex_a34/ac6/src/tx_thread_system_return.S index 0ec7cdb5..112e1454 100644 --- a/ports/cortex_a34/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a34/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_a34/ac6/src/tx_timer_interrupt.S b/ports/cortex_a34/ac6/src/tx_timer_interrupt.S index 92bdef3d..ac61450b 100644 --- a/ports/cortex_a34/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a34/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,12 +58,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_a34/gnu/example_build/sample_threadx/.cproject b/ports/cortex_a34/gnu/example_build/sample_threadx/.cproject index d801e51a..eae50159 100644 --- a/ports/cortex_a34/gnu/example_build/sample_threadx/.cproject +++ b/ports/cortex_a34/gnu/example_build/sample_threadx/.cproject @@ -1,242 +1,242 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a34/gnu/example_build/sample_threadx/GICv3.h b/ports/cortex_a34/gnu/example_build/sample_threadx/GICv3.h index 23bc7fd8..dfe37586 100644 --- a/ports/cortex_a34/gnu/example_build/sample_threadx/GICv3.h +++ b/ports/cortex_a34/gnu/example_build/sample_threadx/GICv3.h @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef GICV3_h diff --git a/ports/cortex_a34/gnu/example_build/sample_threadx/GICv3_aliases.h b/ports/cortex_a34/gnu/example_build/sample_threadx/GICv3_aliases.h index 0928d14c..826ba973 100644 --- a/ports/cortex_a34/gnu/example_build/sample_threadx/GICv3_aliases.h +++ b/ports/cortex_a34/gnu/example_build/sample_threadx/GICv3_aliases.h @@ -3,7 +3,7 @@ // // Copyright (c) 2016-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports/cortex_a34/gnu/example_build/sample_threadx/GICv3_gicc.h b/ports/cortex_a34/gnu/example_build/sample_threadx/GICv3_gicc.h index 2b8a2d3e..998d92b5 100644 --- a/ports/cortex_a34/gnu/example_build/sample_threadx/GICv3_gicc.h +++ b/ports/cortex_a34/gnu/example_build/sample_threadx/GICv3_gicc.h @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef GICV3_gicc_h diff --git a/ports/cortex_a34/gnu/example_build/sample_threadx/GICv3_gicd.c b/ports/cortex_a34/gnu/example_build/sample_threadx/GICv3_gicd.c index 2cf9e843..464ecced 100644 --- a/ports/cortex_a34/gnu/example_build/sample_threadx/GICv3_gicd.c +++ b/ports/cortex_a34/gnu/example_build/sample_threadx/GICv3_gicd.c @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #include diff --git a/ports/cortex_a34/gnu/example_build/sample_threadx/GICv3_gicr.c b/ports/cortex_a34/gnu/example_build/sample_threadx/GICv3_gicr.c index b0d22c40..61addaef 100644 --- a/ports/cortex_a34/gnu/example_build/sample_threadx/GICv3_gicr.c +++ b/ports/cortex_a34/gnu/example_build/sample_threadx/GICv3_gicr.c @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #include "GICv3.h" diff --git a/ports/cortex_a34/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports/cortex_a34/gnu/example_build/sample_threadx/MP_Mutexes.S index e7f95aa7..e8a87f0b 100644 --- a/ports/cortex_a34/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports/cortex_a34/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -4,7 +4,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports/cortex_a34/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports/cortex_a34/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports/cortex_a34/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports/cortex_a34/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports/cortex_a34/gnu/example_build/sample_threadx/PPM_AEM.h b/ports/cortex_a34/gnu/example_build/sample_threadx/PPM_AEM.h index 52c9a0fe..f7501eeb 100644 --- a/ports/cortex_a34/gnu/example_build/sample_threadx/PPM_AEM.h +++ b/ports/cortex_a34/gnu/example_build/sample_threadx/PPM_AEM.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports/cortex_a34/gnu/example_build/sample_threadx/sample_threadx.ld b/ports/cortex_a34/gnu/example_build/sample_threadx/sample_threadx.ld index eec8f12b..3bf47736 100644 --- a/ports/cortex_a34/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports/cortex_a34/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start diff --git a/ports/cortex_a34/gnu/example_build/sample_threadx/sp804_timer.c b/ports/cortex_a34/gnu/example_build/sample_threadx/sp804_timer.c index 4dc009b2..c2ce6faa 100644 --- a/ports/cortex_a34/gnu/example_build/sample_threadx/sp804_timer.c +++ b/ports/cortex_a34/gnu/example_build/sample_threadx/sp804_timer.c @@ -3,7 +3,7 @@ // // Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports/cortex_a34/gnu/example_build/sample_threadx/sp804_timer.h b/ports/cortex_a34/gnu/example_build/sample_threadx/sp804_timer.h index 777062cc..4d423904 100644 --- a/ports/cortex_a34/gnu/example_build/sample_threadx/sp804_timer.h +++ b/ports/cortex_a34/gnu/example_build/sample_threadx/sp804_timer.h @@ -4,7 +4,7 @@ // // Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports/cortex_a34/gnu/example_build/sample_threadx/startup.S b/ports/cortex_a34/gnu/example_build/sample_threadx/startup.S index 67dd8a6a..b44806fe 100644 --- a/ports/cortex_a34/gnu/example_build/sample_threadx/startup.S +++ b/ports/cortex_a34/gnu/example_build/sample_threadx/startup.S @@ -7,7 +7,7 @@ // // Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ @@ -328,7 +328,7 @@ el1_entry_aarch64: // // Cortex-A processors automatically invalidate their caches on reset // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). - // It is therefore not necessary for software to invalidate the caches + // It is therefore not necessary for software to invalidate the caches // on startup, however, this is done here in case of a warm reset. bl InvalidateUDCaches tlbi VMALLE1 diff --git a/ports/cortex_a34/gnu/example_build/sample_threadx/v8_aarch64.S b/ports/cortex_a34/gnu/example_build/sample_threadx/v8_aarch64.S index f8db3bfe..45445a98 100644 --- a/ports/cortex_a34/gnu/example_build/sample_threadx/v8_aarch64.S +++ b/ports/cortex_a34/gnu/example_build/sample_threadx/v8_aarch64.S @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports/cortex_a34/gnu/example_build/sample_threadx/v8_aarch64.h b/ports/cortex_a34/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports/cortex_a34/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports/cortex_a34/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_a34/gnu/example_build/sample_threadx/v8_mmu.h b/ports/cortex_a34/gnu/example_build/sample_threadx/v8_mmu.h index ee8834fa..d0c51601 100644 --- a/ports/cortex_a34/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports/cortex_a34/gnu/example_build/sample_threadx/v8_mmu.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports/cortex_a34/gnu/example_build/sample_threadx/v8_system.h b/ports/cortex_a34/gnu/example_build/sample_threadx/v8_system.h index ff96deff..a62d2a33 100644 --- a/ports/cortex_a34/gnu/example_build/sample_threadx/v8_system.h +++ b/ports/cortex_a34/gnu/example_build/sample_threadx/v8_system.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports/cortex_a34/gnu/example_build/sample_threadx/v8_utils.S b/ports/cortex_a34/gnu/example_build/sample_threadx/v8_utils.S index f0fcef26..888892a0 100644 --- a/ports/cortex_a34/gnu/example_build/sample_threadx/v8_utils.S +++ b/ports/cortex_a34/gnu/example_build/sample_threadx/v8_utils.S @@ -3,7 +3,7 @@ // // Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports/cortex_a34/gnu/example_build/sample_threadx/vectors.S b/ports/cortex_a34/gnu/example_build/sample_threadx/vectors.S index 9e60e001..7784f98e 100644 --- a/ports/cortex_a34/gnu/example_build/sample_threadx/vectors.S +++ b/ports/cortex_a34/gnu/example_build/sample_threadx/vectors.S @@ -3,7 +3,7 @@ // // Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports/cortex_a34/gnu/example_build/tx/.cproject b/ports/cortex_a34/gnu/example_build/tx/.cproject index e5ff05f4..4d9d34ca 100644 --- a/ports/cortex_a34/gnu/example_build/tx/.cproject +++ b/ports/cortex_a34/gnu/example_build/tx/.cproject @@ -1,234 +1,234 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a34/gnu/inc/tx_port.h b/ports/cortex_a34/gnu/inc/tx_port.h index a8d3fd48..e5352338 100644 --- a/ports/cortex_a34/gnu/inc/tx_port.h +++ b/ports/cortex_a34/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -369,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a34/gnu/src/tx_initialize_low_level.S b/ports/cortex_a34/gnu/src/tx_initialize_low_level.S index 9ee098ab..aa3f04cd 100644 --- a/ports/cortex_a34/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_a34/gnu/src/tx_initialize_low_level.S @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Initialize */ /** */ @@ -58,15 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -96,4 +88,4 @@ _tx_initialize_low_level: /* Done, return to caller. */ RET // Return to caller -// } +// } diff --git a/ports/cortex_a34/gnu/src/tx_thread_context_restore.S b/ports/cortex_a34/gnu/src/tx_thread_context_restore.S index 0830026d..54ebca65 100644 --- a/ports/cortex_a34/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a34/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,15 +59,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_a34/gnu/src/tx_thread_context_save.S b/ports/cortex_a34/gnu/src/tx_thread_context_save.S index 3a533f62..ae416079 100644 --- a/ports/cortex_a34/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a34/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_a34/gnu/src/tx_thread_fp_disable.c b/ports/cortex_a34/gnu/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports/cortex_a34/gnu/src/tx_thread_fp_disable.c +++ b/ports/cortex_a34/gnu/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports/cortex_a34/gnu/src/tx_thread_fp_enable.c b/ports/cortex_a34/gnu/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports/cortex_a34/gnu/src/tx_thread_fp_enable.c +++ b/ports/cortex_a34/gnu/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports/cortex_a34/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a34/gnu/src/tx_thread_interrupt_control.S index 14cc0cbd..465e7bb1 100644 --- a/ports/cortex_a34/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a34/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,17 +57,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_a34/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a34/gnu/src/tx_thread_interrupt_disable.S index f88bc834..f2d30435 100644 --- a/ports/cortex_a34/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a34/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports/cortex_a34/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a34/gnu/src/tx_thread_interrupt_restore.S index 51f3b00f..9f703456 100644 --- a/ports/cortex_a34/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a34/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,17 +57,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports/cortex_a34/gnu/src/tx_thread_schedule.S b/ports/cortex_a34/gnu/src/tx_thread_schedule.S index 95eb7d5d..3d9d215c 100644 --- a/ports/cortex_a34/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a34/gnu/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,18 +60,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_a34/gnu/src/tx_thread_stack_build.S b/ports/cortex_a34/gnu/src/tx_thread_stack_build.S index c4ffd3f8..116a2a3c 100644 --- a/ports/cortex_a34/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a34/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_a34/gnu/src/tx_thread_system_return.S b/ports/cortex_a34/gnu/src/tx_thread_system_return.S index 2fee3c65..0db113d5 100644 --- a/ports/cortex_a34/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a34/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,15 +59,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_a34/gnu/src/tx_timer_interrupt.S b/ports/cortex_a34/gnu/src/tx_timer_interrupt.S index 70bf5d3a..2e6c8f8f 100644 --- a/ports/cortex_a34/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a34/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,15 +61,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 03-08-2023 Cindy Deng Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/.cproject b/ports/cortex_a35/ac6/example_build/sample_threadx/.cproject index 42240200..7e53b3fd 100644 --- a/ports/cortex_a35/ac6/example_build/sample_threadx/.cproject +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/.cproject @@ -1,158 +1,158 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.scat index e5783c7c..d8dfde69 100644 --- a/ports/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.scat @@ -2,7 +2,7 @@ ; Scatter file for Armv8-A Startup code on FVP Base model ; Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************** @@ -25,7 +25,7 @@ LOAD 0x80000000 ; in source code for this to work correctly ; ARM_LIB_HEAP +0 ALIGN 64 EMPTY 0xA0000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.h b/ports/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/v8_mmu.h b/ports/cortex_a35/ac6/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports/cortex_a35/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports/cortex_a35/ac6/example_build/tx/.cproject b/ports/cortex_a35/ac6/example_build/tx/.cproject index 3be714ea..e0d1dda5 100644 --- a/ports/cortex_a35/ac6/example_build/tx/.cproject +++ b/ports/cortex_a35/ac6/example_build/tx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a35/ac6/inc/tx_port.h b/ports/cortex_a35/ac6/inc/tx_port.h index a8d3fd48..e5352338 100644 --- a/ports/cortex_a35/ac6/inc/tx_port.h +++ b/ports/cortex_a35/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -369,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a35/ac6/readme_threadx.txt b/ports/cortex_a35/ac6/readme_threadx.txt index fafe435c..3abb7d8e 100644 --- a/ports/cortex_a35/ac6/readme_threadx.txt +++ b/ports/cortex_a35/ac6/readme_threadx.txt @@ -1,19 +1,19 @@ - Microsoft's Azure RTOS ThreadX for Cortex-A35 + Microsoft's Azure RTOS ThreadX for Cortex-A35 Using the ARM Compiler 6 & DS 1. Import the ThreadX Projects -In order to build the ThreadX library and the ThreadX SMP demonstration, first import -the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +In order to build the ThreadX library and the ThreadX SMP demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) into your DS workspace. 2. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply select the Eclipse project file -"tx" and then select the build button. You should now observe the compilation -and assembly of the ThreadX library. This project build produces the ThreadX +Building the ThreadX library is easy; simply select the Eclipse project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. @@ -32,29 +32,29 @@ the ThreadX SMP demonstration. 4. System Initialization -The entry point in ThreadX for the Cortex-A35 using AC6 tools is at label -start64. This is defined within the AC6 compiler's startup code. In addition, -this is where all static and global pre-set C variable initialization processing +The entry point in ThreadX for the Cortex-A35 using AC6 tools is at label +start64. This is defined within the AC6 compiler's startup code. In addition, +this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for determining the -first available RAM address for use by the application, which is supplied as the +The ThreadX tx_initialize_low_level.s file is responsible for determining the +first available RAM address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 5. Register Usage and Stack Frames -The 64-bit AC6 compiler assumes that registers x0-x18 are scratch registers -for each function. All other registers used by a C function must be preserved -by the function. ThreadX takes advantage of this in situations where a context -switch happens as a result of making a ThreadX service call (which is itself a -C function). In such cases, the saved context of a thread is only the +The 64-bit AC6 compiler assumes that registers x0-x18 are scratch registers +for each function. All other registers used by a C function must be preserved +by the function. ThreadX takes advantage of this in situations where a context +switch happens as a result of making a ThreadX service call (which is itself a +C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -73,10 +73,10 @@ FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: 0x040 x22 x21 0x048 x23 x22 0x050 x20 x19 - 0x058 x21 x20 - 0x060 x18 x29 - 0x068 x19 x30 - 0x070 x16 + 0x058 x21 x20 + 0x060 x18 x29 + 0x068 x19 x30 + 0x070 x16 0x078 x17 0x080 x14 0x088 x15 @@ -95,7 +95,7 @@ FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: 0x0F0 x0 0x0F8 x1 0x100 x29 - 0x108 x30 + 0x108 x30 FP enabled and TX_THREAD.tx_thread_fp_enable == 1: @@ -144,19 +144,19 @@ FP enabled and TX_THREAD.tx_thread_fp_enable == 1: 0x1F0 q3 0x200 q0 0x210 q1 - 0x220 x28 - 0x228 reserved - 0x230 x26 - 0x238 x27 - 0x240 x24 - 0x248 x25 - 0x250 x22 - 0x258 x23 - 0x260 x20 - 0x268 x21 - 0x270 x18 - 0x278 x19 - 0x280 x16 + 0x220 x28 + 0x228 reserved + 0x230 x26 + 0x238 x27 + 0x240 x24 + 0x248 x25 + 0x250 x22 + 0x258 x23 + 0x260 x20 + 0x268 x21 + 0x270 x18 + 0x278 x19 + 0x280 x16 0x288 x17 0x290 x14 0x298 x15 @@ -175,20 +175,20 @@ FP enabled and TX_THREAD.tx_thread_fp_enable == 1: 0x300 x0 0x308 x1 0x310 x29 - 0x318 x30 + 0x318 x30 6. Improving Performance -The distribution version of ThreadX is built without any compiler optimizations. -This makes it easy to debug because you can trace or set breakpoints inside of -ThreadX itself. Of course, this costs some performance. To make it run faster, +The distribution version of ThreadX is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the project settings to the desired compiler optimization level. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling @@ -208,22 +208,22 @@ irq_handler: B _tx_thread_context_restore -By default, ThreadX assumes EL3 level of execution. Running and taking exceptions in EL1 +By default, ThreadX assumes EL3 level of execution. Running and taking exceptions in EL1 and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined. 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, thread sleeps, -timeouts, and application timers. Without such a timer interrupt source, these services -are not functional. However, all other ThreadX services are operational without a +ThreadX requires a periodic interrupt source to manage all time-slicing, thread sleeps, +timeouts, and application timers. Without such a timer interrupt source, these services +are not functional. However, all other ThreadX services are operational without a periodic timer source. 9. ARM FP Support By default, FP support is disabled for each thread. If saving the context of the FP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the FP usage: void tx_thread_fp_enable(void); diff --git a/ports/cortex_a35/ac6/src/tx_initialize_low_level.S b/ports/cortex_a35/ac6/src/tx_initialize_low_level.S index f456574e..7d2a4be3 100644 --- a/ports/cortex_a35/ac6/src/tx_initialize_low_level.S +++ b/ports/cortex_a35/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports/cortex_a35/ac6/src/tx_thread_context_restore.S b/ports/cortex_a35/ac6/src/tx_thread_context_restore.S index 8e0d5515..9ba82827 100644 --- a/ports/cortex_a35/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a35/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_a35/ac6/src/tx_thread_context_save.S b/ports/cortex_a35/ac6/src/tx_thread_context_save.S index 7768efc2..c2395155 100644 --- a/ports/cortex_a35/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a35/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_a35/ac6/src/tx_thread_fp_disable.c b/ports/cortex_a35/ac6/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports/cortex_a35/ac6/src/tx_thread_fp_disable.c +++ b/ports/cortex_a35/ac6/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports/cortex_a35/ac6/src/tx_thread_fp_enable.c b/ports/cortex_a35/ac6/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports/cortex_a35/ac6/src/tx_thread_fp_enable.c +++ b/ports/cortex_a35/ac6/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports/cortex_a35/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a35/ac6/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports/cortex_a35/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a35/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_a35/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a35/ac6/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports/cortex_a35/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a35/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports/cortex_a35/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a35/ac6/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports/cortex_a35/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a35/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports/cortex_a35/ac6/src/tx_thread_schedule.S b/ports/cortex_a35/ac6/src/tx_thread_schedule.S index 4cce4a62..057aa538 100644 --- a/ports/cortex_a35/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a35/ac6/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,18 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_a35/ac6/src/tx_thread_stack_build.S b/ports/cortex_a35/ac6/src/tx_thread_stack_build.S index 6c675d9b..01084da7 100644 --- a/ports/cortex_a35/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a35/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_a35/ac6/src/tx_thread_system_return.S b/ports/cortex_a35/ac6/src/tx_thread_system_return.S index 780bb128..b7593d79 100644 --- a/ports/cortex_a35/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a35/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_a35/ac6/src/tx_timer_interrupt.S b/ports/cortex_a35/ac6/src/tx_timer_interrupt.S index d84245c6..1b80a7f2 100644 --- a/ports/cortex_a35/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a35/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/.cproject b/ports/cortex_a35/gnu/example_build/sample_threadx/.cproject index 1c32cb32..40d4912d 100644 --- a/ports/cortex_a35/gnu/example_build/sample_threadx/.cproject +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/.cproject @@ -1,170 +1,170 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.ld b/ports/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.ld index eec8f12b..3bf47736 100644 --- a/ports/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/startup.S b/ports/cortex_a35/gnu/example_build/sample_threadx/startup.S index b71b45f8..b44806fe 100644 --- a/ports/cortex_a35/gnu/example_build/sample_threadx/startup.S +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/startup.S @@ -328,7 +328,7 @@ el1_entry_aarch64: // // Cortex-A processors automatically invalidate their caches on reset // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). - // It is therefore not necessary for software to invalidate the caches + // It is therefore not necessary for software to invalidate the caches // on startup, however, this is done here in case of a warm reset. bl InvalidateUDCaches tlbi VMALLE1 diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.h b/ports/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/v8_mmu.h b/ports/cortex_a35/gnu/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports/cortex_a35/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports/cortex_a35/gnu/example_build/tx/.cproject b/ports/cortex_a35/gnu/example_build/tx/.cproject index f1b8ed5b..9e5a975e 100644 --- a/ports/cortex_a35/gnu/example_build/tx/.cproject +++ b/ports/cortex_a35/gnu/example_build/tx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a35/gnu/inc/tx_port.h b/ports/cortex_a35/gnu/inc/tx_port.h index a8d3fd48..e5352338 100644 --- a/ports/cortex_a35/gnu/inc/tx_port.h +++ b/ports/cortex_a35/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -369,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a35/gnu/readme_threadx.txt b/ports/cortex_a35/gnu/readme_threadx.txt index bab64522..17895ee5 100644 --- a/ports/cortex_a35/gnu/readme_threadx.txt +++ b/ports/cortex_a35/gnu/readme_threadx.txt @@ -1,19 +1,19 @@ - Microsoft's Azure RTOS ThreadX for Cortex-A35 + Microsoft's Azure RTOS ThreadX for Cortex-A35 Using the ARM GNU Compiler & DS 1. Import the ThreadX Projects -In order to build the ThreadX library and the ThreadX SMP demonstration, first import -the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +In order to build the ThreadX library and the ThreadX SMP demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) into your DS workspace. 2. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply select the Eclipse project file -"tx" and then select the build button. You should now observe the compilation -and assembly of the ThreadX library. This project build produces the ThreadX +Building the ThreadX library is easy; simply select the Eclipse project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. @@ -32,29 +32,29 @@ the ThreadX SMP demonstration. 4. System Initialization -The entry point in ThreadX for the Cortex-A35 using GCC tools is at label -"start64". This is defined within the GCC compiler's startup code. In addition, -this is where all static and global pre-set C variable initialization processing +The entry point in ThreadX for the Cortex-A35 using GCC tools is at label +"start64". This is defined within the GCC compiler's startup code. In addition, +this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for determining the -first available RAM address for use by the application, which is supplied as the +The ThreadX tx_initialize_low_level.s file is responsible for determining the +first available RAM address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 5. Register Usage and Stack Frames -The 64-bit GCC compiler assumes that registers x0-x18 are scratch registers -for each function. All other registers used by a C function must be preserved -by the function. ThreadX takes advantage of this in situations where a context -switch happens as a result of making a ThreadX service call (which is itself a -C function). In such cases, the saved context of a thread is only the +The 64-bit GCC compiler assumes that registers x0-x18 are scratch registers +for each function. All other registers used by a C function must be preserved +by the function. ThreadX takes advantage of this in situations where a context +switch happens as a result of making a ThreadX service call (which is itself a +C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -73,10 +73,10 @@ FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: 0x040 x22 x21 0x048 x23 x22 0x050 x20 x19 - 0x058 x21 x20 - 0x060 x18 x29 - 0x068 x19 x30 - 0x070 x16 + 0x058 x21 x20 + 0x060 x18 x29 + 0x068 x19 x30 + 0x070 x16 0x078 x17 0x080 x14 0x088 x15 @@ -95,7 +95,7 @@ FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: 0x0F0 x0 0x0F8 x1 0x100 x29 - 0x108 x30 + 0x108 x30 FP enabled and TX_THREAD.tx_thread_fp_enable == 1: @@ -144,19 +144,19 @@ FP enabled and TX_THREAD.tx_thread_fp_enable == 1: 0x1F0 q3 0x200 q0 0x210 q1 - 0x220 x28 - 0x228 reserved - 0x230 x26 - 0x238 x27 - 0x240 x24 - 0x248 x25 - 0x250 x22 - 0x258 x23 - 0x260 x20 - 0x268 x21 - 0x270 x18 - 0x278 x19 - 0x280 x16 + 0x220 x28 + 0x228 reserved + 0x230 x26 + 0x238 x27 + 0x240 x24 + 0x248 x25 + 0x250 x22 + 0x258 x23 + 0x260 x20 + 0x268 x21 + 0x270 x18 + 0x278 x19 + 0x280 x16 0x288 x17 0x290 x14 0x298 x15 @@ -175,20 +175,20 @@ FP enabled and TX_THREAD.tx_thread_fp_enable == 1: 0x300 x0 0x308 x1 0x310 x29 - 0x318 x30 + 0x318 x30 6. Improving Performance -The distribution version of ThreadX is built without any compiler optimizations. -This makes it easy to debug because you can trace or set breakpoints inside of -ThreadX itself. Of course, this costs some performance. To make it run faster, +The distribution version of ThreadX is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the project settings to the desired compiler optimization level. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling @@ -208,22 +208,22 @@ irq_handler: B _tx_thread_context_restore -By default, ThreadX assumes EL3 level of execution. Running and taking exceptions in EL1 +By default, ThreadX assumes EL3 level of execution. Running and taking exceptions in EL1 and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined. 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, thread sleeps, -timeouts, and application timers. Without such a timer interrupt source, these services -are not functional. However, all other ThreadX services are operational without a +ThreadX requires a periodic interrupt source to manage all time-slicing, thread sleeps, +timeouts, and application timers. Without such a timer interrupt source, these services +are not functional. However, all other ThreadX services are operational without a periodic timer source. 9. ARM FP Support By default, FP support is disabled for each thread. If saving the context of the FP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the FP usage: void tx_thread_fp_enable(void); diff --git a/ports/cortex_a35/gnu/src/tx_initialize_low_level.S b/ports/cortex_a35/gnu/src/tx_initialize_low_level.S index 3dce3cea..3025f12b 100644 --- a/ports/cortex_a35/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_a35/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -99,4 +89,4 @@ _tx_initialize_low_level: /* Done, return to caller. */ RET // Return to caller -// } +// } diff --git a/ports/cortex_a35/gnu/src/tx_thread_context_restore.S b/ports/cortex_a35/gnu/src/tx_thread_context_restore.S index 8e0d5515..9ba82827 100644 --- a/ports/cortex_a35/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a35/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_a35/gnu/src/tx_thread_context_save.S b/ports/cortex_a35/gnu/src/tx_thread_context_save.S index 7768efc2..c2395155 100644 --- a/ports/cortex_a35/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a35/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_a35/gnu/src/tx_thread_fp_disable.c b/ports/cortex_a35/gnu/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports/cortex_a35/gnu/src/tx_thread_fp_disable.c +++ b/ports/cortex_a35/gnu/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports/cortex_a35/gnu/src/tx_thread_fp_enable.c b/ports/cortex_a35/gnu/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports/cortex_a35/gnu/src/tx_thread_fp_enable.c +++ b/ports/cortex_a35/gnu/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports/cortex_a35/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a35/gnu/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports/cortex_a35/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a35/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_a35/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a35/gnu/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports/cortex_a35/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a35/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports/cortex_a35/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a35/gnu/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports/cortex_a35/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a35/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports/cortex_a35/gnu/src/tx_thread_schedule.S b/ports/cortex_a35/gnu/src/tx_thread_schedule.S index 4cce4a62..057aa538 100644 --- a/ports/cortex_a35/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a35/gnu/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,18 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_a35/gnu/src/tx_thread_stack_build.S b/ports/cortex_a35/gnu/src/tx_thread_stack_build.S index 6c675d9b..01084da7 100644 --- a/ports/cortex_a35/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a35/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_a35/gnu/src/tx_thread_system_return.S b/ports/cortex_a35/gnu/src/tx_thread_system_return.S index 780bb128..b7593d79 100644 --- a/ports/cortex_a35/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a35/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_a35/gnu/src/tx_timer_interrupt.S b/ports/cortex_a35/gnu/src/tx_timer_interrupt.S index d84245c6..1b80a7f2 100644 --- a/ports/cortex_a35/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a35/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_a5/ac5/example_build/sample_threadx.c b/ports/cortex_a5/ac5/example_build/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports/cortex_a5/ac5/example_build/sample_threadx.c +++ b/ports/cortex_a5/ac5/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_a5/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_a5/ac5/example_build/tx_initialize_low_level.s index af7e965c..5808714c 100644 --- a/ports/cortex_a5/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_a5/ac5/example_build/tx_initialize_low_level.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -90,45 +90,39 @@ __vectors ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-A5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -179,7 +173,7 @@ _tx_initialize_low_level ; _tx_thread_system_stack_ptr = (VOID_PTR) (sp); ; LDR r1, =_tx_thread_system_stack_ptr ; Pickup address of system stack ptr - LDR r0, [r1, #0] ; Pickup system stack + LDR r0, [r1, #0] ; Pickup system stack ADD r0, r0, #4 ; Increment to next free word ; ; /* Save the first available memory address. */ @@ -201,7 +195,7 @@ _tx_initialize_low_level ; ; ;/* Define initial heap/stack routine for the ARM RealView (and ADS) startup code. This -; routine will set the initial stack to use the ThreadX IRQ & FIQ & +; routine will set the initial stack to use the ThreadX IRQ & FIQ & ; (optionally SYS) stack areas. */ ; EXPORT __user_initial_stackheap @@ -253,7 +247,7 @@ __tx_reserved_handler ; ; EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -261,21 +255,21 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; ; BL _tx_timer_interrupt ; Timer interrupt handler _tx_not_timer_interrupt ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ IF :DEF:TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -285,7 +279,7 @@ _tx_not_timer_interrupt ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ IF :DEF:TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -301,28 +295,28 @@ _tx_not_timer_interrupt __tx_example_vectored_irq_handler ; ; -; /* Save initial context and call context save to prepare for +; /* Save initial context and call context save to prepare for ; vectored ISR execution. */ ; ; STMDB sp!, {r0-r3} ; Save some scratch registers ; MRS r0, SPSR ; Pickup saved SPSR -; SUB lr, lr, #4 ; Adjust point of interrupt +; SUB lr, lr, #4 ; Adjust point of interrupt ; STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers ; BL _tx_thread_vectored_context_save ; Vectored context save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ; IF :DEF:TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_start @@ -331,7 +325,7 @@ __tx_example_vectored_irq_handler ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ; IF :DEF:TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_end @@ -353,11 +347,11 @@ __tx_fiq_processing_return ; /* At this point execution is still in the FIQ mode. The CPSR, point of ; interrupt, and all C scratch registers are available for use. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start ; from FIQ mode with interrupts disabled. This routine switches to the -; system mode and returns with FIQ interrupts enabled. +; system mode and returns with FIQ interrupts enabled. ; -; NOTE: It is very important to ensure all FIQ interrupts are cleared +; NOTE: It is very important to ensure all FIQ interrupts are cleared ; prior to enabling nested FIQ interrupts. */ IF :DEF:TX_ENABLE_FIQ_NESTING BL _tx_thread_fiq_nesting_start diff --git a/ports/cortex_a5/ac5/inc/tx_port.h b/ports/cortex_a5/ac5/inc/tx_port.h index 5f028f6c..3c046e95 100644 --- a/ports/cortex_a5/ac5/inc/tx_port.h +++ b/ports/cortex_a5/ac5/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Cortex-A5/AC5 */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A5/AC5 */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -75,7 +67,7 @@ #include -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -111,12 +103,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -126,8 +118,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -174,7 +166,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -186,13 +178,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -206,11 +198,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -218,8 +210,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -246,21 +238,21 @@ typedef unsigned short USHORT; #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef __thumb - + #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (ULONG) __clz((unsigned int) m); \ - b = 31 - b; + b = 31 - b; #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -280,7 +272,7 @@ typedef unsigned short USHORT; { \ __enable_irq(); \ __enable_fiq(); \ - } + } #else @@ -289,7 +281,7 @@ typedef unsigned short USHORT; #define TX_RESTORE if (!interrupt_save_disabled) \ { \ __enable_irq(); \ - } + } #endif #else @@ -325,8 +317,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-A5/AC5 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A5/AC5 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a5/ac5/readme_threadx.txt b/ports/cortex_a5/ac5/readme_threadx.txt index 12962be2..35e50220 100644 --- a/ports/cortex_a5/ac5/readme_threadx.txt +++ b/ports/cortex_a5/ac5/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for Cortex-A5 + Microsoft's Azure RTOS ThreadX for Cortex-A5 Thumb & 32-bit Mode @@ -6,21 +6,21 @@ 1. Building the ThreadX run-time Library -First make sure you are in the "example_build" directory. Also, make sure that -you have setup your path and other environment variables necessary for the ARM -AC5 development environment. At this point you may run the build_threadx.bat -batch file. This will build the ThreadX run-time environment in the -"example_build" directory. +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the ARM +AC5 development environment. At this point you may run the build_threadx.bat +batch file. This will build the ThreadX run-time environment in the +"example_build" directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. 1.1 Building with Project Files -The ThreadX library can also be built via project files. Simply open -the tx.mcp file with project builder and select make. This will place +The ThreadX library can also be built via project files. Simply open +the tx.mcp file with project builder and select make. This will place the tx.a library file into the Debug sub-directory. @@ -29,45 +29,45 @@ the tx.a library file into the Debug sub-directory. The ThreadX demonstration is designed to execute under the ARM Windows-based simulator. -Building the demonstration is easy; simply execute the build_threadx_demo.bat -batch file while inside the "example_build" directory. +Building the demonstration is easy; simply execute the build_threadx_demo.bat +batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with tx.a. The resulting file sample_threadx.axf +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.axf is a binary file that can be downloaded and executed on the ARM simulator. 2.0.1 Building with Project Files -The ThreadX demonstration can also be built via project files. Simply open -the sample_threadx.mcp file with project builder and select make. This will place +The ThreadX demonstration can also be built via project files. Simply open +the sample_threadx.mcp file with project builder and select make. This will place the sample_threadx.axf output image into the Debug sub-directory. 3. System Initialization -The entry point in ThreadX for the Cortex-A5 using AC5 tools is at label -__main. This is defined within the AC5 compiler's startup code. In -addition, this is where all static and global pre-set C variable +The entry point in ThreadX for the Cortex-A5 using AC5 tools is at label +__main. This is defined within the AC5 compiler's startup code. In +addition, this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. By default, the vector area is defined to be located in the Init area, -which is defined at the top of tx_initialize_low_level.s. This area is typically -located at 0. In situations where this is impossible, the vectors at the beginning +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. By default, the vector area is defined to be located in the Init area, +which is defined at the top of tx_initialize_low_level.s. This area is typically +located at 0. In situations where this is impossible, the vectors at the beginning of the Init area should be copied to address 0. This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 4. Assembler / Compiler Switches -The following are compiler switches used in building the demonstration +The following are compiler switches used in building the demonstration system: Compiler Switch Meaning @@ -83,10 +83,10 @@ Linker Switch Meaning -o demo.axf Specifies demo output file name --elf Specifies elf output file format --ro Specifies that Read-Only memory starts at address 0 - --first tx_initialize_low_level.o(Init) + --first tx_initialize_low_level.o(Init) Specifies that the first area loaded is Init --remove Remove unused areas - --list Specifies map file name + --list Specifies map file name --symbols Specifies symbols for map file --map Creates a map file @@ -97,161 +97,161 @@ Application Defines ThreadX assembly files. If used, it should be used on all assembly files and the generic C source of - ThreadX should be compiled with + ThreadX should be compiled with TX_ENABLE_FIQ_SUPPORT defined as well. --PD "TX_ENABLE_IRQ_NESTING SETL {TRUE}" This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. --PD "TX_ENABLE_FIQ_NESTING SETL {TRUE}" This assembler define enables FIQ - nested support. If FIQ nested + nested support. If FIQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. In addition, IRQ nesting should also be enabled. -DTX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ interrupt handling in the ThreadX - generic C source. This define + generic C source. This define should also be used in conjunction with the corresponding assembler - define. + define. -DTX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - -DTX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + -DTX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - -DTX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + -DTX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - -DTX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + -DTX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - -DTX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + -DTX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - -DTX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + -DTX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - -DTX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + -DTX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - -DTX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + -DTX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - -DTX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + -DTX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - -DTX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + -DTX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - -DTX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + -DTX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - -DTX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + -DTX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - -DTX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + -DTX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - -DTX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + -DTX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - -DTX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + -DTX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - -DTX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + -DTX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - -DTX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + -DTX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - -DTX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + -DTX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - -DTX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + -DTX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - -DTX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + -DTX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. -DTX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - -DTX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + -DTX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - -DTX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + -DTX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. 5. Register Usage and Stack Frames -The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -269,39 +269,39 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make it run faster, you can change the build_threadx.bat file to -remove the -g option and enable all compiler optimizations. +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A5 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-A5 vectors start at address zero. The demonstration system startup -Init area contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +Init area contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs @@ -312,12 +312,12 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.s: EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -325,7 +325,7 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -338,7 +338,7 @@ __tx_irq_processing_return 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.s: EXPORT __tx_irq_example_handler @@ -348,12 +348,12 @@ __tx_irq_example_handler STMDB sp!, {r0-r3} ; Save some scratch registers MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers BL _tx_thread_vectored_context_save ; Call the vectored IRQ context save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -370,22 +370,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.s. When nested IRQ interrupts are no longer required, calling the _tx_thread_irq_nesting_end service disables nesting by disabling -IRQ interrupts and switching back to IRQ mode in preparation for the IRQ +IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -393,10 +393,10 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* Enable nested IRQ interrupts. NOTE: Since this service returns -; with IRQ interrupts enabled, all IRQ interrupt sources must be +; with IRQ interrupts enabled, all IRQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start -; +; ; /* Application ISR call(s) go here! */ ; ; /* Disable nested IRQ interrupts. The mode is switched back to @@ -409,12 +409,12 @@ __tx_irq_processing_return 7.3 FIQ Interrupts -By default, Cortex-A5 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, Cortex-A5 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.s. @@ -423,7 +423,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.s. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.s: @@ -451,18 +451,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.s. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -478,7 +478,7 @@ __tx_fiq_processing_return ; interrupt, and all C scratch registers are available for use. */ ; ; /* Enable nested FIQ interrupts. NOTE: Since this service returns -; with FIQ interrupts enabled, all FIQ interrupt sources must be +; with FIQ interrupts enabled, all FIQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start ; @@ -494,28 +494,28 @@ __tx_fiq_processing_return 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.s in the Integrator sub-directories. 9. Thumb/Cortex-A5 Mixed Mode -By default, ThreadX is setup for running in Cortex-A5 32-bit mode. This is -also true for the demonstration system. It is possible to build any -ThreadX file and/or the application in Thumb mode. If any Thumb code -is used the entire ThreadX source- both C and assembly - should be built +By default, ThreadX is setup for running in Cortex-A5 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. If any Thumb code +is used the entire ThreadX source- both C and assembly - should be built with the "-apcs /interwork" option. 11. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); diff --git a/ports/cortex_a5/ac5/src/tx_thread_context_restore.s b/ports/cortex_a5/ac5/src/tx_thread_context_restore.s index 35652d4f..6c3632e1 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_a5/ac5/src/tx_thread_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -54,44 +54,38 @@ SVC_MODE EQU 0x93 ; SVC mode ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore Cortex-A5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -121,13 +115,13 @@ _tx_thread_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3, #0] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3, #0] ; Store the counter + STR r2, [r3, #0] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs diff --git a/ports/cortex_a5/ac5/src/tx_thread_context_save.s b/ports/cortex_a5/ac5/src/tx_thread_context_save.s index 20630974..df4e96a8 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_context_save.s +++ b/ports/cortex_a5/ac5/src/tx_thread_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,43 +39,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save Cortex-A5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -90,7 +84,7 @@ _tx_thread_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers IF :DEF:TX_ENABLE_FIQ_SUPPORT CPSID if ; Disable FIQ interrupts ENDIF @@ -109,7 +103,7 @@ _tx_thread_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -125,7 +119,7 @@ _tx_thread_context_save POP {lr} ; Recover ISR lr ENDIF - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; __tx_thread_not_nested_save ; } @@ -139,13 +133,13 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} ; Store other registers ; ; /* Save the current stack pointer in the thread's control block. */ @@ -165,7 +159,7 @@ __tx_thread_not_nested_save POP {lr} ; Recover ISR lr ENDIF - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ; else @@ -175,7 +169,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit @@ -190,7 +184,7 @@ __tx_thread_idle_system_save ENDIF ADD sp, sp, #16 ; Recover saved registers - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ;} diff --git a/ports/cortex_a5/ac5/src/tx_thread_fiq_context_restore.s b/ports/cortex_a5/ac5/src/tx_thread_fiq_context_restore.s index fd513c2c..fd0cb587 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_a5/ac5/src/tx_thread_fiq_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -32,7 +32,7 @@ ; SVC_MODE EQU 0xD3 ; SVC mode FIQ_MODE EQU 0xD1 ; FIQ mode -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; ; @@ -50,44 +50,38 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_restore Cortex-A5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the fiq interrupt context when processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* FIQ ISR Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) @@ -113,13 +107,13 @@ _tx_thread_fiq_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3] ; Store the counter + STR r2, [r3] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -164,7 +158,7 @@ __tx_thread_fiq_no_preempt_restore ; /* Restore interrupted thread or ISR. */ ; ; /* Pickup the saved stack pointer. */ -; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; ; ; /* Recover the saved context and return to the point of interrupt. */ ; @@ -209,7 +203,7 @@ _tx_skip_fiq_vfp_save MOV r3, #1 ; Build interrupt stack type STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR STR sp, [r0, #8] ; Save stack pointer in thread control - ; block + ; block ; ; /* Save the remaining time-slice and disable it. */ ; if (_tx_timer_time_slice) @@ -221,7 +215,7 @@ _tx_skip_fiq_vfp_save BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it ; ; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; -; _tx_timer_time_slice = 0; +; _tx_timer_time_slice = 0; ; STR r2, [r0, #24] ; Save thread's time-slice MOV r2, #0 ; Clear value diff --git a/ports/cortex_a5/ac5/src/tx_thread_fiq_context_save.s b/ports/cortex_a5/ac5/src/tx_thread_fiq_context_save.s index e45574f3..21e920ae 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_fiq_context_save.s +++ b/ports/cortex_a5/ac5/src/tx_thread_fiq_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,43 +39,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_save Cortex-A5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) @@ -90,7 +84,7 @@ _tx_thread_fiq_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state CMP r2, #0 ; Is this the first interrupt? @@ -105,7 +99,7 @@ _tx_thread_fiq_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -121,38 +115,38 @@ _tx_thread_fiq_context_save POP {lr} ; Recover ISR lr ENDIF - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; __tx_thread_fiq_not_nested_save -; } +; } ; ; /* Otherwise, not nested, check to see if a thread was running. */ ; else if (_tx_thread_current_ptr) -; { +; { ; ADD r2, r2, #1 ; Increment the interrupt counter STR r2, [r3] ; Store it back in the variable LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in -; ; scheduling loop - nothing needs saving! + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, lr} ; Store other registers, Note that we don't -; ; need to save sl and ip since FIQ has -; ; copies of these registers. Nested +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested ; ; interrupt processing does need to save ; ; these registers. ; ; /* Save the current stack pointer in the thread's control block. */ -; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; ; ; /* Switch to the system stack. */ -; sp = _tx_thread_system_stack_ptr; +; sp = _tx_thread_system_stack_ptr; ; MOV r10, #0 ; Clear stack limit @@ -165,7 +159,7 @@ __tx_thread_fiq_not_nested_save POP {lr} ; Recover ISR lr ENDIF - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } ; else @@ -185,18 +179,18 @@ __tx_thread_fiq_idle_system_save ENDIF ; ; /* Not much to do here, save the current SPSR and LR for possible -; use in IRQ interrupted in idle system conditions, and return to +; use in IRQ interrupted in idle system conditions, and return to ; FIQ interrupt processing. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, lr} ; Store other registers that will get used -; ; or stripped off the stack in context -; ; restore - B __tx_fiq_processing_return ; Continue FIQ processing +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } -;} +;} ; END diff --git a/ports/cortex_a5/ac5/src/tx_thread_fiq_nesting_end.s b/ports/cortex_a5/ac5/src/tx_thread_fiq_nesting_end.s index d5d9f51a..4e6699a7 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_fiq_nesting_end.s +++ b/ports/cortex_a5/ac5/src/tx_thread_fiq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,56 +34,50 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_end Cortex-A5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ -;/* processing from system mode back to FIQ mode prior to the ISR */ -;/* calling _tx_thread_fiq_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with FIQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) @@ -94,7 +88,7 @@ _tx_thread_fiq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_c, r0 ; Disable interrupts - LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports/cortex_a5/ac5/src/tx_thread_fiq_nesting_start.s b/ports/cortex_a5/ac5/src/tx_thread_fiq_nesting_start.s index b12d14da..91a3164f 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_fiq_nesting_start.s +++ b/ports/cortex_a5/ac5/src/tx_thread_fiq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_start Cortex-A5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ -;/* processing to the system mode so nested FIQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with FIQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_a5/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_a5/ac5/src/tx_thread_interrupt_control.s index c8056c39..ded46918 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_interrupt_control.s +++ b/ports/cortex_a5/ac5/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,42 +36,36 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control Cortex-A5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a5/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_a5/ac5/src/tx_thread_interrupt_disable.s index 8a59297c..8c922f00 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_a5/ac5/src/tx_thread_interrupt_disable.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,41 +29,35 @@ ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable Cortex-A5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(void) @@ -80,7 +74,7 @@ _tx_thread_interrupt_disable IF :DEF:TX_ENABLE_FIQ_SUPPORT CPSID if ; Disable IRQ and FIQ ELSE - CPSID i ; Disable IRQ + CPSID i ; Disable IRQ ENDIF IF {INTER} = {TRUE} diff --git a/ports/cortex_a5/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_a5/ac5/src/tx_thread_interrupt_restore.s index aa83ad27..ef515f0e 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_a5/ac5/src/tx_thread_interrupt_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,42 +29,36 @@ ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore Cortex-A5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function is responsible for restoring interrupts to the state */ ;/* returned by a previous _tx_thread_interrupt_disable call. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a5/ac5/src/tx_thread_irq_nesting_end.s b/ports/cortex_a5/ac5/src/tx_thread_irq_nesting_end.s index ae508e4a..be0bb7a5 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_irq_nesting_end.s +++ b/ports/cortex_a5/ac5/src/tx_thread_irq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,56 +34,50 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_end Cortex-A5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -;/* processing from system mode back to IRQ mode prior to the ISR */ -;/* calling _tx_thread_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) @@ -94,7 +88,7 @@ _tx_thread_irq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_c, r0 ; Disable interrupts - LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports/cortex_a5/ac5/src/tx_thread_irq_nesting_start.s b/ports/cortex_a5/ac5/src/tx_thread_irq_nesting_start.s index c326590b..b2f554a7 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_irq_nesting_start.s +++ b/ports/cortex_a5/ac5/src/tx_thread_irq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_start Cortex-A5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_context_save has been called and switches the IRQ */ -;/* processing to the system mode so nested IRQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_a5/ac5/src/tx_thread_schedule.s b/ports/cortex_a5/ac5/src/tx_thread_schedule.s index b75c6836..025a6966 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_a5/ac5/src/tx_thread_schedule.s @@ -1,19 +1,19 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors -; * +; * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -41,45 +41,39 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule Cortex-A5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -108,7 +102,7 @@ __tx_thread_schedule_loop ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Lockout interrupts and ; transfer control to it. */ ; @@ -121,7 +115,7 @@ __tx_thread_schedule_loop ; /* Setup the current thread pointer. */ ; _tx_thread_current_ptr = _tx_thread_execute_ptr; ; - LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread STR r0, [r1, #0] ; Setup current thread pointer ; ; /* Increment the run count for this thread. */ @@ -135,7 +129,7 @@ __tx_thread_schedule_loop ; /* Setup time-slice, if present. */ ; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; ; - LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice ; variable LDR sp, [r0, #8] ; Switch stack pointers STR r3, [r2, #0] ; Setup time-slice diff --git a/ports/cortex_a5/ac5/src/tx_thread_stack_build.s b/ports/cortex_a5/ac5/src/tx_thread_stack_build.s index b006a943..cfba7634 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_stack_build.s +++ b/ports/cortex_a5/ac5/src/tx_thread_stack_build.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -41,44 +41,38 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build Cortex-A5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function builds a stack frame on the supplied thread's stack. */ ;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ ;/* thread_ptr Pointer to thread control blk */ ;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -86,10 +80,10 @@ THUMB_BIT EQU 0x20 ; Thumb-bit EXPORT _tx_thread_stack_build _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-A5 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; a1 (r0) Initial value for a1 diff --git a/ports/cortex_a5/ac5/src/tx_thread_system_return.s b/ports/cortex_a5/ac5/src/tx_thread_system_return.s index 26925f8a..afca3f69 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_system_return.s +++ b/ports/cortex_a5/ac5/src/tx_thread_system_return.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -33,50 +33,44 @@ IMPORT _tx_timer_time_slice IMPORT _tx_thread_schedule IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY - IMPORT _tx_execution_thread_exit + IMPORT _tx_execution_thread_exit ENDIF ; ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return Cortex-A5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -104,7 +98,7 @@ _tx_skip_solicited_vfp_save MOV r0, #0 ; Build a solicited stack type MRS r1, CPSR ; Pickup the CPSR STMDB sp!, {r0-r1} ; Save type and CPSR -; +; ; /* Lockout interrupts. */ ; IF :DEF:TX_ENABLE_FIQ_SUPPORT diff --git a/ports/cortex_a5/ac5/src/tx_thread_vectored_context_save.s b/ports/cortex_a5/ac5/src/tx_thread_vectored_context_save.s index 53b988a0..a902142c 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_vectored_context_save.s +++ b/ports/cortex_a5/ac5/src/tx_thread_vectored_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -38,43 +38,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_vectored_context_save Cortex-A5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) @@ -135,7 +129,7 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Note: Minimal context of interrupted thread is already saved. */ @@ -171,7 +165,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports/cortex_a5/ac5/src/tx_timer_interrupt.s b/ports/cortex_a5/ac5/src/tx_timer_interrupt.s index 052b590d..975911e4 100644 --- a/ports/cortex_a5/ac5/src/tx_timer_interrupt.s +++ b/ports/cortex_a5/ac5/src/tx_timer_interrupt.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -44,46 +44,40 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt Cortex-A5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -107,7 +101,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CMP r2, #0 ; Is it non-active? BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing @@ -225,13 +219,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CMP r2, #0 ; See if the flag is set BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing ; diff --git a/ports/cortex_a5/ac6/example_build/sample_threadx/.cproject b/ports/cortex_a5/ac6/example_build/sample_threadx/.cproject index 27463deb..86a4d2d6 100644 --- a/ports/cortex_a5/ac6/example_build/sample_threadx/.cproject +++ b/ports/cortex_a5/ac6/example_build/sample_threadx/.cproject @@ -1,176 +1,176 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a5/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_a5/ac6/example_build/sample_threadx/sample_threadx.scat index d23881cd..66d0d95a 100644 --- a/ports/cortex_a5/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports/cortex_a5/ac6/example_build/sample_threadx/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports/cortex_a5/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_a5/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 083a57a7..76395459 100644 --- a/ports/cortex_a5/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_a5/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -91,14 +92,6 @@ $_tx_initialize_low_level: /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ .global _tx_initialize_low_level .type _tx_initialize_low_level,function diff --git a/ports/cortex_a5/ac6/example_build/tx/.cproject b/ports/cortex_a5/ac6/example_build/tx/.cproject index 22e5a64c..f50b881e 100644 --- a/ports/cortex_a5/ac6/example_build/tx/.cproject +++ b/ports/cortex_a5/ac6/example_build/tx/.cproject @@ -1,146 +1,146 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a5/ac6/inc/tx_port.h b/ports/cortex_a5/ac6/inc/tx_port.h index f9b96956..f0153046 100644 --- a/ports/cortex_a5/ac6/inc/tx_port.h +++ b/ports/cortex_a5/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,20 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Updated comments, removed */ -/* unneeded temp variable, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -320,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv7-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a5/ac6/src/tx_thread_context_restore.S b/ports/cortex_a5/ac6/src/tx_thread_context_restore.S index 6b4a561d..41b0b0d0 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a5/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,23 +80,6 @@ IRQ_MODE = 0x12 // IRQ mode /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_restore .type _tx_thread_context_restore,function diff --git a/ports/cortex_a5/ac6/src/tx_thread_context_save.S b/ports/cortex_a5/ac6/src/tx_thread_context_save.S index eff06283..d2d29d34 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a5/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,23 +72,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_save .type _tx_thread_context_save,function diff --git a/ports/cortex_a5/ac6/src/tx_thread_fiq_context_restore.S b/ports/cortex_a5/ac6/src/tx_thread_fiq_context_restore.S index d2fbebe1..921c322c 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a5/ac6/src/tx_thread_fiq_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -78,20 +79,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* FIQ ISR Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_restore .type _tx_thread_fiq_context_restore,function diff --git a/ports/cortex_a5/ac6/src/tx_thread_fiq_context_save.S b/ports/cortex_a5/ac6/src/tx_thread_fiq_context_save.S index 88472a3d..2f1a6c40 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a5/ac6/src/tx_thread_fiq_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_save .type _tx_thread_fiq_context_save,function diff --git a/ports/cortex_a5/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a5/ac6/src/tx_thread_fiq_nesting_end.S index fa3886b8..a7ce701e 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a5/ac6/src/tx_thread_fiq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a5/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a5/ac6/src/tx_thread_fiq_nesting_start.S index dbed1cf2..4f095dde 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a5/ac6/src/tx_thread_fiq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a5/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a5/ac6/src/tx_thread_interrupt_control.S index d1223cb8..a5bc47f7 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a5/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,20 +69,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a5/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a5/ac6/src/tx_thread_interrupt_disable.S index a87d1a06..d7b53bc2 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a5/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,20 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a5/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a5/ac6/src/tx_thread_interrupt_restore.S index 53ff2813..3c31e94b 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a5/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,20 +68,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a5/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_a5/ac6/src/tx_thread_irq_nesting_end.S index 18aebc7c..cc4db3a7 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a5/ac6/src/tx_thread_irq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a5/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_a5/ac6/src/tx_thread_irq_nesting_start.S index a2ffd35d..3635874d 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a5/ac6/src/tx_thread_irq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a5/ac6/src/tx_thread_schedule.S b/ports/cortex_a5/ac6/src/tx_thread_schedule.S index f46a339b..a74e2050 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a5/ac6/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,23 +82,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a5/ac6/src/tx_thread_stack_build.S b/ports/cortex_a5/ac6/src/tx_thread_stack_build.S index 3876225a..827554a7 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a5/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,20 +75,6 @@ CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ int /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a5/ac6/src/tx_thread_system_return.S b/ports/cortex_a5/ac6/src/tx_thread_system_return.S index 0eed478d..1a17446b 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a5/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,23 +69,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a5/ac6/src/tx_thread_vectored_context_save.S b/ports/cortex_a5/ac6/src/tx_thread_vectored_context_save.S index fe8a98e8..91653b75 100644 --- a/ports/cortex_a5/ac6/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a5/ac6/src/tx_thread_vectored_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_vectored_context_save .type _tx_thread_vectored_context_save,function diff --git a/ports/cortex_a5/ac6/src/tx_timer_interrupt.S b/ports/cortex_a5/ac6/src/tx_timer_interrupt.S index cb0c1fa2..179ac894 100644 --- a/ports/cortex_a5/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a5/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -77,20 +78,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a5/ghs/example_build/tx_initialize_low_level.arm b/ports/cortex_a5/ghs/example_build/tx_initialize_low_level.arm index 1c7b035e..fe924b61 100644 --- a/ports/cortex_a5/ghs/example_build/tx_initialize_low_level.arm +++ b/ports/cortex_a5/ghs/example_build/tx_initialize_low_level.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a5/ghs/inc/tx_el.h b/ports/cortex_a5/ghs/inc/tx_el.h index b8926921..72e5bbe3 100644 --- a/ports/cortex_a5/ghs/inc/tx_el.h +++ b/ports/cortex_a5/ghs/inc/tx_el.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,12 +37,6 @@ /* EventAnalyzer. It is assumed that tx_api.h and tx_port.h have */ /* already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_EL_H diff --git a/ports/cortex_a5/ghs/inc/tx_port.h b/ports/cortex_a5/ghs/inc/tx_port.h index c93e234c..e9e0b876 100644 --- a/ports/cortex_a5/ghs/inc/tx_port.h +++ b/ports/cortex_a5/ghs/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -394,7 +386,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-A5/Green Hills Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A5/Green Hills Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a5/ghs/readme_threadx.txt b/ports/cortex_a5/ghs/readme_threadx.txt index 28e59b78..154ffc25 100644 --- a/ports/cortex_a5/ghs/readme_threadx.txt +++ b/ports/cortex_a5/ghs/readme_threadx.txt @@ -1,19 +1,19 @@ - Microsoft's Azure RTOS ThreadX for Cortex-A5 + Microsoft's Azure RTOS ThreadX for Cortex-A5 Using the Green Hills Software Tools 1. Open the ThreadX Project Workspace -In order to build the ThreadX library and the ThreadX demonstration first load -the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the -"example_build" directory. +In order to build the ThreadX library and the ThreadX demonstration first load +the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the +"example_build" directory. 2. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply select the MULTI project file -tx.gpj and then select the build button. You should now observe the -compilation and assembly of the ThreadX library. This project build produces +Building the ThreadX library is easy; simply select the MULTI project file +tx.gpj and then select the build button. You should now observe the +compilation and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. @@ -21,55 +21,55 @@ the ThreadX library file tx.a. The ThreadX demonstration is designed to execute under the MULTI environment on the Green Hills Cortex-A5 simulator. The instructions that follow describe -how to get the ThreadX evaluation running under the MULTI Cortex-A5 simulation +how to get the ThreadX evaluation running under the MULTI Cortex-A5 simulation environment. -Building the demonstration is easy; simply select the MULTI project file -sample_threadx.gpj. At this point, select the "Project Build" button and observe -the compilation, assembly, and linkage of the ThreadX demonstration application. +Building the demonstration is easy; simply select the MULTI project file +sample_threadx.gpj. At this point, select the "Project Build" button and observe +the compilation, assembly, and linkage of the ThreadX demonstration application. -After the demonstration is built, invoke the MULTI ARM simulator by selecting -the simulator connection from within the sample_threadx.con connection file. -Once connected to the simulator, select the "Debug" button. You should now -observe the main function of sample_threadx.c. +After the demonstration is built, invoke the MULTI ARM simulator by selecting +the simulator connection from within the sample_threadx.con connection file. +Once connected to the simulator, select the "Debug" button. You should now +observe the main function of sample_threadx.c. At this point, you should setup a simulated timer interrupt for ThreadX by entering "timer 9999 irq" in the "target" window of the debugger. -You are now ready to execute the ThreadX demonstration system. Select -breakpoints and data watches to observe the execution of the sample_threadx.c +You are now ready to execute the ThreadX demonstration system. Select +breakpoints and data watches to observe the execution of the sample_threadx.c application. 4. EventAnalyzer Demonstration -To build a demonstration system that also logs events for the MULTI EventAnalyzer, -perform the same steps as the regular demo, except build the ThreadX library with -txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. -The resulting image will log all system events, which can then be displayed by the +To build a demonstration system that also logs events for the MULTI EventAnalyzer, +perform the same steps as the regular demo, except build the ThreadX library with +txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. +The resulting image will log all system events, which can then be displayed by the MULTI EventAnalyzer. 5. System Initialization -The system entry point using the Green Hills tools is at the label _start. -This is defined within the crt0.arm file supplied by Green Hills. In addition, -this is where all static and global preset C variable initialization +The system entry point using the Green Hills tools is at the label _start. +This is defined within the crt0.arm file supplied by Green Hills. In addition, +this is where all static and global preset C variable initialization processing is called from. After the Green Hills startup function returns, ThreadX initialization is called. The main initialization function is _tx_initialize_low_level and -is located in the file tx_initialize_low_level.arm. This function is responsible -for setting up various system data structures, interrupt vectors, and the +is located in the file tx_initialize_low_level.arm. This function is responsible +for setting up various system data structures, interrupt vectors, and the periodic timer interrupt source of ThreadX. -In addition, _tx_initialize_low_level determines where the first available +In addition, _tx_initialize_low_level determines where the first available RAM memory address is located. This address is supplied to tx_application_define. -By default, the first available RAM memory address is assumed to start at the -beginning of the ThreadX section .free_mem. If changes are made to the -sample_threadx.ld file, the .free_mem section should remain the last allocated -section in the main RAM area. The starting address of this section is passed +By default, the first available RAM memory address is assumed to start at the +beginning of the ThreadX section .free_mem. If changes are made to the +sample_threadx.ld file, the .free_mem section should remain the last allocated +section in the main RAM area. The starting address of this section is passed to tx_application_define. @@ -87,27 +87,27 @@ The following defines and their associated action are as follows: TX_ENABLE_FIQ_NESTING If defined, this brings in special FIQ interrupt nesting logic into the ThreadX library. This define should be applied - to the entire ThreadX library and the + to the entire ThreadX library and the define TX_ENABLE_FIQ_SUPPORT should also be defined. TX_ENABLE_FIQ_SUPPORT If defined, this brings in FIQ context save and restore logic necessary for applications to call ThreadX services from - FIQ interrupt handlers. This define - should be applied to the entire ThreadX + FIQ interrupt handlers. This define + should be applied to the entire ThreadX library. TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 4 in the "ThreadX User Guide" + Chapter 4 in the "ThreadX User Guide" for more details. TX_ENABLE_EVENT_LOGGING This define enables event logging for any or all of the ThreadX source code. If this - option is used anywhere, the tx_initialize_high_level.c + option is used anywhere, the tx_initialize_high_level.c file must be compiled with it as well, since this is where the event log is initialized. @@ -119,121 +119,121 @@ The following defines and their associated action are as follows: If this is enabled, run-time filtering logic is added to the event logging code. - TX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. 7. Register Usage and Stack Frames -The Green Hills compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) -are scratch registers for each function. All other registers used by a C -function must be preserved by the function. ThreadX takes advantage of this -in situations where a context switch happens as a result of making a ThreadX -service call (which is itself a C function). In such cases, the saved +The Green Hills compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) +are scratch registers for each function. All other registers used by a C +function must be preserved by the function. ThreadX takes advantage of this +in situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -251,40 +251,40 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 8. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make ThreadX run faster, you can change the tx.gpj project -to disable debug information and enable the desired optimizations. +to disable debug information and enable the desired optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined before tx_api.h is included. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. 9. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A5 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 9.1 Vector Area The Cortex-A5 vectors start at address zero. The demonstration system reset.arm -file contains the reset section (which contains all the ARM vectors) and is +file contains the reset section (which contains all the ARM vectors) and is typically loaded at address zero. On actual hardware platforms, this section -might have to be copied to address 0. +might have to be copied to address 0. 9.2 IRQ ISRs @@ -294,13 +294,13 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 9.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.arm: .globl __tx_irq_handler - .globl __tx_irq_processing_return + .globl __tx_irq_processing_return __tx_irq_handler: /* Jump to context save to save system context. */ @@ -308,7 +308,7 @@ __tx_irq_handler: __tx_irq_processing_return: /* At this point execution is still in the IRQ mode. The CPSR, point of - interrupt, and all C scratch registers are available for use. Note + interrupt, and all C scratch registers are available for use. Note that IRQ interrupts are still disabled upon return from the context save function. */ @@ -321,7 +321,7 @@ __tx_irq_processing_return: 9.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.arm: .globl __tx_irq_example_handler @@ -331,12 +331,12 @@ __tx_irq_example_handler: STMDB sp!, {r0-r3} # Save some scratch registers MRS r0, SPSR # Pickup saved SPSR - SUB lr, lr, #4 # Adjust point of interrupt + SUB lr, lr, #4 # Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} # Store other scratch registers BL _tx_thread_vectored_context_save # Call the vectored IRQ context save /* At this point execution is still in the IRQ mode. The CPSR, point of - interrupt, and all C scratch registers are available for use. Note + interrupt, and all C scratch registers are available for use. Note that IRQ interrupts are still disabled upon return from the context save function. */ @@ -353,22 +353,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.arm. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables nesting -by disabling IRQ interrupts and switching back to IRQ mode in preparation for +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.arm. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables nesting +by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in the +The following is an example of enabling IRQ nested interrupts in the typical IRQ handler: .globl __tx_irq_handler - .globl __tx_irq_processing_return + .globl __tx_irq_processing_return __tx_irq_handler: /* Jump to context save to save system context. */ @@ -376,10 +376,10 @@ __tx_irq_handler: __tx_irq_processing_return: /* Enable nested IRQ interrupts. NOTE: Since this service returns - with IRQ interrupts enabled, all IRQ interrupt sources must be + with IRQ interrupts enabled, all IRQ interrupt sources must be cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start - + /* Application ISR call(s) go here! */ /* Disable nested IRQ interrupts. The mode is switched back to @@ -392,9 +392,9 @@ __tx_irq_processing_return: 9.3 FIQ Interrupts -By default, Cortex-A5 FIQ interrupts are left completely enabled by ThreadX. -Of course, this means that the application is fully responsible for -saving/restoring any registers used in the FIQ ISR processing. In addition, +By default, Cortex-A5 FIQ interrupts are left completely enabled by ThreadX. +Of course, this means that the application is fully responsible for +saving/restoring any registers used in the FIQ ISR processing. In addition, no ThreadX service calls are allowed from the default FIQ ISRs. The default FIQ interrupt shell is located in tx_initialize_low_level.arm. @@ -403,7 +403,7 @@ FIQ interrupt shell is located in tx_initialize_low_level.arm. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.arm: @@ -431,18 +431,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.arm. When nested FIQ interrupts are no longer -required, calling the _tx_thread_fiq_nesting_end service disables nesting by -disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.arm. When nested FIQ interrupts are no longer +required, calling the _tx_thread_fiq_nesting_end service disables nesting by +disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -458,7 +458,7 @@ __tx_fiq_processing_return: interrupt, and all C scratch registers are available for use. */ /* Enable nested FIQ interrupts. NOTE: Since this service returns - with FIQ interrupts enabled, all FIQ interrupt sources must be + with FIQ interrupts enabled, all FIQ interrupt sources must be cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start @@ -475,29 +475,29 @@ __tx_fiq_processing_return: 10. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.arm. 11. Thumb/Cortex-A5 Mixed Mode -By default, ThreadX is setup for running in Cortex-A5 32-bit mode. This is -also true for the demonstration system. It is possible to build any +By default, ThreadX is setup for running in Cortex-A5 32-bit mode. This is +also true for the demonstration system. It is possible to build any ThreadX file and/or the application in Thumb mode. The only exception -to this is the file tx_thread_shell_entry.c. This file must always be +to this is the file tx_thread_shell_entry.c. This file must always be built in 32-bit mode. 12. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); @@ -520,7 +520,7 @@ information associated with this specific port of ThreadX: 04-02-2021 Release 6.1.6 changes: tx_port.h Updated macro definition -05/19/2020 Initial ThreadX version of Cortex-A5/Green Hills port. +05/19/2020 Initial ThreadX version of Cortex-A5/Green Hills port. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_a5/ghs/src/tx_el.c b/ports/cortex_a5/ghs/src/tx_el.c index 365622cd..b5d3b8b7 100644 --- a/ports/cortex_a5/ghs/src/tx_el.c +++ b/ports/cortex_a5/ghs/src/tx_el.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,12 +83,6 @@ UINT _tx_thread_interrupt_control(UINT new_posture); /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_el_initialize(VOID) { diff --git a/ports/cortex_a5/ghs/src/tx_thread_context_restore.arm b/ports/cortex_a5/ghs/src/tx_thread_context_restore.arm index 52c099c6..4cd43b30 100644 --- a/ports/cortex_a5/ghs/src/tx_thread_context_restore.arm +++ b/ports/cortex_a5/ghs/src/tx_thread_context_restore.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a5/ghs/src/tx_thread_context_save.arm b/ports/cortex_a5/ghs/src/tx_thread_context_save.arm index 48bc08e2..813984e1 100644 --- a/ports/cortex_a5/ghs/src/tx_thread_context_save.arm +++ b/ports/cortex_a5/ghs/src/tx_thread_context_save.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a5/ghs/src/tx_thread_fiq_context_restore.arm b/ports/cortex_a5/ghs/src/tx_thread_fiq_context_restore.arm index 836990e9..e0ea4280 100644 --- a/ports/cortex_a5/ghs/src/tx_thread_fiq_context_restore.arm +++ b/ports/cortex_a5/ghs/src/tx_thread_fiq_context_restore.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a5/ghs/src/tx_thread_fiq_context_save.arm b/ports/cortex_a5/ghs/src/tx_thread_fiq_context_save.arm index 39ac2d37..5d43d442 100644 --- a/ports/cortex_a5/ghs/src/tx_thread_fiq_context_save.arm +++ b/ports/cortex_a5/ghs/src/tx_thread_fiq_context_save.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a5/ghs/src/tx_thread_fiq_nesting_end.arm b/ports/cortex_a5/ghs/src/tx_thread_fiq_nesting_end.arm index 5ddfe98c..28a329dd 100644 --- a/ports/cortex_a5/ghs/src/tx_thread_fiq_nesting_end.arm +++ b/ports/cortex_a5/ghs/src/tx_thread_fiq_nesting_end.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a5/ghs/src/tx_thread_fiq_nesting_start.arm b/ports/cortex_a5/ghs/src/tx_thread_fiq_nesting_start.arm index 6787d19a..936dfad6 100644 --- a/ports/cortex_a5/ghs/src/tx_thread_fiq_nesting_start.arm +++ b/ports/cortex_a5/ghs/src/tx_thread_fiq_nesting_start.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a5/ghs/src/tx_thread_interrupt_control.arm b/ports/cortex_a5/ghs/src/tx_thread_interrupt_control.arm index 9b3c9b19..65810603 100644 --- a/ports/cortex_a5/ghs/src/tx_thread_interrupt_control.arm +++ b/ports/cortex_a5/ghs/src/tx_thread_interrupt_control.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a5/ghs/src/tx_thread_interrupt_disable.arm b/ports/cortex_a5/ghs/src/tx_thread_interrupt_disable.arm index 2bb6d1dc..5e1f9b95 100644 --- a/ports/cortex_a5/ghs/src/tx_thread_interrupt_disable.arm +++ b/ports/cortex_a5/ghs/src/tx_thread_interrupt_disable.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a5/ghs/src/tx_thread_interrupt_restore.arm b/ports/cortex_a5/ghs/src/tx_thread_interrupt_restore.arm index 1185de93..135add2d 100644 --- a/ports/cortex_a5/ghs/src/tx_thread_interrupt_restore.arm +++ b/ports/cortex_a5/ghs/src/tx_thread_interrupt_restore.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a5/ghs/src/tx_thread_irq_nesting_end.arm b/ports/cortex_a5/ghs/src/tx_thread_irq_nesting_end.arm index 09c29276..6796d6e5 100644 --- a/ports/cortex_a5/ghs/src/tx_thread_irq_nesting_end.arm +++ b/ports/cortex_a5/ghs/src/tx_thread_irq_nesting_end.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a5/ghs/src/tx_thread_irq_nesting_start.arm b/ports/cortex_a5/ghs/src/tx_thread_irq_nesting_start.arm index d9e69e25..e75175e8 100644 --- a/ports/cortex_a5/ghs/src/tx_thread_irq_nesting_start.arm +++ b/ports/cortex_a5/ghs/src/tx_thread_irq_nesting_start.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a5/ghs/src/tx_thread_schedule.arm b/ports/cortex_a5/ghs/src/tx_thread_schedule.arm index 69ac7933..128491d0 100644 --- a/ports/cortex_a5/ghs/src/tx_thread_schedule.arm +++ b/ports/cortex_a5/ghs/src/tx_thread_schedule.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a5/ghs/src/tx_thread_stack_build.arm b/ports/cortex_a5/ghs/src/tx_thread_stack_build.arm index 19dd2b47..c3681c87 100644 --- a/ports/cortex_a5/ghs/src/tx_thread_stack_build.arm +++ b/ports/cortex_a5/ghs/src/tx_thread_stack_build.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a5/ghs/src/tx_thread_system_return.arm b/ports/cortex_a5/ghs/src/tx_thread_system_return.arm index 4d7cc93d..4e7a0f60 100644 --- a/ports/cortex_a5/ghs/src/tx_thread_system_return.arm +++ b/ports/cortex_a5/ghs/src/tx_thread_system_return.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a5/ghs/src/tx_thread_vectored_context_save.arm b/ports/cortex_a5/ghs/src/tx_thread_vectored_context_save.arm index 7056e441..f3d2ef20 100644 --- a/ports/cortex_a5/ghs/src/tx_thread_vectored_context_save.arm +++ b/ports/cortex_a5/ghs/src/tx_thread_vectored_context_save.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a5/ghs/src/tx_timer_interrupt.arm b/ports/cortex_a5/ghs/src/tx_timer_interrupt.arm index c85530c8..7592019f 100644 --- a/ports/cortex_a5/ghs/src/tx_timer_interrupt.arm +++ b/ports/cortex_a5/ghs/src/tx_timer_interrupt.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a5/gnu/example_build/MP_GIC.S b/ports/cortex_a5/gnu/example_build/MP_GIC.S index 2ff179fb..a3274f21 100644 --- a/ports/cortex_a5/gnu/example_build/MP_GIC.S +++ b/ports/cortex_a5/gnu/example_build/MP_GIC.S @@ -3,7 +3,7 @@ // // Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports/cortex_a5/gnu/example_build/MP_GIC.h b/ports/cortex_a5/gnu/example_build/MP_GIC.h index 1d047611..42a96c3d 100644 --- a/ports/cortex_a5/gnu/example_build/MP_GIC.h +++ b/ports/cortex_a5/gnu/example_build/MP_GIC.h @@ -4,7 +4,7 @@ // // Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports/cortex_a5/gnu/example_build/MP_PrivateTimer.S b/ports/cortex_a5/gnu/example_build/MP_PrivateTimer.S index 2077d917..58e5afd4 100644 --- a/ports/cortex_a5/gnu/example_build/MP_PrivateTimer.S +++ b/ports/cortex_a5/gnu/example_build/MP_PrivateTimer.S @@ -93,7 +93,7 @@ get_private_timer_count: LDR r0, [r0, #0x604] // Read count register BX lr - + // ------------------------------------------------------------ // void clear_private_timer_irq(void) diff --git a/ports/cortex_a5/gnu/example_build/reset.S b/ports/cortex_a5/gnu/example_build/reset.S index 3ce9efb7..f2e0522b 100644 --- a/ports/cortex_a5/gnu/example_build/reset.S +++ b/ports/cortex_a5/gnu/example_build/reset.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a5/gnu/example_build/sample_threadx.ld b/ports/cortex_a5/gnu/example_build/sample_threadx.ld index cb42c11c..d43e28f1 100644 --- a/ports/cortex_a5/gnu/example_build/sample_threadx.ld +++ b/ports/cortex_a5/gnu/example_build/sample_threadx.ld @@ -7,7 +7,7 @@ OUTPUT_ARCH(arm) SECTIONS { . = 0x00000000; - + .vectors : {reset.o(.text) } /* Read-only sections, merged into text segment: */ @@ -94,8 +94,8 @@ SECTIONS *(.gnu.linkonce.t*) *(.glue_7t) *(.glue_7) } =0 - .init : - { + .init : + { KEEP (*(.init)) } =0 _etext = .; @@ -120,7 +120,7 @@ SECTIONS .data1 : { *(.data1) } .eh_frame : { KEEP (*(.eh_frame)) } .gcc_except_table : { *(.gcc_except_table) } - .ctors : + .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is @@ -153,9 +153,9 @@ SECTIONS /* We want the small data sections together, so single-instruction offsets can access them all, and initialized data all before uninitialized, so we can shorten the on-disk segment size. */ - .sdata : + .sdata : { - *(.sdata) + *(.sdata) *(.sdata.*) *(.gnu.linkonce.s.*) } @@ -191,7 +191,7 @@ SECTIONS _stack_bottom = ABSOLUTE(.) ; - /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and + /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and SYS stack if nested interrupts are enabled. */ . = ALIGN(8) ; . += 4096 ; diff --git a/ports/cortex_a5/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_a5/gnu/example_build/tx_initialize_low_level.S index ed2149dc..ad84429f 100644 --- a/ports/cortex_a5/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_a5/gnu/example_build/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -100,17 +101,6 @@ $_tx_initialize_low_level: /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_initialize_low_level .type _tx_initialize_low_level,function @@ -183,7 +173,7 @@ _stack_error_loop: MOV r0, #0x1F BL setPriorityMask // Set priority mask (local) - // [EL] Change start - don't enable interrupts here! + // [EL] Change start - don't enable interrupts here! //CPSIE i // Clear CPSR I bit // [EL] Change end @@ -246,7 +236,7 @@ __tx_irq_processing_return: if nested IRQ interrupts are desired. Interrupts may be re-enabled over small code sequences where lr is saved before enabling interrupts and restored after interrupts are again disabled. */ - + PUSH {r4, r5} // Save some preserved registers (r5 is saved just for 8-byte alignment) BL readIntAck MOV r4, r0 diff --git a/ports/cortex_a5/gnu/example_build/v7.h b/ports/cortex_a5/gnu/example_build/v7.h index 5a08b43f..c18b945c 100644 --- a/ports/cortex_a5/gnu/example_build/v7.h +++ b/ports/cortex_a5/gnu/example_build/v7.h @@ -4,7 +4,7 @@ // // Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports/cortex_a5/gnu/example_build/v7.s b/ports/cortex_a5/gnu/example_build/v7.s index 82c9ab1e..9487ddde 100644 --- a/ports/cortex_a5/gnu/example_build/v7.s +++ b/ports/cortex_a5/gnu/example_build/v7.s @@ -3,7 +3,7 @@ // // Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ @@ -20,7 +20,7 @@ enableInterrupts: CPSIE i BX lr - + .global disableInterrupts .type disableInterrupts,function @@ -28,7 +28,7 @@ enableInterrupts: disableInterrupts: CPSID i BX lr - + // ------------------------------------------------------------ // Cache Maintenance @@ -44,7 +44,7 @@ enableCaches: MCR p15, 0, r0, c1, c0, 0 // Write System Control Register ISB BX lr - + .global disableCaches @@ -57,7 +57,7 @@ disableCaches: MCR p15, 0, r0, c1, c0, 0 // Write System Control Register ISB BX lr - + .global cleanDCache @@ -114,7 +114,7 @@ clean_dcache_finished: POP {r4-r12} BX lr - + .global cleanInvalidateDCache .type cleanInvalidateDCache,function @@ -170,7 +170,7 @@ clean_invalidate_dcache_finished: POP {r4-r12} BX lr - + .global invalidateCaches @@ -229,7 +229,7 @@ invalidate_caches_skip: invalidate_caches_finished: POP {r4-r12} BX lr - + .global invalidateCaches_IS @@ -284,7 +284,7 @@ invalidate_caches_is_skip: invalidate_caches_is_finished: POP {r4-r12} BX lr - + // ------------------------------------------------------------ // TLB @@ -297,7 +297,7 @@ invalidateUnifiedTLB: MOV r0, #0 MCR p15, 0, r0, c8, c7, 0 // TLBIALL - Invalidate entire unified TLB BX lr - + .global invalidateUnifiedTLB_IS .type invalidateUnifiedTLB_IS,function @@ -306,7 +306,7 @@ invalidateUnifiedTLB_IS: MOV r0, #1 MCR p15, 0, r0, c8, c3, 0 // TLBIALLIS - Invalidate entire unified TLB Inner Shareable BX lr - + // ------------------------------------------------------------ // Branch Prediction @@ -319,7 +319,7 @@ flushBranchTargetCache: MOV r0, #0 MCR p15, 0, r0, c7, c5, 6 // BPIALL - Invalidate entire branch predictor array BX lr - + .global flushBranchTargetCache_IS .type flushBranchTargetCache_IS,function @@ -328,7 +328,7 @@ flushBranchTargetCache_IS: MOV r0, #0 MCR p15, 0, r0, c7, c1, 6 // BPIALLIS - Invalidate entire branch predictor array Inner Shareable BX lr - + // ------------------------------------------------------------ // High Vecs @@ -343,7 +343,7 @@ enableHighVecs: MCR p15, 0, r0, c1, c0, 0 // Write Control Register ISB BX lr - + .global disableHighVecs .type disableHighVecs,function @@ -354,7 +354,7 @@ disableHighVecs: MCR p15, 0, r0, c1, c0, 0 // Write Control Register ISB BX lr - + // ------------------------------------------------------------ // Context ID @@ -366,7 +366,7 @@ disableHighVecs: getContextID: MRC p15, 0, r0, c13, c0, 1 // Read Context ID Register BX lr - + .global setContextID .type setContextID,function @@ -374,7 +374,7 @@ getContextID: setContextID: MCR p15, 0, r0, c13, c0, 1 // Write Context ID Register BX lr - + // ------------------------------------------------------------ // ID registers @@ -386,7 +386,7 @@ setContextID: getMIDR: MRC p15, 0, r0, c0, c0, 0 // Read Main ID Register (MIDR) BX lr - + .global getMPIDR .type getMPIDR,function @@ -394,7 +394,7 @@ getMIDR: getMPIDR: MRC p15, 0, r0, c0 ,c0, 5// Read Multiprocessor ID register (MPIDR) BX lr - + // ------------------------------------------------------------ // CP15 SMP related @@ -407,7 +407,7 @@ getMPIDR: getBaseAddr: MRC p15, 4, r0, c15, c0, 0 // Read peripheral base address BX lr - + // ------------------------------------------------------------ @@ -419,7 +419,7 @@ getCPUID: MRC p15, 0, r0, c0, c0, 5 // Read CPU ID register AND r0, r0, #0x03 // Mask off, leaving the CPU ID field BX lr - + // ------------------------------------------------------------ @@ -431,7 +431,7 @@ goToSleep: WFI // Go into standby B goToSleep // Catch in case of rogue events BX lr - + // ------------------------------------------------------------ @@ -451,7 +451,7 @@ joinSMP: ISB BX lr - + // ------------------------------------------------------------ @@ -469,7 +469,7 @@ leaveSMP: ISB BX lr - + // ------------------------------------------------------------ // End of v7.s diff --git a/ports/cortex_a5/gnu/inc/tx_port.h b/ports/cortex_a5/gnu/inc/tx_port.h index f9b96956..f0153046 100644 --- a/ports/cortex_a5/gnu/inc/tx_port.h +++ b/ports/cortex_a5/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,20 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Updated comments, removed */ -/* unneeded temp variable, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -320,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv7-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a5/gnu/readme_threadx.txt b/ports/cortex_a5/gnu/readme_threadx.txt index 9653bd11..49cad39e 100644 --- a/ports/cortex_a5/gnu/readme_threadx.txt +++ b/ports/cortex_a5/gnu/readme_threadx.txt @@ -1,55 +1,55 @@ - Microsoft's Azure RTOS ThreadX for Cortex-A5 + Microsoft's Azure RTOS ThreadX for Cortex-A5 Using the GNU Tools 1. Building the ThreadX run-time Library -First make sure you are in the "example_build" directory. Also, make sure that -you have setup your path and other environment variables necessary for the GNU -development environment. +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the GNU +development environment. -At this point you may run the build_threadx.bat batch file. This will build the -ThreadX run-time environment in the "example_build" directory. +At this point you may run the build_threadx.bat batch file. This will build the +ThreadX run-time environment in the "example_build" directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. 2. Demonstration System -Building the demonstration is easy; simply execute the build_threadx_sample.bat -batch file while inside the "example_build" directory. +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with TX.A. The resulting file DEMO is a binary file +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with TX.A. The resulting file DEMO is a binary file that can be downloaded and executed. 3. System Initialization -The entry point in ThreadX for the Cortex-A5 using GNU tools is at label _start. +The entry point in ThreadX for the Cortex-A5 using GNU tools is at label _start. This is defined within the modified version of the GNU startup code - crt0.S. -The ThreadX tx_initialize_low_level.S file is responsible for setting up various -system data structures, the interrupt vectors, and a periodic timer interrupt source. -By default, the vector area is defined to be located at the "__vectors" label, -which is defined in reset.S. This area is typically located at 0. In situations -where this is impossible, the vectors at the "__vectors" label should be copied +The ThreadX tx_initialize_low_level.S file is responsible for setting up various +system data structures, the interrupt vectors, and a periodic timer interrupt source. +By default, the vector area is defined to be located at the "__vectors" label, +which is defined in reset.S. This area is typically located at 0. In situations +where this is impossible, the vectors at the "__vectors" label should be copied to address 0. -This is also where initialization of a periodic timer interrupt source should take +This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level defines the first available address -for use by the application, which is supplied as the sole input parameter +In addition, _tx_initialize_low_level defines the first available address +for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 4. Assembler / Compiler Switches -The following are compiler switches used in building the demonstration +The following are compiler switches used in building the demonstration system: Compiler/Assembler Meaning @@ -73,164 +73,164 @@ Application Defines ( -D option) ThreadX assembly files. If used, it should be used on all assembly files and the generic C source of - ThreadX should be compiled with + ThreadX should be compiled with TX_ENABLE_FIQ_SUPPORT defined as well. TX_ENABLE_IRQ_NESTING This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.S. TX_ENABLE_FIQ_NESTING This assembler define enables FIQ - nested support. If FIQ nested + nested support. If FIQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.S. In addition, IRQ nesting should also be enabled. TX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ interrupt handling in the ThreadX - generic C source. This define + generic C source. This define should also be used in conjunction with the corresponding assembler - define. + define. TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - TX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. 5. Register Usage and Stack Frames -The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -248,52 +248,52 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A5 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-A5 vectors start at address zero. The demonstration system startup -reset.S file contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +reset.S file contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs -ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -301,7 +301,7 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -314,7 +314,7 @@ __tx_irq_processing_return: 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_example_handler @@ -324,12 +324,12 @@ __tx_irq_example_handler: STMDB sp!, {r0-r3} @ Save some scratch registers MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers BL _tx_thread_vectored_context_save @ Call the vectored IRQ context save @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -346,22 +346,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.S. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables -nesting by disabling IRQ interrupts and switching back to IRQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -369,10 +369,10 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* Enable nested IRQ interrupts. NOTE: Since this service returns -@ with IRQ interrupts enabled, all IRQ interrupt sources must be +@ with IRQ interrupts enabled, all IRQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start -@ +@ @ /* Application ISR call(s) go here! */ @ @ /* Disable nested IRQ interrupts. The mode is switched back to @@ -385,12 +385,12 @@ __tx_irq_processing_return: 7.3 FIQ Interrupts -By default, FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.S. @@ -399,7 +399,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.S. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.S: @@ -427,18 +427,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.S. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -454,7 +454,7 @@ __tx_fiq_processing_return: @ interrupt, and all C scratch registers are available for use. */ @ @ /* Enable nested FIQ interrupts. NOTE: Since this service returns -@ with FIQ interrupts enabled, all FIQ interrupt sources must be +@ with FIQ interrupts enabled, all FIQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start @ @@ -470,12 +470,12 @@ __tx_fiq_processing_return: 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer -interrupt source, these services are not functional but the remainder of +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of ThreadX will still run. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.S for the demonstration system. @@ -483,7 +483,7 @@ found in the file tx_initialize_low_level.S for the demonstration system. 9. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); diff --git a/ports/cortex_a5/gnu/src/tx_thread_context_restore.S b/ports/cortex_a5/gnu/src/tx_thread_context_restore.S index 6b4a561d..41b0b0d0 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a5/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,23 +80,6 @@ IRQ_MODE = 0x12 // IRQ mode /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_restore .type _tx_thread_context_restore,function diff --git a/ports/cortex_a5/gnu/src/tx_thread_context_save.S b/ports/cortex_a5/gnu/src/tx_thread_context_save.S index eff06283..d2d29d34 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a5/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,23 +72,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_save .type _tx_thread_context_save,function diff --git a/ports/cortex_a5/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_a5/gnu/src/tx_thread_fiq_context_restore.S index d2fbebe1..921c322c 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a5/gnu/src/tx_thread_fiq_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -78,20 +79,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* FIQ ISR Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_restore .type _tx_thread_fiq_context_restore,function diff --git a/ports/cortex_a5/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_a5/gnu/src/tx_thread_fiq_context_save.S index 88472a3d..2f1a6c40 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a5/gnu/src/tx_thread_fiq_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_save .type _tx_thread_fiq_context_save,function diff --git a/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_end.S index fa3886b8..a7ce701e 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_start.S index dbed1cf2..4f095dde 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a5/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a5/gnu/src/tx_thread_interrupt_control.S index d1223cb8..a5bc47f7 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a5/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,20 +69,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a5/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a5/gnu/src/tx_thread_interrupt_disable.S index a87d1a06..d7b53bc2 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a5/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,20 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a5/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a5/gnu/src/tx_thread_interrupt_restore.S index 53ff2813..3c31e94b 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a5/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,20 +68,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_end.S index 18aebc7c..cc4db3a7 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_start.S index a2ffd35d..3635874d 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a5/gnu/src/tx_thread_schedule.S b/ports/cortex_a5/gnu/src/tx_thread_schedule.S index 19627892..a74e2050 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a5/gnu/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,23 +82,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a5/gnu/src/tx_thread_stack_build.S b/ports/cortex_a5/gnu/src/tx_thread_stack_build.S index 3876225a..827554a7 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a5/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,20 +75,6 @@ CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ int /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a5/gnu/src/tx_thread_system_return.S b/ports/cortex_a5/gnu/src/tx_thread_system_return.S index 0eed478d..1a17446b 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a5/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,23 +69,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a5/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_a5/gnu/src/tx_thread_vectored_context_save.S index fe8a98e8..91653b75 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a5/gnu/src/tx_thread_vectored_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_vectored_context_save .type _tx_thread_vectored_context_save,function diff --git a/ports/cortex_a5/gnu/src/tx_timer_interrupt.S b/ports/cortex_a5/gnu/src/tx_timer_interrupt.S index cb0c1fa2..179ac894 100644 --- a/ports/cortex_a5/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a5/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -77,20 +78,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a5/iar/example_build/cstartup.s b/ports/cortex_a5/iar/example_build/cstartup.s index 647de2e8..b4ed8f87 100644 --- a/ports/cortex_a5/iar/example_build/cstartup.s +++ b/ports/cortex_a5/iar/example_build/cstartup.s @@ -1,7 +1,7 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; -;; Part one of the system initialization code, +;; Part one of the system initialization code, ;; contains low-level ;; initialization. ;; @@ -71,13 +71,13 @@ FIQ_Addr: DCD __tx_fiq_handler SECTION .text:CODE:NOROOT(2) -; PUBLIC ?cstartup +; PUBLIC ?cstartup EXTERN ?main REQUIRE __vector - ARM - -__iar_program_start: + ARM + +__iar_program_start: ?cstartup: ; diff --git a/ports/cortex_a5/iar/example_build/sample_threadx.c b/ports/cortex_a5/iar/example_build/sample_threadx.c index 68cd97fe..56f7cd55 100644 --- a/ports/cortex_a5/iar/example_build/sample_threadx.c +++ b/ports/cortex_a5/iar/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -85,42 +85,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -128,23 +128,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -247,11 +247,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -310,7 +310,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -363,7 +363,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_a5/iar/example_build/tx_initialize_low_level.s b/ports/cortex_a5/iar/example_build/tx_initialize_low_level.s index ca458fd3..3ca83a9f 100644 --- a/ports/cortex_a5/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_a5/iar/example_build/tx_initialize_low_level.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -62,7 +62,7 @@ SYS_MODE DEFINE 0xDF ; Disable irq,fiq SYS mode ; ; ; -;/* Define the FREE_MEM segment that will specify where free memory is +;/* Define the FREE_MEM segment that will specify where free memory is ; defined. This must also be located in at the end of other RAM segments ; in the linker control file. The value of this segment is what is passed ; to tx_application_define. */ @@ -75,45 +75,39 @@ __tx_free_memory_start ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-A5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-A5/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -146,7 +140,7 @@ _tx_initialize_low_level ; LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address STR r0, [r2, #0] ; Save first free memory address -; +; ; /* Setup Timer for periodic interrupts. */ ; ; /* Done, return to caller. */ @@ -188,7 +182,7 @@ __tx_reserved_handler RSEG .text:CODE:NOROOT(2) PUBLIC __tx_irq_handler RSEG .text:CODE:NOROOT(2) - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -196,17 +190,17 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -221,7 +215,7 @@ __tx_irq_processing_return ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -240,22 +234,22 @@ __tx_irq_processing_return ; /* Jump to context save to save system context. */ ; STMDB sp!, {r0-r3} ; Save some scratch registers ; MRS r0, SPSR ; Pickup saved SPSR -; SUB lr, lr, #4 ; Adjust point of interrupt +; SUB lr, lr, #4 ; Adjust point of interrupt ; STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; BL _tx_thread_vectored_context_save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ;#ifdef TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_start @@ -264,7 +258,7 @@ __tx_irq_processing_return ; /* Application IRQ handler is called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ;#ifdef TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_end @@ -288,11 +282,11 @@ __tx_fiq_processing_return ; /* At this point execution is still in the FIQ mode. The CPSR, point of ; interrupt, and all C scratch registers are available for use. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start ; from FIQ mode with interrupts disabled. This routine switches to the -; system mode and returns with FIQ interrupts enabled. +; system mode and returns with FIQ interrupts enabled. ; -; NOTE: It is very important to ensure all FIQ interrupts are cleared +; NOTE: It is very important to ensure all FIQ interrupts are cleared ; prior to enabling nested FIQ interrupts. */ #ifdef TX_ENABLE_FIQ_NESTING BL _tx_thread_fiq_nesting_start diff --git a/ports/cortex_a5/iar/inc/tx_port.h b/ports/cortex_a5/iar/inc/tx_port.h index 74f6194a..5ce81a27 100644 --- a/ports/cortex_a5/iar/inc/tx_port.h +++ b/ports/cortex_a5/iar/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Cortex-A5/IAR */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A5/IAR */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -79,7 +71,7 @@ #endif -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -115,12 +107,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -130,8 +122,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -188,7 +180,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -202,18 +194,18 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ - VOID *tx_thread_iar_tls_pointer; + VOID *tx_thread_iar_tls_pointer; #else #define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; #endif -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -227,11 +219,11 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -241,23 +233,23 @@ ULONG _tx_misra_time_stamp_get(VOID); #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #if (__VER__ < 8000000) -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #endif #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -285,8 +277,8 @@ void __iar_Initlocks(void); #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -297,22 +289,22 @@ void __iar_Initlocks(void); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (UINT) __CLZ(m); \ - b = 31 - b; + b = 31 - b; #endif #endif #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ /* First, check and see what mode the file is being compiled in. The IAR compiler - defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode + defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode is present. If ARM 32-bit mode is present, the fast CPSR manipulation macros are available. Otherwise, if Thumb mode is present, we must use function calls. */ @@ -381,8 +373,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-A5/IAR Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A5/IAR Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_a5/iar/readme_threadx.txt b/ports/cortex_a5/iar/readme_threadx.txt index dc62701c..6066b56b 100644 --- a/ports/cortex_a5/iar/readme_threadx.txt +++ b/ports/cortex_a5/iar/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for Cortex-A5 + Microsoft's Azure RTOS ThreadX for Cortex-A5 Thumb & 32-bit Mode @@ -7,10 +7,10 @@ 1. Building the ThreadX run-time Library Building the ThreadX library is easy. First, open the Azure RTOS workspace -azure_rtos.eww. Next, make the TX project the "active project" in the -IAR Embedded Workbench and select the "Make" button. You should observe -assembly and compilation of a series of ThreadX source files. This -results in the ThreadX run-time library file tx.a, which is needed by +azure_rtos.eww. Next, make the TX project the "active project" in the +IAR Embedded Workbench and select the "Make" button. You should observe +assembly and compilation of a series of ThreadX source files. This +results in the ThreadX run-time library file tx.a, which is needed by the application. @@ -20,47 +20,47 @@ The ThreadX demonstration is designed to execute under the IAR Windows-based Cortex-A5 simulator. Building the demonstration is easy; simply make the sample_threadx.ewp project -the "active project" in the IAR Embedded Workbench and select the +the "active project" in the IAR Embedded Workbench and select the "Make" button. -You should observe the compilation of sample_threadx.c (which is the demonstration +You should observe the compilation of sample_threadx.c (which is the demonstration application) and linking with tx.a. The resulting file sample_threadx.out is a binary file that can be downloaded and executed on IAR's Cortex-A5 simulator. 3. System Initialization -The entry point in ThreadX for the Cortex-A5 using IAR tools is at label -?cstartup. This is defined within the IAR compiler's startup code. In -addition, this is where all static and global preset C variable +The entry point in ThreadX for the Cortex-A5 using IAR tools is at label +?cstartup. This is defined within the IAR compiler's startup code. In +addition, this is where all static and global preset C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, and a periodic timer interrupt source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. By default, the vector area is defined at the top of cstartup.s, which is -a slightly modified from the base IAR file. +a slightly modified from the base IAR file. The _tx_initialize_low_level function inside of tx_initialize_low_level.s -also determines the first available address for use by the application, which -is supplied as the sole input parameter to your application definition function, -tx_application_define. To accomplish this, a section is created in -tx_initialize_low_level.s called FREE_MEM, which must be located after all +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all other RAM sections in memory. 4. Register Usage and Stack Frames -The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are -scratch registers for each function. All other registers used by a C function -must be preserved by the function. ThreadX takes advantage of this in -situations where a context switch happens as a result of making a ThreadX -service call (which is itself a C function). In such cases, the saved +The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are +scratch registers for each function. All other registers used by a C function +must be preserved by the function. ThreadX takes advantage of this in +situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -78,12 +78,12 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 5. Conditional Compilation Switches @@ -92,146 +92,146 @@ The following are conditional compilation options for building the ThreadX libra and application: - TX_ENABLE_FIQ_SUPPORT This assembler/compiler define enables + TX_ENABLE_FIQ_SUPPORT This assembler/compiler define enables FIQ interrupt handling support in the ThreadX assembly files. If used, it should be used on all assembly files and the generic C source of - ThreadX should be compiled with + ThreadX should be compiled with TX_ENABLE_FIQ_SUPPORT defined as well. TX_ENABLE_IRQ_NESTING This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. TX_ENABLE_FIQ_NESTING This assembler define enables FIQ - nested support. If FIQ nested + nested support. If FIQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. In addition, IRQ nesting should also be enabled. TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - TX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. TX_THUMB Defined, this option enables the BX LR calling return sequence @@ -245,29 +245,29 @@ and application: 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the ThreadX library -project to enable various compiler optimizations. +project to enable various compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A5 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-A5 vectors start at address zero. The demonstration system startup -cstartup.s file contains the vectors and is loaded at address zero. -On actual hardware platforms, this area might have to be copied to address 0. +cstartup.s file contains the vectors and is loaded at address zero. +On actual hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs @@ -278,12 +278,12 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.s: PUBLIC __tx_irq_handler - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -291,7 +291,7 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -304,7 +304,7 @@ __tx_irq_processing_return 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.s: @@ -315,12 +315,12 @@ __tx_example_vectored_irq_handler ; /* Jump to context save to save system context. */ STMDB sp!, {r0-r3} ; Save some scratch registers MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers BL _tx_thread_vectored_context_save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -337,24 +337,24 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.s. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables -nesting by disabling IRQ interrupts and switching back to IRQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: RSEG .text:CODE:NOROOT(2) PUBLIC __tx_irq_handler RSEG .text:CODE:NOROOT(2) - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -362,15 +362,15 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ; BL _tx_thread_irq_nesting_start @@ -378,7 +378,7 @@ __tx_irq_processing_return ; /* Application ISR dispatch call goes here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ; BL _tx_thread_irq_nesting_end @@ -389,12 +389,12 @@ __tx_irq_processing_return 7.3 FIQ Interrupts -By default, Cortex-A5 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, Cortex-A5 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.s. @@ -403,7 +403,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.s. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.s: @@ -434,18 +434,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.s. When nested FIQ interrupts are no -longer required, calling the _tx_thread_fiq_nesting_end service disables -nesting by disabling FIQ interrupts and switching back to FIQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested FIQ interrupts are no +longer required, calling the _tx_thread_fiq_nesting_end service disables +nesting by disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -463,7 +463,7 @@ __tx_fiq_processing_return: ; interrupt, and all C scratch registers are available for use. */ ; ; /* Enable nested FIQ interrupts. NOTE: Since this service returns -; with FIQ interrupts enabled, all FIQ interrupt sources must be +; with FIQ interrupts enabled, all FIQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start ; @@ -479,22 +479,22 @@ __tx_fiq_processing_return: 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to _tx_timer_interrupt +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. 9. Thumb/Cortex-A5 Mixed Mode -By default, ThreadX is setup for running in Cortex-A5 32-bit mode. This is -also true for the demonstration system. It is possible to build any +By default, ThreadX is setup for running in Cortex-A5 32-bit mode. This is +also true for the demonstration system. It is possible to build any ThreadX file and/or the application in Thumb mode. The only exception -to this is the file tx_thread_shell_entry.c. This file must always be -built in 32-bit mode. In addition, if any Thumb code is used the entire +to this is the file tx_thread_shell_entry.c. This file must always be +built in 32-bit mode. In addition, if any Thumb code is used the entire ThreadX assembly source should be built with TX_THUMB defined. @@ -506,14 +506,14 @@ should have the following line added (if not already in place): initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application -The project options "General Options -> Library Configuration" should also have the +The project options "General Options -> Library Configuration" should also have the "Enable thread support in library" box selected. 11. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); diff --git a/ports/cortex_a5/iar/src/tx_iar.c b/ports/cortex_a5/iar/src/tx_iar.c index 158738ea..238b485e 100644 --- a/ports/cortex_a5/iar/src/tx_iar.c +++ b/ports/cortex_a5/iar/src/tx_iar.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** IAR Multithreaded Library Support */ /** */ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports/cortex_a5/iar/src/tx_thread_context_restore.s b/ports/cortex_a5/iar/src/tx_thread_context_restore.s index c54bd762..5d8a88c2 100644 --- a/ports/cortex_a5/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_a5/iar/src/tx_thread_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,7 +36,7 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask THUMB_MASK DEFINE 0x20 ; Thumb bit mask SVC_MODE_BITS DEFINE 0x13 ; SVC mode value @@ -51,47 +51,38 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore Cortex-A5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-A5/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -121,13 +112,13 @@ _tx_thread_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3, #0] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3, #0] ; Store the counter + STR r2, [r3, #0] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -193,7 +184,7 @@ __tx_thread_preempt_restore LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer - + #ifdef __ARMVFP__ LDR r2, [r0, #144] ; Pickup the VFP enabled flag CMP r2, #0 ; Is the VFP enabled? @@ -206,7 +197,7 @@ __tx_thread_preempt_restore VSTMDB sp!, {D0-D15} ; Save D0-D15 _tx_skip_fiq_vfp_save: #endif - + MOV r3, #1 ; Build interrupt stack type STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR STR sp, [r0, #8] ; Save stack pointer in thread control diff --git a/ports/cortex_a5/iar/src/tx_thread_context_save.s b/ports/cortex_a5/iar/src/tx_thread_context_save.s index 493a0965..daa758ff 100644 --- a/ports/cortex_a5/iar/src/tx_thread_context_save.s +++ b/ports/cortex_a5/iar/src/tx_thread_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -43,46 +43,37 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled EXTERN _tx_execution_isr_enter ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save Cortex-A5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-A5/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -99,7 +90,7 @@ _tx_thread_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt CPSR @@ -119,7 +110,7 @@ _tx_thread_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -135,7 +126,7 @@ _tx_thread_context_save POP {lr} ; Recover ISR lr #endif - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; __tx_thread_not_nested_save ; } @@ -149,13 +140,13 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} ; Store other registers ; ; /* Save the current stack pointer in the thread's control block. */ @@ -175,7 +166,7 @@ __tx_thread_not_nested_save POP {lr} ; Recover ISR lr #endif - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ; else @@ -185,7 +176,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit @@ -200,7 +191,7 @@ __tx_thread_idle_system_save #endif ADD sp, sp, #16 ; Recover saved registers - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ;} diff --git a/ports/cortex_a5/iar/src/tx_thread_fiq_context_restore.s b/ports/cortex_a5/iar/src/tx_thread_fiq_context_restore.s index e040244c..549c3fff 100644 --- a/ports/cortex_a5/iar/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_a5/iar/src/tx_thread_fiq_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -37,7 +37,7 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask THUMB_MASK DEFINE 0x20 ; Thumb bit mask IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits SVC_MODE_BITS DEFINE 0x13 ; SVC mode value @@ -52,47 +52,38 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value EXTERN _tx_execution_isr_exit ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_restore Cortex-A5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore Cortex-A5/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the fiq interrupt context when processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* FIQ ISR Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) @@ -122,13 +113,13 @@ _tx_thread_fiq_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3] ; Store the counter + STR r2, [r3] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -172,7 +163,7 @@ __tx_thread_fiq_no_preempt_restore ; /* Restore interrupted thread or ISR. */ ; ; /* Pickup the saved stack pointer. */ -; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; ; ; /* Recover the saved context and return to the point of interrupt. */ ; @@ -234,7 +225,7 @@ _tx_skip_irq_vfp_save: BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it ; ; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; -; _tx_timer_time_slice = 0; +; _tx_timer_time_slice = 0; ; STR r2, [r0, #24] ; Save thread's time-slice MOV r2, #0 ; Clear value diff --git a/ports/cortex_a5/iar/src/tx_thread_fiq_context_save.s b/ports/cortex_a5/iar/src/tx_thread_fiq_context_save.s index f1510e0d..c140517f 100644 --- a/ports/cortex_a5/iar/src/tx_thread_fiq_context_save.s +++ b/ports/cortex_a5/iar/src/tx_thread_fiq_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,46 +36,37 @@ EXTERN _tx_execution_isr_enter ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_save Cortex-A5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save Cortex-A5/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) @@ -92,7 +83,7 @@ _tx_thread_fiq_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state CMP r2, #0 ; Is this the first interrupt? @@ -107,7 +98,7 @@ _tx_thread_fiq_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -123,38 +114,38 @@ _tx_thread_fiq_context_save POP {lr} ; Recover ISR lr #endif - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; __tx_thread_fiq_not_nested_save -; } +; } ; ; /* Otherwise, not nested, check to see if a thread was running. */ ; else if (_tx_thread_current_ptr) -; { +; { ; ADD r2, r2, #1 ; Increment the interrupt counter STR r2, [r3] ; Store it back in the variable LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in -; ; scheduling loop - nothing needs saving! + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, lr} ; Store other registers, Note that we don't -; ; need to save sl and ip since FIQ has -; ; copies of these registers. Nested +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested ; ; interrupt processing does need to save ; ; these registers. ; ; /* Save the current stack pointer in the thread's control block. */ -; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; ; ; /* Switch to the system stack. */ -; sp = _tx_thread_system_stack_ptr; +; sp = _tx_thread_system_stack_ptr; ; MOV r10, #0 ; Clear stack limit @@ -167,7 +158,7 @@ __tx_thread_fiq_not_nested_save POP {lr} ; Recover ISR lr #endif - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } ; else @@ -187,18 +178,18 @@ __tx_thread_fiq_idle_system_save #endif ; ; /* Not much to do here, save the current SPSR and LR for possible -; use in IRQ interrupted in idle system conditions, and return to +; use in IRQ interrupted in idle system conditions, and return to ; FIQ interrupt processing. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, lr} ; Store other registers that will get used -; ; or stripped off the stack in context -; ; restore - B __tx_fiq_processing_return ; Continue FIQ processing +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } -;} +;} ; ; END diff --git a/ports/cortex_a5/iar/src/tx_thread_fiq_nesting_end.s b/ports/cortex_a5/iar/src/tx_thread_fiq_nesting_end.s index 3b83f0e3..6687874f 100644 --- a/ports/cortex_a5/iar/src/tx_thread_fiq_nesting_end.s +++ b/ports/cortex_a5/iar/src/tx_thread_fiq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,55 +34,49 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_end Cortex-A5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end Cortex-A5/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ -;/* processing from system mode back to FIQ mode prior to the ISR */ -;/* calling _tx_thread_fiq_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s79). */ -;/* */ -;/* This function returns with FIQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/cortex_a5/iar/src/tx_thread_fiq_nesting_start.s b/ports/cortex_a5/iar/src/tx_thread_fiq_nesting_start.s index 68f9eba6..e86e0cf3 100644 --- a/ports/cortex_a5/iar/src/tx_thread_fiq_nesting_start.s +++ b/ports/cortex_a5/iar/src/tx_thread_fiq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ MODE_MASK DEFINE 0x1F ; Mode mask SYS_MODE_BITS DEFINE 0x1F ; System mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_start Cortex-A5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start Cortex-A5/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ -;/* processing to the system mode so nested FIQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s79). */ -;/* */ -;/* This function returns with FIQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_a5/iar/src/tx_thread_interrupt_control.s b/ports/cortex_a5/iar/src/tx_thread_interrupt_control.s index d1d8437e..5e2938b3 100644 --- a/ports/cortex_a5/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_a5/iar/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,42 +35,36 @@ INT_MASK DEFINE 0x80 ; Interrupt bit mask #endif ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control Cortex-A5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-A5/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a5/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_a5/iar/src/tx_thread_interrupt_disable.s index b9a39960..519d0154 100644 --- a/ports/cortex_a5/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_a5/iar/src/tx_thread_interrupt_disable.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,41 +36,35 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable Cortex-A5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-A5/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_a5/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_a5/iar/src/tx_thread_interrupt_restore.s index 4b97a6c4..c489feb0 100644 --- a/ports/cortex_a5/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_a5/iar/src/tx_thread_interrupt_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -28,42 +28,36 @@ ;#include "tx_thread.h" ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore Cortex-A5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-A5/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function is responsible for restoring interrupts to the state */ ;/* returned by a previous _tx_thread_interrupt_disable call. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;void _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a5/iar/src/tx_thread_irq_nesting_end.s b/ports/cortex_a5/iar/src/tx_thread_irq_nesting_end.s index a5a6f15f..9a7d9441 100644 --- a/ports/cortex_a5/iar/src/tx_thread_irq_nesting_end.s +++ b/ports/cortex_a5/iar/src/tx_thread_irq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,55 +35,49 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_end Cortex-A5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-A5/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -;/* processing from system mode back to IRQ mode prior to the ISR */ -;/* calling _tx_thread_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s79). */ -;/* */ -;/* This function returns with IRQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_a5/iar/src/tx_thread_irq_nesting_start.s b/ports/cortex_a5/iar/src/tx_thread_irq_nesting_start.s index 8c424974..6f2c34bd 100644 --- a/ports/cortex_a5/iar/src/tx_thread_irq_nesting_start.s +++ b/ports/cortex_a5/iar/src/tx_thread_irq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ MODE_MASK DEFINE 0x1F ; Mode mask SYS_MODE_BITS DEFINE 0x1F ; System mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_start Cortex-A5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-A5/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_context_save has been called and switches the IRQ */ -;/* processing to the system mode so nested IRQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s79). */ -;/* */ -;/* This function returns with IRQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_a5/iar/src/tx_thread_schedule.s b/ports/cortex_a5/iar/src/tx_thread_schedule.s index 2390c450..9046c40a 100644 --- a/ports/cortex_a5/iar/src/tx_thread_schedule.s +++ b/ports/cortex_a5/iar/src/tx_thread_schedule.s @@ -1,19 +1,19 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors -; * +; * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -44,48 +44,39 @@ ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule Cortex-A5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-A5/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -115,7 +106,7 @@ __tx_thread_schedule_loop ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Lockout interrupts and ; transfer control to it. */ ; @@ -124,7 +115,7 @@ __tx_thread_schedule_loop ; /* Setup the current thread pointer. */ ; _tx_thread_current_ptr = _tx_thread_execute_ptr; ; - LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread STR r0, [r1, #0] ; Setup current thread pointer ; ; /* Increment the run count for this thread. */ @@ -138,7 +129,7 @@ __tx_thread_schedule_loop ; /* Setup time-slice, if present. */ ; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; ; - LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice ; variable LDR sp, [r0, #8] ; Switch stack pointers STR r3, [r2, #0] ; Setup time-slice @@ -203,7 +194,7 @@ _tx_skip_solicited_vfp_restore: #ifdef __ARMVFP__ PUBLIC tx_thread_vfp_enable CODE32 -tx_thread_vfp_enable??rA +tx_thread_vfp_enable??rA tx_thread_vfp_enable MRS r2, CPSR ; Pickup the CPSR #ifdef TX_ENABLE_FIQ_SUPPORT @@ -223,7 +214,7 @@ __tx_no_thread_to_enable: PUBLIC tx_thread_vfp_disable CODE32 -tx_thread_vfp_disable??rA +tx_thread_vfp_disable??rA tx_thread_vfp_disable MRS r2, CPSR ; Pickup the CPSR #ifdef TX_ENABLE_FIQ_SUPPORT diff --git a/ports/cortex_a5/iar/src/tx_thread_stack_build.s b/ports/cortex_a5/iar/src/tx_thread_stack_build.s index 98039b47..8edefc2c 100644 --- a/ports/cortex_a5/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_a5/iar/src/tx_thread_stack_build.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -37,58 +37,52 @@ CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints en #endif ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build Cortex-A5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-A5/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function builds a stack frame on the supplied thread's stack. */ ;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ ;/* thread_ptr Pointer to thread control blk */ ;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) ;{ RSEG .text:CODE:NOROOT(2) PUBLIC _tx_thread_stack_build - + CODE32 _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-A5 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; a1 (r0) Initial value for a1 diff --git a/ports/cortex_a5/iar/src/tx_thread_system_return.s b/ports/cortex_a5/iar/src/tx_thread_system_return.s index 32af6cec..62a7f0b0 100644 --- a/ports/cortex_a5/iar/src/tx_thread_system_return.s +++ b/ports/cortex_a5/iar/src/tx_thread_system_return.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -42,47 +42,38 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return Cortex-A5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-A5/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -115,7 +106,7 @@ _tx_skip_solicited_vfp_save: MOV r0, #0 ; Build a solicited stack type MRS r1, CPSR ; Pickup the CPSR STMDB sp!, {r0-r1} ; Save type and CPSR -; +; ; /* Lockout interrupts. */ ; ORR r2, r1, #DISABLE_INTS ; Build disable interrupt CPSR diff --git a/ports/cortex_a5/iar/src/tx_thread_vectored_context_save.s b/ports/cortex_a5/iar/src/tx_thread_vectored_context_save.s index f928253d..40cabfcb 100644 --- a/ports/cortex_a5/iar/src/tx_thread_vectored_context_save.s +++ b/ports/cortex_a5/iar/src/tx_thread_vectored_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -41,46 +41,37 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled EXTERN _tx_execution_isr_enter ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_vectored_context_save Cortex-A5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-A5/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) @@ -142,7 +133,7 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in ; scheduling loop - nothing needs saving! ; ; /* Note: Minimal context of interrupted thread is already saved. */ @@ -174,7 +165,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports/cortex_a5/iar/src/tx_timer_interrupt.s b/ports/cortex_a5/iar/src/tx_timer_interrupt.s index ddbfda9e..a6889286 100644 --- a/ports/cortex_a5/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_a5/iar/src/tx_timer_interrupt.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -43,46 +43,40 @@ ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt Cortex-A5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-A5/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time-slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time-slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -108,7 +102,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CMP r2, #0 ; Is it non-active? BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing @@ -226,13 +220,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CMP r2, #0 ; See if the flag is set BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing ; diff --git a/ports/cortex_a53/ac6/example_build/sample_threadx/.cproject b/ports/cortex_a53/ac6/example_build/sample_threadx/.cproject index f51a736a..deae61b3 100644 --- a/ports/cortex_a53/ac6/example_build/sample_threadx/.cproject +++ b/ports/cortex_a53/ac6/example_build/sample_threadx/.cproject @@ -1,158 +1,158 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a53/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports/cortex_a53/ac6/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports/cortex_a53/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports/cortex_a53/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports/cortex_a53/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports/cortex_a53/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports/cortex_a53/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports/cortex_a53/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports/cortex_a53/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_a53/ac6/example_build/sample_threadx/sample_threadx.scat index e5783c7c..d8dfde69 100644 --- a/ports/cortex_a53/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports/cortex_a53/ac6/example_build/sample_threadx/sample_threadx.scat @@ -2,7 +2,7 @@ ; Scatter file for Armv8-A Startup code on FVP Base model ; Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************** @@ -25,7 +25,7 @@ LOAD 0x80000000 ; in source code for this to work correctly ; ARM_LIB_HEAP +0 ALIGN 64 EMPTY 0xA0000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary diff --git a/ports/cortex_a53/ac6/example_build/sample_threadx/v8_aarch64.h b/ports/cortex_a53/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports/cortex_a53/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports/cortex_a53/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_a53/ac6/example_build/sample_threadx/v8_mmu.h b/ports/cortex_a53/ac6/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports/cortex_a53/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports/cortex_a53/ac6/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports/cortex_a53/ac6/example_build/tx/.cproject b/ports/cortex_a53/ac6/example_build/tx/.cproject index 35fed0f2..c984b7ff 100644 --- a/ports/cortex_a53/ac6/example_build/tx/.cproject +++ b/ports/cortex_a53/ac6/example_build/tx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a53/ac6/inc/tx_port.h b/ports/cortex_a53/ac6/inc/tx_port.h index a8d3fd48..e5352338 100644 --- a/ports/cortex_a53/ac6/inc/tx_port.h +++ b/ports/cortex_a53/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -369,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a53/ac6/src/tx_initialize_low_level.S b/ports/cortex_a53/ac6/src/tx_initialize_low_level.S index f456574e..7d2a4be3 100644 --- a/ports/cortex_a53/ac6/src/tx_initialize_low_level.S +++ b/ports/cortex_a53/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports/cortex_a53/ac6/src/tx_thread_context_restore.S b/ports/cortex_a53/ac6/src/tx_thread_context_restore.S index 8e0d5515..9ba82827 100644 --- a/ports/cortex_a53/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a53/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_a53/ac6/src/tx_thread_context_save.S b/ports/cortex_a53/ac6/src/tx_thread_context_save.S index 7768efc2..c2395155 100644 --- a/ports/cortex_a53/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a53/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_a53/ac6/src/tx_thread_fp_disable.c b/ports/cortex_a53/ac6/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports/cortex_a53/ac6/src/tx_thread_fp_disable.c +++ b/ports/cortex_a53/ac6/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports/cortex_a53/ac6/src/tx_thread_fp_enable.c b/ports/cortex_a53/ac6/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports/cortex_a53/ac6/src/tx_thread_fp_enable.c +++ b/ports/cortex_a53/ac6/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports/cortex_a53/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a53/ac6/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports/cortex_a53/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a53/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_a53/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a53/ac6/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports/cortex_a53/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a53/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports/cortex_a53/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a53/ac6/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports/cortex_a53/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a53/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports/cortex_a53/ac6/src/tx_thread_schedule.S b/ports/cortex_a53/ac6/src/tx_thread_schedule.S index 4cce4a62..057aa538 100644 --- a/ports/cortex_a53/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a53/ac6/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,18 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_a53/ac6/src/tx_thread_stack_build.S b/ports/cortex_a53/ac6/src/tx_thread_stack_build.S index 6c675d9b..01084da7 100644 --- a/ports/cortex_a53/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a53/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_a53/ac6/src/tx_thread_system_return.S b/ports/cortex_a53/ac6/src/tx_thread_system_return.S index 780bb128..b7593d79 100644 --- a/ports/cortex_a53/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a53/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_a53/ac6/src/tx_timer_interrupt.S b/ports/cortex_a53/ac6/src/tx_timer_interrupt.S index d84245c6..1b80a7f2 100644 --- a/ports/cortex_a53/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a53/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_a53/gnu/example_build/sample_threadx/.cproject b/ports/cortex_a53/gnu/example_build/sample_threadx/.cproject index 1c32cb32..40d4912d 100644 --- a/ports/cortex_a53/gnu/example_build/sample_threadx/.cproject +++ b/ports/cortex_a53/gnu/example_build/sample_threadx/.cproject @@ -1,170 +1,170 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a53/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports/cortex_a53/gnu/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports/cortex_a53/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports/cortex_a53/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports/cortex_a53/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports/cortex_a53/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports/cortex_a53/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports/cortex_a53/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports/cortex_a53/gnu/example_build/sample_threadx/sample_threadx.ld b/ports/cortex_a53/gnu/example_build/sample_threadx/sample_threadx.ld index eec8f12b..3bf47736 100644 --- a/ports/cortex_a53/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports/cortex_a53/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start diff --git a/ports/cortex_a53/gnu/example_build/sample_threadx/startup.S b/ports/cortex_a53/gnu/example_build/sample_threadx/startup.S index b71b45f8..b44806fe 100644 --- a/ports/cortex_a53/gnu/example_build/sample_threadx/startup.S +++ b/ports/cortex_a53/gnu/example_build/sample_threadx/startup.S @@ -328,7 +328,7 @@ el1_entry_aarch64: // // Cortex-A processors automatically invalidate their caches on reset // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). - // It is therefore not necessary for software to invalidate the caches + // It is therefore not necessary for software to invalidate the caches // on startup, however, this is done here in case of a warm reset. bl InvalidateUDCaches tlbi VMALLE1 diff --git a/ports/cortex_a53/gnu/example_build/sample_threadx/v8_aarch64.h b/ports/cortex_a53/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports/cortex_a53/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports/cortex_a53/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_a53/gnu/example_build/sample_threadx/v8_mmu.h b/ports/cortex_a53/gnu/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports/cortex_a53/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports/cortex_a53/gnu/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports/cortex_a53/gnu/example_build/tx/.cproject b/ports/cortex_a53/gnu/example_build/tx/.cproject index f1b8ed5b..9e5a975e 100644 --- a/ports/cortex_a53/gnu/example_build/tx/.cproject +++ b/ports/cortex_a53/gnu/example_build/tx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a53/gnu/inc/tx_port.h b/ports/cortex_a53/gnu/inc/tx_port.h index a8d3fd48..e5352338 100644 --- a/ports/cortex_a53/gnu/inc/tx_port.h +++ b/ports/cortex_a53/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -369,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a53/gnu/src/tx_initialize_low_level.S b/ports/cortex_a53/gnu/src/tx_initialize_low_level.S index 3dce3cea..3025f12b 100644 --- a/ports/cortex_a53/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_a53/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -99,4 +89,4 @@ _tx_initialize_low_level: /* Done, return to caller. */ RET // Return to caller -// } +// } diff --git a/ports/cortex_a53/gnu/src/tx_thread_context_restore.S b/ports/cortex_a53/gnu/src/tx_thread_context_restore.S index 8e0d5515..9ba82827 100644 --- a/ports/cortex_a53/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a53/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_a53/gnu/src/tx_thread_context_save.S b/ports/cortex_a53/gnu/src/tx_thread_context_save.S index 7768efc2..c2395155 100644 --- a/ports/cortex_a53/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a53/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_a53/gnu/src/tx_thread_fp_disable.c b/ports/cortex_a53/gnu/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports/cortex_a53/gnu/src/tx_thread_fp_disable.c +++ b/ports/cortex_a53/gnu/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports/cortex_a53/gnu/src/tx_thread_fp_enable.c b/ports/cortex_a53/gnu/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports/cortex_a53/gnu/src/tx_thread_fp_enable.c +++ b/ports/cortex_a53/gnu/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports/cortex_a53/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a53/gnu/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports/cortex_a53/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a53/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_a53/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a53/gnu/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports/cortex_a53/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a53/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports/cortex_a53/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a53/gnu/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports/cortex_a53/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a53/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports/cortex_a53/gnu/src/tx_thread_schedule.S b/ports/cortex_a53/gnu/src/tx_thread_schedule.S index 4cce4a62..057aa538 100644 --- a/ports/cortex_a53/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a53/gnu/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,18 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_a53/gnu/src/tx_thread_stack_build.S b/ports/cortex_a53/gnu/src/tx_thread_stack_build.S index 6c675d9b..01084da7 100644 --- a/ports/cortex_a53/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a53/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_a53/gnu/src/tx_thread_system_return.S b/ports/cortex_a53/gnu/src/tx_thread_system_return.S index 780bb128..b7593d79 100644 --- a/ports/cortex_a53/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a53/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_a53/gnu/src/tx_timer_interrupt.S b/ports/cortex_a53/gnu/src/tx_timer_interrupt.S index d84245c6..1b80a7f2 100644 --- a/ports/cortex_a53/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a53/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_a55/ac6/example_build/sample_threadx/.cproject b/ports/cortex_a55/ac6/example_build/sample_threadx/.cproject index f4e329dc..96dec1da 100644 --- a/ports/cortex_a55/ac6/example_build/sample_threadx/.cproject +++ b/ports/cortex_a55/ac6/example_build/sample_threadx/.cproject @@ -1,158 +1,158 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a55/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports/cortex_a55/ac6/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports/cortex_a55/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports/cortex_a55/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports/cortex_a55/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports/cortex_a55/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports/cortex_a55/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports/cortex_a55/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports/cortex_a55/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_a55/ac6/example_build/sample_threadx/sample_threadx.scat index e5783c7c..d8dfde69 100644 --- a/ports/cortex_a55/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports/cortex_a55/ac6/example_build/sample_threadx/sample_threadx.scat @@ -2,7 +2,7 @@ ; Scatter file for Armv8-A Startup code on FVP Base model ; Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************** @@ -25,7 +25,7 @@ LOAD 0x80000000 ; in source code for this to work correctly ; ARM_LIB_HEAP +0 ALIGN 64 EMPTY 0xA0000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary diff --git a/ports/cortex_a55/ac6/example_build/sample_threadx/v8_aarch64.h b/ports/cortex_a55/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports/cortex_a55/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports/cortex_a55/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_a55/ac6/example_build/sample_threadx/v8_mmu.h b/ports/cortex_a55/ac6/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports/cortex_a55/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports/cortex_a55/ac6/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports/cortex_a55/ac6/example_build/tx/.cproject b/ports/cortex_a55/ac6/example_build/tx/.cproject index 0d6f5a10..9345d698 100644 --- a/ports/cortex_a55/ac6/example_build/tx/.cproject +++ b/ports/cortex_a55/ac6/example_build/tx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a55/ac6/inc/tx_port.h b/ports/cortex_a55/ac6/inc/tx_port.h index a8d3fd48..e5352338 100644 --- a/ports/cortex_a55/ac6/inc/tx_port.h +++ b/ports/cortex_a55/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -369,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a55/ac6/src/tx_initialize_low_level.S b/ports/cortex_a55/ac6/src/tx_initialize_low_level.S index f456574e..7d2a4be3 100644 --- a/ports/cortex_a55/ac6/src/tx_initialize_low_level.S +++ b/ports/cortex_a55/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports/cortex_a55/ac6/src/tx_thread_context_restore.S b/ports/cortex_a55/ac6/src/tx_thread_context_restore.S index 8e0d5515..9ba82827 100644 --- a/ports/cortex_a55/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a55/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_a55/ac6/src/tx_thread_context_save.S b/ports/cortex_a55/ac6/src/tx_thread_context_save.S index 7768efc2..c2395155 100644 --- a/ports/cortex_a55/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a55/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_a55/ac6/src/tx_thread_fp_disable.c b/ports/cortex_a55/ac6/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports/cortex_a55/ac6/src/tx_thread_fp_disable.c +++ b/ports/cortex_a55/ac6/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports/cortex_a55/ac6/src/tx_thread_fp_enable.c b/ports/cortex_a55/ac6/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports/cortex_a55/ac6/src/tx_thread_fp_enable.c +++ b/ports/cortex_a55/ac6/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports/cortex_a55/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a55/ac6/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports/cortex_a55/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a55/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_a55/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a55/ac6/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports/cortex_a55/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a55/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports/cortex_a55/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a55/ac6/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports/cortex_a55/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a55/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports/cortex_a55/ac6/src/tx_thread_schedule.S b/ports/cortex_a55/ac6/src/tx_thread_schedule.S index 4cce4a62..057aa538 100644 --- a/ports/cortex_a55/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a55/ac6/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,18 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_a55/ac6/src/tx_thread_stack_build.S b/ports/cortex_a55/ac6/src/tx_thread_stack_build.S index 6c675d9b..01084da7 100644 --- a/ports/cortex_a55/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a55/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_a55/ac6/src/tx_thread_system_return.S b/ports/cortex_a55/ac6/src/tx_thread_system_return.S index 780bb128..b7593d79 100644 --- a/ports/cortex_a55/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a55/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_a55/ac6/src/tx_timer_interrupt.S b/ports/cortex_a55/ac6/src/tx_timer_interrupt.S index d84245c6..1b80a7f2 100644 --- a/ports/cortex_a55/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a55/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_a55/gnu/example_build/sample_threadx/.cproject b/ports/cortex_a55/gnu/example_build/sample_threadx/.cproject index 1c32cb32..40d4912d 100644 --- a/ports/cortex_a55/gnu/example_build/sample_threadx/.cproject +++ b/ports/cortex_a55/gnu/example_build/sample_threadx/.cproject @@ -1,170 +1,170 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a55/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports/cortex_a55/gnu/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports/cortex_a55/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports/cortex_a55/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports/cortex_a55/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports/cortex_a55/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports/cortex_a55/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports/cortex_a55/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports/cortex_a55/gnu/example_build/sample_threadx/sample_threadx.ld b/ports/cortex_a55/gnu/example_build/sample_threadx/sample_threadx.ld index eec8f12b..3bf47736 100644 --- a/ports/cortex_a55/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports/cortex_a55/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start diff --git a/ports/cortex_a55/gnu/example_build/sample_threadx/startup.S b/ports/cortex_a55/gnu/example_build/sample_threadx/startup.S index b71b45f8..b44806fe 100644 --- a/ports/cortex_a55/gnu/example_build/sample_threadx/startup.S +++ b/ports/cortex_a55/gnu/example_build/sample_threadx/startup.S @@ -328,7 +328,7 @@ el1_entry_aarch64: // // Cortex-A processors automatically invalidate their caches on reset // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). - // It is therefore not necessary for software to invalidate the caches + // It is therefore not necessary for software to invalidate the caches // on startup, however, this is done here in case of a warm reset. bl InvalidateUDCaches tlbi VMALLE1 diff --git a/ports/cortex_a55/gnu/example_build/sample_threadx/v8_aarch64.h b/ports/cortex_a55/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports/cortex_a55/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports/cortex_a55/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_a55/gnu/example_build/sample_threadx/v8_mmu.h b/ports/cortex_a55/gnu/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports/cortex_a55/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports/cortex_a55/gnu/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports/cortex_a55/gnu/example_build/tx/.cproject b/ports/cortex_a55/gnu/example_build/tx/.cproject index f1b8ed5b..9e5a975e 100644 --- a/ports/cortex_a55/gnu/example_build/tx/.cproject +++ b/ports/cortex_a55/gnu/example_build/tx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a55/gnu/inc/tx_port.h b/ports/cortex_a55/gnu/inc/tx_port.h index a8d3fd48..e5352338 100644 --- a/ports/cortex_a55/gnu/inc/tx_port.h +++ b/ports/cortex_a55/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -369,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a55/gnu/src/tx_initialize_low_level.S b/ports/cortex_a55/gnu/src/tx_initialize_low_level.S index 3dce3cea..3025f12b 100644 --- a/ports/cortex_a55/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_a55/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -99,4 +89,4 @@ _tx_initialize_low_level: /* Done, return to caller. */ RET // Return to caller -// } +// } diff --git a/ports/cortex_a55/gnu/src/tx_thread_context_restore.S b/ports/cortex_a55/gnu/src/tx_thread_context_restore.S index 8e0d5515..9ba82827 100644 --- a/ports/cortex_a55/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a55/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_a55/gnu/src/tx_thread_context_save.S b/ports/cortex_a55/gnu/src/tx_thread_context_save.S index 7768efc2..c2395155 100644 --- a/ports/cortex_a55/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a55/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_a55/gnu/src/tx_thread_fp_disable.c b/ports/cortex_a55/gnu/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports/cortex_a55/gnu/src/tx_thread_fp_disable.c +++ b/ports/cortex_a55/gnu/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports/cortex_a55/gnu/src/tx_thread_fp_enable.c b/ports/cortex_a55/gnu/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports/cortex_a55/gnu/src/tx_thread_fp_enable.c +++ b/ports/cortex_a55/gnu/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports/cortex_a55/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a55/gnu/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports/cortex_a55/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a55/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_a55/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a55/gnu/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports/cortex_a55/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a55/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports/cortex_a55/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a55/gnu/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports/cortex_a55/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a55/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports/cortex_a55/gnu/src/tx_thread_schedule.S b/ports/cortex_a55/gnu/src/tx_thread_schedule.S index 4cce4a62..057aa538 100644 --- a/ports/cortex_a55/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a55/gnu/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,18 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_a55/gnu/src/tx_thread_stack_build.S b/ports/cortex_a55/gnu/src/tx_thread_stack_build.S index 6c675d9b..01084da7 100644 --- a/ports/cortex_a55/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a55/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_a55/gnu/src/tx_thread_system_return.S b/ports/cortex_a55/gnu/src/tx_thread_system_return.S index 780bb128..b7593d79 100644 --- a/ports/cortex_a55/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a55/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_a55/gnu/src/tx_timer_interrupt.S b/ports/cortex_a55/gnu/src/tx_timer_interrupt.S index d84245c6..1b80a7f2 100644 --- a/ports/cortex_a55/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a55/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_a57/ac6/example_build/sample_threadx/.cproject b/ports/cortex_a57/ac6/example_build/sample_threadx/.cproject index d6254b98..c8f4a879 100644 --- a/ports/cortex_a57/ac6/example_build/sample_threadx/.cproject +++ b/ports/cortex_a57/ac6/example_build/sample_threadx/.cproject @@ -1,158 +1,158 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a57/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports/cortex_a57/ac6/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports/cortex_a57/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports/cortex_a57/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports/cortex_a57/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports/cortex_a57/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports/cortex_a57/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports/cortex_a57/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports/cortex_a57/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_a57/ac6/example_build/sample_threadx/sample_threadx.scat index e5783c7c..d8dfde69 100644 --- a/ports/cortex_a57/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports/cortex_a57/ac6/example_build/sample_threadx/sample_threadx.scat @@ -2,7 +2,7 @@ ; Scatter file for Armv8-A Startup code on FVP Base model ; Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************** @@ -25,7 +25,7 @@ LOAD 0x80000000 ; in source code for this to work correctly ; ARM_LIB_HEAP +0 ALIGN 64 EMPTY 0xA0000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary diff --git a/ports/cortex_a57/ac6/example_build/sample_threadx/v8_aarch64.h b/ports/cortex_a57/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports/cortex_a57/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports/cortex_a57/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_a57/ac6/example_build/sample_threadx/v8_mmu.h b/ports/cortex_a57/ac6/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports/cortex_a57/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports/cortex_a57/ac6/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports/cortex_a57/ac6/example_build/tx/.cproject b/ports/cortex_a57/ac6/example_build/tx/.cproject index 5ce4655a..fce48d53 100644 --- a/ports/cortex_a57/ac6/example_build/tx/.cproject +++ b/ports/cortex_a57/ac6/example_build/tx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a57/ac6/inc/tx_port.h b/ports/cortex_a57/ac6/inc/tx_port.h index a8d3fd48..e5352338 100644 --- a/ports/cortex_a57/ac6/inc/tx_port.h +++ b/ports/cortex_a57/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -369,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a57/ac6/src/tx_initialize_low_level.S b/ports/cortex_a57/ac6/src/tx_initialize_low_level.S index f456574e..7d2a4be3 100644 --- a/ports/cortex_a57/ac6/src/tx_initialize_low_level.S +++ b/ports/cortex_a57/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports/cortex_a57/ac6/src/tx_thread_context_restore.S b/ports/cortex_a57/ac6/src/tx_thread_context_restore.S index 8e0d5515..9ba82827 100644 --- a/ports/cortex_a57/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a57/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_a57/ac6/src/tx_thread_context_save.S b/ports/cortex_a57/ac6/src/tx_thread_context_save.S index 7768efc2..c2395155 100644 --- a/ports/cortex_a57/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a57/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_a57/ac6/src/tx_thread_fp_disable.c b/ports/cortex_a57/ac6/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports/cortex_a57/ac6/src/tx_thread_fp_disable.c +++ b/ports/cortex_a57/ac6/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports/cortex_a57/ac6/src/tx_thread_fp_enable.c b/ports/cortex_a57/ac6/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports/cortex_a57/ac6/src/tx_thread_fp_enable.c +++ b/ports/cortex_a57/ac6/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports/cortex_a57/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a57/ac6/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports/cortex_a57/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a57/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_a57/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a57/ac6/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports/cortex_a57/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a57/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports/cortex_a57/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a57/ac6/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports/cortex_a57/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a57/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports/cortex_a57/ac6/src/tx_thread_schedule.S b/ports/cortex_a57/ac6/src/tx_thread_schedule.S index 4cce4a62..057aa538 100644 --- a/ports/cortex_a57/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a57/ac6/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,18 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_a57/ac6/src/tx_thread_stack_build.S b/ports/cortex_a57/ac6/src/tx_thread_stack_build.S index 6c675d9b..01084da7 100644 --- a/ports/cortex_a57/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a57/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_a57/ac6/src/tx_thread_system_return.S b/ports/cortex_a57/ac6/src/tx_thread_system_return.S index 780bb128..b7593d79 100644 --- a/ports/cortex_a57/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a57/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_a57/ac6/src/tx_timer_interrupt.S b/ports/cortex_a57/ac6/src/tx_timer_interrupt.S index d84245c6..1b80a7f2 100644 --- a/ports/cortex_a57/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a57/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_a57/gnu/example_build/sample_threadx/.cproject b/ports/cortex_a57/gnu/example_build/sample_threadx/.cproject index 1c32cb32..40d4912d 100644 --- a/ports/cortex_a57/gnu/example_build/sample_threadx/.cproject +++ b/ports/cortex_a57/gnu/example_build/sample_threadx/.cproject @@ -1,170 +1,170 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a57/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports/cortex_a57/gnu/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports/cortex_a57/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports/cortex_a57/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports/cortex_a57/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports/cortex_a57/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports/cortex_a57/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports/cortex_a57/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports/cortex_a57/gnu/example_build/sample_threadx/sample_threadx.ld b/ports/cortex_a57/gnu/example_build/sample_threadx/sample_threadx.ld index eec8f12b..3bf47736 100644 --- a/ports/cortex_a57/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports/cortex_a57/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start diff --git a/ports/cortex_a57/gnu/example_build/sample_threadx/startup.S b/ports/cortex_a57/gnu/example_build/sample_threadx/startup.S index b71b45f8..b44806fe 100644 --- a/ports/cortex_a57/gnu/example_build/sample_threadx/startup.S +++ b/ports/cortex_a57/gnu/example_build/sample_threadx/startup.S @@ -328,7 +328,7 @@ el1_entry_aarch64: // // Cortex-A processors automatically invalidate their caches on reset // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). - // It is therefore not necessary for software to invalidate the caches + // It is therefore not necessary for software to invalidate the caches // on startup, however, this is done here in case of a warm reset. bl InvalidateUDCaches tlbi VMALLE1 diff --git a/ports/cortex_a57/gnu/example_build/sample_threadx/v8_aarch64.h b/ports/cortex_a57/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports/cortex_a57/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports/cortex_a57/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_a57/gnu/example_build/sample_threadx/v8_mmu.h b/ports/cortex_a57/gnu/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports/cortex_a57/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports/cortex_a57/gnu/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports/cortex_a57/gnu/example_build/tx/.cproject b/ports/cortex_a57/gnu/example_build/tx/.cproject index f1b8ed5b..9e5a975e 100644 --- a/ports/cortex_a57/gnu/example_build/tx/.cproject +++ b/ports/cortex_a57/gnu/example_build/tx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a57/gnu/inc/tx_port.h b/ports/cortex_a57/gnu/inc/tx_port.h index a8d3fd48..e5352338 100644 --- a/ports/cortex_a57/gnu/inc/tx_port.h +++ b/ports/cortex_a57/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -369,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a57/gnu/src/tx_initialize_low_level.S b/ports/cortex_a57/gnu/src/tx_initialize_low_level.S index 3dce3cea..3025f12b 100644 --- a/ports/cortex_a57/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_a57/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -99,4 +89,4 @@ _tx_initialize_low_level: /* Done, return to caller. */ RET // Return to caller -// } +// } diff --git a/ports/cortex_a57/gnu/src/tx_thread_context_restore.S b/ports/cortex_a57/gnu/src/tx_thread_context_restore.S index 8e0d5515..9ba82827 100644 --- a/ports/cortex_a57/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a57/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_a57/gnu/src/tx_thread_context_save.S b/ports/cortex_a57/gnu/src/tx_thread_context_save.S index 7768efc2..c2395155 100644 --- a/ports/cortex_a57/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a57/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_a57/gnu/src/tx_thread_fp_disable.c b/ports/cortex_a57/gnu/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports/cortex_a57/gnu/src/tx_thread_fp_disable.c +++ b/ports/cortex_a57/gnu/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports/cortex_a57/gnu/src/tx_thread_fp_enable.c b/ports/cortex_a57/gnu/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports/cortex_a57/gnu/src/tx_thread_fp_enable.c +++ b/ports/cortex_a57/gnu/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports/cortex_a57/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a57/gnu/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports/cortex_a57/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a57/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_a57/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a57/gnu/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports/cortex_a57/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a57/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports/cortex_a57/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a57/gnu/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports/cortex_a57/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a57/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports/cortex_a57/gnu/src/tx_thread_schedule.S b/ports/cortex_a57/gnu/src/tx_thread_schedule.S index 4cce4a62..057aa538 100644 --- a/ports/cortex_a57/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a57/gnu/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,18 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_a57/gnu/src/tx_thread_stack_build.S b/ports/cortex_a57/gnu/src/tx_thread_stack_build.S index 6c675d9b..01084da7 100644 --- a/ports/cortex_a57/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a57/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_a57/gnu/src/tx_thread_system_return.S b/ports/cortex_a57/gnu/src/tx_thread_system_return.S index 780bb128..b7593d79 100644 --- a/ports/cortex_a57/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a57/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_a57/gnu/src/tx_timer_interrupt.S b/ports/cortex_a57/gnu/src/tx_timer_interrupt.S index d84245c6..1b80a7f2 100644 --- a/ports/cortex_a57/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a57/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_a5x/ac6/example_build/sample_threadx/.cproject b/ports/cortex_a5x/ac6/example_build/sample_threadx/.cproject index f407d39b..46377ece 100644 --- a/ports/cortex_a5x/ac6/example_build/sample_threadx/.cproject +++ b/ports/cortex_a5x/ac6/example_build/sample_threadx/.cproject @@ -1,154 +1,154 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a5x/ac6/example_build/sample_threadx/armv8_aarch64_SystemTimer.S b/ports/cortex_a5x/ac6/example_build/sample_threadx/armv8_aarch64_SystemTimer.S index aaf0f7f8..958c90c3 100644 --- a/ports/cortex_a5x/ac6/example_build/sample_threadx/armv8_aarch64_SystemTimer.S +++ b/ports/cortex_a5x/ac6/example_build/sample_threadx/armv8_aarch64_SystemTimer.S @@ -4,7 +4,7 @@ // Copyright ARM Ltd 2013. All rights reserved. // ------------------------------------------------------------ - + .section AArch64_GenericTimer,"ax" .align 3 @@ -14,10 +14,10 @@ // uint32_t getCNTFRQ(void) // Returns the value of CNTFRQ_EL0 .type getCNTFRQ, @function -getCNTFRQ: +getCNTFRQ: MRS x0, CNTFRQ_EL0 RET - + // ------------------------------------------------------------ @@ -26,7 +26,7 @@ getCNTFRQ: // Sets the value of CNTFRQ_EL0 (only possible at EL3) // w0 - freq - The value to be written into CNTFRQ_EL0 .type setCNTFRQ, @function -setCNTFRQ: +setCNTFRQ: MSR CNTFRQ_EL0, x0 RET @@ -37,10 +37,10 @@ setCNTFRQ: // uint64_t getPhysicalCount(void) // Returns the current value of physical count (CNTPCT_EL0) .type getPhysicalCount, @function -getPhysicalCount: +getPhysicalCount: MRS x0, CNTPCT_EL0 RET - + // ------------------------------------------------------------ @@ -48,10 +48,10 @@ getPhysicalCount: // uint64_t getVirtualCount(void) // Returns the current value of the virtual count register (CNTVCT_EL0) .type getVirtualCount, @function -getVirtualCount: +getVirtualCount: MRS x0, CNTVCT_EL0 RET - + // ------------------------------------------------------------ @@ -59,10 +59,10 @@ getVirtualCount: // uint32_t getEL1Ctrl(void) // Returns the value of EL1 Timer Control Register (CNTKCTL_EL1) .type getEL1Ctrl, @function -getEL1Ctrl: +getEL1Ctrl: MRS x0, CNTKCTL_EL1 RET - + // ------------------------------------------------------------ @@ -71,10 +71,10 @@ getEL1Ctrl: // Sets the value of Counter Non-secure EL1 Control Register (CNTKCTL_EL1) // 0 - value - The value to be written into CNTKCTL_EL1 .type setEL1Ctrl, @function -setEL1Ctrl: +setEL1Ctrl: MSR CNTKCTL_EL1, x0 RET - + // ------------------------------------------------------------ @@ -82,10 +82,10 @@ setEL1Ctrl: // uint32_t getEL2Ctrl(void) // Returns the value of the EL2 Timer Control Register (CNTHCTL_EL2) .type getEL2Ctrl, @function -getEL2Ctrl: +getEL2Ctrl: MRS x0, CNTHCTL_EL2 RET - + // ------------------------------------------------------------ @@ -94,10 +94,10 @@ getEL2Ctrl: // Sets the value of the EL2 Timer Control Register (CNTHCTL_EL2) // x0 - value - The value to be written into CNTHCTL_EL2 .type setEL2Ctrl, @function -setEL2Ctrl: +setEL2Ctrl: MSR CNTHCTL_EL2, x0 RET - + // ------------------------------------------------------------ // Non-Secure Physical Timer @@ -107,10 +107,10 @@ setEL2Ctrl: // uint64_t getNSEL1PhysicalCompValue(void) // Returns the value of Non-Secure EL1 Physical Compare Value Register (CNTP_CVAL_EL0) .type getNSEL1PhysicalCompValue, @function -getNSEL1PhysicalCompValue: +getNSEL1PhysicalCompValue: MRS x0, CNTP_CVAL_EL0 RET - + // ------------------------------------------------------------ @@ -119,10 +119,10 @@ getNSEL1PhysicalCompValue: // Sets the value of the Non-Secure EL1 Physical Compare Value Register (CNTP_CVAL_EL0) // x0 - value - The value to be written into CNTP_CVAL_EL0 .type setNSEL1PhysicalCompValue, @function -setNSEL1PhysicalCompValue: +setNSEL1PhysicalCompValue: MSR CNTP_CVAL_EL0, x0 RET - + // ------------------------------------------------------------ @@ -130,10 +130,10 @@ setNSEL1PhysicalCompValue: // uint32_t getNSEL1PhysicalTimerValue(void) // Returns the value of Non-Secure EL1 Physical Timer Value Register (CNTP_TVAL_EL0) .type getNSEL1PhysicalTimerValue, @function -getNSEL1PhysicalTimerValue: +getNSEL1PhysicalTimerValue: MRS x0, CNTP_TVAL_EL0 RET - + // ------------------------------------------------------------ @@ -142,10 +142,10 @@ getNSEL1PhysicalTimerValue: // Sets the value of the Non-Secure EL1 Physical Timer Value Register (CNTP_TVAL_EL0) // w0 - value - The value to be written into CNTP_TVAL_EL0 .type setNSEL1PhysicalTimerValue, @function -setNSEL1PhysicalTimerValue: +setNSEL1PhysicalTimerValue: MSR CNTP_TVAL_EL0, x0 RET - + // ------------------------------------------------------------ @@ -153,10 +153,10 @@ setNSEL1PhysicalTimerValue: // uint32_t getNSEL1PhysicalTimerCtrl(void) // Returns the value of Non-Secure EL1 Physical Timer Control Register (CNTP_CTL_EL0) .type getNSEL1PhysicalTimerCtrl, @function -getNSEL1PhysicalTimerCtrl: +getNSEL1PhysicalTimerCtrl: MRS x0, CNTP_CTL_EL0 RET - + // ------------------------------------------------------------ @@ -165,10 +165,10 @@ getNSEL1PhysicalTimerCtrl: // Sets the value of the Non-Secure EL1 Physical Timer Control Register (CNTP_CTL_EL0) // w0 - value - The value to be written into CNTP_CTL_EL0 .type setNSEL1PhysicalTimerCtrl, @function -setNSEL1PhysicalTimerCtrl: +setNSEL1PhysicalTimerCtrl: MSR CNTP_CTL_EL0, x0 RET - + // ------------------------------------------------------------ // Secure Physical Timer @@ -178,10 +178,10 @@ setNSEL1PhysicalTimerCtrl: // uint64_t getSEL1PhysicalCompValue(void) // Returns the value of Secure EL1 Physical Compare Value Register (CNTPS_CVAL_EL1) .type getSEL1PhysicalCompValue, @function -getSEL1PhysicalCompValue: +getSEL1PhysicalCompValue: MRS x0, CNTPS_CVAL_EL1 RET - + // ------------------------------------------------------------ @@ -190,10 +190,10 @@ getSEL1PhysicalCompValue: // Sets the value of the Secure EL1 Physical Compare Value Register (CNTPS_CVAL_EL1) // x0 - value - The value to be written into CNTPS_CVAL_EL1 .type setSEL1PhysicalCompValue, @function -setSEL1PhysicalCompValue: +setSEL1PhysicalCompValue: MSR CNTPS_CVAL_EL1, x0 RET - + // ------------------------------------------------------------ @@ -202,10 +202,10 @@ setSEL1PhysicalCompValue: // uint32_t getSEL1PhysicalTimerValue(void) // Returns the value of Secure EL1 Physical Timer Value Register (CNTPS_TVAL_EL1) .type getSEL1PhysicalTimerValue, @function -getSEL1PhysicalTimerValue: +getSEL1PhysicalTimerValue: MRS x0, CNTPS_TVAL_EL1 RET - + // ------------------------------------------------------------ @@ -214,10 +214,10 @@ getSEL1PhysicalTimerValue: // Sets the value of the Secure EL1 Physical Timer Value Register (CNTPS_TVAL_EL1) // w0 - value - The value to be written into CNTPS_TVAL_EL1 .type setSEL1PhysicalTimerValue, @function -setSEL1PhysicalTimerValue: +setSEL1PhysicalTimerValue: MSR CNTPS_TVAL_EL1, x0 RET - + // ------------------------------------------------------------ @@ -225,10 +225,10 @@ setSEL1PhysicalTimerValue: // uint32_t getSEL1PhysicalTimerCtrl(void) // Returns the value of Secure EL1 Physical Timer Control Register (CNTPS_CTL_EL1) .type getSEL1PhysicalTimerCtrl, @function -getSEL1PhysicalTimerCtrl: +getSEL1PhysicalTimerCtrl: MRS x0, CNTPS_CTL_EL1 RET - + // ------------------------------------------------------------ @@ -237,11 +237,11 @@ getSEL1PhysicalTimerCtrl: // Sets the value of the Secure EL1 Physical Timer Control Register (CNTPS_CTL_EL1) // w0 - value - The value to be written into CNTPS_CTL_EL1 .type setSEL1PhysicalTimerCtrl, @function -setSEL1PhysicalTimerCtrl: +setSEL1PhysicalTimerCtrl: MSR CNTPS_CTL_EL1, x0 RET - - + + // ------------------------------------------------------------ .global configSecureEL1TimerAccess @@ -249,12 +249,12 @@ setSEL1PhysicalTimerCtrl: // Sets the values of the SCR_EL3.ST bit (bit 11) based on the value in x0 // EL3 accessible only! .type configSecureEL1TimerAccess, @function -configSecureEL1TimerAccess: +configSecureEL1TimerAccess: MRS x1, SCR_EL3 BFI x1, x0, #11, #1 MSR SCR_EL3, x1 RET - + // ------------------------------------------------------------ // Virtual Timer @@ -264,10 +264,10 @@ configSecureEL1TimerAccess: // uint64_t getEL1VirtualCompValue(void) // Returns the value of EL1 Virtual Compare Value Register (CNTV_CVAL_EL0) .type getEL1VirtualCompValue, @function -getEL1VirtualCompValue: +getEL1VirtualCompValue: MRS x0, CNTV_CVAL_EL0 RET - + // ------------------------------------------------------------ @@ -276,7 +276,7 @@ getEL1VirtualCompValue: // Sets the value of the EL1 Virtual Compare Value Register (CNTV_CVAL_EL0) // x0 - value - The value to be written into CNTV_CVAL_EL0 .type setEL1VirtualCompValue, @function -setEL1VirtualCompValue: +setEL1VirtualCompValue: MSR CNTV_CVAL_EL0, x0 RET @@ -287,10 +287,10 @@ setEL1VirtualCompValue: // uint32_t getEL1VirtualTimerValue(void) // Returns the value of EL1 Virtual Timer Value Register (CNTV_TVAL_EL0) .type getEL1VirtualTimerValue, @function -getEL1VirtualTimerValue: +getEL1VirtualTimerValue: MRS x0, CNTV_TVAL_EL0 RET - + // ------------------------------------------------------------ @@ -299,10 +299,10 @@ getEL1VirtualTimerValue: // Sets the value of the EL1 Virtual Timer Value Register (CNTV_TVAL_EL0) // w0 - value - The value to be written into CNTV_TVAL_EL0 .type setEL1VirtualTimerValue, @function -setEL1VirtualTimerValue: +setEL1VirtualTimerValue: MSR CNTV_TVAL_EL0, x0 RET - + // ------------------------------------------------------------ @@ -310,10 +310,10 @@ setEL1VirtualTimerValue: // uint32_t getEL1VirtualTimerCtrl(void) // Returns the value of EL1 Virtual Timer Control Register (CNTV_CTL_EL0) .type getEL1VirtualTimerCtrl, @function -getEL1VirtualTimerCtrl: +getEL1VirtualTimerCtrl: MRS x0, CNTV_CTL_EL0 RET - + // ------------------------------------------------------------ @@ -322,11 +322,11 @@ getEL1VirtualTimerCtrl: // Sets the value of the EL1 Virtual Timer Control Register (CNTV_CTL_EL0) // w0 - value - The value to be written into CNTV_CTL_EL0 .type setEL1VirtualTimerCtrl, @function -setEL1VirtualTimerCtrl: +setEL1VirtualTimerCtrl: MSR CNTV_CTL_EL0, x0 RET - - + + // ------------------------------------------------------------ // Virtual Timer functions to be called by EL2 // ------------------------------------------------------------ @@ -336,10 +336,10 @@ setEL1VirtualTimerCtrl: // Returns the value of the Counter Virtual Offset Register (CNTVOFF_EL2) // EL2 and EL3 only .type getVirtualCounterOffset, @function -getVirtualCounterOffset: +getVirtualCounterOffset: MRS x0, CNTVOFF_EL2 RET - + // ------------------------------------------------------------ @@ -349,11 +349,11 @@ getVirtualCounterOffset: // x0 - offset - The value to be written into CNTVOFF_EL2 // EL2 and EL3 only .type setVirtualCounterOffset, @function -setVirtualCounterOffset: +setVirtualCounterOffset: MSR CNTVOFF_EL2, x0 RET - - + + // ------------------------------------------------------------ // EL2 Physical Timer // ------------------------------------------------------------ @@ -362,10 +362,10 @@ setVirtualCounterOffset: // uint64_t getEL2PhysicalCompValue(void) // Returns the value of EL2 Physical Compare Value Register (CNTHP_CVAL_EL2) .type getEL2PhysicalCompValue, @function -getEL2PhysicalCompValue: +getEL2PhysicalCompValue: MRS x0, CNTHP_CVAL_EL2 RET - + // ------------------------------------------------------------ @@ -374,10 +374,10 @@ getEL2PhysicalCompValue: // Sets the value of the EL2 Physical Compare Value Register (CNTHP_CVAL_EL2) // x0 - value - The value to be written into CNTHP_CVAL_EL2 .type setEL2PhysicalCompValue, @function -setEL2PhysicalCompValue: +setEL2PhysicalCompValue: MSR CNTHP_CVAL_EL2, x0 RET - + // ------------------------------------------------------------ @@ -386,10 +386,10 @@ setEL2PhysicalCompValue: // uint32_t getEL2PhysicalTimerValue(void) // Returns the value of EL2 Physical Timer Value Register (CNTHP_TVAL_EL2) .type getEL2PhysicalTimerValue, @function -getEL2PhysicalTimerValue: +getEL2PhysicalTimerValue: MRS x0, CNTHP_TVAL_EL2 RET - + // ------------------------------------------------------------ @@ -398,10 +398,10 @@ getEL2PhysicalTimerValue: // Sets the value of the EL2 Physical Timer Value Register (CNTHP_TVAL_EL2) // w0 - value - The value to be written into CNTHP_TVAL_EL2 .type setEL2PhysicalTimerValue, @function -setEL2PhysicalTimerValue: +setEL2PhysicalTimerValue: MSR CNTHP_TVAL_EL2, x0 RET - + // ------------------------------------------------------------ @@ -409,10 +409,10 @@ setEL2PhysicalTimerValue: // uint32_t getEL2PhysicalTimerCtrl(void) // Returns the value of EL2 Physical Timer Control Register (CNTHP_CTL_EL2) .type getEL2PhysicalTimerCtrl, @function -getEL2PhysicalTimerCtrl: +getEL2PhysicalTimerCtrl: MRS x0, CNTHP_CTL_EL2 RET - + // ------------------------------------------------------------ @@ -421,10 +421,10 @@ getEL2PhysicalTimerCtrl: // Sets the value of the EL2 Physical Timer Control Register (CNTHP_CTL_EL2) // w0 - value - The value to be written into CNTHP_CTL_EL2 .type setEL2PhysicalTimerCtrl, @function -setEL2PhysicalTimerCtrl: +setEL2PhysicalTimerCtrl: MSR CNTHP_CTL_EL2, x0 RET - + // ------------------------------------------------------------ // End of code diff --git a/ports/cortex_a5x/ac6/example_build/sample_threadx/el3_vectors.S b/ports/cortex_a5x/ac6/example_build/sample_threadx/el3_vectors.S index 7f4effe7..b76a789e 100644 --- a/ports/cortex_a5x/ac6/example_build/sample_threadx/el3_vectors.S +++ b/ports/cortex_a5x/ac6/example_build/sample_threadx/el3_vectors.S @@ -6,8 +6,8 @@ .section VECTORS,"ax" .align 12 - - + + .global el3_vectors el3_vectors: @@ -59,7 +59,7 @@ serror_current_el_spx: .balign 128 sync_lower_el_aarch64: - B . + B . .balign 128 irq_lower_el_aarch64: @@ -103,7 +103,7 @@ irqFirstLevelHandler: BL irqHandler B _tx_thread_context_restore - + fiqFirstLevelHandler: STP x29, x30, [sp, #-16]! STP x18, x19, [sp, #-16]! diff --git a/ports/cortex_a5x/ac6/example_build/sample_threadx/gic400_gic.c b/ports/cortex_a5x/ac6/example_build/sample_threadx/gic400_gic.c index 1ecd5f33..d37d4c27 100644 --- a/ports/cortex_a5x/ac6/example_build/sample_threadx/gic400_gic.c +++ b/ports/cortex_a5x/ac6/example_build/sample_threadx/gic400_gic.c @@ -102,7 +102,7 @@ void enableIntID(unsigned int ID) void disableIntID(unsigned int ID) { unsigned int bank; - + bank = ID/32; // There are 32 IDs per register, need to work out which register to access ID = ID & 0x1f; // ... and which bit within the register @@ -136,7 +136,7 @@ unsigned int getIntPriority(unsigned int ID) return 0; return gic_dist->GICD_IPRIORITYR[ID]; -} +} // ------------------------------------------------------------ diff --git a/ports/cortex_a5x/ac6/example_build/sample_threadx/hw_setup.c b/ports/cortex_a5x/ac6/example_build/sample_threadx/hw_setup.c index dc19cd3b..3f86523a 100644 --- a/ports/cortex_a5x/ac6/example_build/sample_threadx/hw_setup.c +++ b/ports/cortex_a5x/ac6/example_build/sample_threadx/hw_setup.c @@ -58,7 +58,7 @@ void hw_setup(void) // NOTE: // This code assumes that the IRQ and FIQ exceptions - // have been routed to the appropriate EL. In this + // have been routed to the appropriate EL. In this // example that is done in the startup.s file } diff --git a/ports/cortex_a5x/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a5x/ac6/example_build/sample_threadx/sample_threadx.c index db5318f0..3e4c45a5 100644 --- a/ports/cortex_a5x/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_a5x/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -91,42 +91,42 @@ UCHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -134,23 +134,23 @@ UCHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -254,11 +254,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -317,7 +317,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -370,7 +370,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_a5x/ac6/example_build/sample_threadx/sample_threadx.txt b/ports/cortex_a5x/ac6/example_build/sample_threadx/sample_threadx.txt index 90c80d28..6fb28be1 100644 --- a/ports/cortex_a5x/ac6/example_build/sample_threadx/sample_threadx.txt +++ b/ports/cortex_a5x/ac6/example_build/sample_threadx/sample_threadx.txt @@ -9,7 +9,7 @@ LOAD 0x80000000 { * (+RW, +ZI) } - + ARM_LIB_STACKHEAP 0x80090000 EMPTY -0x00040000 {} } \ No newline at end of file diff --git a/ports/cortex_a5x/ac6/example_build/sample_threadx/startup.S b/ports/cortex_a5x/ac6/example_build/sample_threadx/startup.S index 8b1f8f3b..75ae62c8 100644 --- a/ports/cortex_a5x/ac6/example_build/sample_threadx/startup.S +++ b/ports/cortex_a5x/ac6/example_build/sample_threadx/startup.S @@ -99,7 +99,7 @@ start64: MOV x28, #0 MOV x29, #0 MOV x30, #0 - + // Which core am I // ---------------- MRS x0, MPIDR_EL1 @@ -109,20 +109,20 @@ sleep: WFI B sleep boot: - + // Disable trapping of CPTR_EL3 accesses or use of Adv.SIMD/FPU // ------------------------------------------------------------- MOV x0, #0 // Clear all trap bits MSR CPTR_EL3, x0 - - + + // Install vector table // --------------------- LDR x0, vector_table_address MSR VBAR_EL3, x0 - + // Configure SCR_EL3 // ------------------ MOV w1, #0 // Initial value of register is unknown diff --git a/ports/cortex_a5x/ac6/example_build/tx/.cproject b/ports/cortex_a5x/ac6/example_build/tx/.cproject index 0bc69306..b3e80235 100644 --- a/ports/cortex_a5x/ac6/example_build/tx/.cproject +++ b/ports/cortex_a5x/ac6/example_build/tx/.cproject @@ -1,140 +1,140 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a5x/ac6/inc/tx_port.h b/ports/cortex_a5x/ac6/inc/tx_port.h index 4de50b9f..c679690c 100644 --- a/ports/cortex_a5x/ac6/inc/tx_port.h +++ b/ports/cortex_a5x/ac6/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Cortex-A5x/ARM */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A5x/ARM */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -75,7 +67,7 @@ #include -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -122,19 +114,19 @@ typedef unsigned long long ALIGN_TYPE; #define TX_TIMER_THREAD_STACK_SIZE 4096 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ #define TX_INT_ENABLE 0x00 /* Enable IRQ & FIQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -181,7 +173,7 @@ typedef unsigned long long ALIGN_TYPE; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -193,13 +185,13 @@ typedef unsigned long long ALIGN_TYPE; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #define TX_THREAD_EXTENSION_2 ULONG tx_thread_fp_enable; -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -213,11 +205,11 @@ typedef unsigned long long ALIGN_TYPE; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -225,8 +217,8 @@ typedef unsigned long long ALIGN_TYPE; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -253,8 +245,8 @@ typedef unsigned long long ALIGN_TYPE; #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -266,7 +258,7 @@ typedef unsigned long long ALIGN_TYPE; /* Define the internal timer extension to also hold the thread pointer such that _tx_thread_timeout can figure out what thread timeout to process. */ - + #define TX_TIMER_INTERNAL_EXTENSION VOID *tx_timer_internal_thread_timeout_ptr; @@ -282,9 +274,9 @@ typedef unsigned long long ALIGN_TYPE; #define TX_THREAD_TIMEOUT_POINTER_SETUP(t) (t) = (TX_THREAD *) _tx_timer_expired_timer_ptr -> tx_timer_internal_thread_timeout_ptr; -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -355,8 +347,8 @@ VOID tx_thread_fp_disable(VOID); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-A5x/ARM Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A5x/ARM Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a5x/ac6/readme_threadx.txt b/ports/cortex_a5x/ac6/readme_threadx.txt index c3de31bb..5e80754d 100644 --- a/ports/cortex_a5x/ac6/readme_threadx.txt +++ b/ports/cortex_a5x/ac6/readme_threadx.txt @@ -1,11 +1,11 @@ - Microsoft's Azure RTOS ThreadX for Cortex-A5x + Microsoft's Azure RTOS ThreadX for Cortex-A5x Using the ARM Compiler 6 & DS -1. Open the Azure RTOS Workspace +1. Open the Azure RTOS Workspace -In order to build the ThreadX library and the ThreadX demonstration first load -the Azure RTOS Workspace, which is located inside your ThreadX installation +In order to build the ThreadX library and the ThreadX demonstration first load +the Azure RTOS Workspace, which is located inside your ThreadX installation directory. Note: the workspace and projects were made using DS-5, so DS will prompt you @@ -13,9 +13,9 @@ to migrate the projects. This is expected, so please do so. 2. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply select the Eclipse project file -"tx" and then select the build button. You should now observe the compilation -and assembly of the ThreadX library. This project build produces the ThreadX +Building the ThreadX library is easy; simply select the Eclipse project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. @@ -24,39 +24,39 @@ library file tx.a. The ThreadX demonstration is designed to execute under the DS debugger on the VE-AEMv8x1 Bare Metal simulator. -Building the demonstration is easy; simply open the workspace file, select the -sample_threadx project, and select the build button. Next, right-click on the +Building the demonstration is easy; simply open the workspace file, select the +sample_threadx project, and select the build button. Next, right-click on the project and select "Debug As -> Debug Configurations". The debugger is setup -for VE_AEMv8x1 Bare Metal Debug, so selecting "Debug" will launch the simulator, -load the sample_threadx.axf ELF file and run to main. You are now ready to +for VE_AEMv8x1 Bare Metal Debug, so selecting "Debug" will launch the simulator, +load the sample_threadx.axf ELF file and run to main. You are now ready to execute the ThreadX demonstration. 4. System Initialization -The entry point in ThreadX for the Cortex-A5x using ARM tools is at label -start64. This is defined within the ARM compiler's startup code. In addition, -this is where all static and global pre-set C variable initialization processing +The entry point in ThreadX for the Cortex-A5x using ARM tools is at label +start64. This is defined within the ARM compiler's startup code. In addition, +this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for determining the -first available RAM address for use by the application, which is supplied as the +The ThreadX tx_initialize_low_level.s file is responsible for determining the +first available RAM address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 5. Register Usage and Stack Frames -The 64-bit ARM compiler assumes that registers x0-x18 are scratch registers -for each function. All other registers used by a C function must be preserved -by the function. ThreadX takes advantage of this in situations where a context -switch happens as a result of making a ThreadX service call (which is itself a -C function). In such cases, the saved context of a thread is only the +The 64-bit ARM compiler assumes that registers x0-x18 are scratch registers +for each function. All other registers used by a C function must be preserved +by the function. ThreadX takes advantage of this in situations where a context +switch happens as a result of making a ThreadX service call (which is itself a +C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -75,10 +75,10 @@ FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: 0x040 x22 x21 0x048 x23 x22 0x050 x20 x19 - 0x058 x21 x20 - 0x060 x18 x29 - 0x068 x19 x30 - 0x070 x16 + 0x058 x21 x20 + 0x060 x18 x29 + 0x068 x19 x30 + 0x070 x16 0x078 x17 0x080 x14 0x088 x15 @@ -97,7 +97,7 @@ FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: 0x0F0 x0 0x0F8 x1 0x100 x29 - 0x108 x30 + 0x108 x30 FP enabled and TX_THREAD.tx_thread_fp_enable == 1: @@ -146,19 +146,19 @@ FP enabled and TX_THREAD.tx_thread_fp_enable == 1: 0x1F0 q3 0x200 q0 0x210 q1 - 0x220 x28 - 0x228 reserved - 0x230 x26 - 0x238 x27 - 0x240 x24 - 0x248 x25 - 0x250 x22 - 0x258 x23 - 0x260 x20 - 0x268 x21 - 0x270 x18 - 0x278 x19 - 0x280 x16 + 0x220 x28 + 0x228 reserved + 0x230 x26 + 0x238 x27 + 0x240 x24 + 0x248 x25 + 0x250 x22 + 0x258 x23 + 0x260 x20 + 0x268 x21 + 0x270 x18 + 0x278 x19 + 0x280 x16 0x288 x17 0x290 x14 0x298 x15 @@ -177,20 +177,20 @@ FP enabled and TX_THREAD.tx_thread_fp_enable == 1: 0x300 x0 0x308 x1 0x310 x29 - 0x318 x30 + 0x318 x30 6. Improving Performance -The distribution version of ThreadX is built without any compiler optimizations. -This makes it easy to debug because you can trace or set breakpoints inside of -ThreadX itself. Of course, this costs some performance. To make it run faster, +The distribution version of ThreadX is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the project settings to the desired compiler optimization level. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling @@ -210,22 +210,22 @@ irq_handler: B _tx_thread_context_restore -By default, ThreadX assumes EL3 level of execution. Running and taking exceptions in EL1 +By default, ThreadX assumes EL3 level of execution. Running and taking exceptions in EL1 and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined. 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, thread sleeps, -timeouts, and application timers. Without such a timer interrupt source, these services -are not functional. However, all other ThreadX services are operational without a +ThreadX requires a periodic interrupt source to manage all time-slicing, thread sleeps, +timeouts, and application timers. Without such a timer interrupt source, these services +are not functional. However, all other ThreadX services are operational without a periodic timer source. 9. ARM FP Support By default, FP support is disabled for each thread. If saving the context of the FP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the FP usage: void tx_thread_fp_enable(void); diff --git a/ports/cortex_a5x/ac6/src/tx_initialize_low_level.S b/ports/cortex_a5x/ac6/src/tx_initialize_low_level.S index a45da7c1..1b8d1d8d 100644 --- a/ports/cortex_a5x/ac6/src/tx_initialize_low_level.S +++ b/ports/cortex_a5x/ac6/src/tx_initialize_low_level.S @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Initialize */ /** */ @@ -34,45 +35,39 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_initialize_low_level Cortex-A5x/ARM */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-A5x/ARM */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function is responsible for any low-level processor */ -/* initialization, including setting up interrupt vectors, setting */ -/* up a periodic timer interrupt source, saving the system stack */ -/* pointer for use in ISR processing later, and finding the first */ -/* available RAM memory address for tx_application_define. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ /* */ /**************************************************************************/ /* VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a5x/ac6/src/tx_thread_context_restore.S b/ports/cortex_a5x/ac6/src/tx_thread_context_restore.S index 35674a25..5220dc79 100644 --- a/ports/cortex_a5x/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a5x/ac6/src/tx_thread_context_restore.S @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -25,7 +26,7 @@ /* Include necessary system files. */ -/* +/* #include "tx_api.h" #include "tx_thread.h" #include "tx_timer.h" @@ -35,44 +36,38 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_context_restore Cortex-A5x/ARM */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-A5x/ARM */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function restores the interrupt context if it is processing a */ -/* nested interrupt. If not, it returns to the interrupt thread if no */ -/* preemption is necessary. Otherwise, if preemption is necessary or */ -/* if no thread was running, the function returns to the scheduler. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_thread_schedule Thread scheduling routine */ -/* */ -/* CALLED BY */ -/* */ -/* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ /* */ /**************************************************************************/ /* VOID _tx_thread_context_restore(VOID) @@ -99,13 +94,13 @@ _tx_thread_context_restore: LDR x3, =_tx_thread_system_state // Pickup address of system state var LDR w2, [x3, #0] // Pickup system state SUB w2, w2, #1 // Decrement the counter - STR w2, [x3, #0] // Store the counter + STR w2, [x3, #0] // Store the counter CMP w2, #0 // Was this the first interrupt? BEQ __tx_thread_not_nested_restore // If so, not a nested restore /* Interrupts are nested. */ - /* Just recover the saved registers and return to the point of + /* Just recover the saved registers and return to the point of interrupt. */ LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL diff --git a/ports/cortex_a5x/ac6/src/tx_thread_context_save.S b/ports/cortex_a5x/ac6/src/tx_thread_context_save.S index f1af864e..287e8fa3 100644 --- a/ports/cortex_a5x/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a5x/ac6/src/tx_thread_context_save.S @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -32,43 +33,37 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_context_save Cortex-A5x/ARM */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-A5x/ARM */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function saves the context of an executing thread in the */ -/* beginning of interrupt processing. The function also ensures that */ -/* the system stack is used upon return to the calling ISR. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ /* */ /**************************************************************************/ /* VOID _tx_thread_context_save(VOID) @@ -78,7 +73,7 @@ _tx_thread_context_save: /* Upon entry to this routine, it is assumed that IRQ/FIQ interrupts are locked - out, x29 (frame pointer), x30 (link register) are saved, we are in EL1, + out, x29 (frame pointer), x30 (link register) are saved, we are in EL1, and all other registers are intact. */ /* Check for a nested interrupt condition. */ @@ -147,7 +142,7 @@ __tx_thread_not_nested_save: LDR x1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR x0, [x1, #0] // Pickup current thread pointer CMP x0, #0 // Is it NULL? - BEQ __tx_thread_idle_system_save // If so, interrupt occurred in + BEQ __tx_thread_idle_system_save // If so, interrupt occurred in // scheduling loop - nothing needs saving! /* Save minimal context of interrupted thread. */ @@ -196,7 +191,7 @@ __tx_thread_not_nested_save: LDP x29, x30, [sp], #16 // Recover x29, x30 .endif - RET // Return to caller + RET // Return to caller /* } else @@ -206,7 +201,7 @@ __tx_thread_idle_system_save: /* Interrupt occurred in the scheduling loop. */ - /* Not much to do here, just adjust the stack pointer, and return to IRQ + /* Not much to do here, just adjust the stack pointer, and return to IRQ processing. */ .ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY @@ -219,7 +214,7 @@ __tx_thread_idle_system_save: .endif ADD sp, sp, #48 // Recover saved registers - RET // Continue IRQ processing + RET // Continue IRQ processing /* } } */ diff --git a/ports/cortex_a5x/ac6/src/tx_thread_fp_disable.c b/ports/cortex_a5x/ac6/src/tx_thread_fp_disable.c index e2a0f084..2e3c5c77 100644 --- a/ports/cortex_a5x/ac6/src/tx_thread_fp_disable.c +++ b/ports/cortex_a5x/ac6/src/tx_thread_fp_disable.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -28,41 +29,35 @@ #include "tx_thread.h" -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_fp_disable Cortex-A5x/ARM */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fp_disable Cortex-A5x/ARM */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function disables the FP for the currently executing thread. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function disables the FP for the currently executing thread. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) @@ -81,14 +76,14 @@ ULONG system_state; /* Make sure it is not NULL. */ if (thread_ptr != TX_NULL) { - + /* Thread is running... make sure the call is from the thread context. */ if (system_state == 0) { - + /* Yes, now set the FP enable flag to false in the TX_THREAD structure. */ thread_ptr -> tx_thread_fp_enable = TX_FALSE; } } -} +} diff --git a/ports/cortex_a5x/ac6/src/tx_thread_fp_enable.c b/ports/cortex_a5x/ac6/src/tx_thread_fp_enable.c index 2da34265..ca589fe5 100644 --- a/ports/cortex_a5x/ac6/src/tx_thread_fp_enable.c +++ b/ports/cortex_a5x/ac6/src/tx_thread_fp_enable.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -28,41 +29,35 @@ #include "tx_thread.h" -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_fp_enable Cortex-A5x/ARM */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fp_enable Cortex-A5x/ARM */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function enabled the FP for the currently executing thread. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function enabled the FP for the currently executing thread. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) @@ -81,14 +76,14 @@ ULONG system_state; /* Make sure it is not NULL. */ if (thread_ptr != TX_NULL) { - + /* Thread is running... make sure the call is from the thread context. */ if (system_state == 0) { - + /* Yes, now setup the FP enable flag in the TX_THREAD structure. */ thread_ptr -> tx_thread_fp_enable = TX_TRUE; } } -} +} diff --git a/ports/cortex_a5x/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a5x/ac6/src/tx_thread_interrupt_control.S index 8eff07d9..264850df 100644 --- a/ports/cortex_a5x/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a5x/ac6/src/tx_thread_interrupt_control.S @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -31,42 +32,36 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_interrupt_control Cortex-A5x/ARM */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-A5x/ARM */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function is responsible for changing the interrupt lockout */ -/* posture of the system. */ -/* */ -/* INPUT */ -/* */ -/* new_posture New interrupt lockout posture */ -/* */ -/* OUTPUT */ -/* */ -/* old_posture Old interrupt lockout posture */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a5x/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a5x/ac6/src/tx_thread_interrupt_disable.S index 01ea803c..7c4f6a7b 100644 --- a/ports/cortex_a5x/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a5x/ac6/src/tx_thread_interrupt_disable.S @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -31,41 +32,35 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_interrupt_disable Cortex-A5x/ARM */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-A5x/ARM */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function is responsible for disabling interrupts */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* old_posture Old interrupt lockout posture */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function is responsible for disabling interrupts */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_a5x/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a5x/ac6/src/tx_thread_interrupt_restore.S index 7160f4f0..83b916a7 100644 --- a/ports/cortex_a5x/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a5x/ac6/src/tx_thread_interrupt_restore.S @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -31,42 +32,36 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_interrupt_restore Cortex-A5x/ARM */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-A5x/ARM */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ +/* */ /* This function is responsible for restoring interrupts to the state */ /* returned by a previous _tx_thread_interrupt_disable call. */ -/* */ -/* INPUT */ -/* */ -/* old_posture Old interrupt lockout posture */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* INPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a5x/ac6/src/tx_thread_schedule.S b/ports/cortex_a5x/ac6/src/tx_thread_schedule.S index 37778ce8..5651ad12 100644 --- a/ports/cortex_a5x/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a5x/ac6/src/tx_thread_schedule.S @@ -1,19 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -36,45 +36,39 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_schedule Cortex-A5x/ARM */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-A5x/ARM */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function waits for a thread control block pointer to appear in */ -/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -/* in the variable, the corresponding thread is resumed. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_initialize_kernel_enter ThreadX entry function */ -/* _tx_thread_system_return Return to system from thread */ -/* _tx_thread_context_restore Restore thread's context */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ /* */ /**************************************************************************/ /* VOID _tx_thread_schedule(VOID) @@ -90,15 +84,15 @@ _tx_thread_schedule: /* Wait for a thread to execute. */ /* do { */ - + LDR x1, =_tx_thread_execute_ptr // Address of thread execute ptr .ifdef TX_ENABLE_WFI __tx_thread_schedule_loop: LDR x0, [x1, #0] // Pickup next thread to execute CMP x0, #0 // Is it NULL? - BNE _tx_thread_schedule_thread // - WFI // + BNE _tx_thread_schedule_thread // + WFI // B __tx_thread_schedule_loop // Keep looking for a thread _tx_thread_schedule_thread: .else @@ -110,7 +104,7 @@ __tx_thread_schedule_loop: /* } while(_tx_thread_execute_ptr == TX_NULL); */ - + /* Yes! We have a thread to execute. Lockout interrupts and transfer control to it. */ @@ -119,7 +113,7 @@ __tx_thread_schedule_loop: /* Setup the current thread pointer. */ /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ - LDR x1, =_tx_thread_current_ptr // Pickup address of current thread + LDR x1, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x1, #0] // Setup current thread pointer /* Increment the run count for this thread. */ @@ -133,7 +127,7 @@ __tx_thread_schedule_loop: /* Setup time-slice, if present. */ /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ - LDR x2, =_tx_timer_time_slice // Pickup address of time slice + LDR x2, =_tx_timer_time_slice // Pickup address of time slice // variable LDR x4, [x0, #8] // Switch stack pointers MOV sp, x4 // @@ -234,7 +228,7 @@ _skip_solicited_fp_restore: LDP x19, x20, [sp], #16 // Recover x19, x20 LDP x29, x30, [sp], #16 // Recover x29, x30 MSR DAIF, x4 // Recover DAIF - RET // Return to caller + RET // Return to caller /* } */ diff --git a/ports/cortex_a5x/ac6/src/tx_thread_stack_build.S b/ports/cortex_a5x/ac6/src/tx_thread_stack_build.S index ca9f34b3..f4a0bdb5 100644 --- a/ports/cortex_a5x/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a5x/ac6/src/tx_thread_stack_build.S @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -33,44 +34,38 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_stack_build Cortex-A5x/ARM */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-A5x/ARM */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ +/* */ /* This function builds a stack frame on the supplied thread's stack. */ /* The stack frame results in a fake interrupt return to the supplied */ -/* function pointer. */ -/* */ -/* INPUT */ -/* */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ /* thread_ptr Pointer to thread control blk */ /* function_ptr Pointer to return function */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ /* */ /**************************************************************************/ /* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -79,10 +74,10 @@ .type _tx_thread_stack_build, @function _tx_thread_stack_build: - + /* Build a fake interrupt frame. The form of the fake interrupt stack on the Cortex-A5x should look like the following after it is built: - + Stack Top: SSPR Initial SSPR ELR Point of interrupt x28 Initial value for x28 @@ -128,7 +123,7 @@ _tx_thread_stack_build: MOV x2, #0 // Build clear value MOV x3, #0 // - + STP x2, x3, [x4, #-16]! // Set backtrace to 0 STP x2, x3, [x4, #-16]! // Set initial x29, x30 STP x2, x3, [x4, #-16]! // Set initial x0, x1 diff --git a/ports/cortex_a5x/ac6/src/tx_thread_system_return.S b/ports/cortex_a5x/ac6/src/tx_thread_system_return.S index 45f88be6..bc4a6306 100644 --- a/ports/cortex_a5x/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a5x/ac6/src/tx_thread_system_return.S @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -34,44 +35,38 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_system_return Cortex-A5x/ARM */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-A5x/ARM */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function is target processor specific. It is used to transfer */ -/* control from a thread back to the ThreadX system. Only a */ -/* minimal context is saved since the compiler assumes temp registers */ -/* are going to get slicked by a function call anyway. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_thread_schedule Thread scheduling loop */ -/* */ -/* CALLED BY */ -/* */ -/* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ /* */ /**************************************************************************/ /* VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a5x/ac6/src/tx_timer_interrupt.S b/ports/cortex_a5x/ac6/src/tx_timer_interrupt.S index f6452182..8d1cdf73 100644 --- a/ports/cortex_a5x/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a5x/ac6/src/tx_timer_interrupt.S @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Timer */ /** */ @@ -32,46 +33,40 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_timer_interrupt Cortex-A5x/ARM */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-A5x/ARM */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function processes the hardware timer interrupt. This */ -/* processing includes incrementing the system clock and checking for */ -/* time slice and/or timer expiration. If either is found, the */ -/* interrupt context save/restore functions are called along with the */ -/* expiration functions. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_timer_expiration_process Timer expiration processing */ -/* _tx_thread_time_slice Time slice interrupted thread */ -/* */ -/* CALLED BY */ -/* */ -/* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ /* */ /**************************************************************************/ /* VOID _tx_timer_interrupt(VOID) @@ -96,7 +91,7 @@ _tx_timer_interrupt: /* if (_tx_timer_time_slice) { */ - LDR x3, =_tx_timer_time_slice // Pickup address of time-slice + LDR x3, =_tx_timer_time_slice // Pickup address of time-slice LDR w2, [x3, #0] // Pickup time-slice CMP w2, #0 // Is it non-active? BEQ __tx_timer_no_time_slice // Yes, skip time-slice processing @@ -213,7 +208,7 @@ __tx_timer_dont_activate: /* if (_tx_timer_expired_time_slice) { */ - LDR x3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired + LDR x3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired LDR w2, [x3, #0] // Pickup the actual flag CMP w2, #0 // See if the flag is set BEQ __tx_timer_not_ts_expiration // No, skip time-slice processing diff --git a/ports/cortex_a65/ac6/example_build/sample_threadx/.cproject b/ports/cortex_a65/ac6/example_build/sample_threadx/.cproject index a74327d6..04033b8b 100644 --- a/ports/cortex_a65/ac6/example_build/sample_threadx/.cproject +++ b/ports/cortex_a65/ac6/example_build/sample_threadx/.cproject @@ -1,158 +1,158 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a65/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports/cortex_a65/ac6/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports/cortex_a65/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports/cortex_a65/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports/cortex_a65/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports/cortex_a65/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports/cortex_a65/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports/cortex_a65/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports/cortex_a65/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_a65/ac6/example_build/sample_threadx/sample_threadx.scat index e5783c7c..d8dfde69 100644 --- a/ports/cortex_a65/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports/cortex_a65/ac6/example_build/sample_threadx/sample_threadx.scat @@ -2,7 +2,7 @@ ; Scatter file for Armv8-A Startup code on FVP Base model ; Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************** @@ -25,7 +25,7 @@ LOAD 0x80000000 ; in source code for this to work correctly ; ARM_LIB_HEAP +0 ALIGN 64 EMPTY 0xA0000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary diff --git a/ports/cortex_a65/ac6/example_build/sample_threadx/v8_aarch64.h b/ports/cortex_a65/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports/cortex_a65/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports/cortex_a65/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_a65/ac6/example_build/sample_threadx/v8_mmu.h b/ports/cortex_a65/ac6/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports/cortex_a65/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports/cortex_a65/ac6/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports/cortex_a65/ac6/example_build/tx/.cproject b/ports/cortex_a65/ac6/example_build/tx/.cproject index 033932c0..8d6f8851 100644 --- a/ports/cortex_a65/ac6/example_build/tx/.cproject +++ b/ports/cortex_a65/ac6/example_build/tx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a65/ac6/inc/tx_port.h b/ports/cortex_a65/ac6/inc/tx_port.h index a8d3fd48..e5352338 100644 --- a/ports/cortex_a65/ac6/inc/tx_port.h +++ b/ports/cortex_a65/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -369,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a65/ac6/src/tx_initialize_low_level.S b/ports/cortex_a65/ac6/src/tx_initialize_low_level.S index f456574e..7d2a4be3 100644 --- a/ports/cortex_a65/ac6/src/tx_initialize_low_level.S +++ b/ports/cortex_a65/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports/cortex_a65/ac6/src/tx_thread_context_restore.S b/ports/cortex_a65/ac6/src/tx_thread_context_restore.S index 8e0d5515..9ba82827 100644 --- a/ports/cortex_a65/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a65/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_a65/ac6/src/tx_thread_context_save.S b/ports/cortex_a65/ac6/src/tx_thread_context_save.S index 7768efc2..c2395155 100644 --- a/ports/cortex_a65/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a65/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_a65/ac6/src/tx_thread_fp_disable.c b/ports/cortex_a65/ac6/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports/cortex_a65/ac6/src/tx_thread_fp_disable.c +++ b/ports/cortex_a65/ac6/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports/cortex_a65/ac6/src/tx_thread_fp_enable.c b/ports/cortex_a65/ac6/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports/cortex_a65/ac6/src/tx_thread_fp_enable.c +++ b/ports/cortex_a65/ac6/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports/cortex_a65/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a65/ac6/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports/cortex_a65/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a65/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_a65/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a65/ac6/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports/cortex_a65/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a65/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports/cortex_a65/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a65/ac6/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports/cortex_a65/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a65/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports/cortex_a65/ac6/src/tx_thread_schedule.S b/ports/cortex_a65/ac6/src/tx_thread_schedule.S index 4cce4a62..057aa538 100644 --- a/ports/cortex_a65/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a65/ac6/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,18 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_a65/ac6/src/tx_thread_stack_build.S b/ports/cortex_a65/ac6/src/tx_thread_stack_build.S index 6c675d9b..01084da7 100644 --- a/ports/cortex_a65/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a65/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_a65/ac6/src/tx_thread_system_return.S b/ports/cortex_a65/ac6/src/tx_thread_system_return.S index 780bb128..b7593d79 100644 --- a/ports/cortex_a65/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a65/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_a65/ac6/src/tx_timer_interrupt.S b/ports/cortex_a65/ac6/src/tx_timer_interrupt.S index d84245c6..1b80a7f2 100644 --- a/ports/cortex_a65/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a65/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_a65/gnu/example_build/sample_threadx/.cproject b/ports/cortex_a65/gnu/example_build/sample_threadx/.cproject index 1c32cb32..40d4912d 100644 --- a/ports/cortex_a65/gnu/example_build/sample_threadx/.cproject +++ b/ports/cortex_a65/gnu/example_build/sample_threadx/.cproject @@ -1,170 +1,170 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a65/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports/cortex_a65/gnu/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports/cortex_a65/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports/cortex_a65/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports/cortex_a65/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports/cortex_a65/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports/cortex_a65/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports/cortex_a65/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports/cortex_a65/gnu/example_build/sample_threadx/sample_threadx.ld b/ports/cortex_a65/gnu/example_build/sample_threadx/sample_threadx.ld index eec8f12b..3bf47736 100644 --- a/ports/cortex_a65/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports/cortex_a65/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start diff --git a/ports/cortex_a65/gnu/example_build/sample_threadx/startup.S b/ports/cortex_a65/gnu/example_build/sample_threadx/startup.S index b71b45f8..b44806fe 100644 --- a/ports/cortex_a65/gnu/example_build/sample_threadx/startup.S +++ b/ports/cortex_a65/gnu/example_build/sample_threadx/startup.S @@ -328,7 +328,7 @@ el1_entry_aarch64: // // Cortex-A processors automatically invalidate their caches on reset // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). - // It is therefore not necessary for software to invalidate the caches + // It is therefore not necessary for software to invalidate the caches // on startup, however, this is done here in case of a warm reset. bl InvalidateUDCaches tlbi VMALLE1 diff --git a/ports/cortex_a65/gnu/example_build/sample_threadx/v8_aarch64.h b/ports/cortex_a65/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports/cortex_a65/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports/cortex_a65/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_a65/gnu/example_build/sample_threadx/v8_mmu.h b/ports/cortex_a65/gnu/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports/cortex_a65/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports/cortex_a65/gnu/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports/cortex_a65/gnu/example_build/tx/.cproject b/ports/cortex_a65/gnu/example_build/tx/.cproject index f1b8ed5b..9e5a975e 100644 --- a/ports/cortex_a65/gnu/example_build/tx/.cproject +++ b/ports/cortex_a65/gnu/example_build/tx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a65/gnu/inc/tx_port.h b/ports/cortex_a65/gnu/inc/tx_port.h index a8d3fd48..e5352338 100644 --- a/ports/cortex_a65/gnu/inc/tx_port.h +++ b/ports/cortex_a65/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -369,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a65/gnu/src/tx_initialize_low_level.S b/ports/cortex_a65/gnu/src/tx_initialize_low_level.S index 3dce3cea..3025f12b 100644 --- a/ports/cortex_a65/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_a65/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -99,4 +89,4 @@ _tx_initialize_low_level: /* Done, return to caller. */ RET // Return to caller -// } +// } diff --git a/ports/cortex_a65/gnu/src/tx_thread_context_restore.S b/ports/cortex_a65/gnu/src/tx_thread_context_restore.S index 8e0d5515..9ba82827 100644 --- a/ports/cortex_a65/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a65/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_a65/gnu/src/tx_thread_context_save.S b/ports/cortex_a65/gnu/src/tx_thread_context_save.S index 7768efc2..c2395155 100644 --- a/ports/cortex_a65/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a65/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_a65/gnu/src/tx_thread_fp_disable.c b/ports/cortex_a65/gnu/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports/cortex_a65/gnu/src/tx_thread_fp_disable.c +++ b/ports/cortex_a65/gnu/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports/cortex_a65/gnu/src/tx_thread_fp_enable.c b/ports/cortex_a65/gnu/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports/cortex_a65/gnu/src/tx_thread_fp_enable.c +++ b/ports/cortex_a65/gnu/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports/cortex_a65/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a65/gnu/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports/cortex_a65/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a65/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_a65/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a65/gnu/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports/cortex_a65/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a65/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports/cortex_a65/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a65/gnu/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports/cortex_a65/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a65/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports/cortex_a65/gnu/src/tx_thread_schedule.S b/ports/cortex_a65/gnu/src/tx_thread_schedule.S index 4cce4a62..057aa538 100644 --- a/ports/cortex_a65/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a65/gnu/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,18 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_a65/gnu/src/tx_thread_stack_build.S b/ports/cortex_a65/gnu/src/tx_thread_stack_build.S index 6c675d9b..01084da7 100644 --- a/ports/cortex_a65/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a65/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_a65/gnu/src/tx_thread_system_return.S b/ports/cortex_a65/gnu/src/tx_thread_system_return.S index 780bb128..b7593d79 100644 --- a/ports/cortex_a65/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a65/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_a65/gnu/src/tx_timer_interrupt.S b/ports/cortex_a65/gnu/src/tx_timer_interrupt.S index d84245c6..1b80a7f2 100644 --- a/ports/cortex_a65/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a65/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_a65ae/ac6/example_build/sample_threadx/.cproject b/ports/cortex_a65ae/ac6/example_build/sample_threadx/.cproject index d2474a55..f0ea3c70 100644 --- a/ports/cortex_a65ae/ac6/example_build/sample_threadx/.cproject +++ b/ports/cortex_a65ae/ac6/example_build/sample_threadx/.cproject @@ -1,158 +1,158 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a65ae/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports/cortex_a65ae/ac6/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports/cortex_a65ae/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports/cortex_a65ae/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports/cortex_a65ae/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports/cortex_a65ae/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports/cortex_a65ae/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports/cortex_a65ae/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports/cortex_a65ae/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_a65ae/ac6/example_build/sample_threadx/sample_threadx.scat index e5783c7c..d8dfde69 100644 --- a/ports/cortex_a65ae/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports/cortex_a65ae/ac6/example_build/sample_threadx/sample_threadx.scat @@ -2,7 +2,7 @@ ; Scatter file for Armv8-A Startup code on FVP Base model ; Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************** @@ -25,7 +25,7 @@ LOAD 0x80000000 ; in source code for this to work correctly ; ARM_LIB_HEAP +0 ALIGN 64 EMPTY 0xA0000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary diff --git a/ports/cortex_a65ae/ac6/example_build/sample_threadx/v8_aarch64.h b/ports/cortex_a65ae/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports/cortex_a65ae/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports/cortex_a65ae/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_a65ae/ac6/example_build/sample_threadx/v8_mmu.h b/ports/cortex_a65ae/ac6/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports/cortex_a65ae/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports/cortex_a65ae/ac6/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports/cortex_a65ae/ac6/example_build/tx/.cproject b/ports/cortex_a65ae/ac6/example_build/tx/.cproject index bbfb6933..184e9a0f 100644 --- a/ports/cortex_a65ae/ac6/example_build/tx/.cproject +++ b/ports/cortex_a65ae/ac6/example_build/tx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a65ae/ac6/inc/tx_port.h b/ports/cortex_a65ae/ac6/inc/tx_port.h index a8d3fd48..e5352338 100644 --- a/ports/cortex_a65ae/ac6/inc/tx_port.h +++ b/ports/cortex_a65ae/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -369,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a65ae/ac6/src/tx_initialize_low_level.S b/ports/cortex_a65ae/ac6/src/tx_initialize_low_level.S index f456574e..7d2a4be3 100644 --- a/ports/cortex_a65ae/ac6/src/tx_initialize_low_level.S +++ b/ports/cortex_a65ae/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports/cortex_a65ae/ac6/src/tx_thread_context_restore.S b/ports/cortex_a65ae/ac6/src/tx_thread_context_restore.S index 8e0d5515..9ba82827 100644 --- a/ports/cortex_a65ae/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a65ae/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_a65ae/ac6/src/tx_thread_context_save.S b/ports/cortex_a65ae/ac6/src/tx_thread_context_save.S index 7768efc2..c2395155 100644 --- a/ports/cortex_a65ae/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a65ae/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_a65ae/ac6/src/tx_thread_fp_disable.c b/ports/cortex_a65ae/ac6/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports/cortex_a65ae/ac6/src/tx_thread_fp_disable.c +++ b/ports/cortex_a65ae/ac6/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports/cortex_a65ae/ac6/src/tx_thread_fp_enable.c b/ports/cortex_a65ae/ac6/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports/cortex_a65ae/ac6/src/tx_thread_fp_enable.c +++ b/ports/cortex_a65ae/ac6/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports/cortex_a65ae/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a65ae/ac6/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports/cortex_a65ae/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a65ae/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_a65ae/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a65ae/ac6/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports/cortex_a65ae/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a65ae/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports/cortex_a65ae/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a65ae/ac6/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports/cortex_a65ae/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a65ae/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports/cortex_a65ae/ac6/src/tx_thread_schedule.S b/ports/cortex_a65ae/ac6/src/tx_thread_schedule.S index 4cce4a62..057aa538 100644 --- a/ports/cortex_a65ae/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a65ae/ac6/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,18 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_a65ae/ac6/src/tx_thread_stack_build.S b/ports/cortex_a65ae/ac6/src/tx_thread_stack_build.S index 6c675d9b..01084da7 100644 --- a/ports/cortex_a65ae/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a65ae/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_a65ae/ac6/src/tx_thread_system_return.S b/ports/cortex_a65ae/ac6/src/tx_thread_system_return.S index 780bb128..b7593d79 100644 --- a/ports/cortex_a65ae/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a65ae/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_a65ae/ac6/src/tx_timer_interrupt.S b/ports/cortex_a65ae/ac6/src/tx_timer_interrupt.S index d84245c6..1b80a7f2 100644 --- a/ports/cortex_a65ae/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a65ae/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_a65ae/gnu/example_build/sample_threadx/.cproject b/ports/cortex_a65ae/gnu/example_build/sample_threadx/.cproject index 1c32cb32..40d4912d 100644 --- a/ports/cortex_a65ae/gnu/example_build/sample_threadx/.cproject +++ b/ports/cortex_a65ae/gnu/example_build/sample_threadx/.cproject @@ -1,170 +1,170 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a65ae/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports/cortex_a65ae/gnu/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports/cortex_a65ae/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports/cortex_a65ae/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports/cortex_a65ae/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports/cortex_a65ae/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports/cortex_a65ae/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports/cortex_a65ae/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports/cortex_a65ae/gnu/example_build/sample_threadx/sample_threadx.ld b/ports/cortex_a65ae/gnu/example_build/sample_threadx/sample_threadx.ld index eec8f12b..3bf47736 100644 --- a/ports/cortex_a65ae/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports/cortex_a65ae/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start diff --git a/ports/cortex_a65ae/gnu/example_build/sample_threadx/startup.S b/ports/cortex_a65ae/gnu/example_build/sample_threadx/startup.S index b71b45f8..b44806fe 100644 --- a/ports/cortex_a65ae/gnu/example_build/sample_threadx/startup.S +++ b/ports/cortex_a65ae/gnu/example_build/sample_threadx/startup.S @@ -328,7 +328,7 @@ el1_entry_aarch64: // // Cortex-A processors automatically invalidate their caches on reset // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). - // It is therefore not necessary for software to invalidate the caches + // It is therefore not necessary for software to invalidate the caches // on startup, however, this is done here in case of a warm reset. bl InvalidateUDCaches tlbi VMALLE1 diff --git a/ports/cortex_a65ae/gnu/example_build/sample_threadx/v8_aarch64.h b/ports/cortex_a65ae/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports/cortex_a65ae/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports/cortex_a65ae/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_a65ae/gnu/example_build/sample_threadx/v8_mmu.h b/ports/cortex_a65ae/gnu/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports/cortex_a65ae/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports/cortex_a65ae/gnu/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports/cortex_a65ae/gnu/example_build/tx/.cproject b/ports/cortex_a65ae/gnu/example_build/tx/.cproject index f1b8ed5b..9e5a975e 100644 --- a/ports/cortex_a65ae/gnu/example_build/tx/.cproject +++ b/ports/cortex_a65ae/gnu/example_build/tx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a65ae/gnu/inc/tx_port.h b/ports/cortex_a65ae/gnu/inc/tx_port.h index a8d3fd48..e5352338 100644 --- a/ports/cortex_a65ae/gnu/inc/tx_port.h +++ b/ports/cortex_a65ae/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -369,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a65ae/gnu/src/tx_initialize_low_level.S b/ports/cortex_a65ae/gnu/src/tx_initialize_low_level.S index 3dce3cea..3025f12b 100644 --- a/ports/cortex_a65ae/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_a65ae/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -99,4 +89,4 @@ _tx_initialize_low_level: /* Done, return to caller. */ RET // Return to caller -// } +// } diff --git a/ports/cortex_a65ae/gnu/src/tx_thread_context_restore.S b/ports/cortex_a65ae/gnu/src/tx_thread_context_restore.S index 8e0d5515..9ba82827 100644 --- a/ports/cortex_a65ae/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a65ae/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_a65ae/gnu/src/tx_thread_context_save.S b/ports/cortex_a65ae/gnu/src/tx_thread_context_save.S index 7768efc2..c2395155 100644 --- a/ports/cortex_a65ae/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a65ae/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_a65ae/gnu/src/tx_thread_fp_disable.c b/ports/cortex_a65ae/gnu/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports/cortex_a65ae/gnu/src/tx_thread_fp_disable.c +++ b/ports/cortex_a65ae/gnu/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports/cortex_a65ae/gnu/src/tx_thread_fp_enable.c b/ports/cortex_a65ae/gnu/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports/cortex_a65ae/gnu/src/tx_thread_fp_enable.c +++ b/ports/cortex_a65ae/gnu/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports/cortex_a65ae/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a65ae/gnu/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports/cortex_a65ae/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a65ae/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_a65ae/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a65ae/gnu/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports/cortex_a65ae/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a65ae/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports/cortex_a65ae/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a65ae/gnu/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports/cortex_a65ae/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a65ae/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports/cortex_a65ae/gnu/src/tx_thread_schedule.S b/ports/cortex_a65ae/gnu/src/tx_thread_schedule.S index 4cce4a62..057aa538 100644 --- a/ports/cortex_a65ae/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a65ae/gnu/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,18 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_a65ae/gnu/src/tx_thread_stack_build.S b/ports/cortex_a65ae/gnu/src/tx_thread_stack_build.S index 6c675d9b..01084da7 100644 --- a/ports/cortex_a65ae/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a65ae/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_a65ae/gnu/src/tx_thread_system_return.S b/ports/cortex_a65ae/gnu/src/tx_thread_system_return.S index 780bb128..b7593d79 100644 --- a/ports/cortex_a65ae/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a65ae/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_a65ae/gnu/src/tx_timer_interrupt.S b/ports/cortex_a65ae/gnu/src/tx_timer_interrupt.S index d84245c6..1b80a7f2 100644 --- a/ports/cortex_a65ae/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a65ae/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_a7/ac5/example_build/sample_threadx.c b/ports/cortex_a7/ac5/example_build/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports/cortex_a7/ac5/example_build/sample_threadx.c +++ b/ports/cortex_a7/ac5/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_a7/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_a7/ac5/example_build/tx_initialize_low_level.s index 22770ae1..49ce6c77 100644 --- a/ports/cortex_a7/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_a7/ac5/example_build/tx_initialize_low_level.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -110,45 +110,39 @@ Reset_Vector ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -199,7 +193,7 @@ _tx_initialize_low_level ; _tx_thread_system_stack_ptr = (VOID_PTR) (sp); ; LDR r1, =_tx_thread_system_stack_ptr ; Pickup address of system stack ptr - LDR r0, [r1, #0] ; Pickup system stack + LDR r0, [r1, #0] ; Pickup system stack ADD r0, r0, #4 ; Increment to next free word ; ; /* Save the first available memory address. */ @@ -221,7 +215,7 @@ _tx_initialize_low_level ; ; ;/* Define initial heap/stack routine for the ARM RealView (and ADS) startup code. This -; routine will set the initial stack to use the ThreadX IRQ & FIQ & +; routine will set the initial stack to use the ThreadX IRQ & FIQ & ; (optionally SYS) stack areas. */ ; EXPORT __user_initial_stackheap @@ -273,7 +267,7 @@ __tx_reserved_handler ; ; EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -281,21 +275,21 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; ; BL _tx_timer_interrupt ; Timer interrupt handler _tx_not_timer_interrupt ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ IF :DEF:TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -305,7 +299,7 @@ _tx_not_timer_interrupt ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ IF :DEF:TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -321,28 +315,28 @@ _tx_not_timer_interrupt __tx_example_vectored_irq_handler ; ; -; /* Save initial context and call context save to prepare for +; /* Save initial context and call context save to prepare for ; vectored ISR execution. */ ; ; STMDB sp!, {r0-r3} ; Save some scratch registers ; MRS r0, SPSR ; Pickup saved SPSR -; SUB lr, lr, #4 ; Adjust point of interrupt +; SUB lr, lr, #4 ; Adjust point of interrupt ; STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers ; BL _tx_thread_vectored_context_save ; Vectored context save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ; IF :DEF:TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_start @@ -351,7 +345,7 @@ __tx_example_vectored_irq_handler ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ; IF :DEF:TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_end @@ -373,11 +367,11 @@ __tx_fiq_processing_return ; /* At this point execution is still in the FIQ mode. The CPSR, point of ; interrupt, and all C scratch registers are available for use. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start ; from FIQ mode with interrupts disabled. This routine switches to the -; system mode and returns with FIQ interrupts enabled. +; system mode and returns with FIQ interrupts enabled. ; -; NOTE: It is very important to ensure all FIQ interrupts are cleared +; NOTE: It is very important to ensure all FIQ interrupts are cleared ; prior to enabling nested FIQ interrupts. */ IF :DEF:TX_ENABLE_FIQ_NESTING BL _tx_thread_fiq_nesting_start diff --git a/ports/cortex_a7/ac5/inc/tx_port.h b/ports/cortex_a7/ac5/inc/tx_port.h index 93e0d688..088fc91f 100644 --- a/ports/cortex_a7/ac5/inc/tx_port.h +++ b/ports/cortex_a7/ac5/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Cortex-A7/AC5 */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A7/AC5 */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -75,7 +67,7 @@ #include -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -111,12 +103,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -126,8 +118,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -174,7 +166,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -186,13 +178,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -206,11 +198,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -218,8 +210,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -246,21 +238,21 @@ typedef unsigned short USHORT; #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef __thumb - + #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (ULONG) __clz((unsigned int) m); \ - b = 31 - b; + b = 31 - b; #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -280,7 +272,7 @@ typedef unsigned short USHORT; { \ __enable_irq(); \ __enable_fiq(); \ - } + } #else @@ -289,7 +281,7 @@ typedef unsigned short USHORT; #define TX_RESTORE if (!interrupt_save_disabled) \ { \ __enable_irq(); \ - } + } #endif #else @@ -325,8 +317,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-A7/AC5 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A7/AC5 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a7/ac5/readme_threadx.txt b/ports/cortex_a7/ac5/readme_threadx.txt index 347a5ec9..9ebf1f2c 100644 --- a/ports/cortex_a7/ac5/readme_threadx.txt +++ b/ports/cortex_a7/ac5/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for Cortex-A7 + Microsoft's Azure RTOS ThreadX for Cortex-A7 Thumb & 32-bit Mode @@ -6,20 +6,20 @@ 1. Building the ThreadX run-time Library -First make sure you are in the "example_build" directory. Also, make sure that -you have setup your path and other environment variables necessary for the AC5 -Compiler. At this point you may run the build_threadx.bat batch file. This will -build the ThreadX run-time environment in the "example_build" directory. +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the AC5 +Compiler. At this point you may run the build_threadx.bat batch file. This will +build the ThreadX run-time environment in the "example_build" directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. 1.1 Building with Project Files -The ThreadX library can also be built via project files. Simply open -the tx.mcp file with project builder and select make. This will place +The ThreadX library can also be built via project files. Simply open +the tx.mcp file with project builder and select make. This will place the tx.a library file into the Debug sub-directory. @@ -28,45 +28,45 @@ the tx.a library file into the Debug sub-directory. The ThreadX demonstration is designed to execute under the ARM Windows-based simulator. -Building the demonstration is easy; simply execute the build_threadx_sample.bat -batch file while inside the "example_build" directory. +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with tx.a. The resulting file sample_threadx.axf +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.axf is a binary file that can be downloaded and executed on the ARM simulator. 2.0.1 Building with Project Files -The ThreadX demonstration can also be built via project files. Simply open -the sample_threadx.mcp file with project builder and select make. This will place +The ThreadX demonstration can also be built via project files. Simply open +the sample_threadx.mcp file with project builder and select make. This will place the sample_threadx.axf output image into the Debug sub-directory. 3. System Initialization -The entry point in ThreadX for the Cortex-A7 using AC5 tools is at label -__main. This is defined within the AC5 compiler's startup code. In -addition, this is where all static and global pre-set C variable +The entry point in ThreadX for the Cortex-A7 using AC5 tools is at label +__main. This is defined within the AC5 compiler's startup code. In +addition, this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. By default, the vector area is defined to be located in the Init area, -which is defined at the top of tx_initialize_low_level.s. This area is typically -located at 0. In situations where this is impossible, the vectors at the beginning +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. By default, the vector area is defined to be located in the Init area, +which is defined at the top of tx_initialize_low_level.s. This area is typically +located at 0. In situations where this is impossible, the vectors at the beginning of the Init area should be copied to address 0. This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 4. Assembler / Compiler Switches -The following are compiler switches used in building the demonstration +The following are compiler switches used in building the demonstration system: Compiler Switch Meaning @@ -82,10 +82,10 @@ Linker Switch Meaning -o demo.axf Specifies demo output file name --elf Specifies elf output file format --ro Specifies that Read-Only memory starts at address 0 - --first tx_initialize_low_level.o(Init) + --first tx_initialize_low_level.o(Init) Specifies that the first area loaded is Init --remove Remove unused areas - --list Specifies map file name + --list Specifies map file name --symbols Specifies symbols for map file --map Creates a map file @@ -96,161 +96,161 @@ Application Defines ThreadX assembly files. If used, it should be used on all assembly files and the generic C source of - ThreadX should be compiled with + ThreadX should be compiled with TX_ENABLE_FIQ_SUPPORT defined as well. --PD "TX_ENABLE_IRQ_NESTING SETL {TRUE}" This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. --PD "TX_ENABLE_FIQ_NESTING SETL {TRUE}" This assembler define enables FIQ - nested support. If FIQ nested + nested support. If FIQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. In addition, IRQ nesting should also be enabled. -DTX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ interrupt handling in the ThreadX - generic C source. This define + generic C source. This define should also be used in conjunction with the corresponding assembler - define. + define. -DTX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - -DTX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + -DTX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - -DTX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + -DTX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - -DTX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + -DTX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - -DTX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + -DTX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - -DTX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + -DTX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - -DTX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + -DTX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - -DTX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + -DTX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - -DTX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + -DTX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - -DTX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + -DTX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - -DTX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + -DTX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - -DTX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + -DTX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - -DTX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + -DTX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - -DTX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + -DTX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - -DTX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + -DTX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - -DTX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + -DTX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - -DTX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + -DTX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - -DTX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + -DTX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - -DTX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + -DTX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - -DTX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + -DTX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. -DTX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - -DTX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + -DTX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - -DTX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + -DTX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. 5. Register Usage and Stack Frames -The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -268,39 +268,39 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make it run faster, you can change the build_threadx.bat file to -remove the -g option and enable all compiler optimizations. +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A7 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-A7 vectors start at address zero. The demonstration system startup -Init area contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +Init area contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs @@ -311,12 +311,12 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.s: EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -324,7 +324,7 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -337,7 +337,7 @@ __tx_irq_processing_return 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.s: EXPORT __tx_irq_example_handler @@ -347,12 +347,12 @@ __tx_irq_example_handler STMDB sp!, {r0-r3} ; Save some scratch registers MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers BL _tx_thread_vectored_context_save ; Call the vectored IRQ context save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -369,22 +369,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.s. When nested IRQ interrupts are no longer required, calling the _tx_thread_irq_nesting_end service disables nesting by disabling -IRQ interrupts and switching back to IRQ mode in preparation for the IRQ +IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -392,10 +392,10 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* Enable nested IRQ interrupts. NOTE: Since this service returns -; with IRQ interrupts enabled, all IRQ interrupt sources must be +; with IRQ interrupts enabled, all IRQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start -; +; ; /* Application ISR call(s) go here! */ ; ; /* Disable nested IRQ interrupts. The mode is switched back to @@ -408,12 +408,12 @@ __tx_irq_processing_return 7.3 FIQ Interrupts -By default, Cortex-A7 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, Cortex-A7 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.s. @@ -422,7 +422,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.s. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.s: @@ -450,18 +450,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.s. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -477,7 +477,7 @@ __tx_fiq_processing_return ; interrupt, and all C scratch registers are available for use. */ ; ; /* Enable nested FIQ interrupts. NOTE: Since this service returns -; with FIQ interrupts enabled, all FIQ interrupt sources must be +; with FIQ interrupts enabled, all FIQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start ; @@ -493,28 +493,28 @@ __tx_fiq_processing_return 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.s in the Integrator sub-directories. 9. Thumb/Cortex-A7 Mixed Mode -By default, ThreadX is setup for running in Cortex-A7 32-bit mode. This is -also true for the demonstration system. It is possible to build any -ThreadX file and/or the application in Thumb mode. If any Thumb code -is used the entire ThreadX source- both C and assembly - should be built +By default, ThreadX is setup for running in Cortex-A7 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. If any Thumb code +is used the entire ThreadX source- both C and assembly - should be built with the "-apcs /interwork" option. 10. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); diff --git a/ports/cortex_a7/ac5/src/tx_thread_context_restore.s b/ports/cortex_a7/ac5/src/tx_thread_context_restore.s index 6020c253..031fe720 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_a7/ac5/src/tx_thread_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -54,44 +54,38 @@ SVC_MODE EQU 0x93 ; SVC mode ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -121,13 +115,13 @@ _tx_thread_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3, #0] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3, #0] ; Store the counter + STR r2, [r3, #0] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs diff --git a/ports/cortex_a7/ac5/src/tx_thread_context_save.s b/ports/cortex_a7/ac5/src/tx_thread_context_save.s index 3993d9f0..7c7be45c 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_context_save.s +++ b/ports/cortex_a7/ac5/src/tx_thread_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,43 +39,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -90,7 +84,7 @@ _tx_thread_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers IF :DEF:TX_ENABLE_FIQ_SUPPORT CPSID if ; Disable FIQ interrupts ENDIF @@ -108,7 +102,7 @@ _tx_thread_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -124,7 +118,7 @@ _tx_thread_context_save POP {lr} ; Recover ISR lr ENDIF - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; __tx_thread_not_nested_save ; } @@ -138,13 +132,13 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} ; Store other registers ; ; /* Save the current stack pointer in the thread's control block. */ @@ -164,7 +158,7 @@ __tx_thread_not_nested_save POP {lr} ; Recover ISR lr ENDIF - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ; else @@ -174,7 +168,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit @@ -189,7 +183,7 @@ __tx_thread_idle_system_save ENDIF ADD sp, sp, #16 ; Recover saved registers - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ;} diff --git a/ports/cortex_a7/ac5/src/tx_thread_fiq_context_restore.s b/ports/cortex_a7/ac5/src/tx_thread_fiq_context_restore.s index 44233091..0258ead2 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_a7/ac5/src/tx_thread_fiq_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -32,7 +32,7 @@ ; SVC_MODE EQU 0xD3 ; SVC mode FIQ_MODE EQU 0xD1 ; FIQ mode -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; ; @@ -50,44 +50,38 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_restore Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the fiq interrupt context when processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* FIQ ISR Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) @@ -113,13 +107,13 @@ _tx_thread_fiq_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3] ; Store the counter + STR r2, [r3] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -163,7 +157,7 @@ __tx_thread_fiq_no_preempt_restore ; /* Restore interrupted thread or ISR. */ ; ; /* Pickup the saved stack pointer. */ -; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; ; ; /* Recover the saved context and return to the point of interrupt. */ ; @@ -208,7 +202,7 @@ _tx_skip_fiq_vfp_save MOV r3, #1 ; Build interrupt stack type STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR STR sp, [r0, #8] ; Save stack pointer in thread control - ; block + ; block ; ; /* Save the remaining time-slice and disable it. */ ; if (_tx_timer_time_slice) @@ -220,7 +214,7 @@ _tx_skip_fiq_vfp_save BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it ; ; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; -; _tx_timer_time_slice = 0; +; _tx_timer_time_slice = 0; ; STR r2, [r0, #24] ; Save thread's time-slice MOV r2, #0 ; Clear value diff --git a/ports/cortex_a7/ac5/src/tx_thread_fiq_context_save.s b/ports/cortex_a7/ac5/src/tx_thread_fiq_context_save.s index eb969c1d..7be8a46f 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_fiq_context_save.s +++ b/ports/cortex_a7/ac5/src/tx_thread_fiq_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,43 +39,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_save Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) @@ -90,7 +84,7 @@ _tx_thread_fiq_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state CMP r2, #0 ; Is this the first interrupt? @@ -105,7 +99,7 @@ _tx_thread_fiq_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -121,38 +115,38 @@ _tx_thread_fiq_context_save POP {lr} ; Recover ISR lr ENDIF - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; __tx_thread_fiq_not_nested_save -; } +; } ; ; /* Otherwise, not nested, check to see if a thread was running. */ ; else if (_tx_thread_current_ptr) -; { +; { ; ADD r2, r2, #1 ; Increment the interrupt counter STR r2, [r3] ; Store it back in the variable LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in -; ; scheduling loop - nothing needs saving! + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, lr} ; Store other registers, Note that we don't -; ; need to save sl and ip since FIQ has -; ; copies of these registers. Nested +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested ; ; interrupt processing does need to save ; ; these registers. ; ; /* Save the current stack pointer in the thread's control block. */ -; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; ; ; /* Switch to the system stack. */ -; sp = _tx_thread_system_stack_ptr; +; sp = _tx_thread_system_stack_ptr; ; MOV r10, #0 ; Clear stack limit @@ -165,7 +159,7 @@ __tx_thread_fiq_not_nested_save POP {lr} ; Recover ISR lr ENDIF - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } ; else @@ -185,18 +179,18 @@ __tx_thread_fiq_idle_system_save ENDIF ; ; /* Not much to do here, save the current SPSR and LR for possible -; use in IRQ interrupted in idle system conditions, and return to +; use in IRQ interrupted in idle system conditions, and return to ; FIQ interrupt processing. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, lr} ; Store other registers that will get used -; ; or stripped off the stack in context -; ; restore - B __tx_fiq_processing_return ; Continue FIQ processing +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } -;} +;} ; END diff --git a/ports/cortex_a7/ac5/src/tx_thread_fiq_nesting_end.s b/ports/cortex_a7/ac5/src/tx_thread_fiq_nesting_end.s index 9062160c..8b2fc70b 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_fiq_nesting_end.s +++ b/ports/cortex_a7/ac5/src/tx_thread_fiq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,56 +34,50 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_end Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ -;/* processing from system mode back to FIQ mode prior to the ISR */ -;/* calling _tx_thread_fiq_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with FIQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) @@ -94,7 +88,7 @@ _tx_thread_fiq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_c, r0 ; Disable interrupts - LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports/cortex_a7/ac5/src/tx_thread_fiq_nesting_start.s b/ports/cortex_a7/ac5/src/tx_thread_fiq_nesting_start.s index a1456bd1..a94ff890 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_fiq_nesting_start.s +++ b/ports/cortex_a7/ac5/src/tx_thread_fiq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_start Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ -;/* processing to the system mode so nested FIQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with FIQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_a7/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_a7/ac5/src/tx_thread_interrupt_control.s index 0d422e49..c9d95a58 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_interrupt_control.s +++ b/ports/cortex_a7/ac5/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,42 +36,36 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a7/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_a7/ac5/src/tx_thread_interrupt_disable.s index 5653faf4..de174cb1 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_a7/ac5/src/tx_thread_interrupt_disable.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,41 +29,35 @@ ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(void) @@ -80,7 +74,7 @@ _tx_thread_interrupt_disable IF :DEF:TX_ENABLE_FIQ_SUPPORT CPSID if ; Disable IRQ and FIQ ELSE - CPSID i ; Disable IRQ + CPSID i ; Disable IRQ ENDIF IF {INTER} = {TRUE} diff --git a/ports/cortex_a7/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_a7/ac5/src/tx_thread_interrupt_restore.s index e9f15cc6..c2c32842 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_a7/ac5/src/tx_thread_interrupt_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,42 +29,36 @@ ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function is responsible for restoring interrupts to the state */ ;/* returned by a previous _tx_thread_interrupt_disable call. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a7/ac5/src/tx_thread_irq_nesting_end.s b/ports/cortex_a7/ac5/src/tx_thread_irq_nesting_end.s index f458cb21..73a88636 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_irq_nesting_end.s +++ b/ports/cortex_a7/ac5/src/tx_thread_irq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,56 +34,50 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_end Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -;/* processing from system mode back to IRQ mode prior to the ISR */ -;/* calling _tx_thread_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) @@ -94,7 +88,7 @@ _tx_thread_irq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_c, r0 ; Disable interrupts - LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports/cortex_a7/ac5/src/tx_thread_irq_nesting_start.s b/ports/cortex_a7/ac5/src/tx_thread_irq_nesting_start.s index 2f1814f8..d4c1ca06 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_irq_nesting_start.s +++ b/ports/cortex_a7/ac5/src/tx_thread_irq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_start Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_context_save has been called and switches the IRQ */ -;/* processing to the system mode so nested IRQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_a7/ac5/src/tx_thread_schedule.s b/ports/cortex_a7/ac5/src/tx_thread_schedule.s index a0f10476..5506bcf4 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_a7/ac5/src/tx_thread_schedule.s @@ -1,19 +1,19 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors -; * +; * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -41,45 +41,39 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -108,7 +102,7 @@ __tx_thread_schedule_loop ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Lockout interrupts and ; transfer control to it. */ ; @@ -121,7 +115,7 @@ __tx_thread_schedule_loop ; /* Setup the current thread pointer. */ ; _tx_thread_current_ptr = _tx_thread_execute_ptr; ; - LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread STR r0, [r1, #0] ; Setup current thread pointer ; ; /* Increment the run count for this thread. */ @@ -135,7 +129,7 @@ __tx_thread_schedule_loop ; /* Setup time-slice, if present. */ ; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; ; - LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice ; variable LDR sp, [r0, #8] ; Switch stack pointers STR r3, [r2, #0] ; Setup time-slice diff --git a/ports/cortex_a7/ac5/src/tx_thread_stack_build.s b/ports/cortex_a7/ac5/src/tx_thread_stack_build.s index a868d826..f89d73a6 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_stack_build.s +++ b/ports/cortex_a7/ac5/src/tx_thread_stack_build.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -41,44 +41,38 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function builds a stack frame on the supplied thread's stack. */ ;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ ;/* thread_ptr Pointer to thread control blk */ ;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -86,10 +80,10 @@ THUMB_BIT EQU 0x20 ; Thumb-bit EXPORT _tx_thread_stack_build _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-A7 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; a1 (r0) Initial value for a1 diff --git a/ports/cortex_a7/ac5/src/tx_thread_system_return.s b/ports/cortex_a7/ac5/src/tx_thread_system_return.s index 01e93435..cfaf4f84 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_system_return.s +++ b/ports/cortex_a7/ac5/src/tx_thread_system_return.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -33,50 +33,44 @@ IMPORT _tx_timer_time_slice IMPORT _tx_thread_schedule IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY - IMPORT _tx_execution_thread_exit + IMPORT _tx_execution_thread_exit ENDIF ; ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -104,7 +98,7 @@ _tx_skip_solicited_vfp_save MOV r0, #0 ; Build a solicited stack type MRS r1, CPSR ; Pickup the CPSR STMDB sp!, {r0-r1} ; Save type and CPSR -; +; ; /* Lockout interrupts. */ ; IF :DEF:TX_ENABLE_FIQ_SUPPORT diff --git a/ports/cortex_a7/ac5/src/tx_thread_vectored_context_save.s b/ports/cortex_a7/ac5/src/tx_thread_vectored_context_save.s index 1e9a2f82..d52a9776 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_vectored_context_save.s +++ b/ports/cortex_a7/ac5/src/tx_thread_vectored_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -38,43 +38,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_vectored_context_save Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) @@ -135,7 +129,7 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Note: Minimal context of interrupted thread is already saved. */ @@ -171,7 +165,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports/cortex_a7/ac5/src/tx_timer_interrupt.s b/ports/cortex_a7/ac5/src/tx_timer_interrupt.s index ce94e6e0..0a2a68f6 100644 --- a/ports/cortex_a7/ac5/src/tx_timer_interrupt.s +++ b/ports/cortex_a7/ac5/src/tx_timer_interrupt.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -44,46 +44,40 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -107,7 +101,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CMP r2, #0 ; Is it non-active? BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing @@ -225,13 +219,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CMP r2, #0 ; See if the flag is set BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing ; diff --git a/ports/cortex_a7/ac6/example_build/sample_threadx/.cproject b/ports/cortex_a7/ac6/example_build/sample_threadx/.cproject index e75dac72..c34527a9 100644 --- a/ports/cortex_a7/ac6/example_build/sample_threadx/.cproject +++ b/ports/cortex_a7/ac6/example_build/sample_threadx/.cproject @@ -1,176 +1,176 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a7/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_a7/ac6/example_build/sample_threadx/sample_threadx.scat index d23881cd..66d0d95a 100644 --- a/ports/cortex_a7/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports/cortex_a7/ac6/example_build/sample_threadx/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports/cortex_a7/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_a7/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 083a57a7..76395459 100644 --- a/ports/cortex_a7/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_a7/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -91,14 +92,6 @@ $_tx_initialize_low_level: /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ .global _tx_initialize_low_level .type _tx_initialize_low_level,function diff --git a/ports/cortex_a7/ac6/example_build/tx/.cproject b/ports/cortex_a7/ac6/example_build/tx/.cproject index 476321bb..f17f3f56 100644 --- a/ports/cortex_a7/ac6/example_build/tx/.cproject +++ b/ports/cortex_a7/ac6/example_build/tx/.cproject @@ -1,146 +1,146 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a7/ac6/inc/tx_port.h b/ports/cortex_a7/ac6/inc/tx_port.h index f9b96956..f0153046 100644 --- a/ports/cortex_a7/ac6/inc/tx_port.h +++ b/ports/cortex_a7/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,20 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Updated comments, removed */ -/* unneeded temp variable, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -320,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv7-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a7/ac6/readme_threadx.txt b/ports/cortex_a7/ac6/readme_threadx.txt index b9d6bf88..a18fa47d 100644 --- a/ports/cortex_a7/ac6/readme_threadx.txt +++ b/ports/cortex_a7/ac6/readme_threadx.txt @@ -1,18 +1,18 @@ - Microsoft's Azure RTOS ThreadX for Cortex-A7 + Microsoft's Azure RTOS ThreadX for Cortex-A7 Using ARM Compiler 6 & DS 1. Import the ThreadX Projects -In order to build the ThreadX library and the ThreadX demonstration, first import -the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +In order to build the ThreadX library and the ThreadX demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) into your DS workspace. 2. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply right-click the Eclipse project -"tx" and then select the "Build Project" button. You should now observe the compilation +Building the ThreadX library is easy; simply right-click the Eclipse project +"tx" and then select the "Build Project" button. You should now observe the compilation and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. @@ -22,44 +22,44 @@ library file tx.a. The ThreadX demonstration is designed to execute under the DS debugger on the VE_Cortex-A7 Bare Metal simulator. -Building the demonstration is easy; simply right-click the Eclipse project -"sample_threadx" and then select the "Build Project" button. You should now observe -the compilation and assembly of the ThreadX demonstration. This project build produces -the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder +Building the demonstration is easy; simply right-click the Eclipse project +"sample_threadx" and then select the "Build Project" button. You should now observe +the compilation and assembly of the ThreadX demonstration. This project build produces +the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder in the Project Explorer window, right-click on the 'cortex-a7_tx.launch' file, click 'Debug As', and then click 'cortex-a7_tx' from the submenu. This will cause the -debugger to load the sample_threadx.axf ELF file and run to main. You are now ready +debugger to load the sample_threadx.axf ELF file and run to main. You are now ready to execute the ThreadX demonstration. 4. System Initialization -The entry point in ThreadX for the Cortex-A7 using ARM tools is at label -"Vectors". This is defined within startup.S in the sample_threadx project. In addition, -this is where all static and global pre-set C variable initialization processing +The entry point in ThreadX for the Cortex-A7 using ARM tools is at label +"Vectors". This is defined within startup.S in the sample_threadx project. In addition, +this is where all static and global pre-set C variable initialization processing takes place. -This is also where initialization of a periodic timer interrupt source should take +This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level defines the first available address -for use by the application, which is supplied as the sole input parameter +In addition, _tx_initialize_low_level defines the first available address +for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 5. Register Usage and Stack Frames -The AC6 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The AC6 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -77,52 +77,52 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A7 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-A7 vectors start at address zero. The demonstration system startup -reset.S file contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +reset.S file contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs -ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -130,7 +130,7 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -143,7 +143,7 @@ __tx_irq_processing_return: 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_example_handler @@ -153,12 +153,12 @@ __tx_irq_example_handler: STMDB sp!, {r0-r3} @ Save some scratch registers MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers BL _tx_thread_vectored_context_save @ Call the vectored IRQ context save @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -175,22 +175,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.S. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables -nesting by disabling IRQ interrupts and switching back to IRQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -198,10 +198,10 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* Enable nested IRQ interrupts. NOTE: Since this service returns -@ with IRQ interrupts enabled, all IRQ interrupt sources must be +@ with IRQ interrupts enabled, all IRQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start -@ +@ @ /* Application ISR call(s) go here! */ @ @ /* Disable nested IRQ interrupts. The mode is switched back to @@ -214,12 +214,12 @@ __tx_irq_processing_return: 7.3 FIQ Interrupts -By default, FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.S. @@ -228,7 +228,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.S. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.S: @@ -256,18 +256,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.S. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -283,7 +283,7 @@ __tx_fiq_processing_return: @ interrupt, and all C scratch registers are available for use. */ @ @ /* Enable nested FIQ interrupts. NOTE: Since this service returns -@ with FIQ interrupts enabled, all FIQ interrupt sources must be +@ with FIQ interrupts enabled, all FIQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start @ @@ -299,12 +299,12 @@ __tx_fiq_processing_return: 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer -interrupt source, these services are not functional but the remainder of +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of ThreadX will still run. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.S for the demonstration system. @@ -312,7 +312,7 @@ found in the file tx_initialize_low_level.S for the demonstration system. 9. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); diff --git a/ports/cortex_a7/ac6/src/tx_thread_context_restore.S b/ports/cortex_a7/ac6/src/tx_thread_context_restore.S index 6b4a561d..41b0b0d0 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a7/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,23 +80,6 @@ IRQ_MODE = 0x12 // IRQ mode /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_restore .type _tx_thread_context_restore,function diff --git a/ports/cortex_a7/ac6/src/tx_thread_context_save.S b/ports/cortex_a7/ac6/src/tx_thread_context_save.S index eff06283..d2d29d34 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a7/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,23 +72,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_save .type _tx_thread_context_save,function diff --git a/ports/cortex_a7/ac6/src/tx_thread_fiq_context_restore.S b/ports/cortex_a7/ac6/src/tx_thread_fiq_context_restore.S index d2fbebe1..921c322c 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a7/ac6/src/tx_thread_fiq_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -78,20 +79,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* FIQ ISR Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_restore .type _tx_thread_fiq_context_restore,function diff --git a/ports/cortex_a7/ac6/src/tx_thread_fiq_context_save.S b/ports/cortex_a7/ac6/src/tx_thread_fiq_context_save.S index 88472a3d..2f1a6c40 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a7/ac6/src/tx_thread_fiq_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_save .type _tx_thread_fiq_context_save,function diff --git a/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_end.S index fa3886b8..a7ce701e 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_start.S index dbed1cf2..4f095dde 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a7/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a7/ac6/src/tx_thread_interrupt_control.S index d1223cb8..a5bc47f7 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a7/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,20 +69,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a7/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a7/ac6/src/tx_thread_interrupt_disable.S index a87d1a06..d7b53bc2 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a7/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,20 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a7/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a7/ac6/src/tx_thread_interrupt_restore.S index 53ff2813..3c31e94b 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a7/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,20 +68,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_end.S index 18aebc7c..cc4db3a7 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_start.S index a2ffd35d..3635874d 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a7/ac6/src/tx_thread_schedule.S b/ports/cortex_a7/ac6/src/tx_thread_schedule.S index f46a339b..a74e2050 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a7/ac6/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,23 +82,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a7/ac6/src/tx_thread_stack_build.S b/ports/cortex_a7/ac6/src/tx_thread_stack_build.S index 3876225a..827554a7 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a7/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,20 +75,6 @@ CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ int /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a7/ac6/src/tx_thread_system_return.S b/ports/cortex_a7/ac6/src/tx_thread_system_return.S index 0eed478d..1a17446b 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a7/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,23 +69,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a7/ac6/src/tx_thread_vectored_context_save.S b/ports/cortex_a7/ac6/src/tx_thread_vectored_context_save.S index fe8a98e8..91653b75 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a7/ac6/src/tx_thread_vectored_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_vectored_context_save .type _tx_thread_vectored_context_save,function diff --git a/ports/cortex_a7/ac6/src/tx_timer_interrupt.S b/ports/cortex_a7/ac6/src/tx_timer_interrupt.S index cb0c1fa2..179ac894 100644 --- a/ports/cortex_a7/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a7/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -77,20 +78,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a7/ghs/example_build/tx_initialize_low_level.arm b/ports/cortex_a7/ghs/example_build/tx_initialize_low_level.arm index 0d10366b..b4d024bf 100644 --- a/ports/cortex_a7/ghs/example_build/tx_initialize_low_level.arm +++ b/ports/cortex_a7/ghs/example_build/tx_initialize_low_level.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a7/ghs/inc/tx_el.h b/ports/cortex_a7/ghs/inc/tx_el.h index b8926921..72e5bbe3 100644 --- a/ports/cortex_a7/ghs/inc/tx_el.h +++ b/ports/cortex_a7/ghs/inc/tx_el.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,12 +37,6 @@ /* EventAnalyzer. It is assumed that tx_api.h and tx_port.h have */ /* already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_EL_H diff --git a/ports/cortex_a7/ghs/inc/tx_port.h b/ports/cortex_a7/ghs/inc/tx_port.h index f0f1e2c7..7fa32537 100644 --- a/ports/cortex_a7/ghs/inc/tx_port.h +++ b/ports/cortex_a7/ghs/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -394,7 +386,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-A7/Green Hills Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A7/Green Hills Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a7/ghs/readme_threadx.txt b/ports/cortex_a7/ghs/readme_threadx.txt index 3195b4e4..d7472f9e 100644 --- a/ports/cortex_a7/ghs/readme_threadx.txt +++ b/ports/cortex_a7/ghs/readme_threadx.txt @@ -1,19 +1,19 @@ - Microsoft's Azure RTOS ThreadX for Cortex-A7 + Microsoft's Azure RTOS ThreadX for Cortex-A7 Using the Green Hills Software Tools 1. Open the ThreadX Project Workspace -In order to build the ThreadX library and the ThreadX demonstration first load -the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the -"example_build" directory. +In order to build the ThreadX library and the ThreadX demonstration first load +the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the +"example_build" directory. 2. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply select the MULTI project file -tx.gpj and then select the build button. You should now observe the -compilation and assembly of the ThreadX library. This project build produces +Building the ThreadX library is easy; simply select the MULTI project file +tx.gpj and then select the build button. You should now observe the +compilation and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. @@ -21,55 +21,55 @@ the ThreadX library file tx.a. The ThreadX demonstration is designed to execute under the MULTI environment on the Green Hills Cortex-A7 simulator. The instructions that follow describe -how to get the ThreadX evaluation running under the MULTI Cortex-A7 simulation +how to get the ThreadX evaluation running under the MULTI Cortex-A7 simulation environment. -Building the demonstration is easy; simply select the MULTI project file -sample_threadx.gpj. At this point, select the "Project Build" button and observe -the compilation, assembly, and linkage of the ThreadX demonstration application. +Building the demonstration is easy; simply select the MULTI project file +sample_threadx.gpj. At this point, select the "Project Build" button and observe +the compilation, assembly, and linkage of the ThreadX demonstration application. -After the demonstration is built, invoke the MULTI ARM simulator by selecting -the simulator connection from within the sample_threadx.con connection file. -Once connected to the simulator, select the "Debug" button. You should now -observe the main function of sample_threadx.c. +After the demonstration is built, invoke the MULTI ARM simulator by selecting +the simulator connection from within the sample_threadx.con connection file. +Once connected to the simulator, select the "Debug" button. You should now +observe the main function of sample_threadx.c. At this point, you should setup a simulated timer interrupt for ThreadX by entering "timer 9999 irq" in the "target" window of the debugger. -You are now ready to execute the ThreadX demonstration system. Select -breakpoints and data watches to observe the execution of the sample_threadx.c +You are now ready to execute the ThreadX demonstration system. Select +breakpoints and data watches to observe the execution of the sample_threadx.c application. 4. EventAnalyzer Demonstration -To build a demonstration system that also logs events for the MULTI EventAnalyzer, -perform the same steps as the regular demo, except build the ThreadX library with -txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. -The resulting image will log all system events, which can then be displayed by the +To build a demonstration system that also logs events for the MULTI EventAnalyzer, +perform the same steps as the regular demo, except build the ThreadX library with +txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. +The resulting image will log all system events, which can then be displayed by the MULTI EventAnalyzer. 5. System Initialization -The system entry point using the Green Hills tools is at the label _start. -This is defined within the crt0.arm file supplied by Green Hills. In addition, -this is where all static and global preset C variable initialization +The system entry point using the Green Hills tools is at the label _start. +This is defined within the crt0.arm file supplied by Green Hills. In addition, +this is where all static and global preset C variable initialization processing is called from. After the Green Hills startup function returns, ThreadX initialization is called. The main initialization function is _tx_initialize_low_level and -is located in the file tx_initialize_low_level.arm. This function is responsible -for setting up various system data structures, interrupt vectors, and the +is located in the file tx_initialize_low_level.arm. This function is responsible +for setting up various system data structures, interrupt vectors, and the periodic timer interrupt source of ThreadX. -In addition, _tx_initialize_low_level determines where the first available +In addition, _tx_initialize_low_level determines where the first available RAM memory address is located. This address is supplied to tx_application_define. -By default, the first available RAM memory address is assumed to start at the -beginning of the ThreadX section .free_mem. If changes are made to the -sample_threadx.ld file, the .free_mem section should remain the last allocated -section in the main RAM area. The starting address of this section is passed +By default, the first available RAM memory address is assumed to start at the +beginning of the ThreadX section .free_mem. If changes are made to the +sample_threadx.ld file, the .free_mem section should remain the last allocated +section in the main RAM area. The starting address of this section is passed to tx_application_define. @@ -87,27 +87,27 @@ The following defines and their associated action are as follows: TX_ENABLE_FIQ_NESTING If defined, this brings in special FIQ interrupt nesting logic into the ThreadX library. This define should be applied - to the entire ThreadX library and the + to the entire ThreadX library and the define TX_ENABLE_FIQ_SUPPORT should also be defined. TX_ENABLE_FIQ_SUPPORT If defined, this brings in FIQ context save and restore logic necessary for applications to call ThreadX services from - FIQ interrupt handlers. This define - should be applied to the entire ThreadX + FIQ interrupt handlers. This define + should be applied to the entire ThreadX library. TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 4 in the "ThreadX User Guide" + Chapter 4 in the "ThreadX User Guide" for more details. TX_ENABLE_EVENT_LOGGING This define enables event logging for any or all of the ThreadX source code. If this - option is used anywhere, the tx_initialize_high_level.c + option is used anywhere, the tx_initialize_high_level.c file must be compiled with it as well, since this is where the event log is initialized. @@ -119,121 +119,121 @@ The following defines and their associated action are as follows: If this is enabled, run-time filtering logic is added to the event logging code. - TX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. 7. Register Usage and Stack Frames -The Green Hills compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) -are scratch registers for each function. All other registers used by a C -function must be preserved by the function. ThreadX takes advantage of this -in situations where a context switch happens as a result of making a ThreadX -service call (which is itself a C function). In such cases, the saved +The Green Hills compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) +are scratch registers for each function. All other registers used by a C +function must be preserved by the function. ThreadX takes advantage of this +in situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -251,40 +251,40 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 8. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make ThreadX run faster, you can change the tx.gpj project -to disable debug information and enable the desired optimizations. +to disable debug information and enable the desired optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined before tx_api.h is included. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. 9. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A7 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 9.1 Vector Area The Cortex-A7 vectors start at address zero. The demonstration system reset.arm -file contains the reset section (which contains all the ARM vectors) and is +file contains the reset section (which contains all the ARM vectors) and is typically loaded at address zero. On actual hardware platforms, this section -might have to be copied to address 0. +might have to be copied to address 0. 9.2 IRQ ISRs @@ -294,13 +294,13 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 9.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.arm: .globl __tx_irq_handler - .globl __tx_irq_processing_return + .globl __tx_irq_processing_return __tx_irq_handler: /* Jump to context save to save system context. */ @@ -308,7 +308,7 @@ __tx_irq_handler: __tx_irq_processing_return: /* At this point execution is still in the IRQ mode. The CPSR, point of - interrupt, and all C scratch registers are available for use. Note + interrupt, and all C scratch registers are available for use. Note that IRQ interrupts are still disabled upon return from the context save function. */ @@ -321,7 +321,7 @@ __tx_irq_processing_return: 9.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.arm: .globl __tx_irq_example_handler @@ -331,12 +331,12 @@ __tx_irq_example_handler: STMDB sp!, {r0-r3} # Save some scratch registers MRS r0, SPSR # Pickup saved SPSR - SUB lr, lr, #4 # Adjust point of interrupt + SUB lr, lr, #4 # Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} # Store other scratch registers BL _tx_thread_vectored_context_save # Call the vectored IRQ context save /* At this point execution is still in the IRQ mode. The CPSR, point of - interrupt, and all C scratch registers are available for use. Note + interrupt, and all C scratch registers are available for use. Note that IRQ interrupts are still disabled upon return from the context save function. */ @@ -353,22 +353,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.arm. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables nesting -by disabling IRQ interrupts and switching back to IRQ mode in preparation for +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.arm. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables nesting +by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in the +The following is an example of enabling IRQ nested interrupts in the typical IRQ handler: .globl __tx_irq_handler - .globl __tx_irq_processing_return + .globl __tx_irq_processing_return __tx_irq_handler: /* Jump to context save to save system context. */ @@ -376,10 +376,10 @@ __tx_irq_handler: __tx_irq_processing_return: /* Enable nested IRQ interrupts. NOTE: Since this service returns - with IRQ interrupts enabled, all IRQ interrupt sources must be + with IRQ interrupts enabled, all IRQ interrupt sources must be cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start - + /* Application ISR call(s) go here! */ /* Disable nested IRQ interrupts. The mode is switched back to @@ -392,9 +392,9 @@ __tx_irq_processing_return: 9.3 FIQ Interrupts -By default, Cortex-A7 FIQ interrupts are left completely enabled by ThreadX. -Of course, this means that the application is fully responsible for -saving/restoring any registers used in the FIQ ISR processing. In addition, +By default, Cortex-A7 FIQ interrupts are left completely enabled by ThreadX. +Of course, this means that the application is fully responsible for +saving/restoring any registers used in the FIQ ISR processing. In addition, no ThreadX service calls are allowed from the default FIQ ISRs. The default FIQ interrupt shell is located in tx_initialize_low_level.arm. @@ -403,7 +403,7 @@ FIQ interrupt shell is located in tx_initialize_low_level.arm. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.arm: @@ -431,18 +431,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.arm. When nested FIQ interrupts are no longer -required, calling the _tx_thread_fiq_nesting_end service disables nesting by -disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.arm. When nested FIQ interrupts are no longer +required, calling the _tx_thread_fiq_nesting_end service disables nesting by +disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -458,7 +458,7 @@ __tx_fiq_processing_return: interrupt, and all C scratch registers are available for use. */ /* Enable nested FIQ interrupts. NOTE: Since this service returns - with FIQ interrupts enabled, all FIQ interrupt sources must be + with FIQ interrupts enabled, all FIQ interrupt sources must be cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start @@ -475,29 +475,29 @@ __tx_fiq_processing_return: 10. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.arm. 11. Thumb/Cortex-A7 Mixed Mode -By default, ThreadX is setup for running in Cortex-A7 32-bit mode. This is -also true for the demonstration system. It is possible to build any +By default, ThreadX is setup for running in Cortex-A7 32-bit mode. This is +also true for the demonstration system. It is possible to build any ThreadX file and/or the application in Thumb mode. The only exception -to this is the file tx_thread_shell_entry.c. This file must always be +to this is the file tx_thread_shell_entry.c. This file must always be built in 32-bit mode. 12. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); @@ -520,7 +520,7 @@ information associated with this specific port of ThreadX: 04-02-2021 Release 6.1.6 changes: tx_port.h Updated macro definition -05/19/2020 Initial ThreadX version of Cortex-A7/Green Hills port. +05/19/2020 Initial ThreadX version of Cortex-A7/Green Hills port. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_a7/ghs/src/tx_el.c b/ports/cortex_a7/ghs/src/tx_el.c index 365622cd..b5d3b8b7 100644 --- a/ports/cortex_a7/ghs/src/tx_el.c +++ b/ports/cortex_a7/ghs/src/tx_el.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,12 +83,6 @@ UINT _tx_thread_interrupt_control(UINT new_posture); /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_el_initialize(VOID) { diff --git a/ports/cortex_a7/ghs/src/tx_thread_context_restore.arm b/ports/cortex_a7/ghs/src/tx_thread_context_restore.arm index fa173d80..91af8826 100644 --- a/ports/cortex_a7/ghs/src/tx_thread_context_restore.arm +++ b/ports/cortex_a7/ghs/src/tx_thread_context_restore.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a7/ghs/src/tx_thread_context_save.arm b/ports/cortex_a7/ghs/src/tx_thread_context_save.arm index f1608b92..d9752452 100644 --- a/ports/cortex_a7/ghs/src/tx_thread_context_save.arm +++ b/ports/cortex_a7/ghs/src/tx_thread_context_save.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a7/ghs/src/tx_thread_fiq_context_restore.arm b/ports/cortex_a7/ghs/src/tx_thread_fiq_context_restore.arm index 60c4e5fe..115e8d66 100644 --- a/ports/cortex_a7/ghs/src/tx_thread_fiq_context_restore.arm +++ b/ports/cortex_a7/ghs/src/tx_thread_fiq_context_restore.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a7/ghs/src/tx_thread_fiq_context_save.arm b/ports/cortex_a7/ghs/src/tx_thread_fiq_context_save.arm index 75182da9..c2123b80 100644 --- a/ports/cortex_a7/ghs/src/tx_thread_fiq_context_save.arm +++ b/ports/cortex_a7/ghs/src/tx_thread_fiq_context_save.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a7/ghs/src/tx_thread_fiq_nesting_end.arm b/ports/cortex_a7/ghs/src/tx_thread_fiq_nesting_end.arm index d6898821..16f82495 100644 --- a/ports/cortex_a7/ghs/src/tx_thread_fiq_nesting_end.arm +++ b/ports/cortex_a7/ghs/src/tx_thread_fiq_nesting_end.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a7/ghs/src/tx_thread_fiq_nesting_start.arm b/ports/cortex_a7/ghs/src/tx_thread_fiq_nesting_start.arm index 5f99bae6..af4dcd16 100644 --- a/ports/cortex_a7/ghs/src/tx_thread_fiq_nesting_start.arm +++ b/ports/cortex_a7/ghs/src/tx_thread_fiq_nesting_start.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a7/ghs/src/tx_thread_interrupt_control.arm b/ports/cortex_a7/ghs/src/tx_thread_interrupt_control.arm index d2ec35c7..e492cd80 100644 --- a/ports/cortex_a7/ghs/src/tx_thread_interrupt_control.arm +++ b/ports/cortex_a7/ghs/src/tx_thread_interrupt_control.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a7/ghs/src/tx_thread_interrupt_disable.arm b/ports/cortex_a7/ghs/src/tx_thread_interrupt_disable.arm index 36702beb..f12583d2 100644 --- a/ports/cortex_a7/ghs/src/tx_thread_interrupt_disable.arm +++ b/ports/cortex_a7/ghs/src/tx_thread_interrupt_disable.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a7/ghs/src/tx_thread_interrupt_restore.arm b/ports/cortex_a7/ghs/src/tx_thread_interrupt_restore.arm index aec3e0a2..bb8daa6c 100644 --- a/ports/cortex_a7/ghs/src/tx_thread_interrupt_restore.arm +++ b/ports/cortex_a7/ghs/src/tx_thread_interrupt_restore.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a7/ghs/src/tx_thread_irq_nesting_end.arm b/ports/cortex_a7/ghs/src/tx_thread_irq_nesting_end.arm index b5e7be09..3d35ef54 100644 --- a/ports/cortex_a7/ghs/src/tx_thread_irq_nesting_end.arm +++ b/ports/cortex_a7/ghs/src/tx_thread_irq_nesting_end.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a7/ghs/src/tx_thread_irq_nesting_start.arm b/ports/cortex_a7/ghs/src/tx_thread_irq_nesting_start.arm index 772ce870..f8ff6e7f 100644 --- a/ports/cortex_a7/ghs/src/tx_thread_irq_nesting_start.arm +++ b/ports/cortex_a7/ghs/src/tx_thread_irq_nesting_start.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a7/ghs/src/tx_thread_schedule.arm b/ports/cortex_a7/ghs/src/tx_thread_schedule.arm index 315c1f22..037e259e 100644 --- a/ports/cortex_a7/ghs/src/tx_thread_schedule.arm +++ b/ports/cortex_a7/ghs/src/tx_thread_schedule.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a7/ghs/src/tx_thread_stack_build.arm b/ports/cortex_a7/ghs/src/tx_thread_stack_build.arm index d1552846..2e07532a 100644 --- a/ports/cortex_a7/ghs/src/tx_thread_stack_build.arm +++ b/ports/cortex_a7/ghs/src/tx_thread_stack_build.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a7/ghs/src/tx_thread_system_return.arm b/ports/cortex_a7/ghs/src/tx_thread_system_return.arm index ec6e3a5e..ff6e8512 100644 --- a/ports/cortex_a7/ghs/src/tx_thread_system_return.arm +++ b/ports/cortex_a7/ghs/src/tx_thread_system_return.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a7/ghs/src/tx_thread_vectored_context_save.arm b/ports/cortex_a7/ghs/src/tx_thread_vectored_context_save.arm index dff3ef5c..4433de47 100644 --- a/ports/cortex_a7/ghs/src/tx_thread_vectored_context_save.arm +++ b/ports/cortex_a7/ghs/src/tx_thread_vectored_context_save.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a7/ghs/src/tx_timer_interrupt.arm b/ports/cortex_a7/ghs/src/tx_timer_interrupt.arm index 66e4639a..96753ba9 100644 --- a/ports/cortex_a7/ghs/src/tx_timer_interrupt.arm +++ b/ports/cortex_a7/ghs/src/tx_timer_interrupt.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a7/gnu/example_build/MP_GIC.h b/ports/cortex_a7/gnu/example_build/MP_GIC.h index c34e44c9..05c0f8a5 100644 --- a/ports/cortex_a7/gnu/example_build/MP_GIC.h +++ b/ports/cortex_a7/gnu/example_build/MP_GIC.h @@ -4,7 +4,7 @@ // // Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports/cortex_a7/gnu/example_build/MP_GIC.s b/ports/cortex_a7/gnu/example_build/MP_GIC.s index 7f175c69..6f093bd7 100644 --- a/ports/cortex_a7/gnu/example_build/MP_GIC.s +++ b/ports/cortex_a7/gnu/example_build/MP_GIC.s @@ -1,7 +1,7 @@ //---------------------------------------------------------------- // Copyright (c) 2005-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // // Cortex-A7MP example - Startup Code @@ -37,7 +37,7 @@ enableGIC: STR r1, [r0] // Write the GIC Enable Register (ICDDCR) BX lr - + // ------------------------------------------------------------ .global disableGIC @@ -54,7 +54,7 @@ disableGIC: STR r1, [r0] // Write the GIC Enable Register (ICDDCR) BX lr - + // ------------------------------------------------------------ @@ -84,10 +84,10 @@ enableIntID: STR r3, [r0, r2] // Store out (ICDISER) BX lr - + // ------------------------------------------------------------ - + .global disableIntID .type disableIntID,function // void disableIntID(unsigned int ID) @@ -112,7 +112,7 @@ disableIntID: STR r3, [r0, r2] // Store out (ICDICER) BX lr - + // ------------------------------------------------------------ @@ -130,7 +130,7 @@ setIntPriority: // r0 = base addr // r1 = priority // r2 = ID - + // Make sure that priority value is only 5 bits, and convert to expected format AND r1, r1, #0x1F MOV r1, r1, LSL #3 @@ -156,7 +156,7 @@ setIntPriority: STR r3, [r0] // And store it back again (ICDIPR) BX lr - + // ------------------------------------------------------------ @@ -175,7 +175,7 @@ enableGICProcessorInterface: STR r1, [r0, #0x0] // Write the Processor Interface Control register (ICCICR/ICPICR) BX lr - + // ------------------------------------------------------------ @@ -195,7 +195,7 @@ disableGICProcessorInterface: STR r1, [r0, #0x0] // Write the Processor Interface Control register (ICCICR/ICPICR) BX lr - + // ------------------------------------------------------------ @@ -214,8 +214,8 @@ setPriorityMask: STR r0, [r1, #0x4] // Write the Priority Mask register (ICCPMR/ICCIPMR) BX lr - - + + // ------------------------------------------------------------ .global setBinaryPoint @@ -231,7 +231,7 @@ setBinaryPoint: STR r0, [r1, #0x8] // Write the Binary register (ICCBPR/ICCBPR) BX lr - + // ------------------------------------------------------------ @@ -245,7 +245,7 @@ readIntAck: LDR r0, [r0, #0xC] // Read the Interrupt Acknowledge Register (ICCIAR) BX lr - + // ------------------------------------------------------------ @@ -262,8 +262,8 @@ writeEOI: STR r0, [r1, #0x10] // Write ID to the End of Interrupt register (ICCEOIR) BX lr - - + + //---------------------------------------------------------------- // SGI //---------------------------------------------------------------- diff --git a/ports/cortex_a7/gnu/example_build/MP_PrivateTimer.S b/ports/cortex_a7/gnu/example_build/MP_PrivateTimer.S index b1e2701b..7b83be9e 100644 --- a/ports/cortex_a7/gnu/example_build/MP_PrivateTimer.S +++ b/ports/cortex_a7/gnu/example_build/MP_PrivateTimer.S @@ -64,7 +64,7 @@ stop_private_timer: get_private_timer_count: BX lr - + // ------------------------------------------------------------ // void clear_private_timer_irq(void) diff --git a/ports/cortex_a7/gnu/example_build/reset.S b/ports/cortex_a7/gnu/example_build/reset.S index 3ce9efb7..f2e0522b 100644 --- a/ports/cortex_a7/gnu/example_build/reset.S +++ b/ports/cortex_a7/gnu/example_build/reset.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a7/gnu/example_build/sample_threadx.ld b/ports/cortex_a7/gnu/example_build/sample_threadx.ld index cb42c11c..d43e28f1 100644 --- a/ports/cortex_a7/gnu/example_build/sample_threadx.ld +++ b/ports/cortex_a7/gnu/example_build/sample_threadx.ld @@ -7,7 +7,7 @@ OUTPUT_ARCH(arm) SECTIONS { . = 0x00000000; - + .vectors : {reset.o(.text) } /* Read-only sections, merged into text segment: */ @@ -94,8 +94,8 @@ SECTIONS *(.gnu.linkonce.t*) *(.glue_7t) *(.glue_7) } =0 - .init : - { + .init : + { KEEP (*(.init)) } =0 _etext = .; @@ -120,7 +120,7 @@ SECTIONS .data1 : { *(.data1) } .eh_frame : { KEEP (*(.eh_frame)) } .gcc_except_table : { *(.gcc_except_table) } - .ctors : + .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is @@ -153,9 +153,9 @@ SECTIONS /* We want the small data sections together, so single-instruction offsets can access them all, and initialized data all before uninitialized, so we can shorten the on-disk segment size. */ - .sdata : + .sdata : { - *(.sdata) + *(.sdata) *(.sdata.*) *(.gnu.linkonce.s.*) } @@ -191,7 +191,7 @@ SECTIONS _stack_bottom = ABSOLUTE(.) ; - /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and + /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and SYS stack if nested interrupts are enabled. */ . = ALIGN(8) ; . += 4096 ; diff --git a/ports/cortex_a7/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_a7/gnu/example_build/tx_initialize_low_level.S index c5337622..9b49da8b 100644 --- a/ports/cortex_a7/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_a7/gnu/example_build/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -89,17 +90,6 @@ SYS_STACK_SIZE = 1024 // System stack size /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func @@ -249,7 +239,7 @@ __tx_irq_processing_return: if nested IRQ interrupts are desired. Interrupts may be re-enabled over small code sequences where lr is saved before enabling interrupts and restored after interrupts are again disabled. */ - + PUSH {r4, r5} // Save some preserved registers (r5 is saved just for 8-byte alignment) BL readIntAck MOV r4, r0 diff --git a/ports/cortex_a7/gnu/example_build/v7.h b/ports/cortex_a7/gnu/example_build/v7.h index 5a08b43f..c18b945c 100644 --- a/ports/cortex_a7/gnu/example_build/v7.h +++ b/ports/cortex_a7/gnu/example_build/v7.h @@ -4,7 +4,7 @@ // // Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports/cortex_a7/gnu/example_build/v7.s b/ports/cortex_a7/gnu/example_build/v7.s index 82c9ab1e..9487ddde 100644 --- a/ports/cortex_a7/gnu/example_build/v7.s +++ b/ports/cortex_a7/gnu/example_build/v7.s @@ -3,7 +3,7 @@ // // Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ @@ -20,7 +20,7 @@ enableInterrupts: CPSIE i BX lr - + .global disableInterrupts .type disableInterrupts,function @@ -28,7 +28,7 @@ enableInterrupts: disableInterrupts: CPSID i BX lr - + // ------------------------------------------------------------ // Cache Maintenance @@ -44,7 +44,7 @@ enableCaches: MCR p15, 0, r0, c1, c0, 0 // Write System Control Register ISB BX lr - + .global disableCaches @@ -57,7 +57,7 @@ disableCaches: MCR p15, 0, r0, c1, c0, 0 // Write System Control Register ISB BX lr - + .global cleanDCache @@ -114,7 +114,7 @@ clean_dcache_finished: POP {r4-r12} BX lr - + .global cleanInvalidateDCache .type cleanInvalidateDCache,function @@ -170,7 +170,7 @@ clean_invalidate_dcache_finished: POP {r4-r12} BX lr - + .global invalidateCaches @@ -229,7 +229,7 @@ invalidate_caches_skip: invalidate_caches_finished: POP {r4-r12} BX lr - + .global invalidateCaches_IS @@ -284,7 +284,7 @@ invalidate_caches_is_skip: invalidate_caches_is_finished: POP {r4-r12} BX lr - + // ------------------------------------------------------------ // TLB @@ -297,7 +297,7 @@ invalidateUnifiedTLB: MOV r0, #0 MCR p15, 0, r0, c8, c7, 0 // TLBIALL - Invalidate entire unified TLB BX lr - + .global invalidateUnifiedTLB_IS .type invalidateUnifiedTLB_IS,function @@ -306,7 +306,7 @@ invalidateUnifiedTLB_IS: MOV r0, #1 MCR p15, 0, r0, c8, c3, 0 // TLBIALLIS - Invalidate entire unified TLB Inner Shareable BX lr - + // ------------------------------------------------------------ // Branch Prediction @@ -319,7 +319,7 @@ flushBranchTargetCache: MOV r0, #0 MCR p15, 0, r0, c7, c5, 6 // BPIALL - Invalidate entire branch predictor array BX lr - + .global flushBranchTargetCache_IS .type flushBranchTargetCache_IS,function @@ -328,7 +328,7 @@ flushBranchTargetCache_IS: MOV r0, #0 MCR p15, 0, r0, c7, c1, 6 // BPIALLIS - Invalidate entire branch predictor array Inner Shareable BX lr - + // ------------------------------------------------------------ // High Vecs @@ -343,7 +343,7 @@ enableHighVecs: MCR p15, 0, r0, c1, c0, 0 // Write Control Register ISB BX lr - + .global disableHighVecs .type disableHighVecs,function @@ -354,7 +354,7 @@ disableHighVecs: MCR p15, 0, r0, c1, c0, 0 // Write Control Register ISB BX lr - + // ------------------------------------------------------------ // Context ID @@ -366,7 +366,7 @@ disableHighVecs: getContextID: MRC p15, 0, r0, c13, c0, 1 // Read Context ID Register BX lr - + .global setContextID .type setContextID,function @@ -374,7 +374,7 @@ getContextID: setContextID: MCR p15, 0, r0, c13, c0, 1 // Write Context ID Register BX lr - + // ------------------------------------------------------------ // ID registers @@ -386,7 +386,7 @@ setContextID: getMIDR: MRC p15, 0, r0, c0, c0, 0 // Read Main ID Register (MIDR) BX lr - + .global getMPIDR .type getMPIDR,function @@ -394,7 +394,7 @@ getMIDR: getMPIDR: MRC p15, 0, r0, c0 ,c0, 5// Read Multiprocessor ID register (MPIDR) BX lr - + // ------------------------------------------------------------ // CP15 SMP related @@ -407,7 +407,7 @@ getMPIDR: getBaseAddr: MRC p15, 4, r0, c15, c0, 0 // Read peripheral base address BX lr - + // ------------------------------------------------------------ @@ -419,7 +419,7 @@ getCPUID: MRC p15, 0, r0, c0, c0, 5 // Read CPU ID register AND r0, r0, #0x03 // Mask off, leaving the CPU ID field BX lr - + // ------------------------------------------------------------ @@ -431,7 +431,7 @@ goToSleep: WFI // Go into standby B goToSleep // Catch in case of rogue events BX lr - + // ------------------------------------------------------------ @@ -451,7 +451,7 @@ joinSMP: ISB BX lr - + // ------------------------------------------------------------ @@ -469,7 +469,7 @@ leaveSMP: ISB BX lr - + // ------------------------------------------------------------ // End of v7.s diff --git a/ports/cortex_a7/gnu/inc/tx_port.h b/ports/cortex_a7/gnu/inc/tx_port.h index f9b96956..f0153046 100644 --- a/ports/cortex_a7/gnu/inc/tx_port.h +++ b/ports/cortex_a7/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,20 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Updated comments, removed */ -/* unneeded temp variable, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -320,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv7-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a7/gnu/readme_threadx.txt b/ports/cortex_a7/gnu/readme_threadx.txt index 446d6bcf..32ab1df3 100644 --- a/ports/cortex_a7/gnu/readme_threadx.txt +++ b/ports/cortex_a7/gnu/readme_threadx.txt @@ -1,55 +1,55 @@ - Microsoft's Azure RTOS ThreadX for Cortex-A7 + Microsoft's Azure RTOS ThreadX for Cortex-A7 Using the GNU Tools 1. Building the ThreadX run-time Library -First make sure you are in the "example_build" directory. Also, make sure that -you have setup your path and other environment variables necessary for the GNU -development environment. +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the GNU +development environment. -At this point you may run the build_threadx.bat batch file. This will build the -ThreadX run-time environment in the "example_build" directory. +At this point you may run the build_threadx.bat batch file. This will build the +ThreadX run-time environment in the "example_build" directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. 2. Demonstration System -Building the demonstration is easy; simply execute the build_threadx_sample.bat -batch file while inside the "example_build" directory. +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with TX.A. The resulting file DEMO is a binary file +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with TX.A. The resulting file DEMO is a binary file that can be downloaded and executed. 3. System Initialization -The entry point in ThreadX for the Cortex-A7 using GNU tools is at label _start. +The entry point in ThreadX for the Cortex-A7 using GNU tools is at label _start. This is defined within the modified version of the GNU startup code - crt0.S. -The ThreadX tx_initialize_low_level.S file is responsible for setting up various -system data structures, the interrupt vectors, and a periodic timer interrupt source. -By default, the vector area is defined to be located at the "__vectors" label, -which is defined in reset.S. This area is typically located at 0. In situations -where this is impossible, the vectors at the "__vectors" label should be copied +The ThreadX tx_initialize_low_level.S file is responsible for setting up various +system data structures, the interrupt vectors, and a periodic timer interrupt source. +By default, the vector area is defined to be located at the "__vectors" label, +which is defined in reset.S. This area is typically located at 0. In situations +where this is impossible, the vectors at the "__vectors" label should be copied to address 0. -This is also where initialization of a periodic timer interrupt source should take +This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level defines the first available address -for use by the application, which is supplied as the sole input parameter +In addition, _tx_initialize_low_level defines the first available address +for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 4. Assembler / Compiler Switches -The following are compiler switches used in building the demonstration +The following are compiler switches used in building the demonstration system: Compiler/Assembler Meaning @@ -73,164 +73,164 @@ Application Defines ( -D option) ThreadX assembly files. If used, it should be used on all assembly files and the generic C source of - ThreadX should be compiled with + ThreadX should be compiled with TX_ENABLE_FIQ_SUPPORT defined as well. TX_ENABLE_IRQ_NESTING This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.S. TX_ENABLE_FIQ_NESTING This assembler define enables FIQ - nested support. If FIQ nested + nested support. If FIQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.S. In addition, IRQ nesting should also be enabled. TX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ interrupt handling in the ThreadX - generic C source. This define + generic C source. This define should also be used in conjunction with the corresponding assembler - define. + define. TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - TX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. 5. Register Usage and Stack Frames -The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -248,52 +248,52 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A7 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-A7 vectors start at address zero. The demonstration system startup -reset.S file contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +reset.S file contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs -ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -301,7 +301,7 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -314,7 +314,7 @@ __tx_irq_processing_return: 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_example_handler @@ -324,12 +324,12 @@ __tx_irq_example_handler: STMDB sp!, {r0-r3} @ Save some scratch registers MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers BL _tx_thread_vectored_context_save @ Call the vectored IRQ context save @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -346,22 +346,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.S. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables -nesting by disabling IRQ interrupts and switching back to IRQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -369,10 +369,10 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* Enable nested IRQ interrupts. NOTE: Since this service returns -@ with IRQ interrupts enabled, all IRQ interrupt sources must be +@ with IRQ interrupts enabled, all IRQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start -@ +@ @ /* Application ISR call(s) go here! */ @ @ /* Disable nested IRQ interrupts. The mode is switched back to @@ -385,12 +385,12 @@ __tx_irq_processing_return: 7.3 FIQ Interrupts -By default, FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.S. @@ -399,7 +399,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.S. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.S: @@ -427,18 +427,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.S. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -454,7 +454,7 @@ __tx_fiq_processing_return: @ interrupt, and all C scratch registers are available for use. */ @ @ /* Enable nested FIQ interrupts. NOTE: Since this service returns -@ with FIQ interrupts enabled, all FIQ interrupt sources must be +@ with FIQ interrupts enabled, all FIQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start @ @@ -470,12 +470,12 @@ __tx_fiq_processing_return: 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer -interrupt source, these services are not functional but the remainder of +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of ThreadX will still run. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.S for the demonstration system. @@ -483,7 +483,7 @@ found in the file tx_initialize_low_level.S for the demonstration system. 9. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); diff --git a/ports/cortex_a7/gnu/src/tx_thread_context_restore.S b/ports/cortex_a7/gnu/src/tx_thread_context_restore.S index 6b4a561d..41b0b0d0 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a7/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,23 +80,6 @@ IRQ_MODE = 0x12 // IRQ mode /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_restore .type _tx_thread_context_restore,function diff --git a/ports/cortex_a7/gnu/src/tx_thread_context_save.S b/ports/cortex_a7/gnu/src/tx_thread_context_save.S index eff06283..d2d29d34 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a7/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,23 +72,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_save .type _tx_thread_context_save,function diff --git a/ports/cortex_a7/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_a7/gnu/src/tx_thread_fiq_context_restore.S index d2fbebe1..921c322c 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a7/gnu/src/tx_thread_fiq_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -78,20 +79,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* FIQ ISR Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_restore .type _tx_thread_fiq_context_restore,function diff --git a/ports/cortex_a7/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_a7/gnu/src/tx_thread_fiq_context_save.S index 88472a3d..2f1a6c40 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a7/gnu/src/tx_thread_fiq_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_save .type _tx_thread_fiq_context_save,function diff --git a/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_end.S index fa3886b8..a7ce701e 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_start.S index dbed1cf2..4f095dde 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a7/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a7/gnu/src/tx_thread_interrupt_control.S index d1223cb8..a5bc47f7 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a7/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,20 +69,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a7/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a7/gnu/src/tx_thread_interrupt_disable.S index a87d1a06..d7b53bc2 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a7/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,20 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a7/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a7/gnu/src/tx_thread_interrupt_restore.S index 53ff2813..3c31e94b 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a7/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,20 +68,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_end.S index 18aebc7c..cc4db3a7 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_start.S index a2ffd35d..3635874d 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a7/gnu/src/tx_thread_schedule.S b/ports/cortex_a7/gnu/src/tx_thread_schedule.S index f46a339b..a74e2050 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a7/gnu/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,23 +82,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a7/gnu/src/tx_thread_stack_build.S b/ports/cortex_a7/gnu/src/tx_thread_stack_build.S index 3876225a..827554a7 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a7/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,20 +75,6 @@ CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ int /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a7/gnu/src/tx_thread_system_return.S b/ports/cortex_a7/gnu/src/tx_thread_system_return.S index 0eed478d..1a17446b 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a7/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,23 +69,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a7/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_a7/gnu/src/tx_thread_vectored_context_save.S index fe8a98e8..91653b75 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a7/gnu/src/tx_thread_vectored_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_vectored_context_save .type _tx_thread_vectored_context_save,function diff --git a/ports/cortex_a7/gnu/src/tx_timer_interrupt.S b/ports/cortex_a7/gnu/src/tx_timer_interrupt.S index cb0c1fa2..179ac894 100644 --- a/ports/cortex_a7/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a7/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -77,20 +78,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a7/iar/example_build/cstartup.s b/ports/cortex_a7/iar/example_build/cstartup.s index 647de2e8..b4ed8f87 100644 --- a/ports/cortex_a7/iar/example_build/cstartup.s +++ b/ports/cortex_a7/iar/example_build/cstartup.s @@ -1,7 +1,7 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; -;; Part one of the system initialization code, +;; Part one of the system initialization code, ;; contains low-level ;; initialization. ;; @@ -71,13 +71,13 @@ FIQ_Addr: DCD __tx_fiq_handler SECTION .text:CODE:NOROOT(2) -; PUBLIC ?cstartup +; PUBLIC ?cstartup EXTERN ?main REQUIRE __vector - ARM - -__iar_program_start: + ARM + +__iar_program_start: ?cstartup: ; diff --git a/ports/cortex_a7/iar/example_build/sample_threadx.c b/ports/cortex_a7/iar/example_build/sample_threadx.c index c2cc9886..02183317 100644 --- a/ports/cortex_a7/iar/example_build/sample_threadx.c +++ b/ports/cortex_a7/iar/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -83,42 +83,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -126,23 +126,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -245,11 +245,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -308,7 +308,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -361,7 +361,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_a7/iar/example_build/tx_initialize_low_level.s b/ports/cortex_a7/iar/example_build/tx_initialize_low_level.s index c30a14aa..6252bba4 100644 --- a/ports/cortex_a7/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_a7/iar/example_build/tx_initialize_low_level.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -62,7 +62,7 @@ SYS_MODE DEFINE 0xDF ; Disable irq,fiq SYS mode ; ; ; -;/* Define the FREE_MEM segment that will specify where free memory is +;/* Define the FREE_MEM segment that will specify where free memory is ; defined. This must also be located in at the end of other RAM segments ; in the linker control file. The value of this segment is what is passed ; to tx_application_define. */ @@ -75,45 +75,39 @@ __tx_free_memory_start ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-A7/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -146,7 +140,7 @@ _tx_initialize_low_level ; LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address STR r0, [r2, #0] ; Save first free memory address -; +; ; /* Setup Timer for periodic interrupts. */ ; ; /* Done, return to caller. */ @@ -188,7 +182,7 @@ __tx_reserved_handler RSEG .text:CODE:NOROOT(2) PUBLIC __tx_irq_handler RSEG .text:CODE:NOROOT(2) - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -196,17 +190,17 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -221,7 +215,7 @@ __tx_irq_processing_return ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -240,22 +234,22 @@ __tx_irq_processing_return ; /* Jump to context save to save system context. */ ; STMDB sp!, {r0-r3} ; Save some scratch registers ; MRS r0, SPSR ; Pickup saved SPSR -; SUB lr, lr, #4 ; Adjust point of interrupt +; SUB lr, lr, #4 ; Adjust point of interrupt ; STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; BL _tx_thread_vectored_context_save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ;#ifdef TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_start @@ -264,7 +258,7 @@ __tx_irq_processing_return ; /* Application IRQ handler is called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ;#ifdef TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_end @@ -288,11 +282,11 @@ __tx_fiq_processing_return ; /* At this point execution is still in the FIQ mode. The CPSR, point of ; interrupt, and all C scratch registers are available for use. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start ; from FIQ mode with interrupts disabled. This routine switches to the -; system mode and returns with FIQ interrupts enabled. +; system mode and returns with FIQ interrupts enabled. ; -; NOTE: It is very important to ensure all FIQ interrupts are cleared +; NOTE: It is very important to ensure all FIQ interrupts are cleared ; prior to enabling nested FIQ interrupts. */ #ifdef TX_ENABLE_FIQ_NESTING BL _tx_thread_fiq_nesting_start diff --git a/ports/cortex_a7/iar/inc/tx_port.h b/ports/cortex_a7/iar/inc/tx_port.h index 48f211d8..90477b76 100644 --- a/ports/cortex_a7/iar/inc/tx_port.h +++ b/ports/cortex_a7/iar/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Cortex-A7/IAR */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A7/IAR */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -79,7 +71,7 @@ #endif -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -115,12 +107,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -130,8 +122,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -188,7 +180,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -202,18 +194,18 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ - VOID *tx_thread_iar_tls_pointer; + VOID *tx_thread_iar_tls_pointer; #else #define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; #endif -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -227,11 +219,11 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -241,23 +233,23 @@ ULONG _tx_misra_time_stamp_get(VOID); #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #if (__VER__ < 8000000) -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #endif #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -285,8 +277,8 @@ void __iar_Initlocks(void); #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -297,22 +289,22 @@ void __iar_Initlocks(void); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (UINT) __CLZ(m); \ - b = 31 - b; + b = 31 - b; #endif #endif #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ /* First, check and see what mode the file is being compiled in. The IAR compiler - defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode + defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode is present. If ARM 32-bit mode is present, the fast CPSR manipulation macros are available. Otherwise, if Thumb mode is present, we must use function calls. */ @@ -381,8 +373,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-A7/IAR Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A7/IAR Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a7/iar/readme_threadx.txt b/ports/cortex_a7/iar/readme_threadx.txt index 7f16ed21..504b26ed 100644 --- a/ports/cortex_a7/iar/readme_threadx.txt +++ b/ports/cortex_a7/iar/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for Cortex-A7 + Microsoft's Azure RTOS ThreadX for Cortex-A7 Thumb & 32-bit Mode @@ -7,10 +7,10 @@ 1. Building the ThreadX run-time Library Building the ThreadX library is easy. First, open the Azure RTOS workspace -azure_rtos.eww. Next, make the TX project the "active project" in the -IAR Embedded Workbench and select the "Make" button. You should observe -assembly and compilation of a series of ThreadX source files. This -results in the ThreadX run-time library file tx.a, which is needed by +azure_rtos.eww. Next, make the TX project the "active project" in the +IAR Embedded Workbench and select the "Make" button. You should observe +assembly and compilation of a series of ThreadX source files. This +results in the ThreadX run-time library file tx.a, which is needed by the application. @@ -20,47 +20,47 @@ The ThreadX demonstration is designed to execute under the IAR Windows-based Cortex-A7 simulator. Building the demonstration is easy; simply make the sample_threadx.ewp project -the "active project" in the IAR Embedded Workbench and select the +the "active project" in the IAR Embedded Workbench and select the "Make" button. -You should observe the compilation of sample_threadx.c (which is the demonstration +You should observe the compilation of sample_threadx.c (which is the demonstration application) and linking with tx.a. The resulting file sample_threadx.out is a binary file that can be downloaded and executed on IAR's Cortex-A7 simulator. 3. System Initialization -The entry point in ThreadX for the Cortex-A7 using IAR tools is at label -?cstartup. This is defined within the IAR compiler's startup code. In -addition, this is where all static and global preset C variable +The entry point in ThreadX for the Cortex-A7 using IAR tools is at label +?cstartup. This is defined within the IAR compiler's startup code. In +addition, this is where all static and global preset C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, and a periodic timer interrupt source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. By default, the vector area is defined at the top of cstartup.s, which is -a slightly modified from the base IAR file. +a slightly modified from the base IAR file. The _tx_initialize_low_level function inside of tx_initialize_low_level.s -also determines the first available address for use by the application, which -is supplied as the sole input parameter to your application definition function, -tx_application_define. To accomplish this, a section is created in -tx_initialize_low_level.s called FREE_MEM, which must be located after all +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all other RAM sections in memory. 4. Register Usage and Stack Frames -The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are -scratch registers for each function. All other registers used by a C function -must be preserved by the function. ThreadX takes advantage of this in -situations where a context switch happens as a result of making a ThreadX -service call (which is itself a C function). In such cases, the saved +The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are +scratch registers for each function. All other registers used by a C function +must be preserved by the function. ThreadX takes advantage of this in +situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -78,12 +78,12 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 5. Conditional Compilation Switches @@ -92,146 +92,146 @@ The following are conditional compilation options for building the ThreadX libra and application: - TX_ENABLE_FIQ_SUPPORT This assembler/compiler define enables + TX_ENABLE_FIQ_SUPPORT This assembler/compiler define enables FIQ interrupt handling support in the ThreadX assembly files. If used, it should be used on all assembly files and the generic C source of - ThreadX should be compiled with + ThreadX should be compiled with TX_ENABLE_FIQ_SUPPORT defined as well. TX_ENABLE_IRQ_NESTING This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. TX_ENABLE_FIQ_NESTING This assembler define enables FIQ - nested support. If FIQ nested + nested support. If FIQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. In addition, IRQ nesting should also be enabled. TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - TX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. TX_THUMB Defined, this option enables the BX LR calling return sequence @@ -245,29 +245,29 @@ and application: 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the ThreadX library -project to enable various compiler optimizations. +project to enable various compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A7 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-A7 vectors start at address zero. The demonstration system startup -cstartup.s file contains the vectors and is loaded at address zero. -On actual hardware platforms, this area might have to be copied to address 0. +cstartup.s file contains the vectors and is loaded at address zero. +On actual hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs @@ -278,12 +278,12 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.s: PUBLIC __tx_irq_handler - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -291,7 +291,7 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -304,7 +304,7 @@ __tx_irq_processing_return 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.s: @@ -315,12 +315,12 @@ __tx_example_vectored_irq_handler ; /* Jump to context save to save system context. */ STMDB sp!, {r0-r3} ; Save some scratch registers MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers BL _tx_thread_vectored_context_save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -337,24 +337,24 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.s. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables -nesting by disabling IRQ interrupts and switching back to IRQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: RSEG .text:CODE:NOROOT(2) PUBLIC __tx_irq_handler RSEG .text:CODE:NOROOT(2) - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -362,15 +362,15 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ; BL _tx_thread_irq_nesting_start @@ -378,7 +378,7 @@ __tx_irq_processing_return ; /* Application ISR dispatch call goes here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ; BL _tx_thread_irq_nesting_end @@ -389,12 +389,12 @@ __tx_irq_processing_return 7.3 FIQ Interrupts -By default, Cortex-A7 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, Cortex-A7 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.s. @@ -403,7 +403,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.s. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.s: @@ -434,18 +434,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.s. When nested FIQ interrupts are no -longer required, calling the _tx_thread_fiq_nesting_end service disables -nesting by disabling FIQ interrupts and switching back to FIQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested FIQ interrupts are no +longer required, calling the _tx_thread_fiq_nesting_end service disables +nesting by disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -463,7 +463,7 @@ __tx_fiq_processing_return: ; interrupt, and all C scratch registers are available for use. */ ; ; /* Enable nested FIQ interrupts. NOTE: Since this service returns -; with FIQ interrupts enabled, all FIQ interrupt sources must be +; with FIQ interrupts enabled, all FIQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start ; @@ -479,22 +479,22 @@ __tx_fiq_processing_return: 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to _tx_timer_interrupt +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. 9. Thumb/Cortex-A7 Mixed Mode -By default, ThreadX is setup for running in Cortex-A7 32-bit mode. This is -also true for the demonstration system. It is possible to build any +By default, ThreadX is setup for running in Cortex-A7 32-bit mode. This is +also true for the demonstration system. It is possible to build any ThreadX file and/or the application in Thumb mode. The only exception -to this is the file tx_thread_shell_entry.c. This file must always be -built in 32-bit mode. In addition, if any Thumb code is used the entire +to this is the file tx_thread_shell_entry.c. This file must always be +built in 32-bit mode. In addition, if any Thumb code is used the entire ThreadX assembly source should be built with TX_THUMB defined. @@ -506,14 +506,14 @@ should have the following line added (if not already in place): initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application -The project options "General Options -> Library Configuration" should also have the +The project options "General Options -> Library Configuration" should also have the "Enable thread support in library" box selected. 11. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); diff --git a/ports/cortex_a7/iar/src/tx_iar.c b/ports/cortex_a7/iar/src/tx_iar.c index 158738ea..238b485e 100644 --- a/ports/cortex_a7/iar/src/tx_iar.c +++ b/ports/cortex_a7/iar/src/tx_iar.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** IAR Multithreaded Library Support */ /** */ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports/cortex_a7/iar/src/tx_thread_context_restore.s b/ports/cortex_a7/iar/src/tx_thread_context_restore.s index 0b3814a8..bf2238db 100644 --- a/ports/cortex_a7/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_a7/iar/src/tx_thread_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,7 +36,7 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask THUMB_MASK DEFINE 0x20 ; Thumb bit mask SVC_MODE_BITS DEFINE 0x13 ; SVC mode value @@ -51,47 +51,38 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-A7/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -121,13 +112,13 @@ _tx_thread_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3, #0] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3, #0] ; Store the counter + STR r2, [r3, #0] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -193,7 +184,7 @@ __tx_thread_preempt_restore LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer - + #ifdef __ARMVFP__ LDR r2, [r0, #144] ; Pickup the VFP enabled flag CMP r2, #0 ; Is the VFP enabled? @@ -204,7 +195,7 @@ __tx_thread_preempt_restore VSTMDB sp!, {D0-D15} ; Save D0-D15 _tx_skip_fiq_vfp_save: #endif - + MOV r3, #1 ; Build interrupt stack type STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR STR sp, [r0, #8] ; Save stack pointer in thread control diff --git a/ports/cortex_a7/iar/src/tx_thread_context_save.s b/ports/cortex_a7/iar/src/tx_thread_context_save.s index dfbe7b7b..845284d2 100644 --- a/ports/cortex_a7/iar/src/tx_thread_context_save.s +++ b/ports/cortex_a7/iar/src/tx_thread_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -43,46 +43,37 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled EXTERN _tx_execution_isr_enter ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-A7/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -99,7 +90,7 @@ _tx_thread_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt CPSR @@ -119,7 +110,7 @@ _tx_thread_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -135,7 +126,7 @@ _tx_thread_context_save POP {lr} ; Recover ISR lr #endif - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; __tx_thread_not_nested_save ; } @@ -149,13 +140,13 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} ; Store other registers ; ; /* Save the current stack pointer in the thread's control block. */ @@ -175,7 +166,7 @@ __tx_thread_not_nested_save POP {lr} ; Recover ISR lr #endif - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ; else @@ -185,7 +176,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit @@ -200,7 +191,7 @@ __tx_thread_idle_system_save #endif ADD sp, sp, #16 ; Recover saved registers - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ;} diff --git a/ports/cortex_a7/iar/src/tx_thread_fiq_context_restore.s b/ports/cortex_a7/iar/src/tx_thread_fiq_context_restore.s index af8f462b..3e62e30a 100644 --- a/ports/cortex_a7/iar/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_a7/iar/src/tx_thread_fiq_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -37,7 +37,7 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask THUMB_MASK DEFINE 0x20 ; Thumb bit mask IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits SVC_MODE_BITS DEFINE 0x13 ; SVC mode value @@ -52,47 +52,38 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value EXTERN _tx_execution_isr_exit ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_restore Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore Cortex-A7/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the fiq interrupt context when processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* FIQ ISR Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) @@ -122,13 +113,13 @@ _tx_thread_fiq_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3] ; Store the counter + STR r2, [r3] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -172,7 +163,7 @@ __tx_thread_fiq_no_preempt_restore ; /* Restore interrupted thread or ISR. */ ; ; /* Pickup the saved stack pointer. */ -; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; ; ; /* Recover the saved context and return to the point of interrupt. */ ; @@ -232,7 +223,7 @@ _tx_skip_irq_vfp_save: BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it ; ; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; -; _tx_timer_time_slice = 0; +; _tx_timer_time_slice = 0; ; STR r2, [r0, #24] ; Save thread's time-slice MOV r2, #0 ; Clear value diff --git a/ports/cortex_a7/iar/src/tx_thread_fiq_context_save.s b/ports/cortex_a7/iar/src/tx_thread_fiq_context_save.s index e43fdf76..e34824b1 100644 --- a/ports/cortex_a7/iar/src/tx_thread_fiq_context_save.s +++ b/ports/cortex_a7/iar/src/tx_thread_fiq_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,46 +36,37 @@ EXTERN _tx_execution_isr_enter ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_save Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save Cortex-A7/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) @@ -92,7 +83,7 @@ _tx_thread_fiq_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state CMP r2, #0 ; Is this the first interrupt? @@ -107,7 +98,7 @@ _tx_thread_fiq_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -123,38 +114,38 @@ _tx_thread_fiq_context_save POP {lr} ; Recover ISR lr #endif - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; __tx_thread_fiq_not_nested_save -; } +; } ; ; /* Otherwise, not nested, check to see if a thread was running. */ ; else if (_tx_thread_current_ptr) -; { +; { ; ADD r2, r2, #1 ; Increment the interrupt counter STR r2, [r3] ; Store it back in the variable LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in -; ; scheduling loop - nothing needs saving! + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, lr} ; Store other registers, Note that we don't -; ; need to save sl and ip since FIQ has -; ; copies of these registers. Nested +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested ; ; interrupt processing does need to save ; ; these registers. ; ; /* Save the current stack pointer in the thread's control block. */ -; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; ; ; /* Switch to the system stack. */ -; sp = _tx_thread_system_stack_ptr; +; sp = _tx_thread_system_stack_ptr; ; MOV r10, #0 ; Clear stack limit @@ -167,7 +158,7 @@ __tx_thread_fiq_not_nested_save POP {lr} ; Recover ISR lr #endif - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } ; else @@ -187,18 +178,18 @@ __tx_thread_fiq_idle_system_save #endif ; ; /* Not much to do here, save the current SPSR and LR for possible -; use in IRQ interrupted in idle system conditions, and return to +; use in IRQ interrupted in idle system conditions, and return to ; FIQ interrupt processing. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, lr} ; Store other registers that will get used -; ; or stripped off the stack in context -; ; restore - B __tx_fiq_processing_return ; Continue FIQ processing +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } -;} +;} ; ; END diff --git a/ports/cortex_a7/iar/src/tx_thread_fiq_nesting_end.s b/ports/cortex_a7/iar/src/tx_thread_fiq_nesting_end.s index 155a79b6..69d252bd 100644 --- a/ports/cortex_a7/iar/src/tx_thread_fiq_nesting_end.s +++ b/ports/cortex_a7/iar/src/tx_thread_fiq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,55 +34,49 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_end Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end Cortex-A7/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ -;/* processing from system mode back to FIQ mode prior to the ISR */ -;/* calling _tx_thread_fiq_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s79). */ -;/* */ -;/* This function returns with FIQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/cortex_a7/iar/src/tx_thread_fiq_nesting_start.s b/ports/cortex_a7/iar/src/tx_thread_fiq_nesting_start.s index 8b82e8eb..3a6ebbc7 100644 --- a/ports/cortex_a7/iar/src/tx_thread_fiq_nesting_start.s +++ b/ports/cortex_a7/iar/src/tx_thread_fiq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ MODE_MASK DEFINE 0x1F ; Mode mask SYS_MODE_BITS DEFINE 0x1F ; System mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_start Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start Cortex-A7/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ -;/* processing to the system mode so nested FIQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s79). */ -;/* */ -;/* This function returns with FIQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_a7/iar/src/tx_thread_interrupt_control.s b/ports/cortex_a7/iar/src/tx_thread_interrupt_control.s index e4618a59..37aabfe1 100644 --- a/ports/cortex_a7/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_a7/iar/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,42 +35,36 @@ INT_MASK DEFINE 0x80 ; Interrupt bit mask #endif ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-A7/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a7/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_a7/iar/src/tx_thread_interrupt_disable.s index 43c7952d..d35bdb1b 100644 --- a/ports/cortex_a7/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_a7/iar/src/tx_thread_interrupt_disable.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,41 +36,35 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-A7/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_a7/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_a7/iar/src/tx_thread_interrupt_restore.s index 1893ce17..e3f63d52 100644 --- a/ports/cortex_a7/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_a7/iar/src/tx_thread_interrupt_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -28,42 +28,36 @@ ;#include "tx_thread.h" ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-A7/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function is responsible for restoring interrupts to the state */ ;/* returned by a previous _tx_thread_interrupt_disable call. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;void _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a7/iar/src/tx_thread_irq_nesting_end.s b/ports/cortex_a7/iar/src/tx_thread_irq_nesting_end.s index 5de63f0d..525c310d 100644 --- a/ports/cortex_a7/iar/src/tx_thread_irq_nesting_end.s +++ b/ports/cortex_a7/iar/src/tx_thread_irq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,55 +35,49 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_end Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-A7/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -;/* processing from system mode back to IRQ mode prior to the ISR */ -;/* calling _tx_thread_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s79). */ -;/* */ -;/* This function returns with IRQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_a7/iar/src/tx_thread_irq_nesting_start.s b/ports/cortex_a7/iar/src/tx_thread_irq_nesting_start.s index bf465f81..0e27b060 100644 --- a/ports/cortex_a7/iar/src/tx_thread_irq_nesting_start.s +++ b/ports/cortex_a7/iar/src/tx_thread_irq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ MODE_MASK DEFINE 0x1F ; Mode mask SYS_MODE_BITS DEFINE 0x1F ; System mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_start Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-A7/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_context_save has been called and switches the IRQ */ -;/* processing to the system mode so nested IRQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s79). */ -;/* */ -;/* This function returns with IRQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_a7/iar/src/tx_thread_schedule.s b/ports/cortex_a7/iar/src/tx_thread_schedule.s index 0486e767..f0f0bf5b 100644 --- a/ports/cortex_a7/iar/src/tx_thread_schedule.s +++ b/ports/cortex_a7/iar/src/tx_thread_schedule.s @@ -1,19 +1,19 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors -; * +; * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -44,48 +44,39 @@ ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-A7/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -115,7 +106,7 @@ __tx_thread_schedule_loop ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Lockout interrupts and ; transfer control to it. */ ; @@ -124,7 +115,7 @@ __tx_thread_schedule_loop ; /* Setup the current thread pointer. */ ; _tx_thread_current_ptr = _tx_thread_execute_ptr; ; - LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread STR r0, [r1, #0] ; Setup current thread pointer ; ; /* Increment the run count for this thread. */ @@ -138,7 +129,7 @@ __tx_thread_schedule_loop ; /* Setup time-slice, if present. */ ; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; ; - LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice ; variable LDR sp, [r0, #8] ; Switch stack pointers STR r3, [r2, #0] ; Setup time-slice @@ -199,7 +190,7 @@ _tx_skip_solicited_vfp_restore: #ifdef __ARMVFP__ PUBLIC tx_thread_vfp_enable CODE32 -tx_thread_vfp_enable??rA +tx_thread_vfp_enable??rA tx_thread_vfp_enable MRS r2, CPSR ; Pickup the CPSR #ifdef TX_ENABLE_FIQ_SUPPORT @@ -219,7 +210,7 @@ __tx_no_thread_to_enable: PUBLIC tx_thread_vfp_disable CODE32 -tx_thread_vfp_disable??rA +tx_thread_vfp_disable??rA tx_thread_vfp_disable MRS r2, CPSR ; Pickup the CPSR #ifdef TX_ENABLE_FIQ_SUPPORT diff --git a/ports/cortex_a7/iar/src/tx_thread_stack_build.s b/ports/cortex_a7/iar/src/tx_thread_stack_build.s index fc4e5870..306dc03f 100644 --- a/ports/cortex_a7/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_a7/iar/src/tx_thread_stack_build.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -37,58 +37,52 @@ CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints en #endif ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-A7/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function builds a stack frame on the supplied thread's stack. */ ;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ ;/* thread_ptr Pointer to thread control blk */ ;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) ;{ RSEG .text:CODE:NOROOT(2) PUBLIC _tx_thread_stack_build - + CODE32 _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-A7 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; a1 (r0) Initial value for a1 diff --git a/ports/cortex_a7/iar/src/tx_thread_system_return.s b/ports/cortex_a7/iar/src/tx_thread_system_return.s index c35bc5f6..3bc43a36 100644 --- a/ports/cortex_a7/iar/src/tx_thread_system_return.s +++ b/ports/cortex_a7/iar/src/tx_thread_system_return.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -42,47 +42,38 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-A7/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -113,7 +104,7 @@ _tx_skip_solicited_vfp_save: MOV r0, #0 ; Build a solicited stack type MRS r1, CPSR ; Pickup the CPSR STMDB sp!, {r0-r1} ; Save type and CPSR -; +; ; /* Lockout interrupts. */ ; ORR r2, r1, #DISABLE_INTS ; Build disable interrupt CPSR diff --git a/ports/cortex_a7/iar/src/tx_thread_vectored_context_save.s b/ports/cortex_a7/iar/src/tx_thread_vectored_context_save.s index da8794f7..9427f0a2 100644 --- a/ports/cortex_a7/iar/src/tx_thread_vectored_context_save.s +++ b/ports/cortex_a7/iar/src/tx_thread_vectored_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -41,46 +41,37 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled EXTERN _tx_execution_isr_enter ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_vectored_context_save Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-A7/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) @@ -142,7 +133,7 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in ; scheduling loop - nothing needs saving! ; ; /* Note: Minimal context of interrupted thread is already saved. */ @@ -174,7 +165,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports/cortex_a7/iar/src/tx_timer_interrupt.s b/ports/cortex_a7/iar/src/tx_timer_interrupt.s index da4b2f3f..00ecfc46 100644 --- a/ports/cortex_a7/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_a7/iar/src/tx_timer_interrupt.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -43,46 +43,40 @@ ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-A7/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time-slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time-slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -108,7 +102,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CMP r2, #0 ; Is it non-active? BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing @@ -226,13 +220,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CMP r2, #0 ; See if the flag is set BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing ; diff --git a/ports/cortex_a72/ac6/example_build/sample_threadx/.cproject b/ports/cortex_a72/ac6/example_build/sample_threadx/.cproject index 1f6965bf..d67ddd58 100644 --- a/ports/cortex_a72/ac6/example_build/sample_threadx/.cproject +++ b/ports/cortex_a72/ac6/example_build/sample_threadx/.cproject @@ -1,158 +1,158 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a72/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports/cortex_a72/ac6/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports/cortex_a72/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports/cortex_a72/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports/cortex_a72/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports/cortex_a72/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports/cortex_a72/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports/cortex_a72/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports/cortex_a72/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_a72/ac6/example_build/sample_threadx/sample_threadx.scat index e5783c7c..d8dfde69 100644 --- a/ports/cortex_a72/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports/cortex_a72/ac6/example_build/sample_threadx/sample_threadx.scat @@ -2,7 +2,7 @@ ; Scatter file for Armv8-A Startup code on FVP Base model ; Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************** @@ -25,7 +25,7 @@ LOAD 0x80000000 ; in source code for this to work correctly ; ARM_LIB_HEAP +0 ALIGN 64 EMPTY 0xA0000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary diff --git a/ports/cortex_a72/ac6/example_build/sample_threadx/v8_aarch64.h b/ports/cortex_a72/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports/cortex_a72/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports/cortex_a72/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_a72/ac6/example_build/sample_threadx/v8_mmu.h b/ports/cortex_a72/ac6/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports/cortex_a72/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports/cortex_a72/ac6/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports/cortex_a72/ac6/example_build/tx/.cproject b/ports/cortex_a72/ac6/example_build/tx/.cproject index 10cb82e1..e0dba893 100644 --- a/ports/cortex_a72/ac6/example_build/tx/.cproject +++ b/ports/cortex_a72/ac6/example_build/tx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a72/ac6/inc/tx_port.h b/ports/cortex_a72/ac6/inc/tx_port.h index a8d3fd48..e5352338 100644 --- a/ports/cortex_a72/ac6/inc/tx_port.h +++ b/ports/cortex_a72/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -369,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a72/ac6/src/tx_initialize_low_level.S b/ports/cortex_a72/ac6/src/tx_initialize_low_level.S index f456574e..7d2a4be3 100644 --- a/ports/cortex_a72/ac6/src/tx_initialize_low_level.S +++ b/ports/cortex_a72/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports/cortex_a72/ac6/src/tx_thread_context_restore.S b/ports/cortex_a72/ac6/src/tx_thread_context_restore.S index 8e0d5515..9ba82827 100644 --- a/ports/cortex_a72/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a72/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_a72/ac6/src/tx_thread_context_save.S b/ports/cortex_a72/ac6/src/tx_thread_context_save.S index 7768efc2..c2395155 100644 --- a/ports/cortex_a72/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a72/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_a72/ac6/src/tx_thread_fp_disable.c b/ports/cortex_a72/ac6/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports/cortex_a72/ac6/src/tx_thread_fp_disable.c +++ b/ports/cortex_a72/ac6/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports/cortex_a72/ac6/src/tx_thread_fp_enable.c b/ports/cortex_a72/ac6/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports/cortex_a72/ac6/src/tx_thread_fp_enable.c +++ b/ports/cortex_a72/ac6/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports/cortex_a72/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a72/ac6/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports/cortex_a72/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a72/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_a72/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a72/ac6/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports/cortex_a72/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a72/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports/cortex_a72/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a72/ac6/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports/cortex_a72/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a72/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports/cortex_a72/ac6/src/tx_thread_schedule.S b/ports/cortex_a72/ac6/src/tx_thread_schedule.S index 4cce4a62..057aa538 100644 --- a/ports/cortex_a72/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a72/ac6/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,18 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_a72/ac6/src/tx_thread_stack_build.S b/ports/cortex_a72/ac6/src/tx_thread_stack_build.S index 6c675d9b..01084da7 100644 --- a/ports/cortex_a72/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a72/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_a72/ac6/src/tx_thread_system_return.S b/ports/cortex_a72/ac6/src/tx_thread_system_return.S index 780bb128..b7593d79 100644 --- a/ports/cortex_a72/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a72/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_a72/ac6/src/tx_timer_interrupt.S b/ports/cortex_a72/ac6/src/tx_timer_interrupt.S index d84245c6..1b80a7f2 100644 --- a/ports/cortex_a72/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a72/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_a72/gnu/example_build/sample_threadx/.cproject b/ports/cortex_a72/gnu/example_build/sample_threadx/.cproject index 1c32cb32..40d4912d 100644 --- a/ports/cortex_a72/gnu/example_build/sample_threadx/.cproject +++ b/ports/cortex_a72/gnu/example_build/sample_threadx/.cproject @@ -1,170 +1,170 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a72/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports/cortex_a72/gnu/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports/cortex_a72/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports/cortex_a72/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports/cortex_a72/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports/cortex_a72/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports/cortex_a72/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports/cortex_a72/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports/cortex_a72/gnu/example_build/sample_threadx/sample_threadx.ld b/ports/cortex_a72/gnu/example_build/sample_threadx/sample_threadx.ld index eec8f12b..3bf47736 100644 --- a/ports/cortex_a72/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports/cortex_a72/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start diff --git a/ports/cortex_a72/gnu/example_build/sample_threadx/startup.S b/ports/cortex_a72/gnu/example_build/sample_threadx/startup.S index b71b45f8..b44806fe 100644 --- a/ports/cortex_a72/gnu/example_build/sample_threadx/startup.S +++ b/ports/cortex_a72/gnu/example_build/sample_threadx/startup.S @@ -328,7 +328,7 @@ el1_entry_aarch64: // // Cortex-A processors automatically invalidate their caches on reset // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). - // It is therefore not necessary for software to invalidate the caches + // It is therefore not necessary for software to invalidate the caches // on startup, however, this is done here in case of a warm reset. bl InvalidateUDCaches tlbi VMALLE1 diff --git a/ports/cortex_a72/gnu/example_build/sample_threadx/v8_aarch64.h b/ports/cortex_a72/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports/cortex_a72/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports/cortex_a72/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_a72/gnu/example_build/sample_threadx/v8_mmu.h b/ports/cortex_a72/gnu/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports/cortex_a72/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports/cortex_a72/gnu/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports/cortex_a72/gnu/example_build/tx/.cproject b/ports/cortex_a72/gnu/example_build/tx/.cproject index f1b8ed5b..9e5a975e 100644 --- a/ports/cortex_a72/gnu/example_build/tx/.cproject +++ b/ports/cortex_a72/gnu/example_build/tx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a72/gnu/inc/tx_port.h b/ports/cortex_a72/gnu/inc/tx_port.h index a8d3fd48..e5352338 100644 --- a/ports/cortex_a72/gnu/inc/tx_port.h +++ b/ports/cortex_a72/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -369,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a72/gnu/src/tx_initialize_low_level.S b/ports/cortex_a72/gnu/src/tx_initialize_low_level.S index 3dce3cea..3025f12b 100644 --- a/ports/cortex_a72/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_a72/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -99,4 +89,4 @@ _tx_initialize_low_level: /* Done, return to caller. */ RET // Return to caller -// } +// } diff --git a/ports/cortex_a72/gnu/src/tx_thread_context_restore.S b/ports/cortex_a72/gnu/src/tx_thread_context_restore.S index 8e0d5515..9ba82827 100644 --- a/ports/cortex_a72/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a72/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_a72/gnu/src/tx_thread_context_save.S b/ports/cortex_a72/gnu/src/tx_thread_context_save.S index 7768efc2..c2395155 100644 --- a/ports/cortex_a72/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a72/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_a72/gnu/src/tx_thread_fp_disable.c b/ports/cortex_a72/gnu/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports/cortex_a72/gnu/src/tx_thread_fp_disable.c +++ b/ports/cortex_a72/gnu/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports/cortex_a72/gnu/src/tx_thread_fp_enable.c b/ports/cortex_a72/gnu/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports/cortex_a72/gnu/src/tx_thread_fp_enable.c +++ b/ports/cortex_a72/gnu/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports/cortex_a72/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a72/gnu/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports/cortex_a72/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a72/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_a72/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a72/gnu/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports/cortex_a72/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a72/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports/cortex_a72/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a72/gnu/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports/cortex_a72/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a72/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports/cortex_a72/gnu/src/tx_thread_schedule.S b/ports/cortex_a72/gnu/src/tx_thread_schedule.S index 4cce4a62..057aa538 100644 --- a/ports/cortex_a72/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a72/gnu/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,18 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_a72/gnu/src/tx_thread_stack_build.S b/ports/cortex_a72/gnu/src/tx_thread_stack_build.S index 6c675d9b..01084da7 100644 --- a/ports/cortex_a72/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a72/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_a72/gnu/src/tx_thread_system_return.S b/ports/cortex_a72/gnu/src/tx_thread_system_return.S index 780bb128..b7593d79 100644 --- a/ports/cortex_a72/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a72/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_a72/gnu/src/tx_timer_interrupt.S b/ports/cortex_a72/gnu/src/tx_timer_interrupt.S index d84245c6..1b80a7f2 100644 --- a/ports/cortex_a72/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a72/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_a73/ac6/example_build/sample_threadx/.cproject b/ports/cortex_a73/ac6/example_build/sample_threadx/.cproject index 2d2e59d7..2280a7dd 100644 --- a/ports/cortex_a73/ac6/example_build/sample_threadx/.cproject +++ b/ports/cortex_a73/ac6/example_build/sample_threadx/.cproject @@ -1,158 +1,158 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a73/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports/cortex_a73/ac6/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports/cortex_a73/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports/cortex_a73/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports/cortex_a73/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports/cortex_a73/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports/cortex_a73/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports/cortex_a73/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports/cortex_a73/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_a73/ac6/example_build/sample_threadx/sample_threadx.scat index e5783c7c..d8dfde69 100644 --- a/ports/cortex_a73/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports/cortex_a73/ac6/example_build/sample_threadx/sample_threadx.scat @@ -2,7 +2,7 @@ ; Scatter file for Armv8-A Startup code on FVP Base model ; Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************** @@ -25,7 +25,7 @@ LOAD 0x80000000 ; in source code for this to work correctly ; ARM_LIB_HEAP +0 ALIGN 64 EMPTY 0xA0000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary diff --git a/ports/cortex_a73/ac6/example_build/sample_threadx/v8_aarch64.h b/ports/cortex_a73/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports/cortex_a73/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports/cortex_a73/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_a73/ac6/example_build/sample_threadx/v8_mmu.h b/ports/cortex_a73/ac6/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports/cortex_a73/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports/cortex_a73/ac6/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports/cortex_a73/ac6/example_build/tx/.cproject b/ports/cortex_a73/ac6/example_build/tx/.cproject index 1b43e008..2409ff43 100644 --- a/ports/cortex_a73/ac6/example_build/tx/.cproject +++ b/ports/cortex_a73/ac6/example_build/tx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a73/ac6/inc/tx_port.h b/ports/cortex_a73/ac6/inc/tx_port.h index a8d3fd48..e5352338 100644 --- a/ports/cortex_a73/ac6/inc/tx_port.h +++ b/ports/cortex_a73/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -369,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a73/ac6/src/tx_initialize_low_level.S b/ports/cortex_a73/ac6/src/tx_initialize_low_level.S index f456574e..7d2a4be3 100644 --- a/ports/cortex_a73/ac6/src/tx_initialize_low_level.S +++ b/ports/cortex_a73/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports/cortex_a73/ac6/src/tx_thread_context_restore.S b/ports/cortex_a73/ac6/src/tx_thread_context_restore.S index 8e0d5515..9ba82827 100644 --- a/ports/cortex_a73/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a73/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_a73/ac6/src/tx_thread_context_save.S b/ports/cortex_a73/ac6/src/tx_thread_context_save.S index 7768efc2..c2395155 100644 --- a/ports/cortex_a73/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a73/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_a73/ac6/src/tx_thread_fp_disable.c b/ports/cortex_a73/ac6/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports/cortex_a73/ac6/src/tx_thread_fp_disable.c +++ b/ports/cortex_a73/ac6/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports/cortex_a73/ac6/src/tx_thread_fp_enable.c b/ports/cortex_a73/ac6/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports/cortex_a73/ac6/src/tx_thread_fp_enable.c +++ b/ports/cortex_a73/ac6/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports/cortex_a73/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a73/ac6/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports/cortex_a73/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a73/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_a73/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a73/ac6/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports/cortex_a73/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a73/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports/cortex_a73/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a73/ac6/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports/cortex_a73/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a73/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports/cortex_a73/ac6/src/tx_thread_schedule.S b/ports/cortex_a73/ac6/src/tx_thread_schedule.S index 4cce4a62..057aa538 100644 --- a/ports/cortex_a73/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a73/ac6/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,18 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_a73/ac6/src/tx_thread_stack_build.S b/ports/cortex_a73/ac6/src/tx_thread_stack_build.S index 6c675d9b..01084da7 100644 --- a/ports/cortex_a73/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a73/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_a73/ac6/src/tx_thread_system_return.S b/ports/cortex_a73/ac6/src/tx_thread_system_return.S index 780bb128..b7593d79 100644 --- a/ports/cortex_a73/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a73/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_a73/ac6/src/tx_timer_interrupt.S b/ports/cortex_a73/ac6/src/tx_timer_interrupt.S index d84245c6..1b80a7f2 100644 --- a/ports/cortex_a73/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a73/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_a73/gnu/example_build/sample_threadx/.cproject b/ports/cortex_a73/gnu/example_build/sample_threadx/.cproject index 1c32cb32..40d4912d 100644 --- a/ports/cortex_a73/gnu/example_build/sample_threadx/.cproject +++ b/ports/cortex_a73/gnu/example_build/sample_threadx/.cproject @@ -1,170 +1,170 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a73/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports/cortex_a73/gnu/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports/cortex_a73/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports/cortex_a73/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports/cortex_a73/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports/cortex_a73/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports/cortex_a73/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports/cortex_a73/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports/cortex_a73/gnu/example_build/sample_threadx/sample_threadx.ld b/ports/cortex_a73/gnu/example_build/sample_threadx/sample_threadx.ld index eec8f12b..3bf47736 100644 --- a/ports/cortex_a73/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports/cortex_a73/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start diff --git a/ports/cortex_a73/gnu/example_build/sample_threadx/startup.S b/ports/cortex_a73/gnu/example_build/sample_threadx/startup.S index b71b45f8..b44806fe 100644 --- a/ports/cortex_a73/gnu/example_build/sample_threadx/startup.S +++ b/ports/cortex_a73/gnu/example_build/sample_threadx/startup.S @@ -328,7 +328,7 @@ el1_entry_aarch64: // // Cortex-A processors automatically invalidate their caches on reset // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). - // It is therefore not necessary for software to invalidate the caches + // It is therefore not necessary for software to invalidate the caches // on startup, however, this is done here in case of a warm reset. bl InvalidateUDCaches tlbi VMALLE1 diff --git a/ports/cortex_a73/gnu/example_build/sample_threadx/v8_aarch64.h b/ports/cortex_a73/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports/cortex_a73/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports/cortex_a73/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_a73/gnu/example_build/sample_threadx/v8_mmu.h b/ports/cortex_a73/gnu/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports/cortex_a73/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports/cortex_a73/gnu/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports/cortex_a73/gnu/example_build/tx/.cproject b/ports/cortex_a73/gnu/example_build/tx/.cproject index f1b8ed5b..9e5a975e 100644 --- a/ports/cortex_a73/gnu/example_build/tx/.cproject +++ b/ports/cortex_a73/gnu/example_build/tx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a73/gnu/inc/tx_port.h b/ports/cortex_a73/gnu/inc/tx_port.h index a8d3fd48..e5352338 100644 --- a/ports/cortex_a73/gnu/inc/tx_port.h +++ b/ports/cortex_a73/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -369,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a73/gnu/src/tx_initialize_low_level.S b/ports/cortex_a73/gnu/src/tx_initialize_low_level.S index 3dce3cea..3025f12b 100644 --- a/ports/cortex_a73/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_a73/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -99,4 +89,4 @@ _tx_initialize_low_level: /* Done, return to caller. */ RET // Return to caller -// } +// } diff --git a/ports/cortex_a73/gnu/src/tx_thread_context_restore.S b/ports/cortex_a73/gnu/src/tx_thread_context_restore.S index 8e0d5515..9ba82827 100644 --- a/ports/cortex_a73/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a73/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_a73/gnu/src/tx_thread_context_save.S b/ports/cortex_a73/gnu/src/tx_thread_context_save.S index 7768efc2..c2395155 100644 --- a/ports/cortex_a73/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a73/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_a73/gnu/src/tx_thread_fp_disable.c b/ports/cortex_a73/gnu/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports/cortex_a73/gnu/src/tx_thread_fp_disable.c +++ b/ports/cortex_a73/gnu/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports/cortex_a73/gnu/src/tx_thread_fp_enable.c b/ports/cortex_a73/gnu/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports/cortex_a73/gnu/src/tx_thread_fp_enable.c +++ b/ports/cortex_a73/gnu/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports/cortex_a73/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a73/gnu/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports/cortex_a73/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a73/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_a73/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a73/gnu/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports/cortex_a73/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a73/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports/cortex_a73/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a73/gnu/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports/cortex_a73/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a73/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports/cortex_a73/gnu/src/tx_thread_schedule.S b/ports/cortex_a73/gnu/src/tx_thread_schedule.S index 4cce4a62..057aa538 100644 --- a/ports/cortex_a73/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a73/gnu/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,18 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_a73/gnu/src/tx_thread_stack_build.S b/ports/cortex_a73/gnu/src/tx_thread_stack_build.S index 6c675d9b..01084da7 100644 --- a/ports/cortex_a73/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a73/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_a73/gnu/src/tx_thread_system_return.S b/ports/cortex_a73/gnu/src/tx_thread_system_return.S index 780bb128..b7593d79 100644 --- a/ports/cortex_a73/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a73/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_a73/gnu/src/tx_timer_interrupt.S b/ports/cortex_a73/gnu/src/tx_timer_interrupt.S index d84245c6..1b80a7f2 100644 --- a/ports/cortex_a73/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a73/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_a75/ac6/example_build/sample_threadx/.cproject b/ports/cortex_a75/ac6/example_build/sample_threadx/.cproject index b8d51c26..fdf1a4fa 100644 --- a/ports/cortex_a75/ac6/example_build/sample_threadx/.cproject +++ b/ports/cortex_a75/ac6/example_build/sample_threadx/.cproject @@ -1,158 +1,158 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a75/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports/cortex_a75/ac6/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports/cortex_a75/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports/cortex_a75/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports/cortex_a75/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports/cortex_a75/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports/cortex_a75/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports/cortex_a75/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports/cortex_a75/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_a75/ac6/example_build/sample_threadx/sample_threadx.scat index e5783c7c..d8dfde69 100644 --- a/ports/cortex_a75/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports/cortex_a75/ac6/example_build/sample_threadx/sample_threadx.scat @@ -2,7 +2,7 @@ ; Scatter file for Armv8-A Startup code on FVP Base model ; Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************** @@ -25,7 +25,7 @@ LOAD 0x80000000 ; in source code for this to work correctly ; ARM_LIB_HEAP +0 ALIGN 64 EMPTY 0xA0000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary diff --git a/ports/cortex_a75/ac6/example_build/sample_threadx/v8_aarch64.h b/ports/cortex_a75/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports/cortex_a75/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports/cortex_a75/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_a75/ac6/example_build/sample_threadx/v8_mmu.h b/ports/cortex_a75/ac6/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports/cortex_a75/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports/cortex_a75/ac6/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports/cortex_a75/ac6/example_build/tx/.cproject b/ports/cortex_a75/ac6/example_build/tx/.cproject index e9bbc8ae..55b898b3 100644 --- a/ports/cortex_a75/ac6/example_build/tx/.cproject +++ b/ports/cortex_a75/ac6/example_build/tx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a75/ac6/inc/tx_port.h b/ports/cortex_a75/ac6/inc/tx_port.h index a8d3fd48..e5352338 100644 --- a/ports/cortex_a75/ac6/inc/tx_port.h +++ b/ports/cortex_a75/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -369,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a75/ac6/src/tx_initialize_low_level.S b/ports/cortex_a75/ac6/src/tx_initialize_low_level.S index f456574e..7d2a4be3 100644 --- a/ports/cortex_a75/ac6/src/tx_initialize_low_level.S +++ b/ports/cortex_a75/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports/cortex_a75/ac6/src/tx_thread_context_restore.S b/ports/cortex_a75/ac6/src/tx_thread_context_restore.S index 8e0d5515..9ba82827 100644 --- a/ports/cortex_a75/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a75/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_a75/ac6/src/tx_thread_context_save.S b/ports/cortex_a75/ac6/src/tx_thread_context_save.S index 7768efc2..c2395155 100644 --- a/ports/cortex_a75/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a75/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_a75/ac6/src/tx_thread_fp_disable.c b/ports/cortex_a75/ac6/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports/cortex_a75/ac6/src/tx_thread_fp_disable.c +++ b/ports/cortex_a75/ac6/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports/cortex_a75/ac6/src/tx_thread_fp_enable.c b/ports/cortex_a75/ac6/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports/cortex_a75/ac6/src/tx_thread_fp_enable.c +++ b/ports/cortex_a75/ac6/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports/cortex_a75/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a75/ac6/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports/cortex_a75/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a75/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_a75/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a75/ac6/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports/cortex_a75/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a75/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports/cortex_a75/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a75/ac6/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports/cortex_a75/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a75/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports/cortex_a75/ac6/src/tx_thread_schedule.S b/ports/cortex_a75/ac6/src/tx_thread_schedule.S index 4cce4a62..057aa538 100644 --- a/ports/cortex_a75/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a75/ac6/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,18 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_a75/ac6/src/tx_thread_stack_build.S b/ports/cortex_a75/ac6/src/tx_thread_stack_build.S index 6c675d9b..01084da7 100644 --- a/ports/cortex_a75/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a75/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_a75/ac6/src/tx_thread_system_return.S b/ports/cortex_a75/ac6/src/tx_thread_system_return.S index 780bb128..b7593d79 100644 --- a/ports/cortex_a75/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a75/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_a75/ac6/src/tx_timer_interrupt.S b/ports/cortex_a75/ac6/src/tx_timer_interrupt.S index d84245c6..1b80a7f2 100644 --- a/ports/cortex_a75/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a75/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_a75/gnu/example_build/sample_threadx/.cproject b/ports/cortex_a75/gnu/example_build/sample_threadx/.cproject index 1c32cb32..40d4912d 100644 --- a/ports/cortex_a75/gnu/example_build/sample_threadx/.cproject +++ b/ports/cortex_a75/gnu/example_build/sample_threadx/.cproject @@ -1,170 +1,170 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a75/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports/cortex_a75/gnu/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports/cortex_a75/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports/cortex_a75/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports/cortex_a75/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports/cortex_a75/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports/cortex_a75/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports/cortex_a75/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports/cortex_a75/gnu/example_build/sample_threadx/sample_threadx.ld b/ports/cortex_a75/gnu/example_build/sample_threadx/sample_threadx.ld index eec8f12b..3bf47736 100644 --- a/ports/cortex_a75/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports/cortex_a75/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start diff --git a/ports/cortex_a75/gnu/example_build/sample_threadx/startup.S b/ports/cortex_a75/gnu/example_build/sample_threadx/startup.S index b71b45f8..b44806fe 100644 --- a/ports/cortex_a75/gnu/example_build/sample_threadx/startup.S +++ b/ports/cortex_a75/gnu/example_build/sample_threadx/startup.S @@ -328,7 +328,7 @@ el1_entry_aarch64: // // Cortex-A processors automatically invalidate their caches on reset // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). - // It is therefore not necessary for software to invalidate the caches + // It is therefore not necessary for software to invalidate the caches // on startup, however, this is done here in case of a warm reset. bl InvalidateUDCaches tlbi VMALLE1 diff --git a/ports/cortex_a75/gnu/example_build/sample_threadx/v8_aarch64.h b/ports/cortex_a75/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports/cortex_a75/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports/cortex_a75/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_a75/gnu/example_build/sample_threadx/v8_mmu.h b/ports/cortex_a75/gnu/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports/cortex_a75/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports/cortex_a75/gnu/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports/cortex_a75/gnu/example_build/tx/.cproject b/ports/cortex_a75/gnu/example_build/tx/.cproject index f1b8ed5b..9e5a975e 100644 --- a/ports/cortex_a75/gnu/example_build/tx/.cproject +++ b/ports/cortex_a75/gnu/example_build/tx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a75/gnu/inc/tx_port.h b/ports/cortex_a75/gnu/inc/tx_port.h index a8d3fd48..e5352338 100644 --- a/ports/cortex_a75/gnu/inc/tx_port.h +++ b/ports/cortex_a75/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -369,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a75/gnu/src/tx_initialize_low_level.S b/ports/cortex_a75/gnu/src/tx_initialize_low_level.S index 3dce3cea..3025f12b 100644 --- a/ports/cortex_a75/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_a75/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -99,4 +89,4 @@ _tx_initialize_low_level: /* Done, return to caller. */ RET // Return to caller -// } +// } diff --git a/ports/cortex_a75/gnu/src/tx_thread_context_restore.S b/ports/cortex_a75/gnu/src/tx_thread_context_restore.S index 8e0d5515..9ba82827 100644 --- a/ports/cortex_a75/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a75/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_a75/gnu/src/tx_thread_context_save.S b/ports/cortex_a75/gnu/src/tx_thread_context_save.S index 7768efc2..c2395155 100644 --- a/ports/cortex_a75/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a75/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_a75/gnu/src/tx_thread_fp_disable.c b/ports/cortex_a75/gnu/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports/cortex_a75/gnu/src/tx_thread_fp_disable.c +++ b/ports/cortex_a75/gnu/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports/cortex_a75/gnu/src/tx_thread_fp_enable.c b/ports/cortex_a75/gnu/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports/cortex_a75/gnu/src/tx_thread_fp_enable.c +++ b/ports/cortex_a75/gnu/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports/cortex_a75/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a75/gnu/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports/cortex_a75/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a75/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_a75/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a75/gnu/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports/cortex_a75/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a75/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports/cortex_a75/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a75/gnu/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports/cortex_a75/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a75/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports/cortex_a75/gnu/src/tx_thread_schedule.S b/ports/cortex_a75/gnu/src/tx_thread_schedule.S index 4cce4a62..057aa538 100644 --- a/ports/cortex_a75/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a75/gnu/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,18 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_a75/gnu/src/tx_thread_stack_build.S b/ports/cortex_a75/gnu/src/tx_thread_stack_build.S index 6c675d9b..01084da7 100644 --- a/ports/cortex_a75/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a75/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_a75/gnu/src/tx_thread_system_return.S b/ports/cortex_a75/gnu/src/tx_thread_system_return.S index 780bb128..b7593d79 100644 --- a/ports/cortex_a75/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a75/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_a75/gnu/src/tx_timer_interrupt.S b/ports/cortex_a75/gnu/src/tx_timer_interrupt.S index d84245c6..1b80a7f2 100644 --- a/ports/cortex_a75/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a75/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_a76/ac6/example_build/sample_threadx/.cproject b/ports/cortex_a76/ac6/example_build/sample_threadx/.cproject index 710476e9..0de7cf84 100644 --- a/ports/cortex_a76/ac6/example_build/sample_threadx/.cproject +++ b/ports/cortex_a76/ac6/example_build/sample_threadx/.cproject @@ -1,158 +1,158 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a76/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports/cortex_a76/ac6/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports/cortex_a76/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports/cortex_a76/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports/cortex_a76/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports/cortex_a76/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports/cortex_a76/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports/cortex_a76/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports/cortex_a76/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_a76/ac6/example_build/sample_threadx/sample_threadx.scat index e5783c7c..d8dfde69 100644 --- a/ports/cortex_a76/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports/cortex_a76/ac6/example_build/sample_threadx/sample_threadx.scat @@ -2,7 +2,7 @@ ; Scatter file for Armv8-A Startup code on FVP Base model ; Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************** @@ -25,7 +25,7 @@ LOAD 0x80000000 ; in source code for this to work correctly ; ARM_LIB_HEAP +0 ALIGN 64 EMPTY 0xA0000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary diff --git a/ports/cortex_a76/ac6/example_build/sample_threadx/v8_aarch64.h b/ports/cortex_a76/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports/cortex_a76/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports/cortex_a76/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_a76/ac6/example_build/sample_threadx/v8_mmu.h b/ports/cortex_a76/ac6/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports/cortex_a76/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports/cortex_a76/ac6/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports/cortex_a76/ac6/example_build/tx/.cproject b/ports/cortex_a76/ac6/example_build/tx/.cproject index 8f5835ec..feedcae1 100644 --- a/ports/cortex_a76/ac6/example_build/tx/.cproject +++ b/ports/cortex_a76/ac6/example_build/tx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a76/ac6/inc/tx_port.h b/ports/cortex_a76/ac6/inc/tx_port.h index a8d3fd48..e5352338 100644 --- a/ports/cortex_a76/ac6/inc/tx_port.h +++ b/ports/cortex_a76/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -369,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a76/ac6/src/tx_initialize_low_level.S b/ports/cortex_a76/ac6/src/tx_initialize_low_level.S index f456574e..7d2a4be3 100644 --- a/ports/cortex_a76/ac6/src/tx_initialize_low_level.S +++ b/ports/cortex_a76/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports/cortex_a76/ac6/src/tx_thread_context_restore.S b/ports/cortex_a76/ac6/src/tx_thread_context_restore.S index 8e0d5515..9ba82827 100644 --- a/ports/cortex_a76/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a76/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_a76/ac6/src/tx_thread_context_save.S b/ports/cortex_a76/ac6/src/tx_thread_context_save.S index 7768efc2..c2395155 100644 --- a/ports/cortex_a76/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a76/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_a76/ac6/src/tx_thread_fp_disable.c b/ports/cortex_a76/ac6/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports/cortex_a76/ac6/src/tx_thread_fp_disable.c +++ b/ports/cortex_a76/ac6/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports/cortex_a76/ac6/src/tx_thread_fp_enable.c b/ports/cortex_a76/ac6/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports/cortex_a76/ac6/src/tx_thread_fp_enable.c +++ b/ports/cortex_a76/ac6/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports/cortex_a76/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a76/ac6/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports/cortex_a76/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a76/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_a76/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a76/ac6/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports/cortex_a76/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a76/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports/cortex_a76/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a76/ac6/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports/cortex_a76/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a76/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports/cortex_a76/ac6/src/tx_thread_schedule.S b/ports/cortex_a76/ac6/src/tx_thread_schedule.S index 4cce4a62..057aa538 100644 --- a/ports/cortex_a76/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a76/ac6/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,18 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_a76/ac6/src/tx_thread_stack_build.S b/ports/cortex_a76/ac6/src/tx_thread_stack_build.S index 6c675d9b..01084da7 100644 --- a/ports/cortex_a76/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a76/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_a76/ac6/src/tx_thread_system_return.S b/ports/cortex_a76/ac6/src/tx_thread_system_return.S index 780bb128..b7593d79 100644 --- a/ports/cortex_a76/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a76/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_a76/ac6/src/tx_timer_interrupt.S b/ports/cortex_a76/ac6/src/tx_timer_interrupt.S index d84245c6..1b80a7f2 100644 --- a/ports/cortex_a76/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a76/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_a76/gnu/example_build/sample_threadx/.cproject b/ports/cortex_a76/gnu/example_build/sample_threadx/.cproject index 1c32cb32..40d4912d 100644 --- a/ports/cortex_a76/gnu/example_build/sample_threadx/.cproject +++ b/ports/cortex_a76/gnu/example_build/sample_threadx/.cproject @@ -1,170 +1,170 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a76/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports/cortex_a76/gnu/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports/cortex_a76/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports/cortex_a76/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports/cortex_a76/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports/cortex_a76/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports/cortex_a76/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports/cortex_a76/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports/cortex_a76/gnu/example_build/sample_threadx/sample_threadx.ld b/ports/cortex_a76/gnu/example_build/sample_threadx/sample_threadx.ld index eec8f12b..3bf47736 100644 --- a/ports/cortex_a76/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports/cortex_a76/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start diff --git a/ports/cortex_a76/gnu/example_build/sample_threadx/startup.S b/ports/cortex_a76/gnu/example_build/sample_threadx/startup.S index b71b45f8..b44806fe 100644 --- a/ports/cortex_a76/gnu/example_build/sample_threadx/startup.S +++ b/ports/cortex_a76/gnu/example_build/sample_threadx/startup.S @@ -328,7 +328,7 @@ el1_entry_aarch64: // // Cortex-A processors automatically invalidate their caches on reset // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). - // It is therefore not necessary for software to invalidate the caches + // It is therefore not necessary for software to invalidate the caches // on startup, however, this is done here in case of a warm reset. bl InvalidateUDCaches tlbi VMALLE1 diff --git a/ports/cortex_a76/gnu/example_build/sample_threadx/v8_aarch64.h b/ports/cortex_a76/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports/cortex_a76/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports/cortex_a76/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_a76/gnu/example_build/sample_threadx/v8_mmu.h b/ports/cortex_a76/gnu/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports/cortex_a76/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports/cortex_a76/gnu/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports/cortex_a76/gnu/example_build/tx/.cproject b/ports/cortex_a76/gnu/example_build/tx/.cproject index f1b8ed5b..9e5a975e 100644 --- a/ports/cortex_a76/gnu/example_build/tx/.cproject +++ b/ports/cortex_a76/gnu/example_build/tx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a76/gnu/inc/tx_port.h b/ports/cortex_a76/gnu/inc/tx_port.h index a8d3fd48..e5352338 100644 --- a/ports/cortex_a76/gnu/inc/tx_port.h +++ b/ports/cortex_a76/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -369,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a76/gnu/src/tx_initialize_low_level.S b/ports/cortex_a76/gnu/src/tx_initialize_low_level.S index 3dce3cea..3025f12b 100644 --- a/ports/cortex_a76/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_a76/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -99,4 +89,4 @@ _tx_initialize_low_level: /* Done, return to caller. */ RET // Return to caller -// } +// } diff --git a/ports/cortex_a76/gnu/src/tx_thread_context_restore.S b/ports/cortex_a76/gnu/src/tx_thread_context_restore.S index 8e0d5515..9ba82827 100644 --- a/ports/cortex_a76/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a76/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_a76/gnu/src/tx_thread_context_save.S b/ports/cortex_a76/gnu/src/tx_thread_context_save.S index 7768efc2..c2395155 100644 --- a/ports/cortex_a76/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a76/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_a76/gnu/src/tx_thread_fp_disable.c b/ports/cortex_a76/gnu/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports/cortex_a76/gnu/src/tx_thread_fp_disable.c +++ b/ports/cortex_a76/gnu/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports/cortex_a76/gnu/src/tx_thread_fp_enable.c b/ports/cortex_a76/gnu/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports/cortex_a76/gnu/src/tx_thread_fp_enable.c +++ b/ports/cortex_a76/gnu/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports/cortex_a76/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a76/gnu/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports/cortex_a76/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a76/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_a76/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a76/gnu/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports/cortex_a76/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a76/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports/cortex_a76/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a76/gnu/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports/cortex_a76/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a76/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports/cortex_a76/gnu/src/tx_thread_schedule.S b/ports/cortex_a76/gnu/src/tx_thread_schedule.S index 4cce4a62..057aa538 100644 --- a/ports/cortex_a76/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a76/gnu/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,18 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_a76/gnu/src/tx_thread_stack_build.S b/ports/cortex_a76/gnu/src/tx_thread_stack_build.S index 6c675d9b..01084da7 100644 --- a/ports/cortex_a76/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a76/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_a76/gnu/src/tx_thread_system_return.S b/ports/cortex_a76/gnu/src/tx_thread_system_return.S index 780bb128..b7593d79 100644 --- a/ports/cortex_a76/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a76/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_a76/gnu/src/tx_timer_interrupt.S b/ports/cortex_a76/gnu/src/tx_timer_interrupt.S index d84245c6..1b80a7f2 100644 --- a/ports/cortex_a76/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a76/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_a76ae/ac6/example_build/sample_threadx/.cproject b/ports/cortex_a76ae/ac6/example_build/sample_threadx/.cproject index 7d177795..e4ad93db 100644 --- a/ports/cortex_a76ae/ac6/example_build/sample_threadx/.cproject +++ b/ports/cortex_a76ae/ac6/example_build/sample_threadx/.cproject @@ -1,158 +1,158 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a76ae/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports/cortex_a76ae/ac6/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports/cortex_a76ae/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports/cortex_a76ae/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports/cortex_a76ae/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports/cortex_a76ae/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports/cortex_a76ae/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports/cortex_a76ae/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports/cortex_a76ae/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_a76ae/ac6/example_build/sample_threadx/sample_threadx.scat index e5783c7c..d8dfde69 100644 --- a/ports/cortex_a76ae/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports/cortex_a76ae/ac6/example_build/sample_threadx/sample_threadx.scat @@ -2,7 +2,7 @@ ; Scatter file for Armv8-A Startup code on FVP Base model ; Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************** @@ -25,7 +25,7 @@ LOAD 0x80000000 ; in source code for this to work correctly ; ARM_LIB_HEAP +0 ALIGN 64 EMPTY 0xA0000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary diff --git a/ports/cortex_a76ae/ac6/example_build/sample_threadx/v8_aarch64.h b/ports/cortex_a76ae/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports/cortex_a76ae/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports/cortex_a76ae/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_a76ae/ac6/example_build/sample_threadx/v8_mmu.h b/ports/cortex_a76ae/ac6/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports/cortex_a76ae/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports/cortex_a76ae/ac6/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports/cortex_a76ae/ac6/example_build/tx/.cproject b/ports/cortex_a76ae/ac6/example_build/tx/.cproject index e51aafe2..9f404004 100644 --- a/ports/cortex_a76ae/ac6/example_build/tx/.cproject +++ b/ports/cortex_a76ae/ac6/example_build/tx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a76ae/ac6/inc/tx_port.h b/ports/cortex_a76ae/ac6/inc/tx_port.h index a8d3fd48..e5352338 100644 --- a/ports/cortex_a76ae/ac6/inc/tx_port.h +++ b/ports/cortex_a76ae/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -369,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a76ae/ac6/src/tx_initialize_low_level.S b/ports/cortex_a76ae/ac6/src/tx_initialize_low_level.S index f456574e..7d2a4be3 100644 --- a/ports/cortex_a76ae/ac6/src/tx_initialize_low_level.S +++ b/ports/cortex_a76ae/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports/cortex_a76ae/ac6/src/tx_thread_context_restore.S b/ports/cortex_a76ae/ac6/src/tx_thread_context_restore.S index 8e0d5515..9ba82827 100644 --- a/ports/cortex_a76ae/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a76ae/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_a76ae/ac6/src/tx_thread_context_save.S b/ports/cortex_a76ae/ac6/src/tx_thread_context_save.S index 7768efc2..c2395155 100644 --- a/ports/cortex_a76ae/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a76ae/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_a76ae/ac6/src/tx_thread_fp_disable.c b/ports/cortex_a76ae/ac6/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports/cortex_a76ae/ac6/src/tx_thread_fp_disable.c +++ b/ports/cortex_a76ae/ac6/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports/cortex_a76ae/ac6/src/tx_thread_fp_enable.c b/ports/cortex_a76ae/ac6/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports/cortex_a76ae/ac6/src/tx_thread_fp_enable.c +++ b/ports/cortex_a76ae/ac6/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports/cortex_a76ae/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a76ae/ac6/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports/cortex_a76ae/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a76ae/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_a76ae/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a76ae/ac6/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports/cortex_a76ae/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a76ae/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports/cortex_a76ae/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a76ae/ac6/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports/cortex_a76ae/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a76ae/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports/cortex_a76ae/ac6/src/tx_thread_schedule.S b/ports/cortex_a76ae/ac6/src/tx_thread_schedule.S index 4cce4a62..057aa538 100644 --- a/ports/cortex_a76ae/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a76ae/ac6/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,18 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_a76ae/ac6/src/tx_thread_stack_build.S b/ports/cortex_a76ae/ac6/src/tx_thread_stack_build.S index 6c675d9b..01084da7 100644 --- a/ports/cortex_a76ae/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a76ae/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_a76ae/ac6/src/tx_thread_system_return.S b/ports/cortex_a76ae/ac6/src/tx_thread_system_return.S index 780bb128..b7593d79 100644 --- a/ports/cortex_a76ae/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a76ae/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_a76ae/ac6/src/tx_timer_interrupt.S b/ports/cortex_a76ae/ac6/src/tx_timer_interrupt.S index d84245c6..1b80a7f2 100644 --- a/ports/cortex_a76ae/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a76ae/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_a76ae/gnu/example_build/sample_threadx/.cproject b/ports/cortex_a76ae/gnu/example_build/sample_threadx/.cproject index 1c32cb32..40d4912d 100644 --- a/ports/cortex_a76ae/gnu/example_build/sample_threadx/.cproject +++ b/ports/cortex_a76ae/gnu/example_build/sample_threadx/.cproject @@ -1,170 +1,170 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a76ae/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports/cortex_a76ae/gnu/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports/cortex_a76ae/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports/cortex_a76ae/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports/cortex_a76ae/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports/cortex_a76ae/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports/cortex_a76ae/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports/cortex_a76ae/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports/cortex_a76ae/gnu/example_build/sample_threadx/sample_threadx.ld b/ports/cortex_a76ae/gnu/example_build/sample_threadx/sample_threadx.ld index eec8f12b..3bf47736 100644 --- a/ports/cortex_a76ae/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports/cortex_a76ae/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start diff --git a/ports/cortex_a76ae/gnu/example_build/sample_threadx/startup.S b/ports/cortex_a76ae/gnu/example_build/sample_threadx/startup.S index b71b45f8..b44806fe 100644 --- a/ports/cortex_a76ae/gnu/example_build/sample_threadx/startup.S +++ b/ports/cortex_a76ae/gnu/example_build/sample_threadx/startup.S @@ -328,7 +328,7 @@ el1_entry_aarch64: // // Cortex-A processors automatically invalidate their caches on reset // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). - // It is therefore not necessary for software to invalidate the caches + // It is therefore not necessary for software to invalidate the caches // on startup, however, this is done here in case of a warm reset. bl InvalidateUDCaches tlbi VMALLE1 diff --git a/ports/cortex_a76ae/gnu/example_build/sample_threadx/v8_aarch64.h b/ports/cortex_a76ae/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports/cortex_a76ae/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports/cortex_a76ae/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_a76ae/gnu/example_build/sample_threadx/v8_mmu.h b/ports/cortex_a76ae/gnu/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports/cortex_a76ae/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports/cortex_a76ae/gnu/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports/cortex_a76ae/gnu/example_build/tx/.cproject b/ports/cortex_a76ae/gnu/example_build/tx/.cproject index f1b8ed5b..9e5a975e 100644 --- a/ports/cortex_a76ae/gnu/example_build/tx/.cproject +++ b/ports/cortex_a76ae/gnu/example_build/tx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a76ae/gnu/inc/tx_port.h b/ports/cortex_a76ae/gnu/inc/tx_port.h index a8d3fd48..e5352338 100644 --- a/ports/cortex_a76ae/gnu/inc/tx_port.h +++ b/ports/cortex_a76ae/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -369,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a76ae/gnu/src/tx_initialize_low_level.S b/ports/cortex_a76ae/gnu/src/tx_initialize_low_level.S index 3dce3cea..3025f12b 100644 --- a/ports/cortex_a76ae/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_a76ae/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -99,4 +89,4 @@ _tx_initialize_low_level: /* Done, return to caller. */ RET // Return to caller -// } +// } diff --git a/ports/cortex_a76ae/gnu/src/tx_thread_context_restore.S b/ports/cortex_a76ae/gnu/src/tx_thread_context_restore.S index 8e0d5515..9ba82827 100644 --- a/ports/cortex_a76ae/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a76ae/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_a76ae/gnu/src/tx_thread_context_save.S b/ports/cortex_a76ae/gnu/src/tx_thread_context_save.S index 7768efc2..c2395155 100644 --- a/ports/cortex_a76ae/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a76ae/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_a76ae/gnu/src/tx_thread_fp_disable.c b/ports/cortex_a76ae/gnu/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports/cortex_a76ae/gnu/src/tx_thread_fp_disable.c +++ b/ports/cortex_a76ae/gnu/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports/cortex_a76ae/gnu/src/tx_thread_fp_enable.c b/ports/cortex_a76ae/gnu/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports/cortex_a76ae/gnu/src/tx_thread_fp_enable.c +++ b/ports/cortex_a76ae/gnu/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports/cortex_a76ae/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a76ae/gnu/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports/cortex_a76ae/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a76ae/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_a76ae/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a76ae/gnu/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports/cortex_a76ae/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a76ae/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports/cortex_a76ae/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a76ae/gnu/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports/cortex_a76ae/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a76ae/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports/cortex_a76ae/gnu/src/tx_thread_schedule.S b/ports/cortex_a76ae/gnu/src/tx_thread_schedule.S index 4cce4a62..057aa538 100644 --- a/ports/cortex_a76ae/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a76ae/gnu/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,18 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_a76ae/gnu/src/tx_thread_stack_build.S b/ports/cortex_a76ae/gnu/src/tx_thread_stack_build.S index 6c675d9b..01084da7 100644 --- a/ports/cortex_a76ae/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a76ae/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_a76ae/gnu/src/tx_thread_system_return.S b/ports/cortex_a76ae/gnu/src/tx_thread_system_return.S index 780bb128..b7593d79 100644 --- a/ports/cortex_a76ae/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a76ae/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_a76ae/gnu/src/tx_timer_interrupt.S b/ports/cortex_a76ae/gnu/src/tx_timer_interrupt.S index d84245c6..1b80a7f2 100644 --- a/ports/cortex_a76ae/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a76ae/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_a77/ac6/example_build/sample_threadx/.cproject b/ports/cortex_a77/ac6/example_build/sample_threadx/.cproject index c6e9771f..f097ca78 100644 --- a/ports/cortex_a77/ac6/example_build/sample_threadx/.cproject +++ b/ports/cortex_a77/ac6/example_build/sample_threadx/.cproject @@ -1,158 +1,158 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a77/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports/cortex_a77/ac6/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports/cortex_a77/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports/cortex_a77/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports/cortex_a77/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports/cortex_a77/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports/cortex_a77/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports/cortex_a77/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports/cortex_a77/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_a77/ac6/example_build/sample_threadx/sample_threadx.scat index e5783c7c..d8dfde69 100644 --- a/ports/cortex_a77/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports/cortex_a77/ac6/example_build/sample_threadx/sample_threadx.scat @@ -2,7 +2,7 @@ ; Scatter file for Armv8-A Startup code on FVP Base model ; Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************** @@ -25,7 +25,7 @@ LOAD 0x80000000 ; in source code for this to work correctly ; ARM_LIB_HEAP +0 ALIGN 64 EMPTY 0xA0000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary diff --git a/ports/cortex_a77/ac6/example_build/sample_threadx/v8_aarch64.h b/ports/cortex_a77/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports/cortex_a77/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports/cortex_a77/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_a77/ac6/example_build/sample_threadx/v8_mmu.h b/ports/cortex_a77/ac6/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports/cortex_a77/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports/cortex_a77/ac6/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports/cortex_a77/ac6/example_build/tx/.cproject b/ports/cortex_a77/ac6/example_build/tx/.cproject index 137a756a..4b3c562b 100644 --- a/ports/cortex_a77/ac6/example_build/tx/.cproject +++ b/ports/cortex_a77/ac6/example_build/tx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a77/ac6/inc/tx_port.h b/ports/cortex_a77/ac6/inc/tx_port.h index a8d3fd48..e5352338 100644 --- a/ports/cortex_a77/ac6/inc/tx_port.h +++ b/ports/cortex_a77/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -369,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a77/ac6/src/tx_initialize_low_level.S b/ports/cortex_a77/ac6/src/tx_initialize_low_level.S index f456574e..7d2a4be3 100644 --- a/ports/cortex_a77/ac6/src/tx_initialize_low_level.S +++ b/ports/cortex_a77/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports/cortex_a77/ac6/src/tx_thread_context_restore.S b/ports/cortex_a77/ac6/src/tx_thread_context_restore.S index 8e0d5515..9ba82827 100644 --- a/ports/cortex_a77/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a77/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_a77/ac6/src/tx_thread_context_save.S b/ports/cortex_a77/ac6/src/tx_thread_context_save.S index 7768efc2..c2395155 100644 --- a/ports/cortex_a77/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a77/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_a77/ac6/src/tx_thread_fp_disable.c b/ports/cortex_a77/ac6/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports/cortex_a77/ac6/src/tx_thread_fp_disable.c +++ b/ports/cortex_a77/ac6/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports/cortex_a77/ac6/src/tx_thread_fp_enable.c b/ports/cortex_a77/ac6/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports/cortex_a77/ac6/src/tx_thread_fp_enable.c +++ b/ports/cortex_a77/ac6/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports/cortex_a77/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a77/ac6/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports/cortex_a77/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a77/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_a77/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a77/ac6/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports/cortex_a77/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a77/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports/cortex_a77/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a77/ac6/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports/cortex_a77/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a77/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports/cortex_a77/ac6/src/tx_thread_schedule.S b/ports/cortex_a77/ac6/src/tx_thread_schedule.S index 4cce4a62..057aa538 100644 --- a/ports/cortex_a77/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a77/ac6/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,18 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_a77/ac6/src/tx_thread_stack_build.S b/ports/cortex_a77/ac6/src/tx_thread_stack_build.S index 6c675d9b..01084da7 100644 --- a/ports/cortex_a77/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a77/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_a77/ac6/src/tx_thread_system_return.S b/ports/cortex_a77/ac6/src/tx_thread_system_return.S index 780bb128..b7593d79 100644 --- a/ports/cortex_a77/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a77/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_a77/ac6/src/tx_timer_interrupt.S b/ports/cortex_a77/ac6/src/tx_timer_interrupt.S index d84245c6..1b80a7f2 100644 --- a/ports/cortex_a77/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a77/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_a77/gnu/example_build/sample_threadx/.cproject b/ports/cortex_a77/gnu/example_build/sample_threadx/.cproject index 1c32cb32..40d4912d 100644 --- a/ports/cortex_a77/gnu/example_build/sample_threadx/.cproject +++ b/ports/cortex_a77/gnu/example_build/sample_threadx/.cproject @@ -1,170 +1,170 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a77/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports/cortex_a77/gnu/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports/cortex_a77/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports/cortex_a77/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports/cortex_a77/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports/cortex_a77/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports/cortex_a77/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports/cortex_a77/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports/cortex_a77/gnu/example_build/sample_threadx/sample_threadx.ld b/ports/cortex_a77/gnu/example_build/sample_threadx/sample_threadx.ld index eec8f12b..3bf47736 100644 --- a/ports/cortex_a77/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports/cortex_a77/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start diff --git a/ports/cortex_a77/gnu/example_build/sample_threadx/startup.S b/ports/cortex_a77/gnu/example_build/sample_threadx/startup.S index b71b45f8..b44806fe 100644 --- a/ports/cortex_a77/gnu/example_build/sample_threadx/startup.S +++ b/ports/cortex_a77/gnu/example_build/sample_threadx/startup.S @@ -328,7 +328,7 @@ el1_entry_aarch64: // // Cortex-A processors automatically invalidate their caches on reset // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). - // It is therefore not necessary for software to invalidate the caches + // It is therefore not necessary for software to invalidate the caches // on startup, however, this is done here in case of a warm reset. bl InvalidateUDCaches tlbi VMALLE1 diff --git a/ports/cortex_a77/gnu/example_build/sample_threadx/v8_aarch64.h b/ports/cortex_a77/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports/cortex_a77/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports/cortex_a77/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_a77/gnu/example_build/sample_threadx/v8_mmu.h b/ports/cortex_a77/gnu/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports/cortex_a77/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports/cortex_a77/gnu/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports/cortex_a77/gnu/example_build/tx/.cproject b/ports/cortex_a77/gnu/example_build/tx/.cproject index f1b8ed5b..9e5a975e 100644 --- a/ports/cortex_a77/gnu/example_build/tx/.cproject +++ b/ports/cortex_a77/gnu/example_build/tx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a77/gnu/inc/tx_port.h b/ports/cortex_a77/gnu/inc/tx_port.h index a8d3fd48..e5352338 100644 --- a/ports/cortex_a77/gnu/inc/tx_port.h +++ b/ports/cortex_a77/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -369,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a77/gnu/src/tx_initialize_low_level.S b/ports/cortex_a77/gnu/src/tx_initialize_low_level.S index 3dce3cea..3025f12b 100644 --- a/ports/cortex_a77/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_a77/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -99,4 +89,4 @@ _tx_initialize_low_level: /* Done, return to caller. */ RET // Return to caller -// } +// } diff --git a/ports/cortex_a77/gnu/src/tx_thread_context_restore.S b/ports/cortex_a77/gnu/src/tx_thread_context_restore.S index 8e0d5515..9ba82827 100644 --- a/ports/cortex_a77/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a77/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_a77/gnu/src/tx_thread_context_save.S b/ports/cortex_a77/gnu/src/tx_thread_context_save.S index 7768efc2..c2395155 100644 --- a/ports/cortex_a77/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a77/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_a77/gnu/src/tx_thread_fp_disable.c b/ports/cortex_a77/gnu/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports/cortex_a77/gnu/src/tx_thread_fp_disable.c +++ b/ports/cortex_a77/gnu/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports/cortex_a77/gnu/src/tx_thread_fp_enable.c b/ports/cortex_a77/gnu/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports/cortex_a77/gnu/src/tx_thread_fp_enable.c +++ b/ports/cortex_a77/gnu/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports/cortex_a77/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a77/gnu/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports/cortex_a77/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a77/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_a77/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a77/gnu/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports/cortex_a77/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a77/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports/cortex_a77/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a77/gnu/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports/cortex_a77/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a77/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports/cortex_a77/gnu/src/tx_thread_schedule.S b/ports/cortex_a77/gnu/src/tx_thread_schedule.S index 4cce4a62..057aa538 100644 --- a/ports/cortex_a77/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a77/gnu/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,18 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_a77/gnu/src/tx_thread_stack_build.S b/ports/cortex_a77/gnu/src/tx_thread_stack_build.S index 6c675d9b..01084da7 100644 --- a/ports/cortex_a77/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a77/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_a77/gnu/src/tx_thread_system_return.S b/ports/cortex_a77/gnu/src/tx_thread_system_return.S index 780bb128..b7593d79 100644 --- a/ports/cortex_a77/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a77/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_a77/gnu/src/tx_timer_interrupt.S b/ports/cortex_a77/gnu/src/tx_timer_interrupt.S index d84245c6..1b80a7f2 100644 --- a/ports/cortex_a77/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a77/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_a8/ac5/example_build/sample_threadx.c b/ports/cortex_a8/ac5/example_build/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports/cortex_a8/ac5/example_build/sample_threadx.c +++ b/ports/cortex_a8/ac5/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_a8/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_a8/ac5/example_build/tx_initialize_low_level.s index ddf3e8bb..89fec36b 100644 --- a/ports/cortex_a8/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_a8/ac5/example_build/tx_initialize_low_level.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -90,45 +90,39 @@ __vectors ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-A8/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-A8/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -179,7 +173,7 @@ _tx_initialize_low_level ; _tx_thread_system_stack_ptr = (VOID_PTR) (sp); ; LDR r1, =_tx_thread_system_stack_ptr ; Pickup address of system stack ptr - LDR r0, [r1, #0] ; Pickup system stack + LDR r0, [r1, #0] ; Pickup system stack ADD r0, r0, #4 ; Increment to next free word ; ; /* Save the first available memory address. */ @@ -201,7 +195,7 @@ _tx_initialize_low_level ; ; ;/* Define initial heap/stack routine for the ARM RealView (and ADS) startup code. This -; routine will set the initial stack to use the ThreadX IRQ & FIQ & +; routine will set the initial stack to use the ThreadX IRQ & FIQ & ; (optionally SYS) stack areas. */ ; EXPORT __user_initial_stackheap @@ -253,7 +247,7 @@ __tx_reserved_handler ; ; EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -261,21 +255,21 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; ; BL _tx_timer_interrupt ; Timer interrupt handler _tx_not_timer_interrupt ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ IF :DEF:TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -285,7 +279,7 @@ _tx_not_timer_interrupt ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ IF :DEF:TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -301,28 +295,28 @@ _tx_not_timer_interrupt __tx_example_vectored_irq_handler ; ; -; /* Save initial context and call context save to prepare for +; /* Save initial context and call context save to prepare for ; vectored ISR execution. */ ; ; STMDB sp!, {r0-r3} ; Save some scratch registers ; MRS r0, SPSR ; Pickup saved SPSR -; SUB lr, lr, #4 ; Adjust point of interrupt +; SUB lr, lr, #4 ; Adjust point of interrupt ; STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers ; BL _tx_thread_vectored_context_save ; Vectored context save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ; IF :DEF:TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_start @@ -331,7 +325,7 @@ __tx_example_vectored_irq_handler ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ; IF :DEF:TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_end @@ -353,11 +347,11 @@ __tx_fiq_processing_return ; /* At this point execution is still in the FIQ mode. The CPSR, point of ; interrupt, and all C scratch registers are available for use. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start ; from FIQ mode with interrupts disabled. This routine switches to the -; system mode and returns with FIQ interrupts enabled. +; system mode and returns with FIQ interrupts enabled. ; -; NOTE: It is very important to ensure all FIQ interrupts are cleared +; NOTE: It is very important to ensure all FIQ interrupts are cleared ; prior to enabling nested FIQ interrupts. */ IF :DEF:TX_ENABLE_FIQ_NESTING BL _tx_thread_fiq_nesting_start diff --git a/ports/cortex_a8/ac5/inc/tx_port.h b/ports/cortex_a8/ac5/inc/tx_port.h index 69e14287..7dc9a522 100644 --- a/ports/cortex_a8/ac5/inc/tx_port.h +++ b/ports/cortex_a8/ac5/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Cortex-A8/AC5 */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A8/AC5 */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -75,7 +67,7 @@ #include -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -111,12 +103,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -126,8 +118,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -174,7 +166,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -186,13 +178,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -206,11 +198,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -218,8 +210,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -246,21 +238,21 @@ typedef unsigned short USHORT; #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef __thumb - + #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (ULONG) __clz((unsigned int) m); \ - b = 31 - b; + b = 31 - b; #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -280,7 +272,7 @@ typedef unsigned short USHORT; { \ __enable_irq(); \ __enable_fiq(); \ - } + } #else @@ -289,7 +281,7 @@ typedef unsigned short USHORT; #define TX_RESTORE if (!interrupt_save_disabled) \ { \ __enable_irq(); \ - } + } #endif #else @@ -325,8 +317,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-A8/AC5 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A8/AC5 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a8/ac5/readme_threadx.txt b/ports/cortex_a8/ac5/readme_threadx.txt index 13fa045f..a52ee156 100644 --- a/ports/cortex_a8/ac5/readme_threadx.txt +++ b/ports/cortex_a8/ac5/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for Cortex-A8 + Microsoft's Azure RTOS ThreadX for Cortex-A8 Thumb & 32-bit Mode @@ -6,21 +6,21 @@ 1. Building the ThreadX run-time Library -First make sure you are in the "example_build" directory. Also, make sure that -you have setup your path and other environment variables necessary for the ARM -AC5 development environment. At this point you may run the build_threadx.bat -batch file. This will build the ThreadX run-time environment in the -"example_build" directory. +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the ARM +AC5 development environment. At this point you may run the build_threadx.bat +batch file. This will build the ThreadX run-time environment in the +"example_build" directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. 1.1 Building with Project Files -The ThreadX library can also be built via project files. Simply open -the tx.mcp file with project builder and select make. This will place +The ThreadX library can also be built via project files. Simply open +the tx.mcp file with project builder and select make. This will place the tx.a library file into the Debug sub-directory. @@ -29,45 +29,45 @@ the tx.a library file into the Debug sub-directory. The ThreadX demonstration is designed to execute under the ARM Windows-based simulator. -Building the demonstration is easy; simply execute the build_threadx_demo.bat -batch file while inside the "example_build" directory. +Building the demonstration is easy; simply execute the build_threadx_demo.bat +batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with tx.a. The resulting file sample_threadx.axf +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.axf is a binary file that can be downloaded and executed on the ARM simulator. 2.0.1 Building with Project Files -The ThreadX demonstration can also be built via project files. Simply open -the sample_threadx.mcp file with project builder and select make. This will place +The ThreadX demonstration can also be built via project files. Simply open +the sample_threadx.mcp file with project builder and select make. This will place the sample_threadx.axf output image into the Debug sub-directory. 3. System Initialization -The entry point in ThreadX for the Cortex-A8 using AC5 tools is at label -__main. This is defined within the AC5 compiler's startup code. In -addition, this is where all static and global pre-set C variable +The entry point in ThreadX for the Cortex-A8 using AC5 tools is at label +__main. This is defined within the AC5 compiler's startup code. In +addition, this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. By default, the vector area is defined to be located in the Init area, -which is defined at the top of tx_initialize_low_level.s. This area is typically -located at 0. In situations where this is impossible, the vectors at the beginning +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. By default, the vector area is defined to be located in the Init area, +which is defined at the top of tx_initialize_low_level.s. This area is typically +located at 0. In situations where this is impossible, the vectors at the beginning of the Init area should be copied to address 0. This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 4. Assembler / Compiler Switches -The following are compiler switches used in building the demonstration +The following are compiler switches used in building the demonstration system: Compiler Switch Meaning @@ -83,10 +83,10 @@ Linker Switch Meaning -o demo.axf Specifies demo output file name --elf Specifies elf output file format --ro Specifies that Read-Only memory starts at address 0 - --first tx_initialize_low_level.o(Init) + --first tx_initialize_low_level.o(Init) Specifies that the first area loaded is Init --remove Remove unused areas - --list Specifies map file name + --list Specifies map file name --symbols Specifies symbols for map file --map Creates a map file @@ -97,161 +97,161 @@ Application Defines ThreadX assembly files. If used, it should be used on all assembly files and the generic C source of - ThreadX should be compiled with + ThreadX should be compiled with TX_ENABLE_FIQ_SUPPORT defined as well. --PD "TX_ENABLE_IRQ_NESTING SETL {TRUE}" This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. --PD "TX_ENABLE_FIQ_NESTING SETL {TRUE}" This assembler define enables FIQ - nested support. If FIQ nested + nested support. If FIQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. In addition, IRQ nesting should also be enabled. -DTX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ interrupt handling in the ThreadX - generic C source. This define + generic C source. This define should also be used in conjunction with the corresponding assembler - define. + define. -DTX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - -DTX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + -DTX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - -DTX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + -DTX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - -DTX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + -DTX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - -DTX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + -DTX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - -DTX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + -DTX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - -DTX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + -DTX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - -DTX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + -DTX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - -DTX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + -DTX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - -DTX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + -DTX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - -DTX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + -DTX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - -DTX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + -DTX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - -DTX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + -DTX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - -DTX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + -DTX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - -DTX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + -DTX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - -DTX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + -DTX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - -DTX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + -DTX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - -DTX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + -DTX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - -DTX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + -DTX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - -DTX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + -DTX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. -DTX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - -DTX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + -DTX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - -DTX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + -DTX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. 5. Register Usage and Stack Frames -The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -269,39 +269,39 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make it run faster, you can change the build_threadx.bat file to -remove the -g option and enable all compiler optimizations. +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A8 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-A8 vectors start at address zero. The demonstration system startup -Init area contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +Init area contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs @@ -312,12 +312,12 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.s: EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -325,7 +325,7 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -338,7 +338,7 @@ __tx_irq_processing_return 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.s: EXPORT __tx_irq_example_handler @@ -348,12 +348,12 @@ __tx_irq_example_handler STMDB sp!, {r0-r3} ; Save some scratch registers MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers BL _tx_thread_vectored_context_save ; Call the vectored IRQ context save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -370,22 +370,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.s. When nested IRQ interrupts are no longer required, calling the _tx_thread_irq_nesting_end service disables nesting by disabling -IRQ interrupts and switching back to IRQ mode in preparation for the IRQ +IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -393,10 +393,10 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* Enable nested IRQ interrupts. NOTE: Since this service returns -; with IRQ interrupts enabled, all IRQ interrupt sources must be +; with IRQ interrupts enabled, all IRQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start -; +; ; /* Application ISR call(s) go here! */ ; ; /* Disable nested IRQ interrupts. The mode is switched back to @@ -409,12 +409,12 @@ __tx_irq_processing_return 7.3 FIQ Interrupts -By default, Cortex-A8 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, Cortex-A8 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.s. @@ -423,7 +423,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.s. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.s: @@ -451,18 +451,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.s. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -478,7 +478,7 @@ __tx_fiq_processing_return ; interrupt, and all C scratch registers are available for use. */ ; ; /* Enable nested FIQ interrupts. NOTE: Since this service returns -; with FIQ interrupts enabled, all FIQ interrupt sources must be +; with FIQ interrupts enabled, all FIQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start ; @@ -494,29 +494,29 @@ __tx_fiq_processing_return 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.s in the Integrator sub-directories. 9. Thumb/Cortex-A8 Mixed Mode -By default, ThreadX is setup for running in Cortex-A8 32-bit mode. This is -also true for the demonstration system. It is possible to build any -ThreadX file and/or the application in Thumb mode. If any Thumb code -is used the entire ThreadX source- both C and assembly - should be built +By default, ThreadX is setup for running in Cortex-A8 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. If any Thumb code +is used the entire ThreadX source- both C and assembly - should be built with the "-apcs /interwork" option. 10. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); diff --git a/ports/cortex_a8/ac5/src/tx_thread_context_restore.s b/ports/cortex_a8/ac5/src/tx_thread_context_restore.s index d2cbdc19..403ddd31 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_a8/ac5/src/tx_thread_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -54,44 +54,38 @@ SVC_MODE EQU 0x93 ; SVC mode ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore Cortex-A8/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-A8/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -121,13 +115,13 @@ _tx_thread_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3, #0] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3, #0] ; Store the counter + STR r2, [r3, #0] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs diff --git a/ports/cortex_a8/ac5/src/tx_thread_context_save.s b/ports/cortex_a8/ac5/src/tx_thread_context_save.s index 6c1d90c8..fbcea2bd 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_context_save.s +++ b/ports/cortex_a8/ac5/src/tx_thread_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,43 +39,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save Cortex-A8/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-A8/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -90,7 +84,7 @@ _tx_thread_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers IF :DEF:TX_ENABLE_FIQ_SUPPORT CPSID if ; Disable FIQ interrupts ENDIF @@ -109,7 +103,7 @@ _tx_thread_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -125,7 +119,7 @@ _tx_thread_context_save POP {lr} ; Recover ISR lr ENDIF - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; __tx_thread_not_nested_save ; } @@ -139,13 +133,13 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} ; Store other registers ; ; /* Save the current stack pointer in the thread's control block. */ @@ -165,7 +159,7 @@ __tx_thread_not_nested_save POP {lr} ; Recover ISR lr ENDIF - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ; else @@ -175,7 +169,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit @@ -190,7 +184,7 @@ __tx_thread_idle_system_save ENDIF ADD sp, sp, #16 ; Recover saved registers - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ;} diff --git a/ports/cortex_a8/ac5/src/tx_thread_fiq_context_restore.s b/ports/cortex_a8/ac5/src/tx_thread_fiq_context_restore.s index 9fb18339..3efdad98 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_a8/ac5/src/tx_thread_fiq_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -32,7 +32,7 @@ ; SVC_MODE EQU 0xD3 ; SVC mode FIQ_MODE EQU 0xD1 ; FIQ mode -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; ; @@ -50,44 +50,38 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_restore Cortex-A8/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore Cortex-A8/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the fiq interrupt context when processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* FIQ ISR Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) @@ -113,13 +107,13 @@ _tx_thread_fiq_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3] ; Store the counter + STR r2, [r3] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -164,7 +158,7 @@ __tx_thread_fiq_no_preempt_restore ; /* Restore interrupted thread or ISR. */ ; ; /* Pickup the saved stack pointer. */ -; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; ; ; /* Recover the saved context and return to the point of interrupt. */ ; @@ -209,7 +203,7 @@ _tx_skip_fiq_vfp_save MOV r3, #1 ; Build interrupt stack type STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR STR sp, [r0, #8] ; Save stack pointer in thread control - ; block + ; block ; ; /* Save the remaining time-slice and disable it. */ ; if (_tx_timer_time_slice) @@ -221,7 +215,7 @@ _tx_skip_fiq_vfp_save BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it ; ; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; -; _tx_timer_time_slice = 0; +; _tx_timer_time_slice = 0; ; STR r2, [r0, #24] ; Save thread's time-slice MOV r2, #0 ; Clear value diff --git a/ports/cortex_a8/ac5/src/tx_thread_fiq_context_save.s b/ports/cortex_a8/ac5/src/tx_thread_fiq_context_save.s index 7ba4eee3..2f9486dc 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_fiq_context_save.s +++ b/ports/cortex_a8/ac5/src/tx_thread_fiq_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,43 +39,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_save Cortex-A8/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save Cortex-A8/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) @@ -90,7 +84,7 @@ _tx_thread_fiq_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state CMP r2, #0 ; Is this the first interrupt? @@ -105,7 +99,7 @@ _tx_thread_fiq_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -121,38 +115,38 @@ _tx_thread_fiq_context_save POP {lr} ; Recover ISR lr ENDIF - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; __tx_thread_fiq_not_nested_save -; } +; } ; ; /* Otherwise, not nested, check to see if a thread was running. */ ; else if (_tx_thread_current_ptr) -; { +; { ; ADD r2, r2, #1 ; Increment the interrupt counter STR r2, [r3] ; Store it back in the variable LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in -; ; scheduling loop - nothing needs saving! + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, lr} ; Store other registers, Note that we don't -; ; need to save sl and ip since FIQ has -; ; copies of these registers. Nested +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested ; ; interrupt processing does need to save ; ; these registers. ; ; /* Save the current stack pointer in the thread's control block. */ -; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; ; ; /* Switch to the system stack. */ -; sp = _tx_thread_system_stack_ptr; +; sp = _tx_thread_system_stack_ptr; ; MOV r10, #0 ; Clear stack limit @@ -165,7 +159,7 @@ __tx_thread_fiq_not_nested_save POP {lr} ; Recover ISR lr ENDIF - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } ; else @@ -185,18 +179,18 @@ __tx_thread_fiq_idle_system_save ENDIF ; ; /* Not much to do here, save the current SPSR and LR for possible -; use in IRQ interrupted in idle system conditions, and return to +; use in IRQ interrupted in idle system conditions, and return to ; FIQ interrupt processing. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, lr} ; Store other registers that will get used -; ; or stripped off the stack in context -; ; restore - B __tx_fiq_processing_return ; Continue FIQ processing +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } -;} +;} ; END diff --git a/ports/cortex_a8/ac5/src/tx_thread_fiq_nesting_end.s b/ports/cortex_a8/ac5/src/tx_thread_fiq_nesting_end.s index 0089d6bd..885cbcf8 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_fiq_nesting_end.s +++ b/ports/cortex_a8/ac5/src/tx_thread_fiq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,56 +34,50 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_end Cortex-A8/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end Cortex-A8/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ -;/* processing from system mode back to FIQ mode prior to the ISR */ -;/* calling _tx_thread_fiq_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with FIQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) @@ -94,7 +88,7 @@ _tx_thread_fiq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_c, r0 ; Disable interrupts - LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports/cortex_a8/ac5/src/tx_thread_fiq_nesting_start.s b/ports/cortex_a8/ac5/src/tx_thread_fiq_nesting_start.s index 34b3d0a9..585a1e7d 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_fiq_nesting_start.s +++ b/ports/cortex_a8/ac5/src/tx_thread_fiq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_start Cortex-A8/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start Cortex-A8/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ -;/* processing to the system mode so nested FIQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with FIQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_a8/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_a8/ac5/src/tx_thread_interrupt_control.s index 8339da10..ee782a88 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_interrupt_control.s +++ b/ports/cortex_a8/ac5/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,42 +36,36 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control Cortex-A8/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-A8/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a8/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_a8/ac5/src/tx_thread_interrupt_disable.s index 72586e25..301a33e6 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_a8/ac5/src/tx_thread_interrupt_disable.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,41 +29,35 @@ ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable Cortex-A8/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-A8/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(void) @@ -80,7 +74,7 @@ _tx_thread_interrupt_disable IF :DEF:TX_ENABLE_FIQ_SUPPORT CPSID if ; Disable IRQ and FIQ ELSE - CPSID i ; Disable IRQ + CPSID i ; Disable IRQ ENDIF IF {INTER} = {TRUE} diff --git a/ports/cortex_a8/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_a8/ac5/src/tx_thread_interrupt_restore.s index 630a5dc9..25b1dbae 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_a8/ac5/src/tx_thread_interrupt_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,42 +29,36 @@ ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore Cortex-A8/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-A8/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function is responsible for restoring interrupts to the state */ ;/* returned by a previous _tx_thread_interrupt_disable call. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a8/ac5/src/tx_thread_irq_nesting_end.s b/ports/cortex_a8/ac5/src/tx_thread_irq_nesting_end.s index c3ff143f..5be031b4 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_irq_nesting_end.s +++ b/ports/cortex_a8/ac5/src/tx_thread_irq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,56 +34,50 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_end Cortex-A8/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-A8/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -;/* processing from system mode back to IRQ mode prior to the ISR */ -;/* calling _tx_thread_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) @@ -94,7 +88,7 @@ _tx_thread_irq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_c, r0 ; Disable interrupts - LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports/cortex_a8/ac5/src/tx_thread_irq_nesting_start.s b/ports/cortex_a8/ac5/src/tx_thread_irq_nesting_start.s index 67f48378..72b194a8 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_irq_nesting_start.s +++ b/ports/cortex_a8/ac5/src/tx_thread_irq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_start Cortex-A8/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-A8/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_context_save has been called and switches the IRQ */ -;/* processing to the system mode so nested IRQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_a8/ac5/src/tx_thread_schedule.s b/ports/cortex_a8/ac5/src/tx_thread_schedule.s index 42645b44..55808cb7 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_a8/ac5/src/tx_thread_schedule.s @@ -1,19 +1,19 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors -; * +; * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -41,45 +41,39 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule Cortex-A8/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-A8/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -108,7 +102,7 @@ __tx_thread_schedule_loop ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Lockout interrupts and ; transfer control to it. */ ; @@ -121,7 +115,7 @@ __tx_thread_schedule_loop ; /* Setup the current thread pointer. */ ; _tx_thread_current_ptr = _tx_thread_execute_ptr; ; - LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread STR r0, [r1, #0] ; Setup current thread pointer ; ; /* Increment the run count for this thread. */ @@ -135,7 +129,7 @@ __tx_thread_schedule_loop ; /* Setup time-slice, if present. */ ; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; ; - LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice ; variable LDR sp, [r0, #8] ; Switch stack pointers STR r3, [r2, #0] ; Setup time-slice diff --git a/ports/cortex_a8/ac5/src/tx_thread_stack_build.s b/ports/cortex_a8/ac5/src/tx_thread_stack_build.s index 18f16095..571c5d78 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_stack_build.s +++ b/ports/cortex_a8/ac5/src/tx_thread_stack_build.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -41,44 +41,38 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build Cortex-A8/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-A8/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function builds a stack frame on the supplied thread's stack. */ ;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ ;/* thread_ptr Pointer to thread control blk */ ;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -86,10 +80,10 @@ THUMB_BIT EQU 0x20 ; Thumb-bit EXPORT _tx_thread_stack_build _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-A8 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; a1 (r0) Initial value for a1 diff --git a/ports/cortex_a8/ac5/src/tx_thread_system_return.s b/ports/cortex_a8/ac5/src/tx_thread_system_return.s index 62155944..d0a1e738 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_system_return.s +++ b/ports/cortex_a8/ac5/src/tx_thread_system_return.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -33,50 +33,44 @@ IMPORT _tx_timer_time_slice IMPORT _tx_thread_schedule IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY - IMPORT _tx_execution_thread_exit + IMPORT _tx_execution_thread_exit ENDIF ; ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return Cortex-A8/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-A8/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -104,7 +98,7 @@ _tx_skip_solicited_vfp_save MOV r0, #0 ; Build a solicited stack type MRS r1, CPSR ; Pickup the CPSR STMDB sp!, {r0-r1} ; Save type and CPSR -; +; ; /* Lockout interrupts. */ ; IF :DEF:TX_ENABLE_FIQ_SUPPORT diff --git a/ports/cortex_a8/ac5/src/tx_thread_vectored_context_save.s b/ports/cortex_a8/ac5/src/tx_thread_vectored_context_save.s index e7d10bfb..f5cb7e2a 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_vectored_context_save.s +++ b/ports/cortex_a8/ac5/src/tx_thread_vectored_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -38,43 +38,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_vectored_context_save Cortex-A8/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-A8/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) @@ -135,7 +129,7 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Note: Minimal context of interrupted thread is already saved. */ @@ -171,7 +165,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports/cortex_a8/ac5/src/tx_timer_interrupt.s b/ports/cortex_a8/ac5/src/tx_timer_interrupt.s index 41b21a33..00a0b30c 100644 --- a/ports/cortex_a8/ac5/src/tx_timer_interrupt.s +++ b/ports/cortex_a8/ac5/src/tx_timer_interrupt.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -44,46 +44,40 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt Cortex-A8/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-A8/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -107,7 +101,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CMP r2, #0 ; Is it non-active? BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing @@ -225,13 +219,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CMP r2, #0 ; See if the flag is set BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing ; diff --git a/ports/cortex_a8/ac6/example_build/sample_threadx/.cproject b/ports/cortex_a8/ac6/example_build/sample_threadx/.cproject index e039b0b0..00f3c7c7 100644 --- a/ports/cortex_a8/ac6/example_build/sample_threadx/.cproject +++ b/ports/cortex_a8/ac6/example_build/sample_threadx/.cproject @@ -1,176 +1,176 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a8/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_a8/ac6/example_build/sample_threadx/sample_threadx.scat index d23881cd..66d0d95a 100644 --- a/ports/cortex_a8/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports/cortex_a8/ac6/example_build/sample_threadx/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports/cortex_a8/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_a8/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 083a57a7..76395459 100644 --- a/ports/cortex_a8/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_a8/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -91,14 +92,6 @@ $_tx_initialize_low_level: /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ .global _tx_initialize_low_level .type _tx_initialize_low_level,function diff --git a/ports/cortex_a8/ac6/example_build/tx/.cproject b/ports/cortex_a8/ac6/example_build/tx/.cproject index 3d1f0818..e2f1d00b 100644 --- a/ports/cortex_a8/ac6/example_build/tx/.cproject +++ b/ports/cortex_a8/ac6/example_build/tx/.cproject @@ -1,146 +1,146 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a8/ac6/inc/tx_port.h b/ports/cortex_a8/ac6/inc/tx_port.h index f9b96956..f0153046 100644 --- a/ports/cortex_a8/ac6/inc/tx_port.h +++ b/ports/cortex_a8/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,20 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Updated comments, removed */ -/* unneeded temp variable, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -320,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv7-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a8/ac6/readme_threadx.txt b/ports/cortex_a8/ac6/readme_threadx.txt index a6e5a5c0..37125d30 100644 --- a/ports/cortex_a8/ac6/readme_threadx.txt +++ b/ports/cortex_a8/ac6/readme_threadx.txt @@ -1,18 +1,18 @@ - Microsoft's Azure RTOS ThreadX for Cortex-A8 + Microsoft's Azure RTOS ThreadX for Cortex-A8 Using ARM Compiler 6 & DS 1. Import the ThreadX Projects -In order to build the ThreadX library and the ThreadX demonstration, first import -the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +In order to build the ThreadX library and the ThreadX demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) into your DS workspace. 2. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply right-click the Eclipse project -"tx" and then select the "Build Project" button. You should now observe the compilation +Building the ThreadX library is easy; simply right-click the Eclipse project +"tx" and then select the "Build Project" button. You should now observe the compilation and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. @@ -23,40 +23,40 @@ Since there is no ARM Cortex-A8 FVP, there are no instructions here for running the demonstration; users are expected to run the demonstration on their platform of choice. -Building the demonstration is easy; simply right-click the Eclipse project -"sample_threadx" and then select the "Build Project" button. You should now observe -the compilation and assembly of the ThreadX demonstration. This project build produces +Building the demonstration is easy; simply right-click the Eclipse project +"sample_threadx" and then select the "Build Project" button. You should now observe +the compilation and assembly of the ThreadX demonstration. This project build produces the ThreadX library file sample_threadx.axf. 4. System Initialization -The entry point in ThreadX for the Cortex-A8 using ARM tools is at label -"Vectors". This is defined within startup.S in the sample_threadx project. In addition, -this is where all static and global pre-set C variable initialization processing +The entry point in ThreadX for the Cortex-A8 using ARM tools is at label +"Vectors". This is defined within startup.S in the sample_threadx project. In addition, +this is where all static and global pre-set C variable initialization processing takes place. -This is also where initialization of a periodic timer interrupt source should take +This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level defines the first available address -for use by the application, which is supplied as the sole input parameter +In addition, _tx_initialize_low_level defines the first available address +for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 5. Register Usage and Stack Frames -The AC6 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The AC6 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -74,52 +74,52 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A8 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-A8 vectors start at address zero. The demonstration system startup -reset.S file contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +reset.S file contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs -ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -127,7 +127,7 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -140,7 +140,7 @@ __tx_irq_processing_return: 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_example_handler @@ -150,12 +150,12 @@ __tx_irq_example_handler: STMDB sp!, {r0-r3} @ Save some scratch registers MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers BL _tx_thread_vectored_context_save @ Call the vectored IRQ context save @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -172,22 +172,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.S. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables -nesting by disabling IRQ interrupts and switching back to IRQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -195,10 +195,10 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* Enable nested IRQ interrupts. NOTE: Since this service returns -@ with IRQ interrupts enabled, all IRQ interrupt sources must be +@ with IRQ interrupts enabled, all IRQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start -@ +@ @ /* Application ISR call(s) go here! */ @ @ /* Disable nested IRQ interrupts. The mode is switched back to @@ -211,12 +211,12 @@ __tx_irq_processing_return: 7.3 FIQ Interrupts -By default, FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.S. @@ -225,7 +225,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.S. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.S: @@ -253,18 +253,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.S. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -280,7 +280,7 @@ __tx_fiq_processing_return: @ interrupt, and all C scratch registers are available for use. */ @ @ /* Enable nested FIQ interrupts. NOTE: Since this service returns -@ with FIQ interrupts enabled, all FIQ interrupt sources must be +@ with FIQ interrupts enabled, all FIQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start @ @@ -296,12 +296,12 @@ __tx_fiq_processing_return: 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer -interrupt source, these services are not functional but the remainder of +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of ThreadX will still run. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.S for the demonstration system. @@ -309,7 +309,7 @@ found in the file tx_initialize_low_level.S for the demonstration system. 9. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); diff --git a/ports/cortex_a8/ac6/src/tx_thread_context_restore.S b/ports/cortex_a8/ac6/src/tx_thread_context_restore.S index 6b4a561d..41b0b0d0 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a8/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,23 +80,6 @@ IRQ_MODE = 0x12 // IRQ mode /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_restore .type _tx_thread_context_restore,function diff --git a/ports/cortex_a8/ac6/src/tx_thread_context_save.S b/ports/cortex_a8/ac6/src/tx_thread_context_save.S index eff06283..d2d29d34 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a8/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,23 +72,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_save .type _tx_thread_context_save,function diff --git a/ports/cortex_a8/ac6/src/tx_thread_fiq_context_restore.S b/ports/cortex_a8/ac6/src/tx_thread_fiq_context_restore.S index d2fbebe1..921c322c 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a8/ac6/src/tx_thread_fiq_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -78,20 +79,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* FIQ ISR Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_restore .type _tx_thread_fiq_context_restore,function diff --git a/ports/cortex_a8/ac6/src/tx_thread_fiq_context_save.S b/ports/cortex_a8/ac6/src/tx_thread_fiq_context_save.S index 88472a3d..2f1a6c40 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a8/ac6/src/tx_thread_fiq_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_save .type _tx_thread_fiq_context_save,function diff --git a/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_end.S index fa3886b8..a7ce701e 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_start.S index dbed1cf2..4f095dde 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a8/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a8/ac6/src/tx_thread_interrupt_control.S index d1223cb8..a5bc47f7 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a8/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,20 +69,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a8/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a8/ac6/src/tx_thread_interrupt_disable.S index a87d1a06..d7b53bc2 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a8/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,20 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a8/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a8/ac6/src/tx_thread_interrupt_restore.S index 53ff2813..3c31e94b 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a8/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,20 +68,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_end.S index 18aebc7c..cc4db3a7 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_start.S index a2ffd35d..3635874d 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a8/ac6/src/tx_thread_schedule.S b/ports/cortex_a8/ac6/src/tx_thread_schedule.S index f46a339b..a74e2050 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a8/ac6/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,23 +82,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a8/ac6/src/tx_thread_stack_build.S b/ports/cortex_a8/ac6/src/tx_thread_stack_build.S index 3876225a..827554a7 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a8/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,20 +75,6 @@ CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ int /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a8/ac6/src/tx_thread_system_return.S b/ports/cortex_a8/ac6/src/tx_thread_system_return.S index 0eed478d..1a17446b 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a8/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,23 +69,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a8/ac6/src/tx_thread_vectored_context_save.S b/ports/cortex_a8/ac6/src/tx_thread_vectored_context_save.S index fe8a98e8..91653b75 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a8/ac6/src/tx_thread_vectored_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_vectored_context_save .type _tx_thread_vectored_context_save,function diff --git a/ports/cortex_a8/ac6/src/tx_timer_interrupt.S b/ports/cortex_a8/ac6/src/tx_timer_interrupt.S index cb0c1fa2..179ac894 100644 --- a/ports/cortex_a8/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a8/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -77,20 +78,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a8/ghs/example_build/tx_initialize_low_level.arm b/ports/cortex_a8/ghs/example_build/tx_initialize_low_level.arm index 2fa61dc0..96b77de4 100644 --- a/ports/cortex_a8/ghs/example_build/tx_initialize_low_level.arm +++ b/ports/cortex_a8/ghs/example_build/tx_initialize_low_level.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a8/ghs/inc/tx_el.h b/ports/cortex_a8/ghs/inc/tx_el.h index b8926921..72e5bbe3 100644 --- a/ports/cortex_a8/ghs/inc/tx_el.h +++ b/ports/cortex_a8/ghs/inc/tx_el.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,12 +37,6 @@ /* EventAnalyzer. It is assumed that tx_api.h and tx_port.h have */ /* already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_EL_H diff --git a/ports/cortex_a8/ghs/inc/tx_port.h b/ports/cortex_a8/ghs/inc/tx_port.h index 6750bfe7..d9dd3413 100644 --- a/ports/cortex_a8/ghs/inc/tx_port.h +++ b/ports/cortex_a8/ghs/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -394,7 +386,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-A8/Green Hills Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A8/Green Hills Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a8/ghs/readme_threadx.txt b/ports/cortex_a8/ghs/readme_threadx.txt index be5de73a..849c7efe 100644 --- a/ports/cortex_a8/ghs/readme_threadx.txt +++ b/ports/cortex_a8/ghs/readme_threadx.txt @@ -1,19 +1,19 @@ - Microsoft's Azure RTOS ThreadX for Cortex-A8 + Microsoft's Azure RTOS ThreadX for Cortex-A8 Using the Green Hills Software Tools 1. Open the ThreadX Project Workspace -In order to build the ThreadX library and the ThreadX demonstration first load -the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the -"example_build" directory. +In order to build the ThreadX library and the ThreadX demonstration first load +the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the +"example_build" directory. 2. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply select the MULTI project file -tx.gpj and then select the build button. You should now observe the -compilation and assembly of the ThreadX library. This project build produces +Building the ThreadX library is easy; simply select the MULTI project file +tx.gpj and then select the build button. You should now observe the +compilation and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. @@ -21,55 +21,55 @@ the ThreadX library file tx.a. The ThreadX demonstration is designed to execute under the MULTI environment on the Green Hills Cortex-A8 simulator. The instructions that follow describe -how to get the ThreadX evaluation running under the MULTI Cortex-A8 simulation +how to get the ThreadX evaluation running under the MULTI Cortex-A8 simulation environment. -Building the demonstration is easy; simply select the MULTI project file -sample_threadx.gpj. At this point, select the "Project Build" button and observe -the compilation, assembly, and linkage of the ThreadX demonstration application. +Building the demonstration is easy; simply select the MULTI project file +sample_threadx.gpj. At this point, select the "Project Build" button and observe +the compilation, assembly, and linkage of the ThreadX demonstration application. -After the demonstration is built, invoke the MULTI ARM simulator by selecting -the simulator connection from within the sample_threadx.con connection file. -Once connected to the simulator, select the "Debug" button. You should now -observe the main function of sample_threadx.c. +After the demonstration is built, invoke the MULTI ARM simulator by selecting +the simulator connection from within the sample_threadx.con connection file. +Once connected to the simulator, select the "Debug" button. You should now +observe the main function of sample_threadx.c. At this point, you should setup a simulated timer interrupt for ThreadX by entering "timer 9999 irq" in the "target" window of the debugger. -You are now ready to execute the ThreadX demonstration system. Select -breakpoints and data watches to observe the execution of the sample_threadx.c +You are now ready to execute the ThreadX demonstration system. Select +breakpoints and data watches to observe the execution of the sample_threadx.c application. 4. EventAnalyzer Demonstration -To build a demonstration system that also logs events for the MULTI EventAnalyzer, -perform the same steps as the regular demo, except build the ThreadX library with -txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. -The resulting image will log all system events, which can then be displayed by the +To build a demonstration system that also logs events for the MULTI EventAnalyzer, +perform the same steps as the regular demo, except build the ThreadX library with +txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. +The resulting image will log all system events, which can then be displayed by the MULTI EventAnalyzer. 5. System Initialization -The system entry point using the Green Hills tools is at the label _start. -This is defined within the crt0.arm file supplied by Green Hills. In addition, -this is where all static and global preset C variable initialization +The system entry point using the Green Hills tools is at the label _start. +This is defined within the crt0.arm file supplied by Green Hills. In addition, +this is where all static and global preset C variable initialization processing is called from. After the Green Hills startup function returns, ThreadX initialization is called. The main initialization function is _tx_initialize_low_level and -is located in the file tx_initialize_low_level.arm. This function is responsible -for setting up various system data structures, interrupt vectors, and the +is located in the file tx_initialize_low_level.arm. This function is responsible +for setting up various system data structures, interrupt vectors, and the periodic timer interrupt source of ThreadX. -In addition, _tx_initialize_low_level determines where the first available +In addition, _tx_initialize_low_level determines where the first available RAM memory address is located. This address is supplied to tx_application_define. -By default, the first available RAM memory address is assumed to start at the -beginning of the ThreadX section .free_mem. If changes are made to the -sample_threadx.ld file, the .free_mem section should remain the last allocated -section in the main RAM area. The starting address of this section is passed +By default, the first available RAM memory address is assumed to start at the +beginning of the ThreadX section .free_mem. If changes are made to the +sample_threadx.ld file, the .free_mem section should remain the last allocated +section in the main RAM area. The starting address of this section is passed to tx_application_define. @@ -87,27 +87,27 @@ The following defines and their associated action are as follows: TX_ENABLE_FIQ_NESTING If defined, this brings in special FIQ interrupt nesting logic into the ThreadX library. This define should be applied - to the entire ThreadX library and the + to the entire ThreadX library and the define TX_ENABLE_FIQ_SUPPORT should also be defined. TX_ENABLE_FIQ_SUPPORT If defined, this brings in FIQ context save and restore logic necessary for applications to call ThreadX services from - FIQ interrupt handlers. This define - should be applied to the entire ThreadX + FIQ interrupt handlers. This define + should be applied to the entire ThreadX library. TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 4 in the "ThreadX User Guide" + Chapter 4 in the "ThreadX User Guide" for more details. TX_ENABLE_EVENT_LOGGING This define enables event logging for any or all of the ThreadX source code. If this - option is used anywhere, the tx_initialize_high_level.c + option is used anywhere, the tx_initialize_high_level.c file must be compiled with it as well, since this is where the event log is initialized. @@ -119,121 +119,121 @@ The following defines and their associated action are as follows: If this is enabled, run-time filtering logic is added to the event logging code. - TX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. 7. Register Usage and Stack Frames -The Green Hills compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) -are scratch registers for each function. All other registers used by a C -function must be preserved by the function. ThreadX takes advantage of this -in situations where a context switch happens as a result of making a ThreadX -service call (which is itself a C function). In such cases, the saved +The Green Hills compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) +are scratch registers for each function. All other registers used by a C +function must be preserved by the function. ThreadX takes advantage of this +in situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -251,40 +251,40 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 8. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make ThreadX run faster, you can change the tx.gpj project -to disable debug information and enable the desired optimizations. +to disable debug information and enable the desired optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined before tx_api.h is included. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. 9. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A8 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 9.1 Vector Area The Cortex-A8 vectors start at address zero. The demonstration system reset.arm -file contains the reset section (which contains all the ARM vectors) and is +file contains the reset section (which contains all the ARM vectors) and is typically loaded at address zero. On actual hardware platforms, this section -might have to be copied to address 0. +might have to be copied to address 0. 9.2 IRQ ISRs @@ -294,13 +294,13 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 9.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.arm: .globl __tx_irq_handler - .globl __tx_irq_processing_return + .globl __tx_irq_processing_return __tx_irq_handler: /* Jump to context save to save system context. */ @@ -308,7 +308,7 @@ __tx_irq_handler: __tx_irq_processing_return: /* At this point execution is still in the IRQ mode. The CPSR, point of - interrupt, and all C scratch registers are available for use. Note + interrupt, and all C scratch registers are available for use. Note that IRQ interrupts are still disabled upon return from the context save function. */ @@ -321,7 +321,7 @@ __tx_irq_processing_return: 9.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.arm: .globl __tx_irq_example_handler @@ -331,12 +331,12 @@ __tx_irq_example_handler: STMDB sp!, {r0-r3} # Save some scratch registers MRS r0, SPSR # Pickup saved SPSR - SUB lr, lr, #4 # Adjust point of interrupt + SUB lr, lr, #4 # Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} # Store other scratch registers BL _tx_thread_vectored_context_save # Call the vectored IRQ context save /* At this point execution is still in the IRQ mode. The CPSR, point of - interrupt, and all C scratch registers are available for use. Note + interrupt, and all C scratch registers are available for use. Note that IRQ interrupts are still disabled upon return from the context save function. */ @@ -353,22 +353,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.arm. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables nesting -by disabling IRQ interrupts and switching back to IRQ mode in preparation for +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.arm. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables nesting +by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in the +The following is an example of enabling IRQ nested interrupts in the typical IRQ handler: .globl __tx_irq_handler - .globl __tx_irq_processing_return + .globl __tx_irq_processing_return __tx_irq_handler: /* Jump to context save to save system context. */ @@ -376,10 +376,10 @@ __tx_irq_handler: __tx_irq_processing_return: /* Enable nested IRQ interrupts. NOTE: Since this service returns - with IRQ interrupts enabled, all IRQ interrupt sources must be + with IRQ interrupts enabled, all IRQ interrupt sources must be cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start - + /* Application ISR call(s) go here! */ /* Disable nested IRQ interrupts. The mode is switched back to @@ -392,9 +392,9 @@ __tx_irq_processing_return: 9.3 FIQ Interrupts -By default, Cortex-A8 FIQ interrupts are left completely enabled by ThreadX. -Of course, this means that the application is fully responsible for -saving/restoring any registers used in the FIQ ISR processing. In addition, +By default, Cortex-A8 FIQ interrupts are left completely enabled by ThreadX. +Of course, this means that the application is fully responsible for +saving/restoring any registers used in the FIQ ISR processing. In addition, no ThreadX service calls are allowed from the default FIQ ISRs. The default FIQ interrupt shell is located in tx_initialize_low_level.arm. @@ -403,7 +403,7 @@ FIQ interrupt shell is located in tx_initialize_low_level.arm. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.arm: @@ -431,18 +431,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.arm. When nested FIQ interrupts are no longer -required, calling the _tx_thread_fiq_nesting_end service disables nesting by -disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.arm. When nested FIQ interrupts are no longer +required, calling the _tx_thread_fiq_nesting_end service disables nesting by +disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -458,7 +458,7 @@ __tx_fiq_processing_return: interrupt, and all C scratch registers are available for use. */ /* Enable nested FIQ interrupts. NOTE: Since this service returns - with FIQ interrupts enabled, all FIQ interrupt sources must be + with FIQ interrupts enabled, all FIQ interrupt sources must be cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start @@ -475,29 +475,29 @@ __tx_fiq_processing_return: 10. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.arm. 11. Thumb/Cortex-A8 Mixed Mode -By default, ThreadX is setup for running in Cortex-A8 32-bit mode. This is -also true for the demonstration system. It is possible to build any +By default, ThreadX is setup for running in Cortex-A8 32-bit mode. This is +also true for the demonstration system. It is possible to build any ThreadX file and/or the application in Thumb mode. The only exception -to this is the file tx_thread_shell_entry.c. This file must always be +to this is the file tx_thread_shell_entry.c. This file must always be built in 32-bit mode. 12. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); @@ -521,7 +521,7 @@ information associated with this specific port of ThreadX: 04-02-2021 Release 6.1.6 changes: tx_port.h Updated macro definition -05/19/2020 Initial ThreadX version of Cortex-A8/Green Hills port. +05/19/2020 Initial ThreadX version of Cortex-A8/Green Hills port. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_a8/ghs/src/tx_el.c b/ports/cortex_a8/ghs/src/tx_el.c index 365622cd..b5d3b8b7 100644 --- a/ports/cortex_a8/ghs/src/tx_el.c +++ b/ports/cortex_a8/ghs/src/tx_el.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,12 +83,6 @@ UINT _tx_thread_interrupt_control(UINT new_posture); /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_el_initialize(VOID) { diff --git a/ports/cortex_a8/ghs/src/tx_thread_context_restore.arm b/ports/cortex_a8/ghs/src/tx_thread_context_restore.arm index 95465a10..8bc0eb43 100644 --- a/ports/cortex_a8/ghs/src/tx_thread_context_restore.arm +++ b/ports/cortex_a8/ghs/src/tx_thread_context_restore.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a8/ghs/src/tx_thread_context_save.arm b/ports/cortex_a8/ghs/src/tx_thread_context_save.arm index eb40e4c8..e0dead86 100644 --- a/ports/cortex_a8/ghs/src/tx_thread_context_save.arm +++ b/ports/cortex_a8/ghs/src/tx_thread_context_save.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a8/ghs/src/tx_thread_fiq_context_restore.arm b/ports/cortex_a8/ghs/src/tx_thread_fiq_context_restore.arm index dc0f5050..a1ae9cc0 100644 --- a/ports/cortex_a8/ghs/src/tx_thread_fiq_context_restore.arm +++ b/ports/cortex_a8/ghs/src/tx_thread_fiq_context_restore.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a8/ghs/src/tx_thread_fiq_context_save.arm b/ports/cortex_a8/ghs/src/tx_thread_fiq_context_save.arm index a233eb30..4befded9 100644 --- a/ports/cortex_a8/ghs/src/tx_thread_fiq_context_save.arm +++ b/ports/cortex_a8/ghs/src/tx_thread_fiq_context_save.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a8/ghs/src/tx_thread_fiq_nesting_end.arm b/ports/cortex_a8/ghs/src/tx_thread_fiq_nesting_end.arm index 6f78dabb..48065cce 100644 --- a/ports/cortex_a8/ghs/src/tx_thread_fiq_nesting_end.arm +++ b/ports/cortex_a8/ghs/src/tx_thread_fiq_nesting_end.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a8/ghs/src/tx_thread_fiq_nesting_start.arm b/ports/cortex_a8/ghs/src/tx_thread_fiq_nesting_start.arm index ea667ebb..178e2ac6 100644 --- a/ports/cortex_a8/ghs/src/tx_thread_fiq_nesting_start.arm +++ b/ports/cortex_a8/ghs/src/tx_thread_fiq_nesting_start.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a8/ghs/src/tx_thread_interrupt_control.arm b/ports/cortex_a8/ghs/src/tx_thread_interrupt_control.arm index d43559b4..11283b99 100644 --- a/ports/cortex_a8/ghs/src/tx_thread_interrupt_control.arm +++ b/ports/cortex_a8/ghs/src/tx_thread_interrupt_control.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a8/ghs/src/tx_thread_interrupt_disable.arm b/ports/cortex_a8/ghs/src/tx_thread_interrupt_disable.arm index 66db3d04..f693d578 100644 --- a/ports/cortex_a8/ghs/src/tx_thread_interrupt_disable.arm +++ b/ports/cortex_a8/ghs/src/tx_thread_interrupt_disable.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a8/ghs/src/tx_thread_interrupt_restore.arm b/ports/cortex_a8/ghs/src/tx_thread_interrupt_restore.arm index 372bde01..c344a482 100644 --- a/ports/cortex_a8/ghs/src/tx_thread_interrupt_restore.arm +++ b/ports/cortex_a8/ghs/src/tx_thread_interrupt_restore.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a8/ghs/src/tx_thread_irq_nesting_end.arm b/ports/cortex_a8/ghs/src/tx_thread_irq_nesting_end.arm index b16499ad..ebb1692b 100644 --- a/ports/cortex_a8/ghs/src/tx_thread_irq_nesting_end.arm +++ b/ports/cortex_a8/ghs/src/tx_thread_irq_nesting_end.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a8/ghs/src/tx_thread_irq_nesting_start.arm b/ports/cortex_a8/ghs/src/tx_thread_irq_nesting_start.arm index 1edd8c56..26d03b01 100644 --- a/ports/cortex_a8/ghs/src/tx_thread_irq_nesting_start.arm +++ b/ports/cortex_a8/ghs/src/tx_thread_irq_nesting_start.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a8/ghs/src/tx_thread_schedule.arm b/ports/cortex_a8/ghs/src/tx_thread_schedule.arm index f6ae087b..eca5af9c 100644 --- a/ports/cortex_a8/ghs/src/tx_thread_schedule.arm +++ b/ports/cortex_a8/ghs/src/tx_thread_schedule.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a8/ghs/src/tx_thread_stack_build.arm b/ports/cortex_a8/ghs/src/tx_thread_stack_build.arm index a9c921d4..d5320f10 100644 --- a/ports/cortex_a8/ghs/src/tx_thread_stack_build.arm +++ b/ports/cortex_a8/ghs/src/tx_thread_stack_build.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a8/ghs/src/tx_thread_system_return.arm b/ports/cortex_a8/ghs/src/tx_thread_system_return.arm index 32a1c85f..af41522e 100644 --- a/ports/cortex_a8/ghs/src/tx_thread_system_return.arm +++ b/ports/cortex_a8/ghs/src/tx_thread_system_return.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a8/ghs/src/tx_thread_vectored_context_save.arm b/ports/cortex_a8/ghs/src/tx_thread_vectored_context_save.arm index 0fcc99c3..ddbea71e 100644 --- a/ports/cortex_a8/ghs/src/tx_thread_vectored_context_save.arm +++ b/ports/cortex_a8/ghs/src/tx_thread_vectored_context_save.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a8/ghs/src/tx_timer_interrupt.arm b/ports/cortex_a8/ghs/src/tx_timer_interrupt.arm index eeb14672..8a64d59e 100644 --- a/ports/cortex_a8/ghs/src/tx_timer_interrupt.arm +++ b/ports/cortex_a8/ghs/src/tx_timer_interrupt.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a8/gnu/example_build/MP_GIC.h b/ports/cortex_a8/gnu/example_build/MP_GIC.h index 82f2ea13..070a4936 100644 --- a/ports/cortex_a8/gnu/example_build/MP_GIC.h +++ b/ports/cortex_a8/gnu/example_build/MP_GIC.h @@ -4,7 +4,7 @@ // // Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports/cortex_a8/gnu/example_build/MP_GIC.s b/ports/cortex_a8/gnu/example_build/MP_GIC.s index 6626d583..1387a5b5 100644 --- a/ports/cortex_a8/gnu/example_build/MP_GIC.s +++ b/ports/cortex_a8/gnu/example_build/MP_GIC.s @@ -1,7 +1,7 @@ //---------------------------------------------------------------- // Copyright (c) 2005-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // // Cortex-A8MP example - Startup Code @@ -37,7 +37,7 @@ enableGIC: STR r1, [r0] // Write the GIC Enable Register (ICDDCR) BX lr - + // ------------------------------------------------------------ .global disableGIC @@ -54,7 +54,7 @@ disableGIC: STR r1, [r0] // Write the GIC Enable Register (ICDDCR) BX lr - + // ------------------------------------------------------------ @@ -84,10 +84,10 @@ enableIntID: STR r3, [r0, r2] // Store out (ICDISER) BX lr - + // ------------------------------------------------------------ - + .global disableIntID .type disableIntID,function // void disableIntID(unsigned int ID) @@ -112,7 +112,7 @@ disableIntID: STR r3, [r0, r2] // Store out (ICDICER) BX lr - + // ------------------------------------------------------------ @@ -130,7 +130,7 @@ setIntPriority: // r0 = base addr // r1 = priority // r2 = ID - + // Make sure that priority value is only 5 bits, and convert to expected format AND r1, r1, #0x1F MOV r1, r1, LSL #3 @@ -156,7 +156,7 @@ setIntPriority: STR r3, [r0] // And store it back again (ICDIPR) BX lr - + // ------------------------------------------------------------ @@ -175,7 +175,7 @@ enableGICProcessorInterface: STR r1, [r0, #0x0] // Write the Processor Interface Control register (ICCICR/ICPICR) BX lr - + // ------------------------------------------------------------ @@ -195,7 +195,7 @@ disableGICProcessorInterface: STR r1, [r0, #0x0] // Write the Processor Interface Control register (ICCICR/ICPICR) BX lr - + // ------------------------------------------------------------ @@ -214,8 +214,8 @@ setPriorityMask: STR r0, [r1, #0x4] // Write the Priority Mask register (ICCPMR/ICCIPMR) BX lr - - + + // ------------------------------------------------------------ .global setBinaryPoint @@ -231,7 +231,7 @@ setBinaryPoint: STR r0, [r1, #0x8] // Write the Binary register (ICCBPR/ICCBPR) BX lr - + // ------------------------------------------------------------ @@ -245,7 +245,7 @@ readIntAck: LDR r0, [r0, #0xC] // Read the Interrupt Acknowledge Register (ICCIAR) BX lr - + // ------------------------------------------------------------ @@ -262,8 +262,8 @@ writeEOI: STR r0, [r1, #0x10] // Write ID to the End of Interrupt register (ICCEOIR) BX lr - - + + //---------------------------------------------------------------- // SGI //---------------------------------------------------------------- diff --git a/ports/cortex_a8/gnu/example_build/MP_PrivateTimer.S b/ports/cortex_a8/gnu/example_build/MP_PrivateTimer.S index b1e2701b..7b83be9e 100644 --- a/ports/cortex_a8/gnu/example_build/MP_PrivateTimer.S +++ b/ports/cortex_a8/gnu/example_build/MP_PrivateTimer.S @@ -64,7 +64,7 @@ stop_private_timer: get_private_timer_count: BX lr - + // ------------------------------------------------------------ // void clear_private_timer_irq(void) diff --git a/ports/cortex_a8/gnu/example_build/reset.S b/ports/cortex_a8/gnu/example_build/reset.S index 3ce9efb7..f2e0522b 100644 --- a/ports/cortex_a8/gnu/example_build/reset.S +++ b/ports/cortex_a8/gnu/example_build/reset.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a8/gnu/example_build/sample_threadx.ld b/ports/cortex_a8/gnu/example_build/sample_threadx.ld index cb42c11c..d43e28f1 100644 --- a/ports/cortex_a8/gnu/example_build/sample_threadx.ld +++ b/ports/cortex_a8/gnu/example_build/sample_threadx.ld @@ -7,7 +7,7 @@ OUTPUT_ARCH(arm) SECTIONS { . = 0x00000000; - + .vectors : {reset.o(.text) } /* Read-only sections, merged into text segment: */ @@ -94,8 +94,8 @@ SECTIONS *(.gnu.linkonce.t*) *(.glue_7t) *(.glue_7) } =0 - .init : - { + .init : + { KEEP (*(.init)) } =0 _etext = .; @@ -120,7 +120,7 @@ SECTIONS .data1 : { *(.data1) } .eh_frame : { KEEP (*(.eh_frame)) } .gcc_except_table : { *(.gcc_except_table) } - .ctors : + .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is @@ -153,9 +153,9 @@ SECTIONS /* We want the small data sections together, so single-instruction offsets can access them all, and initialized data all before uninitialized, so we can shorten the on-disk segment size. */ - .sdata : + .sdata : { - *(.sdata) + *(.sdata) *(.sdata.*) *(.gnu.linkonce.s.*) } @@ -191,7 +191,7 @@ SECTIONS _stack_bottom = ABSOLUTE(.) ; - /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and + /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and SYS stack if nested interrupts are enabled. */ . = ALIGN(8) ; . += 4096 ; diff --git a/ports/cortex_a8/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_a8/gnu/example_build/tx_initialize_low_level.S index a0adb55d..1120db44 100644 --- a/ports/cortex_a8/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_a8/gnu/example_build/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -100,17 +101,6 @@ $_tx_initialize_low_level: /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_initialize_low_level .type _tx_initialize_low_level,function @@ -242,7 +232,7 @@ __tx_irq_processing_return: if nested IRQ interrupts are desired. Interrupts may be re-enabled over small code sequences where lr is saved before enabling interrupts and restored after interrupts are again disabled. */ - + PUSH {r4, r5} // Save some preserved registers (r5 is saved just for 8-byte alignment) BL readIntAck MOV r4, r0 diff --git a/ports/cortex_a8/gnu/example_build/v7.h b/ports/cortex_a8/gnu/example_build/v7.h index 5a08b43f..c18b945c 100644 --- a/ports/cortex_a8/gnu/example_build/v7.h +++ b/ports/cortex_a8/gnu/example_build/v7.h @@ -4,7 +4,7 @@ // // Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports/cortex_a8/gnu/example_build/v7.s b/ports/cortex_a8/gnu/example_build/v7.s index 82c9ab1e..9487ddde 100644 --- a/ports/cortex_a8/gnu/example_build/v7.s +++ b/ports/cortex_a8/gnu/example_build/v7.s @@ -3,7 +3,7 @@ // // Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ @@ -20,7 +20,7 @@ enableInterrupts: CPSIE i BX lr - + .global disableInterrupts .type disableInterrupts,function @@ -28,7 +28,7 @@ enableInterrupts: disableInterrupts: CPSID i BX lr - + // ------------------------------------------------------------ // Cache Maintenance @@ -44,7 +44,7 @@ enableCaches: MCR p15, 0, r0, c1, c0, 0 // Write System Control Register ISB BX lr - + .global disableCaches @@ -57,7 +57,7 @@ disableCaches: MCR p15, 0, r0, c1, c0, 0 // Write System Control Register ISB BX lr - + .global cleanDCache @@ -114,7 +114,7 @@ clean_dcache_finished: POP {r4-r12} BX lr - + .global cleanInvalidateDCache .type cleanInvalidateDCache,function @@ -170,7 +170,7 @@ clean_invalidate_dcache_finished: POP {r4-r12} BX lr - + .global invalidateCaches @@ -229,7 +229,7 @@ invalidate_caches_skip: invalidate_caches_finished: POP {r4-r12} BX lr - + .global invalidateCaches_IS @@ -284,7 +284,7 @@ invalidate_caches_is_skip: invalidate_caches_is_finished: POP {r4-r12} BX lr - + // ------------------------------------------------------------ // TLB @@ -297,7 +297,7 @@ invalidateUnifiedTLB: MOV r0, #0 MCR p15, 0, r0, c8, c7, 0 // TLBIALL - Invalidate entire unified TLB BX lr - + .global invalidateUnifiedTLB_IS .type invalidateUnifiedTLB_IS,function @@ -306,7 +306,7 @@ invalidateUnifiedTLB_IS: MOV r0, #1 MCR p15, 0, r0, c8, c3, 0 // TLBIALLIS - Invalidate entire unified TLB Inner Shareable BX lr - + // ------------------------------------------------------------ // Branch Prediction @@ -319,7 +319,7 @@ flushBranchTargetCache: MOV r0, #0 MCR p15, 0, r0, c7, c5, 6 // BPIALL - Invalidate entire branch predictor array BX lr - + .global flushBranchTargetCache_IS .type flushBranchTargetCache_IS,function @@ -328,7 +328,7 @@ flushBranchTargetCache_IS: MOV r0, #0 MCR p15, 0, r0, c7, c1, 6 // BPIALLIS - Invalidate entire branch predictor array Inner Shareable BX lr - + // ------------------------------------------------------------ // High Vecs @@ -343,7 +343,7 @@ enableHighVecs: MCR p15, 0, r0, c1, c0, 0 // Write Control Register ISB BX lr - + .global disableHighVecs .type disableHighVecs,function @@ -354,7 +354,7 @@ disableHighVecs: MCR p15, 0, r0, c1, c0, 0 // Write Control Register ISB BX lr - + // ------------------------------------------------------------ // Context ID @@ -366,7 +366,7 @@ disableHighVecs: getContextID: MRC p15, 0, r0, c13, c0, 1 // Read Context ID Register BX lr - + .global setContextID .type setContextID,function @@ -374,7 +374,7 @@ getContextID: setContextID: MCR p15, 0, r0, c13, c0, 1 // Write Context ID Register BX lr - + // ------------------------------------------------------------ // ID registers @@ -386,7 +386,7 @@ setContextID: getMIDR: MRC p15, 0, r0, c0, c0, 0 // Read Main ID Register (MIDR) BX lr - + .global getMPIDR .type getMPIDR,function @@ -394,7 +394,7 @@ getMIDR: getMPIDR: MRC p15, 0, r0, c0 ,c0, 5// Read Multiprocessor ID register (MPIDR) BX lr - + // ------------------------------------------------------------ // CP15 SMP related @@ -407,7 +407,7 @@ getMPIDR: getBaseAddr: MRC p15, 4, r0, c15, c0, 0 // Read peripheral base address BX lr - + // ------------------------------------------------------------ @@ -419,7 +419,7 @@ getCPUID: MRC p15, 0, r0, c0, c0, 5 // Read CPU ID register AND r0, r0, #0x03 // Mask off, leaving the CPU ID field BX lr - + // ------------------------------------------------------------ @@ -431,7 +431,7 @@ goToSleep: WFI // Go into standby B goToSleep // Catch in case of rogue events BX lr - + // ------------------------------------------------------------ @@ -451,7 +451,7 @@ joinSMP: ISB BX lr - + // ------------------------------------------------------------ @@ -469,7 +469,7 @@ leaveSMP: ISB BX lr - + // ------------------------------------------------------------ // End of v7.s diff --git a/ports/cortex_a8/gnu/inc/tx_port.h b/ports/cortex_a8/gnu/inc/tx_port.h index f9b96956..f0153046 100644 --- a/ports/cortex_a8/gnu/inc/tx_port.h +++ b/ports/cortex_a8/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,20 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Updated comments, removed */ -/* unneeded temp variable, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -320,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv7-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a8/gnu/readme_threadx.txt b/ports/cortex_a8/gnu/readme_threadx.txt index 8f57bf4a..437f49d8 100644 --- a/ports/cortex_a8/gnu/readme_threadx.txt +++ b/ports/cortex_a8/gnu/readme_threadx.txt @@ -1,55 +1,55 @@ - Microsoft's Azure RTOS ThreadX for Cortex-A8 + Microsoft's Azure RTOS ThreadX for Cortex-A8 Using the GNU Tools 1. Building the ThreadX run-time Library -First make sure you are in the "example_build" directory. Also, make sure that -you have setup your path and other environment variables necessary for the GNU -development environment. +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the GNU +development environment. -At this point you may run the build_threadx.bat batch file. This will build the -ThreadX run-time environment in the "example_build" directory. +At this point you may run the build_threadx.bat batch file. This will build the +ThreadX run-time environment in the "example_build" directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. 2. Demonstration System -Building the demonstration is easy; simply execute the build_threadx_sample.bat -batch file while inside the "example_build" directory. +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with TX.A. The resulting file DEMO is a binary file +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with TX.A. The resulting file DEMO is a binary file that can be downloaded and executed. 3. System Initialization -The entry point in ThreadX for the Cortex-A8 using GNU tools is at label _start. +The entry point in ThreadX for the Cortex-A8 using GNU tools is at label _start. This is defined within the modified version of the GNU startup code - crt0.S. -The ThreadX tx_initialize_low_level.S file is responsible for setting up various -system data structures, the interrupt vectors, and a periodic timer interrupt source. -By default, the vector area is defined to be located at the "__vectors" label, -which is defined in reset.S. This area is typically located at 0. In situations -where this is impossible, the vectors at the "__vectors" label should be copied +The ThreadX tx_initialize_low_level.S file is responsible for setting up various +system data structures, the interrupt vectors, and a periodic timer interrupt source. +By default, the vector area is defined to be located at the "__vectors" label, +which is defined in reset.S. This area is typically located at 0. In situations +where this is impossible, the vectors at the "__vectors" label should be copied to address 0. -This is also where initialization of a periodic timer interrupt source should take +This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level defines the first available address -for use by the application, which is supplied as the sole input parameter +In addition, _tx_initialize_low_level defines the first available address +for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 4. Assembler / Compiler Switches -The following are compiler switches used in building the demonstration +The following are compiler switches used in building the demonstration system: Compiler/Assembler Meaning @@ -73,164 +73,164 @@ Application Defines ( -D option) ThreadX assembly files. If used, it should be used on all assembly files and the generic C source of - ThreadX should be compiled with + ThreadX should be compiled with TX_ENABLE_FIQ_SUPPORT defined as well. TX_ENABLE_IRQ_NESTING This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.S. TX_ENABLE_FIQ_NESTING This assembler define enables FIQ - nested support. If FIQ nested + nested support. If FIQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.S. In addition, IRQ nesting should also be enabled. TX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ interrupt handling in the ThreadX - generic C source. This define + generic C source. This define should also be used in conjunction with the corresponding assembler - define. + define. TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - TX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. 5. Register Usage and Stack Frames -The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -248,52 +248,52 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A8 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-A8 vectors start at address zero. The demonstration system startup -reset.S file contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +reset.S file contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs -ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -301,7 +301,7 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -314,7 +314,7 @@ __tx_irq_processing_return: 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_example_handler @@ -324,12 +324,12 @@ __tx_irq_example_handler: STMDB sp!, {r0-r3} @ Save some scratch registers MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers BL _tx_thread_vectored_context_save @ Call the vectored IRQ context save @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -346,22 +346,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.S. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables -nesting by disabling IRQ interrupts and switching back to IRQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -369,10 +369,10 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* Enable nested IRQ interrupts. NOTE: Since this service returns -@ with IRQ interrupts enabled, all IRQ interrupt sources must be +@ with IRQ interrupts enabled, all IRQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start -@ +@ @ /* Application ISR call(s) go here! */ @ @ /* Disable nested IRQ interrupts. The mode is switched back to @@ -385,12 +385,12 @@ __tx_irq_processing_return: 7.3 FIQ Interrupts -By default, FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.S. @@ -399,7 +399,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.S. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.S: @@ -427,18 +427,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.S. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -454,7 +454,7 @@ __tx_fiq_processing_return: @ interrupt, and all C scratch registers are available for use. */ @ @ /* Enable nested FIQ interrupts. NOTE: Since this service returns -@ with FIQ interrupts enabled, all FIQ interrupt sources must be +@ with FIQ interrupts enabled, all FIQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start @ @@ -470,12 +470,12 @@ __tx_fiq_processing_return: 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer -interrupt source, these services are not functional but the remainder of +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of ThreadX will still run. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.S for the demonstration system. @@ -483,7 +483,7 @@ found in the file tx_initialize_low_level.S for the demonstration system. 9. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); diff --git a/ports/cortex_a8/gnu/src/tx_thread_context_restore.S b/ports/cortex_a8/gnu/src/tx_thread_context_restore.S index 6b4a561d..41b0b0d0 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a8/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,23 +80,6 @@ IRQ_MODE = 0x12 // IRQ mode /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_restore .type _tx_thread_context_restore,function diff --git a/ports/cortex_a8/gnu/src/tx_thread_context_save.S b/ports/cortex_a8/gnu/src/tx_thread_context_save.S index eff06283..d2d29d34 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a8/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,23 +72,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_save .type _tx_thread_context_save,function diff --git a/ports/cortex_a8/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_a8/gnu/src/tx_thread_fiq_context_restore.S index d2fbebe1..921c322c 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a8/gnu/src/tx_thread_fiq_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -78,20 +79,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* FIQ ISR Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_restore .type _tx_thread_fiq_context_restore,function diff --git a/ports/cortex_a8/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_a8/gnu/src/tx_thread_fiq_context_save.S index 88472a3d..2f1a6c40 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a8/gnu/src/tx_thread_fiq_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_save .type _tx_thread_fiq_context_save,function diff --git a/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_end.S index fa3886b8..a7ce701e 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_start.S index dbed1cf2..4f095dde 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a8/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a8/gnu/src/tx_thread_interrupt_control.S index d1223cb8..a5bc47f7 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a8/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,20 +69,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a8/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a8/gnu/src/tx_thread_interrupt_disable.S index a87d1a06..d7b53bc2 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a8/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,20 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a8/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a8/gnu/src/tx_thread_interrupt_restore.S index 53ff2813..3c31e94b 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a8/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,20 +68,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_end.S index 18aebc7c..cc4db3a7 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_start.S index a2ffd35d..3635874d 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a8/gnu/src/tx_thread_schedule.S b/ports/cortex_a8/gnu/src/tx_thread_schedule.S index f46a339b..a74e2050 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a8/gnu/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,23 +82,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a8/gnu/src/tx_thread_stack_build.S b/ports/cortex_a8/gnu/src/tx_thread_stack_build.S index 3876225a..827554a7 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a8/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,20 +75,6 @@ CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ int /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a8/gnu/src/tx_thread_system_return.S b/ports/cortex_a8/gnu/src/tx_thread_system_return.S index 0eed478d..1a17446b 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a8/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,23 +69,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a8/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_a8/gnu/src/tx_thread_vectored_context_save.S index fe8a98e8..91653b75 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a8/gnu/src/tx_thread_vectored_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_vectored_context_save .type _tx_thread_vectored_context_save,function diff --git a/ports/cortex_a8/gnu/src/tx_timer_interrupt.S b/ports/cortex_a8/gnu/src/tx_timer_interrupt.S index cb0c1fa2..179ac894 100644 --- a/ports/cortex_a8/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a8/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -77,20 +78,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a8/iar/example_build/cstartup.s b/ports/cortex_a8/iar/example_build/cstartup.s index b95efc0e..3da2b79d 100644 --- a/ports/cortex_a8/iar/example_build/cstartup.s +++ b/ports/cortex_a8/iar/example_build/cstartup.s @@ -1,7 +1,7 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; -;; Part one of the system initialization code, +;; Part one of the system initialization code, ;; contains low-level ;; initialization. ;; @@ -71,13 +71,13 @@ FIQ_Addr: DCD __tx_fiq_handler SECTION .text:CODE:NOROOT(2) -; PUBLIC ?cstartup +; PUBLIC ?cstartup EXTERN ?main REQUIRE __vector - ARM - -__iar_program_start: + ARM + +__iar_program_start: ?cstartup: ; diff --git a/ports/cortex_a8/iar/example_build/sample_threadx.c b/ports/cortex_a8/iar/example_build/sample_threadx.c index c7c300cb..afbd4ea8 100644 --- a/ports/cortex_a8/iar/example_build/sample_threadx.c +++ b/ports/cortex_a8/iar/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -83,42 +83,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -126,23 +126,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -245,11 +245,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -308,7 +308,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -361,7 +361,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_a8/iar/example_build/tx_initialize_low_level.s b/ports/cortex_a8/iar/example_build/tx_initialize_low_level.s index f6ed88d7..eff62877 100644 --- a/ports/cortex_a8/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_a8/iar/example_build/tx_initialize_low_level.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -62,7 +62,7 @@ SYS_MODE DEFINE 0xDF ; Disable irq,fiq SYS mode ; ; ; -;/* Define the FREE_MEM segment that will specify where free memory is +;/* Define the FREE_MEM segment that will specify where free memory is ; defined. This must also be located in at the end of other RAM segments ; in the linker control file. The value of this segment is what is passed ; to tx_application_define. */ @@ -75,45 +75,39 @@ __tx_free_memory_start ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-A8/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-A8/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -146,7 +140,7 @@ _tx_initialize_low_level ; LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address STR r0, [r2, #0] ; Save first free memory address -; +; ; /* Setup Timer for periodic interrupts. */ ; ; /* Done, return to caller. */ @@ -188,7 +182,7 @@ __tx_reserved_handler RSEG .text:CODE:NOROOT(2) PUBLIC __tx_irq_handler RSEG .text:CODE:NOROOT(2) - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -196,17 +190,17 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -221,7 +215,7 @@ __tx_irq_processing_return ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -240,22 +234,22 @@ __tx_irq_processing_return ; /* Jump to context save to save system context. */ ; STMDB sp!, {r0-r3} ; Save some scratch registers ; MRS r0, SPSR ; Pickup saved SPSR -; SUB lr, lr, #4 ; Adjust point of interrupt +; SUB lr, lr, #4 ; Adjust point of interrupt ; STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; BL _tx_thread_vectored_context_save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ;#ifdef TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_start @@ -264,7 +258,7 @@ __tx_irq_processing_return ; /* Application IRQ handler is called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ;#ifdef TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_end @@ -288,11 +282,11 @@ __tx_fiq_processing_return ; /* At this point execution is still in the FIQ mode. The CPSR, point of ; interrupt, and all C scratch registers are available for use. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start ; from FIQ mode with interrupts disabled. This routine switches to the -; system mode and returns with FIQ interrupts enabled. +; system mode and returns with FIQ interrupts enabled. ; -; NOTE: It is very important to ensure all FIQ interrupts are cleared +; NOTE: It is very important to ensure all FIQ interrupts are cleared ; prior to enabling nested FIQ interrupts. */ #ifdef TX_ENABLE_FIQ_NESTING BL _tx_thread_fiq_nesting_start diff --git a/ports/cortex_a8/iar/inc/tx_port.h b/ports/cortex_a8/iar/inc/tx_port.h index 494a9be7..940d7f68 100644 --- a/ports/cortex_a8/iar/inc/tx_port.h +++ b/ports/cortex_a8/iar/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Cortex-A8/IAR */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A8/IAR */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -79,7 +71,7 @@ #endif -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -115,12 +107,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -130,8 +122,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -188,7 +180,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -202,18 +194,18 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ - VOID *tx_thread_iar_tls_pointer; + VOID *tx_thread_iar_tls_pointer; #else #define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; #endif -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -227,11 +219,11 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -241,23 +233,23 @@ ULONG _tx_misra_time_stamp_get(VOID); #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #if (__VER__ < 8000000) -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #endif #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -285,8 +277,8 @@ void __iar_Initlocks(void); #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -297,22 +289,22 @@ void __iar_Initlocks(void); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (UINT) __CLZ(m); \ - b = 31 - b; + b = 31 - b; #endif #endif #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ /* First, check and see what mode the file is being compiled in. The IAR compiler - defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode + defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode is present. If ARM 32-bit mode is present, the fast CPSR manipulation macros are available. Otherwise, if Thumb mode is present, we must use function calls. */ @@ -382,8 +374,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-A8/IAR Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A8/IAR Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_a8/iar/readme_threadx.txt b/ports/cortex_a8/iar/readme_threadx.txt index 9c55e729..cd01608c 100644 --- a/ports/cortex_a8/iar/readme_threadx.txt +++ b/ports/cortex_a8/iar/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for Cortex-A8 + Microsoft's Azure RTOS ThreadX for Cortex-A8 Thumb & 32-bit Mode @@ -7,10 +7,10 @@ 1. Building the ThreadX run-time Library Building the ThreadX library is easy. First, open the Azure RTOS workspace -azure_rtos.eww. Next, make the TX project the "active project" in the -IAR Embedded Workbench and select the "Make" button. You should observe -assembly and compilation of a series of ThreadX source files. This -results in the ThreadX run-time library file tx.a, which is needed by +azure_rtos.eww. Next, make the TX project the "active project" in the +IAR Embedded Workbench and select the "Make" button. You should observe +assembly and compilation of a series of ThreadX source files. This +results in the ThreadX run-time library file tx.a, which is needed by the application. @@ -20,47 +20,47 @@ The ThreadX demonstration is designed to execute under the IAR Windows-based Cortex-A8 simulator. Building the demonstration is easy; simply make the sample_threadx.ewp project -the "active project" in the IAR Embedded Workbench and select the +the "active project" in the IAR Embedded Workbench and select the "Make" button. -You should observe the compilation of sample_threadx.c (which is the demonstration +You should observe the compilation of sample_threadx.c (which is the demonstration application) and linking with tx.a. The resulting file sample_threadx.out is a binary file that can be downloaded and executed on IAR's Cortex-A8 simulator. 3. System Initialization -The entry point in ThreadX for the Cortex-A8 using IAR tools is at label -?cstartup. This is defined within the IAR compiler's startup code. In -addition, this is where all static and global preset C variable +The entry point in ThreadX for the Cortex-A8 using IAR tools is at label +?cstartup. This is defined within the IAR compiler's startup code. In +addition, this is where all static and global preset C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, and a periodic timer interrupt source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. By default, the vector area is defined at the top of cstartup.s, which is -a slightly modified from the base IAR file. +a slightly modified from the base IAR file. The _tx_initialize_low_level function inside of tx_initialize_low_level.s -also determines the first available address for use by the application, which -is supplied as the sole input parameter to your application definition function, -tx_application_define. To accomplish this, a section is created in -tx_initialize_low_level.s called FREE_MEM, which must be located after all +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all other RAM sections in memory. 4. Register Usage and Stack Frames -The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are -scratch registers for each function. All other registers used by a C function -must be preserved by the function. ThreadX takes advantage of this in -situations where a context switch happens as a result of making a ThreadX -service call (which is itself a C function). In such cases, the saved +The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are +scratch registers for each function. All other registers used by a C function +must be preserved by the function. ThreadX takes advantage of this in +situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -78,12 +78,12 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 5. Conditional Compilation Switches @@ -92,146 +92,146 @@ The following are conditional compilation options for building the ThreadX libra and application: - TX_ENABLE_FIQ_SUPPORT This assembler/compiler define enables + TX_ENABLE_FIQ_SUPPORT This assembler/compiler define enables FIQ interrupt handling support in the ThreadX assembly files. If used, it should be used on all assembly files and the generic C source of - ThreadX should be compiled with + ThreadX should be compiled with TX_ENABLE_FIQ_SUPPORT defined as well. TX_ENABLE_IRQ_NESTING This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. TX_ENABLE_FIQ_NESTING This assembler define enables FIQ - nested support. If FIQ nested + nested support. If FIQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. In addition, IRQ nesting should also be enabled. TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - TX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. TX_THUMB Defined, this option enables the BX LR calling return sequence @@ -245,29 +245,29 @@ and application: 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the ThreadX library -project to enable various compiler optimizations. +project to enable various compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A8 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-A8 vectors start at address zero. The demonstration system startup -cstartup.s file contains the vectors and is loaded at address zero. -On actual hardware platforms, this area might have to be copied to address 0. +cstartup.s file contains the vectors and is loaded at address zero. +On actual hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs @@ -278,12 +278,12 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.s: PUBLIC __tx_irq_handler - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -291,7 +291,7 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -304,7 +304,7 @@ __tx_irq_processing_return 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.s: @@ -315,12 +315,12 @@ __tx_example_vectored_irq_handler ; /* Jump to context save to save system context. */ STMDB sp!, {r0-r3} ; Save some scratch registers MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers BL _tx_thread_vectored_context_save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -337,24 +337,24 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.s. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables -nesting by disabling IRQ interrupts and switching back to IRQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: RSEG .text:CODE:NOROOT(2) PUBLIC __tx_irq_handler RSEG .text:CODE:NOROOT(2) - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -362,15 +362,15 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ; BL _tx_thread_irq_nesting_start @@ -378,7 +378,7 @@ __tx_irq_processing_return ; /* Application ISR dispatch call goes here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ; BL _tx_thread_irq_nesting_end @@ -389,12 +389,12 @@ __tx_irq_processing_return 7.3 FIQ Interrupts -By default, Cortex-A8 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, Cortex-A8 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.s. @@ -403,7 +403,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.s. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.s: @@ -434,18 +434,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.s. When nested FIQ interrupts are no -longer required, calling the _tx_thread_fiq_nesting_end service disables -nesting by disabling FIQ interrupts and switching back to FIQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested FIQ interrupts are no +longer required, calling the _tx_thread_fiq_nesting_end service disables +nesting by disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -463,7 +463,7 @@ __tx_fiq_processing_return: ; interrupt, and all C scratch registers are available for use. */ ; ; /* Enable nested FIQ interrupts. NOTE: Since this service returns -; with FIQ interrupts enabled, all FIQ interrupt sources must be +; with FIQ interrupts enabled, all FIQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start ; @@ -479,22 +479,22 @@ __tx_fiq_processing_return: 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to _tx_timer_interrupt +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. 9. Thumb/Cortex-A8 Mixed Mode -By default, ThreadX is setup for running in Cortex-A8 32-bit mode. This is -also true for the demonstration system. It is possible to build any +By default, ThreadX is setup for running in Cortex-A8 32-bit mode. This is +also true for the demonstration system. It is possible to build any ThreadX file and/or the application in Thumb mode. The only exception -to this is the file tx_thread_shell_entry.c. This file must always be -built in 32-bit mode. In addition, if any Thumb code is used the entire +to this is the file tx_thread_shell_entry.c. This file must always be +built in 32-bit mode. In addition, if any Thumb code is used the entire ThreadX assembly source should be built with TX_THUMB defined. @@ -506,14 +506,14 @@ should have the following line added (if not already in place): initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application -The project options "General Options -> Library Configuration" should also have the +The project options "General Options -> Library Configuration" should also have the "Enable thread support in library" box selected. 11. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); diff --git a/ports/cortex_a8/iar/src/tx_iar.c b/ports/cortex_a8/iar/src/tx_iar.c index 158738ea..238b485e 100644 --- a/ports/cortex_a8/iar/src/tx_iar.c +++ b/ports/cortex_a8/iar/src/tx_iar.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** IAR Multithreaded Library Support */ /** */ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports/cortex_a8/iar/src/tx_thread_context_restore.s b/ports/cortex_a8/iar/src/tx_thread_context_restore.s index b189af01..fb356284 100644 --- a/ports/cortex_a8/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_a8/iar/src/tx_thread_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,7 +36,7 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask THUMB_MASK DEFINE 0x20 ; Thumb bit mask SVC_MODE_BITS DEFINE 0x13 ; SVC mode value @@ -51,47 +51,38 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore Cortex-A8/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-A8/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -121,13 +112,13 @@ _tx_thread_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3, #0] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3, #0] ; Store the counter + STR r2, [r3, #0] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -193,7 +184,7 @@ __tx_thread_preempt_restore LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer - + #ifdef __ARMVFP__ LDR r2, [r0, #144] ; Pickup the VFP enabled flag CMP r2, #0 ; Is the VFP enabled? diff --git a/ports/cortex_a8/iar/src/tx_thread_context_save.s b/ports/cortex_a8/iar/src/tx_thread_context_save.s index cf9c22eb..98f88283 100644 --- a/ports/cortex_a8/iar/src/tx_thread_context_save.s +++ b/ports/cortex_a8/iar/src/tx_thread_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -43,46 +43,37 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled EXTERN _tx_execution_isr_enter ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save Cortex-A8/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-A8/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -99,7 +90,7 @@ _tx_thread_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt CPSR @@ -119,7 +110,7 @@ _tx_thread_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -135,7 +126,7 @@ _tx_thread_context_save POP {lr} ; Recover ISR lr #endif - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; __tx_thread_not_nested_save ; } @@ -149,13 +140,13 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} ; Store other registers ; ; /* Save the current stack pointer in the thread's control block. */ @@ -175,7 +166,7 @@ __tx_thread_not_nested_save POP {lr} ; Recover ISR lr #endif - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ; else @@ -185,7 +176,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit @@ -200,7 +191,7 @@ __tx_thread_idle_system_save #endif ADD sp, sp, #16 ; Recover saved registers - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ;} diff --git a/ports/cortex_a8/iar/src/tx_thread_fiq_context_restore.s b/ports/cortex_a8/iar/src/tx_thread_fiq_context_restore.s index 723d0ba5..091a5551 100644 --- a/ports/cortex_a8/iar/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_a8/iar/src/tx_thread_fiq_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -37,7 +37,7 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask THUMB_MASK DEFINE 0x20 ; Thumb bit mask IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits SVC_MODE_BITS DEFINE 0x13 ; SVC mode value @@ -52,47 +52,38 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value EXTERN _tx_execution_isr_exit ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_restore Cortex-A8/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore Cortex-A8/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the fiq interrupt context when processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* FIQ ISR Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) @@ -122,13 +113,13 @@ _tx_thread_fiq_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3] ; Store the counter + STR r2, [r3] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -172,7 +163,7 @@ __tx_thread_fiq_no_preempt_restore ; /* Restore interrupted thread or ISR. */ ; ; /* Pickup the saved stack pointer. */ -; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; ; ; /* Recover the saved context and return to the point of interrupt. */ ; @@ -232,7 +223,7 @@ _tx_skip_irq_vfp_save: BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it ; ; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; -; _tx_timer_time_slice = 0; +; _tx_timer_time_slice = 0; ; STR r2, [r0, #24] ; Save thread's time-slice MOV r2, #0 ; Clear value diff --git a/ports/cortex_a8/iar/src/tx_thread_fiq_context_save.s b/ports/cortex_a8/iar/src/tx_thread_fiq_context_save.s index a9fa3890..c9cdc190 100644 --- a/ports/cortex_a8/iar/src/tx_thread_fiq_context_save.s +++ b/ports/cortex_a8/iar/src/tx_thread_fiq_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,46 +36,37 @@ EXTERN _tx_execution_isr_enter ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_save Cortex-A8/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save Cortex-A8/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) @@ -92,7 +83,7 @@ _tx_thread_fiq_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state CMP r2, #0 ; Is this the first interrupt? @@ -107,7 +98,7 @@ _tx_thread_fiq_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -123,38 +114,38 @@ _tx_thread_fiq_context_save POP {lr} ; Recover ISR lr #endif - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; __tx_thread_fiq_not_nested_save -; } +; } ; ; /* Otherwise, not nested, check to see if a thread was running. */ ; else if (_tx_thread_current_ptr) -; { +; { ; ADD r2, r2, #1 ; Increment the interrupt counter STR r2, [r3] ; Store it back in the variable LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in -; ; scheduling loop - nothing needs saving! + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, lr} ; Store other registers, Note that we don't -; ; need to save sl and ip since FIQ has -; ; copies of these registers. Nested +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested ; ; interrupt processing does need to save ; ; these registers. ; ; /* Save the current stack pointer in the thread's control block. */ -; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; ; ; /* Switch to the system stack. */ -; sp = _tx_thread_system_stack_ptr; +; sp = _tx_thread_system_stack_ptr; ; MOV r10, #0 ; Clear stack limit @@ -167,7 +158,7 @@ __tx_thread_fiq_not_nested_save POP {lr} ; Recover ISR lr #endif - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } ; else @@ -187,18 +178,18 @@ __tx_thread_fiq_idle_system_save #endif ; ; /* Not much to do here, save the current SPSR and LR for possible -; use in IRQ interrupted in idle system conditions, and return to +; use in IRQ interrupted in idle system conditions, and return to ; FIQ interrupt processing. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, lr} ; Store other registers that will get used -; ; or stripped off the stack in context -; ; restore - B __tx_fiq_processing_return ; Continue FIQ processing +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } -;} +;} ; ; END diff --git a/ports/cortex_a8/iar/src/tx_thread_fiq_nesting_end.s b/ports/cortex_a8/iar/src/tx_thread_fiq_nesting_end.s index ea0855c5..980a803e 100644 --- a/ports/cortex_a8/iar/src/tx_thread_fiq_nesting_end.s +++ b/ports/cortex_a8/iar/src/tx_thread_fiq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,55 +34,49 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_end Cortex-A8/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end Cortex-A8/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ -;/* processing from system mode back to FIQ mode prior to the ISR */ -;/* calling _tx_thread_fiq_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s79). */ -;/* */ -;/* This function returns with FIQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/cortex_a8/iar/src/tx_thread_fiq_nesting_start.s b/ports/cortex_a8/iar/src/tx_thread_fiq_nesting_start.s index 76fe6bb5..8ec71833 100644 --- a/ports/cortex_a8/iar/src/tx_thread_fiq_nesting_start.s +++ b/ports/cortex_a8/iar/src/tx_thread_fiq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ MODE_MASK DEFINE 0x1F ; Mode mask SYS_MODE_BITS DEFINE 0x1F ; System mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_start Cortex-A8/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start Cortex-A8/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ -;/* processing to the system mode so nested FIQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s79). */ -;/* */ -;/* This function returns with FIQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_a8/iar/src/tx_thread_interrupt_control.s b/ports/cortex_a8/iar/src/tx_thread_interrupt_control.s index c1a42e43..a8c64050 100644 --- a/ports/cortex_a8/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_a8/iar/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,42 +35,36 @@ INT_MASK DEFINE 0x80 ; Interrupt bit mask #endif ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control Cortex-A8/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-A8/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a8/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_a8/iar/src/tx_thread_interrupt_disable.s index 15f9c425..5dbf7181 100644 --- a/ports/cortex_a8/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_a8/iar/src/tx_thread_interrupt_disable.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,41 +36,35 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable Cortex-A8/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-A8/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_a8/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_a8/iar/src/tx_thread_interrupt_restore.s index 90fc68e9..3d40ceef 100644 --- a/ports/cortex_a8/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_a8/iar/src/tx_thread_interrupt_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -28,42 +28,36 @@ ;#include "tx_thread.h" ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore Cortex-A8/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-A8/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function is responsible for restoring interrupts to the state */ ;/* returned by a previous _tx_thread_interrupt_disable call. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;void _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a8/iar/src/tx_thread_irq_nesting_end.s b/ports/cortex_a8/iar/src/tx_thread_irq_nesting_end.s index b0c927b2..de93f738 100644 --- a/ports/cortex_a8/iar/src/tx_thread_irq_nesting_end.s +++ b/ports/cortex_a8/iar/src/tx_thread_irq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,55 +35,49 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_end Cortex-A8/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-A8/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -;/* processing from system mode back to IRQ mode prior to the ISR */ -;/* calling _tx_thread_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s79). */ -;/* */ -;/* This function returns with IRQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_a8/iar/src/tx_thread_irq_nesting_start.s b/ports/cortex_a8/iar/src/tx_thread_irq_nesting_start.s index 0b9e4a77..2a327a17 100644 --- a/ports/cortex_a8/iar/src/tx_thread_irq_nesting_start.s +++ b/ports/cortex_a8/iar/src/tx_thread_irq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ MODE_MASK DEFINE 0x1F ; Mode mask SYS_MODE_BITS DEFINE 0x1F ; System mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_start Cortex-A8/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-A8/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_context_save has been called and switches the IRQ */ -;/* processing to the system mode so nested IRQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s79). */ -;/* */ -;/* This function returns with IRQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_a8/iar/src/tx_thread_schedule.s b/ports/cortex_a8/iar/src/tx_thread_schedule.s index c7a4f3f8..4044a81f 100644 --- a/ports/cortex_a8/iar/src/tx_thread_schedule.s +++ b/ports/cortex_a8/iar/src/tx_thread_schedule.s @@ -1,19 +1,19 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors -; * +; * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -44,48 +44,39 @@ ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule Cortex-A8/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-A8/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -115,7 +106,7 @@ __tx_thread_schedule_loop ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Lockout interrupts and ; transfer control to it. */ ; @@ -124,7 +115,7 @@ __tx_thread_schedule_loop ; /* Setup the current thread pointer. */ ; _tx_thread_current_ptr = _tx_thread_execute_ptr; ; - LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread STR r0, [r1, #0] ; Setup current thread pointer ; ; /* Increment the run count for this thread. */ @@ -138,7 +129,7 @@ __tx_thread_schedule_loop ; /* Setup time-slice, if present. */ ; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; ; - LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice ; variable LDR sp, [r0, #8] ; Switch stack pointers STR r3, [r2, #0] ; Setup time-slice @@ -199,7 +190,7 @@ _tx_skip_solicited_vfp_restore: #ifdef __ARMVFP__ PUBLIC tx_thread_vfp_enable CODE32 -tx_thread_vfp_enable??rA +tx_thread_vfp_enable??rA tx_thread_vfp_enable MRS r2, CPSR ; Pickup the CPSR #ifdef TX_ENABLE_FIQ_SUPPORT @@ -219,7 +210,7 @@ __tx_no_thread_to_enable: PUBLIC tx_thread_vfp_disable CODE32 -tx_thread_vfp_disable??rA +tx_thread_vfp_disable??rA tx_thread_vfp_disable MRS r2, CPSR ; Pickup the CPSR #ifdef TX_ENABLE_FIQ_SUPPORT diff --git a/ports/cortex_a8/iar/src/tx_thread_stack_build.s b/ports/cortex_a8/iar/src/tx_thread_stack_build.s index 962f7813..ed90c4a3 100644 --- a/ports/cortex_a8/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_a8/iar/src/tx_thread_stack_build.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -37,58 +37,52 @@ CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints en #endif ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build Cortex-A8/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-A8/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function builds a stack frame on the supplied thread's stack. */ ;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ ;/* thread_ptr Pointer to thread control blk */ ;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) ;{ RSEG .text:CODE:NOROOT(2) PUBLIC _tx_thread_stack_build - + CODE32 _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-A8 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; a1 (r0) Initial value for a1 diff --git a/ports/cortex_a8/iar/src/tx_thread_system_return.s b/ports/cortex_a8/iar/src/tx_thread_system_return.s index 13e04f6c..42f5c9a3 100644 --- a/ports/cortex_a8/iar/src/tx_thread_system_return.s +++ b/ports/cortex_a8/iar/src/tx_thread_system_return.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -42,47 +42,38 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return Cortex-A8/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-A8/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -113,7 +104,7 @@ _tx_skip_solicited_vfp_save: MOV r0, #0 ; Build a solicited stack type MRS r1, CPSR ; Pickup the CPSR STMDB sp!, {r0-r1} ; Save type and CPSR -; +; ; /* Lockout interrupts. */ ; ORR r2, r1, #DISABLE_INTS ; Build disable interrupt CPSR diff --git a/ports/cortex_a8/iar/src/tx_thread_vectored_context_save.s b/ports/cortex_a8/iar/src/tx_thread_vectored_context_save.s index 2e1ac10c..0816576f 100644 --- a/ports/cortex_a8/iar/src/tx_thread_vectored_context_save.s +++ b/ports/cortex_a8/iar/src/tx_thread_vectored_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -41,46 +41,37 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled EXTERN _tx_execution_isr_enter ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_vectored_context_save Cortex-A8/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-A8/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) @@ -142,7 +133,7 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in ; scheduling loop - nothing needs saving! ; ; /* Note: Minimal context of interrupted thread is already saved. */ @@ -174,7 +165,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports/cortex_a8/iar/src/tx_timer_interrupt.s b/ports/cortex_a8/iar/src/tx_timer_interrupt.s index 49d4219b..03ca45db 100644 --- a/ports/cortex_a8/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_a8/iar/src/tx_timer_interrupt.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -43,46 +43,40 @@ ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt Cortex-A8/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-A8/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time-slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time-slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -108,7 +102,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CMP r2, #0 ; Is it non-active? BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing @@ -226,13 +220,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CMP r2, #0 ; See if the flag is set BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing ; diff --git a/ports/cortex_a9/ac5/example_build/sample_threadx.c b/ports/cortex_a9/ac5/example_build/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports/cortex_a9/ac5/example_build/sample_threadx.c +++ b/ports/cortex_a9/ac5/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_a9/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_a9/ac5/example_build/tx_initialize_low_level.s index a15994e1..c9b06bd1 100644 --- a/ports/cortex_a9/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_a9/ac5/example_build/tx_initialize_low_level.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -110,45 +110,39 @@ Reset_Vector ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -199,7 +193,7 @@ _tx_initialize_low_level ; _tx_thread_system_stack_ptr = (VOID_PTR) (sp); ; LDR r1, =_tx_thread_system_stack_ptr ; Pickup address of system stack ptr - LDR r0, [r1, #0] ; Pickup system stack + LDR r0, [r1, #0] ; Pickup system stack ADD r0, r0, #4 ; Increment to next free word ; ; /* Save the first available memory address. */ @@ -221,7 +215,7 @@ _tx_initialize_low_level ; ; ;/* Define initial heap/stack routine for the ARM RealView (and ADS) startup code. This -; routine will set the initial stack to use the ThreadX IRQ & FIQ & +; routine will set the initial stack to use the ThreadX IRQ & FIQ & ; (optionally SYS) stack areas. */ ; EXPORT __user_initial_stackheap @@ -273,7 +267,7 @@ __tx_reserved_handler ; ; EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -281,21 +275,21 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; ; BL _tx_timer_interrupt ; Timer interrupt handler _tx_not_timer_interrupt ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ IF :DEF:TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -305,7 +299,7 @@ _tx_not_timer_interrupt ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ IF :DEF:TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -321,28 +315,28 @@ _tx_not_timer_interrupt __tx_example_vectored_irq_handler ; ; -; /* Save initial context and call context save to prepare for +; /* Save initial context and call context save to prepare for ; vectored ISR execution. */ ; ; STMDB sp!, {r0-r3} ; Save some scratch registers ; MRS r0, SPSR ; Pickup saved SPSR -; SUB lr, lr, #4 ; Adjust point of interrupt +; SUB lr, lr, #4 ; Adjust point of interrupt ; STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers ; BL _tx_thread_vectored_context_save ; Vectored context save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ; IF :DEF:TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_start @@ -351,7 +345,7 @@ __tx_example_vectored_irq_handler ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ; IF :DEF:TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_end @@ -373,11 +367,11 @@ __tx_fiq_processing_return ; /* At this point execution is still in the FIQ mode. The CPSR, point of ; interrupt, and all C scratch registers are available for use. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start ; from FIQ mode with interrupts disabled. This routine switches to the -; system mode and returns with FIQ interrupts enabled. +; system mode and returns with FIQ interrupts enabled. ; -; NOTE: It is very important to ensure all FIQ interrupts are cleared +; NOTE: It is very important to ensure all FIQ interrupts are cleared ; prior to enabling nested FIQ interrupts. */ IF :DEF:TX_ENABLE_FIQ_NESTING BL _tx_thread_fiq_nesting_start diff --git a/ports/cortex_a9/ac5/inc/tx_port.h b/ports/cortex_a9/ac5/inc/tx_port.h index 74ed6e00..0c145156 100644 --- a/ports/cortex_a9/ac5/inc/tx_port.h +++ b/ports/cortex_a9/ac5/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Cortex-A9/AC5 */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A9/AC5 */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -75,7 +67,7 @@ #include -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -111,12 +103,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -126,8 +118,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -174,7 +166,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -186,13 +178,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -206,11 +198,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -218,8 +210,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -246,21 +238,21 @@ typedef unsigned short USHORT; #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef __thumb - + #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (ULONG) __clz((unsigned int) m); \ - b = 31 - b; + b = 31 - b; #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -280,7 +272,7 @@ typedef unsigned short USHORT; { \ __enable_irq(); \ __enable_fiq(); \ - } + } #else @@ -289,7 +281,7 @@ typedef unsigned short USHORT; #define TX_RESTORE if (!interrupt_save_disabled) \ { \ __enable_irq(); \ - } + } #endif #else @@ -325,8 +317,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-A9/AC5 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A9/AC5 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a9/ac5/readme_threadx.txt b/ports/cortex_a9/ac5/readme_threadx.txt index 56cff19c..b29a95e2 100644 --- a/ports/cortex_a9/ac5/readme_threadx.txt +++ b/ports/cortex_a9/ac5/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for Cortex-A9 + Microsoft's Azure RTOS ThreadX for Cortex-A9 Thumb & 32-bit Mode @@ -6,21 +6,21 @@ 1. Building the ThreadX run-time Library -First make sure you are in the "example_build" directory. Also, make sure that -you have setup your path and other environment variables necessary for the ARM -AC5 development environment. At this point you may run the build_threadx.bat -batch file. This will build the ThreadX run-time environment in the -"example_build" directory. +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the ARM +AC5 development environment. At this point you may run the build_threadx.bat +batch file. This will build the ThreadX run-time environment in the +"example_build" directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. 1.1 Building with Project Files -The ThreadX library can also be built via project files. Simply open -the tx.mcp file with project builder and select make. This will place +The ThreadX library can also be built via project files. Simply open +the tx.mcp file with project builder and select make. This will place the tx.a library file into the Debug sub-directory. @@ -29,45 +29,45 @@ the tx.a library file into the Debug sub-directory. The ThreadX demonstration is designed to execute under the ARM Windows-based simulator. -Building the demonstration is easy; simply execute the build_threadx_demo.bat -batch file while inside the "example_build" directory. +Building the demonstration is easy; simply execute the build_threadx_demo.bat +batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with tx.a. The resulting file sample_threadx.axf +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.axf is a binary file that can be downloaded and executed on the ARM simulator. 2.0.1 Building with Project Files -The ThreadX demonstration can also be built via project files. Simply open -the sample_threadx.mcp file with project builder and select make. This will place +The ThreadX demonstration can also be built via project files. Simply open +the sample_threadx.mcp file with project builder and select make. This will place the sample_threadx.axf output image into the Debug sub-directory. 3. System Initialization -The entry point in ThreadX for the Cortex-A9 using AC5 tools is at label -__main. This is defined within the AC5 compiler's startup code. In -addition, this is where all static and global pre-set C variable +The entry point in ThreadX for the Cortex-A9 using AC5 tools is at label +__main. This is defined within the AC5 compiler's startup code. In +addition, this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. By default, the vector area is defined to be located in the Init area, -which is defined at the top of tx_initialize_low_level.s. This area is typically -located at 0. In situations where this is impossible, the vectors at the beginning +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. By default, the vector area is defined to be located in the Init area, +which is defined at the top of tx_initialize_low_level.s. This area is typically +located at 0. In situations where this is impossible, the vectors at the beginning of the Init area should be copied to address 0. This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 4. Assembler / Compiler Switches -The following are compiler switches used in building the demonstration +The following are compiler switches used in building the demonstration system: Compiler Switch Meaning @@ -83,10 +83,10 @@ Linker Switch Meaning -o demo.axf Specifies demo output file name --elf Specifies elf output file format --ro Specifies that Read-Only memory starts at address 0 - --first tx_initialize_low_level.o(Init) + --first tx_initialize_low_level.o(Init) Specifies that the first area loaded is Init --remove Remove unused areas - --list Specifies map file name + --list Specifies map file name --symbols Specifies symbols for map file --map Creates a map file @@ -97,161 +97,161 @@ Application Defines ThreadX assembly files. If used, it should be used on all assembly files and the generic C source of - ThreadX should be compiled with + ThreadX should be compiled with TX_ENABLE_FIQ_SUPPORT defined as well. --PD "TX_ENABLE_IRQ_NESTING SETL {TRUE}" This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. --PD "TX_ENABLE_FIQ_NESTING SETL {TRUE}" This assembler define enables FIQ - nested support. If FIQ nested + nested support. If FIQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. In addition, IRQ nesting should also be enabled. -DTX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ interrupt handling in the ThreadX - generic C source. This define + generic C source. This define should also be used in conjunction with the corresponding assembler - define. + define. -DTX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - -DTX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + -DTX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - -DTX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + -DTX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - -DTX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + -DTX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - -DTX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + -DTX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - -DTX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + -DTX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - -DTX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + -DTX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - -DTX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + -DTX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - -DTX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + -DTX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - -DTX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + -DTX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - -DTX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + -DTX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - -DTX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + -DTX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - -DTX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + -DTX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - -DTX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + -DTX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - -DTX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + -DTX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - -DTX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + -DTX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - -DTX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + -DTX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - -DTX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + -DTX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - -DTX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + -DTX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - -DTX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + -DTX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. -DTX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - -DTX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + -DTX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - -DTX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + -DTX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. 5. Register Usage and Stack Frames -The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -269,39 +269,39 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make it run faster, you can change the build_threadx.bat file to -remove the -g option and enable all compiler optimizations. +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A9 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-A9 vectors start at address zero. The demonstration system startup -Init area contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +Init area contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs @@ -312,12 +312,12 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.s: EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -325,7 +325,7 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -338,7 +338,7 @@ __tx_irq_processing_return 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.s: EXPORT __tx_irq_example_handler @@ -348,12 +348,12 @@ __tx_irq_example_handler STMDB sp!, {r0-r3} ; Save some scratch registers MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers BL _tx_thread_vectored_context_save ; Call the vectored IRQ context save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -370,22 +370,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.s. When nested IRQ interrupts are no longer required, calling the _tx_thread_irq_nesting_end service disables nesting by disabling -IRQ interrupts and switching back to IRQ mode in preparation for the IRQ +IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -393,10 +393,10 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* Enable nested IRQ interrupts. NOTE: Since this service returns -; with IRQ interrupts enabled, all IRQ interrupt sources must be +; with IRQ interrupts enabled, all IRQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start -; +; ; /* Application ISR call(s) go here! */ ; ; /* Disable nested IRQ interrupts. The mode is switched back to @@ -409,12 +409,12 @@ __tx_irq_processing_return 7.3 FIQ Interrupts -By default, Cortex-A9 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, Cortex-A9 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.s. @@ -423,7 +423,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.s. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.s: @@ -451,18 +451,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.s. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -478,7 +478,7 @@ __tx_fiq_processing_return ; interrupt, and all C scratch registers are available for use. */ ; ; /* Enable nested FIQ interrupts. NOTE: Since this service returns -; with FIQ interrupts enabled, all FIQ interrupt sources must be +; with FIQ interrupts enabled, all FIQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start ; @@ -494,28 +494,28 @@ __tx_fiq_processing_return 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.s in the Integrator sub-directories. 9. Thumb/Cortex-A9 Mixed Mode -By default, ThreadX is setup for running in Cortex-A9 32-bit mode. This is -also true for the demonstration system. It is possible to build any -ThreadX file and/or the application in Thumb mode. If any Thumb code -is used the entire ThreadX source- both C and assembly - should be built +By default, ThreadX is setup for running in Cortex-A9 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. If any Thumb code +is used the entire ThreadX source- both C and assembly - should be built with the "-apcs /interwork" option. 10. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); diff --git a/ports/cortex_a9/ac5/src/tx_thread_context_restore.s b/ports/cortex_a9/ac5/src/tx_thread_context_restore.s index 49add8f8..147719a2 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_a9/ac5/src/tx_thread_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -54,44 +54,38 @@ SVC_MODE EQU 0x93 ; SVC mode ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -121,13 +115,13 @@ _tx_thread_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3, #0] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3, #0] ; Store the counter + STR r2, [r3, #0] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs diff --git a/ports/cortex_a9/ac5/src/tx_thread_context_save.s b/ports/cortex_a9/ac5/src/tx_thread_context_save.s index 2ccb6ba9..234277a5 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_context_save.s +++ b/ports/cortex_a9/ac5/src/tx_thread_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,43 +39,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -90,7 +84,7 @@ _tx_thread_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers IF :DEF:TX_ENABLE_FIQ_SUPPORT CPSID if ; Disable FIQ interrupts ENDIF @@ -108,7 +102,7 @@ _tx_thread_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -124,7 +118,7 @@ _tx_thread_context_save POP {lr} ; Recover ISR lr ENDIF - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; __tx_thread_not_nested_save ; } @@ -138,13 +132,13 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} ; Store other registers ; ; /* Save the current stack pointer in the thread's control block. */ @@ -164,7 +158,7 @@ __tx_thread_not_nested_save POP {lr} ; Recover ISR lr ENDIF - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ; else @@ -174,7 +168,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit @@ -189,7 +183,7 @@ __tx_thread_idle_system_save ENDIF ADD sp, sp, #16 ; Recover saved registers - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ;} diff --git a/ports/cortex_a9/ac5/src/tx_thread_fiq_context_restore.s b/ports/cortex_a9/ac5/src/tx_thread_fiq_context_restore.s index 3069b0de..5f75fa49 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_a9/ac5/src/tx_thread_fiq_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -32,7 +32,7 @@ ; SVC_MODE EQU 0xD3 ; SVC mode FIQ_MODE EQU 0xD1 ; FIQ mode -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; ; @@ -50,44 +50,38 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_restore Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the fiq interrupt context when processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* FIQ ISR Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) @@ -113,13 +107,13 @@ _tx_thread_fiq_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3] ; Store the counter + STR r2, [r3] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -163,7 +157,7 @@ __tx_thread_fiq_no_preempt_restore ; /* Restore interrupted thread or ISR. */ ; ; /* Pickup the saved stack pointer. */ -; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; ; ; /* Recover the saved context and return to the point of interrupt. */ ; @@ -208,7 +202,7 @@ _tx_skip_fiq_vfp_save MOV r3, #1 ; Build interrupt stack type STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR STR sp, [r0, #8] ; Save stack pointer in thread control - ; block + ; block ; ; /* Save the remaining time-slice and disable it. */ ; if (_tx_timer_time_slice) @@ -220,7 +214,7 @@ _tx_skip_fiq_vfp_save BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it ; ; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; -; _tx_timer_time_slice = 0; +; _tx_timer_time_slice = 0; ; STR r2, [r0, #24] ; Save thread's time-slice MOV r2, #0 ; Clear value diff --git a/ports/cortex_a9/ac5/src/tx_thread_fiq_context_save.s b/ports/cortex_a9/ac5/src/tx_thread_fiq_context_save.s index 7faeb3c8..ce4ac25f 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_fiq_context_save.s +++ b/ports/cortex_a9/ac5/src/tx_thread_fiq_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,43 +39,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_save Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) @@ -90,7 +84,7 @@ _tx_thread_fiq_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state CMP r2, #0 ; Is this the first interrupt? @@ -105,7 +99,7 @@ _tx_thread_fiq_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -121,38 +115,38 @@ _tx_thread_fiq_context_save POP {lr} ; Recover ISR lr ENDIF - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; __tx_thread_fiq_not_nested_save -; } +; } ; ; /* Otherwise, not nested, check to see if a thread was running. */ ; else if (_tx_thread_current_ptr) -; { +; { ; ADD r2, r2, #1 ; Increment the interrupt counter STR r2, [r3] ; Store it back in the variable LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in -; ; scheduling loop - nothing needs saving! + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, lr} ; Store other registers, Note that we don't -; ; need to save sl and ip since FIQ has -; ; copies of these registers. Nested +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested ; ; interrupt processing does need to save ; ; these registers. ; ; /* Save the current stack pointer in the thread's control block. */ -; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; ; ; /* Switch to the system stack. */ -; sp = _tx_thread_system_stack_ptr; +; sp = _tx_thread_system_stack_ptr; ; MOV r10, #0 ; Clear stack limit @@ -165,7 +159,7 @@ __tx_thread_fiq_not_nested_save POP {lr} ; Recover ISR lr ENDIF - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } ; else @@ -185,18 +179,18 @@ __tx_thread_fiq_idle_system_save ENDIF ; ; /* Not much to do here, save the current SPSR and LR for possible -; use in IRQ interrupted in idle system conditions, and return to +; use in IRQ interrupted in idle system conditions, and return to ; FIQ interrupt processing. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, lr} ; Store other registers that will get used -; ; or stripped off the stack in context -; ; restore - B __tx_fiq_processing_return ; Continue FIQ processing +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } -;} +;} ; END diff --git a/ports/cortex_a9/ac5/src/tx_thread_fiq_nesting_end.s b/ports/cortex_a9/ac5/src/tx_thread_fiq_nesting_end.s index 43ae1483..db3131d3 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_fiq_nesting_end.s +++ b/ports/cortex_a9/ac5/src/tx_thread_fiq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,56 +34,50 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_end Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ -;/* processing from system mode back to FIQ mode prior to the ISR */ -;/* calling _tx_thread_fiq_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with FIQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) @@ -94,7 +88,7 @@ _tx_thread_fiq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_c, r0 ; Disable interrupts - LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports/cortex_a9/ac5/src/tx_thread_fiq_nesting_start.s b/ports/cortex_a9/ac5/src/tx_thread_fiq_nesting_start.s index 876f19a5..d5bac9db 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_fiq_nesting_start.s +++ b/ports/cortex_a9/ac5/src/tx_thread_fiq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_start Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ -;/* processing to the system mode so nested FIQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with FIQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_a9/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_a9/ac5/src/tx_thread_interrupt_control.s index eb141f70..0a4caa71 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_interrupt_control.s +++ b/ports/cortex_a9/ac5/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,42 +36,36 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a9/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_a9/ac5/src/tx_thread_interrupt_disable.s index f3014ace..b17a2404 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_a9/ac5/src/tx_thread_interrupt_disable.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,41 +29,35 @@ ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(void) @@ -80,7 +74,7 @@ _tx_thread_interrupt_disable IF :DEF:TX_ENABLE_FIQ_SUPPORT CPSID if ; Disable IRQ and FIQ ELSE - CPSID i ; Disable IRQ + CPSID i ; Disable IRQ ENDIF IF {INTER} = {TRUE} diff --git a/ports/cortex_a9/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_a9/ac5/src/tx_thread_interrupt_restore.s index b00872b3..701a21cd 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_a9/ac5/src/tx_thread_interrupt_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,42 +29,36 @@ ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function is responsible for restoring interrupts to the state */ ;/* returned by a previous _tx_thread_interrupt_disable call. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a9/ac5/src/tx_thread_irq_nesting_end.s b/ports/cortex_a9/ac5/src/tx_thread_irq_nesting_end.s index 4ef900fa..76efaf8a 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_irq_nesting_end.s +++ b/ports/cortex_a9/ac5/src/tx_thread_irq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,56 +34,50 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_end Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -;/* processing from system mode back to IRQ mode prior to the ISR */ -;/* calling _tx_thread_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) @@ -94,7 +88,7 @@ _tx_thread_irq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_c, r0 ; Disable interrupts - LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports/cortex_a9/ac5/src/tx_thread_irq_nesting_start.s b/ports/cortex_a9/ac5/src/tx_thread_irq_nesting_start.s index 1f9dfc8d..0f2719d8 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_irq_nesting_start.s +++ b/ports/cortex_a9/ac5/src/tx_thread_irq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_start Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_context_save has been called and switches the IRQ */ -;/* processing to the system mode so nested IRQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_a9/ac5/src/tx_thread_schedule.s b/ports/cortex_a9/ac5/src/tx_thread_schedule.s index 2b986ee5..c03f7f2b 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_a9/ac5/src/tx_thread_schedule.s @@ -1,19 +1,19 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors -; * +; * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -41,45 +41,39 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -108,7 +102,7 @@ __tx_thread_schedule_loop ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Lockout interrupts and ; transfer control to it. */ ; @@ -121,7 +115,7 @@ __tx_thread_schedule_loop ; /* Setup the current thread pointer. */ ; _tx_thread_current_ptr = _tx_thread_execute_ptr; ; - LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread STR r0, [r1, #0] ; Setup current thread pointer ; ; /* Increment the run count for this thread. */ @@ -135,7 +129,7 @@ __tx_thread_schedule_loop ; /* Setup time-slice, if present. */ ; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; ; - LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice ; variable LDR sp, [r0, #8] ; Switch stack pointers STR r3, [r2, #0] ; Setup time-slice diff --git a/ports/cortex_a9/ac5/src/tx_thread_stack_build.s b/ports/cortex_a9/ac5/src/tx_thread_stack_build.s index f10d9769..eda5cb08 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_stack_build.s +++ b/ports/cortex_a9/ac5/src/tx_thread_stack_build.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -41,44 +41,38 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function builds a stack frame on the supplied thread's stack. */ ;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ ;/* thread_ptr Pointer to thread control blk */ ;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -86,10 +80,10 @@ THUMB_BIT EQU 0x20 ; Thumb-bit EXPORT _tx_thread_stack_build _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-A9 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; a1 (r0) Initial value for a1 diff --git a/ports/cortex_a9/ac5/src/tx_thread_system_return.s b/ports/cortex_a9/ac5/src/tx_thread_system_return.s index bc6f3087..0dee4ef3 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_system_return.s +++ b/ports/cortex_a9/ac5/src/tx_thread_system_return.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -33,50 +33,44 @@ IMPORT _tx_timer_time_slice IMPORT _tx_thread_schedule IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY - IMPORT _tx_execution_thread_exit + IMPORT _tx_execution_thread_exit ENDIF ; ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -104,7 +98,7 @@ _tx_skip_solicited_vfp_save MOV r0, #0 ; Build a solicited stack type MRS r1, CPSR ; Pickup the CPSR STMDB sp!, {r0-r1} ; Save type and CPSR -; +; ; /* Lockout interrupts. */ ; IF :DEF:TX_ENABLE_FIQ_SUPPORT diff --git a/ports/cortex_a9/ac5/src/tx_thread_vectored_context_save.s b/ports/cortex_a9/ac5/src/tx_thread_vectored_context_save.s index e2a5a8c4..eb71247a 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_vectored_context_save.s +++ b/ports/cortex_a9/ac5/src/tx_thread_vectored_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -38,43 +38,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_vectored_context_save Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) @@ -135,7 +129,7 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Note: Minimal context of interrupted thread is already saved. */ @@ -171,7 +165,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports/cortex_a9/ac5/src/tx_timer_interrupt.s b/ports/cortex_a9/ac5/src/tx_timer_interrupt.s index 05e9fdda..e88155cc 100644 --- a/ports/cortex_a9/ac5/src/tx_timer_interrupt.s +++ b/ports/cortex_a9/ac5/src/tx_timer_interrupt.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -44,46 +44,40 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -107,7 +101,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CMP r2, #0 ; Is it non-active? BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing @@ -225,13 +219,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CMP r2, #0 ; See if the flag is set BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing ; diff --git a/ports/cortex_a9/ac6/example_build/sample_threadx/.cproject b/ports/cortex_a9/ac6/example_build/sample_threadx/.cproject index 72d51c5b..9aa9b1e3 100644 --- a/ports/cortex_a9/ac6/example_build/sample_threadx/.cproject +++ b/ports/cortex_a9/ac6/example_build/sample_threadx/.cproject @@ -1,176 +1,176 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a9/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_a9/ac6/example_build/sample_threadx/sample_threadx.scat index d23881cd..66d0d95a 100644 --- a/ports/cortex_a9/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports/cortex_a9/ac6/example_build/sample_threadx/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports/cortex_a9/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_a9/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 083a57a7..76395459 100644 --- a/ports/cortex_a9/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_a9/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -91,14 +92,6 @@ $_tx_initialize_low_level: /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ .global _tx_initialize_low_level .type _tx_initialize_low_level,function diff --git a/ports/cortex_a9/ac6/example_build/tx/.cproject b/ports/cortex_a9/ac6/example_build/tx/.cproject index 52a6e44b..59f20612 100644 --- a/ports/cortex_a9/ac6/example_build/tx/.cproject +++ b/ports/cortex_a9/ac6/example_build/tx/.cproject @@ -1,146 +1,146 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_a9/ac6/inc/tx_port.h b/ports/cortex_a9/ac6/inc/tx_port.h index f9b96956..f0153046 100644 --- a/ports/cortex_a9/ac6/inc/tx_port.h +++ b/ports/cortex_a9/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,20 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Updated comments, removed */ -/* unneeded temp variable, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -320,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv7-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a9/ac6/readme_threadx.txt b/ports/cortex_a9/ac6/readme_threadx.txt index f8196fb5..84c154af 100644 --- a/ports/cortex_a9/ac6/readme_threadx.txt +++ b/ports/cortex_a9/ac6/readme_threadx.txt @@ -1,18 +1,18 @@ - Microsoft's Azure RTOS ThreadX for Cortex-A9 + Microsoft's Azure RTOS ThreadX for Cortex-A9 Using ARM Compiler 6 & DS 1. Import the ThreadX Projects -In order to build the ThreadX library and the ThreadX demonstration, first import -the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +In order to build the ThreadX library and the ThreadX demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) into your DS workspace. 2. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply right-click the Eclipse project -"tx" and then select the "Build Project" button. You should now observe the compilation +Building the ThreadX library is easy; simply right-click the Eclipse project +"tx" and then select the "Build Project" button. You should now observe the compilation and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. @@ -22,44 +22,44 @@ library file tx.a. The ThreadX demonstration is designed to execute under the DS debugger on the VE_Cortex-A9 Bare Metal simulator. -Building the demonstration is easy; simply right-click the Eclipse project -"sample_threadx" and then select the "Build Project" button. You should now observe -the compilation and assembly of the ThreadX demonstration. This project build produces -the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder +Building the demonstration is easy; simply right-click the Eclipse project +"sample_threadx" and then select the "Build Project" button. You should now observe +the compilation and assembly of the ThreadX demonstration. This project build produces +the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder in the Project Explorer window, right-click on the 'cortex-a9_tx.launch' file, click 'Debug As', and then click 'cortex-a9_tx' from the submenu. This will cause the -debugger to load the sample_threadx.axf ELF file and run to main. You are now ready +debugger to load the sample_threadx.axf ELF file and run to main. You are now ready to execute the ThreadX demonstration. 4. System Initialization -The entry point in ThreadX for the Cortex-A9 using ARM tools is at label -"Vectors". This is defined within startup.S in the sample_threadx project. In addition, -this is where all static and global pre-set C variable initialization processing +The entry point in ThreadX for the Cortex-A9 using ARM tools is at label +"Vectors". This is defined within startup.S in the sample_threadx project. In addition, +this is where all static and global pre-set C variable initialization processing takes place. -This is also where initialization of a periodic timer interrupt source should take +This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level defines the first available address -for use by the application, which is supplied as the sole input parameter +In addition, _tx_initialize_low_level defines the first available address +for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 5. Register Usage and Stack Frames -The AC6 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The AC6 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -77,52 +77,52 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A9 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-A9 vectors start at address zero. The demonstration system startup -reset.S file contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +reset.S file contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs -ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -130,7 +130,7 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -143,7 +143,7 @@ __tx_irq_processing_return: 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_example_handler @@ -153,12 +153,12 @@ __tx_irq_example_handler: STMDB sp!, {r0-r3} @ Save some scratch registers MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers BL _tx_thread_vectored_context_save @ Call the vectored IRQ context save @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -175,22 +175,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.S. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables -nesting by disabling IRQ interrupts and switching back to IRQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -198,10 +198,10 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* Enable nested IRQ interrupts. NOTE: Since this service returns -@ with IRQ interrupts enabled, all IRQ interrupt sources must be +@ with IRQ interrupts enabled, all IRQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start -@ +@ @ /* Application ISR call(s) go here! */ @ @ /* Disable nested IRQ interrupts. The mode is switched back to @@ -214,12 +214,12 @@ __tx_irq_processing_return: 7.3 FIQ Interrupts -By default, FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.S. @@ -228,7 +228,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.S. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.S: @@ -256,18 +256,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.S. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -283,7 +283,7 @@ __tx_fiq_processing_return: @ interrupt, and all C scratch registers are available for use. */ @ @ /* Enable nested FIQ interrupts. NOTE: Since this service returns -@ with FIQ interrupts enabled, all FIQ interrupt sources must be +@ with FIQ interrupts enabled, all FIQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start @ @@ -299,12 +299,12 @@ __tx_fiq_processing_return: 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer -interrupt source, these services are not functional but the remainder of +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of ThreadX will still run. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.S for the demonstration system. @@ -312,7 +312,7 @@ found in the file tx_initialize_low_level.S for the demonstration system. 9. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); diff --git a/ports/cortex_a9/ac6/src/tx_thread_context_restore.S b/ports/cortex_a9/ac6/src/tx_thread_context_restore.S index 6b4a561d..41b0b0d0 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a9/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,23 +80,6 @@ IRQ_MODE = 0x12 // IRQ mode /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_restore .type _tx_thread_context_restore,function diff --git a/ports/cortex_a9/ac6/src/tx_thread_context_save.S b/ports/cortex_a9/ac6/src/tx_thread_context_save.S index eff06283..d2d29d34 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a9/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,23 +72,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_save .type _tx_thread_context_save,function diff --git a/ports/cortex_a9/ac6/src/tx_thread_fiq_context_restore.S b/ports/cortex_a9/ac6/src/tx_thread_fiq_context_restore.S index d2fbebe1..921c322c 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a9/ac6/src/tx_thread_fiq_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -78,20 +79,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* FIQ ISR Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_restore .type _tx_thread_fiq_context_restore,function diff --git a/ports/cortex_a9/ac6/src/tx_thread_fiq_context_save.S b/ports/cortex_a9/ac6/src/tx_thread_fiq_context_save.S index 88472a3d..2f1a6c40 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a9/ac6/src/tx_thread_fiq_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_save .type _tx_thread_fiq_context_save,function diff --git a/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_end.S index fa3886b8..a7ce701e 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_start.S index dbed1cf2..4f095dde 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a9/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a9/ac6/src/tx_thread_interrupt_control.S index d1223cb8..a5bc47f7 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a9/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,20 +69,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a9/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a9/ac6/src/tx_thread_interrupt_disable.S index a87d1a06..d7b53bc2 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a9/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,20 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a9/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a9/ac6/src/tx_thread_interrupt_restore.S index 53ff2813..3c31e94b 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a9/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,20 +68,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_end.S index 18aebc7c..cc4db3a7 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_start.S index a2ffd35d..3635874d 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a9/ac6/src/tx_thread_schedule.S b/ports/cortex_a9/ac6/src/tx_thread_schedule.S index f46a339b..a74e2050 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a9/ac6/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,23 +82,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a9/ac6/src/tx_thread_stack_build.S b/ports/cortex_a9/ac6/src/tx_thread_stack_build.S index 3876225a..827554a7 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a9/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,20 +75,6 @@ CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ int /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a9/ac6/src/tx_thread_system_return.S b/ports/cortex_a9/ac6/src/tx_thread_system_return.S index 0eed478d..1a17446b 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a9/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,23 +69,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a9/ac6/src/tx_thread_vectored_context_save.S b/ports/cortex_a9/ac6/src/tx_thread_vectored_context_save.S index fe8a98e8..91653b75 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a9/ac6/src/tx_thread_vectored_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_vectored_context_save .type _tx_thread_vectored_context_save,function diff --git a/ports/cortex_a9/ac6/src/tx_timer_interrupt.S b/ports/cortex_a9/ac6/src/tx_timer_interrupt.S index cb0c1fa2..179ac894 100644 --- a/ports/cortex_a9/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a9/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -77,20 +78,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a9/ghs/example_build/tx_initialize_low_level.arm b/ports/cortex_a9/ghs/example_build/tx_initialize_low_level.arm index c0fe4cce..b19d5e00 100644 --- a/ports/cortex_a9/ghs/example_build/tx_initialize_low_level.arm +++ b/ports/cortex_a9/ghs/example_build/tx_initialize_low_level.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a9/ghs/inc/tx_el.h b/ports/cortex_a9/ghs/inc/tx_el.h index b8926921..72e5bbe3 100644 --- a/ports/cortex_a9/ghs/inc/tx_el.h +++ b/ports/cortex_a9/ghs/inc/tx_el.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,12 +37,6 @@ /* EventAnalyzer. It is assumed that tx_api.h and tx_port.h have */ /* already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_EL_H diff --git a/ports/cortex_a9/ghs/inc/tx_port.h b/ports/cortex_a9/ghs/inc/tx_port.h index ffdf1460..75e76900 100644 --- a/ports/cortex_a9/ghs/inc/tx_port.h +++ b/ports/cortex_a9/ghs/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -394,7 +386,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-A9/Green Hills Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A9/Green Hills Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a9/ghs/readme_threadx.txt b/ports/cortex_a9/ghs/readme_threadx.txt index db232e1f..b32d1003 100644 --- a/ports/cortex_a9/ghs/readme_threadx.txt +++ b/ports/cortex_a9/ghs/readme_threadx.txt @@ -1,19 +1,19 @@ - Microsoft's Azure RTOS ThreadX for Cortex-A9 + Microsoft's Azure RTOS ThreadX for Cortex-A9 Using the Green Hills Software Tools 1. Open the ThreadX Project Workspace -In order to build the ThreadX library and the ThreadX demonstration first load -the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the -"example_build" directory. +In order to build the ThreadX library and the ThreadX demonstration first load +the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the +"example_build" directory. 2. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply select the MULTI project file -tx.gpj and then select the build button. You should now observe the -compilation and assembly of the ThreadX library. This project build produces +Building the ThreadX library is easy; simply select the MULTI project file +tx.gpj and then select the build button. You should now observe the +compilation and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. @@ -21,55 +21,55 @@ the ThreadX library file tx.a. The ThreadX demonstration is designed to execute under the MULTI environment on the Green Hills Cortex-A9 simulator. The instructions that follow describe -how to get the ThreadX evaluation running under the MULTI Cortex-A9 simulation +how to get the ThreadX evaluation running under the MULTI Cortex-A9 simulation environment. -Building the demonstration is easy; simply select the MULTI project file -sample_threadx.gpj. At this point, select the "Project Build" button and observe -the compilation, assembly, and linkage of the ThreadX demonstration application. +Building the demonstration is easy; simply select the MULTI project file +sample_threadx.gpj. At this point, select the "Project Build" button and observe +the compilation, assembly, and linkage of the ThreadX demonstration application. -After the demonstration is built, invoke the MULTI ARM simulator by selecting -the simulator connection from within the sample_threadx.con connection file. -Once connected to the simulator, select the "Debug" button. You should now -observe the main function of sample_threadx.c. +After the demonstration is built, invoke the MULTI ARM simulator by selecting +the simulator connection from within the sample_threadx.con connection file. +Once connected to the simulator, select the "Debug" button. You should now +observe the main function of sample_threadx.c. At this point, you should setup a simulated timer interrupt for ThreadX by entering "timer 9999 irq" in the "target" window of the debugger. -You are now ready to execute the ThreadX demonstration system. Select -breakpoints and data watches to observe the execution of the sample_threadx.c +You are now ready to execute the ThreadX demonstration system. Select +breakpoints and data watches to observe the execution of the sample_threadx.c application. 4. EventAnalyzer Demonstration -To build a demonstration system that also logs events for the MULTI EventAnalyzer, -perform the same steps as the regular demo, except build the ThreadX library with -txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. -The resulting image will log all system events, which can then be displayed by the +To build a demonstration system that also logs events for the MULTI EventAnalyzer, +perform the same steps as the regular demo, except build the ThreadX library with +txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. +The resulting image will log all system events, which can then be displayed by the MULTI EventAnalyzer. 5. System Initialization -The system entry point using the Green Hills tools is at the label _start. -This is defined within the crt0.arm file supplied by Green Hills. In addition, -this is where all static and global preset C variable initialization +The system entry point using the Green Hills tools is at the label _start. +This is defined within the crt0.arm file supplied by Green Hills. In addition, +this is where all static and global preset C variable initialization processing is called from. After the Green Hills startup function returns, ThreadX initialization is called. The main initialization function is _tx_initialize_low_level and -is located in the file tx_initialize_low_level.arm. This function is responsible -for setting up various system data structures, interrupt vectors, and the +is located in the file tx_initialize_low_level.arm. This function is responsible +for setting up various system data structures, interrupt vectors, and the periodic timer interrupt source of ThreadX. -In addition, _tx_initialize_low_level determines where the first available +In addition, _tx_initialize_low_level determines where the first available RAM memory address is located. This address is supplied to tx_application_define. -By default, the first available RAM memory address is assumed to start at the -beginning of the ThreadX section .free_mem. If changes are made to the -sample_threadx.ld file, the .free_mem section should remain the last allocated -section in the main RAM area. The starting address of this section is passed +By default, the first available RAM memory address is assumed to start at the +beginning of the ThreadX section .free_mem. If changes are made to the +sample_threadx.ld file, the .free_mem section should remain the last allocated +section in the main RAM area. The starting address of this section is passed to tx_application_define. @@ -87,27 +87,27 @@ The following defines and their associated action are as follows: TX_ENABLE_FIQ_NESTING If defined, this brings in special FIQ interrupt nesting logic into the ThreadX library. This define should be applied - to the entire ThreadX library and the + to the entire ThreadX library and the define TX_ENABLE_FIQ_SUPPORT should also be defined. TX_ENABLE_FIQ_SUPPORT If defined, this brings in FIQ context save and restore logic necessary for applications to call ThreadX services from - FIQ interrupt handlers. This define - should be applied to the entire ThreadX + FIQ interrupt handlers. This define + should be applied to the entire ThreadX library. TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 4 in the "ThreadX User Guide" + Chapter 4 in the "ThreadX User Guide" for more details. TX_ENABLE_EVENT_LOGGING This define enables event logging for any or all of the ThreadX source code. If this - option is used anywhere, the tx_initialize_high_level.c + option is used anywhere, the tx_initialize_high_level.c file must be compiled with it as well, since this is where the event log is initialized. @@ -119,121 +119,121 @@ The following defines and their associated action are as follows: If this is enabled, run-time filtering logic is added to the event logging code. - TX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. 7. Register Usage and Stack Frames -The Green Hills compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) -are scratch registers for each function. All other registers used by a C -function must be preserved by the function. ThreadX takes advantage of this -in situations where a context switch happens as a result of making a ThreadX -service call (which is itself a C function). In such cases, the saved +The Green Hills compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) +are scratch registers for each function. All other registers used by a C +function must be preserved by the function. ThreadX takes advantage of this +in situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -251,40 +251,40 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 8. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make ThreadX run faster, you can change the tx.gpj project -to disable debug information and enable the desired optimizations. +to disable debug information and enable the desired optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined before tx_api.h is included. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. 9. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A9 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 9.1 Vector Area The Cortex-A9 vectors start at address zero. The demonstration system reset.arm -file contains the reset section (which contains all the ARM vectors) and is +file contains the reset section (which contains all the ARM vectors) and is typically loaded at address zero. On actual hardware platforms, this section -might have to be copied to address 0. +might have to be copied to address 0. 9.2 IRQ ISRs @@ -294,13 +294,13 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 9.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.arm: .globl __tx_irq_handler - .globl __tx_irq_processing_return + .globl __tx_irq_processing_return __tx_irq_handler: /* Jump to context save to save system context. */ @@ -308,7 +308,7 @@ __tx_irq_handler: __tx_irq_processing_return: /* At this point execution is still in the IRQ mode. The CPSR, point of - interrupt, and all C scratch registers are available for use. Note + interrupt, and all C scratch registers are available for use. Note that IRQ interrupts are still disabled upon return from the context save function. */ @@ -321,7 +321,7 @@ __tx_irq_processing_return: 9.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.arm: .globl __tx_irq_example_handler @@ -331,12 +331,12 @@ __tx_irq_example_handler: STMDB sp!, {r0-r3} # Save some scratch registers MRS r0, SPSR # Pickup saved SPSR - SUB lr, lr, #4 # Adjust point of interrupt + SUB lr, lr, #4 # Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} # Store other scratch registers BL _tx_thread_vectored_context_save # Call the vectored IRQ context save /* At this point execution is still in the IRQ mode. The CPSR, point of - interrupt, and all C scratch registers are available for use. Note + interrupt, and all C scratch registers are available for use. Note that IRQ interrupts are still disabled upon return from the context save function. */ @@ -353,22 +353,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.arm. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables nesting -by disabling IRQ interrupts and switching back to IRQ mode in preparation for +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.arm. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables nesting +by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in the +The following is an example of enabling IRQ nested interrupts in the typical IRQ handler: .globl __tx_irq_handler - .globl __tx_irq_processing_return + .globl __tx_irq_processing_return __tx_irq_handler: /* Jump to context save to save system context. */ @@ -376,10 +376,10 @@ __tx_irq_handler: __tx_irq_processing_return: /* Enable nested IRQ interrupts. NOTE: Since this service returns - with IRQ interrupts enabled, all IRQ interrupt sources must be + with IRQ interrupts enabled, all IRQ interrupt sources must be cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start - + /* Application ISR call(s) go here! */ /* Disable nested IRQ interrupts. The mode is switched back to @@ -392,9 +392,9 @@ __tx_irq_processing_return: 9.3 FIQ Interrupts -By default, Cortex-A9 FIQ interrupts are left completely enabled by ThreadX. -Of course, this means that the application is fully responsible for -saving/restoring any registers used in the FIQ ISR processing. In addition, +By default, Cortex-A9 FIQ interrupts are left completely enabled by ThreadX. +Of course, this means that the application is fully responsible for +saving/restoring any registers used in the FIQ ISR processing. In addition, no ThreadX service calls are allowed from the default FIQ ISRs. The default FIQ interrupt shell is located in tx_initialize_low_level.arm. @@ -403,7 +403,7 @@ FIQ interrupt shell is located in tx_initialize_low_level.arm. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.arm: @@ -431,18 +431,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.arm. When nested FIQ interrupts are no longer -required, calling the _tx_thread_fiq_nesting_end service disables nesting by -disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.arm. When nested FIQ interrupts are no longer +required, calling the _tx_thread_fiq_nesting_end service disables nesting by +disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -458,7 +458,7 @@ __tx_fiq_processing_return: interrupt, and all C scratch registers are available for use. */ /* Enable nested FIQ interrupts. NOTE: Since this service returns - with FIQ interrupts enabled, all FIQ interrupt sources must be + with FIQ interrupts enabled, all FIQ interrupt sources must be cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start @@ -475,29 +475,29 @@ __tx_fiq_processing_return: 10. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.arm. 11. Thumb/Cortex-A9 Mixed Mode -By default, ThreadX is setup for running in Cortex-A9 32-bit mode. This is -also true for the demonstration system. It is possible to build any +By default, ThreadX is setup for running in Cortex-A9 32-bit mode. This is +also true for the demonstration system. It is possible to build any ThreadX file and/or the application in Thumb mode. The only exception -to this is the file tx_thread_shell_entry.c. This file must always be +to this is the file tx_thread_shell_entry.c. This file must always be built in 32-bit mode. 12. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); @@ -520,7 +520,7 @@ information associated with this specific port of ThreadX: 04-02-2021 Release 6.1.6 changes: tx_port.h Updated macro definition -05/19/2020 Initial ThreadX version of Cortex-A9/Green Hills port. +05/19/2020 Initial ThreadX version of Cortex-A9/Green Hills port. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_a9/ghs/src/tx_el.c b/ports/cortex_a9/ghs/src/tx_el.c index 365622cd..b5d3b8b7 100644 --- a/ports/cortex_a9/ghs/src/tx_el.c +++ b/ports/cortex_a9/ghs/src/tx_el.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,12 +83,6 @@ UINT _tx_thread_interrupt_control(UINT new_posture); /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_el_initialize(VOID) { diff --git a/ports/cortex_a9/ghs/src/tx_thread_context_restore.arm b/ports/cortex_a9/ghs/src/tx_thread_context_restore.arm index d28b0066..5366e496 100644 --- a/ports/cortex_a9/ghs/src/tx_thread_context_restore.arm +++ b/ports/cortex_a9/ghs/src/tx_thread_context_restore.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a9/ghs/src/tx_thread_context_save.arm b/ports/cortex_a9/ghs/src/tx_thread_context_save.arm index 5930e4ce..304acf64 100644 --- a/ports/cortex_a9/ghs/src/tx_thread_context_save.arm +++ b/ports/cortex_a9/ghs/src/tx_thread_context_save.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a9/ghs/src/tx_thread_fiq_context_restore.arm b/ports/cortex_a9/ghs/src/tx_thread_fiq_context_restore.arm index a2abbcde..14cb3624 100644 --- a/ports/cortex_a9/ghs/src/tx_thread_fiq_context_restore.arm +++ b/ports/cortex_a9/ghs/src/tx_thread_fiq_context_restore.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a9/ghs/src/tx_thread_fiq_context_save.arm b/ports/cortex_a9/ghs/src/tx_thread_fiq_context_save.arm index c305529e..75298816 100644 --- a/ports/cortex_a9/ghs/src/tx_thread_fiq_context_save.arm +++ b/ports/cortex_a9/ghs/src/tx_thread_fiq_context_save.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a9/ghs/src/tx_thread_fiq_nesting_end.arm b/ports/cortex_a9/ghs/src/tx_thread_fiq_nesting_end.arm index c7b1e54a..c4f8b98c 100644 --- a/ports/cortex_a9/ghs/src/tx_thread_fiq_nesting_end.arm +++ b/ports/cortex_a9/ghs/src/tx_thread_fiq_nesting_end.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a9/ghs/src/tx_thread_fiq_nesting_start.arm b/ports/cortex_a9/ghs/src/tx_thread_fiq_nesting_start.arm index 26641c10..195899b4 100644 --- a/ports/cortex_a9/ghs/src/tx_thread_fiq_nesting_start.arm +++ b/ports/cortex_a9/ghs/src/tx_thread_fiq_nesting_start.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a9/ghs/src/tx_thread_interrupt_control.arm b/ports/cortex_a9/ghs/src/tx_thread_interrupt_control.arm index b517aa84..a3a629ef 100644 --- a/ports/cortex_a9/ghs/src/tx_thread_interrupt_control.arm +++ b/ports/cortex_a9/ghs/src/tx_thread_interrupt_control.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a9/ghs/src/tx_thread_interrupt_disable.arm b/ports/cortex_a9/ghs/src/tx_thread_interrupt_disable.arm index 863408dd..2016da56 100644 --- a/ports/cortex_a9/ghs/src/tx_thread_interrupt_disable.arm +++ b/ports/cortex_a9/ghs/src/tx_thread_interrupt_disable.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a9/ghs/src/tx_thread_interrupt_restore.arm b/ports/cortex_a9/ghs/src/tx_thread_interrupt_restore.arm index 89b7868d..3dd8866f 100644 --- a/ports/cortex_a9/ghs/src/tx_thread_interrupt_restore.arm +++ b/ports/cortex_a9/ghs/src/tx_thread_interrupt_restore.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a9/ghs/src/tx_thread_irq_nesting_end.arm b/ports/cortex_a9/ghs/src/tx_thread_irq_nesting_end.arm index 0ffd056e..17e98e41 100644 --- a/ports/cortex_a9/ghs/src/tx_thread_irq_nesting_end.arm +++ b/ports/cortex_a9/ghs/src/tx_thread_irq_nesting_end.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a9/ghs/src/tx_thread_irq_nesting_start.arm b/ports/cortex_a9/ghs/src/tx_thread_irq_nesting_start.arm index b287af00..570ffd77 100644 --- a/ports/cortex_a9/ghs/src/tx_thread_irq_nesting_start.arm +++ b/ports/cortex_a9/ghs/src/tx_thread_irq_nesting_start.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a9/ghs/src/tx_thread_schedule.arm b/ports/cortex_a9/ghs/src/tx_thread_schedule.arm index 4ff185d6..3ab6fee4 100644 --- a/ports/cortex_a9/ghs/src/tx_thread_schedule.arm +++ b/ports/cortex_a9/ghs/src/tx_thread_schedule.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a9/ghs/src/tx_thread_stack_build.arm b/ports/cortex_a9/ghs/src/tx_thread_stack_build.arm index a445c985..93739563 100644 --- a/ports/cortex_a9/ghs/src/tx_thread_stack_build.arm +++ b/ports/cortex_a9/ghs/src/tx_thread_stack_build.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a9/ghs/src/tx_thread_system_return.arm b/ports/cortex_a9/ghs/src/tx_thread_system_return.arm index 10d5413e..84240480 100644 --- a/ports/cortex_a9/ghs/src/tx_thread_system_return.arm +++ b/ports/cortex_a9/ghs/src/tx_thread_system_return.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a9/ghs/src/tx_thread_vectored_context_save.arm b/ports/cortex_a9/ghs/src/tx_thread_vectored_context_save.arm index c21bb410..d8d3a946 100644 --- a/ports/cortex_a9/ghs/src/tx_thread_vectored_context_save.arm +++ b/ports/cortex_a9/ghs/src/tx_thread_vectored_context_save.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a9/ghs/src/tx_timer_interrupt.arm b/ports/cortex_a9/ghs/src/tx_timer_interrupt.arm index ee5b1680..38f9906a 100644 --- a/ports/cortex_a9/ghs/src/tx_timer_interrupt.arm +++ b/ports/cortex_a9/ghs/src/tx_timer_interrupt.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a9/gnu/example_build/MP_GIC.S b/ports/cortex_a9/gnu/example_build/MP_GIC.S index d23bca23..f769bf9f 100644 --- a/ports/cortex_a9/gnu/example_build/MP_GIC.S +++ b/ports/cortex_a9/gnu/example_build/MP_GIC.S @@ -3,7 +3,7 @@ // // Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports/cortex_a9/gnu/example_build/MP_GIC.h b/ports/cortex_a9/gnu/example_build/MP_GIC.h index 1d047611..42a96c3d 100644 --- a/ports/cortex_a9/gnu/example_build/MP_GIC.h +++ b/ports/cortex_a9/gnu/example_build/MP_GIC.h @@ -4,7 +4,7 @@ // // Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports/cortex_a9/gnu/example_build/MP_PrivateTimer.S b/ports/cortex_a9/gnu/example_build/MP_PrivateTimer.S index a01fd0cc..bb29b8ff 100644 --- a/ports/cortex_a9/gnu/example_build/MP_PrivateTimer.S +++ b/ports/cortex_a9/gnu/example_build/MP_PrivateTimer.S @@ -93,7 +93,7 @@ get_private_timer_count: LDR r0, [r0, #0x604] // Read count register BX lr - + // ------------------------------------------------------------ // void clear_private_timer_irq(void) diff --git a/ports/cortex_a9/gnu/example_build/reset.S b/ports/cortex_a9/gnu/example_build/reset.S index 3ce9efb7..f2e0522b 100644 --- a/ports/cortex_a9/gnu/example_build/reset.S +++ b/ports/cortex_a9/gnu/example_build/reset.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_a9/gnu/example_build/sample_threadx.ld b/ports/cortex_a9/gnu/example_build/sample_threadx.ld index cb42c11c..d43e28f1 100644 --- a/ports/cortex_a9/gnu/example_build/sample_threadx.ld +++ b/ports/cortex_a9/gnu/example_build/sample_threadx.ld @@ -7,7 +7,7 @@ OUTPUT_ARCH(arm) SECTIONS { . = 0x00000000; - + .vectors : {reset.o(.text) } /* Read-only sections, merged into text segment: */ @@ -94,8 +94,8 @@ SECTIONS *(.gnu.linkonce.t*) *(.glue_7t) *(.glue_7) } =0 - .init : - { + .init : + { KEEP (*(.init)) } =0 _etext = .; @@ -120,7 +120,7 @@ SECTIONS .data1 : { *(.data1) } .eh_frame : { KEEP (*(.eh_frame)) } .gcc_except_table : { *(.gcc_except_table) } - .ctors : + .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is @@ -153,9 +153,9 @@ SECTIONS /* We want the small data sections together, so single-instruction offsets can access them all, and initialized data all before uninitialized, so we can shorten the on-disk segment size. */ - .sdata : + .sdata : { - *(.sdata) + *(.sdata) *(.sdata.*) *(.gnu.linkonce.s.*) } @@ -191,7 +191,7 @@ SECTIONS _stack_bottom = ABSOLUTE(.) ; - /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and + /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and SYS stack if nested interrupts are enabled. */ . = ALIGN(8) ; . += 4096 ; diff --git a/ports/cortex_a9/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_a9/gnu/example_build/tx_initialize_low_level.S index 7e218299..bf082474 100644 --- a/ports/cortex_a9/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_a9/gnu/example_build/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -100,17 +101,6 @@ $_tx_initialize_low_level: /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_initialize_low_level .type _tx_initialize_low_level,function @@ -183,7 +173,7 @@ _stack_error_loop: MOV r0, #0x1F BL setPriorityMask // Set priority mask (local) - // [EL] Change start - don't enable interrupts here! + // [EL] Change start - don't enable interrupts here! //CPSIE i // Clear CPSR I bit // [EL] Change end @@ -202,7 +192,7 @@ _stack_error_loop: MOV r1, #0x0 BL init_private_timer BL start_private_timer - + // // Enable receipt of SGI 0 // ------------------------ @@ -257,7 +247,7 @@ __tx_irq_processing_return: if nested IRQ interrupts are desired. Interrupts may be re-enabled over small code sequences where lr is saved before enabling interrupts and restored after interrupts are again disabled. */ - + PUSH {r4, r5} // Save some preserved registers (r5 is saved just for 8-byte alignment) BL readIntAck MOV r4, r0 diff --git a/ports/cortex_a9/gnu/example_build/v7.h b/ports/cortex_a9/gnu/example_build/v7.h index 5a08b43f..c18b945c 100644 --- a/ports/cortex_a9/gnu/example_build/v7.h +++ b/ports/cortex_a9/gnu/example_build/v7.h @@ -4,7 +4,7 @@ // // Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports/cortex_a9/gnu/example_build/v7.s b/ports/cortex_a9/gnu/example_build/v7.s index 82c9ab1e..9487ddde 100644 --- a/ports/cortex_a9/gnu/example_build/v7.s +++ b/ports/cortex_a9/gnu/example_build/v7.s @@ -3,7 +3,7 @@ // // Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ @@ -20,7 +20,7 @@ enableInterrupts: CPSIE i BX lr - + .global disableInterrupts .type disableInterrupts,function @@ -28,7 +28,7 @@ enableInterrupts: disableInterrupts: CPSID i BX lr - + // ------------------------------------------------------------ // Cache Maintenance @@ -44,7 +44,7 @@ enableCaches: MCR p15, 0, r0, c1, c0, 0 // Write System Control Register ISB BX lr - + .global disableCaches @@ -57,7 +57,7 @@ disableCaches: MCR p15, 0, r0, c1, c0, 0 // Write System Control Register ISB BX lr - + .global cleanDCache @@ -114,7 +114,7 @@ clean_dcache_finished: POP {r4-r12} BX lr - + .global cleanInvalidateDCache .type cleanInvalidateDCache,function @@ -170,7 +170,7 @@ clean_invalidate_dcache_finished: POP {r4-r12} BX lr - + .global invalidateCaches @@ -229,7 +229,7 @@ invalidate_caches_skip: invalidate_caches_finished: POP {r4-r12} BX lr - + .global invalidateCaches_IS @@ -284,7 +284,7 @@ invalidate_caches_is_skip: invalidate_caches_is_finished: POP {r4-r12} BX lr - + // ------------------------------------------------------------ // TLB @@ -297,7 +297,7 @@ invalidateUnifiedTLB: MOV r0, #0 MCR p15, 0, r0, c8, c7, 0 // TLBIALL - Invalidate entire unified TLB BX lr - + .global invalidateUnifiedTLB_IS .type invalidateUnifiedTLB_IS,function @@ -306,7 +306,7 @@ invalidateUnifiedTLB_IS: MOV r0, #1 MCR p15, 0, r0, c8, c3, 0 // TLBIALLIS - Invalidate entire unified TLB Inner Shareable BX lr - + // ------------------------------------------------------------ // Branch Prediction @@ -319,7 +319,7 @@ flushBranchTargetCache: MOV r0, #0 MCR p15, 0, r0, c7, c5, 6 // BPIALL - Invalidate entire branch predictor array BX lr - + .global flushBranchTargetCache_IS .type flushBranchTargetCache_IS,function @@ -328,7 +328,7 @@ flushBranchTargetCache_IS: MOV r0, #0 MCR p15, 0, r0, c7, c1, 6 // BPIALLIS - Invalidate entire branch predictor array Inner Shareable BX lr - + // ------------------------------------------------------------ // High Vecs @@ -343,7 +343,7 @@ enableHighVecs: MCR p15, 0, r0, c1, c0, 0 // Write Control Register ISB BX lr - + .global disableHighVecs .type disableHighVecs,function @@ -354,7 +354,7 @@ disableHighVecs: MCR p15, 0, r0, c1, c0, 0 // Write Control Register ISB BX lr - + // ------------------------------------------------------------ // Context ID @@ -366,7 +366,7 @@ disableHighVecs: getContextID: MRC p15, 0, r0, c13, c0, 1 // Read Context ID Register BX lr - + .global setContextID .type setContextID,function @@ -374,7 +374,7 @@ getContextID: setContextID: MCR p15, 0, r0, c13, c0, 1 // Write Context ID Register BX lr - + // ------------------------------------------------------------ // ID registers @@ -386,7 +386,7 @@ setContextID: getMIDR: MRC p15, 0, r0, c0, c0, 0 // Read Main ID Register (MIDR) BX lr - + .global getMPIDR .type getMPIDR,function @@ -394,7 +394,7 @@ getMIDR: getMPIDR: MRC p15, 0, r0, c0 ,c0, 5// Read Multiprocessor ID register (MPIDR) BX lr - + // ------------------------------------------------------------ // CP15 SMP related @@ -407,7 +407,7 @@ getMPIDR: getBaseAddr: MRC p15, 4, r0, c15, c0, 0 // Read peripheral base address BX lr - + // ------------------------------------------------------------ @@ -419,7 +419,7 @@ getCPUID: MRC p15, 0, r0, c0, c0, 5 // Read CPU ID register AND r0, r0, #0x03 // Mask off, leaving the CPU ID field BX lr - + // ------------------------------------------------------------ @@ -431,7 +431,7 @@ goToSleep: WFI // Go into standby B goToSleep // Catch in case of rogue events BX lr - + // ------------------------------------------------------------ @@ -451,7 +451,7 @@ joinSMP: ISB BX lr - + // ------------------------------------------------------------ @@ -469,7 +469,7 @@ leaveSMP: ISB BX lr - + // ------------------------------------------------------------ // End of v7.s diff --git a/ports/cortex_a9/gnu/inc/tx_port.h b/ports/cortex_a9/gnu/inc/tx_port.h index f9b96956..f0153046 100644 --- a/ports/cortex_a9/gnu/inc/tx_port.h +++ b/ports/cortex_a9/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,20 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Updated comments, removed */ -/* unneeded temp variable, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -320,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv7-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a9/gnu/readme_threadx.txt b/ports/cortex_a9/gnu/readme_threadx.txt index d4d7627a..eb183c37 100644 --- a/ports/cortex_a9/gnu/readme_threadx.txt +++ b/ports/cortex_a9/gnu/readme_threadx.txt @@ -1,55 +1,55 @@ - Microsoft's Azure RTOS ThreadX for Cortex-A9 + Microsoft's Azure RTOS ThreadX for Cortex-A9 Using the GNU Tools 1. Building the ThreadX run-time Library -First make sure you are in the "example_build" directory. Also, make sure that -you have setup your path and other environment variables necessary for the GNU -development environment. +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the GNU +development environment. -At this point you may run the build_threadx.bat batch file. This will build the -ThreadX run-time environment in the "example_build" directory. +At this point you may run the build_threadx.bat batch file. This will build the +ThreadX run-time environment in the "example_build" directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. 2. Demonstration System -Building the demonstration is easy; simply execute the build_threadx_sample.bat -batch file while inside the "example_build" directory. +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with TX.A. The resulting file DEMO is a binary file +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with TX.A. The resulting file DEMO is a binary file that can be downloaded and executed. 3. System Initialization -The entry point in ThreadX for the Cortex-A9 using GNU tools is at label _start. +The entry point in ThreadX for the Cortex-A9 using GNU tools is at label _start. This is defined within the modified version of the GNU startup code - crt0.S. -The ThreadX tx_initialize_low_level.S file is responsible for setting up various -system data structures, the interrupt vectors, and a periodic timer interrupt source. -By default, the vector area is defined to be located at the "__vectors" label, -which is defined in reset.S. This area is typically located at 0. In situations -where this is impossible, the vectors at the "__vectors" label should be copied +The ThreadX tx_initialize_low_level.S file is responsible for setting up various +system data structures, the interrupt vectors, and a periodic timer interrupt source. +By default, the vector area is defined to be located at the "__vectors" label, +which is defined in reset.S. This area is typically located at 0. In situations +where this is impossible, the vectors at the "__vectors" label should be copied to address 0. -This is also where initialization of a periodic timer interrupt source should take +This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level defines the first available address -for use by the application, which is supplied as the sole input parameter +In addition, _tx_initialize_low_level defines the first available address +for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 4. Assembler / Compiler Switches -The following are compiler switches used in building the demonstration +The following are compiler switches used in building the demonstration system: Compiler/Assembler Meaning @@ -73,164 +73,164 @@ Application Defines ( -D option) ThreadX assembly files. If used, it should be used on all assembly files and the generic C source of - ThreadX should be compiled with + ThreadX should be compiled with TX_ENABLE_FIQ_SUPPORT defined as well. TX_ENABLE_IRQ_NESTING This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.S. TX_ENABLE_FIQ_NESTING This assembler define enables FIQ - nested support. If FIQ nested + nested support. If FIQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.S. In addition, IRQ nesting should also be enabled. TX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ interrupt handling in the ThreadX - generic C source. This define + generic C source. This define should also be used in conjunction with the corresponding assembler - define. + define. TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - TX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. 5. Register Usage and Stack Frames -The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -248,52 +248,52 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A9 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-A9 vectors start at address zero. The demonstration system startup -reset.S file contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +reset.S file contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs -ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -301,7 +301,7 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -314,7 +314,7 @@ __tx_irq_processing_return: 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_example_handler @@ -324,12 +324,12 @@ __tx_irq_example_handler: STMDB sp!, {r0-r3} @ Save some scratch registers MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers BL _tx_thread_vectored_context_save @ Call the vectored IRQ context save @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -346,22 +346,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.S. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables -nesting by disabling IRQ interrupts and switching back to IRQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -369,10 +369,10 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* Enable nested IRQ interrupts. NOTE: Since this service returns -@ with IRQ interrupts enabled, all IRQ interrupt sources must be +@ with IRQ interrupts enabled, all IRQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start -@ +@ @ /* Application ISR call(s) go here! */ @ @ /* Disable nested IRQ interrupts. The mode is switched back to @@ -385,12 +385,12 @@ __tx_irq_processing_return: 7.3 FIQ Interrupts -By default, FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.S. @@ -399,7 +399,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.S. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.S: @@ -427,18 +427,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.S. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -454,7 +454,7 @@ __tx_fiq_processing_return: @ interrupt, and all C scratch registers are available for use. */ @ @ /* Enable nested FIQ interrupts. NOTE: Since this service returns -@ with FIQ interrupts enabled, all FIQ interrupt sources must be +@ with FIQ interrupts enabled, all FIQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start @ @@ -470,12 +470,12 @@ __tx_fiq_processing_return: 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer -interrupt source, these services are not functional but the remainder of +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of ThreadX will still run. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.S for the demonstration system. @@ -483,7 +483,7 @@ found in the file tx_initialize_low_level.S for the demonstration system. 9. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); diff --git a/ports/cortex_a9/gnu/src/tx_thread_context_restore.S b/ports/cortex_a9/gnu/src/tx_thread_context_restore.S index 6b4a561d..41b0b0d0 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a9/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,23 +80,6 @@ IRQ_MODE = 0x12 // IRQ mode /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_restore .type _tx_thread_context_restore,function diff --git a/ports/cortex_a9/gnu/src/tx_thread_context_save.S b/ports/cortex_a9/gnu/src/tx_thread_context_save.S index eff06283..d2d29d34 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a9/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,23 +72,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_save .type _tx_thread_context_save,function diff --git a/ports/cortex_a9/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_a9/gnu/src/tx_thread_fiq_context_restore.S index d2fbebe1..921c322c 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a9/gnu/src/tx_thread_fiq_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -78,20 +79,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* FIQ ISR Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_restore .type _tx_thread_fiq_context_restore,function diff --git a/ports/cortex_a9/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_a9/gnu/src/tx_thread_fiq_context_save.S index 88472a3d..2f1a6c40 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a9/gnu/src/tx_thread_fiq_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_save .type _tx_thread_fiq_context_save,function diff --git a/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_end.S index fa3886b8..a7ce701e 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_start.S index dbed1cf2..4f095dde 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a9/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a9/gnu/src/tx_thread_interrupt_control.S index d1223cb8..a5bc47f7 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a9/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,20 +69,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a9/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a9/gnu/src/tx_thread_interrupt_disable.S index a87d1a06..d7b53bc2 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a9/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,20 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a9/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a9/gnu/src/tx_thread_interrupt_restore.S index 53ff2813..3c31e94b 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a9/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,20 +68,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_end.S index 18aebc7c..cc4db3a7 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_start.S index a2ffd35d..3635874d 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a9/gnu/src/tx_thread_schedule.S b/ports/cortex_a9/gnu/src/tx_thread_schedule.S index f46a339b..a74e2050 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a9/gnu/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,23 +82,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a9/gnu/src/tx_thread_stack_build.S b/ports/cortex_a9/gnu/src/tx_thread_stack_build.S index 3876225a..827554a7 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a9/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,20 +75,6 @@ CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ int /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a9/gnu/src/tx_thread_system_return.S b/ports/cortex_a9/gnu/src/tx_thread_system_return.S index 0eed478d..1a17446b 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a9/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,23 +69,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a9/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_a9/gnu/src/tx_thread_vectored_context_save.S index fe8a98e8..91653b75 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a9/gnu/src/tx_thread_vectored_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_vectored_context_save .type _tx_thread_vectored_context_save,function diff --git a/ports/cortex_a9/gnu/src/tx_timer_interrupt.S b/ports/cortex_a9/gnu/src/tx_timer_interrupt.S index cb0c1fa2..179ac894 100644 --- a/ports/cortex_a9/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a9/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -77,20 +78,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports/cortex_a9/iar/example_build/cstartup.s b/ports/cortex_a9/iar/example_build/cstartup.s index 647de2e8..b4ed8f87 100644 --- a/ports/cortex_a9/iar/example_build/cstartup.s +++ b/ports/cortex_a9/iar/example_build/cstartup.s @@ -1,7 +1,7 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; -;; Part one of the system initialization code, +;; Part one of the system initialization code, ;; contains low-level ;; initialization. ;; @@ -71,13 +71,13 @@ FIQ_Addr: DCD __tx_fiq_handler SECTION .text:CODE:NOROOT(2) -; PUBLIC ?cstartup +; PUBLIC ?cstartup EXTERN ?main REQUIRE __vector - ARM - -__iar_program_start: + ARM + +__iar_program_start: ?cstartup: ; diff --git a/ports/cortex_a9/iar/example_build/sample_threadx.c b/ports/cortex_a9/iar/example_build/sample_threadx.c index c7c300cb..afbd4ea8 100644 --- a/ports/cortex_a9/iar/example_build/sample_threadx.c +++ b/ports/cortex_a9/iar/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -83,42 +83,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -126,23 +126,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -245,11 +245,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -308,7 +308,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -361,7 +361,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_a9/iar/example_build/tx_initialize_low_level.s b/ports/cortex_a9/iar/example_build/tx_initialize_low_level.s index 5820192d..6d8bfc9f 100644 --- a/ports/cortex_a9/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_a9/iar/example_build/tx_initialize_low_level.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -62,7 +62,7 @@ SYS_MODE DEFINE 0xDF ; Disable irq,fiq SYS mode ; ; ; -;/* Define the FREE_MEM segment that will specify where free memory is +;/* Define the FREE_MEM segment that will specify where free memory is ; defined. This must also be located in at the end of other RAM segments ; in the linker control file. The value of this segment is what is passed ; to tx_application_define. */ @@ -75,45 +75,39 @@ __tx_free_memory_start ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-A9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-A9/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -146,7 +140,7 @@ _tx_initialize_low_level ; LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address STR r0, [r2, #0] ; Save first free memory address -; +; ; /* Setup Timer for periodic interrupts. */ ; ; /* Done, return to caller. */ @@ -188,7 +182,7 @@ __tx_reserved_handler RSEG .text:CODE:NOROOT(2) PUBLIC __tx_irq_handler RSEG .text:CODE:NOROOT(2) - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -196,17 +190,17 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -221,7 +215,7 @@ __tx_irq_processing_return ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -240,22 +234,22 @@ __tx_irq_processing_return ; /* Jump to context save to save system context. */ ; STMDB sp!, {r0-r3} ; Save some scratch registers ; MRS r0, SPSR ; Pickup saved SPSR -; SUB lr, lr, #4 ; Adjust point of interrupt +; SUB lr, lr, #4 ; Adjust point of interrupt ; STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; BL _tx_thread_vectored_context_save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ;#ifdef TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_start @@ -264,7 +258,7 @@ __tx_irq_processing_return ; /* Application IRQ handler is called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ;#ifdef TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_end @@ -288,11 +282,11 @@ __tx_fiq_processing_return ; /* At this point execution is still in the FIQ mode. The CPSR, point of ; interrupt, and all C scratch registers are available for use. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start ; from FIQ mode with interrupts disabled. This routine switches to the -; system mode and returns with FIQ interrupts enabled. +; system mode and returns with FIQ interrupts enabled. ; -; NOTE: It is very important to ensure all FIQ interrupts are cleared +; NOTE: It is very important to ensure all FIQ interrupts are cleared ; prior to enabling nested FIQ interrupts. */ #ifdef TX_ENABLE_FIQ_NESTING BL _tx_thread_fiq_nesting_start diff --git a/ports/cortex_a9/iar/inc/tx_port.h b/ports/cortex_a9/iar/inc/tx_port.h index be24e9b9..46f042a9 100644 --- a/ports/cortex_a9/iar/inc/tx_port.h +++ b/ports/cortex_a9/iar/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Cortex-A9/IAR */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A9/IAR */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -79,7 +71,7 @@ #endif -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -115,12 +107,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -130,8 +122,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -189,7 +181,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -203,18 +195,18 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ - VOID *tx_thread_iar_tls_pointer; + VOID *tx_thread_iar_tls_pointer; #else #define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; #endif -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -228,11 +220,11 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -242,23 +234,23 @@ ULONG _tx_misra_time_stamp_get(VOID); #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #if (__VER__ < 8000000) -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #endif #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -286,8 +278,8 @@ void __iar_Initlocks(void); #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -298,22 +290,22 @@ void __iar_Initlocks(void); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (UINT) __CLZ(m); \ - b = 31 - b; + b = 31 - b; #endif #endif #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ /* First, check and see what mode the file is being compiled in. The IAR compiler - defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode + defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode is present. If ARM 32-bit mode is present, the fast CPSR manipulation macros are available. Otherwise, if Thumb mode is present, we must use function calls. */ @@ -383,8 +375,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-A9/IAR Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A9/IAR Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_a9/iar/readme_threadx.txt b/ports/cortex_a9/iar/readme_threadx.txt index 1b8ed694..bd142b40 100644 --- a/ports/cortex_a9/iar/readme_threadx.txt +++ b/ports/cortex_a9/iar/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for Cortex-A9 + Microsoft's Azure RTOS ThreadX for Cortex-A9 Thumb & 32-bit Mode @@ -7,10 +7,10 @@ 1. Building the ThreadX run-time Library Building the ThreadX library is easy. First, open the Azure RTOS workspace -azure_rtos.eww. Next, make the TX project the "active project" in the -IAR Embedded Workbench and select the "Make" button. You should observe -assembly and compilation of a series of ThreadX source files. This -results in the ThreadX run-time library file tx.a, which is needed by +azure_rtos.eww. Next, make the TX project the "active project" in the +IAR Embedded Workbench and select the "Make" button. You should observe +assembly and compilation of a series of ThreadX source files. This +results in the ThreadX run-time library file tx.a, which is needed by the application. @@ -20,47 +20,47 @@ The ThreadX demonstration is designed to execute under the IAR Windows-based Cortex-A9 simulator. Building the demonstration is easy; simply make the sample_threadx.ewp project -the "active project" in the IAR Embedded Workbench and select the +the "active project" in the IAR Embedded Workbench and select the "Make" button. -You should observe the compilation of sample_threadx.c (which is the demonstration +You should observe the compilation of sample_threadx.c (which is the demonstration application) and linking with tx.a. The resulting file sample_threadx.out is a binary file that can be downloaded and executed on IAR's Cortex-A9 simulator. 3. System Initialization -The entry point in ThreadX for the Cortex-A9 using IAR tools is at label -?cstartup. This is defined within the IAR compiler's startup code. In -addition, this is where all static and global preset C variable +The entry point in ThreadX for the Cortex-A9 using IAR tools is at label +?cstartup. This is defined within the IAR compiler's startup code. In +addition, this is where all static and global preset C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, and a periodic timer interrupt source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. By default, the vector area is defined at the top of cstartup.s, which is -a slightly modified from the base IAR file. +a slightly modified from the base IAR file. The _tx_initialize_low_level function inside of tx_initialize_low_level.s -also determines the first available address for use by the application, which -is supplied as the sole input parameter to your application definition function, -tx_application_define. To accomplish this, a section is created in -tx_initialize_low_level.s called FREE_MEM, which must be located after all +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all other RAM sections in memory. 4. Register Usage and Stack Frames -The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are -scratch registers for each function. All other registers used by a C function -must be preserved by the function. ThreadX takes advantage of this in -situations where a context switch happens as a result of making a ThreadX -service call (which is itself a C function). In such cases, the saved +The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are +scratch registers for each function. All other registers used by a C function +must be preserved by the function. ThreadX takes advantage of this in +situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -78,12 +78,12 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 5. Conditional Compilation Switches @@ -92,146 +92,146 @@ The following are conditional compilation options for building the ThreadX libra and application: - TX_ENABLE_FIQ_SUPPORT This assembler/compiler define enables + TX_ENABLE_FIQ_SUPPORT This assembler/compiler define enables FIQ interrupt handling support in the ThreadX assembly files. If used, it should be used on all assembly files and the generic C source of - ThreadX should be compiled with + ThreadX should be compiled with TX_ENABLE_FIQ_SUPPORT defined as well. TX_ENABLE_IRQ_NESTING This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. TX_ENABLE_FIQ_NESTING This assembler define enables FIQ - nested support. If FIQ nested + nested support. If FIQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. In addition, IRQ nesting should also be enabled. TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - TX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. TX_THUMB Defined, this option enables the BX LR calling return sequence @@ -245,29 +245,29 @@ and application: 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the ThreadX library -project to enable various compiler optimizations. +project to enable various compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A9 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-A9 vectors start at address zero. The demonstration system startup -cstartup.s file contains the vectors and is loaded at address zero. -On actual hardware platforms, this area might have to be copied to address 0. +cstartup.s file contains the vectors and is loaded at address zero. +On actual hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs @@ -278,12 +278,12 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.s: PUBLIC __tx_irq_handler - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -291,7 +291,7 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -304,7 +304,7 @@ __tx_irq_processing_return 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.s: @@ -315,12 +315,12 @@ __tx_example_vectored_irq_handler ; /* Jump to context save to save system context. */ STMDB sp!, {r0-r3} ; Save some scratch registers MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers BL _tx_thread_vectored_context_save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -337,24 +337,24 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.s. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables -nesting by disabling IRQ interrupts and switching back to IRQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: RSEG .text:CODE:NOROOT(2) PUBLIC __tx_irq_handler RSEG .text:CODE:NOROOT(2) - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -362,15 +362,15 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ; BL _tx_thread_irq_nesting_start @@ -378,7 +378,7 @@ __tx_irq_processing_return ; /* Application ISR dispatch call goes here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ; BL _tx_thread_irq_nesting_end @@ -389,12 +389,12 @@ __tx_irq_processing_return 7.3 FIQ Interrupts -By default, Cortex-A9 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, Cortex-A9 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.s. @@ -403,7 +403,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.s. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.s: @@ -434,18 +434,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.s. When nested FIQ interrupts are no -longer required, calling the _tx_thread_fiq_nesting_end service disables -nesting by disabling FIQ interrupts and switching back to FIQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested FIQ interrupts are no +longer required, calling the _tx_thread_fiq_nesting_end service disables +nesting by disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -463,7 +463,7 @@ __tx_fiq_processing_return: ; interrupt, and all C scratch registers are available for use. */ ; ; /* Enable nested FIQ interrupts. NOTE: Since this service returns -; with FIQ interrupts enabled, all FIQ interrupt sources must be +; with FIQ interrupts enabled, all FIQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start ; @@ -479,22 +479,22 @@ __tx_fiq_processing_return: 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to _tx_timer_interrupt +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. 9. Thumb/Cortex-A9 Mixed Mode -By default, ThreadX is setup for running in Cortex-A9 32-bit mode. This is -also true for the demonstration system. It is possible to build any +By default, ThreadX is setup for running in Cortex-A9 32-bit mode. This is +also true for the demonstration system. It is possible to build any ThreadX file and/or the application in Thumb mode. The only exception -to this is the file tx_thread_shell_entry.c. This file must always be -built in 32-bit mode. In addition, if any Thumb code is used the entire +to this is the file tx_thread_shell_entry.c. This file must always be +built in 32-bit mode. In addition, if any Thumb code is used the entire ThreadX assembly source should be built with TX_THUMB defined. @@ -506,14 +506,14 @@ should have the following line added (if not already in place): initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application -The project options "General Options -> Library Configuration" should also have the +The project options "General Options -> Library Configuration" should also have the "Enable thread support in library" box selected. 11. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); diff --git a/ports/cortex_a9/iar/src/tx_iar.c b/ports/cortex_a9/iar/src/tx_iar.c index 158738ea..238b485e 100644 --- a/ports/cortex_a9/iar/src/tx_iar.c +++ b/ports/cortex_a9/iar/src/tx_iar.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** IAR Multithreaded Library Support */ /** */ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports/cortex_a9/iar/src/tx_thread_context_restore.s b/ports/cortex_a9/iar/src/tx_thread_context_restore.s index e063a2b1..967760e0 100644 --- a/ports/cortex_a9/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_a9/iar/src/tx_thread_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,7 +36,7 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask THUMB_MASK DEFINE 0x20 ; Thumb bit mask SVC_MODE_BITS DEFINE 0x13 ; SVC mode value @@ -51,47 +51,38 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore Cortex-A9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-A9/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -121,13 +112,13 @@ _tx_thread_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3, #0] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3, #0] ; Store the counter + STR r2, [r3, #0] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -193,7 +184,7 @@ __tx_thread_preempt_restore LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer - + #ifdef __ARMVFP__ LDR r2, [r0, #144] ; Pickup the VFP enabled flag CMP r2, #0 ; Is the VFP enabled? @@ -204,7 +195,7 @@ __tx_thread_preempt_restore VSTMDB sp!, {D0-D15} ; Save D0-D15 _tx_skip_fiq_vfp_save: #endif - + MOV r3, #1 ; Build interrupt stack type STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR STR sp, [r0, #8] ; Save stack pointer in thread control diff --git a/ports/cortex_a9/iar/src/tx_thread_context_save.s b/ports/cortex_a9/iar/src/tx_thread_context_save.s index 75045787..7603d79a 100644 --- a/ports/cortex_a9/iar/src/tx_thread_context_save.s +++ b/ports/cortex_a9/iar/src/tx_thread_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -43,46 +43,37 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled EXTERN _tx_execution_isr_enter ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save Cortex-A9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-A9/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -99,7 +90,7 @@ _tx_thread_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt CPSR @@ -119,7 +110,7 @@ _tx_thread_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -135,7 +126,7 @@ _tx_thread_context_save POP {lr} ; Recover ISR lr #endif - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; __tx_thread_not_nested_save ; } @@ -149,13 +140,13 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} ; Store other registers ; ; /* Save the current stack pointer in the thread's control block. */ @@ -175,7 +166,7 @@ __tx_thread_not_nested_save POP {lr} ; Recover ISR lr #endif - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ; else @@ -185,7 +176,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit @@ -200,7 +191,7 @@ __tx_thread_idle_system_save #endif ADD sp, sp, #16 ; Recover saved registers - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ;} diff --git a/ports/cortex_a9/iar/src/tx_thread_fiq_context_restore.s b/ports/cortex_a9/iar/src/tx_thread_fiq_context_restore.s index 999febae..7d97d09b 100644 --- a/ports/cortex_a9/iar/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_a9/iar/src/tx_thread_fiq_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -37,7 +37,7 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask THUMB_MASK DEFINE 0x20 ; Thumb bit mask IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits SVC_MODE_BITS DEFINE 0x13 ; SVC mode value @@ -52,47 +52,38 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value EXTERN _tx_execution_isr_exit ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_restore Cortex-A9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore Cortex-A9/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the fiq interrupt context when processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* FIQ ISR Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) @@ -122,13 +113,13 @@ _tx_thread_fiq_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3] ; Store the counter + STR r2, [r3] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -172,7 +163,7 @@ __tx_thread_fiq_no_preempt_restore ; /* Restore interrupted thread or ISR. */ ; ; /* Pickup the saved stack pointer. */ -; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; ; ; /* Recover the saved context and return to the point of interrupt. */ ; @@ -232,7 +223,7 @@ _tx_skip_irq_vfp_save: BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it ; ; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; -; _tx_timer_time_slice = 0; +; _tx_timer_time_slice = 0; ; STR r2, [r0, #24] ; Save thread's time-slice MOV r2, #0 ; Clear value diff --git a/ports/cortex_a9/iar/src/tx_thread_fiq_context_save.s b/ports/cortex_a9/iar/src/tx_thread_fiq_context_save.s index 7f974a72..5eabfd4b 100644 --- a/ports/cortex_a9/iar/src/tx_thread_fiq_context_save.s +++ b/ports/cortex_a9/iar/src/tx_thread_fiq_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,46 +36,37 @@ EXTERN _tx_execution_isr_enter ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_save Cortex-A9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save Cortex-A9/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) @@ -92,7 +83,7 @@ _tx_thread_fiq_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state CMP r2, #0 ; Is this the first interrupt? @@ -107,7 +98,7 @@ _tx_thread_fiq_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -123,38 +114,38 @@ _tx_thread_fiq_context_save POP {lr} ; Recover ISR lr #endif - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; __tx_thread_fiq_not_nested_save -; } +; } ; ; /* Otherwise, not nested, check to see if a thread was running. */ ; else if (_tx_thread_current_ptr) -; { +; { ; ADD r2, r2, #1 ; Increment the interrupt counter STR r2, [r3] ; Store it back in the variable LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in -; ; scheduling loop - nothing needs saving! + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, lr} ; Store other registers, Note that we don't -; ; need to save sl and ip since FIQ has -; ; copies of these registers. Nested +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested ; ; interrupt processing does need to save ; ; these registers. ; ; /* Save the current stack pointer in the thread's control block. */ -; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; ; ; /* Switch to the system stack. */ -; sp = _tx_thread_system_stack_ptr; +; sp = _tx_thread_system_stack_ptr; ; MOV r10, #0 ; Clear stack limit @@ -167,7 +158,7 @@ __tx_thread_fiq_not_nested_save POP {lr} ; Recover ISR lr #endif - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } ; else @@ -187,18 +178,18 @@ __tx_thread_fiq_idle_system_save #endif ; ; /* Not much to do here, save the current SPSR and LR for possible -; use in IRQ interrupted in idle system conditions, and return to +; use in IRQ interrupted in idle system conditions, and return to ; FIQ interrupt processing. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, lr} ; Store other registers that will get used -; ; or stripped off the stack in context -; ; restore - B __tx_fiq_processing_return ; Continue FIQ processing +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } -;} +;} ; ; END diff --git a/ports/cortex_a9/iar/src/tx_thread_fiq_nesting_end.s b/ports/cortex_a9/iar/src/tx_thread_fiq_nesting_end.s index 27221a2b..42aea60c 100644 --- a/ports/cortex_a9/iar/src/tx_thread_fiq_nesting_end.s +++ b/ports/cortex_a9/iar/src/tx_thread_fiq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,55 +34,49 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_end Cortex-A9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end Cortex-A9/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ -;/* processing from system mode back to FIQ mode prior to the ISR */ -;/* calling _tx_thread_fiq_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s79). */ -;/* */ -;/* This function returns with FIQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/cortex_a9/iar/src/tx_thread_fiq_nesting_start.s b/ports/cortex_a9/iar/src/tx_thread_fiq_nesting_start.s index af3d7786..52467afa 100644 --- a/ports/cortex_a9/iar/src/tx_thread_fiq_nesting_start.s +++ b/ports/cortex_a9/iar/src/tx_thread_fiq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ MODE_MASK DEFINE 0x1F ; Mode mask SYS_MODE_BITS DEFINE 0x1F ; System mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_start Cortex-A9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start Cortex-A9/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ -;/* processing to the system mode so nested FIQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s79). */ -;/* */ -;/* This function returns with FIQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_a9/iar/src/tx_thread_interrupt_control.s b/ports/cortex_a9/iar/src/tx_thread_interrupt_control.s index 75d7279b..acb20eaf 100644 --- a/ports/cortex_a9/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_a9/iar/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,42 +35,36 @@ INT_MASK DEFINE 0x80 ; Interrupt bit mask #endif ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control Cortex-A9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-A9/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a9/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_a9/iar/src/tx_thread_interrupt_disable.s index ce8e51cf..c7c2539e 100644 --- a/ports/cortex_a9/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_a9/iar/src/tx_thread_interrupt_disable.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,41 +36,35 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable Cortex-A9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-A9/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_a9/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_a9/iar/src/tx_thread_interrupt_restore.s index bad3cf79..eb6968c8 100644 --- a/ports/cortex_a9/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_a9/iar/src/tx_thread_interrupt_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -28,42 +28,36 @@ ;#include "tx_thread.h" ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore Cortex-A9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-A9/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function is responsible for restoring interrupts to the state */ ;/* returned by a previous _tx_thread_interrupt_disable call. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;void _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a9/iar/src/tx_thread_irq_nesting_end.s b/ports/cortex_a9/iar/src/tx_thread_irq_nesting_end.s index a3e6d819..12ab0fd5 100644 --- a/ports/cortex_a9/iar/src/tx_thread_irq_nesting_end.s +++ b/ports/cortex_a9/iar/src/tx_thread_irq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,55 +35,49 @@ DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts #else DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts #endif -MODE_MASK DEFINE 0x1F ; Mode mask +MODE_MASK DEFINE 0x1F ; Mode mask IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_end Cortex-A9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-A9/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -;/* processing from system mode back to IRQ mode prior to the ISR */ -;/* calling _tx_thread_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s79). */ -;/* */ -;/* This function returns with IRQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_a9/iar/src/tx_thread_irq_nesting_start.s b/ports/cortex_a9/iar/src/tx_thread_irq_nesting_start.s index ed787d24..77d2cd5b 100644 --- a/ports/cortex_a9/iar/src/tx_thread_irq_nesting_start.s +++ b/ports/cortex_a9/iar/src/tx_thread_irq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ MODE_MASK DEFINE 0x1F ; Mode mask SYS_MODE_BITS DEFINE 0x1F ; System mode bits ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_start Cortex-A9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-A9/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_context_save has been called and switches the IRQ */ -;/* processing to the system mode so nested IRQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s79). */ -;/* */ -;/* This function returns with IRQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_a9/iar/src/tx_thread_schedule.s b/ports/cortex_a9/iar/src/tx_thread_schedule.s index a2367096..be461cb1 100644 --- a/ports/cortex_a9/iar/src/tx_thread_schedule.s +++ b/ports/cortex_a9/iar/src/tx_thread_schedule.s @@ -1,19 +1,19 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors -; * +; * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -44,48 +44,39 @@ ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule Cortex-A9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-A9/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -115,7 +106,7 @@ __tx_thread_schedule_loop ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Lockout interrupts and ; transfer control to it. */ ; @@ -124,7 +115,7 @@ __tx_thread_schedule_loop ; /* Setup the current thread pointer. */ ; _tx_thread_current_ptr = _tx_thread_execute_ptr; ; - LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread STR r0, [r1, #0] ; Setup current thread pointer ; ; /* Increment the run count for this thread. */ @@ -138,7 +129,7 @@ __tx_thread_schedule_loop ; /* Setup time-slice, if present. */ ; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; ; - LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice ; variable LDR sp, [r0, #8] ; Switch stack pointers STR r3, [r2, #0] ; Setup time-slice @@ -200,7 +191,7 @@ _tx_skip_solicited_vfp_restore: #ifdef __ARMVFP__ PUBLIC tx_thread_vfp_enable CODE32 -tx_thread_vfp_enable??rA +tx_thread_vfp_enable??rA tx_thread_vfp_enable MRS r2, CPSR ; Pickup the CPSR #ifdef TX_ENABLE_FIQ_SUPPORT @@ -220,7 +211,7 @@ __tx_no_thread_to_enable: PUBLIC tx_thread_vfp_disable CODE32 -tx_thread_vfp_disable??rA +tx_thread_vfp_disable??rA tx_thread_vfp_disable MRS r2, CPSR ; Pickup the CPSR #ifdef TX_ENABLE_FIQ_SUPPORT diff --git a/ports/cortex_a9/iar/src/tx_thread_stack_build.s b/ports/cortex_a9/iar/src/tx_thread_stack_build.s index 8b153c14..3fa21263 100644 --- a/ports/cortex_a9/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_a9/iar/src/tx_thread_stack_build.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -37,58 +37,52 @@ CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints en #endif ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build Cortex-A9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-A9/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function builds a stack frame on the supplied thread's stack. */ ;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ ;/* thread_ptr Pointer to thread control blk */ ;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) ;{ RSEG .text:CODE:NOROOT(2) PUBLIC _tx_thread_stack_build - + CODE32 _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-A9 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; a1 (r0) Initial value for a1 diff --git a/ports/cortex_a9/iar/src/tx_thread_system_return.s b/ports/cortex_a9/iar/src/tx_thread_system_return.s index d8d1b096..8f357380 100644 --- a/ports/cortex_a9/iar/src/tx_thread_system_return.s +++ b/ports/cortex_a9/iar/src/tx_thread_system_return.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -42,47 +42,38 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return Cortex-A9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-A9/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -121,7 +112,7 @@ _tx_skip_solicited_vfp_save: MOV r0, #0 ; Build a solicited stack type STMDB sp!, {r0-r1} ; Save type and CPSR -; +; ; #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) ; diff --git a/ports/cortex_a9/iar/src/tx_thread_vectored_context_save.s b/ports/cortex_a9/iar/src/tx_thread_vectored_context_save.s index 76d9b155..923863ed 100644 --- a/ports/cortex_a9/iar/src/tx_thread_vectored_context_save.s +++ b/ports/cortex_a9/iar/src/tx_thread_vectored_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -41,46 +41,37 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled EXTERN _tx_execution_isr_enter ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_vectored_context_save Cortex-A9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-A9/IAR */ ;/* 6.1.9 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), added */ -;/* execution profile support, */ -;/* resulting in version 6.1.9 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) @@ -142,7 +133,7 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in ; scheduling loop - nothing needs saving! ; ; /* Note: Minimal context of interrupted thread is already saved. */ @@ -174,7 +165,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports/cortex_a9/iar/src/tx_timer_interrupt.s b/ports/cortex_a9/iar/src/tx_timer_interrupt.s index 86c6960e..d7b9810e 100644 --- a/ports/cortex_a9/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_a9/iar/src/tx_timer_interrupt.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -43,46 +43,40 @@ ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt Cortex-A9/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-A9/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time-slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time-slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -108,7 +102,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CMP r2, #0 ; Is it non-active? BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing @@ -226,13 +220,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CMP r2, #0 ; See if the flag is set BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing ; diff --git a/ports/cortex_m0/ac5/example_build/sample_threadx.c b/ports/cortex_m0/ac5/example_build/sample_threadx.c index 4d95c2ed..dd5ee155 100644 --- a/ports/cortex_m0/ac5/example_build/sample_threadx.c +++ b/ports/cortex_m0/ac5/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s index f1a83341..b16b3e20 100644 --- a/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -120,12 +120,6 @@ Reset_Handler ;/* */ ;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) ;{ diff --git a/ports/cortex_m0/ac5/inc/tx_port.h b/ports/cortex_m0/ac5/inc/tx_port.h index 20d9c4ee..f163f1c6 100644 --- a/ports/cortex_m0/ac5/inc/tx_port.h +++ b/ports/cortex_m0/ac5/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,18 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -64,7 +53,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -113,7 +102,7 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY +#ifndef TX_TIMER_THREAD_PRIORITY #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -124,8 +113,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0 /* Enable interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0x0a800024) @@ -164,7 +153,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -178,13 +167,13 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -198,11 +187,11 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -210,10 +199,10 @@ ULONG _tx_misra_time_stamp_get(VOID); tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) -#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) #ifndef TX_MISRA_ENABLE @@ -246,7 +235,7 @@ register unsigned int _ipsr __asm("ipsr"); /* Define the get system state macro. */ - + #ifndef TX_THREAD_GET_SYSTEM_STATE #ifndef TX_MISRA_ENABLE #define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _ipsr) @@ -263,19 +252,19 @@ ULONG _tx_misra_ipsr_get(VOID); zero after initialization for Cortex-M ports. */ #ifndef TX_THREAD_SYSTEM_RETURN_CHECK -#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); #endif -/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to prevent early scheduling on Cortex-M parts. */ - + #define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -322,8 +311,8 @@ unsigned int was_masked; /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M0/AC5 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0/AC5 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m0/ac5/readme_threadx.txt b/ports/cortex_m0/ac5/readme_threadx.txt index 301aa31e..20f7ebef 100644 --- a/ports/cortex_m0/ac5/readme_threadx.txt +++ b/ports/cortex_m0/ac5/readme_threadx.txt @@ -1,18 +1,18 @@ - Microsoft's Azure RTOS ThreadX for Cortex-M0 + Microsoft's Azure RTOS ThreadX for Cortex-M0 Using ARM Compiler 5 (AC5) 1. Building the ThreadX run-time Library -First make sure you are in the "example_build" directory. Also, make sure that -you have setup your path and other environment variables necessary for the AC5 -development environment. At this point you may run the build_threadx.bat batch -file. This will build the ThreadX run-time environment in the "example_build" -directory. +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the AC5 +development environment. At this point you may run the build_threadx.bat batch +file. This will build the ThreadX run-time environment in the "example_build" +directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. @@ -21,27 +21,27 @@ application in order to use ThreadX. The ThreadX demonstration is designed to execute under the ARM Windows-based simulator. -Building the demonstration is easy; simply execute the build_threadx_sample.bat -batch file while inside the "example_build" directory. +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with tx.a. The resulting file sample_threadx.axf +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.axf is a binary file that can be downloaded and executed on the ARM simulator. 3. System Initialization -The entry point in ThreadX for the Cortex-M0 using AC5 tools is at label -__main. This is defined within the AC5 compiler's startup code. In -addition, this is where all static and global pre-set C variable +The entry point in ThreadX for the Cortex-M0 using AC5 tools is at label +__main. This is defined within the AC5 compiler's startup code. In +addition, this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. @@ -50,11 +50,11 @@ parameter to your application definition function, tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M0 version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. - Stack Offset Stack Contents + Stack Offset Stack Contents 0x00 r8 0x04 r9 @@ -76,21 +76,21 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. 5. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make it run faster, you can change the build_threadx.bat file to -remove the -g option and enable all compiler optimizations. +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M0 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: diff --git a/ports/cortex_m0/ac5/src/tx_thread_context_restore.s b/ports/cortex_m0/ac5/src/tx_thread_context_restore.s index 673ba8c6..85d6cf35 100644 --- a/ports/cortex_m0/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_m0/ac5/src/tx_thread_context_restore.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -20,7 +20,7 @@ ;/**************************************************************************/ ; ; -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) IMPORT _tx_execution_isr_exit #endif ; @@ -61,19 +61,13 @@ ;/* */ ;/* ISRs Interrupt Service Routines */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) ;{ EXPORT _tx_thread_context_restore _tx_thread_context_restore -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) ; ; /* Call the ISR exit function to indicate an ISR is complete. */ ; diff --git a/ports/cortex_m0/ac5/src/tx_thread_context_save.s b/ports/cortex_m0/ac5/src/tx_thread_context_save.s index df7d1721..d0c2c9e4 100644 --- a/ports/cortex_m0/ac5/src/tx_thread_context_save.s +++ b/ports/cortex_m0/ac5/src/tx_thread_context_save.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -20,7 +20,7 @@ ;/**************************************************************************/ ; ; -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) IMPORT _tx_execution_isr_enter #endif ; @@ -61,18 +61,12 @@ ;/* */ ;/* ISRs */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) ;{ EXPORT _tx_thread_context_save _tx_thread_context_save -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) ; ; /* Call the ISR enter function to indicate an ISR is executing. */ ; diff --git a/ports/cortex_m0/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_m0/ac5/src/tx_thread_interrupt_control.s index a8504791..be0da62d 100644 --- a/ports/cortex_m0/ac5/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m0/ac5/src/tx_thread_interrupt_control.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -52,12 +52,6 @@ ;/* */ ;/* Application Code */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) ;{ diff --git a/ports/cortex_m0/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_m0/ac5/src/tx_thread_interrupt_disable.s index aac316ea..86ab4562 100644 --- a/ports/cortex_m0/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m0/ac5/src/tx_thread_interrupt_disable.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -52,12 +52,6 @@ ;/* */ ;/* Application Code */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) ;{ diff --git a/ports/cortex_m0/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_m0/ac5/src/tx_thread_interrupt_restore.s index b94b9e7b..8e71728a 100644 --- a/ports/cortex_m0/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m0/ac5/src/tx_thread_interrupt_restore.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -52,12 +52,6 @@ ;/* */ ;/* Application Code */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) ;{ diff --git a/ports/cortex_m0/ac5/src/tx_thread_schedule.s b/ports/cortex_m0/ac5/src/tx_thread_schedule.s index 06f03cca..701eeef4 100644 --- a/ports/cortex_m0/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_m0/ac5/src/tx_thread_schedule.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -25,7 +25,7 @@ IMPORT _tx_timer_time_slice IMPORT _tx_thread_system_stack_ptr IMPORT _tx_thread_preempt_disable -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) IMPORT _tx_execution_thread_enter IMPORT _tx_execution_thread_exit #endif @@ -71,15 +71,6 @@ ;/* _tx_thread_system_return Return to system from thread */ ;/* _tx_thread_context_restore Restore thread's context */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 03-02-2021 Scott Larson Modified comment(s), add */ -;/* low power code, */ -;/* resulting in version 6.1.5 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) ;{ @@ -126,7 +117,7 @@ __tx_PendSVHandler ; __tx_ts_handler -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) ; ; /* Call the thread exit function to indicate the thread is no longer executing. */ ; @@ -209,7 +200,7 @@ __tx_ts_restore ; STR r5, [r4] ; Setup global time-slice -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) ; ; /* Call the thread entry function to indicate the thread is executing. */ ; diff --git a/ports/cortex_m0/ac5/src/tx_thread_stack_build.s b/ports/cortex_m0/ac5/src/tx_thread_stack_build.s index 8324238a..e1cf9d16 100644 --- a/ports/cortex_m0/ac5/src/tx_thread_stack_build.s +++ b/ports/cortex_m0/ac5/src/tx_thread_stack_build.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -54,12 +54,6 @@ ;/* */ ;/* _tx_thread_create Create thread service */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) ;{ diff --git a/ports/cortex_m0/ac5/src/tx_thread_system_return.s b/ports/cortex_m0/ac5/src/tx_thread_system_return.s index d37623fc..db1ab63d 100644 --- a/ports/cortex_m0/ac5/src/tx_thread_system_return.s +++ b/ports/cortex_m0/ac5/src/tx_thread_system_return.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -54,12 +54,6 @@ ;/* */ ;/* ThreadX components */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) ;{ diff --git a/ports/cortex_m0/ac5/src/tx_timer_interrupt.s b/ports/cortex_m0/ac5/src/tx_timer_interrupt.s index e6ebbc76..b712487f 100644 --- a/ports/cortex_m0/ac5/src/tx_timer_interrupt.s +++ b/ports/cortex_m0/ac5/src/tx_timer_interrupt.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -71,12 +71,6 @@ ;/* */ ;/* interrupt vector */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) ;{ diff --git a/ports/cortex_m0/ac6/example_build/sample_threadx/.cproject b/ports/cortex_m0/ac6/example_build/sample_threadx/.cproject index ca43166b..a6b39187 100644 --- a/ports/cortex_m0/ac6/example_build/sample_threadx/.cproject +++ b/ports/cortex_m0/ac6/example_build/sample_threadx/.cproject @@ -1,166 +1,166 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_m0/ac6/example_build/sample_threadx/exceptions.c b/ports/cortex_m0/ac6/example_build/sample_threadx/exceptions.c index 96597048..47c84ea1 100644 --- a/ports/cortex_m0/ac6/example_build/sample_threadx/exceptions.c +++ b/ports/cortex_m0/ac6/example_build/sample_threadx/exceptions.c @@ -1,7 +1,7 @@ /* ** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ** Use, modification and redistribution of this file is subject to your possession of a -** valid End User License Agreement for the Arm Product of which these examples are part of +** valid End User License Agreement for the Arm Product of which these examples are part of ** and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_m0/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_m0/ac6/example_build/sample_threadx/sample_threadx.c index f400736a..01f48910 100644 --- a/ports/cortex_m0/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_m0/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -83,42 +83,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -126,23 +126,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -245,11 +245,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -308,7 +308,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -361,7 +361,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_m0/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_m0/ac6/example_build/sample_threadx/sample_threadx.scat index 8578282d..7e806ce3 100644 --- a/ports/cortex_m0/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports/cortex_m0/ac6/example_build/sample_threadx/sample_threadx.scat @@ -3,7 +3,7 @@ ;******************************************************* ; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 5786976d..f7e3eb2d 100644 --- a/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,10 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @@ -67,12 +67,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* */ @/* _tx_initialize_kernel_enter ThreadX entry function */ @/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) @{ diff --git a/ports/cortex_m0/ac6/example_build/tx/.cproject b/ports/cortex_m0/ac6/example_build/tx/.cproject index f4200860..84b4712c 100644 --- a/ports/cortex_m0/ac6/example_build/tx/.cproject +++ b/ports/cortex_m0/ac6/example_build/tx/.cproject @@ -1,146 +1,146 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_m0/ac6/inc/tx_port.h b/ports/cortex_m0/ac6/inc/tx_port.h index de4ec330..9c9e6470 100644 --- a/ports/cortex_m0/ac6/inc/tx_port.h +++ b/ports/cortex_m0/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,18 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -64,7 +53,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -130,7 +119,7 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY +#ifndef TX_TIMER_THREAD_PRIORITY #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -141,8 +130,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0 /* Enable interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0x0a800024) @@ -181,7 +170,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -195,13 +184,13 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -215,11 +204,11 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -227,8 +216,8 @@ ULONG _tx_misra_time_stamp_get(VOID); tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -256,7 +245,7 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the get system state macro. */ - + #ifndef TX_THREAD_GET_SYSTEM_STATE #ifndef TX_MISRA_ENABLE @@ -285,9 +274,9 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); #endif -/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to prevent early scheduling on Cortex-M parts. */ - + #define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; @@ -338,7 +327,7 @@ unsigned int interrupt_save; interrupt_save = __get_primask_value(); __enable_interrupts(); __restore_interrupts(interrupt_save); - } + } } @@ -365,8 +354,8 @@ unsigned int interrupt_save; /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M0/AC6 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0/AC6 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m0/ac6/readme_threadx.txt b/ports/cortex_m0/ac6/readme_threadx.txt index a84dfa25..2a3f56f9 100644 --- a/ports/cortex_m0/ac6/readme_threadx.txt +++ b/ports/cortex_m0/ac6/readme_threadx.txt @@ -1,18 +1,18 @@ - Microsoft's Azure RTOS ThreadX for Cortex-M0 + Microsoft's Azure RTOS ThreadX for Cortex-M0 Using ARM Compiler 6 & DS 1. Import the ThreadX Projects -In order to build the ThreadX library and the ThreadX demonstration, first import -the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +In order to build the ThreadX library and the ThreadX demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) into your DS workspace. 2. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply right-click the Eclipse project -"tx" and then select the "Build Project" button. You should now observe the compilation +Building the ThreadX library is easy; simply right-click the Eclipse project +"tx" and then select the "Build Project" button. You should now observe the compilation and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. @@ -22,27 +22,27 @@ library file tx.a. The ThreadX demonstration is designed to execute under the DS debugger on the MPS2_Cortex_M0 Bare Metal simulator. -Building the demonstration is easy; simply right-click the Eclipse project -"sample_threadx" and then select the "Build Project" button. You should now observe -the compilation and assembly of the ThreadX demonstration. This project build produces -the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder +Building the demonstration is easy; simply right-click the Eclipse project +"sample_threadx" and then select the "Build Project" button. You should now observe +the compilation and assembly of the ThreadX demonstration. This project build produces +the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder in the Project Explorer window, right-click on the 'cortex-m0_tx.launch' file, click 'Debug As', and then click 'cortex-m0_tx' from the submenu. This will cause the -debugger to load the sample_threadx.axf ELF file and run to main. You are now ready +debugger to load the sample_threadx.axf ELF file and run to main. You are now ready to execute the ThreadX demonstration. 4. System Initialization -The entry point in ThreadX for the Cortex-M0 using AC6 tools uses the standard AC6 +The entry point in ThreadX for the Cortex-M0 using AC6 tools uses the standard AC6 Cortex-M0 reset sequence. From the reset vector the C runtime will be initialized. -The ThreadX tx_initialize_low_level.S file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. +The ThreadX tx_initialize_low_level.S file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. @@ -51,11 +51,11 @@ parameter to your application definition function, tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M0 version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. - Stack Offset Stack Contents + Stack Offset Stack Contents 0x00 r8 0x04 r9 @@ -77,29 +77,29 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. 6. Improving Performance -The distribution version of ThreadX is built without any compiler optimizations. -This makes it easy to debug because you can trace or set breakpoints inside of -ThreadX itself. Of course, this costs some performance. To make it run faster, -you can change the build_threadx.bat file to remove the -g option and enable -all compiler optimizations. +The distribution version of ThreadX is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX itself. Of course, this costs some performance. To make it run faster, +you can change the build_threadx.bat file to remove the -g option and enable +all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M0 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-M0 vectors start at the label __tx_vectors or similar. The application may modify -the vector area according to its needs. There is code in tx_initialize_low_level() that will -configure the vector base register. +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. 7.2 Managed Interrupts @@ -125,7 +125,7 @@ your_assembly_isr: ; VOID your_assembly_isr(VOID) ; { PUSH {r0, lr} -; +; ; /* Do interrupt handler work here */ ; /* BL */ @@ -137,8 +137,8 @@ your_assembly_isr: Note: the Cortex-M0 requires exception handlers to be thumb labels, this implies bit 0 set. To accomplish this, the declaration of the label has to be preceded by the assembler directive -.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to -be inserted in the correct location in the interrupt vector table. This table is typically +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically located in either your runtime startup file or in the tx_initialize_low_level.S file. diff --git a/ports/cortex_m0/ac6/src/tx_thread_context_restore.S b/ports/cortex_m0/ac6/src/tx_thread_context_restore.S index a2aedaf0..cf90182f 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m0/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,10 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @@ -23,7 +23,7 @@ #include "tx_user.h" #endif @ -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_exit #endif .global _tx_thread_system_state @@ -73,14 +73,6 @@ @/* */ @/* ISRs Interrupt Service Routines */ @/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Scott Larson Include tx_user.h, */ -@/* resulting in version 6.2.1 */ -@/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) @{ diff --git a/ports/cortex_m0/ac6/src/tx_thread_context_save.S b/ports/cortex_m0/ac6/src/tx_thread_context_save.S index 0a00a628..f2d4f031 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m0/ac6/src/tx_thread_context_save.S @@ -1,10 +1,10 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @@ -23,7 +23,7 @@ #include "tx_user.h" #endif @ -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_enter #endif .global _tx_thread_system_state @@ -67,14 +67,6 @@ @/* */ @/* ISRs */ @/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Scott Larson Include tx_user.h, */ -@/* resulting in version 6.2.1 */ -@/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) @{ @@ -82,7 +74,7 @@ .thumb_func _tx_thread_context_save: @ -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR enter function to indicate an ISR is starting. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_enter // Call the ISR enter function diff --git a/ports/cortex_m0/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m0/ac6/src/tx_thread_interrupt_control.S index 766b740e..5ce46db8 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m0/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,10 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @@ -58,14 +58,6 @@ @/* */ @/* Application Code */ @/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Scott Larson Include tx_user.h, */ -@/* resulting in version 6.2.1 */ -@/* */ @/**************************************************************************/ @/* UINT _tx_thread_interrupt_control(UINT new_posture) { */ diff --git a/ports/cortex_m0/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_m0/ac6/src/tx_thread_interrupt_disable.S index 7aa32ba8..be91372b 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m0/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,10 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @@ -57,14 +57,6 @@ @/* */ @/* Application Code */ @/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Scott Larson Include tx_user.h, */ -@/* resulting in version 6.2.1 */ -@/* */ @/**************************************************************************/ @/* UINT _tx_thread_interrupt_disable(VOID) { */ diff --git a/ports/cortex_m0/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_m0/ac6/src/tx_thread_interrupt_restore.S index 5e61de27..5094b31d 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m0/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,10 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @@ -58,14 +58,6 @@ @/* */ @/* Application Code */ @/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Scott Larson Include tx_user.h, */ -@/* resulting in version 6.2.1 */ -@/* */ @/**************************************************************************/ @/* VOID _tx_thread_interrupt_restore(UINT old_posture) { */ diff --git a/ports/cortex_m0/ac6/src/tx_thread_schedule.S b/ports/cortex_m0/ac6/src/tx_thread_schedule.S index 0bb81904..552da6ab 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m0/ac6/src/tx_thread_schedule.S @@ -1,10 +1,10 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @@ -27,7 +27,7 @@ .global _tx_thread_execute_ptr .global _tx_timer_time_slice .global _tx_thread_system_stack_ptr -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_thread_enter .global _tx_execution_thread_exit #endif @@ -74,17 +74,6 @@ @/* _tx_thread_system_return Return to system from thread */ @/* _tx_thread_context_restore Restore thread's context */ @/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-02-2021 Scott Larson Modified comment(s), add */ -@/* low power code, */ -@/* resulting in version 6.1.5 */ -@/* 03-08-2023 Scott Larson Include tx_user.h, */ -@/* resulting in version 6.2.1 */ -@/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) @{ @@ -139,7 +128,7 @@ __tx_SVCallHandler: .thumb_func __tx_ts_handler: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) @ @ /* Call the thread exit function to indicate the thread is no longer executing. */ @ @@ -222,7 +211,7 @@ __tx_ts_restore: @ STR r5, [r4] @ Setup global time-slice -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) @ @ /* Call the thread entry function to indicate the thread is executing. */ @ diff --git a/ports/cortex_m0/ac6/src/tx_thread_stack_build.S b/ports/cortex_m0/ac6/src/tx_thread_stack_build.S index 6a757530..7621d9b7 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_m0/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,10 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @@ -59,14 +59,6 @@ @/* */ @/* _tx_thread_create Create thread service */ @/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Scott Larson Include tx_user.h, */ -@/* resulting in version 6.2.1 */ -@/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @{ diff --git a/ports/cortex_m0/ac6/src/tx_thread_system_return.S b/ports/cortex_m0/ac6/src/tx_thread_system_return.S index 009b7210..fc62c0c6 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m0/ac6/src/tx_thread_system_return.S @@ -1,10 +1,10 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @@ -59,14 +59,6 @@ @/* */ @/* ThreadX components */ @/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Scott Larson Include tx_user.h, */ -@/* resulting in version 6.2.1 */ -@/* */ @/**************************************************************************/ @/* VOID _tx_thread_system_return(VOID) @{ */ diff --git a/ports/cortex_m0/ac6/src/tx_timer_interrupt.S b/ports/cortex_m0/ac6/src/tx_timer_interrupt.S index f45ebfde..01608532 100644 --- a/ports/cortex_m0/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_m0/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,10 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @@ -72,14 +72,6 @@ @/* */ @/* interrupt vector */ @/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 03-08-2023 Scott Larson Include tx_user.h, */ -@/* resulting in version 6.2.1 */ -@/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) @{ diff --git a/ports/cortex_m0/gnu/example_build/cortexm0_crt0.S b/ports/cortex_m0/gnu/example_build/cortexm0_crt0.S index bb530ac5..070871a3 100644 --- a/ports/cortex_m0/gnu/example_build/cortexm0_crt0.S +++ b/ports/cortex_m0/gnu/example_build/cortexm0_crt0.S @@ -63,7 +63,7 @@ crt0_ctor_loop: beq crt0_ctor_end ldr r2, [r0] add r0, #4 - push {r0-r1} + push {r0-r1} blx r2 pop {r0-r1} b crt0_ctor_loop @@ -83,7 +83,7 @@ start: /* when main returns, loop forever. */ crt0_exit_loop: b crt0_exit_loop - + /* Startup helper functions. */ @@ -116,4 +116,3 @@ memory_set_done: .section .stack, "wa", %nobits .section .stack_process, "wa", %nobits .section .heap, "wa", %nobits - \ No newline at end of file diff --git a/ports/cortex_m0/gnu/example_build/cortexm0_vectors.S b/ports/cortex_m0/gnu/example_build/cortexm0_vectors.S index 6ae558e4..dc8d0aad 100644 --- a/ports/cortex_m0/gnu/example_build/cortexm0_vectors.S +++ b/ports/cortex_m0/gnu/example_build/cortexm0_vectors.S @@ -4,8 +4,8 @@ .global __tx_BadHandler .global __tx_SVCallHandler .global __tx_DBGHandler - .global __tx_PendSVHandler - .global __tx_SysTickHandler + .global __tx_PendSVHandler + .global __tx_SysTickHandler .global __tx_BadHandler .syntax unified @@ -15,9 +15,9 @@ .global _vectors _vectors: - .word __stack_end__ - .word reset_handler - .word __tx_NMIHandler + .word __stack_end__ + .word reset_handler + .word __tx_NMIHandler .word __tx_HardfaultHandler .word __tx_BadHandler .word __tx_BadHandler @@ -29,7 +29,7 @@ _vectors: .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // .word __tx_DBGHandler .word 0 // Reserved - .word __tx_PendSVHandler + .word __tx_PendSVHandler .word __tx_SysTickHandler // Used by Threadx timer functionality .word __tx_BadHandler // Populate with user Interrupt handler .word __tx_BadHandler diff --git a/ports/cortex_m0/gnu/example_build/sample_threadx.c b/ports/cortex_m0/gnu/example_build/sample_threadx.c index f400736a..01f48910 100644 --- a/ports/cortex_m0/gnu/example_build/sample_threadx.c +++ b/ports/cortex_m0/gnu/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -83,42 +83,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -126,23 +126,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -245,11 +245,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -308,7 +308,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -361,7 +361,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_m0/gnu/example_build/sample_threadx.ld b/ports/cortex_m0/gnu/example_build/sample_threadx.ld index c65a1346..3f19c29e 100644 --- a/ports/cortex_m0/gnu/example_build/sample_threadx.ld +++ b/ports/cortex_m0/gnu/example_build/sample_threadx.ld @@ -10,7 +10,7 @@ __HEAPSIZE__ = 128; SECTIONS { - .vectors : + .vectors : { KEEP(*(.vectors .vectors.*)) } > FLASH @@ -45,7 +45,7 @@ SECTIONS KEEP(*(.eh_frame*)) } > FLASH - .ARM.extab : + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH @@ -59,7 +59,7 @@ SECTIONS __data_load_start__ = ALIGN (4); - .data : AT (__data_load_start__) + .data : AT (__data_load_start__) { __data_start__ = .; @@ -89,7 +89,7 @@ SECTIONS KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ - + __data_end__ = .; } > RAM @@ -104,7 +104,7 @@ SECTIONS __bss_end__ = .; } > RAM - + .heap (COPY): { __heap_start__ = ALIGN(4); diff --git a/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S index fe760077..e9dfb329 100644 --- a/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S @@ -1,10 +1,10 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @@ -79,16 +79,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* */ @/* _tx_initialize_kernel_enter ThreadX entry function */ @/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 09-30-2020 Scott Larson Modified comment(s), and */ -@/* commented out code for */ -@/* enabling DWT, */ -@/* resulting in version 6.1 */ -@/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) @{ @@ -101,10 +91,10 @@ _tx_initialize_low_level: CPSID i @ @ /* Set base of available memory to end of non-initialised RAM area. */ -@ +@ LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer - LDR r1, =__RAM_segment_used_end__ @ Build first free address - ADDS r1, r1, #4 @ + LDR r1, =__RAM_segment_used_end__ @ Build first free address + ADDS r1, r1, #4 @ STR r1, [r0] @ Setup first unused memory pointer @ @ /* Enable the cycle count register. */ @@ -113,15 +103,15 @@ _tx_initialize_low_level: @ LDR r1, [r0] @ Pickup the current value @ MOVS r2, #1 @ ORRS r1, r1, r2 @ Set the CYCCNTENA bit -@ STR r1, [r0] @ Enable the cycle count register +@ STR r1, [r0] @ Enable the cycle count register @ @ /* Setup Vector Table Offset Register. */ -@ +@ LDR r0, =0xE000E000 @ Build address of NVIC registers LDR r2, =0xD08 @ Offset to vector base register ADD r0, r0, r2 @ Build vector base register LDR r1, =_vectors @ Pickup address of vector table - STR r1, [r0] @ Set vector table address + STR r1, [r0] @ Set vector table address @ @ /* Set system stack pointer from vector value. */ @ @@ -143,18 +133,18 @@ _tx_initialize_low_level: LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM LDR r0, =0xE000E000 // Build address of NVIC registers LDR r2, =0xD18 // - ADD r0, r0, r2 // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 4-7 Priority Registers LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD1C // - ADD r0, r0, r2 // + LDR r2, =0xD1C // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 8-11 Priority Registers // Note: SVC must be lowest priority, which is 0xFF LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD20 // - ADD r0, r0, r2 // + LDR r2, =0xD20 // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 12-15 Priority Registers // Note: PnSV must be lowest priority, which is 0xFF diff --git a/ports/cortex_m0/gnu/inc/tx_port.h b/ports/cortex_m0/gnu/inc/tx_port.h index 0f56ca73..9b315869 100644 --- a/ports/cortex_m0/gnu/inc/tx_port.h +++ b/ports/cortex_m0/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,20 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 William E. Lamie Modified comment(s), */ -/* resulting in version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -66,7 +53,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -132,7 +119,7 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY +#ifndef TX_TIMER_THREAD_PRIORITY #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -143,8 +130,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0 /* Enable interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0x0a800024) @@ -183,7 +170,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -197,13 +184,13 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -217,11 +204,11 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -229,8 +216,8 @@ ULONG _tx_misra_time_stamp_get(VOID); tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -258,7 +245,7 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the get system state macro. */ - + #ifndef TX_THREAD_GET_SYSTEM_STATE #ifndef TX_MISRA_ENABLE @@ -287,9 +274,9 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); #endif -/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to prevent early scheduling on Cortex-M parts. */ - + #define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; @@ -340,7 +327,7 @@ unsigned int interrupt_save; interrupt_save = __get_primask_value(); __enable_interrupts(); __restore_interrupts(interrupt_save); - } + } } @@ -367,8 +354,8 @@ unsigned int interrupt_save; /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M0/GNU Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0/GNU Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m0/gnu/readme_threadx.txt b/ports/cortex_m0/gnu/readme_threadx.txt index 6ef8a028..d7f00f6d 100644 --- a/ports/cortex_m0/gnu/readme_threadx.txt +++ b/ports/cortex_m0/gnu/readme_threadx.txt @@ -1,18 +1,18 @@ - Microsoft's Azure RTOS ThreadX for Cortex-M0 + Microsoft's Azure RTOS ThreadX for Cortex-M0 Using the GNU Tools 1. Building the ThreadX run-time Library -First make sure you are in the "example_build" directory. Also, make sure that -you have setup your path and other environment variables necessary for the ARM -gnu (GNU) compiler. At this point you may run the build_threadx.bat batch file. -This will build the ThreadX run-time environment in the "example_build" -directory. +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the ARM +gnu (GNU) compiler. At this point you may run the build_threadx.bat batch file. +This will build the ThreadX run-time environment in the "example_build" +directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. @@ -21,25 +21,25 @@ application in order to use ThreadX. The ThreadX demonstration is designed to execute on Cortex-M0 evaluation boards or on a dedicated simulator. -Building the demonstration is easy, simply execute the build_threadx_sample.bat -batch file while inside the "example_build" directory. +Building the demonstration is easy, simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with tx.a. The resulting file sample_threadx.out is a binary +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.out is a binary file that can be downloaded and executed on the a simulator, or downloaded to a board. 3. System Initialization -The entry point in ThreadX for the Cortex-M0 using gnu tools uses the standard GNU +The entry point in ThreadX for the Cortex-M0 using gnu tools uses the standard GNU Cortex-M0 reset sequence. From the reset vector the C runtime will be initialized. -The ThreadX tx_initialize_low_level.S file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. +The ThreadX tx_initialize_low_level.S file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. @@ -48,11 +48,11 @@ parameter to your application definition function, tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M0 version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. - Stack Offset Stack Contents + Stack Offset Stack Contents 0x00 r8 0x04 r9 @@ -74,29 +74,29 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. 5. Improving Performance -The distribution version of ThreadX is built without any compiler optimizations. -This makes it easy to debug because you can trace or set breakpoints inside of -ThreadX itself. Of course, this costs some performance. To make it run faster, -you can change the build_threadx.bat file to remove the -g option and enable -all compiler optimizations. +The distribution version of ThreadX is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX itself. Of course, this costs some performance. To make it run faster, +you can change the build_threadx.bat file to remove the -g option and enable +all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M0 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 6.1 Vector Area The Cortex-M0 vectors start at the label __tx_vectors or similar. The application may modify -the vector area according to its needs. There is code in tx_initialize_low_level() that will -configure the vector base register. +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. 6.2 Managed Interrupts @@ -122,7 +122,7 @@ your_assembly_isr: ; VOID your_assembly_isr(VOID) ; { PUSH {r0, lr} -; +; ; /* Do interrupt handler work here */ ; /* BL */ @@ -134,8 +134,8 @@ your_assembly_isr: Note: the Cortex-M0 requires exception handlers to be thumb labels, this implies bit 0 set. To accomplish this, the declaration of the label has to be preceded by the assembler directive -.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to -be inserted in the correct location in the interrupt vector table. This table is typically +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically located in either your runtime startup file or in the tx_initialize_low_level.S file. @@ -151,7 +151,7 @@ information associated with this specific port of ThreadX: 03-02-2021 The following files were changed/added for version 6.1.5: tx_thread_schedule.s Added low power feature -09-30-2020 ThreadX update of Cortex-M0/GNU port. The following files were +09-30-2020 ThreadX update of Cortex-M0/GNU port. The following files were changed/added for port specific version 6.1: tx_initialize_low_level.S Comment out DWT code. diff --git a/ports/cortex_m0/gnu/src/tx_thread_context_restore.S b/ports/cortex_m0/gnu/src/tx_thread_context_restore.S index 8222f9de..96854867 100644 --- a/ports/cortex_m0/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m0/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,10 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @@ -31,7 +31,7 @@ .global _tx_thread_schedule .global _tx_thread_preempt_disable .global _tx_execution_isr_exit -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) .global _tx_execution_isr_exit #endif @ @@ -74,17 +74,6 @@ @/* */ @/* ISRs Interrupt Service Routines */ @/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 09-30-2020 Scott Larson Modified comment(s), and */ -@/* cleaned up whitespace, */ -@/* resulting in version 6.1 */ -@/* 03-08-2023 Scott Larson Include tx_user.h, */ -@/* resulting in version 6.2.1 */ -@/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) @{ diff --git a/ports/cortex_m0/gnu/src/tx_thread_context_save.S b/ports/cortex_m0/gnu/src/tx_thread_context_save.S index c7c6a142..9866da13 100644 --- a/ports/cortex_m0/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m0/gnu/src/tx_thread_context_save.S @@ -1,10 +1,10 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @@ -65,17 +65,6 @@ @/* */ @/* ISRs */ @/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 09-30-2020 Scott Larson Modified comment(s), and */ -@/* cleaned up whitespace, */ -@/* resulting in version 6.1 */ -@/* 03-08-2023 Scott Larson Include tx_user.h, */ -@/* resulting in version 6.2.1 */ -@/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) @{ @@ -83,7 +72,7 @@ .thumb_func _tx_thread_context_save: @ -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) /* Call the ISR enter function to indicate an ISR is starting. */ PUSH {r0, lr} // Save return address BL _tx_execution_isr_enter // Call the ISR enter function @@ -91,6 +80,6 @@ _tx_thread_context_save: #endif /* Context is already saved - just return. */ - + BX lr @} diff --git a/ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S index 3fc8cc23..cc79fb79 100644 --- a/ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,10 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @@ -58,16 +58,6 @@ @/* */ @/* Application Code */ @/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 09-30-2020 William E. Lamie Modified comment(s), */ -@/* resulting in version 6.1 */ -@/* 03-08-2023 Scott Larson Include tx_user.h, */ -@/* resulting in version 6.2.1 */ -@/* */ @/**************************************************************************/ @/* UINT _tx_thread_interrupt_control(UINT new_posture) { */ diff --git a/ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S index fd3a0ae8..126893d4 100644 --- a/ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,10 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @@ -57,16 +57,6 @@ @/* */ @/* Application Code */ @/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 09-30-2020 William E. Lamie Modified comment(s), */ -@/* resulting in version 6.1 */ -@/* 03-08-2023 Scott Larson Include tx_user.h, */ -@/* resulting in version 6.2.1 */ -@/* */ @/**************************************************************************/ @/* UINT _tx_thread_interrupt_disable(VOID) { */ diff --git a/ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S index 41c5dd21..567ae747 100644 --- a/ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,10 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @@ -58,16 +58,6 @@ @/* */ @/* Application Code */ @/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 09-30-2020 William E. Lamie Modified comment(s), */ -@/* resulting in version 6.1 */ -@/* 03-08-2023 Scott Larson Include tx_user.h, */ -@/* resulting in version 6.2.1 */ -@/* */ @/**************************************************************************/ @/* VOID _tx_thread_interrupt_restore(UINT old_posture) { */ diff --git a/ports/cortex_m0/gnu/src/tx_thread_schedule.S b/ports/cortex_m0/gnu/src/tx_thread_schedule.S index 46d9f8ba..21b6118a 100644 --- a/ports/cortex_m0/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m0/gnu/src/tx_thread_schedule.S @@ -1,10 +1,10 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @@ -72,19 +72,6 @@ @/* _tx_thread_system_return Return to system from thread */ @/* _tx_thread_context_restore Restore thread's context */ @/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 09-30-2020 William E. Lamie Modified comment(s), */ -@/* resulting in version 6.1 */ -@/* 03-02-2021 Scott Larson Modified comment(s), add */ -@/* low power code, */ -@/* resulting in version 6.1.5 */ -@/* 03-08-2023 Scott Larson Include tx_user.h, */ -@/* resulting in version 6.2.1 */ -@/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) @{ @@ -139,7 +126,7 @@ __tx_SVCallHandler: .thumb_func __tx_ts_handler: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) @ @ /* Call the thread exit function to indicate the thread is no longer executing. */ @ @@ -222,7 +209,7 @@ __tx_ts_restore: @ STR r5, [r4] @ Setup global time-slice -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) @ @ /* Call the thread entry function to indicate the thread is executing. */ @ diff --git a/ports/cortex_m0/gnu/src/tx_thread_stack_build.S b/ports/cortex_m0/gnu/src/tx_thread_stack_build.S index fee960e3..deef33dd 100644 --- a/ports/cortex_m0/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m0/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,10 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @@ -59,20 +59,6 @@ @/* */ @/* _tx_thread_create Create thread service */ @/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 09-30-2020 William E. Lamie Modified Comment(s), setting */ -@/* R10 to top of stack is not */ -@/* needed. Removed references */ -@/* to stack frame, clean up */ -@/* whitespace, resulting */ -@/* in version 6.1 */ -@/* 03-08-2023 Scott Larson Include tx_user.h, */ -@/* resulting in version 6.2.1 */ -@/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @{ diff --git a/ports/cortex_m0/gnu/src/tx_thread_system_return.S b/ports/cortex_m0/gnu/src/tx_thread_system_return.S index cef9159f..d798994e 100644 --- a/ports/cortex_m0/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m0/gnu/src/tx_thread_system_return.S @@ -1,10 +1,10 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @@ -59,16 +59,6 @@ @/* */ @/* ThreadX components */ @/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 09-30-2020 William E. Lamie Modified comment(s), */ -@/* resulting in version 6.1 */ -@/* 03-08-2023 Scott Larson Include tx_user.h, */ -@/* resulting in version 6.2.1 */ -@/* */ @/**************************************************************************/ @/* VOID _tx_thread_system_return(VOID) @{ */ diff --git a/ports/cortex_m0/gnu/src/tx_timer_interrupt.S b/ports/cortex_m0/gnu/src/tx_timer_interrupt.S index 3b64e055..434edc60 100644 --- a/ports/cortex_m0/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_m0/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,10 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @@ -72,16 +72,6 @@ @/* */ @/* interrupt vector */ @/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 09-30-2020 William E. Lamie Modified comment(s), */ -@/* resulting in version 6.1 */ -@/* 03-08-2023 Scott Larson Include tx_user.h, */ -@/* resulting in version 6.2.1 */ -@/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) @{ diff --git a/ports/cortex_m0/iar/CMakeLists.txt b/ports/cortex_m0/iar/CMakeLists.txt index a524d79f..57be3aeb 100644 --- a/ports/cortex_m0/iar/CMakeLists.txt +++ b/ports/cortex_m0/iar/CMakeLists.txt @@ -7,7 +7,7 @@ target_sources(${PROJECT_NAME} ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_disable.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_restore.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_restore.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S diff --git a/ports/cortex_m0/iar/example_build/cstartup_M.s b/ports/cortex_m0/iar/example_build/cstartup_M.s index a498443c..3ae600b5 100644 --- a/ports/cortex_m0/iar/example_build/cstartup_M.s +++ b/ports/cortex_m0/iar/example_build/cstartup_M.s @@ -2,16 +2,16 @@ PUBLIC __vector_table SECTION .text:CODE:REORDER(1) - + ;; Keep vector table even if it's not referenced REQUIRE __vector_table - + THUMB - + ;; Forward declaration of sections. SECTION CSTACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) - + DATA __vector_table @@ -53,7 +53,7 @@ __vector_table __Reset_Vector: CPSID i ; Disable interrupts LDR r0, =__iar_program_start - BX r0 + BX r0 NMI_Handler HardFault_Handler diff --git a/ports/cortex_m0/iar/example_build/sample_threadx.c b/ports/cortex_m0/iar/example_build/sample_threadx.c index 95ff3a47..8f1d9757 100644 --- a/ports/cortex_m0/iar/example_build/sample_threadx.c +++ b/ports/cortex_m0/iar/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -85,7 +85,7 @@ CHAR *pointer; #ifdef TX_ENABLE_EVENT_TRACE tx_trace_enable(trace_buffer, sizeof(trace_buffer), 32); #endif - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(&byte_pool_0, "byte pool 0", byte_pool_memory, DEMO_BYTE_POOL_SIZE); @@ -96,42 +96,42 @@ CHAR *pointer; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -139,23 +139,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -258,11 +258,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -321,7 +321,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -374,7 +374,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s b/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s index 19469eae..cec6e9b2 100644 --- a/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -74,12 +74,6 @@ __tx_free_memory_start ;/* */ ;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) ;{ diff --git a/ports/cortex_m0/iar/inc/tx_port.h b/ports/cortex_m0/iar/inc/tx_port.h index 76e6abca..af5f58bb 100644 --- a/ports/cortex_m0/iar/inc/tx_port.h +++ b/ports/cortex_m0/iar/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,18 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -64,7 +53,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -117,7 +106,7 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY +#ifndef TX_TIMER_THREAD_PRIORITY #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -128,8 +117,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0 /* Enable interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0x0a800024) @@ -168,7 +157,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -182,17 +171,17 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -206,11 +195,11 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -220,23 +209,23 @@ ULONG _tx_misra_time_stamp_get(VOID); #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #if (__VER__ < 8000000) -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #endif #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -265,7 +254,7 @@ void __iar_Initlocks(void); /* Define the get system state macro. */ - + #ifndef TX_THREAD_GET_SYSTEM_STATE #ifndef TX_MISRA_ENABLE #define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __get_IPSR()) @@ -282,19 +271,19 @@ ULONG _tx_misra_ipsr_get(VOID); zero after initialization for Cortex-M ports. */ #ifndef TX_THREAD_SYSTEM_RETURN_CHECK -#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); #endif -/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to prevent early scheduling on Cortex-M parts. */ - + #define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -348,8 +337,8 @@ __istate_t interrupt_save; /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M0/IAR Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0/IAR Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m0/iar/readme_threadx.txt b/ports/cortex_m0/iar/readme_threadx.txt index 580a0736..2d255bfa 100644 --- a/ports/cortex_m0/iar/readme_threadx.txt +++ b/ports/cortex_m0/iar/readme_threadx.txt @@ -1,14 +1,14 @@ - Microsoft's Azure RTOS ThreadX for Cortex-M0 + Microsoft's Azure RTOS ThreadX for Cortex-M0 Using the IAR Tools 1. Building the ThreadX run-time Library Building the ThreadX library is easy. First, open the Azure RTOS workspace -azure_rtos.eww. Next, make the TX project the "active project" in the -IAR Embedded Workbench and select the "Make" button. You should observe -assembly and compilation of a series of ThreadX source files. This -results in the ThreadX run-time library file tx.a, which is needed by +azure_rtos.eww. Next, make the TX project the "active project" in the +IAR Embedded Workbench and select the "Make" button. You should observe +assembly and compilation of a series of ThreadX source files. This +results in the ThreadX run-time library file tx.a, which is needed by the application. @@ -18,31 +18,31 @@ The ThreadX demonstration is designed to execute under the IAR Windows-based Cortex-M0 simulator. Building the demonstration is easy; simply make the sample_threadx.ewp project -the "active project" in the IAR Embedded Workbench and select the +the "active project" in the IAR Embedded Workbench and select the "Make" button. -You should observe the compilation of sample_threadx.c (which is the demonstration +You should observe the compilation of sample_threadx.c (which is the demonstration application) and linking with tx.a. The resulting file sample_threadx.out is a binary file that can be downloaded and executed on IAR's Cortex-M0 simulator. 3. System Initialization -The entry point in ThreadX for the Cortex-M0 using IAR tools is at label -__iar_program_start. This is defined within the IAR compiler's startup code. -In addition, this is where all static and global preset C variable +The entry point in ThreadX for the Cortex-M0 using IAR tools is at label +__iar_program_start. This is defined within the IAR compiler's startup code. +In addition, this is where all static and global preset C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, and a periodic timer interrupt source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. By default, the vector area is defined at the top of cstartup_M.s, which is -a slightly modified from the base IAR file. +a slightly modified from the base IAR file. The _tx_initialize_low_level function inside of tx_initialize_low_level.s -also determines the first available address for use by the application, which -is supplied as the sole input parameter to your application definition function, -tx_application_define. To accomplish this, a section is created in -tx_initialize_low_level.s called FREE_MEM, which must be located after all +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all other RAM sections in memory. @@ -51,54 +51,54 @@ other RAM sections in memory. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M0 version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. - Stack Offset Stack Contents + Stack Offset Stack Contents 0x00 LR Interrupted LR (LR at time of PENDSV) - 0x04 r4 - 0x08 r5 - 0x0C r6 - 0x10 r7 - 0x14 r8 - 0x18 r9 - 0x1C r10 (sl) - 0x20 r11 + 0x04 r4 + 0x08 r5 + 0x0C r6 + 0x10 r7 + 0x14 r8 + 0x18 r9 + 0x1C r10 (sl) + 0x20 r11 0x24 r0 (Hardware stack starts here!!) - 0x28 r1 - 0x2C r2 - 0x30 r3 - 0x34 r12 - 0x38 lr - 0x3C pc - 0x40 xPSR + 0x28 r1 + 0x2C r2 + 0x30 r3 + 0x34 r12 + 0x38 lr + 0x3C pc + 0x40 xPSR 5. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the ThreadX library -project to enable various compiler optimizations. +project to enable various compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M3 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 6.1 Vector Area -The Cortex-M3 vectors start at the label __vector_table and is defined in cstartup_M.s. +The Cortex-M3 vectors start at the label __vector_table and is defined in cstartup_M.s. The application may modify the vector area according to its needs. @@ -138,7 +138,7 @@ should have the following line added (if not already in place): initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application -The project options "General Options -> Library Configuration" should also have the +The project options "General Options -> Library Configuration" should also have the "Enable thread support in library" box selected. diff --git a/ports/cortex_m0/iar/src/tx_iar.c b/ports/cortex_m0/iar/src/tx_iar.c index ee47f10f..238b485e 100644 --- a/ports/cortex_m0/iar/src/tx_iar.c +++ b/ports/cortex_m0/iar/src/tx_iar.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports/cortex_m0/iar/src/tx_thread_context_restore.s b/ports/cortex_m0/iar/src/tx_thread_context_restore.s index b2fb8162..3bd0af0c 100644 --- a/ports/cortex_m0/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_m0/iar/src/tx_thread_context_restore.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -67,19 +67,13 @@ ;/* */ ;/* ISRs Interrupt Service Routines */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) ;{ PUBLIC _tx_thread_context_restore _tx_thread_context_restore: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) ; ; /* Call the ISR exit function to indicate an ISR is complete. */ ; diff --git a/ports/cortex_m0/iar/src/tx_thread_context_save.s b/ports/cortex_m0/iar/src/tx_thread_context_save.s index 9463b229..1d4d5a1b 100644 --- a/ports/cortex_m0/iar/src/tx_thread_context_save.s +++ b/ports/cortex_m0/iar/src/tx_thread_context_save.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -61,18 +61,12 @@ ;/* */ ;/* ISRs */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) ;{ PUBLIC _tx_thread_context_save _tx_thread_context_save: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) ; ; /* Call the ISR enter function to indicate an ISR is starting. */ ; diff --git a/ports/cortex_m0/iar/src/tx_thread_interrupt_control.s b/ports/cortex_m0/iar/src/tx_thread_interrupt_control.s index 01fbb194..261b1c61 100644 --- a/ports/cortex_m0/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m0/iar/src/tx_thread_interrupt_control.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -53,12 +53,6 @@ ;/* */ ;/* Application Code */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) ;{ diff --git a/ports/cortex_m0/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m0/iar/src/tx_thread_interrupt_disable.s index f64aff1f..3c508fa6 100644 --- a/ports/cortex_m0/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m0/iar/src/tx_thread_interrupt_disable.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -53,12 +53,6 @@ ;/* */ ;/* Application Code */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) ;{ diff --git a/ports/cortex_m0/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_m0/iar/src/tx_thread_interrupt_restore.s index b08efc47..5d76a72e 100644 --- a/ports/cortex_m0/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m0/iar/src/tx_thread_interrupt_restore.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -53,12 +53,6 @@ ;/* */ ;/* Application Code */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) ;{ diff --git a/ports/cortex_m0/iar/src/tx_thread_schedule.s b/ports/cortex_m0/iar/src/tx_thread_schedule.s index b5f05400..8458193e 100644 --- a/ports/cortex_m0/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m0/iar/src/tx_thread_schedule.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -69,15 +69,6 @@ ;/* _tx_thread_system_return Return to system from thread */ ;/* _tx_thread_context_restore Restore thread's context */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 03-02-2021 Scott Larson Modified comment(s), add */ -;/* low power code, */ -;/* resulting in version 6.1.5 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) ;{ @@ -123,7 +114,7 @@ __tx_PendSVHandler: ; __tx_ts_handler: -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) ; ; /* Call the thread exit function to indicate the thread is no longer executing. */ ; @@ -207,7 +198,7 @@ __tx_ts_restore: ; STR r5, [r4] ; Setup global time-slice -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) ; ; /* Call the thread entry function to indicate the thread is executing. */ ; diff --git a/ports/cortex_m0/iar/src/tx_thread_stack_build.s b/ports/cortex_m0/iar/src/tx_thread_stack_build.s index 508ccc6d..6c700585 100644 --- a/ports/cortex_m0/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_m0/iar/src/tx_thread_stack_build.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -55,12 +55,6 @@ ;/* */ ;/* _tx_thread_create Create thread service */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) ;{ diff --git a/ports/cortex_m0/iar/src/tx_thread_system_return.s b/ports/cortex_m0/iar/src/tx_thread_system_return.s index 8a878783..da8a481e 100644 --- a/ports/cortex_m0/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m0/iar/src/tx_thread_system_return.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -55,12 +55,6 @@ ;/* */ ;/* ThreadX components */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) ;{ diff --git a/ports/cortex_m0/iar/src/tx_timer_interrupt.s b/ports/cortex_m0/iar/src/tx_timer_interrupt.s index 8e163a89..25774db7 100644 --- a/ports/cortex_m0/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_m0/iar/src/tx_timer_interrupt.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -71,12 +71,6 @@ ;/* */ ;/* interrupt vector */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) ;{ diff --git a/ports/cortex_m0/keil/example_build/sample_threadx.c b/ports/cortex_m0/keil/example_build/sample_threadx.c index 4d95c2ed..dd5ee155 100644 --- a/ports/cortex_m0/keil/example_build/sample_threadx.c +++ b/ports/cortex_m0/keil/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s b/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s index f1a83341..b16b3e20 100644 --- a/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -120,12 +120,6 @@ Reset_Handler ;/* */ ;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) ;{ diff --git a/ports/cortex_m0/keil/inc/tx_port.h b/ports/cortex_m0/keil/inc/tx_port.h index e2d40a62..f163f1c6 100644 --- a/ports/cortex_m0/keil/inc/tx_port.h +++ b/ports/cortex_m0/keil/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,18 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -64,7 +53,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -113,7 +102,7 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY +#ifndef TX_TIMER_THREAD_PRIORITY #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -124,8 +113,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0 /* Enable interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0x0a800024) @@ -164,7 +153,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -178,13 +167,13 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -198,11 +187,11 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -210,10 +199,10 @@ ULONG _tx_misra_time_stamp_get(VOID); tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) -#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) #ifndef TX_MISRA_ENABLE @@ -246,7 +235,7 @@ register unsigned int _ipsr __asm("ipsr"); /* Define the get system state macro. */ - + #ifndef TX_THREAD_GET_SYSTEM_STATE #ifndef TX_MISRA_ENABLE #define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _ipsr) @@ -263,19 +252,19 @@ ULONG _tx_misra_ipsr_get(VOID); zero after initialization for Cortex-M ports. */ #ifndef TX_THREAD_SYSTEM_RETURN_CHECK -#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); #endif -/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to prevent early scheduling on Cortex-M parts. */ - + #define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -322,8 +311,8 @@ unsigned int was_masked; /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M0/AC5 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0/AC5 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m0/keil/readme_threadx.txt b/ports/cortex_m0/keil/readme_threadx.txt index b1c1c0fd..e58cf259 100644 --- a/ports/cortex_m0/keil/readme_threadx.txt +++ b/ports/cortex_m0/keil/readme_threadx.txt @@ -1,32 +1,32 @@ - Microsoft's Azure RTOS ThreadX for Cortex-M0 + Microsoft's Azure RTOS ThreadX for Cortex-M0 Using ARM Compiler 5 (AC5) and Keil Microcontroller Development Kit 1. Building the ThreadX run-time Library -Building the ThreadX library is easy, simply load the project file -tx.uvprojx, which is located inside the "example_build" directory. +Building the ThreadX library is easy, simply load the project file +tx.uvprojx, which is located inside the "example_build" directory. Once the ThreadX library files are displayed in the project window, select the "Build Target" operation and observe the compilation and assembly -of the ThreadX library. This project build produces the ThreadX library +of the ThreadX library. This project build produces the ThreadX library file tx.lib. 2. Demonstration System The ThreadX demonstration is designed to execute under the Keil simulator or -Cortex-M0 hardware. This demonstration is slightly smaller than typical ThreadX +Cortex-M0 hardware. This demonstration is slightly smaller than typical ThreadX demonstrations, and thus requires less than 7KB of Flash and less than 4KB of RAM. -Building the demonstration is easy; simply open the ThreadX demonstration -project file sample_threadx.uvprojx, which is located inside the "example_build" -directory. +Building the demonstration is easy; simply open the ThreadX demonstration +project file sample_threadx.uvprojx, which is located inside the "example_build" +directory. -Once open, select the "Build Target" operation and observe the compilation of -sample_threadx.c (which is the demonstration application) and linking with +Once open, select the "Build Target" operation and observe the compilation of +sample_threadx.c (which is the demonstration application) and linking with tx.lib. The resulting file sample_threadx.axf is a binary file that can be downloaded -and executed under the uVision simulator or Cortex-M0 hardware. +and executed under the uVision simulator or Cortex-M0 hardware. For simulator execution, the following memory regions need to be defined via the "Debug -> Memory Map" dialog: @@ -37,17 +37,17 @@ the "Debug -> Memory Map" dialog: 3. System Initialization -The entry point in ThreadX for the Cortex-M0 using AC5 tools is at label -__main. This is defined within the AC5 compiler's startup code. In -addition, this is where all static and global pre-set C variable +The entry point in ThreadX for the Cortex-M0 using AC5 tools is at label +__main. This is defined within the AC5 compiler's startup code. In +addition, this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. @@ -56,11 +56,11 @@ parameter to your application definition function, tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M0 version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. - Stack Offset Stack Contents + Stack Offset Stack Contents 0x00 r8 0x04 r9 @@ -82,21 +82,21 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. 5. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make it run faster, you can change the build_threadx.bat file to -remove the -g option and enable all compiler optimizations. +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M0 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: diff --git a/ports/cortex_m0/keil/src/tx_thread_context_restore.s b/ports/cortex_m0/keil/src/tx_thread_context_restore.s index 15e74269..6723cd19 100644 --- a/ports/cortex_m0/keil/src/tx_thread_context_restore.s +++ b/ports/cortex_m0/keil/src/tx_thread_context_restore.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -20,10 +20,10 @@ ;/**************************************************************************/ ; ; -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) IMPORT _tx_execution_isr_exit #endif - + ; AREA ||.text||, CODE, READONLY PRESERVE8 @@ -62,19 +62,13 @@ ;/* */ ;/* ISRs Interrupt Service Routines */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) ;{ EXPORT _tx_thread_context_restore _tx_thread_context_restore -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) ; ; /* Call the ISR exit function to indicate an ISR is complete. */ ; diff --git a/ports/cortex_m0/keil/src/tx_thread_context_save.s b/ports/cortex_m0/keil/src/tx_thread_context_save.s index 3245b512..d0c2c9e4 100644 --- a/ports/cortex_m0/keil/src/tx_thread_context_save.s +++ b/ports/cortex_m0/keil/src/tx_thread_context_save.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -20,7 +20,7 @@ ;/**************************************************************************/ ; ; -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) IMPORT _tx_execution_isr_enter #endif ; @@ -61,18 +61,12 @@ ;/* */ ;/* ISRs */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) ;{ EXPORT _tx_thread_context_save _tx_thread_context_save -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) ; ; /* Call the ISR enter function to indicate an ISR is executing. */ ; diff --git a/ports/cortex_m0/keil/src/tx_thread_interrupt_control.s b/ports/cortex_m0/keil/src/tx_thread_interrupt_control.s index a8504791..be0da62d 100644 --- a/ports/cortex_m0/keil/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m0/keil/src/tx_thread_interrupt_control.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -52,12 +52,6 @@ ;/* */ ;/* Application Code */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) ;{ diff --git a/ports/cortex_m0/keil/src/tx_thread_interrupt_disable.s b/ports/cortex_m0/keil/src/tx_thread_interrupt_disable.s index aac316ea..86ab4562 100644 --- a/ports/cortex_m0/keil/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m0/keil/src/tx_thread_interrupt_disable.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -52,12 +52,6 @@ ;/* */ ;/* Application Code */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) ;{ diff --git a/ports/cortex_m0/keil/src/tx_thread_interrupt_restore.s b/ports/cortex_m0/keil/src/tx_thread_interrupt_restore.s index b94b9e7b..8e71728a 100644 --- a/ports/cortex_m0/keil/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m0/keil/src/tx_thread_interrupt_restore.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -52,12 +52,6 @@ ;/* */ ;/* Application Code */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) ;{ diff --git a/ports/cortex_m0/keil/src/tx_thread_schedule.s b/ports/cortex_m0/keil/src/tx_thread_schedule.s index f9fa8184..f900848b 100644 --- a/ports/cortex_m0/keil/src/tx_thread_schedule.s +++ b/ports/cortex_m0/keil/src/tx_thread_schedule.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -25,7 +25,7 @@ IMPORT _tx_timer_time_slice IMPORT _tx_thread_system_stack_ptr IMPORT _tx_thread_preempt_disable -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) IMPORT _tx_execution_thread_enter IMPORT _tx_execution_thread_exit #endif @@ -71,15 +71,6 @@ ;/* _tx_thread_system_return Return to system from thread */ ;/* _tx_thread_context_restore Restore thread's context */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 03-02-2021 Scott Larson Modified comment(s), add */ -;/* low power code, */ -;/* resulting in version 6.1.5 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) ;{ @@ -126,7 +117,7 @@ __tx_PendSVHandler ; __tx_ts_handler -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) ; ; /* Call the thread exit function to indicate the thread is no longer executing. */ ; @@ -210,7 +201,7 @@ __tx_ts_restore ; STR r5, [r4] ; Setup global time-slice -#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) +#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) ; ; /* Call the thread entry function to indicate the thread is executing. */ ; diff --git a/ports/cortex_m0/keil/src/tx_thread_stack_build.s b/ports/cortex_m0/keil/src/tx_thread_stack_build.s index 8324238a..e1cf9d16 100644 --- a/ports/cortex_m0/keil/src/tx_thread_stack_build.s +++ b/ports/cortex_m0/keil/src/tx_thread_stack_build.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -54,12 +54,6 @@ ;/* */ ;/* _tx_thread_create Create thread service */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) ;{ diff --git a/ports/cortex_m0/keil/src/tx_thread_system_return.s b/ports/cortex_m0/keil/src/tx_thread_system_return.s index d37623fc..db1ab63d 100644 --- a/ports/cortex_m0/keil/src/tx_thread_system_return.s +++ b/ports/cortex_m0/keil/src/tx_thread_system_return.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -54,12 +54,6 @@ ;/* */ ;/* ThreadX components */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) ;{ diff --git a/ports/cortex_m0/keil/src/tx_timer_interrupt.s b/ports/cortex_m0/keil/src/tx_timer_interrupt.s index e6ebbc76..b712487f 100644 --- a/ports/cortex_m0/keil/src/tx_timer_interrupt.s +++ b/ports/cortex_m0/keil/src/tx_timer_interrupt.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -71,12 +71,6 @@ ;/* */ ;/* interrupt vector */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) ;{ diff --git a/ports/cortex_m23/ac6/example_build/ARMCM23_TZ_config.txt b/ports/cortex_m23/ac6/example_build/ARMCM23_TZ_config.txt index 0d31ad76..3ea82e17 100644 --- a/ports/cortex_m23/ac6/example_build/ARMCM23_TZ_config.txt +++ b/ports/cortex_m23/ac6/example_build/ARMCM23_TZ_config.txt @@ -2,7 +2,7 @@ # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic diff --git a/ports/cortex_m23/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h b/ports/cortex_m23/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h index 476361d7..66e03dff 100644 --- a/ports/cortex_m23/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h +++ b/ports/cortex_m23/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'ThreadX_Library' - * Target: 'ThreadX_Library_Project' + * Project: 'ThreadX_Library' + * Target: 'ThreadX_Library_Project' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM23_TZ.h" diff --git a/ports/cortex_m23/ac6/example_build/demo_secure_zone/Abstract.txt b/ports/cortex_m23/ac6/example_build/demo_secure_zone/Abstract.txt index 0d1d8c52..f2b8a819 100644 --- a/ports/cortex_m23/ac6/example_build/demo_secure_zone/Abstract.txt +++ b/ports/cortex_m23/ac6/example_build/demo_secure_zone/Abstract.txt @@ -1,10 +1,10 @@ This ARM Cortex-M33 secure/non-secure example project that -shows the setup of the CMSIS-RTOS2 RTX for TrustZone for -ARMv8-M applications. +shows the setup of the CMSIS-RTOS2 RTX for TrustZone for +ARMv8-M applications. The application uses CMSIS and can be executed on a Fixed -Virtual Platform (FVP) simulation model. The application -demonstrates three RTOS threads. +Virtual Platform (FVP) simulation model. The application +demonstrates three RTOS threads. Secure application: diff --git a/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h b/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h index 77383657..6988d132 100644 --- a/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h +++ b/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h @@ -326,7 +326,7 @@ // <0=>Secure // <1=>Non-Secure // Value for SCB->ICSR register bit STTNS -// only for single SysTick implementation +// only for single SysTick implementation */ #define SCB_ICSR_STTNS_VAL 0 diff --git a/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c b/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c index cf78a4ed..a79cb61d 100644 --- a/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c +++ b/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c @@ -77,7 +77,7 @@ void SystemInit (void) #endif SystemCoreClock = SYSTEM_CLOCK; - + *(uint32_t *)0xE000ED24 = 0x000F0000; /* S: enable secure, usage, bus, mem faults */ *(uint32_t *)0xE002ED24 = 0x000F0000; /* NS: enable secure, usage, bus, mem faults */ } diff --git a/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h index a37b412e..40fc81c1 100644 --- a/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h +++ b/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'demo_secure_zone' - * Target: 'FVP Simulation Model' + * Project: 'demo_secure_zone' + * Target: 'FVP Simulation Model' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM23_TZ.h" diff --git a/ports/cortex_m23/ac6/example_build/demo_secure_zone/interface.c b/ports/cortex_m23/ac6/example_build/demo_secure_zone/interface.c index 4e6e8eee..af6533c3 100644 --- a/ports/cortex_m23/ac6/example_build/demo_secure_zone/interface.c +++ b/ports/cortex_m23/ac6/example_build/demo_secure_zone/interface.c @@ -31,19 +31,19 @@ typedef funcptr funcptr_NS __attribute__((cmse_nonsecure_call)); /* Non-secure callable (entry) function */ -int func1(int x) __attribute__((cmse_nonsecure_entry)) { - return x+3; +int func1(int x) __attribute__((cmse_nonsecure_entry)) { + return x+3; } /* Non-secure callable (entry) function, calling a non-secure callback function */ int func2(funcptr callback, int x) __attribute__((cmse_nonsecure_entry)) { funcptr_NS callback_NS; // non-secure callback function pointer int y; - + /* return function pointer with cleared LSB */ callback_NS = (funcptr_NS)cmse_nsfptr_create(callback); - + y = callback_NS (x+1); - + return (y+2); } diff --git a/ports/cortex_m23/ac6/example_build/demo_secure_zone/main_ns.c b/ports/cortex_m23/ac6/example_build/demo_secure_zone/main_ns.c index 5d16e1bb..31ca367c 100644 --- a/ports/cortex_m23/ac6/example_build/demo_secure_zone/main_ns.c +++ b/ports/cortex_m23/ac6/example_build/demo_secure_zone/main_ns.c @@ -63,7 +63,7 @@ void ThreadA (void *argument) { static int callbackB (int val) { uint32_t flags; - + flags = osThreadFlagsWait (1U, osFlagsWaitAny, osWaitForever); if (flags == 1U) { return (val+1); diff --git a/ports/cortex_m23/ac6/example_build/demo_secure_zone/main_s.c b/ports/cortex_m23/ac6/example_build/demo_secure_zone/main_s.c index 2c667821..74fa242e 100644 --- a/ports/cortex_m23/ac6/example_build/demo_secure_zone/main_s.c +++ b/ports/cortex_m23/ac6/example_build/demo_secure_zone/main_s.c @@ -24,36 +24,36 @@ * Title: Code template for secure main function * *---------------------------------------------------------------------------*/ - + /* Use CMSE intrinsics */ #include #include #include "RTE_Components.h" #include CMSIS_device_header - + /* TZ_START_NS: Start address of non-secure application */ #ifndef TZ_START_NS #define TZ_START_NS (0x200000U) #endif - + /* typedef for non-secure callback functions */ typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call)); - + /* Secure main() */ int main(void) { funcptr_void NonSecure_ResetHandler; - + /* Add user setup code for secure part here*/ - + /* Set non-secure main stack (MSP_NS) */ __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS))); - + /* Get non-secure reset handler */ NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U))); - + /* Start non-secure state software application */ NonSecure_ResetHandler(); - + /* Non-secure software does not return, this code is not executed */ while (1) { __NOP(); diff --git a/ports/cortex_m23/ac6/example_build/demo_secure_zone/tx_secure_interface.h b/ports/cortex_m23/ac6/example_build/demo_secure_zone/tx_secure_interface.h index b5a76bfb..63f683c1 100644 --- a/ports/cortex_m23/ac6/example_build/demo_secure_zone/tx_secure_interface.h +++ b/ports/cortex_m23/ac6/example_build/demo_secure_zone/tx_secure_interface.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,12 +38,6 @@ /* It is assumed that tx_api.h and tx_port.h have already been */ /* included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_SECURE_INTERFACE_H diff --git a/ports/cortex_m23/ac6/example_build/demo_secure_zone/tz_context.c b/ports/cortex_m23/ac6/example_build/demo_secure_zone/tz_context.c index f3152890..ca7f0c56 100644 --- a/ports/cortex_m23/ac6/example_build/demo_secure_zone/tz_context.c +++ b/ports/cortex_m23/ac6/example_build/demo_secure_zone/tz_context.c @@ -24,7 +24,7 @@ * Title: Context Management for ARMv8-M TrustZone - Sample implementation * *---------------------------------------------------------------------------*/ - + #include "RTE_Components.h" #include CMSIS_device_header #include "tz_context.h" diff --git a/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c index e4871014..d0f6b08b 100644 --- a/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c +++ b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c @@ -24,17 +24,17 @@ * * ----------------------------------------------------------------------------- */ - + #include "cmsis_compiler.h" #include "rtx_os.h" - + // OS Idle Thread __WEAK __NO_RETURN void osRtxIdleThread (void *argument) { (void)argument; for (;;) {} } - + // OS Error Callback function __WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { (void)object_id; diff --git a/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h index 3021efbc..49fc392e 100644 --- a/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h +++ b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h @@ -24,52 +24,52 @@ * * ----------------------------------------------------------------------------- */ - + #ifndef RTX_CONFIG_H_ #define RTX_CONFIG_H_ - + #ifdef _RTE_ #include "RTE_Components.h" #ifdef RTE_RTX_CONFIG_H #include RTE_RTX_CONFIG_H #endif #endif - + //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - + // System Configuration // ======================= - + // Global Dynamic Memory size [bytes] <0-1073741824:8> // Defines the combined global dynamic memory size. // Default: 4096 #ifndef OS_DYNAMIC_MEM_SIZE #define OS_DYNAMIC_MEM_SIZE 4096 #endif - + // Kernel Tick Frequency [Hz] <1-1000000> // Defines base time unit for delays and timeouts. // Default: 1000 (1ms tick) #ifndef OS_TICK_FREQ #define OS_TICK_FREQ 1000 #endif - + // Round-Robin Thread switching // Enables Round-Robin Thread switching. #ifndef OS_ROBIN_ENABLE #define OS_ROBIN_ENABLE 1 #endif - + // Round-Robin Timeout <1-1000> // Defines how many ticks a thread will execute before a thread switch. // Default: 5 #ifndef OS_ROBIN_TIMEOUT #define OS_ROBIN_TIMEOUT 5 #endif - + // - -// ISR FIFO Queue + +// ISR FIFO Queue // <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries // <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries // <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries @@ -78,38 +78,38 @@ #ifndef OS_ISR_FIFO_QUEUE #define OS_ISR_FIFO_QUEUE 16 #endif - + // Object Memory usage counters // Enables object memory usage counters (requires RTX source variant). #ifndef OS_OBJ_MEM_USAGE #define OS_OBJ_MEM_USAGE 0 #endif - + // - + // Thread Configuration // ======================= - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_THREAD_OBJ_MEM #define OS_THREAD_OBJ_MEM 0 #endif - + // Number of user Threads <1-1000> // Defines maximum number of user threads that can be active at the same time. // Applies to user threads with system provided memory for control blocks. #ifndef OS_THREAD_NUM #define OS_THREAD_NUM 1 #endif - + // Number of user Threads with default Stack size <0-1000> // Defines maximum number of user threads with default stack size. // Applies to user threads with zero stack size specified. #ifndef OS_THREAD_DEF_STACK_NUM #define OS_THREAD_DEF_STACK_NUM 0 #endif - + // Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> // Defines the combined stack size for user threads with user-provided stack size. // Applies to user threads with user-provided stack size and system provided memory for stack. @@ -117,23 +117,23 @@ #ifndef OS_THREAD_USER_STACK_SIZE #define OS_THREAD_USER_STACK_SIZE 0 #endif - + // - + // Default Thread Stack size [bytes] <96-1073741824:8> // Defines stack size for threads with zero stack size specified. // Default: 256 #ifndef OS_STACK_SIZE #define OS_STACK_SIZE 256 #endif - + // Idle Thread Stack size [bytes] <72-1073741824:8> // Defines stack size for Idle thread. // Default: 256 #ifndef OS_IDLE_THREAD_STACK_SIZE #define OS_IDLE_THREAD_STACK_SIZE 256 #endif - + // Idle Thread TrustZone Module Identifier // Defines TrustZone Thread Context Management Identifier. // Applies only to cores with TrustZone technology. @@ -141,49 +141,49 @@ #ifndef OS_IDLE_THREAD_TZ_MOD_ID #define OS_IDLE_THREAD_TZ_MOD_ID 0 #endif - + // Stack overrun checking // Enables stack overrun check at thread switch. // Enabling this option increases slightly the execution time of a thread switch. #ifndef OS_STACK_CHECK #define OS_STACK_CHECK 1 #endif - + // Stack usage watermark // Initializes thread stack with watermark pattern for analyzing stack usage. // Enabling this option increases significantly the execution time of thread creation. #ifndef OS_STACK_WATERMARK #define OS_STACK_WATERMARK 0 #endif - -// Processor mode for Thread execution -// <0=> Unprivileged mode + +// Processor mode for Thread execution +// <0=> Unprivileged mode // <1=> Privileged mode // Default: Privileged mode #ifndef OS_PRIVILEGE_MODE #define OS_PRIVILEGE_MODE 1 #endif - + // - + // Timer Configuration // ====================== - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_TIMER_OBJ_MEM #define OS_TIMER_OBJ_MEM 0 #endif - + // Number of Timer objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_TIMER_NUM #define OS_TIMER_NUM 1 #endif - + // - + // Timer Thread Priority // <8=> Low // <16=> Below Normal <24=> Normal <32=> Above Normal @@ -194,7 +194,7 @@ #ifndef OS_TIMER_THREAD_PRIO #define OS_TIMER_THREAD_PRIO 40 #endif - + // Timer Thread Stack size [bytes] <0-1073741824:8> // Defines stack size for Timer thread. // May be set to 0 when timers are not used. @@ -202,7 +202,7 @@ #ifndef OS_TIMER_THREAD_STACK_SIZE #define OS_TIMER_THREAD_STACK_SIZE 256 #endif - + // Timer Thread TrustZone Module Identifier // Defines TrustZone Thread Context Management Identifier. // Applies only to cores with TrustZone technology. @@ -210,7 +210,7 @@ #ifndef OS_TIMER_THREAD_TZ_MOD_ID #define OS_TIMER_THREAD_TZ_MOD_ID 0 #endif - + // Timer Callback Queue entries <0-256> // Number of concurrent active timer callback functions. // May be set to 0 when timers are not used. @@ -218,85 +218,85 @@ #ifndef OS_TIMER_CB_QUEUE #define OS_TIMER_CB_QUEUE 4 #endif - + // - + // Event Flags Configuration // ============================ - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_EVFLAGS_OBJ_MEM #define OS_EVFLAGS_OBJ_MEM 0 #endif - + // Number of Event Flags objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_EVFLAGS_NUM #define OS_EVFLAGS_NUM 1 #endif - + // - + // - + // Mutex Configuration // ====================== - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_MUTEX_OBJ_MEM #define OS_MUTEX_OBJ_MEM 0 #endif - + // Number of Mutex objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_MUTEX_NUM #define OS_MUTEX_NUM 1 #endif - + // - + // - + // Semaphore Configuration // ========================== - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_SEMAPHORE_OBJ_MEM #define OS_SEMAPHORE_OBJ_MEM 0 #endif - + // Number of Semaphore objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_SEMAPHORE_NUM #define OS_SEMAPHORE_NUM 1 #endif - + // - + // - + // Memory Pool Configuration // ============================ - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_MEMPOOL_OBJ_MEM #define OS_MEMPOOL_OBJ_MEM 0 #endif - + // Number of Memory Pool objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_MEMPOOL_NUM #define OS_MEMPOOL_NUM 1 #endif - + // Data Storage Memory size [bytes] <0-1073741824:8> // Defines the combined data storage memory size. // Applies to objects with system provided memory for data storage. @@ -304,27 +304,27 @@ #ifndef OS_MEMPOOL_DATA_SIZE #define OS_MEMPOOL_DATA_SIZE 0 #endif - + // - + // - + // Message Queue Configuration // ============================== - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_MSGQUEUE_OBJ_MEM #define OS_MSGQUEUE_OBJ_MEM 0 #endif - + // Number of Message Queue objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_MSGQUEUE_NUM #define OS_MSGQUEUE_NUM 1 #endif - + // Data Storage Memory size [bytes] <0-1073741824:8> // Defines the combined data storage memory size. // Applies to objects with system provided memory for data storage. @@ -332,26 +332,26 @@ #ifndef OS_MSGQUEUE_DATA_SIZE #define OS_MSGQUEUE_DATA_SIZE 0 #endif - + // - + // - + // Event Recorder Configuration // =============================== - + // Global Initialization // Initialize Event Recorder during 'osKernelInitialize'. #ifndef OS_EVR_INIT #define OS_EVR_INIT 0 #endif - + // Start recording // Start event recording after initialization. #ifndef OS_EVR_START #define OS_EVR_START 1 #endif - + // Global Event Filter Setup // Initial recording level applied to all components. // Error events @@ -362,11 +362,11 @@ #ifndef OS_EVR_LEVEL #define OS_EVR_LEVEL 0x00U #endif - + // RTOS Event Filter Setup // Recording levels for RTX components. // Only applicable if events for the respective component are generated. - + // Memory Management // Recording level for Memory Management events. // Error events @@ -374,10 +374,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_MEMORY_LEVEL +#ifndef OS_EVR_MEMORY_LEVEL #define OS_EVR_MEMORY_LEVEL 0x01U #endif - + // Kernel // Recording level for Kernel events. // Error events @@ -385,10 +385,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_KERNEL_LEVEL +#ifndef OS_EVR_KERNEL_LEVEL #define OS_EVR_KERNEL_LEVEL 0x01U #endif - + // Thread // Recording level for Thread events. // Error events @@ -396,10 +396,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_THREAD_LEVEL +#ifndef OS_EVR_THREAD_LEVEL #define OS_EVR_THREAD_LEVEL 0x05U #endif - + // Generic Wait // Recording level for Generic Wait events. // Error events @@ -407,10 +407,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_WAIT_LEVEL +#ifndef OS_EVR_WAIT_LEVEL #define OS_EVR_WAIT_LEVEL 0x01U #endif - + // Thread Flags // Recording level for Thread Flags events. // Error events @@ -418,10 +418,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_THFLAGS_LEVEL +#ifndef OS_EVR_THFLAGS_LEVEL #define OS_EVR_THFLAGS_LEVEL 0x01U #endif - + // Event Flags // Recording level for Event Flags events. // Error events @@ -429,10 +429,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_EVFLAGS_LEVEL +#ifndef OS_EVR_EVFLAGS_LEVEL #define OS_EVR_EVFLAGS_LEVEL 0x01U #endif - + // Timer // Recording level for Timer events. // Error events @@ -440,10 +440,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_TIMER_LEVEL +#ifndef OS_EVR_TIMER_LEVEL #define OS_EVR_TIMER_LEVEL 0x01U #endif - + // Mutex // Recording level for Mutex events. // Error events @@ -451,10 +451,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_MUTEX_LEVEL +#ifndef OS_EVR_MUTEX_LEVEL #define OS_EVR_MUTEX_LEVEL 0x01U #endif - + // Semaphore // Recording level for Semaphore events. // Error events @@ -462,10 +462,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_SEMAPHORE_LEVEL +#ifndef OS_EVR_SEMAPHORE_LEVEL #define OS_EVR_SEMAPHORE_LEVEL 0x01U #endif - + // Memory Pool // Recording level for Memory Pool events. // Error events @@ -473,10 +473,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_MEMPOOL_LEVEL +#ifndef OS_EVR_MEMPOOL_LEVEL #define OS_EVR_MEMPOOL_LEVEL 0x01U #endif - + // Message Queue // Recording level for Message Queue events. // Error events @@ -484,87 +484,87 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_MSGQUEUE_LEVEL +#ifndef OS_EVR_MSGQUEUE_LEVEL #define OS_EVR_MSGQUEUE_LEVEL 0x01U #endif - + // - + // - + // RTOS Event Generation // Enables event generation for RTX components (requires RTX source variant). - + // Memory Management // Enables Memory Management event generation. #ifndef OS_EVR_MEMORY #define OS_EVR_MEMORY 1 #endif - + // Kernel // Enables Kernel event generation. #ifndef OS_EVR_KERNEL #define OS_EVR_KERNEL 1 #endif - + // Thread // Enables Thread event generation. #ifndef OS_EVR_THREAD #define OS_EVR_THREAD 1 #endif - + // Generic Wait // Enables Generic Wait event generation. #ifndef OS_EVR_WAIT #define OS_EVR_WAIT 1 #endif - + // Thread Flags // Enables Thread Flags event generation. #ifndef OS_EVR_THFLAGS #define OS_EVR_THFLAGS 1 #endif - + // Event Flags // Enables Event Flags event generation. #ifndef OS_EVR_EVFLAGS #define OS_EVR_EVFLAGS 1 #endif - + // Timer // Enables Timer event generation. #ifndef OS_EVR_TIMER #define OS_EVR_TIMER 1 #endif - + // Mutex // Enables Mutex event generation. #ifndef OS_EVR_MUTEX #define OS_EVR_MUTEX 1 #endif - + // Semaphore // Enables Semaphore event generation. #ifndef OS_EVR_SEMAPHORE #define OS_EVR_SEMAPHORE 1 #endif - + // Memory Pool // Enables Memory Pool event generation. #ifndef OS_EVR_MEMPOOL #define OS_EVR_MEMPOOL 1 #endif - + // Message Queue // Enables Message Queue event generation. #ifndef OS_EVR_MSGQUEUE #define OS_EVR_MSGQUEUE 1 #endif - + // - + // - + // Number of Threads which use standard C/C++ library libspace // (when thread specific memory allocation is not used). #if (OS_THREAD_OBJ_MEM == 0) @@ -572,7 +572,7 @@ #else #define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM #endif - + //------------- <<< end of configuration section >>> --------------------------- - + #endif // RTX_CONFIG_H_ diff --git a/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h index a7a090e7..3cb7eeb4 100644 --- a/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h +++ b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h @@ -326,7 +326,7 @@ // <0=>Secure // <1=>Non-Secure // Value for SCB->ICSR register bit STTNS -// only for single SysTick implementation +// only for single SysTick implementation */ #define SCB_ICSR_STTNS_VAL 0 diff --git a/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h index 1cde6a79..35f9ceae 100644 --- a/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h +++ b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'demo_threadx_non-secure_zone' - * Target: 'FVP Simulation Model' + * Project: 'demo_threadx_non-secure_zone' + * Target: 'FVP Simulation Model' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM23_TZ.h" diff --git a/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h index 476361d7..66e03dff 100644 --- a/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h +++ b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'ThreadX_Library' - * Target: 'ThreadX_Library_Project' + * Project: 'ThreadX_Library' + * Target: 'ThreadX_Library_Project' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM23_TZ.h" diff --git a/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c index 7320b94d..df82f09b 100644 --- a/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c +++ b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete description of this demonstration. */ @@ -69,7 +69,7 @@ void thread_6_and_7_entry(ULONG thread_input); int main() { - + /* Please refer to Chapter 6 of the ThreadX User Guide for a complete description of this demonstration. */ @@ -102,91 +102,91 @@ CHAR *pointer; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate secure stack space for thread. */ tx_thread_secure_stack_allocate(&thread_0,256); - + /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate secure stack space for thread. */ tx_thread_secure_stack_allocate(&thread_1,256); - + /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate secure stack space for thread. */ tx_thread_secure_stack_allocate(&thread_2,256); - + /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate secure stack space for thread. */ tx_thread_secure_stack_allocate(&thread_3,256); - + /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate secure stack space for thread. */ tx_thread_secure_stack_allocate(&thread_4,256); - + /* Allocate the stack for thread 5. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate secure stack space for thread. */ tx_thread_secure_stack_allocate(&thread_5,256); - + /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate secure stack space for thread. */ tx_thread_secure_stack_allocate(&thread_6,256); - + /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate secure stack space for thread. */ tx_thread_secure_stack_allocate(&thread_7,256); - + /* Allocate the message queue. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); @@ -226,9 +226,9 @@ void thread_0_entry(ULONG thread_input) { UINT status; INT test_secure; - + (VOID)thread_input; /* unused parameter. */ - + #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) /* Secure call and callback example. Only to be used when not running in a single mode. */ @@ -236,7 +236,7 @@ INT test_secure; test_secure = func2(callbackA, test_secure); tx_thread_secure_stack_free(&thread_0); #endif - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -263,7 +263,7 @@ void thread_1_entry(ULONG thread_input) UINT status; (VOID)thread_input; /* unused parameter. */ - + /* This thread simply sends messages to a queue shared by thread 2. */ while(1) { @@ -290,7 +290,7 @@ ULONG received_message; UINT status; (VOID)thread_input; /* unused parameter. */ - + /* This thread retrieves messages placed on the queue by thread 1. */ while(1) { @@ -301,11 +301,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -316,7 +316,7 @@ void thread_3_and_4_entry(ULONG thread_input) { UINT status; - + /* This function is executed from thread 3 and thread 4. As the loop below shows, these function compete for ownership of semaphore_0. */ while(1) @@ -355,7 +355,7 @@ UINT status; ULONG actual_flags; (VOID)thread_input; /* unused parameter. */ - + /* This thread simply waits for an event in a forever loop. */ while(1) { @@ -364,7 +364,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -417,7 +417,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_m23/ac6/example_build/tx_initialize_low_level.S b/ports/cortex_m23/ac6/example_build/tx_initialize_low_level.S index 00fd8775..c5565bdd 100644 --- a/ports/cortex_m23/ac6/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m23/ac6/example_build/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ HEAP_SIZE = 0x00000000 /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -103,7 +96,7 @@ _tx_initialize_low_level: // LDR r0, =0xE0001000 // Build address of DWT register // LDR r1, [r0] // Pickup the current value // ORR r1, r1, #1 // Set the CYCCNTENA bit -// STR r1, [r0] // Enable the cycle count register +// STR r1, [r0] // Enable the cycle count register /* Set system stack pointer from vector value. */ LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer @@ -121,21 +114,21 @@ _tx_initialize_low_level: /* Configure handler priorities. */ LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD18 // - ADD r0, r0, r2 // + LDR r2, =0xD18 // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 4-7 Priority Registers LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD1C // - ADD r0, r0, r2 // + LDR r2, =0xD1C // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 8-11 Priority Registers // Note: SVC must be lowest priority, which is 0xFF LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD20 // - ADD r0, r0, r2 // + LDR r2, =0xD20 // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 12-15 Priority Registers // Note: PnSV must be lowest priority, which is 0xFF @@ -216,7 +209,7 @@ HardFault_Handler: // A stack overflow will trigger a hardfault. // There is no CFSR in M23, so we will not try to // determine if the fault is caused by a stack overflow - // or some other condition. + // or some other condition. B HardFault_Handler .end diff --git a/ports/cortex_m23/ac6/inc/tx_port.h b/ports/cortex_m23/ac6/inc/tx_port.h index 4294c29d..5ae0b62b 100644 --- a/ports/cortex_m23/ac6/inc/tx_port.h +++ b/ports/cortex_m23/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,30 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-02-2021 Scott Larson Modified comment(s), added */ -/* ULONG64_DEFINED, */ -/* resulting in version 6.1.5 */ -/* 06-02-2021 Yuxin Zhou Modified comment(s), removed */ -/* unneeded header file, added */ -/* conditional compilation */ -/* for ARMv8-M (Cortex M23/33) */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ -/* stack check error handling, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -74,7 +51,7 @@ /* Determine if the optional ThreadX user define file should be used. */ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -111,17 +88,17 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); #define TX_PORT_THREAD_STACK_ERROR_HANDLING -/* Define the system API mappings based on the error checking - selected by the user. Note: this section is only applicable to +/* Define the system API mappings based on the error checking + selected by the user. Note: this section is only applicable to application source code, hence the conditional that turns off this stuff when the include file is processed by the ThreadX source. */ #ifndef TX_SOURCE_CODE -/* Determine if error checking is desired. If so, map API functions +/* Determine if error checking is desired. If so, map API functions to the appropriate error checking front-ends. Otherwise, map API - functions to the core functions that actually perform the work. + functions to the core functions that actually perform the work. Note: error checking is enabled by default. */ #ifdef TX_DISABLE_ERROR_CHECKING @@ -166,7 +143,7 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY +#ifndef TX_TIMER_THREAD_PRIORITY #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -178,7 +155,7 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); /* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0x0a800024) @@ -217,7 +194,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -231,7 +208,7 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ #define TX_THREAD_EXTENSION_0 @@ -255,7 +232,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION @@ -322,7 +299,7 @@ inline static unsigned int _get_ipsr(void) /* Define the get system state macro. */ - + #ifndef TX_THREAD_GET_SYSTEM_STATE #ifndef TX_MISRA_ENABLE #define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _get_ipsr()) @@ -348,14 +325,14 @@ extern void _tx_thread_secure_stack_initialize(void); #define TX_PORT_SPECIFIC_PRE_INITIALIZATION _tx_thread_secure_stack_initialize(); #endif -/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to prevent early scheduling on Cortex-M parts. */ - + #define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -365,9 +342,9 @@ extern void _tx_thread_secure_stack_initialize(void); #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -413,8 +390,8 @@ unsigned int was_masked; /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M23/AC6 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M23/AC6 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m23/ac6/inc/tx_secure_interface.h b/ports/cortex_m23/ac6/inc/tx_secure_interface.h index fbf20b31..5ac37fbf 100644 --- a/ports/cortex_m23/ac6/inc/tx_secure_interface.h +++ b/ports/cortex_m23/ac6/inc/tx_secure_interface.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,12 +38,6 @@ /* It is assumed that tx_api.h and tx_port.h have already been */ /* included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_SECURE_INTERFACE_H diff --git a/ports/cortex_m23/ac6/readme_threadx.txt b/ports/cortex_m23/ac6/readme_threadx.txt index 787881bc..8169ebc1 100644 --- a/ports/cortex_m23/ac6/readme_threadx.txt +++ b/ports/cortex_m23/ac6/readme_threadx.txt @@ -1,22 +1,22 @@ - Microsoft's Azure RTOS ThreadX for Cortex-M23 + Microsoft's Azure RTOS ThreadX for Cortex-M23 Using the AC6 Tools in Keil uVision 1. Import the ThreadX Projects -In order to build the ThreadX library and the ThreadX demonstration, first open -the AzureRTOS.uvmpw workspace (located in the "example_build" directory) +In order to build the ThreadX library and the ThreadX demonstration, first open +the AzureRTOS.uvmpw workspace (located in the "example_build" directory) into Keil. 2. Building the ThreadX run-time Library Building the ThreadX library is easy; simply set the ThreadX_Library project -as active, then then build the library. You should now observe the compilation +as active, then then build the library. You should now observe the compilation and assembly of the ThreadX library. This project build produces the ThreadX library file ThreadX_Library.lib. -Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c -replace the common files of the same name. +Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c +replace the common files of the same name. 3. Demonstration System @@ -24,24 +24,24 @@ replace the common files of the same name. The ThreadX demonstration is designed to execute under the Keil debugger on the FVP_MPS2_Cortex-M23_MDK simulator. -Building the demonstration is easy; simply select the "Batch Build" button. -You should now observe the compilation and assembly of the ThreadX demonstration of -both the demo_secure_zone and demo_threadx_non-secure_zone projects. +Building the demonstration is easy; simply select the "Batch Build" button. +You should now observe the compilation and assembly of the ThreadX demonstration of +both the demo_secure_zone and demo_threadx_non-secure_zone projects. Then click the Start/Stop Debug Session button to start the simulator and begin debugging. You are now ready to execute the ThreadX demonstration. 4. System Initialization -The entry point in ThreadX for the Cortex-M23 using AC6 tools uses the standard AC6 +The entry point in ThreadX for the Cortex-M23 using AC6 tools uses the standard AC6 Cortex-M23 reset sequence. From the reset vector the C runtime will be initialized. -The ThreadX tx_initialize_low_level.S file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. +The ThreadX tx_initialize_low_level.S file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. @@ -50,11 +50,11 @@ parameter to your application definition function, tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M23 version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. - Stack Offset Stack Contents + Stack Offset Stack Contents 0x00 LR Interrupted LR (LR at time of PENDSV) 0x04 r8 @@ -77,26 +77,26 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. 6. Improving Performance -To make ThreadX and the application(s) run faster, you can enable -all compiler optimizations. +To make ThreadX and the application(s) run faster, you can enable +all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M23 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-M23 vectors start at the label __Vectors or similar. The application may modify -the vector area according to its needs. There is code in tx_initialize_low_level() that will -configure the vector base register. +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. 7.2 Managed Interrupts @@ -122,7 +122,7 @@ your_assembly_isr: ; VOID your_assembly_isr(VOID) ; { PUSH {r0, lr} -; +; ; /* Do interrupt handler work here */ ; /* BL */ @@ -134,8 +134,8 @@ your_assembly_isr: Note: the Cortex-M23 requires exception handlers to be thumb labels, this implies bit 0 set. To accomplish this, the declaration of the label has to be preceded by the assembler directive -.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to -be inserted in the correct location in the interrupt vector table. This table is typically +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically located in either your runtime startup file or in the tx_initialize_low_level.S file. @@ -150,7 +150,7 @@ information associated with this specific port of ThreadX: tx_thread_secure_stack_initialize.S New file tx_thread_schedule.S Added secure stack initialize to SVC hander tx_thread_secure_stack.c Fixed stack pointer save, initialize in handler mode - + 04-02-2021 Release 6.1.6 changes: tx_port.h Updated macro definition diff --git a/ports/cortex_m23/ac6/src/tx_misra.S b/ports/cortex_m23/ac6/src/tx_misra.S index 221b9e1a..b4735cc1 100644 --- a/ports/cortex_m23/ac6/src/tx_misra.S +++ b/ports/cortex_m23/ac6/src/tx_misra.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -672,7 +673,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -687,7 +688,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARM_FP /***********************************************************************************************/ @@ -704,8 +705,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -719,9 +720,9 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - + .data .word 0 diff --git a/ports/cortex_m23/ac6/src/tx_thread_context_restore.S b/ports/cortex_m23/ac6/src/tx_thread_context_restore.S index c8478c85..1b0052ef 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m23/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_m23/ac6/src/tx_thread_context_save.S b/ports/cortex_m23/ac6/src/tx_thread_context_save.S index a0b2bdd6..463a4417 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m23/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_m23/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m23/ac6/src/tx_thread_interrupt_control.S index fc624fa1..71e1d835 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m23/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_m23/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_m23/ac6/src/tx_thread_interrupt_disable.S index 3bd783b0..82ac2588 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m23/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports/cortex_m23/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_m23/ac6/src/tx_thread_interrupt_restore.S index d63de10e..03cae94a 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m23/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports/cortex_m23/ac6/src/tx_thread_schedule.S b/ports/cortex_m23/ac6/src/tx_thread_schedule.S index a582e85f..be5661f0 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m23/ac6/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,20 +61,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 04-02-2021 Scott Larson Modified comment(s), added */ -/* low power code, */ -/* resulting in version 6.1.6 */ -/* 06-02-2021 Scott Larson Added secure stack initialize */ -/* in SVC handler, */ -/* resulting in version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -325,7 +312,7 @@ _tx_get_svc: CMP r1, #2 // Is it a secure stack free request? BEQ _tx_svc_secure_free // Yes, go there - + CMP r1, #3 // Is it a secure stack init request? BEQ _tx_svc_secure_init // Yes, go there diff --git a/ports/cortex_m23/ac6/src/tx_thread_secure_stack.c b/ports/cortex_m23/ac6/src/tx_thread_secure_stack.c index baae59d8..0073bd47 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_secure_stack.c +++ b/ports/cortex_m23/ac6/src/tx_thread_secure_stack.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -102,21 +103,6 @@ static INT tx_head_free_index = 0U; /* */ /* _tx_initialize_kernel_enter */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-16-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.1 */ -/* 06-02-2021 Scott Larson Modified comment(s), and */ -/* changed name, execute in */ -/* handler mode, */ -/* resulting in version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments, updated */ -/* secure stack allocation, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_initialize(void) diff --git a/ports/cortex_m23/ac6/src/tx_thread_secure_stack_allocate.S b/ports/cortex_m23/ac6/src/tx_thread_secure_stack_allocate.S index eda6d513..87108d8a 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_secure_stack_allocate.S +++ b/ports/cortex_m23/ac6/src/tx_thread_secure_stack_allocate.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,14 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) // { diff --git a/ports/cortex_m23/ac6/src/tx_thread_secure_stack_free.S b/ports/cortex_m23/ac6/src/tx_thread_secure_stack_free.S index 2a02ee12..a24f1f82 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_secure_stack_free.S +++ b/ports/cortex_m23/ac6/src/tx_thread_secure_stack_free.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) // { diff --git a/ports/cortex_m23/ac6/src/tx_thread_secure_stack_initialize.S b/ports/cortex_m23/ac6/src/tx_thread_secure_stack_initialize.S index 03368cca..4a046400 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_secure_stack_initialize.S +++ b/ports/cortex_m23/ac6/src/tx_thread_secure_stack_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,18 +54,6 @@ /* */ /* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) // { diff --git a/ports/cortex_m23/ac6/src/tx_thread_stack_build.S b/ports/cortex_m23/ac6/src/tx_thread_stack_build.S index 204e3cf1..c28ef1e2 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_m23/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { @@ -100,7 +93,7 @@ _tx_thread_stack_build: Stack Bottom: (higher memory address) */ LDR r2, [r0, #16] // Pickup end of stack area - MOVW r3, #0x7 // + MOVW r3, #0x7 // BICS r2, r2, r3 // Align frame for 8-byte alignment SUBS r2, r2, #68 // Subtract frame size #ifdef TX_SINGLE_MODE_SECURE diff --git a/ports/cortex_m23/ac6/src/tx_thread_system_return.S b/ports/cortex_m23/ac6/src/tx_thread_system_return.S index 05e2be40..d85981da 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m23/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_m23/ac6/src/tx_timer_interrupt.S b/ports/cortex_m23/ac6/src/tx_timer_interrupt.S index 47604260..b5da696e 100644 --- a/ports/cortex_m23/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_m23/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_m23/ac6/src/txe_thread_secure_stack_allocate.c b/ports/cortex_m23/ac6/src/txe_thread_secure_stack_allocate.c index aff98e87..9bade139 100644 --- a/ports/cortex_m23/ac6/src/txe_thread_secure_stack_allocate.c +++ b/ports/cortex_m23/ac6/src/txe_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { @@ -76,10 +71,10 @@ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_siz return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports/cortex_m23/ac6/src/txe_thread_secure_stack_free.c b/ports/cortex_m23/ac6/src/txe_thread_secure_stack_free.c index eb2d6b0e..75a26945 100644 --- a/ports/cortex_m23/ac6/src/txe_thread_secure_stack_free.c +++ b/ports/cortex_m23/ac6/src/txe_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { @@ -74,10 +69,10 @@ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports/cortex_m23/gnu/inc/tx_port.h b/ports/cortex_m23/gnu/inc/tx_port.h index e05f826f..b1eab9e3 100644 --- a/ports/cortex_m23/gnu/inc/tx_port.h +++ b/ports/cortex_m23/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,31 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-02-2021 Scott Larson Modified comment(s), */ -/* remove unneeded headers, */ -/* use builtins, added */ -/* ULONG64_DEFINED, */ -/* resulting in version 6.1.5 */ -/* 06-02-2021 Yuxin Zhou Modified comment(s), added */ -/* conditional compilation */ -/* for ARMv8-M (Cortex M23/33) */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ -/* stack check error handling, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -75,7 +51,7 @@ /* Determine if the optional ThreadX user define file should be used. */ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -111,17 +87,17 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); #define TX_PORT_THREAD_STACK_ERROR_HANDLING -/* Define the system API mappings based on the error checking - selected by the user. Note: this section is only applicable to +/* Define the system API mappings based on the error checking + selected by the user. Note: this section is only applicable to application source code, hence the conditional that turns off this stuff when the include file is processed by the ThreadX source. */ #ifndef TX_SOURCE_CODE -/* Determine if error checking is desired. If so, map API functions +/* Determine if error checking is desired. If so, map API functions to the appropriate error checking front-ends. Otherwise, map API - functions to the core functions that actually perform the work. + functions to the core functions that actually perform the work. Note: error checking is enabled by default. */ #ifdef TX_DISABLE_ERROR_CHECKING @@ -166,7 +142,7 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY +#ifndef TX_TIMER_THREAD_PRIORITY #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -178,7 +154,7 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); /* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0x0a800024) @@ -217,7 +193,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -231,7 +207,7 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ #define TX_THREAD_EXTENSION_0 @@ -255,7 +231,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION @@ -321,7 +297,7 @@ inline static unsigned int _get_ipsr(void) /* Define the get system state macro. */ - + #ifndef TX_THREAD_GET_SYSTEM_STATE #ifndef TX_MISRA_ENABLE #define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _get_ipsr()) @@ -347,14 +323,14 @@ extern void _tx_thread_secure_stack_initialize(void); #define TX_PORT_SPECIFIC_PRE_INITIALIZATION _tx_thread_secure_stack_initialize(); #endif -/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to prevent early scheduling on Cortex-M parts. */ - + #define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -364,9 +340,9 @@ extern void _tx_thread_secure_stack_initialize(void); #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -445,8 +421,8 @@ unsigned int interrupt_save; /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M23/GNU Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M23/GNU Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m23/gnu/inc/tx_secure_interface.h b/ports/cortex_m23/gnu/inc/tx_secure_interface.h index fbf20b31..5ac37fbf 100644 --- a/ports/cortex_m23/gnu/inc/tx_secure_interface.h +++ b/ports/cortex_m23/gnu/inc/tx_secure_interface.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,12 +38,6 @@ /* It is assumed that tx_api.h and tx_port.h have already been */ /* included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_SECURE_INTERFACE_H diff --git a/ports/cortex_m23/gnu/readme_threadx.txt b/ports/cortex_m23/gnu/readme_threadx.txt index 08a8ca82..9ce76341 100644 --- a/ports/cortex_m23/gnu/readme_threadx.txt +++ b/ports/cortex_m23/gnu/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for Cortex-M23 + Microsoft's Azure RTOS ThreadX for Cortex-M23 Using the GNU Tools @@ -6,8 +6,8 @@ 1. Building the ThreadX run-time Library An example .bat file is in the example_build directory. -Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c -replace the common files of the same name. +Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c +replace the common files of the same name. 2. Demonstration System @@ -16,15 +16,15 @@ No demonstration example is provided. 3. System Initialization -The entry point in ThreadX for the Cortex-M23 using gnu tools uses the standard GNU +The entry point in ThreadX for the Cortex-M23 using gnu tools uses the standard GNU Cortex-M23 reset sequence. From the reset vector the C runtime will be initialized. -The ThreadX tx_initialize_low_level.S file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. +The ThreadX tx_initialize_low_level.S file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. @@ -33,11 +33,11 @@ parameter to your application definition function, tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M23 version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. - Stack Offset Stack Contents + Stack Offset Stack Contents 0x00 LR Interrupted LR (LR at time of PENDSV) 0x04 r8 @@ -60,26 +60,26 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. 5. Improving Performance -To make ThreadX and the application(s) run faster, you can enable -all compiler optimizations. +To make ThreadX and the application(s) run faster, you can enable +all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M23 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 6.1 Vector Area The Cortex-M23 vectors start at the label __tx_vectors or similar. The application may modify -the vector area according to its needs. There is code in tx_initialize_low_level() that will -configure the vector base register. +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. 6.2 Managed Interrupts @@ -105,7 +105,7 @@ your_assembly_isr: ; VOID your_assembly_isr(VOID) ; { PUSH {r0, lr} -; +; ; /* Do interrupt handler work here */ ; /* BL */ @@ -117,8 +117,8 @@ your_assembly_isr: Note: the Cortex-M23 requires exception handlers to be thumb labels, this implies bit 0 set. To accomplish this, the declaration of the label has to be preceded by the assembler directive -.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to -be inserted in the correct location in the interrupt vector table. This table is typically +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically located in either your runtime startup file or in the tx_initialize_low_level.S file. @@ -140,14 +140,14 @@ information associated with this specific port of ThreadX: 03-02-2021 The following files were changed/added for version 6.1.5: tx_port.h Added ULONG64_DEFINED -12-31-2020 The following files were +12-31-2020 The following files were changed/added for port specific version 6.1.3: - - tx_port.h Remove unneeded include files, + + tx_port.h Remove unneeded include files, use builtin functions, modified comments. - - tx_thread_secure_stack.c Remove unneeded include file, + + tx_thread_secure_stack.c Remove unneeded include file, use inline get/set functions, modified comments. diff --git a/ports/cortex_m23/gnu/src/tx_initialize_low_level.S b/ports/cortex_m23/gnu/src/tx_initialize_low_level.S index 6cdaa552..ba092253 100644 --- a/ports/cortex_m23/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_m23/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ HEAP_SIZE = 0x00000000 /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -91,20 +84,20 @@ _tx_initialize_low_level: /* Set base of available memory to end of non-initialised RAM area. */ LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer LDR r1, =Image$$ARM_LIB_STACK$$ZI$$Limit // Build first free address - ADDS r1, r1, #4 // + ADDS r1, r1, #4 // STR r1, [r0] // Setup first unused memory pointer /* Setup Vector Table Offset Register. */ LDR r0, =0xE000ED08 // Build address of NVIC registers LDR r1, =__Vectors // Pickup address of vector table - STR r1, [r0] // Set vector table address + STR r1, [r0] // Set vector table address // /* Enable the cycle count register. */ // // LDR r0, =0xE0001000 // Build address of DWT register // LDR r1, [r0] // Pickup the current value // ORR r1, r1, #1 // Set the CYCCNTENA bit -// STR r1, [r0] // Enable the cycle count register +// STR r1, [r0] // Enable the cycle count register /* Set system stack pointer from vector value. */ LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer @@ -122,21 +115,21 @@ _tx_initialize_low_level: /* Configure handler priorities. */ LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD18 // - ADD r0, r0, r2 // + LDR r2, =0xD18 // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 4-7 Priority Registers LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD1C // - ADD r0, r0, r2 // + LDR r2, =0xD1C // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 8-11 Priority Registers // Note: SVC must be lowest priority, which is 0xFF LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD20 // - ADD r0, r0, r2 // + LDR r2, =0xD20 // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 12-15 Priority Registers // Note: PnSV must be lowest priority, which is 0xFF @@ -217,7 +210,7 @@ HardFault_Handler: // A stack overflow will trigger a hardfault. // There is no CFSR in M23, so we will not try to // determine if the fault is caused by a stack overflow - // or some other condition. + // or some other condition. B HardFault_Handler .end diff --git a/ports/cortex_m23/gnu/src/tx_misra.S b/ports/cortex_m23/gnu/src/tx_misra.S index 221b9e1a..b4735cc1 100644 --- a/ports/cortex_m23/gnu/src/tx_misra.S +++ b/ports/cortex_m23/gnu/src/tx_misra.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -672,7 +673,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -687,7 +688,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARM_FP /***********************************************************************************************/ @@ -704,8 +705,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -719,9 +720,9 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - + .data .word 0 diff --git a/ports/cortex_m23/gnu/src/tx_thread_context_restore.S b/ports/cortex_m23/gnu/src/tx_thread_context_restore.S index 59e577b0..6f2b453c 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m23/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_m23/gnu/src/tx_thread_context_save.S b/ports/cortex_m23/gnu/src/tx_thread_context_save.S index ab5eecde..84bf9908 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m23/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_m23/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m23/gnu/src/tx_thread_interrupt_control.S index 4b2a2689..53fd963c 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m23/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_m23/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_m23/gnu/src/tx_thread_interrupt_disable.S index e670a1bd..a528ae25 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m23/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports/cortex_m23/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_m23/gnu/src/tx_thread_interrupt_restore.S index 56cf9f49..e8193789 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m23/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports/cortex_m23/gnu/src/tx_thread_schedule.S b/ports/cortex_m23/gnu/src/tx_thread_schedule.S index c41cf38b..81919921 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m23/gnu/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,20 +57,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 04-02-2021 Scott Larson Modified comment(s), added */ -/* low power code, */ -/* resulting in version 6.1.6 */ -/* 06-02-2021 Scott Larson Added secure stack initialize */ -/* in SVC handler, */ -/* resulting in version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -321,7 +308,7 @@ _tx_get_svc: CMP r1, #2 // Is it a secure stack free request? BEQ _tx_svc_secure_free // Yes, go there - + CMP r1, #3 // Is it a secure stack init request? BEQ _tx_svc_secure_init // Yes, go there diff --git a/ports/cortex_m23/gnu/src/tx_thread_secure_stack.c b/ports/cortex_m23/gnu/src/tx_thread_secure_stack.c index 4f757f90..44376c27 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_secure_stack.c +++ b/ports/cortex_m23/gnu/src/tx_thread_secure_stack.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -98,21 +99,6 @@ static INT tx_head_free_index = 0U; /* */ /* _tx_initialize_kernel_enter */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-16-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.1 */ -/* 06-02-2021 Scott Larson Modified comment(s), changed */ -/* name, execute in handler */ -/* mode, disable optimization, */ -/* resulting in version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments, updated */ -/* secure stack allocation, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry, optimize(0))) UINT _tx_thread_secure_mode_stack_initialize(void) diff --git a/ports/cortex_m23/gnu/src/tx_thread_secure_stack_allocate.S b/ports/cortex_m23/gnu/src/tx_thread_secure_stack_allocate.S index 90b9686b..cf07f868 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_secure_stack_allocate.S +++ b/ports/cortex_m23/gnu/src/tx_thread_secure_stack_allocate.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,14 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) // { diff --git a/ports/cortex_m23/gnu/src/tx_thread_secure_stack_free.S b/ports/cortex_m23/gnu/src/tx_thread_secure_stack_free.S index dda4843e..725f00cc 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_secure_stack_free.S +++ b/ports/cortex_m23/gnu/src/tx_thread_secure_stack_free.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) // { diff --git a/ports/cortex_m23/gnu/src/tx_thread_secure_stack_initialize.S b/ports/cortex_m23/gnu/src/tx_thread_secure_stack_initialize.S index b784cd91..48aec578 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_secure_stack_initialize.S +++ b/ports/cortex_m23/gnu/src/tx_thread_secure_stack_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,18 +54,6 @@ /* */ /* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) // { diff --git a/ports/cortex_m23/gnu/src/tx_thread_stack_build.S b/ports/cortex_m23/gnu/src/tx_thread_stack_build.S index b569dfe0..bd25b57d 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m23/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { @@ -100,7 +93,7 @@ _tx_thread_stack_build: Stack Bottom: (higher memory address) */ LDR r2, [r0, #16] // Pickup end of stack area - MOVW r3, #0x7 // + MOVW r3, #0x7 // BICS r2, r2, r3 // Align frame for 8-byte alignment SUBS r2, r2, #68 // Subtract frame size #ifdef TX_SINGLE_MODE_SECURE diff --git a/ports/cortex_m23/gnu/src/tx_thread_system_return.S b/ports/cortex_m23/gnu/src/tx_thread_system_return.S index add8dd86..a14fdba3 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m23/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_m23/gnu/src/tx_timer_interrupt.S b/ports/cortex_m23/gnu/src/tx_timer_interrupt.S index ca3d52d4..bde6c316 100644 --- a/ports/cortex_m23/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_m23/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_m23/gnu/src/txe_thread_secure_stack_allocate.c b/ports/cortex_m23/gnu/src/txe_thread_secure_stack_allocate.c index aff98e87..9bade139 100644 --- a/ports/cortex_m23/gnu/src/txe_thread_secure_stack_allocate.c +++ b/ports/cortex_m23/gnu/src/txe_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { @@ -76,10 +71,10 @@ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_siz return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports/cortex_m23/gnu/src/txe_thread_secure_stack_free.c b/ports/cortex_m23/gnu/src/txe_thread_secure_stack_free.c index eb2d6b0e..75a26945 100644 --- a/ports/cortex_m23/gnu/src/txe_thread_secure_stack_free.c +++ b/ports/cortex_m23/gnu/src/txe_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { @@ -74,10 +69,10 @@ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports/cortex_m23/iar/inc/tx_port.h b/ports/cortex_m23/iar/inc/tx_port.h index 5172ce92..be6bebd5 100644 --- a/ports/cortex_m23/iar/inc/tx_port.h +++ b/ports/cortex_m23/iar/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,29 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-02-2021 Scott Larson Modified comment(s), added */ -/* ULONG64_DEFINED, */ -/* resulting in version 6.1.5 */ -/* 06-02-2021 Yuxin Zhou Modified comment(s), added */ -/* conditional compilation */ -/* for ARMv8-M (Cortex M23/33) */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ -/* stack check error handling, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -73,7 +51,7 @@ /* Determine if the optional ThreadX user define file should be used. */ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -114,17 +92,17 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); #define TX_PORT_THREAD_STACK_ERROR_HANDLING -/* Define the system API mappings based on the error checking - selected by the user. Note: this section is only applicable to +/* Define the system API mappings based on the error checking + selected by the user. Note: this section is only applicable to application source code, hence the conditional that turns off this stuff when the include file is processed by the ThreadX source. */ #ifndef TX_SOURCE_CODE -/* Determine if error checking is desired. If so, map API functions +/* Determine if error checking is desired. If so, map API functions to the appropriate error checking front-ends. Otherwise, map API - functions to the core functions that actually perform the work. + functions to the core functions that actually perform the work. Note: error checking is enabled by default. */ #ifdef TX_DISABLE_ERROR_CHECKING @@ -169,7 +147,7 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY +#ifndef TX_TIMER_THREAD_PRIORITY #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -181,7 +159,7 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); /* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0x0a800024) @@ -220,7 +198,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -234,7 +212,7 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ #define TX_THREAD_EXTENSION_0 @@ -277,7 +255,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION @@ -304,7 +282,7 @@ void __iar_Initlocks(void); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else /* No IAR library support. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) #define TX_THREAD_DELETE_EXTENSION(thread_ptr) if(thread_ptr -> tx_thread_secure_stack_context){_tx_thread_secure_stack_free(thread_ptr);} #else @@ -346,7 +324,7 @@ void __iar_Initlocks(void); /* Define the get system state macro. */ - + #ifndef TX_THREAD_GET_SYSTEM_STATE #ifndef TX_MISRA_ENABLE #define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __get_IPSR()) @@ -372,14 +350,14 @@ extern void _tx_thread_secure_stack_initialize(void); #define TX_PORT_SPECIFIC_PRE_INITIALIZATION _tx_thread_secure_stack_initialize(); #endif -/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to prevent early scheduling on Cortex-M parts. */ - + #define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -389,9 +367,9 @@ extern void _tx_thread_secure_stack_initialize(void); #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -435,8 +413,8 @@ __istate_t interrupt_save; /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M23/IAR Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M23/IAR Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m23/iar/inc/tx_secure_interface.h b/ports/cortex_m23/iar/inc/tx_secure_interface.h index fbf20b31..5ac37fbf 100644 --- a/ports/cortex_m23/iar/inc/tx_secure_interface.h +++ b/ports/cortex_m23/iar/inc/tx_secure_interface.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,12 +38,6 @@ /* It is assumed that tx_api.h and tx_port.h have already been */ /* included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_SECURE_INTERFACE_H diff --git a/ports/cortex_m23/iar/readme_threadx.txt b/ports/cortex_m23/iar/readme_threadx.txt index bd190400..8c3217c0 100644 --- a/ports/cortex_m23/iar/readme_threadx.txt +++ b/ports/cortex_m23/iar/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for Cortex-M23 + Microsoft's Azure RTOS ThreadX for Cortex-M23 Using the IAR Tools @@ -6,33 +6,33 @@ 1. Building the ThreadX run-time Library Import all ThreadX common and port-specific source files into an IAR project. -Configure the project to build a library rather than an executable. This -results in the ThreadX run-time library file tx.a, which is needed by +Configure the project to build a library rather than an executable. This +results in the ThreadX run-time library file tx.a, which is needed by the application. -Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c -replace the common files of the same name. +Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c +replace the common files of the same name. 2. Demonstration System No demonstration is provided because the IAR EWARM 8.50 simulator does -not simulate the Cortex-M23 correctly. +not simulate the Cortex-M23 correctly. 3. System Initialization -The entry point in ThreadX for the Cortex-M23 using IAR tools is at label -__iar_program_start. This is defined within the IAR compiler's startup code. -In addition, this is where all static and global preset C variable +The entry point in ThreadX for the Cortex-M23 using IAR tools is at label +__iar_program_start. This is defined within the IAR compiler's startup code. +In addition, this is where all static and global preset C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, and a periodic timer interrupt source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. The _tx_initialize_low_level function inside of tx_initialize_low_level.s -also determines the first available address for use by the application, which -is supplied as the sole input parameter to your application definition function, -tx_application_define. To accomplish this, a section is created in -tx_initialize_low_level.s called FREE_MEM, which must be located after all +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all other RAM sections in memory. @@ -41,10 +41,10 @@ other RAM sections in memory. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M23 version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. - Stack Offset Stack Contents + Stack Offset Stack Contents 0x00 LR Interrupted LR (LR at time of PENDSV) 0x04 r8 @@ -67,17 +67,17 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. 5. Improving Performance -To make ThreadX and the application(s) run faster, you can enable -all compiler optimizations. +To make ThreadX and the application(s) run faster, you can enable +all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling -The Cortex-M23 vectors start at the label __vector_table and is typically defined in a +The Cortex-M23 vectors start at the label __vector_table and is typically defined in a startup.s file (or similar). The application may modify the vector area according to its needs. @@ -126,7 +126,7 @@ should have the following line added (if not already in place): initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application -The project options "General Options -> Library Configuration" should also have the +The project options "General Options -> Library Configuration" should also have the "Enable thread support in library" box selected. diff --git a/ports/cortex_m23/iar/src/tx_iar.c b/ports/cortex_m23/iar/src/tx_iar.c index ee47f10f..238b485e 100644 --- a/ports/cortex_m23/iar/src/tx_iar.c +++ b/ports/cortex_m23/iar/src/tx_iar.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports/cortex_m23/iar/src/tx_initialize_low_level.s b/ports/cortex_m23/iar/src/tx_initialize_low_level.s index aec8f69c..fb6a109f 100644 --- a/ports/cortex_m23/iar/src/tx_initialize_low_level.s +++ b/ports/cortex_m23/iar/src/tx_initialize_low_level.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,13 +71,6 @@ __tx_free_memory_start /* CALLED BY */ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -118,21 +112,21 @@ _tx_initialize_low_level: /* Configure handler priorities. */ LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD18 // - ADD r0, r0, r2 // + LDR r2, =0xD18 // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 4-7 Priority Registers LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD1C // - ADD r0, r0, r2 // + LDR r2, =0xD1C // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 8-11 Priority Registers // Note: SVC must be lowest priority, which is 0xFF LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD20 // - ADD r0, r0, r2 // + LDR r2, =0xD20 // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 12-15 Priority Registers // Note: PnSV must be lowest priority, which is 0xFF @@ -191,7 +185,7 @@ HardFault_Handler: // A stack overflow will trigger a hardfault. // There is no CFSR in M23, so we will not try to // determine if the fault is caused by a stack overflow - // or some other condition. + // or some other condition. B HardFault_Handler diff --git a/ports/cortex_m23/iar/src/tx_misra.s b/ports/cortex_m23/iar/src/tx_misra.s index a42b9e51..e43d258f 100644 --- a/ports/cortex_m23/iar/src/tx_misra.s +++ b/ports/cortex_m23/iar/src/tx_misra.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -116,7 +117,7 @@ SECTION `.data`:DATA:REORDER:NOROOT(2) DATA -// 51 CHAR _tx_version_id[100] = "Copyright (c) 2024 Microsoft Corporation. * ThreadX 6.1 MISRA C Compliant *"; +// 51 CHAR _tx_version_id[100] = "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX 6.1 MISRA C Compliant *"; _tx_version_id: DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H @@ -708,7 +709,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -723,7 +724,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARMVFP__ /***********************************************************************************************/ @@ -740,8 +741,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -755,10 +756,10 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - - + + SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2) SECTION_TYPE SHT_PROGBITS, 0 DATA diff --git a/ports/cortex_m23/iar/src/tx_thread_context_restore.s b/ports/cortex_m23/iar/src/tx_thread_context_restore.s index 83ab38c9..11f3d018 100644 --- a/ports/cortex_m23/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_m23/iar/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_m23/iar/src/tx_thread_context_save.s b/ports/cortex_m23/iar/src/tx_thread_context_save.s index 8ea8a775..bb6b9d51 100644 --- a/ports/cortex_m23/iar/src/tx_thread_context_save.s +++ b/ports/cortex_m23/iar/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_m23/iar/src/tx_thread_interrupt_control.s b/ports/cortex_m23/iar/src/tx_thread_interrupt_control.s index 1e5e1973..5a74b366 100644 --- a/ports/cortex_m23/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m23/iar/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_m23/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m23/iar/src/tx_thread_interrupt_disable.s index 375c9926..6b95841a 100644 --- a/ports/cortex_m23/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m23/iar/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports/cortex_m23/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_m23/iar/src/tx_thread_interrupt_restore.s index 3768cfb3..c5a40257 100644 --- a/ports/cortex_m23/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m23/iar/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports/cortex_m23/iar/src/tx_thread_schedule.s b/ports/cortex_m23/iar/src/tx_thread_schedule.s index b3f110e9..bd902dc4 100644 --- a/ports/cortex_m23/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m23/iar/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -69,19 +70,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 04-02-2021 Scott Larson Modified comment(s), added */ -/* low power code, */ -/* resulting in version 6.1.6 */ -/* 06-02-2021 Scott Larson Added secure stack initialize */ -/* in SVC handler, */ -/* resulting in version 6.1.7 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -314,7 +302,7 @@ _tx_get_svc: CMP r1, #2 // Is it a secure stack free request? BEQ _tx_svc_secure_free // Yes, go there - + CMP r1, #3 // Is it a secure stack init request? BEQ _tx_svc_secure_init // Yes, go there diff --git a/ports/cortex_m23/iar/src/tx_thread_secure_stack.c b/ports/cortex_m23/iar/src/tx_thread_secure_stack.c index 099097fb..9ce9ccc3 100644 --- a/ports/cortex_m23/iar/src/tx_thread_secure_stack.c +++ b/ports/cortex_m23/iar/src/tx_thread_secure_stack.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -102,21 +103,6 @@ static INT tx_head_free_index = 0U; /* */ /* _tx_initialize_kernel_enter */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-16-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.1 */ -/* 06-02-2021 Scott Larson Modified comment(s), changed */ -/* name, execute in handler */ -/* mode, disable optimization, */ -/* resulting in version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments, updated */ -/* secure stack allocation, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_initialize(void) diff --git a/ports/cortex_m23/iar/src/tx_thread_secure_stack_allocate.s b/ports/cortex_m23/iar/src/tx_thread_secure_stack_allocate.s index a722d4de..5c847788 100644 --- a/ports/cortex_m23/iar/src/tx_thread_secure_stack_allocate.s +++ b/ports/cortex_m23/iar/src/tx_thread_secure_stack_allocate.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,13 +53,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) // { diff --git a/ports/cortex_m23/iar/src/tx_thread_secure_stack_free.s b/ports/cortex_m23/iar/src/tx_thread_secure_stack_free.s index cba64bec..4ce87ee3 100644 --- a/ports/cortex_m23/iar/src/tx_thread_secure_stack_free.s +++ b/ports/cortex_m23/iar/src/tx_thread_secure_stack_free.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,13 +51,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) // { diff --git a/ports/cortex_m23/iar/src/tx_thread_secure_stack_initialize.s b/ports/cortex_m23/iar/src/tx_thread_secure_stack_initialize.s index 95f0c250..325a62bf 100644 --- a/ports/cortex_m23/iar/src/tx_thread_secure_stack_initialize.s +++ b/ports/cortex_m23/iar/src/tx_thread_secure_stack_initialize.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,17 +51,6 @@ /* CALLED BY */ /* */ /* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) // { diff --git a/ports/cortex_m23/iar/src/tx_thread_stack_build.s b/ports/cortex_m23/iar/src/tx_thread_stack_build.s index bbb60ae6..71d25cec 100644 --- a/ports/cortex_m23/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_m23/iar/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { @@ -90,7 +84,7 @@ _tx_thread_stack_build: Stack Bottom: (higher memory address) */ LDR r2, [r0, #16] // Pickup end of stack area - MOVW r3, #0x7 // + MOVW r3, #0x7 // BICS r2, r2, r3 // Align frame for 8-byte alignment SUBS r2, r2, #68 // Subtract frame size #ifdef TX_SINGLE_MODE_SECURE diff --git a/ports/cortex_m23/iar/src/tx_thread_system_return.s b/ports/cortex_m23/iar/src/tx_thread_system_return.s index f574ed35..91ef52c7 100644 --- a/ports/cortex_m23/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m23/iar/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_m23/iar/src/tx_timer_interrupt.s b/ports/cortex_m23/iar/src/tx_timer_interrupt.s index 9dd72463..eadef8bf 100644 --- a/ports/cortex_m23/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_m23/iar/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,13 +68,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_m23/iar/src/txe_thread_secure_stack_allocate.c b/ports/cortex_m23/iar/src/txe_thread_secure_stack_allocate.c index aff98e87..9bade139 100644 --- a/ports/cortex_m23/iar/src/txe_thread_secure_stack_allocate.c +++ b/ports/cortex_m23/iar/src/txe_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { @@ -76,10 +71,10 @@ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_siz return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports/cortex_m23/iar/src/txe_thread_secure_stack_free.c b/ports/cortex_m23/iar/src/txe_thread_secure_stack_free.c index eb2d6b0e..75a26945 100644 --- a/ports/cortex_m23/iar/src/txe_thread_secure_stack_free.c +++ b/ports/cortex_m23/iar/src/txe_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { @@ -74,10 +69,10 @@ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports/cortex_m3/ac5/example_build/sample_threadx.c b/ports/cortex_m3/ac5/example_build/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports/cortex_m3/ac5/example_build/sample_threadx.c +++ b/ports/cortex_m3/ac5/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_m3/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_m3/ac5/example_build/tx_initialize_low_level.s index 696ea4ef..f0c38db2 100644 --- a/ports/cortex_m3/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m3/ac5/example_build/tx_initialize_low_level.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -122,12 +122,6 @@ Reset_Handler ;/* */ ;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) ;{ diff --git a/ports/cortex_m3/ac5/inc/tx_port.h b/ports/cortex_m3/ac5/inc/tx_port.h index 2e67b649..32e640ba 100644 --- a/ports/cortex_m3/ac5/inc/tx_port.h +++ b/ports/cortex_m3/ac5/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,23 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comments, updated */ -/* typedef to fix misra */ -/* violation, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -371,7 +355,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -530,7 +514,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #endif @@ -715,7 +699,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M3/AC5 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3/AC5 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m3/ac5/readme_threadx.txt b/ports/cortex_m3/ac5/readme_threadx.txt index b7b7cee9..e261213e 100644 --- a/ports/cortex_m3/ac5/readme_threadx.txt +++ b/ports/cortex_m3/ac5/readme_threadx.txt @@ -5,14 +5,14 @@ 1. Building the ThreadX run-time Library -Navigate to the "example_build" directory. Ensure that -you have setup your path and other environment variables necessary for the AC5 -compiler. At this point you may run the build_threadx.bat batch file. This will -build the ThreadX run-time environment in the "example_build" directory. +Navigate to the "example_build" directory. Ensure that +you have setup your path and other environment variables necessary for the AC5 +compiler. At this point you may run the build_threadx.bat batch file. This will +build the ThreadX run-time environment in the "example_build" directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. @@ -21,28 +21,28 @@ application in order to use ThreadX. The ThreadX demonstration is designed to execute under the ARM DS Cortex-M simulator. -Building the demonstration is easy; simply execute the build_threadx_sample.bat +Building the demonstration is easy; simply execute the build_threadx_sample.bat batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with tx.a. The resulting file sample_threadx.axf +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.axf is a binary file that can be downloaded and executed on the ARM DS Cortex-M simulator. 3. System Initialization -The entry point in ThreadX for the Cortex-M using AC5 tools is at label -__main. This is defined within the AC5 compiler's startup code. In -addition, this is where all static and global pre-set C variable +The entry point in ThreadX for the Cortex-M using AC5 tools is at label +__main. This is defined within the AC5 compiler's startup code. In +addition, this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. @@ -51,7 +51,7 @@ parameter to your application definition function, tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -134,21 +134,21 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 5. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the ThreadX library project to enable various compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: @@ -187,8 +187,8 @@ your_assembly_isr 7. FPU Support -ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context - no additional setup by the application. diff --git a/ports/cortex_m3/ac5/src/tx_thread_context_restore.s b/ports/cortex_m3/ac5/src/tx_thread_context_restore.s index 23503273..d8c8d6dd 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_m3/ac5/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_m3/ac5/src/tx_thread_context_save.s b/ports/cortex_m3/ac5/src/tx_thread_context_save.s index 75a68861..3d59c966 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_context_save.s +++ b/ports/cortex_m3/ac5/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_m3/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_m3/ac5/src/tx_thread_interrupt_control.s index 050d349d..340ef0f6 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m3/ac5/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_m3/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_m3/ac5/src/tx_thread_interrupt_disable.s index 01642018..86308572 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m3/ac5/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports/cortex_m3/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_m3/ac5/src/tx_thread_interrupt_restore.s index d5b937f6..917db4e4 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m3/ac5/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports/cortex_m3/ac5/src/tx_thread_schedule.s b/ports/cortex_m3/ac5/src/tx_thread_schedule.s index 44449388..84613f2d 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_m3/ac5/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,17 +68,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 04-25-2022 Scott Larson Added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_m3/ac5/src/tx_thread_stack_build.s b/ports/cortex_m3/ac5/src/tx_thread_stack_build.s index fa77e2d6..6639bdf8 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_stack_build.s +++ b/ports/cortex_m3/ac5/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_m3/ac5/src/tx_thread_system_return.s b/ports/cortex_m3/ac5/src/tx_thread_system_return.s index 53d48047..e10d05c6 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_system_return.s +++ b/ports/cortex_m3/ac5/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_m3/ac5/src/tx_timer_interrupt.s b/ports/cortex_m3/ac5/src/tx_timer_interrupt.s index b87639de..68b30e98 100644 --- a/ports/cortex_m3/ac5/src/tx_timer_interrupt.s +++ b/ports/cortex_m3/ac5/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,18 +72,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_m3/ac6/example_build/sample_threadx/.cproject b/ports/cortex_m3/ac6/example_build/sample_threadx/.cproject index 5f5a5f66..5aedaf80 100644 --- a/ports/cortex_m3/ac6/example_build/sample_threadx/.cproject +++ b/ports/cortex_m3/ac6/example_build/sample_threadx/.cproject @@ -1,170 +1,170 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_m3/ac6/example_build/sample_threadx/exceptions.c b/ports/cortex_m3/ac6/example_build/sample_threadx/exceptions.c index 94c87d7a..f0dd8600 100644 --- a/ports/cortex_m3/ac6/example_build/sample_threadx/exceptions.c +++ b/ports/cortex_m3/ac6/example_build/sample_threadx/exceptions.c @@ -1,7 +1,7 @@ /* ** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ** Use, modification and redistribution of this file is subject to your possession of a -** valid End User License Agreement for the Arm Product of which these examples are part of +** valid End User License Agreement for the Arm Product of which these examples are part of ** and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.c index 597f373c..13ffadba 100644 --- a/ports/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -81,42 +81,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -124,23 +124,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -243,11 +243,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -306,7 +306,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -359,7 +359,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.scat index 8578282d..7e806ce3 100644 --- a/ports/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.scat @@ -3,7 +3,7 @@ ;******************************************************* ; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S index bd52395a..b5ef57e5 100644 --- a/ports/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,10 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @@ -75,12 +75,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* */ @/* _tx_initialize_kernel_enter ThreadX entry function */ @/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) @{ diff --git a/ports/cortex_m3/ac6/example_build/tx/.cproject b/ports/cortex_m3/ac6/example_build/tx/.cproject index a3f5ed91..bf2786fa 100644 --- a/ports/cortex_m3/ac6/example_build/tx/.cproject +++ b/ports/cortex_m3/ac6/example_build/tx/.cproject @@ -1,146 +1,146 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_m3/ac6/inc/tx_port.h b/ports/cortex_m3/ac6/inc/tx_port.h index 592cecf8..0a25ae64 100644 --- a/ports/cortex_m3/ac6/inc/tx_port.h +++ b/ports/cortex_m3/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,23 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comments, updated */ -/* typedef to fix misra */ -/* violation, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -371,7 +355,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -530,7 +514,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #endif @@ -715,7 +699,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M3/AC6 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3/AC6 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m3/ac6/readme_threadx.txt b/ports/cortex_m3/ac6/readme_threadx.txt index d98c90cb..6447c517 100644 --- a/ports/cortex_m3/ac6/readme_threadx.txt +++ b/ports/cortex_m3/ac6/readme_threadx.txt @@ -5,12 +5,12 @@ 1. Building the ThreadX run-time Library -In order to build the ThreadX library and the ThreadX demonstration, first import -the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +In order to build the ThreadX library and the ThreadX demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) into your DS workspace. -Building the ThreadX library is easy; simply right-click the Eclipse project -"tx" and then select the "Build Project" button. You should now observe the compilation +Building the ThreadX library is easy; simply right-click the Eclipse project +"tx" and then select the "Build Project" button. You should now observe the compilation and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. @@ -20,27 +20,27 @@ library file tx.a. The ThreadX demonstration is designed to execute under the DS debugger on the MPS2_Cortex_Mx Bare Metal simulator. -Building the demonstration is easy; simply right-click the Eclipse project -"sample_threadx" and then select the "Build Project" button. You should now observe -the compilation and assembly of the ThreadX demonstration. This project build produces -the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder +Building the demonstration is easy; simply right-click the Eclipse project +"sample_threadx" and then select the "Build Project" button. You should now observe +the compilation and assembly of the ThreadX demonstration. This project build produces +the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder in the Project Explorer window, right-click on the 'cortex-mx_tx.launch' file, click 'Debug As', and then click 'cortex-mx_tx' from the submenu. This will cause the -debugger to load the sample_threadx.axf ELF file and run to main. You are now ready +debugger to load the sample_threadx.axf ELF file and run to main. You are now ready to execute the ThreadX demonstration. 3. System Initialization -The entry point in ThreadX for the Cortex-M using AC6 tools uses the standard GNU +The entry point in ThreadX for the Cortex-M using AC6 tools uses the standard GNU Cortex-M reset sequence. From the reset vector the C runtime will be initialized. -The ThreadX tx_initialize_low_level.S file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. +The ThreadX tx_initialize_low_level.S file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. @@ -49,7 +49,7 @@ parameter to your application definition function, tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -132,34 +132,34 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 5. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the ThreadX library project to enable various compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 6.1 Vector Area The Cortex-M vectors start at the label __tx_vectors or similar. The application may modify -the vector area according to its needs. There is code in tx_initialize_low_level() that will -configure the vector base register. +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. 6.2 Managed Interrupts -A ThreadX managed interrupt is defined below. By following these conventions, the +A ThreadX managed interrupt is defined below. By following these conventions, the application ISR is then allowed access to various ThreadX services from the ISR. Here is the standard template for managed ISRs in ThreadX: @@ -181,15 +181,15 @@ __tx_IntHandler: Note: the Cortex-M requires exception handlers to be thumb labels, this implies bit 0 set. To accomplish this, the declaration of the label has to be preceded by the assembler directive -.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to -be inserted in the correct location in the interrupt vector table. This table is typically +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically located in either your runtime startup file or in the tx_initialize_low_level.S file. 7. FPU Support -ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context - no additional setup by the application. diff --git a/ports/cortex_m3/ac6/src/tx_misra.S b/ports/cortex_m3/ac6/src/tx_misra.S index 8ac0c629..10548671 100644 --- a/ports/cortex_m3/ac6/src/tx_misra.S +++ b/ports/cortex_m3/ac6/src/tx_misra.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -667,7 +668,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -682,7 +683,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARM_FP /***********************************************************************************************/ @@ -699,8 +700,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -714,9 +715,9 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - + .data .word 0 diff --git a/ports/cortex_m3/ac6/src/tx_thread_context_restore.S b/ports/cortex_m3/ac6/src/tx_thread_context_restore.S index 949478b5..bc2b4752 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m3/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_m3/ac6/src/tx_thread_context_save.S b/ports/cortex_m3/ac6/src/tx_thread_context_save.S index f6a10399..22f46a26 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m3/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,14 +61,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_m3/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m3/ac6/src/tx_thread_interrupt_control.S index dcc24d49..c2435528 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m3/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_m3/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_m3/ac6/src/tx_thread_interrupt_disable.S index a1a0b459..37525e38 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m3/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports/cortex_m3/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_m3/ac6/src/tx_thread_interrupt_restore.S index bc5b910a..3c3e2473 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m3/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports/cortex_m3/ac6/src/tx_thread_schedule.S b/ports/cortex_m3/ac6/src/tx_thread_schedule.S index 5f22b3ff..98d21f36 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m3/ac6/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,16 +71,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 04-25-2022 Scott Larson Added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_m3/ac6/src/tx_thread_stack_build.S b/ports/cortex_m3/ac6/src/tx_thread_stack_build.S index d5cc0b49..31303ef8 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_m3/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_m3/ac6/src/tx_thread_system_return.S b/ports/cortex_m3/ac6/src/tx_thread_system_return.S index e7471605..e1c5c2a2 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m3/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_m3/ac6/src/tx_timer_interrupt.S b/ports/cortex_m3/ac6/src/tx_timer_interrupt.S index ee13bef8..05d5c227 100644 --- a/ports/cortex_m3/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_m3/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,17 +71,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_m3/ghs/example_build/sample_threadx.c b/ports/cortex_m3/ghs/example_build/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports/cortex_m3/ghs/example_build/sample_threadx.c +++ b/ports/cortex_m3/ghs/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_m3/ghs/example_build/tx_initialize_low_level.arm b/ports/cortex_m3/ghs/example_build/tx_initialize_low_level.arm index f8b7bb8e..9259c2f4 100644 --- a/ports/cortex_m3/ghs/example_build/tx_initialize_low_level.arm +++ b/ports/cortex_m3/ghs/example_build/tx_initialize_low_level.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_m3/ghs/inc/tx_el.h b/ports/cortex_m3/ghs/inc/tx_el.h index b8926921..72e5bbe3 100644 --- a/ports/cortex_m3/ghs/inc/tx_el.h +++ b/ports/cortex_m3/ghs/inc/tx_el.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,12 +37,6 @@ /* EventAnalyzer. It is assumed that tx_api.h and tx_port.h have */ /* already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_EL_H diff --git a/ports/cortex_m3/ghs/inc/tx_port.h b/ports/cortex_m3/ghs/inc/tx_port.h index a0f6cae5..1327b3a7 100644 --- a/ports/cortex_m3/ghs/inc/tx_port.h +++ b/ports/cortex_m3/ghs/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -379,7 +371,7 @@ asm void restore_ints(int a) #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M3/GHS Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3/GHS Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m3/ghs/readme_threadx.txt b/ports/cortex_m3/ghs/readme_threadx.txt index ad1110fe..02f70c65 100644 --- a/ports/cortex_m3/ghs/readme_threadx.txt +++ b/ports/cortex_m3/ghs/readme_threadx.txt @@ -4,16 +4,16 @@ 1. Open the ThreadX Project Workspace -In order to build the ThreadX library and the ThreadX demonstration first load -the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the -"example_build" directory. +In order to build the ThreadX library and the ThreadX demonstration first load +the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the +"example_build" directory. 2. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply select the MULTI project file -tx.gpj and then select the build button. You should now observe the -compilation and assembly of the ThreadX library. This project build produces +Building the ThreadX library is easy; simply select the MULTI project file +tx.gpj and then select the build button. You should now observe the +compilation and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. @@ -21,52 +21,52 @@ the ThreadX library file tx.a. The ThreadX demonstration is designed to execute under the MULTI environment on the Green Hills Cortex-M3 simulator. The instructions that follow describe -how to get the ThreadX evaluation running under the MULTI Cortex-M3 simulation +how to get the ThreadX evaluation running under the MULTI Cortex-M3 simulation environment. -Building the demonstration is easy; simply select the MULTI project file -sample_threadx.gpj. At this point, select the "Project Build" button and observe -the compilation, assembly, and linkage of the ThreadX demonstration application. +Building the demonstration is easy; simply select the MULTI project file +sample_threadx.gpj. At this point, select the "Project Build" button and observe +the compilation, assembly, and linkage of the ThreadX demonstration application. -After the demonstration is built, invoke the MULTI ARM simulator by selecting -the simulator connection from within the sample_threadx.con connection file. -Once connected to the simulator, select the "Debug" button. You should now -observe the main function of sample_threadx.c. +After the demonstration is built, invoke the MULTI ARM simulator by selecting +the simulator connection from within the sample_threadx.con connection file. +Once connected to the simulator, select the "Debug" button. You should now +observe the main function of sample_threadx.c. -You are now ready to execute the ThreadX demonstration system. Select -breakpoints and data watches to observe the execution of the sample_threadx.c +You are now ready to execute the ThreadX demonstration system. Select +breakpoints and data watches to observe the execution of the sample_threadx.c application. 4. EventAnalyzer Demonstration -To build a demonstration system that also logs events for the MULTI EventAnalyzer, -perform the same steps as the regular demo, except build the ThreadX library with -txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. -The resulting image will log all system events, which can then be displayed by the +To build a demonstration system that also logs events for the MULTI EventAnalyzer, +perform the same steps as the regular demo, except build the ThreadX library with +txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. +The resulting image will log all system events, which can then be displayed by the MULTI EventAnalyzer. 5. System Initialization -The system entry point using the Green Hills tools is at the label _start. -This is defined within the crt0.arm file supplied by Green Hills. In addition, -this is where all static and global preset C variable initialization +The system entry point using the Green Hills tools is at the label _start. +This is defined within the crt0.arm file supplied by Green Hills. In addition, +this is where all static and global preset C variable initialization processing is called from. After the Green Hills startup function returns, ThreadX initialization is called. The main initialization function is _tx_initialize_low_level and -is located in the file tx_initialize_low_level.arm. This function is responsible -for setting up various system data structures, interrupt vectors, and the +is located in the file tx_initialize_low_level.arm. This function is responsible +for setting up various system data structures, interrupt vectors, and the periodic timer interrupt source of ThreadX. -In addition, _tx_initialize_low_level determines where the first available +In addition, _tx_initialize_low_level determines where the first available RAM memory address is located. This address is supplied to tx_application_define. -By default, the first available RAM memory address is assumed to start at the -beginning of the ThreadX section .free_mem. If changes are made to the -sample_threadx.ld file, the .free_mem section should remain the last allocated -section in the main RAM area. The starting address of this section is passed +By default, the first available RAM memory address is assumed to start at the +beginning of the ThreadX section .free_mem. If changes are made to the +sample_threadx.ld file, the .free_mem section should remain the last allocated +section in the main RAM area. The starting address of this section is passed to tx_application_define. @@ -75,11 +75,11 @@ to tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M3 version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. - Stack Offset Stack Contents + Stack Offset Stack Contents 0x00 r4 0x04 r5 @@ -101,21 +101,21 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. 7. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make ThreadX run faster, you can change the tx.gpj project -to disable debug information and enable the desired optimizations. +to disable debug information and enable the desired optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined before tx_api.h is included. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. 8. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M3 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: @@ -127,7 +127,7 @@ the vector area according to its needs. 8.2 Managed Interrupts -A ThreadX managed interrupt is defined below. By following these conventions, the +A ThreadX managed interrupt is defined below. By following these conventions, the application ISR is then allowed access to various ThreadX services from the ISR. Here is the standard template for managed ISRs in ThreadX: @@ -136,7 +136,7 @@ Here is the standard template for managed ISRs in ThreadX: __tx_IntHandler: PUSH {lr} BL _tx_thread_context_save - + /* Do interrupt handler work here */ B _tx_thread_context_restore @@ -154,7 +154,7 @@ information associated with this specific port of ThreadX: 03-02-2021 The following files were changed/added for version 6.1.5: tx_thread_schedule.s Added low power feature -05/19/2020 Initial ThreadX version of Cortex-M3/Green Hills port. +05/19/2020 Initial ThreadX version of Cortex-M3/Green Hills port. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_m3/ghs/src/tx_el.c b/ports/cortex_m3/ghs/src/tx_el.c index fd58768f..b5d3b8b7 100644 --- a/ports/cortex_m3/ghs/src/tx_el.c +++ b/ports/cortex_m3/ghs/src/tx_el.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** ThreadX/GHS Event Log (EL) */ /** */ @@ -49,44 +50,38 @@ extern TX_THREAD *_tx_thread_current_ptr; UINT _tx_thread_interrupt_control(UINT new_posture); -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_initialize PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_initialize PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function creates the Event Log (in the format dictated by the */ -/* GHS Event Analyzer) and sets up various information for subsequent */ -/* operation. The start and end of the Event Log is determined by the */ -/* .eventlog section in the linker control file. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function creates the Event Log (in the format dictated by the */ +/* GHS Event Analyzer) and sets up various information for subsequent */ +/* operation. The start and end of the Event Log is determined by the */ +/* .eventlog section in the linker control file. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ VOID _tx_el_initialize(VOID) @@ -150,7 +145,7 @@ UINT i; /* Setup event_ptr (pointer to oldest event) field to the start of the event pool. */ - *_tx_el_current_event = (UCHAR *) (((ULONG) __ghsbegin_eventlog) + TX_EL_HEADER_SIZE + + *_tx_el_current_event = (UCHAR *) (((ULONG) __ghsbegin_eventlog) + TX_EL_HEADER_SIZE + (TX_EL_TNIS * TX_EL_TNI_ENTRY_SIZE)); work_ptr = work_ptr + sizeof(ULONG); @@ -166,17 +161,17 @@ UINT i; /* Clear the entire TNI array, this is the initial setting. */ end_ptr = work_ptr + (TX_EL_TNIS * TX_EL_TNI_ENTRY_SIZE); memset((void *)work_ptr, 0, (TX_EL_TNIS * TX_EL_TNI_ENTRY_SIZE)); - work_ptr = end_ptr; + work_ptr = end_ptr; /* At this point, we are pointing at the actual Event Entry area. */ - + /* Remember the start of the actual event log area. */ _tx_el_event_area_start = work_ptr; /* Clear the entire Event area. */ end_ptr = work_ptr + event_log_size; memset((void *)work_ptr, 0, event_log_size); - work_ptr = end_ptr; + work_ptr = end_ptr; /* Save the end pointer for later use. */ _tx_el_event_area_end = work_ptr; @@ -201,7 +196,7 @@ UINT i; { /* Yes, insert a NULL into the event log string. */ - *work_ptr = (unsigned char) 0; + *work_ptr = (unsigned char) 0; } /* Setup the thread ID to NULL. */ @@ -216,40 +211,40 @@ UINT i; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_thread_register PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_thread_register PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function registers a thread in the event log for future */ +/* */ +/* This function registers a thread in the event log for future */ /* display purposes. */ -/* */ -/* INPUT */ -/* */ -/* thread_ptr Pointer to thread control block */ -/* */ -/* OUTPUT */ -/* */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control block */ +/* */ +/* OUTPUT */ +/* */ /* TX_SUCCESS Thread was placed in TNI area */ /* TX_ERROR No more room in the TNI area */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_thread_create ThreadX thread create function */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create ThreadX thread create function */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -278,7 +273,7 @@ UINT i; i++; entry_ptr = entry_ptr + TX_EL_TNI_ENTRY_SIZE; } - + /* Check to see if there were no more valid entries. */ if (i >= TX_EL_TNIS) return(TX_EL_NO_MORE_TNI_ROOM); @@ -304,7 +299,7 @@ UINT i; { /* Yes, insert a NULL into the event log string. */ - *work_ptr = (unsigned char) 0; + *work_ptr = (unsigned char) 0; } /* Setup the thread ID. */ @@ -321,40 +316,40 @@ UINT i; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_thread_unregister PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_thread_unregister PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function unregisters a thread in the event log for future */ +/* */ +/* This function unregisters a thread in the event log for future */ /* display purposes. */ -/* */ -/* INPUT */ -/* */ -/* thread_ptr Pointer to thread control block */ -/* */ -/* OUTPUT */ -/* */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control block */ +/* */ +/* OUTPUT */ +/* */ /* TX_SUCCESS Thread was placed in TNI area */ /* TX_ERROR No more room in the TNI area */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_thread_create ThreadX thread create function */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create ThreadX thread create function */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -394,7 +389,7 @@ UINT i, j; } else if (*work_ptr == 0) { - + /* Null terminated, just break the loop. */ break; } @@ -426,7 +421,7 @@ UINT i, j; i++; entry_ptr = entry_ptr + TX_EL_TNI_ENTRY_SIZE; } - + /* Determine status to return. */ if (found) return(TX_SUCCESS); @@ -435,49 +430,49 @@ UINT i, j; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_user_event_insert PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_user_event_insert PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ +/* */ /* This function inserts a user event into the event log. */ -/* If the event log is full, the oldest event is overwritten. */ -/* */ -/* INPUT */ -/* */ +/* If the event log is full, the oldest event is overwritten. */ +/* */ +/* INPUT */ +/* */ /* sub_type Event subtype for kernel call */ /* info_1 First information field */ /* info_2 Second information field */ /* info_3 Third information field */ /* info_4 Fourth information field */ /* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* ThreadX services */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX services */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ -VOID _tx_el_user_event_insert(UINT sub_type, ULONG info_1, ULONG info_2, +VOID _tx_el_user_event_insert(UINT sub_type, ULONG info_1, ULONG info_2, ULONG info_3, ULONG info_4) { @@ -545,7 +540,7 @@ UCHAR *entry_ptr; if (entry_ptr >= _tx_el_event_area_end) { - /* Yes, we have wrapped around to the end of the event area. + /* Yes, we have wrapped around to the end of the event area. Start back at the top! */ entry_ptr = _tx_el_event_area_start; } @@ -558,41 +553,41 @@ UCHAR *entry_ptr; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_thread_running PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_thread_running PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ +/* */ /* This function inserts a thread change event into the event */ /* log, which indicates that a context switch is taking place. */ /* If the event log is full, the oldest event is overwritten. */ -/* */ -/* INPUT */ -/* */ +/* */ +/* INPUT */ +/* */ /* thread_ptr Pointer to thread being */ /* scheduled */ /* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_thread_schedule ThreadX scheduler */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_schedule ThreadX scheduler */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -604,7 +599,7 @@ VOID _tx_el_thread_running(TX_THREAD *thread_ptr) UINT upper_tb; UCHAR *entry_ptr; - TX_EL_NO_STATUS_EVENTS + TX_EL_NO_STATUS_EVENTS /* Increment total event counter. */ _tx_el_total_events++; @@ -646,7 +641,7 @@ UCHAR *entry_ptr; if (entry_ptr >= _tx_el_event_area_end) { - /* Yes, we have wrapped around to the end of the event area. + /* Yes, we have wrapped around to the end of the event area. Start back at the top! */ entry_ptr = _tx_el_event_area_start; } @@ -658,43 +653,43 @@ UCHAR *entry_ptr; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_thread_preempted PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_thread_preempted PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ +/* */ /* This function inserts a thread preempted event into the event */ /* log, which indicates that an interrupt occurred that made a higher */ /* priority thread ready for execution. In this case, the previously */ /* executing thread has an event entered to indicate it is no longer */ /* running. */ -/* */ -/* INPUT */ -/* */ +/* */ +/* INPUT */ +/* */ /* thread_ptr Pointer to thread being */ /* scheduled */ /* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_thread_context_restore ThreadX context restore */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_context_restore ThreadX context restore */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -707,7 +702,7 @@ UINT upper_tb; UCHAR *entry_ptr; - TX_EL_NO_STATUS_EVENTS + TX_EL_NO_STATUS_EVENTS /* Increment total event counter. */ _tx_el_total_events++; @@ -749,7 +744,7 @@ UCHAR *entry_ptr; if (entry_ptr >= _tx_el_event_area_end) { - /* Yes, we have wrapped around to the end of the event area. + /* Yes, we have wrapped around to the end of the event area. Start back at the top! */ entry_ptr = _tx_el_event_area_start; } @@ -761,40 +756,40 @@ UCHAR *entry_ptr; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_interrupt PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_interrupt PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ +/* */ /* This function inserts an interrupt event into the log, which */ /* indicates the start of interrupt processing for the specific */ -/* */ -/* INPUT */ -/* */ +/* */ +/* INPUT */ +/* */ /* interrupt_number Interrupt number supplied by */ /* ISR */ /* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* ISR processing */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISR processing */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -807,7 +802,7 @@ UINT upper_tb; UCHAR *entry_ptr; - TX_EL_NO_INTERRUPT_EVENTS + TX_EL_NO_INTERRUPT_EVENTS /* Increment total event counter. */ _tx_el_total_events++; @@ -853,7 +848,7 @@ UCHAR *entry_ptr; if (entry_ptr >= _tx_el_event_area_end) { - /* Yes, we have wrapped around to the end of the event area. + /* Yes, we have wrapped around to the end of the event area. Start back at the top! */ entry_ptr = _tx_el_event_area_start; } @@ -865,40 +860,40 @@ UCHAR *entry_ptr; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_interrupt_end PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_interrupt_end PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ +/* */ /* This function inserts an interrupt end event into the log, which */ /* indicates the end of interrupt processing for the specific */ -/* */ -/* INPUT */ -/* */ +/* */ +/* INPUT */ +/* */ /* interrupt_number Interrupt number supplied by */ /* ISR */ /* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* ISR processing */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISR processing */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -911,7 +906,7 @@ UINT upper_tb; UCHAR *entry_ptr; - TX_EL_NO_INTERRUPT_EVENTS + TX_EL_NO_INTERRUPT_EVENTS /* Increment total event counter. */ _tx_el_total_events++; @@ -957,7 +952,7 @@ UCHAR *entry_ptr; if (entry_ptr >= _tx_el_event_area_end) { - /* Yes, we have wrapped around to the end of the event area. + /* Yes, we have wrapped around to the end of the event area. Start back at the top! */ entry_ptr = _tx_el_event_area_start; } @@ -969,39 +964,39 @@ UCHAR *entry_ptr; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_interrupt_control PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_interrupt_control PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function remaps the tx_interrupt_control service call so that */ -/* it can be tracked in the event log. */ -/* */ -/* INPUT */ -/* */ +/* */ +/* This function remaps the tx_interrupt_control service call so that */ +/* it can be tracked in the event log. */ +/* */ +/* INPUT */ +/* */ /* new_posture New interrupt posture */ /* */ -/* OUTPUT */ -/* */ -/* old_posture Old interrupt posture */ -/* */ -/* CALLS */ -/* */ -/* _tx_thread_interrupt_control Interrupt control service */ -/* */ -/* CALLED BY */ -/* */ -/* ThreadX services */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt posture */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_interrupt_control Interrupt control service */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX services */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -1014,7 +1009,7 @@ TX_INTERRUPT_SAVE_AREA UINT old_posture; - TX_EL_NO_INTERRUPT_EVENTS + TX_EL_NO_INTERRUPT_EVENTS TX_DISABLE TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_INTERRUPT_CONTROL, _tx_thread_current_ptr, new_posture) @@ -1027,38 +1022,38 @@ UINT old_posture; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_event_log_on PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_event_log_on PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function disables all event filters. */ -/* */ -/* INPUT */ -/* */ -/* None */ /* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* This function disables all event filters. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -1072,39 +1067,39 @@ VOID _tx_el_event_log_on(void) } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_event_log_off PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_event_log_off PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function sets all event filters, thereby turning event */ -/* logging off. */ -/* */ -/* INPUT */ -/* */ -/* None */ /* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* This function sets all event filters, thereby turning event */ +/* logging off. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -1118,38 +1113,38 @@ VOID _tx_el_event_log_off(void) } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_event_log_set PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_event_log_set PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function sets the events filters specified by the user. */ -/* */ -/* INPUT */ -/* */ -/* filter Events to filter */ /* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* This function sets the events filters specified by the user. */ +/* */ +/* INPUT */ +/* */ +/* filter Events to filter */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ diff --git a/ports/cortex_m3/ghs/src/tx_ghs.c b/ports/cortex_m3/ghs/src/tx_ghs.c index 0be9d715..30b8054e 100644 --- a/ports/cortex_m3/ghs/src/tx_ghs.c +++ b/ports/cortex_m3/ghs/src/tx_ghs.c @@ -55,7 +55,7 @@ extern TX_THREAD *_tx_thread_current_ptr; If you customize the System Library, you should remove ind_thrd.c from the libsys.gpj subproject. - + */ /* Provide global __eh_globals value to support C++ exception handling diff --git a/ports/cortex_m3/ghs/src/tx_thread_context_restore.arm b/ports/cortex_m3/ghs/src/tx_thread_context_restore.arm index d89fcfd6..89e8f9d5 100644 --- a/ports/cortex_m3/ghs/src/tx_thread_context_restore.arm +++ b/ports/cortex_m3/ghs/src/tx_thread_context_restore.arm @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; diff --git a/ports/cortex_m3/ghs/src/tx_thread_context_save.arm b/ports/cortex_m3/ghs/src/tx_thread_context_save.arm index 13cd6d9e..ee496a2f 100644 --- a/ports/cortex_m3/ghs/src/tx_thread_context_save.arm +++ b/ports/cortex_m3/ghs/src/tx_thread_context_save.arm @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; diff --git a/ports/cortex_m3/ghs/src/tx_thread_interrupt_control.arm b/ports/cortex_m3/ghs/src/tx_thread_interrupt_control.arm index fa8e83a6..114674c6 100644 --- a/ports/cortex_m3/ghs/src/tx_thread_interrupt_control.arm +++ b/ports/cortex_m3/ghs/src/tx_thread_interrupt_control.arm @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; diff --git a/ports/cortex_m3/ghs/src/tx_thread_interrupt_disable.arm b/ports/cortex_m3/ghs/src/tx_thread_interrupt_disable.arm index 26dcfec2..295219c1 100644 --- a/ports/cortex_m3/ghs/src/tx_thread_interrupt_disable.arm +++ b/ports/cortex_m3/ghs/src/tx_thread_interrupt_disable.arm @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; diff --git a/ports/cortex_m3/ghs/src/tx_thread_interrupt_restore.arm b/ports/cortex_m3/ghs/src/tx_thread_interrupt_restore.arm index b850d47b..f841f177 100644 --- a/ports/cortex_m3/ghs/src/tx_thread_interrupt_restore.arm +++ b/ports/cortex_m3/ghs/src/tx_thread_interrupt_restore.arm @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; diff --git a/ports/cortex_m3/ghs/src/tx_thread_schedule.arm b/ports/cortex_m3/ghs/src/tx_thread_schedule.arm index 86ef0b20..aad9e090 100644 --- a/ports/cortex_m3/ghs/src/tx_thread_schedule.arm +++ b/ports/cortex_m3/ghs/src/tx_thread_schedule.arm @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; diff --git a/ports/cortex_m3/ghs/src/tx_thread_stack_build.arm b/ports/cortex_m3/ghs/src/tx_thread_stack_build.arm index 30a47d88..9e1494ea 100644 --- a/ports/cortex_m3/ghs/src/tx_thread_stack_build.arm +++ b/ports/cortex_m3/ghs/src/tx_thread_stack_build.arm @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; diff --git a/ports/cortex_m3/ghs/src/tx_thread_system_return.arm b/ports/cortex_m3/ghs/src/tx_thread_system_return.arm index a1cfe337..d62b43fd 100644 --- a/ports/cortex_m3/ghs/src/tx_thread_system_return.arm +++ b/ports/cortex_m3/ghs/src/tx_thread_system_return.arm @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; diff --git a/ports/cortex_m3/ghs/src/tx_timer_interrupt.arm b/ports/cortex_m3/ghs/src/tx_timer_interrupt.arm index 16d0c031..c17b147e 100644 --- a/ports/cortex_m3/ghs/src/tx_timer_interrupt.arm +++ b/ports/cortex_m3/ghs/src/tx_timer_interrupt.arm @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; diff --git a/ports/cortex_m3/gnu/example_build/cortexm3_crt0.S b/ports/cortex_m3/gnu/example_build/cortexm3_crt0.S index 4228fc11..e06430d7 100644 --- a/ports/cortex_m3/gnu/example_build/cortexm3_crt0.S +++ b/ports/cortex_m3/gnu/example_build/cortexm3_crt0.S @@ -39,7 +39,7 @@ crt0_ctor_loop: beq crt0_ctor_end ldr r2, [r0] add r0, #4 - push {r0-r1} + push {r0-r1} blx r2 pop {r0-r1} b crt0_ctor_loop @@ -88,4 +88,3 @@ memory_set_done: .section .stack, "wa", %nobits .section .stack_process, "wa", %nobits .section .heap, "wa", %nobits - \ No newline at end of file diff --git a/ports/cortex_m3/gnu/example_build/cortexm3_vectors.S b/ports/cortex_m3/gnu/example_build/cortexm3_vectors.S index 6ae558e4..dc8d0aad 100644 --- a/ports/cortex_m3/gnu/example_build/cortexm3_vectors.S +++ b/ports/cortex_m3/gnu/example_build/cortexm3_vectors.S @@ -4,8 +4,8 @@ .global __tx_BadHandler .global __tx_SVCallHandler .global __tx_DBGHandler - .global __tx_PendSVHandler - .global __tx_SysTickHandler + .global __tx_PendSVHandler + .global __tx_SysTickHandler .global __tx_BadHandler .syntax unified @@ -15,9 +15,9 @@ .global _vectors _vectors: - .word __stack_end__ - .word reset_handler - .word __tx_NMIHandler + .word __stack_end__ + .word reset_handler + .word __tx_NMIHandler .word __tx_HardfaultHandler .word __tx_BadHandler .word __tx_BadHandler @@ -29,7 +29,7 @@ _vectors: .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // .word __tx_DBGHandler .word 0 // Reserved - .word __tx_PendSVHandler + .word __tx_PendSVHandler .word __tx_SysTickHandler // Used by Threadx timer functionality .word __tx_BadHandler // Populate with user Interrupt handler .word __tx_BadHandler diff --git a/ports/cortex_m3/gnu/example_build/sample_threadx.c b/ports/cortex_m3/gnu/example_build/sample_threadx.c index 597f373c..13ffadba 100644 --- a/ports/cortex_m3/gnu/example_build/sample_threadx.c +++ b/ports/cortex_m3/gnu/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -81,42 +81,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -124,23 +124,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -243,11 +243,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -306,7 +306,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -359,7 +359,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_m3/gnu/example_build/sample_threadx.ld b/ports/cortex_m3/gnu/example_build/sample_threadx.ld index c65a1346..3f19c29e 100644 --- a/ports/cortex_m3/gnu/example_build/sample_threadx.ld +++ b/ports/cortex_m3/gnu/example_build/sample_threadx.ld @@ -10,7 +10,7 @@ __HEAPSIZE__ = 128; SECTIONS { - .vectors : + .vectors : { KEEP(*(.vectors .vectors.*)) } > FLASH @@ -45,7 +45,7 @@ SECTIONS KEEP(*(.eh_frame*)) } > FLASH - .ARM.extab : + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH @@ -59,7 +59,7 @@ SECTIONS __data_load_start__ = ALIGN (4); - .data : AT (__data_load_start__) + .data : AT (__data_load_start__) { __data_start__ = .; @@ -89,7 +89,7 @@ SECTIONS KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ - + __data_end__ = .; } > RAM @@ -104,7 +104,7 @@ SECTIONS __bss_end__ = .; } > RAM - + .heap (COPY): { __heap_start__ = ALIGN(4); diff --git a/ports/cortex_m3/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_m3/gnu/example_build/tx_initialize_low_level.S index c0dbf150..1a724410 100644 --- a/ports/cortex_m3/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m3/gnu/example_build/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,16 +73,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 William E. Lamie Modified Comment(s), fixed */ -/* GNU assembly comment, clean */ -/* up whitespace, resulting */ -/* in version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports/cortex_m3/gnu/inc/tx_port.h b/ports/cortex_m3/gnu/inc/tx_port.h index 02d61f38..23affb8b 100644 --- a/ports/cortex_m3/gnu/inc/tx_port.h +++ b/ports/cortex_m3/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,23 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comments, updated */ -/* typedef to fix misra */ -/* violation, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -371,7 +355,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -530,7 +514,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #endif @@ -715,7 +699,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M3/GNU Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3/GNU Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m3/gnu/readme_threadx.txt b/ports/cortex_m3/gnu/readme_threadx.txt index d9063d65..58181f85 100644 --- a/ports/cortex_m3/gnu/readme_threadx.txt +++ b/ports/cortex_m3/gnu/readme_threadx.txt @@ -5,15 +5,15 @@ 1. Building the ThreadX run-time Library -Navigate to the "example_build" directory. Ensure that -you have setup your path and other environment variables necessary for the ARM -GNU compiler. At this point you may run the build_threadx.bat batch file. -This will build the ThreadX run-time environment in the "example_build" -directory. +Navigate to the "example_build" directory. Ensure that +you have setup your path and other environment variables necessary for the ARM +GNU compiler. At this point you may run the build_threadx.bat batch file. +This will build the ThreadX run-time environment in the "example_build" +directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. @@ -22,25 +22,25 @@ application in order to use ThreadX. The ThreadX demonstration is designed to execute on Cortex-M evaluation boards or on a dedicated simulator. -Building the demonstration is easy, simply execute the build_threadx_sample.bat +Building the demonstration is easy, simply execute the build_threadx_sample.bat batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with tx.a. The resulting file sample_threadx.out is a binary +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.out is a binary file that can be downloaded and executed on the a simulator, or downloaded to a board. 3. System Initialization -The entry point in ThreadX for the Cortex-M using gnu tools uses the standard GNU +The entry point in ThreadX for the Cortex-M using gnu tools uses the standard GNU Cortex-M reset sequence. From the reset vector the C runtime will be initialized. -The ThreadX tx_initialize_low_level.S file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. +The ThreadX tx_initialize_low_level.S file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. @@ -49,7 +49,7 @@ parameter to your application definition function, tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -132,34 +132,34 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 5. Improving Performance -The distribution version of ThreadX is built without any compiler optimizations. -This makes it easy to debug because you can trace or set breakpoints inside of -ThreadX itself. Of course, this costs some performance. To make it run faster, -you can change the build_threadx.bat file to remove the -g option and enable -all compiler optimizations. +The distribution version of ThreadX is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX itself. Of course, this costs some performance. To make it run faster, +you can change the build_threadx.bat file to remove the -g option and enable +all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 6.1 Vector Area The Cortex-M vectors start at the label __tx_vectors or similar. The application may modify -the vector area according to its needs. There is code in tx_initialize_low_level() that will -configure the vector base register. +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. 6.2 Managed Interrupts -A ThreadX managed interrupt is defined below. By following these conventions, the +A ThreadX managed interrupt is defined below. By following these conventions, the application ISR is then allowed access to various ThreadX services from the ISR. Here is the standard template for managed ISRs in ThreadX: @@ -181,15 +181,15 @@ __tx_IntHandler: Note: the Cortex-M requires exception handlers to be thumb labels, this implies bit 0 set. To accomplish this, the declaration of the label has to be preceded by the assembler directive -.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to -be inserted in the correct location in the interrupt vector table. This table is typically +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically located in either your runtime startup file or in the tx_initialize_low_level.S file. 7. FPU Support -ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context - no additional setup by the application. diff --git a/ports/cortex_m3/gnu/src/tx_misra.S b/ports/cortex_m3/gnu/src/tx_misra.S index 8ac0c629..10548671 100644 --- a/ports/cortex_m3/gnu/src/tx_misra.S +++ b/ports/cortex_m3/gnu/src/tx_misra.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -667,7 +668,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -682,7 +683,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARM_FP /***********************************************************************************************/ @@ -699,8 +700,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -714,9 +715,9 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - + .data .word 0 diff --git a/ports/cortex_m3/gnu/src/tx_thread_context_restore.S b/ports/cortex_m3/gnu/src/tx_thread_context_restore.S index f36f0e79..1862bb58 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m3/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_m3/gnu/src/tx_thread_context_save.S b/ports/cortex_m3/gnu/src/tx_thread_context_save.S index bcc690d0..ac76a239 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m3/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_m3/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m3/gnu/src/tx_thread_interrupt_control.S index e7ea870e..a56149e3 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m3/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_m3/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_m3/gnu/src/tx_thread_interrupt_disable.S index b0169c6d..dee2237f 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m3/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports/cortex_m3/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_m3/gnu/src/tx_thread_interrupt_restore.S index ef0298b4..bd00f5f7 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m3/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports/cortex_m3/gnu/src/tx_thread_schedule.S b/ports/cortex_m3/gnu/src/tx_thread_schedule.S index 22f4f38b..9581ec38 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m3/gnu/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,18 +69,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Fixed predefined macro name, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_m3/gnu/src/tx_thread_stack_build.S b/ports/cortex_m3/gnu/src/tx_thread_stack_build.S index d78ebdc1..5b7d97c4 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m3/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_m3/gnu/src/tx_thread_system_return.S b/ports/cortex_m3/gnu/src/tx_thread_system_return.S index 3fa0c7a2..9d9a32fc 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m3/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_m3/gnu/src/tx_timer_interrupt.S b/ports/cortex_m3/gnu/src/tx_timer_interrupt.S index fc3e9db3..7f9a4359 100644 --- a/ports/cortex_m3/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_m3/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,17 +71,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_m3/iar/CMakeLists.txt b/ports/cortex_m3/iar/CMakeLists.txt index a524d79f..57be3aeb 100644 --- a/ports/cortex_m3/iar/CMakeLists.txt +++ b/ports/cortex_m3/iar/CMakeLists.txt @@ -7,7 +7,7 @@ target_sources(${PROJECT_NAME} ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_disable.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_restore.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_restore.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S diff --git a/ports/cortex_m3/iar/example_build/cstartup_M.s b/ports/cortex_m3/iar/example_build/cstartup_M.s index 75d9369b..d1c5aa3e 100644 --- a/ports/cortex_m3/iar/example_build/cstartup_M.s +++ b/ports/cortex_m3/iar/example_build/cstartup_M.s @@ -2,16 +2,16 @@ PUBLIC __vector_table SECTION .text:CODE:REORDER(1) - + ;; Keep vector table even if it's not referenced REQUIRE __vector_table - + THUMB - + ;; Forward declaration of sections. SECTION CSTACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) - + DATA __vector_table diff --git a/ports/cortex_m3/iar/example_build/sample_threadx.c b/ports/cortex_m3/iar/example_build/sample_threadx.c index c67d75d0..a12160fa 100644 --- a/ports/cortex_m3/iar/example_build/sample_threadx.c +++ b/ports/cortex_m3/iar/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -85,7 +85,7 @@ CHAR *pointer = TX_NULL; #ifdef TX_ENABLE_EVENT_TRACE tx_trace_enable(trace_buffer, sizeof(trace_buffer), 32); #endif - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(&byte_pool_0, "byte pool 0", byte_pool_memory, DEMO_BYTE_POOL_SIZE); @@ -96,42 +96,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -139,23 +139,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -258,11 +258,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -321,7 +321,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -374,7 +374,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_m3/iar/example_build/tx_initialize_low_level.s b/ports/cortex_m3/iar/example_build/tx_initialize_low_level.s index 4a62fd94..bf7b64b0 100644 --- a/ports/cortex_m3/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m3/iar/example_build/tx_initialize_low_level.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -73,12 +73,6 @@ __tx_free_memory_start ;/* */ ;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) ;{ diff --git a/ports/cortex_m3/iar/inc/tx_port.h b/ports/cortex_m3/iar/inc/tx_port.h index 54818730..ff8b75ca 100644 --- a/ports/cortex_m3/iar/inc/tx_port.h +++ b/ports/cortex_m3/iar/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,23 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comments, updated */ -/* typedef to fix misra */ -/* violation, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -371,7 +355,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -530,7 +514,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #endif @@ -715,7 +699,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M3/IAR Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3/IAR Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m3/iar/readme_threadx.txt b/ports/cortex_m3/iar/readme_threadx.txt index 28b54e03..388c40e6 100644 --- a/ports/cortex_m3/iar/readme_threadx.txt +++ b/ports/cortex_m3/iar/readme_threadx.txt @@ -6,45 +6,45 @@ 1. Building the ThreadX run-time Library Building the ThreadX library is easy. First, open the Azure RTOS workspace -azure_rtos.eww. Next, make the TX project the "active project" in the -IAR Embedded Workbench and select the "Make" button. You should observe -assembly and compilation of a series of ThreadX source files. This -results in the ThreadX run-time library file tx.a, which is needed by +azure_rtos.eww. Next, make the TX project the "active project" in the +IAR Embedded Workbench and select the "Make" button. You should observe +assembly and compilation of a series of ThreadX source files. This +results in the ThreadX run-time library file tx.a, which is needed by the application. 2. Demonstration System -The ThreadX demonstration is designed to execute under the IAR debugger under +The ThreadX demonstration is designed to execute under the IAR debugger under simulation. Building the demonstration is easy; simply open the threadx.www workspace file, -make the sample_threadx.ewp project the "active project" in the IAR Embedded +make the sample_threadx.ewp project the "active project" in the IAR Embedded Workbench, and select the "Make" button. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with tx.a. The resulting file sample_threadx.out is a -binary ELF file that can be downloaded and executed on the IAR Windows-based +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.out is a +binary ELF file that can be downloaded and executed on the IAR Windows-based Cortex-M simulator. 3. System Initialization -The entry point in ThreadX for the Cortex-M using IAR tools is at label -__iar_program_start. This is defined within the IAR compiler's startup code. -In addition, this is where all static and global preset C variable +The entry point in ThreadX for the Cortex-M using IAR tools is at label +__iar_program_start. This is defined within the IAR compiler's startup code. +In addition, this is where all static and global preset C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, and a periodic timer interrupt source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. By default, the vector area is defined at the top of cstartup_M.s, which is -a slightly modified from the base IAR file. +a slightly modified from the base IAR file. The _tx_initialize_low_level function inside of tx_initialize_low_level.s -also determines the first available address for use by the application, which -is supplied as the sole input parameter to your application definition function, -tx_application_define. To accomplish this, a section is created in -tx_initialize_low_level.s called FREE_MEM, which must be located after all +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all other RAM sections in memory. @@ -53,7 +53,7 @@ other RAM sections in memory. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -136,20 +136,20 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 5. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the ThreadX library project to enable various compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling -The Cortex-M vectors start at the label __vector_table and is defined in cstartup_M.s. +The Cortex-M vectors start at the label __vector_table and is defined in cstartup_M.s. The application may modify the vector area according to its needs. @@ -188,14 +188,14 @@ should have the following line added (if not already in place): initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application -The project options "General Options -> Library Configuration" should also have the +The project options "General Options -> Library Configuration" should also have the "Enable thread support in library" box selected. 8. VFP Support -ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context - no additional setup by the application. diff --git a/ports/cortex_m3/iar/src/tx_iar.c b/ports/cortex_m3/iar/src/tx_iar.c index ee47f10f..238b485e 100644 --- a/ports/cortex_m3/iar/src/tx_iar.c +++ b/ports/cortex_m3/iar/src/tx_iar.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports/cortex_m3/iar/src/tx_misra.s b/ports/cortex_m3/iar/src/tx_misra.s index f86d9a65..642bb89e 100644 --- a/ports/cortex_m3/iar/src/tx_misra.s +++ b/ports/cortex_m3/iar/src/tx_misra.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -120,7 +121,7 @@ SECTION `.data`:DATA:REORDER:NOROOT(2) DATA -// 51 CHAR _tx_version_id[100] = "Copyright (c) 2024 Microsoft Corporation. * ThreadX 6.1 MISRA C Compliant *"; +// 51 CHAR _tx_version_id[100] = "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX 6.1 MISRA C Compliant *"; _tx_version_id: DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H @@ -707,7 +708,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -722,7 +723,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARMVFP__ /***********************************************************************************************/ @@ -739,8 +740,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -754,10 +755,10 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - - + + SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2) SECTION_TYPE SHT_PROGBITS, 0 DATA diff --git a/ports/cortex_m3/iar/src/tx_thread_context_restore.s b/ports/cortex_m3/iar/src/tx_thread_context_restore.s index 35aeaf5b..96b7d2d7 100644 --- a/ports/cortex_m3/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_m3/iar/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_m3/iar/src/tx_thread_context_save.s b/ports/cortex_m3/iar/src/tx_thread_context_save.s index f8bf5036..9d575f8f 100644 --- a/ports/cortex_m3/iar/src/tx_thread_context_save.s +++ b/ports/cortex_m3/iar/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_m3/iar/src/tx_thread_interrupt_control.s b/ports/cortex_m3/iar/src/tx_thread_interrupt_control.s index a0f3a5d0..75952281 100644 --- a/ports/cortex_m3/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m3/iar/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_m3/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m3/iar/src/tx_thread_interrupt_disable.s index 999af964..ce7ceb62 100644 --- a/ports/cortex_m3/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m3/iar/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports/cortex_m3/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_m3/iar/src/tx_thread_interrupt_restore.s index 2e55ed27..3cc26d93 100644 --- a/ports/cortex_m3/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m3/iar/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports/cortex_m3/iar/src/tx_thread_schedule.s b/ports/cortex_m3/iar/src/tx_thread_schedule.s index 882d2017..0ef3a88e 100644 --- a/ports/cortex_m3/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m3/iar/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,17 +68,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 04-25-2022 Scott Larson Added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_m3/iar/src/tx_thread_stack_build.s b/ports/cortex_m3/iar/src/tx_thread_stack_build.s index 116ba71c..eb2c3ffb 100644 --- a/ports/cortex_m3/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_m3/iar/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_m3/iar/src/tx_thread_system_return.s b/ports/cortex_m3/iar/src/tx_thread_system_return.s index a19bd35d..712a6e5c 100644 --- a/ports/cortex_m3/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m3/iar/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_m3/iar/src/tx_timer_interrupt.s b/ports/cortex_m3/iar/src/tx_timer_interrupt.s index a2d8ca32..2801dd7d 100644 --- a/ports/cortex_m3/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_m3/iar/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,18 +72,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_m3/keil/example_build/sample_threadx.c b/ports/cortex_m3/keil/example_build/sample_threadx.c index 96c4eb5a..34453f42 100644 --- a/ports/cortex_m3/keil/example_build/sample_threadx.c +++ b/ports/cortex_m3/keil/example_build/sample_threadx.c @@ -77,35 +77,35 @@ void tx_application_define(void *first_unused_memory) /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - thread_0_stack, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + thread_0_stack, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - thread_1_stack, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + thread_1_stack, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - thread_2_stack, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + thread_2_stack, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - thread_3_stack, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + thread_3_stack, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - thread_4_stack, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + thread_4_stack, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - thread_5_stack, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + thread_5_stack, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Create the message queue shared by threads 1 and 2. */ @@ -189,11 +189,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -252,7 +252,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ diff --git a/ports/cortex_m3/keil/example_build/tx_initialize_low_level.s b/ports/cortex_m3/keil/example_build/tx_initialize_low_level.s index 4ecf4ab2..9c6dd97c 100644 --- a/ports/cortex_m3/keil/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m3/keil/example_build/tx_initialize_low_level.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -121,12 +121,6 @@ Reset_Handler ;/* */ ;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) ;{ diff --git a/ports/cortex_m3/keil/inc/tx_port.h b/ports/cortex_m3/keil/inc/tx_port.h index 04e83be9..6ec876dc 100644 --- a/ports/cortex_m3/keil/inc/tx_port.h +++ b/ports/cortex_m3/keil/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,23 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comments, updated */ -/* typedef to fix misra */ -/* violation, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -371,7 +355,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -530,7 +514,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #endif @@ -715,7 +699,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M3/Keil Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3/Keil Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m3/keil/readme_threadx.txt b/ports/cortex_m3/keil/readme_threadx.txt index 9cd94bc2..7eee605e 100644 --- a/ports/cortex_m3/keil/readme_threadx.txt +++ b/ports/cortex_m3/keil/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for Cortex-M3 + Microsoft's Azure RTOS ThreadX for Cortex-M3 Thumb & 32-bit Mode @@ -6,29 +6,29 @@ 1. Building the ThreadX run-time Library -Building the ThreadX library is easy, simply load the project file -ThreadX_Library.Uv2, which is located inside the "example_build" directory. +Building the ThreadX library is easy, simply load the project file +ThreadX_Library.Uv2, which is located inside the "example_build" directory. Once the ThreadX library files are displayed in the project window, select the "Build Target" operation and observe the compilation and assembly -of the ThreadX library. This project build produces the ThreadX library +of the ThreadX library. This project build produces the ThreadX library file ThreadX_Library.lib. 2. Demonstration System The ThreadX demonstration is designed to execute under the Keil simulator or -Cortex-M3 hardware. This demonstration is slightly smaller than typical ThreadX +Cortex-M3 hardware. This demonstration is slightly smaller than typical ThreadX demonstrations, and thus requires less than 7KB of Flash and less than 4KB of RAM. -Building the demonstration is easy; simply open the ThreadX demonstration -project file ThreadX_Demo.Uv2, which is located inside the "example_build" -directory. +Building the demonstration is easy; simply open the ThreadX demonstration +project file ThreadX_Demo.Uv2, which is located inside the "example_build" +directory. -Once open, select the "Build Target" operation and observe the compilation of -sample_threadx.c (which is the demonstration application) and linking with -ThreadX_Library.lib. The resulting file ThreadX_Demo.axf is a binary file that -can be downloaded and executed under the uVision simulator or Cortex-M3 hardware. +Once open, select the "Build Target" operation and observe the compilation of +sample_threadx.c (which is the demonstration application) and linking with +ThreadX_Library.lib. The resulting file ThreadX_Demo.axf is a binary file that +can be downloaded and executed under the uVision simulator or Cortex-M3 hardware. For simulator execution, the following memory regions need to be defined via the "Debug -> Memory Map" dialog: @@ -39,17 +39,17 @@ the "Debug -> Memory Map" dialog: 3. System Initialization -The entry point in ThreadX for the Cortex-M3 using Keil tools is at label -__main. This is defined within the Keil compiler's startup code. In -addition, this is where all static and global pre-set C variable +The entry point in ThreadX for the Cortex-M3 using Keil tools is at label +__main. This is defined within the Keil compiler's startup code. In +addition, this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. @@ -58,11 +58,11 @@ parameter to your application definition function, tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M3 version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. - Stack Offset Stack Contents + Stack Offset Stack Contents 0x00 r4 0x04 r5 @@ -84,21 +84,21 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. 5. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make it run faster, you can change the ThreadX_Library.Uv2 -project to debugging and enable all compiler optimizations. +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the ThreadX_Library.Uv2 +project to debugging and enable all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M3 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: diff --git a/ports/cortex_m3/keil/src/tx_thread_context_restore.s b/ports/cortex_m3/keil/src/tx_thread_context_restore.s index c7cd720d..bdb0e782 100644 --- a/ports/cortex_m3/keil/src/tx_thread_context_restore.s +++ b/ports/cortex_m3/keil/src/tx_thread_context_restore.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -62,12 +62,6 @@ ;/* */ ;/* ISRs Interrupt Service Routines */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) ;{ diff --git a/ports/cortex_m3/keil/src/tx_thread_context_save.s b/ports/cortex_m3/keil/src/tx_thread_context_save.s index e6fe47cb..09fc9959 100644 --- a/ports/cortex_m3/keil/src/tx_thread_context_save.s +++ b/ports/cortex_m3/keil/src/tx_thread_context_save.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -61,12 +61,6 @@ ;/* */ ;/* ISRs */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) ;{ diff --git a/ports/cortex_m3/keil/src/tx_thread_interrupt_control.s b/ports/cortex_m3/keil/src/tx_thread_interrupt_control.s index 2d7fa49c..29bf8f5c 100644 --- a/ports/cortex_m3/keil/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m3/keil/src/tx_thread_interrupt_control.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -52,12 +52,6 @@ ;/* */ ;/* Application Code */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) ;{ diff --git a/ports/cortex_m3/keil/src/tx_thread_interrupt_disable.s b/ports/cortex_m3/keil/src/tx_thread_interrupt_disable.s index a63737ab..d40d4550 100644 --- a/ports/cortex_m3/keil/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m3/keil/src/tx_thread_interrupt_disable.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -52,12 +52,6 @@ ;/* */ ;/* Application Code */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) ;{ diff --git a/ports/cortex_m3/keil/src/tx_thread_interrupt_restore.s b/ports/cortex_m3/keil/src/tx_thread_interrupt_restore.s index 29ff36ec..6661a9d3 100644 --- a/ports/cortex_m3/keil/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m3/keil/src/tx_thread_interrupt_restore.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -52,12 +52,6 @@ ;/* */ ;/* Application Code */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) ;{ diff --git a/ports/cortex_m3/keil/src/tx_thread_schedule.s b/ports/cortex_m3/keil/src/tx_thread_schedule.s index afaa3082..bef93a8e 100644 --- a/ports/cortex_m3/keil/src/tx_thread_schedule.s +++ b/ports/cortex_m3/keil/src/tx_thread_schedule.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -71,15 +71,6 @@ ;/* _tx_thread_system_return Return to system from thread */ ;/* _tx_thread_context_restore Restore thread's context */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 03-02-2021 Scott Larson Modified comment(s), add */ -;/* low power code, */ -;/* resulting in version 6.1.5 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) ;{ diff --git a/ports/cortex_m3/keil/src/tx_thread_stack_build.s b/ports/cortex_m3/keil/src/tx_thread_stack_build.s index cf5cf6a3..a01b9daa 100644 --- a/ports/cortex_m3/keil/src/tx_thread_stack_build.s +++ b/ports/cortex_m3/keil/src/tx_thread_stack_build.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -54,12 +54,6 @@ ;/* */ ;/* _tx_thread_create Create thread service */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) ;{ diff --git a/ports/cortex_m3/keil/src/tx_thread_system_return.s b/ports/cortex_m3/keil/src/tx_thread_system_return.s index 80bb5259..75f43ee5 100644 --- a/ports/cortex_m3/keil/src/tx_thread_system_return.s +++ b/ports/cortex_m3/keil/src/tx_thread_system_return.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -54,12 +54,6 @@ ;/* */ ;/* ThreadX components */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) ;{ diff --git a/ports/cortex_m3/keil/src/tx_timer_interrupt.s b/ports/cortex_m3/keil/src/tx_timer_interrupt.s index 2ad0ac89..5946c7e6 100644 --- a/ports/cortex_m3/keil/src/tx_timer_interrupt.s +++ b/ports/cortex_m3/keil/src/tx_timer_interrupt.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -71,12 +71,6 @@ ;/* */ ;/* interrupt vector */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) ;{ diff --git a/ports/cortex_m33/ac6/example_build/ARMCM33_DSP_FP_TZ_config.txt b/ports/cortex_m33/ac6/example_build/ARMCM33_DSP_FP_TZ_config.txt index 04e32d1f..b65ba4c8 100644 --- a/ports/cortex_m33/ac6/example_build/ARMCM33_DSP_FP_TZ_config.txt +++ b/ports/cortex_m33/ac6/example_build/ARMCM33_DSP_FP_TZ_config.txt @@ -14,7 +14,7 @@ cpu0.INITNSVTOR=0x0 # (int , init-time) defa cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set -idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write diff --git a/ports/cortex_m33/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h b/ports/cortex_m33/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h index 1eb74752..262dc09b 100644 --- a/ports/cortex_m33/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h +++ b/ports/cortex_m33/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'ThreadX_Library' - * Target: 'ThreadX_Library_Project' + * Project: 'ThreadX_Library' + * Target: 'ThreadX_Library_Project' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h" diff --git a/ports/cortex_m33/ac6/example_build/demo_secure_zone/Abstract.txt b/ports/cortex_m33/ac6/example_build/demo_secure_zone/Abstract.txt index 0d1d8c52..f2b8a819 100644 --- a/ports/cortex_m33/ac6/example_build/demo_secure_zone/Abstract.txt +++ b/ports/cortex_m33/ac6/example_build/demo_secure_zone/Abstract.txt @@ -1,10 +1,10 @@ This ARM Cortex-M33 secure/non-secure example project that -shows the setup of the CMSIS-RTOS2 RTX for TrustZone for -ARMv8-M applications. +shows the setup of the CMSIS-RTOS2 RTX for TrustZone for +ARMv8-M applications. The application uses CMSIS and can be executed on a Fixed -Virtual Platform (FVP) simulation model. The application -demonstrates three RTOS threads. +Virtual Platform (FVP) simulation model. The application +demonstrates three RTOS threads. Secure application: diff --git a/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c b/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c index 2df478ae..3d625287 100644 --- a/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c +++ b/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c @@ -94,7 +94,7 @@ void SystemInit (void) #endif SystemCoreClock = SYSTEM_CLOCK; - + *(uint32_t *)0xE000ED24 = 0x000F0000; /* S: enable secure, usage, bus, mem faults */ *(uint32_t *)0xE002ED24 = 0x000F0000; /* NS: enable secure, usage, bus, mem faults */ } diff --git a/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h index 65bfdcd7..ebbc79c0 100644 --- a/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h +++ b/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'demo_secure_zone' - * Target: 'FVP Simulation Model' + * Project: 'demo_secure_zone' + * Target: 'FVP Simulation Model' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h" diff --git a/ports/cortex_m33/ac6/example_build/demo_secure_zone/interface.c b/ports/cortex_m33/ac6/example_build/demo_secure_zone/interface.c index 4e6e8eee..af6533c3 100644 --- a/ports/cortex_m33/ac6/example_build/demo_secure_zone/interface.c +++ b/ports/cortex_m33/ac6/example_build/demo_secure_zone/interface.c @@ -31,19 +31,19 @@ typedef funcptr funcptr_NS __attribute__((cmse_nonsecure_call)); /* Non-secure callable (entry) function */ -int func1(int x) __attribute__((cmse_nonsecure_entry)) { - return x+3; +int func1(int x) __attribute__((cmse_nonsecure_entry)) { + return x+3; } /* Non-secure callable (entry) function, calling a non-secure callback function */ int func2(funcptr callback, int x) __attribute__((cmse_nonsecure_entry)) { funcptr_NS callback_NS; // non-secure callback function pointer int y; - + /* return function pointer with cleared LSB */ callback_NS = (funcptr_NS)cmse_nsfptr_create(callback); - + y = callback_NS (x+1); - + return (y+2); } diff --git a/ports/cortex_m33/ac6/example_build/demo_secure_zone/main_ns.c b/ports/cortex_m33/ac6/example_build/demo_secure_zone/main_ns.c index a65b6880..04d857ff 100644 --- a/ports/cortex_m33/ac6/example_build/demo_secure_zone/main_ns.c +++ b/ports/cortex_m33/ac6/example_build/demo_secure_zone/main_ns.c @@ -63,7 +63,7 @@ void ThreadA (void *argument) { static int callbackB (int val) { uint32_t flags; - + flags = osThreadFlagsWait (1U, osFlagsWaitAny, osWaitForever); if (flags == 1U) { return (val+1); diff --git a/ports/cortex_m33/ac6/example_build/demo_secure_zone/main_s.c b/ports/cortex_m33/ac6/example_build/demo_secure_zone/main_s.c index 2c667821..74fa242e 100644 --- a/ports/cortex_m33/ac6/example_build/demo_secure_zone/main_s.c +++ b/ports/cortex_m33/ac6/example_build/demo_secure_zone/main_s.c @@ -24,36 +24,36 @@ * Title: Code template for secure main function * *---------------------------------------------------------------------------*/ - + /* Use CMSE intrinsics */ #include #include #include "RTE_Components.h" #include CMSIS_device_header - + /* TZ_START_NS: Start address of non-secure application */ #ifndef TZ_START_NS #define TZ_START_NS (0x200000U) #endif - + /* typedef for non-secure callback functions */ typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call)); - + /* Secure main() */ int main(void) { funcptr_void NonSecure_ResetHandler; - + /* Add user setup code for secure part here*/ - + /* Set non-secure main stack (MSP_NS) */ __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS))); - + /* Get non-secure reset handler */ NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U))); - + /* Start non-secure state software application */ NonSecure_ResetHandler(); - + /* Non-secure software does not return, this code is not executed */ while (1) { __NOP(); diff --git a/ports/cortex_m33/ac6/example_build/demo_secure_zone/tz_context.c b/ports/cortex_m33/ac6/example_build/demo_secure_zone/tz_context.c index f3152890..ca7f0c56 100644 --- a/ports/cortex_m33/ac6/example_build/demo_secure_zone/tz_context.c +++ b/ports/cortex_m33/ac6/example_build/demo_secure_zone/tz_context.c @@ -24,7 +24,7 @@ * Title: Context Management for ARMv8-M TrustZone - Sample implementation * *---------------------------------------------------------------------------*/ - + #include "RTE_Components.h" #include CMSIS_device_header #include "tz_context.h" diff --git a/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c index e4871014..d0f6b08b 100644 --- a/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c +++ b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c @@ -24,17 +24,17 @@ * * ----------------------------------------------------------------------------- */ - + #include "cmsis_compiler.h" #include "rtx_os.h" - + // OS Idle Thread __WEAK __NO_RETURN void osRtxIdleThread (void *argument) { (void)argument; for (;;) {} } - + // OS Error Callback function __WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { (void)object_id; diff --git a/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h index 3021efbc..49fc392e 100644 --- a/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h +++ b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h @@ -24,52 +24,52 @@ * * ----------------------------------------------------------------------------- */ - + #ifndef RTX_CONFIG_H_ #define RTX_CONFIG_H_ - + #ifdef _RTE_ #include "RTE_Components.h" #ifdef RTE_RTX_CONFIG_H #include RTE_RTX_CONFIG_H #endif #endif - + //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - + // System Configuration // ======================= - + // Global Dynamic Memory size [bytes] <0-1073741824:8> // Defines the combined global dynamic memory size. // Default: 4096 #ifndef OS_DYNAMIC_MEM_SIZE #define OS_DYNAMIC_MEM_SIZE 4096 #endif - + // Kernel Tick Frequency [Hz] <1-1000000> // Defines base time unit for delays and timeouts. // Default: 1000 (1ms tick) #ifndef OS_TICK_FREQ #define OS_TICK_FREQ 1000 #endif - + // Round-Robin Thread switching // Enables Round-Robin Thread switching. #ifndef OS_ROBIN_ENABLE #define OS_ROBIN_ENABLE 1 #endif - + // Round-Robin Timeout <1-1000> // Defines how many ticks a thread will execute before a thread switch. // Default: 5 #ifndef OS_ROBIN_TIMEOUT #define OS_ROBIN_TIMEOUT 5 #endif - + // - -// ISR FIFO Queue + +// ISR FIFO Queue // <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries // <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries // <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries @@ -78,38 +78,38 @@ #ifndef OS_ISR_FIFO_QUEUE #define OS_ISR_FIFO_QUEUE 16 #endif - + // Object Memory usage counters // Enables object memory usage counters (requires RTX source variant). #ifndef OS_OBJ_MEM_USAGE #define OS_OBJ_MEM_USAGE 0 #endif - + // - + // Thread Configuration // ======================= - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_THREAD_OBJ_MEM #define OS_THREAD_OBJ_MEM 0 #endif - + // Number of user Threads <1-1000> // Defines maximum number of user threads that can be active at the same time. // Applies to user threads with system provided memory for control blocks. #ifndef OS_THREAD_NUM #define OS_THREAD_NUM 1 #endif - + // Number of user Threads with default Stack size <0-1000> // Defines maximum number of user threads with default stack size. // Applies to user threads with zero stack size specified. #ifndef OS_THREAD_DEF_STACK_NUM #define OS_THREAD_DEF_STACK_NUM 0 #endif - + // Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> // Defines the combined stack size for user threads with user-provided stack size. // Applies to user threads with user-provided stack size and system provided memory for stack. @@ -117,23 +117,23 @@ #ifndef OS_THREAD_USER_STACK_SIZE #define OS_THREAD_USER_STACK_SIZE 0 #endif - + // - + // Default Thread Stack size [bytes] <96-1073741824:8> // Defines stack size for threads with zero stack size specified. // Default: 256 #ifndef OS_STACK_SIZE #define OS_STACK_SIZE 256 #endif - + // Idle Thread Stack size [bytes] <72-1073741824:8> // Defines stack size for Idle thread. // Default: 256 #ifndef OS_IDLE_THREAD_STACK_SIZE #define OS_IDLE_THREAD_STACK_SIZE 256 #endif - + // Idle Thread TrustZone Module Identifier // Defines TrustZone Thread Context Management Identifier. // Applies only to cores with TrustZone technology. @@ -141,49 +141,49 @@ #ifndef OS_IDLE_THREAD_TZ_MOD_ID #define OS_IDLE_THREAD_TZ_MOD_ID 0 #endif - + // Stack overrun checking // Enables stack overrun check at thread switch. // Enabling this option increases slightly the execution time of a thread switch. #ifndef OS_STACK_CHECK #define OS_STACK_CHECK 1 #endif - + // Stack usage watermark // Initializes thread stack with watermark pattern for analyzing stack usage. // Enabling this option increases significantly the execution time of thread creation. #ifndef OS_STACK_WATERMARK #define OS_STACK_WATERMARK 0 #endif - -// Processor mode for Thread execution -// <0=> Unprivileged mode + +// Processor mode for Thread execution +// <0=> Unprivileged mode // <1=> Privileged mode // Default: Privileged mode #ifndef OS_PRIVILEGE_MODE #define OS_PRIVILEGE_MODE 1 #endif - + // - + // Timer Configuration // ====================== - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_TIMER_OBJ_MEM #define OS_TIMER_OBJ_MEM 0 #endif - + // Number of Timer objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_TIMER_NUM #define OS_TIMER_NUM 1 #endif - + // - + // Timer Thread Priority // <8=> Low // <16=> Below Normal <24=> Normal <32=> Above Normal @@ -194,7 +194,7 @@ #ifndef OS_TIMER_THREAD_PRIO #define OS_TIMER_THREAD_PRIO 40 #endif - + // Timer Thread Stack size [bytes] <0-1073741824:8> // Defines stack size for Timer thread. // May be set to 0 when timers are not used. @@ -202,7 +202,7 @@ #ifndef OS_TIMER_THREAD_STACK_SIZE #define OS_TIMER_THREAD_STACK_SIZE 256 #endif - + // Timer Thread TrustZone Module Identifier // Defines TrustZone Thread Context Management Identifier. // Applies only to cores with TrustZone technology. @@ -210,7 +210,7 @@ #ifndef OS_TIMER_THREAD_TZ_MOD_ID #define OS_TIMER_THREAD_TZ_MOD_ID 0 #endif - + // Timer Callback Queue entries <0-256> // Number of concurrent active timer callback functions. // May be set to 0 when timers are not used. @@ -218,85 +218,85 @@ #ifndef OS_TIMER_CB_QUEUE #define OS_TIMER_CB_QUEUE 4 #endif - + // - + // Event Flags Configuration // ============================ - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_EVFLAGS_OBJ_MEM #define OS_EVFLAGS_OBJ_MEM 0 #endif - + // Number of Event Flags objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_EVFLAGS_NUM #define OS_EVFLAGS_NUM 1 #endif - + // - + // - + // Mutex Configuration // ====================== - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_MUTEX_OBJ_MEM #define OS_MUTEX_OBJ_MEM 0 #endif - + // Number of Mutex objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_MUTEX_NUM #define OS_MUTEX_NUM 1 #endif - + // - + // - + // Semaphore Configuration // ========================== - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_SEMAPHORE_OBJ_MEM #define OS_SEMAPHORE_OBJ_MEM 0 #endif - + // Number of Semaphore objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_SEMAPHORE_NUM #define OS_SEMAPHORE_NUM 1 #endif - + // - + // - + // Memory Pool Configuration // ============================ - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_MEMPOOL_OBJ_MEM #define OS_MEMPOOL_OBJ_MEM 0 #endif - + // Number of Memory Pool objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_MEMPOOL_NUM #define OS_MEMPOOL_NUM 1 #endif - + // Data Storage Memory size [bytes] <0-1073741824:8> // Defines the combined data storage memory size. // Applies to objects with system provided memory for data storage. @@ -304,27 +304,27 @@ #ifndef OS_MEMPOOL_DATA_SIZE #define OS_MEMPOOL_DATA_SIZE 0 #endif - + // - + // - + // Message Queue Configuration // ============================== - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_MSGQUEUE_OBJ_MEM #define OS_MSGQUEUE_OBJ_MEM 0 #endif - + // Number of Message Queue objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_MSGQUEUE_NUM #define OS_MSGQUEUE_NUM 1 #endif - + // Data Storage Memory size [bytes] <0-1073741824:8> // Defines the combined data storage memory size. // Applies to objects with system provided memory for data storage. @@ -332,26 +332,26 @@ #ifndef OS_MSGQUEUE_DATA_SIZE #define OS_MSGQUEUE_DATA_SIZE 0 #endif - + // - + // - + // Event Recorder Configuration // =============================== - + // Global Initialization // Initialize Event Recorder during 'osKernelInitialize'. #ifndef OS_EVR_INIT #define OS_EVR_INIT 0 #endif - + // Start recording // Start event recording after initialization. #ifndef OS_EVR_START #define OS_EVR_START 1 #endif - + // Global Event Filter Setup // Initial recording level applied to all components. // Error events @@ -362,11 +362,11 @@ #ifndef OS_EVR_LEVEL #define OS_EVR_LEVEL 0x00U #endif - + // RTOS Event Filter Setup // Recording levels for RTX components. // Only applicable if events for the respective component are generated. - + // Memory Management // Recording level for Memory Management events. // Error events @@ -374,10 +374,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_MEMORY_LEVEL +#ifndef OS_EVR_MEMORY_LEVEL #define OS_EVR_MEMORY_LEVEL 0x01U #endif - + // Kernel // Recording level for Kernel events. // Error events @@ -385,10 +385,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_KERNEL_LEVEL +#ifndef OS_EVR_KERNEL_LEVEL #define OS_EVR_KERNEL_LEVEL 0x01U #endif - + // Thread // Recording level for Thread events. // Error events @@ -396,10 +396,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_THREAD_LEVEL +#ifndef OS_EVR_THREAD_LEVEL #define OS_EVR_THREAD_LEVEL 0x05U #endif - + // Generic Wait // Recording level for Generic Wait events. // Error events @@ -407,10 +407,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_WAIT_LEVEL +#ifndef OS_EVR_WAIT_LEVEL #define OS_EVR_WAIT_LEVEL 0x01U #endif - + // Thread Flags // Recording level for Thread Flags events. // Error events @@ -418,10 +418,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_THFLAGS_LEVEL +#ifndef OS_EVR_THFLAGS_LEVEL #define OS_EVR_THFLAGS_LEVEL 0x01U #endif - + // Event Flags // Recording level for Event Flags events. // Error events @@ -429,10 +429,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_EVFLAGS_LEVEL +#ifndef OS_EVR_EVFLAGS_LEVEL #define OS_EVR_EVFLAGS_LEVEL 0x01U #endif - + // Timer // Recording level for Timer events. // Error events @@ -440,10 +440,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_TIMER_LEVEL +#ifndef OS_EVR_TIMER_LEVEL #define OS_EVR_TIMER_LEVEL 0x01U #endif - + // Mutex // Recording level for Mutex events. // Error events @@ -451,10 +451,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_MUTEX_LEVEL +#ifndef OS_EVR_MUTEX_LEVEL #define OS_EVR_MUTEX_LEVEL 0x01U #endif - + // Semaphore // Recording level for Semaphore events. // Error events @@ -462,10 +462,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_SEMAPHORE_LEVEL +#ifndef OS_EVR_SEMAPHORE_LEVEL #define OS_EVR_SEMAPHORE_LEVEL 0x01U #endif - + // Memory Pool // Recording level for Memory Pool events. // Error events @@ -473,10 +473,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_MEMPOOL_LEVEL +#ifndef OS_EVR_MEMPOOL_LEVEL #define OS_EVR_MEMPOOL_LEVEL 0x01U #endif - + // Message Queue // Recording level for Message Queue events. // Error events @@ -484,87 +484,87 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_MSGQUEUE_LEVEL +#ifndef OS_EVR_MSGQUEUE_LEVEL #define OS_EVR_MSGQUEUE_LEVEL 0x01U #endif - + // - + // - + // RTOS Event Generation // Enables event generation for RTX components (requires RTX source variant). - + // Memory Management // Enables Memory Management event generation. #ifndef OS_EVR_MEMORY #define OS_EVR_MEMORY 1 #endif - + // Kernel // Enables Kernel event generation. #ifndef OS_EVR_KERNEL #define OS_EVR_KERNEL 1 #endif - + // Thread // Enables Thread event generation. #ifndef OS_EVR_THREAD #define OS_EVR_THREAD 1 #endif - + // Generic Wait // Enables Generic Wait event generation. #ifndef OS_EVR_WAIT #define OS_EVR_WAIT 1 #endif - + // Thread Flags // Enables Thread Flags event generation. #ifndef OS_EVR_THFLAGS #define OS_EVR_THFLAGS 1 #endif - + // Event Flags // Enables Event Flags event generation. #ifndef OS_EVR_EVFLAGS #define OS_EVR_EVFLAGS 1 #endif - + // Timer // Enables Timer event generation. #ifndef OS_EVR_TIMER #define OS_EVR_TIMER 1 #endif - + // Mutex // Enables Mutex event generation. #ifndef OS_EVR_MUTEX #define OS_EVR_MUTEX 1 #endif - + // Semaphore // Enables Semaphore event generation. #ifndef OS_EVR_SEMAPHORE #define OS_EVR_SEMAPHORE 1 #endif - + // Memory Pool // Enables Memory Pool event generation. #ifndef OS_EVR_MEMPOOL #define OS_EVR_MEMPOOL 1 #endif - + // Message Queue // Enables Message Queue event generation. #ifndef OS_EVR_MSGQUEUE #define OS_EVR_MSGQUEUE 1 #endif - + // - + // - + // Number of Threads which use standard C/C++ library libspace // (when thread specific memory allocation is not used). #if (OS_THREAD_OBJ_MEM == 0) @@ -572,7 +572,7 @@ #else #define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM #endif - + //------------- <<< end of configuration section >>> --------------------------- - + #endif // RTX_CONFIG_H_ diff --git a/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h index 78d1b429..62e042d2 100644 --- a/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h +++ b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'demo_threadx_non-secure_zone' - * Target: 'FVP Simulation Model' + * Project: 'demo_threadx_non-secure_zone' + * Target: 'FVP Simulation Model' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h" diff --git a/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h index 1eb74752..262dc09b 100644 --- a/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h +++ b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'ThreadX_Library' - * Target: 'ThreadX_Library_Project' + * Project: 'ThreadX_Library' + * Target: 'ThreadX_Library_Project' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h" diff --git a/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c index 7257ac6d..cea22889 100644 --- a/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c +++ b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete description of this demonstration. */ @@ -68,7 +68,7 @@ void thread_6_and_7_entry(ULONG thread_input); int main() { - + /* Please refer to Chapter 6 of the ThreadX User Guide for a complete description of this demonstration. */ @@ -86,7 +86,7 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer; (VOID)first_unused_memory; /* unused parameter. */ - + #ifdef TX_ENABLE_EVENT_TRACE tx_trace_enable(trace_buffer, sizeof(trace_buffer), 32); #endif @@ -101,41 +101,41 @@ CHAR *pointer; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -143,23 +143,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -188,7 +188,7 @@ CHAR *pointer; /* Release the block back to the pool. */ tx_block_release(pointer); - + tx_thread_secure_stack_allocate(&thread_0,256); tx_thread_secure_stack_allocate(&thread_1,256); tx_thread_secure_stack_allocate(&thread_2,256); @@ -206,13 +206,13 @@ CHAR *pointer; void thread_0_entry(ULONG thread_input) { UINT status; - + (VOID)thread_input; /* unused parameter. */ - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { - + /* Increment the thread counter. */ thread_0_counter++; @@ -235,11 +235,11 @@ void thread_1_entry(ULONG thread_input) UINT status; (VOID)thread_input; /* unused parameter. */ - + /* This thread simply sends messages to a queue shared by thread 2. */ while(1) { - + /* Increment the thread counter. */ thread_1_counter++; @@ -263,7 +263,7 @@ ULONG received_message; UINT status; (VOID)thread_input; /* unused parameter. */ - + /* This thread retrieves messages placed on the queue by thread 1. */ while(1) { @@ -274,11 +274,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -289,7 +289,7 @@ void thread_3_and_4_entry(ULONG thread_input) { UINT status; - + /* This function is executed from thread 3 and thread 4. As the loop below shows, these function compete for ownership of semaphore_0. */ while(1) @@ -328,7 +328,7 @@ UINT status; ULONG actual_flags; (VOID)thread_input; /* unused parameter. */ - + /* This thread simply waits for an event in a forever loop. */ while(1) { @@ -337,7 +337,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -390,7 +390,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_m33/ac6/example_build/tx_initialize_low_level.S b/ports/cortex_m33/ac6/example_build/tx_initialize_low_level.S index 765b8174..2f10e84a 100644 --- a/ports/cortex_m33/ac6/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m33/ac6/example_build/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,12 +63,6 @@ HEAP_SIZE = 0x00000000 /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports/cortex_m33/ac6/inc/tx_port.h b/ports/cortex_m33/ac6/inc/tx_port.h index bf50152d..e2a8f6e6 100644 --- a/ports/cortex_m33/ac6/inc/tx_port.h +++ b/ports/cortex_m33/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,39 +46,6 @@ /* This file replaces the previous Cortex-M33 files. It unifies */ /* the Cortex-M33 compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-02-2021 Scott Larson Modified comment(s), added */ -/* ULONG64_DEFINED, */ -/* resulting in version 6.1.5 */ -/* 06-02-2021 Scott Larson Modified comment(s), removed */ -/* unneeded header file, funcs */ -/* set_control and get_control */ -/* changed to inline, */ -/* added symbol to enable */ -/* stack error handler, */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ -/* stack check error handling, */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), unified */ -/* this file across compilers, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* 03-08-2023 Scott Larson Removed unneeded #include, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -645,7 +613,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M33/AC6 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M33/AC6 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m33/ac6/inc/tx_secure_interface.h b/ports/cortex_m33/ac6/inc/tx_secure_interface.h index 39b5d5fd..5ac37fbf 100644 --- a/ports/cortex_m33/ac6/inc/tx_secure_interface.h +++ b/ports/cortex_m33/ac6/inc/tx_secure_interface.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,12 +38,6 @@ /* It is assumed that tx_api.h and tx_port.h have already been */ /* included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_SECURE_INTERFACE_H diff --git a/ports/cortex_m33/ac6/readme_threadx.txt b/ports/cortex_m33/ac6/readme_threadx.txt index 9311ffd4..a99a096a 100644 --- a/ports/cortex_m33/ac6/readme_threadx.txt +++ b/ports/cortex_m33/ac6/readme_threadx.txt @@ -1,46 +1,46 @@ - Microsoft's Azure RTOS ThreadX for Cortex-M33 + Microsoft's Azure RTOS ThreadX for Cortex-M33 Using the AC6 Tools in Keil uVision 1. Import the ThreadX Projects -In order to build the ThreadX library and the ThreadX demonstration, first open -the AzureRTOS.uvmpw workspace (located in the "example_build" directory) +In order to build the ThreadX library and the ThreadX demonstration, first open +the AzureRTOS.uvmpw workspace (located in the "example_build" directory) into Keil. 2. Building the ThreadX run-time Library Building the ThreadX library is easy; simply set the ThreadX_Library project -as active, then then build the library. You should now observe the compilation +as active, then then build the library. You should now observe the compilation and assembly of the ThreadX library. This project build produces the ThreadX library file ThreadX_Library.lib. -Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c -replace the common files of the same name. +Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c +replace the common files of the same name. 3. Demonstration System The ThreadX demonstration is designed to execute under the Keil debugger on the FVP_MPS2_Cortex-M33_MDK simulator. -Building the demonstration is easy; simply select the "Batch Build" button. -You should now observe the compilation and assembly of the ThreadX demonstration of -both the demo_secure_zone and demo_threadx_non-secure_zone projects. +Building the demonstration is easy; simply select the "Batch Build" button. +You should now observe the compilation and assembly of the ThreadX demonstration of +both the demo_secure_zone and demo_threadx_non-secure_zone projects. Then click the Start/Stop Debug Session button to start the simulator and begin debugging. You are now ready to execute the ThreadX demonstration. 4. System Initialization -The entry point in ThreadX for the Cortex-M33 using AC6 tools uses the standard AC6 +The entry point in ThreadX for the Cortex-M33 using AC6 tools uses the standard AC6 Cortex-M33 reset sequence. From the reset vector the C runtime will be initialized. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. @@ -49,7 +49,7 @@ parameter to your application definition function, tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M33 version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -132,26 +132,26 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 6. Improving Performance -To make ThreadX and the application(s) run faster, you can enable -all compiler optimizations. +To make ThreadX and the application(s) run faster, you can enable +all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M33 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-M33 vectors start at the label __Vectors or similar. The application may modify -the vector area according to its needs. There is code in tx_initialize_low_level() that will -configure the vector base register. +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. 7.2 Managed Interrupts @@ -177,7 +177,7 @@ your_assembly_isr: ; VOID your_assembly_isr(VOID) ; { PUSH {r0, lr} -; +; ; /* Do interrupt handler work here */ ; /* BL */ @@ -187,15 +187,15 @@ your_assembly_isr: Note: the Cortex-M33 requires exception handlers to be thumb labels, this implies bit 0 set. To accomplish this, the declaration of the label has to be preceded by the assembler directive -.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to -be inserted in the correct location in the interrupt vector table. This table is typically +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically located in either your runtime startup file or in the tx_initialize_low_level.s file. 8. FPU Support -ThreadX for Cortex-M33 supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-M33 supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context. diff --git a/ports/cortex_m33/ac6/src/tx_initialize_low_level.S b/ports/cortex_m33/ac6/src/tx_initialize_low_level.S index 04bd54c2..896abe06 100644 --- a/ports/cortex_m33/ac6/src/tx_initialize_low_level.S +++ b/ports/cortex_m33/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ HEAP_SIZE = 0x00000000 /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports/cortex_m33/ac6/src/tx_misra.S b/ports/cortex_m33/ac6/src/tx_misra.S index 8ac0c629..10548671 100644 --- a/ports/cortex_m33/ac6/src/tx_misra.S +++ b/ports/cortex_m33/ac6/src/tx_misra.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -667,7 +668,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -682,7 +683,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARM_FP /***********************************************************************************************/ @@ -699,8 +700,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -714,9 +715,9 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - + .data .word 0 diff --git a/ports/cortex_m33/ac6/src/tx_thread_context_restore.S b/ports/cortex_m33/ac6/src/tx_thread_context_restore.S index caaec9e6..da331bcc 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m33/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_m33/ac6/src/tx_thread_context_save.S b/ports/cortex_m33/ac6/src/tx_thread_context_save.S index 71c1a185..3519b6cb 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m33/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_m33/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m33/ac6/src/tx_thread_interrupt_control.S index e2c9e1a5..a408e71d 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m33/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_m33/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_m33/ac6/src/tx_thread_interrupt_disable.S index 03e63305..8a56f098 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m33/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports/cortex_m33/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_m33/ac6/src/tx_thread_interrupt_restore.S index d88390fc..1a8e4767 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m33/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports/cortex_m33/ac6/src/tx_thread_schedule.S b/ports/cortex_m33/ac6/src/tx_thread_schedule.S index 1609d902..5aec68b6 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m33/ac6/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,23 +61,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 04-02-2021 Scott Larson Modified comment(s), added */ -/* low power code, */ -/* resulting in version 6.1.6 */ -/* 06-02-2021 Scott Larson Added secure stack initialize */ -/* in SVC handler, */ -/* resulting in version 6.1.7 */ -/* 04-25-2022 Scott Larson Added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 03-08-2023 Scott Larson Added preproc FPU option, */ -/* included tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -354,7 +338,7 @@ SVC_Handler: CMP r1, #2 // Is it a secure stack free request? BEQ _tx_svc_secure_free // Yes, go there - + CMP r1, #3 // Is it a secure stack init request? BEQ _tx_svc_secure_init // Yes, go there diff --git a/ports/cortex_m33/ac6/src/tx_thread_secure_stack.c b/ports/cortex_m33/ac6/src/tx_thread_secure_stack.c index 3f585b78..50b85fa1 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_secure_stack.c +++ b/ports/cortex_m33/ac6/src/tx_thread_secure_stack.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -102,21 +103,6 @@ static INT tx_head_free_index = 0U; /* */ /* _tx_initialize_kernel_enter */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-16-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.1 */ -/* 06-02-2021 Scott Larson Modified comment(s), and */ -/* changed name, execute in */ -/* handler mode, */ -/* resulting in version 6.1.7 */ -/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ -/* secure stack allocation, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_initialize(void) diff --git a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_allocate.S b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_allocate.S index 2b14e227..e6cb78d2 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_allocate.S +++ b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_allocate.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,14 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) // { diff --git a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_free.S b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_free.S index 33dc5fba..a2ebaab4 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_free.S +++ b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_free.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) // { diff --git a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_initialize.S b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_initialize.S index a5bab0f0..3413f31c 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_initialize.S +++ b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,18 +54,6 @@ /* */ /* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) // { diff --git a/ports/cortex_m33/ac6/src/tx_thread_stack_build.S b/ports/cortex_m33/ac6/src/tx_thread_stack_build.S index 7d39f949..02dcddf3 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_m33/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_m33/ac6/src/tx_thread_system_return.S b/ports/cortex_m33/ac6/src/tx_thread_system_return.S index 0a61cfc7..3c97b666 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m33/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_m33/ac6/src/tx_timer_interrupt.S b/ports/cortex_m33/ac6/src/tx_timer_interrupt.S index b8cc2be5..1182f910 100644 --- a/ports/cortex_m33/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_m33/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_m33/ac6/src/txe_thread_secure_stack_allocate.c b/ports/cortex_m33/ac6/src/txe_thread_secure_stack_allocate.c index 7d669a6f..344e5fd9 100644 --- a/ports/cortex_m33/ac6/src/txe_thread_secure_stack_allocate.c +++ b/ports/cortex_m33/ac6/src/txe_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { @@ -76,10 +71,10 @@ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_siz return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports/cortex_m33/ac6/src/txe_thread_secure_stack_free.c b/ports/cortex_m33/ac6/src/txe_thread_secure_stack_free.c index 55299fe9..76832975 100644 --- a/ports/cortex_m33/ac6/src/txe_thread_secure_stack_free.c +++ b/ports/cortex_m33/ac6/src/txe_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { @@ -74,10 +69,10 @@ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports/cortex_m33/gnu/inc/tx_port.h b/ports/cortex_m33/gnu/inc/tx_port.h index 08f0dab5..727e9fce 100644 --- a/ports/cortex_m33/gnu/inc/tx_port.h +++ b/ports/cortex_m33/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,39 +46,6 @@ /* This file replaces the previous Cortex-M33 files. It unifies */ /* the Cortex-M33 compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-02-2021 Scott Larson Modified comment(s), added */ -/* ULONG64_DEFINED, */ -/* resulting in version 6.1.5 */ -/* 06-02-2021 Scott Larson Modified comment(s), removed */ -/* unneeded header file, funcs */ -/* set_control and get_control */ -/* changed to inline, */ -/* added symbol to enable */ -/* stack error handler, */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ -/* stack check error handling, */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), unified */ -/* this file across compilers, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* 03-08-2023 Scott Larson Removed unneeded #include, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -645,7 +613,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M33/GNU Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M33/GNU Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m33/gnu/inc/tx_secure_interface.h b/ports/cortex_m33/gnu/inc/tx_secure_interface.h index 39b5d5fd..5ac37fbf 100644 --- a/ports/cortex_m33/gnu/inc/tx_secure_interface.h +++ b/ports/cortex_m33/gnu/inc/tx_secure_interface.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,12 +38,6 @@ /* It is assumed that tx_api.h and tx_port.h have already been */ /* included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_SECURE_INTERFACE_H diff --git a/ports/cortex_m33/gnu/readme_threadx.txt b/ports/cortex_m33/gnu/readme_threadx.txt index c7d5774e..79efe0eb 100644 --- a/ports/cortex_m33/gnu/readme_threadx.txt +++ b/ports/cortex_m33/gnu/readme_threadx.txt @@ -1,32 +1,32 @@ - Microsoft's Azure RTOS ThreadX for Cortex-M33 + Microsoft's Azure RTOS ThreadX for Cortex-M33 Using the GNU Tools 1. Building the ThreadX run-time Library Import all ThreadX common and port-specific source files into a GNU project. -Configure the project to build a library rather than an executable. This -results in the ThreadX run-time library file tx.a, which is needed by +Configure the project to build a library rather than an executable. This +results in the ThreadX run-time library file tx.a, which is needed by the application. -Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c -replace the common files of the same name. +Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c +replace the common files of the same name. 2. Demonstration System -No demonstration project is provided. +No demonstration project is provided. 3. System Initialization -The entry point in ThreadX for the Cortex-M33 using gnu tools uses the standard GNU +The entry point in ThreadX for the Cortex-M33 using gnu tools uses the standard GNU Cortex-M33 reset sequence. From the reset vector the C runtime will be initialized. -The ThreadX tx_initialize_low_level.S file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. +The ThreadX tx_initialize_low_level.S file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. @@ -35,7 +35,7 @@ parameter to your application definition function, tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M33 version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -118,26 +118,26 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 5. Improving Performance -To make ThreadX and the application(s) run faster, you can enable -all compiler optimizations. +To make ThreadX and the application(s) run faster, you can enable +all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M33 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 6.1 Vector Area The Cortex-M33 vectors start at the label __tx_vectors or similar. The application may modify -the vector area according to its needs. There is code in tx_initialize_low_level() that will -configure the vector base register. +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. 6.2 Managed Interrupts @@ -170,15 +170,15 @@ your_assembly_isr: Note: the Cortex-M33 requires exception handlers to be thumb labels, this implies bit 0 set. To accomplish this, the declaration of the label has to be preceded by the assembler directive -.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to -be inserted in the correct location in the interrupt vector table. This table is typically +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically located in either your runtime startup file or in the tx_initialize_low_level.S file. 7. FPU Support -ThreadX for Cortex-M33 supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-M33 supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context. diff --git a/ports/cortex_m33/gnu/src/tx_initialize_low_level.S b/ports/cortex_m33/gnu/src/tx_initialize_low_level.S index 31a22a2b..5915dc96 100644 --- a/ports/cortex_m33/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_m33/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,16 +66,6 @@ HEAP_SIZE = 0x00000000 /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Fixed predefined macro name, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports/cortex_m33/gnu/src/tx_misra.S b/ports/cortex_m33/gnu/src/tx_misra.S index 8ac0c629..10548671 100644 --- a/ports/cortex_m33/gnu/src/tx_misra.S +++ b/ports/cortex_m33/gnu/src/tx_misra.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -667,7 +668,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -682,7 +683,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARM_FP /***********************************************************************************************/ @@ -699,8 +700,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -714,9 +715,9 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - + .data .word 0 diff --git a/ports/cortex_m33/gnu/src/tx_thread_context_restore.S b/ports/cortex_m33/gnu/src/tx_thread_context_restore.S index fd4f1423..5d9d074a 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m33/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_m33/gnu/src/tx_thread_context_save.S b/ports/cortex_m33/gnu/src/tx_thread_context_save.S index 60105cd4..8d094cec 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m33/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_m33/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m33/gnu/src/tx_thread_interrupt_control.S index a1492269..4ce5bc22 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m33/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_m33/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_m33/gnu/src/tx_thread_interrupt_disable.S index a67dff03..463ceeee 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m33/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports/cortex_m33/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_m33/gnu/src/tx_thread_interrupt_restore.S index 6adc1d35..63667fa8 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m33/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports/cortex_m33/gnu/src/tx_thread_schedule.S b/ports/cortex_m33/gnu/src/tx_thread_schedule.S index 68368cd0..601d89da 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m33/gnu/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,24 +57,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 04-02-2021 Scott Larson Modified comment(s), added */ -/* low power code, */ -/* resulting in version 6.1.6 */ -/* 06-02-2021 Scott Larson Added secure stack initialize */ -/* in SVC handler, */ -/* resulting in version 6.1.7 */ -/* 01-31-2022 Scott Larson Fixed predefined macro name, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -351,7 +334,7 @@ SVC_Handler: CMP r1, #2 // Is it a secure stack free request? BEQ _tx_svc_secure_free // Yes, go there - + CMP r1, #3 // Is it a secure stack init request? BEQ _tx_svc_secure_init // Yes, go there diff --git a/ports/cortex_m33/gnu/src/tx_thread_secure_stack.c b/ports/cortex_m33/gnu/src/tx_thread_secure_stack.c index ac0e90a1..82acdfbb 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_secure_stack.c +++ b/ports/cortex_m33/gnu/src/tx_thread_secure_stack.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -98,21 +99,6 @@ static INT tx_head_free_index = 0U; /* */ /* _tx_initialize_kernel_enter */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-16-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.1 */ -/* 06-02-2021 Scott Larson Change name, execute in */ -/* handler mode, */ -/* disable optimizations, */ -/* resulting in version 6.1.7 */ -/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ -/* secure stack allocation, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry, optimize(0))) UINT _tx_thread_secure_mode_stack_initialize(void) diff --git a/ports/cortex_m33/gnu/src/tx_thread_secure_stack_allocate.S b/ports/cortex_m33/gnu/src/tx_thread_secure_stack_allocate.S index 9e875354..7a45b388 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_secure_stack_allocate.S +++ b/ports/cortex_m33/gnu/src/tx_thread_secure_stack_allocate.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,14 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) // { diff --git a/ports/cortex_m33/gnu/src/tx_thread_secure_stack_free.S b/ports/cortex_m33/gnu/src/tx_thread_secure_stack_free.S index bffb1d1e..950f1ce9 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_secure_stack_free.S +++ b/ports/cortex_m33/gnu/src/tx_thread_secure_stack_free.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) // { diff --git a/ports/cortex_m33/gnu/src/tx_thread_secure_stack_initialize.S b/ports/cortex_m33/gnu/src/tx_thread_secure_stack_initialize.S index 945adb75..4d778d5c 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_secure_stack_initialize.S +++ b/ports/cortex_m33/gnu/src/tx_thread_secure_stack_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,18 +54,6 @@ /* */ /* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) // { diff --git a/ports/cortex_m33/gnu/src/tx_thread_stack_build.S b/ports/cortex_m33/gnu/src/tx_thread_stack_build.S index 036b8238..df938e5e 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m33/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_m33/gnu/src/tx_thread_system_return.S b/ports/cortex_m33/gnu/src/tx_thread_system_return.S index 5649e3a7..17db56a5 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m33/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_m33/gnu/src/tx_timer_interrupt.S b/ports/cortex_m33/gnu/src/tx_timer_interrupt.S index 2e215343..869d81a7 100644 --- a/ports/cortex_m33/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_m33/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_m33/gnu/src/txe_thread_secure_stack_allocate.c b/ports/cortex_m33/gnu/src/txe_thread_secure_stack_allocate.c index 7d669a6f..344e5fd9 100644 --- a/ports/cortex_m33/gnu/src/txe_thread_secure_stack_allocate.c +++ b/ports/cortex_m33/gnu/src/txe_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { @@ -76,10 +71,10 @@ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_siz return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports/cortex_m33/gnu/src/txe_thread_secure_stack_free.c b/ports/cortex_m33/gnu/src/txe_thread_secure_stack_free.c index 55299fe9..76832975 100644 --- a/ports/cortex_m33/gnu/src/txe_thread_secure_stack_free.c +++ b/ports/cortex_m33/gnu/src/txe_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { @@ -74,10 +69,10 @@ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports/cortex_m33/iar/inc/tx_port.h b/ports/cortex_m33/iar/inc/tx_port.h index 36afbf7e..62f20620 100644 --- a/ports/cortex_m33/iar/inc/tx_port.h +++ b/ports/cortex_m33/iar/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,39 +46,6 @@ /* This file replaces the previous Cortex-M33 files. It unifies */ /* the Cortex-M33 compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-02-2021 Scott Larson Modified comment(s), added */ -/* ULONG64_DEFINED, */ -/* resulting in version 6.1.5 */ -/* 06-02-2021 Scott Larson Modified comment(s), removed */ -/* unneeded header file, funcs */ -/* set_control and get_control */ -/* changed to inline, */ -/* added symbol to enable */ -/* stack error handler, */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ -/* stack check error handling, */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), unified */ -/* this file across compilers, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* 03-08-2023 Scott Larson Removed unneeded #include, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -645,7 +613,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M33/IAR Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M33/IAR Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m33/iar/inc/tx_secure_interface.h b/ports/cortex_m33/iar/inc/tx_secure_interface.h index 39b5d5fd..5ac37fbf 100644 --- a/ports/cortex_m33/iar/inc/tx_secure_interface.h +++ b/ports/cortex_m33/iar/inc/tx_secure_interface.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,12 +38,6 @@ /* It is assumed that tx_api.h and tx_port.h have already been */ /* included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_SECURE_INTERFACE_H diff --git a/ports/cortex_m33/iar/readme_threadx.txt b/ports/cortex_m33/iar/readme_threadx.txt index 7758306e..ee6af2fa 100644 --- a/ports/cortex_m33/iar/readme_threadx.txt +++ b/ports/cortex_m33/iar/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for Cortex-M33 + Microsoft's Azure RTOS ThreadX for Cortex-M33 Using the IAR Tools @@ -6,33 +6,33 @@ 1. Building the ThreadX run-time Library Import all ThreadX common and port-specific source files into an IAR project. -Configure the project to build a library rather than an executable. This -results in the ThreadX run-time library file tx.a, which is needed by +Configure the project to build a library rather than an executable. This +results in the ThreadX run-time library file tx.a, which is needed by the application. -Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c -replace the common files of the same name. +Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c +replace the common files of the same name. 2. Demonstration System No demonstration is provided because the IAR EWARM 8.50 simulator does -not simulate the Cortex-M33 correctly. +not simulate the Cortex-M33 correctly. 3. System Initialization -The entry point in ThreadX for the Cortex-M33 using IAR tools is at label -__iar_program_start. This is defined within the IAR compiler's startup code. -In addition, this is where all static and global preset C variable +The entry point in ThreadX for the Cortex-M33 using IAR tools is at label +__iar_program_start. This is defined within the IAR compiler's startup code. +In addition, this is where all static and global preset C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, and a periodic timer interrupt source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. The _tx_initialize_low_level function inside of tx_initialize_low_level.s -also determines the first available address for use by the application, which -is supplied as the sole input parameter to your application definition function, -tx_application_define. To accomplish this, a section is created in -tx_initialize_low_level.s called FREE_MEM, which must be located after all +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all other RAM sections in memory. @@ -41,7 +41,7 @@ other RAM sections in memory. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M33 version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -124,17 +124,17 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 5. Improving Performance -To make ThreadX and the application(s) run faster, you can enable -all compiler optimizations. +To make ThreadX and the application(s) run faster, you can enable +all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling -The Cortex-M33 vectors start at the label __vector_table and is typically defined in a +The Cortex-M33 vectors start at the label __vector_table and is typically defined in a startup.s file (or similar). The application may modify the vector area according to its needs. @@ -182,14 +182,14 @@ should have the following line added (if not already in place): initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application -The project options "General Options -> Library Configuration" should also have the +The project options "General Options -> Library Configuration" should also have the "Enable thread support in library" box selected. 8. VFP Support -ThreadX for Cortex-M33 supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-M33 supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context. diff --git a/ports/cortex_m33/iar/src/tx_iar.c b/ports/cortex_m33/iar/src/tx_iar.c index ee47f10f..238b485e 100644 --- a/ports/cortex_m33/iar/src/tx_iar.c +++ b/ports/cortex_m33/iar/src/tx_iar.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports/cortex_m33/iar/src/tx_initialize_low_level.s b/ports/cortex_m33/iar/src/tx_initialize_low_level.s index 16fec218..8544e8a5 100644 --- a/ports/cortex_m33/iar/src/tx_initialize_low_level.s +++ b/ports/cortex_m33/iar/src/tx_initialize_low_level.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,13 +75,6 @@ __tx_free_memory_start /* CALLED BY */ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports/cortex_m33/iar/src/tx_misra.s b/ports/cortex_m33/iar/src/tx_misra.s index f86d9a65..642bb89e 100644 --- a/ports/cortex_m33/iar/src/tx_misra.s +++ b/ports/cortex_m33/iar/src/tx_misra.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -120,7 +121,7 @@ SECTION `.data`:DATA:REORDER:NOROOT(2) DATA -// 51 CHAR _tx_version_id[100] = "Copyright (c) 2024 Microsoft Corporation. * ThreadX 6.1 MISRA C Compliant *"; +// 51 CHAR _tx_version_id[100] = "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX 6.1 MISRA C Compliant *"; _tx_version_id: DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H @@ -707,7 +708,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -722,7 +723,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARMVFP__ /***********************************************************************************************/ @@ -739,8 +740,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -754,10 +755,10 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - - + + SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2) SECTION_TYPE SHT_PROGBITS, 0 DATA diff --git a/ports/cortex_m33/iar/src/tx_thread_context_restore.s b/ports/cortex_m33/iar/src/tx_thread_context_restore.s index ec1e10eb..3faf1113 100644 --- a/ports/cortex_m33/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_m33/iar/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,13 +56,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_m33/iar/src/tx_thread_context_save.s b/ports/cortex_m33/iar/src/tx_thread_context_save.s index 2d5629f9..2c623b9b 100644 --- a/ports/cortex_m33/iar/src/tx_thread_context_save.s +++ b/ports/cortex_m33/iar/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,13 +56,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_m33/iar/src/tx_thread_interrupt_control.s b/ports/cortex_m33/iar/src/tx_thread_interrupt_control.s index e268a93f..c33f8b70 100644 --- a/ports/cortex_m33/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m33/iar/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,13 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_m33/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m33/iar/src/tx_thread_interrupt_disable.s index c3b6c7d4..7df58dbf 100644 --- a/ports/cortex_m33/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m33/iar/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,13 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports/cortex_m33/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_m33/iar/src/tx_thread_interrupt_restore.s index 5cea7a57..443a5d51 100644 --- a/ports/cortex_m33/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m33/iar/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,13 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports/cortex_m33/iar/src/tx_thread_schedule.s b/ports/cortex_m33/iar/src/tx_thread_schedule.s index 231f69b5..af0f9196 100644 --- a/ports/cortex_m33/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m33/iar/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -73,23 +74,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 04-02-2021 Scott Larson Modified comment(s), added */ -/* low power code, */ -/* resulting in version 6.1.6 */ -/* 06-02-2021 Scott Larson Added secure stack initialize */ -/* in SVC handler, */ -/* resulting in version 6.1.7 */ -/* 04-25-2022 Scott Larson Added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 03-08-2023 Scott Larson Added preproc FPU option, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -348,7 +332,7 @@ SVC_Handler: CMP r1, #2 // Is it a secure stack free request? BEQ _tx_svc_secure_free // Yes, go there - + CMP r1, #3 // Is it a secure stack init request? BEQ _tx_svc_secure_init // Yes, go there diff --git a/ports/cortex_m33/iar/src/tx_thread_secure_stack.c b/ports/cortex_m33/iar/src/tx_thread_secure_stack.c index f2cf79f5..4e4a7803 100644 --- a/ports/cortex_m33/iar/src/tx_thread_secure_stack.c +++ b/ports/cortex_m33/iar/src/tx_thread_secure_stack.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -102,20 +103,6 @@ static INT tx_head_free_index = 0U; /* */ /* _tx_initialize_kernel_enter */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-16-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.1 */ -/* 06-02-2021 Scott Larson Change name, execute in */ -/* handler mode, */ -/* resulting in version 6.1.7 */ -/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ -/* secure stack allocation, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_initialize(void) diff --git a/ports/cortex_m33/iar/src/tx_thread_secure_stack_allocate.s b/ports/cortex_m33/iar/src/tx_thread_secure_stack_allocate.s index 49413f19..7a59008b 100644 --- a/ports/cortex_m33/iar/src/tx_thread_secure_stack_allocate.s +++ b/ports/cortex_m33/iar/src/tx_thread_secure_stack_allocate.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,13 +57,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) // { diff --git a/ports/cortex_m33/iar/src/tx_thread_secure_stack_free.s b/ports/cortex_m33/iar/src/tx_thread_secure_stack_free.s index 281feacb..f3431f06 100644 --- a/ports/cortex_m33/iar/src/tx_thread_secure_stack_free.s +++ b/ports/cortex_m33/iar/src/tx_thread_secure_stack_free.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,13 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) // { diff --git a/ports/cortex_m33/iar/src/tx_thread_secure_stack_initialize.s b/ports/cortex_m33/iar/src/tx_thread_secure_stack_initialize.s index 20d101eb..c8e75cdd 100644 --- a/ports/cortex_m33/iar/src/tx_thread_secure_stack_initialize.s +++ b/ports/cortex_m33/iar/src/tx_thread_secure_stack_initialize.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* CALLED BY */ /* */ /* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) // { diff --git a/ports/cortex_m33/iar/src/tx_thread_stack_build.s b/ports/cortex_m33/iar/src/tx_thread_stack_build.s index 51da3e87..68adac04 100644 --- a/ports/cortex_m33/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_m33/iar/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,13 +58,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_m33/iar/src/tx_thread_system_return.s b/ports/cortex_m33/iar/src/tx_thread_system_return.s index 9f2b721f..442e0e14 100644 --- a/ports/cortex_m33/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m33/iar/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,13 +58,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_m33/iar/src/tx_timer_interrupt.s b/ports/cortex_m33/iar/src/tx_timer_interrupt.s index edf7400b..de3cbf40 100644 --- a/ports/cortex_m33/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_m33/iar/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,13 +72,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_m33/iar/src/txe_thread_secure_stack_allocate.c b/ports/cortex_m33/iar/src/txe_thread_secure_stack_allocate.c index 7d669a6f..344e5fd9 100644 --- a/ports/cortex_m33/iar/src/txe_thread_secure_stack_allocate.c +++ b/ports/cortex_m33/iar/src/txe_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { @@ -76,10 +71,10 @@ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_siz return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports/cortex_m33/iar/src/txe_thread_secure_stack_free.c b/ports/cortex_m33/iar/src/txe_thread_secure_stack_free.c index 55299fe9..76832975 100644 --- a/ports/cortex_m33/iar/src/txe_thread_secure_stack_free.c +++ b/ports/cortex_m33/iar/src/txe_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { @@ -74,10 +69,10 @@ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports/cortex_m4/ac5/example_build/sample_threadx.c b/ports/cortex_m4/ac5/example_build/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports/cortex_m4/ac5/example_build/sample_threadx.c +++ b/ports/cortex_m4/ac5/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_m4/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_m4/ac5/example_build/tx_initialize_low_level.s index d6d6a6bf..5f5e42b5 100644 --- a/ports/cortex_m4/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m4/ac5/example_build/tx_initialize_low_level.s @@ -126,12 +126,6 @@ Reset_Handler ;/* */ ;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) ;{ diff --git a/ports/cortex_m4/ac5/inc/tx_port.h b/ports/cortex_m4/ac5/inc/tx_port.h index 46304cd8..87b3dd5c 100644 --- a/ports/cortex_m4/ac5/inc/tx_port.h +++ b/ports/cortex_m4/ac5/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,23 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comments, updated */ -/* typedef to fix misra */ -/* violation, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -371,7 +355,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -530,7 +514,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #endif @@ -715,7 +699,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M4/AC5 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4/AC5 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m4/ac5/readme_threadx.txt b/ports/cortex_m4/ac5/readme_threadx.txt index b7b7cee9..e261213e 100644 --- a/ports/cortex_m4/ac5/readme_threadx.txt +++ b/ports/cortex_m4/ac5/readme_threadx.txt @@ -5,14 +5,14 @@ 1. Building the ThreadX run-time Library -Navigate to the "example_build" directory. Ensure that -you have setup your path and other environment variables necessary for the AC5 -compiler. At this point you may run the build_threadx.bat batch file. This will -build the ThreadX run-time environment in the "example_build" directory. +Navigate to the "example_build" directory. Ensure that +you have setup your path and other environment variables necessary for the AC5 +compiler. At this point you may run the build_threadx.bat batch file. This will +build the ThreadX run-time environment in the "example_build" directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. @@ -21,28 +21,28 @@ application in order to use ThreadX. The ThreadX demonstration is designed to execute under the ARM DS Cortex-M simulator. -Building the demonstration is easy; simply execute the build_threadx_sample.bat +Building the demonstration is easy; simply execute the build_threadx_sample.bat batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with tx.a. The resulting file sample_threadx.axf +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.axf is a binary file that can be downloaded and executed on the ARM DS Cortex-M simulator. 3. System Initialization -The entry point in ThreadX for the Cortex-M using AC5 tools is at label -__main. This is defined within the AC5 compiler's startup code. In -addition, this is where all static and global pre-set C variable +The entry point in ThreadX for the Cortex-M using AC5 tools is at label +__main. This is defined within the AC5 compiler's startup code. In +addition, this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. @@ -51,7 +51,7 @@ parameter to your application definition function, tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -134,21 +134,21 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 5. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the ThreadX library project to enable various compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: @@ -187,8 +187,8 @@ your_assembly_isr 7. FPU Support -ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context - no additional setup by the application. diff --git a/ports/cortex_m4/ac5/src/tx_thread_context_restore.s b/ports/cortex_m4/ac5/src/tx_thread_context_restore.s index de72ba83..f401e147 100644 --- a/ports/cortex_m4/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_m4/ac5/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_m4/ac5/src/tx_thread_context_save.s b/ports/cortex_m4/ac5/src/tx_thread_context_save.s index 572f40a8..16d7536e 100644 --- a/ports/cortex_m4/ac5/src/tx_thread_context_save.s +++ b/ports/cortex_m4/ac5/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_m4/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_m4/ac5/src/tx_thread_interrupt_control.s index c64bac49..f3e273ed 100644 --- a/ports/cortex_m4/ac5/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m4/ac5/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_m4/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_m4/ac5/src/tx_thread_interrupt_disable.s index 58191f13..555691e4 100644 --- a/ports/cortex_m4/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m4/ac5/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports/cortex_m4/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_m4/ac5/src/tx_thread_interrupt_restore.s index 0564cfc5..7eb19d65 100644 --- a/ports/cortex_m4/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m4/ac5/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports/cortex_m4/ac5/src/tx_thread_schedule.s b/ports/cortex_m4/ac5/src/tx_thread_schedule.s index f6ff9510..f11a31c7 100644 --- a/ports/cortex_m4/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_m4/ac5/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,17 +68,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 04-25-2022 Scott Larson Added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_m4/ac5/src/tx_thread_stack_build.s b/ports/cortex_m4/ac5/src/tx_thread_stack_build.s index ce5e27db..5d090bbc 100644 --- a/ports/cortex_m4/ac5/src/tx_thread_stack_build.s +++ b/ports/cortex_m4/ac5/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_m4/ac5/src/tx_thread_system_return.s b/ports/cortex_m4/ac5/src/tx_thread_system_return.s index b32ebf2e..06d5ccae 100644 --- a/ports/cortex_m4/ac5/src/tx_thread_system_return.s +++ b/ports/cortex_m4/ac5/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_m4/ac5/src/tx_timer_interrupt.s b/ports/cortex_m4/ac5/src/tx_timer_interrupt.s index 3e66442b..e2682bf3 100644 --- a/ports/cortex_m4/ac5/src/tx_timer_interrupt.s +++ b/ports/cortex_m4/ac5/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,18 +72,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_m4/ac6/example_build/sample_threadx/.cproject b/ports/cortex_m4/ac6/example_build/sample_threadx/.cproject index c131df5e..f3357354 100644 --- a/ports/cortex_m4/ac6/example_build/sample_threadx/.cproject +++ b/ports/cortex_m4/ac6/example_build/sample_threadx/.cproject @@ -1,170 +1,170 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_m4/ac6/example_build/sample_threadx/exceptions.c b/ports/cortex_m4/ac6/example_build/sample_threadx/exceptions.c index 94c87d7a..f0dd8600 100644 --- a/ports/cortex_m4/ac6/example_build/sample_threadx/exceptions.c +++ b/ports/cortex_m4/ac6/example_build/sample_threadx/exceptions.c @@ -1,7 +1,7 @@ /* ** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ** Use, modification and redistribution of this file is subject to your possession of a -** valid End User License Agreement for the Arm Product of which these examples are part of +** valid End User License Agreement for the Arm Product of which these examples are part of ** and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.c index 597f373c..13ffadba 100644 --- a/ports/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -81,42 +81,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -124,23 +124,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -243,11 +243,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -306,7 +306,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -359,7 +359,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.scat index eb8e0c23..1b489e7d 100644 --- a/ports/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S index c60db600..16dd113e 100644 --- a/ports/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,10 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @@ -75,12 +75,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* */ @/* _tx_initialize_kernel_enter ThreadX entry function */ @/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) @{ diff --git a/ports/cortex_m4/ac6/example_build/tx/.cproject b/ports/cortex_m4/ac6/example_build/tx/.cproject index 91e9ca8f..3e44eb06 100644 --- a/ports/cortex_m4/ac6/example_build/tx/.cproject +++ b/ports/cortex_m4/ac6/example_build/tx/.cproject @@ -1,146 +1,146 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_m4/ac6/inc/tx_port.h b/ports/cortex_m4/ac6/inc/tx_port.h index d1c65859..fa109c52 100644 --- a/ports/cortex_m4/ac6/inc/tx_port.h +++ b/ports/cortex_m4/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,23 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comments, updated */ -/* typedef to fix misra */ -/* violation, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -371,7 +355,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -530,7 +514,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #endif @@ -715,7 +699,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M4/AC6 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4/AC6 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m4/ac6/readme_threadx.txt b/ports/cortex_m4/ac6/readme_threadx.txt index d98c90cb..6447c517 100644 --- a/ports/cortex_m4/ac6/readme_threadx.txt +++ b/ports/cortex_m4/ac6/readme_threadx.txt @@ -5,12 +5,12 @@ 1. Building the ThreadX run-time Library -In order to build the ThreadX library and the ThreadX demonstration, first import -the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +In order to build the ThreadX library and the ThreadX demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) into your DS workspace. -Building the ThreadX library is easy; simply right-click the Eclipse project -"tx" and then select the "Build Project" button. You should now observe the compilation +Building the ThreadX library is easy; simply right-click the Eclipse project +"tx" and then select the "Build Project" button. You should now observe the compilation and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. @@ -20,27 +20,27 @@ library file tx.a. The ThreadX demonstration is designed to execute under the DS debugger on the MPS2_Cortex_Mx Bare Metal simulator. -Building the demonstration is easy; simply right-click the Eclipse project -"sample_threadx" and then select the "Build Project" button. You should now observe -the compilation and assembly of the ThreadX demonstration. This project build produces -the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder +Building the demonstration is easy; simply right-click the Eclipse project +"sample_threadx" and then select the "Build Project" button. You should now observe +the compilation and assembly of the ThreadX demonstration. This project build produces +the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder in the Project Explorer window, right-click on the 'cortex-mx_tx.launch' file, click 'Debug As', and then click 'cortex-mx_tx' from the submenu. This will cause the -debugger to load the sample_threadx.axf ELF file and run to main. You are now ready +debugger to load the sample_threadx.axf ELF file and run to main. You are now ready to execute the ThreadX demonstration. 3. System Initialization -The entry point in ThreadX for the Cortex-M using AC6 tools uses the standard GNU +The entry point in ThreadX for the Cortex-M using AC6 tools uses the standard GNU Cortex-M reset sequence. From the reset vector the C runtime will be initialized. -The ThreadX tx_initialize_low_level.S file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. +The ThreadX tx_initialize_low_level.S file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. @@ -49,7 +49,7 @@ parameter to your application definition function, tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -132,34 +132,34 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 5. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the ThreadX library project to enable various compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 6.1 Vector Area The Cortex-M vectors start at the label __tx_vectors or similar. The application may modify -the vector area according to its needs. There is code in tx_initialize_low_level() that will -configure the vector base register. +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. 6.2 Managed Interrupts -A ThreadX managed interrupt is defined below. By following these conventions, the +A ThreadX managed interrupt is defined below. By following these conventions, the application ISR is then allowed access to various ThreadX services from the ISR. Here is the standard template for managed ISRs in ThreadX: @@ -181,15 +181,15 @@ __tx_IntHandler: Note: the Cortex-M requires exception handlers to be thumb labels, this implies bit 0 set. To accomplish this, the declaration of the label has to be preceded by the assembler directive -.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to -be inserted in the correct location in the interrupt vector table. This table is typically +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically located in either your runtime startup file or in the tx_initialize_low_level.S file. 7. FPU Support -ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context - no additional setup by the application. diff --git a/ports/cortex_m4/ac6/src/tx_misra.S b/ports/cortex_m4/ac6/src/tx_misra.S index 8ac0c629..10548671 100644 --- a/ports/cortex_m4/ac6/src/tx_misra.S +++ b/ports/cortex_m4/ac6/src/tx_misra.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -667,7 +668,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -682,7 +683,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARM_FP /***********************************************************************************************/ @@ -699,8 +700,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -714,9 +715,9 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - + .data .word 0 diff --git a/ports/cortex_m4/ac6/src/tx_thread_context_restore.S b/ports/cortex_m4/ac6/src/tx_thread_context_restore.S index d60cf6b8..330789f4 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m4/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_m4/ac6/src/tx_thread_context_save.S b/ports/cortex_m4/ac6/src/tx_thread_context_save.S index abc0ac5d..a6c1a053 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m4/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,14 +61,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_m4/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m4/ac6/src/tx_thread_interrupt_control.S index 76b114b8..51b0e3fe 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m4/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_m4/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_m4/ac6/src/tx_thread_interrupt_disable.S index b2fb050d..df262e8c 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m4/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports/cortex_m4/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_m4/ac6/src/tx_thread_interrupt_restore.S index 47c8f0f9..d3e167bd 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m4/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports/cortex_m4/ac6/src/tx_thread_schedule.S b/ports/cortex_m4/ac6/src/tx_thread_schedule.S index b02b6eee..0b15b4de 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m4/ac6/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,16 +71,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 04-25-2022 Scott Larson Added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_m4/ac6/src/tx_thread_stack_build.S b/ports/cortex_m4/ac6/src/tx_thread_stack_build.S index 8cdaa034..5ae2c8f7 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_m4/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_m4/ac6/src/tx_thread_system_return.S b/ports/cortex_m4/ac6/src/tx_thread_system_return.S index f75b1e7a..b4348f9d 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m4/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_m4/ac6/src/tx_timer_interrupt.S b/ports/cortex_m4/ac6/src/tx_timer_interrupt.S index f1f39c3f..1a52ecda 100644 --- a/ports/cortex_m4/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_m4/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,17 +71,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_m4/ghs/example_build/sample_threadx.c b/ports/cortex_m4/ghs/example_build/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports/cortex_m4/ghs/example_build/sample_threadx.c +++ b/ports/cortex_m4/ghs/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_m4/ghs/example_build/tx_initialize_low_level.arm b/ports/cortex_m4/ghs/example_build/tx_initialize_low_level.arm index 03a9a100..1a144b7b 100644 --- a/ports/cortex_m4/ghs/example_build/tx_initialize_low_level.arm +++ b/ports/cortex_m4/ghs/example_build/tx_initialize_low_level.arm @@ -1,18 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Initialize */ /** */ @@ -24,42 +24,42 @@ .text .align 4 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_initialize_low_level Cortex-M4/GHS */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M4/GHS */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function is responsible for any low-level processor */ -/* initialization, including setting up interrupt vectors, setting */ -/* up a periodic timer interrupt source, saving the system stack */ -/* pointer for use in ISR processing later, and finding the first */ -/* available RAM memory address for tx_application_define. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -71,7 +71,7 @@ _tx_initialize_low_level: /* Disable interrupts. */ - + CPSID i ; Disable interrupts @@ -79,7 +79,7 @@ _tx_initialize_low_level: /* _tx_thread_system_stack_ptr = (VOID_PTR) (sp); */ LDR r1,=_tx_thread_system_stack_ptr ; Pickup address of system stack ptr - STR sp, [r1] ; Save system stack + STR sp, [r1] ; Save system stack /* Save the first available memory address. */ @@ -95,14 +95,14 @@ _tx_initialize_low_level: LDR r0, =0xE0001000 ; Build address of DWT register LDR r1, [r0] ; Pickup the current value ORR r1, r1, 1 ; Set the CYCCNTENA bit - STR r1, [r0] ; Enable the cycle count register + STR r1, [r0] ; Enable the cycle count register /* Setup Vector Table Offset Register. */ - + MOV r0, 0xE000E000 ; Build address of NVIC registers LDR r1, =__vectors ; Pickup address of vector table - STR r1, [r0, 0xD08] ; Set vector table address + STR r1, [r0, 0xD08] ; Set vector table address /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ @@ -134,7 +134,7 @@ _tx_initialize_low_level: #endif /* Return to caller. */ - + BX lr ; Return to caller .type _tx_initialize_low_level,$function @@ -145,7 +145,7 @@ _tx_initialize_low_level: /* Define shells for each of the interrupt vectors. */ .globl __tx_BadHandler -__tx_BadHandler: +__tx_BadHandler: B __tx_BadHandler .type __tx_BadHandler,$function @@ -161,7 +161,7 @@ __tx_IntHandler: MOV r0, 0 ; Build interrupt code BL _tx_el_interrupt ; Call interrupt event logging #endif - + ; /* Do interrupt handler work here */ ; /* .... */ @@ -199,7 +199,7 @@ __tx_SysTickHandler: .size __tx_SysTickHandler,.-__tx_SysTickHandler - .globl __tx_NMIHandler + .globl __tx_NMIHandler __tx_NMIHandler: B __tx_NMIHandler @@ -220,7 +220,7 @@ __tx_SVCallHandler: B __tx_SVCallHandler .type __tx_SVCallHandler,$function - .size __tx_SVCallHandler,.-__tx_SVCallHandler + .size __tx_SVCallHandler,.-__tx_SVCallHandler /* Reference build options and version ID to ensure they come in. */ diff --git a/ports/cortex_m4/ghs/inc/tx_el.h b/ports/cortex_m4/ghs/inc/tx_el.h index 4662f241..72e5bbe3 100644 --- a/ports/cortex_m4/ghs/inc/tx_el.h +++ b/ports/cortex_m4/ghs/inc/tx_el.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** ThreadX/GHS Event Log (EL) */ @@ -20,27 +21,21 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* COMPONENT DEFINITION RELEASE */ -/* */ -/* tx_el.h PORTABLE C/GHS */ +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_el.h PORTABLE C/GHS */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file defines the ThreadX event log functions for the GHS MULTI */ -/* EventAnalyzer. It is assumed that tx_api.h and tx_port.h have */ -/* already been included. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This file defines the ThreadX event log functions for the GHS MULTI */ +/* EventAnalyzer. It is assumed that tx_api.h and tx_port.h have */ +/* already been included. */ /* */ /**************************************************************************/ @@ -53,16 +48,16 @@ #define TX_EL_VERSION_ID 2 /* Event log version ID */ #define TX_EL_HEADER_SIZE 24 /* Event log header size */ #define TX_EL_TNIS 16 /* Number of thread names supported */ - /* If the application needs to */ - /* track more thread names, just */ - /* increase this number and re- */ - /* build the ThreadX library. */ + /* If the application needs to */ + /* track more thread names, just */ + /* increase this number and re- */ + /* build the ThreadX library. */ #define TX_EL_TNI_ENTRY_SIZE 44 /* Thread name entries are 44 bytes */ #define TX_EL_TNI_NAME_SIZE 34 /* Thread name size in TNI */ #define TX_EL_NO_MORE_TNI_ROOM 1 /* Error return from thread register*/ -#define TX_EL_NAME_NOT_FOUND 2 /* Error return from un-register */ +#define TX_EL_NAME_NOT_FOUND 2 /* Error return from un-register */ #define TX_EL_EVENT_SIZE 32 /* Number of bytes in each event */ -#define TX_EL_VALID_ENTRY 1 /* Valid log entry */ +#define TX_EL_VALID_ENTRY 1 /* Valid log entry */ #define TX_EL_INVALID_ENTRY 0 /* Invalid log entry */ @@ -295,7 +290,7 @@ /* Define filter macros that are inserted in-line with the other macros below. */ -#ifdef TX_ENABLE_EVENT_FILTERS +#ifdef TX_ENABLE_EVENT_FILTERS #define TX_EL_NO_STATUS_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_STATUS_CHANGE)) { #define TX_EL_NO_INTERRUPT_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_INTERRUPTS)) { #define TX_EL_NO_THREAD_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_THREAD_CALLS)) { @@ -430,7 +425,7 @@ extern ULONG _tx_el_time_base_lower; VOID _tx_el_initialize(VOID); UINT _tx_el_thread_register(TX_THREAD *thread_ptr); UINT _tx_el_thread_unregister(TX_THREAD *thread_ptr); -VOID _tx_el_user_event_insert(UINT sub_type, ULONG info_1, ULONG info_2, +VOID _tx_el_user_event_insert(UINT sub_type, ULONG info_1, ULONG info_2, ULONG info_3, ULONG info_4); VOID _tx_el_thread_running(TX_THREAD *thread_ptr); VOID _tx_el_thread_preempted(TX_THREAD *thread_ptr); @@ -747,7 +742,7 @@ VOID _tx_el_event_filter_set(UINT filter); #define TX_EL_THREAD_UNREGISTER(a) \ _tx_el_thread_unregister(a); #define TX_EL_INITIALIZE _tx_el_initialize(); -#endif +#endif #else #define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(a, b, c, d, e) #define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(a, b, c, d) diff --git a/ports/cortex_m4/ghs/inc/tx_port.h b/ports/cortex_m4/ghs/inc/tx_port.h index 5d6b9be1..4382845a 100644 --- a/ports/cortex_m4/ghs/inc/tx_port.h +++ b/ports/cortex_m4/ghs/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -61,7 +53,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -112,7 +104,7 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY +#ifndef TX_TIMER_THREAD_PRIORITY #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -123,8 +115,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0 /* Enable interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -133,7 +125,7 @@ typedef unsigned short USHORT; */ #ifndef TX_TRACE_TIME_SOURCE -#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) #endif #ifndef TX_TRACE_TIME_MASK #define TX_TRACE_TIME_MASK 0xFFFFFFFFUL @@ -145,13 +137,13 @@ typedef unsigned short USHORT; /* Define the number of ticks per second. This informs the EventAnalyzer what the timestamps represent. By default, this is set to 1,000,000 i.e., one tick every microsecond. */ -#define TX_EL_TICKS_PER_SECOND 1000000 +#define TX_EL_TICKS_PER_SECOND 1000000 /* Define the method of how to get the upper and lower 32-bits of the time stamp. By default, simply - simulate the time-stamp source with a counter. */ + simulate the time-stamp source with a counter. */ -#define read_tbu() _tx_el_time_base_upper -#define read_tbl() ++_tx_el_time_base_lower +#define read_tbu() _tx_el_time_base_upper +#define read_tbl() ++_tx_el_time_base_lower /* Define the port specific options for the _tx_build_options variable. This variable indicates @@ -167,7 +159,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -179,19 +171,19 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #define TX_THREAD_EXTENSION_2 VOID * tx_thread_eh_globals; \ int Errno; /* errno. */ \ char * strtok_saved_pos; /* strtok() position. */ #ifndef TX_ENABLE_EXECUTION_CHANGE_NOTIFY -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -206,11 +198,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -240,7 +232,7 @@ typedef unsigned short USHORT; extern void __tx_cpp_exception_cleanup(TX_THREAD *thread_ptr); \ __tx_cpp_exception_cleanup(thread_ptr); \ } -#else +#else #define TX_THREAD_DELETE_EXTENSION(thread_ptr) \ { \ #pragma weak __cpp_exception_cleanup \ @@ -279,7 +271,7 @@ typedef unsigned short USHORT; /* Define the get system state macro. */ - + #ifndef TX_THREAD_GET_SYSTEM_STATE #define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __MRS(__IPSR)) #endif @@ -291,32 +283,32 @@ typedef unsigned short USHORT; zero after initialization for Cortex-M ports. */ #ifndef TX_THREAD_SYSTEM_RETURN_CHECK -#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); #endif -/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to prevent early scheduling on Cortex-M parts. */ - + #define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = __CLZ32(m); \ - b = 31 - b; + b = 31 - b; #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -386,7 +378,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M4/GHS Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4/GHS Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m4/ghs/readme_threadx.txt b/ports/cortex_m4/ghs/readme_threadx.txt index 86a49522..f57a1679 100644 --- a/ports/cortex_m4/ghs/readme_threadx.txt +++ b/ports/cortex_m4/ghs/readme_threadx.txt @@ -4,16 +4,16 @@ 1. Open the ThreadX Project Workspace -In order to build the ThreadX library and the ThreadX demonstration first load -the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the -"example_build" directory. +In order to build the ThreadX library and the ThreadX demonstration first load +the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the +"example_build" directory. 2. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply select the MULTI project file -tx.gpj and then select the build button. You should now observe the -compilation and assembly of the ThreadX library. This project build produces +Building the ThreadX library is easy; simply select the MULTI project file +tx.gpj and then select the build button. You should now observe the +compilation and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. @@ -21,52 +21,52 @@ the ThreadX library file tx.a. The ThreadX demonstration is designed to execute under the MULTI environment on the Green Hills Cortex-M4 simulator. The instructions that follow describe -how to get the ThreadX evaluation running under the MULTI Cortex-M4 simulation +how to get the ThreadX evaluation running under the MULTI Cortex-M4 simulation environment. -Building the demonstration is easy; simply select the MULTI project file -sample_threadx.gpj. At this point, select the "Project Build" button and observe -the compilation, assembly, and linkage of the ThreadX demonstration application. +Building the demonstration is easy; simply select the MULTI project file +sample_threadx.gpj. At this point, select the "Project Build" button and observe +the compilation, assembly, and linkage of the ThreadX demonstration application. -After the demonstration is built, invoke the MULTI ARM simulator by selecting -the simulator connection from within the sample_threadx.con connection file. -Once connected to the simulator, select the "Debug" button. You should now -observe the main function of sample_threadx.c. +After the demonstration is built, invoke the MULTI ARM simulator by selecting +the simulator connection from within the sample_threadx.con connection file. +Once connected to the simulator, select the "Debug" button. You should now +observe the main function of sample_threadx.c. -You are now ready to execute the ThreadX demonstration system. Select -breakpoints and data watches to observe the execution of the sample_threadx.c +You are now ready to execute the ThreadX demonstration system. Select +breakpoints and data watches to observe the execution of the sample_threadx.c application. 4. EventAnalyzer Demonstration -To build a demonstration system that also logs events for the MULTI EventAnalyzer, -perform the same steps as the regular demo, except build the ThreadX library with -txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. -The resulting image will log all system events, which can then be displayed by the +To build a demonstration system that also logs events for the MULTI EventAnalyzer, +perform the same steps as the regular demo, except build the ThreadX library with +txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. +The resulting image will log all system events, which can then be displayed by the MULTI EventAnalyzer. 5. System Initialization -The system entry point using the Green Hills tools is at the label _start. -This is defined within the crt0.arm file supplied by Green Hills. In addition, -this is where all static and global preset C variable initialization +The system entry point using the Green Hills tools is at the label _start. +This is defined within the crt0.arm file supplied by Green Hills. In addition, +this is where all static and global preset C variable initialization processing is called from. After the Green Hills startup function returns, ThreadX initialization is called. The main initialization function is _tx_initialize_low_level and -is located in the file tx_initialize_low_level.arm. This function is responsible -for setting up various system data structures, interrupt vectors, and the +is located in the file tx_initialize_low_level.arm. This function is responsible +for setting up various system data structures, interrupt vectors, and the periodic timer interrupt source of ThreadX. -In addition, _tx_initialize_low_level determines where the first available +In addition, _tx_initialize_low_level determines where the first available RAM memory address is located. This address is supplied to tx_application_define. -By default, the first available RAM memory address is assumed to start at the -beginning of the ThreadX section .free_mem. If changes are made to the -sample_threadx.ld file, the .free_mem section should remain the last allocated -section in the main RAM area. The starting address of this section is passed +By default, the first available RAM memory address is assumed to start at the +beginning of the ThreadX section .free_mem. If changes are made to the +sample_threadx.ld file, the .free_mem section should remain the last allocated +section in the main RAM area. The starting address of this section is passed to tx_application_define. @@ -75,7 +75,7 @@ to tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M4 version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -159,21 +159,21 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 7. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make ThreadX run faster, you can change the tx.gpj project -to disable debug information and enable the desired optimizations. +to disable debug information and enable the desired optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined before tx_api.h is included. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. 8. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M4 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: @@ -185,7 +185,7 @@ the vector area according to its needs. 8.2 Managed Interrupts -A ThreadX managed interrupt is defined below. By following these conventions, the +A ThreadX managed interrupt is defined below. By following these conventions, the application ISR is then allowed access to various ThreadX services from the ISR. Here is the standard template for managed ISRs in ThreadX: @@ -194,7 +194,7 @@ Here is the standard template for managed ISRs in ThreadX: __tx_IntHandler: PUSH {lr} BL _tx_thread_context_save - + /* Do interrupt handler work here */ B _tx_thread_context_restore @@ -204,7 +204,7 @@ __tx_IntHandler: By default, FPU support is disabled for each thread. If saving the context of the FPU registers is needed, the ThreadX library should be re-built with TX_ENABLE_FPU_SUPPORT defined. In addition, -the following API call must be made from the context of the application thread - before +the following API call must be made from the context of the application thread - before the FPU usage: void tx_thread_fpu_enable(void); @@ -231,7 +231,7 @@ information associated with this specific port of ThreadX: 03-02-2021 The following files were changed/added for version 6.1.5: tx_thread_schedule.s Added low power feature -05/19/2020 Initial ThreadX version of Cortex-M4/Green Hills port. +05/19/2020 Initial ThreadX version of Cortex-M4/Green Hills port. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_m4/ghs/src/tx_el.c b/ports/cortex_m4/ghs/src/tx_el.c index fd58768f..b5d3b8b7 100644 --- a/ports/cortex_m4/ghs/src/tx_el.c +++ b/ports/cortex_m4/ghs/src/tx_el.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** ThreadX/GHS Event Log (EL) */ /** */ @@ -49,44 +50,38 @@ extern TX_THREAD *_tx_thread_current_ptr; UINT _tx_thread_interrupt_control(UINT new_posture); -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_initialize PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_initialize PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function creates the Event Log (in the format dictated by the */ -/* GHS Event Analyzer) and sets up various information for subsequent */ -/* operation. The start and end of the Event Log is determined by the */ -/* .eventlog section in the linker control file. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function creates the Event Log (in the format dictated by the */ +/* GHS Event Analyzer) and sets up various information for subsequent */ +/* operation. The start and end of the Event Log is determined by the */ +/* .eventlog section in the linker control file. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ VOID _tx_el_initialize(VOID) @@ -150,7 +145,7 @@ UINT i; /* Setup event_ptr (pointer to oldest event) field to the start of the event pool. */ - *_tx_el_current_event = (UCHAR *) (((ULONG) __ghsbegin_eventlog) + TX_EL_HEADER_SIZE + + *_tx_el_current_event = (UCHAR *) (((ULONG) __ghsbegin_eventlog) + TX_EL_HEADER_SIZE + (TX_EL_TNIS * TX_EL_TNI_ENTRY_SIZE)); work_ptr = work_ptr + sizeof(ULONG); @@ -166,17 +161,17 @@ UINT i; /* Clear the entire TNI array, this is the initial setting. */ end_ptr = work_ptr + (TX_EL_TNIS * TX_EL_TNI_ENTRY_SIZE); memset((void *)work_ptr, 0, (TX_EL_TNIS * TX_EL_TNI_ENTRY_SIZE)); - work_ptr = end_ptr; + work_ptr = end_ptr; /* At this point, we are pointing at the actual Event Entry area. */ - + /* Remember the start of the actual event log area. */ _tx_el_event_area_start = work_ptr; /* Clear the entire Event area. */ end_ptr = work_ptr + event_log_size; memset((void *)work_ptr, 0, event_log_size); - work_ptr = end_ptr; + work_ptr = end_ptr; /* Save the end pointer for later use. */ _tx_el_event_area_end = work_ptr; @@ -201,7 +196,7 @@ UINT i; { /* Yes, insert a NULL into the event log string. */ - *work_ptr = (unsigned char) 0; + *work_ptr = (unsigned char) 0; } /* Setup the thread ID to NULL. */ @@ -216,40 +211,40 @@ UINT i; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_thread_register PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_thread_register PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function registers a thread in the event log for future */ +/* */ +/* This function registers a thread in the event log for future */ /* display purposes. */ -/* */ -/* INPUT */ -/* */ -/* thread_ptr Pointer to thread control block */ -/* */ -/* OUTPUT */ -/* */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control block */ +/* */ +/* OUTPUT */ +/* */ /* TX_SUCCESS Thread was placed in TNI area */ /* TX_ERROR No more room in the TNI area */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_thread_create ThreadX thread create function */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create ThreadX thread create function */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -278,7 +273,7 @@ UINT i; i++; entry_ptr = entry_ptr + TX_EL_TNI_ENTRY_SIZE; } - + /* Check to see if there were no more valid entries. */ if (i >= TX_EL_TNIS) return(TX_EL_NO_MORE_TNI_ROOM); @@ -304,7 +299,7 @@ UINT i; { /* Yes, insert a NULL into the event log string. */ - *work_ptr = (unsigned char) 0; + *work_ptr = (unsigned char) 0; } /* Setup the thread ID. */ @@ -321,40 +316,40 @@ UINT i; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_thread_unregister PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_thread_unregister PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function unregisters a thread in the event log for future */ +/* */ +/* This function unregisters a thread in the event log for future */ /* display purposes. */ -/* */ -/* INPUT */ -/* */ -/* thread_ptr Pointer to thread control block */ -/* */ -/* OUTPUT */ -/* */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control block */ +/* */ +/* OUTPUT */ +/* */ /* TX_SUCCESS Thread was placed in TNI area */ /* TX_ERROR No more room in the TNI area */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_thread_create ThreadX thread create function */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create ThreadX thread create function */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -394,7 +389,7 @@ UINT i, j; } else if (*work_ptr == 0) { - + /* Null terminated, just break the loop. */ break; } @@ -426,7 +421,7 @@ UINT i, j; i++; entry_ptr = entry_ptr + TX_EL_TNI_ENTRY_SIZE; } - + /* Determine status to return. */ if (found) return(TX_SUCCESS); @@ -435,49 +430,49 @@ UINT i, j; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_user_event_insert PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_user_event_insert PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ +/* */ /* This function inserts a user event into the event log. */ -/* If the event log is full, the oldest event is overwritten. */ -/* */ -/* INPUT */ -/* */ +/* If the event log is full, the oldest event is overwritten. */ +/* */ +/* INPUT */ +/* */ /* sub_type Event subtype for kernel call */ /* info_1 First information field */ /* info_2 Second information field */ /* info_3 Third information field */ /* info_4 Fourth information field */ /* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* ThreadX services */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX services */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ -VOID _tx_el_user_event_insert(UINT sub_type, ULONG info_1, ULONG info_2, +VOID _tx_el_user_event_insert(UINT sub_type, ULONG info_1, ULONG info_2, ULONG info_3, ULONG info_4) { @@ -545,7 +540,7 @@ UCHAR *entry_ptr; if (entry_ptr >= _tx_el_event_area_end) { - /* Yes, we have wrapped around to the end of the event area. + /* Yes, we have wrapped around to the end of the event area. Start back at the top! */ entry_ptr = _tx_el_event_area_start; } @@ -558,41 +553,41 @@ UCHAR *entry_ptr; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_thread_running PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_thread_running PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ +/* */ /* This function inserts a thread change event into the event */ /* log, which indicates that a context switch is taking place. */ /* If the event log is full, the oldest event is overwritten. */ -/* */ -/* INPUT */ -/* */ +/* */ +/* INPUT */ +/* */ /* thread_ptr Pointer to thread being */ /* scheduled */ /* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_thread_schedule ThreadX scheduler */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_schedule ThreadX scheduler */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -604,7 +599,7 @@ VOID _tx_el_thread_running(TX_THREAD *thread_ptr) UINT upper_tb; UCHAR *entry_ptr; - TX_EL_NO_STATUS_EVENTS + TX_EL_NO_STATUS_EVENTS /* Increment total event counter. */ _tx_el_total_events++; @@ -646,7 +641,7 @@ UCHAR *entry_ptr; if (entry_ptr >= _tx_el_event_area_end) { - /* Yes, we have wrapped around to the end of the event area. + /* Yes, we have wrapped around to the end of the event area. Start back at the top! */ entry_ptr = _tx_el_event_area_start; } @@ -658,43 +653,43 @@ UCHAR *entry_ptr; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_thread_preempted PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_thread_preempted PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ +/* */ /* This function inserts a thread preempted event into the event */ /* log, which indicates that an interrupt occurred that made a higher */ /* priority thread ready for execution. In this case, the previously */ /* executing thread has an event entered to indicate it is no longer */ /* running. */ -/* */ -/* INPUT */ -/* */ +/* */ +/* INPUT */ +/* */ /* thread_ptr Pointer to thread being */ /* scheduled */ /* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_thread_context_restore ThreadX context restore */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_context_restore ThreadX context restore */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -707,7 +702,7 @@ UINT upper_tb; UCHAR *entry_ptr; - TX_EL_NO_STATUS_EVENTS + TX_EL_NO_STATUS_EVENTS /* Increment total event counter. */ _tx_el_total_events++; @@ -749,7 +744,7 @@ UCHAR *entry_ptr; if (entry_ptr >= _tx_el_event_area_end) { - /* Yes, we have wrapped around to the end of the event area. + /* Yes, we have wrapped around to the end of the event area. Start back at the top! */ entry_ptr = _tx_el_event_area_start; } @@ -761,40 +756,40 @@ UCHAR *entry_ptr; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_interrupt PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_interrupt PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ +/* */ /* This function inserts an interrupt event into the log, which */ /* indicates the start of interrupt processing for the specific */ -/* */ -/* INPUT */ -/* */ +/* */ +/* INPUT */ +/* */ /* interrupt_number Interrupt number supplied by */ /* ISR */ /* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* ISR processing */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISR processing */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -807,7 +802,7 @@ UINT upper_tb; UCHAR *entry_ptr; - TX_EL_NO_INTERRUPT_EVENTS + TX_EL_NO_INTERRUPT_EVENTS /* Increment total event counter. */ _tx_el_total_events++; @@ -853,7 +848,7 @@ UCHAR *entry_ptr; if (entry_ptr >= _tx_el_event_area_end) { - /* Yes, we have wrapped around to the end of the event area. + /* Yes, we have wrapped around to the end of the event area. Start back at the top! */ entry_ptr = _tx_el_event_area_start; } @@ -865,40 +860,40 @@ UCHAR *entry_ptr; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_interrupt_end PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_interrupt_end PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ +/* */ /* This function inserts an interrupt end event into the log, which */ /* indicates the end of interrupt processing for the specific */ -/* */ -/* INPUT */ -/* */ +/* */ +/* INPUT */ +/* */ /* interrupt_number Interrupt number supplied by */ /* ISR */ /* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* ISR processing */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISR processing */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -911,7 +906,7 @@ UINT upper_tb; UCHAR *entry_ptr; - TX_EL_NO_INTERRUPT_EVENTS + TX_EL_NO_INTERRUPT_EVENTS /* Increment total event counter. */ _tx_el_total_events++; @@ -957,7 +952,7 @@ UCHAR *entry_ptr; if (entry_ptr >= _tx_el_event_area_end) { - /* Yes, we have wrapped around to the end of the event area. + /* Yes, we have wrapped around to the end of the event area. Start back at the top! */ entry_ptr = _tx_el_event_area_start; } @@ -969,39 +964,39 @@ UCHAR *entry_ptr; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_interrupt_control PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_interrupt_control PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function remaps the tx_interrupt_control service call so that */ -/* it can be tracked in the event log. */ -/* */ -/* INPUT */ -/* */ +/* */ +/* This function remaps the tx_interrupt_control service call so that */ +/* it can be tracked in the event log. */ +/* */ +/* INPUT */ +/* */ /* new_posture New interrupt posture */ /* */ -/* OUTPUT */ -/* */ -/* old_posture Old interrupt posture */ -/* */ -/* CALLS */ -/* */ -/* _tx_thread_interrupt_control Interrupt control service */ -/* */ -/* CALLED BY */ -/* */ -/* ThreadX services */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt posture */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_interrupt_control Interrupt control service */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX services */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -1014,7 +1009,7 @@ TX_INTERRUPT_SAVE_AREA UINT old_posture; - TX_EL_NO_INTERRUPT_EVENTS + TX_EL_NO_INTERRUPT_EVENTS TX_DISABLE TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_INTERRUPT_CONTROL, _tx_thread_current_ptr, new_posture) @@ -1027,38 +1022,38 @@ UINT old_posture; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_event_log_on PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_event_log_on PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function disables all event filters. */ -/* */ -/* INPUT */ -/* */ -/* None */ /* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* This function disables all event filters. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -1072,39 +1067,39 @@ VOID _tx_el_event_log_on(void) } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_event_log_off PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_event_log_off PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function sets all event filters, thereby turning event */ -/* logging off. */ -/* */ -/* INPUT */ -/* */ -/* None */ /* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* This function sets all event filters, thereby turning event */ +/* logging off. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -1118,38 +1113,38 @@ VOID _tx_el_event_log_off(void) } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_event_log_set PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_event_log_set PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function sets the events filters specified by the user. */ -/* */ -/* INPUT */ -/* */ -/* filter Events to filter */ /* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* This function sets the events filters specified by the user. */ +/* */ +/* INPUT */ +/* */ +/* filter Events to filter */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ diff --git a/ports/cortex_m4/ghs/src/tx_ghs.c b/ports/cortex_m4/ghs/src/tx_ghs.c index 0be9d715..30b8054e 100644 --- a/ports/cortex_m4/ghs/src/tx_ghs.c +++ b/ports/cortex_m4/ghs/src/tx_ghs.c @@ -55,7 +55,7 @@ extern TX_THREAD *_tx_thread_current_ptr; If you customize the System Library, you should remove ind_thrd.c from the libsys.gpj subproject. - + */ /* Provide global __eh_globals value to support C++ exception handling diff --git a/ports/cortex_m4/ghs/src/tx_thread_context_restore.arm b/ports/cortex_m4/ghs/src/tx_thread_context_restore.arm index 4a15e661..90064083 100644 --- a/ports/cortex_m4/ghs/src/tx_thread_context_restore.arm +++ b/ports/cortex_m4/ghs/src/tx_thread_context_restore.arm @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; diff --git a/ports/cortex_m4/ghs/src/tx_thread_context_save.arm b/ports/cortex_m4/ghs/src/tx_thread_context_save.arm index 4ee07714..284e9ac6 100644 --- a/ports/cortex_m4/ghs/src/tx_thread_context_save.arm +++ b/ports/cortex_m4/ghs/src/tx_thread_context_save.arm @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; diff --git a/ports/cortex_m4/ghs/src/tx_thread_interrupt_control.arm b/ports/cortex_m4/ghs/src/tx_thread_interrupt_control.arm index 62d2391f..b7cfe4fc 100644 --- a/ports/cortex_m4/ghs/src/tx_thread_interrupt_control.arm +++ b/ports/cortex_m4/ghs/src/tx_thread_interrupt_control.arm @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; diff --git a/ports/cortex_m4/ghs/src/tx_thread_interrupt_disable.arm b/ports/cortex_m4/ghs/src/tx_thread_interrupt_disable.arm index 57292d50..06a571d3 100644 --- a/ports/cortex_m4/ghs/src/tx_thread_interrupt_disable.arm +++ b/ports/cortex_m4/ghs/src/tx_thread_interrupt_disable.arm @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -81,4 +81,4 @@ _tx_thread_interrupt_disable: ; ;} .type _tx_thread_interrupt_disable,$function - .size _tx_thread_interrupt_disable,.-_tx_thread_interrupt_disable + .size _tx_thread_interrupt_disable,.-_tx_thread_interrupt_disable diff --git a/ports/cortex_m4/ghs/src/tx_thread_interrupt_restore.arm b/ports/cortex_m4/ghs/src/tx_thread_interrupt_restore.arm index 8b38ea80..12a1307a 100644 --- a/ports/cortex_m4/ghs/src/tx_thread_interrupt_restore.arm +++ b/ports/cortex_m4/ghs/src/tx_thread_interrupt_restore.arm @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -72,4 +72,4 @@ _tx_thread_interrupt_restore: ; ;} .type _tx_thread_interrupt_restore,$function - .size _tx_thread_interrupt_restore,.-_tx_thread_interrupt_restore + .size _tx_thread_interrupt_restore,.-_tx_thread_interrupt_restore diff --git a/ports/cortex_m4/ghs/src/tx_thread_schedule.arm b/ports/cortex_m4/ghs/src/tx_thread_schedule.arm index efc8f667..dc15054a 100644 --- a/ports/cortex_m4/ghs/src/tx_thread_schedule.arm +++ b/ports/cortex_m4/ghs/src/tx_thread_schedule.arm @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -85,7 +85,7 @@ _tx_thread_schedule: ; #ifdef __VFP__ MRS r0, CONTROL ; Pickup current CONTROL register - BIC r0, r0, #4 ; Clear the FPCA bit + BIC r0, r0, #4 ; Clear the FPCA bit MSR CONTROL, r0 ; Setup new CONTROL register #endif ; @@ -118,8 +118,8 @@ PendSV_Handler: __tx_PendSVHandler: ; ; /* Get current thread value and new thread pointer. */ -; -__tx_ts_handler: +; +__tx_ts_handler: #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; @@ -137,7 +137,7 @@ __tx_ts_handler: LDR r1, [r0] ; Pickup current thread pointer ; ; /* Determine if there is a current thread to finish preserving. */ -; +; CBZ r1, __tx_ts_new ; If NULL, skip preservation ; ; /* Recover PSP and preserve current thread context. */ @@ -212,7 +212,7 @@ __tx_ts_restore: LDR.W LR, [r12], #4 ; Pickup LR #ifdef __VFP__ TST LR, #0x10 ; Determine if the VFP extended frame is present - BNE _skip_vfp_restore ; If not, skip VFP restore + BNE _skip_vfp_restore ; If not, skip VFP restore VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers _skip_vfp_restore: #endif @@ -224,7 +224,7 @@ _skip_vfp_restore: BX lr ; Return to thread! ; ; /* The following is the idle wait processing... in this case, no threads are ready for execution and the -; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts ; are disabled to allow use of WFI for waiting for a thread to arrive. */ ; __tx_ts_wait: @@ -254,13 +254,13 @@ __tx_ts_wait: CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; -; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are ; already in the handler! */ ; __tx_ts_ready: MOV r7, #0x08000000 ; Build clear PendSV value MOV r8, #0xE000E000 ; Build base NVIC address - STR r7, [r8, #0xD04] ; Clear any PendSV + STR r7, [r8, #0xD04] ; Clear any PendSV ; ; /* Re-enable interrupts and restore new thread. */ ; @@ -269,14 +269,14 @@ __tx_ts_ready: ;} ; .type __tx_PendSVHandler,$function - .size __tx_PendSVHandler,.-__tx_PendSVHandler + .size __tx_PendSVHandler,.-__tx_PendSVHandler #ifdef __VFP__ .globl tx_thread_fpu_enable tx_thread_fpu_enable: ; -; /* Automatic VPF logic is supported, this function is present only for +; /* Automatic VPF logic is supported, this function is present only for ; backward compatibility purposes and therefore simply returns. */ ; BX LR ; Return to caller @@ -287,12 +287,12 @@ tx_thread_fpu_enable: .global tx_thread_fpu_disable tx_thread_fpu_disable: ; -; /* Automatic VPF logic is supported, this function is present only for +; /* Automatic VPF logic is supported, this function is present only for ; backward compatibility purposes and therefore simply returns. */ ; BX LR ; Return to caller .type tx_thread_fpu_disable,$function - .size tx_thread_fpu_disable,.-tx_thread_fpu_disable + .size tx_thread_fpu_disable,.-tx_thread_fpu_disable #endif diff --git a/ports/cortex_m4/ghs/src/tx_thread_stack_build.arm b/ports/cortex_m4/ghs/src/tx_thread_stack_build.arm index 39bdec1f..9b0646ea 100644 --- a/ports/cortex_m4/ghs/src/tx_thread_stack_build.arm +++ b/ports/cortex_m4/ghs/src/tx_thread_stack_build.arm @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; diff --git a/ports/cortex_m4/ghs/src/tx_thread_system_return.arm b/ports/cortex_m4/ghs/src/tx_thread_system_return.arm index e579fb4d..8971e409 100644 --- a/ports/cortex_m4/ghs/src/tx_thread_system_return.arm +++ b/ports/cortex_m4/ghs/src/tx_thread_system_return.arm @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -80,7 +80,7 @@ _tx_thread_system_return: CPSIE i ; Enable interrupts MSR PRIMASK, r1 ; Restore original interrupt posture _isr_context: - BX lr ; Return to caller + BX lr ; Return to caller ;} .type _tx_thread_system_return,$function .size _tx_thread_system_return,.-_tx_thread_system_return diff --git a/ports/cortex_m4/ghs/src/tx_timer_interrupt.arm b/ports/cortex_m4/ghs/src/tx_timer_interrupt.arm index 8b67b4d7..97613d88 100644 --- a/ports/cortex_m4/ghs/src/tx_timer_interrupt.arm +++ b/ports/cortex_m4/ghs/src/tx_timer_interrupt.arm @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -83,7 +83,7 @@ _tx_timer_interrupt: ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CBZ r2, __tx_timer_no_time_slice ; Is it non-active? ; Yes, skip time-slice processing @@ -200,13 +200,13 @@ __tx_timer_dont_activate: ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing LDR r0, =_tx_thread_preempt_disable ; Build address of preempt disable flag diff --git a/ports/cortex_m4/gnu/example_build/cortexm4_crt0.S b/ports/cortex_m4/gnu/example_build/cortexm4_crt0.S index bb530ac5..070871a3 100644 --- a/ports/cortex_m4/gnu/example_build/cortexm4_crt0.S +++ b/ports/cortex_m4/gnu/example_build/cortexm4_crt0.S @@ -63,7 +63,7 @@ crt0_ctor_loop: beq crt0_ctor_end ldr r2, [r0] add r0, #4 - push {r0-r1} + push {r0-r1} blx r2 pop {r0-r1} b crt0_ctor_loop @@ -83,7 +83,7 @@ start: /* when main returns, loop forever. */ crt0_exit_loop: b crt0_exit_loop - + /* Startup helper functions. */ @@ -116,4 +116,3 @@ memory_set_done: .section .stack, "wa", %nobits .section .stack_process, "wa", %nobits .section .heap, "wa", %nobits - \ No newline at end of file diff --git a/ports/cortex_m4/gnu/example_build/cortexm4_vectors.S b/ports/cortex_m4/gnu/example_build/cortexm4_vectors.S index 6ae558e4..dc8d0aad 100644 --- a/ports/cortex_m4/gnu/example_build/cortexm4_vectors.S +++ b/ports/cortex_m4/gnu/example_build/cortexm4_vectors.S @@ -4,8 +4,8 @@ .global __tx_BadHandler .global __tx_SVCallHandler .global __tx_DBGHandler - .global __tx_PendSVHandler - .global __tx_SysTickHandler + .global __tx_PendSVHandler + .global __tx_SysTickHandler .global __tx_BadHandler .syntax unified @@ -15,9 +15,9 @@ .global _vectors _vectors: - .word __stack_end__ - .word reset_handler - .word __tx_NMIHandler + .word __stack_end__ + .word reset_handler + .word __tx_NMIHandler .word __tx_HardfaultHandler .word __tx_BadHandler .word __tx_BadHandler @@ -29,7 +29,7 @@ _vectors: .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // .word __tx_DBGHandler .word 0 // Reserved - .word __tx_PendSVHandler + .word __tx_PendSVHandler .word __tx_SysTickHandler // Used by Threadx timer functionality .word __tx_BadHandler // Populate with user Interrupt handler .word __tx_BadHandler diff --git a/ports/cortex_m4/gnu/example_build/sample_threadx.c b/ports/cortex_m4/gnu/example_build/sample_threadx.c index 597f373c..13ffadba 100644 --- a/ports/cortex_m4/gnu/example_build/sample_threadx.c +++ b/ports/cortex_m4/gnu/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -81,42 +81,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -124,23 +124,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -243,11 +243,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -306,7 +306,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -359,7 +359,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_m4/gnu/example_build/sample_threadx.ld b/ports/cortex_m4/gnu/example_build/sample_threadx.ld index c65a1346..3f19c29e 100644 --- a/ports/cortex_m4/gnu/example_build/sample_threadx.ld +++ b/ports/cortex_m4/gnu/example_build/sample_threadx.ld @@ -10,7 +10,7 @@ __HEAPSIZE__ = 128; SECTIONS { - .vectors : + .vectors : { KEEP(*(.vectors .vectors.*)) } > FLASH @@ -45,7 +45,7 @@ SECTIONS KEEP(*(.eh_frame*)) } > FLASH - .ARM.extab : + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH @@ -59,7 +59,7 @@ SECTIONS __data_load_start__ = ALIGN (4); - .data : AT (__data_load_start__) + .data : AT (__data_load_start__) { __data_start__ = .; @@ -89,7 +89,7 @@ SECTIONS KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ - + __data_end__ = .; } > RAM @@ -104,7 +104,7 @@ SECTIONS __bss_end__ = .; } > RAM - + .heap (COPY): { __heap_start__ = ALIGN(4); diff --git a/ports/cortex_m4/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_m4/gnu/example_build/tx_initialize_low_level.S index d7e11c06..4c7a6223 100644 --- a/ports/cortex_m4/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m4/gnu/example_build/tx_initialize_low_level.S @@ -1,10 +1,10 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @@ -77,16 +77,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* */ @/* _tx_initialize_kernel_enter ThreadX entry function */ @/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 09-30-2020 William E. Lamie Modified Comment(s), fixed */ -@/* GNU assembly comment, */ -@/* cleaned up whitespace, */ -@/* resulting in version 6.1 */ -@/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) @{ diff --git a/ports/cortex_m4/gnu/inc/tx_port.h b/ports/cortex_m4/gnu/inc/tx_port.h index 3eb8dbff..7c2b04c5 100644 --- a/ports/cortex_m4/gnu/inc/tx_port.h +++ b/ports/cortex_m4/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,23 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comments, updated */ -/* typedef to fix misra */ -/* violation, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -371,7 +355,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -530,7 +514,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #endif @@ -715,7 +699,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M4/GNU Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4/GNU Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m4/gnu/readme_threadx.txt b/ports/cortex_m4/gnu/readme_threadx.txt index d9063d65..58181f85 100644 --- a/ports/cortex_m4/gnu/readme_threadx.txt +++ b/ports/cortex_m4/gnu/readme_threadx.txt @@ -5,15 +5,15 @@ 1. Building the ThreadX run-time Library -Navigate to the "example_build" directory. Ensure that -you have setup your path and other environment variables necessary for the ARM -GNU compiler. At this point you may run the build_threadx.bat batch file. -This will build the ThreadX run-time environment in the "example_build" -directory. +Navigate to the "example_build" directory. Ensure that +you have setup your path and other environment variables necessary for the ARM +GNU compiler. At this point you may run the build_threadx.bat batch file. +This will build the ThreadX run-time environment in the "example_build" +directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. @@ -22,25 +22,25 @@ application in order to use ThreadX. The ThreadX demonstration is designed to execute on Cortex-M evaluation boards or on a dedicated simulator. -Building the demonstration is easy, simply execute the build_threadx_sample.bat +Building the demonstration is easy, simply execute the build_threadx_sample.bat batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with tx.a. The resulting file sample_threadx.out is a binary +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.out is a binary file that can be downloaded and executed on the a simulator, or downloaded to a board. 3. System Initialization -The entry point in ThreadX for the Cortex-M using gnu tools uses the standard GNU +The entry point in ThreadX for the Cortex-M using gnu tools uses the standard GNU Cortex-M reset sequence. From the reset vector the C runtime will be initialized. -The ThreadX tx_initialize_low_level.S file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. +The ThreadX tx_initialize_low_level.S file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. @@ -49,7 +49,7 @@ parameter to your application definition function, tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -132,34 +132,34 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 5. Improving Performance -The distribution version of ThreadX is built without any compiler optimizations. -This makes it easy to debug because you can trace or set breakpoints inside of -ThreadX itself. Of course, this costs some performance. To make it run faster, -you can change the build_threadx.bat file to remove the -g option and enable -all compiler optimizations. +The distribution version of ThreadX is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX itself. Of course, this costs some performance. To make it run faster, +you can change the build_threadx.bat file to remove the -g option and enable +all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 6.1 Vector Area The Cortex-M vectors start at the label __tx_vectors or similar. The application may modify -the vector area according to its needs. There is code in tx_initialize_low_level() that will -configure the vector base register. +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. 6.2 Managed Interrupts -A ThreadX managed interrupt is defined below. By following these conventions, the +A ThreadX managed interrupt is defined below. By following these conventions, the application ISR is then allowed access to various ThreadX services from the ISR. Here is the standard template for managed ISRs in ThreadX: @@ -181,15 +181,15 @@ __tx_IntHandler: Note: the Cortex-M requires exception handlers to be thumb labels, this implies bit 0 set. To accomplish this, the declaration of the label has to be preceded by the assembler directive -.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to -be inserted in the correct location in the interrupt vector table. This table is typically +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically located in either your runtime startup file or in the tx_initialize_low_level.S file. 7. FPU Support -ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context - no additional setup by the application. diff --git a/ports/cortex_m4/gnu/src/tx_misra.S b/ports/cortex_m4/gnu/src/tx_misra.S index 8ac0c629..10548671 100644 --- a/ports/cortex_m4/gnu/src/tx_misra.S +++ b/ports/cortex_m4/gnu/src/tx_misra.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -667,7 +668,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -682,7 +683,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARM_FP /***********************************************************************************************/ @@ -699,8 +700,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -714,9 +715,9 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - + .data .word 0 diff --git a/ports/cortex_m4/gnu/src/tx_thread_context_restore.S b/ports/cortex_m4/gnu/src/tx_thread_context_restore.S index af374956..85b1ee2a 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m4/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_m4/gnu/src/tx_thread_context_save.S b/ports/cortex_m4/gnu/src/tx_thread_context_save.S index 0728d86e..9c0f547a 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m4/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_m4/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m4/gnu/src/tx_thread_interrupt_control.S index 38790a85..55791677 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m4/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_m4/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_m4/gnu/src/tx_thread_interrupt_disable.S index e0ae359a..56c4c4bc 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m4/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports/cortex_m4/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_m4/gnu/src/tx_thread_interrupt_restore.S index 32839c40..9d2ba7b0 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m4/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports/cortex_m4/gnu/src/tx_thread_schedule.S b/ports/cortex_m4/gnu/src/tx_thread_schedule.S index 8b283009..5b6fb534 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m4/gnu/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,18 +69,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Fixed predefined macro name, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_m4/gnu/src/tx_thread_stack_build.S b/ports/cortex_m4/gnu/src/tx_thread_stack_build.S index c62ccf30..0b26d993 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m4/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_m4/gnu/src/tx_thread_system_return.S b/ports/cortex_m4/gnu/src/tx_thread_system_return.S index 234a2121..8c4a09fd 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m4/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_m4/gnu/src/tx_timer_interrupt.S b/ports/cortex_m4/gnu/src/tx_timer_interrupt.S index 4d0c8003..6a14a673 100644 --- a/ports/cortex_m4/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_m4/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,17 +71,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_m4/iar/CMakeLists.txt b/ports/cortex_m4/iar/CMakeLists.txt index a524d79f..57be3aeb 100644 --- a/ports/cortex_m4/iar/CMakeLists.txt +++ b/ports/cortex_m4/iar/CMakeLists.txt @@ -7,7 +7,7 @@ target_sources(${PROJECT_NAME} ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_disable.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_restore.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_restore.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S diff --git a/ports/cortex_m4/iar/example_build/cstartup_M.s b/ports/cortex_m4/iar/example_build/cstartup_M.s index 75d9369b..d1c5aa3e 100644 --- a/ports/cortex_m4/iar/example_build/cstartup_M.s +++ b/ports/cortex_m4/iar/example_build/cstartup_M.s @@ -2,16 +2,16 @@ PUBLIC __vector_table SECTION .text:CODE:REORDER(1) - + ;; Keep vector table even if it's not referenced REQUIRE __vector_table - + THUMB - + ;; Forward declaration of sections. SECTION CSTACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) - + DATA __vector_table diff --git a/ports/cortex_m4/iar/example_build/sample_threadx.c b/ports/cortex_m4/iar/example_build/sample_threadx.c index 60f5a3d3..55b63731 100644 --- a/ports/cortex_m4/iar/example_build/sample_threadx.c +++ b/ports/cortex_m4/iar/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete description of this demonstration. */ @@ -69,7 +69,7 @@ void thread_6_and_7_entry(ULONG thread_input); int main() { - + /* Please refer to Chapter 6 of the ThreadX User Guide for a complete description of this demonstration. */ @@ -101,41 +101,41 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -143,23 +143,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -262,11 +262,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -325,7 +325,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -378,7 +378,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_m4/iar/example_build/tx_initialize_low_level.s b/ports/cortex_m4/iar/example_build/tx_initialize_low_level.s index d3e6d9af..a84667c3 100644 --- a/ports/cortex_m4/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m4/iar/example_build/tx_initialize_low_level.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -73,12 +73,6 @@ __tx_free_memory_start ;/* */ ;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) ;{ diff --git a/ports/cortex_m4/iar/inc/tx_port.h b/ports/cortex_m4/iar/inc/tx_port.h index d6ac2000..1253befa 100644 --- a/ports/cortex_m4/iar/inc/tx_port.h +++ b/ports/cortex_m4/iar/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,23 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comments, updated */ -/* typedef to fix misra */ -/* violation, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -371,7 +355,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -530,7 +514,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #endif @@ -715,7 +699,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M4/IAR Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4/IAR Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m4/iar/readme_threadx.txt b/ports/cortex_m4/iar/readme_threadx.txt index 28b54e03..388c40e6 100644 --- a/ports/cortex_m4/iar/readme_threadx.txt +++ b/ports/cortex_m4/iar/readme_threadx.txt @@ -6,45 +6,45 @@ 1. Building the ThreadX run-time Library Building the ThreadX library is easy. First, open the Azure RTOS workspace -azure_rtos.eww. Next, make the TX project the "active project" in the -IAR Embedded Workbench and select the "Make" button. You should observe -assembly and compilation of a series of ThreadX source files. This -results in the ThreadX run-time library file tx.a, which is needed by +azure_rtos.eww. Next, make the TX project the "active project" in the +IAR Embedded Workbench and select the "Make" button. You should observe +assembly and compilation of a series of ThreadX source files. This +results in the ThreadX run-time library file tx.a, which is needed by the application. 2. Demonstration System -The ThreadX demonstration is designed to execute under the IAR debugger under +The ThreadX demonstration is designed to execute under the IAR debugger under simulation. Building the demonstration is easy; simply open the threadx.www workspace file, -make the sample_threadx.ewp project the "active project" in the IAR Embedded +make the sample_threadx.ewp project the "active project" in the IAR Embedded Workbench, and select the "Make" button. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with tx.a. The resulting file sample_threadx.out is a -binary ELF file that can be downloaded and executed on the IAR Windows-based +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.out is a +binary ELF file that can be downloaded and executed on the IAR Windows-based Cortex-M simulator. 3. System Initialization -The entry point in ThreadX for the Cortex-M using IAR tools is at label -__iar_program_start. This is defined within the IAR compiler's startup code. -In addition, this is where all static and global preset C variable +The entry point in ThreadX for the Cortex-M using IAR tools is at label +__iar_program_start. This is defined within the IAR compiler's startup code. +In addition, this is where all static and global preset C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, and a periodic timer interrupt source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. By default, the vector area is defined at the top of cstartup_M.s, which is -a slightly modified from the base IAR file. +a slightly modified from the base IAR file. The _tx_initialize_low_level function inside of tx_initialize_low_level.s -also determines the first available address for use by the application, which -is supplied as the sole input parameter to your application definition function, -tx_application_define. To accomplish this, a section is created in -tx_initialize_low_level.s called FREE_MEM, which must be located after all +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all other RAM sections in memory. @@ -53,7 +53,7 @@ other RAM sections in memory. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -136,20 +136,20 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 5. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the ThreadX library project to enable various compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling -The Cortex-M vectors start at the label __vector_table and is defined in cstartup_M.s. +The Cortex-M vectors start at the label __vector_table and is defined in cstartup_M.s. The application may modify the vector area according to its needs. @@ -188,14 +188,14 @@ should have the following line added (if not already in place): initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application -The project options "General Options -> Library Configuration" should also have the +The project options "General Options -> Library Configuration" should also have the "Enable thread support in library" box selected. 8. VFP Support -ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context - no additional setup by the application. diff --git a/ports/cortex_m4/iar/src/tx_iar.c b/ports/cortex_m4/iar/src/tx_iar.c index ee47f10f..238b485e 100644 --- a/ports/cortex_m4/iar/src/tx_iar.c +++ b/ports/cortex_m4/iar/src/tx_iar.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports/cortex_m4/iar/src/tx_misra.s b/ports/cortex_m4/iar/src/tx_misra.s index f86d9a65..642bb89e 100644 --- a/ports/cortex_m4/iar/src/tx_misra.s +++ b/ports/cortex_m4/iar/src/tx_misra.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -120,7 +121,7 @@ SECTION `.data`:DATA:REORDER:NOROOT(2) DATA -// 51 CHAR _tx_version_id[100] = "Copyright (c) 2024 Microsoft Corporation. * ThreadX 6.1 MISRA C Compliant *"; +// 51 CHAR _tx_version_id[100] = "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX 6.1 MISRA C Compliant *"; _tx_version_id: DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H @@ -707,7 +708,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -722,7 +723,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARMVFP__ /***********************************************************************************************/ @@ -739,8 +740,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -754,10 +755,10 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - - + + SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2) SECTION_TYPE SHT_PROGBITS, 0 DATA diff --git a/ports/cortex_m4/iar/src/tx_thread_context_restore.s b/ports/cortex_m4/iar/src/tx_thread_context_restore.s index ff4f11e0..d0033b5b 100644 --- a/ports/cortex_m4/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_m4/iar/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_m4/iar/src/tx_thread_context_save.s b/ports/cortex_m4/iar/src/tx_thread_context_save.s index c26d32c5..f1291fec 100644 --- a/ports/cortex_m4/iar/src/tx_thread_context_save.s +++ b/ports/cortex_m4/iar/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_m4/iar/src/tx_thread_interrupt_control.s b/ports/cortex_m4/iar/src/tx_thread_interrupt_control.s index b72bbad3..e0e028c8 100644 --- a/ports/cortex_m4/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m4/iar/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_m4/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m4/iar/src/tx_thread_interrupt_disable.s index 4002679f..00dab2e2 100644 --- a/ports/cortex_m4/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m4/iar/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports/cortex_m4/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_m4/iar/src/tx_thread_interrupt_restore.s index b9093f8a..cf834228 100644 --- a/ports/cortex_m4/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m4/iar/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports/cortex_m4/iar/src/tx_thread_schedule.s b/ports/cortex_m4/iar/src/tx_thread_schedule.s index 8feaf239..229fd5df 100644 --- a/ports/cortex_m4/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m4/iar/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,17 +68,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 04-25-2022 Scott Larson Added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_m4/iar/src/tx_thread_stack_build.s b/ports/cortex_m4/iar/src/tx_thread_stack_build.s index 01213848..a80261c2 100644 --- a/ports/cortex_m4/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_m4/iar/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_m4/iar/src/tx_thread_system_return.s b/ports/cortex_m4/iar/src/tx_thread_system_return.s index 3260e917..4f8b9870 100644 --- a/ports/cortex_m4/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m4/iar/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_m4/iar/src/tx_timer_interrupt.s b/ports/cortex_m4/iar/src/tx_timer_interrupt.s index 72cc4f61..fbf9c2ab 100644 --- a/ports/cortex_m4/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_m4/iar/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,18 +72,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_m4/keil/example_build/demo_threadx.c b/ports/cortex_m4/keil/example_build/demo_threadx.c index 96c4eb5a..34453f42 100644 --- a/ports/cortex_m4/keil/example_build/demo_threadx.c +++ b/ports/cortex_m4/keil/example_build/demo_threadx.c @@ -77,35 +77,35 @@ void tx_application_define(void *first_unused_memory) /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - thread_0_stack, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + thread_0_stack, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - thread_1_stack, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + thread_1_stack, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - thread_2_stack, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + thread_2_stack, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - thread_3_stack, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + thread_3_stack, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - thread_4_stack, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + thread_4_stack, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - thread_5_stack, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + thread_5_stack, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Create the message queue shared by threads 1 and 2. */ @@ -189,11 +189,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -252,7 +252,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ diff --git a/ports/cortex_m4/keil/example_build/tx_initialize_low_level.s b/ports/cortex_m4/keil/example_build/tx_initialize_low_level.s index e2aec801..58aee89c 100644 --- a/ports/cortex_m4/keil/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m4/keil/example_build/tx_initialize_low_level.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -141,12 +141,6 @@ Reset_Handler ;/* */ ;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) ;{ diff --git a/ports/cortex_m4/keil/inc/tx_port.h b/ports/cortex_m4/keil/inc/tx_port.h index 331a75a8..f96d819e 100644 --- a/ports/cortex_m4/keil/inc/tx_port.h +++ b/ports/cortex_m4/keil/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,23 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comments, updated */ -/* typedef to fix misra */ -/* violation, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -371,7 +355,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -530,7 +514,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #endif @@ -715,7 +699,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M4/Keil Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4/Keil Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m4/keil/readme_threadx.txt b/ports/cortex_m4/keil/readme_threadx.txt index 12848341..e84f29c9 100644 --- a/ports/cortex_m4/keil/readme_threadx.txt +++ b/ports/cortex_m4/keil/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for Cortex-M4 + Microsoft's Azure RTOS ThreadX for Cortex-M4 Thumb & 32-bit Mode @@ -6,44 +6,44 @@ 1. Building the ThreadX run-time Library -Building the ThreadX library is easy, simply load the project file -ThreadX_Library.Uv2, which is located inside the "example_build" directory. +Building the ThreadX library is easy, simply load the project file +ThreadX_Library.Uv2, which is located inside the "example_build" directory. Once the ThreadX library files are displayed in the project window, select the "Build Target" operation and observe the compilation and assembly -of the ThreadX library. This project build produces the ThreadX library +of the ThreadX library. This project build produces the ThreadX library file ThreadX_Library.lib. 2. Demonstration System The ThreadX demonstration is designed to execute under the Keil debugger or -Cortex-M4 hardware. This demonstration is slightly smaller than typical ThreadX +Cortex-M4 hardware. This demonstration is slightly smaller than typical ThreadX demonstrations, and thus requires less than 7KB of Flash and less than 4KB of RAM. -Building the demonstration is easy; simply open the ThreadX demonstration -project file ThreadX_Demo.Uv2, which is located inside the "example_build" -directory. +Building the demonstration is easy; simply open the ThreadX demonstration +project file ThreadX_Demo.Uv2, which is located inside the "example_build" +directory. -Once open, select the "Build Target" operation and observe the compilation of -sample_threadx.c (which is the demonstration application) and linking with -ThreadX_Library.lib. The resulting file sample_threadx.axf is a binary file that -can be downloaded and executed on Cortex-M4 hardware. +Once open, select the "Build Target" operation and observe the compilation of +sample_threadx.c (which is the demonstration application) and linking with +ThreadX_Library.lib. The resulting file sample_threadx.axf is a binary file that +can be downloaded and executed on Cortex-M4 hardware. 3. System Initialization -The entry point in ThreadX for the Cortex-M4 using Keil tools is at label -__main. This is defined within the Keil compiler's startup code. In -addition, this is where all static and global pre-set C variable +The entry point in ThreadX for the Cortex-M4 using Keil tools is at label +__main. This is defined within the Keil compiler's startup code. In +addition, this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. @@ -52,7 +52,7 @@ parameter to your application definition function, tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M4 version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -135,21 +135,21 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 5. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make it run faster, you can change the ThreadX_Library.Uv2 -project to debugging and enable all compiler optimizations. +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the ThreadX_Library.Uv2 +project to debugging and enable all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M4 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: @@ -188,8 +188,8 @@ your_assembly_isr 7. FPU Support -ThreadX for Cortex-M4 supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-M4 supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context - no additional setup by the application. diff --git a/ports/cortex_m4/keil/src/tx_thread_context_restore.s b/ports/cortex_m4/keil/src/tx_thread_context_restore.s index dddaca7b..32a10e61 100644 --- a/ports/cortex_m4/keil/src/tx_thread_context_restore.s +++ b/ports/cortex_m4/keil/src/tx_thread_context_restore.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -62,12 +62,6 @@ ;/* */ ;/* ISRs Interrupt Service Routines */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) ;{ diff --git a/ports/cortex_m4/keil/src/tx_thread_context_save.s b/ports/cortex_m4/keil/src/tx_thread_context_save.s index 207ab4b1..fd6dfcf6 100644 --- a/ports/cortex_m4/keil/src/tx_thread_context_save.s +++ b/ports/cortex_m4/keil/src/tx_thread_context_save.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -61,12 +61,6 @@ ;/* */ ;/* ISRs */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) ;{ diff --git a/ports/cortex_m4/keil/src/tx_thread_interrupt_control.s b/ports/cortex_m4/keil/src/tx_thread_interrupt_control.s index 35367af7..e83f9abb 100644 --- a/ports/cortex_m4/keil/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m4/keil/src/tx_thread_interrupt_control.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -52,12 +52,6 @@ ;/* */ ;/* Application Code */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) ;{ diff --git a/ports/cortex_m4/keil/src/tx_thread_interrupt_disable.s b/ports/cortex_m4/keil/src/tx_thread_interrupt_disable.s index 825eaf12..c64ce546 100644 --- a/ports/cortex_m4/keil/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m4/keil/src/tx_thread_interrupt_disable.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -52,12 +52,6 @@ ;/* */ ;/* Application Code */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) ;{ diff --git a/ports/cortex_m4/keil/src/tx_thread_interrupt_restore.s b/ports/cortex_m4/keil/src/tx_thread_interrupt_restore.s index 4cc24369..53d7ecb7 100644 --- a/ports/cortex_m4/keil/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m4/keil/src/tx_thread_interrupt_restore.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -52,12 +52,6 @@ ;/* */ ;/* Application Code */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) ;{ diff --git a/ports/cortex_m4/keil/src/tx_thread_schedule.s b/ports/cortex_m4/keil/src/tx_thread_schedule.s index d97cf136..eba721e7 100644 --- a/ports/cortex_m4/keil/src/tx_thread_schedule.s +++ b/ports/cortex_m4/keil/src/tx_thread_schedule.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -71,15 +71,6 @@ ;/* _tx_thread_system_return Return to system from thread */ ;/* _tx_thread_context_restore Restore thread's context */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 03-02-2021 Scott Larson Modified comment(s), add */ -;/* low power code, */ -;/* resulting in version 6.1.5 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) ;{ diff --git a/ports/cortex_m4/keil/src/tx_thread_stack_build.s b/ports/cortex_m4/keil/src/tx_thread_stack_build.s index f73651ce..1f72e52a 100644 --- a/ports/cortex_m4/keil/src/tx_thread_stack_build.s +++ b/ports/cortex_m4/keil/src/tx_thread_stack_build.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -54,12 +54,6 @@ ;/* */ ;/* _tx_thread_create Create thread service */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) ;{ diff --git a/ports/cortex_m4/keil/src/tx_thread_system_return.s b/ports/cortex_m4/keil/src/tx_thread_system_return.s index 5ee774d9..dd666162 100644 --- a/ports/cortex_m4/keil/src/tx_thread_system_return.s +++ b/ports/cortex_m4/keil/src/tx_thread_system_return.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -54,12 +54,6 @@ ;/* */ ;/* ThreadX components */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) ;{ diff --git a/ports/cortex_m4/keil/src/tx_timer_interrupt.s b/ports/cortex_m4/keil/src/tx_timer_interrupt.s index 240db972..7a7b0041 100644 --- a/ports/cortex_m4/keil/src/tx_timer_interrupt.s +++ b/ports/cortex_m4/keil/src/tx_timer_interrupt.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -71,12 +71,6 @@ ;/* */ ;/* interrupt vector */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) ;{ diff --git a/ports/cortex_m55/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h b/ports/cortex_m55/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h index 2ec1c863..a5cd11d9 100644 --- a/ports/cortex_m55/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h +++ b/ports/cortex_m55/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'ThreadX_Library' - * Target: 'ThreadX_Library_Project' + * Project: 'ThreadX_Library' + * Target: 'ThreadX_Library_Project' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM55.h" diff --git a/ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c b/ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c index ce3ad161..e54aa490 100644 --- a/ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c +++ b/ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c @@ -88,8 +88,8 @@ typedef struct /* see "Arm Cortex-Mxx Technical Reference Manual r0p1" #define ITGU_BASE (0xE001E500UL) /* ITCM Gating Unit */ #define DTGU_BASE (0xE001E600UL) /* DTCM Gating Unit */ -#define ITGU ((TGU_TypeDef *) ITGU_BASE) -#define DTGU ((TGU_TypeDef *) DTGU_BASE) +#define ITGU ((TGU_TypeDef *) ITGU_BASE) +#define DTGU ((TGU_TypeDef *) DTGU_BASE) /*****************************************************************/ @@ -160,7 +160,7 @@ void SystemInit (void) /* configure unsecure code area: ITCM 512K 0x00080000 - 0x00100000 */ // blk_cfg = ITGU->CFG & 0xF; /* = 0x7 */ - // blk_size = 1UL << (blk_cfg + 5U); /* = 0x1000 (4K) */ + // blk_size = 1UL << (blk_cfg + 5U); /* = 0x1000 (4K) */ ITGU->LUT[4] = 0xFFFFFFFF; ITGU->LUT[5] = 0xFFFFFFFF; ITGU->LUT[6] = 0xFFFFFFFF; @@ -168,7 +168,7 @@ void SystemInit (void) /* configure unsecure data area: DTCM 512K 0x20080000 - 0x20100000 */ // blk_cfg = DTGU->CFG & 0xF; /* = 0x7 */ - // blk_size = 1UL << (blk_cfg + 5U); /* = 0x1000 (4K) */ + // blk_size = 1UL << (blk_cfg + 5U); /* = 0x1000 (4K) */ DTGU->LUT[4] = 0xFFFFFFFF; DTGU->LUT[5] = 0xFFFFFFFF; DTGU->LUT[6] = 0xFFFFFFFF; diff --git a/ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h index c7f94da9..e2a867f3 100644 --- a/ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h +++ b/ports/cortex_m55/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'demo_secure_zone' - * Target: 'FVP Simulation Model' + * Project: 'demo_secure_zone' + * Target: 'FVP Simulation Model' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "SSE300MPS3.h" diff --git a/ports/cortex_m55/ac6/example_build/demo_secure_zone/interface.c b/ports/cortex_m55/ac6/example_build/demo_secure_zone/interface.c index 4e6e8eee..af6533c3 100644 --- a/ports/cortex_m55/ac6/example_build/demo_secure_zone/interface.c +++ b/ports/cortex_m55/ac6/example_build/demo_secure_zone/interface.c @@ -31,19 +31,19 @@ typedef funcptr funcptr_NS __attribute__((cmse_nonsecure_call)); /* Non-secure callable (entry) function */ -int func1(int x) __attribute__((cmse_nonsecure_entry)) { - return x+3; +int func1(int x) __attribute__((cmse_nonsecure_entry)) { + return x+3; } /* Non-secure callable (entry) function, calling a non-secure callback function */ int func2(funcptr callback, int x) __attribute__((cmse_nonsecure_entry)) { funcptr_NS callback_NS; // non-secure callback function pointer int y; - + /* return function pointer with cleared LSB */ callback_NS = (funcptr_NS)cmse_nsfptr_create(callback); - + y = callback_NS (x+1); - + return (y+2); } diff --git a/ports/cortex_m55/ac6/example_build/demo_secure_zone/main_s.c b/ports/cortex_m55/ac6/example_build/demo_secure_zone/main_s.c index 422969de..92730392 100644 --- a/ports/cortex_m55/ac6/example_build/demo_secure_zone/main_s.c +++ b/ports/cortex_m55/ac6/example_build/demo_secure_zone/main_s.c @@ -24,35 +24,35 @@ * Title: Code template for secure main function * *---------------------------------------------------------------------------*/ - + #include "region_limits.h" #include "RTE_Components.h" #include CMSIS_device_header - + /* TZ_START_NS: Start address of non-secure application */ #ifndef TZ_START_NS #define TZ_START_NS 0x00080000U #endif - + /* typedef for non-secure callback functions */ typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call)); - + /* Secure main() */ int main(void) { funcptr_void NonSecure_ResetHandler; - + /* Add user setup code for secure part here*/ - + /* Set non-secure main stack (MSP_NS) */ __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS))); - + /* Get non-secure reset handler */ NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U))); - + /* Start non-secure state software application */ NonSecure_ResetHandler(); - + /* Non-secure software does not return, this code is not executed */ while (1) { __NOP(); diff --git a/ports/cortex_m55/ac6/example_build/demo_secure_zone/tz_context.c b/ports/cortex_m55/ac6/example_build/demo_secure_zone/tz_context.c index f3152890..ca7f0c56 100644 --- a/ports/cortex_m55/ac6/example_build/demo_secure_zone/tz_context.c +++ b/ports/cortex_m55/ac6/example_build/demo_secure_zone/tz_context.c @@ -24,7 +24,7 @@ * Title: Context Management for ARMv8-M TrustZone - Sample implementation * *---------------------------------------------------------------------------*/ - + #include "RTE_Components.h" #include CMSIS_device_header #include "tz_context.h" diff --git a/ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h index 3b0b521d..f6dfdef3 100644 --- a/ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h +++ b/ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'demo_threadx_non-secure_zone' - * Target: 'FVP Simulation Model' + * Project: 'demo_threadx_non-secure_zone' + * Target: 'FVP Simulation Model' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "SSE300MPS3.h" diff --git a/ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c b/ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c index 7257ac6d..cea22889 100644 --- a/ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c +++ b/ports/cortex_m55/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete description of this demonstration. */ @@ -68,7 +68,7 @@ void thread_6_and_7_entry(ULONG thread_input); int main() { - + /* Please refer to Chapter 6 of the ThreadX User Guide for a complete description of this demonstration. */ @@ -86,7 +86,7 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer; (VOID)first_unused_memory; /* unused parameter. */ - + #ifdef TX_ENABLE_EVENT_TRACE tx_trace_enable(trace_buffer, sizeof(trace_buffer), 32); #endif @@ -101,41 +101,41 @@ CHAR *pointer; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -143,23 +143,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -188,7 +188,7 @@ CHAR *pointer; /* Release the block back to the pool. */ tx_block_release(pointer); - + tx_thread_secure_stack_allocate(&thread_0,256); tx_thread_secure_stack_allocate(&thread_1,256); tx_thread_secure_stack_allocate(&thread_2,256); @@ -206,13 +206,13 @@ CHAR *pointer; void thread_0_entry(ULONG thread_input) { UINT status; - + (VOID)thread_input; /* unused parameter. */ - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { - + /* Increment the thread counter. */ thread_0_counter++; @@ -235,11 +235,11 @@ void thread_1_entry(ULONG thread_input) UINT status; (VOID)thread_input; /* unused parameter. */ - + /* This thread simply sends messages to a queue shared by thread 2. */ while(1) { - + /* Increment the thread counter. */ thread_1_counter++; @@ -263,7 +263,7 @@ ULONG received_message; UINT status; (VOID)thread_input; /* unused parameter. */ - + /* This thread retrieves messages placed on the queue by thread 1. */ while(1) { @@ -274,11 +274,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -289,7 +289,7 @@ void thread_3_and_4_entry(ULONG thread_input) { UINT status; - + /* This function is executed from thread 3 and thread 4. As the loop below shows, these function compete for ownership of semaphore_0. */ while(1) @@ -328,7 +328,7 @@ UINT status; ULONG actual_flags; (VOID)thread_input; /* unused parameter. */ - + /* This thread simply waits for an event in a forever loop. */ while(1) { @@ -337,7 +337,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -390,7 +390,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_m55/ac6/example_build/tx_initialize_low_level.S b/ports/cortex_m55/ac6/example_build/tx_initialize_low_level.S index 60c5d476..fdd8aaed 100644 --- a/ports/cortex_m55/ac6/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m55/ac6/example_build/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,12 +63,6 @@ HEAP_SIZE = 0x00000000 /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports/cortex_m55/ac6/inc/tx_port.h b/ports/cortex_m55/ac6/inc/tx_port.h index b5fe5f59..9d11a04b 100644 --- a/ports/cortex_m55/ac6/inc/tx_port.h +++ b/ports/cortex_m55/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,39 +46,6 @@ /* This file replaces the previous Cortex-M55 files. It unifies */ /* the Cortex-M55 compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-02-2021 Scott Larson Modified comment(s), added */ -/* ULONG64_DEFINED, */ -/* resulting in version 6.1.5 */ -/* 06-02-2021 Scott Larson Modified comment(s), removed */ -/* unneeded header file, funcs */ -/* set_control and get_control */ -/* changed to inline, */ -/* added symbol to enable */ -/* stack error handler, */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ -/* stack check error handling, */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), unified */ -/* this file across compilers, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* 03-08-2023 Scott Larson Removed unneeded #include, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -645,7 +613,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M55/AC6 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M55/AC6 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m55/ac6/inc/tx_secure_interface.h b/ports/cortex_m55/ac6/inc/tx_secure_interface.h index 39b5d5fd..5ac37fbf 100644 --- a/ports/cortex_m55/ac6/inc/tx_secure_interface.h +++ b/ports/cortex_m55/ac6/inc/tx_secure_interface.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,12 +38,6 @@ /* It is assumed that tx_api.h and tx_port.h have already been */ /* included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_SECURE_INTERFACE_H diff --git a/ports/cortex_m55/ac6/readme_threadx.txt b/ports/cortex_m55/ac6/readme_threadx.txt index fc0aa404..63e8196e 100644 --- a/ports/cortex_m55/ac6/readme_threadx.txt +++ b/ports/cortex_m55/ac6/readme_threadx.txt @@ -1,46 +1,46 @@ - Microsoft's Azure RTOS ThreadX for Cortex-M55 + Microsoft's Azure RTOS ThreadX for Cortex-M55 Using the AC6 Tools in Keil uVision 1. Import the ThreadX Projects -In order to build the ThreadX library and the ThreadX demonstration, first open -the AzureRTOS.uvmpw workspace (located in the "example_build" directory) +In order to build the ThreadX library and the ThreadX demonstration, first open +the AzureRTOS.uvmpw workspace (located in the "example_build" directory) into Keil. 2. Building the ThreadX run-time Library Building the ThreadX library is easy; simply set the ThreadX_Library project -as active, then then build the library. You should now observe the compilation +as active, then then build the library. You should now observe the compilation and assembly of the ThreadX library. This project build produces the ThreadX library file ThreadX_Library.lib. -Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c -replace the common files of the same name. +Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c +replace the common files of the same name. 3. Demonstration System The ThreadX demonstration is designed to execute under the Keil debugger on the FVP_MPS2_Cortex-M55_MDK simulator. -Building the demonstration is easy; simply select the "Batch Build" button. -You should now observe the compilation and assembly of the ThreadX demonstration of -both the demo_secure_zone and demo_threadx_non-secure_zone projects. +Building the demonstration is easy; simply select the "Batch Build" button. +You should now observe the compilation and assembly of the ThreadX demonstration of +both the demo_secure_zone and demo_threadx_non-secure_zone projects. Then click the Start/Stop Debug Session button to start the simulator and begin debugging. You are now ready to execute the ThreadX demonstration. 4. System Initialization -The entry point in ThreadX for the Cortex-M55 using AC6 tools uses the standard AC6 +The entry point in ThreadX for the Cortex-M55 using AC6 tools uses the standard AC6 Cortex-M55 reset sequence. From the reset vector the C runtime will be initialized. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. @@ -49,7 +49,7 @@ parameter to your application definition function, tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M55 version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -132,26 +132,26 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 6. Improving Performance -To make ThreadX and the application(s) run faster, you can enable -all compiler optimizations. +To make ThreadX and the application(s) run faster, you can enable +all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M55 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-M55 vectors start at the label __Vectors or similar. The application may modify -the vector area according to its needs. There is code in tx_initialize_low_level() that will -configure the vector base register. +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. 7.2 Managed Interrupts @@ -177,7 +177,7 @@ your_assembly_isr: ; VOID your_assembly_isr(VOID) ; { PUSH {r0, lr} -; +; ; /* Do interrupt handler work here */ ; /* BL */ @@ -187,15 +187,15 @@ your_assembly_isr: Note: the Cortex-M55 requires exception handlers to be thumb labels, this implies bit 0 set. To accomplish this, the declaration of the label has to be preceded by the assembler directive -.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to -be inserted in the correct location in the interrupt vector table. This table is typically +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically located in either your runtime startup file or in the tx_initialize_low_level.s file. 8. FPU Support -ThreadX for Cortex-M55 supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-M55 supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context. diff --git a/ports/cortex_m55/ac6/src/tx_initialize_low_level.S b/ports/cortex_m55/ac6/src/tx_initialize_low_level.S index 55e56af0..d6e39792 100644 --- a/ports/cortex_m55/ac6/src/tx_initialize_low_level.S +++ b/ports/cortex_m55/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ HEAP_SIZE = 0x00000000 /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports/cortex_m55/ac6/src/tx_misra.S b/ports/cortex_m55/ac6/src/tx_misra.S index 8ac0c629..10548671 100644 --- a/ports/cortex_m55/ac6/src/tx_misra.S +++ b/ports/cortex_m55/ac6/src/tx_misra.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -667,7 +668,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -682,7 +683,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARM_FP /***********************************************************************************************/ @@ -699,8 +700,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -714,9 +715,9 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - + .data .word 0 diff --git a/ports/cortex_m55/ac6/src/tx_thread_context_restore.S b/ports/cortex_m55/ac6/src/tx_thread_context_restore.S index 57f8654a..5743e7d1 100644 --- a/ports/cortex_m55/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m55/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_m55/ac6/src/tx_thread_context_save.S b/ports/cortex_m55/ac6/src/tx_thread_context_save.S index 90cdbace..4b696f21 100644 --- a/ports/cortex_m55/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m55/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_m55/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m55/ac6/src/tx_thread_interrupt_control.S index 964cb460..6f34fbfd 100644 --- a/ports/cortex_m55/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m55/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_m55/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_m55/ac6/src/tx_thread_interrupt_disable.S index 04aeb300..530e18e4 100644 --- a/ports/cortex_m55/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m55/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports/cortex_m55/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_m55/ac6/src/tx_thread_interrupt_restore.S index 4a85216c..58ebf0d6 100644 --- a/ports/cortex_m55/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m55/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports/cortex_m55/ac6/src/tx_thread_schedule.S b/ports/cortex_m55/ac6/src/tx_thread_schedule.S index 76867723..a1f38fbc 100644 --- a/ports/cortex_m55/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m55/ac6/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,23 +61,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 04-02-2021 Scott Larson Modified comment(s), added */ -/* low power code, */ -/* resulting in version 6.1.6 */ -/* 06-02-2021 Scott Larson Added secure stack initialize */ -/* in SVC handler, */ -/* resulting in version 6.1.7 */ -/* 04-25-2022 Scott Larson Added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 03-08-2023 Scott Larson Added preproc FPU option, */ -/* included tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -354,7 +338,7 @@ SVC_Handler: CMP r1, #2 // Is it a secure stack free request? BEQ _tx_svc_secure_free // Yes, go there - + CMP r1, #3 // Is it a secure stack init request? BEQ _tx_svc_secure_init // Yes, go there diff --git a/ports/cortex_m55/ac6/src/tx_thread_secure_stack.c b/ports/cortex_m55/ac6/src/tx_thread_secure_stack.c index 2395e44b..c01e9fcc 100644 --- a/ports/cortex_m55/ac6/src/tx_thread_secure_stack.c +++ b/ports/cortex_m55/ac6/src/tx_thread_secure_stack.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -102,21 +103,6 @@ static INT tx_head_free_index = 0U; /* */ /* _tx_initialize_kernel_enter */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-16-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.1 */ -/* 06-02-2021 Scott Larson Modified comment(s), and */ -/* changed name, execute in */ -/* handler mode, */ -/* resulting in version 6.1.7 */ -/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ -/* secure stack allocation, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_initialize(void) diff --git a/ports/cortex_m55/ac6/src/tx_thread_secure_stack_allocate.S b/ports/cortex_m55/ac6/src/tx_thread_secure_stack_allocate.S index e6459612..bc6a2f5d 100644 --- a/ports/cortex_m55/ac6/src/tx_thread_secure_stack_allocate.S +++ b/ports/cortex_m55/ac6/src/tx_thread_secure_stack_allocate.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,14 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) // { diff --git a/ports/cortex_m55/ac6/src/tx_thread_secure_stack_free.S b/ports/cortex_m55/ac6/src/tx_thread_secure_stack_free.S index 961f2047..5de780d6 100644 --- a/ports/cortex_m55/ac6/src/tx_thread_secure_stack_free.S +++ b/ports/cortex_m55/ac6/src/tx_thread_secure_stack_free.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) // { diff --git a/ports/cortex_m55/ac6/src/tx_thread_secure_stack_initialize.S b/ports/cortex_m55/ac6/src/tx_thread_secure_stack_initialize.S index db354865..951ca86f 100644 --- a/ports/cortex_m55/ac6/src/tx_thread_secure_stack_initialize.S +++ b/ports/cortex_m55/ac6/src/tx_thread_secure_stack_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,18 +54,6 @@ /* */ /* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) // { diff --git a/ports/cortex_m55/ac6/src/tx_thread_stack_build.S b/ports/cortex_m55/ac6/src/tx_thread_stack_build.S index 8938d429..3d67bdf0 100644 --- a/ports/cortex_m55/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_m55/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_m55/ac6/src/tx_thread_system_return.S b/ports/cortex_m55/ac6/src/tx_thread_system_return.S index 297dc5a1..a27c2756 100644 --- a/ports/cortex_m55/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m55/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_m55/ac6/src/tx_timer_interrupt.S b/ports/cortex_m55/ac6/src/tx_timer_interrupt.S index 017c784b..0f0922b3 100644 --- a/ports/cortex_m55/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_m55/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_m55/ac6/src/txe_thread_secure_stack_allocate.c b/ports/cortex_m55/ac6/src/txe_thread_secure_stack_allocate.c index e7d234f6..7a5560ec 100644 --- a/ports/cortex_m55/ac6/src/txe_thread_secure_stack_allocate.c +++ b/ports/cortex_m55/ac6/src/txe_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { @@ -76,10 +71,10 @@ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_siz return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports/cortex_m55/ac6/src/txe_thread_secure_stack_free.c b/ports/cortex_m55/ac6/src/txe_thread_secure_stack_free.c index 88fa6b47..9572bad8 100644 --- a/ports/cortex_m55/ac6/src/txe_thread_secure_stack_free.c +++ b/ports/cortex_m55/ac6/src/txe_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { @@ -74,10 +69,10 @@ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports/cortex_m55/gnu/inc/tx_port.h b/ports/cortex_m55/gnu/inc/tx_port.h index 4dc8e10a..a70426fa 100644 --- a/ports/cortex_m55/gnu/inc/tx_port.h +++ b/ports/cortex_m55/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,39 +46,6 @@ /* This file replaces the previous Cortex-M55 files. It unifies */ /* the Cortex-M55 compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-02-2021 Scott Larson Modified comment(s), added */ -/* ULONG64_DEFINED, */ -/* resulting in version 6.1.5 */ -/* 06-02-2021 Scott Larson Modified comment(s), removed */ -/* unneeded header file, funcs */ -/* set_control and get_control */ -/* changed to inline, */ -/* added symbol to enable */ -/* stack error handler, */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ -/* stack check error handling, */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), unified */ -/* this file across compilers, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* 03-08-2023 Scott Larson Removed unneeded #include, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -645,7 +613,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M55/GNU Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M55/GNU Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m55/gnu/inc/tx_secure_interface.h b/ports/cortex_m55/gnu/inc/tx_secure_interface.h index 39b5d5fd..5ac37fbf 100644 --- a/ports/cortex_m55/gnu/inc/tx_secure_interface.h +++ b/ports/cortex_m55/gnu/inc/tx_secure_interface.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,12 +38,6 @@ /* It is assumed that tx_api.h and tx_port.h have already been */ /* included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_SECURE_INTERFACE_H diff --git a/ports/cortex_m55/gnu/readme_threadx.txt b/ports/cortex_m55/gnu/readme_threadx.txt index 78d64041..3358694d 100644 --- a/ports/cortex_m55/gnu/readme_threadx.txt +++ b/ports/cortex_m55/gnu/readme_threadx.txt @@ -1,32 +1,32 @@ - Microsoft's Azure RTOS ThreadX for Cortex-M55 + Microsoft's Azure RTOS ThreadX for Cortex-M55 Using the GNU Tools 1. Building the ThreadX run-time Library Import all ThreadX common and port-specific source files into a GNU project. -Configure the project to build a library rather than an executable. This -results in the ThreadX run-time library file tx.a, which is needed by +Configure the project to build a library rather than an executable. This +results in the ThreadX run-time library file tx.a, which is needed by the application. -Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c -replace the common files of the same name. +Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c +replace the common files of the same name. 2. Demonstration System -No demonstration project is provided. +No demonstration project is provided. 3. System Initialization -The entry point in ThreadX for the Cortex-M55 using gnu tools uses the standard GNU +The entry point in ThreadX for the Cortex-M55 using gnu tools uses the standard GNU Cortex-M55 reset sequence. From the reset vector the C runtime will be initialized. -The ThreadX tx_initialize_low_level.S file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. +The ThreadX tx_initialize_low_level.S file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. @@ -35,7 +35,7 @@ parameter to your application definition function, tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M55 version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -118,26 +118,26 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 5. Improving Performance -To make ThreadX and the application(s) run faster, you can enable -all compiler optimizations. +To make ThreadX and the application(s) run faster, you can enable +all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M55 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 6.1 Vector Area The Cortex-M55 vectors start at the label __tx_vectors or similar. The application may modify -the vector area according to its needs. There is code in tx_initialize_low_level() that will -configure the vector base register. +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. 6.2 Managed Interrupts @@ -170,15 +170,15 @@ your_assembly_isr: Note: the Cortex-M55 requires exception handlers to be thumb labels, this implies bit 0 set. To accomplish this, the declaration of the label has to be preceded by the assembler directive -.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to -be inserted in the correct location in the interrupt vector table. This table is typically +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically located in either your runtime startup file or in the tx_initialize_low_level.S file. 7. FPU Support -ThreadX for Cortex-M55 supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-M55 supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context. diff --git a/ports/cortex_m55/gnu/src/tx_initialize_low_level.S b/ports/cortex_m55/gnu/src/tx_initialize_low_level.S index a782cce5..ee23d9cb 100644 --- a/ports/cortex_m55/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_m55/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,16 +66,6 @@ HEAP_SIZE = 0x00000000 /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Fixed predefined macro name, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports/cortex_m55/gnu/src/tx_misra.S b/ports/cortex_m55/gnu/src/tx_misra.S index 8ac0c629..10548671 100644 --- a/ports/cortex_m55/gnu/src/tx_misra.S +++ b/ports/cortex_m55/gnu/src/tx_misra.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -667,7 +668,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -682,7 +683,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARM_FP /***********************************************************************************************/ @@ -699,8 +700,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -714,9 +715,9 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - + .data .word 0 diff --git a/ports/cortex_m55/gnu/src/tx_thread_context_restore.S b/ports/cortex_m55/gnu/src/tx_thread_context_restore.S index 4a065cbf..1805d105 100644 --- a/ports/cortex_m55/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m55/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_m55/gnu/src/tx_thread_context_save.S b/ports/cortex_m55/gnu/src/tx_thread_context_save.S index d8af04bd..634440b6 100644 --- a/ports/cortex_m55/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m55/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_m55/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m55/gnu/src/tx_thread_interrupt_control.S index 30aa8120..a2db9028 100644 --- a/ports/cortex_m55/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m55/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_m55/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_m55/gnu/src/tx_thread_interrupt_disable.S index d6ba1636..65bb5781 100644 --- a/ports/cortex_m55/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m55/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports/cortex_m55/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_m55/gnu/src/tx_thread_interrupt_restore.S index 95dbff40..37b02ef3 100644 --- a/ports/cortex_m55/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m55/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports/cortex_m55/gnu/src/tx_thread_schedule.S b/ports/cortex_m55/gnu/src/tx_thread_schedule.S index 2c9b0608..2bcc96f6 100644 --- a/ports/cortex_m55/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m55/gnu/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,24 +57,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 04-02-2021 Scott Larson Modified comment(s), added */ -/* low power code, */ -/* resulting in version 6.1.6 */ -/* 06-02-2021 Scott Larson Added secure stack initialize */ -/* in SVC handler, */ -/* resulting in version 6.1.7 */ -/* 01-31-2022 Scott Larson Fixed predefined macro name, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -351,7 +334,7 @@ SVC_Handler: CMP r1, #2 // Is it a secure stack free request? BEQ _tx_svc_secure_free // Yes, go there - + CMP r1, #3 // Is it a secure stack init request? BEQ _tx_svc_secure_init // Yes, go there diff --git a/ports/cortex_m55/gnu/src/tx_thread_secure_stack.c b/ports/cortex_m55/gnu/src/tx_thread_secure_stack.c index bbc953d7..6abfe7c7 100644 --- a/ports/cortex_m55/gnu/src/tx_thread_secure_stack.c +++ b/ports/cortex_m55/gnu/src/tx_thread_secure_stack.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -98,21 +99,6 @@ static INT tx_head_free_index = 0U; /* */ /* _tx_initialize_kernel_enter */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-16-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.1 */ -/* 06-02-2021 Scott Larson Change name, execute in */ -/* handler mode, */ -/* disable optimizations, */ -/* resulting in version 6.1.7 */ -/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ -/* secure stack allocation, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry, optimize(0))) UINT _tx_thread_secure_mode_stack_initialize(void) diff --git a/ports/cortex_m55/gnu/src/tx_thread_secure_stack_allocate.S b/ports/cortex_m55/gnu/src/tx_thread_secure_stack_allocate.S index 8db2c058..e8b290cf 100644 --- a/ports/cortex_m55/gnu/src/tx_thread_secure_stack_allocate.S +++ b/ports/cortex_m55/gnu/src/tx_thread_secure_stack_allocate.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,14 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) // { diff --git a/ports/cortex_m55/gnu/src/tx_thread_secure_stack_free.S b/ports/cortex_m55/gnu/src/tx_thread_secure_stack_free.S index 7a9e9af5..63bf3960 100644 --- a/ports/cortex_m55/gnu/src/tx_thread_secure_stack_free.S +++ b/ports/cortex_m55/gnu/src/tx_thread_secure_stack_free.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) // { diff --git a/ports/cortex_m55/gnu/src/tx_thread_secure_stack_initialize.S b/ports/cortex_m55/gnu/src/tx_thread_secure_stack_initialize.S index 57d8fb95..3d38f451 100644 --- a/ports/cortex_m55/gnu/src/tx_thread_secure_stack_initialize.S +++ b/ports/cortex_m55/gnu/src/tx_thread_secure_stack_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,18 +54,6 @@ /* */ /* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) // { diff --git a/ports/cortex_m55/gnu/src/tx_thread_stack_build.S b/ports/cortex_m55/gnu/src/tx_thread_stack_build.S index 3ac38296..4cc67002 100644 --- a/ports/cortex_m55/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m55/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_m55/gnu/src/tx_thread_system_return.S b/ports/cortex_m55/gnu/src/tx_thread_system_return.S index a06a3109..0fc717b9 100644 --- a/ports/cortex_m55/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m55/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_m55/gnu/src/tx_timer_interrupt.S b/ports/cortex_m55/gnu/src/tx_timer_interrupt.S index c2a389aa..c2cd185a 100644 --- a/ports/cortex_m55/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_m55/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_m55/gnu/src/txe_thread_secure_stack_allocate.c b/ports/cortex_m55/gnu/src/txe_thread_secure_stack_allocate.c index e7d234f6..7a5560ec 100644 --- a/ports/cortex_m55/gnu/src/txe_thread_secure_stack_allocate.c +++ b/ports/cortex_m55/gnu/src/txe_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { @@ -76,10 +71,10 @@ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_siz return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports/cortex_m55/gnu/src/txe_thread_secure_stack_free.c b/ports/cortex_m55/gnu/src/txe_thread_secure_stack_free.c index 88fa6b47..9572bad8 100644 --- a/ports/cortex_m55/gnu/src/txe_thread_secure_stack_free.c +++ b/ports/cortex_m55/gnu/src/txe_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { @@ -74,10 +69,10 @@ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports/cortex_m55/iar/inc/tx_port.h b/ports/cortex_m55/iar/inc/tx_port.h index 2d29efe3..b8a389f5 100644 --- a/ports/cortex_m55/iar/inc/tx_port.h +++ b/ports/cortex_m55/iar/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,39 +46,6 @@ /* This file replaces the previous Cortex-M55 files. It unifies */ /* the Cortex-M55 compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-02-2021 Scott Larson Modified comment(s), added */ -/* ULONG64_DEFINED, */ -/* resulting in version 6.1.5 */ -/* 06-02-2021 Scott Larson Modified comment(s), removed */ -/* unneeded header file, funcs */ -/* set_control and get_control */ -/* changed to inline, */ -/* added symbol to enable */ -/* stack error handler, */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ -/* stack check error handling, */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), unified */ -/* this file across compilers, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* 03-08-2023 Scott Larson Removed unneeded #include, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -645,7 +613,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M55/IAR Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M55/IAR Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m55/iar/inc/tx_secure_interface.h b/ports/cortex_m55/iar/inc/tx_secure_interface.h index 39b5d5fd..5ac37fbf 100644 --- a/ports/cortex_m55/iar/inc/tx_secure_interface.h +++ b/ports/cortex_m55/iar/inc/tx_secure_interface.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,12 +38,6 @@ /* It is assumed that tx_api.h and tx_port.h have already been */ /* included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_SECURE_INTERFACE_H diff --git a/ports/cortex_m55/iar/readme_threadx.txt b/ports/cortex_m55/iar/readme_threadx.txt index 1d89e2cb..dcbee39e 100644 --- a/ports/cortex_m55/iar/readme_threadx.txt +++ b/ports/cortex_m55/iar/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for Cortex-M55 + Microsoft's Azure RTOS ThreadX for Cortex-M55 Using the IAR Tools @@ -6,33 +6,33 @@ 1. Building the ThreadX run-time Library Import all ThreadX common and port-specific source files into an IAR project. -Configure the project to build a library rather than an executable. This -results in the ThreadX run-time library file tx.a, which is needed by +Configure the project to build a library rather than an executable. This +results in the ThreadX run-time library file tx.a, which is needed by the application. -Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c -replace the common files of the same name. +Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c +replace the common files of the same name. 2. Demonstration System No demonstration is provided because the IAR EWARM 8.50 simulator does -not simulate the Cortex-M55 correctly. +not simulate the Cortex-M55 correctly. 3. System Initialization -The entry point in ThreadX for the Cortex-M55 using IAR tools is at label -__iar_program_start. This is defined within the IAR compiler's startup code. -In addition, this is where all static and global preset C variable +The entry point in ThreadX for the Cortex-M55 using IAR tools is at label +__iar_program_start. This is defined within the IAR compiler's startup code. +In addition, this is where all static and global preset C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, and a periodic timer interrupt source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. The _tx_initialize_low_level function inside of tx_initialize_low_level.s -also determines the first available address for use by the application, which -is supplied as the sole input parameter to your application definition function, -tx_application_define. To accomplish this, a section is created in -tx_initialize_low_level.s called FREE_MEM, which must be located after all +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all other RAM sections in memory. @@ -41,7 +41,7 @@ other RAM sections in memory. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M55 version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -124,17 +124,17 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 5. Improving Performance -To make ThreadX and the application(s) run faster, you can enable -all compiler optimizations. +To make ThreadX and the application(s) run faster, you can enable +all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling -The Cortex-M55 vectors start at the label __vector_table and is typically defined in a +The Cortex-M55 vectors start at the label __vector_table and is typically defined in a startup.s file (or similar). The application may modify the vector area according to its needs. @@ -182,14 +182,14 @@ should have the following line added (if not already in place): initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application -The project options "General Options -> Library Configuration" should also have the +The project options "General Options -> Library Configuration" should also have the "Enable thread support in library" box selected. 8. VFP Support -ThreadX for Cortex-M55 supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-M55 supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context. diff --git a/ports/cortex_m55/iar/src/tx_iar.c b/ports/cortex_m55/iar/src/tx_iar.c index ee47f10f..238b485e 100644 --- a/ports/cortex_m55/iar/src/tx_iar.c +++ b/ports/cortex_m55/iar/src/tx_iar.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports/cortex_m55/iar/src/tx_initialize_low_level.s b/ports/cortex_m55/iar/src/tx_initialize_low_level.s index 3bb984aa..312e8267 100644 --- a/ports/cortex_m55/iar/src/tx_initialize_low_level.s +++ b/ports/cortex_m55/iar/src/tx_initialize_low_level.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,13 +75,6 @@ __tx_free_memory_start /* CALLED BY */ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports/cortex_m55/iar/src/tx_misra.s b/ports/cortex_m55/iar/src/tx_misra.s index f86d9a65..642bb89e 100644 --- a/ports/cortex_m55/iar/src/tx_misra.s +++ b/ports/cortex_m55/iar/src/tx_misra.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -120,7 +121,7 @@ SECTION `.data`:DATA:REORDER:NOROOT(2) DATA -// 51 CHAR _tx_version_id[100] = "Copyright (c) 2024 Microsoft Corporation. * ThreadX 6.1 MISRA C Compliant *"; +// 51 CHAR _tx_version_id[100] = "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX 6.1 MISRA C Compliant *"; _tx_version_id: DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H @@ -707,7 +708,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -722,7 +723,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARMVFP__ /***********************************************************************************************/ @@ -739,8 +740,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -754,10 +755,10 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - - + + SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2) SECTION_TYPE SHT_PROGBITS, 0 DATA diff --git a/ports/cortex_m55/iar/src/tx_thread_context_restore.s b/ports/cortex_m55/iar/src/tx_thread_context_restore.s index 3be0669a..623329ae 100644 --- a/ports/cortex_m55/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_m55/iar/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,13 +56,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_m55/iar/src/tx_thread_context_save.s b/ports/cortex_m55/iar/src/tx_thread_context_save.s index fc1acfa4..5c8d88de 100644 --- a/ports/cortex_m55/iar/src/tx_thread_context_save.s +++ b/ports/cortex_m55/iar/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,13 +56,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_m55/iar/src/tx_thread_interrupt_control.s b/ports/cortex_m55/iar/src/tx_thread_interrupt_control.s index c4bae75f..ccfd7289 100644 --- a/ports/cortex_m55/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m55/iar/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,13 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_m55/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m55/iar/src/tx_thread_interrupt_disable.s index 59546c0e..fce50a21 100644 --- a/ports/cortex_m55/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m55/iar/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,13 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports/cortex_m55/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_m55/iar/src/tx_thread_interrupt_restore.s index 2efba029..9ba67719 100644 --- a/ports/cortex_m55/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m55/iar/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,13 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports/cortex_m55/iar/src/tx_thread_schedule.s b/ports/cortex_m55/iar/src/tx_thread_schedule.s index d0441084..822fa83a 100644 --- a/ports/cortex_m55/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m55/iar/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -73,23 +74,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 04-02-2021 Scott Larson Modified comment(s), added */ -/* low power code, */ -/* resulting in version 6.1.6 */ -/* 06-02-2021 Scott Larson Added secure stack initialize */ -/* in SVC handler, */ -/* resulting in version 6.1.7 */ -/* 04-25-2022 Scott Larson Added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 03-08-2023 Scott Larson Added preproc FPU option, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -348,7 +332,7 @@ SVC_Handler: CMP r1, #2 // Is it a secure stack free request? BEQ _tx_svc_secure_free // Yes, go there - + CMP r1, #3 // Is it a secure stack init request? BEQ _tx_svc_secure_init // Yes, go there diff --git a/ports/cortex_m55/iar/src/tx_thread_secure_stack.c b/ports/cortex_m55/iar/src/tx_thread_secure_stack.c index d7ec07cb..fd6388f2 100644 --- a/ports/cortex_m55/iar/src/tx_thread_secure_stack.c +++ b/ports/cortex_m55/iar/src/tx_thread_secure_stack.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -102,20 +103,6 @@ static INT tx_head_free_index = 0U; /* */ /* _tx_initialize_kernel_enter */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-16-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.1 */ -/* 06-02-2021 Scott Larson Change name, execute in */ -/* handler mode, */ -/* resulting in version 6.1.7 */ -/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ -/* secure stack allocation, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_initialize(void) diff --git a/ports/cortex_m55/iar/src/tx_thread_secure_stack_allocate.s b/ports/cortex_m55/iar/src/tx_thread_secure_stack_allocate.s index 0183e0f8..c3cbf71d 100644 --- a/ports/cortex_m55/iar/src/tx_thread_secure_stack_allocate.s +++ b/ports/cortex_m55/iar/src/tx_thread_secure_stack_allocate.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,13 +57,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) // { diff --git a/ports/cortex_m55/iar/src/tx_thread_secure_stack_free.s b/ports/cortex_m55/iar/src/tx_thread_secure_stack_free.s index 54c56e7d..46af894b 100644 --- a/ports/cortex_m55/iar/src/tx_thread_secure_stack_free.s +++ b/ports/cortex_m55/iar/src/tx_thread_secure_stack_free.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,13 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) // { diff --git a/ports/cortex_m55/iar/src/tx_thread_secure_stack_initialize.s b/ports/cortex_m55/iar/src/tx_thread_secure_stack_initialize.s index b9683f7a..7e1a4fb1 100644 --- a/ports/cortex_m55/iar/src/tx_thread_secure_stack_initialize.s +++ b/ports/cortex_m55/iar/src/tx_thread_secure_stack_initialize.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* CALLED BY */ /* */ /* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) // { diff --git a/ports/cortex_m55/iar/src/tx_thread_stack_build.s b/ports/cortex_m55/iar/src/tx_thread_stack_build.s index dde61ace..31dc6469 100644 --- a/ports/cortex_m55/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_m55/iar/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,13 +58,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_m55/iar/src/tx_thread_system_return.s b/ports/cortex_m55/iar/src/tx_thread_system_return.s index a5e158ab..2762f49e 100644 --- a/ports/cortex_m55/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m55/iar/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,13 +58,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_m55/iar/src/tx_timer_interrupt.s b/ports/cortex_m55/iar/src/tx_timer_interrupt.s index c8cb6eea..9a25fb24 100644 --- a/ports/cortex_m55/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_m55/iar/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,13 +72,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_m55/iar/src/txe_thread_secure_stack_allocate.c b/ports/cortex_m55/iar/src/txe_thread_secure_stack_allocate.c index e7d234f6..7a5560ec 100644 --- a/ports/cortex_m55/iar/src/txe_thread_secure_stack_allocate.c +++ b/ports/cortex_m55/iar/src/txe_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { @@ -76,10 +71,10 @@ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_siz return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports/cortex_m55/iar/src/txe_thread_secure_stack_free.c b/ports/cortex_m55/iar/src/txe_thread_secure_stack_free.c index 88fa6b47..9572bad8 100644 --- a/ports/cortex_m55/iar/src/txe_thread_secure_stack_free.c +++ b/ports/cortex_m55/iar/src/txe_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { @@ -74,10 +69,10 @@ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports/cortex_m7/ac5/example_build/sample_threadx.c b/ports/cortex_m7/ac5/example_build/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports/cortex_m7/ac5/example_build/sample_threadx.c +++ b/ports/cortex_m7/ac5/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_m7/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_m7/ac5/example_build/tx_initialize_low_level.s index bd6aa150..07c27743 100644 --- a/ports/cortex_m7/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m7/ac5/example_build/tx_initialize_low_level.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -131,12 +131,6 @@ Reset_Handler ;/* */ ;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) ;{ diff --git a/ports/cortex_m7/ac5/inc/tx_port.h b/ports/cortex_m7/ac5/inc/tx_port.h index b0c57c9c..717bd127 100644 --- a/ports/cortex_m7/ac5/inc/tx_port.h +++ b/ports/cortex_m7/ac5/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,23 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comments, updated */ -/* typedef to fix misra */ -/* violation, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -371,7 +355,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -530,7 +514,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #endif @@ -715,7 +699,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M7/AC5 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7/AC5 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m7/ac5/readme_threadx.txt b/ports/cortex_m7/ac5/readme_threadx.txt index b7b7cee9..e261213e 100644 --- a/ports/cortex_m7/ac5/readme_threadx.txt +++ b/ports/cortex_m7/ac5/readme_threadx.txt @@ -5,14 +5,14 @@ 1. Building the ThreadX run-time Library -Navigate to the "example_build" directory. Ensure that -you have setup your path and other environment variables necessary for the AC5 -compiler. At this point you may run the build_threadx.bat batch file. This will -build the ThreadX run-time environment in the "example_build" directory. +Navigate to the "example_build" directory. Ensure that +you have setup your path and other environment variables necessary for the AC5 +compiler. At this point you may run the build_threadx.bat batch file. This will +build the ThreadX run-time environment in the "example_build" directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. @@ -21,28 +21,28 @@ application in order to use ThreadX. The ThreadX demonstration is designed to execute under the ARM DS Cortex-M simulator. -Building the demonstration is easy; simply execute the build_threadx_sample.bat +Building the demonstration is easy; simply execute the build_threadx_sample.bat batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with tx.a. The resulting file sample_threadx.axf +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.axf is a binary file that can be downloaded and executed on the ARM DS Cortex-M simulator. 3. System Initialization -The entry point in ThreadX for the Cortex-M using AC5 tools is at label -__main. This is defined within the AC5 compiler's startup code. In -addition, this is where all static and global pre-set C variable +The entry point in ThreadX for the Cortex-M using AC5 tools is at label +__main. This is defined within the AC5 compiler's startup code. In +addition, this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. @@ -51,7 +51,7 @@ parameter to your application definition function, tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -134,21 +134,21 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 5. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the ThreadX library project to enable various compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: @@ -187,8 +187,8 @@ your_assembly_isr 7. FPU Support -ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context - no additional setup by the application. diff --git a/ports/cortex_m7/ac5/src/tx_thread_context_restore.s b/ports/cortex_m7/ac5/src/tx_thread_context_restore.s index 5e826e21..0fb0e6c9 100644 --- a/ports/cortex_m7/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_m7/ac5/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_m7/ac5/src/tx_thread_context_save.s b/ports/cortex_m7/ac5/src/tx_thread_context_save.s index 0445f04c..12b27e73 100644 --- a/ports/cortex_m7/ac5/src/tx_thread_context_save.s +++ b/ports/cortex_m7/ac5/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_m7/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_m7/ac5/src/tx_thread_interrupt_control.s index 13ad3b6f..760396b3 100644 --- a/ports/cortex_m7/ac5/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m7/ac5/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_m7/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_m7/ac5/src/tx_thread_interrupt_disable.s index f3268762..02506666 100644 --- a/ports/cortex_m7/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m7/ac5/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports/cortex_m7/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_m7/ac5/src/tx_thread_interrupt_restore.s index b51e9997..1b099aa2 100644 --- a/ports/cortex_m7/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m7/ac5/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports/cortex_m7/ac5/src/tx_thread_schedule.s b/ports/cortex_m7/ac5/src/tx_thread_schedule.s index 1f7d6e13..4ff53e17 100644 --- a/ports/cortex_m7/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_m7/ac5/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,17 +68,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 04-25-2022 Scott Larson Added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_m7/ac5/src/tx_thread_stack_build.s b/ports/cortex_m7/ac5/src/tx_thread_stack_build.s index 6f0a830f..d54a8486 100644 --- a/ports/cortex_m7/ac5/src/tx_thread_stack_build.s +++ b/ports/cortex_m7/ac5/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_m7/ac5/src/tx_thread_system_return.s b/ports/cortex_m7/ac5/src/tx_thread_system_return.s index 98ac59de..ed7165df 100644 --- a/ports/cortex_m7/ac5/src/tx_thread_system_return.s +++ b/ports/cortex_m7/ac5/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_m7/ac5/src/tx_timer_interrupt.s b/ports/cortex_m7/ac5/src/tx_timer_interrupt.s index ea6286b8..f2393840 100644 --- a/ports/cortex_m7/ac5/src/tx_timer_interrupt.s +++ b/ports/cortex_m7/ac5/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,18 +72,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_m7/ac6/example_build/sample_threadx/.cproject b/ports/cortex_m7/ac6/example_build/sample_threadx/.cproject index c131df5e..f3357354 100644 --- a/ports/cortex_m7/ac6/example_build/sample_threadx/.cproject +++ b/ports/cortex_m7/ac6/example_build/sample_threadx/.cproject @@ -1,170 +1,170 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_m7/ac6/example_build/sample_threadx/exceptions.c b/ports/cortex_m7/ac6/example_build/sample_threadx/exceptions.c index 94c87d7a..f0dd8600 100644 --- a/ports/cortex_m7/ac6/example_build/sample_threadx/exceptions.c +++ b/ports/cortex_m7/ac6/example_build/sample_threadx/exceptions.c @@ -1,7 +1,7 @@ /* ** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ** Use, modification and redistribution of this file is subject to your possession of a -** valid End User License Agreement for the Arm Product of which these examples are part of +** valid End User License Agreement for the Arm Product of which these examples are part of ** and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.c index 597f373c..13ffadba 100644 --- a/ports/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -81,42 +81,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -124,23 +124,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -243,11 +243,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -306,7 +306,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -359,7 +359,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.scat index 8b4bb5bd..8be90bfd 100644 --- a/ports/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S index ae298a34..11525a95 100644 --- a/ports/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,10 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @@ -75,12 +75,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* */ @/* _tx_initialize_kernel_enter ThreadX entry function */ @/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) @{ diff --git a/ports/cortex_m7/ac6/example_build/tx/.cproject b/ports/cortex_m7/ac6/example_build/tx/.cproject index 7593891a..5cd65b69 100644 --- a/ports/cortex_m7/ac6/example_build/tx/.cproject +++ b/ports/cortex_m7/ac6/example_build/tx/.cproject @@ -1,146 +1,146 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_m7/ac6/inc/tx_port.h b/ports/cortex_m7/ac6/inc/tx_port.h index f3168bbf..d3b3bb01 100644 --- a/ports/cortex_m7/ac6/inc/tx_port.h +++ b/ports/cortex_m7/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,23 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comments, updated */ -/* typedef to fix misra */ -/* violation, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -371,7 +355,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -530,7 +514,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #endif @@ -715,7 +699,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M7/AC6 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7/AC6 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m7/ac6/readme_threadx.txt b/ports/cortex_m7/ac6/readme_threadx.txt index d98c90cb..6447c517 100644 --- a/ports/cortex_m7/ac6/readme_threadx.txt +++ b/ports/cortex_m7/ac6/readme_threadx.txt @@ -5,12 +5,12 @@ 1. Building the ThreadX run-time Library -In order to build the ThreadX library and the ThreadX demonstration, first import -the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +In order to build the ThreadX library and the ThreadX demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) into your DS workspace. -Building the ThreadX library is easy; simply right-click the Eclipse project -"tx" and then select the "Build Project" button. You should now observe the compilation +Building the ThreadX library is easy; simply right-click the Eclipse project +"tx" and then select the "Build Project" button. You should now observe the compilation and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. @@ -20,27 +20,27 @@ library file tx.a. The ThreadX demonstration is designed to execute under the DS debugger on the MPS2_Cortex_Mx Bare Metal simulator. -Building the demonstration is easy; simply right-click the Eclipse project -"sample_threadx" and then select the "Build Project" button. You should now observe -the compilation and assembly of the ThreadX demonstration. This project build produces -the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder +Building the demonstration is easy; simply right-click the Eclipse project +"sample_threadx" and then select the "Build Project" button. You should now observe +the compilation and assembly of the ThreadX demonstration. This project build produces +the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder in the Project Explorer window, right-click on the 'cortex-mx_tx.launch' file, click 'Debug As', and then click 'cortex-mx_tx' from the submenu. This will cause the -debugger to load the sample_threadx.axf ELF file and run to main. You are now ready +debugger to load the sample_threadx.axf ELF file and run to main. You are now ready to execute the ThreadX demonstration. 3. System Initialization -The entry point in ThreadX for the Cortex-M using AC6 tools uses the standard GNU +The entry point in ThreadX for the Cortex-M using AC6 tools uses the standard GNU Cortex-M reset sequence. From the reset vector the C runtime will be initialized. -The ThreadX tx_initialize_low_level.S file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. +The ThreadX tx_initialize_low_level.S file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. @@ -49,7 +49,7 @@ parameter to your application definition function, tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -132,34 +132,34 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 5. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the ThreadX library project to enable various compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 6.1 Vector Area The Cortex-M vectors start at the label __tx_vectors or similar. The application may modify -the vector area according to its needs. There is code in tx_initialize_low_level() that will -configure the vector base register. +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. 6.2 Managed Interrupts -A ThreadX managed interrupt is defined below. By following these conventions, the +A ThreadX managed interrupt is defined below. By following these conventions, the application ISR is then allowed access to various ThreadX services from the ISR. Here is the standard template for managed ISRs in ThreadX: @@ -181,15 +181,15 @@ __tx_IntHandler: Note: the Cortex-M requires exception handlers to be thumb labels, this implies bit 0 set. To accomplish this, the declaration of the label has to be preceded by the assembler directive -.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to -be inserted in the correct location in the interrupt vector table. This table is typically +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically located in either your runtime startup file or in the tx_initialize_low_level.S file. 7. FPU Support -ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context - no additional setup by the application. diff --git a/ports/cortex_m7/ac6/src/tx_misra.S b/ports/cortex_m7/ac6/src/tx_misra.S index 8ac0c629..10548671 100644 --- a/ports/cortex_m7/ac6/src/tx_misra.S +++ b/ports/cortex_m7/ac6/src/tx_misra.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -667,7 +668,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -682,7 +683,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARM_FP /***********************************************************************************************/ @@ -699,8 +700,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -714,9 +715,9 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - + .data .word 0 diff --git a/ports/cortex_m7/ac6/src/tx_thread_context_restore.S b/ports/cortex_m7/ac6/src/tx_thread_context_restore.S index 003bf20d..9ecbaa0c 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m7/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_m7/ac6/src/tx_thread_context_save.S b/ports/cortex_m7/ac6/src/tx_thread_context_save.S index a88957cc..1fab2a9b 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m7/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,14 +61,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_m7/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m7/ac6/src/tx_thread_interrupt_control.S index ddd46eb5..a10c760a 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m7/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_m7/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_m7/ac6/src/tx_thread_interrupt_disable.S index f58e63d0..ea8bfd4d 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m7/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports/cortex_m7/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_m7/ac6/src/tx_thread_interrupt_restore.S index d195b3ff..7ea62177 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m7/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports/cortex_m7/ac6/src/tx_thread_schedule.S b/ports/cortex_m7/ac6/src/tx_thread_schedule.S index d9d202ae..e411198e 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m7/ac6/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,16 +71,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 04-25-2022 Scott Larson Added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_m7/ac6/src/tx_thread_stack_build.S b/ports/cortex_m7/ac6/src/tx_thread_stack_build.S index fd1aa689..0fd0dc46 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_m7/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_m7/ac6/src/tx_thread_system_return.S b/ports/cortex_m7/ac6/src/tx_thread_system_return.S index 57262ceb..831c00e4 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m7/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_m7/ac6/src/tx_timer_interrupt.S b/ports/cortex_m7/ac6/src/tx_timer_interrupt.S index 86f2a7f3..a2f1a438 100644 --- a/ports/cortex_m7/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_m7/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,17 +71,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_m7/ghs/example_build/sample_threadx.c b/ports/cortex_m7/ghs/example_build/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports/cortex_m7/ghs/example_build/sample_threadx.c +++ b/ports/cortex_m7/ghs/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_m7/ghs/example_build/tx_initialize_low_level.arm b/ports/cortex_m7/ghs/example_build/tx_initialize_low_level.arm index d71a73db..57c964b3 100644 --- a/ports/cortex_m7/ghs/example_build/tx_initialize_low_level.arm +++ b/ports/cortex_m7/ghs/example_build/tx_initialize_low_level.arm @@ -1,18 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Initialize */ /** */ @@ -24,42 +24,42 @@ .text .align 4 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_initialize_low_level Cortex-M7/GHS */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M7/GHS */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function is responsible for any low-level processor */ -/* initialization, including setting up interrupt vectors, setting */ -/* up a periodic timer interrupt source, saving the system stack */ -/* pointer for use in ISR processing later, and finding the first */ -/* available RAM memory address for tx_application_define. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -71,7 +71,7 @@ _tx_initialize_low_level: /* Disable interrupts. */ - + CPSID i ; Disable interrupts @@ -79,7 +79,7 @@ _tx_initialize_low_level: /* _tx_thread_system_stack_ptr = (VOID_PTR) (sp); */ LDR r1,=_tx_thread_system_stack_ptr ; Pickup address of system stack ptr - STR sp, [r1] ; Save system stack + STR sp, [r1] ; Save system stack /* Save the first available memory address. */ @@ -95,14 +95,14 @@ _tx_initialize_low_level: LDR r0, =0xE0001000 ; Build address of DWT register LDR r1, [r0] ; Pickup the current value ORR r1, r1, 1 ; Set the CYCCNTENA bit - STR r1, [r0] ; Enable the cycle count register + STR r1, [r0] ; Enable the cycle count register /* Setup Vector Table Offset Register. */ - + MOV r0, 0xE000E000 ; Build address of NVIC registers LDR r1, =__vectors ; Pickup address of vector table - STR r1, [r0, 0xD08] ; Set vector table address + STR r1, [r0, 0xD08] ; Set vector table address /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ @@ -134,7 +134,7 @@ _tx_initialize_low_level: #endif /* Return to caller. */ - + BX lr ; Return to caller .type _tx_initialize_low_level,$function @@ -145,7 +145,7 @@ _tx_initialize_low_level: /* Define shells for each of the interrupt vectors. */ .globl __tx_BadHandler -__tx_BadHandler: +__tx_BadHandler: B __tx_BadHandler .type __tx_BadHandler,$function @@ -161,7 +161,7 @@ __tx_IntHandler: MOV r0, 0 ; Build interrupt code BL _tx_el_interrupt ; Call interrupt event logging #endif - + ; /* Do interrupt handler work here */ ; /* .... */ @@ -199,7 +199,7 @@ __tx_SysTickHandler: .size __tx_SysTickHandler,.-__tx_SysTickHandler - .globl __tx_NMIHandler + .globl __tx_NMIHandler __tx_NMIHandler: B __tx_NMIHandler @@ -220,7 +220,7 @@ __tx_SVCallHandler: B __tx_SVCallHandler .type __tx_SVCallHandler,$function - .size __tx_SVCallHandler,.-__tx_SVCallHandler + .size __tx_SVCallHandler,.-__tx_SVCallHandler /* Reference build options and version ID to ensure they come in. */ diff --git a/ports/cortex_m7/ghs/inc/tx_el.h b/ports/cortex_m7/ghs/inc/tx_el.h index 4662f241..72e5bbe3 100644 --- a/ports/cortex_m7/ghs/inc/tx_el.h +++ b/ports/cortex_m7/ghs/inc/tx_el.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** ThreadX/GHS Event Log (EL) */ @@ -20,27 +21,21 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* COMPONENT DEFINITION RELEASE */ -/* */ -/* tx_el.h PORTABLE C/GHS */ +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_el.h PORTABLE C/GHS */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file defines the ThreadX event log functions for the GHS MULTI */ -/* EventAnalyzer. It is assumed that tx_api.h and tx_port.h have */ -/* already been included. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This file defines the ThreadX event log functions for the GHS MULTI */ +/* EventAnalyzer. It is assumed that tx_api.h and tx_port.h have */ +/* already been included. */ /* */ /**************************************************************************/ @@ -53,16 +48,16 @@ #define TX_EL_VERSION_ID 2 /* Event log version ID */ #define TX_EL_HEADER_SIZE 24 /* Event log header size */ #define TX_EL_TNIS 16 /* Number of thread names supported */ - /* If the application needs to */ - /* track more thread names, just */ - /* increase this number and re- */ - /* build the ThreadX library. */ + /* If the application needs to */ + /* track more thread names, just */ + /* increase this number and re- */ + /* build the ThreadX library. */ #define TX_EL_TNI_ENTRY_SIZE 44 /* Thread name entries are 44 bytes */ #define TX_EL_TNI_NAME_SIZE 34 /* Thread name size in TNI */ #define TX_EL_NO_MORE_TNI_ROOM 1 /* Error return from thread register*/ -#define TX_EL_NAME_NOT_FOUND 2 /* Error return from un-register */ +#define TX_EL_NAME_NOT_FOUND 2 /* Error return from un-register */ #define TX_EL_EVENT_SIZE 32 /* Number of bytes in each event */ -#define TX_EL_VALID_ENTRY 1 /* Valid log entry */ +#define TX_EL_VALID_ENTRY 1 /* Valid log entry */ #define TX_EL_INVALID_ENTRY 0 /* Invalid log entry */ @@ -295,7 +290,7 @@ /* Define filter macros that are inserted in-line with the other macros below. */ -#ifdef TX_ENABLE_EVENT_FILTERS +#ifdef TX_ENABLE_EVENT_FILTERS #define TX_EL_NO_STATUS_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_STATUS_CHANGE)) { #define TX_EL_NO_INTERRUPT_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_INTERRUPTS)) { #define TX_EL_NO_THREAD_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_THREAD_CALLS)) { @@ -430,7 +425,7 @@ extern ULONG _tx_el_time_base_lower; VOID _tx_el_initialize(VOID); UINT _tx_el_thread_register(TX_THREAD *thread_ptr); UINT _tx_el_thread_unregister(TX_THREAD *thread_ptr); -VOID _tx_el_user_event_insert(UINT sub_type, ULONG info_1, ULONG info_2, +VOID _tx_el_user_event_insert(UINT sub_type, ULONG info_1, ULONG info_2, ULONG info_3, ULONG info_4); VOID _tx_el_thread_running(TX_THREAD *thread_ptr); VOID _tx_el_thread_preempted(TX_THREAD *thread_ptr); @@ -747,7 +742,7 @@ VOID _tx_el_event_filter_set(UINT filter); #define TX_EL_THREAD_UNREGISTER(a) \ _tx_el_thread_unregister(a); #define TX_EL_INITIALIZE _tx_el_initialize(); -#endif +#endif #else #define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(a, b, c, d, e) #define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(a, b, c, d) diff --git a/ports/cortex_m7/ghs/inc/tx_port.h b/ports/cortex_m7/ghs/inc/tx_port.h index 4f0ae8f1..aabf714e 100644 --- a/ports/cortex_m7/ghs/inc/tx_port.h +++ b/ports/cortex_m7/ghs/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -61,7 +53,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -112,7 +104,7 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY +#ifndef TX_TIMER_THREAD_PRIORITY #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -123,8 +115,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0 /* Enable interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -133,7 +125,7 @@ typedef unsigned short USHORT; */ #ifndef TX_TRACE_TIME_SOURCE -#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) #endif #ifndef TX_TRACE_TIME_MASK #define TX_TRACE_TIME_MASK 0xFFFFFFFFUL @@ -145,13 +137,13 @@ typedef unsigned short USHORT; /* Define the number of ticks per second. This informs the EventAnalyzer what the timestamps represent. By default, this is set to 1,000,000 i.e., one tick every microsecond. */ -#define TX_EL_TICKS_PER_SECOND 1000000 +#define TX_EL_TICKS_PER_SECOND 1000000 /* Define the method of how to get the upper and lower 32-bits of the time stamp. By default, simply - simulate the time-stamp source with a counter. */ + simulate the time-stamp source with a counter. */ -#define read_tbu() _tx_el_time_base_upper -#define read_tbl() ++_tx_el_time_base_lower +#define read_tbu() _tx_el_time_base_upper +#define read_tbl() ++_tx_el_time_base_lower /* Define the port specific options for the _tx_build_options variable. This variable indicates @@ -167,7 +159,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -179,19 +171,19 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #define TX_THREAD_EXTENSION_2 VOID * tx_thread_eh_globals; \ int Errno; /* errno. */ \ char * strtok_saved_pos; /* strtok() position. */ #ifndef TX_ENABLE_EXECUTION_CHANGE_NOTIFY -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -206,11 +198,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -240,7 +232,7 @@ typedef unsigned short USHORT; extern void __tx_cpp_exception_cleanup(TX_THREAD *thread_ptr); \ __tx_cpp_exception_cleanup(thread_ptr); \ } -#else +#else #define TX_THREAD_DELETE_EXTENSION(thread_ptr) \ { \ #pragma weak __cpp_exception_cleanup \ @@ -279,7 +271,7 @@ typedef unsigned short USHORT; /* Define the get system state macro. */ - + #ifndef TX_THREAD_GET_SYSTEM_STATE #define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __MRS(__IPSR)) #endif @@ -291,32 +283,32 @@ typedef unsigned short USHORT; zero after initialization for Cortex-M ports. */ #ifndef TX_THREAD_SYSTEM_RETURN_CHECK -#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); #endif -/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to prevent early scheduling on Cortex-M parts. */ - + #define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = __CLZ32(m); \ - b = 31 - b; + b = 31 - b; #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -386,7 +378,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M7/GHS Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7/GHS Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m7/ghs/readme_threadx.txt b/ports/cortex_m7/ghs/readme_threadx.txt index 22466c4e..f494875f 100644 --- a/ports/cortex_m7/ghs/readme_threadx.txt +++ b/ports/cortex_m7/ghs/readme_threadx.txt @@ -4,16 +4,16 @@ 1. Open the ThreadX Project Workspace -In order to build the ThreadX library and the ThreadX demonstration first load -the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the -"example_build" directory. +In order to build the ThreadX library and the ThreadX demonstration first load +the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the +"example_build" directory. 2. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply select the MULTI project file -tx.gpj and then select the build button. You should now observe the -compilation and assembly of the ThreadX library. This project build produces +Building the ThreadX library is easy; simply select the MULTI project file +tx.gpj and then select the build button. You should now observe the +compilation and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. @@ -21,52 +21,52 @@ the ThreadX library file tx.a. The ThreadX demonstration is designed to execute under the MULTI environment on the Green Hills Cortex-M7 simulator. The instructions that follow describe -how to get the ThreadX evaluation running under the MULTI Cortex-M7 simulation +how to get the ThreadX evaluation running under the MULTI Cortex-M7 simulation environment. -Building the demonstration is easy; simply select the MULTI project file -sample_threadx.gpj. At this point, select the "Project Build" button and observe -the compilation, assembly, and linkage of the ThreadX demonstration application. +Building the demonstration is easy; simply select the MULTI project file +sample_threadx.gpj. At this point, select the "Project Build" button and observe +the compilation, assembly, and linkage of the ThreadX demonstration application. -After the demonstration is built, invoke the MULTI ARM simulator by selecting -the simulator connection from within the sample_threadx.con connection file. -Once connected to the simulator, select the "Debug" button. You should now -observe the main function of sample_threadx.c. +After the demonstration is built, invoke the MULTI ARM simulator by selecting +the simulator connection from within the sample_threadx.con connection file. +Once connected to the simulator, select the "Debug" button. You should now +observe the main function of sample_threadx.c. -You are now ready to execute the ThreadX demonstration system. Select -breakpoints and data watches to observe the execution of the sample_threadx.c +You are now ready to execute the ThreadX demonstration system. Select +breakpoints and data watches to observe the execution of the sample_threadx.c application. 4. EventAnalyzer Demonstration -To build a demonstration system that also logs events for the MULTI EventAnalyzer, -perform the same steps as the regular demo, except build the ThreadX library with -txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. -The resulting image will log all system events, which can then be displayed by the +To build a demonstration system that also logs events for the MULTI EventAnalyzer, +perform the same steps as the regular demo, except build the ThreadX library with +txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. +The resulting image will log all system events, which can then be displayed by the MULTI EventAnalyzer. 5. System Initialization -The system entry point using the Green Hills tools is at the label _start. -This is defined within the crt0.arm file supplied by Green Hills. In addition, -this is where all static and global preset C variable initialization +The system entry point using the Green Hills tools is at the label _start. +This is defined within the crt0.arm file supplied by Green Hills. In addition, +this is where all static and global preset C variable initialization processing is called from. After the Green Hills startup function returns, ThreadX initialization is called. The main initialization function is _tx_initialize_low_level and -is located in the file tx_initialize_low_level.arm. This function is responsible -for setting up various system data structures, interrupt vectors, and the +is located in the file tx_initialize_low_level.arm. This function is responsible +for setting up various system data structures, interrupt vectors, and the periodic timer interrupt source of ThreadX. -In addition, _tx_initialize_low_level determines where the first available +In addition, _tx_initialize_low_level determines where the first available RAM memory address is located. This address is supplied to tx_application_define. -By default, the first available RAM memory address is assumed to start at the -beginning of the ThreadX section .free_mem. If changes are made to the -sample_threadx.ld file, the .free_mem section should remain the last allocated -section in the main RAM area. The starting address of this section is passed +By default, the first available RAM memory address is assumed to start at the +beginning of the ThreadX section .free_mem. If changes are made to the +sample_threadx.ld file, the .free_mem section should remain the last allocated +section in the main RAM area. The starting address of this section is passed to tx_application_define. @@ -75,7 +75,7 @@ to tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M7 version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -159,21 +159,21 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 7. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make ThreadX run faster, you can change the tx.gpj project -to disable debug information and enable the desired optimizations. +to disable debug information and enable the desired optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined before tx_api.h is included. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. 8. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M7 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: @@ -185,7 +185,7 @@ the vector area according to its needs. 8.2 Managed Interrupts -A ThreadX managed interrupt is defined below. By following these conventions, the +A ThreadX managed interrupt is defined below. By following these conventions, the application ISR is then allowed access to various ThreadX services from the ISR. Here is the standard template for managed ISRs in ThreadX: @@ -194,7 +194,7 @@ Here is the standard template for managed ISRs in ThreadX: __tx_IntHandler: PUSH {lr} BL _tx_thread_context_save - + /* Do interrupt handler work here */ B _tx_thread_context_restore @@ -204,7 +204,7 @@ __tx_IntHandler: By default, FPU support is disabled for each thread. If saving the context of the FPU registers is needed, the ThreadX library should be re-built with TX_ENABLE_FPU_SUPPORT defined. In addition, -the following API call must be made from the context of the application thread - before +the following API call must be made from the context of the application thread - before the FPU usage: void tx_thread_fpu_enable(void); @@ -231,7 +231,7 @@ information associated with this specific port of ThreadX: 03-02-2021 The following files were changed/added for version 6.1.5: tx_thread_schedule.s Added low power feature -05/19/2020 Initial ThreadX version of Cortex-M7/Green Hills port. +05/19/2020 Initial ThreadX version of Cortex-M7/Green Hills port. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_m7/ghs/src/tx_el.c b/ports/cortex_m7/ghs/src/tx_el.c index fd58768f..b5d3b8b7 100644 --- a/ports/cortex_m7/ghs/src/tx_el.c +++ b/ports/cortex_m7/ghs/src/tx_el.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** ThreadX/GHS Event Log (EL) */ /** */ @@ -49,44 +50,38 @@ extern TX_THREAD *_tx_thread_current_ptr; UINT _tx_thread_interrupt_control(UINT new_posture); -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_initialize PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_initialize PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function creates the Event Log (in the format dictated by the */ -/* GHS Event Analyzer) and sets up various information for subsequent */ -/* operation. The start and end of the Event Log is determined by the */ -/* .eventlog section in the linker control file. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function creates the Event Log (in the format dictated by the */ +/* GHS Event Analyzer) and sets up various information for subsequent */ +/* operation. The start and end of the Event Log is determined by the */ +/* .eventlog section in the linker control file. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ VOID _tx_el_initialize(VOID) @@ -150,7 +145,7 @@ UINT i; /* Setup event_ptr (pointer to oldest event) field to the start of the event pool. */ - *_tx_el_current_event = (UCHAR *) (((ULONG) __ghsbegin_eventlog) + TX_EL_HEADER_SIZE + + *_tx_el_current_event = (UCHAR *) (((ULONG) __ghsbegin_eventlog) + TX_EL_HEADER_SIZE + (TX_EL_TNIS * TX_EL_TNI_ENTRY_SIZE)); work_ptr = work_ptr + sizeof(ULONG); @@ -166,17 +161,17 @@ UINT i; /* Clear the entire TNI array, this is the initial setting. */ end_ptr = work_ptr + (TX_EL_TNIS * TX_EL_TNI_ENTRY_SIZE); memset((void *)work_ptr, 0, (TX_EL_TNIS * TX_EL_TNI_ENTRY_SIZE)); - work_ptr = end_ptr; + work_ptr = end_ptr; /* At this point, we are pointing at the actual Event Entry area. */ - + /* Remember the start of the actual event log area. */ _tx_el_event_area_start = work_ptr; /* Clear the entire Event area. */ end_ptr = work_ptr + event_log_size; memset((void *)work_ptr, 0, event_log_size); - work_ptr = end_ptr; + work_ptr = end_ptr; /* Save the end pointer for later use. */ _tx_el_event_area_end = work_ptr; @@ -201,7 +196,7 @@ UINT i; { /* Yes, insert a NULL into the event log string. */ - *work_ptr = (unsigned char) 0; + *work_ptr = (unsigned char) 0; } /* Setup the thread ID to NULL. */ @@ -216,40 +211,40 @@ UINT i; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_thread_register PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_thread_register PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function registers a thread in the event log for future */ +/* */ +/* This function registers a thread in the event log for future */ /* display purposes. */ -/* */ -/* INPUT */ -/* */ -/* thread_ptr Pointer to thread control block */ -/* */ -/* OUTPUT */ -/* */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control block */ +/* */ +/* OUTPUT */ +/* */ /* TX_SUCCESS Thread was placed in TNI area */ /* TX_ERROR No more room in the TNI area */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_thread_create ThreadX thread create function */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create ThreadX thread create function */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -278,7 +273,7 @@ UINT i; i++; entry_ptr = entry_ptr + TX_EL_TNI_ENTRY_SIZE; } - + /* Check to see if there were no more valid entries. */ if (i >= TX_EL_TNIS) return(TX_EL_NO_MORE_TNI_ROOM); @@ -304,7 +299,7 @@ UINT i; { /* Yes, insert a NULL into the event log string. */ - *work_ptr = (unsigned char) 0; + *work_ptr = (unsigned char) 0; } /* Setup the thread ID. */ @@ -321,40 +316,40 @@ UINT i; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_thread_unregister PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_thread_unregister PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function unregisters a thread in the event log for future */ +/* */ +/* This function unregisters a thread in the event log for future */ /* display purposes. */ -/* */ -/* INPUT */ -/* */ -/* thread_ptr Pointer to thread control block */ -/* */ -/* OUTPUT */ -/* */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control block */ +/* */ +/* OUTPUT */ +/* */ /* TX_SUCCESS Thread was placed in TNI area */ /* TX_ERROR No more room in the TNI area */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_thread_create ThreadX thread create function */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create ThreadX thread create function */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -394,7 +389,7 @@ UINT i, j; } else if (*work_ptr == 0) { - + /* Null terminated, just break the loop. */ break; } @@ -426,7 +421,7 @@ UINT i, j; i++; entry_ptr = entry_ptr + TX_EL_TNI_ENTRY_SIZE; } - + /* Determine status to return. */ if (found) return(TX_SUCCESS); @@ -435,49 +430,49 @@ UINT i, j; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_user_event_insert PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_user_event_insert PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ +/* */ /* This function inserts a user event into the event log. */ -/* If the event log is full, the oldest event is overwritten. */ -/* */ -/* INPUT */ -/* */ +/* If the event log is full, the oldest event is overwritten. */ +/* */ +/* INPUT */ +/* */ /* sub_type Event subtype for kernel call */ /* info_1 First information field */ /* info_2 Second information field */ /* info_3 Third information field */ /* info_4 Fourth information field */ /* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* ThreadX services */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX services */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ -VOID _tx_el_user_event_insert(UINT sub_type, ULONG info_1, ULONG info_2, +VOID _tx_el_user_event_insert(UINT sub_type, ULONG info_1, ULONG info_2, ULONG info_3, ULONG info_4) { @@ -545,7 +540,7 @@ UCHAR *entry_ptr; if (entry_ptr >= _tx_el_event_area_end) { - /* Yes, we have wrapped around to the end of the event area. + /* Yes, we have wrapped around to the end of the event area. Start back at the top! */ entry_ptr = _tx_el_event_area_start; } @@ -558,41 +553,41 @@ UCHAR *entry_ptr; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_thread_running PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_thread_running PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ +/* */ /* This function inserts a thread change event into the event */ /* log, which indicates that a context switch is taking place. */ /* If the event log is full, the oldest event is overwritten. */ -/* */ -/* INPUT */ -/* */ +/* */ +/* INPUT */ +/* */ /* thread_ptr Pointer to thread being */ /* scheduled */ /* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_thread_schedule ThreadX scheduler */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_schedule ThreadX scheduler */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -604,7 +599,7 @@ VOID _tx_el_thread_running(TX_THREAD *thread_ptr) UINT upper_tb; UCHAR *entry_ptr; - TX_EL_NO_STATUS_EVENTS + TX_EL_NO_STATUS_EVENTS /* Increment total event counter. */ _tx_el_total_events++; @@ -646,7 +641,7 @@ UCHAR *entry_ptr; if (entry_ptr >= _tx_el_event_area_end) { - /* Yes, we have wrapped around to the end of the event area. + /* Yes, we have wrapped around to the end of the event area. Start back at the top! */ entry_ptr = _tx_el_event_area_start; } @@ -658,43 +653,43 @@ UCHAR *entry_ptr; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_thread_preempted PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_thread_preempted PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ +/* */ /* This function inserts a thread preempted event into the event */ /* log, which indicates that an interrupt occurred that made a higher */ /* priority thread ready for execution. In this case, the previously */ /* executing thread has an event entered to indicate it is no longer */ /* running. */ -/* */ -/* INPUT */ -/* */ +/* */ +/* INPUT */ +/* */ /* thread_ptr Pointer to thread being */ /* scheduled */ /* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_thread_context_restore ThreadX context restore */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_context_restore ThreadX context restore */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -707,7 +702,7 @@ UINT upper_tb; UCHAR *entry_ptr; - TX_EL_NO_STATUS_EVENTS + TX_EL_NO_STATUS_EVENTS /* Increment total event counter. */ _tx_el_total_events++; @@ -749,7 +744,7 @@ UCHAR *entry_ptr; if (entry_ptr >= _tx_el_event_area_end) { - /* Yes, we have wrapped around to the end of the event area. + /* Yes, we have wrapped around to the end of the event area. Start back at the top! */ entry_ptr = _tx_el_event_area_start; } @@ -761,40 +756,40 @@ UCHAR *entry_ptr; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_interrupt PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_interrupt PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ +/* */ /* This function inserts an interrupt event into the log, which */ /* indicates the start of interrupt processing for the specific */ -/* */ -/* INPUT */ -/* */ +/* */ +/* INPUT */ +/* */ /* interrupt_number Interrupt number supplied by */ /* ISR */ /* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* ISR processing */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISR processing */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -807,7 +802,7 @@ UINT upper_tb; UCHAR *entry_ptr; - TX_EL_NO_INTERRUPT_EVENTS + TX_EL_NO_INTERRUPT_EVENTS /* Increment total event counter. */ _tx_el_total_events++; @@ -853,7 +848,7 @@ UCHAR *entry_ptr; if (entry_ptr >= _tx_el_event_area_end) { - /* Yes, we have wrapped around to the end of the event area. + /* Yes, we have wrapped around to the end of the event area. Start back at the top! */ entry_ptr = _tx_el_event_area_start; } @@ -865,40 +860,40 @@ UCHAR *entry_ptr; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_interrupt_end PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_interrupt_end PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ +/* */ /* This function inserts an interrupt end event into the log, which */ /* indicates the end of interrupt processing for the specific */ -/* */ -/* INPUT */ -/* */ +/* */ +/* INPUT */ +/* */ /* interrupt_number Interrupt number supplied by */ /* ISR */ /* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* ISR processing */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISR processing */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -911,7 +906,7 @@ UINT upper_tb; UCHAR *entry_ptr; - TX_EL_NO_INTERRUPT_EVENTS + TX_EL_NO_INTERRUPT_EVENTS /* Increment total event counter. */ _tx_el_total_events++; @@ -957,7 +952,7 @@ UCHAR *entry_ptr; if (entry_ptr >= _tx_el_event_area_end) { - /* Yes, we have wrapped around to the end of the event area. + /* Yes, we have wrapped around to the end of the event area. Start back at the top! */ entry_ptr = _tx_el_event_area_start; } @@ -969,39 +964,39 @@ UCHAR *entry_ptr; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_interrupt_control PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_interrupt_control PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function remaps the tx_interrupt_control service call so that */ -/* it can be tracked in the event log. */ -/* */ -/* INPUT */ -/* */ +/* */ +/* This function remaps the tx_interrupt_control service call so that */ +/* it can be tracked in the event log. */ +/* */ +/* INPUT */ +/* */ /* new_posture New interrupt posture */ /* */ -/* OUTPUT */ -/* */ -/* old_posture Old interrupt posture */ -/* */ -/* CALLS */ -/* */ -/* _tx_thread_interrupt_control Interrupt control service */ -/* */ -/* CALLED BY */ -/* */ -/* ThreadX services */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt posture */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_interrupt_control Interrupt control service */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX services */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -1014,7 +1009,7 @@ TX_INTERRUPT_SAVE_AREA UINT old_posture; - TX_EL_NO_INTERRUPT_EVENTS + TX_EL_NO_INTERRUPT_EVENTS TX_DISABLE TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_INTERRUPT_CONTROL, _tx_thread_current_ptr, new_posture) @@ -1027,38 +1022,38 @@ UINT old_posture; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_event_log_on PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_event_log_on PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function disables all event filters. */ -/* */ -/* INPUT */ -/* */ -/* None */ /* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* This function disables all event filters. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -1072,39 +1067,39 @@ VOID _tx_el_event_log_on(void) } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_event_log_off PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_event_log_off PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function sets all event filters, thereby turning event */ -/* logging off. */ -/* */ -/* INPUT */ -/* */ -/* None */ /* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* This function sets all event filters, thereby turning event */ +/* logging off. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -1118,38 +1113,38 @@ VOID _tx_el_event_log_off(void) } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_el_event_log_set PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_event_log_set PORTABLE C */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function sets the events filters specified by the user. */ -/* */ -/* INPUT */ -/* */ -/* filter Events to filter */ /* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* This function sets the events filters specified by the user. */ +/* */ +/* INPUT */ +/* */ +/* filter Events to filter */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ diff --git a/ports/cortex_m7/ghs/src/tx_ghs.c b/ports/cortex_m7/ghs/src/tx_ghs.c index 0be9d715..30b8054e 100644 --- a/ports/cortex_m7/ghs/src/tx_ghs.c +++ b/ports/cortex_m7/ghs/src/tx_ghs.c @@ -55,7 +55,7 @@ extern TX_THREAD *_tx_thread_current_ptr; If you customize the System Library, you should remove ind_thrd.c from the libsys.gpj subproject. - + */ /* Provide global __eh_globals value to support C++ exception handling diff --git a/ports/cortex_m7/ghs/src/tx_thread_context_restore.arm b/ports/cortex_m7/ghs/src/tx_thread_context_restore.arm index 556e4940..136d2666 100644 --- a/ports/cortex_m7/ghs/src/tx_thread_context_restore.arm +++ b/ports/cortex_m7/ghs/src/tx_thread_context_restore.arm @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; diff --git a/ports/cortex_m7/ghs/src/tx_thread_context_save.arm b/ports/cortex_m7/ghs/src/tx_thread_context_save.arm index edf1ab03..275059e2 100644 --- a/ports/cortex_m7/ghs/src/tx_thread_context_save.arm +++ b/ports/cortex_m7/ghs/src/tx_thread_context_save.arm @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; diff --git a/ports/cortex_m7/ghs/src/tx_thread_interrupt_control.arm b/ports/cortex_m7/ghs/src/tx_thread_interrupt_control.arm index 3d514ab4..2775e088 100644 --- a/ports/cortex_m7/ghs/src/tx_thread_interrupt_control.arm +++ b/ports/cortex_m7/ghs/src/tx_thread_interrupt_control.arm @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; diff --git a/ports/cortex_m7/ghs/src/tx_thread_interrupt_disable.arm b/ports/cortex_m7/ghs/src/tx_thread_interrupt_disable.arm index 1d014f8a..fef336a3 100644 --- a/ports/cortex_m7/ghs/src/tx_thread_interrupt_disable.arm +++ b/ports/cortex_m7/ghs/src/tx_thread_interrupt_disable.arm @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -81,4 +81,4 @@ _tx_thread_interrupt_disable: ; ;} .type _tx_thread_interrupt_disable,$function - .size _tx_thread_interrupt_disable,.-_tx_thread_interrupt_disable + .size _tx_thread_interrupt_disable,.-_tx_thread_interrupt_disable diff --git a/ports/cortex_m7/ghs/src/tx_thread_interrupt_restore.arm b/ports/cortex_m7/ghs/src/tx_thread_interrupt_restore.arm index 55a5289a..1541dd37 100644 --- a/ports/cortex_m7/ghs/src/tx_thread_interrupt_restore.arm +++ b/ports/cortex_m7/ghs/src/tx_thread_interrupt_restore.arm @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -72,4 +72,4 @@ _tx_thread_interrupt_restore: ; ;} .type _tx_thread_interrupt_restore,$function - .size _tx_thread_interrupt_restore,.-_tx_thread_interrupt_restore + .size _tx_thread_interrupt_restore,.-_tx_thread_interrupt_restore diff --git a/ports/cortex_m7/ghs/src/tx_thread_schedule.arm b/ports/cortex_m7/ghs/src/tx_thread_schedule.arm index 3b8aa405..6796f7b4 100644 --- a/ports/cortex_m7/ghs/src/tx_thread_schedule.arm +++ b/ports/cortex_m7/ghs/src/tx_thread_schedule.arm @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -85,7 +85,7 @@ _tx_thread_schedule: ; #ifdef __VFP__ MRS r0, CONTROL ; Pickup current CONTROL register - BIC r0, r0, #4 ; Clear the FPCA bit + BIC r0, r0, #4 ; Clear the FPCA bit MSR CONTROL, r0 ; Setup new CONTROL register #endif ; @@ -118,8 +118,8 @@ PendSV_Handler: __tx_PendSVHandler: ; ; /* Get current thread value and new thread pointer. */ -; -__tx_ts_handler: +; +__tx_ts_handler: #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; @@ -137,7 +137,7 @@ __tx_ts_handler: LDR r1, [r0] ; Pickup current thread pointer ; ; /* Determine if there is a current thread to finish preserving. */ -; +; CBZ r1, __tx_ts_new ; If NULL, skip preservation ; ; /* Recover PSP and preserve current thread context. */ @@ -212,7 +212,7 @@ __tx_ts_restore: LDR.W LR, [r12], #4 ; Pickup LR #ifdef __VFP__ TST LR, #0x10 ; Determine if the VFP extended frame is present - BNE _skip_vfp_restore ; If not, skip VFP restore + BNE _skip_vfp_restore ; If not, skip VFP restore VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers _skip_vfp_restore: #endif @@ -224,7 +224,7 @@ _skip_vfp_restore: BX lr ; Return to thread! ; ; /* The following is the idle wait processing... in this case, no threads are ready for execution and the -; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts ; are disabled to allow use of WFI for waiting for a thread to arrive. */ ; __tx_ts_wait: @@ -254,13 +254,13 @@ __tx_ts_wait: CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; -; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are ; already in the handler! */ ; __tx_ts_ready: MOV r7, #0x08000000 ; Build clear PendSV value MOV r8, #0xE000E000 ; Build base NVIC address - STR r7, [r8, #0xD04] ; Clear any PendSV + STR r7, [r8, #0xD04] ; Clear any PendSV ; ; /* Re-enable interrupts and restore new thread. */ ; @@ -269,14 +269,14 @@ __tx_ts_ready: ;} ; .type __tx_PendSVHandler,$function - .size __tx_PendSVHandler,.-__tx_PendSVHandler + .size __tx_PendSVHandler,.-__tx_PendSVHandler #ifdef __VFP__ .globl tx_thread_fpu_enable tx_thread_fpu_enable: ; -; /* Automatic VPF logic is supported, this function is present only for +; /* Automatic VPF logic is supported, this function is present only for ; backward compatibility purposes and therefore simply returns. */ ; BX LR ; Return to caller @@ -287,12 +287,12 @@ tx_thread_fpu_enable: .global tx_thread_fpu_disable tx_thread_fpu_disable: ; -; /* Automatic VPF logic is supported, this function is present only for +; /* Automatic VPF logic is supported, this function is present only for ; backward compatibility purposes and therefore simply returns. */ ; BX LR ; Return to caller .type tx_thread_fpu_disable,$function - .size tx_thread_fpu_disable,.-tx_thread_fpu_disable + .size tx_thread_fpu_disable,.-tx_thread_fpu_disable #endif diff --git a/ports/cortex_m7/ghs/src/tx_thread_stack_build.arm b/ports/cortex_m7/ghs/src/tx_thread_stack_build.arm index e2f0182e..45c950c8 100644 --- a/ports/cortex_m7/ghs/src/tx_thread_stack_build.arm +++ b/ports/cortex_m7/ghs/src/tx_thread_stack_build.arm @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; diff --git a/ports/cortex_m7/ghs/src/tx_thread_system_return.arm b/ports/cortex_m7/ghs/src/tx_thread_system_return.arm index da4ae3cb..b2c3dd25 100644 --- a/ports/cortex_m7/ghs/src/tx_thread_system_return.arm +++ b/ports/cortex_m7/ghs/src/tx_thread_system_return.arm @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -80,7 +80,7 @@ _tx_thread_system_return: CPSIE i ; Enable interrupts MSR PRIMASK, r1 ; Restore original interrupt posture _isr_context: - BX lr ; Return to caller + BX lr ; Return to caller ;} .type _tx_thread_system_return,$function .size _tx_thread_system_return,.-_tx_thread_system_return diff --git a/ports/cortex_m7/ghs/src/tx_timer_interrupt.arm b/ports/cortex_m7/ghs/src/tx_timer_interrupt.arm index 6a9531fd..451e13dd 100644 --- a/ports/cortex_m7/ghs/src/tx_timer_interrupt.arm +++ b/ports/cortex_m7/ghs/src/tx_timer_interrupt.arm @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -83,7 +83,7 @@ _tx_timer_interrupt: ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CBZ r2, __tx_timer_no_time_slice ; Is it non-active? ; Yes, skip time-slice processing @@ -200,13 +200,13 @@ __tx_timer_dont_activate: ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing LDR r0, =_tx_thread_preempt_disable ; Build address of preempt disable flag diff --git a/ports/cortex_m7/gnu/example_build/cortexm7_crt0.S b/ports/cortex_m7/gnu/example_build/cortexm7_crt0.S index 4228fc11..e06430d7 100644 --- a/ports/cortex_m7/gnu/example_build/cortexm7_crt0.S +++ b/ports/cortex_m7/gnu/example_build/cortexm7_crt0.S @@ -39,7 +39,7 @@ crt0_ctor_loop: beq crt0_ctor_end ldr r2, [r0] add r0, #4 - push {r0-r1} + push {r0-r1} blx r2 pop {r0-r1} b crt0_ctor_loop @@ -88,4 +88,3 @@ memory_set_done: .section .stack, "wa", %nobits .section .stack_process, "wa", %nobits .section .heap, "wa", %nobits - \ No newline at end of file diff --git a/ports/cortex_m7/gnu/example_build/cortexm7_vectors.S b/ports/cortex_m7/gnu/example_build/cortexm7_vectors.S index 6ae558e4..dc8d0aad 100644 --- a/ports/cortex_m7/gnu/example_build/cortexm7_vectors.S +++ b/ports/cortex_m7/gnu/example_build/cortexm7_vectors.S @@ -4,8 +4,8 @@ .global __tx_BadHandler .global __tx_SVCallHandler .global __tx_DBGHandler - .global __tx_PendSVHandler - .global __tx_SysTickHandler + .global __tx_PendSVHandler + .global __tx_SysTickHandler .global __tx_BadHandler .syntax unified @@ -15,9 +15,9 @@ .global _vectors _vectors: - .word __stack_end__ - .word reset_handler - .word __tx_NMIHandler + .word __stack_end__ + .word reset_handler + .word __tx_NMIHandler .word __tx_HardfaultHandler .word __tx_BadHandler .word __tx_BadHandler @@ -29,7 +29,7 @@ _vectors: .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // .word __tx_DBGHandler .word 0 // Reserved - .word __tx_PendSVHandler + .word __tx_PendSVHandler .word __tx_SysTickHandler // Used by Threadx timer functionality .word __tx_BadHandler // Populate with user Interrupt handler .word __tx_BadHandler diff --git a/ports/cortex_m7/gnu/example_build/sample_threadx.c b/ports/cortex_m7/gnu/example_build/sample_threadx.c index 597f373c..13ffadba 100644 --- a/ports/cortex_m7/gnu/example_build/sample_threadx.c +++ b/ports/cortex_m7/gnu/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -81,42 +81,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -124,23 +124,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -243,11 +243,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -306,7 +306,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -359,7 +359,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_m7/gnu/example_build/sample_threadx.ld b/ports/cortex_m7/gnu/example_build/sample_threadx.ld index c65a1346..3f19c29e 100644 --- a/ports/cortex_m7/gnu/example_build/sample_threadx.ld +++ b/ports/cortex_m7/gnu/example_build/sample_threadx.ld @@ -10,7 +10,7 @@ __HEAPSIZE__ = 128; SECTIONS { - .vectors : + .vectors : { KEEP(*(.vectors .vectors.*)) } > FLASH @@ -45,7 +45,7 @@ SECTIONS KEEP(*(.eh_frame*)) } > FLASH - .ARM.extab : + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH @@ -59,7 +59,7 @@ SECTIONS __data_load_start__ = ALIGN (4); - .data : AT (__data_load_start__) + .data : AT (__data_load_start__) { __data_start__ = .; @@ -89,7 +89,7 @@ SECTIONS KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ - + __data_end__ = .; } > RAM @@ -104,7 +104,7 @@ SECTIONS __bss_end__ = .; } > RAM - + .heap (COPY): { __heap_start__ = ALIGN(4); diff --git a/ports/cortex_m7/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_m7/gnu/example_build/tx_initialize_low_level.S index 5aaaaad3..e146e47f 100644 --- a/ports/cortex_m7/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m7/gnu/example_build/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,16 +73,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 William E. Lamie Modified Comment(s), fixed */ -/* GNU assembly comment, clean */ -/* up whitespace, resulting */ -/* in version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports/cortex_m7/gnu/inc/tx_port.h b/ports/cortex_m7/gnu/inc/tx_port.h index 55157def..48a34cfa 100644 --- a/ports/cortex_m7/gnu/inc/tx_port.h +++ b/ports/cortex_m7/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,23 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comments, updated */ -/* typedef to fix misra */ -/* violation, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -371,7 +355,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -530,7 +514,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #endif @@ -715,7 +699,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M7/GNU Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7/GNU Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m7/gnu/readme_threadx.txt b/ports/cortex_m7/gnu/readme_threadx.txt index d9063d65..58181f85 100644 --- a/ports/cortex_m7/gnu/readme_threadx.txt +++ b/ports/cortex_m7/gnu/readme_threadx.txt @@ -5,15 +5,15 @@ 1. Building the ThreadX run-time Library -Navigate to the "example_build" directory. Ensure that -you have setup your path and other environment variables necessary for the ARM -GNU compiler. At this point you may run the build_threadx.bat batch file. -This will build the ThreadX run-time environment in the "example_build" -directory. +Navigate to the "example_build" directory. Ensure that +you have setup your path and other environment variables necessary for the ARM +GNU compiler. At this point you may run the build_threadx.bat batch file. +This will build the ThreadX run-time environment in the "example_build" +directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. @@ -22,25 +22,25 @@ application in order to use ThreadX. The ThreadX demonstration is designed to execute on Cortex-M evaluation boards or on a dedicated simulator. -Building the demonstration is easy, simply execute the build_threadx_sample.bat +Building the demonstration is easy, simply execute the build_threadx_sample.bat batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with tx.a. The resulting file sample_threadx.out is a binary +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.out is a binary file that can be downloaded and executed on the a simulator, or downloaded to a board. 3. System Initialization -The entry point in ThreadX for the Cortex-M using gnu tools uses the standard GNU +The entry point in ThreadX for the Cortex-M using gnu tools uses the standard GNU Cortex-M reset sequence. From the reset vector the C runtime will be initialized. -The ThreadX tx_initialize_low_level.S file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. +The ThreadX tx_initialize_low_level.S file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. @@ -49,7 +49,7 @@ parameter to your application definition function, tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -132,34 +132,34 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 5. Improving Performance -The distribution version of ThreadX is built without any compiler optimizations. -This makes it easy to debug because you can trace or set breakpoints inside of -ThreadX itself. Of course, this costs some performance. To make it run faster, -you can change the build_threadx.bat file to remove the -g option and enable -all compiler optimizations. +The distribution version of ThreadX is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX itself. Of course, this costs some performance. To make it run faster, +you can change the build_threadx.bat file to remove the -g option and enable +all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 6.1 Vector Area The Cortex-M vectors start at the label __tx_vectors or similar. The application may modify -the vector area according to its needs. There is code in tx_initialize_low_level() that will -configure the vector base register. +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. 6.2 Managed Interrupts -A ThreadX managed interrupt is defined below. By following these conventions, the +A ThreadX managed interrupt is defined below. By following these conventions, the application ISR is then allowed access to various ThreadX services from the ISR. Here is the standard template for managed ISRs in ThreadX: @@ -181,15 +181,15 @@ __tx_IntHandler: Note: the Cortex-M requires exception handlers to be thumb labels, this implies bit 0 set. To accomplish this, the declaration of the label has to be preceded by the assembler directive -.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to -be inserted in the correct location in the interrupt vector table. This table is typically +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically located in either your runtime startup file or in the tx_initialize_low_level.S file. 7. FPU Support -ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context - no additional setup by the application. diff --git a/ports/cortex_m7/gnu/src/tx_misra.S b/ports/cortex_m7/gnu/src/tx_misra.S index 8ac0c629..10548671 100644 --- a/ports/cortex_m7/gnu/src/tx_misra.S +++ b/ports/cortex_m7/gnu/src/tx_misra.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -667,7 +668,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -682,7 +683,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARM_FP /***********************************************************************************************/ @@ -699,8 +700,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -714,9 +715,9 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - + .data .word 0 diff --git a/ports/cortex_m7/gnu/src/tx_thread_context_restore.S b/ports/cortex_m7/gnu/src/tx_thread_context_restore.S index 57b18cf6..63895928 100644 --- a/ports/cortex_m7/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m7/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_m7/gnu/src/tx_thread_context_save.S b/ports/cortex_m7/gnu/src/tx_thread_context_save.S index d118c5bd..96df9ac5 100644 --- a/ports/cortex_m7/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m7/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S index 62301c14..5778d8d4 100644 --- a/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_m7/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_m7/gnu/src/tx_thread_interrupt_disable.S index f74a3748..19f6f854 100644 --- a/ports/cortex_m7/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m7/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports/cortex_m7/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_m7/gnu/src/tx_thread_interrupt_restore.S index f4be7eba..25f1aac3 100644 --- a/ports/cortex_m7/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m7/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports/cortex_m7/gnu/src/tx_thread_schedule.S b/ports/cortex_m7/gnu/src/tx_thread_schedule.S index e2743401..6700fd97 100644 --- a/ports/cortex_m7/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m7/gnu/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,18 +69,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Fixed predefined macro name, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_m7/gnu/src/tx_thread_stack_build.S b/ports/cortex_m7/gnu/src/tx_thread_stack_build.S index 0c72a44f..d0e2eaf3 100644 --- a/ports/cortex_m7/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m7/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_m7/gnu/src/tx_thread_system_return.S b/ports/cortex_m7/gnu/src/tx_thread_system_return.S index 4987b047..ce5a3f46 100644 --- a/ports/cortex_m7/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m7/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_m7/gnu/src/tx_timer_interrupt.S b/ports/cortex_m7/gnu/src/tx_timer_interrupt.S index d9477dea..6cc18b25 100644 --- a/ports/cortex_m7/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_m7/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,17 +71,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_m7/iar/CMakeLists.txt b/ports/cortex_m7/iar/CMakeLists.txt index a524d79f..57be3aeb 100644 --- a/ports/cortex_m7/iar/CMakeLists.txt +++ b/ports/cortex_m7/iar/CMakeLists.txt @@ -7,7 +7,7 @@ target_sources(${PROJECT_NAME} ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_disable.S - ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_restore.S + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_restore.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S diff --git a/ports/cortex_m7/iar/example_build/cstartup_M.s b/ports/cortex_m7/iar/example_build/cstartup_M.s index 75d9369b..d1c5aa3e 100644 --- a/ports/cortex_m7/iar/example_build/cstartup_M.s +++ b/ports/cortex_m7/iar/example_build/cstartup_M.s @@ -2,16 +2,16 @@ PUBLIC __vector_table SECTION .text:CODE:REORDER(1) - + ;; Keep vector table even if it's not referenced REQUIRE __vector_table - + THUMB - + ;; Forward declaration of sections. SECTION CSTACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) - + DATA __vector_table diff --git a/ports/cortex_m7/iar/example_build/sample_threadx.c b/ports/cortex_m7/iar/example_build/sample_threadx.c index 9a626828..f1f4cb87 100644 --- a/ports/cortex_m7/iar/example_build/sample_threadx.c +++ b/ports/cortex_m7/iar/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete description of this demonstration. */ @@ -65,7 +65,7 @@ void thread_6_and_7_entry(ULONG thread_input); int main() { - + /* Please refer to Chapter 6 of the ThreadX User Guide for a complete description of this demonstration. */ @@ -93,41 +93,41 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -135,23 +135,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -254,11 +254,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -317,7 +317,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -370,7 +370,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_m7/iar/example_build/tx_initialize_low_level.s b/ports/cortex_m7/iar/example_build/tx_initialize_low_level.s index b725ef99..76d065cf 100644 --- a/ports/cortex_m7/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m7/iar/example_build/tx_initialize_low_level.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -73,12 +73,6 @@ __tx_free_memory_start ;/* */ ;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) ;{ diff --git a/ports/cortex_m7/iar/inc/tx_port.h b/ports/cortex_m7/iar/inc/tx_port.h index a2d0526f..63d821bf 100644 --- a/ports/cortex_m7/iar/inc/tx_port.h +++ b/ports/cortex_m7/iar/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,23 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comments, updated */ -/* typedef to fix misra */ -/* violation, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -371,7 +355,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -530,7 +514,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #endif @@ -715,7 +699,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M7/IAR Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7/IAR Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m7/iar/readme_threadx.txt b/ports/cortex_m7/iar/readme_threadx.txt index 28b54e03..388c40e6 100644 --- a/ports/cortex_m7/iar/readme_threadx.txt +++ b/ports/cortex_m7/iar/readme_threadx.txt @@ -6,45 +6,45 @@ 1. Building the ThreadX run-time Library Building the ThreadX library is easy. First, open the Azure RTOS workspace -azure_rtos.eww. Next, make the TX project the "active project" in the -IAR Embedded Workbench and select the "Make" button. You should observe -assembly and compilation of a series of ThreadX source files. This -results in the ThreadX run-time library file tx.a, which is needed by +azure_rtos.eww. Next, make the TX project the "active project" in the +IAR Embedded Workbench and select the "Make" button. You should observe +assembly and compilation of a series of ThreadX source files. This +results in the ThreadX run-time library file tx.a, which is needed by the application. 2. Demonstration System -The ThreadX demonstration is designed to execute under the IAR debugger under +The ThreadX demonstration is designed to execute under the IAR debugger under simulation. Building the demonstration is easy; simply open the threadx.www workspace file, -make the sample_threadx.ewp project the "active project" in the IAR Embedded +make the sample_threadx.ewp project the "active project" in the IAR Embedded Workbench, and select the "Make" button. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with tx.a. The resulting file sample_threadx.out is a -binary ELF file that can be downloaded and executed on the IAR Windows-based +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.out is a +binary ELF file that can be downloaded and executed on the IAR Windows-based Cortex-M simulator. 3. System Initialization -The entry point in ThreadX for the Cortex-M using IAR tools is at label -__iar_program_start. This is defined within the IAR compiler's startup code. -In addition, this is where all static and global preset C variable +The entry point in ThreadX for the Cortex-M using IAR tools is at label +__iar_program_start. This is defined within the IAR compiler's startup code. +In addition, this is where all static and global preset C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, and a periodic timer interrupt source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. By default, the vector area is defined at the top of cstartup_M.s, which is -a slightly modified from the base IAR file. +a slightly modified from the base IAR file. The _tx_initialize_low_level function inside of tx_initialize_low_level.s -also determines the first available address for use by the application, which -is supplied as the sole input parameter to your application definition function, -tx_application_define. To accomplish this, a section is created in -tx_initialize_low_level.s called FREE_MEM, which must be located after all +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all other RAM sections in memory. @@ -53,7 +53,7 @@ other RAM sections in memory. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -136,20 +136,20 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 5. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the ThreadX library project to enable various compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling -The Cortex-M vectors start at the label __vector_table and is defined in cstartup_M.s. +The Cortex-M vectors start at the label __vector_table and is defined in cstartup_M.s. The application may modify the vector area according to its needs. @@ -188,14 +188,14 @@ should have the following line added (if not already in place): initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application -The project options "General Options -> Library Configuration" should also have the +The project options "General Options -> Library Configuration" should also have the "Enable thread support in library" box selected. 8. VFP Support -ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context - no additional setup by the application. diff --git a/ports/cortex_m7/iar/src/tx_iar.c b/ports/cortex_m7/iar/src/tx_iar.c index ee47f10f..238b485e 100644 --- a/ports/cortex_m7/iar/src/tx_iar.c +++ b/ports/cortex_m7/iar/src/tx_iar.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports/cortex_m7/iar/src/tx_misra.s b/ports/cortex_m7/iar/src/tx_misra.s index f86d9a65..642bb89e 100644 --- a/ports/cortex_m7/iar/src/tx_misra.s +++ b/ports/cortex_m7/iar/src/tx_misra.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -120,7 +121,7 @@ SECTION `.data`:DATA:REORDER:NOROOT(2) DATA -// 51 CHAR _tx_version_id[100] = "Copyright (c) 2024 Microsoft Corporation. * ThreadX 6.1 MISRA C Compliant *"; +// 51 CHAR _tx_version_id[100] = "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX 6.1 MISRA C Compliant *"; _tx_version_id: DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H @@ -707,7 +708,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -722,7 +723,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARMVFP__ /***********************************************************************************************/ @@ -739,8 +740,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -754,10 +755,10 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - - + + SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2) SECTION_TYPE SHT_PROGBITS, 0 DATA diff --git a/ports/cortex_m7/iar/src/tx_thread_context_restore.s b/ports/cortex_m7/iar/src/tx_thread_context_restore.s index 52c33328..ccc96ede 100644 --- a/ports/cortex_m7/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_m7/iar/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_m7/iar/src/tx_thread_context_save.s b/ports/cortex_m7/iar/src/tx_thread_context_save.s index f3bca66a..dcf510a6 100644 --- a/ports/cortex_m7/iar/src/tx_thread_context_save.s +++ b/ports/cortex_m7/iar/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_m7/iar/src/tx_thread_interrupt_control.s b/ports/cortex_m7/iar/src/tx_thread_interrupt_control.s index 8950acd5..f28d5bde 100644 --- a/ports/cortex_m7/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m7/iar/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_m7/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m7/iar/src/tx_thread_interrupt_disable.s index 76e09a1c..36aaaf0a 100644 --- a/ports/cortex_m7/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m7/iar/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports/cortex_m7/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_m7/iar/src/tx_thread_interrupt_restore.s index 57102c6d..55aa1d62 100644 --- a/ports/cortex_m7/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m7/iar/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports/cortex_m7/iar/src/tx_thread_schedule.s b/ports/cortex_m7/iar/src/tx_thread_schedule.s index 7125056b..58279c1a 100644 --- a/ports/cortex_m7/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m7/iar/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,17 +68,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 04-25-2022 Scott Larson Added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports/cortex_m7/iar/src/tx_thread_stack_build.s b/ports/cortex_m7/iar/src/tx_thread_stack_build.s index 04b1479c..2f7ac3ab 100644 --- a/ports/cortex_m7/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_m7/iar/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_m7/iar/src/tx_thread_system_return.s b/ports/cortex_m7/iar/src/tx_thread_system_return.s index 51c85491..0cef80c6 100644 --- a/ports/cortex_m7/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m7/iar/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_m7/iar/src/tx_timer_interrupt.s b/ports/cortex_m7/iar/src/tx_timer_interrupt.s index 1da9431e..775c0a45 100644 --- a/ports/cortex_m7/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_m7/iar/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,18 +72,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_m85/ac6/inc/tx_port.h b/ports/cortex_m85/ac6/inc/tx_port.h index 2eb69f38..7e119fee 100644 --- a/ports/cortex_m85/ac6/inc/tx_port.h +++ b/ports/cortex_m85/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,39 +46,6 @@ /* This file replaces the previous Cortex-M85 files. It unifies */ /* the Cortex-M85 compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-02-2021 Scott Larson Modified comment(s), added */ -/* ULONG64_DEFINED, */ -/* resulting in version 6.1.5 */ -/* 06-02-2021 Scott Larson Modified comment(s), removed */ -/* unneeded header file, funcs */ -/* set_control and get_control */ -/* changed to inline, */ -/* added symbol to enable */ -/* stack error handler, */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ -/* stack check error handling, */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), unified */ -/* this file across compilers, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* 03-08-2023 Scott Larson Removed unneeded #include, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -645,7 +613,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M85/AC6 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M85/AC6 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m85/ac6/inc/tx_secure_interface.h b/ports/cortex_m85/ac6/inc/tx_secure_interface.h index 39b5d5fd..5ac37fbf 100644 --- a/ports/cortex_m85/ac6/inc/tx_secure_interface.h +++ b/ports/cortex_m85/ac6/inc/tx_secure_interface.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,12 +38,6 @@ /* It is assumed that tx_api.h and tx_port.h have already been */ /* included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_SECURE_INTERFACE_H diff --git a/ports/cortex_m85/ac6/readme_threadx.txt b/ports/cortex_m85/ac6/readme_threadx.txt index dda0c1c4..abe80bf8 100644 --- a/ports/cortex_m85/ac6/readme_threadx.txt +++ b/ports/cortex_m85/ac6/readme_threadx.txt @@ -1,46 +1,46 @@ - Microsoft's Azure RTOS ThreadX for Cortex-M85 + Microsoft's Azure RTOS ThreadX for Cortex-M85 Using the AC6 Tools in Keil uVision 1. Import the ThreadX Projects -In order to build the ThreadX library and the ThreadX demonstration, first open -the AzureRTOS.uvmpw workspace (located in the "example_build" directory) +In order to build the ThreadX library and the ThreadX demonstration, first open +the AzureRTOS.uvmpw workspace (located in the "example_build" directory) into Keil. 2. Building the ThreadX run-time Library Building the ThreadX library is easy; simply set the ThreadX_Library project -as active, then then build the library. You should now observe the compilation +as active, then then build the library. You should now observe the compilation and assembly of the ThreadX library. This project build produces the ThreadX library file ThreadX_Library.lib. -Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c -replace the common files of the same name. +Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c +replace the common files of the same name. 3. Demonstration System The ThreadX demonstration is designed to execute under the Keil debugger on the FVP_MPS2_Cortex-M85_MDK simulator. -Building the demonstration is easy; simply select the "Batch Build" button. -You should now observe the compilation and assembly of the ThreadX demonstration of -both the demo_secure_zone and demo_threadx_non-secure_zone projects. +Building the demonstration is easy; simply select the "Batch Build" button. +You should now observe the compilation and assembly of the ThreadX demonstration of +both the demo_secure_zone and demo_threadx_non-secure_zone projects. Then click the Start/Stop Debug Session button to start the simulator and begin debugging. You are now ready to execute the ThreadX demonstration. 4. System Initialization -The entry point in ThreadX for the Cortex-M85 using AC6 tools uses the standard AC6 +The entry point in ThreadX for the Cortex-M85 using AC6 tools uses the standard AC6 Cortex-M85 reset sequence. From the reset vector the C runtime will be initialized. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. @@ -49,7 +49,7 @@ parameter to your application definition function, tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M85 version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -132,26 +132,26 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 6. Improving Performance -To make ThreadX and the application(s) run faster, you can enable -all compiler optimizations. +To make ThreadX and the application(s) run faster, you can enable +all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M85 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-M85 vectors start at the label __Vectors or similar. The application may modify -the vector area according to its needs. There is code in tx_initialize_low_level() that will -configure the vector base register. +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. 7.2 Managed Interrupts @@ -177,7 +177,7 @@ your_assembly_isr: ; VOID your_assembly_isr(VOID) ; { PUSH {r0, lr} -; +; ; /* Do interrupt handler work here */ ; /* BL */ @@ -187,15 +187,15 @@ your_assembly_isr: Note: the Cortex-M85 requires exception handlers to be thumb labels, this implies bit 0 set. To accomplish this, the declaration of the label has to be preceded by the assembler directive -.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to -be inserted in the correct location in the interrupt vector table. This table is typically +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically located in either your runtime startup file or in the tx_initialize_low_level.s file. 8. FPU Support -ThreadX for Cortex-M85 supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-M85 supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context. diff --git a/ports/cortex_m85/ac6/src/tx_initialize_low_level.S b/ports/cortex_m85/ac6/src/tx_initialize_low_level.S index fca21594..a3daea70 100644 --- a/ports/cortex_m85/ac6/src/tx_initialize_low_level.S +++ b/ports/cortex_m85/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ HEAP_SIZE = 0x00000000 /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports/cortex_m85/ac6/src/tx_misra.S b/ports/cortex_m85/ac6/src/tx_misra.S index 8ac0c629..10548671 100644 --- a/ports/cortex_m85/ac6/src/tx_misra.S +++ b/ports/cortex_m85/ac6/src/tx_misra.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -667,7 +668,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -682,7 +683,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARM_FP /***********************************************************************************************/ @@ -699,8 +700,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -714,9 +715,9 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - + .data .word 0 diff --git a/ports/cortex_m85/ac6/src/tx_thread_context_restore.S b/ports/cortex_m85/ac6/src/tx_thread_context_restore.S index 6320f475..5c5a6b25 100644 --- a/ports/cortex_m85/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m85/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_m85/ac6/src/tx_thread_context_save.S b/ports/cortex_m85/ac6/src/tx_thread_context_save.S index d5911b43..46a1bda7 100644 --- a/ports/cortex_m85/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m85/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_m85/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m85/ac6/src/tx_thread_interrupt_control.S index 13256055..43483a79 100644 --- a/ports/cortex_m85/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m85/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_m85/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_m85/ac6/src/tx_thread_interrupt_disable.S index b14623a6..e0d27e80 100644 --- a/ports/cortex_m85/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m85/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports/cortex_m85/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_m85/ac6/src/tx_thread_interrupt_restore.S index ffe8649f..a844935d 100644 --- a/ports/cortex_m85/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m85/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports/cortex_m85/ac6/src/tx_thread_schedule.S b/ports/cortex_m85/ac6/src/tx_thread_schedule.S index 202860ad..62412fff 100644 --- a/ports/cortex_m85/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m85/ac6/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,23 +61,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 04-02-2021 Scott Larson Modified comment(s), added */ -/* low power code, */ -/* resulting in version 6.1.6 */ -/* 06-02-2021 Scott Larson Added secure stack initialize */ -/* in SVC handler, */ -/* resulting in version 6.1.7 */ -/* 04-25-2022 Scott Larson Added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 03-08-2023 Scott Larson Added preproc FPU option, */ -/* included tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -354,7 +338,7 @@ SVC_Handler: CMP r1, #2 // Is it a secure stack free request? BEQ _tx_svc_secure_free // Yes, go there - + CMP r1, #3 // Is it a secure stack init request? BEQ _tx_svc_secure_init // Yes, go there diff --git a/ports/cortex_m85/ac6/src/tx_thread_secure_stack.c b/ports/cortex_m85/ac6/src/tx_thread_secure_stack.c index 46ac71d3..f3582653 100644 --- a/ports/cortex_m85/ac6/src/tx_thread_secure_stack.c +++ b/ports/cortex_m85/ac6/src/tx_thread_secure_stack.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -102,21 +103,6 @@ static INT tx_head_free_index = 0U; /* */ /* _tx_initialize_kernel_enter */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-16-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.1 */ -/* 06-02-2021 Scott Larson Modified comment(s), and */ -/* changed name, execute in */ -/* handler mode, */ -/* resulting in version 6.1.7 */ -/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ -/* secure stack allocation, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_initialize(void) diff --git a/ports/cortex_m85/ac6/src/tx_thread_secure_stack_allocate.S b/ports/cortex_m85/ac6/src/tx_thread_secure_stack_allocate.S index 99215d59..6ecda22d 100644 --- a/ports/cortex_m85/ac6/src/tx_thread_secure_stack_allocate.S +++ b/ports/cortex_m85/ac6/src/tx_thread_secure_stack_allocate.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,14 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) // { diff --git a/ports/cortex_m85/ac6/src/tx_thread_secure_stack_free.S b/ports/cortex_m85/ac6/src/tx_thread_secure_stack_free.S index 441c2100..9a9d6555 100644 --- a/ports/cortex_m85/ac6/src/tx_thread_secure_stack_free.S +++ b/ports/cortex_m85/ac6/src/tx_thread_secure_stack_free.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) // { diff --git a/ports/cortex_m85/ac6/src/tx_thread_secure_stack_initialize.S b/ports/cortex_m85/ac6/src/tx_thread_secure_stack_initialize.S index 08b2ada0..01abe965 100644 --- a/ports/cortex_m85/ac6/src/tx_thread_secure_stack_initialize.S +++ b/ports/cortex_m85/ac6/src/tx_thread_secure_stack_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,18 +54,6 @@ /* */ /* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) // { diff --git a/ports/cortex_m85/ac6/src/tx_thread_stack_build.S b/ports/cortex_m85/ac6/src/tx_thread_stack_build.S index 6e3fe5e9..10ed7c6a 100644 --- a/ports/cortex_m85/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_m85/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_m85/ac6/src/tx_thread_system_return.S b/ports/cortex_m85/ac6/src/tx_thread_system_return.S index 9290a621..2b335f8d 100644 --- a/ports/cortex_m85/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m85/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_m85/ac6/src/tx_timer_interrupt.S b/ports/cortex_m85/ac6/src/tx_timer_interrupt.S index 36266e85..8e2af8bd 100644 --- a/ports/cortex_m85/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_m85/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_m85/ac6/src/txe_thread_secure_stack_allocate.c b/ports/cortex_m85/ac6/src/txe_thread_secure_stack_allocate.c index 17cc9f53..43b4db08 100644 --- a/ports/cortex_m85/ac6/src/txe_thread_secure_stack_allocate.c +++ b/ports/cortex_m85/ac6/src/txe_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { @@ -76,10 +71,10 @@ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_siz return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports/cortex_m85/ac6/src/txe_thread_secure_stack_free.c b/ports/cortex_m85/ac6/src/txe_thread_secure_stack_free.c index a41b1c24..d6431134 100644 --- a/ports/cortex_m85/ac6/src/txe_thread_secure_stack_free.c +++ b/ports/cortex_m85/ac6/src/txe_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { @@ -74,10 +69,10 @@ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports/cortex_m85/gnu/inc/tx_port.h b/ports/cortex_m85/gnu/inc/tx_port.h index 0590434f..9057a132 100644 --- a/ports/cortex_m85/gnu/inc/tx_port.h +++ b/ports/cortex_m85/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,39 +46,6 @@ /* This file replaces the previous Cortex-M85 files. It unifies */ /* the Cortex-M85 compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-02-2021 Scott Larson Modified comment(s), added */ -/* ULONG64_DEFINED, */ -/* resulting in version 6.1.5 */ -/* 06-02-2021 Scott Larson Modified comment(s), removed */ -/* unneeded header file, funcs */ -/* set_control and get_control */ -/* changed to inline, */ -/* added symbol to enable */ -/* stack error handler, */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ -/* stack check error handling, */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), unified */ -/* this file across compilers, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* 03-08-2023 Scott Larson Removed unneeded #include, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -645,7 +613,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M85/GNU Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M85/GNU Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m85/gnu/inc/tx_secure_interface.h b/ports/cortex_m85/gnu/inc/tx_secure_interface.h index 39b5d5fd..5ac37fbf 100644 --- a/ports/cortex_m85/gnu/inc/tx_secure_interface.h +++ b/ports/cortex_m85/gnu/inc/tx_secure_interface.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,12 +38,6 @@ /* It is assumed that tx_api.h and tx_port.h have already been */ /* included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_SECURE_INTERFACE_H diff --git a/ports/cortex_m85/gnu/readme_threadx.txt b/ports/cortex_m85/gnu/readme_threadx.txt index e38d20ee..d497b037 100644 --- a/ports/cortex_m85/gnu/readme_threadx.txt +++ b/ports/cortex_m85/gnu/readme_threadx.txt @@ -1,32 +1,32 @@ - Microsoft's Azure RTOS ThreadX for Cortex-M85 + Microsoft's Azure RTOS ThreadX for Cortex-M85 Using the GNU Tools 1. Building the ThreadX run-time Library Import all ThreadX common and port-specific source files into a GNU project. -Configure the project to build a library rather than an executable. This -results in the ThreadX run-time library file tx.a, which is needed by +Configure the project to build a library rather than an executable. This +results in the ThreadX run-time library file tx.a, which is needed by the application. -Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c -replace the common files of the same name. +Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c +replace the common files of the same name. 2. Demonstration System -No demonstration project is provided. +No demonstration project is provided. 3. System Initialization -The entry point in ThreadX for the Cortex-M85 using gnu tools uses the standard GNU +The entry point in ThreadX for the Cortex-M85 using gnu tools uses the standard GNU Cortex-M85 reset sequence. From the reset vector the C runtime will be initialized. -The ThreadX tx_initialize_low_level.S file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. +The ThreadX tx_initialize_low_level.S file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. @@ -35,7 +35,7 @@ parameter to your application definition function, tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M85 version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -118,26 +118,26 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 5. Improving Performance -To make ThreadX and the application(s) run faster, you can enable -all compiler optimizations. +To make ThreadX and the application(s) run faster, you can enable +all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M85 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 6.1 Vector Area The Cortex-M85 vectors start at the label __tx_vectors or similar. The application may modify -the vector area according to its needs. There is code in tx_initialize_low_level() that will -configure the vector base register. +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. 6.2 Managed Interrupts @@ -170,15 +170,15 @@ your_assembly_isr: Note: the Cortex-M85 requires exception handlers to be thumb labels, this implies bit 0 set. To accomplish this, the declaration of the label has to be preceded by the assembler directive -.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to -be inserted in the correct location in the interrupt vector table. This table is typically +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically located in either your runtime startup file or in the tx_initialize_low_level.S file. 7. FPU Support -ThreadX for Cortex-M85 supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-M85 supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context. diff --git a/ports/cortex_m85/gnu/src/tx_initialize_low_level.S b/ports/cortex_m85/gnu/src/tx_initialize_low_level.S index e34d1d6f..22dc0780 100644 --- a/ports/cortex_m85/gnu/src/tx_initialize_low_level.S +++ b/ports/cortex_m85/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,16 +66,6 @@ HEAP_SIZE = 0x00000000 /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Fixed predefined macro name, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports/cortex_m85/gnu/src/tx_misra.S b/ports/cortex_m85/gnu/src/tx_misra.S index 8ac0c629..10548671 100644 --- a/ports/cortex_m85/gnu/src/tx_misra.S +++ b/ports/cortex_m85/gnu/src/tx_misra.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -667,7 +668,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -682,7 +683,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARM_FP /***********************************************************************************************/ @@ -699,8 +700,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -714,9 +715,9 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - + .data .word 0 diff --git a/ports/cortex_m85/gnu/src/tx_thread_context_restore.S b/ports/cortex_m85/gnu/src/tx_thread_context_restore.S index 56c06886..6daf837e 100644 --- a/ports/cortex_m85/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m85/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_m85/gnu/src/tx_thread_context_save.S b/ports/cortex_m85/gnu/src/tx_thread_context_save.S index e6bf9501..8af9fbb1 100644 --- a/ports/cortex_m85/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m85/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_m85/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m85/gnu/src/tx_thread_interrupt_control.S index acf05310..431c2e38 100644 --- a/ports/cortex_m85/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m85/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_m85/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_m85/gnu/src/tx_thread_interrupt_disable.S index 092c3b55..e734b6f4 100644 --- a/ports/cortex_m85/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m85/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports/cortex_m85/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_m85/gnu/src/tx_thread_interrupt_restore.S index 34530d70..9e874eca 100644 --- a/ports/cortex_m85/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m85/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports/cortex_m85/gnu/src/tx_thread_schedule.S b/ports/cortex_m85/gnu/src/tx_thread_schedule.S index 91a60319..f46f5737 100644 --- a/ports/cortex_m85/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m85/gnu/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,24 +57,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 04-02-2021 Scott Larson Modified comment(s), added */ -/* low power code, */ -/* resulting in version 6.1.6 */ -/* 06-02-2021 Scott Larson Added secure stack initialize */ -/* in SVC handler, */ -/* resulting in version 6.1.7 */ -/* 01-31-2022 Scott Larson Fixed predefined macro name, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -351,7 +334,7 @@ SVC_Handler: CMP r1, #2 // Is it a secure stack free request? BEQ _tx_svc_secure_free // Yes, go there - + CMP r1, #3 // Is it a secure stack init request? BEQ _tx_svc_secure_init // Yes, go there diff --git a/ports/cortex_m85/gnu/src/tx_thread_secure_stack.c b/ports/cortex_m85/gnu/src/tx_thread_secure_stack.c index 51a93e18..0d0cf1a3 100644 --- a/ports/cortex_m85/gnu/src/tx_thread_secure_stack.c +++ b/ports/cortex_m85/gnu/src/tx_thread_secure_stack.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -98,21 +99,6 @@ static INT tx_head_free_index = 0U; /* */ /* _tx_initialize_kernel_enter */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-16-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.1 */ -/* 06-02-2021 Scott Larson Change name, execute in */ -/* handler mode, */ -/* disable optimizations, */ -/* resulting in version 6.1.7 */ -/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ -/* secure stack allocation, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry, optimize(0))) UINT _tx_thread_secure_mode_stack_initialize(void) diff --git a/ports/cortex_m85/gnu/src/tx_thread_secure_stack_allocate.S b/ports/cortex_m85/gnu/src/tx_thread_secure_stack_allocate.S index 907cb845..02e27a3c 100644 --- a/ports/cortex_m85/gnu/src/tx_thread_secure_stack_allocate.S +++ b/ports/cortex_m85/gnu/src/tx_thread_secure_stack_allocate.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,14 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) // { diff --git a/ports/cortex_m85/gnu/src/tx_thread_secure_stack_free.S b/ports/cortex_m85/gnu/src/tx_thread_secure_stack_free.S index a7ebdd53..da5a2520 100644 --- a/ports/cortex_m85/gnu/src/tx_thread_secure_stack_free.S +++ b/ports/cortex_m85/gnu/src/tx_thread_secure_stack_free.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) // { diff --git a/ports/cortex_m85/gnu/src/tx_thread_secure_stack_initialize.S b/ports/cortex_m85/gnu/src/tx_thread_secure_stack_initialize.S index fcf88b53..3f17fc59 100644 --- a/ports/cortex_m85/gnu/src/tx_thread_secure_stack_initialize.S +++ b/ports/cortex_m85/gnu/src/tx_thread_secure_stack_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,18 +54,6 @@ /* */ /* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) // { diff --git a/ports/cortex_m85/gnu/src/tx_thread_stack_build.S b/ports/cortex_m85/gnu/src/tx_thread_stack_build.S index 17f0fe26..b22d0830 100644 --- a/ports/cortex_m85/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m85/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_m85/gnu/src/tx_thread_system_return.S b/ports/cortex_m85/gnu/src/tx_thread_system_return.S index a2b94618..bbb5a630 100644 --- a/ports/cortex_m85/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m85/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_m85/gnu/src/tx_timer_interrupt.S b/ports/cortex_m85/gnu/src/tx_timer_interrupt.S index 21ab9f63..0113be17 100644 --- a/ports/cortex_m85/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_m85/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_m85/gnu/src/txe_thread_secure_stack_allocate.c b/ports/cortex_m85/gnu/src/txe_thread_secure_stack_allocate.c index 17cc9f53..43b4db08 100644 --- a/ports/cortex_m85/gnu/src/txe_thread_secure_stack_allocate.c +++ b/ports/cortex_m85/gnu/src/txe_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { @@ -76,10 +71,10 @@ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_siz return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports/cortex_m85/gnu/src/txe_thread_secure_stack_free.c b/ports/cortex_m85/gnu/src/txe_thread_secure_stack_free.c index a41b1c24..d6431134 100644 --- a/ports/cortex_m85/gnu/src/txe_thread_secure_stack_free.c +++ b/ports/cortex_m85/gnu/src/txe_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { @@ -74,10 +69,10 @@ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports/cortex_m85/iar/inc/tx_port.h b/ports/cortex_m85/iar/inc/tx_port.h index 46f53b8b..bf245049 100644 --- a/ports/cortex_m85/iar/inc/tx_port.h +++ b/ports/cortex_m85/iar/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,39 +46,6 @@ /* This file replaces the previous Cortex-M85 files. It unifies */ /* the Cortex-M85 compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-02-2021 Scott Larson Modified comment(s), added */ -/* ULONG64_DEFINED, */ -/* resulting in version 6.1.5 */ -/* 06-02-2021 Scott Larson Modified comment(s), removed */ -/* unneeded header file, funcs */ -/* set_control and get_control */ -/* changed to inline, */ -/* added symbol to enable */ -/* stack error handler, */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ -/* stack check error handling, */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), unified */ -/* this file across compilers, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* 03-08-2023 Scott Larson Removed unneeded #include, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -645,7 +613,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M85/IAR Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M85/IAR Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m85/iar/inc/tx_secure_interface.h b/ports/cortex_m85/iar/inc/tx_secure_interface.h index 39b5d5fd..5ac37fbf 100644 --- a/ports/cortex_m85/iar/inc/tx_secure_interface.h +++ b/ports/cortex_m85/iar/inc/tx_secure_interface.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,12 +38,6 @@ /* It is assumed that tx_api.h and tx_port.h have already been */ /* included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_SECURE_INTERFACE_H diff --git a/ports/cortex_m85/iar/readme_threadx.txt b/ports/cortex_m85/iar/readme_threadx.txt index 6a39bbc7..6436cfa8 100644 --- a/ports/cortex_m85/iar/readme_threadx.txt +++ b/ports/cortex_m85/iar/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for Cortex-M85 + Microsoft's Azure RTOS ThreadX for Cortex-M85 Using the IAR Tools @@ -6,33 +6,33 @@ 1. Building the ThreadX run-time Library Import all ThreadX common and port-specific source files into an IAR project. -Configure the project to build a library rather than an executable. This -results in the ThreadX run-time library file tx.a, which is needed by +Configure the project to build a library rather than an executable. This +results in the ThreadX run-time library file tx.a, which is needed by the application. -Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c -replace the common files of the same name. +Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c +replace the common files of the same name. 2. Demonstration System No demonstration is provided because the IAR EWARM 8.50 simulator does -not simulate the Cortex-M85 correctly. +not simulate the Cortex-M85 correctly. 3. System Initialization -The entry point in ThreadX for the Cortex-M85 using IAR tools is at label -__iar_program_start. This is defined within the IAR compiler's startup code. -In addition, this is where all static and global preset C variable +The entry point in ThreadX for the Cortex-M85 using IAR tools is at label +__iar_program_start. This is defined within the IAR compiler's startup code. +In addition, this is where all static and global preset C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, and a periodic timer interrupt source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. The _tx_initialize_low_level function inside of tx_initialize_low_level.s -also determines the first available address for use by the application, which -is supplied as the sole input parameter to your application definition function, -tx_application_define. To accomplish this, a section is created in -tx_initialize_low_level.s called FREE_MEM, which must be located after all +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all other RAM sections in memory. @@ -41,7 +41,7 @@ other RAM sections in memory. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M85 version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -124,17 +124,17 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 5. Improving Performance -To make ThreadX and the application(s) run faster, you can enable -all compiler optimizations. +To make ThreadX and the application(s) run faster, you can enable +all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling -The Cortex-M85 vectors start at the label __vector_table and is typically defined in a +The Cortex-M85 vectors start at the label __vector_table and is typically defined in a startup.s file (or similar). The application may modify the vector area according to its needs. @@ -182,14 +182,14 @@ should have the following line added (if not already in place): initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application -The project options "General Options -> Library Configuration" should also have the +The project options "General Options -> Library Configuration" should also have the "Enable thread support in library" box selected. 8. VFP Support -ThreadX for Cortex-M85 supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-M85 supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context. diff --git a/ports/cortex_m85/iar/src/tx_iar.c b/ports/cortex_m85/iar/src/tx_iar.c index ee47f10f..238b485e 100644 --- a/ports/cortex_m85/iar/src/tx_iar.c +++ b/ports/cortex_m85/iar/src/tx_iar.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports/cortex_m85/iar/src/tx_initialize_low_level.s b/ports/cortex_m85/iar/src/tx_initialize_low_level.s index 9c113881..64260c52 100644 --- a/ports/cortex_m85/iar/src/tx_initialize_low_level.s +++ b/ports/cortex_m85/iar/src/tx_initialize_low_level.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,13 +75,6 @@ __tx_free_memory_start /* CALLED BY */ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports/cortex_m85/iar/src/tx_misra.s b/ports/cortex_m85/iar/src/tx_misra.s index f86d9a65..642bb89e 100644 --- a/ports/cortex_m85/iar/src/tx_misra.s +++ b/ports/cortex_m85/iar/src/tx_misra.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -120,7 +121,7 @@ SECTION `.data`:DATA:REORDER:NOROOT(2) DATA -// 51 CHAR _tx_version_id[100] = "Copyright (c) 2024 Microsoft Corporation. * ThreadX 6.1 MISRA C Compliant *"; +// 51 CHAR _tx_version_id[100] = "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX 6.1 MISRA C Compliant *"; _tx_version_id: DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H @@ -707,7 +708,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -722,7 +723,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARMVFP__ /***********************************************************************************************/ @@ -739,8 +740,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -754,10 +755,10 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - - + + SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2) SECTION_TYPE SHT_PROGBITS, 0 DATA diff --git a/ports/cortex_m85/iar/src/tx_thread_context_restore.s b/ports/cortex_m85/iar/src/tx_thread_context_restore.s index 349d3e20..ca914644 100644 --- a/ports/cortex_m85/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_m85/iar/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,13 +56,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports/cortex_m85/iar/src/tx_thread_context_save.s b/ports/cortex_m85/iar/src/tx_thread_context_save.s index dcad5553..ec1c3538 100644 --- a/ports/cortex_m85/iar/src/tx_thread_context_save.s +++ b/ports/cortex_m85/iar/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,13 +56,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports/cortex_m85/iar/src/tx_thread_interrupt_control.s b/ports/cortex_m85/iar/src/tx_thread_interrupt_control.s index 86f54c3e..24cc2ff7 100644 --- a/ports/cortex_m85/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m85/iar/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,13 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports/cortex_m85/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m85/iar/src/tx_thread_interrupt_disable.s index d58176c2..414b53dd 100644 --- a/ports/cortex_m85/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m85/iar/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,13 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports/cortex_m85/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_m85/iar/src/tx_thread_interrupt_restore.s index d21b373e..c9ce1596 100644 --- a/ports/cortex_m85/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m85/iar/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,13 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports/cortex_m85/iar/src/tx_thread_schedule.s b/ports/cortex_m85/iar/src/tx_thread_schedule.s index d54fd420..fa2d7ba0 100644 --- a/ports/cortex_m85/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m85/iar/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -73,23 +74,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 04-02-2021 Scott Larson Modified comment(s), added */ -/* low power code, */ -/* resulting in version 6.1.6 */ -/* 06-02-2021 Scott Larson Added secure stack initialize */ -/* in SVC handler, */ -/* resulting in version 6.1.7 */ -/* 04-25-2022 Scott Larson Added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 03-08-2023 Scott Larson Added preproc FPU option, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -348,7 +332,7 @@ SVC_Handler: CMP r1, #2 // Is it a secure stack free request? BEQ _tx_svc_secure_free // Yes, go there - + CMP r1, #3 // Is it a secure stack init request? BEQ _tx_svc_secure_init // Yes, go there diff --git a/ports/cortex_m85/iar/src/tx_thread_secure_stack.c b/ports/cortex_m85/iar/src/tx_thread_secure_stack.c index 4360e63b..c4b79ad1 100644 --- a/ports/cortex_m85/iar/src/tx_thread_secure_stack.c +++ b/ports/cortex_m85/iar/src/tx_thread_secure_stack.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -102,20 +103,6 @@ static INT tx_head_free_index = 0U; /* */ /* _tx_initialize_kernel_enter */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-16-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.1 */ -/* 06-02-2021 Scott Larson Change name, execute in */ -/* handler mode, */ -/* resulting in version 6.1.7 */ -/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ -/* secure stack allocation, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_initialize(void) diff --git a/ports/cortex_m85/iar/src/tx_thread_secure_stack_allocate.s b/ports/cortex_m85/iar/src/tx_thread_secure_stack_allocate.s index 7cb99950..112f0136 100644 --- a/ports/cortex_m85/iar/src/tx_thread_secure_stack_allocate.s +++ b/ports/cortex_m85/iar/src/tx_thread_secure_stack_allocate.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,13 +57,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) // { diff --git a/ports/cortex_m85/iar/src/tx_thread_secure_stack_free.s b/ports/cortex_m85/iar/src/tx_thread_secure_stack_free.s index 206369e6..e0cc7a87 100644 --- a/ports/cortex_m85/iar/src/tx_thread_secure_stack_free.s +++ b/ports/cortex_m85/iar/src/tx_thread_secure_stack_free.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,13 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) // { diff --git a/ports/cortex_m85/iar/src/tx_thread_secure_stack_initialize.s b/ports/cortex_m85/iar/src/tx_thread_secure_stack_initialize.s index dd92ca35..364044bc 100644 --- a/ports/cortex_m85/iar/src/tx_thread_secure_stack_initialize.s +++ b/ports/cortex_m85/iar/src/tx_thread_secure_stack_initialize.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* CALLED BY */ /* */ /* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) // { diff --git a/ports/cortex_m85/iar/src/tx_thread_stack_build.s b/ports/cortex_m85/iar/src/tx_thread_stack_build.s index d21f51b3..b6b5837e 100644 --- a/ports/cortex_m85/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_m85/iar/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,13 +58,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/cortex_m85/iar/src/tx_thread_system_return.s b/ports/cortex_m85/iar/src/tx_thread_system_return.s index 07d9a5dd..768262a2 100644 --- a/ports/cortex_m85/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m85/iar/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,13 +58,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports/cortex_m85/iar/src/tx_timer_interrupt.s b/ports/cortex_m85/iar/src/tx_timer_interrupt.s index e1ce095a..b7d7c589 100644 --- a/ports/cortex_m85/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_m85/iar/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,13 +72,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports/cortex_m85/iar/src/txe_thread_secure_stack_allocate.c b/ports/cortex_m85/iar/src/txe_thread_secure_stack_allocate.c index 17cc9f53..43b4db08 100644 --- a/ports/cortex_m85/iar/src/txe_thread_secure_stack_allocate.c +++ b/ports/cortex_m85/iar/src/txe_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { @@ -76,10 +71,10 @@ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_siz return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports/cortex_m85/iar/src/txe_thread_secure_stack_free.c b/ports/cortex_m85/iar/src/txe_thread_secure_stack_free.c index a41b1c24..d6431134 100644 --- a/ports/cortex_m85/iar/src/txe_thread_secure_stack_free.c +++ b/ports/cortex_m85/iar/src/txe_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { @@ -74,10 +69,10 @@ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports/cortex_r4/ac5/example_build/sample_threadx.c b/ports/cortex_r4/ac5/example_build/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports/cortex_r4/ac5/example_build/sample_threadx.c +++ b/ports/cortex_r4/ac5/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_r4/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_r4/ac5/example_build/tx_initialize_low_level.s index c36819eb..6d7ddf4f 100644 --- a/ports/cortex_r4/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_r4/ac5/example_build/tx_initialize_low_level.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -90,45 +90,39 @@ __vectors ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-R4/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-R4/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -179,7 +173,7 @@ _tx_initialize_low_level ; _tx_thread_system_stack_ptr = (VOID_PTR) (sp); ; LDR r1, =_tx_thread_system_stack_ptr ; Pickup address of system stack ptr - LDR r0, [r1, #0] ; Pickup system stack + LDR r0, [r1, #0] ; Pickup system stack ADD r0, r0, #4 ; Increment to next free word ; ; /* Save the first available memory address. */ @@ -201,7 +195,7 @@ _tx_initialize_low_level ; ; ;/* Define initial heap/stack routine for the ARM RealView (and ADS) startup code. This -; routine will set the initial stack to use the ThreadX IRQ & FIQ & +; routine will set the initial stack to use the ThreadX IRQ & FIQ & ; (optionally SYS) stack areas. */ ; EXPORT __user_initial_stackheap @@ -253,7 +247,7 @@ __tx_reserved_handler ; ; EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -261,21 +255,21 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; ; BL _tx_timer_interrupt ; Timer interrupt handler _tx_not_timer_interrupt ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ IF :DEF:TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -285,7 +279,7 @@ _tx_not_timer_interrupt ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ IF :DEF:TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -301,28 +295,28 @@ _tx_not_timer_interrupt __tx_example_vectored_irq_handler ; ; -; /* Save initial context and call context save to prepare for +; /* Save initial context and call context save to prepare for ; vectored ISR execution. */ ; ; STMDB sp!, {r0-r3} ; Save some scratch registers ; MRS r0, SPSR ; Pickup saved SPSR -; SUB lr, lr, #4 ; Adjust point of interrupt +; SUB lr, lr, #4 ; Adjust point of interrupt ; STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers ; BL _tx_thread_vectored_context_save ; Vectored context save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ; IF :DEF:TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_start @@ -331,7 +325,7 @@ __tx_example_vectored_irq_handler ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ; IF :DEF:TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_end @@ -353,11 +347,11 @@ __tx_fiq_processing_return ; /* At this point execution is still in the FIQ mode. The CPSR, point of ; interrupt, and all C scratch registers are available for use. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start ; from FIQ mode with interrupts disabled. This routine switches to the -; system mode and returns with FIQ interrupts enabled. +; system mode and returns with FIQ interrupts enabled. ; -; NOTE: It is very important to ensure all FIQ interrupts are cleared +; NOTE: It is very important to ensure all FIQ interrupts are cleared ; prior to enabling nested FIQ interrupts. */ IF :DEF:TX_ENABLE_FIQ_NESTING BL _tx_thread_fiq_nesting_start diff --git a/ports/cortex_r4/ac5/inc/tx_port.h b/ports/cortex_r4/ac5/inc/tx_port.h index c77e3146..07233290 100644 --- a/ports/cortex_r4/ac5/inc/tx_port.h +++ b/ports/cortex_r4/ac5/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Cortex-R4/AC5 */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-R4/AC5 */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -75,7 +67,7 @@ #include -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -111,12 +103,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -126,8 +118,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -174,7 +166,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -186,13 +178,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -206,11 +198,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -218,8 +210,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -246,21 +238,21 @@ typedef unsigned short USHORT; #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef __thumb #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (ULONG) __clz((unsigned int) m); \ - b = 31 - b; + b = 31 - b; #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -280,7 +272,7 @@ typedef unsigned short USHORT; { \ __enable_irq(); \ __enable_fiq(); \ - } + } #else @@ -289,7 +281,7 @@ typedef unsigned short USHORT; #define TX_RESTORE if (!interrupt_save_disabled) \ { \ __enable_irq(); \ - } + } #endif #else @@ -325,8 +317,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-R4/AC5 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R4/AC5 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r4/ac5/readme_threadx.txt b/ports/cortex_r4/ac5/readme_threadx.txt index d27aa166..718f1c03 100644 --- a/ports/cortex_r4/ac5/readme_threadx.txt +++ b/ports/cortex_r4/ac5/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for Cortex-R4 + Microsoft's Azure RTOS ThreadX for Cortex-R4 Thumb & 32-bit Mode @@ -6,21 +6,21 @@ 1. Building the ThreadX run-time Library -First make sure you are in the "example_build" directory. Also, make sure that -you have setup your path and other environment variables necessary for the ARM -AC5 development environment. At this point you may run the build_threadx.bat -batch file. This will build the ThreadX run-time environment in the -"example_build" directory. +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the ARM +AC5 development environment. At this point you may run the build_threadx.bat +batch file. This will build the ThreadX run-time environment in the +"example_build" directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. 1.1 Building with Project Files -The ThreadX library can also be built via project files. Simply open -the tx.mcp file with project builder and select make. This will place +The ThreadX library can also be built via project files. Simply open +the tx.mcp file with project builder and select make. This will place the tx.a library file into the Debug sub-directory. @@ -29,45 +29,45 @@ the tx.a library file into the Debug sub-directory. The ThreadX demonstration is designed to execute under the ARM Windows-based simulator. -Building the demonstration is easy; simply execute the build_threadx_demo.bat -batch file while inside the "example_build" directory. +Building the demonstration is easy; simply execute the build_threadx_demo.bat +batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with tx.a. The resulting file sample_threadx.axf +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.axf is a binary file that can be downloaded and executed on the ARM simulator. 2.0.1 Building with Project Files -The ThreadX demonstration can also be built via project files. Simply open -the sample_threadx.mcp file with project builder and select make. This will place +The ThreadX demonstration can also be built via project files. Simply open +the sample_threadx.mcp file with project builder and select make. This will place the sample_threadx.axf output image into the Debug sub-directory. 3. System Initialization -The entry point in ThreadX for the Cortex-R4 using AC5 tools is at label -__main. This is defined within the AC5 compiler's startup code. In -addition, this is where all static and global pre-set C variable +The entry point in ThreadX for the Cortex-R4 using AC5 tools is at label +__main. This is defined within the AC5 compiler's startup code. In +addition, this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. By default, the vector area is defined to be located in the Init area, -which is defined at the top of tx_initialize_low_level.s. This area is typically -located at 0. In situations where this is impossible, the vectors at the beginning +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. By default, the vector area is defined to be located in the Init area, +which is defined at the top of tx_initialize_low_level.s. This area is typically +located at 0. In situations where this is impossible, the vectors at the beginning of the Init area should be copied to address 0. This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 4. Assembler / Compiler Switches -The following are compiler switches used in building the demonstration +The following are compiler switches used in building the demonstration system: Compiler Switch Meaning @@ -83,10 +83,10 @@ Linker Switch Meaning -o demo.axf Specifies demo output file name --elf Specifies elf output file format --ro Specifies that Read-Only memory starts at address 0 - --first tx_initialize_low_level.o(Init) + --first tx_initialize_low_level.o(Init) Specifies that the first area loaded is Init --remove Remove unused areas - --list Specifies map file name + --list Specifies map file name --symbols Specifies symbols for map file --map Creates a map file @@ -97,161 +97,161 @@ Application Defines ThreadX assembly files. If used, it should be used on all assembly files and the generic C source of - ThreadX should be compiled with + ThreadX should be compiled with TX_ENABLE_FIQ_SUPPORT defined as well. --PD "TX_ENABLE_IRQ_NESTING SETL {TRUE}" This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. --PD "TX_ENABLE_FIQ_NESTING SETL {TRUE}" This assembler define enables FIQ - nested support. If FIQ nested + nested support. If FIQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. In addition, IRQ nesting should also be enabled. -DTX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ interrupt handling in the ThreadX - generic C source. This define + generic C source. This define should also be used in conjunction with the corresponding assembler - define. + define. -DTX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - -DTX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + -DTX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - -DTX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + -DTX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - -DTX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + -DTX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - -DTX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + -DTX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - -DTX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + -DTX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - -DTX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + -DTX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - -DTX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + -DTX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - -DTX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + -DTX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - -DTX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + -DTX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - -DTX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + -DTX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - -DTX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + -DTX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - -DTX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + -DTX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - -DTX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + -DTX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - -DTX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + -DTX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - -DTX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + -DTX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - -DTX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + -DTX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - -DTX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + -DTX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - -DTX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + -DTX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - -DTX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + -DTX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. -DTX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - -DTX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + -DTX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - -DTX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + -DTX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. 5. Register Usage and Stack Frames -The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -269,39 +269,39 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make it run faster, you can change the build_threadx.bat file to -remove the -g option and enable all compiler optimizations. +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-R4 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-R4 vectors start at address zero. The demonstration system startup -Init area contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +Init area contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs @@ -312,12 +312,12 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.s: EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -325,7 +325,7 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -338,7 +338,7 @@ __tx_irq_processing_return 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.s: EXPORT __tx_irq_example_handler @@ -348,12 +348,12 @@ __tx_irq_example_handler STMDB sp!, {r0-r3} ; Save some scratch registers MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers BL _tx_thread_vectored_context_save ; Call the vectored IRQ context save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -370,22 +370,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.s. When nested IRQ interrupts are no longer required, calling the _tx_thread_irq_nesting_end service disables nesting by disabling -IRQ interrupts and switching back to IRQ mode in preparation for the IRQ +IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -393,10 +393,10 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* Enable nested IRQ interrupts. NOTE: Since this service returns -; with IRQ interrupts enabled, all IRQ interrupt sources must be +; with IRQ interrupts enabled, all IRQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start -; +; ; /* Application ISR call(s) go here! */ ; ; /* Disable nested IRQ interrupts. The mode is switched back to @@ -409,12 +409,12 @@ __tx_irq_processing_return 7.3 FIQ Interrupts -By default, Cortex-R4 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, Cortex-R4 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.s. @@ -423,7 +423,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.s. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.s: @@ -451,18 +451,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.s. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -478,7 +478,7 @@ __tx_fiq_processing_return ; interrupt, and all C scratch registers are available for use. */ ; ; /* Enable nested FIQ interrupts. NOTE: Since this service returns -; with FIQ interrupts enabled, all FIQ interrupt sources must be +; with FIQ interrupts enabled, all FIQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start ; @@ -494,29 +494,29 @@ __tx_fiq_processing_return 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.s in the Integrator sub-directories. 9. Thumb/Cortex-R4 Mixed Mode -By default, ThreadX is setup for running in Cortex-R4 32-bit mode. This is -also true for the demonstration system. It is possible to build any -ThreadX file and/or the application in Thumb mode. If any Thumb code -is used the entire ThreadX source- both C and assembly - should be built +By default, ThreadX is setup for running in Cortex-R4 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. If any Thumb code +is used the entire ThreadX source- both C and assembly - should be built with the "-apcs /interwork" option. 10. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); diff --git a/ports/cortex_r4/ac5/src/tx_thread_context_restore.s b/ports/cortex_r4/ac5/src/tx_thread_context_restore.s index 3a4eef8c..0572cd1c 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_r4/ac5/src/tx_thread_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -54,44 +54,38 @@ SVC_MODE EQU 0x93 ; SVC mode ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore Cortex-R4/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-R4/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -121,13 +115,13 @@ _tx_thread_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3, #0] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3, #0] ; Store the counter + STR r2, [r3, #0] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs diff --git a/ports/cortex_r4/ac5/src/tx_thread_context_save.s b/ports/cortex_r4/ac5/src/tx_thread_context_save.s index c03187e4..c3c6de9b 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_context_save.s +++ b/ports/cortex_r4/ac5/src/tx_thread_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,43 +39,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save Cortex-R4/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-R4/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -90,7 +84,7 @@ _tx_thread_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers IF :DEF:TX_ENABLE_FIQ_SUPPORT CPSID if ; Disable FIQ interrupts ENDIF @@ -108,7 +102,7 @@ _tx_thread_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -124,7 +118,7 @@ _tx_thread_context_save POP {lr} ; Recover ISR lr ENDIF - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; __tx_thread_not_nested_save ; } @@ -138,13 +132,13 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} ; Store other registers ; ; /* Save the current stack pointer in the thread's control block. */ @@ -164,7 +158,7 @@ __tx_thread_not_nested_save POP {lr} ; Recover ISR lr ENDIF - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ; else @@ -174,7 +168,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit @@ -189,7 +183,7 @@ __tx_thread_idle_system_save ENDIF ADD sp, sp, #16 ; Recover saved registers - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ;} diff --git a/ports/cortex_r4/ac5/src/tx_thread_fiq_context_restore.s b/ports/cortex_r4/ac5/src/tx_thread_fiq_context_restore.s index e2a712a7..89cab39d 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_r4/ac5/src/tx_thread_fiq_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -32,7 +32,7 @@ ; SVC_MODE EQU 0xD3 ; SVC mode FIQ_MODE EQU 0xD1 ; FIQ mode -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; ; @@ -50,44 +50,38 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_restore Cortex-R4/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore Cortex-R4/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the fiq interrupt context when processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* FIQ ISR Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) @@ -113,13 +107,13 @@ _tx_thread_fiq_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3] ; Store the counter + STR r2, [r3] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -163,7 +157,7 @@ __tx_thread_fiq_no_preempt_restore ; /* Restore interrupted thread or ISR. */ ; ; /* Pickup the saved stack pointer. */ -; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; ; ; /* Recover the saved context and return to the point of interrupt. */ ; @@ -207,7 +201,7 @@ _tx_skip_fiq_vfp_save MOV r3, #1 ; Build interrupt stack type STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR STR sp, [r0, #8] ; Save stack pointer in thread control - ; block + ; block ; ; /* Save the remaining time-slice and disable it. */ ; if (_tx_timer_time_slice) @@ -219,7 +213,7 @@ _tx_skip_fiq_vfp_save BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it ; ; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; -; _tx_timer_time_slice = 0; +; _tx_timer_time_slice = 0; ; STR r2, [r0, #24] ; Save thread's time-slice MOV r2, #0 ; Clear value diff --git a/ports/cortex_r4/ac5/src/tx_thread_fiq_context_save.s b/ports/cortex_r4/ac5/src/tx_thread_fiq_context_save.s index 9026e56d..8fd1fcac 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_fiq_context_save.s +++ b/ports/cortex_r4/ac5/src/tx_thread_fiq_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,43 +39,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_save Cortex-R4/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save Cortex-R4/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) @@ -90,7 +84,7 @@ _tx_thread_fiq_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state CMP r2, #0 ; Is this the first interrupt? @@ -105,7 +99,7 @@ _tx_thread_fiq_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -121,38 +115,38 @@ _tx_thread_fiq_context_save POP {lr} ; Recover ISR lr ENDIF - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; __tx_thread_fiq_not_nested_save -; } +; } ; ; /* Otherwise, not nested, check to see if a thread was running. */ ; else if (_tx_thread_current_ptr) -; { +; { ; ADD r2, r2, #1 ; Increment the interrupt counter STR r2, [r3] ; Store it back in the variable LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in -; ; scheduling loop - nothing needs saving! + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, lr} ; Store other registers, Note that we don't -; ; need to save sl and ip since FIQ has -; ; copies of these registers. Nested +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested ; ; interrupt processing does need to save ; ; these registers. ; ; /* Save the current stack pointer in the thread's control block. */ -; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; ; ; /* Switch to the system stack. */ -; sp = _tx_thread_system_stack_ptr; +; sp = _tx_thread_system_stack_ptr; ; MOV r10, #0 ; Clear stack limit @@ -165,7 +159,7 @@ __tx_thread_fiq_not_nested_save POP {lr} ; Recover ISR lr ENDIF - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } ; else @@ -185,18 +179,18 @@ __tx_thread_fiq_idle_system_save ENDIF ; ; /* Not much to do here, save the current SPSR and LR for possible -; use in IRQ interrupted in idle system conditions, and return to +; use in IRQ interrupted in idle system conditions, and return to ; FIQ interrupt processing. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, lr} ; Store other registers that will get used -; ; or stripped off the stack in context -; ; restore - B __tx_fiq_processing_return ; Continue FIQ processing +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } -;} +;} ; END diff --git a/ports/cortex_r4/ac5/src/tx_thread_fiq_nesting_end.s b/ports/cortex_r4/ac5/src/tx_thread_fiq_nesting_end.s index a26bab46..2f67e820 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_fiq_nesting_end.s +++ b/ports/cortex_r4/ac5/src/tx_thread_fiq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,56 +34,50 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_end Cortex-R4/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end Cortex-R4/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ -;/* processing from system mode back to FIQ mode prior to the ISR */ -;/* calling _tx_thread_fiq_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with FIQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) @@ -94,7 +88,7 @@ _tx_thread_fiq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_c, r0 ; Disable interrupts - LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports/cortex_r4/ac5/src/tx_thread_fiq_nesting_start.s b/ports/cortex_r4/ac5/src/tx_thread_fiq_nesting_start.s index d714b4b3..d5e01f06 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_fiq_nesting_start.s +++ b/ports/cortex_r4/ac5/src/tx_thread_fiq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_start Cortex-R4/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start Cortex-R4/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ -;/* processing to the system mode so nested FIQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with FIQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_r4/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_r4/ac5/src/tx_thread_interrupt_control.s index e69cb941..e242582c 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_interrupt_control.s +++ b/ports/cortex_r4/ac5/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,42 +36,36 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control Cortex-R4/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-R4/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_r4/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_r4/ac5/src/tx_thread_interrupt_disable.s index 239cb49e..62158e06 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_r4/ac5/src/tx_thread_interrupt_disable.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,41 +29,35 @@ ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable Cortex-R4/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-R4/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(void) @@ -80,7 +74,7 @@ _tx_thread_interrupt_disable IF :DEF:TX_ENABLE_FIQ_SUPPORT CPSID if ; Disable IRQ and FIQ ELSE - CPSID i ; Disable IRQ + CPSID i ; Disable IRQ ENDIF IF {INTER} = {TRUE} diff --git a/ports/cortex_r4/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_r4/ac5/src/tx_thread_interrupt_restore.s index bbf8ccd7..36bdebf1 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_r4/ac5/src/tx_thread_interrupt_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,42 +29,36 @@ ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore Cortex-R4/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-R4/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function is responsible for restoring interrupts to the state */ ;/* returned by a previous _tx_thread_interrupt_disable call. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_r4/ac5/src/tx_thread_irq_nesting_end.s b/ports/cortex_r4/ac5/src/tx_thread_irq_nesting_end.s index 2c718a74..ab4ff39b 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_irq_nesting_end.s +++ b/ports/cortex_r4/ac5/src/tx_thread_irq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,56 +34,50 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_end Cortex-R4/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-R4/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -;/* processing from system mode back to IRQ mode prior to the ISR */ -;/* calling _tx_thread_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) @@ -94,7 +88,7 @@ _tx_thread_irq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_c, r0 ; Disable interrupts - LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports/cortex_r4/ac5/src/tx_thread_irq_nesting_start.s b/ports/cortex_r4/ac5/src/tx_thread_irq_nesting_start.s index 2bd74a99..01442b0c 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_irq_nesting_start.s +++ b/ports/cortex_r4/ac5/src/tx_thread_irq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_start Cortex-R4/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-R4/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_context_save has been called and switches the IRQ */ -;/* processing to the system mode so nested IRQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_r4/ac5/src/tx_thread_schedule.s b/ports/cortex_r4/ac5/src/tx_thread_schedule.s index 64af5589..fb788268 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_r4/ac5/src/tx_thread_schedule.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -40,45 +40,39 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule Cortex-R4/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-R4/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -107,7 +101,7 @@ __tx_thread_schedule_loop ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Lockout interrupts and ; transfer control to it. */ ; @@ -120,7 +114,7 @@ __tx_thread_schedule_loop ; /* Setup the current thread pointer. */ ; _tx_thread_current_ptr = _tx_thread_execute_ptr; ; - LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread STR r0, [r1, #0] ; Setup current thread pointer ; ; /* Increment the run count for this thread. */ @@ -134,7 +128,7 @@ __tx_thread_schedule_loop ; /* Setup time-slice, if present. */ ; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; ; - LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice ; variable LDR sp, [r0, #8] ; Switch stack pointers STR r3, [r2, #0] ; Setup time-slice diff --git a/ports/cortex_r4/ac5/src/tx_thread_stack_build.s b/ports/cortex_r4/ac5/src/tx_thread_stack_build.s index 2f21d30c..d2ffcd2f 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_stack_build.s +++ b/ports/cortex_r4/ac5/src/tx_thread_stack_build.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -41,44 +41,38 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build Cortex-R4/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-R4/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function builds a stack frame on the supplied thread's stack. */ ;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ ;/* thread_ptr Pointer to thread control blk */ ;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -86,10 +80,10 @@ THUMB_BIT EQU 0x20 ; Thumb-bit EXPORT _tx_thread_stack_build _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-R4 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; a1 (r0) Initial value for a1 diff --git a/ports/cortex_r4/ac5/src/tx_thread_system_return.s b/ports/cortex_r4/ac5/src/tx_thread_system_return.s index f6128d56..cd3ffb00 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_system_return.s +++ b/ports/cortex_r4/ac5/src/tx_thread_system_return.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -33,50 +33,44 @@ IMPORT _tx_timer_time_slice IMPORT _tx_thread_schedule IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY - IMPORT _tx_execution_thread_exit + IMPORT _tx_execution_thread_exit ENDIF ; ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return Cortex-R4/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-R4/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -103,7 +97,7 @@ _tx_skip_solicited_vfp_save MOV r0, #0 ; Build a solicited stack type MRS r1, CPSR ; Pickup the CPSR STMDB sp!, {r0-r1} ; Save type and CPSR -; +; ; /* Lockout interrupts. */ ; IF :DEF:TX_ENABLE_FIQ_SUPPORT diff --git a/ports/cortex_r4/ac5/src/tx_thread_vectored_context_save.s b/ports/cortex_r4/ac5/src/tx_thread_vectored_context_save.s index aec5717d..8d3f023d 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_vectored_context_save.s +++ b/ports/cortex_r4/ac5/src/tx_thread_vectored_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -38,43 +38,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_vectored_context_save Cortex-R4/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-R4/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) @@ -107,7 +101,7 @@ _tx_thread_vectored_context_save ; /* Return to the ISR. */ ; MOV r10, #0 ; Clear stack limit - + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; ; /* Call the ISR enter function to indicate an ISR is executing. */ @@ -135,7 +129,7 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Note: Minimal context of interrupted thread is already saved. */ @@ -171,7 +165,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports/cortex_r4/ac5/src/tx_timer_interrupt.s b/ports/cortex_r4/ac5/src/tx_timer_interrupt.s index a5d96fda..10e49b6c 100644 --- a/ports/cortex_r4/ac5/src/tx_timer_interrupt.s +++ b/ports/cortex_r4/ac5/src/tx_timer_interrupt.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -44,46 +44,40 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt Cortex-R4/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-R4/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -107,7 +101,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CMP r2, #0 ; Is it non-active? BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing @@ -225,13 +219,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CMP r2, #0 ; See if the flag is set BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing ; diff --git a/ports/cortex_r4/ac6/example_build/sample_threadx/.cproject b/ports/cortex_r4/ac6/example_build/sample_threadx/.cproject index e2104d21..4265aaf8 100644 --- a/ports/cortex_r4/ac6/example_build/sample_threadx/.cproject +++ b/ports/cortex_r4/ac6/example_build/sample_threadx/.cproject @@ -1,158 +1,158 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.c index a32037a6..6a996f77 100644 --- a/ports/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -85,41 +85,41 @@ CHAR *pointer = TX_NULL; /* Create the main thread. */ tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -127,23 +127,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -246,11 +246,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -309,7 +309,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -362,7 +362,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.scat index 926647b2..9eb35ca0 100644 --- a/ports/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.scat @@ -18,21 +18,21 @@ SDRAM 0x0 0x40000000 * (+RO-CODE) ; Application RO code (.text) * (+RO-DATA) ; Application RO data (.constdata) } - + IRQ_STACK +0 ALIGN 8 EMPTY 1024 {} - + FIQ_STACK +0 ALIGN 8 EMPTY 512 {} - + SVC_STACK +0 ALIGN 8 EMPTY 2048 {} - + SYS_STACK +0 ALIGN 8 EMPTY 2048 {} - + ABORT_STACK +0 ALIGN 8 EMPTY 2048 {} ; Application RW & ZI data (.data & .bss) DATA +0 0x100000 { - * (+RW,+ZI) + * (+RW,+ZI) } PERIPHERALS 0xA0000000 EMPTY 0x20000000 { }; Peripherals diff --git a/ports/cortex_r4/ac6/example_build/sample_threadx/startup.S b/ports/cortex_r4/ac6/example_build/sample_threadx/startup.S index 98d3b2b1..cc59bcd9 100644 --- a/ports/cortex_r4/ac6/example_build/sample_threadx/startup.S +++ b/ports/cortex_r4/ac6/example_build/sample_threadx/startup.S @@ -3,7 +3,7 @@ // // Copyright (c) 2006-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. //---------------------------------------------------------------- @@ -196,7 +196,7 @@ Reset_Handler: // Enable Branch prediction //---------------------------------------------------------------- -// In the Cortex-R4, the Z-bit of the SCTLR does not control the program flow prediction. +// In the Cortex-R4, the Z-bit of the SCTLR does not control the program flow prediction. // Some control bits in the ACTLR control the program flow and prefetch features instead. // These are enabled by default, but are shown here for completeness. diff --git a/ports/cortex_r4/ac6/example_build/tx/.cproject b/ports/cortex_r4/ac6/example_build/tx/.cproject index 87d4b781..e1eba1a5 100644 --- a/ports/cortex_r4/ac6/example_build/tx/.cproject +++ b/ports/cortex_r4/ac6/example_build/tx/.cproject @@ -1,162 +1,162 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_r4/ac6/inc/tx_port.h b/ports/cortex_r4/ac6/inc/tx_port.h index 357b2298..ff4ed9d1 100644 --- a/ports/cortex_r4/ac6/inc/tx_port.h +++ b/ports/cortex_r4/ac6/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Cortex-R4/AC6 */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-R4/AC6 */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -78,7 +70,7 @@ #include -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -114,12 +106,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -129,8 +121,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -177,7 +169,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -189,13 +181,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -209,11 +201,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -221,8 +213,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -249,21 +241,21 @@ typedef unsigned short USHORT; #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef __thumb #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (ULONG) __clz((unsigned int) m); \ - b = 31 - b; + b = 31 - b; #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -283,7 +275,7 @@ typedef unsigned short USHORT; { \ __enable_irq(); \ __enable_fiq(); \ - } + } #else @@ -292,7 +284,7 @@ typedef unsigned short USHORT; #define TX_RESTORE if (!interrupt_save_disabled) \ { \ __enable_irq(); \ - } + } #endif #else @@ -328,8 +320,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-R4/AC6 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R4/AC6 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r4/ac6/readme_threadx.txt b/ports/cortex_r4/ac6/readme_threadx.txt index b861033f..9c0019aa 100644 --- a/ports/cortex_r4/ac6/readme_threadx.txt +++ b/ports/cortex_r4/ac6/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for Cortex-R4 + Microsoft's Azure RTOS ThreadX for Cortex-R4 Thumb & 32-bit Mode @@ -6,12 +6,12 @@ 1. Import the ThreadX Projects -In order to build the ThreadX library and the ThreadX demonstration, first move -the project folders into your DS workspace directory. The project folders are -named 'tx' and 'sample_threadx' and are located in the installation directory. +In order to build the ThreadX library and the ThreadX demonstration, first move +the project folders into your DS workspace directory. The project folders are +named 'tx' and 'sample_threadx' and are located in the installation directory. Now that the projects are in the workspace directory, import them into DS by -doing the following for each project: +doing the following for each project: 1. Click 'File -> Import -> Existing Projects into Workspace' 2. Set the root directory the project i.e. the 'tx' or 'sample_threadx' directory @@ -23,8 +23,8 @@ This is expected, so please do so. 2. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply right-click the Eclipse project -"tx" and then select the "Build Project" button. You should now observe the compilation +Building the ThreadX library is easy; simply right-click the Eclipse project +"tx" and then select the "Build Project" button. You should now observe the compilation and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. @@ -34,41 +34,41 @@ library file tx.a. The ThreadX demonstration is designed to execute under the DS-5 debugger on the VE_Cortex-R4 Bare Metal simulator. -Building the demonstration is easy; simply right-click the Eclipse project -"sample_threadx" and then select the "Build Project" button. You should now observe -the compilation and assembly of the ThreadX demonstration. This project build produces -the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder +Building the demonstration is easy; simply right-click the Eclipse project +"sample_threadx" and then select the "Build Project" button. You should now observe +the compilation and assembly of the ThreadX demonstration. This project build produces +the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder in the Project Explorer window, right-click on the 'cortex-r4_tx.launch' file, click 'Debug As', and then click 'cortex-r4_tx' from the submenu. This will cause the -debugger to load the sample_threadx.axf ELF file and run to main. You are now ready +debugger to load the sample_threadx.axf ELF file and run to main. You are now ready to execute the ThreadX demonstration. 4. System Initialization -The entry point in ThreadX for the Cortex-R4 using ARM tools is at label -"Vectors". This is defined within startup.S in the sample_threadx project. In addition, -this is where all static and global pre-set C variable initialization processing +The entry point in ThreadX for the Cortex-R4 using ARM tools is at label +"Vectors". This is defined within startup.S in the sample_threadx project. In addition, +this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for determining the -first available RAM address for use by the application, which is supplied as the +The ThreadX tx_initialize_low_level.s file is responsible for determining the +first available RAM address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 5. Register Usage and Stack Frames -The ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -86,39 +86,39 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make it run faster, you can change the build_threadx.bat file to -remove the -g option and enable all compiler optimizations. +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-R4 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-R4 vectors start at address zero. The demonstration system startup.S -file contains the vectors and is loaded at address zero. On actual hardware platforms, -this area might have to be copied to address 0. +file contains the vectors and is loaded at address zero. On actual hardware platforms, +this area might have to be copied to address 0. 7.2 IRQ ISRs @@ -129,8 +129,8 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.s: .global __tx_irq_handler @@ -159,7 +159,7 @@ __tx_irq_handler: 7.2.2 Vectored IRQ ISRs The vectored ARM ISR mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example ISR handler defined in +by the particular implementation. The following is an example ISR handler defined in tx_initialize_low_level.s: .global __tx_example_vectored_irq_handler @@ -200,18 +200,18 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.s. When nested IRQ interrupts are no longer required, calling the _tx_thread_irq_nesting_end service disables nesting by disabling -IRQ interrupts and switching back to IRQ mode in preparation for the IRQ +IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: .global __tx_irq_handler @@ -249,12 +249,12 @@ __tx_irq_processing_return: 7.3 FIQ Interrupts -By default, Cortex-R4 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, Cortex-R4 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.s. @@ -263,7 +263,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.s. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.s: @@ -293,18 +293,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.s. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -322,7 +322,7 @@ __tx_fiq_processing_return: interrupt, and all C scratch registers are available for use. */ /* Enable nested FIQ interrupts. NOTE: Since this service returns - with FIQ interrupts enabled, all FIQ interrupt sources must be + with FIQ interrupts enabled, all FIQ interrupt sources must be cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start @@ -338,28 +338,28 @@ __tx_fiq_processing_return: 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.s in the Integrator sub-directories. 9. Thumb/Cortex-R4 Mixed Mode -By default, ThreadX is setup for running in Cortex-R4 32-bit mode. This is -also true for the demonstration system. It is possible to build any -ThreadX file and/or the application in Thumb mode. To build ThreadX -assembly files in Thumb mode, define TX_THUMB_MODE. +By default, ThreadX is setup for running in Cortex-R4 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. To build ThreadX +assembly files in Thumb mode, define TX_THUMB_MODE. 10. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); diff --git a/ports/cortex_r4/ac6/src/tx_initialize_low_level.S b/ports/cortex_r4/ac6/src/tx_initialize_low_level.S index c14ebc5d..a4f0ada0 100644 --- a/ports/cortex_r4/ac6/src/tx_initialize_low_level.S +++ b/ports/cortex_r4/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -100,12 +101,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_initialize_low_level(VOID) { */ diff --git a/ports/cortex_r4/ac6/src/tx_thread_context_restore.S b/ports/cortex_r4/ac6/src/tx_thread_context_restore.S index 410b465f..51203843 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_r4/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,7 +55,7 @@ #endif .text .eabi_attribute Tag_ABI_align_preserved, 1 - + /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -88,12 +89,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_context_restore(VOID) { */ @@ -181,15 +176,15 @@ __tx_thread_preempt_restore: LDMIA sp!, {r3, r10, r12, lr} // Recover temporarily saved registers MOV r1, lr // Save lr (point of interrupt) - + CPS #SVC_MODE // Switch to SVC mode to save context on thread stack STR r1, [sp, #-4]! // Save point of interrupt STMDB sp!, {r4-r12, lr} // Save upper half of registers MOV r4, r3 // Save SPSR in r4 - + CPS #IRQ_MODE // Switch back to IRQ mode LDMIA sp!, {r0-r3} // Recover r0-r3 - + CPS #SVC_MODE // Switch to SVC mode to save remaining context on thread stack STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack diff --git a/ports/cortex_r4/ac6/src/tx_thread_context_save.S b/ports/cortex_r4/ac6/src/tx_thread_context_save.S index 696dc985..68951b08 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_r4/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -76,12 +77,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_context_save(VOID) { */ diff --git a/ports/cortex_r4/ac6/src/tx_thread_fiq_context_restore.S b/ports/cortex_r4/ac6/src/tx_thread_fiq_context_restore.S index 94c20b72..7fbcc84a 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_r4/ac6/src/tx_thread_fiq_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -88,12 +89,6 @@ /* */ /* FIQ ISR Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_fiq_context_restore(VOID) */ /* { */ @@ -186,15 +181,15 @@ __tx_thread_fiq_preempt_restore: LDMIA sp!, {r3, lr} // Recover temporarily saved registers MOV r1, lr // Save lr (point of interrupt) - + CPS #SVC_MODE // Switch to SVC mode to save context on thread stack STR r1, [sp, #-4]! // Save point of interrupt STMDB sp!, {r4-r12, lr} // Save upper half of registers MOV r4, r3 // Save SPSR in r4 - + CPS #FIQ_MODE // Switch back to FIQ mode LDMIA sp!, {r0-r3} // Recover r0-r3 - + CPS #SVC_MODE // Switch to SVC mode to save remaining context on thread stack STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack diff --git a/ports/cortex_r4/ac6/src/tx_thread_fiq_context_save.S b/ports/cortex_r4/ac6/src/tx_thread_fiq_context_save.S index 1d85abe5..3c1333b3 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_r4/ac6/src/tx_thread_fiq_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -76,12 +77,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_fiq_context_save(VOID) */ /* { */ @@ -90,7 +85,7 @@ .type _tx_thread_fiq_context_save, "function" _tx_thread_fiq_context_save: - /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked out, we are in IRQ mode, and all registers are intact. */ /* Check for a nested interrupt condition. */ diff --git a/ports/cortex_r4/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_r4/ac6/src/tx_thread_fiq_nesting_end.S index df8a4633..5abbdddf 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_r4/ac6/src/tx_thread_fiq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -77,12 +78,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_fiq_nesting_end(VOID) */ /* { */ @@ -90,13 +85,13 @@ .type _tx_thread_fiq_nesting_end, "function" _tx_thread_fiq_nesting_end: MOV r3, lr // Save ISR return address - + #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if // Disable IRQ and FIQ interrupts #else CPSID i // Disable IRQ interrupts #endif - + LDMIA sp!, {r1, lr} // Pickup saved lr (and r1 throw-away for // 8-byte alignment logic) CPS #FIQ_MODE // Switch back to FIQ mode diff --git a/ports/cortex_r4/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_r4/ac6/src/tx_thread_fiq_nesting_start.S index f26d9a0c..73564d78 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_r4/ac6/src/tx_thread_fiq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,12 +75,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_fiq_nesting_start(VOID) */ /* { */ diff --git a/ports/cortex_r4/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_r4/ac6/src/tx_thread_interrupt_control.S index 11ab4e4f..83aa06c4 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_r4/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -73,12 +74,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_control(UINT new_posture) */ /* { */ diff --git a/ports/cortex_r4/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_r4/ac6/src/tx_thread_interrupt_disable.S index cd7476a6..d605e034 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_r4/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,12 +66,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_disable(void) */ /* { */ diff --git a/ports/cortex_r4/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_r4/ac6/src/tx_thread_interrupt_restore.S index 8e966de6..f9315d7f 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_r4/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,12 +67,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_restore(UINT old_posture) */ /* { */ diff --git a/ports/cortex_r4/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_r4/ac6/src/tx_thread_irq_nesting_end.S index cf8e0ac1..664e02c5 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_r4/ac6/src/tx_thread_irq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -77,12 +78,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_irq_nesting_end(VOID) */ /* { */ @@ -96,7 +91,7 @@ _tx_thread_irq_nesting_end: #else CPSID i // Disable IRQ interrupts #endif - + LDMIA sp!, {r1, lr} // Pickup saved lr (and r1 throw-away for // 8-byte alignment logic) CPS #IRQ_MODE // Switch back to IRQ mode diff --git a/ports/cortex_r4/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_r4/ac6/src/tx_thread_irq_nesting_start.S index b3ebe405..1d50b484 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_r4/ac6/src/tx_thread_irq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,12 +75,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_irq_nesting_start(VOID) */ /* { */ diff --git a/ports/cortex_r4/ac6/src/tx_thread_schedule.S b/ports/cortex_r4/ac6/src/tx_thread_schedule.S index c12d5442..7148bd9e 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_r4/ac6/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,12 +75,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_schedule(VOID) */ /* { */ diff --git a/ports/cortex_r4/ac6/src/tx_thread_stack_build.S b/ports/cortex_r4/ac6/src/tx_thread_stack_build.S index 9f72ba6c..a2993136 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_r4/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,12 +80,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) */ /* { */ diff --git a/ports/cortex_r4/ac6/src/tx_thread_system_return.S b/ports/cortex_r4/ac6/src/tx_thread_system_return.S index 2c5f11d6..048b4525 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_r4/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -77,12 +78,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_system_return(VOID) */ /* { */ diff --git a/ports/cortex_r4/ac6/src/tx_thread_vectored_context_save.S b/ports/cortex_r4/ac6/src/tx_thread_vectored_context_save.S index de49cc0d..dbb40aba 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_r4/ac6/src/tx_thread_vectored_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -75,12 +76,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_vectored_context_save(VOID) */ /* { */ diff --git a/ports/cortex_r4/ac6/src/tx_timer_interrupt.S b/ports/cortex_r4/ac6/src/tx_timer_interrupt.S index d48313ef..8c3abf90 100644 --- a/ports/cortex_r4/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_r4/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -84,12 +85,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_timer_interrupt(VOID) */ /* { */ diff --git a/ports/cortex_r4/ghs/example_build/tx_initialize_low_level.arm b/ports/cortex_r4/ghs/example_build/tx_initialize_low_level.arm index e9271a0e..212056fb 100644 --- a/ports/cortex_r4/ghs/example_build/tx_initialize_low_level.arm +++ b/ports/cortex_r4/ghs/example_build/tx_initialize_low_level.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r4/ghs/inc/tx_el.h b/ports/cortex_r4/ghs/inc/tx_el.h index b8926921..72e5bbe3 100644 --- a/ports/cortex_r4/ghs/inc/tx_el.h +++ b/ports/cortex_r4/ghs/inc/tx_el.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,12 +37,6 @@ /* EventAnalyzer. It is assumed that tx_api.h and tx_port.h have */ /* already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_EL_H diff --git a/ports/cortex_r4/ghs/inc/tx_port.h b/ports/cortex_r4/ghs/inc/tx_port.h index 8bdac17b..22daf8ea 100644 --- a/ports/cortex_r4/ghs/inc/tx_port.h +++ b/ports/cortex_r4/ghs/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -384,7 +376,7 @@ asm void restore_ints(int a) #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-R4/Green Hills Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R4/Green Hills Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r4/ghs/readme_threadx.txt b/ports/cortex_r4/ghs/readme_threadx.txt index f0fe2220..b7e10db3 100644 --- a/ports/cortex_r4/ghs/readme_threadx.txt +++ b/ports/cortex_r4/ghs/readme_threadx.txt @@ -1,19 +1,19 @@ - Microsoft's Azure RTOS ThreadX for Cortex-R4 + Microsoft's Azure RTOS ThreadX for Cortex-R4 Using the Green Hills Software Tools 1. Open the ThreadX Project Workspace -In order to build the ThreadX library and the ThreadX demonstration first load -the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the -"example_build" directory. +In order to build the ThreadX library and the ThreadX demonstration first load +the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the +"example_build" directory. 2. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply select the MULTI project file -tx.gpj and then select the build button. You should now observe the -compilation and assembly of the ThreadX library. This project build produces +Building the ThreadX library is easy; simply select the MULTI project file +tx.gpj and then select the build button. You should now observe the +compilation and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. @@ -21,55 +21,55 @@ the ThreadX library file tx.a. The ThreadX demonstration is designed to execute under the MULTI environment on the Green Hills Cortex-R4 simulator. The instructions that follow describe -how to get the ThreadX evaluation running under the MULTI Cortex-R4 simulation +how to get the ThreadX evaluation running under the MULTI Cortex-R4 simulation environment. -Building the demonstration is easy; simply select the MULTI project file -sample_threadx.gpj. At this point, select the "Project Build" button and observe -the compilation, assembly, and linkage of the ThreadX demonstration application. +Building the demonstration is easy; simply select the MULTI project file +sample_threadx.gpj. At this point, select the "Project Build" button and observe +the compilation, assembly, and linkage of the ThreadX demonstration application. -After the demonstration is built, invoke the MULTI ARM simulator by selecting -the simulator connection from within the sample_threadx.con connection file. -Once connected to the simulator, select the "Debug" button. You should now -observe the main function of sample_threadx.c. +After the demonstration is built, invoke the MULTI ARM simulator by selecting +the simulator connection from within the sample_threadx.con connection file. +Once connected to the simulator, select the "Debug" button. You should now +observe the main function of sample_threadx.c. At this point, you should setup a simulated timer interrupt for ThreadX by entering "timer 9999 irq" in the "target" window of the debugger. -You are now ready to execute the ThreadX demonstration system. Select -breakpoints and data watches to observe the execution of the sample_threadx.c +You are now ready to execute the ThreadX demonstration system. Select +breakpoints and data watches to observe the execution of the sample_threadx.c application. 4. EventAnalyzer Demonstration -To build a demonstration system that also logs events for the MULTI EventAnalyzer, -perform the same steps as the regular demo, except build the ThreadX library with -txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. -The resulting image will log all system events, which can then be displayed by the +To build a demonstration system that also logs events for the MULTI EventAnalyzer, +perform the same steps as the regular demo, except build the ThreadX library with +txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. +The resulting image will log all system events, which can then be displayed by the MULTI EventAnalyzer. 5. System Initialization -The system entry point using the Green Hills tools is at the label _start. -This is defined within the crt0.arm file supplied by Green Hills. In addition, -this is where all static and global preset C variable initialization +The system entry point using the Green Hills tools is at the label _start. +This is defined within the crt0.arm file supplied by Green Hills. In addition, +this is where all static and global preset C variable initialization processing is called from. After the Green Hills startup function returns, ThreadX initialization is called. The main initialization function is _tx_initialize_low_level and -is located in the file tx_initialize_low_level.arm. This function is responsible -for setting up various system data structures, interrupt vectors, and the +is located in the file tx_initialize_low_level.arm. This function is responsible +for setting up various system data structures, interrupt vectors, and the periodic timer interrupt source of ThreadX. -In addition, _tx_initialize_low_level determines where the first available +In addition, _tx_initialize_low_level determines where the first available RAM memory address is located. This address is supplied to tx_application_define. -By default, the first available RAM memory address is assumed to start at the -beginning of the ThreadX section .free_mem. If changes are made to the -sample_threadx.ld file, the .free_mem section should remain the last allocated -section in the main RAM area. The starting address of this section is passed +By default, the first available RAM memory address is assumed to start at the +beginning of the ThreadX section .free_mem. If changes are made to the +sample_threadx.ld file, the .free_mem section should remain the last allocated +section in the main RAM area. The starting address of this section is passed to tx_application_define. @@ -87,27 +87,27 @@ The following defines and their associated action are as follows: TX_ENABLE_FIQ_NESTING If defined, this brings in special FIQ interrupt nesting logic into the ThreadX library. This define should be applied - to the entire ThreadX library and the + to the entire ThreadX library and the define TX_ENABLE_FIQ_SUPPORT should also be defined. TX_ENABLE_FIQ_SUPPORT If defined, this brings in FIQ context save and restore logic necessary for applications to call ThreadX services from - FIQ interrupt handlers. This define - should be applied to the entire ThreadX + FIQ interrupt handlers. This define + should be applied to the entire ThreadX library. TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 4 in the "ThreadX User Guide" + Chapter 4 in the "ThreadX User Guide" for more details. TX_ENABLE_EVENT_LOGGING This define enables event logging for any or all of the ThreadX source code. If this - option is used anywhere, the tx_initialize_high_level.c + option is used anywhere, the tx_initialize_high_level.c file must be compiled with it as well, since this is where the event log is initialized. @@ -119,121 +119,121 @@ The following defines and their associated action are as follows: If this is enabled, run-time filtering logic is added to the event logging code. - TX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. 7. Register Usage and Stack Frames -The Green Hills compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) -are scratch registers for each function. All other registers used by a C -function must be preserved by the function. ThreadX takes advantage of this -in situations where a context switch happens as a result of making a ThreadX -service call (which is itself a C function). In such cases, the saved +The Green Hills compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) +are scratch registers for each function. All other registers used by a C +function must be preserved by the function. ThreadX takes advantage of this +in situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -251,40 +251,40 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 8. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make ThreadX run faster, you can change the tx.gpj project -to disable debug information and enable the desired optimizations. +to disable debug information and enable the desired optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined before tx_api.h is included. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. 9. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-R4 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 9.1 Vector Area The Cortex-R4 vectors start at address zero. The demonstration system reset.arm -file contains the reset section (which contains all the ARM vectors) and is +file contains the reset section (which contains all the ARM vectors) and is typically loaded at address zero. On actual hardware platforms, this section -might have to be copied to address 0. +might have to be copied to address 0. 9.2 IRQ ISRs @@ -294,13 +294,13 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 9.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.arm: .globl __tx_irq_handler - .globl __tx_irq_processing_return + .globl __tx_irq_processing_return __tx_irq_handler: /* Jump to context save to save system context. */ @@ -308,7 +308,7 @@ __tx_irq_handler: __tx_irq_processing_return: /* At this point execution is still in the IRQ mode. The CPSR, point of - interrupt, and all C scratch registers are available for use. Note + interrupt, and all C scratch registers are available for use. Note that IRQ interrupts are still disabled upon return from the context save function. */ @@ -321,7 +321,7 @@ __tx_irq_processing_return: 9.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.arm: .globl __tx_irq_example_handler @@ -331,12 +331,12 @@ __tx_irq_example_handler: STMDB sp!, {r0-r3} # Save some scratch registers MRS r0, SPSR # Pickup saved SPSR - SUB lr, lr, #4 # Adjust point of interrupt + SUB lr, lr, #4 # Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} # Store other scratch registers BL _tx_thread_vectored_context_save # Call the vectored IRQ context save /* At this point execution is still in the IRQ mode. The CPSR, point of - interrupt, and all C scratch registers are available for use. Note + interrupt, and all C scratch registers are available for use. Note that IRQ interrupts are still disabled upon return from the context save function. */ @@ -353,22 +353,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.arm. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables nesting -by disabling IRQ interrupts and switching back to IRQ mode in preparation for +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.arm. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables nesting +by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in the +The following is an example of enabling IRQ nested interrupts in the typical IRQ handler: .globl __tx_irq_handler - .globl __tx_irq_processing_return + .globl __tx_irq_processing_return __tx_irq_handler: /* Jump to context save to save system context. */ @@ -376,10 +376,10 @@ __tx_irq_handler: __tx_irq_processing_return: /* Enable nested IRQ interrupts. NOTE: Since this service returns - with IRQ interrupts enabled, all IRQ interrupt sources must be + with IRQ interrupts enabled, all IRQ interrupt sources must be cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start - + /* Application ISR call(s) go here! */ /* Disable nested IRQ interrupts. The mode is switched back to @@ -392,9 +392,9 @@ __tx_irq_processing_return: 9.3 FIQ Interrupts -By default, Cortex-R4 FIQ interrupts are left completely enabled by ThreadX. -Of course, this means that the application is fully responsible for -saving/restoring any registers used in the FIQ ISR processing. In addition, +By default, Cortex-R4 FIQ interrupts are left completely enabled by ThreadX. +Of course, this means that the application is fully responsible for +saving/restoring any registers used in the FIQ ISR processing. In addition, no ThreadX service calls are allowed from the default FIQ ISRs. The default FIQ interrupt shell is located in tx_initialize_low_level.arm. @@ -403,7 +403,7 @@ FIQ interrupt shell is located in tx_initialize_low_level.arm. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.arm: @@ -431,18 +431,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.arm. When nested FIQ interrupts are no longer -required, calling the _tx_thread_fiq_nesting_end service disables nesting by -disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.arm. When nested FIQ interrupts are no longer +required, calling the _tx_thread_fiq_nesting_end service disables nesting by +disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -458,7 +458,7 @@ __tx_fiq_processing_return: interrupt, and all C scratch registers are available for use. */ /* Enable nested FIQ interrupts. NOTE: Since this service returns - with FIQ interrupts enabled, all FIQ interrupt sources must be + with FIQ interrupts enabled, all FIQ interrupt sources must be cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start @@ -475,22 +475,22 @@ __tx_fiq_processing_return: 10. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.arm. 11. Thumb/Cortex-R4 Mixed Mode -By default, ThreadX is setup for running in Cortex-R4 32-bit mode. This is -also true for the demonstration system. It is possible to build any +By default, ThreadX is setup for running in Cortex-R4 32-bit mode. This is +also true for the demonstration system. It is possible to build any ThreadX file and/or the application in Thumb mode. The only exception -to this is the file tx_thread_shell_entry.c. This file must always be +to this is the file tx_thread_shell_entry.c. This file must always be built in 32-bit mode. @@ -503,7 +503,7 @@ information associated with this specific port of ThreadX: 04-02-2021 Release 6.1.6 changes: tx_port.h Updated macro definition -05/19/2020 Initial ThreadX version of Cortex-R4/Green Hills port. +05/19/2020 Initial ThreadX version of Cortex-R4/Green Hills port. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_r4/ghs/src/tx_el.c b/ports/cortex_r4/ghs/src/tx_el.c index 365622cd..b5d3b8b7 100644 --- a/ports/cortex_r4/ghs/src/tx_el.c +++ b/ports/cortex_r4/ghs/src/tx_el.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,12 +83,6 @@ UINT _tx_thread_interrupt_control(UINT new_posture); /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_el_initialize(VOID) { diff --git a/ports/cortex_r4/ghs/src/tx_thread_context_restore.arm b/ports/cortex_r4/ghs/src/tx_thread_context_restore.arm index 75450de7..6e9ef7d7 100644 --- a/ports/cortex_r4/ghs/src/tx_thread_context_restore.arm +++ b/ports/cortex_r4/ghs/src/tx_thread_context_restore.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r4/ghs/src/tx_thread_context_save.arm b/ports/cortex_r4/ghs/src/tx_thread_context_save.arm index 416edebc..adf474ce 100644 --- a/ports/cortex_r4/ghs/src/tx_thread_context_save.arm +++ b/ports/cortex_r4/ghs/src/tx_thread_context_save.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r4/ghs/src/tx_thread_fiq_context_restore.arm b/ports/cortex_r4/ghs/src/tx_thread_fiq_context_restore.arm index bdee5905..c41f5217 100644 --- a/ports/cortex_r4/ghs/src/tx_thread_fiq_context_restore.arm +++ b/ports/cortex_r4/ghs/src/tx_thread_fiq_context_restore.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r4/ghs/src/tx_thread_fiq_context_save.arm b/ports/cortex_r4/ghs/src/tx_thread_fiq_context_save.arm index d60d4174..e51721ff 100644 --- a/ports/cortex_r4/ghs/src/tx_thread_fiq_context_save.arm +++ b/ports/cortex_r4/ghs/src/tx_thread_fiq_context_save.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r4/ghs/src/tx_thread_fiq_nesting_end.arm b/ports/cortex_r4/ghs/src/tx_thread_fiq_nesting_end.arm index fe229cd5..606bb33b 100644 --- a/ports/cortex_r4/ghs/src/tx_thread_fiq_nesting_end.arm +++ b/ports/cortex_r4/ghs/src/tx_thread_fiq_nesting_end.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r4/ghs/src/tx_thread_fiq_nesting_start.arm b/ports/cortex_r4/ghs/src/tx_thread_fiq_nesting_start.arm index 2c81a48c..a79e0ef1 100644 --- a/ports/cortex_r4/ghs/src/tx_thread_fiq_nesting_start.arm +++ b/ports/cortex_r4/ghs/src/tx_thread_fiq_nesting_start.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r4/ghs/src/tx_thread_interrupt_control.arm b/ports/cortex_r4/ghs/src/tx_thread_interrupt_control.arm index ad438998..21642ef3 100644 --- a/ports/cortex_r4/ghs/src/tx_thread_interrupt_control.arm +++ b/ports/cortex_r4/ghs/src/tx_thread_interrupt_control.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r4/ghs/src/tx_thread_interrupt_disable.arm b/ports/cortex_r4/ghs/src/tx_thread_interrupt_disable.arm index 14fc9798..8fef75d1 100644 --- a/ports/cortex_r4/ghs/src/tx_thread_interrupt_disable.arm +++ b/ports/cortex_r4/ghs/src/tx_thread_interrupt_disable.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r4/ghs/src/tx_thread_interrupt_restore.arm b/ports/cortex_r4/ghs/src/tx_thread_interrupt_restore.arm index 01794ebb..145588da 100644 --- a/ports/cortex_r4/ghs/src/tx_thread_interrupt_restore.arm +++ b/ports/cortex_r4/ghs/src/tx_thread_interrupt_restore.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r4/ghs/src/tx_thread_irq_nesting_end.arm b/ports/cortex_r4/ghs/src/tx_thread_irq_nesting_end.arm index 9c0dfe53..60b91854 100644 --- a/ports/cortex_r4/ghs/src/tx_thread_irq_nesting_end.arm +++ b/ports/cortex_r4/ghs/src/tx_thread_irq_nesting_end.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r4/ghs/src/tx_thread_irq_nesting_start.arm b/ports/cortex_r4/ghs/src/tx_thread_irq_nesting_start.arm index d83340e3..e132b877 100644 --- a/ports/cortex_r4/ghs/src/tx_thread_irq_nesting_start.arm +++ b/ports/cortex_r4/ghs/src/tx_thread_irq_nesting_start.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r4/ghs/src/tx_thread_schedule.arm b/ports/cortex_r4/ghs/src/tx_thread_schedule.arm index 38b6d693..a902fef1 100644 --- a/ports/cortex_r4/ghs/src/tx_thread_schedule.arm +++ b/ports/cortex_r4/ghs/src/tx_thread_schedule.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r4/ghs/src/tx_thread_stack_build.arm b/ports/cortex_r4/ghs/src/tx_thread_stack_build.arm index a6de7389..6bb4de3c 100644 --- a/ports/cortex_r4/ghs/src/tx_thread_stack_build.arm +++ b/ports/cortex_r4/ghs/src/tx_thread_stack_build.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r4/ghs/src/tx_thread_system_return.arm b/ports/cortex_r4/ghs/src/tx_thread_system_return.arm index ea2fe6bb..3e4c34b0 100644 --- a/ports/cortex_r4/ghs/src/tx_thread_system_return.arm +++ b/ports/cortex_r4/ghs/src/tx_thread_system_return.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r4/ghs/src/tx_thread_vectored_context_save.arm b/ports/cortex_r4/ghs/src/tx_thread_vectored_context_save.arm index 18c844f4..764ee154 100644 --- a/ports/cortex_r4/ghs/src/tx_thread_vectored_context_save.arm +++ b/ports/cortex_r4/ghs/src/tx_thread_vectored_context_save.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r4/ghs/src/tx_timer_interrupt.arm b/ports/cortex_r4/ghs/src/tx_timer_interrupt.arm index b7303701..e6c8ac0e 100644 --- a/ports/cortex_r4/ghs/src/tx_timer_interrupt.arm +++ b/ports/cortex_r4/ghs/src/tx_timer_interrupt.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r4/gnu/example_build/crt0.S b/ports/cortex_r4/gnu/example_build/crt0.S index aa0f3239..56b6c958 100644 --- a/ports/cortex_r4/gnu/example_build/crt0.S +++ b/ports/cortex_r4/gnu/example_build/crt0.S @@ -26,13 +26,13 @@ _mainCRTStartup: mov a2, #0 /* Second arg: fill value */ mov fp, a2 /* Null frame pointer */ mov r7, a2 /* Null frame pointer for Thumb */ - - ldr a1, .LC1 /* First arg: start of memory block */ - ldr a3, .LC2 - sub a3, a3, a1 /* Third arg: length of block */ - - + ldr a1, .LC1 /* First arg: start of memory block */ + ldr a3, .LC2 + sub a3, a3, a1 /* Third arg: length of block */ + + + bl memset mov r0, #0 /* no arguments */ mov r1, #0 /* no argv either */ @@ -48,15 +48,15 @@ _mainCRTStartup: /* bl init */ mov r0, r4 mov r1, r5 -#endif +#endif bl main bl exit /* Should not return. */ - - /* For Thumb, constants must be after the code since only + + /* For Thumb, constants must be after the code since only positive offsets are supported for PC relative addresses. */ - + .align 0 .LC0: .LC1: diff --git a/ports/cortex_r4/gnu/example_build/reset.S b/ports/cortex_r4/gnu/example_build/reset.S index a11c826a..5d05258b 100644 --- a/ports/cortex_r4/gnu/example_build/reset.S +++ b/ports/cortex_r4/gnu/example_build/reset.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Initialize */ @/** */ @@ -65,11 +65,11 @@ SWI: .word __tx_swi_interrupt @ Software interrupt handler PREFETCH: .word __tx_prefetch_handler @ Prefetch exception handler -ABORT: +ABORT: .word __tx_abort_handler @ Abort exception handler -RESERVED: +RESERVED: .word __tx_reserved_handler @ Reserved exception handler -IRQ: +IRQ: .word __tx_irq_handler @ IRQ interrupt handler FIQ: .word __tx_fiq_handler @ FIQ interrupt handler diff --git a/ports/cortex_r4/gnu/example_build/sample_threadx.c b/ports/cortex_r4/gnu/example_build/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports/cortex_r4/gnu/example_build/sample_threadx.c +++ b/ports/cortex_r4/gnu/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_r4/gnu/example_build/sample_threadx.ld b/ports/cortex_r4/gnu/example_build/sample_threadx.ld index 3dea4e1c..e940b2b8 100644 --- a/ports/cortex_r4/gnu/example_build/sample_threadx.ld +++ b/ports/cortex_r4/gnu/example_build/sample_threadx.ld @@ -7,7 +7,7 @@ OUTPUT_ARCH(arm) SECTIONS { . = 0x00000000; - + .vectors : {reset.o(.text) } /* Read-only sections, merged into text segment: */ @@ -94,8 +94,8 @@ SECTIONS *(.gnu.linkonce.t*) *(.glue_7t) *(.glue_7) } =0 - .init : - { + .init : + { KEEP (*(.init)) } =0 _etext = .; @@ -120,7 +120,7 @@ SECTIONS .data1 : { *(.data1) } .eh_frame : { KEEP (*(.eh_frame)) } .gcc_except_table : { *(.gcc_except_table) } - .ctors : + .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is @@ -153,9 +153,9 @@ SECTIONS /* We want the small data sections together, so single-instruction offsets can access them all, and initialized data all before uninitialized, so we can shorten the on-disk segment size. */ - .sdata : + .sdata : { - *(.sdata) + *(.sdata) *(.sdata.*) *(.gnu.linkonce.s.*) } @@ -191,7 +191,7 @@ SECTIONS _stack_bottom = ABSOLUTE(.) ; - /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and + /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and SYS stack if nested interrupts are enabled. */ . = ALIGN(8) ; . += 4096 ; diff --git a/ports/cortex_r4/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_r4/gnu/example_build/tx_initialize_low_level.S index 82304d36..1abcf7f5 100644 --- a/ports/cortex_r4/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_r4/gnu/example_build/tx_initialize_low_level.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Initialize */ @/** */ @@ -62,7 +62,7 @@ SYS_STACK_SIZE = 1024 @ System stack size .type $_tx_initialize_low_level,function $_tx_initialize_low_level: BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_initialize_low_level @ Call _tx_initialize_low_level function @@ -72,45 +72,39 @@ $_tx_initialize_low_level: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_initialize_low_level Cortex-R4/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level Cortex-R4/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is responsible for any low-level processor */ -@/* initialization, including setting up interrupt vectors, setting */ -@/* up a periodic timer interrupt source, saving the system stack */ -@/* pointer for use in ISR processing later, and finding the first */ -@/* available RAM memory address for tx_application_define. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_initialize_kernel_enter ThreadX entry function */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) @@ -125,7 +119,7 @@ _tx_initialize_low_level: @ LDR r1, =_sp @ Get pointer to stack area -#ifdef TX_ENABLE_IRQ_NESTING +#ifdef TX_ENABLE_IRQ_NESTING @ @ /* Setup the system mode stack for nested interrupt support */ @ @@ -156,7 +150,7 @@ _tx_initialize_low_level: MSR CPSR, r0 @ Enter SVC mode LDR r2, =_stack_bottom @ Pickup stack bottom CMP r3, r2 @ Compare the current stack end with the bottom -_stack_error_loop: +_stack_error_loop: BLT _stack_error_loop @ If the IRQ stack exceeds the stack bottom, just sit here! @ @ /* Save the system stack pointer. */ @@ -208,7 +202,7 @@ __tx_reserved_handler: B __tx_reserved_handler @ Reserved exception handler @ .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -216,17 +210,17 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. In +@ interrupt, and all C scratch registers are available for use. In @ addition, IRQ interrupts may be re-enabled - with certain restrictions - @ if nested IRQ interrupts are desired. Interrupts may be re-enabled over -@ small code sequences where lr is saved before enabling interrupts and +@ small code sequences where lr is saved before enabling interrupts and @ restored after interrupts are again disabled. */ @ -@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start @ from IRQ mode with interrupts disabled. This routine switches to the -@ system mode and returns with IRQ interrupts enabled. -@ -@ NOTE: It is very important to ensure all IRQ interrupts are cleared +@ system mode and returns with IRQ interrupts enabled. +@ +@ NOTE: It is very important to ensure all IRQ interrupts are cleared @ prior to enabling nested IRQ interrupts. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -240,7 +234,7 @@ __tx_irq_processing_return: @ @ @ /* If interrupt nesting was started earlier, the end of interrupt nesting -@ service must be called before returning to _tx_thread_context_restore. +@ service must be called before returning to _tx_thread_context_restore. @ This routine returns in processing in IRQ mode with interrupts disabled. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -256,28 +250,28 @@ __tx_irq_processing_return: @__tx_example_vectored_irq_handler: @ @ -@ /* Save initial context and call context save to prepare for +@ /* Save initial context and call context save to prepare for @ vectored ISR execution. */ @ @ STMDB sp!, {r0-r3} @ Save some scratch registers @ MRS r0, SPSR @ Pickup saved SPSR -@ SUB lr, lr, #4 @ Adjust point of interrupt +@ SUB lr, lr, #4 @ Adjust point of interrupt @ STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers @ BL _tx_thread_vectored_context_save @ Vectored context save @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. In +@ interrupt, and all C scratch registers are available for use. In @ addition, IRQ interrupts may be re-enabled - with certain restrictions - @ if nested IRQ interrupts are desired. Interrupts may be re-enabled over -@ small code sequences where lr is saved before enabling interrupts and +@ small code sequences where lr is saved before enabling interrupts and @ restored after interrupts are again disabled. */ @ @ -@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start @ from IRQ mode with interrupts disabled. This routine switches to the -@ system mode and returns with IRQ interrupts enabled. -@ -@ NOTE: It is very important to ensure all IRQ interrupts are cleared +@ system mode and returns with IRQ interrupts enabled. +@ +@ NOTE: It is very important to ensure all IRQ interrupts are cleared @ prior to enabling nested IRQ interrupts. */ @#ifdef TX_ENABLE_IRQ_NESTING @ BL _tx_thread_irq_nesting_start @@ -286,7 +280,7 @@ __tx_irq_processing_return: @ /* Application IRQ handlers can be called here! */ @ @ /* If interrupt nesting was started earlier, the end of interrupt nesting -@ service must be called before returning to _tx_thread_context_restore. +@ service must be called before returning to _tx_thread_context_restore. @ This routine returns in processing in IRQ mode with interrupts disabled. */ @#ifdef TX_ENABLE_IRQ_NESTING @ BL _tx_thread_irq_nesting_end @@ -308,11 +302,11 @@ __tx_fiq_processing_return: @ /* At this point execution is still in the FIQ mode. The CPSR, point of @ interrupt, and all C scratch registers are available for use. */ @ -@ /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +@ /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start @ from FIQ mode with interrupts disabled. This routine switches to the -@ system mode and returns with FIQ interrupts enabled. +@ system mode and returns with FIQ interrupts enabled. @ -@ NOTE: It is very important to ensure all FIQ interrupts are cleared +@ NOTE: It is very important to ensure all FIQ interrupts are cleared @ prior to enabling nested FIQ interrupts. */ #ifdef TX_ENABLE_FIQ_NESTING BL _tx_thread_fiq_nesting_start diff --git a/ports/cortex_r4/gnu/inc/tx_port.h b/ports/cortex_r4/gnu/inc/tx_port.h index ec22b11a..827590c9 100644 --- a/ports/cortex_r4/gnu/inc/tx_port.h +++ b/ports/cortex_r4/gnu/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Cortex-R4/GNU */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-R4/GNU */ /* 6.1.12 */ /* */ /* AUTHOR */ @@ -32,27 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 07-29-2022 Scott Larson Updated comments, removed */ -/* unneeded temp variable, */ -/* resulting in version 6.1.12 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -65,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -78,7 +67,7 @@ #include -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -114,12 +103,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -129,8 +118,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -177,7 +166,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -189,13 +178,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -209,11 +198,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -221,8 +210,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -249,24 +238,24 @@ typedef unsigned short USHORT; #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ - + #if __TARGET_ARCH_ARM > 4 #ifndef __thumb__ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ asm volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); \ - b = 31 - b; + b = 31 - b; #endif #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -310,8 +299,8 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-R4/GNU Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R4/GNU Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r4/gnu/readme_threadx.txt b/ports/cortex_r4/gnu/readme_threadx.txt index 06712f8a..93d69abb 100644 --- a/ports/cortex_r4/gnu/readme_threadx.txt +++ b/ports/cortex_r4/gnu/readme_threadx.txt @@ -1,55 +1,55 @@ - Microsoft's Azure RTOS ThreadX for Cortex-R4 + Microsoft's Azure RTOS ThreadX for Cortex-R4 Using the GNU Tools 1. Building the ThreadX run-time Library -First make sure you are in the "example_build" directory. Also, make sure that -you have setup your path and other environment variables necessary for the GNU -development environment. +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the GNU +development environment. -At this point you may run the build_threadx.bat batch file. This will build the -ThreadX run-time environment in the "example_build" directory. +At this point you may run the build_threadx.bat batch file. This will build the +ThreadX run-time environment in the "example_build" directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. 2. Demonstration System -Building the demonstration is easy; simply execute the build_threadx_sample.bat -batch file while inside the "example_build" directory. +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with TX.A. The resulting file DEMO is a binary file +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with TX.A. The resulting file DEMO is a binary file that can be downloaded and executed. 3. System Initialization -The entry point in ThreadX for the Cortex-R4 using GNU tools is at label _start. +The entry point in ThreadX for the Cortex-R4 using GNU tools is at label _start. This is defined within the modified version of the GNU startup code - crt0.S. -The ThreadX tx_initialize_low_level.S file is responsible for setting up various -system data structures, the interrupt vectors, and a periodic timer interrupt source. -By default, the vector area is defined to be located at the "__vectors" label, -which is defined in reset.S. This area is typically located at 0. In situations -where this is impossible, the vectors at the "__vectors" label should be copied +The ThreadX tx_initialize_low_level.S file is responsible for setting up various +system data structures, the interrupt vectors, and a periodic timer interrupt source. +By default, the vector area is defined to be located at the "__vectors" label, +which is defined in reset.S. This area is typically located at 0. In situations +where this is impossible, the vectors at the "__vectors" label should be copied to address 0. -This is also where initialization of a periodic timer interrupt source should take +This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level defines the first available address -for use by the application, which is supplied as the sole input parameter +In addition, _tx_initialize_low_level defines the first available address +for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 4. Assembler / Compiler Switches -The following are compiler switches used in building the demonstration +The following are compiler switches used in building the demonstration system: Compiler/Assembler Meaning @@ -73,164 +73,164 @@ Application Defines ( -D option) ThreadX assembly files. If used, it should be used on all assembly files and the generic C source of - ThreadX should be compiled with + ThreadX should be compiled with TX_ENABLE_FIQ_SUPPORT defined as well. TX_ENABLE_IRQ_NESTING This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.S. TX_ENABLE_FIQ_NESTING This assembler define enables FIQ - nested support. If FIQ nested + nested support. If FIQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.S. In addition, IRQ nesting should also be enabled. TX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ interrupt handling in the ThreadX - generic C source. This define + generic C source. This define should also be used in conjunction with the corresponding assembler - define. + define. TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - TX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. 5. Register Usage and Stack Frames -The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -248,52 +248,52 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-R4 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-R4 vectors start at address zero. The demonstration system startup -reset.S file contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +reset.S file contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs -ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -301,7 +301,7 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -314,7 +314,7 @@ __tx_irq_processing_return: 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_example_handler @@ -324,12 +324,12 @@ __tx_irq_example_handler: STMDB sp!, {r0-r3} @ Save some scratch registers MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers BL _tx_thread_vectored_context_save @ Call the vectored IRQ context save @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -346,22 +346,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.S. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables -nesting by disabling IRQ interrupts and switching back to IRQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -369,10 +369,10 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* Enable nested IRQ interrupts. NOTE: Since this service returns -@ with IRQ interrupts enabled, all IRQ interrupt sources must be +@ with IRQ interrupts enabled, all IRQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start -@ +@ @ /* Application ISR call(s) go here! */ @ @ /* Disable nested IRQ interrupts. The mode is switched back to @@ -385,12 +385,12 @@ __tx_irq_processing_return: 7.3 FIQ Interrupts -By default, FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.S. @@ -399,7 +399,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.S. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.S: @@ -427,18 +427,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.S. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -454,7 +454,7 @@ __tx_fiq_processing_return: @ interrupt, and all C scratch registers are available for use. */ @ @ /* Enable nested FIQ interrupts. NOTE: Since this service returns -@ with FIQ interrupts enabled, all FIQ interrupt sources must be +@ with FIQ interrupts enabled, all FIQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start @ @@ -470,12 +470,12 @@ __tx_fiq_processing_return: 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer -interrupt source, these services are not functional but the remainder of +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of ThreadX will still run. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.S for the demonstration system. diff --git a/ports/cortex_r4/gnu/src/tx_thread_context_restore.S b/ports/cortex_r4/gnu/src/tx_thread_context_restore.S index b56b9d83..aab6ce05 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_r4/gnu/src/tx_thread_context_restore.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -43,48 +43,42 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @ @/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore @ since it will never be called 16-bit mode. */ -@ +@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_context_restore Cortex-R4/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore Cortex-R4/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function restores the interrupt context if it is processing a */ -@/* nested interrupt. If not, it returns to the interrupt thread if no */ -@/* preemption is necessary. Otherwise, if preemption is necessary or */ -@/* if no thread was running, the function returns to the scheduler. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling routine */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs Interrupt Service Routines */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) @@ -115,13 +109,13 @@ _tx_thread_context_restore: LDR r3, =_tx_thread_system_state @ Pickup address of system state variable LDR r2, [r3] @ Pickup system state SUB r2, r2, #1 @ Decrement the counter - STR r2, [r3] @ Store the counter + STR r2, [r3] @ Store the counter CMP r2, #0 @ Was this the first interrupt? BEQ __tx_thread_not_nested_restore @ If so, not a nested restore @ @ /* Interrupts are nested. */ @ -@ /* Just recover the saved registers and return to the point of +@ /* Just recover the saved registers and return to the point of @ interrupt. */ @ LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs diff --git a/ports/cortex_r4/gnu/src/tx_thread_context_save.S b/ports/cortex_r4/gnu/src/tx_thread_context_save.S index 1dfb9ecd..8533f8b9 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_r4/gnu/src/tx_thread_context_save.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -30,47 +30,41 @@ @ @/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save @ since it will never be called 16-bit mode. */ -@ +@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_context_save Cortex-R4/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save Cortex-R4/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function saves the context of an executing thread in the */ -@/* beginning of interrupt processing. The function also ensures that */ -@/* the system stack is used upon return to the calling ISR. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) @@ -86,7 +80,7 @@ _tx_thread_context_save: @ if (_tx_thread_system_state++) @ { @ - STMDB sp!, {r0-r3} @ Save some working registers + STMDB sp!, {r0-r3} @ Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if @ Disable FIQ interrupts #endif @@ -104,7 +98,7 @@ _tx_thread_context_save: @ calling ISR. */ @ MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other registers @ @ /* Return to the ISR. */ @@ -120,7 +114,7 @@ _tx_thread_context_save: POP {lr} @ Recover ISR lr #endif - B __tx_irq_processing_return @ Continue IRQ processing + B __tx_irq_processing_return @ Continue IRQ processing @ __tx_thread_not_nested_save: @ } @@ -134,13 +128,13 @@ __tx_thread_not_nested_save: LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr LDR r0, [r1] @ Pickup current thread pointer CMP r0, #0 @ Is it NULL? - BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in @ scheduling loop - nothing needs saving! @ @ /* Save minimal context of interrupted thread. */ @ MRS r2, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} @ Store other registers @ @ /* Save the current stack pointer in the thread's control block. */ @@ -160,7 +154,7 @@ __tx_thread_not_nested_save: POP {lr} @ Recover ISR lr #endif - B __tx_irq_processing_return @ Continue IRQ processing + B __tx_irq_processing_return @ Continue IRQ processing @ @ } @ else @@ -170,7 +164,7 @@ __tx_thread_idle_system_save: @ @ /* Interrupt occurred in the scheduling loop. */ @ -@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ @ processing. */ @ MOV r10, #0 @ Clear stack limit @@ -185,7 +179,7 @@ __tx_thread_idle_system_save: #endif ADD sp, sp, #16 @ Recover saved registers - B __tx_irq_processing_return @ Continue IRQ processing + B __tx_irq_processing_return @ Continue IRQ processing @ @ } @} diff --git a/ports/cortex_r4/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_r4/gnu/src/tx_thread_fiq_context_restore.S index 6e0212c9..bf7f2de3 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_r4/gnu/src/tx_thread_fiq_context_restore.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -24,7 +24,7 @@ SVC_MODE = 0xD3 @ SVC mode FIQ_MODE = 0xD1 @ FIQ mode -MODE_MASK = 0x1F @ Mode mask +MODE_MASK = 0x1F @ Mode mask THUMB_MASK = 0x20 @ Thumb bit mask IRQ_MODE_BITS = 0x12 @ IRQ mode bits @ @@ -45,44 +45,38 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_fiq_context_restore Cortex-R4/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_restore Cortex-R4/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function restores the fiq interrupt context when processing a */ -@/* nested interrupt. If not, it returns to the interrupt thread if no */ -@/* preemption is necessary. Otherwise, if preemption is necessary or */ -@/* if no thread was running, the function returns to the scheduler. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling routine */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* FIQ ISR Interrupt Service Routines */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function restores the fiq interrupt context when processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* FIQ ISR Interrupt Service Routines */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_context_restore(VOID) @@ -109,13 +103,13 @@ _tx_thread_fiq_context_restore: LDR r3, =_tx_thread_system_state @ Pickup address of system state variable LDR r2, [r3] @ Pickup system state SUB r2, r2, #1 @ Decrement the counter - STR r2, [r3] @ Store the counter + STR r2, [r3] @ Store the counter CMP r2, #0 @ Was this the first interrupt? BEQ __tx_thread_fiq_not_nested_restore @ If so, not a nested restore @ @ /* Interrupts are nested. */ @ -@ /* Just recover the saved registers and return to the point of +@ /* Just recover the saved registers and return to the point of @ interrupt. */ @ LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs @@ -203,7 +197,7 @@ __tx_thread_fiq_preempt_restore: BEQ __tx_thread_fiq_dont_save_ts @ No, don't save it @ @ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; -@ _tx_timer_time_slice = 0; +@ _tx_timer_time_slice = 0; @ STR r2, [r0, #24] @ Save thread's time-slice MOV r2, #0 @ Clear value diff --git a/ports/cortex_r4/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_r4/gnu/src/tx_thread_fiq_context_save.S index 330bb9d5..4b3b9f4f 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_r4/gnu/src/tx_thread_fiq_context_save.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -34,43 +34,37 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_fiq_context_save Cortex-R4/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_save Cortex-R4/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function saves the context of an executing thread in the */ -@/* beginning of interrupt processing. The function also ensures that */ -@/* the system stack is used upon return to the calling ISR. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @ VOID _tx_thread_fiq_context_save(VOID) @@ -86,7 +80,7 @@ _tx_thread_fiq_context_save: @ if (_tx_thread_system_state++) @ { @ - STMDB sp!, {r0-r3} @ Save some working registers + STMDB sp!, {r0-r3} @ Save some working registers LDR r3, =_tx_thread_system_state @ Pickup address of system state variable LDR r2, [r3] @ Pickup system state CMP r2, #0 @ Is this the first interrupt? @@ -101,7 +95,7 @@ _tx_thread_fiq_context_save: @ calling ISR. */ @ MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other registers @ @ /* Return to the ISR. */ @@ -117,38 +111,38 @@ _tx_thread_fiq_context_save: POP {lr} @ Recover ISR lr #endif - B __tx_fiq_processing_return @ Continue FIQ processing + B __tx_fiq_processing_return @ Continue FIQ processing @ __tx_thread_fiq_not_nested_save: -@ } +@ } @ @ /* Otherwise, not nested, check to see if a thread was running. */ @ else if (_tx_thread_current_ptr) -@ { +@ { @ ADD r2, r2, #1 @ Increment the interrupt counter STR r2, [r3] @ Store it back in the variable LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr LDR r0, [r1] @ Pickup current thread pointer CMP r0, #0 @ Is it NULL? - BEQ __tx_thread_fiq_idle_system_save @ If so, interrupt occurred in -@ @ scheduling loop - nothing needs saving! + BEQ __tx_thread_fiq_idle_system_save @ If so, interrupt occurred in +@ @ scheduling loop - nothing needs saving! @ @ /* Save minimal context of interrupted thread. */ @ MRS r2, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r2, lr} @ Store other registers, Note that we don't -@ @ need to save sl and ip since FIQ has -@ @ copies of these registers. Nested +@ @ need to save sl and ip since FIQ has +@ @ copies of these registers. Nested @ @ interrupt processing does need to save @ @ these registers. @ @ /* Save the current stack pointer in the thread's control block. */ -@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; @ @ /* Switch to the system stack. */ -@ sp = _tx_thread_system_stack_ptr; +@ sp = _tx_thread_system_stack_ptr; @ MOV r10, #0 @ Clear stack limit @@ -161,7 +155,7 @@ __tx_thread_fiq_not_nested_save: POP {lr} @ Recover ISR lr #endif - B __tx_fiq_processing_return @ Continue FIQ processing + B __tx_fiq_processing_return @ Continue FIQ processing @ @ } @ else @@ -181,16 +175,16 @@ __tx_thread_fiq_idle_system_save: #endif @ @ /* Not much to do here, save the current SPSR and LR for possible -@ use in IRQ interrupted in idle system conditions, and return to +@ use in IRQ interrupted in idle system conditions, and return to @ FIQ interrupt processing. */ @ MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, lr} @ Store other registers that will get used -@ @ or stripped off the stack in context -@ @ restore - B __tx_fiq_processing_return @ Continue FIQ processing +@ @ or stripped off the stack in context +@ @ restore + B __tx_fiq_processing_return @ Continue FIQ processing @ @ } -@} +@} diff --git a/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_end.S index 245752a5..8e5cd21c 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_end.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -27,7 +27,7 @@ DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts #else DISABLE_INTS = 0x80 @ Disable IRQ interrupts #endif -MODE_MASK = 0x1F @ Mode mask +MODE_MASK = 0x1F @ Mode mask FIQ_MODE_BITS = 0x11 @ FIQ mode bits @ @ @@ -37,51 +37,45 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_fiq_nesting_end Cortex-R4/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_end Cortex-R4/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from FIQ mode after */ -@/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ -@/* processing from system mode back to FIQ mode prior to the ISR */ -@/* calling _tx_thread_fiq_context_restore. Note that this function */ -@/* assumes the system stack pointer is in the same position after */ -@/* nesting start function was called. */ -@/* */ -@/* This function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with FIQ interrupts disabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +@/* processing from system mode back to FIQ mode prior to the ISR */ +@/* calling _tx_thread_fiq_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_end(VOID) @@ -93,7 +87,7 @@ _tx_thread_fiq_nesting_end: MRS r0, CPSR @ Pickup the CPSR ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value MSR CPSR_c, r0 @ Disable interrupts - LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for @ 8-byte alignment logic) BIC r0, r0, #MODE_MASK @ Clear mode bits ORR r0, r0, #FIQ_MODE_BITS @ Build IRQ mode CPSR diff --git a/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_start.S index 636007cb..f836f639 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_start.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -33,48 +33,42 @@ SYS_MODE_BITS = 0x1F @ System mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_fiq_nesting_start Cortex-R4/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_start Cortex-R4/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from FIQ mode after */ -@/* _tx_thread_fiq_context_save has been called and switches the FIQ */ -@/* processing to the system mode so nested FIQ interrupt processing */ -@/* is possible (system mode has its own "lr" register). Note that */ -@/* this function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with FIQ interrupts enabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +@/* processing to the system mode so nested FIQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_r4/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_r4/gnu/src/tx_thread_interrupt_control.S index b78773a0..df05d745 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_r4/gnu/src/tx_thread_interrupt_control.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -34,7 +34,7 @@ INT_MASK = 0x03F $_tx_thread_interrupt_control: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_interrupt_control @ Call _tx_thread_interrupt_control function @@ -44,42 +44,36 @@ $_tx_thread_interrupt_control: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_interrupt_control Cortex-R4/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control Cortex-R4/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is responsible for changing the interrupt lockout */ -@/* posture of the system. */ -@/* */ -@/* INPUT */ -@/* */ -@/* new_posture New interrupt lockout posture */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_r4/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_r4/gnu/src/tx_thread_interrupt_disable.S index 7e376a51..9440f6c2 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_r4/gnu/src/tx_thread_interrupt_disable.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -31,7 +31,7 @@ $_tx_thread_interrupt_disable: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_interrupt_disable @ Call _tx_thread_interrupt_disable function @@ -41,41 +41,35 @@ $_tx_thread_interrupt_disable: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_interrupt_disable Cortex-R4/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_disable Cortex-R4/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is responsible for disabling interrupts */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is responsible for disabling interrupts */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_disable(void) @@ -93,7 +87,7 @@ _tx_thread_interrupt_disable: #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if @ Disable IRQ and FIQ #else - CPSID i @ Disable IRQ + CPSID i @ Disable IRQ #endif #ifdef __THUMB_INTERWORK diff --git a/ports/cortex_r4/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_r4/gnu/src/tx_thread_interrupt_restore.S index 209cb658..3728f23e 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_r4/gnu/src/tx_thread_interrupt_restore.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -31,7 +31,7 @@ $_tx_thread_interrupt_restore: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_interrupt_restore @ Call _tx_thread_interrupt_restore function @@ -41,42 +41,36 @@ $_tx_thread_interrupt_restore: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_interrupt_restore Cortex-R4/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_restore Cortex-R4/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ +@/* */ @/* This function is responsible for restoring interrupts to the state */ @/* returned by a previous _tx_thread_interrupt_disable call. */ -@/* */ -@/* INPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* INPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_end.S index 84caee5b..10a81ac0 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_end.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -27,7 +27,7 @@ DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts #else DISABLE_INTS = 0x80 @ Disable IRQ interrupts #endif -MODE_MASK = 0x1F @ Mode mask +MODE_MASK = 0x1F @ Mode mask IRQ_MODE_BITS = 0x12 @ IRQ mode bits @ @ @@ -37,51 +37,45 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_irq_nesting_end Cortex-R4/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_end Cortex-R4/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from IRQ mode after */ -@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -@/* processing from system mode back to IRQ mode prior to the ISR */ -@/* calling _tx_thread_context_restore. Note that this function */ -@/* assumes the system stack pointer is in the same position after */ -@/* nesting start function was called. */ -@/* */ -@/* This function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with IRQ interrupts disabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +@/* processing from system mode back to IRQ mode prior to the ISR */ +@/* calling _tx_thread_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_end(VOID) @@ -93,7 +87,7 @@ _tx_thread_irq_nesting_end: MRS r0, CPSR @ Pickup the CPSR ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value MSR CPSR_c, r0 @ Disable interrupts - LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for @ 8-byte alignment logic) BIC r0, r0, #MODE_MASK @ Clear mode bits ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR diff --git a/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_start.S index 9a2b1cc3..9a123b31 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_start.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -33,48 +33,42 @@ SYS_MODE_BITS = 0x1F @ System mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_irq_nesting_start Cortex-R4/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_start Cortex-R4/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from IRQ mode after */ -@/* _tx_thread_context_save has been called and switches the IRQ */ -@/* processing to the system mode so nested IRQ interrupt processing */ -@/* is possible (system mode has its own "lr" register). Note that */ -@/* this function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with IRQ interrupts enabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_context_save has been called and switches the IRQ */ +@/* processing to the system mode so nested IRQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_r4/gnu/src/tx_thread_schedule.S b/ports/cortex_r4/gnu/src/tx_thread_schedule.S index 36a3ed61..10054a49 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_r4/gnu/src/tx_thread_schedule.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -38,7 +38,7 @@ $_tx_thread_schedule: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_schedule @ Call _tx_thread_schedule function @@ -48,45 +48,39 @@ $_tx_thread_schedule: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_schedule Cortex-R4/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_schedule Cortex-R4/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function waits for a thread control block pointer to appear in */ -@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -@/* in the variable, the corresponding thread is resumed. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_initialize_kernel_enter ThreadX entry function */ -@/* _tx_thread_system_return Return to system from thread */ -@/* _tx_thread_context_restore Restore thread's context */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function waits for a thread control block pointer to appear in */ +@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +@/* in the variable, the corresponding thread is resumed. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* _tx_thread_system_return Return to system from thread */ +@/* _tx_thread_context_restore Restore thread's context */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) @@ -116,7 +110,7 @@ __tx_thread_schedule_loop: @ @ } @ while(_tx_thread_execute_ptr == TX_NULL); -@ +@ @ /* Yes! We have a thread to execute. Lockout interrupts and @ transfer control to it. */ @ @@ -129,7 +123,7 @@ __tx_thread_schedule_loop: @ /* Setup the current thread pointer. */ @ _tx_thread_current_ptr = _tx_thread_execute_ptr; @ - LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread STR r0, [r1] @ Setup current thread pointer @ @ /* Increment the run count for this thread. */ @@ -143,7 +137,7 @@ __tx_thread_schedule_loop: @ /* Setup time-slice, if present. */ @ _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; @ - LDR r2, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r2, =_tx_timer_time_slice @ Pickup address of time-slice @ variable LDR sp, [r0, #8] @ Switch stack pointers STR r3, [r2] @ Setup time-slice diff --git a/ports/cortex_r4/gnu/src/tx_thread_stack_build.S b/ports/cortex_r4/gnu/src/tx_thread_stack_build.S index 678e7a9b..f5748109 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_r4/gnu/src/tx_thread_stack_build.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -42,7 +42,7 @@ CPSR_MASK = 0x9F @ Mask initial CPSR, IRQ interru .type $_tx_thread_stack_build,function $_tx_thread_stack_build: BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_stack_build @ Call _tx_thread_stack_build function @@ -52,44 +52,38 @@ $_tx_thread_stack_build: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_stack_build Cortex-R4/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build Cortex-R4/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ +@/* */ @/* This function builds a stack frame on the supplied thread's stack. */ @/* The stack frame results in a fake interrupt return to the supplied */ -@/* function pointer. */ -@/* */ -@/* INPUT */ -@/* */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ @/* thread_ptr Pointer to thread control blk */ @/* function_ptr Pointer to return function */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_thread_create Create thread service */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -98,10 +92,10 @@ $_tx_thread_stack_build: .type _tx_thread_stack_build,function _tx_thread_stack_build: @ -@ +@ @ /* Build a fake interrupt frame. The form of the fake interrupt stack @ on the ARM9 should look like the following after it is built: -@ +@ @ Stack Top: 1 Interrupt stack frame type @ CPSR Initial value for CPSR @ a1 (r0) Initial value for a1 diff --git a/ports/cortex_r4/gnu/src/tx_thread_system_return.S b/ports/cortex_r4/gnu/src/tx_thread_system_return.S index eee00ce6..f8a0ee09 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_r4/gnu/src/tx_thread_system_return.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -42,7 +42,7 @@ $_tx_thread_system_return: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_system_return @ Call _tx_thread_system_return function @@ -52,44 +52,38 @@ $_tx_thread_system_return: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_system_return Cortex-R4/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return Cortex-R4/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is target processor specific. It is used to transfer */ -@/* control from a thread back to the ThreadX system. Only a */ -@/* minimal context is saved since the compiler assumes temp registers */ -@/* are going to get slicked by a function call anyway. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling loop */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX components */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ @/* */ @/**************************************************************************/ @VOID _tx_thread_system_return(VOID) @@ -124,7 +118,7 @@ _tx_skip_solicited_vfp_save: @ MOV r0, #0 @ Build a solicited stack type STMDB sp!, {r0-r1} @ Save type and CPSR -@ +@ @ #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY @ diff --git a/ports/cortex_r4/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_r4/gnu/src/tx_thread_vectored_context_save.S index a303ef54..1c4f07ce 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_r4/gnu/src/tx_thread_vectored_context_save.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -30,47 +30,41 @@ @ @/* No 16-bit Thumb mode veneer code is needed for _tx_thread_vectored_context_save @ since it will never be called 16-bit mode. */ -@ +@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_vectored_context_save Cortex-R4/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_vectored_context_save Cortex-R4/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function saves the context of an executing thread in the */ -@/* beginning of interrupt processing. The function also ensures that */ -@/* the system stack is used upon return to the calling ISR. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_vectored_context_save(VOID) @@ -128,7 +122,7 @@ __tx_thread_not_nested_save: LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr LDR r0, [r1, #0] @ Pickup current thread pointer CMP r0, #0 @ Is it NULL? - BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in @ scheduling loop - nothing needs saving! @ @ /* Note: Minimal context of interrupted thread is already saved. */ @@ -160,7 +154,7 @@ __tx_thread_idle_system_save: @ @ /* Interrupt occurred in the scheduling loop. */ @ -@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ @ processing. */ @ MOV r10, #0 @ Clear stack limit diff --git a/ports/cortex_r4/gnu/src/tx_timer_interrupt.S b/ports/cortex_r4/gnu/src/tx_timer_interrupt.S index 0b6c8381..99a1dff7 100644 --- a/ports/cortex_r4/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_r4/gnu/src/tx_timer_interrupt.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Timer */ @/** */ @@ -48,7 +48,7 @@ .type $_tx_timer_interrupt,function $_tx_timer_interrupt: BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_timer_interrupt @ Call _tx_timer_interrupt function @@ -58,46 +58,40 @@ $_tx_timer_interrupt: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_timer_interrupt Cortex-R4/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt Cortex-R4/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function processes the hardware timer interrupt. This */ -@/* processing includes incrementing the system clock and checking for */ -@/* time slice and/or timer expiration. If either is found, the */ -@/* interrupt context save/restore functions are called along with the */ -@/* expiration functions. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_time_slice Time slice interrupted thread */ -@/* _tx_timer_expiration_process Timer expiration processing */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* interrupt vector */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) @@ -122,7 +116,7 @@ _tx_timer_interrupt: @ if (_tx_timer_time_slice) @ { @ - LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice LDR r2, [r3] @ Pickup time-slice CMP r2, #0 @ Is it non-active? BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing @@ -240,7 +234,7 @@ __tx_timer_dont_activate: @ if (_tx_timer_expired_time_slice) @ { @ - LDR r3, =_tx_timer_expired_time_slice @ Pickup address of time-slice expired + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of time-slice expired LDR r2, [r3] @ Pickup the actual flag CMP r2, #0 @ See if the flag is set BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing diff --git a/ports/cortex_r4/iar/example_build/sample_threadx.c b/ports/cortex_r4/iar/example_build/sample_threadx.c index 983109cc..ca92ff86 100644 --- a/ports/cortex_r4/iar/example_build/sample_threadx.c +++ b/ports/cortex_r4/iar/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -63,7 +63,7 @@ void thread_6_and_7_entry(ULONG thread_input); int main() { - + /* Enter the ThreadX kernel. */ tx_kernel_enter(); } @@ -87,42 +87,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -130,23 +130,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -249,11 +249,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -312,7 +312,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -365,7 +365,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_r4/iar/example_build/tx_initialize_low_level.s b/ports/cortex_r4/iar/example_build/tx_initialize_low_level.s index 1b743b09..b3310a39 100644 --- a/ports/cortex_r4/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_r4/iar/example_build/tx_initialize_low_level.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Initialize */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -52,7 +52,7 @@ SVC_MODE DEFINE 0x13 ; SVC mode ; ; ; -;/* Define the FREE_MEM segment that will specify where free memory is +;/* Define the FREE_MEM segment that will specify where free memory is ; defined. This must also be located in at the end of other RAM segments ; in the linker control file. The value of this segment is what is passed ; to tx_application_define. */ @@ -65,45 +65,39 @@ __tx_free_memory_start ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -135,7 +129,7 @@ _tx_initialize_low_level ; LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address STR r0, [r2, #0] ; Save first free memory address -; +; ; /* Setup Timer for periodic interrupts. */ ; ; /* Done, return to caller. */ @@ -183,17 +177,17 @@ IRQ_Handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -208,7 +202,7 @@ __tx_irq_processing_return ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -227,22 +221,22 @@ __tx_irq_processing_return ; /* Jump to context save to save system context. */ ; STMDB sp!, {r0-r3} ; Save some scratch registers ; MRS r0, SPSR ; Pickup saved SPSR -; SUB lr, lr, #4 ; Adjust point of interrupt +; SUB lr, lr, #4 ; Adjust point of interrupt ; STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; BL _tx_thread_vectored_context_save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ;#ifdef TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_start @@ -251,7 +245,7 @@ __tx_irq_processing_return ; /* Application IRQ handler is called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ;#ifdef TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_end diff --git a/ports/cortex_r4/iar/inc/tx_port.h b/ports/cortex_r4/iar/inc/tx_port.h index 25abc49d..c2950326 100644 --- a/ports/cortex_r4/iar/inc/tx_port.h +++ b/ports/cortex_r4/iar/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Cortex-R4/IAR */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-R4/IAR */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -79,7 +71,7 @@ #endif -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -115,19 +107,19 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -172,7 +164,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -186,18 +178,18 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ - VOID *tx_thread_iar_tls_pointer; + VOID *tx_thread_iar_tls_pointer; #else #define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; #endif -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -211,11 +203,11 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -225,23 +217,23 @@ ULONG _tx_misra_time_stamp_get(VOID); #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #if (__VER__ < 8000000) -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #endif #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -269,8 +261,8 @@ void __iar_Initlocks(void); #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -281,22 +273,22 @@ void __iar_Initlocks(void); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (UINT) __CLZ(m); \ - b = 31 - b; + b = 31 - b; #endif #endif #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ /* First, check and see what mode the file is being compiled in. The IAR compiler - defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode + defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode is present. If ARM 32-bit mode is present, the fast CPSR manipulation macros are available. Otherwise, if Thumb mode is present, we must use function calls. */ @@ -365,8 +357,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-R4/IAR Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R4/IAR Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_r4/iar/readme_threadx.txt b/ports/cortex_r4/iar/readme_threadx.txt index 400eaa1f..ac297f16 100644 --- a/ports/cortex_r4/iar/readme_threadx.txt +++ b/ports/cortex_r4/iar/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for Cortex-R4 + Microsoft's Azure RTOS ThreadX for Cortex-R4 Thumb & 32-bit Mode @@ -7,10 +7,10 @@ 1. Building the ThreadX run-time Library Building the ThreadX library is easy. First, open the Azure RTOS workspace -azure_rtos.eww. Next, make the TX project the "active project" in the -IAR Embedded Workbench and select the "Make" button. You should observe -assembly and compilation of a series of ThreadX source files. This -results in the ThreadX run-time library file tx.a, which is needed by +azure_rtos.eww. Next, make the TX project the "active project" in the +IAR Embedded Workbench and select the "Make" button. You should observe +assembly and compilation of a series of ThreadX source files. This +results in the ThreadX run-time library file tx.a, which is needed by the application. @@ -20,47 +20,47 @@ The ThreadX demonstration is designed to execute under the IAR Windows-based Cortex-R4 simulator. Building the demonstration is easy; simply make the sample_threadx.ewp project -the "active project" in the IAR Embedded Workbench and select the +the "active project" in the IAR Embedded Workbench and select the "Make" button. -You should observe the compilation of sample_threadx.c (which is the demonstration +You should observe the compilation of sample_threadx.c (which is the demonstration application) and linking with tx.a. The resulting file sample_threadx.out is a binary file that can be downloaded and executed on IAR's Cortex-R4 simulator. 3. System Initialization -The entry point in ThreadX for the Cortex-R4 using IAR tools is at label -?cstartup. This is defined within the IAR compiler's startup code. In -addition, this is where all static and global preset C variable +The entry point in ThreadX for the Cortex-R4 using IAR tools is at label +?cstartup. This is defined within the IAR compiler's startup code. In +addition, this is where all static and global preset C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, and a periodic timer interrupt source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. By default, the vector area is defined at the top of cstartup.s, which is -a slightly modified from the base IAR file. +a slightly modified from the base IAR file. The _tx_initialize_low_level function inside of tx_initialize_low_level.s -also determines the first available address for use by the application, which -is supplied as the sole input parameter to your application definition function, -tx_application_define. To accomplish this, a section is created in -tx_initialize_low_level.s called FREE_MEM, which must be located after all +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all other RAM sections in memory. 4. Register Usage and Stack Frames -The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are -scratch registers for each function. All other registers used by a C function -must be preserved by the function. ThreadX takes advantage of this in -situations where a context switch happens as a result of making a ThreadX -service call (which is itself a C function). In such cases, the saved +The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are +scratch registers for each function. All other registers used by a C function +must be preserved by the function. ThreadX takes advantage of this in +situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -78,12 +78,12 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 5. Conditional Compilation Switches @@ -92,159 +92,159 @@ The following are conditional compilation options for building the ThreadX libra and application: TX_ENABLE_IRQ_NESTING This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - TX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the ThreadX library -project to enable various compiler optimizations. +project to enable various compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-R4 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-R4 vectors start at address zero. The demonstration system startup -cstartup.s file contains the vectors and is loaded at address zero. -On actual hardware platforms, this area might have to be copied to address 0. +cstartup.s file contains the vectors and is loaded at address zero. +On actual hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs @@ -255,12 +255,12 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.s: PUBLIC __tx_irq_handler - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -268,7 +268,7 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -281,7 +281,7 @@ __tx_irq_processing_return 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.s: @@ -292,12 +292,12 @@ __tx_example_vectored_irq_handler ; /* Jump to context save to save system context. */ STMDB sp!, {r0-r3} ; Save some scratch registers MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers BL _tx_thread_vectored_context_save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -314,24 +314,24 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.s. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables -nesting by disabling IRQ interrupts and switching back to IRQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: RSEG .text:CODE:NOROOT(2) PUBLIC __tx_irq_handler RSEG .text:CODE:NOROOT(2) - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -339,15 +339,15 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ; BL _tx_thread_irq_nesting_start @@ -355,7 +355,7 @@ __tx_irq_processing_return ; /* Application ISR dispatch call goes here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ; BL _tx_thread_irq_nesting_end @@ -366,12 +366,12 @@ __tx_irq_processing_return 7.3 FIQ Interrupts -By default, Cortex-R4 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of a thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, Cortex-R4 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of a thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.s. @@ -383,21 +383,21 @@ cannot be disabled. The hardware does not support nested FIQ interrupts. 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to _tx_timer_interrupt +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. 9. Thumb/Cortex-R4 Mixed Mode -By default, ThreadX is setup for running in Cortex-R4 32-bit mode. This is -also true for the demonstration system. It is possible to build any +By default, ThreadX is setup for running in Cortex-R4 32-bit mode. This is +also true for the demonstration system. It is possible to build any ThreadX file and/or the application in Thumb mode. The only exception -to this is the file tx_thread_shell_entry.c. This file must always be +to this is the file tx_thread_shell_entry.c. This file must always be built in 32-bit mode. diff --git a/ports/cortex_r4/iar/src/tx_iar.c b/ports/cortex_r4/iar/src/tx_iar.c index 158738ea..238b485e 100644 --- a/ports/cortex_r4/iar/src/tx_iar.c +++ b/ports/cortex_r4/iar/src/tx_iar.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** IAR Multithreaded Library Support */ /** */ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports/cortex_r4/iar/src/tx_thread_context_restore.s b/ports/cortex_r4/iar/src/tx_thread_context_restore.s index 1b51ccdc..7f7d414a 100644 --- a/ports/cortex_r4/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_r4/iar/src/tx_thread_context_restore.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -47,44 +47,38 @@ THUMB_MASK DEFINE 0x20 ; Thumb bit mask ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -112,13 +106,13 @@ _tx_thread_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3] ; Store the counter + STR r2, [r3] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -181,7 +175,7 @@ __tx_thread_preempt_restore LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer - + #ifdef __ARMVFP__ LDR r2, [r0, #144] ; Pickup the VFP enabled flag CMP r2, #0 ; Is the VFP enabled? @@ -191,7 +185,7 @@ __tx_thread_preempt_restore VSTMDB sp!, {D0-D15} ; Save D0-D15 _tx_skip_irq_vfp_save #endif - + MOV r3, #1 ; Build interrupt stack type STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR STR sp, [r0, #8] ; Save stack pointer in thread control @@ -237,7 +231,7 @@ __tx_thread_idle_system_restore ; /* Just return back to the scheduler! */ ; CPS #SVC_MODE ; Enter SVC mode - + B _tx_thread_schedule ; Return to scheduler ;} ; diff --git a/ports/cortex_r4/iar/src/tx_thread_context_save.s b/ports/cortex_r4/iar/src/tx_thread_context_save.s index 9c01112d..6ce8cd84 100644 --- a/ports/cortex_r4/iar/src/tx_thread_context_save.s +++ b/ports/cortex_r4/iar/src/tx_thread_context_save.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -36,43 +36,37 @@ EXTERN _tx_execution_isr_enter ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -89,7 +83,7 @@ _tx_thread_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3, #0] ; Pickup system state CMP r2, #0 ; Is this the first interrupt? @@ -104,7 +98,7 @@ _tx_thread_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -120,7 +114,7 @@ _tx_thread_context_save POP {lr} ; Recover ISR lr #endif - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; __tx_thread_not_nested_save ; } @@ -134,13 +128,13 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} ; Store other registers ; ; /* Save the current stack pointer in the thread's control block. */ @@ -160,7 +154,7 @@ __tx_thread_not_nested_save POP {lr} ; Recover ISR lr #endif - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ; else @@ -170,7 +164,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit @@ -185,7 +179,7 @@ __tx_thread_idle_system_save #endif ADD sp, sp, #16 ; Recover saved registers - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ;} diff --git a/ports/cortex_r4/iar/src/tx_thread_interrupt_control.s b/ports/cortex_r4/iar/src/tx_thread_interrupt_control.s index 44561789..ece9c9a9 100644 --- a/ports/cortex_r4/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_r4/iar/src/tx_thread_interrupt_control.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ;#define TX_SOURCE_CODE ; @@ -32,42 +32,36 @@ INT_MASK DEFINE 0x80 ; Interrupt bit mask ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) @@ -87,7 +81,7 @@ _tx_thread_interrupt_control ; MSR CPSR_cxsf, r1 ; Setup new CPSR AND r0, r3, #INT_MASK ; Return previous interrupt mask - + BX lr ; Return to caller ; ;} diff --git a/ports/cortex_r4/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_r4/iar/src/tx_thread_interrupt_disable.s index cc071a5b..bb162749 100644 --- a/ports/cortex_r4/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_r4/iar/src/tx_thread_interrupt_disable.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ;#define TX_SOURCE_CODE ; @@ -32,41 +32,35 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_r4/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_r4/iar/src/tx_thread_interrupt_restore.s index a2bc5506..b96ebe46 100644 --- a/ports/cortex_r4/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_r4/iar/src/tx_thread_interrupt_restore.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ;#define TX_SOURCE_CODE ; @@ -28,42 +28,36 @@ ;#include "tx_thread.h" ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for restoring interrupts to the state */ -;/* returned by a previous _tx_thread_interrupt_disable call. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for restoring interrupts to the state */ +;/* returned by a previous _tx_thread_interrupt_disable call. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;void _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_r4/iar/src/tx_thread_irq_nesting_end.s b/ports/cortex_r4/iar/src/tx_thread_irq_nesting_end.s index 42b1deae..cf06f9b0 100644 --- a/ports/cortex_r4/iar/src/tx_thread_irq_nesting_end.s +++ b/ports/cortex_r4/iar/src/tx_thread_irq_nesting_end.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -33,51 +33,45 @@ IRQ_MODE DEFINE 0x12 ; IRQ mode ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_end Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -;/* processing from system mode back to IRQ mode prior to the ISR */ -;/* calling _tx_thread_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_r4/iar/src/tx_thread_irq_nesting_start.s b/ports/cortex_r4/iar/src/tx_thread_irq_nesting_start.s index 83fbbd17..1a7c99d2 100644 --- a/ports/cortex_r4/iar/src/tx_thread_irq_nesting_start.s +++ b/ports/cortex_r4/iar/src/tx_thread_irq_nesting_start.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -33,48 +33,42 @@ SYS_MODE DEFINE 0x1F ; System mode ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_start Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_context_save has been called and switches the IRQ */ -;/* processing to the system mode so nested IRQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_r4/iar/src/tx_thread_schedule.s b/ports/cortex_r4/iar/src/tx_thread_schedule.s index 42be1490..dd548e46 100644 --- a/ports/cortex_r4/iar/src/tx_thread_schedule.s +++ b/ports/cortex_r4/iar/src/tx_thread_schedule.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -37,45 +37,39 @@ ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -104,7 +98,7 @@ __tx_thread_schedule_loop ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Lockout interrupts and ; transfer control to it. */ ; @@ -113,7 +107,7 @@ __tx_thread_schedule_loop ; /* Setup the current thread pointer. */ ; _tx_thread_current_ptr = _tx_thread_execute_ptr; ; - LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread STR r0, [r1, #0] ; Setup current thread pointer ; ; /* Increment the run count for this thread. */ @@ -127,7 +121,7 @@ __tx_thread_schedule_loop ; /* Setup time-slice, if present. */ ; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; ; - LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice ; variable LDR sp, [r0, #8] ; Switch stack pointers STR r3, [r2, #0] ; Setup time-slice @@ -184,7 +178,7 @@ _tx_skip_solicited_vfp_restore: #ifdef __ARMVFP__ PUBLIC tx_thread_vfp_enable CODE32 -tx_thread_vfp_enable??rA +tx_thread_vfp_enable??rA tx_thread_vfp_enable MRS r2, CPSR ; Pickup the CPSR CPSID i ; Disable IRQ interrupts @@ -200,7 +194,7 @@ __tx_no_thread_to_enable: PUBLIC tx_thread_vfp_disable CODE32 -tx_thread_vfp_disable??rA +tx_thread_vfp_disable??rA tx_thread_vfp_disable MRS r2, CPSR ; Pickup the CPSR CPSID i ; Disable IRQ interrupts diff --git a/ports/cortex_r4/iar/src/tx_thread_stack_build.s b/ports/cortex_r4/iar/src/tx_thread_stack_build.s index bbb86848..7a95aeb7 100644 --- a/ports/cortex_r4/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_r4/iar/src/tx_thread_stack_build.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -33,58 +33,52 @@ SVC_MODE DEFINE 0x13 ; SVC mode CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints enabled ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function builds a stack frame on the supplied thread's stack. */ -;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Pointer to thread control blk */ -;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) ;{ RSEG .text:CODE:NOROOT(2) PUBLIC _tx_thread_stack_build - + ARM _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-R4 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; a1 (r0) Initial value for a1 diff --git a/ports/cortex_r4/iar/src/tx_thread_system_return.s b/ports/cortex_r4/iar/src/tx_thread_system_return.s index a8c755fa..89a42df4 100644 --- a/ports/cortex_r4/iar/src/tx_thread_system_return.s +++ b/ports/cortex_r4/iar/src/tx_thread_system_return.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ;#define TX_SOURCE_CODE ; @@ -37,44 +37,38 @@ ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -107,7 +101,7 @@ _tx_skip_solicited_vfp_save: MOV r0, #0 ; Build a solicited stack type STMDB sp!, {r0-r1} ; Save type and CPSR -; +; ; #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; diff --git a/ports/cortex_r4/iar/src/tx_thread_vectored_context_save.s b/ports/cortex_r4/iar/src/tx_thread_vectored_context_save.s index aa24d6c3..91fb156e 100644 --- a/ports/cortex_r4/iar/src/tx_thread_vectored_context_save.s +++ b/ports/cortex_r4/iar/src/tx_thread_vectored_context_save.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -35,43 +35,37 @@ EXTERN _tx_execution_isr_enter ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_vectored_context_save Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) @@ -128,7 +122,7 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in ; scheduling loop - nothing needs saving! ; ; /* Note: Minimal context of interrupted thread is already saved. */ @@ -160,7 +154,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports/cortex_r4/iar/src/tx_timer_interrupt.s b/ports/cortex_r4/iar/src/tx_timer_interrupt.s index 896c5525..c17b011d 100644 --- a/ports/cortex_r4/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_r4/iar/src/tx_timer_interrupt.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Timer */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ;#define TX_SOURCE_CODE ; @@ -43,46 +43,40 @@ ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time-slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time-slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -108,7 +102,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CMP r2, #0 ; Is it non-active? BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing @@ -226,13 +220,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CMP r2, #0 ; See if the flag is set BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing ; diff --git a/ports/cortex_r5/ac5/example_build/sample_threadx.c b/ports/cortex_r5/ac5/example_build/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports/cortex_r5/ac5/example_build/sample_threadx.c +++ b/ports/cortex_r5/ac5/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_r5/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_r5/ac5/example_build/tx_initialize_low_level.s index 0ae74009..a403c04a 100644 --- a/ports/cortex_r5/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_r5/ac5/example_build/tx_initialize_low_level.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -90,45 +90,39 @@ __vectors ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-R5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-R5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -179,7 +173,7 @@ _tx_initialize_low_level ; _tx_thread_system_stack_ptr = (VOID_PTR) (sp); ; LDR r1, =_tx_thread_system_stack_ptr ; Pickup address of system stack ptr - LDR r0, [r1, #0] ; Pickup system stack + LDR r0, [r1, #0] ; Pickup system stack ADD r0, r0, #4 ; Increment to next free word ; ; /* Save the first available memory address. */ @@ -201,7 +195,7 @@ _tx_initialize_low_level ; ; ;/* Define initial heap/stack routine for the ARM RealView (and ADS) startup code. This -; routine will set the initial stack to use the ThreadX IRQ & FIQ & +; routine will set the initial stack to use the ThreadX IRQ & FIQ & ; (optionally SYS) stack areas. */ ; EXPORT __user_initial_stackheap @@ -253,7 +247,7 @@ __tx_reserved_handler ; ; EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -261,21 +255,21 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; ; BL _tx_timer_interrupt ; Timer interrupt handler _tx_not_timer_interrupt ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ IF :DEF:TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -285,7 +279,7 @@ _tx_not_timer_interrupt ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ IF :DEF:TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -301,28 +295,28 @@ _tx_not_timer_interrupt __tx_example_vectored_irq_handler ; ; -; /* Save initial context and call context save to prepare for +; /* Save initial context and call context save to prepare for ; vectored ISR execution. */ ; ; STMDB sp!, {r0-r3} ; Save some scratch registers ; MRS r0, SPSR ; Pickup saved SPSR -; SUB lr, lr, #4 ; Adjust point of interrupt +; SUB lr, lr, #4 ; Adjust point of interrupt ; STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers ; BL _tx_thread_vectored_context_save ; Vectored context save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ; IF :DEF:TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_start @@ -331,7 +325,7 @@ __tx_example_vectored_irq_handler ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ; IF :DEF:TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_end @@ -353,11 +347,11 @@ __tx_fiq_processing_return ; /* At this point execution is still in the FIQ mode. The CPSR, point of ; interrupt, and all C scratch registers are available for use. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start ; from FIQ mode with interrupts disabled. This routine switches to the -; system mode and returns with FIQ interrupts enabled. +; system mode and returns with FIQ interrupts enabled. ; -; NOTE: It is very important to ensure all FIQ interrupts are cleared +; NOTE: It is very important to ensure all FIQ interrupts are cleared ; prior to enabling nested FIQ interrupts. */ IF :DEF:TX_ENABLE_FIQ_NESTING BL _tx_thread_fiq_nesting_start diff --git a/ports/cortex_r5/ac5/inc/tx_port.h b/ports/cortex_r5/ac5/inc/tx_port.h index 881d5872..aa188c5c 100644 --- a/ports/cortex_r5/ac5/inc/tx_port.h +++ b/ports/cortex_r5/ac5/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Cortex-R5/AC5 */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-R5/AC5 */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -75,7 +67,7 @@ #include -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -111,12 +103,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -126,8 +118,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -174,7 +166,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -186,13 +178,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -206,11 +198,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -218,8 +210,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -246,21 +238,21 @@ typedef unsigned short USHORT; #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef __thumb #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (ULONG) __clz((unsigned int) m); \ - b = 31 - b; + b = 31 - b; #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -280,7 +272,7 @@ typedef unsigned short USHORT; { \ __enable_irq(); \ __enable_fiq(); \ - } + } #else @@ -289,7 +281,7 @@ typedef unsigned short USHORT; #define TX_RESTORE if (!interrupt_save_disabled) \ { \ __enable_irq(); \ - } + } #endif #else @@ -318,8 +310,8 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-R5/AC5 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R5/AC5 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r5/ac5/readme_threadx.txt b/ports/cortex_r5/ac5/readme_threadx.txt index 9910f87e..0df144e2 100644 --- a/ports/cortex_r5/ac5/readme_threadx.txt +++ b/ports/cortex_r5/ac5/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for Cortex-R5 + Microsoft's Azure RTOS ThreadX for Cortex-R5 Thumb & 32-bit Mode @@ -6,21 +6,21 @@ 1. Building the ThreadX run-time Library -First make sure you are in the "example_build" directory. Also, make sure that -you have setup your path and other environment variables necessary for the ARM -AC5 development environment. At this point you may run the build_threadx.bat -batch file. This will build the ThreadX run-time environment in the -"example_build" directory. +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the ARM +AC5 development environment. At this point you may run the build_threadx.bat +batch file. This will build the ThreadX run-time environment in the +"example_build" directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. 1.1 Building with Project Files -The ThreadX library can also be built via project files. Simply open -the tx.mcp file with project builder and select make. This will place +The ThreadX library can also be built via project files. Simply open +the tx.mcp file with project builder and select make. This will place the tx.a library file into the Debug sub-directory. @@ -29,45 +29,45 @@ the tx.a library file into the Debug sub-directory. The ThreadX demonstration is designed to execute under the ARM Windows-based simulator. -Building the demonstration is easy; simply execute the build_threadx_demo.bat -batch file while inside the "example_build" directory. +Building the demonstration is easy; simply execute the build_threadx_demo.bat +batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with tx.a. The resulting file sample_threadx.axf +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.axf is a binary file that can be downloaded and executed on the ARM simulator. 2.0.1 Building with Project Files -The ThreadX demonstration can also be built via project files. Simply open -the sample_threadx.mcp file with project builder and select make. This will place +The ThreadX demonstration can also be built via project files. Simply open +the sample_threadx.mcp file with project builder and select make. This will place the sample_threadx.axf output image into the Debug sub-directory. 3. System Initialization -The entry point in ThreadX for the Cortex-R5 using AC5 tools is at label -__main. This is defined within the AC5 compiler's startup code. In -addition, this is where all static and global pre-set C variable +The entry point in ThreadX for the Cortex-R5 using AC5 tools is at label +__main. This is defined within the AC5 compiler's startup code. In +addition, this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. By default, the vector area is defined to be located in the Init area, -which is defined at the top of tx_initialize_low_level.s. This area is typically -located at 0. In situations where this is impossible, the vectors at the beginning +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. By default, the vector area is defined to be located in the Init area, +which is defined at the top of tx_initialize_low_level.s. This area is typically +located at 0. In situations where this is impossible, the vectors at the beginning of the Init area should be copied to address 0. This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 4. Assembler / Compiler Switches -The following are compiler switches used in building the demonstration +The following are compiler switches used in building the demonstration system: Compiler Switch Meaning @@ -83,10 +83,10 @@ Linker Switch Meaning -o demo.axf Specifies demo output file name --elf Specifies elf output file format --ro Specifies that Read-Only memory starts at address 0 - --first tx_initialize_low_level.o(Init) + --first tx_initialize_low_level.o(Init) Specifies that the first area loaded is Init --remove Remove unused areas - --list Specifies map file name + --list Specifies map file name --symbols Specifies symbols for map file --map Creates a map file @@ -97,161 +97,161 @@ Application Defines ThreadX assembly files. If used, it should be used on all assembly files and the generic C source of - ThreadX should be compiled with + ThreadX should be compiled with TX_ENABLE_FIQ_SUPPORT defined as well. --PD "TX_ENABLE_IRQ_NESTING SETL {TRUE}" This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. --PD "TX_ENABLE_FIQ_NESTING SETL {TRUE}" This assembler define enables FIQ - nested support. If FIQ nested + nested support. If FIQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. In addition, IRQ nesting should also be enabled. -DTX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ interrupt handling in the ThreadX - generic C source. This define + generic C source. This define should also be used in conjunction with the corresponding assembler - define. + define. -DTX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - -DTX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + -DTX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - -DTX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + -DTX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - -DTX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + -DTX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - -DTX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + -DTX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - -DTX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + -DTX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - -DTX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + -DTX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - -DTX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + -DTX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - -DTX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + -DTX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - -DTX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + -DTX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - -DTX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + -DTX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - -DTX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + -DTX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - -DTX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + -DTX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - -DTX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + -DTX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - -DTX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + -DTX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - -DTX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + -DTX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - -DTX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + -DTX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - -DTX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + -DTX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - -DTX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + -DTX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - -DTX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + -DTX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. -DTX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - -DTX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + -DTX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - -DTX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + -DTX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. 5. Register Usage and Stack Frames -The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -269,39 +269,39 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make it run faster, you can change the build_threadx.bat file to -remove the -g option and enable all compiler optimizations. +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-R5 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-R5 vectors start at address zero. The demonstration system startup -Init area contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +Init area contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs @@ -312,12 +312,12 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.s: EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -325,7 +325,7 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -338,7 +338,7 @@ __tx_irq_processing_return 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.s: EXPORT __tx_irq_example_handler @@ -348,12 +348,12 @@ __tx_irq_example_handler STMDB sp!, {r0-r3} ; Save some scratch registers MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers BL _tx_thread_vectored_context_save ; Call the vectored IRQ context save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -370,22 +370,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.s. When nested IRQ interrupts are no longer required, calling the _tx_thread_irq_nesting_end service disables nesting by disabling -IRQ interrupts and switching back to IRQ mode in preparation for the IRQ +IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -393,10 +393,10 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* Enable nested IRQ interrupts. NOTE: Since this service returns -; with IRQ interrupts enabled, all IRQ interrupt sources must be +; with IRQ interrupts enabled, all IRQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start -; +; ; /* Application ISR call(s) go here! */ ; ; /* Disable nested IRQ interrupts. The mode is switched back to @@ -409,12 +409,12 @@ __tx_irq_processing_return 7.3 FIQ Interrupts -By default, Cortex-R5 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, Cortex-R5 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.s. @@ -423,7 +423,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.s. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.s: @@ -451,18 +451,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.s. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -478,7 +478,7 @@ __tx_fiq_processing_return ; interrupt, and all C scratch registers are available for use. */ ; ; /* Enable nested FIQ interrupts. NOTE: Since this service returns -; with FIQ interrupts enabled, all FIQ interrupt sources must be +; with FIQ interrupts enabled, all FIQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start ; @@ -494,22 +494,22 @@ __tx_fiq_processing_return 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.s in the Integrator sub-directories. 9. Thumb/Cortex-R5 Mixed Mode -By default, ThreadX is setup for running in Cortex-R5 32-bit mode. This is -also true for the demonstration system. It is possible to build any -ThreadX file and/or the application in Thumb mode. If any Thumb code -is used the entire ThreadX source- both C and assembly - should be built +By default, ThreadX is setup for running in Cortex-R5 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. If any Thumb code +is used the entire ThreadX source- both C and assembly - should be built with the "-apcs /interwork" option. diff --git a/ports/cortex_r5/ac5/src/tx_thread_context_restore.s b/ports/cortex_r5/ac5/src/tx_thread_context_restore.s index 15fbb1e9..1d070d89 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_r5/ac5/src/tx_thread_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -54,44 +54,38 @@ SVC_MODE EQU 0x93 ; SVC mode ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore Cortex-R5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-R5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -121,13 +115,13 @@ _tx_thread_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3, #0] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3, #0] ; Store the counter + STR r2, [r3, #0] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -193,7 +187,7 @@ __tx_thread_preempt_restore LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer - + IF {TARGET_FPU_VFP} = {TRUE} LDR r2, [r0, #144] ; Pickup the VFP enabled flag CMP r2, #0 ; Is the VFP enabled? diff --git a/ports/cortex_r5/ac5/src/tx_thread_context_save.s b/ports/cortex_r5/ac5/src/tx_thread_context_save.s index 9d1b2d14..043fbdeb 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_context_save.s +++ b/ports/cortex_r5/ac5/src/tx_thread_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,43 +39,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save Cortex-R5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-R5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -90,7 +84,7 @@ _tx_thread_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers IF :DEF:TX_ENABLE_FIQ_SUPPORT CPSID if ; Disable FIQ interrupts ENDIF @@ -108,7 +102,7 @@ _tx_thread_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -124,7 +118,7 @@ _tx_thread_context_save POP {lr} ; Recover ISR lr ENDIF - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; __tx_thread_not_nested_save ; } @@ -138,13 +132,13 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} ; Store other registers ; ; /* Save the current stack pointer in the thread's control block. */ @@ -164,7 +158,7 @@ __tx_thread_not_nested_save POP {lr} ; Recover ISR lr ENDIF - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ; else @@ -174,7 +168,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit @@ -189,7 +183,7 @@ __tx_thread_idle_system_save ENDIF ADD sp, sp, #16 ; Recover saved registers - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ;} diff --git a/ports/cortex_r5/ac5/src/tx_thread_fiq_context_restore.s b/ports/cortex_r5/ac5/src/tx_thread_fiq_context_restore.s index 65a4be5a..f58456b9 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_r5/ac5/src/tx_thread_fiq_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -32,7 +32,7 @@ ; SVC_MODE EQU 0xD3 ; SVC mode FIQ_MODE EQU 0xD1 ; FIQ mode -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; ; @@ -50,44 +50,38 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_restore Cortex-R5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore Cortex-R5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the fiq interrupt context when processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* FIQ ISR Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) @@ -113,13 +107,13 @@ _tx_thread_fiq_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3] ; Store the counter + STR r2, [r3] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -163,7 +157,7 @@ __tx_thread_fiq_no_preempt_restore ; /* Restore interrupted thread or ISR. */ ; ; /* Pickup the saved stack pointer. */ -; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; ; ; /* Recover the saved context and return to the point of interrupt. */ ; @@ -195,7 +189,7 @@ __tx_thread_fiq_preempt_restore LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1] ; Pickup current thread pointer STR sp, [r0, #8] ; Save stack pointer in thread control - ; block + ; block ; ; /* Save the remaining time-slice and disable it. */ ; if (_tx_timer_time_slice) @@ -207,7 +201,7 @@ __tx_thread_fiq_preempt_restore BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it ; ; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; -; _tx_timer_time_slice = 0; +; _tx_timer_time_slice = 0; ; STR r2, [r0, #24] ; Save thread's time-slice MOV r2, #0 ; Clear value diff --git a/ports/cortex_r5/ac5/src/tx_thread_fiq_context_save.s b/ports/cortex_r5/ac5/src/tx_thread_fiq_context_save.s index bc99650a..67bc6290 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_fiq_context_save.s +++ b/ports/cortex_r5/ac5/src/tx_thread_fiq_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,43 +39,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_save Cortex-R5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save Cortex-R5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) @@ -90,7 +84,7 @@ _tx_thread_fiq_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state CMP r2, #0 ; Is this the first interrupt? @@ -105,7 +99,7 @@ _tx_thread_fiq_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -121,38 +115,38 @@ _tx_thread_fiq_context_save POP {lr} ; Recover ISR lr ENDIF - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; __tx_thread_fiq_not_nested_save -; } +; } ; ; /* Otherwise, not nested, check to see if a thread was running. */ ; else if (_tx_thread_current_ptr) -; { +; { ; ADD r2, r2, #1 ; Increment the interrupt counter STR r2, [r3] ; Store it back in the variable LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in -; ; scheduling loop - nothing needs saving! + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, lr} ; Store other registers, Note that we don't -; ; need to save sl and ip since FIQ has -; ; copies of these registers. Nested +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested ; ; interrupt processing does need to save ; ; these registers. ; ; /* Save the current stack pointer in the thread's control block. */ -; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; ; ; /* Switch to the system stack. */ -; sp = _tx_thread_system_stack_ptr; +; sp = _tx_thread_system_stack_ptr; ; MOV r10, #0 ; Clear stack limit @@ -165,7 +159,7 @@ __tx_thread_fiq_not_nested_save POP {lr} ; Recover ISR lr ENDIF - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } ; else @@ -185,18 +179,18 @@ __tx_thread_fiq_idle_system_save ENDIF ; ; /* Not much to do here, save the current SPSR and LR for possible -; use in IRQ interrupted in idle system conditions, and return to +; use in IRQ interrupted in idle system conditions, and return to ; FIQ interrupt processing. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, lr} ; Store other registers that will get used -; ; or stripped off the stack in context -; ; restore - B __tx_fiq_processing_return ; Continue FIQ processing +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } -;} +;} ; END diff --git a/ports/cortex_r5/ac5/src/tx_thread_fiq_nesting_end.s b/ports/cortex_r5/ac5/src/tx_thread_fiq_nesting_end.s index 89e58b50..091737b6 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_fiq_nesting_end.s +++ b/ports/cortex_r5/ac5/src/tx_thread_fiq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,56 +34,50 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_end Cortex-R5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end Cortex-R5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ -;/* processing from system mode back to FIQ mode prior to the ISR */ -;/* calling _tx_thread_fiq_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with FIQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) @@ -94,7 +88,7 @@ _tx_thread_fiq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_c, r0 ; Disable interrupts - LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports/cortex_r5/ac5/src/tx_thread_fiq_nesting_start.s b/ports/cortex_r5/ac5/src/tx_thread_fiq_nesting_start.s index 224966a7..d4b870ac 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_fiq_nesting_start.s +++ b/ports/cortex_r5/ac5/src/tx_thread_fiq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_start Cortex-R5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start Cortex-R5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ -;/* processing to the system mode so nested FIQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with FIQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_r5/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_r5/ac5/src/tx_thread_interrupt_control.s index 2a3698d7..97dbf4f7 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_interrupt_control.s +++ b/ports/cortex_r5/ac5/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,42 +36,36 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control Cortex-R5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-R5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_r5/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_r5/ac5/src/tx_thread_interrupt_disable.s index 7af79f59..bf80f986 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_r5/ac5/src/tx_thread_interrupt_disable.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,41 +29,35 @@ ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable Cortex-R5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-R5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(void) @@ -80,7 +74,7 @@ _tx_thread_interrupt_disable IF :DEF:TX_ENABLE_FIQ_SUPPORT CPSID if ; Disable IRQ and FIQ ELSE - CPSID i ; Disable IRQ + CPSID i ; Disable IRQ ENDIF IF {INTER} = {TRUE} diff --git a/ports/cortex_r5/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_r5/ac5/src/tx_thread_interrupt_restore.s index 61ebae01..9e1bafaf 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_r5/ac5/src/tx_thread_interrupt_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,42 +29,36 @@ ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore Cortex-R5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-R5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function is responsible for restoring interrupts to the state */ ;/* returned by a previous _tx_thread_interrupt_disable call. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_r5/ac5/src/tx_thread_irq_nesting_end.s b/ports/cortex_r5/ac5/src/tx_thread_irq_nesting_end.s index 5b85a17f..00f1f123 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_irq_nesting_end.s +++ b/ports/cortex_r5/ac5/src/tx_thread_irq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,56 +34,50 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_end Cortex-R5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-R5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -;/* processing from system mode back to IRQ mode prior to the ISR */ -;/* calling _tx_thread_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) @@ -94,7 +88,7 @@ _tx_thread_irq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_c, r0 ; Disable interrupts - LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports/cortex_r5/ac5/src/tx_thread_irq_nesting_start.s b/ports/cortex_r5/ac5/src/tx_thread_irq_nesting_start.s index f46318ae..819449cc 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_irq_nesting_start.s +++ b/ports/cortex_r5/ac5/src/tx_thread_irq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_start Cortex-R5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-R5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_context_save has been called and switches the IRQ */ -;/* processing to the system mode so nested IRQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_r5/ac5/src/tx_thread_schedule.s b/ports/cortex_r5/ac5/src/tx_thread_schedule.s index 0144fb47..b50d0614 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_r5/ac5/src/tx_thread_schedule.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -40,45 +40,39 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule Cortex-R5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-R5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -107,7 +101,7 @@ __tx_thread_schedule_loop ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Lockout interrupts and ; transfer control to it. */ ; @@ -120,7 +114,7 @@ __tx_thread_schedule_loop ; /* Setup the current thread pointer. */ ; _tx_thread_current_ptr = _tx_thread_execute_ptr; ; - LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread STR r0, [r1, #0] ; Setup current thread pointer ; ; /* Increment the run count for this thread. */ @@ -134,7 +128,7 @@ __tx_thread_schedule_loop ; /* Setup time-slice, if present. */ ; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; ; - LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice ; variable LDR sp, [r0, #8] ; Switch stack pointers STR r3, [r2, #0] ; Setup time-slice diff --git a/ports/cortex_r5/ac5/src/tx_thread_stack_build.s b/ports/cortex_r5/ac5/src/tx_thread_stack_build.s index af6a3657..899e6ade 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_stack_build.s +++ b/ports/cortex_r5/ac5/src/tx_thread_stack_build.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -41,44 +41,38 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build Cortex-R5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-R5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function builds a stack frame on the supplied thread's stack. */ ;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ ;/* thread_ptr Pointer to thread control blk */ ;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -86,10 +80,10 @@ THUMB_BIT EQU 0x20 ; Thumb-bit EXPORT _tx_thread_stack_build _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-R5 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; a1 (r0) Initial value for a1 diff --git a/ports/cortex_r5/ac5/src/tx_thread_system_return.s b/ports/cortex_r5/ac5/src/tx_thread_system_return.s index 69ed81f1..ac35c95f 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_system_return.s +++ b/ports/cortex_r5/ac5/src/tx_thread_system_return.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -33,50 +33,44 @@ IMPORT _tx_timer_time_slice IMPORT _tx_thread_schedule IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY - IMPORT _tx_execution_thread_exit + IMPORT _tx_execution_thread_exit ENDIF ; ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return Cortex-R5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-R5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -110,7 +104,7 @@ _tx_skip_solicited_vfp_save MOV r0, #0 ; Build a solicited stack type STMDB sp!, {r0-r1} ; Save type and CPSR -; +; ; IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; diff --git a/ports/cortex_r5/ac5/src/tx_thread_vectored_context_save.s b/ports/cortex_r5/ac5/src/tx_thread_vectored_context_save.s index c1dad6a9..b1918801 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_vectored_context_save.s +++ b/ports/cortex_r5/ac5/src/tx_thread_vectored_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -38,43 +38,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_vectored_context_save Cortex-R5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-R5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) @@ -107,7 +101,7 @@ _tx_thread_vectored_context_save ; /* Return to the ISR. */ ; MOV r10, #0 ; Clear stack limit - + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; ; /* Call the ISR enter function to indicate an ISR is executing. */ @@ -135,7 +129,7 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Note: Minimal context of interrupted thread is already saved. */ @@ -171,7 +165,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports/cortex_r5/ac5/src/tx_timer_interrupt.s b/ports/cortex_r5/ac5/src/tx_timer_interrupt.s index f2408e30..89bc535c 100644 --- a/ports/cortex_r5/ac5/src/tx_timer_interrupt.s +++ b/ports/cortex_r5/ac5/src/tx_timer_interrupt.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -44,46 +44,40 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt Cortex-R5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-R5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -107,7 +101,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CMP r2, #0 ; Is it non-active? BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing @@ -225,13 +219,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CMP r2, #0 ; See if the flag is set BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing ; diff --git a/ports/cortex_r5/ac6/example_build/sample_threadx/.cproject b/ports/cortex_r5/ac6/example_build/sample_threadx/.cproject index bcac3d15..01a0335e 100644 --- a/ports/cortex_r5/ac6/example_build/sample_threadx/.cproject +++ b/ports/cortex_r5/ac6/example_build/sample_threadx/.cproject @@ -1,170 +1,170 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_r5/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_r5/ac6/example_build/sample_threadx/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports/cortex_r5/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports/cortex_r5/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_r5/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_r5/ac6/example_build/sample_threadx/sample_threadx.scat index c13f39f8..4b7265d3 100644 --- a/ports/cortex_r5/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports/cortex_r5/ac6/example_build/sample_threadx/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2011-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports/cortex_r5/ac6/example_build/sample_threadx/startup.S b/ports/cortex_r5/ac6/example_build/sample_threadx/startup.S index 584f08a1..e67cfc98 100644 --- a/ports/cortex_r5/ac6/example_build/sample_threadx/startup.S +++ b/ports/cortex_r5/ac6/example_build/sample_threadx/startup.S @@ -3,7 +3,7 @@ // // Copyright (c) 2006-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. //---------------------------------------------------------------- @@ -310,7 +310,7 @@ regions_done: // Enable Branch prediction //---------------------------------------------------------------- -// In the Cortex-R5, the Z-bit of the SCTLR does not control the program flow prediction. +// In the Cortex-R5, the Z-bit of the SCTLR does not control the program flow prediction. // Some control bits in the ACTLR control the program flow and prefetch features instead. // These are enabled by default, but are shown here for completeness. diff --git a/ports/cortex_r5/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_r5/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 1f80ff96..3913a0cb 100644 --- a/ports/cortex_r5/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_r5/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Initialize */ @/** */ @@ -59,7 +59,7 @@ SYS_STACK_SIZE = 1024 @ System stack size .type $_tx_initialize_low_level,function $_tx_initialize_low_level: BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_initialize_low_level @ Call _tx_initialize_low_level function @@ -69,45 +69,39 @@ $_tx_initialize_low_level: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_initialize_low_level Cortex-R5/AC6 */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level Cortex-R5/AC6 */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is responsible for any low-level processor */ -@/* initialization, including setting up interrupt vectors, setting */ -@/* up a periodic timer interrupt source, saving the system stack */ -@/* pointer for use in ISR processing later, and finding the first */ -@/* available RAM memory address for tx_application_define. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_initialize_kernel_enter ThreadX entry function */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) @@ -122,7 +116,7 @@ _tx_initialize_low_level: @ LDR r1, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit @ Get pointer to stack area -#ifdef TX_ENABLE_IRQ_NESTING +#ifdef TX_ENABLE_IRQ_NESTING @ @ /* Setup the system mode stack for nested interrupt support */ @ @@ -153,7 +147,7 @@ _tx_initialize_low_level: MSR CPSR, r0 @ Enter SVC mode LDR r2, =Image$$ARM_LIB_STACKHEAP$$Base @ Pickup stack bottom CMP r3, r2 @ Compare the current stack end with the bottom -_stack_error_loop: +_stack_error_loop: BLT _stack_error_loop @ If the IRQ stack exceeds the stack bottom, just sit here! @ @ /* Save the system stack pointer. */ @@ -214,17 +208,17 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. In +@ interrupt, and all C scratch registers are available for use. In @ addition, IRQ interrupts may be re-enabled - with certain restrictions - @ if nested IRQ interrupts are desired. Interrupts may be re-enabled over -@ small code sequences where lr is saved before enabling interrupts and +@ small code sequences where lr is saved before enabling interrupts and @ restored after interrupts are again disabled. */ @ -@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start @ from IRQ mode with interrupts disabled. This routine switches to the -@ system mode and returns with IRQ interrupts enabled. -@ -@ NOTE: It is very important to ensure all IRQ interrupts are cleared +@ system mode and returns with IRQ interrupts enabled. +@ +@ NOTE: It is very important to ensure all IRQ interrupts are cleared @ prior to enabling nested IRQ interrupts. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -238,7 +232,7 @@ __tx_irq_processing_return: @ @ @ /* If interrupt nesting was started earlier, the end of interrupt nesting -@ service must be called before returning to _tx_thread_context_restore. +@ service must be called before returning to _tx_thread_context_restore. @ This routine returns in processing in IRQ mode with interrupts disabled. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -254,28 +248,28 @@ __tx_irq_processing_return: @__tx_example_vectored_irq_handler: @ @ -@ /* Save initial context and call context save to prepare for +@ /* Save initial context and call context save to prepare for @ vectored ISR execution. */ @ @ STMDB sp!, {r0-r3} @ Save some scratch registers @ MRS r0, SPSR @ Pickup saved SPSR -@ SUB lr, lr, #4 @ Adjust point of interrupt +@ SUB lr, lr, #4 @ Adjust point of interrupt @ STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers @ BL _tx_thread_vectored_context_save @ Vectored context save @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. In +@ interrupt, and all C scratch registers are available for use. In @ addition, IRQ interrupts may be re-enabled - with certain restrictions - @ if nested IRQ interrupts are desired. Interrupts may be re-enabled over -@ small code sequences where lr is saved before enabling interrupts and +@ small code sequences where lr is saved before enabling interrupts and @ restored after interrupts are again disabled. */ @ @ -@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start @ from IRQ mode with interrupts disabled. This routine switches to the -@ system mode and returns with IRQ interrupts enabled. -@ -@ NOTE: It is very important to ensure all IRQ interrupts are cleared +@ system mode and returns with IRQ interrupts enabled. +@ +@ NOTE: It is very important to ensure all IRQ interrupts are cleared @ prior to enabling nested IRQ interrupts. */ @#ifdef TX_ENABLE_IRQ_NESTING @ BL _tx_thread_irq_nesting_start @@ -284,7 +278,7 @@ __tx_irq_processing_return: @ /* Application IRQ handlers can be called here! */ @ @ /* If interrupt nesting was started earlier, the end of interrupt nesting -@ service must be called before returning to _tx_thread_context_restore. +@ service must be called before returning to _tx_thread_context_restore. @ This routine returns in processing in IRQ mode with interrupts disabled. */ @#ifdef TX_ENABLE_IRQ_NESTING @ BL _tx_thread_irq_nesting_end @@ -306,11 +300,11 @@ __tx_fiq_processing_return: @ /* At this point execution is still in the FIQ mode. The CPSR, point of @ interrupt, and all C scratch registers are available for use. */ @ -@ /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +@ /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start @ from FIQ mode with interrupts disabled. This routine switches to the -@ system mode and returns with FIQ interrupts enabled. +@ system mode and returns with FIQ interrupts enabled. @ -@ NOTE: It is very important to ensure all FIQ interrupts are cleared +@ NOTE: It is very important to ensure all FIQ interrupts are cleared @ prior to enabling nested FIQ interrupts. */ #ifdef TX_ENABLE_FIQ_NESTING BL _tx_thread_fiq_nesting_start diff --git a/ports/cortex_r5/ac6/example_build/tx/.cproject b/ports/cortex_r5/ac6/example_build/tx/.cproject index aa051b97..63d5638f 100644 --- a/ports/cortex_r5/ac6/example_build/tx/.cproject +++ b/ports/cortex_r5/ac6/example_build/tx/.cproject @@ -1,150 +1,150 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports/cortex_r5/ac6/inc/tx_port.h b/ports/cortex_r5/ac6/inc/tx_port.h index 06f1f80a..360e3178 100644 --- a/ports/cortex_r5/ac6/inc/tx_port.h +++ b/ports/cortex_r5/ac6/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Cortex-R5/AC6 */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-R5/AC6 */ /* 6.1.12 */ /* */ /* AUTHOR */ @@ -32,27 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 07-29-2022 Scott Larson Updated comments, removed */ -/* unneeded temp variable, */ -/* resulting in version 6.1.12 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -65,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -78,7 +67,7 @@ #include -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -114,12 +103,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -129,8 +118,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -177,7 +166,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -189,13 +178,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -209,11 +198,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -221,8 +210,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -249,24 +238,24 @@ typedef unsigned short USHORT; #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ - + #if __TARGET_ARCH_ARM > 4 #ifndef __thumb__ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ asm volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); \ - b = 31 - b; + b = 31 - b; #endif #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -310,8 +299,8 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-R5/AC6 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R5/AC6 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r5/ac6/readme_threadx.txt b/ports/cortex_r5/ac6/readme_threadx.txt index f2b1b0a4..1efd85af 100644 --- a/ports/cortex_r5/ac6/readme_threadx.txt +++ b/ports/cortex_r5/ac6/readme_threadx.txt @@ -1,18 +1,18 @@ - Microsoft's Azure RTOS ThreadX for Cortex-R5 + Microsoft's Azure RTOS ThreadX for Cortex-R5 Using ARM Compiler 6 & DS 1. Import the ThreadX Projects -In order to build the ThreadX library and the ThreadX demonstration, first import -the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +In order to build the ThreadX library and the ThreadX demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) into your DS workspace. 2. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply right-click the Eclipse project -"tx" and then select the "Build Project" button. You should now observe the compilation +Building the ThreadX library is easy; simply right-click the Eclipse project +"tx" and then select the "Build Project" button. You should now observe the compilation and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. @@ -22,44 +22,44 @@ library file tx.a. The ThreadX demonstration is designed to execute under the DS debugger on the VE_Cortex-R5 Bare Metal simulator. -Building the demonstration is easy; simply right-click the Eclipse project -"sample_threadx" and then select the "Build Project" button. You should now observe -the compilation and assembly of the ThreadX demonstration. This project build produces -the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder +Building the demonstration is easy; simply right-click the Eclipse project +"sample_threadx" and then select the "Build Project" button. You should now observe +the compilation and assembly of the ThreadX demonstration. This project build produces +the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder in the Project Explorer window, right-click on the 'cortex-r5_tx.launch' file, click 'Debug As', and then click 'cortex-r5_tx' from the submenu. This will cause the -debugger to load the sample_threadx.axf ELF file and run to main. You are now ready +debugger to load the sample_threadx.axf ELF file and run to main. You are now ready to execute the ThreadX demonstration. 4. System Initialization -The entry point in ThreadX for the Cortex-R5 using ARM tools is at label -"Vectors". This is defined within startup.S in the sample_threadx project. In addition, -this is where all static and global pre-set C variable initialization processing +The entry point in ThreadX for the Cortex-R5 using ARM tools is at label +"Vectors". This is defined within startup.S in the sample_threadx project. In addition, +this is where all static and global pre-set C variable initialization processing takes place. -This is also where initialization of a periodic timer interrupt source should take +This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level defines the first available address -for use by the application, which is supplied as the sole input parameter +In addition, _tx_initialize_low_level defines the first available address +for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 5. Register Usage and Stack Frames -The AC6 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The AC6 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -77,52 +77,52 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-R5 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-R5 vectors start at address zero. The demonstration system startup -reset.S file contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +reset.S file contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs -ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -130,7 +130,7 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -143,7 +143,7 @@ __tx_irq_processing_return: 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_example_handler @@ -153,12 +153,12 @@ __tx_irq_example_handler: STMDB sp!, {r0-r3} @ Save some scratch registers MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers BL _tx_thread_vectored_context_save @ Call the vectored IRQ context save @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -175,22 +175,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.S. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables -nesting by disabling IRQ interrupts and switching back to IRQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -198,10 +198,10 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* Enable nested IRQ interrupts. NOTE: Since this service returns -@ with IRQ interrupts enabled, all IRQ interrupt sources must be +@ with IRQ interrupts enabled, all IRQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start -@ +@ @ /* Application ISR call(s) go here! */ @ @ /* Disable nested IRQ interrupts. The mode is switched back to @@ -214,12 +214,12 @@ __tx_irq_processing_return: 7.3 FIQ Interrupts -By default, FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.S. @@ -228,7 +228,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.S. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.S: @@ -256,18 +256,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.S. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -283,7 +283,7 @@ __tx_fiq_processing_return: @ interrupt, and all C scratch registers are available for use. */ @ @ /* Enable nested FIQ interrupts. NOTE: Since this service returns -@ with FIQ interrupts enabled, all FIQ interrupt sources must be +@ with FIQ interrupts enabled, all FIQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start @ @@ -299,12 +299,12 @@ __tx_fiq_processing_return: 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer -interrupt source, these services are not functional but the remainder of +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of ThreadX will still run. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.S for the demonstration system. diff --git a/ports/cortex_r5/ac6/src/tx_thread_context_restore.S b/ports/cortex_r5/ac6/src/tx_thread_context_restore.S index 198d4ad1..da9ae44f 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_r5/ac6/src/tx_thread_context_restore.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -49,48 +49,42 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @ @/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore @ since it will never be called 16-bit mode. */ -@ +@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_context_restore Cortex-R5/AC6 */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore Cortex-R5/AC6 */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function restores the interrupt context if it is processing a */ -@/* nested interrupt. If not, it returns to the interrupt thread if no */ -@/* preemption is necessary. Otherwise, if preemption is necessary or */ -@/* if no thread was running, the function returns to the scheduler. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling routine */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs Interrupt Service Routines */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) @@ -121,13 +115,13 @@ _tx_thread_context_restore: LDR r3, =_tx_thread_system_state @ Pickup address of system state variable LDR r2, [r3] @ Pickup system state SUB r2, r2, #1 @ Decrement the counter - STR r2, [r3] @ Store the counter + STR r2, [r3] @ Store the counter CMP r2, #0 @ Was this the first interrupt? BEQ __tx_thread_not_nested_restore @ If so, not a nested restore @ @ /* Interrupts are nested. */ @ -@ /* Just recover the saved registers and return to the point of +@ /* Just recover the saved registers and return to the point of @ interrupt. */ @ LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs diff --git a/ports/cortex_r5/ac6/src/tx_thread_context_save.S b/ports/cortex_r5/ac6/src/tx_thread_context_save.S index 26440a92..f0324d69 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_r5/ac6/src/tx_thread_context_save.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -37,47 +37,41 @@ @ @/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save @ since it will never be called 16-bit mode. */ -@ +@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_context_save Cortex-R5/AC6 */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save Cortex-R5/AC6 */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function saves the context of an executing thread in the */ -@/* beginning of interrupt processing. The function also ensures that */ -@/* the system stack is used upon return to the calling ISR. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) @@ -93,7 +87,7 @@ _tx_thread_context_save: @ if (_tx_thread_system_state++) @ { @ - STMDB sp!, {r0-r3} @ Save some working registers + STMDB sp!, {r0-r3} @ Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if @ Disable FIQ interrupts #endif @@ -111,7 +105,7 @@ _tx_thread_context_save: @ calling ISR. */ @ MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other registers @ @ /* Return to the ISR. */ @@ -127,7 +121,7 @@ _tx_thread_context_save: POP {lr} @ Recover ISR lr #endif - B __tx_irq_processing_return @ Continue IRQ processing + B __tx_irq_processing_return @ Continue IRQ processing @ __tx_thread_not_nested_save: @ } @@ -141,13 +135,13 @@ __tx_thread_not_nested_save: LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr LDR r0, [r1] @ Pickup current thread pointer CMP r0, #0 @ Is it NULL? - BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in @ scheduling loop - nothing needs saving! @ @ /* Save minimal context of interrupted thread. */ @ MRS r2, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} @ Store other registers @ @ /* Save the current stack pointer in the thread's control block. */ @@ -167,7 +161,7 @@ __tx_thread_not_nested_save: POP {lr} @ Recover ISR lr #endif - B __tx_irq_processing_return @ Continue IRQ processing + B __tx_irq_processing_return @ Continue IRQ processing @ @ } @ else @@ -177,7 +171,7 @@ __tx_thread_idle_system_save: @ @ /* Interrupt occurred in the scheduling loop. */ @ -@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ @ processing. */ @ MOV r10, #0 @ Clear stack limit @@ -192,7 +186,7 @@ __tx_thread_idle_system_save: #endif ADD sp, sp, #16 @ Recover saved registers - B __tx_irq_processing_return @ Continue IRQ processing + B __tx_irq_processing_return @ Continue IRQ processing @ @ } @} diff --git a/ports/cortex_r5/ac6/src/tx_thread_fiq_context_restore.S b/ports/cortex_r5/ac6/src/tx_thread_fiq_context_restore.S index 8a46e22c..51fe146b 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_r5/ac6/src/tx_thread_fiq_context_restore.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -32,7 +32,7 @@ @ SVC_MODE = 0xD3 @ SVC mode FIQ_MODE = 0xD1 @ FIQ mode -MODE_MASK = 0x1F @ Mode mask +MODE_MASK = 0x1F @ Mode mask THUMB_MASK = 0x20 @ Thumb bit mask IRQ_MODE_BITS = 0x12 @ IRQ mode bits @ @@ -52,44 +52,38 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_fiq_context_restore Cortex-R5/AC6 */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_restore Cortex-R5/AC6 */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function restores the fiq interrupt context when processing a */ -@/* nested interrupt. If not, it returns to the interrupt thread if no */ -@/* preemption is necessary. Otherwise, if preemption is necessary or */ -@/* if no thread was running, the function returns to the scheduler. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling routine */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* FIQ ISR Interrupt Service Routines */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function restores the fiq interrupt context when processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* FIQ ISR Interrupt Service Routines */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_context_restore(VOID) @@ -116,13 +110,13 @@ _tx_thread_fiq_context_restore: LDR r3, =_tx_thread_system_state @ Pickup address of system state variable LDR r2, [r3] @ Pickup system state SUB r2, r2, #1 @ Decrement the counter - STR r2, [r3] @ Store the counter + STR r2, [r3] @ Store the counter CMP r2, #0 @ Was this the first interrupt? BEQ __tx_thread_fiq_not_nested_restore @ If so, not a nested restore @ @ /* Interrupts are nested. */ @ -@ /* Just recover the saved registers and return to the point of +@ /* Just recover the saved registers and return to the point of @ interrupt. */ @ LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs @@ -210,7 +204,7 @@ __tx_thread_fiq_preempt_restore: BEQ __tx_thread_fiq_dont_save_ts @ No, don't save it @ @ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; -@ _tx_timer_time_slice = 0; +@ _tx_timer_time_slice = 0; @ STR r2, [r0, #24] @ Save thread's time-slice MOV r2, #0 @ Clear value diff --git a/ports/cortex_r5/ac6/src/tx_thread_fiq_context_save.S b/ports/cortex_r5/ac6/src/tx_thread_fiq_context_save.S index a898aa07..15303740 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_r5/ac6/src/tx_thread_fiq_context_save.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -40,43 +40,37 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_fiq_context_save Cortex-R5/AC6 */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_save Cortex-R5/AC6 */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function saves the context of an executing thread in the */ -@/* beginning of interrupt processing. The function also ensures that */ -@/* the system stack is used upon return to the calling ISR. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @ VOID _tx_thread_fiq_context_save(VOID) @@ -92,7 +86,7 @@ _tx_thread_fiq_context_save: @ if (_tx_thread_system_state++) @ { @ - STMDB sp!, {r0-r3} @ Save some working registers + STMDB sp!, {r0-r3} @ Save some working registers LDR r3, =_tx_thread_system_state @ Pickup address of system state variable LDR r2, [r3] @ Pickup system state CMP r2, #0 @ Is this the first interrupt? @@ -107,7 +101,7 @@ _tx_thread_fiq_context_save: @ calling ISR. */ @ MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other registers @ @ /* Return to the ISR. */ @@ -123,38 +117,38 @@ _tx_thread_fiq_context_save: POP {lr} @ Recover ISR lr #endif - B __tx_fiq_processing_return @ Continue FIQ processing + B __tx_fiq_processing_return @ Continue FIQ processing @ __tx_thread_fiq_not_nested_save: -@ } +@ } @ @ /* Otherwise, not nested, check to see if a thread was running. */ @ else if (_tx_thread_current_ptr) -@ { +@ { @ ADD r2, r2, #1 @ Increment the interrupt counter STR r2, [r3] @ Store it back in the variable LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr LDR r0, [r1] @ Pickup current thread pointer CMP r0, #0 @ Is it NULL? - BEQ __tx_thread_fiq_idle_system_save @ If so, interrupt occurred in -@ @ scheduling loop - nothing needs saving! + BEQ __tx_thread_fiq_idle_system_save @ If so, interrupt occurred in +@ @ scheduling loop - nothing needs saving! @ @ /* Save minimal context of interrupted thread. */ @ MRS r2, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r2, lr} @ Store other registers, Note that we don't -@ @ need to save sl and ip since FIQ has -@ @ copies of these registers. Nested +@ @ need to save sl and ip since FIQ has +@ @ copies of these registers. Nested @ @ interrupt processing does need to save @ @ these registers. @ @ /* Save the current stack pointer in the thread's control block. */ -@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; @ @ /* Switch to the system stack. */ -@ sp = _tx_thread_system_stack_ptr; +@ sp = _tx_thread_system_stack_ptr; @ MOV r10, #0 @ Clear stack limit @@ -167,7 +161,7 @@ __tx_thread_fiq_not_nested_save: POP {lr} @ Recover ISR lr #endif - B __tx_fiq_processing_return @ Continue FIQ processing + B __tx_fiq_processing_return @ Continue FIQ processing @ @ } @ else @@ -187,16 +181,16 @@ __tx_thread_fiq_idle_system_save: #endif @ @ /* Not much to do here, save the current SPSR and LR for possible -@ use in IRQ interrupted in idle system conditions, and return to +@ use in IRQ interrupted in idle system conditions, and return to @ FIQ interrupt processing. */ @ MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, lr} @ Store other registers that will get used -@ @ or stripped off the stack in context -@ @ restore - B __tx_fiq_processing_return @ Continue FIQ processing +@ @ or stripped off the stack in context +@ @ restore + B __tx_fiq_processing_return @ Continue FIQ processing @ @ } -@} +@} diff --git a/ports/cortex_r5/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_r5/ac6/src/tx_thread_fiq_nesting_end.S index d9d3d30b..9d61bf40 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_r5/ac6/src/tx_thread_fiq_nesting_end.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -34,7 +34,7 @@ DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts #else DISABLE_INTS = 0x80 @ Disable IRQ interrupts #endif -MODE_MASK = 0x1F @ Mode mask +MODE_MASK = 0x1F @ Mode mask FIQ_MODE_BITS = 0x11 @ FIQ mode bits @ @ @@ -44,51 +44,45 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_fiq_nesting_end Cortex-R5/AC6 */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_end Cortex-R5/AC6 */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from FIQ mode after */ -@/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ -@/* processing from system mode back to FIQ mode prior to the ISR */ -@/* calling _tx_thread_fiq_context_restore. Note that this function */ -@/* assumes the system stack pointer is in the same position after */ -@/* nesting start function was called. */ -@/* */ -@/* This function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with FIQ interrupts disabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +@/* processing from system mode back to FIQ mode prior to the ISR */ +@/* calling _tx_thread_fiq_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_end(VOID) @@ -100,7 +94,7 @@ _tx_thread_fiq_nesting_end: MRS r0, CPSR @ Pickup the CPSR ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value MSR CPSR_c, r0 @ Disable interrupts - LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for @ 8-byte alignment logic) BIC r0, r0, #MODE_MASK @ Clear mode bits ORR r0, r0, #FIQ_MODE_BITS @ Build IRQ mode CPSR diff --git a/ports/cortex_r5/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_r5/ac6/src/tx_thread_fiq_nesting_start.S index c3045e8c..54d16410 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_r5/ac6/src/tx_thread_fiq_nesting_start.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -40,48 +40,42 @@ SYS_MODE_BITS = 0x1F @ System mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_fiq_nesting_start Cortex-R5/AC6 */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_start Cortex-R5/AC6 */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from FIQ mode after */ -@/* _tx_thread_fiq_context_save has been called and switches the FIQ */ -@/* processing to the system mode so nested FIQ interrupt processing */ -@/* is possible (system mode has its own "lr" register). Note that */ -@/* this function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with FIQ interrupts enabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +@/* processing to the system mode so nested FIQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_r5/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_r5/ac6/src/tx_thread_interrupt_control.S index e73e4d7c..f99412f2 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_r5/ac6/src/tx_thread_interrupt_control.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -40,7 +40,7 @@ INT_MASK = 0x03F $_tx_thread_interrupt_control: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_interrupt_control @ Call _tx_thread_interrupt_control function @@ -50,42 +50,36 @@ $_tx_thread_interrupt_control: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_interrupt_control Cortex-R5/AC6 */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control Cortex-R5/AC6 */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is responsible for changing the interrupt lockout */ -@/* posture of the system. */ -@/* */ -@/* INPUT */ -@/* */ -@/* new_posture New interrupt lockout posture */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_r5/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_r5/ac6/src/tx_thread_interrupt_disable.S index 688d243d..1c52ec6f 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_r5/ac6/src/tx_thread_interrupt_disable.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -37,7 +37,7 @@ $_tx_thread_interrupt_disable: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_interrupt_disable @ Call _tx_thread_interrupt_disable function @@ -47,41 +47,35 @@ $_tx_thread_interrupt_disable: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_interrupt_disable Cortex-R5/AC6 */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_disable Cortex-R5/AC6 */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is responsible for disabling interrupts */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is responsible for disabling interrupts */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_disable(void) @@ -99,7 +93,7 @@ _tx_thread_interrupt_disable: #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if @ Disable IRQ and FIQ #else - CPSID i @ Disable IRQ + CPSID i @ Disable IRQ #endif #ifdef __THUMB_INTERWORK diff --git a/ports/cortex_r5/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_r5/ac6/src/tx_thread_interrupt_restore.S index 7872802b..6824ceee 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_r5/ac6/src/tx_thread_interrupt_restore.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -37,7 +37,7 @@ $_tx_thread_interrupt_restore: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_interrupt_restore @ Call _tx_thread_interrupt_restore function @@ -47,42 +47,36 @@ $_tx_thread_interrupt_restore: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_interrupt_restore Cortex-R5/AC6 */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_restore Cortex-R5/AC6 */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ +@/* */ @/* This function is responsible for restoring interrupts to the state */ @/* returned by a previous _tx_thread_interrupt_disable call. */ -@/* */ -@/* INPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* INPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_r5/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_r5/ac6/src/tx_thread_irq_nesting_end.S index 5d58b2a5..aab78cfd 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_r5/ac6/src/tx_thread_irq_nesting_end.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -34,7 +34,7 @@ DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts #else DISABLE_INTS = 0x80 @ Disable IRQ interrupts #endif -MODE_MASK = 0x1F @ Mode mask +MODE_MASK = 0x1F @ Mode mask IRQ_MODE_BITS = 0x12 @ IRQ mode bits @ @ @@ -44,51 +44,45 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_irq_nesting_end Cortex-R5/AC6 */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_end Cortex-R5/AC6 */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from IRQ mode after */ -@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -@/* processing from system mode back to IRQ mode prior to the ISR */ -@/* calling _tx_thread_context_restore. Note that this function */ -@/* assumes the system stack pointer is in the same position after */ -@/* nesting start function was called. */ -@/* */ -@/* This function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with IRQ interrupts disabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +@/* processing from system mode back to IRQ mode prior to the ISR */ +@/* calling _tx_thread_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_end(VOID) @@ -100,7 +94,7 @@ _tx_thread_irq_nesting_end: MRS r0, CPSR @ Pickup the CPSR ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value MSR CPSR_c, r0 @ Disable interrupts - LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for @ 8-byte alignment logic) BIC r0, r0, #MODE_MASK @ Clear mode bits ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR diff --git a/ports/cortex_r5/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_r5/ac6/src/tx_thread_irq_nesting_start.S index 33aa6f37..7a5cb91b 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_r5/ac6/src/tx_thread_irq_nesting_start.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -40,48 +40,42 @@ SYS_MODE_BITS = 0x1F @ System mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_irq_nesting_start Cortex-R5/AC6 */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_start Cortex-R5/AC6 */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from IRQ mode after */ -@/* _tx_thread_context_save has been called and switches the IRQ */ -@/* processing to the system mode so nested IRQ interrupt processing */ -@/* is possible (system mode has its own "lr" register). Note that */ -@/* this function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with IRQ interrupts enabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_context_save has been called and switches the IRQ */ +@/* processing to the system mode so nested IRQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_r5/ac6/src/tx_thread_schedule.S b/ports/cortex_r5/ac6/src/tx_thread_schedule.S index b895b143..dc014e83 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_r5/ac6/src/tx_thread_schedule.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -45,7 +45,7 @@ $_tx_thread_schedule: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_schedule @ Call _tx_thread_schedule function @@ -55,45 +55,39 @@ $_tx_thread_schedule: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_schedule Cortex-R5/AC6 */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_schedule Cortex-R5/AC6 */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function waits for a thread control block pointer to appear in */ -@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -@/* in the variable, the corresponding thread is resumed. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_initialize_kernel_enter ThreadX entry function */ -@/* _tx_thread_system_return Return to system from thread */ -@/* _tx_thread_context_restore Restore thread's context */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function waits for a thread control block pointer to appear in */ +@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +@/* in the variable, the corresponding thread is resumed. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* _tx_thread_system_return Return to system from thread */ +@/* _tx_thread_context_restore Restore thread's context */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) @@ -123,7 +117,7 @@ __tx_thread_schedule_loop: @ @ } @ while(_tx_thread_execute_ptr == TX_NULL); -@ +@ @ /* Yes! We have a thread to execute. Lockout interrupts and @ transfer control to it. */ @ @@ -136,7 +130,7 @@ __tx_thread_schedule_loop: @ /* Setup the current thread pointer. */ @ _tx_thread_current_ptr = _tx_thread_execute_ptr; @ - LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread STR r0, [r1] @ Setup current thread pointer @ @ /* Increment the run count for this thread. */ @@ -150,7 +144,7 @@ __tx_thread_schedule_loop: @ /* Setup time-slice, if present. */ @ _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; @ - LDR r2, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r2, =_tx_timer_time_slice @ Pickup address of time-slice @ variable LDR sp, [r0, #8] @ Switch stack pointers STR r3, [r2] @ Setup time-slice diff --git a/ports/cortex_r5/ac6/src/tx_thread_stack_build.S b/ports/cortex_r5/ac6/src/tx_thread_stack_build.S index 2b2de3dd..30dac972 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_r5/ac6/src/tx_thread_stack_build.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -48,7 +48,7 @@ CPSR_MASK = 0x9F @ Mask initial CPSR, IRQ interru .type $_tx_thread_stack_build,function $_tx_thread_stack_build: BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_stack_build @ Call _tx_thread_stack_build function @@ -58,44 +58,38 @@ $_tx_thread_stack_build: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_stack_build Cortex-R5/AC6 */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build Cortex-R5/AC6 */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ +@/* */ @/* This function builds a stack frame on the supplied thread's stack. */ @/* The stack frame results in a fake interrupt return to the supplied */ -@/* function pointer. */ -@/* */ -@/* INPUT */ -@/* */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ @/* thread_ptr Pointer to thread control blk */ @/* function_ptr Pointer to return function */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_thread_create Create thread service */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -104,10 +98,10 @@ $_tx_thread_stack_build: .type _tx_thread_stack_build,function _tx_thread_stack_build: @ -@ +@ @ /* Build a fake interrupt frame. The form of the fake interrupt stack @ on the ARM9 should look like the following after it is built: -@ +@ @ Stack Top: 1 Interrupt stack frame type @ CPSR Initial value for CPSR @ a1 (r0) Initial value for a1 diff --git a/ports/cortex_r5/ac6/src/tx_thread_system_return.S b/ports/cortex_r5/ac6/src/tx_thread_system_return.S index 3ca9650e..50e5d2e2 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_r5/ac6/src/tx_thread_system_return.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -47,7 +47,7 @@ $_tx_thread_system_return: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_system_return @ Call _tx_thread_system_return function @@ -57,44 +57,38 @@ $_tx_thread_system_return: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_system_return Cortex-R5/AC6 */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return Cortex-R5/AC6 */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is target processor specific. It is used to transfer */ -@/* control from a thread back to the ThreadX system. Only a */ -@/* minimal context is saved since the compiler assumes temp registers */ -@/* are going to get slicked by a function call anyway. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling loop */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX components */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ @/* */ @/**************************************************************************/ @VOID _tx_thread_system_return(VOID) @@ -129,7 +123,7 @@ _tx_skip_solicited_vfp_save: @ MOV r0, #0 @ Build a solicited stack type STMDB sp!, {r0-r1} @ Save type and CPSR -@ +@ @ #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY @ diff --git a/ports/cortex_r5/ac6/src/tx_thread_vectored_context_save.S b/ports/cortex_r5/ac6/src/tx_thread_vectored_context_save.S index aa5bc2f3..b79d8792 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_r5/ac6/src/tx_thread_vectored_context_save.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -36,47 +36,41 @@ @ @/* No 16-bit Thumb mode veneer code is needed for _tx_thread_vectored_context_save @ since it will never be called 16-bit mode. */ -@ +@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_vectored_context_save Cortex-R5/AC6 */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_vectored_context_save Cortex-R5/AC6 */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function saves the context of an executing thread in the */ -@/* beginning of interrupt processing. The function also ensures that */ -@/* the system stack is used upon return to the calling ISR. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_vectored_context_save(VOID) @@ -134,7 +128,7 @@ __tx_thread_not_nested_save: LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr LDR r0, [r1, #0] @ Pickup current thread pointer CMP r0, #0 @ Is it NULL? - BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in @ scheduling loop - nothing needs saving! @ @ /* Note: Minimal context of interrupted thread is already saved. */ @@ -166,7 +160,7 @@ __tx_thread_idle_system_save: @ @ /* Interrupt occurred in the scheduling loop. */ @ -@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ @ processing. */ @ MOV r10, #0 @ Clear stack limit diff --git a/ports/cortex_r5/ac6/src/tx_timer_interrupt.S b/ports/cortex_r5/ac6/src/tx_timer_interrupt.S index 0261bddc..5bab06c0 100644 --- a/ports/cortex_r5/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_r5/ac6/src/tx_timer_interrupt.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Timer */ @/** */ @@ -55,7 +55,7 @@ .type $_tx_timer_interrupt,function $_tx_timer_interrupt: BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_timer_interrupt @ Call _tx_timer_interrupt function @@ -65,46 +65,40 @@ $_tx_timer_interrupt: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_timer_interrupt Cortex-R5/AC6 */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt Cortex-R5/AC6 */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function processes the hardware timer interrupt. This */ -@/* processing includes incrementing the system clock and checking for */ -@/* time slice and/or timer expiration. If either is found, the */ -@/* interrupt context save/restore functions are called along with the */ -@/* expiration functions. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_time_slice Time slice interrupted thread */ -@/* _tx_timer_expiration_process Timer expiration processing */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* interrupt vector */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) @@ -129,7 +123,7 @@ _tx_timer_interrupt: @ if (_tx_timer_time_slice) @ { @ - LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice LDR r2, [r3] @ Pickup time-slice CMP r2, #0 @ Is it non-active? BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing @@ -247,7 +241,7 @@ __tx_timer_dont_activate: @ if (_tx_timer_expired_time_slice) @ { @ - LDR r3, =_tx_timer_expired_time_slice @ Pickup address of time-slice expired + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of time-slice expired LDR r2, [r3] @ Pickup the actual flag CMP r2, #0 @ See if the flag is set BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing diff --git a/ports/cortex_r5/ghs/example_build/tx_initialize_low_level.arm b/ports/cortex_r5/ghs/example_build/tx_initialize_low_level.arm index 296a427d..e3dc99a5 100644 --- a/ports/cortex_r5/ghs/example_build/tx_initialize_low_level.arm +++ b/ports/cortex_r5/ghs/example_build/tx_initialize_low_level.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r5/ghs/inc/tx_el.h b/ports/cortex_r5/ghs/inc/tx_el.h index b8926921..72e5bbe3 100644 --- a/ports/cortex_r5/ghs/inc/tx_el.h +++ b/ports/cortex_r5/ghs/inc/tx_el.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,12 +37,6 @@ /* EventAnalyzer. It is assumed that tx_api.h and tx_port.h have */ /* already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_EL_H diff --git a/ports/cortex_r5/ghs/inc/tx_port.h b/ports/cortex_r5/ghs/inc/tx_port.h index 19c7de48..5b435fcb 100644 --- a/ports/cortex_r5/ghs/inc/tx_port.h +++ b/ports/cortex_r5/ghs/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -394,7 +386,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-R5/Green Hills Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R5/Green Hills Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r5/ghs/readme_threadx.txt b/ports/cortex_r5/ghs/readme_threadx.txt index 62383547..ac06719a 100644 --- a/ports/cortex_r5/ghs/readme_threadx.txt +++ b/ports/cortex_r5/ghs/readme_threadx.txt @@ -1,19 +1,19 @@ - Microsoft's Azure RTOS ThreadX for Cortex-R5 + Microsoft's Azure RTOS ThreadX for Cortex-R5 Using the Green Hills Software Tools 1. Open the ThreadX Project Workspace -In order to build the ThreadX library and the ThreadX demonstration first load -the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the -"example_build" directory. +In order to build the ThreadX library and the ThreadX demonstration first load +the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the +"example_build" directory. 2. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply select the MULTI project file -tx.gpj and then select the build button. You should now observe the -compilation and assembly of the ThreadX library. This project build produces +Building the ThreadX library is easy; simply select the MULTI project file +tx.gpj and then select the build button. You should now observe the +compilation and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. @@ -21,55 +21,55 @@ the ThreadX library file tx.a. The ThreadX demonstration is designed to execute under the MULTI environment on the Green Hills Cortex-R5 simulator. The instructions that follow describe -how to get the ThreadX evaluation running under the MULTI Cortex-R5 simulation +how to get the ThreadX evaluation running under the MULTI Cortex-R5 simulation environment. -Building the demonstration is easy; simply select the MULTI project file -sample_threadx.gpj. At this point, select the "Project Build" button and observe -the compilation, assembly, and linkage of the ThreadX demonstration application. +Building the demonstration is easy; simply select the MULTI project file +sample_threadx.gpj. At this point, select the "Project Build" button and observe +the compilation, assembly, and linkage of the ThreadX demonstration application. -After the demonstration is built, invoke the MULTI ARM simulator by selecting -the simulator connection from within the sample_threadx.con connection file. -Once connected to the simulator, select the "Debug" button. You should now -observe the main function of sample_threadx.c. +After the demonstration is built, invoke the MULTI ARM simulator by selecting +the simulator connection from within the sample_threadx.con connection file. +Once connected to the simulator, select the "Debug" button. You should now +observe the main function of sample_threadx.c. At this point, you should setup a simulated timer interrupt for ThreadX by entering "timer 9999 irq" in the "target" window of the debugger. -You are now ready to execute the ThreadX demonstration system. Select -breakpoints and data watches to observe the execution of the sample_threadx.c +You are now ready to execute the ThreadX demonstration system. Select +breakpoints and data watches to observe the execution of the sample_threadx.c application. 4. EventAnalyzer Demonstration -To build a demonstration system that also logs events for the MULTI EventAnalyzer, -perform the same steps as the regular demo, except build the ThreadX library with -txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. -The resulting image will log all system events, which can then be displayed by the +To build a demonstration system that also logs events for the MULTI EventAnalyzer, +perform the same steps as the regular demo, except build the ThreadX library with +txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. +The resulting image will log all system events, which can then be displayed by the MULTI EventAnalyzer. 5. System Initialization -The system entry point using the Green Hills tools is at the label _start. -This is defined within the crt0.arm file supplied by Green Hills. In addition, -this is where all static and global preset C variable initialization +The system entry point using the Green Hills tools is at the label _start. +This is defined within the crt0.arm file supplied by Green Hills. In addition, +this is where all static and global preset C variable initialization processing is called from. After the Green Hills startup function returns, ThreadX initialization is called. The main initialization function is _tx_initialize_low_level and -is located in the file tx_initialize_low_level.arm. This function is responsible -for setting up various system data structures, interrupt vectors, and the +is located in the file tx_initialize_low_level.arm. This function is responsible +for setting up various system data structures, interrupt vectors, and the periodic timer interrupt source of ThreadX. -In addition, _tx_initialize_low_level determines where the first available +In addition, _tx_initialize_low_level determines where the first available RAM memory address is located. This address is supplied to tx_application_define. -By default, the first available RAM memory address is assumed to start at the -beginning of the ThreadX section .free_mem. If changes are made to the -sample_threadx.ld file, the .free_mem section should remain the last allocated -section in the main RAM area. The starting address of this section is passed +By default, the first available RAM memory address is assumed to start at the +beginning of the ThreadX section .free_mem. If changes are made to the +sample_threadx.ld file, the .free_mem section should remain the last allocated +section in the main RAM area. The starting address of this section is passed to tx_application_define. @@ -87,27 +87,27 @@ The following defines and their associated action are as follows: TX_ENABLE_FIQ_NESTING If defined, this brings in special FIQ interrupt nesting logic into the ThreadX library. This define should be applied - to the entire ThreadX library and the + to the entire ThreadX library and the define TX_ENABLE_FIQ_SUPPORT should also be defined. TX_ENABLE_FIQ_SUPPORT If defined, this brings in FIQ context save and restore logic necessary for applications to call ThreadX services from - FIQ interrupt handlers. This define - should be applied to the entire ThreadX + FIQ interrupt handlers. This define + should be applied to the entire ThreadX library. TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 4 in the "ThreadX User Guide" + Chapter 4 in the "ThreadX User Guide" for more details. TX_ENABLE_EVENT_LOGGING This define enables event logging for any or all of the ThreadX source code. If this - option is used anywhere, the tx_initialize_high_level.c + option is used anywhere, the tx_initialize_high_level.c file must be compiled with it as well, since this is where the event log is initialized. @@ -119,121 +119,121 @@ The following defines and their associated action are as follows: If this is enabled, run-time filtering logic is added to the event logging code. - TX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. 7. Register Usage and Stack Frames -The Green Hills compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) -are scratch registers for each function. All other registers used by a C -function must be preserved by the function. ThreadX takes advantage of this -in situations where a context switch happens as a result of making a ThreadX -service call (which is itself a C function). In such cases, the saved +The Green Hills compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) +are scratch registers for each function. All other registers used by a C +function must be preserved by the function. ThreadX takes advantage of this +in situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -251,40 +251,40 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 8. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make ThreadX run faster, you can change the tx.gpj project -to disable debug information and enable the desired optimizations. +to disable debug information and enable the desired optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined before tx_api.h is included. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. 9. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-R5 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 9.1 Vector Area The Cortex-R5 vectors start at address zero. The demonstration system reset.arm -file contains the reset section (which contains all the ARM vectors) and is +file contains the reset section (which contains all the ARM vectors) and is typically loaded at address zero. On actual hardware platforms, this section -might have to be copied to address 0. +might have to be copied to address 0. 9.2 IRQ ISRs @@ -294,13 +294,13 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 9.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.arm: .globl __tx_irq_handler - .globl __tx_irq_processing_return + .globl __tx_irq_processing_return __tx_irq_handler: /* Jump to context save to save system context. */ @@ -308,7 +308,7 @@ __tx_irq_handler: __tx_irq_processing_return: /* At this point execution is still in the IRQ mode. The CPSR, point of - interrupt, and all C scratch registers are available for use. Note + interrupt, and all C scratch registers are available for use. Note that IRQ interrupts are still disabled upon return from the context save function. */ @@ -321,7 +321,7 @@ __tx_irq_processing_return: 9.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.arm: .globl __tx_irq_example_handler @@ -331,12 +331,12 @@ __tx_irq_example_handler: STMDB sp!, {r0-r3} # Save some scratch registers MRS r0, SPSR # Pickup saved SPSR - SUB lr, lr, #4 # Adjust point of interrupt + SUB lr, lr, #4 # Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} # Store other scratch registers BL _tx_thread_vectored_context_save # Call the vectored IRQ context save /* At this point execution is still in the IRQ mode. The CPSR, point of - interrupt, and all C scratch registers are available for use. Note + interrupt, and all C scratch registers are available for use. Note that IRQ interrupts are still disabled upon return from the context save function. */ @@ -353,22 +353,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.arm. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables nesting -by disabling IRQ interrupts and switching back to IRQ mode in preparation for +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.arm. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables nesting +by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in the +The following is an example of enabling IRQ nested interrupts in the typical IRQ handler: .globl __tx_irq_handler - .globl __tx_irq_processing_return + .globl __tx_irq_processing_return __tx_irq_handler: /* Jump to context save to save system context. */ @@ -376,10 +376,10 @@ __tx_irq_handler: __tx_irq_processing_return: /* Enable nested IRQ interrupts. NOTE: Since this service returns - with IRQ interrupts enabled, all IRQ interrupt sources must be + with IRQ interrupts enabled, all IRQ interrupt sources must be cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start - + /* Application ISR call(s) go here! */ /* Disable nested IRQ interrupts. The mode is switched back to @@ -392,9 +392,9 @@ __tx_irq_processing_return: 9.3 FIQ Interrupts -By default, Cortex-R5 FIQ interrupts are left completely enabled by ThreadX. -Of course, this means that the application is fully responsible for -saving/restoring any registers used in the FIQ ISR processing. In addition, +By default, Cortex-R5 FIQ interrupts are left completely enabled by ThreadX. +Of course, this means that the application is fully responsible for +saving/restoring any registers used in the FIQ ISR processing. In addition, no ThreadX service calls are allowed from the default FIQ ISRs. The default FIQ interrupt shell is located in tx_initialize_low_level.arm. @@ -403,7 +403,7 @@ FIQ interrupt shell is located in tx_initialize_low_level.arm. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.arm: @@ -431,18 +431,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.arm. When nested FIQ interrupts are no longer -required, calling the _tx_thread_fiq_nesting_end service disables nesting by -disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.arm. When nested FIQ interrupts are no longer +required, calling the _tx_thread_fiq_nesting_end service disables nesting by +disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -458,7 +458,7 @@ __tx_fiq_processing_return: interrupt, and all C scratch registers are available for use. */ /* Enable nested FIQ interrupts. NOTE: Since this service returns - with FIQ interrupts enabled, all FIQ interrupt sources must be + with FIQ interrupts enabled, all FIQ interrupt sources must be cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start @@ -475,29 +475,29 @@ __tx_fiq_processing_return: 10. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.arm. 11. Thumb/Cortex-R5 Mixed Mode -By default, ThreadX is setup for running in Cortex-R5 32-bit mode. This is -also true for the demonstration system. It is possible to build any +By default, ThreadX is setup for running in Cortex-R5 32-bit mode. This is +also true for the demonstration system. It is possible to build any ThreadX file and/or the application in Thumb mode. The only exception -to this is the file tx_thread_shell_entry.c. This file must always be +to this is the file tx_thread_shell_entry.c. This file must always be built in 32-bit mode. 12. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); @@ -520,7 +520,7 @@ information associated with this specific port of ThreadX: 04-02-2021 Release 6.1.6 changes: tx_port.h Updated macro definition -05/19/2020 Initial ThreadX version of Cortex-R5/Green Hills port. +05/19/2020 Initial ThreadX version of Cortex-R5/Green Hills port. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_r5/ghs/src/tx_el.c b/ports/cortex_r5/ghs/src/tx_el.c index 365622cd..b5d3b8b7 100644 --- a/ports/cortex_r5/ghs/src/tx_el.c +++ b/ports/cortex_r5/ghs/src/tx_el.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,12 +83,6 @@ UINT _tx_thread_interrupt_control(UINT new_posture); /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_el_initialize(VOID) { diff --git a/ports/cortex_r5/ghs/src/tx_thread_context_restore.arm b/ports/cortex_r5/ghs/src/tx_thread_context_restore.arm index 724b4995..b103b804 100644 --- a/ports/cortex_r5/ghs/src/tx_thread_context_restore.arm +++ b/ports/cortex_r5/ghs/src/tx_thread_context_restore.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r5/ghs/src/tx_thread_context_save.arm b/ports/cortex_r5/ghs/src/tx_thread_context_save.arm index 408ad512..29a95aae 100644 --- a/ports/cortex_r5/ghs/src/tx_thread_context_save.arm +++ b/ports/cortex_r5/ghs/src/tx_thread_context_save.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r5/ghs/src/tx_thread_fiq_context_restore.arm b/ports/cortex_r5/ghs/src/tx_thread_fiq_context_restore.arm index e1e917a2..4287f779 100644 --- a/ports/cortex_r5/ghs/src/tx_thread_fiq_context_restore.arm +++ b/ports/cortex_r5/ghs/src/tx_thread_fiq_context_restore.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r5/ghs/src/tx_thread_fiq_context_save.arm b/ports/cortex_r5/ghs/src/tx_thread_fiq_context_save.arm index 166a9898..28725995 100644 --- a/ports/cortex_r5/ghs/src/tx_thread_fiq_context_save.arm +++ b/ports/cortex_r5/ghs/src/tx_thread_fiq_context_save.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r5/ghs/src/tx_thread_fiq_nesting_end.arm b/ports/cortex_r5/ghs/src/tx_thread_fiq_nesting_end.arm index c00013a3..8e2dcd91 100644 --- a/ports/cortex_r5/ghs/src/tx_thread_fiq_nesting_end.arm +++ b/ports/cortex_r5/ghs/src/tx_thread_fiq_nesting_end.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r5/ghs/src/tx_thread_fiq_nesting_start.arm b/ports/cortex_r5/ghs/src/tx_thread_fiq_nesting_start.arm index 0ab401e4..b83c3661 100644 --- a/ports/cortex_r5/ghs/src/tx_thread_fiq_nesting_start.arm +++ b/ports/cortex_r5/ghs/src/tx_thread_fiq_nesting_start.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r5/ghs/src/tx_thread_interrupt_control.arm b/ports/cortex_r5/ghs/src/tx_thread_interrupt_control.arm index 66670a6b..a38ad2b5 100644 --- a/ports/cortex_r5/ghs/src/tx_thread_interrupt_control.arm +++ b/ports/cortex_r5/ghs/src/tx_thread_interrupt_control.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r5/ghs/src/tx_thread_interrupt_disable.arm b/ports/cortex_r5/ghs/src/tx_thread_interrupt_disable.arm index c632e920..bea8c467 100644 --- a/ports/cortex_r5/ghs/src/tx_thread_interrupt_disable.arm +++ b/ports/cortex_r5/ghs/src/tx_thread_interrupt_disable.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r5/ghs/src/tx_thread_interrupt_restore.arm b/ports/cortex_r5/ghs/src/tx_thread_interrupt_restore.arm index cf8d3220..1e3de8d8 100644 --- a/ports/cortex_r5/ghs/src/tx_thread_interrupt_restore.arm +++ b/ports/cortex_r5/ghs/src/tx_thread_interrupt_restore.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r5/ghs/src/tx_thread_irq_nesting_end.arm b/ports/cortex_r5/ghs/src/tx_thread_irq_nesting_end.arm index 34d15f49..a8085f71 100644 --- a/ports/cortex_r5/ghs/src/tx_thread_irq_nesting_end.arm +++ b/ports/cortex_r5/ghs/src/tx_thread_irq_nesting_end.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r5/ghs/src/tx_thread_irq_nesting_start.arm b/ports/cortex_r5/ghs/src/tx_thread_irq_nesting_start.arm index 5fa03cea..86bca486 100644 --- a/ports/cortex_r5/ghs/src/tx_thread_irq_nesting_start.arm +++ b/ports/cortex_r5/ghs/src/tx_thread_irq_nesting_start.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r5/ghs/src/tx_thread_schedule.arm b/ports/cortex_r5/ghs/src/tx_thread_schedule.arm index 50ea6b47..e0548e7f 100644 --- a/ports/cortex_r5/ghs/src/tx_thread_schedule.arm +++ b/ports/cortex_r5/ghs/src/tx_thread_schedule.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r5/ghs/src/tx_thread_stack_build.arm b/ports/cortex_r5/ghs/src/tx_thread_stack_build.arm index 373990dc..eaad8d16 100644 --- a/ports/cortex_r5/ghs/src/tx_thread_stack_build.arm +++ b/ports/cortex_r5/ghs/src/tx_thread_stack_build.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r5/ghs/src/tx_thread_system_return.arm b/ports/cortex_r5/ghs/src/tx_thread_system_return.arm index b9b3c0bd..488b9363 100644 --- a/ports/cortex_r5/ghs/src/tx_thread_system_return.arm +++ b/ports/cortex_r5/ghs/src/tx_thread_system_return.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r5/ghs/src/tx_thread_vectored_context_save.arm b/ports/cortex_r5/ghs/src/tx_thread_vectored_context_save.arm index 117ab499..11bca1b9 100644 --- a/ports/cortex_r5/ghs/src/tx_thread_vectored_context_save.arm +++ b/ports/cortex_r5/ghs/src/tx_thread_vectored_context_save.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r5/ghs/src/tx_timer_interrupt.arm b/ports/cortex_r5/ghs/src/tx_timer_interrupt.arm index c9125dca..5b3a4e3e 100644 --- a/ports/cortex_r5/ghs/src/tx_timer_interrupt.arm +++ b/ports/cortex_r5/ghs/src/tx_timer_interrupt.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r5/gnu/example_build/crt0.S b/ports/cortex_r5/gnu/example_build/crt0.S index aa0f3239..56b6c958 100644 --- a/ports/cortex_r5/gnu/example_build/crt0.S +++ b/ports/cortex_r5/gnu/example_build/crt0.S @@ -26,13 +26,13 @@ _mainCRTStartup: mov a2, #0 /* Second arg: fill value */ mov fp, a2 /* Null frame pointer */ mov r7, a2 /* Null frame pointer for Thumb */ - - ldr a1, .LC1 /* First arg: start of memory block */ - ldr a3, .LC2 - sub a3, a3, a1 /* Third arg: length of block */ - - + ldr a1, .LC1 /* First arg: start of memory block */ + ldr a3, .LC2 + sub a3, a3, a1 /* Third arg: length of block */ + + + bl memset mov r0, #0 /* no arguments */ mov r1, #0 /* no argv either */ @@ -48,15 +48,15 @@ _mainCRTStartup: /* bl init */ mov r0, r4 mov r1, r5 -#endif +#endif bl main bl exit /* Should not return. */ - - /* For Thumb, constants must be after the code since only + + /* For Thumb, constants must be after the code since only positive offsets are supported for PC relative addresses. */ - + .align 0 .LC0: .LC1: diff --git a/ports/cortex_r5/gnu/example_build/reset.S b/ports/cortex_r5/gnu/example_build/reset.S index a11c826a..5d05258b 100644 --- a/ports/cortex_r5/gnu/example_build/reset.S +++ b/ports/cortex_r5/gnu/example_build/reset.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Initialize */ @/** */ @@ -65,11 +65,11 @@ SWI: .word __tx_swi_interrupt @ Software interrupt handler PREFETCH: .word __tx_prefetch_handler @ Prefetch exception handler -ABORT: +ABORT: .word __tx_abort_handler @ Abort exception handler -RESERVED: +RESERVED: .word __tx_reserved_handler @ Reserved exception handler -IRQ: +IRQ: .word __tx_irq_handler @ IRQ interrupt handler FIQ: .word __tx_fiq_handler @ FIQ interrupt handler diff --git a/ports/cortex_r5/gnu/example_build/sample_threadx.c b/ports/cortex_r5/gnu/example_build/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports/cortex_r5/gnu/example_build/sample_threadx.c +++ b/ports/cortex_r5/gnu/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_r5/gnu/example_build/sample_threadx.ld b/ports/cortex_r5/gnu/example_build/sample_threadx.ld index 3dea4e1c..e940b2b8 100644 --- a/ports/cortex_r5/gnu/example_build/sample_threadx.ld +++ b/ports/cortex_r5/gnu/example_build/sample_threadx.ld @@ -7,7 +7,7 @@ OUTPUT_ARCH(arm) SECTIONS { . = 0x00000000; - + .vectors : {reset.o(.text) } /* Read-only sections, merged into text segment: */ @@ -94,8 +94,8 @@ SECTIONS *(.gnu.linkonce.t*) *(.glue_7t) *(.glue_7) } =0 - .init : - { + .init : + { KEEP (*(.init)) } =0 _etext = .; @@ -120,7 +120,7 @@ SECTIONS .data1 : { *(.data1) } .eh_frame : { KEEP (*(.eh_frame)) } .gcc_except_table : { *(.gcc_except_table) } - .ctors : + .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is @@ -153,9 +153,9 @@ SECTIONS /* We want the small data sections together, so single-instruction offsets can access them all, and initialized data all before uninitialized, so we can shorten the on-disk segment size. */ - .sdata : + .sdata : { - *(.sdata) + *(.sdata) *(.sdata.*) *(.gnu.linkonce.s.*) } @@ -191,7 +191,7 @@ SECTIONS _stack_bottom = ABSOLUTE(.) ; - /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and + /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and SYS stack if nested interrupts are enabled. */ . = ALIGN(8) ; . += 4096 ; diff --git a/ports/cortex_r5/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_r5/gnu/example_build/tx_initialize_low_level.S index a3471277..b51eaeba 100644 --- a/ports/cortex_r5/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_r5/gnu/example_build/tx_initialize_low_level.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Initialize */ @/** */ @@ -62,7 +62,7 @@ SYS_STACK_SIZE = 1024 @ System stack size .type $_tx_initialize_low_level,function $_tx_initialize_low_level: BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_initialize_low_level @ Call _tx_initialize_low_level function @@ -72,45 +72,39 @@ $_tx_initialize_low_level: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_initialize_low_level Cortex-R5/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level Cortex-R5/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is responsible for any low-level processor */ -@/* initialization, including setting up interrupt vectors, setting */ -@/* up a periodic timer interrupt source, saving the system stack */ -@/* pointer for use in ISR processing later, and finding the first */ -@/* available RAM memory address for tx_application_define. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_initialize_kernel_enter ThreadX entry function */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) @@ -125,7 +119,7 @@ _tx_initialize_low_level: @ LDR r1, =_sp @ Get pointer to stack area -#ifdef TX_ENABLE_IRQ_NESTING +#ifdef TX_ENABLE_IRQ_NESTING @ @ /* Setup the system mode stack for nested interrupt support */ @ @@ -156,7 +150,7 @@ _tx_initialize_low_level: MSR CPSR, r0 @ Enter SVC mode LDR r2, =_stack_bottom @ Pickup stack bottom CMP r3, r2 @ Compare the current stack end with the bottom -_stack_error_loop: +_stack_error_loop: BLT _stack_error_loop @ If the IRQ stack exceeds the stack bottom, just sit here! @ @ /* Save the system stack pointer. */ @@ -208,7 +202,7 @@ __tx_reserved_handler: B __tx_reserved_handler @ Reserved exception handler @ .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -216,17 +210,17 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. In +@ interrupt, and all C scratch registers are available for use. In @ addition, IRQ interrupts may be re-enabled - with certain restrictions - @ if nested IRQ interrupts are desired. Interrupts may be re-enabled over -@ small code sequences where lr is saved before enabling interrupts and +@ small code sequences where lr is saved before enabling interrupts and @ restored after interrupts are again disabled. */ @ -@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start @ from IRQ mode with interrupts disabled. This routine switches to the -@ system mode and returns with IRQ interrupts enabled. -@ -@ NOTE: It is very important to ensure all IRQ interrupts are cleared +@ system mode and returns with IRQ interrupts enabled. +@ +@ NOTE: It is very important to ensure all IRQ interrupts are cleared @ prior to enabling nested IRQ interrupts. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -240,7 +234,7 @@ __tx_irq_processing_return: @ @ @ /* If interrupt nesting was started earlier, the end of interrupt nesting -@ service must be called before returning to _tx_thread_context_restore. +@ service must be called before returning to _tx_thread_context_restore. @ This routine returns in processing in IRQ mode with interrupts disabled. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -256,28 +250,28 @@ __tx_irq_processing_return: @__tx_example_vectored_irq_handler: @ @ -@ /* Save initial context and call context save to prepare for +@ /* Save initial context and call context save to prepare for @ vectored ISR execution. */ @ @ STMDB sp!, {r0-r3} @ Save some scratch registers @ MRS r0, SPSR @ Pickup saved SPSR -@ SUB lr, lr, #4 @ Adjust point of interrupt +@ SUB lr, lr, #4 @ Adjust point of interrupt @ STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers @ BL _tx_thread_vectored_context_save @ Vectored context save @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. In +@ interrupt, and all C scratch registers are available for use. In @ addition, IRQ interrupts may be re-enabled - with certain restrictions - @ if nested IRQ interrupts are desired. Interrupts may be re-enabled over -@ small code sequences where lr is saved before enabling interrupts and +@ small code sequences where lr is saved before enabling interrupts and @ restored after interrupts are again disabled. */ @ @ -@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start @ from IRQ mode with interrupts disabled. This routine switches to the -@ system mode and returns with IRQ interrupts enabled. -@ -@ NOTE: It is very important to ensure all IRQ interrupts are cleared +@ system mode and returns with IRQ interrupts enabled. +@ +@ NOTE: It is very important to ensure all IRQ interrupts are cleared @ prior to enabling nested IRQ interrupts. */ @#ifdef TX_ENABLE_IRQ_NESTING @ BL _tx_thread_irq_nesting_start @@ -286,7 +280,7 @@ __tx_irq_processing_return: @ /* Application IRQ handlers can be called here! */ @ @ /* If interrupt nesting was started earlier, the end of interrupt nesting -@ service must be called before returning to _tx_thread_context_restore. +@ service must be called before returning to _tx_thread_context_restore. @ This routine returns in processing in IRQ mode with interrupts disabled. */ @#ifdef TX_ENABLE_IRQ_NESTING @ BL _tx_thread_irq_nesting_end @@ -308,11 +302,11 @@ __tx_fiq_processing_return: @ /* At this point execution is still in the FIQ mode. The CPSR, point of @ interrupt, and all C scratch registers are available for use. */ @ -@ /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +@ /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start @ from FIQ mode with interrupts disabled. This routine switches to the -@ system mode and returns with FIQ interrupts enabled. +@ system mode and returns with FIQ interrupts enabled. @ -@ NOTE: It is very important to ensure all FIQ interrupts are cleared +@ NOTE: It is very important to ensure all FIQ interrupts are cleared @ prior to enabling nested FIQ interrupts. */ #ifdef TX_ENABLE_FIQ_NESTING BL _tx_thread_fiq_nesting_start diff --git a/ports/cortex_r5/gnu/inc/tx_port.h b/ports/cortex_r5/gnu/inc/tx_port.h index 9b645b69..0a09f9ea 100644 --- a/ports/cortex_r5/gnu/inc/tx_port.h +++ b/ports/cortex_r5/gnu/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Cortex-R5/GNU */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-R5/GNU */ /* 6.1.12 */ /* */ /* AUTHOR */ @@ -32,27 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 07-29-2022 Scott Larson Updated comments, removed */ -/* unneeded temp variable, */ -/* resulting in version 6.1.12 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -65,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -78,7 +67,7 @@ #include -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -114,12 +103,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -129,8 +118,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -177,7 +166,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -189,13 +178,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -209,11 +198,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -221,8 +210,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -249,24 +238,24 @@ typedef unsigned short USHORT; #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ - + #if __TARGET_ARCH_ARM > 4 #ifndef __thumb__ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ asm volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); \ - b = 31 - b; + b = 31 - b; #endif #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -310,8 +299,8 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-R5/GNU Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R5/GNU Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r5/gnu/readme_threadx.txt b/ports/cortex_r5/gnu/readme_threadx.txt index a9a28305..bc806c75 100644 --- a/ports/cortex_r5/gnu/readme_threadx.txt +++ b/ports/cortex_r5/gnu/readme_threadx.txt @@ -1,55 +1,55 @@ - Microsoft's Azure RTOS ThreadX for Cortex-R5 + Microsoft's Azure RTOS ThreadX for Cortex-R5 Using the GNU Tools 1. Building the ThreadX run-time Library -First make sure you are in the "example_build" directory. Also, make sure that -you have setup your path and other environment variables necessary for the GNU -development environment. +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the GNU +development environment. -At this point you may run the build_threadx.bat batch file. This will build the -ThreadX run-time environment in the "example_build" directory. +At this point you may run the build_threadx.bat batch file. This will build the +ThreadX run-time environment in the "example_build" directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. 2. Demonstration System -Building the demonstration is easy; simply execute the build_threadx_sample.bat -batch file while inside the "example_build" directory. +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with TX.A. The resulting file DEMO is a binary file +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with TX.A. The resulting file DEMO is a binary file that can be downloaded and executed. 3. System Initialization -The entry point in ThreadX for the Cortex-R5 using GNU tools is at label _start. +The entry point in ThreadX for the Cortex-R5 using GNU tools is at label _start. This is defined within the modified version of the GNU startup code - crt0.S. -The ThreadX tx_initialize_low_level.S file is responsible for setting up various -system data structures, the interrupt vectors, and a periodic timer interrupt source. -By default, the vector area is defined to be located at the "__vectors" label, -which is defined in reset.S. This area is typically located at 0. In situations -where this is impossible, the vectors at the "__vectors" label should be copied +The ThreadX tx_initialize_low_level.S file is responsible for setting up various +system data structures, the interrupt vectors, and a periodic timer interrupt source. +By default, the vector area is defined to be located at the "__vectors" label, +which is defined in reset.S. This area is typically located at 0. In situations +where this is impossible, the vectors at the "__vectors" label should be copied to address 0. -This is also where initialization of a periodic timer interrupt source should take +This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level defines the first available address -for use by the application, which is supplied as the sole input parameter +In addition, _tx_initialize_low_level defines the first available address +for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 4. Assembler / Compiler Switches -The following are compiler switches used in building the demonstration +The following are compiler switches used in building the demonstration system: Compiler/Assembler Meaning @@ -73,164 +73,164 @@ Application Defines ( -D option) ThreadX assembly files. If used, it should be used on all assembly files and the generic C source of - ThreadX should be compiled with + ThreadX should be compiled with TX_ENABLE_FIQ_SUPPORT defined as well. TX_ENABLE_IRQ_NESTING This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.S. TX_ENABLE_FIQ_NESTING This assembler define enables FIQ - nested support. If FIQ nested + nested support. If FIQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.S. In addition, IRQ nesting should also be enabled. TX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ interrupt handling in the ThreadX - generic C source. This define + generic C source. This define should also be used in conjunction with the corresponding assembler - define. + define. TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - TX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. 5. Register Usage and Stack Frames -The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -248,52 +248,52 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-R5 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-R5 vectors start at address zero. The demonstration system startup -reset.S file contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +reset.S file contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs -ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -301,7 +301,7 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -314,7 +314,7 @@ __tx_irq_processing_return: 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.S: .global __tx_irq_example_handler @@ -324,12 +324,12 @@ __tx_irq_example_handler: STMDB sp!, {r0-r3} @ Save some scratch registers MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers BL _tx_thread_vectored_context_save @ Call the vectored IRQ context save @ @ /* At this point execution is still in the IRQ mode. The CPSR, point of -@ interrupt, and all C scratch registers are available for use. Note +@ interrupt, and all C scratch registers are available for use. Note @ that IRQ interrupts are still disabled upon return from the context @ save function. */ @ @@ -346,22 +346,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.S. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables -nesting by disabling IRQ interrupts and switching back to IRQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: .global __tx_irq_handler - .global __tx_irq_processing_return + .global __tx_irq_processing_return __tx_irq_handler: @ @ /* Jump to context save to save system context. */ @@ -369,10 +369,10 @@ __tx_irq_handler: __tx_irq_processing_return: @ @ /* Enable nested IRQ interrupts. NOTE: Since this service returns -@ with IRQ interrupts enabled, all IRQ interrupt sources must be +@ with IRQ interrupts enabled, all IRQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start -@ +@ @ /* Application ISR call(s) go here! */ @ @ /* Disable nested IRQ interrupts. The mode is switched back to @@ -385,12 +385,12 @@ __tx_irq_processing_return: 7.3 FIQ Interrupts -By default, FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.S. @@ -399,7 +399,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.S. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.S: @@ -427,18 +427,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.S. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -454,7 +454,7 @@ __tx_fiq_processing_return: @ interrupt, and all C scratch registers are available for use. */ @ @ /* Enable nested FIQ interrupts. NOTE: Since this service returns -@ with FIQ interrupts enabled, all FIQ interrupt sources must be +@ with FIQ interrupts enabled, all FIQ interrupt sources must be @ cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start @ @@ -470,12 +470,12 @@ __tx_fiq_processing_return: 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer -interrupt source, these services are not functional but the remainder of +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of ThreadX will still run. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.S for the demonstration system. diff --git a/ports/cortex_r5/gnu/src/tx_thread_context_restore.S b/ports/cortex_r5/gnu/src/tx_thread_context_restore.S index 4f3721cb..c8c28acb 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_r5/gnu/src/tx_thread_context_restore.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -43,48 +43,42 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @ @/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore @ since it will never be called 16-bit mode. */ -@ +@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_context_restore Cortex-R5/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore Cortex-R5/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function restores the interrupt context if it is processing a */ -@/* nested interrupt. If not, it returns to the interrupt thread if no */ -@/* preemption is necessary. Otherwise, if preemption is necessary or */ -@/* if no thread was running, the function returns to the scheduler. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling routine */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs Interrupt Service Routines */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) @@ -115,13 +109,13 @@ _tx_thread_context_restore: LDR r3, =_tx_thread_system_state @ Pickup address of system state variable LDR r2, [r3] @ Pickup system state SUB r2, r2, #1 @ Decrement the counter - STR r2, [r3] @ Store the counter + STR r2, [r3] @ Store the counter CMP r2, #0 @ Was this the first interrupt? BEQ __tx_thread_not_nested_restore @ If so, not a nested restore @ @ /* Interrupts are nested. */ @ -@ /* Just recover the saved registers and return to the point of +@ /* Just recover the saved registers and return to the point of @ interrupt. */ @ LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs diff --git a/ports/cortex_r5/gnu/src/tx_thread_context_save.S b/ports/cortex_r5/gnu/src/tx_thread_context_save.S index 8806203d..12434186 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_r5/gnu/src/tx_thread_context_save.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -30,47 +30,41 @@ @ @/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save @ since it will never be called 16-bit mode. */ -@ +@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_context_save Cortex-R5/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save Cortex-R5/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function saves the context of an executing thread in the */ -@/* beginning of interrupt processing. The function also ensures that */ -@/* the system stack is used upon return to the calling ISR. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) @@ -86,7 +80,7 @@ _tx_thread_context_save: @ if (_tx_thread_system_state++) @ { @ - STMDB sp!, {r0-r3} @ Save some working registers + STMDB sp!, {r0-r3} @ Save some working registers #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if @ Disable FIQ interrupts #endif @@ -104,7 +98,7 @@ _tx_thread_context_save: @ calling ISR. */ @ MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other registers @ @ /* Return to the ISR. */ @@ -120,7 +114,7 @@ _tx_thread_context_save: POP {lr} @ Recover ISR lr #endif - B __tx_irq_processing_return @ Continue IRQ processing + B __tx_irq_processing_return @ Continue IRQ processing @ __tx_thread_not_nested_save: @ } @@ -134,13 +128,13 @@ __tx_thread_not_nested_save: LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr LDR r0, [r1] @ Pickup current thread pointer CMP r0, #0 @ Is it NULL? - BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in @ scheduling loop - nothing needs saving! @ @ /* Save minimal context of interrupted thread. */ @ MRS r2, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} @ Store other registers @ @ /* Save the current stack pointer in the thread's control block. */ @@ -160,7 +154,7 @@ __tx_thread_not_nested_save: POP {lr} @ Recover ISR lr #endif - B __tx_irq_processing_return @ Continue IRQ processing + B __tx_irq_processing_return @ Continue IRQ processing @ @ } @ else @@ -170,7 +164,7 @@ __tx_thread_idle_system_save: @ @ /* Interrupt occurred in the scheduling loop. */ @ -@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ @ processing. */ @ MOV r10, #0 @ Clear stack limit @@ -185,7 +179,7 @@ __tx_thread_idle_system_save: #endif ADD sp, sp, #16 @ Recover saved registers - B __tx_irq_processing_return @ Continue IRQ processing + B __tx_irq_processing_return @ Continue IRQ processing @ @ } @} diff --git a/ports/cortex_r5/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_r5/gnu/src/tx_thread_fiq_context_restore.S index 5d1c2cc8..5ebe4ac4 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_r5/gnu/src/tx_thread_fiq_context_restore.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -24,7 +24,7 @@ SVC_MODE = 0xD3 @ SVC mode FIQ_MODE = 0xD1 @ FIQ mode -MODE_MASK = 0x1F @ Mode mask +MODE_MASK = 0x1F @ Mode mask THUMB_MASK = 0x20 @ Thumb bit mask IRQ_MODE_BITS = 0x12 @ IRQ mode bits @ @@ -45,44 +45,38 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_fiq_context_restore Cortex-R5/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_restore Cortex-R5/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function restores the fiq interrupt context when processing a */ -@/* nested interrupt. If not, it returns to the interrupt thread if no */ -@/* preemption is necessary. Otherwise, if preemption is necessary or */ -@/* if no thread was running, the function returns to the scheduler. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling routine */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* FIQ ISR Interrupt Service Routines */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function restores the fiq interrupt context when processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* FIQ ISR Interrupt Service Routines */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_context_restore(VOID) @@ -109,13 +103,13 @@ _tx_thread_fiq_context_restore: LDR r3, =_tx_thread_system_state @ Pickup address of system state variable LDR r2, [r3] @ Pickup system state SUB r2, r2, #1 @ Decrement the counter - STR r2, [r3] @ Store the counter + STR r2, [r3] @ Store the counter CMP r2, #0 @ Was this the first interrupt? BEQ __tx_thread_fiq_not_nested_restore @ If so, not a nested restore @ @ /* Interrupts are nested. */ @ -@ /* Just recover the saved registers and return to the point of +@ /* Just recover the saved registers and return to the point of @ interrupt. */ @ LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs @@ -203,7 +197,7 @@ __tx_thread_fiq_preempt_restore: BEQ __tx_thread_fiq_dont_save_ts @ No, don't save it @ @ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; -@ _tx_timer_time_slice = 0; +@ _tx_timer_time_slice = 0; @ STR r2, [r0, #24] @ Save thread's time-slice MOV r2, #0 @ Clear value diff --git a/ports/cortex_r5/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_r5/gnu/src/tx_thread_fiq_context_save.S index 6c94dc91..ccd30f3d 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_r5/gnu/src/tx_thread_fiq_context_save.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -34,43 +34,37 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_fiq_context_save Cortex-R5/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_save Cortex-R5/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function saves the context of an executing thread in the */ -@/* beginning of interrupt processing. The function also ensures that */ -@/* the system stack is used upon return to the calling ISR. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @ VOID _tx_thread_fiq_context_save(VOID) @@ -86,7 +80,7 @@ _tx_thread_fiq_context_save: @ if (_tx_thread_system_state++) @ { @ - STMDB sp!, {r0-r3} @ Save some working registers + STMDB sp!, {r0-r3} @ Save some working registers LDR r3, =_tx_thread_system_state @ Pickup address of system state variable LDR r2, [r3] @ Pickup system state CMP r2, #0 @ Is this the first interrupt? @@ -101,7 +95,7 @@ _tx_thread_fiq_context_save: @ calling ISR. */ @ MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other registers @ @ /* Return to the ISR. */ @@ -117,38 +111,38 @@ _tx_thread_fiq_context_save: POP {lr} @ Recover ISR lr #endif - B __tx_fiq_processing_return @ Continue FIQ processing + B __tx_fiq_processing_return @ Continue FIQ processing @ __tx_thread_fiq_not_nested_save: -@ } +@ } @ @ /* Otherwise, not nested, check to see if a thread was running. */ @ else if (_tx_thread_current_ptr) -@ { +@ { @ ADD r2, r2, #1 @ Increment the interrupt counter STR r2, [r3] @ Store it back in the variable LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr LDR r0, [r1] @ Pickup current thread pointer CMP r0, #0 @ Is it NULL? - BEQ __tx_thread_fiq_idle_system_save @ If so, interrupt occurred in -@ @ scheduling loop - nothing needs saving! + BEQ __tx_thread_fiq_idle_system_save @ If so, interrupt occurred in +@ @ scheduling loop - nothing needs saving! @ @ /* Save minimal context of interrupted thread. */ @ MRS r2, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r2, lr} @ Store other registers, Note that we don't -@ @ need to save sl and ip since FIQ has -@ @ copies of these registers. Nested +@ @ need to save sl and ip since FIQ has +@ @ copies of these registers. Nested @ @ interrupt processing does need to save @ @ these registers. @ @ /* Save the current stack pointer in the thread's control block. */ -@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; @ @ /* Switch to the system stack. */ -@ sp = _tx_thread_system_stack_ptr; +@ sp = _tx_thread_system_stack_ptr; @ MOV r10, #0 @ Clear stack limit @@ -161,7 +155,7 @@ __tx_thread_fiq_not_nested_save: POP {lr} @ Recover ISR lr #endif - B __tx_fiq_processing_return @ Continue FIQ processing + B __tx_fiq_processing_return @ Continue FIQ processing @ @ } @ else @@ -181,16 +175,16 @@ __tx_thread_fiq_idle_system_save: #endif @ @ /* Not much to do here, save the current SPSR and LR for possible -@ use in IRQ interrupted in idle system conditions, and return to +@ use in IRQ interrupted in idle system conditions, and return to @ FIQ interrupt processing. */ @ MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, lr} @ Store other registers that will get used -@ @ or stripped off the stack in context -@ @ restore - B __tx_fiq_processing_return @ Continue FIQ processing +@ @ or stripped off the stack in context +@ @ restore + B __tx_fiq_processing_return @ Continue FIQ processing @ @ } -@} +@} diff --git a/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_end.S index 752d6e63..4f9e04e3 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_end.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -27,7 +27,7 @@ DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts #else DISABLE_INTS = 0x80 @ Disable IRQ interrupts #endif -MODE_MASK = 0x1F @ Mode mask +MODE_MASK = 0x1F @ Mode mask FIQ_MODE_BITS = 0x11 @ FIQ mode bits @ @ @@ -37,51 +37,45 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_fiq_nesting_end Cortex-R5/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_end Cortex-R5/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from FIQ mode after */ -@/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ -@/* processing from system mode back to FIQ mode prior to the ISR */ -@/* calling _tx_thread_fiq_context_restore. Note that this function */ -@/* assumes the system stack pointer is in the same position after */ -@/* nesting start function was called. */ -@/* */ -@/* This function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with FIQ interrupts disabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +@/* processing from system mode back to FIQ mode prior to the ISR */ +@/* calling _tx_thread_fiq_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_end(VOID) @@ -93,7 +87,7 @@ _tx_thread_fiq_nesting_end: MRS r0, CPSR @ Pickup the CPSR ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value MSR CPSR_c, r0 @ Disable interrupts - LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for @ 8-byte alignment logic) BIC r0, r0, #MODE_MASK @ Clear mode bits ORR r0, r0, #FIQ_MODE_BITS @ Build IRQ mode CPSR diff --git a/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_start.S index f013cc3a..58eddaf4 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_start.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -33,48 +33,42 @@ SYS_MODE_BITS = 0x1F @ System mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_fiq_nesting_start Cortex-R5/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_start Cortex-R5/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from FIQ mode after */ -@/* _tx_thread_fiq_context_save has been called and switches the FIQ */ -@/* processing to the system mode so nested FIQ interrupt processing */ -@/* is possible (system mode has its own "lr" register). Note that */ -@/* this function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with FIQ interrupts enabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +@/* processing to the system mode so nested FIQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_r5/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_r5/gnu/src/tx_thread_interrupt_control.S index 7ef4c98d..babf7690 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_r5/gnu/src/tx_thread_interrupt_control.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -35,7 +35,7 @@ INT_MASK = 0x03F $_tx_thread_interrupt_control: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_interrupt_control @ Call _tx_thread_interrupt_control function @@ -45,42 +45,36 @@ $_tx_thread_interrupt_control: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_interrupt_control Cortex-R5/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control Cortex-R5/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is responsible for changing the interrupt lockout */ -@/* posture of the system. */ -@/* */ -@/* INPUT */ -@/* */ -@/* new_posture New interrupt lockout posture */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_r5/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_r5/gnu/src/tx_thread_interrupt_disable.S index 00b10b7d..98daf99e 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_r5/gnu/src/tx_thread_interrupt_disable.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -31,7 +31,7 @@ $_tx_thread_interrupt_disable: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_interrupt_disable @ Call _tx_thread_interrupt_disable function @@ -41,41 +41,35 @@ $_tx_thread_interrupt_disable: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_interrupt_disable Cortex-R5/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_disable Cortex-R5/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is responsible for disabling interrupts */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is responsible for disabling interrupts */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_disable(void) @@ -93,7 +87,7 @@ _tx_thread_interrupt_disable: #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if @ Disable IRQ and FIQ #else - CPSID i @ Disable IRQ + CPSID i @ Disable IRQ #endif #ifdef __THUMB_INTERWORK diff --git a/ports/cortex_r5/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_r5/gnu/src/tx_thread_interrupt_restore.S index 8e510f15..44134fa4 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_r5/gnu/src/tx_thread_interrupt_restore.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -31,7 +31,7 @@ $_tx_thread_interrupt_restore: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_interrupt_restore @ Call _tx_thread_interrupt_restore function @@ -41,42 +41,36 @@ $_tx_thread_interrupt_restore: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_interrupt_restore Cortex-R5/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_restore Cortex-R5/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ +@/* */ @/* This function is responsible for restoring interrupts to the state */ @/* returned by a previous _tx_thread_interrupt_disable call. */ -@/* */ -@/* INPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* INPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_end.S index 61edbd15..5099bf15 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_end.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -27,7 +27,7 @@ DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts #else DISABLE_INTS = 0x80 @ Disable IRQ interrupts #endif -MODE_MASK = 0x1F @ Mode mask +MODE_MASK = 0x1F @ Mode mask IRQ_MODE_BITS = 0x12 @ IRQ mode bits @ @ @@ -37,51 +37,45 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_irq_nesting_end Cortex-R5/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_end Cortex-R5/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from IRQ mode after */ -@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -@/* processing from system mode back to IRQ mode prior to the ISR */ -@/* calling _tx_thread_context_restore. Note that this function */ -@/* assumes the system stack pointer is in the same position after */ -@/* nesting start function was called. */ -@/* */ -@/* This function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with IRQ interrupts disabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +@/* processing from system mode back to IRQ mode prior to the ISR */ +@/* calling _tx_thread_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_end(VOID) @@ -93,7 +87,7 @@ _tx_thread_irq_nesting_end: MRS r0, CPSR @ Pickup the CPSR ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value MSR CPSR_c, r0 @ Disable interrupts - LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for @ 8-byte alignment logic) BIC r0, r0, #MODE_MASK @ Clear mode bits ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR diff --git a/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_start.S index b547290c..2fb5733f 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_start.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -33,48 +33,42 @@ SYS_MODE_BITS = 0x1F @ System mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_irq_nesting_start Cortex-R5/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_start Cortex-R5/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from IRQ mode after */ -@/* _tx_thread_context_save has been called and switches the IRQ */ -@/* processing to the system mode so nested IRQ interrupt processing */ -@/* is possible (system mode has its own "lr" register). Note that */ -@/* this function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with IRQ interrupts enabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_context_save has been called and switches the IRQ */ +@/* processing to the system mode so nested IRQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_r5/gnu/src/tx_thread_schedule.S b/ports/cortex_r5/gnu/src/tx_thread_schedule.S index 011af480..e19265f5 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_r5/gnu/src/tx_thread_schedule.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -38,7 +38,7 @@ $_tx_thread_schedule: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_schedule @ Call _tx_thread_schedule function @@ -48,45 +48,39 @@ $_tx_thread_schedule: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_schedule Cortex-R5/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_schedule Cortex-R5/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function waits for a thread control block pointer to appear in */ -@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -@/* in the variable, the corresponding thread is resumed. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_initialize_kernel_enter ThreadX entry function */ -@/* _tx_thread_system_return Return to system from thread */ -@/* _tx_thread_context_restore Restore thread's context */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function waits for a thread control block pointer to appear in */ +@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +@/* in the variable, the corresponding thread is resumed. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* _tx_thread_system_return Return to system from thread */ +@/* _tx_thread_context_restore Restore thread's context */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) @@ -116,7 +110,7 @@ __tx_thread_schedule_loop: @ @ } @ while(_tx_thread_execute_ptr == TX_NULL); -@ +@ @ /* Yes! We have a thread to execute. Lockout interrupts and @ transfer control to it. */ @ @@ -129,7 +123,7 @@ __tx_thread_schedule_loop: @ /* Setup the current thread pointer. */ @ _tx_thread_current_ptr = _tx_thread_execute_ptr; @ - LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread STR r0, [r1] @ Setup current thread pointer @ @ /* Increment the run count for this thread. */ @@ -143,7 +137,7 @@ __tx_thread_schedule_loop: @ /* Setup time-slice, if present. */ @ _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; @ - LDR r2, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r2, =_tx_timer_time_slice @ Pickup address of time-slice @ variable LDR sp, [r0, #8] @ Switch stack pointers STR r3, [r2] @ Setup time-slice diff --git a/ports/cortex_r5/gnu/src/tx_thread_stack_build.S b/ports/cortex_r5/gnu/src/tx_thread_stack_build.S index 0bcc63ed..f586573b 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_r5/gnu/src/tx_thread_stack_build.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -42,7 +42,7 @@ CPSR_MASK = 0x9F @ Mask initial CPSR, IRQ interru .type $_tx_thread_stack_build,function $_tx_thread_stack_build: BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_stack_build @ Call _tx_thread_stack_build function @@ -52,44 +52,38 @@ $_tx_thread_stack_build: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_stack_build Cortex-R5/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build Cortex-R5/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ +@/* */ @/* This function builds a stack frame on the supplied thread's stack. */ @/* The stack frame results in a fake interrupt return to the supplied */ -@/* function pointer. */ -@/* */ -@/* INPUT */ -@/* */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ @/* thread_ptr Pointer to thread control blk */ @/* function_ptr Pointer to return function */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_thread_create Create thread service */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -98,10 +92,10 @@ $_tx_thread_stack_build: .type _tx_thread_stack_build,function _tx_thread_stack_build: @ -@ +@ @ /* Build a fake interrupt frame. The form of the fake interrupt stack @ on the ARM9 should look like the following after it is built: -@ +@ @ Stack Top: 1 Interrupt stack frame type @ CPSR Initial value for CPSR @ a1 (r0) Initial value for a1 diff --git a/ports/cortex_r5/gnu/src/tx_thread_system_return.S b/ports/cortex_r5/gnu/src/tx_thread_system_return.S index 77cf89d5..0144b037 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_r5/gnu/src/tx_thread_system_return.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -42,7 +42,7 @@ $_tx_thread_system_return: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_system_return @ Call _tx_thread_system_return function @@ -52,44 +52,38 @@ $_tx_thread_system_return: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_system_return Cortex-R5/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return Cortex-R5/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is target processor specific. It is used to transfer */ -@/* control from a thread back to the ThreadX system. Only a */ -@/* minimal context is saved since the compiler assumes temp registers */ -@/* are going to get slicked by a function call anyway. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling loop */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX components */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ @/* */ @/**************************************************************************/ @VOID _tx_thread_system_return(VOID) @@ -124,7 +118,7 @@ _tx_skip_solicited_vfp_save: @ MOV r0, #0 @ Build a solicited stack type STMDB sp!, {r0-r1} @ Save type and CPSR -@ +@ @ #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY @ diff --git a/ports/cortex_r5/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_r5/gnu/src/tx_thread_vectored_context_save.S index 96e58d4f..e985f24f 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_r5/gnu/src/tx_thread_vectored_context_save.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -30,47 +30,41 @@ @ @/* No 16-bit Thumb mode veneer code is needed for _tx_thread_vectored_context_save @ since it will never be called 16-bit mode. */ -@ +@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_vectored_context_save Cortex-R5/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_vectored_context_save Cortex-R5/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function saves the context of an executing thread in the */ -@/* beginning of interrupt processing. The function also ensures that */ -@/* the system stack is used upon return to the calling ISR. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_vectored_context_save(VOID) @@ -128,7 +122,7 @@ __tx_thread_not_nested_save: LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr LDR r0, [r1, #0] @ Pickup current thread pointer CMP r0, #0 @ Is it NULL? - BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in @ scheduling loop - nothing needs saving! @ @ /* Note: Minimal context of interrupted thread is already saved. */ @@ -160,7 +154,7 @@ __tx_thread_idle_system_save: @ @ /* Interrupt occurred in the scheduling loop. */ @ -@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ @ processing. */ @ MOV r10, #0 @ Clear stack limit diff --git a/ports/cortex_r5/gnu/src/tx_timer_interrupt.S b/ports/cortex_r5/gnu/src/tx_timer_interrupt.S index b5d2553a..87715017 100644 --- a/ports/cortex_r5/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_r5/gnu/src/tx_timer_interrupt.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Timer */ @/** */ @@ -48,7 +48,7 @@ .type $_tx_timer_interrupt,function $_tx_timer_interrupt: BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_timer_interrupt @ Call _tx_timer_interrupt function @@ -58,46 +58,40 @@ $_tx_timer_interrupt: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_timer_interrupt Cortex-R5/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt Cortex-R5/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function processes the hardware timer interrupt. This */ -@/* processing includes incrementing the system clock and checking for */ -@/* time slice and/or timer expiration. If either is found, the */ -@/* interrupt context save/restore functions are called along with the */ -@/* expiration functions. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_time_slice Time slice interrupted thread */ -@/* _tx_timer_expiration_process Timer expiration processing */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* interrupt vector */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) @@ -122,7 +116,7 @@ _tx_timer_interrupt: @ if (_tx_timer_time_slice) @ { @ - LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice LDR r2, [r3] @ Pickup time-slice CMP r2, #0 @ Is it non-active? BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing @@ -240,7 +234,7 @@ __tx_timer_dont_activate: @ if (_tx_timer_expired_time_slice) @ { @ - LDR r3, =_tx_timer_expired_time_slice @ Pickup address of time-slice expired + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of time-slice expired LDR r2, [r3] @ Pickup the actual flag CMP r2, #0 @ See if the flag is set BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing diff --git a/ports/cortex_r5/iar/example_build/sample_threadx.c b/ports/cortex_r5/iar/example_build/sample_threadx.c index 983109cc..ca92ff86 100644 --- a/ports/cortex_r5/iar/example_build/sample_threadx.c +++ b/ports/cortex_r5/iar/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -63,7 +63,7 @@ void thread_6_and_7_entry(ULONG thread_input); int main() { - + /* Enter the ThreadX kernel. */ tx_kernel_enter(); } @@ -87,42 +87,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -130,23 +130,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -249,11 +249,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -312,7 +312,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -365,7 +365,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/cortex_r5/iar/example_build/tx_initialize_low_level.s b/ports/cortex_r5/iar/example_build/tx_initialize_low_level.s index 745a9d19..680aeb6d 100644 --- a/ports/cortex_r5/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_r5/iar/example_build/tx_initialize_low_level.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Initialize */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -52,7 +52,7 @@ SVC_MODE DEFINE 0x13 ; SVC mode ; ; ; -;/* Define the FREE_MEM segment that will specify where free memory is +;/* Define the FREE_MEM segment that will specify where free memory is ; defined. This must also be located in at the end of other RAM segments ; in the linker control file. The value of this segment is what is passed ; to tx_application_define. */ @@ -65,45 +65,39 @@ __tx_free_memory_start ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-R5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-R5/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -135,7 +129,7 @@ _tx_initialize_low_level ; LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address STR r0, [r2, #0] ; Save first free memory address -; +; ; /* Setup Timer for periodic interrupts. */ ; ; /* Done, return to caller. */ @@ -183,17 +177,17 @@ IRQ_Handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -208,7 +202,7 @@ __tx_irq_processing_return ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -227,22 +221,22 @@ __tx_irq_processing_return ; /* Jump to context save to save system context. */ ; STMDB sp!, {r0-r3} ; Save some scratch registers ; MRS r0, SPSR ; Pickup saved SPSR -; SUB lr, lr, #4 ; Adjust point of interrupt +; SUB lr, lr, #4 ; Adjust point of interrupt ; STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; BL _tx_thread_vectored_context_save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ;#ifdef TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_start @@ -251,7 +245,7 @@ __tx_irq_processing_return ; /* Application IRQ handler is called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ;#ifdef TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_end diff --git a/ports/cortex_r5/iar/inc/tx_port.h b/ports/cortex_r5/iar/inc/tx_port.h index 45e196fd..eb5e46d9 100644 --- a/ports/cortex_r5/iar/inc/tx_port.h +++ b/ports/cortex_r5/iar/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Cortex-R5/IAR */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-R5/IAR */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -79,7 +71,7 @@ #endif -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -115,19 +107,19 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -172,7 +164,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -186,18 +178,18 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ - VOID *tx_thread_iar_tls_pointer; + VOID *tx_thread_iar_tls_pointer; #else #define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; #endif -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -211,11 +203,11 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -225,23 +217,23 @@ ULONG _tx_misra_time_stamp_get(VOID); #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #if (__VER__ < 8000000) -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #endif #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -269,8 +261,8 @@ void __iar_Initlocks(void); #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -281,22 +273,22 @@ void __iar_Initlocks(void); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (UINT) __CLZ(m); \ - b = 31 - b; + b = 31 - b; #endif #endif #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ /* First, check and see what mode the file is being compiled in. The IAR compiler - defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode + defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode is present. If ARM 32-bit mode is present, the fast CPSR manipulation macros are available. Otherwise, if Thumb mode is present, we must use function calls. */ @@ -365,8 +357,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-R5/IAR Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R5/IAR Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_r5/iar/readme_threadx.txt b/ports/cortex_r5/iar/readme_threadx.txt index fd6174a7..4d1b8b55 100644 --- a/ports/cortex_r5/iar/readme_threadx.txt +++ b/ports/cortex_r5/iar/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for Cortex-R5 + Microsoft's Azure RTOS ThreadX for Cortex-R5 Thumb & 32-bit Mode @@ -7,10 +7,10 @@ 1. Building the ThreadX run-time Library Building the ThreadX library is easy. First, open the Azure RTOS workspace -azure_rtos.eww. Next, make the TX project the "active project" in the -IAR Embedded Workbench and select the "Make" button. You should observe -assembly and compilation of a series of ThreadX source files. This -results in the ThreadX run-time library file tx.a, which is needed by +azure_rtos.eww. Next, make the TX project the "active project" in the +IAR Embedded Workbench and select the "Make" button. You should observe +assembly and compilation of a series of ThreadX source files. This +results in the ThreadX run-time library file tx.a, which is needed by the application. @@ -20,47 +20,47 @@ The ThreadX demonstration is designed to execute under the IAR Windows-based Cortex-R5 simulator. Building the demonstration is easy; simply make the sample_threadx.ewp project -the "active project" in the IAR Embedded Workbench and select the +the "active project" in the IAR Embedded Workbench and select the "Make" button. -You should observe the compilation of sample_threadx.c (which is the demonstration +You should observe the compilation of sample_threadx.c (which is the demonstration application) and linking with tx.a. The resulting file sample_threadx.out is a binary file that can be downloaded and executed on IAR's Cortex-R5 simulator. 3. System Initialization -The entry point in ThreadX for the Cortex-R5 using IAR tools is at label -?cstartup. This is defined within the IAR compiler's startup code. In -addition, this is where all static and global preset C variable +The entry point in ThreadX for the Cortex-R5 using IAR tools is at label +?cstartup. This is defined within the IAR compiler's startup code. In +addition, this is where all static and global preset C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, and a periodic timer interrupt source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. By default, the vector area is defined at the top of cstartup.s, which is -a slightly modified from the base IAR file. +a slightly modified from the base IAR file. The _tx_initialize_low_level function inside of tx_initialize_low_level.s -also determines the first available address for use by the application, which -is supplied as the sole input parameter to your application definition function, -tx_application_define. To accomplish this, a section is created in -tx_initialize_low_level.s called FREE_MEM, which must be located after all +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all other RAM sections in memory. 4. Register Usage and Stack Frames -The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are -scratch registers for each function. All other registers used by a C function -must be preserved by the function. ThreadX takes advantage of this in -situations where a context switch happens as a result of making a ThreadX -service call (which is itself a C function). In such cases, the saved +The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are +scratch registers for each function. All other registers used by a C function +must be preserved by the function. ThreadX takes advantage of this in +situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -78,12 +78,12 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 5. Conditional Compilation Switches @@ -92,159 +92,159 @@ The following are conditional compilation options for building the ThreadX libra and application: TX_ENABLE_IRQ_NESTING This assembler define enables IRQ - nested support. If IRQ nested + nested support. If IRQ nested interrupt support is needed, this - define should be applied to + define should be applied to tx_initialize_low_level.s. TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 2 in the "ThreadX User Guide" + Chapter 2 in the "ThreadX User Guide" for more details. - TX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace feature. The trace buffer is supplied at a later time via an application call to tx_trace_enable. - TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. - This define is only pertinent if the ThreadX library is + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. - TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace - time-stamp source defined previously. If the time-stamp - source is 16-bits, this value should be 0xFFFF. Alternatively, - if the time-stamp source is 32-bits, this value should be - 0xFFFFFFFF. This define is only pertinent if the ThreadX + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX library is built with TX_ENABLE_EVENT_TRACE defined. 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the ThreadX library -project to enable various compiler optimizations. +project to enable various compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-R5 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-R5 vectors start at address zero. The demonstration system startup -cstartup.s file contains the vectors and is loaded at address zero. -On actual hardware platforms, this area might have to be copied to address 0. +cstartup.s file contains the vectors and is loaded at address zero. +On actual hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs @@ -255,12 +255,12 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.s: PUBLIC __tx_irq_handler - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -268,7 +268,7 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -281,7 +281,7 @@ __tx_irq_processing_return 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.s: @@ -292,12 +292,12 @@ __tx_example_vectored_irq_handler ; /* Jump to context save to save system context. */ STMDB sp!, {r0-r3} ; Save some scratch registers MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers BL _tx_thread_vectored_context_save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -314,24 +314,24 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.s. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables -nesting by disabling IRQ interrupts and switching back to IRQ mode in +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: RSEG .text:CODE:NOROOT(2) PUBLIC __tx_irq_handler RSEG .text:CODE:NOROOT(2) - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -339,15 +339,15 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ; BL _tx_thread_irq_nesting_start @@ -355,7 +355,7 @@ __tx_irq_processing_return ; /* Application ISR dispatch call goes here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ; BL _tx_thread_irq_nesting_end @@ -366,12 +366,12 @@ __tx_irq_processing_return 7.3 FIQ Interrupts -By default, Cortex-R5 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of a thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, Cortex-R5 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of a thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.s. @@ -383,21 +383,21 @@ cannot be disabled. The hardware does not support nested FIQ interrupts. 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to _tx_timer_interrupt +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. 9. Thumb/Cortex-R5 Mixed Mode -By default, ThreadX is setup for running in Cortex-R5 32-bit mode. This is -also true for the demonstration system. It is possible to build any +By default, ThreadX is setup for running in Cortex-R5 32-bit mode. This is +also true for the demonstration system. It is possible to build any ThreadX file and/or the application in Thumb mode. The only exception -to this is the file tx_thread_shell_entry.c. This file must always be +to this is the file tx_thread_shell_entry.c. This file must always be built in 32-bit mode. diff --git a/ports/cortex_r5/iar/src/tx_iar.c b/ports/cortex_r5/iar/src/tx_iar.c index 158738ea..238b485e 100644 --- a/ports/cortex_r5/iar/src/tx_iar.c +++ b/ports/cortex_r5/iar/src/tx_iar.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** IAR Multithreaded Library Support */ /** */ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports/cortex_r5/iar/src/tx_thread_context_restore.s b/ports/cortex_r5/iar/src/tx_thread_context_restore.s index 62f098eb..a035dc5e 100644 --- a/ports/cortex_r5/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_r5/iar/src/tx_thread_context_restore.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -47,44 +47,38 @@ THUMB_MASK DEFINE 0x20 ; Thumb bit mask ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore Cortex-R5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-R5/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -112,13 +106,13 @@ _tx_thread_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3] ; Store the counter + STR r2, [r3] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -181,7 +175,7 @@ __tx_thread_preempt_restore LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer - + #ifdef __ARMVFP__ LDR r2, [r0, #144] ; Pickup the VFP enabled flag CMP r2, #0 ; Is the VFP enabled? @@ -191,7 +185,7 @@ __tx_thread_preempt_restore VSTMDB sp!, {D0-D15} ; Save D0-D15 _tx_skip_irq_vfp_save #endif - + MOV r3, #1 ; Build interrupt stack type STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR STR sp, [r0, #8] ; Save stack pointer in thread control @@ -237,7 +231,7 @@ __tx_thread_idle_system_restore ; /* Just return back to the scheduler! */ ; CPS #SVC_MODE ; Enter SVC mode - + B _tx_thread_schedule ; Return to scheduler ;} ; diff --git a/ports/cortex_r5/iar/src/tx_thread_context_save.s b/ports/cortex_r5/iar/src/tx_thread_context_save.s index ce3a27d7..acd05d0a 100644 --- a/ports/cortex_r5/iar/src/tx_thread_context_save.s +++ b/ports/cortex_r5/iar/src/tx_thread_context_save.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -36,43 +36,37 @@ EXTERN _tx_execution_isr_enter ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save Cortex-R5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-R5/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -89,7 +83,7 @@ _tx_thread_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3, #0] ; Pickup system state CMP r2, #0 ; Is this the first interrupt? @@ -104,7 +98,7 @@ _tx_thread_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -120,7 +114,7 @@ _tx_thread_context_save POP {lr} ; Recover ISR lr #endif - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; __tx_thread_not_nested_save ; } @@ -134,13 +128,13 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} ; Store other registers ; ; /* Save the current stack pointer in the thread's control block. */ @@ -160,7 +154,7 @@ __tx_thread_not_nested_save POP {lr} ; Recover ISR lr #endif - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ; else @@ -170,7 +164,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit @@ -185,7 +179,7 @@ __tx_thread_idle_system_save #endif ADD sp, sp, #16 ; Recover saved registers - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ;} diff --git a/ports/cortex_r5/iar/src/tx_thread_interrupt_control.s b/ports/cortex_r5/iar/src/tx_thread_interrupt_control.s index 6a7768c9..423ba167 100644 --- a/ports/cortex_r5/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_r5/iar/src/tx_thread_interrupt_control.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ;#define TX_SOURCE_CODE ; @@ -32,42 +32,36 @@ INT_MASK DEFINE 0x80 ; Interrupt bit mask ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control Cortex-R5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-R5/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) @@ -87,7 +81,7 @@ _tx_thread_interrupt_control ; MSR CPSR_cxsf, r1 ; Setup new CPSR AND r0, r3, #INT_MASK ; Return previous interrupt mask - + BX lr ; Return to caller ; ;} diff --git a/ports/cortex_r5/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_r5/iar/src/tx_thread_interrupt_disable.s index 687a56e6..c7520107 100644 --- a/ports/cortex_r5/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_r5/iar/src/tx_thread_interrupt_disable.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ;#define TX_SOURCE_CODE ; @@ -32,41 +32,35 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable Cortex-R5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-R5/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_r5/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_r5/iar/src/tx_thread_interrupt_restore.s index 3a60ca6d..def631f2 100644 --- a/ports/cortex_r5/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_r5/iar/src/tx_thread_interrupt_restore.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ;#define TX_SOURCE_CODE ; @@ -28,42 +28,36 @@ ;#include "tx_thread.h" ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore Cortex-R5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-R5/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for restoring interrupts to the state */ -;/* returned by a previous _tx_thread_interrupt_disable call. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for restoring interrupts to the state */ +;/* returned by a previous _tx_thread_interrupt_disable call. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;void _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_r5/iar/src/tx_thread_irq_nesting_end.s b/ports/cortex_r5/iar/src/tx_thread_irq_nesting_end.s index f2153ae6..b6a9908f 100644 --- a/ports/cortex_r5/iar/src/tx_thread_irq_nesting_end.s +++ b/ports/cortex_r5/iar/src/tx_thread_irq_nesting_end.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -33,51 +33,45 @@ IRQ_MODE DEFINE 0x12 ; IRQ mode ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_end Cortex-R5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-R5/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -;/* processing from system mode back to IRQ mode prior to the ISR */ -;/* calling _tx_thread_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_r5/iar/src/tx_thread_irq_nesting_start.s b/ports/cortex_r5/iar/src/tx_thread_irq_nesting_start.s index e81f900a..29137f8a 100644 --- a/ports/cortex_r5/iar/src/tx_thread_irq_nesting_start.s +++ b/ports/cortex_r5/iar/src/tx_thread_irq_nesting_start.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -33,48 +33,42 @@ SYS_MODE DEFINE 0x1F ; System mode ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_start Cortex-R5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-R5/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_context_save has been called and switches the IRQ */ -;/* processing to the system mode so nested IRQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_r5/iar/src/tx_thread_schedule.s b/ports/cortex_r5/iar/src/tx_thread_schedule.s index fc88ce8f..4152a2cb 100644 --- a/ports/cortex_r5/iar/src/tx_thread_schedule.s +++ b/ports/cortex_r5/iar/src/tx_thread_schedule.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -37,45 +37,39 @@ ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule Cortex-R5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-R5/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -104,7 +98,7 @@ __tx_thread_schedule_loop ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Lockout interrupts and ; transfer control to it. */ ; @@ -113,7 +107,7 @@ __tx_thread_schedule_loop ; /* Setup the current thread pointer. */ ; _tx_thread_current_ptr = _tx_thread_execute_ptr; ; - LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread STR r0, [r1, #0] ; Setup current thread pointer ; ; /* Increment the run count for this thread. */ @@ -127,7 +121,7 @@ __tx_thread_schedule_loop ; /* Setup time-slice, if present. */ ; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; ; - LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice ; variable LDR sp, [r0, #8] ; Switch stack pointers STR r3, [r2, #0] ; Setup time-slice @@ -184,7 +178,7 @@ _tx_skip_solicited_vfp_restore: #ifdef __ARMVFP__ PUBLIC tx_thread_vfp_enable CODE32 -tx_thread_vfp_enable??rA +tx_thread_vfp_enable??rA tx_thread_vfp_enable MRS r2, CPSR ; Pickup the CPSR CPSID i ; Disable IRQ interrupts @@ -200,7 +194,7 @@ __tx_no_thread_to_enable: PUBLIC tx_thread_vfp_disable CODE32 -tx_thread_vfp_disable??rA +tx_thread_vfp_disable??rA tx_thread_vfp_disable MRS r2, CPSR ; Pickup the CPSR CPSID i ; Disable IRQ interrupts diff --git a/ports/cortex_r5/iar/src/tx_thread_stack_build.s b/ports/cortex_r5/iar/src/tx_thread_stack_build.s index 3b9dbc49..264ee4c3 100644 --- a/ports/cortex_r5/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_r5/iar/src/tx_thread_stack_build.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -33,58 +33,52 @@ SVC_MODE DEFINE 0x13 ; SVC mode CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints enabled ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build Cortex-R5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-R5/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function builds a stack frame on the supplied thread's stack. */ -;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Pointer to thread control blk */ -;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) ;{ RSEG .text:CODE:NOROOT(2) PUBLIC _tx_thread_stack_build - + ARM _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-R5 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; a1 (r0) Initial value for a1 diff --git a/ports/cortex_r5/iar/src/tx_thread_system_return.s b/ports/cortex_r5/iar/src/tx_thread_system_return.s index 58e5d072..6ceabc46 100644 --- a/ports/cortex_r5/iar/src/tx_thread_system_return.s +++ b/ports/cortex_r5/iar/src/tx_thread_system_return.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ;#define TX_SOURCE_CODE ; @@ -37,44 +37,38 @@ ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return Cortex-R5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-R5/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -107,7 +101,7 @@ _tx_skip_solicited_vfp_save: MOV r0, #0 ; Build a solicited stack type STMDB sp!, {r0-r1} ; Save type and CPSR -; +; ; #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; diff --git a/ports/cortex_r5/iar/src/tx_thread_vectored_context_save.s b/ports/cortex_r5/iar/src/tx_thread_vectored_context_save.s index 4029bbb4..3a5ed54a 100644 --- a/ports/cortex_r5/iar/src/tx_thread_vectored_context_save.s +++ b/ports/cortex_r5/iar/src/tx_thread_vectored_context_save.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -35,43 +35,37 @@ EXTERN _tx_execution_isr_enter ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_vectored_context_save Cortex-R5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-R5/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) @@ -128,7 +122,7 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in ; scheduling loop - nothing needs saving! ; ; /* Note: Minimal context of interrupted thread is already saved. */ @@ -160,7 +154,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports/cortex_r5/iar/src/tx_timer_interrupt.s b/ports/cortex_r5/iar/src/tx_timer_interrupt.s index 85274fa2..b3935abc 100644 --- a/ports/cortex_r5/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_r5/iar/src/tx_timer_interrupt.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Timer */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ;#define TX_SOURCE_CODE ; @@ -43,46 +43,40 @@ ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt Cortex-R5/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-R5/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time-slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time-slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -108,7 +102,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CMP r2, #0 ; Is it non-active? BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing @@ -226,13 +220,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CMP r2, #0 ; See if the flag is set BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing ; diff --git a/ports/cortex_r7/ghs/example_build/tx_initialize_low_level.arm b/ports/cortex_r7/ghs/example_build/tx_initialize_low_level.arm index a8cbf83a..c3b9f420 100644 --- a/ports/cortex_r7/ghs/example_build/tx_initialize_low_level.arm +++ b/ports/cortex_r7/ghs/example_build/tx_initialize_low_level.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r7/ghs/inc/tx_el.h b/ports/cortex_r7/ghs/inc/tx_el.h index b8926921..72e5bbe3 100644 --- a/ports/cortex_r7/ghs/inc/tx_el.h +++ b/ports/cortex_r7/ghs/inc/tx_el.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,12 +37,6 @@ /* EventAnalyzer. It is assumed that tx_api.h and tx_port.h have */ /* already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_EL_H diff --git a/ports/cortex_r7/ghs/inc/tx_port.h b/ports/cortex_r7/ghs/inc/tx_port.h index c72beba6..11e05937 100644 --- a/ports/cortex_r7/ghs/inc/tx_port.h +++ b/ports/cortex_r7/ghs/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -394,7 +386,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-R7/Green Hills Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R7/Green Hills Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r7/ghs/readme_threadx.txt b/ports/cortex_r7/ghs/readme_threadx.txt index 6f498f11..427d29f3 100644 --- a/ports/cortex_r7/ghs/readme_threadx.txt +++ b/ports/cortex_r7/ghs/readme_threadx.txt @@ -1,19 +1,19 @@ - Microsoft's Azure RTOS ThreadX for Cortex-R7 + Microsoft's Azure RTOS ThreadX for Cortex-R7 Using the Green Hills Software Tools 1. Open the ThreadX Project Workspace -In order to build the ThreadX library and the ThreadX demonstration first load -the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the -"example_build" directory. +In order to build the ThreadX library and the ThreadX demonstration first load +the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the +"example_build" directory. 2. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply select the MULTI project file -tx.gpj and then select the build button. You should now observe the -compilation and assembly of the ThreadX library. This project build produces +Building the ThreadX library is easy; simply select the MULTI project file +tx.gpj and then select the build button. You should now observe the +compilation and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. @@ -21,55 +21,55 @@ the ThreadX library file tx.a. The ThreadX demonstration is designed to execute under the MULTI environment on the Green Hills Cortex-R7 simulator. The instructions that follow describe -how to get the ThreadX evaluation running under the MULTI Cortex-R7 simulation +how to get the ThreadX evaluation running under the MULTI Cortex-R7 simulation environment. -Building the demonstration is easy; simply select the MULTI project file -sample_threadx.gpj. At this point, select the "Project Build" button and observe -the compilation, assembly, and linkage of the ThreadX demonstration application. +Building the demonstration is easy; simply select the MULTI project file +sample_threadx.gpj. At this point, select the "Project Build" button and observe +the compilation, assembly, and linkage of the ThreadX demonstration application. -After the demonstration is built, invoke the MULTI ARM simulator by selecting -the simulator connection from within the sample_threadx.con connection file. -Once connected to the simulator, select the "Debug" button. You should now -observe the main function of sample_threadx.c. +After the demonstration is built, invoke the MULTI ARM simulator by selecting +the simulator connection from within the sample_threadx.con connection file. +Once connected to the simulator, select the "Debug" button. You should now +observe the main function of sample_threadx.c. At this point, you should setup a simulated timer interrupt for ThreadX by entering "timer 9999 irq" in the "target" window of the debugger. -You are now ready to execute the ThreadX demonstration system. Select -breakpoints and data watches to observe the execution of the sample_threadx.c +You are now ready to execute the ThreadX demonstration system. Select +breakpoints and data watches to observe the execution of the sample_threadx.c application. 4. EventAnalyzer Demonstration -To build a demonstration system that also logs events for the MULTI EventAnalyzer, -perform the same steps as the regular demo, except build the ThreadX library with -txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. -The resulting image will log all system events, which can then be displayed by the +To build a demonstration system that also logs events for the MULTI EventAnalyzer, +perform the same steps as the regular demo, except build the ThreadX library with +txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. +The resulting image will log all system events, which can then be displayed by the MULTI EventAnalyzer. 5. System Initialization -The system entry point using the Green Hills tools is at the label _start. -This is defined within the crt0.arm file supplied by Green Hills. In addition, -this is where all static and global preset C variable initialization +The system entry point using the Green Hills tools is at the label _start. +This is defined within the crt0.arm file supplied by Green Hills. In addition, +this is where all static and global preset C variable initialization processing is called from. After the Green Hills startup function returns, ThreadX initialization is called. The main initialization function is _tx_initialize_low_level and -is located in the file tx_initialize_low_level.arm. This function is responsible -for setting up various system data structures, interrupt vectors, and the +is located in the file tx_initialize_low_level.arm. This function is responsible +for setting up various system data structures, interrupt vectors, and the periodic timer interrupt source of ThreadX. -In addition, _tx_initialize_low_level determines where the first available +In addition, _tx_initialize_low_level determines where the first available RAM memory address is located. This address is supplied to tx_application_define. -By default, the first available RAM memory address is assumed to start at the -beginning of the ThreadX section .free_mem. If changes are made to the -sample_threadx.ld file, the .free_mem section should remain the last allocated -section in the main RAM area. The starting address of this section is passed +By default, the first available RAM memory address is assumed to start at the +beginning of the ThreadX section .free_mem. If changes are made to the +sample_threadx.ld file, the .free_mem section should remain the last allocated +section in the main RAM area. The starting address of this section is passed to tx_application_define. @@ -87,27 +87,27 @@ The following defines and their associated action are as follows: TX_ENABLE_FIQ_NESTING If defined, this brings in special FIQ interrupt nesting logic into the ThreadX library. This define should be applied - to the entire ThreadX library and the + to the entire ThreadX library and the define TX_ENABLE_FIQ_SUPPORT should also be defined. TX_ENABLE_FIQ_SUPPORT If defined, this brings in FIQ context save and restore logic necessary for applications to call ThreadX services from - FIQ interrupt handlers. This define - should be applied to the entire ThreadX + FIQ interrupt handlers. This define + should be applied to the entire ThreadX library. TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, this define causes basic ThreadX error checking to be disabled. Please see - Chapter 4 in the "ThreadX User Guide" + Chapter 4 in the "ThreadX User Guide" for more details. TX_ENABLE_EVENT_LOGGING This define enables event logging for any or all of the ThreadX source code. If this - option is used anywhere, the tx_initialize_high_level.c + option is used anywhere, the tx_initialize_high_level.c file must be compiled with it as well, since this is where the event log is initialized. @@ -119,121 +119,121 @@ The following defines and their associated action are as follows: If this is enabled, run-time filtering logic is added to the event logging code. - TX_MAX_PRIORITIES Defines the priority levels for ThreadX. - Legal values range from 32 through - 1024 (inclusive) and MUST be evenly divisible - by 32. Increasing the number of priority levels - supported increases the RAM usage by 128 bytes - for every group of 32 priorities. However, there - is only a negligible effect on performance. By + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By default, this value is set to 32 priority levels. - TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is - used for error checking when threads are created. - The default value is port-specific and is found + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal - ThreadX timer thread. This thread processes all - thread sleep requests as well as all service call - timeouts. In addition, all application timer callback - routines are invoked from this context. The default + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default value is port-specific and is found in tx_port.h. - TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer - thread. The default value is priority 0 - the highest - priority in ThreadX. The default value is defined + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined in tx_port.h. - TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system - timer thread for ThreadX. This results in improved - performance on timer events and smaller RAM requirements - because the timer stack and control block are no - longer needed. However, using this option moves all - the timer expiration processing to the timer ISR level. + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. By default, this option is not defined. - TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX - timers in-line instead of using a function call. This - improves performance but slightly increases code size. + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. By default, this option is not defined. - TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each - thread's stack is disabled. By default, this option is + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is not defined. - TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, - which includes analysis of how much stack has been used and - examination of data pattern "fences" before and after the - stack area. If a stack error is detected, the registered - application stack error handler is called. This option does - result in slightly increased overhead and code size. Please - review the tx_thread_stack_error_notify API for more information. + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. By default, this option is not defined. - TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature - and slightly reduces code size and improves performance. Of course, - the preemption-threshold capabilities are no longer available. + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. By default, this option is not defined. - TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX - global C data structures to zero. This should only be used if - the compiler's initialization code sets all un-initialized - C global data to zero. Using this option slightly reduces - code size and improves performance during initialization. + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. By default, this option is not defined. - TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various - ThreadX objects. Using this option slightly reduces code size + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size and improves performance. - TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on block pools. By default, this option is + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is not defined. - TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on byte pools. By default, this option is + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is not defined. - TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on event flags groups. By default, this option + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option is not defined. - TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on mutexes. By default, this option is + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is not defined. - TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on queues. By default, this option is + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is not defined. - TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on semaphores. By default, this option is + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is not defined. - TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on threads. By default, this option is + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is not defined. - TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance - information on timers. By default, this option is + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is not defined. 7. Register Usage and Stack Frames -The Green Hills compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) -are scratch registers for each function. All other registers used by a C -function must be preserved by the function. ThreadX takes advantage of this -in situations where a context switch happens as a result of making a ThreadX -service call (which is itself a C function). In such cases, the saved +The Green Hills compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) +are scratch registers for each function. All other registers used by a C +function must be preserved by the function. ThreadX takes advantage of this +in situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -251,40 +251,40 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 8. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make ThreadX run faster, you can change the tx.gpj project -to disable debug information and enable the desired optimizations. +to disable debug information and enable the desired optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined before tx_api.h is included. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. 9. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-R7 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 9.1 Vector Area The Cortex-R7 vectors start at address zero. The demonstration system reset.arm -file contains the reset section (which contains all the ARM vectors) and is +file contains the reset section (which contains all the ARM vectors) and is typically loaded at address zero. On actual hardware platforms, this section -might have to be copied to address 0. +might have to be copied to address 0. 9.2 IRQ ISRs @@ -294,13 +294,13 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 9.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.arm: .globl __tx_irq_handler - .globl __tx_irq_processing_return + .globl __tx_irq_processing_return __tx_irq_handler: /* Jump to context save to save system context. */ @@ -308,7 +308,7 @@ __tx_irq_handler: __tx_irq_processing_return: /* At this point execution is still in the IRQ mode. The CPSR, point of - interrupt, and all C scratch registers are available for use. Note + interrupt, and all C scratch registers are available for use. Note that IRQ interrupts are still disabled upon return from the context save function. */ @@ -321,7 +321,7 @@ __tx_irq_processing_return: 9.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.arm: .globl __tx_irq_example_handler @@ -331,12 +331,12 @@ __tx_irq_example_handler: STMDB sp!, {r0-r3} # Save some scratch registers MRS r0, SPSR # Pickup saved SPSR - SUB lr, lr, #4 # Adjust point of interrupt + SUB lr, lr, #4 # Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} # Store other scratch registers BL _tx_thread_vectored_context_save # Call the vectored IRQ context save /* At this point execution is still in the IRQ mode. The CPSR, point of - interrupt, and all C scratch registers are available for use. Note + interrupt, and all C scratch registers are available for use. Note that IRQ interrupts are still disabled upon return from the context save function. */ @@ -353,22 +353,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.arm. When nested IRQ interrupts are no -longer required, calling the _tx_thread_irq_nesting_end service disables nesting -by disabling IRQ interrupts and switching back to IRQ mode in preparation for +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.arm. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables nesting +by disabling IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in the +The following is an example of enabling IRQ nested interrupts in the typical IRQ handler: .globl __tx_irq_handler - .globl __tx_irq_processing_return + .globl __tx_irq_processing_return __tx_irq_handler: /* Jump to context save to save system context. */ @@ -376,10 +376,10 @@ __tx_irq_handler: __tx_irq_processing_return: /* Enable nested IRQ interrupts. NOTE: Since this service returns - with IRQ interrupts enabled, all IRQ interrupt sources must be + with IRQ interrupts enabled, all IRQ interrupt sources must be cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start - + /* Application ISR call(s) go here! */ /* Disable nested IRQ interrupts. The mode is switched back to @@ -392,9 +392,9 @@ __tx_irq_processing_return: 9.3 FIQ Interrupts -By default, Cortex-R7 FIQ interrupts are left completely enabled by ThreadX. -Of course, this means that the application is fully responsible for -saving/restoring any registers used in the FIQ ISR processing. In addition, +By default, Cortex-R7 FIQ interrupts are left completely enabled by ThreadX. +Of course, this means that the application is fully responsible for +saving/restoring any registers used in the FIQ ISR processing. In addition, no ThreadX service calls are allowed from the default FIQ ISRs. The default FIQ interrupt shell is located in tx_initialize_low_level.arm. @@ -403,7 +403,7 @@ FIQ interrupt shell is located in tx_initialize_low_level.arm. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.arm: @@ -431,18 +431,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was -setup in tx_initialize_low_level.arm. When nested FIQ interrupts are no longer -required, calling the _tx_thread_fiq_nesting_end service disables nesting by -disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.arm. When nested FIQ interrupts are no longer +required, calling the _tx_thread_fiq_nesting_end service disables nesting by +disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -458,7 +458,7 @@ __tx_fiq_processing_return: interrupt, and all C scratch registers are available for use. */ /* Enable nested FIQ interrupts. NOTE: Since this service returns - with FIQ interrupts enabled, all FIQ interrupt sources must be + with FIQ interrupts enabled, all FIQ interrupt sources must be cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start @@ -475,29 +475,29 @@ __tx_fiq_processing_return: 10. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.arm. 11. Thumb/Cortex-R7 Mixed Mode -By default, ThreadX is setup for running in Cortex-R7 32-bit mode. This is -also true for the demonstration system. It is possible to build any +By default, ThreadX is setup for running in Cortex-R7 32-bit mode. This is +also true for the demonstration system. It is possible to build any ThreadX file and/or the application in Thumb mode. The only exception -to this is the file tx_thread_shell_entry.c. This file must always be +to this is the file tx_thread_shell_entry.c. This file must always be built in 32-bit mode. 12. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); @@ -520,7 +520,7 @@ information associated with this specific port of ThreadX: 04-02-2021 Release 6.1.6 changes: tx_port.h Updated macro definition -05/19/2020 Initial ThreadX version of Cortex-R7/Green Hills port. +05/19/2020 Initial ThreadX version of Cortex-R7/Green Hills port. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_r7/ghs/src/tx_el.c b/ports/cortex_r7/ghs/src/tx_el.c index 365622cd..b5d3b8b7 100644 --- a/ports/cortex_r7/ghs/src/tx_el.c +++ b/ports/cortex_r7/ghs/src/tx_el.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,12 +83,6 @@ UINT _tx_thread_interrupt_control(UINT new_posture); /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_el_initialize(VOID) { diff --git a/ports/cortex_r7/ghs/src/tx_thread_context_restore.arm b/ports/cortex_r7/ghs/src/tx_thread_context_restore.arm index 84e9a4f9..9f829864 100644 --- a/ports/cortex_r7/ghs/src/tx_thread_context_restore.arm +++ b/ports/cortex_r7/ghs/src/tx_thread_context_restore.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r7/ghs/src/tx_thread_context_save.arm b/ports/cortex_r7/ghs/src/tx_thread_context_save.arm index c83232f5..656ade3c 100644 --- a/ports/cortex_r7/ghs/src/tx_thread_context_save.arm +++ b/ports/cortex_r7/ghs/src/tx_thread_context_save.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r7/ghs/src/tx_thread_fiq_context_restore.arm b/ports/cortex_r7/ghs/src/tx_thread_fiq_context_restore.arm index 0c37d12d..7d83f989 100644 --- a/ports/cortex_r7/ghs/src/tx_thread_fiq_context_restore.arm +++ b/ports/cortex_r7/ghs/src/tx_thread_fiq_context_restore.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r7/ghs/src/tx_thread_fiq_context_save.arm b/ports/cortex_r7/ghs/src/tx_thread_fiq_context_save.arm index 5ab8d701..82d2bdac 100644 --- a/ports/cortex_r7/ghs/src/tx_thread_fiq_context_save.arm +++ b/ports/cortex_r7/ghs/src/tx_thread_fiq_context_save.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r7/ghs/src/tx_thread_fiq_nesting_end.arm b/ports/cortex_r7/ghs/src/tx_thread_fiq_nesting_end.arm index 1577f5eb..30ac7c28 100644 --- a/ports/cortex_r7/ghs/src/tx_thread_fiq_nesting_end.arm +++ b/ports/cortex_r7/ghs/src/tx_thread_fiq_nesting_end.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r7/ghs/src/tx_thread_fiq_nesting_start.arm b/ports/cortex_r7/ghs/src/tx_thread_fiq_nesting_start.arm index 81cefcff..491366b8 100644 --- a/ports/cortex_r7/ghs/src/tx_thread_fiq_nesting_start.arm +++ b/ports/cortex_r7/ghs/src/tx_thread_fiq_nesting_start.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r7/ghs/src/tx_thread_interrupt_control.arm b/ports/cortex_r7/ghs/src/tx_thread_interrupt_control.arm index 1c84c17d..00297ae5 100644 --- a/ports/cortex_r7/ghs/src/tx_thread_interrupt_control.arm +++ b/ports/cortex_r7/ghs/src/tx_thread_interrupt_control.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r7/ghs/src/tx_thread_interrupt_disable.arm b/ports/cortex_r7/ghs/src/tx_thread_interrupt_disable.arm index 68ff706b..6e1745b9 100644 --- a/ports/cortex_r7/ghs/src/tx_thread_interrupt_disable.arm +++ b/ports/cortex_r7/ghs/src/tx_thread_interrupt_disable.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r7/ghs/src/tx_thread_interrupt_restore.arm b/ports/cortex_r7/ghs/src/tx_thread_interrupt_restore.arm index 2e3a4cd8..7b63b0cb 100644 --- a/ports/cortex_r7/ghs/src/tx_thread_interrupt_restore.arm +++ b/ports/cortex_r7/ghs/src/tx_thread_interrupt_restore.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r7/ghs/src/tx_thread_irq_nesting_end.arm b/ports/cortex_r7/ghs/src/tx_thread_irq_nesting_end.arm index f5e644d6..dc535b04 100644 --- a/ports/cortex_r7/ghs/src/tx_thread_irq_nesting_end.arm +++ b/ports/cortex_r7/ghs/src/tx_thread_irq_nesting_end.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r7/ghs/src/tx_thread_irq_nesting_start.arm b/ports/cortex_r7/ghs/src/tx_thread_irq_nesting_start.arm index 48776848..322b5211 100644 --- a/ports/cortex_r7/ghs/src/tx_thread_irq_nesting_start.arm +++ b/ports/cortex_r7/ghs/src/tx_thread_irq_nesting_start.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r7/ghs/src/tx_thread_schedule.arm b/ports/cortex_r7/ghs/src/tx_thread_schedule.arm index acf51ff0..011813ed 100644 --- a/ports/cortex_r7/ghs/src/tx_thread_schedule.arm +++ b/ports/cortex_r7/ghs/src/tx_thread_schedule.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r7/ghs/src/tx_thread_stack_build.arm b/ports/cortex_r7/ghs/src/tx_thread_stack_build.arm index 04921a51..b1157128 100644 --- a/ports/cortex_r7/ghs/src/tx_thread_stack_build.arm +++ b/ports/cortex_r7/ghs/src/tx_thread_stack_build.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r7/ghs/src/tx_thread_system_return.arm b/ports/cortex_r7/ghs/src/tx_thread_system_return.arm index 2c15127c..2cef1a6c 100644 --- a/ports/cortex_r7/ghs/src/tx_thread_system_return.arm +++ b/ports/cortex_r7/ghs/src/tx_thread_system_return.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r7/ghs/src/tx_thread_vectored_context_save.arm b/ports/cortex_r7/ghs/src/tx_thread_vectored_context_save.arm index 56f5d276..6d210e97 100644 --- a/ports/cortex_r7/ghs/src/tx_thread_vectored_context_save.arm +++ b/ports/cortex_r7/ghs/src/tx_thread_vectored_context_save.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/cortex_r7/ghs/src/tx_timer_interrupt.arm b/ports/cortex_r7/ghs/src/tx_timer_interrupt.arm index 5534b398..44afdde5 100644 --- a/ports/cortex_r7/ghs/src/tx_timer_interrupt.arm +++ b/ports/cortex_r7/ghs/src/tx_timer_interrupt.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports/linux/gnu/example_build/Makefile b/ports/linux/gnu/example_build/Makefile index 17607360..ddce0164 100644 --- a/ports/linux/gnu/example_build/Makefile +++ b/ports/linux/gnu/example_build/Makefile @@ -34,7 +34,7 @@ $(OUTPUT_FOLDER): sample_threadx: $(OUTPUT_FOLDER)/sample_threadx.o tx.a echo LD $@ - $(LINK) -o $@ $^ $(LIBS) + $(LINK) -o $@ $^ $(LIBS) tx.a: $(OUTPUT_FOLDER) $(LINUX_OBJS) $(GENERIC_OBJS) echo AR $@ @@ -68,7 +68,7 @@ files: do \ filename=`basename $$file`; \ [ "$$file" == "sample_threadx.c" ] || echo "$$filename \\" >> $(FILE_LIST); \ - done; + done; @printf "\n" >> $(FILE_LIST); @echo 'LINUX_OBJS = $$(LINUX_SRCS:%.c=$(OUTPUT_FOLDER)/%.o)' >> $(FILE_LIST); @printf "\n\n" >> $(FILE_LIST); @@ -77,7 +77,7 @@ files: do \ filename=`basename $$file`; \ [ "$$file" == "sample_threadx.c" ] || echo "$$filename \\" >> $(FILE_LIST); \ - done; + done; @printf "\n" >> $(FILE_LIST); @echo 'GENERIC_OBJS = $$(GENERIC_SRCS:%.c=$(OUTPUT_FOLDER)/generic/%.o)' >> $(FILE_LIST); diff --git a/ports/linux/gnu/example_build/sample_threadx.c b/ports/linux/gnu/example_build/sample_threadx.c index 080be3c4..43c0bdd4 100644 --- a/ports/linux/gnu/example_build/sample_threadx.c +++ b/ports/linux/gnu/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -253,11 +253,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -316,7 +316,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -369,7 +369,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/linux/gnu/inc/tx_port.h b/ports/linux/gnu/inc/tx_port.h index 7ca6161d..83d72df0 100644 --- a/ports/linux/gnu/inc/tx_port.h +++ b/ports/linux/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Linux/GNU */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Linux/GNU */ /* 6.3.0 */ /* */ /* AUTHOR */ @@ -32,30 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* symbol ULONG64_DEFINED, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 William E. Lamie Modified comment(s), removed */ -/* useless definition, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yanwu Cai Modified comment(s), fixed */ -/* compile warnings, */ -/* resulting in version 6.3.0 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -547,7 +533,7 @@ VOID _tx_thread_interrupt_restore(UINT previous_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation * ThreadX Linux/gcc Version 6.4.2 *"; + "Copyright (c) Microsoft Corporation * ThreadX Linux/gcc Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/linux/gnu/readme_threadx.txt b/ports/linux/gnu/readme_threadx.txt index 997607c7..ba546d83 100644 --- a/ports/linux/gnu/readme_threadx.txt +++ b/ports/linux/gnu/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for Linux + Microsoft's Azure RTOS ThreadX for Linux Using the GNU GCC Tools @@ -8,29 +8,29 @@ First make sure you are in the "example_build" directory. Also, make sure that you have setup your path and other environment variables necessary for the GNU development environment. The following command retrieves and installs GCC multilib on a Ubuntu system: - + sudo apt-get install gcc-multilib -At this point you may run the GNU make command to build the ThreadX core -library. This will build the ThreadX run-time environment in the -"example_build" directory. +At this point you may run the GNU make command to build the ThreadX core +library. This will build the ThreadX run-time environment in the +"example_build" directory. make tx.a -you should now observe the compilation of the ThreadX library source. At the +you should now observe the compilation of the ThreadX library source. At the end of the make, they are all combined into the run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. - + 2. Demonstration System -Building the demonstration is easy; simply execute the GNU make command while -inside the "example_build" directory. +Building the demonstration is easy; simply execute the GNU make command while +inside the "example_build" directory. make sample_threadx -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with tx.a. The resulting file DEMO is a binary file +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file DEMO is a binary file that can be executed. 2.1 Includes @@ -56,15 +56,15 @@ the tx_port.h header to include tx_user.h. 3. System Initialization -The system entry point is at main(), which is defined in the application. -Once the application calls tx_kernel_enter, ThreadX starts running and -performs various initialization duties prior to starting the scheduler. The +The system entry point is at main(), which is defined in the application. +Once the application calls tx_kernel_enter, ThreadX starts running and +performs various initialization duties prior to starting the scheduler. The Linux-specific initialization is done in the function _tx_initialize_low_level, -which is located in the file tx_initialize_low_level.c. This function is -responsible for setting up various system data structures and simulated +which is located in the file tx_initialize_low_level.c. This function is +responsible for setting up various system data structures and simulated interrupts - including the periodic timer interrupt source for ThreadX. -In addition, _tx_initialize_low_level determines the first available +In addition, _tx_initialize_low_level determines the first available address for use by the application. In Linux, this is basically done by using malloc to get a big block of memory from Linux. @@ -73,12 +73,12 @@ by using malloc to get a big block of memory from Linux. ThreadX for Linux is implemented using POSIX pthreads. Each application thread in ThreadX actually runs as a Linux pthread. The determination of -which application thread to run is made by the ThreadX scheduler, which -itself is a Linux pthread. The ThreadX scheduler is the highest priority +which application thread to run is made by the ThreadX scheduler, which +itself is a Linux pthread. The ThreadX scheduler is the highest priority thread in the system. Interrupts in ThreadX/Linux are also simulated by pthreads. A good example -is the ThreadX system timer interrupt, which can be found in +is the ThreadX system timer interrupt, which can be found in tx_initialize_low_level.c. ThreadX for linux utilizes the API pthread_setschedparam() which requires @@ -89,12 +89,12 @@ to run a ThreadX application: 5. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make it run faster, you can change the makefile to -enable all compiler optimizations. In addition, you can eliminate the -ThreadX basic API error checking by compiling your application code with the +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the makefile to +enable all compiler optimizations. In addition, you can eliminate the +ThreadX basic API error checking by compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING defined. @@ -102,7 +102,7 @@ symbol TX_DISABLE_ERROR_CHECKING defined. ThreadX provides simulated interrupt handling with Linux pthreads. Simulated interrupt threads may be created by the application or may be added to the -simulated timer interrupt defined in tx_initialize_low_level.c. The following +simulated timer interrupt defined in tx_initialize_low_level.c. The following format for creating simulated interrupts should be used: 6.1 Data structures @@ -133,7 +133,7 @@ struct sched_param sp; 6.3 Simulated Interrupt Thread Template The following is a template for the simulated interrupt thread. This interrupt will occur on -a periodic basis. +a periodic basis. void *_sample_linux_interrupt_entry(void *p) { @@ -154,7 +154,7 @@ struct timespec ts; /* Call ThreadX context restore for interrupt completion. */ _tx_thread_context_restore(); - } + } } diff --git a/ports/linux/gnu/src/tx_initialize_low_level.c b/ports/linux/gnu/src/tx_initialize_low_level.c index d3516aaa..32de408f 100644 --- a/ports/linux/gnu/src/tx_initialize_low_level.c +++ b/ports/linux/gnu/src/tx_initialize_low_level.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Initialize */ /** */ @@ -42,18 +43,18 @@ sem_t _tx_linux_semaphore_no_idle; ULONG _tx_linux_global_int_disabled_flag; struct timespec _tx_linux_time_stamp; __thread int _tx_linux_threadx_thread = 0; - + /* Define signals for linux thread. */ #define SUSPEND_SIG SIGUSR1 #define RESUME_SIG SIGUSR2 static sigset_t _tx_linux_thread_wait_mask; -static __thread int _tx_linux_thread_suspended; +static __thread int _tx_linux_thread_suspended; static sem_t _tx_linux_thread_timer_wait; static sem_t _tx_linux_thread_other_wait; /* Define simulated timer interrupt. This is done inside a thread, which is - how other interrupts may be defined as well. See code below for an + how other interrupts may be defined as well. See code below for an example. */ pthread_t _tx_linux_timer_id; @@ -136,11 +137,11 @@ pthread_mutex_t temp_copy; /* Now move to the next entry. */ _tx_linux_debug_entry_index++; - + /* Determine if we need to wrap the list. */ if (_tx_linux_debug_entry_index >= TX_LINUX_DEBUG_EVENT_SIZE) { - + /* Yes, wrap the list! */ _tx_linux_debug_entry_index = 0; } @@ -169,54 +170,48 @@ VOID _tx_thread_context_restore(VOID); extern VOID *_tx_initialize_unused_memory; -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_initialize_low_level Linux/GNU */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Linux/GNU */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function is responsible for any low-level processor */ -/* initialization, including setting up interrupt vectors, setting */ -/* up a periodic timer interrupt source, saving the system stack */ -/* pointer for use in ISR processing later, and finding the first */ -/* available RAM memory address for tx_application_define. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* sched_setaffinity */ -/* getpid */ -/* _tx_linux_thread_init */ -/* pthread_setschedparam */ -/* pthread_mutexattr_init */ -/* pthread_mutex_init */ -/* _tx_linux_thread_suspend */ -/* sem_init */ -/* pthread_create */ -/* printf */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* sched_setaffinity */ +/* getpid */ +/* _tx_linux_thread_init */ +/* pthread_setschedparam */ +/* pthread_mutexattr_init */ +/* pthread_mutex_init */ +/* _tx_linux_thread_suspend */ +/* sem_init */ +/* pthread_create */ +/* printf */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ /* */ /**************************************************************************/ VOID _tx_initialize_low_level(VOID) @@ -238,7 +233,7 @@ cpu_set_t mask; CPU_SET(rand() % get_nprocs(), &mask); if (sched_setaffinity(getpid(), sizeof(mask), &mask) != 0) { - + /* Error restricting the process to one core. */ printf("ThreadX Linux error restricting the process to one core!\n"); while(1) @@ -260,7 +255,7 @@ cpu_set_t mask; sp.sched_priority = TX_LINUX_PRIORITY_SCHEDULE; pthread_setschedparam(pthread_self(), SCHED_FIFO, &sp); - /* Create the system critical section. This is used by the + /* Create the system critical section. This is used by the scheduler thread (which is the main thread) to block all other stuff out. */ pthread_mutexattr_init(&attr); @@ -273,10 +268,10 @@ cpu_set_t mask; /* Initialize the global interrupt disabled flag. */ _tx_linux_global_int_disabled_flag = TX_FALSE; - + /* Create semaphore for timer thread. */ sem_init(&_tx_linux_timer_semaphore, 0, 0); - + /* Create semaphore for ISR thread. */ sem_init(&_tx_linux_isr_semaphore, 0, 0); @@ -302,7 +297,7 @@ cpu_set_t mask; /* This routine is called after initialization is complete in order to start - all interrupt threads. Interrupt threads in addition to the timer may + all interrupt threads. Interrupt threads in addition to the timer may be added to this routine as well. */ void _tx_initialize_start_interrupts(void) @@ -377,7 +372,7 @@ int err; tx_linux_mutex_unlock(_tx_linux_mutex); #endif /* TX_LINUX_NO_IDLE_ENABLE */ - } + } } /* Define functions for linux thread. */ @@ -395,11 +390,11 @@ void _tx_linux_thread_suspend_handler(int sig) else tx_linux_sem_post_nolock(&_tx_linux_thread_other_wait); - if(_tx_linux_thread_suspended) + if(_tx_linux_thread_suspended) return; _tx_linux_thread_suspended = 1; - sigsuspend(&_tx_linux_thread_wait_mask); + sigsuspend(&_tx_linux_thread_wait_mask); _tx_linux_thread_suspended = 0; } diff --git a/ports/linux/gnu/src/tx_thread_context_restore.c b/ports/linux/gnu/src/tx_thread_context_restore.c index 5466b30e..3d7b44bb 100644 --- a/ports/linux/gnu/src/tx_thread_context_restore.c +++ b/ports/linux/gnu/src/tx_thread_context_restore.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -31,50 +32,44 @@ extern sem_t _tx_linux_isr_semaphore; UINT _tx_linux_timer_waiting = 0; -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_context_restore Linux/GNU */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Linux/GNU */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function restores the interrupt context if it is processing a */ -/* nested interrupt. If not, it returns to the interrupt thread if no */ -/* preemption is necessary. Otherwise, if preemption is necessary or */ -/* if no thread was running, the function returns to the scheduler. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_linux_debug_entry_insert */ -/* tx_linux_mutex_lock */ -/* sem_trywait */ -/* tx_linux_sem_post */ -/* tx_linux_sem_wait */ -/* _tx_linux_thread_resume */ -/* tx_linux_mutex_recursive_unlock */ -/* */ -/* CALLED BY */ -/* */ -/* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_linux_debug_entry_insert */ +/* tx_linux_mutex_lock */ +/* sem_trywait */ +/* tx_linux_sem_post */ +/* tx_linux_sem_wait */ +/* _tx_linux_thread_resume */ +/* tx_linux_mutex_recursive_unlock */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ /* */ /**************************************************************************/ VOID _tx_thread_context_restore(VOID) @@ -101,7 +96,7 @@ VOID _tx_thread_context_restore(VOID) if ((_tx_thread_preempt_disable == 0) && (_tx_thread_current_ptr != _tx_thread_execute_ptr)) { - /* Preempt the running application thread. We don't need to suspend the + /* Preempt the running application thread. We don't need to suspend the application thread since that is done in the context save processing. */ /* Indicate that this thread was suspended asynchronously. */ diff --git a/ports/linux/gnu/src/tx_thread_context_save.c b/ports/linux/gnu/src/tx_thread_context_save.c index c98943fa..7bca3945 100644 --- a/ports/linux/gnu/src/tx_thread_context_save.c +++ b/ports/linux/gnu/src/tx_thread_context_save.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -30,46 +31,40 @@ #include "tx_timer.h" -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_context_save Linux/GNU */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Linux/GNU */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function saves the context of an executing thread in the */ -/* beginning of interrupt processing. The function also ensures that */ -/* the system stack is used upon return to the calling ISR. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_linux_debug_entry_insert */ -/* tx_linux_mutex_lock */ -/* _tx_linux_thread_suspend */ -/* tx_linux_mutex_unlock */ -/* */ -/* CALLED BY */ -/* */ -/* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_linux_debug_entry_insert */ +/* tx_linux_mutex_lock */ +/* _tx_linux_thread_suspend */ +/* tx_linux_mutex_unlock */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ /* */ /**************************************************************************/ VOID _tx_thread_context_save(VOID) diff --git a/ports/linux/gnu/src/tx_thread_interrupt_control.c b/ports/linux/gnu/src/tx_thread_interrupt_control.c index 657cf72e..75b62511 100644 --- a/ports/linux/gnu/src/tx_thread_interrupt_control.c +++ b/ports/linux/gnu/src/tx_thread_interrupt_control.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -47,53 +48,47 @@ VOID _tx_thread_interrupt_restore(UINT previous_posture) } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_interrupt_control Linux/GNU */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Linux/GNU */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function is responsible for changing the interrupt lockout */ -/* posture of the system. */ -/* */ -/* INPUT */ -/* */ -/* new_posture New interrupt lockout posture */ -/* */ -/* OUTPUT */ -/* */ -/* old_posture Old interrupt lockout posture */ -/* */ -/* CALLS */ -/* */ -/* tx_linux_mutex_lock */ -/* pthread_self */ -/* pthread_getschedparam */ -/* tx_linux_mutex_recursive_unlock */ -/* pthread_exit */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* tx_linux_mutex_lock */ +/* pthread_self */ +/* pthread_getschedparam */ +/* tx_linux_mutex_recursive_unlock */ +/* pthread_exit */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ UINT _tx_thread_interrupt_control(UINT new_posture) { UINT old_posture; -TX_THREAD *thread_ptr; +TX_THREAD *thread_ptr; pthread_t thread_id; int exit_code = 0; @@ -107,18 +102,18 @@ int exit_code = 0; /* Pickup the current thread pointer. */ thread_ptr = _tx_thread_current_ptr; - /* Determine if this is a thread and it does not + /* Determine if this is a thread and it does not match the current thread pointer. */ - if ((_tx_linux_threadx_thread) && - ((!thread_ptr) || (!pthread_equal(thread_ptr -> tx_thread_linux_thread_id, thread_id)))) - { + if ((_tx_linux_threadx_thread) && + ((!thread_ptr) || (!pthread_equal(thread_ptr -> tx_thread_linux_thread_id, thread_id)))) + { - /* This indicates the Linux thread was actually terminated by ThreadX is only + /* This indicates the Linux thread was actually terminated by ThreadX is only being allowed to run in order to cleanup its resources. */ /* Unlock linux mutex. */ tx_linux_mutex_recursive_unlock(_tx_linux_mutex); pthread_exit((void *)&exit_code); - } + } /* Determine the current interrupt lockout condition. */ if (tx_linux_mutex_recursive_count == 1) @@ -155,7 +150,7 @@ int exit_code = 0; _tx_linux_global_int_disabled_flag = TX_TRUE; } } - else if (thread_ptr) + else if (thread_ptr) { /* Determine how to apply the new posture. */ diff --git a/ports/linux/gnu/src/tx_thread_schedule.c b/ports/linux/gnu/src/tx_thread_schedule.c index d65104a1..eeff680f 100644 --- a/ports/linux/gnu/src/tx_thread_schedule.c +++ b/ports/linux/gnu/src/tx_thread_schedule.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -39,7 +40,7 @@ extern pthread_t _tx_linux_timer_id; /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_schedule Linux/GNU */ +/* _tx_thread_schedule Linux/GNU */ /* 6.1 */ /* AUTHOR */ /* */ @@ -73,12 +74,6 @@ extern pthread_t _tx_linux_timer_id; /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_thread_schedule(VOID) { @@ -127,9 +122,9 @@ struct timespec ts; ts.tv_sec++; } sem_timedwait(&_tx_linux_semaphore_no_idle, &ts); -#else +#else nanosleep(&ts, &ts); -#endif /* TX_LINUX_NO_IDLE_ENABLE */ +#endif /* TX_LINUX_NO_IDLE_ENABLE */ } } diff --git a/ports/linux/gnu/src/tx_thread_stack_build.c b/ports/linux/gnu/src/tx_thread_stack_build.c index 424f53e2..cdadba6c 100644 --- a/ports/linux/gnu/src/tx_thread_stack_build.c +++ b/ports/linux/gnu/src/tx_thread_stack_build.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -36,50 +37,44 @@ void *_tx_linux_thread_entry(void *ptr); -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_stack_build Linux/GNU */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Linux/GNU */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ +/* */ /* This function builds a stack frame on the supplied thread's stack. */ /* The stack frame results in a fake interrupt return to the supplied */ -/* function pointer. */ -/* */ -/* INPUT */ -/* */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ /* thread_ptr Pointer to thread control blk */ /* function_ptr Pointer to return function */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* pthread_create */ -/* pthread_setschedparam */ -/* _tx_linux_thread_suspend */ -/* sem_init */ -/* printf */ -/* _tx_linux_thread_resume */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_thread_create Create thread service */ -/* _tx_thread_reset Reset thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* pthread_create */ +/* pthread_setschedparam */ +/* _tx_linux_thread_suspend */ +/* sem_init */ +/* printf */ +/* _tx_linux_thread_resume */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* _tx_thread_reset Reset thread service */ /* */ /**************************************************************************/ VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -115,11 +110,11 @@ struct sched_param sp; sp.sched_priority = TX_LINUX_PRIORITY_USER_THREAD; pthread_setschedparam(thread_ptr -> tx_thread_linux_thread_id, SCHED_FIFO, &sp); - /* Setup the thread suspension type to solicited thread suspension. + /* Setup the thread suspension type to solicited thread suspension. Pseudo interrupt handlers will suspend with this field set to 1. */ thread_ptr -> tx_thread_linux_suspension_type = 0; - /* Clear the disabled count that will keep track of the + /* Clear the disabled count that will keep track of the tx_interrupt_control nesting. */ thread_ptr -> tx_thread_linux_int_disabled_flag = 0; diff --git a/ports/linux/gnu/src/tx_thread_system_return.c b/ports/linux/gnu/src/tx_thread_system_return.c index 16d81d59..cc876721 100644 --- a/ports/linux/gnu/src/tx_thread_system_return.c +++ b/ports/linux/gnu/src/tx_thread_system_return.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -30,54 +31,48 @@ #include -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_system_return Linux/GNU */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Linux/GNU */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function is target processor specific. It is used to transfer */ -/* control from a thread back to the system. Only a minimal context */ -/* is saved since the compiler assumes temp registers are going to get */ -/* slicked by a function call anyway. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_linux_debug_entry_insert */ -/* tx_linux_mutex_lock */ -/* pthread_self */ -/* pthread_getschedparam */ -/* pthread_equal */ -/* tx_linux_mutex_recursive_unlock */ -/* tx_linux_mutex_unlock */ -/* pthread_exit */ -/* tx_linux_sem_post */ -/* sem_trywait */ -/* tx_linux_sem_wait */ -/* */ -/* CALLED BY */ -/* */ -/* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the system. Only a minimal context */ +/* is saved since the compiler assumes temp registers are going to get */ +/* slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_linux_debug_entry_insert */ +/* tx_linux_mutex_lock */ +/* pthread_self */ +/* pthread_getschedparam */ +/* pthread_equal */ +/* tx_linux_mutex_recursive_unlock */ +/* tx_linux_mutex_unlock */ +/* pthread_exit */ +/* tx_linux_sem_post */ +/* sem_trywait */ +/* tx_linux_sem_wait */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ /* */ /**************************************************************************/ VOID _tx_thread_system_return(VOID) @@ -104,13 +99,13 @@ int exit_code = 0; /* Pickup the current thread pointer. */ temp_thread_ptr = _tx_thread_current_ptr; - /* Determine if this is a thread (0) and it does not + /* Determine if this is a thread (0) and it does not match the current thread pointer. */ - if ((_tx_linux_threadx_thread) && - ((!temp_thread_ptr) || (!pthread_equal(temp_thread_ptr -> tx_thread_linux_thread_id, thread_id)))) - { + if ((_tx_linux_threadx_thread) && + ((!temp_thread_ptr) || (!pthread_equal(temp_thread_ptr -> tx_thread_linux_thread_id, thread_id)))) + { - /* This indicates the Linux thread was actually terminated by ThreadX is only + /* This indicates the Linux thread was actually terminated by ThreadX is only being allowed to run in order to cleanup its resources. */ /* Unlock linux mutex. */ tx_linux_mutex_recursive_unlock(_tx_linux_mutex); @@ -176,19 +171,19 @@ int exit_code = 0; /* Pickup the current thread pointer. */ temp_thread_ptr = _tx_thread_current_ptr; - /* Determine if this is a thread and it does not + /* Determine if this is a thread and it does not match the current thread pointer. */ - if ((_tx_linux_threadx_thread) && - ((!temp_thread_ptr) || (!pthread_equal(temp_thread_ptr -> tx_thread_linux_thread_id, thread_id)))) - { + if ((_tx_linux_threadx_thread) && + ((!temp_thread_ptr) || (!pthread_equal(temp_thread_ptr -> tx_thread_linux_thread_id, thread_id)))) + { /* Unlock Linux mutex. */ tx_linux_mutex_recursive_unlock(_tx_linux_mutex); - /* This indicates the Linux thread was actually terminated by ThreadX and is only + /* This indicates the Linux thread was actually terminated by ThreadX and is only being allowed to run in order to cleanup its resources. */ pthread_exit((void *)&exit_code); - } + } /* Now determine if the application thread last had interrupts disabled. */ diff --git a/ports/linux/gnu/src/tx_timer_interrupt.c b/ports/linux/gnu/src/tx_timer_interrupt.c index 8e55ca7f..d139fd9b 100644 --- a/ports/linux/gnu/src/tx_timer_interrupt.c +++ b/ports/linux/gnu/src/tx_timer_interrupt.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Timer */ /** */ @@ -30,49 +31,43 @@ VOID _tx_timer_interrupt(VOID); -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_timer_interrupt Linux/GNU */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Linux/GNU */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function processes the hardware timer interrupt. This */ -/* processing includes incrementing the system clock and checking for */ -/* time slice and/or timer expiration. If either is found, the */ -/* interrupt context save/restore functions are called along with the */ -/* expiration functions. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_linux_debug_entry_insert */ -/* tx_linux_mutex_lock */ -/* tx_linux_mutex_unlock */ -/* _tx_timer_expiration_process */ -/* _tx_thread_time_slice */ -/* */ -/* CALLED BY */ -/* */ -/* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_linux_debug_entry_insert */ +/* tx_linux_mutex_lock */ +/* tx_linux_mutex_unlock */ +/* _tx_timer_expiration_process */ +/* _tx_thread_time_slice */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ /* */ /**************************************************************************/ VOID _tx_timer_interrupt(VOID) diff --git a/ports/risc-v32/clang/example_build/qemu_virt/csr.h b/ports/risc-v32/clang/example_build/qemu_virt/csr.h index 0c163404..ab335dcc 100644 --- a/ports/risc-v32/clang/example_build/qemu_virt/csr.h +++ b/ports/risc-v32/clang/example_build/qemu_virt/csr.h @@ -23,7 +23,7 @@ #define MSTATUS_FS (1L << 13) // Machine-mode Interrupt Enable -#define MIE_MTIE (1L << 7) +#define MIE_MTIE (1L << 7) #define MIE_MSIE (1L << 3) #define MIE_MEIE (1L << 11) #define MIE_STIE (1L << 5) // supervisor timer diff --git a/ports/risc-v32/clang/example_build/qemu_virt/tx_initialize_low_level.S b/ports/risc-v32/clang/example_build/qemu_virt/tx_initialize_low_level.S index 4cbfcf65..f3cd99a1 100644 --- a/ports/risc-v32/clang/example_build/qemu_virt/tx_initialize_low_level.S +++ b/ports/risc-v32/clang/example_build/qemu_virt/tx_initialize_low_level.S @@ -44,11 +44,6 @@ /* CALLED BY */ /* */ /* hardware exception */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 02-02-2026 Francisco Merino Adapted for RV32 Clang */ /* */ /**************************************************************************/ diff --git a/ports/risc-v32/clang/example_build/qemu_virt/uart.h b/ports/risc-v32/clang/example_build/qemu_virt/uart.h index 19e8f73d..debfd9df 100644 --- a/ports/risc-v32/clang/example_build/qemu_virt/uart.h +++ b/ports/risc-v32/clang/example_build/qemu_virt/uart.h @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at diff --git a/ports/risc-v32/clang/inc/tx_port.h b/ports/risc-v32/clang/inc/tx_port.h index ece70953..f89c148c 100644 --- a/ports/risc-v32/clang/inc/tx_port.h +++ b/ports/risc-v32/clang/inc/tx_port.h @@ -42,12 +42,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 02-26-2026 Francisco Merino Initial Version 6.4.x */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -282,7 +276,7 @@ UINT _tx_thread_interrupt_control(UIN #ifndef __ASSEMBLER__ #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX RISC-V32/GNU Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RISC-V32/GNU Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif /* TX_THREAD_INIT */ diff --git a/ports/risc-v32/clang/readme_threadx.txt b/ports/risc-v32/clang/readme_threadx.txt index 53ffcf23..ce838553 100644 --- a/ports/risc-v32/clang/readme_threadx.txt +++ b/ports/risc-v32/clang/readme_threadx.txt @@ -24,7 +24,7 @@ CMake-based build (recommended) From the ThreadX top-level directory: - Set environment variable "GCC_INSTALL_PREFIX" with the location of the + Set environment variable "GCC_INSTALL_PREFIX" with the location of the GNU toolchain, i.e., export GCC_INSTALL_PREFIX=/opt/riscv_rv32ima cmake -Bbuild -GNinja -DCMAKE_TOOLCHAIN_FILE=cmake/riscv32_clang.cmake . @@ -90,7 +90,7 @@ After tx_initialize_low_level returns, main() calls board_init() to: The RISC-V32 ABI defines t0-t6 and a0-a7 as caller-saved (scratch) registers. All other registers used by a function must be preserved by the function. -ThreadX takes advantage of this: when a context switch happens during a +ThreadX takes advantage of this: when a context switch happens during a function call, only the non-scratch registers need to be saved. Stack Frame Types @@ -147,8 +147,8 @@ Stack Layout for Interrupt Frame (with FP enabled): 47-62 0xBC-0xF8 ft0-ft11 Scratch FP registers* 63 0xFC fcsr FP control/status register ───────────────────────────────────────────────── - *Note: In ilp32d ABI, FP registers are 8 bytes each, but current - port implementation uses 4-byte indexing which may cause + *Note: In ilp32d ABI, FP registers are 8 bytes each, but current + port implementation uses 4-byte indexing which may cause overlap if fsd/fld are used. @@ -329,19 +329,19 @@ Example from QEMU virt build: SECTIONS { . = 0x80000000; /* QEMU virt base address */ - + .text : { *(.text .text.*) } .rodata : { *(.rodata .rodata.*) } .data : { *(.data .data.*) } .bss : { *(.bss .bss.*) } - + .stack : { . = ALIGN(4096); _sysstack_start = .; . += 0x1000; /* 4KB initial stack */ _sysstack_end = .; } - + PROVIDE(_end = .); } diff --git a/ports/risc-v32/clang/src/tx_initialize_low_level.S b/ports/risc-v32/clang/src/tx_initialize_low_level.S index 6414e1be..467c3735 100644 --- a/ports/risc-v32/clang/src/tx_initialize_low_level.S +++ b/ports/risc-v32/clang/src/tx_initialize_low_level.S @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (c) 2026 Quintauris + * Copyright (c) 2026 Quintauris * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -59,12 +59,6 @@ __tx_free_memory_start: /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 26-02-2026 Francisco Merino Initial Version 6.4.x */ -/* */ /**************************************************************************/ /* VOID _tx_initialize_low_level(VOID) { */ diff --git a/ports/risc-v32/clang/src/tx_thread_context_restore.S b/ports/risc-v32/clang/src/tx_thread_context_restore.S index 8fa108b4..88ac0ce3 100644 --- a/ports/risc-v32/clang/src/tx_thread_context_restore.S +++ b/ports/risc-v32/clang/src/tx_thread_context_restore.S @@ -53,12 +53,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 26-02-2026 Francisco Merino Initial Version 6.4.x */ -/* */ /**************************************************************************/ /* VOID _tx_thread_context_restore(VOID) { */ @@ -149,13 +143,13 @@ _tx_thread_context_restore: /* Compose mstatus via read/modify/write to avoid clobbering unrelated bits. Set MPIE and restore MPP to Machine, preserve other fields. */ - + csrr t1, mstatus /* Clear MPP/MPIE/MIE bits in t1 then set desired values. */ li t2, 0x1888 // MPP(0x1800) | MPIE(0x80) | MIE(0x08) - li t3, 0x1800 // Set MPP to Machine mode (bits 12:11) + li t3, 0x1800 // Set MPP to Machine mode (bits 12:11) /* Construct new mstatus in t1: clear mask bits, set MPP/MPIE and optionally FP bit, preserve everything except the bits we will modify. */ @@ -406,7 +400,7 @@ _tx_thread_dont_save_ts: la t0, _tx_thread_current_ptr // Pickup current thread pointer address sw x0, 0(t0) // Clear current thread pointer - + /* } */ _tx_thread_idle_system_restore: diff --git a/ports/risc-v32/clang/src/tx_thread_context_save.S b/ports/risc-v32/clang/src/tx_thread_context_save.S index 8801374e..ffb302e3 100644 --- a/ports/risc-v32/clang/src/tx_thread_context_save.S +++ b/ports/risc-v32/clang/src/tx_thread_context_save.S @@ -52,12 +52,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 26-02-2026 Francisco Merino Initial Version 6.4.x */ -/* */ /**************************************************************************/ /* VOID _tx_thread_context_save(VOID) { */ diff --git a/ports/risc-v32/clang/src/tx_thread_interrupt_control.S b/ports/risc-v32/clang/src/tx_thread_interrupt_control.S index 867174ad..86b6745e 100644 --- a/ports/risc-v32/clang/src/tx_thread_interrupt_control.S +++ b/ports/risc-v32/clang/src/tx_thread_interrupt_control.S @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (c) 2026 Quintauris + * Copyright (c) 2026 Quintauris * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -52,12 +52,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 26-02-2026 Francisco Merino Initial Version 6.4.x */ -/* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_control(UINT new_posture) { */ diff --git a/ports/risc-v32/clang/src/tx_thread_schedule.S b/ports/risc-v32/clang/src/tx_thread_schedule.S index 3e6d3506..d5a54fa2 100644 --- a/ports/risc-v32/clang/src/tx_thread_schedule.S +++ b/ports/risc-v32/clang/src/tx_thread_schedule.S @@ -1,6 +1,6 @@ /*************************************************************************** - * Copyright (c) 2026 Quintauris - * + * Copyright (c) 2026 Quintauris + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. @@ -55,12 +55,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */ -/* */ /**************************************************************************/ /* VOID _tx_thread_schedule(VOID) { */ diff --git a/ports/risc-v32/clang/src/tx_thread_stack_build.S b/ports/risc-v32/clang/src/tx_thread_stack_build.S index 20ceed2f..2b8ebae1 100644 --- a/ports/risc-v32/clang/src/tx_thread_stack_build.S +++ b/ports/risc-v32/clang/src/tx_thread_stack_build.S @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (c) 2026 Quintauris + * Copyright (c) 2026 Quintauris * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at @@ -54,12 +54,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 26-02-2026 Francisco Merino Initial Version 6.4.x */ -/* */ /**************************************************************************/ /* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) { */ diff --git a/ports/risc-v32/clang/src/tx_thread_system_return.S b/ports/risc-v32/clang/src/tx_thread_system_return.S index e8fe5617..b54f54fa 100644 --- a/ports/risc-v32/clang/src/tx_thread_system_return.S +++ b/ports/risc-v32/clang/src/tx_thread_system_return.S @@ -1,6 +1,6 @@ /*************************************************************************** - * Copyright (c) 2026 Quintauris - * + * Copyright (c) 2026 Quintauris + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. @@ -54,12 +54,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 26-02-2026 Francisco Merino Initial Version 6.4.x */ -/* */ /**************************************************************************/ /* VOID _tx_thread_system_return(VOID) { */ diff --git a/ports/risc-v32/clang/src/tx_timer_interrupt.S b/ports/risc-v32/clang/src/tx_timer_interrupt.S index b32256ba..b64bf06b 100644 --- a/ports/risc-v32/clang/src/tx_timer_interrupt.S +++ b/ports/risc-v32/clang/src/tx_timer_interrupt.S @@ -56,12 +56,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-20-2023 Akif Ejaz Initial Version 6.2.1 */ -/* */ /**************************************************************************/ /* VOID _tx_timer_interrupt(VOID) { */ diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/tx_initialize_low_level.S b/ports/risc-v32/gnu/example_build/qemu_virt/tx_initialize_low_level.S index d7108c27..9a7a74ff 100644 --- a/ports/risc-v32/gnu/example_build/qemu_virt/tx_initialize_low_level.S +++ b/ports/risc-v32/gnu/example_build/qemu_virt/tx_initialize_low_level.S @@ -43,11 +43,6 @@ /* CALLED BY */ /* */ /* hardware exception */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-29-2025 Akif Ejaz Adapted for RV32 from RV64 port */ /* */ /**************************************************************************/ diff --git a/ports/risc-v32/gnu/example_build/qemu_virt/uart.h b/ports/risc-v32/gnu/example_build/qemu_virt/uart.h index 19e8f73d..debfd9df 100644 --- a/ports/risc-v32/gnu/example_build/qemu_virt/uart.h +++ b/ports/risc-v32/gnu/example_build/qemu_virt/uart.h @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at diff --git a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/gcc_flash_smartl.ld b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/gcc_flash_smartl.ld index 3cfad67d..19fac7e4 100644 --- a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/gcc_flash_smartl.ld +++ b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/gcc_flash_smartl.ld @@ -48,7 +48,7 @@ SECTIONS KEEP(*startup.o(*.vectors)) KEEP(*vectors.o(*.text)) KEEP(*whetstone.o(*.text)) - KEEP(*startup.S.obj(*.text)) + KEEP(*startup.S.obj(*.text)) KEEP(*startup.S.obj(*.vectors)) KEEP(*vectors.S.obj(*.text)) KEEP(*whetstone.c.obj(*.text)) diff --git a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/include/asm/riscv_asm_macro.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/include/asm/riscv_asm_macro.h index dfa08578..456061ca 100644 --- a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/include/asm/riscv_asm_macro.h +++ b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/include/asm/riscv_asm_macro.h @@ -19,7 +19,7 @@ /* * attention: don't modify this file as a suggest * you should copy from chip_riscv_dummy/include/asm/riscv_asm_macro.h and keep it newer - * please contact xuantie-rtos os team if have question + * please contact xuantie-rtos os team if have question */ #ifndef __RISCV_ASM_MACRO_H__ diff --git a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/include/asm/riscv_csr.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/include/asm/riscv_csr.h index 0bea1b57..22e36ab4 100644 --- a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/include/asm/riscv_csr.h +++ b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/include/asm/riscv_csr.h @@ -19,7 +19,7 @@ /* * attention: don't modify this file as a suggest * you should copy from chip_riscv_dummy/include/asm/riscv_csr.h and keep it newer - * please contact xuantie-rtos os team if have question + * please contact xuantie-rtos os team if have question */ #ifndef __RISCV_CSR_H__ diff --git a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/sys/feature.c b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/sys/feature.c index 018011df..4895e52c 100644 --- a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/sys/feature.c +++ b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/chip_riscv_dummy/src/sys/feature.c @@ -295,7 +295,7 @@ void cpu_features_init(void) while(1); } break; - case 0x8: + case 0x8: if (cpu_ver >= 0x0) { rv_csr_clear(CSR_MXSTATUS, 0x1); rv_csr_write(CSR_MISELECT,CSR_MNASTATUS); diff --git a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/core/csi_rv64_gcc.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/core/csi_rv64_gcc.h index 9878668e..cbfcf95a 100644 --- a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/core/csi_rv64_gcc.h +++ b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/core/csi_rv64_gcc.h @@ -1643,8 +1643,8 @@ __ALWAYS_STATIC_INLINE void __ICACHE_IALL(void) } /** - \brief Invalid all icache and broadcast to other cores - \details Invalid all icache and broadcast to other cores + \brief Invalid all icache and broadcast to other cores + \details Invalid all icache and broadcast to other cores */ __ALWAYS_STATIC_INLINE void __ICACHE_IALLS(void) { diff --git a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/gpio.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/gpio.h index fb8aed65..e3354518 100755 --- a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/gpio.h +++ b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/gpio.h @@ -189,7 +189,7 @@ csi_error_t csi_gpio_attach_callback(csi_gpio_t *gpio, void *callback, void *ar /** \brief Detach the interrupt callback to the port \param[in] gpio GPIO port handle - \return None + \return None */ void csi_gpio_detach_callback(csi_gpio_t *gpio); @@ -203,7 +203,7 @@ csi_error_t csi_gpio_enable_pm(csi_gpio_t *gpio); /** \brief Disable gpio power manage \param[in] gpio GPIO handle to operate - \return None + \return None */ void csi_gpio_disable_pm(csi_gpio_t *gpio); diff --git a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/irq.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/irq.h index 6272d15b..73a7c211 100755 --- a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/irq.h +++ b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/irq.h @@ -72,7 +72,7 @@ void csi_irq_attach(uint32_t irq_num, void *irq_handler, csi_dev_t *dev); \param[in] irq_num Number of IRQ. \param[in] irq_handler2 IRQ Handler. \param[in] dev The dev to operate - \param[in] arg user data of irq_handler2 + \param[in] arg user data of irq_handler2 \return None. */ void csi_irq_attach2(uint32_t irq_num, void *irq_handler2, csi_dev_t *dev, void *arg); diff --git a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/pin.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/pin.h index d1a614b6..4173f641 100755 --- a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/pin.h +++ b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/drv/pin.h @@ -74,7 +74,7 @@ typedef enum{ PIN_I2S_SDI, PIN_I2S_SDO }csi_pin_i2s_t; - + typedef struct { pin_name_t pin_name; uint8_t idx; ///< ctrl idx. e.g: ADC0 channel 1, idx = 0, channel = 1 diff --git a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/syslog.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/syslog.h index 063649c8..b24586db 100755 --- a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/syslog.h +++ b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/csi/csi2/include/syslog.h @@ -15,7 +15,7 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - + /****************************************************************************** * @file syslog.h * @brief Defines syslog APIs and usage diff --git a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/libc_threadx/include/serf/minilibc_stdio.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/libc_threadx/include/serf/minilibc_stdio.h index 67b6bb40..5ea1534f 100644 --- a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/libc_threadx/include/serf/minilibc_stdio.h +++ b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/components/libc_threadx/include/serf/minilibc_stdio.h @@ -51,7 +51,7 @@ extern fmt_in_fn g_current_inputs; #define print_current_in_set(fn) do{g_current_inputs = fn;}while(0) static inline int is_normal_outputs(void) { - if(g_current_inputs) + if(g_current_inputs) return 0; return 1; } diff --git a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/demo_threadx.c b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/demo_threadx.c index 5f17f954..3df2c251 100644 --- a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/demo_threadx.c +++ b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/demo_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include @@ -82,42 +82,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -125,23 +125,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -244,11 +244,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -308,7 +308,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -361,7 +361,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/readme_e906.txt b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/readme_e906.txt index 2ffd7618..c1c46394 100644 --- a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/readme_e906.txt +++ b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/readme_e906.txt @@ -9,7 +9,7 @@ delivers considerable integer and enhanced, energy-efficient floating-point comp Prerequisites - Install a XuanTie bare-metal GNU toolchain with riscv64-unknown-elf prefix -- Download URL: https://www.xrvm.cn/community/download?versionId=4460156621967921152 +- Download URL: https://www.xrvm.cn/community/download?versionId=4460156621967921152 - Toolchain archive name: XuanTie-900-gcc-elf-newlib-x86_64-V3.2.0-20250627.tar.gz Verify the toolchain: diff --git a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/tx_user.h b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/tx_user.h index 896e2233..fb692057 100644 --- a/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/tx_user.h +++ b/ports/risc-v32/gnu/example_build/xuantie_smartl_fpga/tx_user.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -39,33 +40,6 @@ /* Note that all the defines in this file may also be made on the */ /* command line when building ThreadX library and application objects. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1 */ -/* 03-02-2021 Scott Larson Modified comment(s), */ -/* added option to remove */ -/* FileX pointer, */ -/* resulting in version 6.1.5 */ -/* 06-02-2021 Scott Larson Added options for multiple */ -/* block pool search & delay, */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 Yuxin Zhou Modified comment(s), added */ -/* user-configurable symbol */ -/* TX_TIMER_TICKS_PER_SECOND */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Wenhui Xie Modified comment(s), */ -/* optimized the definition of */ -/* TX_TIMER_TICKS_PER_SECOND, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Xiuwen Cai Modified comment(s), */ -/* added option for random */ -/* number stack filling, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #ifndef TX_USER_H @@ -228,7 +202,7 @@ static inline int _csi_vlenb_get_value(void) /* Determine if random number is used for stack filling. By default, ThreadX uses a fixed pattern for stack filling. When the following is defined, ThreadX uses a random number - for stack filling. This is effective only when TX_ENABLE_STACK_CHECKING is defined. */ + for stack filling. This is effective only when TX_ENABLE_STACK_CHECKING is defined. */ /* #define TX_ENABLE_RANDOM_NUMBER_STACK_FILLING diff --git a/ports/risc-v32/gnu/inc/tx_port.h b/ports/risc-v32/gnu/inc/tx_port.h index f4dd75af..ed014675 100644 --- a/ports/risc-v32/gnu/inc/tx_port.h +++ b/ports/risc-v32/gnu/inc/tx_port.h @@ -42,12 +42,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -282,7 +276,7 @@ UINT _tx_thread_interrupt_control(UIN #ifndef __ASSEMBLER__ #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX RISC-V32/GNU Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RISC-V32/GNU Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif /* TX_THREAD_INIT */ diff --git a/ports/risc-v32/gnu/readme_threadx.txt b/ports/risc-v32/gnu/readme_threadx.txt index e4f16971..da61ae9c 100644 --- a/ports/risc-v32/gnu/readme_threadx.txt +++ b/ports/risc-v32/gnu/readme_threadx.txt @@ -80,7 +80,7 @@ After tx_initialize_low_level returns, main() calls board_init() to: The RISC-V32 ABI defines t0-t6 and a0-a7 as caller-saved (scratch) registers. All other registers used by a function must be preserved by the function. -ThreadX takes advantage of this: when a context switch happens during a +ThreadX takes advantage of this: when a context switch happens during a function call, only the non-scratch registers need to be saved. Stack Frame Types @@ -137,8 +137,8 @@ Stack Layout for Interrupt Frame (with FP enabled): 47-62 0xBC-0xF8 ft0-ft11 Scratch FP registers* 63 0xFC fcsr FP control/status register ───────────────────────────────────────────────── - *Note: In ilp32d ABI, FP registers are 8 bytes each, but current - port implementation uses 4-byte indexing which may cause + *Note: In ilp32d ABI, FP registers are 8 bytes each, but current + port implementation uses 4-byte indexing which may cause overlap if fsd/fld are used. @@ -319,19 +319,19 @@ Example from QEMU virt build: SECTIONS { . = 0x80000000; /* QEMU virt base address */ - + .text : { *(.text .text.*) } .rodata : { *(.rodata .rodata.*) } .data : { *(.data .data.*) } .bss : { *(.bss .bss.*) } - + .stack : { . = ALIGN(4096); _sysstack_start = .; . += 0x1000; /* 4KB initial stack */ _sysstack_end = .; } - + PROVIDE(_end = .); } diff --git a/ports/risc-v32/gnu/src/tx_initialize_low_level.S b/ports/risc-v32/gnu/src/tx_initialize_low_level.S index 70fefc84..703466bd 100644 --- a/ports/risc-v32/gnu/src/tx_initialize_low_level.S +++ b/ports/risc-v32/gnu/src/tx_initialize_low_level.S @@ -59,12 +59,6 @@ __tx_free_memory_start: /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */ -/* */ /**************************************************************************/ /* VOID _tx_initialize_low_level(VOID) { */ diff --git a/ports/risc-v32/gnu/src/tx_thread_context_restore.S b/ports/risc-v32/gnu/src/tx_thread_context_restore.S index ba553a46..73a07f61 100644 --- a/ports/risc-v32/gnu/src/tx_thread_context_restore.S +++ b/ports/risc-v32/gnu/src/tx_thread_context_restore.S @@ -53,12 +53,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */ -/* */ /**************************************************************************/ /* VOID _tx_thread_context_restore(VOID) { */ @@ -149,13 +143,13 @@ _tx_thread_context_restore: /* Compose mstatus via read/modify/write to avoid clobbering unrelated bits. Set MPIE and restore MPP to Machine, preserve other fields. */ - + csrr t1, mstatus /* Clear MPP/MPIE/MIE bits in t1 then set desired values. */ li t2, 0x1888 // MPP(0x1800) | MPIE(0x80) | MIE(0x08) - li t3, 0x1800 // Set MPP to Machine mode (bits 12:11) + li t3, 0x1800 // Set MPP to Machine mode (bits 12:11) /* Construct new mstatus in t1: clear mask bits, set MPP/MPIE and optionally FP bit, preserve everything except the bits we will modify. */ @@ -406,7 +400,7 @@ _tx_thread_dont_save_ts: la t0, _tx_thread_current_ptr // Pickup current thread pointer address sw x0, 0(t0) // Clear current thread pointer - + /* } */ _tx_thread_idle_system_restore: diff --git a/ports/risc-v32/gnu/src/tx_thread_context_save.S b/ports/risc-v32/gnu/src/tx_thread_context_save.S index 3b7496b3..66402934 100644 --- a/ports/risc-v32/gnu/src/tx_thread_context_save.S +++ b/ports/risc-v32/gnu/src/tx_thread_context_save.S @@ -52,12 +52,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */ -/* */ /**************************************************************************/ /* VOID _tx_thread_context_save(VOID) { */ diff --git a/ports/risc-v32/gnu/src/tx_thread_interrupt_control.S b/ports/risc-v32/gnu/src/tx_thread_interrupt_control.S index 8e28cf74..aab2955b 100644 --- a/ports/risc-v32/gnu/src/tx_thread_interrupt_control.S +++ b/ports/risc-v32/gnu/src/tx_thread_interrupt_control.S @@ -52,12 +52,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */ -/* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_control(UINT new_posture) { */ diff --git a/ports/risc-v32/gnu/src/tx_thread_schedule.S b/ports/risc-v32/gnu/src/tx_thread_schedule.S index edf3462f..1c235a2d 100644 --- a/ports/risc-v32/gnu/src/tx_thread_schedule.S +++ b/ports/risc-v32/gnu/src/tx_thread_schedule.S @@ -55,12 +55,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */ -/* */ /**************************************************************************/ /* VOID _tx_thread_schedule(VOID) { */ diff --git a/ports/risc-v32/gnu/src/tx_thread_stack_build.S b/ports/risc-v32/gnu/src/tx_thread_stack_build.S index 36f9b317..4ade60ca 100644 --- a/ports/risc-v32/gnu/src/tx_thread_stack_build.S +++ b/ports/risc-v32/gnu/src/tx_thread_stack_build.S @@ -54,12 +54,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */ -/* */ /**************************************************************************/ /* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) { */ diff --git a/ports/risc-v32/gnu/src/tx_thread_system_return.S b/ports/risc-v32/gnu/src/tx_thread_system_return.S index 110f6ac1..4090e7b2 100644 --- a/ports/risc-v32/gnu/src/tx_thread_system_return.S +++ b/ports/risc-v32/gnu/src/tx_thread_system_return.S @@ -54,12 +54,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */ -/* */ /**************************************************************************/ /* VOID _tx_thread_system_return(VOID) { */ diff --git a/ports/risc-v32/gnu/src/tx_timer_interrupt.S b/ports/risc-v32/gnu/src/tx_timer_interrupt.S index 92b5c6b6..d3b2fc60 100644 --- a/ports/risc-v32/gnu/src/tx_timer_interrupt.S +++ b/ports/risc-v32/gnu/src/tx_timer_interrupt.S @@ -56,12 +56,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-20-2023 Akif Ejaz Initial Version 6.2.1 */ -/* */ /**************************************************************************/ /* VOID _tx_timer_interrupt(VOID) { */ diff --git a/ports/risc-v32/iar/example_build/sample_threadx.c b/ports/risc-v32/iar/example_build/sample_threadx.c index 525dcc5b..3c6d2587 100644 --- a/ports/risc-v32/iar/example_build/sample_threadx.c +++ b/ports/risc-v32/iar/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete description of this demonstration. */ @@ -69,7 +69,7 @@ void thread_6_and_7_entry(ULONG thread_input); int main() { - + /* Please refer to Chapter 6 of the ThreadX User Guide for a complete description of this demonstration. */ @@ -100,41 +100,41 @@ CHAR *pointer; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -142,23 +142,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -261,11 +261,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -324,7 +324,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -377,7 +377,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/risc-v32/iar/inc/tx_port.h b/ports/risc-v32/iar/inc/tx_port.h index d971ccb2..d6232b95 100644 --- a/ports/risc-v32/iar/inc/tx_port.h +++ b/ports/risc-v32/iar/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,38 +21,29 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ /* tx_port.h RISC-V32/IAR */ /* 6.1.6 */ /* */ -/* AUTHOR */ -/* */ +/* AUTHOR */ +/* */ /* William E. Lamie, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* */ -/**************************************************************************/ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/**************************************************************************/ #ifndef TX_PORT_H #define TX_PORT_H @@ -68,7 +60,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -78,7 +70,7 @@ /* Define compiler library include files. */ -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -114,19 +106,19 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX RISC-V port. */ +/* Define various constants for the ThreadX RISC-V port. */ #define TX_INT_DISABLE 0x00000000 /* Disable interrupts value */ #define TX_INT_ENABLE 0x00000008 /* Enable interrupt value */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -155,7 +147,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -167,13 +159,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -187,11 +179,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -226,9 +218,9 @@ typedef unsigned short USHORT; #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -264,8 +256,8 @@ unsigned int _tx_thread_interrupt_control(uns /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX RISC-V32/IAR Version G6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RISC-V32/IAR Version G6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/risc-v32/iar/readme_threadx.txt b/ports/risc-v32/iar/readme_threadx.txt index 99504275..9e117dd3 100644 --- a/ports/risc-v32/iar/readme_threadx.txt +++ b/ports/risc-v32/iar/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for RISC-V + Microsoft's Azure RTOS ThreadX for RISC-V 32-bit Mode @@ -7,10 +7,10 @@ 1. Building the ThreadX run-time Library Building the ThreadX library is easy. First, open the Azure RTOS workspace -azure_rtos.eww. Next, make the tx.ewp project the "active project" in the -IAR Embedded Workbench and select the "Make" button. You should observe -assembly and compilation of a series of ThreadX source files. This -results in the ThreadX run-time library file tx.a, which is needed by +azure_rtos.eww. Next, make the tx.ewp project the "active project" in the +IAR Embedded Workbench and select the "Make" button. You should observe +assembly and compilation of a series of ThreadX source files. This +results in the ThreadX run-time library file tx.a, which is needed by the application. @@ -20,45 +20,45 @@ The ThreadX demonstration is designed to execute under the IAR Windows-based RISC-V simulator. Building the demonstration is easy; simply make the sample_threadx.ewp project -the "active project" in the IAR Embedded Workbench and select the +the "active project" in the IAR Embedded Workbench and select the "Make" button. -You should observe the compilation of sample_threadx.c (which is the demonstration +You should observe the compilation of sample_threadx.c (which is the demonstration application) and linking with tx.a. The resulting file sample_threadx.out is a binary file that can be downloaded and executed on IAR's RISC-V simulator. 3. System Initialization -The entry point in ThreadX for the RISC-V using IAR tools is at label -__iar_program_start. This is defined within the IAR compiler's startup code. In -addition, this is where all static and global preset C variable +The entry point in ThreadX for the RISC-V using IAR tools is at label +__iar_program_start. This is defined within the IAR compiler's startup code. In +addition, this is where all static and global preset C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, and a periodic timer interrupt source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. The _tx_initialize_low_level function inside of tx_initialize_low_level.s -also determines the first available address for use by the application, which -is supplied as the sole input parameter to your application definition function, -tx_application_define. To accomplish this, a section is created in -tx_initialize_low_level.s called FREE_MEM, which must be located after all +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all other RAM sections in memory. 4. Register Usage and Stack Frames -The IAR RISC-V compiler assumes that registers t0-t6 and a0-a7 are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The IAR RISC-V compiler assumes that registers t0-t6 and a0-a7 are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -76,8 +76,8 @@ associated thread control block TX_THREAD. 0x20 s4 (x20) s4 (x20) 0x24 s3 (x19) s3 (x19) 0x28 s2 (x18) s2 (x18) - 0x2C s1 (x9) s1 (x9) - 0x30 s0 (x8) s0 (x8) + 0x2C s1 (x9) s1 (x9) + 0x30 s0 (x8) s0 (x8) 0x34 t6 (x31) ra (x1) 0x38 t5 (x30) mstatus 0x3C t4 (x29) fs0 @@ -85,18 +85,18 @@ associated thread control block TX_THREAD. 0x44 t2 (x7) fs2 0x48 t1 (x6) fs3 0x4C t0 (x5) fs4 - 0x50 a7 (x17) fs5 - 0x54 a6 (x16) fs6 - 0x58 a5 (x15) fs7 - 0x5C a4 (x14) fs8 - 0x60 a3 (x13) fs9 - 0x64 a2 (x12) fs10 - 0x68 a1 (x11) fs11 + 0x50 a7 (x17) fs5 + 0x54 a6 (x16) fs6 + 0x58 a5 (x15) fs7 + 0x5C a4 (x14) fs8 + 0x60 a3 (x13) fs9 + 0x64 a2 (x12) fs10 + 0x68 a1 (x11) fs11 0x6C a0 (x10) fcsr 0x70 ra (x1) 0x74 reserved 0x78 mepc -#if __iar_riscv_base_isa == rv32e +#if __iar_riscv_base_isa == rv32e 0x7C ft0 0x80 ft1 0x84 ft2 @@ -135,22 +135,22 @@ associated thread control block TX_THREAD. 5. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make ThreadX run faster, you can change the project -options to disable debug information and enable the desired -compiler optimizations. +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make ThreadX run faster, you can change the project +options to disable debug information and enable the desired +compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined before tx_api.h is included. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. 6. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for RISC-V -targets.The ThreadX general exception handler sample is defined as follows, +targets.The ThreadX general exception handler sample is defined as follows, where "*" represents the interrupt vector number: PUBLIC _sample_interrupt_handler @@ -163,7 +163,7 @@ __minterrupt_00000*: /* Before calling _tx_thread_context_save, we have to allocate an interrupt stack frame and save the current value of x1 (ra). */ -#if __iar_riscv_base_isa == rv32e +#if __iar_riscv_base_isa == rv32e addi sp, sp, -260 ; Allocate space for all registers - with floating point enabled #else addi sp, sp, -128 ; Allocate space for all registers - without floating point enabled @@ -197,9 +197,9 @@ Some additional conditions: midway block MVECTOR }; } -6.1 Sample Timer ISR +6.1 Sample Timer ISR -The following sample timer ISR using vector 7 is defined in tx_initialize_low_level.s such that timer +The following sample timer ISR using vector 7 is defined in tx_initialize_low_level.s such that timer functionality is available under IAR simulation: PUBLIC _tx_timer_interrupt_handler @@ -212,7 +212,7 @@ __minterrupt_000007: /* Before calling _tx_thread_context_save, we have to allocate an interrupt stack frame and save the current value of x1 (ra). */ -#if __iar_riscv_base_isa == rv32e +#if __iar_riscv_base_isa == rv32e addi sp, sp, -260 ; Allocate space for all registers - with floating point enabled #else addi sp, sp, -128 ; Allocate space for all registers - without floating point enabled diff --git a/ports/risc-v32/iar/src/tx_initialize_low_level.s b/ports/risc-v32/iar/src/tx_initialize_low_level.s index af4caffc..28d81b04 100644 --- a/ports/risc-v32/iar/src/tx_initialize_low_level.s +++ b/ports/risc-v32/iar/src/tx_initialize_low_level.s @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Initialize */ /** */ @@ -29,63 +30,56 @@ #include "tx_initialize.h" #include "tx_thread.h" #include "tx_timer.h" */ - + EXTERN _tx_thread_system_stack_ptr EXTERN _tx_initialize_unused_memory EXTERN _tx_thread_context_save EXTERN _tx_thread_context_restore EXTERN _tx_timer_interrupt - + RSEG FREE_MEM:DATA PUBLIC __tx_free_memory_start __tx_free_memory_start: - DS32 4 + DS32 4 SECTION `.text`:CODE:REORDER:NOROOT(2) CODE -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ /* _tx_initialize_low_level RISC-V32/IAR */ /* 6.1 */ -/* AUTHOR */ -/* */ -/* William E. Lamie, Microsoft Corporation */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ /* Tom van Leeuwen, Technolution B.V. */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function is responsible for any low-level processor */ -/* initialization, including setting up interrupt vectors, setting */ -/* up a periodic timer interrupt source, saving the system stack */ -/* pointer for use in ISR processing later, and finding the first */ -/* available RAM memory address for tx_application_define. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ -/**************************************************************************/ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/**************************************************************************/ /* VOID _tx_initialize_low_level(VOID) { */ PUBLIC _tx_initialize_low_level @@ -95,7 +89,7 @@ _tx_initialize_low_level: la t0, __tx_free_memory_start ; Pickup first free address sw t0, _tx_initialize_unused_memory, t1 ; Save unused memory address - ret + ret /* Define the actual timer interrupt/exception handler. */ @@ -110,7 +104,7 @@ __minterrupt_000007: /* Before calling _tx_thread_context_save, we have to allocate an interrupt stack frame and save the current value of x1 (ra). */ -#if __iar_riscv_base_isa == rv32e +#if __iar_riscv_base_isa == rv32e addi sp, sp, -260 ; Allocate space for all registers - with floating point enabled #else addi sp, sp, -128 ; Allocate space for all registers - without floating point enabled @@ -126,4 +120,3 @@ __minterrupt_000007: END - \ No newline at end of file diff --git a/ports/risc-v32/iar/src/tx_thread_context_restore.s b/ports/risc-v32/iar/src/tx_thread_context_restore.s index 53763f64..56ab986b 100644 --- a/ports/risc-v32/iar/src/tx_thread_context_restore.s +++ b/ports/risc-v32/iar/src/tx_thread_context_restore.s @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -28,7 +29,7 @@ /* #include "tx_api.h" #include "tx_thread.h" #include "tx_timer.h" */ - + EXTERN _tx_thread_execute_ptr EXTERN _tx_thread_current_ptr EXTERN _tx_timer_time_slice @@ -42,47 +43,40 @@ SECTION `.text`:CODE:REORDER:NOROOT(2) CODE -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ /* _tx_thread_context_restore RISC-V32/IAR */ /* 6.1 */ -/* AUTHOR */ -/* */ -/* William E. Lamie, Microsoft Corporation */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ /* Tom van Leeuwen, Technolution B.V. */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function restores the interrupt context if it is processing a */ -/* nested interrupt. If not, it returns to the interrupt thread if no */ -/* preemption is necessary. Otherwise, if preemption is necessary or */ -/* if no thread was running, the function returns to the scheduler. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_thread_schedule Thread scheduling routine */ -/* */ -/* CALLED BY */ -/* */ -/* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ -/**************************************************************************/ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/**************************************************************************/ /* VOID _tx_thread_context_restore(VOID) { */ PUBLIC _tx_thread_context_restore @@ -108,10 +102,10 @@ _tx_thread_context_restore: /* Interrupts are nested. */ - /* Just recover the saved registers and return to the point of + /* Just recover the saved registers and return to the point of interrupt. */ - -#if __iar_riscv_base_isa == rv32e + +#if __iar_riscv_base_isa == rv32e /* Recover floating point registers. */ @@ -136,7 +130,7 @@ _tx_thread_context_restore: flw f30,0xF4(sp) ; Recover ft10 flw f31,0xF8(sp) ; Recover ft11 lw t0, 0xFC(sp) ; Recover fcsr - csrw fcsr, t0 ; + csrw fcsr, t0 ; #endif /* Recover standard registers. */ @@ -169,7 +163,7 @@ _tx_thread_context_restore: lw x30, 0x38(sp) ; Recover t5 lw x31, 0x34(sp) ; Recover t6 -#if __iar_riscv_base_isa == rv32e +#if __iar_riscv_base_isa == rv32e addi sp, sp, 260 ; Recover stack frame - with floating point enabled #else addi sp, sp, 128 ; Recover stack frame - without floating point enabled @@ -201,7 +195,7 @@ _tx_thread_no_preempt_restore: lw sp, 8(t1) ; Switch back to thread's stack -#if __iar_riscv_base_isa == rv32e +#if __iar_riscv_base_isa == rv32e /* Recover floating point registers. */ @@ -226,7 +220,7 @@ _tx_thread_no_preempt_restore: flw f30,0xF4(sp) ; Recover ft10 flw f31,0xF8(sp) ; Recover ft11 lw t0, 0xFC(sp) ; Recover fcsr - csrw fcsr, t0 ; + csrw fcsr, t0 ; #endif /* Recover the saved context and return to the point of interrupt. */ @@ -258,7 +252,7 @@ _tx_thread_no_preempt_restore: lw x30, 0x38(sp) ; Recover t5 lw x31, 0x34(sp) ; Recover t6 -#if __iar_riscv_base_isa == rv32e +#if __iar_riscv_base_isa == rv32e addi sp, sp, 260 ; Recover stack frame - with floating point enabled #else addi sp, sp, 128 ; Recover stack frame - without floating point enabled @@ -276,10 +270,10 @@ _tx_thread_preempt_restore: ori t3, x0, 1 ; Build interrupt stack type sw t3, 0(t0) ; Store stack type -#if __iar_riscv_base_isa == rv32e +#if __iar_riscv_base_isa == rv32e /* Store floating point preserved registers. */ - + fsw f8, 0x9C(t0) ; Store fs0 fsw f9, 0xA0(t0) ; Store fs1 fsw f18, 0xC4(t0) ; Store fs2 diff --git a/ports/risc-v32/iar/src/tx_thread_context_save.s b/ports/risc-v32/iar/src/tx_thread_context_save.s index c4b0f273..00b971ef 100644 --- a/ports/risc-v32/iar/src/tx_thread_context_save.s +++ b/ports/risc-v32/iar/src/tx_thread_context_save.s @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -39,46 +40,39 @@ SECTION `.text`:CODE:REORDER:NOROOT(2) CODE -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ /* _tx_thread_context_save RISC-V32/IAR */ /* 6.1 */ -/* AUTHOR */ -/* */ -/* William E. Lamie, Microsoft Corporation */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ /* Tom van Leeuwen, Technolution B.V. */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function saves the context of an executing thread in the */ -/* beginning of interrupt processing. The function also ensures that */ -/* the system stack is used upon return to the calling ISR. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ -/**************************************************************************/ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/**************************************************************************/ /* VOID _tx_thread_context_save(VOID) { */ PUBLIC _tx_thread_context_save @@ -122,10 +116,10 @@ _tx_thread_context_save: csrr t0, mepc ; Load exception program counter sw t0, 0x78(sp) ; Save it on the stack -#if __iar_riscv_base_isa == rv32e +#if __iar_riscv_base_isa == rv32e /* Save floating point scratch registers. */ - + fsw f0, 0x7C(sp) ; Store ft0 fsw f1, 0x80(sp) ; Store ft1 fsw f2, 0x84(sp) ; Store ft2 @@ -154,7 +148,7 @@ _tx_thread_context_save: call _tx_execution_isr_enter ; Call the ISR execution enter function #endif - ret ; Return to calling ISR + ret ; Return to calling ISR _tx_thread_not_nested_save: /* } */ @@ -190,7 +184,7 @@ _tx_thread_not_nested_save: csrr t0, mepc ; Load exception program counter sw t0, 0x78(sp) ; Save it on the stack -#if __iar_riscv_base_isa == rv32e +#if __iar_riscv_base_isa == rv32e /* Save floating point scratch registers. */ @@ -251,7 +245,7 @@ _tx_thread_idle_system_save: /* } } */ -#if __iar_riscv_base_isa == rv32e +#if __iar_riscv_base_isa == rv32e addi sp, sp, 260 ; Recover stack frame - with floating point enabled #else addi sp, sp, 128 ; Recover the reserved stack space @@ -259,4 +253,3 @@ _tx_thread_idle_system_save: ret ; Return to calling ISR END - \ No newline at end of file diff --git a/ports/risc-v32/iar/src/tx_thread_interrupt_control.s b/ports/risc-v32/iar/src/tx_thread_interrupt_control.s index 08e87a9b..30a4bdda 100644 --- a/ports/risc-v32/iar/src/tx_thread_interrupt_control.s +++ b/ports/risc-v32/iar/src/tx_thread_interrupt_control.s @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -32,45 +33,38 @@ SET_SR_MASK DEFINE 0xFFFFFFF0 SECTION `.text`:CODE:REORDER:NOROOT(2) CODE -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ /* _tx_thread_interrupt_control RISC-V32/IAR */ /* 6.1 */ -/* AUTHOR */ -/* */ -/* William E. Lamie, Microsoft Corporation */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ /* Tom van Leeuwen, Technolution B.V. */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function is responsible for changing the interrupt lockout */ -/* posture of the system. */ -/* */ -/* INPUT */ -/* */ -/* new_posture New interrupt lockout posture */ -/* */ -/* OUTPUT */ -/* */ -/* old_posture Old interrupt lockout posture */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ -/**************************************************************************/ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/**************************************************************************/ /* UINT _tx_thread_interrupt_control(UINT new_posture) { */ PUBLIC _tx_thread_interrupt_control @@ -81,7 +75,7 @@ _tx_thread_interrupt_control: mv t1, t0 ; Save original mstatus for return /* Apply the new interrupt posture. */ - + li t2, SET_SR_MASK ; Build set SR mask and t0, t0, t2 ; Isolate interrupt lockout bits or t0, t0, a0 ; Put new lockout bits in @@ -90,4 +84,3 @@ _tx_thread_interrupt_control: ret /* } */ END - \ No newline at end of file diff --git a/ports/risc-v32/iar/src/tx_thread_schedule.s b/ports/risc-v32/iar/src/tx_thread_schedule.s index 6ebccef3..d8ce66ce 100644 --- a/ports/risc-v32/iar/src/tx_thread_schedule.s +++ b/ports/risc-v32/iar/src/tx_thread_schedule.s @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -40,48 +41,41 @@ SECTION `.text`:CODE:REORDER:NOROOT(2) CODE -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ /* _tx_thread_schedule RISC-V32/IAR */ /* 6.1 */ -/* AUTHOR */ -/* */ -/* William E. Lamie, Microsoft Corporation */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ /* Tom van Leeuwen, Technolution B.V. */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function waits for a thread control block pointer to appear in */ -/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -/* in the variable, the corresponding thread is resumed. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ /* None */ -/* */ -/* CALLS */ -/* */ +/* */ +/* OUTPUT */ +/* */ /* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_initialize_kernel_enter ThreadX entry function */ -/* _tx_thread_system_return Return to system from thread */ -/* _tx_thread_context_restore Restore thread's context */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ -/**************************************************************************/ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/**************************************************************************/ /* VOID _tx_thread_schedule(VOID) { */ PUBLIC _tx_thread_schedule @@ -101,7 +95,7 @@ _tx_thread_schedule_loop: /* } while(_tx_thread_execute_ptr == TX_NULL); */ - + /* Yes! We have a thread to execute. Lockout interrupts and transfer control to it. */ csrci mstatus, 0x08 ; Lockout interrupts @@ -144,7 +138,7 @@ _tx_thread_schedule_loop: /* Determine if floating point registers need to be recovered. */ -#if __iar_riscv_base_isa == rv32e +#if __iar_riscv_base_isa == rv32e flw f0, 0x7C(sp) ; Recover ft0 flw f1, 0x80(sp) ; Recover ft1 flw f2, 0x84(sp) ; Recover ft2 @@ -178,7 +172,7 @@ _tx_thread_schedule_loop: flw f30,0xF4(sp) ; Recover ft10 flw f31,0xF8(sp) ; Recover ft11 lw t0, 0xFC(sp) ; Recover fcsr - csrw fcsr, t0 ; + csrw fcsr, t0 ; #endif /* Recover standard registers. */ @@ -217,8 +211,8 @@ _tx_thread_schedule_loop: lw x30, 0x38(sp) ; Recover t5 lw x31, 0x34(sp) ; Recover t6 -#if __iar_riscv_base_isa == rv32e - addi sp, sp, 260 ; Recover stack frame - with floating point registers +#if __iar_riscv_base_isa == rv32e + addi sp, sp, 260 ; Recover stack frame - with floating point registers #else addi sp, sp, 128 ; Recover stack frame - without floating point registers #endif @@ -226,7 +220,7 @@ _tx_thread_schedule_loop: _tx_thread_synch_return: -#if __iar_riscv_base_isa == rv32e +#if __iar_riscv_base_isa == rv32e flw f8, 0x3C(sp) ; Recover fs0 flw f9, 0x40(sp) ; Recover fs1 flw f18,0x44(sp) ; Recover fs2 @@ -240,7 +234,7 @@ _tx_thread_synch_return: flw f26,0x64(sp) ; Recover fs10 flw f27,0x68(sp) ; Recover fs11 lw t0, 0x6C(sp) ; Recover fcsr - csrw fcsr, t0 ; + csrw fcsr, t0 ; #endif /* Recover standard preserved registers. */ @@ -261,7 +255,7 @@ _tx_thread_synch_return: lw x27, 0x04(sp) ; Recover s11 lw t0, 0x38(sp) ; Recover mstatus csrw mstatus, t0 ; Store mstatus, enables interrupt -#if __iar_riscv_base_isa == rv32e +#if __iar_riscv_base_isa == rv32e addi sp, sp, 116 ; Recover stack frame #else addi sp, sp, 64 ; Recover stack frame @@ -270,4 +264,4 @@ _tx_thread_synch_return: /* } */ END - + diff --git a/ports/risc-v32/iar/src/tx_thread_stack_build.s b/ports/risc-v32/iar/src/tx_thread_stack_build.s index 09b6ef09..eb850146 100644 --- a/ports/risc-v32/iar/src/tx_thread_stack_build.s +++ b/ports/risc-v32/iar/src/tx_thread_stack_build.s @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -30,56 +31,49 @@ SECTION `.text`:CODE:REORDER:NOROOT(2) CODE -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ /* _tx_thread_stack_build RISC-V32/IAR */ /* 6.1 */ -/* AUTHOR */ -/* */ -/* William E. Lamie, Microsoft Corporation */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ /* Tom van Leeuwen, Technolution B.V. */ -/* */ -/* DESCRIPTION */ -/* */ +/* */ +/* DESCRIPTION */ +/* */ /* This function builds a stack frame on the supplied thread's stack. */ /* The stack frame results in a fake interrupt return to the supplied */ -/* function pointer. */ -/* */ -/* INPUT */ -/* */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ /* thread_ptr Pointer to thread control blk */ /* function_ptr Pointer to return function */ -/* */ -/* OUTPUT */ -/* */ +/* */ +/* OUTPUT */ +/* */ /* None */ -/* */ -/* CALLS */ -/* */ +/* */ +/* CALLS */ +/* */ /* None */ -/* */ -/* CALLED BY */ -/* */ +/* */ +/* CALLED BY */ +/* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ -/**************************************************************************/ +/**************************************************************************/ /* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) { */ PUBLIC _tx_thread_stack_build _tx_thread_stack_build: - + /* Build a fake interrupt frame. The form of the fake interrupt stack on the RISC-V RV32 should look like the following after it is built: - + Stack Top: 1 (00) Interrupt stack frame type x27 (04) Initial s11 x26 (08) Initial s10 @@ -153,7 +147,7 @@ If floating point support: /* Actually build the stack frame. */ -#if __iar_riscv_base_isa == rv32e +#if __iar_riscv_base_isa == rv32e addi t0, t0, -260 #else addi t0, t0, -128 ; Allocate space for the stack frame @@ -189,7 +183,7 @@ If floating point support: sw x0, 108(t0) ; Initial a0 sw x0, 112(t0) ; Initial ra sw a1, 120(t0) ; Initial mepc -#if __iar_riscv_base_isa == rv32e +#if __iar_riscv_base_isa == rv32e sw x0, 124(t0) ; Inital ft0 sw x0, 128(t0) ; Inital ft1 sw x0, 132(t0) ; Inital ft2 @@ -236,4 +230,4 @@ If floating point support: ret ; control block and return /* } */ END - + diff --git a/ports/risc-v32/iar/src/tx_thread_system_return.s b/ports/risc-v32/iar/src/tx_thread_system_return.s index 22fcc4ef..377656f8 100644 --- a/ports/risc-v32/iar/src/tx_thread_system_return.s +++ b/ports/risc-v32/iar/src/tx_thread_system_return.s @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -39,47 +40,40 @@ SECTION `.text`:CODE:REORDER:NOROOT(2) CODE -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ /* _tx_thread_system_return RISC-V32/IAR */ /* 6.1 */ -/* AUTHOR */ -/* */ -/* William E. Lamie, Microsoft Corporation */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ /* Tom van Leeuwen, Technolution B.V. */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function is target processor specific. It is used to transfer */ -/* control from a thread back to the system. Only a minimal context */ -/* is saved since the compiler assumes temp registers are going to get */ -/* slicked by a function call anyway. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_thread_schedule Thread scheduling loop */ -/* */ -/* CALLED BY */ -/* */ -/* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ -/**************************************************************************/ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the system. Only a minimal context */ +/* is saved since the compiler assumes temp registers are going to get */ +/* slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/**************************************************************************/ /* VOID _tx_thread_system_return(VOID) { */ PUBLIC _tx_thread_system_return @@ -87,16 +81,16 @@ _tx_thread_system_return: /* Save minimal context on the stack. */ -#if __iar_riscv_base_isa == rv32e +#if __iar_riscv_base_isa == rv32e addi sp, sp, -116 ; Allocate space on the stack - with floating point enabled #else addi sp, sp, -64 ; Allocate space on the stack - without floating point enabled #endif -#if __iar_riscv_base_isa == rv32e +#if __iar_riscv_base_isa == rv32e /* Store floating point preserved registers. */ - + fsw f8, 0x3C(sp) ; Store fs0 fsw f9, 0x40(sp) ; Store fs1 fsw f18, 0x44(sp) ; Store fs2 @@ -133,14 +127,14 @@ _tx_thread_system_return: /* Lockout interrupts. - will be enabled in _tx_thread_schedule */ - - csrci mstatus, 0xF - + + csrci mstatus, 0xF + #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY call _tx_execution_thread_exit ; Call the thread execution exit function #endif - + la t0, _tx_thread_current_ptr ; Pickup address of pointer lw t1, 0(t0) ; Pickup current thread pointer la t2,_tx_thread_system_stack_ptr ; Pickup stack pointer address @@ -180,4 +174,3 @@ _tx_thread_dont_save_ts: /* } */ END - \ No newline at end of file diff --git a/ports/risc-v32/iar/src/tx_timer_interrupt.s b/ports/risc-v32/iar/src/tx_timer_interrupt.s index 2a4c36f8..bad9a366 100644 --- a/ports/risc-v32/iar/src/tx_timer_interrupt.s +++ b/ports/risc-v32/iar/src/tx_timer_interrupt.s @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Timer */ /** */ @@ -41,49 +42,42 @@ SECTION `.mtext`:CODE:REORDER:NOROOT(2) CODE -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ /* _tx_timer_interrupt RISC-V32/IAR */ /* 6.1 */ -/* AUTHOR */ -/* */ -/* William E. Lamie, Microsoft Corporation */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ /* Tom van Leeuwen, Technolution B.V. */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function processes the hardware timer interrupt. This */ -/* processing includes incrementing the system clock and checking for */ -/* time slice and/or timer expiration. If either is found, the */ -/* interrupt context save/restore functions are called along with the */ -/* expiration functions. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_timer_expiration_process Timer expiration processing */ -/* _tx_thread_time_slice Time slice interrupted thread */ -/* */ -/* CALLED BY */ -/* */ -/* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ -/**************************************************************************/ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/**************************************************************************/ /* VOID _tx_timer_interrupt(VOID) { */ PUBLIC _tx_timer_interrupt @@ -230,4 +224,3 @@ _tx_timer_nothing_expired: /* } */ END - \ No newline at end of file diff --git a/ports/risc-v64/gnu/example_build/qemu_virt/board.c b/ports/risc-v64/gnu/example_build/qemu_virt/board.c index 29652bee..60a61163 100644 --- a/ports/risc-v64/gnu/example_build/qemu_virt/board.c +++ b/ports/risc-v64/gnu/example_build/qemu_virt/board.c @@ -12,7 +12,7 @@ void *memset(const void *des, int c,size_t n) int i; for(i=0;i tx_thread_stack_ptr = R1; +; thread_ptr -> tx_thread_stack_ptr = R1; MOV.L R3, 8[R1] ; Store initial SP in thread control block RTS - + ;} .END diff --git a/ports/rxv1/ccrx/src/tx_thread_system_return.src b/ports/rxv1/ccrx/src/tx_thread_system_return.src index c1363639..989235a7 100644 --- a/ports/rxv1/ccrx/src/tx_thread_system_return.src +++ b/ports/rxv1/ccrx/src/tx_thread_system_return.src @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; diff --git a/ports/rxv1/ccrx/src/tx_timer_interrupt.src b/ports/rxv1/ccrx/src/tx_timer_interrupt.src index a386e50a..b76329ee 100644 --- a/ports/rxv1/ccrx/src/tx_timer_interrupt.src +++ b/ports/rxv1/ccrx/src/tx_timer_interrupt.src @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -95,8 +95,8 @@ ;/* 10-15-2021 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.9 */ ;/* 01-31-2022 William E. Lamie Modified comment(s), and */ -;/* added missing thread */ -;/* preemption logic, */ +;/* added missing thread */ +;/* preemption logic, */ ;/* resulting in version 6.1.10 */ ;/* 04-25-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.11 */ @@ -164,7 +164,7 @@ __tx_timer_no_time_slice: MOV.L [R2+], R1 ; Pickup timer list entry, _tx_timer_current_ptr++ CMP #0, R1 ; Is timer pointer NULL? BEQ __tx_timer_no_timer ; Yes, no timer has expired - + ; ; /* Set expiration flag. */ ; _tx_timer_expired = TX_TRUE; @@ -182,7 +182,7 @@ __tx_timer_no_timer: ; /* No timer expired, increment the timer pointer. */ ; _tx_timer_current_ptr++; ; -; /* R2 already contains __tx_timer_current_ptr++ */ +; /* R2 already contains __tx_timer_current_ptr++ */ ; ; /* Check for wrap-around. */ ; if (_tx_timer_current_ptr == _tx_timer_list_end) @@ -201,9 +201,9 @@ __tx_timer_no_timer: ; } ; __tx_timer_skip_wrap: - MOV.L #__tx_timer_current_ptr,R1 + MOV.L #__tx_timer_current_ptr,R1 MOV.L R2, [R1] ; Store in updated pointer in _tx_timer_current_ptr - + __tx_timer_done: ; ; /* See if anything has expired. */ @@ -237,14 +237,14 @@ __tx_timer_dont_activate: ; /* Did time slice expire? */ ; if (_tx_timer_expired_time_slice) ; { -; +; MOV.L #__tx_timer_expired_time_slice, R1 ; Pickup time-slice expired flag addr MOV.L [R1], R1 ; Pickup actual flag CMP #0,R1 ; Has time-slice expired? BEQ __tx_timer_not_ts_expiration ; No, skip time-slice expiration ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BSR __tx_thread_time_slice ; Call time-slice processing diff --git a/ports/rxv1/gnu/inc/tx_port.h b/ports/rxv1/gnu/inc/tx_port.h index 8321ae85..bc1f415c 100644 --- a/ports/rxv1/gnu/inc/tx_port.h +++ b/ports/rxv1/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,20 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 08-02-2021 William E. Lamie Initial Version 6.1.8 */ -/* 10-15-2021 William E. Lamie Modified comment(s), */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 William E. Lamie Modified comment(s), and */ -/* added missing interrupt */ -/* control defines, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comment(s), */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -69,13 +56,13 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" #endif -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -119,8 +106,8 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -145,7 +132,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -157,13 +144,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -177,11 +164,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -189,8 +176,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -216,9 +203,9 @@ typedef unsigned short USHORT; #define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -269,8 +256,8 @@ static void _tx_thread_system_return_inline(void) /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX RXv1/GNURX Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv1/GNURX Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv1/gnu/readme_threadx.txt b/ports/rxv1/gnu/readme_threadx.txt index d1b74f6c..f3ae6a16 100644 --- a/ports/rxv1/gnu/readme_threadx.txt +++ b/ports/rxv1/gnu/readme_threadx.txt @@ -18,40 +18,40 @@ for the RXv1. 3. System Initialization -The system entry point using the GNU tools is at the label _PowerON_Reset. +The system entry point using the GNU tools is at the label _PowerON_Reset. -The vector area is setup in the file tx_initialize_low_level.S. This file is also -responsible for setting up various system data structures, interrupt vectors, and -the periodic timer interrupt. This file is also an ideal place to add additional hardware +The vector area is setup in the file tx_initialize_low_level.S. This file is also +responsible for setting up various system data structures, interrupt vectors, and +the periodic timer interrupt. This file is also an ideal place to add additional hardware initialization code. -The ThreadX demonstration for the RXv1 utilizes CMT0 as a periodic timer interrupt -source. The CMT0 interrupt is typically setup for 10ms periodic interrupts and the -interrupt priority level is set to level 5 with the symbol CMT_RX_CFG_IPR in -r_cmt_rx_config.h of Renesas CMT timer module(r_cmt_rx). You may change any of the timer +The ThreadX demonstration for the RXv1 utilizes CMT0 as a periodic timer interrupt +source. The CMT0 interrupt is typically setup for 10ms periodic interrupts and the +interrupt priority level is set to level 5 with the symbol CMT_RX_CFG_IPR in +r_cmt_rx_config.h of Renesas CMT timer module(r_cmt_rx). You may change any of the timer parameters as needed. Increasing the timer interrupt frequency increases the overhead of the timer handling code on the system. -In addition, _tx_initialize_low_level determines the first available address for use -by the application, which is supplied as the sole input parameter to your application -definition function, tx_application_define. The first available memory is determined +In addition, _tx_initialize_low_level determines the first available address for use +by the application, which is supplied as the sole input parameter to your application +definition function, tx_application_define. The first available memory is determined by the location of the '_end' label the is defined in the linker script. -'_end' should reference the first memory AFTER all other RAM +'_end' should reference the first memory AFTER all other RAM sections in your linker control file. 4. Context Switch, Register Usage and Stack Frames The RXv1 port for ThreadX uses the first software interrupt, SWINT, i.e., interrupt #27, -to perform context switch with the interrupt priority level 1. This ISR is thus reserved -when using ThreadX and the SWINT should not be manipulated in any way by the application. -The port will setup the interrupt within _tx_initialize_low_level and the compiler will -automatically install the necessary interrupt vector. As such no additional initialization +to perform context switch with the interrupt priority level 1. This ISR is thus reserved +when using ThreadX and the SWINT should not be manipulated in any way by the application. +The port will setup the interrupt within _tx_initialize_low_level and the compiler will +automatically install the necessary interrupt vector. As such no additional initialization is necessary by the application. The following defines the saved context stack frame used by the ThreadX port. The -state of the CPU registers at the time of a context switch is saved on the running -thread's stack The top of the suspended thread's stack is pointed to by +state of the CPU registers at the time of a context switch is saved on the running +thread's stack The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Offset Stack Frame @@ -74,23 +74,23 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. 0x44 R2 0x48 PC - return address 0x4C PSW - + Note: By default GNURX does not save the state of the accumulator register ACC0 when entering an ISR. This means that if the ISR uses any of the DSP instructions the content of the accumulator could be corrupted. Saving and restoring of the accumulator can be enabled by adding the -msave-acc-in-interrupts command line option. - + 5. Improving Performance -The distribution version of ThreadX is built without any compiler optimizations. This -makes it easy to debug because you can trace or set breakpoints inside of ThreadX itself. -Of course, this costs some performance. To make ThreadX run faster, you can change the -ThreadX Library project to disable debug information and enable the desired optimizations. +The distribution version of ThreadX is built without any compiler optimizations. This +makes it easy to debug because you can trace or set breakpoints inside of ThreadX itself. +Of course, this costs some performance. To make ThreadX run faster, you can change the +ThreadX Library project to disable debug information and enable the desired optimizations. -In addition, you can eliminate the ThreadX basic API error checking by compiling your -application code with the symbol TX_DISABLE_ERROR_CHECKING defined before tx_api.h -is included. +In addition, you can eliminate the ThreadX basic API error checking by compiling your +application code with the symbol TX_DISABLE_ERROR_CHECKING defined before tx_api.h +is included. 6. Timer Processing @@ -102,18 +102,18 @@ a Renesas Fit CMT periodic timer module (r_cmt_rx) is used as the timer source. 7. Interrupt Handling -Interrupt handling is unaffected by the ThreadX port as such user interrupts can be +Interrupt handling is unaffected by the ThreadX port as such user interrupts can be written according to the toolchain's documentation. It is recommended not to use interrupt priority 1 as this is the priority of the context switch interrupt. However using interrupt -priority 1 won't cause any negative side effects but doing so may slightly reduce +priority 1 won't cause any negative side effects but doing so may slightly reduce performance. Please refer to the toolchain documentation for additional details on how to define interrupt service routines. 8. Execution Profiling -The RX port adds support for the Execution Profiling Kit (EPK). The EPK consists -of the files tx_execution_profile.c and tx_execution_profile.h. See the documentation +The RX port adds support for the Execution Profiling Kit (EPK). The EPK consists +of the files tx_execution_profile.c and tx_execution_profile.h. See the documentation of the EPK for generic usage details. To add the EPK to your RXv1 release make the following modifications: @@ -132,7 +132,7 @@ typedef unsigned long long EXECUTION_TIME; typedef unsigned long EXECUTION_TIME; #define TX_EXECUTION_MAX_TIME_SOURCE 0xFFFF #endif - + /* Define basic constants for the execution profile kit. */ #define TX_EXECUTION_TIME_SOURCE (EXECUTION_TIME) *((USHORT *) 0x8800A) @@ -155,9 +155,9 @@ information associated with this specific port of ThreadX: tx_timer_interrupt.s Added missing thread preemption logic 10-15-2021 Release 6.1.9 changes: - tx_thread_context_restore.s Removed unnecessary stack type placement + tx_thread_context_restore.s Removed unnecessary stack type placement tx_thread_schedule.s Removed unnecessary stack type checking - tx_thread_stack_build.s Removed unnecessary stack type placement + tx_thread_stack_build.s Removed unnecessary stack type placement 08-02-2021 Initial ThreadX release for the RXv1 using GNURX tools, version 6.1.8 diff --git a/ports/rxv1/gnu/src/tx_initialize_low_level.S b/ports/rxv1/gnu/src/tx_initialize_low_level.S index 7fda9938..71c13da0 100644 --- a/ports/rxv1/gnu/src/tx_initialize_low_level.S +++ b/ports/rxv1/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -57,18 +57,6 @@ ;/* */ ;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 08-02-2021 William E. Lamie Initial Version 6.1.8 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ .global __tx_initialize_low_level __tx_initialize_low_level: diff --git a/ports/rxv1/gnu/src/tx_thread_context_restore.S b/ports/rxv1/gnu/src/tx_thread_context_restore.S index f4f54afc..838f8c2b 100644 --- a/ports/rxv1/gnu/src/tx_thread_context_restore.S +++ b/ports/rxv1/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -73,20 +73,6 @@ ;/* */ ;/* ISRs Interrupt Service Routines */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 08-02-2021 William E. Lamie Initial Version 6.1.8 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* removed unnecessary stack */ -;/* type placement, */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) ;{ diff --git a/ports/rxv1/gnu/src/tx_thread_context_save.S b/ports/rxv1/gnu/src/tx_thread_context_save.S index 6d74b81a..228c4991 100644 --- a/ports/rxv1/gnu/src/tx_thread_context_save.S +++ b/ports/rxv1/gnu/src/tx_thread_context_save.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -56,18 +56,6 @@ ;/* */ ;/* ISRs */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 08-02-2021 William E. Lamie Initial Version 6.1.8 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) ;{ diff --git a/ports/rxv1/gnu/src/tx_thread_interrupt_control.S b/ports/rxv1/gnu/src/tx_thread_interrupt_control.S index 73cd1f27..c41c5d82 100644 --- a/ports/rxv1/gnu/src/tx_thread_interrupt_control.S +++ b/ports/rxv1/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -51,18 +51,6 @@ ;/* */ ;/* Application Code */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 08-02-2021 William E. Lamie Initial Version 6.1.8 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) ;{ diff --git a/ports/rxv1/gnu/src/tx_thread_schedule.S b/ports/rxv1/gnu/src/tx_thread_schedule.S index b3f16809..e2261c1a 100644 --- a/ports/rxv1/gnu/src/tx_thread_schedule.S +++ b/ports/rxv1/gnu/src/tx_thread_schedule.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -64,21 +64,6 @@ ;/* _tx_thread_system_return Return to system from thread */ ;/* _tx_thread_context_restore Restore thread's context */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 08-02-2021 William E. Lamie Initial Version 6.1.8 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* removed unnecessary stack */ -;/* type checking, */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), and */ -;/* added low power support, */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) ;{ @@ -96,7 +81,7 @@ __tx_thread_schedule_loop: MOV.L [R1],R2 ; Pickup next thread to execute CMP #0,R2 ; Is it NULL? BNE __tx_thread_thread_ready ; Not NULL, schedule the thread - ; Idle system - no thread is ready + ; Idle system - no thread is ready #if (TX_LOW_POWER == 1) MOV.L #__tx_thread_preempt_disable, R1 ; Load prempt disable flag. MOV.L [R1], R2 @@ -125,7 +110,7 @@ __tx_thread_thread_ready: ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Note that interrupts are locked out at this point. */ ; ; /* Setup the current thread pointer. */ diff --git a/ports/rxv1/gnu/src/tx_thread_stack_build.S b/ports/rxv1/gnu/src/tx_thread_stack_build.S index 278d5814..66c2f8e7 100644 --- a/ports/rxv1/gnu/src/tx_thread_stack_build.S +++ b/ports/rxv1/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -53,20 +53,6 @@ ;/* */ ;/* _tx_thread_create Create thread service */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 08-02-2021 William E. Lamie Initial Version 6.1.8 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* removed unnecessary stack */ -;/* type placement, */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) ;{ diff --git a/ports/rxv1/gnu/src/tx_thread_system_return.S b/ports/rxv1/gnu/src/tx_thread_system_return.S index a9e3df99..e40f624f 100644 --- a/ports/rxv1/gnu/src/tx_thread_system_return.S +++ b/ports/rxv1/gnu/src/tx_thread_system_return.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -57,19 +57,6 @@ ;/* */ ;/* ThreadX components */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 08-02-2021 William E. Lamie Initial Version 6.1.8 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* removed unused code, */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) ;{ diff --git a/ports/rxv1/gnu/src/tx_timer_interrupt.S b/ports/rxv1/gnu/src/tx_timer_interrupt.S index 29ed1a7a..e5ff3c60 100644 --- a/ports/rxv1/gnu/src/tx_timer_interrupt.S +++ b/ports/rxv1/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -73,20 +73,6 @@ ;/* */ ;/* interrupt vector */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 08-02-2021 William E. Lamie Initial Version 6.1.8 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), and */ -;/* added missing thread */ -;/* preemption logic, */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) ;{ diff --git a/ports/rxv1/iar/inc/tx_port.h b/ports/rxv1/iar/inc/tx_port.h index f052bbb7..1010e464 100644 --- a/ports/rxv1/iar/inc/tx_port.h +++ b/ports/rxv1/iar/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,21 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 08-02-2021 William E. Lamie Initial Version 6.1.8 */ -/* 10-15-2021 William E. Lamie Modified comment(s), */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 William E. Lamie Modified comment(s), removed */ -/* system state macro, and */ -/* added missing interrupt */ -/* control defines, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comment(s), */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -70,13 +56,13 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" #endif -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -120,8 +106,8 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -146,7 +132,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -158,13 +144,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -178,11 +164,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -190,8 +176,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -217,9 +203,9 @@ typedef unsigned short USHORT; #define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -270,8 +256,8 @@ static void _tx_thread_system_return_inline(void) /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX RXv1/IAR Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv1/IAR Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv1/iar/readme_threadx.txt b/ports/rxv1/iar/readme_threadx.txt index a9d8137a..f6207109 100644 --- a/ports/rxv1/iar/readme_threadx.txt +++ b/ports/rxv1/iar/readme_threadx.txt @@ -17,38 +17,38 @@ for the RXv1. 3. System Initialization -The system entry point using the IAR tools is at the label __iar_program_start. +The system entry point using the IAR tools is at the label __iar_program_start. -The vector area is setup in the file tx_initialize_low_level.s. This file is also -responsible for setting up various system data structures, interrupt vectors, and -the periodic timer interrupt. This file is also an ideal place add hardware +The vector area is setup in the file tx_initialize_low_level.s. This file is also +responsible for setting up various system data structures, interrupt vectors, and +the periodic timer interrupt. This file is also an ideal place add hardware initialization code. -The ThreadX demonstration for the RXv1 utilizes CMT0 as a periodic timer interrupt -source. The CMT0 interrupt is typically setup for 10ms periodic interrupts and the -interrupt priority level is set to level 5 with the symbol CMT_RX_CFG_IPR in -r_cmt_rx_config.h of Renesas CMT timer module(r_cmt_rx). You may change any of the +The ThreadX demonstration for the RXv1 utilizes CMT0 as a periodic timer interrupt +source. The CMT0 interrupt is typically setup for 10ms periodic interrupts and the +interrupt priority level is set to level 5 with the symbol CMT_RX_CFG_IPR in +r_cmt_rx_config.h of Renesas CMT timer module(r_cmt_rx). You may change any of the timer parameters as needed. -In addition, _tx_initialize_low_level determines the first available address for use -by the application, which is supplied as the sole input parameter to your application -definition function, tx_application_define. The first available memory is determined -by the location of the FREEMEM section so it should be placed AFTER all other RAM +In addition, _tx_initialize_low_level determines the first available address for use +by the application, which is supplied as the sole input parameter to your application +definition function, tx_application_define. The first available memory is determined +by the location of the FREEMEM section so it should be placed AFTER all other RAM sections in your linker control file. 4. Context Switch, Register Usage and Stack Frames The RXv1 port for ThreadX uses the first software interrupt, SWINT, i.e., interrupt #27, -to perform context switch with the interrupt priority level 1. This ISR is thus reserved -when using ThreadX and the SWINT should not be manipulated in any way by the application. -The port will setup the interrupt within _tx_initialize_low_level and the compiler will -automatically install the necessary interrupt vector. As such no additional initialization +to perform context switch with the interrupt priority level 1. This ISR is thus reserved +when using ThreadX and the SWINT should not be manipulated in any way by the application. +The port will setup the interrupt within _tx_initialize_low_level and the compiler will +automatically install the necessary interrupt vector. As such no additional initialization is necessary by the application. The following defines the saved context stack frame used by the ThreadX port. The -state of the CPU registers at the time of a context switch is saved on the running -thread's stack The top of the suspended thread's stack is pointed to by +state of the CPU registers at the time of a context switch is saved on the running +thread's stack The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Offset Stack Frame @@ -71,23 +71,23 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. 0x44 R2 0x48 PC - return address 0x4C PSW - + Note: By default IAR does not save the state of the accumulator register ACC0 when entering an ISR. This means that if the ISR uses any of the DSP instructions the content of the accumulator could be corrupted. Saving and restoring of the accumulator can be enabled by adding the --save_acc command line option. - + 5. Improving Performance -The distribution version of ThreadX is built without any compiler optimizations. This -makes it easy to debug because you can trace or set breakpoints inside of ThreadX itself. -Of course, this costs some performance. To make ThreadX run faster, you can change the -ThreadX Library project to disable debug information and enable the desired optimizations. +The distribution version of ThreadX is built without any compiler optimizations. This +makes it easy to debug because you can trace or set breakpoints inside of ThreadX itself. +Of course, this costs some performance. To make ThreadX run faster, you can change the +ThreadX Library project to disable debug information and enable the desired optimizations. -In addition, you can eliminate the ThreadX basic API error checking by compiling your -application code with the symbol TX_DISABLE_ERROR_CHECKING defined before tx_api.h -is included. +In addition, you can eliminate the ThreadX basic API error checking by compiling your +application code with the symbol TX_DISABLE_ERROR_CHECKING defined before tx_api.h +is included. 6. Timer Processing @@ -99,18 +99,18 @@ a Renesas Fit CMT periodic timer module (r_cmt_rx) is used as the timer source. 7. Interrupt Handling -Interrupt handling is unaffected by the ThreadX port as such user interrupts can be +Interrupt handling is unaffected by the ThreadX port as such user interrupts can be written according to the toolchain's documentation. It is recommended not to use interrupt priority 1 as this is the priority of the context switch interrupt. However using interrupt -priority 1 won't cause any negative side effects but doing so may slightly reduce +priority 1 won't cause any negative side effects but doing so may slightly reduce performance. Please refer to the toolchain documentation for additional details on how to define interrupt service routines. 8. Execution Profiling -The RX port adds support for the Execution Profiling Kit (EPK). The EPK consists -of the files tx_execution_profile.c and tx_execution_profile.h. See the documentation +The RX port adds support for the Execution Profiling Kit (EPK). The EPK consists +of the files tx_execution_profile.c and tx_execution_profile.h. See the documentation of the EPK for generic usage details. To add the EPK to your RXv1 release make the following modifications: @@ -129,7 +129,7 @@ typedef unsigned long long EXECUTION_TIME; typedef unsigned long EXECUTION_TIME; #define TX_EXECUTION_MAX_TIME_SOURCE 0xFFFF #endif - + /* Define basic constants for the execution profile kit. */ #define TX_EXECUTION_TIME_SOURCE (EXECUTION_TIME) *((USHORT *) 0x8800A) @@ -148,14 +148,14 @@ information associated with this specific port of ThreadX: tx_thread_schedule.s Added low power support 01-31-2022 Release 6.1.10 changes: - tx_port.h Removed system state macro, and added + tx_port.h Removed system state macro, and added missing interrupt control defines tx_timer_interrupt.s Added missing thread preemption logic 10-15-2021 Release 6.1.9 changes: - tx_thread_context_restore.s Removed unnecessary stack type placement + tx_thread_context_restore.s Removed unnecessary stack type placement tx_thread_schedule.s Removed unnecessary stack type checking - tx_thread_stack_build.s Removed unnecessary stack type placement + tx_thread_stack_build.s Removed unnecessary stack type placement 08-02-2021 Initial ThreadX release for the RXv1using IAR tools, version 6.1.8 diff --git a/ports/rxv1/iar/src/tx_initialize_low_level.s b/ports/rxv1/iar/src/tx_initialize_low_level.s index 081f529c..edff1d8f 100644 --- a/ports/rxv1/iar/src/tx_initialize_low_level.s +++ b/ports/rxv1/iar/src/tx_initialize_low_level.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -59,18 +59,6 @@ ;/* */ ;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 08-02-2021 William E. Lamie Initial Version 6.1.8 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ public __tx_initialize_low_level @@ -80,7 +68,7 @@ __tx_initialize_low_level: ; _tx_initialize_unused_memory = (VOID_PTR) &free_mem_start; ; MOV.L #__tx_free_memory_start, R1 ; Pickup unused memory address - MOV.L #__tx_initialize_unused_memory,R2 + MOV.L #__tx_initialize_unused_memory,R2 MOV.L R1,[R2] ; Save first free memory address ; /* Set priority of SWINT to 1. */ diff --git a/ports/rxv1/iar/src/tx_thread_context_restore.s b/ports/rxv1/iar/src/tx_thread_context_restore.s index 4abefcc9..6b3c17c8 100644 --- a/ports/rxv1/iar/src/tx_thread_context_restore.s +++ b/ports/rxv1/iar/src/tx_thread_context_restore.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -61,20 +61,6 @@ ;/* */ ;/* ISRs Interrupt Service Routines */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 08-02-2021 William E. Lamie Initial Version 6.1.8 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* removed unnecessary stack */ -;/* type placement, */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ public __tx_thread_context_restore @@ -92,7 +78,7 @@ __tx_thread_context_restore: MOV.L [R1], R2 SUB #1, R2 MOV.L R2,[R1] - BEQ __tx_thread_not_nested_restore + BEQ __tx_thread_not_nested_restore ; ; /* Interrupts are nested. */ @@ -113,17 +99,17 @@ __tx_thread_not_nested_restore: ; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { - + MOV.L #__tx_thread_current_ptr, R1 ; Pickup current thread ptr address MOV.L [R1], R2 CMP #0, R2 - BEQ __tx_thread_idle_system_restore - + BEQ __tx_thread_idle_system_restore + MOV.L #__tx_thread_preempt_disable, R3 ; Pick up preempt disable flag MOV.L [R3], R3 CMP #0, R3 BNE __tx_thread_no_preempt_restore ; If pre-empt disable flag set, we simply return to the original point of interrupt regardless - + MOV.L #__tx_thread_execute_ptr, R3 ; (_tx_thread_current_ptr != _tx_thread_execute_ptr) CMP [R3], R2 BNE __tx_thread_preempt_restore ; Jump to pre-empt restoring @@ -163,11 +149,11 @@ __tx_thread_dont_save_ts: SETPSW U ; User stack PUSHM R6-R13 - + MVFACHI R5 MVFACMI R6 PUSHM R5-R6 - + ; ; /* Clear the current task pointer. */ ; _tx_thread_current_ptr = TX_NULL; diff --git a/ports/rxv1/iar/src/tx_thread_context_save.s b/ports/rxv1/iar/src/tx_thread_context_save.s index b79ba6f4..4e613330 100644 --- a/ports/rxv1/iar/src/tx_thread_context_save.s +++ b/ports/rxv1/iar/src/tx_thread_context_save.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -55,18 +55,6 @@ ;/* */ ;/* ISRs */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 08-02-2021 William E. Lamie Initial Version 6.1.8 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) ;{ @@ -94,7 +82,7 @@ __tx_thread_context_save: BEQ __tx_thread_not_nested_save ; ; /* Nested interrupt condition. */ -; +; ADD #1, r2 ; _tx_thread_system_state++ MOV.L r2, [r1] @@ -119,7 +107,7 @@ __tx_thread_not_nested_save: MOV.L #__tx_thread_current_ptr, R2 ; Pickup current thread pointer MOV.L [R2], R2 - CMP #0,R2 ; Is it NULL? + CMP #0,R2 ; Is it NULL? BEQ __tx_thread_idle_system_save ; Yes, idle system is running - idle restore ; ; /* Move stack frame over to the current threads stack. */ @@ -139,7 +127,7 @@ __tx_thread_not_nested_save: MOV.L R3, [-R1] ; Save R3 on thread stack MOV.L R15, [-R1] ; Save R15 on thread stack MOV.L R14, [-R1] ; Save R14 on thread stack - + POP R2 ; Pick up return address from interrupt stack ADD #16, R0, R0 ; Correct interrupt stack pointer back to the bottom MVTC R1, USP ; Set user/thread stack pointer @@ -158,5 +146,5 @@ __tx_thread_idle_system_save: JMP R1 ; Return to caller ; ; } -;} +;} END diff --git a/ports/rxv1/iar/src/tx_thread_interrupt_control.s b/ports/rxv1/iar/src/tx_thread_interrupt_control.s index 3c510df7..bd945bfc 100644 --- a/ports/rxv1/iar/src/tx_thread_interrupt_control.s +++ b/ports/rxv1/iar/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -51,18 +51,6 @@ ;/* */ ;/* Application Code */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 08-02-2021 William E. Lamie Initial Version 6.1.8 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) ;{ @@ -71,20 +59,20 @@ __tx_thread_interrupt_control: ; ; /* Pickup current interrupt lockout posture. */ ; - + MVFC PSW, R2 ; Save PSW to R2 MOV.L R2, R3 ; Make a copy of PSW in r3 - + ; ; /* Apply the new interrupt posture. */ ; - + BTST #16, R1 ; Test I bit of PSW of "new posture" BMNE #16, R2 ; Conditionally set I bit of intermediate posture - + MVTC R2, PSW ; Save intermediate posture to PSW - - MOV.L R3,R1 ; Get original SR + + MOV.L R3,R1 ; Get original SR RTS ; Return to caller ;} END diff --git a/ports/rxv1/iar/src/tx_thread_schedule.s b/ports/rxv1/iar/src/tx_thread_schedule.s index 2602d46b..86fa3785 100644 --- a/ports/rxv1/iar/src/tx_thread_schedule.s +++ b/ports/rxv1/iar/src/tx_thread_schedule.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -64,21 +64,6 @@ ;/* _tx_thread_system_return Return to system from thread */ ;/* _tx_thread_context_restore Restore thread's context */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 08-02-2021 William E. Lamie Initial Version 6.1.8 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* removed unnecessary stack */ -;/* type checking, */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), and */ -;/* added low power support, */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) ;{ @@ -97,7 +82,7 @@ __tx_thread_schedule_loop: MOV.L [R1],R2 ; Pickup next thread to execute CMP #0,R2 ; Is it NULL? BNE __tx_thread_thread_ready ; Not NULL, schedule the thread - ; Idle system - no thread is ready + ; Idle system - no thread is ready #if (TX_LOW_POWER == 1) MOV.L #__tx_thread_preempt_disable, R1 ; Load prempt disable flag. MOV.L [R1], R2 @@ -126,7 +111,7 @@ __tx_thread_thread_ready: ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Note that interrupts are locked out at this point. */ ; ; /* Setup the current thread pointer. */ @@ -164,9 +149,9 @@ __tx_thread_thread_ready: POPM R6-R13 ; Recover interrupt stack frame POPM R14-R15 POPM R3-R5 - POPM R1-R2 + POPM R1-R2 RTE ; Return to point of interrupt, this restores PC and PSW - + ; ;} diff --git a/ports/rxv1/iar/src/tx_thread_stack_build.s b/ports/rxv1/iar/src/tx_thread_stack_build.s index 30809756..91694f64 100644 --- a/ports/rxv1/iar/src/tx_thread_stack_build.s +++ b/ports/rxv1/iar/src/tx_thread_stack_build.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -55,30 +55,16 @@ ;/* */ ;/* _tx_thread_create Create thread service */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 08-02-2021 William E. Lamie Initial Version 6.1.8 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* removed unnecessary stack */ -;/* type placement, */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ public __tx_thread_stack_build __tx_thread_stack_build: ; -; +; ; /* Build an interrupt frame. The form of the fake interrupt stack ; on the Renesas RX should look like the following after it is built: -; +; ; Stack Top: ACC0 ; R6 ; R7 @@ -131,11 +117,11 @@ __tx_thread_stack_build: MOV.L R4,[-R3] ; /* Setup stack pointer. */ -; thread_ptr -> tx_thread_stack_ptr = R1; +; thread_ptr -> tx_thread_stack_ptr = R1; MOV.L R3, 8[R1] ; Store initial SP in thread control block RTS - + ;} END diff --git a/ports/rxv1/iar/src/tx_thread_system_return.s b/ports/rxv1/iar/src/tx_thread_system_return.s index b524fb7b..1d8f8020 100644 --- a/ports/rxv1/iar/src/tx_thread_system_return.s +++ b/ports/rxv1/iar/src/tx_thread_system_return.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -20,7 +20,7 @@ ;/**************************************************************************/ section .text:CODE:ROOT - + ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ @@ -54,18 +54,6 @@ ;/* */ ;/* ThreadX components */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 08-02-2021 William E. Lamie Initial Version 6.1.8 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ public __tx_thread_system_return diff --git a/ports/rxv1/iar/src/tx_timer_interrupt.s b/ports/rxv1/iar/src/tx_timer_interrupt.s index ea330250..04917936 100644 --- a/ports/rxv1/iar/src/tx_timer_interrupt.s +++ b/ports/rxv1/iar/src/tx_timer_interrupt.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -73,20 +73,6 @@ SWI0 EQU 0x872E0 ;/* */ ;/* interrupt vector */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 08-02-2021 William E. Lamie Initial Version 6.1.8 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), and */ -;/* added missing thread */ -;/* preemption logic, */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ public __tx_timer_interrupt @@ -149,14 +135,14 @@ __tx_timer_no_time_slice: MOV.L [R2+], R1 ; pickup timer list entry, _tx_timer_current_ptr++ CMP #0, R1 ; Is timer pointer NULL? BEQ __tx_timer_no_timer ; Yes, no timer has expired - + ; ; /* Set expiration flag. */ ; _tx_timer_expired = TX_TRUE; ; MOV.L #__tx_timer_expired,R2 ; Build address of expired flag MOV.L #1, R1 ; Build expired value - MOV.L R1, [R2] + MOV.L R1, [R2] BRA __tx_timer_done ; Finished with timer processing ; ; } @@ -167,7 +153,7 @@ __tx_timer_no_timer: ; /* No timer expired, increment the timer pointer. */ ; _tx_timer_current_ptr++; ; -; /* R2 already contains __tx_timer_current_ptr++ */ +; /* R2 already contains __tx_timer_current_ptr++ */ ; ; /* Check for wrap-around. */ ; if (_tx_timer_current_ptr == _tx_timer_list_end) @@ -186,9 +172,9 @@ __tx_timer_no_timer: ; } ; __tx_timer_skip_wrap: - MOV.L #__tx_timer_current_ptr,R1 + MOV.L #__tx_timer_current_ptr,R1 MOV.L R2, [R1] ; Store in updated pointer in _tx_timer_current_ptr - + __tx_timer_done: ; ; /* See if anything has expired. */ @@ -222,14 +208,14 @@ __tx_timer_dont_activate: ; /* Did time slice expire? */ ; if (_tx_timer_expired_time_slice) ; { -; +; MOV.L #__tx_timer_expired_time_slice, R1 ; Pickup time-slice expired flag addr MOV.L [R1], R1 ; Pickup actual flag CMP #0,R1 ; Has time-slice expired? BEQ __tx_timer_not_ts_expiration ; No, skip time-slice expiration ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BSR __tx_thread_time_slice ; Call time-slice processing diff --git a/ports/rxv2/ccrx/CMakeLists.txt b/ports/rxv2/ccrx/CMakeLists.txt index fabadffe..f2269c51 100644 --- a/ports/rxv2/ccrx/CMakeLists.txt +++ b/ports/rxv2/ccrx/CMakeLists.txt @@ -2,7 +2,7 @@ target_sources(${PROJECT_NAME} PRIVATE # {{BEGIN_TARGET_SOURCES}} - ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.src + ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.src ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.src ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.src ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.src diff --git a/ports/rxv2/ccrx/inc/tx_port.h b/ports/rxv2/ccrx/inc/tx_port.h index f9ef4a91..95f578eb 100644 --- a/ports/rxv2/ccrx/inc/tx_port.h +++ b/ports/rxv2/ccrx/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,46 +21,29 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ /* tx_port.h RXv2/CCRX */ /* 6.1.11 */ /* */ -/* AUTHOR */ -/* */ -/* William E. Lamie, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -/* 06-02-2021 William E. Lamie Modified comments, */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 William E. Lamie Modified comment(s), */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 William E. Lamie Modified comment(s), removed */ -/* system state macro, and */ -/* added missing interrupt */ -/* control defines, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comment(s), */ -/* resulting in version 6.1.11 */ -/* */ -/**************************************************************************/ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/**************************************************************************/ #ifndef TX_PORT_H #define TX_PORT_H @@ -69,13 +53,13 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" #endif -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -119,8 +103,8 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif #ifndef TX_TRACE_TIME_SOURCE @@ -144,7 +128,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -156,13 +140,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -176,11 +160,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -188,8 +172,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -216,16 +200,16 @@ typedef unsigned short USHORT; #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ /* UINT _tx_thread_interrupt_control(UINT new_posture); */ -#pragma inline_asm _tx_thread_interrupt_disable +#pragma inline_asm _tx_thread_interrupt_disable static UINT _tx_thread_interrupt_disable(void){ MVFC PSW,R1 ; CLRPSW I ; @@ -275,8 +259,8 @@ static void _tx_thread_system_return_inline(void) /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX RXv2/CCRX Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv2/CCRX Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv2/ccrx/readme_threadx.txt b/ports/rxv2/ccrx/readme_threadx.txt index 2b6bd50c..e8cd3090 100644 --- a/ports/rxv2/ccrx/readme_threadx.txt +++ b/ports/rxv2/ccrx/readme_threadx.txt @@ -16,25 +16,25 @@ for the RXv2 3. System Initialization -The system entry point using Renesas tools is at the label _PowerON_Reset_PC. -Use the resetprg.c file that comes with your release. Most notable is that Threadx -applications run in supervisor mode and do not use user mode. Hence switching to +The system entry point using Renesas tools is at the label _PowerON_Reset_PC. +Use the resetprg.c file that comes with your release. Most notable is that Threadx +applications run in supervisor mode and do not use user mode. Hence switching to user mode has been commented out. The vector area is set up using either intprg.c or in the file tx_initialize_low_level.src. -The file tx_initialize_low_level.src is responsible for setting up various system data -structures, interrupt vectors, and a periodic timer. This is the ideal place add +The file tx_initialize_low_level.src is responsible for setting up various system data +structures, interrupt vectors, and a periodic timer. This is the ideal place add application specific hardware initialization code. -ThreadX utilizes CMT0 as a periodic timer interrupt source. The CMT0 interrupt is -typically setup for 10ms periodic interrupts and the interrupt priority level is set to +ThreadX utilizes CMT0 as a periodic timer interrupt source. The CMT0 interrupt is +typically setup for 10ms periodic interrupts and the interrupt priority level is set to level 5 with the symbol CMT_RX_CFG_IPR in r_cmt_rx_config.h of Renesas CMT timer module (r_cmt_rx). You may change any of the timer parameters to suit your needs. -In addition, _tx_initialize_low_level determines the first available address for use by -the application, which is supplied as the sole input parameter to your application -definition function, tx_application_define(). The mechanism is implemented by creating the -FREEMEM section, this section should be linked last in the RAM area. tx_initialize_low_level +In addition, _tx_initialize_low_level determines the first available address for use by +the application, which is supplied as the sole input parameter to your application +definition function, tx_application_define(). The mechanism is implemented by creating the +FREEMEM section, this section should be linked last in the RAM area. tx_initialize_low_level will pick up the starting label of this section and put it in the global variable: _tx_initialize_unused_memory @@ -42,15 +42,15 @@ _tx_initialize_unused_memory 4. Context Switch, Register Usage and Stack Frames The RXv2 port for ThreadX uses the first software interrupt, SWINT, i.e., interrupt #27, -to perform context switch with the interrupt priority level 1. This ISR is thus reserved -when using ThreadX and the SWINT should not be manipulated in any way by the application. -The port will setup the interrupt within _tx_initialize_low_level and the compiler will -automatically install the necessary interrupt vector. As such no additional initialization +to perform context switch with the interrupt priority level 1. This ISR is thus reserved +when using ThreadX and the SWINT should not be manipulated in any way by the application. +The port will setup the interrupt within _tx_initialize_low_level and the compiler will +automatically install the necessary interrupt vector. As such no additional initialization is necessary by the application. The following defines the saved context stack frame used by the ThreadX port. The -state of the CPU registers at the time of a context switch is saved on the running -thread's stack The top of the suspended thread's stack is pointed to by +state of the CPU registers at the time of a context switch is saved on the running +thread's stack The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Offset Interrupted Stack Frame @@ -76,24 +76,24 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. 0x48 R2 0x4C PC - return address 0x50 PSW - + Note: By default ccrx does not save the state of the accumulator registers ACC0 and ACC1 when entering an ISR. This means that if the ISR uses any of the DSP instructions the content of those registers could be corrupted. Saving and restoring of the acummulators can be enabled by adding the -save_acc command line option. - + 5. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make ThreadX run faster, you can change the ThreadX Library -project to disable debug information and enable the desired optimizations. +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make ThreadX run faster, you can change the ThreadX Library +project to disable debug information and enable the desired optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined before tx_api.h is included. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. 6. Timer Processing @@ -105,18 +105,18 @@ a Renesas Fit CMT periodic timer module (r_cmt_rx) is used as the timer source. 7. Interrupt Handling -Interrupt handling is unaffected by the ThreadX port as such user interrupts can be +Interrupt handling is unaffected by the ThreadX port as such user interrupts can be written according to the toolchain's documentation. It is recommended not to use interrupt priority 1 as this is the priority of the context switch interrupt. However using interrupt -priority 1 won't cause any negative side effects but doing so may slightly reduce +priority 1 won't cause any negative side effects but doing so may slightly reduce performance. Please refer to the toolchain documentation for additional details on how to define interrupt service routines. 8. Execution Profiling -The RX port adds support for the Execution Profiling Kit (EPK). The EPK consists -of the files tx_execution_profile.c and tx_execution_profile.h. See the documentation +The RX port adds support for the Execution Profiling Kit (EPK). The EPK consists +of the files tx_execution_profile.c and tx_execution_profile.h. See the documentation of the EPK for generic usage details. To add the EPK to your RXv2 release make the following modifications: @@ -135,7 +135,7 @@ typedef unsigned long long EXECUTION_TIME; typedef unsigned long EXECUTION_TIME; #define TX_EXECUTION_MAX_TIME_SOURCE 0xFFFF #endif - + /* Define basic constants for the execution profile kit. */ #define TX_EXECUTION_TIME_SOURCE (EXECUTION_TIME) *((USHORT *) 0x8800A) @@ -158,14 +158,14 @@ information associated with this specific port of ThreadX: tx_thread_schedule.src Added low power support 01-31-2022 Release 6.1.10 changes: - tx_port.h Removed system state macro, and added + tx_port.h Removed system state macro, and added missing interrupt control defines tx_timer_interrupt.src Added missing thread preemption logic 10-15-2021 Release 6.1.9 changes: - tx_thread_context_restore.src Removed unnecessary stack type placement + tx_thread_context_restore.src Removed unnecessary stack type placement tx_thread_schedule.src Removed unnecessary stack type checking - tx_thread_stack_build.src Removed unnecessary stack type placement + tx_thread_stack_build.src Removed unnecessary stack type placement 06-02-2021 Release 6.1.7 changes: readme_threadx.txt Updated instructions on how to use execution profile. diff --git a/ports/rxv2/ccrx/src/tx_initialize_low_level.src b/ports/rxv2/ccrx/src/tx_initialize_low_level.src index 84e9eacf..db5273b2 100644 --- a/ports/rxv2/ccrx/src/tx_initialize_low_level.src +++ b/ports/rxv2/ccrx/src/tx_initialize_low_level.src @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -26,46 +26,46 @@ IEN03 .EQU 87203H .SECTION P,CODE - + ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_initialize_low_level RXv2/CCRX */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ ;/* 10-15-2021 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.9 */ @@ -73,8 +73,8 @@ ;/* resulting in version 6.1.10 */ ;/* 04-25-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ .GLB __tx_initialize_low_level __tx_initialize_low_level: @@ -97,7 +97,7 @@ __tx_initialize_low_level: OR #(1 << 3), r2 MOV.B r2, [r1] - RTS + RTS .SECTION FREEMEM ,DATA, ALIGN=4 free_mem_start: diff --git a/ports/rxv2/ccrx/src/tx_thread_context_restore.src b/ports/rxv2/ccrx/src/tx_thread_context_restore.src index 641f5ab3..3594b613 100644 --- a/ports/rxv2/ccrx/src/tx_thread_context_restore.src +++ b/ports/rxv2/ccrx/src/tx_thread_context_restore.src @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,43 +39,43 @@ .GLB __tx_thread_preempt_disable ; .SECTION P,CODE -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_context_restore RXv2/CCRX */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ ;/* 10-15-2021 William E. Lamie Modified comment(s), and */ ;/* removed unnecessary stack */ @@ -85,8 +85,8 @@ ;/* resulting in version 6.1.10 */ ;/* 04-25-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) ;{ .GLB __tx_thread_context_restore @@ -104,7 +104,7 @@ __tx_thread_context_restore: MOV.L [R1], R2 SUB #1, R2 MOV.L R2,[R1] - BEQ __tx_thread_not_nested_restore + BEQ __tx_thread_not_nested_restore ; ; /* Interrupts are nested. */ @@ -126,17 +126,17 @@ __tx_thread_not_nested_restore: ; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { - + MOV.L #__tx_thread_current_ptr, R1 ; Pickup current thread ptr address MOV.L [R1], R2 CMP #0, R2 - BEQ __tx_thread_idle_system_restore - + BEQ __tx_thread_idle_system_restore + MOV.L #__tx_thread_preempt_disable, R3 ; Pick up preempt disable flag MOV.L [R3], R3 CMP #0, R3 BNE __tx_thread_no_preempt_restore ; If pre-empt disable flag set, we simply return to the original point of interrupt regardless - + MOV.L #__tx_thread_execute_ptr, R3 ; (_tx_thread_current_ptr != _tx_thread_execute_ptr) CMP [R3], R2 BNE __tx_thread_preempt_restore ; Jump to pre-empt restoring diff --git a/ports/rxv2/ccrx/src/tx_thread_context_save.src b/ports/rxv2/ccrx/src/tx_thread_context_save.src index 4f0fbeaf..65b95a0a 100644 --- a/ports/rxv2/ccrx/src/tx_thread_context_save.src +++ b/ports/rxv2/ccrx/src/tx_thread_context_save.src @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,42 +34,42 @@ .GLB __tx_thread_system_stack_ptr .SECTION P,CODE -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_context_save RXv2/CCRX */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ ;/* 10-15-2021 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.9 */ @@ -77,8 +77,8 @@ ;/* resulting in version 6.1.10 */ ;/* 04-25-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) ;{ .GLB __tx_thread_context_save @@ -104,7 +104,7 @@ __tx_thread_context_save: BEQ __tx_thread_not_nested_save ; ; /* Nested interrupt condition. */ -; +; ADD #1, r2 ; _tx_thread_system_state++ MOV.L r2, [r1] @@ -152,7 +152,7 @@ __tx_thread_not_nested_save: MOV.L R14, [-R1] ; Save R14 on thread stack MVFC FPSW, R3 MOV.L R3, [-R1] ; Save FPSW on thread stack - + POP R2 ; Pick up return address from interrupt stack ADD #16, R0, R0 ; Correct interrupt stack pointer back to the bottom MVTC R1, USP ; Set user/thread stack pointer diff --git a/ports/rxv2/ccrx/src/tx_thread_interrupt_control.src b/ports/rxv2/ccrx/src/tx_thread_interrupt_control.src index a8688a52..b11d2382 100644 --- a/ports/rxv2/ccrx/src/tx_thread_interrupt_control.src +++ b/ports/rxv2/ccrx/src/tx_thread_interrupt_control.src @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,41 +29,41 @@ ; ; .SECTION P,CODE -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_interrupt_control RXc2/CCRX */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ ;/* 10-15-2021 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.9 */ @@ -71,8 +71,8 @@ ;/* resulting in version 6.1.10 */ ;/* 04-25-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) ;{ @@ -81,20 +81,20 @@ __tx_thread_interrupt_control: ; ; /* Pickup current interrupt lockout posture. */ ; - + MVFC PSW, R2 ; Save PSW to R2 MOV.L R2, R3 ; Make a copy of PSW in r3 - + ; ; /* Apply the new interrupt posture. */ ; - + BTST #16, R1 ; Test I bit of PSW of "new posture" BMNE #16, R2 ; Conditionally set I bit of intermediate posture - + MVTC R2, PSW ; Save intermediate posture to PSW - - MOV.L R3,R1 ; Get original SR + + MOV.L R3,R1 ; Get original SR RTS ; Return to caller ;} .END diff --git a/ports/rxv2/ccrx/src/tx_thread_schedule.src b/ports/rxv2/ccrx/src/tx_thread_schedule.src index e148a51b..d994993e 100644 --- a/ports/rxv2/ccrx/src/tx_thread_schedule.src +++ b/ports/rxv2/ccrx/src/tx_thread_schedule.src @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -41,44 +41,44 @@ ; .SECTION P,CODE -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_schedule RXv2/CCRX */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLS */ -;/* */ +;/* */ +;/* OUTPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ ;/* 10-15-2021 William E. Lamie Modified comment(s), and */ ;/* removed unnecessary stack */ @@ -86,11 +86,11 @@ ;/* resulting in version 6.1.9 */ ;/* 01-31-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), and */ -;/* added low power support, */ -;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* 04-25-2022 William E. Lamie Modified comment(s), and */ +;/* added low power support, */ +;/* resulting in version 6.1.11 */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) ;{ .GLB __tx_thread_schedule @@ -107,7 +107,7 @@ __tx_thread_schedule_loop: MOV.L [R1],R2 ; Pickup next thread to execute CMP #0,R2 ; Is it NULL? BNE __tx_thread_thread_ready ; Not NULL, schedule the thread - ; Idle system - no thread is ready + ; Idle system - no thread is ready .IF TX_LOW_POWER==1 MOV.L #__tx_thread_preempt_disable, R1 ; Load prempt disable flag. MOV.L [R1], R2 @@ -136,7 +136,7 @@ __tx_thread_thread_ready: ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Note that interrupts are locked out at this point. */ ; ; /* Setup the current thread pointer. */ @@ -174,10 +174,10 @@ __tx_thread_thread_ready: MVTACGU R1, A1 POPM R6-R13 ; Recover interrupt stack frame - POPC FPSW + POPC FPSW POPM R14-R15 POPM R3-R5 - POPM R1-R2 + POPM R1-R2 RTE ; return to point of interrupt, this restores PC and PSW ; diff --git a/ports/rxv2/ccrx/src/tx_thread_stack_build.src b/ports/rxv2/ccrx/src/tx_thread_stack_build.src index 7e309c3d..e5d5e344 100644 --- a/ports/rxv2/ccrx/src/tx_thread_stack_build.src +++ b/ports/rxv2/ccrx/src/tx_thread_stack_build.src @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -30,43 +30,43 @@ ; ; .SECTION P,CODE -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_stack_build RXc2/CCRX */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ ;/* This function builds a stack frame on the supplied thread's stack. */ ;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ ;/* thread_ptr Pointer to thread control blk */ ;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ +;/* */ +;/* OUTPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLS */ -;/* */ +;/* */ +;/* CALLS */ +;/* */ ;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ +;/* */ +;/* CALLED BY */ +;/* */ ;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ ;/* 10-15-2021 William E. Lamie Modified comment(s), and */ ;/* removed unnecessary stack */ @@ -76,17 +76,17 @@ ;/* resulting in version 6.1.10 */ ;/* 04-25-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) ;{ .GLB __tx_thread_stack_build __tx_thread_stack_build: ; -; +; ; /* Build an interrupt frame. The form of the fake interrupt stack ; on the Renesas RX should look like the following after it is built: -; +; ; Stack Top: ACC0 ; ACC1 ; R6 @@ -149,10 +149,10 @@ __tx_thread_stack_build: MOV.L R4,[-R3] ; /* Setup stack pointer. */ -; thread_ptr -> tx_thread_stack_ptr = R1; +; thread_ptr -> tx_thread_stack_ptr = R1; MOV.L R3, 8[R1] ; Store initial SP in thread control block RTS - + ;} .END diff --git a/ports/rxv2/ccrx/src/tx_thread_system_return.src b/ports/rxv2/ccrx/src/tx_thread_system_return.src index 9e83585c..61cd5143 100644 --- a/ports/rxv2/ccrx/src/tx_thread_system_return.src +++ b/ports/rxv2/ccrx/src/tx_thread_system_return.src @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; diff --git a/ports/rxv2/ccrx/src/tx_timer_interrupt.src b/ports/rxv2/ccrx/src/tx_timer_interrupt.src index a1806c4a..498c45bf 100644 --- a/ports/rxv2/ccrx/src/tx_timer_interrupt.src +++ b/ports/rxv2/ccrx/src/tx_timer_interrupt.src @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -50,47 +50,47 @@ .GLB __tx_thread_current_ptr ; .SECTION P,CODE -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_timer_interrupt RXv2/CCRX */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_context_save Save interrupted context */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* _tx_thread_context_restore Restore interrupted context */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_context_save Save interrupted context */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* _tx_thread_context_restore Restore interrupted context */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ ;/* 10-15-2021 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.9 */ @@ -100,8 +100,8 @@ ;/* resulting in version 6.1.10 */ ;/* 04-25-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) ;{ .GLB __tx_timer_interrupt @@ -164,14 +164,14 @@ __tx_timer_no_time_slice: MOV.L [R2+], R1 ; Pickup timer list entry, _tx_timer_current_ptr++ CMP #0, R1 ; Is timer pointer NULL? BEQ __tx_timer_no_timer ; Yes, no timer has expired - + ; ; /* Set expiration flag. */ ; _tx_timer_expired = TX_TRUE; ; MOV.L #__tx_timer_expired,R2 ; Build address of expired flag MOV.L #1, R1 ; Build expired value - MOV.L R1, [R2] + MOV.L R1, [R2] BRA __tx_timer_done ; Finished with timer processing ; ; } @@ -182,7 +182,7 @@ __tx_timer_no_timer: ; /* No timer expired, increment the timer pointer. */ ; _tx_timer_current_ptr++; ; -; /* R2 already contains __tx_timer_current_ptr++ */ +; /* R2 already contains __tx_timer_current_ptr++ */ ; ; /* Check for wrap-around. */ ; if (_tx_timer_current_ptr == _tx_timer_list_end) @@ -201,9 +201,9 @@ __tx_timer_no_timer: ; } ; __tx_timer_skip_wrap: - MOV.L #__tx_timer_current_ptr,R1 + MOV.L #__tx_timer_current_ptr,R1 MOV.L R2, [R1] ; Store in updated pointer in _tx_timer_current_ptr - + __tx_timer_done: ; ; /* See if anything has expired. */ @@ -237,14 +237,14 @@ __tx_timer_dont_activate: ; /* Did time slice expire? */ ; if (_tx_timer_expired_time_slice) ; { -; +; MOV.L #__tx_timer_expired_time_slice, R1 ; Pickup time-slice expired flag addr MOV.L [R1], R1 ; Pickup actual flag CMP #0,R1 ; Has time-slice expired? BEQ __tx_timer_not_ts_expiration ; No, skip time-slice expiration ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BSR __tx_thread_time_slice ; Call time-slice processing diff --git a/ports/rxv2/gnu/inc/tx_port.h b/ports/rxv2/gnu/inc/tx_port.h index 73662111..74f36a4c 100644 --- a/ports/rxv2/gnu/inc/tx_port.h +++ b/ports/rxv2/gnu/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,45 +21,29 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ /* tx_port.h RXv2/GNURX */ /* 6.1.11 */ /* */ -/* AUTHOR */ -/* */ -/* William E. Lamie, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -/* 06-02-2021 William E. Lamie Modified comments, */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 William E. Lamie Modified comment(s), */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 William E. Lamie Modified comment(s), and */ -/* added missing interrupt */ -/* control defines, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comment(s), */ -/* resulting in version 6.1.11 */ -/* */ -/**************************************************************************/ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/**************************************************************************/ #ifndef TX_PORT_H #define TX_PORT_H @@ -71,13 +56,13 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" #endif -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -121,8 +106,8 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -147,7 +132,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -159,13 +144,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -179,11 +164,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -191,8 +176,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -218,9 +203,9 @@ typedef unsigned short USHORT; #define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -271,8 +256,8 @@ static void _tx_thread_system_return_inline(void) /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX RXv2/GNURX Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv2/GNURX Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv2/gnu/readme_threadx.txt b/ports/rxv2/gnu/readme_threadx.txt index c1ac9912..43d46e0a 100644 --- a/ports/rxv2/gnu/readme_threadx.txt +++ b/ports/rxv2/gnu/readme_threadx.txt @@ -18,40 +18,40 @@ for the RXv2. 3. System Initialization -The system entry point using the GNU tools is at the label _PowerON_Reset. +The system entry point using the GNU tools is at the label _PowerON_Reset. -The vector area is setup in the file tx_initialize_low_level.S. This file is also -responsible for setting up various system data structures, interrupt vectors, and -the periodic timer interrupt. This file is also an ideal place to add additional hardware +The vector area is setup in the file tx_initialize_low_level.S. This file is also +responsible for setting up various system data structures, interrupt vectors, and +the periodic timer interrupt. This file is also an ideal place to add additional hardware initialization code. -The ThreadX demonstration for the RXv2 utilizes CMT0 as a periodic timer interrupt -source. The CMT0 interrupt is typically setup for 10ms periodic interrupts and the -interrupt priority level is set to level 5 with the symbol CMT_RX_CFG_IPR in -r_cmt_rx_config.h of Renesas CMT timer module(r_cmt_rx). You may change any of the timer +The ThreadX demonstration for the RXv2 utilizes CMT0 as a periodic timer interrupt +source. The CMT0 interrupt is typically setup for 10ms periodic interrupts and the +interrupt priority level is set to level 5 with the symbol CMT_RX_CFG_IPR in +r_cmt_rx_config.h of Renesas CMT timer module(r_cmt_rx). You may change any of the timer parameters as needed. Increasing the timer interrupt frequency increases the overhead of the timer handling code on the system. -In addition, _tx_initialize_low_level determines the first available address for use -by the application, which is supplied as the sole input parameter to your application -definition function, tx_application_define. The first available memory is determined +In addition, _tx_initialize_low_level determines the first available address for use +by the application, which is supplied as the sole input parameter to your application +definition function, tx_application_define. The first available memory is determined by the location of the '_end' label the is defined in the linker script. -'_end' should reference the first memory AFTER all other RAM +'_end' should reference the first memory AFTER all other RAM sections in your linker control file. 4. Context Switch, Register Usage and Stack Frames The RXv2 port for ThreadX uses the first software interrupt, SWINT, i.e., interrupt #27, -to perform context switch with the interrupt priority level 1. This ISR is thus reserved -when using ThreadX and the SWINT should not be manipulated in any way by the application. -The port will setup the interrupt within _tx_initialize_low_level and the compiler will -automatically install the necessary interrupt vector. As such no additional initialization +to perform context switch with the interrupt priority level 1. This ISR is thus reserved +when using ThreadX and the SWINT should not be manipulated in any way by the application. +The port will setup the interrupt within _tx_initialize_low_level and the compiler will +automatically install the necessary interrupt vector. As such no additional initialization is necessary by the application. The following defines the saved context stack frame used by the ThreadX port. The -state of the CPU registers at the time of a context switch is saved on the running -thread's stack The top of the suspended thread's stack is pointed to by +state of the CPU registers at the time of a context switch is saved on the running +thread's stack The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Offset Interrupted Stack Frame @@ -77,23 +77,23 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. 0x48 R2 0x4C PC - return address 0x50 PSW - + Note: By default GNURX does not save the state of the accumulator registers ACC0 and ACC1 when entering an ISR. This means that if the ISR uses any of the DSP instructions the content of those registers could be corrupted. Saving and restoring of the acummulators can be enabled by adding the -msave-acc-in-interrupts command line option. - + 5. Improving Performance -The distribution version of ThreadX is built without any compiler optimizations. This -makes it easy to debug because you can trace or set breakpoints inside of ThreadX itself. -Of course, this costs some performance. To make ThreadX run faster, you can change the -ThreadX Library project to disable debug information and enable the desired optimizations. +The distribution version of ThreadX is built without any compiler optimizations. This +makes it easy to debug because you can trace or set breakpoints inside of ThreadX itself. +Of course, this costs some performance. To make ThreadX run faster, you can change the +ThreadX Library project to disable debug information and enable the desired optimizations. -In addition, you can eliminate the ThreadX basic API error checking by compiling your -application code with the symbol TX_DISABLE_ERROR_CHECKING defined before tx_api.h -is included. +In addition, you can eliminate the ThreadX basic API error checking by compiling your +application code with the symbol TX_DISABLE_ERROR_CHECKING defined before tx_api.h +is included. 6. Timer Processing @@ -105,18 +105,18 @@ a Renesas Fit CMT periodic timer module (r_cmt_rx) is used as the timer source. 7. Interrupt Handling -Interrupt handling is unaffected by the ThreadX port as such user interrupts can be +Interrupt handling is unaffected by the ThreadX port as such user interrupts can be written according to the toolchain's documentation. It is recommended not to use interrupt priority 1 as this is the priority of the context switch interrupt. However using interrupt -priority 1 won't cause any negative side effects but doing so may slightly reduce +priority 1 won't cause any negative side effects but doing so may slightly reduce performance. Please refer to the toolchain documentation for additional details on how to define interrupt service routines. 8. Execution Profiling -The RX port adds support for the Execution Profiling Kit (EPK). The EPK consists -of the files tx_execution_profile.c and tx_execution_profile.h. See the documentation +The RX port adds support for the Execution Profiling Kit (EPK). The EPK consists +of the files tx_execution_profile.c and tx_execution_profile.h. See the documentation of the EPK for generic usage details. To add the EPK to your RXv2 release make the following modifications: @@ -135,7 +135,7 @@ typedef unsigned long long EXECUTION_TIME; typedef unsigned long EXECUTION_TIME; #define TX_EXECUTION_MAX_TIME_SOURCE 0xFFFF #endif - + /* Define basic constants for the execution profile kit. */ #define TX_EXECUTION_TIME_SOURCE (EXECUTION_TIME) *((USHORT *) 0x8800A) @@ -158,9 +158,9 @@ information associated with this specific port of ThreadX: tx_timer_interrupt.s Added missing thread preemption logic 10-15-2021 Release 6.1.9 changes: - tx_thread_context_restore.s Removed unnecessary stack type placement + tx_thread_context_restore.s Removed unnecessary stack type placement tx_thread_schedule.s Removed unnecessary stack type checking - tx_thread_stack_build.s Removed unnecessary stack type placement + tx_thread_stack_build.s Removed unnecessary stack type placement 06-02-2021 Release 6.1.7 changes: tx_port.h Fix TX_RESTORE issue diff --git a/ports/rxv2/gnu/src/tx_initialize_low_level.S b/ports/rxv2/gnu/src/tx_initialize_low_level.S index 23454a75..bc0bce33 100644 --- a/ports/rxv2/gnu/src/tx_initialize_low_level.S +++ b/ports/rxv2/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -57,18 +57,6 @@ ;/* */ ;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ .global __tx_initialize_low_level __tx_initialize_low_level: diff --git a/ports/rxv2/gnu/src/tx_thread_context_restore.S b/ports/rxv2/gnu/src/tx_thread_context_restore.S index a34f9ccd..c3529c4d 100644 --- a/ports/rxv2/gnu/src/tx_thread_context_restore.S +++ b/ports/rxv2/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -73,20 +73,6 @@ ;/* */ ;/* ISRs Interrupt Service Routines */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* removed unnecessary stack */ -;/* type placement, */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) ;{ diff --git a/ports/rxv2/gnu/src/tx_thread_context_save.S b/ports/rxv2/gnu/src/tx_thread_context_save.S index 9740b6af..f08f2450 100644 --- a/ports/rxv2/gnu/src/tx_thread_context_save.S +++ b/ports/rxv2/gnu/src/tx_thread_context_save.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -66,18 +66,6 @@ ;/* */ ;/* ISRs */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) ;{ diff --git a/ports/rxv2/gnu/src/tx_thread_interrupt_control.S b/ports/rxv2/gnu/src/tx_thread_interrupt_control.S index 69859e11..1bcdf78d 100644 --- a/ports/rxv2/gnu/src/tx_thread_interrupt_control.S +++ b/ports/rxv2/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -60,18 +60,6 @@ ;/* */ ;/* Application Code */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) ;{ diff --git a/ports/rxv2/gnu/src/tx_thread_schedule.S b/ports/rxv2/gnu/src/tx_thread_schedule.S index c8a9abab..74b33411 100644 --- a/ports/rxv2/gnu/src/tx_thread_schedule.S +++ b/ports/rxv2/gnu/src/tx_thread_schedule.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -75,21 +75,6 @@ ;/* _tx_thread_system_return Return to system from thread */ ;/* _tx_thread_context_restore Restore thread's context */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* removed unnecessary stack */ -;/* type checking, */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), and */ -;/* added low power support, */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) ;{ @@ -107,7 +92,7 @@ __tx_thread_schedule_loop: MOV.L [R1],R2 ; Pickup next thread to execute CMP #0,R2 ; Is it NULL? BNE __tx_thread_thread_ready ; Not NULL, schedule the thread - ; Idle system - no thread is ready + ; Idle system - no thread is ready #if (TX_LOW_POWER == 1) MOV.L #__tx_thread_preempt_disable, R1 ; Load prempt disable flag. MOV.L [R1], R2 @@ -136,7 +121,7 @@ __tx_thread_thread_ready: ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Note that interrupts are locked out at this point. */ ; ; /* Setup the current thread pointer. */ diff --git a/ports/rxv2/gnu/src/tx_thread_stack_build.S b/ports/rxv2/gnu/src/tx_thread_stack_build.S index 57ddac62..ca3e38e6 100644 --- a/ports/rxv2/gnu/src/tx_thread_stack_build.S +++ b/ports/rxv2/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -63,20 +63,6 @@ ;/* */ ;/* _tx_thread_create Create thread service */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* removed unnecessary stack */ -;/* type placement, */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) ;{ diff --git a/ports/rxv2/gnu/src/tx_thread_system_return.S b/ports/rxv2/gnu/src/tx_thread_system_return.S index fc981a49..bfa80cfa 100644 --- a/ports/rxv2/gnu/src/tx_thread_system_return.S +++ b/ports/rxv2/gnu/src/tx_thread_system_return.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -57,19 +57,6 @@ ;/* */ ;/* ThreadX components */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* removed unused code, */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) ;{ diff --git a/ports/rxv2/gnu/src/tx_timer_interrupt.S b/ports/rxv2/gnu/src/tx_timer_interrupt.S index 0af2e2ca..95c62baf 100644 --- a/ports/rxv2/gnu/src/tx_timer_interrupt.S +++ b/ports/rxv2/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -86,20 +86,6 @@ ;/* */ ;/* interrupt vector */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), and */ -;/* added missing thread */ -;/* preemption logic, */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) ;{ diff --git a/ports/rxv2/iar/inc/tx_port.h b/ports/rxv2/iar/inc/tx_port.h index 709d4c0e..351c51d0 100644 --- a/ports/rxv2/iar/inc/tx_port.h +++ b/ports/rxv2/iar/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,46 +21,29 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ /* tx_port.h RXv2/IAR */ /* 6.1.11 */ /* */ -/* AUTHOR */ -/* */ -/* William E. Lamie, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -/* 06-02-2021 William E. Lamie Modified comments, */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 William E. Lamie Modified comment(s), */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 William E. Lamie Modified comment(s), removed */ -/* system state macro, and */ -/* added missing interrupt */ -/* control defines, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comment(s), */ -/* resulting in version 6.1.11 */ -/* */ -/**************************************************************************/ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/**************************************************************************/ #ifndef TX_PORT_H #define TX_PORT_H @@ -72,13 +56,13 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" #endif -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -122,8 +106,8 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -148,7 +132,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -160,13 +144,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -180,11 +164,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -192,8 +176,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -219,9 +203,9 @@ typedef unsigned short USHORT; #define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -271,8 +255,8 @@ static void _tx_thread_system_return_inline(void) /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX RXv2/IAR Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv2/IAR Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv2/iar/readme_threadx.txt b/ports/rxv2/iar/readme_threadx.txt index 5f09a2b3..d15e7c18 100644 --- a/ports/rxv2/iar/readme_threadx.txt +++ b/ports/rxv2/iar/readme_threadx.txt @@ -17,38 +17,38 @@ for the RXv2. 3. System Initialization -The system entry point using the IAR tools is at the label __iar_program_start. +The system entry point using the IAR tools is at the label __iar_program_start. -The vector area is setup in the file tx_initialize_low_level.s. This file is also -responsible for setting up various system data structures, interrupt vectors, and -the periodic timer interrupt. This file is also an ideal place add hardware +The vector area is setup in the file tx_initialize_low_level.s. This file is also +responsible for setting up various system data structures, interrupt vectors, and +the periodic timer interrupt. This file is also an ideal place add hardware initialization code. -The ThreadX demonstration for the RXv2 utilizes CMT0 as a periodic timer interrupt -source. The CMT0 interrupt is typically setup for 10ms periodic interrupts and the -interrupt priority level is set to level 5 with the symbol CMT_RX_CFG_IPR in -r_cmt_rx_config.h of Renesas CMT timer module(r_cmt_rx). You may change any of the +The ThreadX demonstration for the RXv2 utilizes CMT0 as a periodic timer interrupt +source. The CMT0 interrupt is typically setup for 10ms periodic interrupts and the +interrupt priority level is set to level 5 with the symbol CMT_RX_CFG_IPR in +r_cmt_rx_config.h of Renesas CMT timer module(r_cmt_rx). You may change any of the timer parameters as needed. -In addition, _tx_initialize_low_level determines the first available address for use -by the application, which is supplied as the sole input parameter to your application -definition function, tx_application_define. The first available memory is determined -by the location of the FREEMEM section so it should be placed AFTER all other RAM +In addition, _tx_initialize_low_level determines the first available address for use +by the application, which is supplied as the sole input parameter to your application +definition function, tx_application_define. The first available memory is determined +by the location of the FREEMEM section so it should be placed AFTER all other RAM sections in your linker control file. 4. Context Switch, Register Usage and Stack Frames The RXv2 port for ThreadX uses the first software interrupt, SWINT, i.e., interrupt #27, -to perform context switch with the interrupt priority level 1. This ISR is thus reserved -when using ThreadX and the SWINT should not be manipulated in any way by the application. -The port will setup the interrupt within _tx_initialize_low_level and the compiler will -automatically install the necessary interrupt vector. As such no additional initialization +to perform context switch with the interrupt priority level 1. This ISR is thus reserved +when using ThreadX and the SWINT should not be manipulated in any way by the application. +The port will setup the interrupt within _tx_initialize_low_level and the compiler will +automatically install the necessary interrupt vector. As such no additional initialization is necessary by the application. The following defines the saved context stack frame used by the ThreadX port. The -state of the CPU registers at the time of a context switch is saved on the running -thread's stack The top of the suspended thread's stack is pointed to by +state of the CPU registers at the time of a context switch is saved on the running +thread's stack The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Offset Interrupted Stack Frame @@ -74,23 +74,23 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. 0x48 R2 0x4C PC - return address 0x50 PSW - + Note: By default IAR does not save the state of the accumulator registers ACC0 and ACC1 when entering an ISR. This means that if the ISR uses any of the DSP instructions the content of those registers could be corrupted. Saving and restoring of the acummulators can be enabled by adding the --save_acc command line option. - + 5. Improving Performance -The distribution version of ThreadX is built without any compiler optimizations. This -makes it easy to debug because you can trace or set breakpoints inside of ThreadX itself. -Of course, this costs some performance. To make ThreadX run faster, you can change the -ThreadX Library project to disable debug information and enable the desired optimizations. +The distribution version of ThreadX is built without any compiler optimizations. This +makes it easy to debug because you can trace or set breakpoints inside of ThreadX itself. +Of course, this costs some performance. To make ThreadX run faster, you can change the +ThreadX Library project to disable debug information and enable the desired optimizations. -In addition, you can eliminate the ThreadX basic API error checking by compiling your -application code with the symbol TX_DISABLE_ERROR_CHECKING defined before tx_api.h -is included. +In addition, you can eliminate the ThreadX basic API error checking by compiling your +application code with the symbol TX_DISABLE_ERROR_CHECKING defined before tx_api.h +is included. 6. Timer Processing @@ -102,18 +102,18 @@ a Renesas Fit CMT periodic timer module (r_cmt_rx) is used as the timer source. 7. Interrupt Handling -Interrupt handling is unaffected by the ThreadX port as such user interrupts can be +Interrupt handling is unaffected by the ThreadX port as such user interrupts can be written according to the toolchain's documentation. It is recommended not to use interrupt priority 1 as this is the priority of the context switch interrupt. However using interrupt -priority 1 won't cause any negative side effects but doing so may slightly reduce +priority 1 won't cause any negative side effects but doing so may slightly reduce performance. Please refer to the toolchain documentation for additional details on how to define interrupt service routines. 8. Execution Profiling -The RX port adds support for the Execution Profiling Kit (EPK). The EPK consists -of the files tx_execution_profile.c and tx_execution_profile.h. See the documentation +The RX port adds support for the Execution Profiling Kit (EPK). The EPK consists +of the files tx_execution_profile.c and tx_execution_profile.h. See the documentation of the EPK for generic usage details. To add the EPK to your RXv2 release make the following modifications: @@ -132,7 +132,7 @@ typedef unsigned long long EXECUTION_TIME; typedef unsigned long EXECUTION_TIME; #define TX_EXECUTION_MAX_TIME_SOURCE 0xFFFF #endif - + /* Define basic constants for the execution profile kit. */ #define TX_EXECUTION_TIME_SOURCE (EXECUTION_TIME) *((USHORT *) 0x8800A) @@ -151,14 +151,14 @@ information associated with this specific port of ThreadX: tx_thread_schedule.s Added low power support 01-31-2022 Release 6.1.10 changes: - tx_port.h Removed system state macro, and added + tx_port.h Removed system state macro, and added missing interrupt control defines tx_timer_interrupt.s Added missing thread preemption logic 10-15-2021 Release 6.1.9 changes: - tx_thread_context_restore.s Removed unnecessary stack type placement + tx_thread_context_restore.s Removed unnecessary stack type placement tx_thread_schedule.s Removed unnecessary stack type checking - tx_thread_stack_build.s Removed unnecessary stack type placement + tx_thread_stack_build.s Removed unnecessary stack type placement 06-02-2021 Release 6.1.7 changes: readme_threadx.txt Updated instructions on how to use execution profile. diff --git a/ports/rxv2/iar/src/tx_initialize_low_level.s b/ports/rxv2/iar/src/tx_initialize_low_level.s index eafcd6c0..482b29af 100644 --- a/ports/rxv2/iar/src/tx_initialize_low_level.s +++ b/ports/rxv2/iar/src/tx_initialize_low_level.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -25,53 +25,41 @@ section .text:CODE:ROOT ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_initialize_low_level RXv2/IAR */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/**************************************************************************/ public __tx_initialize_low_level __tx_initialize_low_level: @@ -80,7 +68,7 @@ __tx_initialize_low_level: ; _tx_initialize_unused_memory = (VOID_PTR) &free_mem_start; ; MOV.L #__tx_free_memory_start, R1 ; Pickup unused memory address - MOV.L #__tx_initialize_unused_memory,R2 + MOV.L #__tx_initialize_unused_memory,R2 MOV.L R1,[R2] ; Save first free memory address ; /* Set priority of SWINT to 1. */ diff --git a/ports/rxv2/iar/src/tx_thread_context_restore.s b/ports/rxv2/iar/src/tx_thread_context_restore.s index c8a452ed..7998506d 100644 --- a/ports/rxv2/iar/src/tx_thread_context_restore.s +++ b/ports/rxv2/iar/src/tx_thread_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,54 +39,40 @@ section .text:CODE:ROOT -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_context_restore RXv2/IAR */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* removed unnecessary stack */ -;/* type placement, */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/**************************************************************************/ public __tx_thread_context_restore __tx_thread_context_restore: @@ -103,7 +89,7 @@ __tx_thread_context_restore: MOV.L [R1], R2 SUB #1, R2 MOV.L R2,[R1] - BEQ __tx_thread_not_nested_restore + BEQ __tx_thread_not_nested_restore ; ; /* Interrupts are nested. */ @@ -125,17 +111,17 @@ __tx_thread_not_nested_restore: ; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { - + MOV.L #__tx_thread_current_ptr, R1 ; Pickup current thread ptr address MOV.L [R1], R2 CMP #0, R2 - BEQ __tx_thread_idle_system_restore - + BEQ __tx_thread_idle_system_restore + MOV.L #__tx_thread_preempt_disable, R3 ; Pick up preempt disable flag MOV.L [R3], R3 CMP #0, R3 BNE __tx_thread_no_preempt_restore ; If pre-empt disable flag set, we simply return to the original point of interrupt regardless - + MOV.L #__tx_thread_execute_ptr, R3 ; (_tx_thread_current_ptr != _tx_thread_execute_ptr) CMP [R3], R2 BNE __tx_thread_preempt_restore ; Jump to pre-empt restoring @@ -176,7 +162,7 @@ __tx_thread_dont_save_ts: SETPSW U ; User stack PUSHM R6-R13 - + MVFACGU #0, A1, R4 ; Save accumulators. MVFACHI #0, A1, R5 MVFACLO #0, A1, R6 diff --git a/ports/rxv2/iar/src/tx_thread_context_save.s b/ports/rxv2/iar/src/tx_thread_context_save.s index 28c0ea5f..dd29a288 100644 --- a/ports/rxv2/iar/src/tx_thread_context_save.s +++ b/ports/rxv2/iar/src/tx_thread_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -33,51 +33,39 @@ extern __tx_thread_current_ptr section .text:CODE:ROOT -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_context_save RXv2/IAR */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) ;{ public __tx_thread_context_save @@ -104,7 +92,7 @@ __tx_thread_context_save: BEQ __tx_thread_not_nested_save ; ; /* Nested interrupt condition. */ -; +; ADD #1, r2 ; _tx_thread_system_state++ MOV.L r2, [r1] @@ -130,7 +118,7 @@ __tx_thread_not_nested_save: MOV.L #__tx_thread_current_ptr, R2 ; Pickup current thread pointer MOV.L [R2], R2 - CMP #0,R2 ; Is it NULL? + CMP #0,R2 ; Is it NULL? BEQ __tx_thread_idle_system_save ; Yes, idle system is running - idle restore ; ; /* Move stack frame over to the current threads stack. */ @@ -152,7 +140,7 @@ __tx_thread_not_nested_save: MOV.L R14, [-R1] ; Save R14 on thread stack MVFC FPSW, R3 MOV.L R3, [-R1] ; Save FPSW on thread stack - + POP R2 ; Pick up return address from interrupt stack ADD #16, R0, R0 ; Correct interrupt stack pointer back to the bottom MVTC R1, USP ; Set user/thread stack pointer @@ -171,5 +159,5 @@ __tx_thread_idle_system_save: JMP R1 ; Return to caller ; ; } -;} +;} END diff --git a/ports/rxv2/iar/src/tx_thread_interrupt_control.s b/ports/rxv2/iar/src/tx_thread_interrupt_control.s index d4656214..1c29ec80 100644 --- a/ports/rxv2/iar/src/tx_thread_interrupt_control.s +++ b/ports/rxv2/iar/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -28,50 +28,38 @@ ;#include "tx_thread.h" ; section .text:CODE:ROOT -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_interrupt_control RXv2/IAR */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) ;{ public __tx_thread_interrupt_control @@ -79,20 +67,20 @@ __tx_thread_interrupt_control: ; ; /* Pickup current interrupt lockout posture. */ ; - + MVFC PSW, R2 ; Save PSW to R2 MOV.L R2, R3 ; Make a copy of PSW in r3 - + ; ; /* Apply the new interrupt posture. */ ; - + BTST #16, R1 ; Test I bit of PSW of "new posture" BMNE #16, R2 ; Conditionally set I bit of intermediate posture - + MVTC R2, PSW ; Save intermediate posture to PSW - - MOV.L R3,R1 ; Get original SR + + MOV.L R3,R1 ; Get original SR RTS ; Return to caller ;} END diff --git a/ports/rxv2/iar/src/tx_thread_schedule.s b/ports/rxv2/iar/src/tx_thread_schedule.s index 5cf106c7..8d0c02f6 100644 --- a/ports/rxv2/iar/src/tx_thread_schedule.s +++ b/ports/rxv2/iar/src/tx_thread_schedule.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -41,56 +41,41 @@ section .text:CODE:ROOT -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_schedule RXv2/IAR */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLS */ -;/* */ +;/* */ +;/* OUTPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* removed unnecessary stack */ -;/* type checking, */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), and */ -;/* added low power support, */ -;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) ;{ public __tx_thread_schedule @@ -108,7 +93,7 @@ __tx_thread_schedule_loop: MOV.L [R1],R2 ; Pickup next thread to execute CMP #0,R2 ; Is it NULL? BNE __tx_thread_thread_ready ; Not NULL, schedule the thread - ; Idle system - no thread is ready + ; Idle system - no thread is ready #if (TX_LOW_POWER == 1) MOV.L #__tx_thread_preempt_disable, R1 ; Load prempt disable flag. MOV.L [R1], R2 @@ -137,7 +122,7 @@ __tx_thread_thread_ready: ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Note that interrupts are locked out at this point. */ ; ; /* Setup the current thread pointer. */ @@ -173,14 +158,14 @@ __tx_thread_thread_ready: MVTACLO R3, A1 MVTACHI R2, A1 MVTACGU R1, A1 - + POPM R6-R13 ; Recover interrupt stack frame - POPC FPSW + POPC FPSW POPM R14-R15 POPM R3-R5 - POPM R1-R2 + POPM R1-R2 RTE ; Return to point of interrupt, this restores PC and PSW - + ;} extern __tx_thread_context_save diff --git a/ports/rxv2/iar/src/tx_thread_stack_build.s b/ports/rxv2/iar/src/tx_thread_stack_build.s index 1d6be57f..632ac6e3 100644 --- a/ports/rxv2/iar/src/tx_thread_stack_build.s +++ b/ports/rxv2/iar/src/tx_thread_stack_build.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -55,28 +55,14 @@ ;/* */ ;/* _tx_thread_create Create thread service */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* removed unnecessary stack */ -;/* type placement, */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ public __tx_thread_stack_build __tx_thread_stack_build: ; -; +; ; /* Build an interrupt frame. The form of the fake interrupt stack ; on the Renesas RX should look like the following after it is built: -; +; ; Stack Top: ACC0 ; ACC1 ; R6 @@ -139,11 +125,11 @@ __tx_thread_stack_build: MOV.L R4,[-R3] ; /* Setup stack pointer. */ -; thread_ptr -> tx_thread_stack_ptr = R1; +; thread_ptr -> tx_thread_stack_ptr = R1; MOV.L R3, 8[R1] ; Store initial SP in thread control block RTS - + ;} END diff --git a/ports/rxv2/iar/src/tx_thread_system_return.s b/ports/rxv2/iar/src/tx_thread_system_return.s index 0e312291..53f0855f 100644 --- a/ports/rxv2/iar/src/tx_thread_system_return.s +++ b/ports/rxv2/iar/src/tx_thread_system_return.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -20,7 +20,7 @@ ;/**************************************************************************/ section .text:CODE:ROOT - + ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ @@ -54,18 +54,6 @@ ;/* */ ;/* ThreadX components */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ public __tx_thread_system_return diff --git a/ports/rxv2/iar/src/tx_timer_interrupt.s b/ports/rxv2/iar/src/tx_timer_interrupt.s index 9bc43b24..a1ec6147 100644 --- a/ports/rxv2/iar/src/tx_timer_interrupt.s +++ b/ports/rxv2/iar/src/tx_timer_interrupt.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -73,20 +73,6 @@ SWI0 EQU 0x872E0 ;/* */ ;/* interrupt vector */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), and */ -;/* added missing thread */ -;/* preemption logic, */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ public __tx_timer_interrupt @@ -149,14 +135,14 @@ __tx_timer_no_time_slice: MOV.L [R2+], R1 ; Pickup timer list entry, _tx_timer_current_ptr++ CMP #0, R1 ; Is timer pointer NULL? BEQ __tx_timer_no_timer ; Yes, no timer has expired - + ; ; /* Set expiration flag. */ ; _tx_timer_expired = TX_TRUE; ; MOV.L #__tx_timer_expired,R2 ; Build address of expired flag MOV.L #1, R1 ; Build expired value - MOV.L R1, [R2] + MOV.L R1, [R2] BRA __tx_timer_done ; Finished with timer processing ; ; } @@ -167,7 +153,7 @@ __tx_timer_no_timer: ; /* No timer expired, increment the timer pointer. */ ; _tx_timer_current_ptr++; ; -; /* R2 already contains __tx_timer_current_ptr++ */ +; /* R2 already contains __tx_timer_current_ptr++ */ ; ; /* Check for wrap-around. */ ; if (_tx_timer_current_ptr == _tx_timer_list_end) @@ -186,9 +172,9 @@ __tx_timer_no_timer: ; } ; __tx_timer_skip_wrap: - MOV.L #__tx_timer_current_ptr,R1 + MOV.L #__tx_timer_current_ptr,R1 MOV.L R2, [R1] ; Store in updated pointer in _tx_timer_current_ptr - + __tx_timer_done: ; ; /* See if anything has expired. */ @@ -222,14 +208,14 @@ __tx_timer_dont_activate: ; /* Did time slice expire? */ ; if (_tx_timer_expired_time_slice) ; { -; +; MOV.L #__tx_timer_expired_time_slice, R1 ; Pickup time-slice expired flag addr MOV.L [R1], R1 ; Pickup actual flag CMP #0,R1 ; Has time-slice expired? BEQ __tx_timer_not_ts_expiration ; No, skip time-slice expiration ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BSR __tx_thread_time_slice ; Call time-slice processing diff --git a/ports/rxv3/ccrx/CMakeLists.txt b/ports/rxv3/ccrx/CMakeLists.txt index fabadffe..f2269c51 100644 --- a/ports/rxv3/ccrx/CMakeLists.txt +++ b/ports/rxv3/ccrx/CMakeLists.txt @@ -2,7 +2,7 @@ target_sources(${PROJECT_NAME} PRIVATE # {{BEGIN_TARGET_SOURCES}} - ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.src + ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.src ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.src ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.src ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.src diff --git a/ports/rxv3/ccrx/inc/tx_port.h b/ports/rxv3/ccrx/inc/tx_port.h index 86a29a9b..a56636bd 100644 --- a/ports/rxv3/ccrx/inc/tx_port.h +++ b/ports/rxv3/ccrx/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,45 +21,29 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ /* tx_port.h RXv3/CCRX */ /* 6.1.11 */ /* */ -/* AUTHOR */ +/* AUTHOR */ /* */ -/* William E. Lamie, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* 10-15-2021 William E. Lamie Modified comment(s), and */ -/* added FPU support, */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 William E. Lamie Modified comment(s), removed */ -/* system state macro, and */ -/* added missing interrupt */ -/* control defines, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comment(s), */ -/* resulting in version 6.1.11 */ -/* */ -/**************************************************************************/ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/**************************************************************************/ #ifndef TX_PORT_H #define TX_PORT_H @@ -68,13 +53,13 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" #endif -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -118,8 +103,8 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif #ifndef TX_TRACE_TIME_SOURCE @@ -143,7 +128,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -155,13 +140,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #define TX_THREAD_EXTENSION_2 ULONG tx_thread_fpu_enable; /* FPU Register Save Flag. */ -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -175,11 +160,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -187,8 +172,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -215,16 +200,16 @@ typedef unsigned short USHORT; #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ /* UINT _tx_thread_interrupt_control(UINT new_posture); */ -#pragma inline_asm _tx_thread_interrupt_disable +#pragma inline_asm _tx_thread_interrupt_disable static UINT _tx_thread_interrupt_disable(void){ MVFC PSW,R1 ; CLRPSW I ; @@ -279,8 +264,8 @@ void tx_thread_fpu_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX RXv3/CCRX Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv3/CCRX Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv3/ccrx/readme_threadx.txt b/ports/rxv3/ccrx/readme_threadx.txt index cbc8149d..06e306e1 100644 --- a/ports/rxv3/ccrx/readme_threadx.txt +++ b/ports/rxv3/ccrx/readme_threadx.txt @@ -16,25 +16,25 @@ for the RXv3 3. System Initialization -The system entry point using Renesas tools is at the label _PowerON_Reset_PC. -Use the resetprg.c file that comes with your release. Most notable is that Threadx -applications run in supervisor mode and do not use user mode. Hence switching to +The system entry point using Renesas tools is at the label _PowerON_Reset_PC. +Use the resetprg.c file that comes with your release. Most notable is that Threadx +applications run in supervisor mode and do not use user mode. Hence switching to user mode has been commented out. The vector area is set up using either intprg.c or in the file tx_initialize_low_level.src. -The file tx_initialize_low_level.src is responsible for setting up various system data -structures, interrupt vectors, and a periodic timer. This is the ideal place add +The file tx_initialize_low_level.src is responsible for setting up various system data +structures, interrupt vectors, and a periodic timer. This is the ideal place add application specific hardware initialization code. -ThreadX utilizes CMT0 as a periodic timer interrupt source. The CMT0 interrupt is -typically setup for 10ms periodic interrupts and the interrupt priority level is set to +ThreadX utilizes CMT0 as a periodic timer interrupt source. The CMT0 interrupt is +typically setup for 10ms periodic interrupts and the interrupt priority level is set to level 5 with the symbol CMT_RX_CFG_IPR in r_cmt_rx_config.h of Renesas CMT timer module (r_cmt_rx). You may change any of the timer parameters to suit your needs. -In addition, _tx_initialize_low_level determines the first available address for use by -the application, which is supplied as the sole input parameter to your application -definition function, tx_application_define(). The mechanism is implemented by creating the -FREEMEM section, this section should be linked last in the RAM area. tx_initialize_low_level +In addition, _tx_initialize_low_level determines the first available address for use by +the application, which is supplied as the sole input parameter to your application +definition function, tx_application_define(). The mechanism is implemented by creating the +FREEMEM section, this section should be linked last in the RAM area. tx_initialize_low_level will pick up the starting label of this section and put it in the global variable: _tx_initialize_unused_memory @@ -42,15 +42,15 @@ _tx_initialize_unused_memory 4. Context Switch, Register Usage and Stack Frames The RXv3 port for ThreadX uses the first software interrupt, SWINT, i.e., interrupt #27, -to perform context switch with the interrupt priority level 1. This ISR is thus reserved -when using ThreadX and the SWINT should not be manipulated in any way by the application. -The port will setup the interrupt within _tx_initialize_low_level and the compiler will -automatically install the necessary interrupt vector. As such no additional initialization +to perform context switch with the interrupt priority level 1. This ISR is thus reserved +when using ThreadX and the SWINT should not be manipulated in any way by the application. +The port will setup the interrupt within _tx_initialize_low_level and the compiler will +automatically install the necessary interrupt vector. As such no additional initialization is necessary by the application. The following defines the saved context stack frame used by the ThreadX port. The -state of the CPU registers at the time of a context switch is saved on the running -thread's stack The top of the suspended thread's stack is pointed to by +state of the CPU registers at the time of a context switch is saved on the running +thread's stack The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Offset Stack Frame without DFPU Register @@ -75,7 +75,7 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. 0x44 R2 0x48 PC - return address 0x4C PSW - + Offset Stack Frame with DFPU Register 0x00 DPSW @@ -118,7 +118,7 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. 0x94 R2 0x98 PC - return address 0x9C PSW - + Note: By default ccrx does not save the state of the accumulator registers ACC0 and ACC1 when entering an ISR. This means that if the ISR uses any of the DSP instructions the content of those registers could be corrupted. Saving and restoring of the accumulators @@ -127,29 +127,29 @@ can be enabled by adding the -save_acc command line option. 5. Double Precision FPU Instructions Support -The RXv3 architecture supports an optional set of double precision instructions which -makes use of a new set of registers that must be saved and restored during context -switches. This feature can be accessed by adding the -dfpu compiler switch. +The RXv3 architecture supports an optional set of double precision instructions which +makes use of a new set of registers that must be saved and restored during context +switches. This feature can be accessed by adding the -dfpu compiler switch. To reduce the overhead of saving and restoring the FPU registers for all threads -the RXv3 port allows each thread to enable and disable saving and restoring the DFPU -registers. By default the feature is disabled for new threads. To enable the feature -tx_thread_fpu_enable() must be called within the context of every thread that will +the RXv3 port allows each thread to enable and disable saving and restoring the DFPU +registers. By default the feature is disabled for new threads. To enable the feature +tx_thread_fpu_enable() must be called within the context of every thread that will perform FPU operation. The saving and restoring of DFPU registers can be disabled again by calling tx_thread_fpu_disable(). This can be useful if a thread only makes occasional use of the FPU. - + 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make ThreadX run faster, you can change the ThreadX Library -project to disable debug information and enable the desired optimizations. +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make ThreadX run faster, you can change the ThreadX Library +project to disable debug information and enable the desired optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined before tx_api.h is included. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. 7. Timer Processing @@ -161,18 +161,18 @@ a Renesas Fit CMT periodic timer module (r_cmt_rx) is used as the timer source. 8. Interrupt Handling -Interrupt handling is unaffected by the ThreadX port as such user interrupts can be +Interrupt handling is unaffected by the ThreadX port as such user interrupts can be written according to the toolchain's documentation. It is recommended not to use interrupt priority 1 as this is the priority of the context switch interrupt. However using interrupt -priority 1 won't cause any negative side effects but doing so may slightly reduce +priority 1 won't cause any negative side effects but doing so may slightly reduce performance. Please refer to the toolchain documentation for additional details on how to define interrupt service routines. 9. Execution Profiling -The RX port adds support for the Execution Profiling Kit (EPK). The EPK consists -of the files tx_execution_profile.c and tx_execution_profile.h. See the documentation +The RX port adds support for the Execution Profiling Kit (EPK). The EPK consists +of the files tx_execution_profile.c and tx_execution_profile.h. See the documentation of the EPK for generic usage details. To add the EPK to your RXv3 release make the following modifications: @@ -191,7 +191,7 @@ typedef unsigned long long EXECUTION_TIME; typedef unsigned long EXECUTION_TIME; #define TX_EXECUTION_MAX_TIME_SOURCE 0xFFFF #endif - + /* Define basic constants for the execution profile kit. */ #define TX_EXECUTION_TIME_SOURCE (EXECUTION_TIME) *((USHORT *) 0x8800A) @@ -214,7 +214,7 @@ information associated with this specific port of ThreadX: tx_thread_schedule.src Added low power support 01-31-2022 Release 6.1.10 changes: - tx_port.h Removed system state macro, and added + tx_port.h Removed system state macro, and added missing interrupt control defines tx_timer_interrupt.src Added missing thread preemption logic diff --git a/ports/rxv3/ccrx/src/tx_initialize_low_level.src b/ports/rxv3/ccrx/src/tx_initialize_low_level.src index bec6521c..172144ff 100644 --- a/ports/rxv3/ccrx/src/tx_initialize_low_level.src +++ b/ports/rxv3/ccrx/src/tx_initialize_low_level.src @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -26,55 +26,55 @@ IEN03 .EQU 87203H .SECTION P,CODE - + ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_initialize_low_level RXv3/CCRX */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ +;/* 10-15-2021 William E. Lamie Modified comment(s), */ +;/* resulting in version 6.1.9 */ ;/* 01-31-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.10 */ ;/* 04-25-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ .GLB __tx_initialize_low_level __tx_initialize_low_level: @@ -97,7 +97,7 @@ __tx_initialize_low_level: OR #(1 << 3), r2 MOV.B r2, [r1] - RTS + RTS .SECTION FREEMEM ,DATA, ALIGN=4 free_mem_start: diff --git a/ports/rxv3/ccrx/src/tx_thread_context_restore.src b/ports/rxv3/ccrx/src/tx_thread_context_restore.src index d64f15e1..2a5b2217 100644 --- a/ports/rxv3/ccrx/src/tx_thread_context_restore.src +++ b/ports/rxv3/ccrx/src/tx_thread_context_restore.src @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,53 +39,53 @@ .GLB __tx_thread_preempt_disable ; .SECTION P,CODE -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_context_restore RXv3/CCRX */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* added FPU support, */ -;/* resulting in version 6.1.9 */ +;/* 10-15-2021 William E. Lamie Modified comment(s), and */ +;/* added FPU support, */ +;/* resulting in version 6.1.9 */ ;/* 01-31-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.10 */ ;/* 04-25-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) ;{ .GLB __tx_thread_context_restore @@ -103,7 +103,7 @@ __tx_thread_context_restore: MOV.L [R1], R2 SUB #1, R2 MOV.L R2,[R1] - BEQ __tx_thread_not_nested_restore + BEQ __tx_thread_not_nested_restore ; ; /* Interrupts are nested. */ @@ -112,7 +112,7 @@ __tx_thread_context_restore: ; and return to the point of interrupt. */ ; __tx_thread_nested_restore: - POPC FPSW ; Restore FPU status + POPC FPSW ; Restore FPU status POPM R14-R15 ; Restore R14-R15 POPM R3-R5 ; Restore R3-R5 POPM R1-R2 ; Restore R1-R2 @@ -125,17 +125,17 @@ __tx_thread_not_nested_restore: ; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { - + MOV.L #__tx_thread_current_ptr, R1 ; Pickup current thread ptr address MOV.L [R1], R2 CMP #0, R2 - BEQ __tx_thread_idle_system_restore - + BEQ __tx_thread_idle_system_restore + MOV.L #__tx_thread_preempt_disable, R3 ; Pick up preempt disable flag MOV.L [R3], R3 CMP #0, R3 BNE __tx_thread_no_preempt_restore ; If pre-empt disable flag set, we simply return to the original point of interrupt regardless - + MOV.L #__tx_thread_execute_ptr, R3 ; (_tx_thread_current_ptr != _tx_thread_execute_ptr) CMP [R3], R2 BNE __tx_thread_preempt_restore ; Jump to pre-empt restoring diff --git a/ports/rxv3/ccrx/src/tx_thread_context_save.src b/ports/rxv3/ccrx/src/tx_thread_context_save.src index 0e4dce94..69bbd670 100644 --- a/ports/rxv3/ccrx/src/tx_thread_context_save.src +++ b/ports/rxv3/ccrx/src/tx_thread_context_save.src @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,51 +34,51 @@ .GLB __tx_thread_system_stack_ptr .SECTION P,CODE -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_context_save RXv3/CCRX */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ +;/* 10-15-2021 William E. Lamie Modified comment(s), */ +;/* resulting in version 6.1.9 */ ;/* 01-31-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.10 */ ;/* 04-25-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) ;{ .GLB __tx_thread_context_save @@ -104,7 +104,7 @@ __tx_thread_context_save: BEQ __tx_thread_not_nested_save ; ; /* Nested interrupt condition. */ -; +; ADD #1, r2 ; _tx_thread_system_state++ MOV.L r2, [r1] @@ -130,7 +130,7 @@ __tx_thread_not_nested_save: MOV.L #__tx_thread_current_ptr, R2 ; Pickup current thread pointer MOV.L [R2], R2 - CMP #0,R2 ; Is it NULL? + CMP #0,R2 ; Is it NULL? BEQ __tx_thread_idle_system_save ; Yes, idle system is running - idle restore ; ; /* Move stack frame over to the current threads stack. */ @@ -142,9 +142,9 @@ __tx_thread_not_nested_save: MOV.L 12[R0], R2 MOV.L R2, [-R1] ; Save PC on thread stack MOV.L 8[R0], R2 - MOV.L R2, [-R1] ; Save R2 on thread stack + MOV.L R2, [-R1] ; Save R2 on thread stack MOV.L 4[R0], R2 - MOV.L R2, [-R1] ; Save R1 on thread stack + MOV.L R2, [-R1] ; Save R1 on thread stack MOV.L R5, [-R1] ; Save R5 on thread stack MOV.L R4, [-R1] ; Save R4 on thread stack MOV.L R3, [-R1] ; Save R3 on thread stack @@ -152,9 +152,9 @@ __tx_thread_not_nested_save: MOV.L R14, [-R1] ; Save R14 on thread stack MVFC FPSW, R3 MOV.L R3, [-R1] ; Save FPSW on thread stack - + POP R2 ; Pick up return address from interrupt stack - ADD #16, R0, R0 ; Correct interrupt stack pointer back to the bottom + ADD #16, R0, R0 ; Correct interrupt stack pointer back to the bottom MVTC R1, USP ; Set user/thread stack pointer JMP R2 ; Return to ISR diff --git a/ports/rxv3/ccrx/src/tx_thread_interrupt_control.src b/ports/rxv3/ccrx/src/tx_thread_interrupt_control.src index e3d1d640..ec4208ec 100644 --- a/ports/rxv3/ccrx/src/tx_thread_interrupt_control.src +++ b/ports/rxv3/ccrx/src/tx_thread_interrupt_control.src @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,50 +29,50 @@ ; ; .SECTION P,CODE -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_interrupt_control RXv3/CCRX */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ +;/* 10-15-2021 William E. Lamie Modified comment(s), */ +;/* resulting in version 6.1.9 */ ;/* 01-31-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.10 */ ;/* 04-25-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) ;{ @@ -81,20 +81,20 @@ __tx_thread_interrupt_control: ; ; /* Pickup current interrupt lockout posture. */ ; - + MVFC PSW, R2 ; Save PSW to R2 MOV.L R2, R3 ; Make a copy of PSW in r3 - + ; ; /* Apply the new interrupt posture. */ ; - + BTST #16, R1 ; Test I bit of PSW of "new posture" - BMNE #16, R2 ; Conditionally set I bit of intermediate posture - + BMNE #16, R2 ; Conditionally set I bit of intermediate posture + MVTC R2, PSW ; Save intermediate posture to PSW - - MOV.L R3,R1 ; Get original SR + + MOV.L R3,R1 ; Get original SR RTS ; Return to caller ;} .END diff --git a/ports/rxv3/ccrx/src/tx_thread_schedule.src b/ports/rxv3/ccrx/src/tx_thread_schedule.src index abbd6cbf..116281ee 100644 --- a/ports/rxv3/ccrx/src/tx_thread_schedule.src +++ b/ports/rxv3/ccrx/src/tx_thread_schedule.src @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -41,55 +41,55 @@ ; .SECTION P,CODE -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_schedule RXv3/CCRX */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLS */ -;/* */ +;/* */ +;/* OUTPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* added FPU support, */ -;/* resulting in version 6.1.9 */ +;/* 10-15-2021 William E. Lamie Modified comment(s), and */ +;/* added FPU support, */ +;/* resulting in version 6.1.9 */ ;/* 01-31-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), and */ -;/* added low power support, */ -;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* 04-25-2022 William E. Lamie Modified comment(s), and */ +;/* added low power support, */ +;/* resulting in version 6.1.11 */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) ;{ .GLB __tx_thread_schedule @@ -106,7 +106,7 @@ __tx_thread_schedule_loop: MOV.L [R1],R2 ; Pickup next thread to execute CMP #0,R2 ; Is it NULL? BNE __tx_thread_thread_ready ; Not NULL, schedule the thread - ; Idle system - no thread is ready + ; Idle system - no thread is ready .IF TX_LOW_POWER==1 MOV.L #__tx_thread_preempt_disable, R1 ; Load prempt disable flag. MOV.L [R1], R2 @@ -135,7 +135,7 @@ __tx_thread_thread_ready: ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Note that interrupts are locked out at this point. */ ; ; /* Setup the current thread pointer. */ @@ -147,7 +147,7 @@ __tx_thread_thread_ready: ; /* Increment the run count for this thread. */ ; _tx_thread_current_ptr -> tx_thread_run_count++; ; - MOV.L 4[R2],R3 ; Pickup run count + MOV.L 4[R2],R3 ; Pickup run count ADD #1,R3 ; Increment run counter MOV.L R3,4[R2] ; Store it back in control block ; @@ -156,7 +156,7 @@ __tx_thread_thread_ready: ; MOV.L 24[R2],R3 ; Pickup thread time-slice MOV.L #__tx_timer_time_slice,R4 ; Pickup pointer to time-slice - MOV.L R3, [R4] ; Setup time-slice + MOV.L R3, [R4] ; Setup time-slice ; ; /* Switch to the thread's stack. */ ; SP = _tx_thread_execute_ptr -> tx_thread_stack_ptr; @@ -184,12 +184,12 @@ __tx_thread_schedule_fpu_skip: MVTACGU R1, A1 POPM R6-R13 ; Recover interrupt stack frame - POPC FPSW + POPC FPSW POPM R14-R15 POPM R3-R5 - POPM R1-R2 + POPM R1-R2 RTE ; Return to point of interrupt, this restores PC and PSW - + ; ;} diff --git a/ports/rxv3/ccrx/src/tx_thread_stack_build.src b/ports/rxv3/ccrx/src/tx_thread_stack_build.src index 6738fef3..749d459d 100644 --- a/ports/rxv3/ccrx/src/tx_thread_stack_build.src +++ b/ports/rxv3/ccrx/src/tx_thread_stack_build.src @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -30,61 +30,61 @@ ; ; .SECTION P,CODE -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_stack_build RXv3/CCRX */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ ;/* This function builds a stack frame on the supplied thread's stack. */ ;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ ;/* thread_ptr Pointer to thread control blk */ ;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ +;/* */ +;/* OUTPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLS */ -;/* */ +;/* */ +;/* CALLS */ +;/* */ ;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ +;/* */ +;/* CALLED BY */ +;/* */ ;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ +;/* 10-15-2021 William E. Lamie Modified comment(s), */ +;/* resulting in version 6.1.9 */ ;/* 01-31-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.10 */ ;/* 04-25-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) ;{ .GLB __tx_thread_stack_build __tx_thread_stack_build: ; -; +; ; /* Build an interrupt frame. The form of the fake interrupt stack ; on the Renesas RX should look like the following after it is built: -; +; ; Stack Top: ACC0 ; ACC1 ; R6 @@ -120,22 +120,22 @@ __tx_thread_stack_build: MOV.L R2, [-R3] ; Initial PC MOV.L #0, R4 MOV.L R4,[-R3] ; Initial R2 ... - MOV.L R4,[-R3] ; Initial R1 ... + MOV.L R4,[-R3] ; Initial R1 ... MOV.L R4,[-R3] ; Initial R5 ... MOV.L R4,[-R3] ; Initial R4 ... - MOV.L R4,[-R3] ; Initial R3 ... + MOV.L R4,[-R3] ; Initial R3 ... MOV.L R4,[-R3] ; Initial R15 ... MOV.L R4,[-R3] ; Initial R14 ... MVFC FPSW, r4 MOV.L R4, [-R3] ; Initial FPSW MOV.L #0, R4 - MOV.L R4,[-R3] ; Initial R13 ... + MOV.L R4,[-R3] ; Initial R13 ... MOV.L R4,[-R3] ; Initial R12 ... MOV.L R4,[-R3] ; Initial R11 ... - MOV.L R4,[-R3] ; Initial R10 ... + MOV.L R4,[-R3] ; Initial R10 ... MOV.L R4,[-R3] ; Initial R9 ... MOV.L R4,[-R3] ; Initial R8 ... - MOV.L R4,[-R3] ; Initial R7 ... + MOV.L R4,[-R3] ; Initial R7 ... MOV.L R4,[-R3] ; Initial R6 ... MOV.L R4,[-R3] ; Accumulator 1 @@ -147,11 +147,11 @@ __tx_thread_stack_build: MOV.L R4,[-R3] ; /* Setup stack pointer. */ -; thread_ptr -> tx_thread_stack_ptr = R1; +; thread_ptr -> tx_thread_stack_ptr = R1; MOV.L R3, 8[R1] ; Store initial SP in thread control block RTS - + ;} .END diff --git a/ports/rxv3/ccrx/src/tx_thread_system_return.src b/ports/rxv3/ccrx/src/tx_thread_system_return.src index a3e41c9a..8614ab58 100644 --- a/ports/rxv3/ccrx/src/tx_thread_system_return.src +++ b/ports/rxv3/ccrx/src/tx_thread_system_return.src @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,43 +34,43 @@ .GLB __tx_thread_schedule .SECTION P,CODE -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_system_return RXv3/CCRX */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the system. Only a minimal context */ -;/* is saved since the compiler assumes temp registers are going to get */ -;/* slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the system. Only a minimal context */ +;/* is saved since the compiler assumes temp registers are going to get */ +;/* slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ ;/* 10-15-2021 William E. Lamie Modified comment(s), and */ ;/* removed unused code, */ @@ -79,8 +79,8 @@ ;/* resulting in version 6.1.10 */ ;/* 04-25-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) ;{ .GLB __tx_thread_system_return diff --git a/ports/rxv3/ccrx/src/tx_timer_interrupt.src b/ports/rxv3/ccrx/src/tx_timer_interrupt.src index 3d5d1a36..a0edaa6f 100644 --- a/ports/rxv3/ccrx/src/tx_timer_interrupt.src +++ b/ports/rxv3/ccrx/src/tx_timer_interrupt.src @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -50,58 +50,58 @@ .GLB __tx_thread_current_ptr ; .SECTION P,CODE -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_timer_interrupt RXv3/CCRX */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_context_save Save interrupted context */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* _tx_thread_context_restore Restore interrupted context */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_context_save Save interrupted context */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* _tx_thread_context_restore Restore interrupted context */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ ;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ +;/* 10-15-2021 William E. Lamie Modified comment(s), */ +;/* resulting in version 6.1.9 */ ;/* 01-31-2022 William E. Lamie Modified comment(s), and */ ;/* added missing thread */ ;/* preemption logic, */ ;/* resulting in version 6.1.10 */ ;/* 04-25-2022 William E. Lamie Modified comment(s), */ ;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) ;{ .GLB __tx_timer_interrupt @@ -164,14 +164,14 @@ __tx_timer_no_time_slice: MOV.L [R2+], R1 ; Pickup timer list entry, _tx_timer_current_ptr++ CMP #0, R1 ; Is timer pointer NULL? BEQ __tx_timer_no_timer ; Yes, no timer has expired - + ; ; /* Set expiration flag. */ ; _tx_timer_expired = TX_TRUE; ; MOV.L #__tx_timer_expired,R2 ; Build address of expired flag MOV.L #1, R1 ; Build expired value - MOV.L R1, [R2] + MOV.L R1, [R2] BRA __tx_timer_done ; Finished with timer processing ; ; } @@ -182,7 +182,7 @@ __tx_timer_no_timer: ; /* No timer expired, increment the timer pointer. */ ; _tx_timer_current_ptr++; ; -; /* R2 already contains __tx_timer_current_ptr++ */ +; /* R2 already contains __tx_timer_current_ptr++ */ ; ; /* Check for wrap-around. */ ; if (_tx_timer_current_ptr == _tx_timer_list_end) @@ -201,9 +201,9 @@ __tx_timer_no_timer: ; } ; __tx_timer_skip_wrap: - MOV.L #__tx_timer_current_ptr,R1 - MOV.L R2, [R1] ; Store in updated pointer in _tx_timer_current_ptr - + MOV.L #__tx_timer_current_ptr,R1 + MOV.L R2, [R1] ; Store in updated pointer in _tx_timer_current_ptr + __tx_timer_done: ; ; /* See if anything has expired. */ @@ -237,14 +237,14 @@ __tx_timer_dont_activate: ; /* Did time slice expire? */ ; if (_tx_timer_expired_time_slice) ; { -; +; MOV.L #__tx_timer_expired_time_slice, R1 ; Pickup time-slice expired flag addr MOV.L [R1], R1 ; Pickup actual flag CMP #0,R1 ; Has time-slice expired? BEQ __tx_timer_not_ts_expiration ; No, skip time-slice expiration ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BSR __tx_thread_time_slice ; Call time-slice processing diff --git a/ports/rxv3/gnu/inc/tx_port.h b/ports/rxv3/gnu/inc/tx_port.h index 70ff629c..52da26d8 100644 --- a/ports/rxv3/gnu/inc/tx_port.h +++ b/ports/rxv3/gnu/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,44 +21,29 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ /* tx_port.h RXv3/GNURX */ /* 6.1.11 */ /* */ -/* AUTHOR */ -/* */ +/* AUTHOR */ +/* */ /* William E. Lamie, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* 10-15-2021 William E. Lamie Modified comment(s), and */ -/* added FPU support, */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 William E. Lamie Modified comment(s), and */ -/* added missing interrupt */ -/* control defines, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comment(s), */ -/* resulting in version 6.1.11 */ -/* */ -/**************************************************************************/ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/**************************************************************************/ #ifndef TX_PORT_H #define TX_PORT_H @@ -70,13 +56,13 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" #endif -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -120,8 +106,8 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -146,7 +132,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -158,13 +144,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #define TX_THREAD_EXTENSION_2 ULONG tx_thread_fpu_enable; /* FPU Register Save Flag. */ -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -178,11 +164,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -190,8 +176,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -217,9 +203,9 @@ typedef unsigned short USHORT; #define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -275,8 +261,8 @@ void tx_thread_fpu_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX RXv3/GNURX Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv3/GNURX Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv3/gnu/readme_threadx.txt b/ports/rxv3/gnu/readme_threadx.txt index 3d68313c..2a812d62 100644 --- a/ports/rxv3/gnu/readme_threadx.txt +++ b/ports/rxv3/gnu/readme_threadx.txt @@ -18,40 +18,40 @@ for the RXv3. 3. System Initialization -The system entry point using the GNU tools is at the label _PowerON_Reset. +The system entry point using the GNU tools is at the label _PowerON_Reset. -The vector area is setup in the file tx_initialize_low_level.S. This file is also -responsible for setting up various system data structures, interrupt vectors, and -the periodic timer interrupt. This file is also an ideal place to add additional hardware +The vector area is setup in the file tx_initialize_low_level.S. This file is also +responsible for setting up various system data structures, interrupt vectors, and +the periodic timer interrupt. This file is also an ideal place to add additional hardware initialization code. -The ThreadX demonstration for the RXv3 utilizes CMT0 as a periodic timer interrupt -source. The CMT0 interrupt is typically setup for 10ms periodic interrupts and the -interrupt priority level is set to level 5 with the symbol CMT_RX_CFG_IPR in -r_cmt_rx_config.h of Renesas CMT timer module(r_cmt_rx). You may change any of the timer +The ThreadX demonstration for the RXv3 utilizes CMT0 as a periodic timer interrupt +source. The CMT0 interrupt is typically setup for 10ms periodic interrupts and the +interrupt priority level is set to level 5 with the symbol CMT_RX_CFG_IPR in +r_cmt_rx_config.h of Renesas CMT timer module(r_cmt_rx). You may change any of the timer parameters as needed. Increasing the timer interrupt frequency increases the overhead of the timer handling code on the system. -In addition, _tx_initialize_low_level determines the first available address for use -by the application, which is supplied as the sole input parameter to your application -definition function, tx_application_define. The first available memory is determined +In addition, _tx_initialize_low_level determines the first available address for use +by the application, which is supplied as the sole input parameter to your application +definition function, tx_application_define. The first available memory is determined by the location of the '_end' label the is defined in the linker script. -'_end' should reference the first memory AFTER all other RAM +'_end' should reference the first memory AFTER all other RAM sections in your linker control file. 4. Context Switch, Register Usage and Stack Frames The RXv3 port for ThreadX uses the first software interrupt, SWINT, i.e., interrupt #27, -to perform context switch with the interrupt priority level 1. This ISR is thus reserved -when using ThreadX and the SWINT should not be manipulated in any way by the application. -The port will setup the interrupt within _tx_initialize_low_level and the compiler will -automatically install the necessary interrupt vector. As such no additional initialization +to perform context switch with the interrupt priority level 1. This ISR is thus reserved +when using ThreadX and the SWINT should not be manipulated in any way by the application. +The port will setup the interrupt within _tx_initialize_low_level and the compiler will +automatically install the necessary interrupt vector. As such no additional initialization is necessary by the application. The following defines the saved context stack frame used by the ThreadX port. The -state of the CPU registers at the time of a context switch is saved on the running -thread's stack The top of the suspended thread's stack is pointed to by +state of the CPU registers at the time of a context switch is saved on the running +thread's stack The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Offset Stack Frame without DFPU Register @@ -76,7 +76,7 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. 0x44 R2 0x48 PC - return address 0x4C PSW - + Offset Stack Frame with DFPU Register 0x00 DPSW @@ -119,7 +119,7 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. 0x94 R2 0x98 PC - return address 0x9C PSW - + Note: By default GNURX does not save the state of the accumulator registers ACC0 and ACC1 when entering an ISR. This means that if the ISR uses any of the DSP instructions the content of those registers could be corrupted. Saving and restoring of the accumulators @@ -127,27 +127,27 @@ can be enabled by adding the -msave-acc-in-interrupts command line option. 5. Double Precision FPU Instructions Support -The RXv3 architecture supports an optional set of double precision instructions which -makes use of a new set of registers that must be saved and restored during context -switches. This feature can be accessed by adding the -mdfpu -m64bit-doubles compiler switches. +The RXv3 architecture supports an optional set of double precision instructions which +makes use of a new set of registers that must be saved and restored during context +switches. This feature can be accessed by adding the -mdfpu -m64bit-doubles compiler switches. To reduce the overhead of saving and restoring the FPU registers for all threads -the RXv3 port allows each thread to enable and disable saving and restoring the DFPU -registers. By default the feature is disabled for new threads. To enable the feature -tx_thread_fpu_enable() must be called within the context of every thread that will +the RXv3 port allows each thread to enable and disable saving and restoring the DFPU +registers. By default the feature is disabled for new threads. To enable the feature +tx_thread_fpu_enable() must be called within the context of every thread that will perform FPU operation. The saving and restoring of DFPU registers can be disabled again by calling tx_thread_fpu_disable(). This can be useful if a thread only makes occasional use of the FPU. - + 6. Improving Performance -The distribution version of ThreadX is built without any compiler optimizations. This -makes it easy to debug because you can trace or set breakpoints inside of ThreadX itself. -Of course, this costs some performance. To make ThreadX run faster, you can change the -ThreadX Library project to disable debug information and enable the desired optimizations. +The distribution version of ThreadX is built without any compiler optimizations. This +makes it easy to debug because you can trace or set breakpoints inside of ThreadX itself. +Of course, this costs some performance. To make ThreadX run faster, you can change the +ThreadX Library project to disable debug information and enable the desired optimizations. -In addition, you can eliminate the ThreadX basic API error checking by compiling your -application code with the symbol TX_DISABLE_ERROR_CHECKING defined before tx_api.h -is included. +In addition, you can eliminate the ThreadX basic API error checking by compiling your +application code with the symbol TX_DISABLE_ERROR_CHECKING defined before tx_api.h +is included. 7. Timer Processing @@ -159,18 +159,18 @@ a Renesas Fit CMT periodic timer module (r_cmt_rx) is used as the timer source. 8. Interrupt Handling -Interrupt handling is unaffected by the ThreadX port as such user interrupts can be +Interrupt handling is unaffected by the ThreadX port as such user interrupts can be written according to the toolchain's documentation. It is recommended not to use interrupt priority 1 as this is the priority of the context switch interrupt. However using interrupt -priority 1 won't cause any negative side effects but doing so may slightly reduce +priority 1 won't cause any negative side effects but doing so may slightly reduce performance. Please refer to the toolchain documentation for additional details on how to define interrupt service routines. 9. Execution Profiling -The RX port adds support for the Execution Profiling Kit (EPK). The EPK consists -of the files tx_execution_profile.c and tx_execution_profile.h. See the documentation +The RX port adds support for the Execution Profiling Kit (EPK). The EPK consists +of the files tx_execution_profile.c and tx_execution_profile.h. See the documentation of the EPK for generic usage details. To add the EPK to your RXv3 release make the following modifications: @@ -189,7 +189,7 @@ typedef unsigned long long EXECUTION_TIME; typedef unsigned long EXECUTION_TIME; #define TX_EXECUTION_MAX_TIME_SOURCE 0xFFFF #endif - + /* Define basic constants for the execution profile kit. */ #define TX_EXECUTION_TIME_SOURCE (EXECUTION_TIME) *((USHORT *) 0x8800A) diff --git a/ports/rxv3/gnu/src/tx_initialize_low_level.S b/ports/rxv3/gnu/src/tx_initialize_low_level.S index e0f89d99..3512d9c3 100644 --- a/ports/rxv3/gnu/src/tx_initialize_low_level.S +++ b/ports/rxv3/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -57,18 +57,6 @@ ;/* */ ;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ .global __tx_initialize_low_level __tx_initialize_low_level: diff --git a/ports/rxv3/gnu/src/tx_thread_context_restore.S b/ports/rxv3/gnu/src/tx_thread_context_restore.S index 2090fc48..8c8b42f0 100644 --- a/ports/rxv3/gnu/src/tx_thread_context_restore.S +++ b/ports/rxv3/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -73,19 +73,6 @@ ;/* */ ;/* ISRs Interrupt Service Routines */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* added FPU support, */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) ;{ diff --git a/ports/rxv3/gnu/src/tx_thread_context_save.S b/ports/rxv3/gnu/src/tx_thread_context_save.S index eb4caee0..3fbfc3a1 100644 --- a/ports/rxv3/gnu/src/tx_thread_context_save.S +++ b/ports/rxv3/gnu/src/tx_thread_context_save.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -66,18 +66,6 @@ ;/* */ ;/* ISRs */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) ;{ diff --git a/ports/rxv3/gnu/src/tx_thread_interrupt_control.S b/ports/rxv3/gnu/src/tx_thread_interrupt_control.S index 1111dc97..4dba35ef 100644 --- a/ports/rxv3/gnu/src/tx_thread_interrupt_control.S +++ b/ports/rxv3/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -60,18 +60,6 @@ ;/* */ ;/* Application Code */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) ;{ diff --git a/ports/rxv3/gnu/src/tx_thread_schedule.S b/ports/rxv3/gnu/src/tx_thread_schedule.S index f01b22bf..6165d7ef 100644 --- a/ports/rxv3/gnu/src/tx_thread_schedule.S +++ b/ports/rxv3/gnu/src/tx_thread_schedule.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -75,20 +75,6 @@ ;/* _tx_thread_system_return Return to system from thread */ ;/* _tx_thread_context_restore Restore thread's context */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* added FPU support, */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), and */ -;/* added low power support, */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) ;{ @@ -106,7 +92,7 @@ __tx_thread_schedule_loop: MOV.L [R1],R2 ; Pickup next thread to execute CMP #0,R2 ; Is it NULL? BNE __tx_thread_thread_ready ; Not NULL, schedule the thread - ; Idle system - no thread is ready + ; Idle system - no thread is ready #if (TX_LOW_POWER == 1) MOV.L #__tx_thread_preempt_disable, R1 ; Load prempt disable flag. MOV.L [R1], R2 @@ -135,7 +121,7 @@ __tx_thread_thread_ready: ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Note that interrupts are locked out at this point. */ ; ; /* Setup the current thread pointer. */ diff --git a/ports/rxv3/gnu/src/tx_thread_stack_build.S b/ports/rxv3/gnu/src/tx_thread_stack_build.S index a1398c51..5908e00f 100644 --- a/ports/rxv3/gnu/src/tx_thread_stack_build.S +++ b/ports/rxv3/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -63,18 +63,6 @@ ;/* */ ;/* _tx_thread_create Create thread service */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) ;{ diff --git a/ports/rxv3/gnu/src/tx_thread_system_return.S b/ports/rxv3/gnu/src/tx_thread_system_return.S index ecd7b205..c1106461 100644 --- a/ports/rxv3/gnu/src/tx_thread_system_return.S +++ b/ports/rxv3/gnu/src/tx_thread_system_return.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -67,19 +67,6 @@ ;/* */ ;/* ThreadX components */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* removed unused code, */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) ;{ diff --git a/ports/rxv3/gnu/src/tx_timer_interrupt.S b/ports/rxv3/gnu/src/tx_timer_interrupt.S index 5fd09f8f..bc09965d 100644 --- a/ports/rxv3/gnu/src/tx_timer_interrupt.S +++ b/ports/rxv3/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -85,20 +85,6 @@ ;/* */ ;/* interrupt vector */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), and */ -;/* added missing thread */ -;/* preemption logic, */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) ;{ diff --git a/ports/rxv3/iar/inc/tx_port.h b/ports/rxv3/iar/inc/tx_port.h index 624fec4d..e40be831 100644 --- a/ports/rxv3/iar/inc/tx_port.h +++ b/ports/rxv3/iar/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,45 +21,29 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ /* tx_port.h RXv3/IAR */ /* 6.1.11 */ /* */ -/* AUTHOR */ -/* */ +/* AUTHOR */ +/* */ /* William E. Lamie, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* 10-15-2021 William E. Lamie Modified comment(s), and */ -/* added FPU support, */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 William E. Lamie Modified comment(s), removed */ -/* system state macro, and */ -/* added missing interrupt */ -/* control defines, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comment(s), */ -/* resulting in version 6.1.11 */ -/* */ -/**************************************************************************/ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/**************************************************************************/ #ifndef TX_PORT_H #define TX_PORT_H @@ -71,13 +56,13 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" #endif -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -121,8 +106,8 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -147,7 +132,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -159,13 +144,13 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #define TX_THREAD_EXTENSION_2 ULONG tx_thread_fpu_enable; /* FPU Register Save Flag. */ -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -179,11 +164,11 @@ typedef unsigned short USHORT; #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -191,8 +176,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -218,9 +203,9 @@ typedef unsigned short USHORT; #define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -276,8 +261,8 @@ void tx_thread_fpu_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX RXv3/IAR Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv3/IAR Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/rxv3/iar/readme_threadx.txt b/ports/rxv3/iar/readme_threadx.txt index 2100d92d..e0564ae9 100644 --- a/ports/rxv3/iar/readme_threadx.txt +++ b/ports/rxv3/iar/readme_threadx.txt @@ -17,38 +17,38 @@ for the RXv3. 3. System Initialization -The system entry point using the IAR tools is at the label __iar_program_start. +The system entry point using the IAR tools is at the label __iar_program_start. -The vector area is setup in the file tx_initialize_low_level.s. This file is also -responsible for setting up various system data structures, interrupt vectors, and -the periodic timer interrupt. This file is also an ideal place add hardware +The vector area is setup in the file tx_initialize_low_level.s. This file is also +responsible for setting up various system data structures, interrupt vectors, and +the periodic timer interrupt. This file is also an ideal place add hardware initialization code. -The ThreadX demonstration for the RXv3 utilizes CMT0 as a periodic timer interrupt -source. The CMT0 interrupt is typically setup for 10ms periodic interrupts and the -interrupt priority level is set to level 5 with the symbol CMT_RX_CFG_IPR in -r_cmt_rx_config.h of Renesas CMT timer module(r_cmt_rx). You may change any of the +The ThreadX demonstration for the RXv3 utilizes CMT0 as a periodic timer interrupt +source. The CMT0 interrupt is typically setup for 10ms periodic interrupts and the +interrupt priority level is set to level 5 with the symbol CMT_RX_CFG_IPR in +r_cmt_rx_config.h of Renesas CMT timer module(r_cmt_rx). You may change any of the timer parameters as needed. -In addition, _tx_initialize_low_level determines the first available address for use -by the application, which is supplied as the sole input parameter to your application -definition function, tx_application_define. The first available memory is determined -by the location of the FREEMEM section so it should be placed AFTER all other RAM +In addition, _tx_initialize_low_level determines the first available address for use +by the application, which is supplied as the sole input parameter to your application +definition function, tx_application_define. The first available memory is determined +by the location of the FREEMEM section so it should be placed AFTER all other RAM sections in your linker control file. 4. Context Switch, Register Usage and Stack Frames The RXv3 port for ThreadX uses the first software interrupt, SWINT, i.e., interrupt #27, -to perform context switch with the interrupt priority level 1. This ISR is thus reserved -when using ThreadX and the SWINT should not be manipulated in any way by the application. -The port will setup the interrupt within _tx_initialize_low_level and the compiler will -automatically install the necessary interrupt vector. As such no additional initialization +to perform context switch with the interrupt priority level 1. This ISR is thus reserved +when using ThreadX and the SWINT should not be manipulated in any way by the application. +The port will setup the interrupt within _tx_initialize_low_level and the compiler will +automatically install the necessary interrupt vector. As such no additional initialization is necessary by the application. The following defines the saved context stack frame used by the ThreadX port. The -state of the CPU registers at the time of a context switch is saved on the running -thread's stack The top of the suspended thread's stack is pointed to by +state of the CPU registers at the time of a context switch is saved on the running +thread's stack The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Offset Stack Frame @@ -73,7 +73,7 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. 0x44 R2 0x48 PC - return address 0x4C PSW - + Offset Stack Frame with DFPU Register 0x00 DPSW @@ -116,38 +116,38 @@ tx_thread_stack_ptr in the associated thread control block TX_THREAD. 0x94 R2 0x98 PC - return address 0x9C PSW - - + + Note: By default IAR does not save the state of the accumulator registers ACC0 and ACC1 when entering an ISR. This means that if the ISR uses any of the DSP instructions the content of those registers could be corrupted. Saving and restoring of the acummulators can be enabled by adding the --save_acc command line option. - + 5. Double Precision FPU Instructions Support -The RXv3 architecture supports an optional set of double precision instructions which -makes use of a new set of registers that must be saved and restored during context +The RXv3 architecture supports an optional set of double precision instructions which +makes use of a new set of registers that must be saved and restored during context switches. This feature can be accessed by setting the size of double to 64 bit in the -compiler options. To reduce the overhead of saving and restoring the FPU registers -for all threads the RXv3 port allows each thread to enable and disable saving and -restoring the DFPU registers. By default the feature is disabled for new threads. -To enable the feature tx_thread_fpu_enable() must be called within the context of every +compiler options. To reduce the overhead of saving and restoring the FPU registers +for all threads the RXv3 port allows each thread to enable and disable saving and +restoring the DFPU registers. By default the feature is disabled for new threads. +To enable the feature tx_thread_fpu_enable() must be called within the context of every thread that will perform FPU operation. The saving and restoring of DFPU registers can -be disabled again by calling tx_thread_fpu_disable(). This can be useful if a thread +be disabled again by calling tx_thread_fpu_disable(). This can be useful if a thread only makes occasional use of the FPU. 6. Improving Performance -The distribution version of ThreadX is built without any compiler optimizations. This -makes it easy to debug because you can trace or set breakpoints inside of ThreadX itself. -Of course, this costs some performance. To make ThreadX run faster, you can change the -ThreadX Library project to disable debug information and enable the desired optimizations. +The distribution version of ThreadX is built without any compiler optimizations. This +makes it easy to debug because you can trace or set breakpoints inside of ThreadX itself. +Of course, this costs some performance. To make ThreadX run faster, you can change the +ThreadX Library project to disable debug information and enable the desired optimizations. -In addition, you can eliminate the ThreadX basic API error checking by compiling your -application code with the symbol TX_DISABLE_ERROR_CHECKING defined before tx_api.h -is included. +In addition, you can eliminate the ThreadX basic API error checking by compiling your +application code with the symbol TX_DISABLE_ERROR_CHECKING defined before tx_api.h +is included. 7. Timer Processing @@ -159,18 +159,18 @@ a Renesas Fit CMT periodic timer module (r_cmt_rx) is used as the timer source. 8. Interrupt Handling -Interrupt handling is unaffected by the ThreadX port as such user interrupts can be +Interrupt handling is unaffected by the ThreadX port as such user interrupts can be written according to the toolchain's documentation. It is recommended not to use interrupt priority 1 as this is the priority of the context switch interrupt. However using interrupt -priority 1 won't cause any negative side effectd but doing so may slightly reduce +priority 1 won't cause any negative side effectd but doing so may slightly reduce performance. Please refer to the toolchain documentation for additional details on how to define interrupt service routines. 9. Execution Profiling -The RX port adds support for the Execution Profiling Kit (EPK). The EPK consists -of the files tx_execution_profile.c and tx_execution_profile.h. See the documentation +The RX port adds support for the Execution Profiling Kit (EPK). The EPK consists +of the files tx_execution_profile.c and tx_execution_profile.h. See the documentation of the EPK for generic usage details. To add the EPK to your RXv3 release make the following modifications: @@ -189,7 +189,7 @@ typedef unsigned long long EXECUTION_TIME; typedef unsigned long EXECUTION_TIME; #define TX_EXECUTION_MAX_TIME_SOURCE 0xFFFF #endif - + /* Define basic constants for the execution profile kit. */ #define TX_EXECUTION_TIME_SOURCE (EXECUTION_TIME) *((USHORT *) 0x8800A) @@ -208,7 +208,7 @@ information associated with this specific port of ThreadX: tx_thread_schedule.s Added low power support 01-31-2022 Release 6.1.10 changes: - tx_port.h Removed system state macro, and added + tx_port.h Removed system state macro, and added missing interrupt control defines tx_timer_interrupt.s Added missing thread preemption logic diff --git a/ports/rxv3/iar/src/tx_initialize_low_level.s b/ports/rxv3/iar/src/tx_initialize_low_level.s index 5b0c04e5..c40b4300 100644 --- a/ports/rxv3/iar/src/tx_initialize_low_level.s +++ b/ports/rxv3/iar/src/tx_initialize_low_level.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -25,53 +25,41 @@ section .text:CODE:ROOT ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_initialize_low_level RXv3/IAR */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/**************************************************************************/ public __tx_initialize_low_level __tx_initialize_low_level: @@ -80,7 +68,7 @@ __tx_initialize_low_level: ; _tx_initialize_unused_memory = (VOID_PTR) &free_mem_start; ; MOV.L #__tx_free_memory_start, R1 ; Pickup unused memory address - MOV.L #__tx_initialize_unused_memory,R2 + MOV.L #__tx_initialize_unused_memory,R2 MOV.L R1,[R2] ; Save first free memory address ; /* Set priority of SWINT to 1. */ diff --git a/ports/rxv3/iar/src/tx_thread_context_restore.s b/ports/rxv3/iar/src/tx_thread_context_restore.s index 9306d159..f6d0e605 100644 --- a/ports/rxv3/iar/src/tx_thread_context_restore.s +++ b/ports/rxv3/iar/src/tx_thread_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,53 +39,40 @@ section .text:CODE:ROOT -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_context_restore RXv3/IAR */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* added FPU support, */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/**************************************************************************/ public __tx_thread_context_restore __tx_thread_context_restore: @@ -102,7 +89,7 @@ __tx_thread_context_restore: MOV.L [R1], R2 SUB #1, R2 MOV.L R2,[R1] - BEQ __tx_thread_not_nested_restore + BEQ __tx_thread_not_nested_restore ; ; /* Interrupts are nested. */ @@ -111,7 +98,7 @@ __tx_thread_context_restore: ; and return to the point of interrupt. */ ; __tx_thread_nested_restore: - POPC FPSW ; Restore FPU status + POPC FPSW ; Restore FPU status POPM R14-R15 ; Restore R14-R15 POPM R3-R5 ; Restore R3-R5 POPM R1-R2 ; Restore R1-R2 @@ -124,17 +111,17 @@ __tx_thread_not_nested_restore: ; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { - + MOV.L #__tx_thread_current_ptr, R1 ; Pickup current thread ptr address MOV.L [R1], R2 CMP #0, R2 - BEQ __tx_thread_idle_system_restore - + BEQ __tx_thread_idle_system_restore + MOV.L #__tx_thread_preempt_disable, R3 ; Pick up preempt disable flag MOV.L [R3], R3 CMP #0, R3 BNE __tx_thread_no_preempt_restore ; If pre-empt disable flag set, we simply return to the original point of interrupt regardless - + MOV.L #__tx_thread_execute_ptr, R3 ; (_tx_thread_current_ptr != _tx_thread_execute_ptr) CMP [R3], R2 BNE __tx_thread_preempt_restore ; Jump to pre-empt restoring @@ -175,7 +162,7 @@ __tx_thread_dont_save_ts: SETPSW U ; User stack PUSHM R6-R13 - + MVFACGU #0, A1, R4 ; Save accumulators. MVFACHI #0, A1, R5 MVFACLO #0, A1, R6 @@ -184,7 +171,7 @@ __tx_thread_dont_save_ts: MVFACHI #0, A0, R5 MVFACLO #0, A0, R6 PUSHM R4-R6 - + #if (__DPFPU == 1) MOV.L 144[R2], R4 ; Get tx_thread_fpu_enable. CMP #0, R4 diff --git a/ports/rxv3/iar/src/tx_thread_context_save.s b/ports/rxv3/iar/src/tx_thread_context_save.s index f6128347..91ac51a1 100644 --- a/ports/rxv3/iar/src/tx_thread_context_save.s +++ b/ports/rxv3/iar/src/tx_thread_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -33,51 +33,39 @@ extern __tx_thread_current_ptr section .text:CODE:ROOT -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_context_save RXv3/IAR */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) ;{ public __tx_thread_context_save @@ -104,7 +92,7 @@ __tx_thread_context_save: BEQ __tx_thread_not_nested_save ; ; /* Nested interrupt condition. */ -; +; ADD #1, r2 ; _tx_thread_system_state++ MOV.L r2, [r1] @@ -130,7 +118,7 @@ __tx_thread_not_nested_save: MOV.L #__tx_thread_current_ptr, R2 ; Pickup current thread pointer MOV.L [R2], R2 - CMP #0,R2 ; Is it NULL? + CMP #0,R2 ; Is it NULL? BEQ __tx_thread_idle_system_save ; Yes, idle system is running - idle restore ; ; /* Move stack frame over to the current threads stack. */ @@ -142,9 +130,9 @@ __tx_thread_not_nested_save: MOV.L 12[R0], R2 MOV.L R2, [-R1] ; Save PC on thread stack MOV.L 8[R0], R2 - MOV.L R2, [-R1] ; Save R2 on thread stack + MOV.L R2, [-R1] ; Save R2 on thread stack MOV.L 4[R0], R2 - MOV.L R2, [-R1] ; Save R1 on thread stack + MOV.L R2, [-R1] ; Save R1 on thread stack MOV.L R5, [-R1] ; Save R5 on thread stack MOV.L R4, [-R1] ; Save R4 on thread stack MOV.L R3, [-R1] ; Save R3 on thread stack @@ -152,9 +140,9 @@ __tx_thread_not_nested_save: MOV.L R14, [-R1] ; Save R14 on thread stack MVFC FPSW, R3 MOV.L R3, [-R1] ; Save FPSW on thread stack - + POP R2 ; Pick up return address from interrupt stack - ADD #16, R0, R0 ; Correct interrupt stack pointer back to the bottom + ADD #16, R0, R0 ; Correct interrupt stack pointer back to the bottom MVTC R1, USP ; Set user/thread stack pointer JMP R2 ; Return to ISR @@ -171,6 +159,6 @@ __tx_thread_idle_system_save: JMP R1 ; Return to caller ; ; } -;} +;} END diff --git a/ports/rxv3/iar/src/tx_thread_interrupt_control.s b/ports/rxv3/iar/src/tx_thread_interrupt_control.s index 9db56216..b642cd22 100644 --- a/ports/rxv3/iar/src/tx_thread_interrupt_control.s +++ b/ports/rxv3/iar/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -28,50 +28,38 @@ ;#include "tx_thread.h" ; section .text:CODE:ROOT -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_interrupt_control RXv3/IAR */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) ;{ public __tx_thread_interrupt_control @@ -79,20 +67,20 @@ __tx_thread_interrupt_control: ; ; /* Pickup current interrupt lockout posture. */ ; - + MVFC PSW, R2 ; Save PSW to R2 MOV.L R2, R3 ; Make a copy of PSW in r3 - + ; ; /* Apply the new interrupt posture. */ ; - + BTST #16, R1 ; Test I bit of PSW of "new posture" - BMNE #16, R2 ; Conditionally set I bit of intermediate posture - + BMNE #16, R2 ; Conditionally set I bit of intermediate posture + MVTC R2, PSW ; Save intermediate posture to PSW - - MOV.L R3,R1 ; Get original SR + + MOV.L R3,R1 ; Get original SR RTS ; Return to caller ;} END diff --git a/ports/rxv3/iar/src/tx_thread_schedule.s b/ports/rxv3/iar/src/tx_thread_schedule.s index 37f82438..5df75776 100644 --- a/ports/rxv3/iar/src/tx_thread_schedule.s +++ b/ports/rxv3/iar/src/tx_thread_schedule.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -41,52 +41,41 @@ section .text:CODE:ROOT -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_schedule RXv3/IAR */ ;/* 6.1.11 */ -;/* AUTHOR */ -;/* */ +;/* AUTHOR */ +;/* */ ;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLS */ -;/* */ +;/* */ +;/* OUTPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* added FPU support, */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* */ -;/**************************************************************************/ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) ;{ public __tx_thread_schedule @@ -104,7 +93,7 @@ __tx_thread_schedule_loop: MOV.L [R1],R2 ; Pickup next thread to execute CMP #0,R2 ; Is it NULL? BNE __tx_thread_thread_ready ; Not NULL, schedule the thread - ; Idle system - no thread is ready + ; Idle system - no thread is ready #if (TX_LOW_POWER == 1) MOV.L #__tx_thread_preempt_disable, R1 ; Load prempt disable flag. MOV.L [R1], R2 @@ -133,7 +122,7 @@ __tx_thread_thread_ready: ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Note that interrupts are locked out at this point. */ ; ; /* Setup the current thread pointer. */ @@ -145,7 +134,7 @@ __tx_thread_thread_ready: ; /* Increment the run count for this thread. */ ; _tx_thread_current_ptr -> tx_thread_run_count++; ; - MOV.L 4[R2],R3 ; Pickup run count + MOV.L 4[R2],R3 ; Pickup run count ADD #1,R3 ; Increment run counter MOV.L R3,4[R2] ; Store it back in control block ; @@ -154,7 +143,7 @@ __tx_thread_thread_ready: ; MOV.L 24[R2],R3 ; Pickup thread time-slice MOV.L #__tx_timer_time_slice,R4 ; Pickup pointer to time-slice - MOV.L R3, [R4] ; Setup time-slice + MOV.L R3, [R4] ; Setup time-slice ; ; /* Switch to the thread's stack. */ ; SP = _tx_thread_execute_ptr -> tx_thread_stack_ptr; @@ -180,12 +169,12 @@ __tx_thread_schedule_fpu_skip: MVTACLO R3, A1 MVTACHI R2, A1 MVTACGU R1, A1 - + POPM R6-R13 ; Recover interrupt stack frame - POPC FPSW + POPC FPSW POPM R14-R15 POPM R3-R5 - POPM R1-R2 + POPM R1-R2 RTE ; Return to point of interrupt, this restores PC and PSW ; diff --git a/ports/rxv3/iar/src/tx_thread_stack_build.s b/ports/rxv3/iar/src/tx_thread_stack_build.s index a5872e63..6a1064b0 100644 --- a/ports/rxv3/iar/src/tx_thread_stack_build.s +++ b/ports/rxv3/iar/src/tx_thread_stack_build.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -55,28 +55,16 @@ ;/* */ ;/* _tx_thread_create Create thread service */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ public __tx_thread_stack_build __tx_thread_stack_build: ; -; +; ; /* Build an interrupt frame. The form of the fake interrupt stack ; on the Renesas RX should look like the following after it is built: -; +; ; Stack Top: ACC0 ; ACC1 ; R6 @@ -112,22 +100,22 @@ __tx_thread_stack_build: MOV.L R2, [-R3] ; Initial PC MOV.L #0, R4 MOV.L R4,[-R3] ; Initial R2 ... - MOV.L R4,[-R3] ; Initial R1 ... + MOV.L R4,[-R3] ; Initial R1 ... MOV.L R4,[-R3] ; Initial R5 ... MOV.L R4,[-R3] ; Initial R4 ... - MOV.L R4,[-R3] ; Initial R3 ... + MOV.L R4,[-R3] ; Initial R3 ... MOV.L R4,[-R3] ; Initial R15 ... MOV.L R4,[-R3] ; Initial R14 ... MVFC FPSW, r4 MOV.L R4, [-R3] ; Initial FPSW MOV.L #0, R4 - MOV.L R4,[-R3] ; Initial R13 ... + MOV.L R4,[-R3] ; Initial R13 ... MOV.L R4,[-R3] ; Initial R12 ... MOV.L R4,[-R3] ; Initial R11 ... - MOV.L R4,[-R3] ; Initial R10 ... + MOV.L R4,[-R3] ; Initial R10 ... MOV.L R4,[-R3] ; Initial R9 ... MOV.L R4,[-R3] ; Initial R8 ... - MOV.L R4,[-R3] ; Initial R7 ... + MOV.L R4,[-R3] ; Initial R7 ... MOV.L R4,[-R3] ; Initial R6 ... MOV.L R4,[-R3] ; Accumulator 1 @@ -139,11 +127,11 @@ __tx_thread_stack_build: MOV.L R4,[-R3] ; /* Setup stack pointer. */ -; thread_ptr -> tx_thread_stack_ptr = R1; +; thread_ptr -> tx_thread_stack_ptr = R1; MOV.L R3, 8[R1] ; Store initial SP in thread control block RTS - + ;} END diff --git a/ports/rxv3/iar/src/tx_thread_system_return.s b/ports/rxv3/iar/src/tx_thread_system_return.s index 160d90c3..05d20217 100644 --- a/ports/rxv3/iar/src/tx_thread_system_return.s +++ b/ports/rxv3/iar/src/tx_thread_system_return.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -20,7 +20,7 @@ ;/**************************************************************************/ section .text:CODE:ROOT - + ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ @@ -54,18 +54,6 @@ ;/* */ ;/* ThreadX components */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ public __tx_thread_system_return diff --git a/ports/rxv3/iar/src/tx_timer_interrupt.s b/ports/rxv3/iar/src/tx_timer_interrupt.s index 78f0cf98..f96c2317 100644 --- a/ports/rxv3/iar/src/tx_timer_interrupt.s +++ b/ports/rxv3/iar/src/tx_timer_interrupt.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -74,20 +74,6 @@ SWI0 EQU 0x872E0 ;/* */ ;/* interrupt vector */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), and */ -;/* added missing thread */ -;/* preemption logic, */ -;/* resulting in version 6.1.10 */ -;/* 04-25-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.11 */ -;/* */ ;/**************************************************************************/ public __tx_timer_interrupt @@ -150,14 +136,14 @@ __tx_timer_no_time_slice: MOV.L [R2+], R1 ; pickup timer list entry, _tx_timer_current_ptr++ CMP #0, R1 ; Is timer pointer NULL? BEQ __tx_timer_no_timer ; Yes, no timer has expired - + ; ; /* Set expiration flag. */ ; _tx_timer_expired = TX_TRUE; ; MOV.L #__tx_timer_expired,R2 ; Build address of expired flag MOV.L #1, R1 ; Build expired value - MOV.L R1, [R2] + MOV.L R1, [R2] BRA __tx_timer_done ; Finished with timer processing ; ; } @@ -168,7 +154,7 @@ __tx_timer_no_timer: ; /* No timer expired, increment the timer pointer. */ ; _tx_timer_current_ptr++; ; -; /* R2 already contains __tx_timer_current_ptr++ */ +; /* R2 already contains __tx_timer_current_ptr++ */ ; ; /* Check for wrap-around. */ ; if (_tx_timer_current_ptr == _tx_timer_list_end) @@ -187,9 +173,9 @@ __tx_timer_no_timer: ; } ; __tx_timer_skip_wrap: - MOV.L #__tx_timer_current_ptr,R1 - MOV.L R2, [R1] ; Store in updated pointer in _tx_timer_current_ptr - + MOV.L #__tx_timer_current_ptr,R1 + MOV.L R2, [R1] ; Store in updated pointer in _tx_timer_current_ptr + __tx_timer_done: ; ; /* See if anything has expired. */ @@ -223,14 +209,14 @@ __tx_timer_dont_activate: ; /* Did time slice expire? */ ; if (_tx_timer_expired_time_slice) ; { -; +; MOV.L #__tx_timer_expired_time_slice, R1 ; Pickup time-slice expired flag addr MOV.L [R1], R1 ; Pickup actual flag CMP #0,R1 ; Has time-slice expired? BEQ __tx_timer_not_ts_expiration ; No, skip time-slice expiration ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BSR __tx_thread_time_slice ; Call time-slice processing @@ -249,7 +235,7 @@ __tx_timer_dont_activate: MOV.L #SWI0, R1 MOV.L #1, [R1] - + ; } ; __tx_timer_not_ts_expiration: diff --git a/ports/win32/vs_2019/example_build/sample_threadx/sample_threadx.c b/ports/win32/vs_2019/example_build/sample_threadx/sample_threadx.c index 46d2aff4..4bd7f5bc 100644 --- a/ports/win32/vs_2019/example_build/sample_threadx/sample_threadx.c +++ b/ports/win32/vs_2019/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -81,42 +81,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -124,23 +124,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -254,11 +254,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -317,7 +317,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -370,7 +370,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/win32/vs_2019/inc/tx_port.h b/ports/win32/vs_2019/inc/tx_port.h index e96bbf8a..2cd61b43 100644 --- a/ports/win32/vs_2019/inc/tx_port.h +++ b/ports/win32/vs_2019/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Win32/Visual */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Win32/Visual */ /* 6.1 */ /* */ /* AUTHOR */ @@ -32,21 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -59,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -114,7 +109,7 @@ #endif -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -128,7 +123,7 @@ typedef unsigned short USHORT; /* Add Win32 debug insert prototype. */ - + void _tx_win32_debug_entry_insert(char *action, char *file, unsigned long line); #ifndef TX_WIN32_DEBUG_ENABLE @@ -155,7 +150,7 @@ void _tx_win32_debug_entry_insert(char *action, char *file, unsigned long lin *ptr++ = value; \ } \ } - + /* Include windows include file. */ @@ -185,19 +180,19 @@ void _tx_win32_debug_entry_insert(char *action, char *file, unsigned long lin #define TX_TIMER_THREAD_STACK_SIZE 400 /* Default timer thread stack size - Not used in Win32 port! */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX port. */ +/* Define various constants for the ThreadX port. */ #define TX_INT_DISABLE 1 /* Disable interrupts */ #define TX_INT_ENABLE 0 /* Enable interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -215,7 +210,7 @@ void _tx_win32_debug_entry_insert(char *action, char *file, unsigned long lin /* Define the port-specific trace extension to pickup the Windows timer. */ -#define TX_TRACE_PORT_EXTENSION QueryPerformanceCounter((LARGE_INTEGER *)&_tx_win32_time_stamp); +#define TX_TRACE_PORT_EXTENSION QueryPerformanceCounter((LARGE_INTEGER *)&_tx_win32_time_stamp); /* Define the port specific options for the _tx_build_options variable. This variable indicates @@ -238,7 +233,7 @@ void _tx_initialize_start_interrupts(void); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION _tx_initialize_start_interrupts(); -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -250,7 +245,7 @@ void _tx_initialize_start_interrupts(void); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ #define TX_THREAD_EXTENSION_0 HANDLE tx_thread_win32_thread_handle; \ @@ -258,9 +253,9 @@ void _tx_initialize_start_interrupts(void); HANDLE tx_thread_win32_thread_run_semaphore; \ UINT tx_thread_win32_suspension_type; \ UINT tx_thread_win32_int_disabled_flag; -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -274,11 +269,11 @@ void _tx_initialize_start_interrupts(void); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -286,10 +281,10 @@ void _tx_initialize_start_interrupts(void); tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) #define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) -#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) /* Define the ThreadX object creation extensions for the remaining objects. */ @@ -387,9 +382,9 @@ HANDLE threadhandle; } -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -417,8 +412,8 @@ VOID _tx_thread_interrupt_restore(UINT previous_posture); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Win32/Visual Studio Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Win32/Visual Studio Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/win32/vs_2019/readme_threadx.txt b/ports/win32/vs_2019/readme_threadx.txt index 13ce3d33..2d17b995 100644 --- a/ports/win32/vs_2019/readme_threadx.txt +++ b/ports/win32/vs_2019/readme_threadx.txt @@ -1,26 +1,26 @@ - Microsoft's Azure RTOS ThreadX for Win32 + Microsoft's Azure RTOS ThreadX for Win32 Using the Visual Studio Tools 1. Open the ThreadX Project Workspace -In order to build the ThreadX library and the ThreadX demonstration first load +In order to build the ThreadX library and the ThreadX demonstration first load the Azure RTOS Workspace azure_rtos.sln, which is located inside the "example_build" -directory. +directory. 2. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply make the "tx" project active and -then select the build button. You should now observe the compilation of the -ThreadX library source. This project build produces the ThreadX library file +Building the ThreadX library is easy; simply make the "tx" project active and +then select the build button. You should now observe the compilation of the +ThreadX library source. This project build produces the ThreadX library file tx.lib. 3. Building the Demonstration System -You are now ready to run the ThreadX Win32 demonstration. Simply make the +You are now ready to run the ThreadX Win32 demonstration. Simply make the "sample_thread" project active and then select the build button. When the build is finished, select the run button from Visual Studio and observe various demonstration statistics being printed to the console window. You may also set @@ -29,15 +29,15 @@ breakpoints, single step, perform data watches, etc. 4. System Initialization -The system entry point is at main(), which is defined in the application. -Once the application calls tx_kernel_enter, ThreadX starts running and -performs various initialization duties prior to starting the scheduler. The +The system entry point is at main(), which is defined in the application. +Once the application calls tx_kernel_enter, ThreadX starts running and +performs various initialization duties prior to starting the scheduler. The Win32-specific initialization is done in the function _tx_initialize_low_level, -which is located in the file tx_initialize_low_level.c. This function is -responsible for setting up various system data structures and simulated +which is located in the file tx_initialize_low_level.c. This function is +responsible for setting up various system data structures and simulated interrupts - including the periodic timer interrupt source for ThreadX. -In addition, _tx_initialize_low_level determines the first available +In addition, _tx_initialize_low_level determines the first available address for use by the application. In Win32, this is basically done by using malloc to get a big block of memory from Windows. @@ -46,32 +46,32 @@ by using malloc to get a big block of memory from Windows. ThreadX for Win32 is implemented using Win32 threads. Each application thread in ThreadX actually runs as a Win32 thread. The determination of -which application thread to run is made by the ThreadX scheduler, which -itself is a Win32 thread. The ThreadX scheduler is the highest priority +which application thread to run is made by the ThreadX scheduler, which +itself is a Win32 thread. The ThreadX scheduler is the highest priority thread in the system. Interrupts in ThreadX/Win32 are also simulated by threads. A good example -is the ThreadX system timer interrupt, which can be found in +is the ThreadX system timer interrupt, which can be found in tx_initialize_low_level.c. 5.1 ThreadX Limitations -ThreadX for Win32 behaves in the same manner as ThreadX in an embedded -environment EXCEPT in the case of thread termination. Unfortunately, the +ThreadX for Win32 behaves in the same manner as ThreadX in an embedded +environment EXCEPT in the case of thread termination. Unfortunately, the Win32 API does not have a good mechanism to terminate threads and instead must rely on the thread itself terminating. Hence, threads in the ThreadX -Win32 implementation must have some ThreadX call periodically in their +Win32 implementation must have some ThreadX call periodically in their processing if they can be terminated by another ThreadX thread. 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make it run faster, you can change the tx project file to -enable all compiler optimizations. In addition, you can eliminate the -ThreadX basic API error checking by compiling your application code with the +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the tx project file to +enable all compiler optimizations. In addition, you can eliminate the +ThreadX basic API error checking by compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING defined. @@ -79,7 +79,7 @@ symbol TX_DISABLE_ERROR_CHECKING defined. ThreadX provides simulated interrupt handling with Win32 threads. Simulated interrupt threads may be created by the application or may be added to the -simulated timer interrupt defined in tx_initialize_low_level.c. The following +simulated timer interrupt defined in tx_initialize_low_level.c. The following format for creating simulated interrupts should be used: 7.1 Data structures @@ -116,7 +116,7 @@ in tx_initialize_low_level.c called _tx_initialize_start_interrupts or into the 7.4 Simulated Interrupt Thread Template The following is a template for the simulated interrupt thread. This interrupt will occur on -a periodic basis. +a periodic basis. DWORD WINAPI _sample_win32_interrupt(LPVOID *ptr) { @@ -135,7 +135,7 @@ DWORD WINAPI _sample_win32_interrupt(LPVOID *ptr) /* Call ThreadX context restore for interrupt completion. */ _tx_thread_context_restore(); - } + } } diff --git a/ports/win32/vs_2019/src/tx_initialize_low_level.c b/ports/win32/vs_2019/src/tx_initialize_low_level.c index b62d1615..dd364d06 100644 --- a/ports/win32/vs_2019/src/tx_initialize_low_level.c +++ b/ports/win32/vs_2019/src/tx_initialize_low_level.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Initialize */ /** */ @@ -43,7 +44,7 @@ extern TX_THREAD *_tx_thread_current_ptr; /* Define simulated timer interrupt. This is done inside a thread, which is - how other interrupts may be defined as well. See code below for an + how other interrupts may be defined as well. See code below for an example. */ UINT _tx_win32_timer_id; @@ -115,22 +116,22 @@ void _tx_win32_debug_entry_insert(char *action, char *file, unsigned long lin _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_current_thread = _tx_thread_current_ptr; if (_tx_thread_current_ptr) _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_current_thread_id = _tx_thread_current_ptr -> tx_thread_win32_thread_id; - else + else _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_current_thread_id = 0; _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_execute_thread = _tx_thread_execute_ptr; if (_tx_thread_execute_ptr) _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_execute_thread_id = _tx_thread_execute_ptr -> tx_thread_win32_thread_id; - else + else _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_execute_thread_id = 0; _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_running_id = GetCurrentThreadId(); /* Now move to the next entry. */ _tx_win32_debug_entry_index++; - + /* Determine if we need to wrap the list. */ if (_tx_win32_debug_entry_index >= TX_WIN32_DEBUG_EVENT_SIZE) { - + /* Yes, wrap the list! */ _tx_win32_debug_entry_index = 0; } @@ -156,50 +157,44 @@ VOID _tx_thread_context_restore(VOID); extern VOID *_tx_initialize_unused_memory; -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_initialize_low_level Win32/Visual */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Win32/Visual */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function is responsible for any low-level processor */ -/* initialization, including setting up interrupt vectors, setting */ -/* up a periodic timer interrupt source, saving the system stack */ -/* pointer for use in ISR processing later, and finding the first */ -/* available RAM memory address for tx_application_define. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* CreateMutex Win32 create mutex */ -/* CreateThread Win32 create thread */ -/* CreateSemaphore Win32 create semaphore */ -/* GetCurrentThreadId Win32 get current thread ID */ -/* SetProcessAffinityMask Win32 process affinity set */ -/* SetThreadPriority Win32 set thread priority */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* CreateMutex Win32 create mutex */ +/* CreateThread Win32 create thread */ +/* CreateSemaphore Win32 create semaphore */ +/* GetCurrentThreadId Win32 get current thread ID */ +/* SetProcessAffinityMask Win32 process affinity set */ +/* SetThreadPriority Win32 set thread priority */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ /* */ /**************************************************************************/ VOID _tx_initialize_low_level(VOID) @@ -213,7 +208,7 @@ VOID _tx_initialize_low_level(VOID) /* Limit this ThreadX simulation on Win32 to a single core. */ if (SetProcessAffinityMask( GetCurrentProcess(), 1 ) == 0) { - + /* Error restricting the process to one core. */ printf("ThreadX Win32 error restricting the process to one core!\n"); while(1) @@ -235,7 +230,7 @@ VOID _tx_initialize_low_level(VOID) _tx_win32_critical_section.tx_win32_critical_section_mutex_handle = CreateMutex(NULL, FALSE, NULL); _tx_win32_critical_section.tx_win32_critical_section_nested_count = 0; _tx_win32_critical_section.tx_win32_critical_section_owner = 0; - + /* Create the semaphore that regulates when the scheduler executes. */ _tx_win32_scheduler_semaphore = CreateSemaphore(NULL, 0, 1, NULL); @@ -247,7 +242,7 @@ VOID _tx_initialize_low_level(VOID) /* This routine is called after initialization is complete in order to start - all interrupt threads. Interrupt threads in addition to the timer may + all interrupt threads. Interrupt threads in addition to the timer may be added to this routine as well. */ void _tx_initialize_start_interrupts(void) diff --git a/ports/win32/vs_2019/src/tx_thread_context_restore.c b/ports/win32/vs_2019/src/tx_thread_context_restore.c index 3272348d..36fa1e4b 100644 --- a/ports/win32/vs_2019/src/tx_thread_context_restore.c +++ b/ports/win32/vs_2019/src/tx_thread_context_restore.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -30,47 +31,41 @@ #include "tx_timer.h" -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_context_restore Win32/Visual */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Win32/Visual */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function restores the interrupt context if it is processing a */ -/* nested interrupt. If not, it returns to the interrupt thread if no */ -/* preemption is necessary. Otherwise, if preemption is necessary or */ -/* if no thread was running, the function returns to the scheduler. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* ReleaseSemaphore Win32 release semaphore */ -/* ResumeThread Win32 resume thread */ -/* _tx_win32_critical_section_obtain Obtain critical section */ -/* _tx_win32_critical_section_release Release critical section */ -/* */ -/* CALLED BY */ -/* */ -/* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* ReleaseSemaphore Win32 release semaphore */ +/* ResumeThread Win32 resume thread */ +/* _tx_win32_critical_section_obtain Obtain critical section */ +/* _tx_win32_critical_section_release Release critical section */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ /* */ /**************************************************************************/ VOID _tx_thread_context_restore(VOID) @@ -97,7 +92,7 @@ VOID _tx_thread_context_restore(VOID) if ((_tx_thread_preempt_disable == 0) && (_tx_thread_current_ptr != _tx_thread_execute_ptr)) { - /* Preempt the running application thread. We don't need to suspend the + /* Preempt the running application thread. We don't need to suspend the application thread since that is done in the context save processing. */ /* Indicate that this thread was suspended asynchronously. */ diff --git a/ports/win32/vs_2019/src/tx_thread_context_save.c b/ports/win32/vs_2019/src/tx_thread_context_save.c index b39fc52c..2f4afb40 100644 --- a/ports/win32/vs_2019/src/tx_thread_context_save.c +++ b/ports/win32/vs_2019/src/tx_thread_context_save.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -30,45 +31,39 @@ #include "tx_timer.h" -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_context_save Win32/Visual */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Win32/Visual */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function saves the context of an executing thread in the */ -/* beginning of interrupt processing. The function also ensures that */ -/* the system stack is used upon return to the calling ISR. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* SuspendThread Win32 thread suspend */ -/* _tx_win32_critical_section_obtain Obtain critical section */ -/* _tx_win32_critical_section_release Release critical section */ -/* */ -/* CALLED BY */ -/* */ -/* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* SuspendThread Win32 thread suspend */ +/* _tx_win32_critical_section_obtain Obtain critical section */ +/* _tx_win32_critical_section_release Release critical section */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ /* */ /**************************************************************************/ VOID _tx_thread_context_save(VOID) diff --git a/ports/win32/vs_2019/src/tx_thread_interrupt_control.c b/ports/win32/vs_2019/src/tx_thread_interrupt_control.c index 5b99eeb8..019aabef 100644 --- a/ports/win32/vs_2019/src/tx_thread_interrupt_control.c +++ b/ports/win32/vs_2019/src/tx_thread_interrupt_control.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -49,49 +50,43 @@ VOID _tx_thread_interrupt_restore(UINT previous_posture) } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_interrupt_control Win32/Visual */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Win32/Visual */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function is responsible for changing the interrupt lockout */ -/* posture of the system. */ -/* */ -/* INPUT */ -/* */ -/* new_posture New interrupt lockout posture */ -/* */ -/* OUTPUT */ -/* */ -/* old_posture Old interrupt lockout posture */ -/* */ -/* CALLS */ -/* */ -/* ExitThread Win32 thread exit */ -/* GetCurrentThread Win32 get current thread */ -/* GetCurrentThreadId Win32 get current thread ID */ -/* GetThreadPriority Win32 get thread priority */ -/* _tx_win32_critical_section_obtain Obtain critical section */ -/* _tx_win32_critical_section_release Release critical section */ -/* _tx_win32_critical_section_release_all */ -/* Release critical section */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* ExitThread Win32 thread exit */ +/* GetCurrentThread Win32 get current thread */ +/* GetCurrentThreadId Win32 get current thread ID */ +/* GetThreadPriority Win32 get thread priority */ +/* _tx_win32_critical_section_obtain Obtain critical section */ +/* _tx_win32_critical_section_release Release critical section */ +/* _tx_win32_critical_section_release_all */ +/* Release critical section */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ UINT _tx_thread_interrupt_control(UINT new_posture) @@ -99,9 +94,9 @@ UINT _tx_thread_interrupt_control(UINT new_posture) UINT old_posture; HANDLE threadhandle; -int threadpriority; +int threadpriority; DWORD threadid; -TX_THREAD *thread_ptr; +TX_THREAD *thread_ptr; /* Enter Win32 critical section. */ @@ -116,7 +111,7 @@ TX_THREAD *thread_ptr; _tx_win32_debug_entry_insert("RESTORE", __FILE__, __LINE__); } else - { + { /* Disable. */ _tx_win32_debug_entry_insert("DISABLE", __FILE__, __LINE__); } @@ -131,24 +126,24 @@ TX_THREAD *thread_ptr; thread_ptr = _tx_thread_current_ptr; /* Pickup the priority of the current thread. */ - threadpriority = GetThreadPriority(threadhandle); + threadpriority = GetThreadPriority(threadhandle); /* Pickup the ID of the current thread. */ threadid = GetCurrentThreadId(); - /* Determine if this is a thread (THREAD_PRIORITY_LOWEST) and it does not + /* Determine if this is a thread (THREAD_PRIORITY_LOWEST) and it does not match the current thread pointer. */ - if ((threadpriority == THREAD_PRIORITY_LOWEST) && - ((!thread_ptr) || (thread_ptr -> tx_thread_win32_thread_id != threadid))) - { + if ((threadpriority == THREAD_PRIORITY_LOWEST) && + ((!thread_ptr) || (thread_ptr -> tx_thread_win32_thread_id != threadid))) + { - /* This indicates the Win32 thread was actually terminated by ThreadX is only + /* This indicates the Win32 thread was actually terminated by ThreadX is only being allowed to run in order to cleanup its resources. */ _tx_win32_critical_section_release_all(&_tx_win32_critical_section); /* Exit this thread. */ - ExitThread(0); - } + ExitThread(0); + } /* Determine the current interrupt lockout condition. */ if (_tx_win32_critical_section.tx_win32_critical_section_nested_count == 1) @@ -185,7 +180,7 @@ TX_THREAD *thread_ptr; _tx_win32_global_int_disabled_flag = TX_TRUE; } } - else if (thread_ptr) + else if (thread_ptr) { /* Determine how to apply the new posture. */ diff --git a/ports/win32/vs_2019/src/tx_thread_schedule.c b/ports/win32/vs_2019/src/tx_thread_schedule.c index 9b8092da..d67efee8 100644 --- a/ports/win32/vs_2019/src/tx_thread_schedule.c +++ b/ports/win32/vs_2019/src/tx_thread_schedule.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -30,48 +31,42 @@ #include "tx_timer.h" -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_schedule Win32/Visual */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Win32/Visual */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function waits for a thread control block pointer to appear in */ -/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -/* in the variable, the corresponding thread is resumed. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* ReleaseSemaphore Win32 release semaphore */ -/* ResumeThread Win32 resume thread */ -/* Sleep Win32 thread sleep */ -/* WaitForSingleObject Win32 wait on a semaphore */ -/* _tx_win32_critical_section_obtain Obtain critical section */ -/* _tx_win32_critical_section_release Release critical section */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* ReleaseSemaphore Win32 release semaphore */ +/* ResumeThread Win32 resume thread */ +/* Sleep Win32 thread sleep */ +/* WaitForSingleObject Win32 wait on a semaphore */ +/* _tx_win32_critical_section_obtain Obtain critical section */ +/* _tx_win32_critical_section_release Release critical section */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ /* */ /**************************************************************************/ VOID _tx_thread_schedule(VOID) @@ -93,7 +88,7 @@ VOID _tx_thread_schedule(VOID) /* Debug entry. */ _tx_win32_debug_entry_insert("SCHEDULE-wake_up", __FILE__, __LINE__); - /* Determine if there is a thread ready to execute AND all ISRs + /* Determine if there is a thread ready to execute AND all ISRs are complete. */ if ((_tx_thread_execute_ptr != TX_NULL) && (_tx_thread_system_state == 0)) { @@ -111,8 +106,8 @@ VOID _tx_thread_schedule(VOID) Sleep(2); } } - - /* Yes! We have a thread to execute. Note that the critical section is already + + /* Yes! We have a thread to execute. Note that the critical section is already active from the scheduling loop above. */ /* Setup the current thread pointer. */ @@ -168,12 +163,12 @@ TX_THREAD *thread_ptr; /* Is the protection owned? */ if (critical_section -> tx_win32_critical_section_owner == GetCurrentThreadId()) { - + /* Simply increment the nested counter. */ critical_section -> tx_win32_critical_section_nested_count++; } else - { + { /* Pickup the current thread pointer. */ thread_ptr = _tx_thread_current_ptr; @@ -182,12 +177,12 @@ TX_THREAD *thread_ptr; while (WaitForSingleObject(critical_section -> tx_win32_critical_section_mutex_handle, 3) != WAIT_OBJECT_0) { } - + /* At this point we have the mutex. */ - + /* Increment the nesting counter. */ critical_section -> tx_win32_critical_section_nested_count = 1; - + /* Remember the owner. */ critical_section -> tx_win32_critical_section_owner = GetCurrentThreadId(); } @@ -201,25 +196,25 @@ void _tx_win32_critical_section_release(TX_WIN32_CRITICAL_SECTION *critical_s /* Ensure the caller is the mutex owner. */ if (critical_section -> tx_win32_critical_section_owner == GetCurrentThreadId()) { - + /* Determine if there is protection. */ if (critical_section -> tx_win32_critical_section_nested_count) { - + /* Decrement the nesting counter. */ critical_section -> tx_win32_critical_section_nested_count--; - + /* Determine if the critical section is now being released. */ if (critical_section -> tx_win32_critical_section_nested_count == 0) { - + /* Yes, it is being released clear the owner. */ critical_section -> tx_win32_critical_section_owner = 0; /* Finally, release the mutex. */ if (ReleaseMutex(critical_section -> tx_win32_critical_section_mutex_handle) != TX_TRUE) { - + /* Increment the system error counter. */ _tx_win32_system_error++; } @@ -239,7 +234,7 @@ void _tx_win32_critical_section_release(TX_WIN32_CRITICAL_SECTION *critical_s } else { - + /* Increment the system error counter. */ _tx_win32_system_error++; } @@ -252,14 +247,14 @@ void _tx_win32_critical_section_release_all(TX_WIN32_CRITICAL_SECTION *cri /* Ensure the caller is the mutex owner. */ if (critical_section -> tx_win32_critical_section_owner == GetCurrentThreadId()) { - + /* Determine if there is protection. */ if (critical_section -> tx_win32_critical_section_nested_count) { - + /* Clear the nesting counter. */ critical_section -> tx_win32_critical_section_nested_count = 0; - + /* Yes, it is being release clear the owner. */ critical_section -> tx_win32_critical_section_owner = 0; @@ -270,7 +265,7 @@ void _tx_win32_critical_section_release_all(TX_WIN32_CRITICAL_SECTION *cri /* Increment the system error counter. */ _tx_win32_system_error++; } - + /* Just in case, make sure there the mutex is not owned. */ while (ReleaseMutex(critical_section -> tx_win32_critical_section_mutex_handle) == TX_TRUE) { @@ -282,7 +277,7 @@ void _tx_win32_critical_section_release_all(TX_WIN32_CRITICAL_SECTION *cri } else { - + /* Increment the system error counter. */ _tx_win32_system_error++; } diff --git a/ports/win32/vs_2019/src/tx_thread_stack_build.c b/ports/win32/vs_2019/src/tx_thread_stack_build.c index 55b74c2b..da51e7c4 100644 --- a/ports/win32/vs_2019/src/tx_thread_stack_build.c +++ b/ports/win32/vs_2019/src/tx_thread_stack_build.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -35,47 +36,41 @@ DWORD WINAPI _tx_win32_thread_entry(LPVOID p); -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_stack_build Win32/Visual */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Win32/Visual */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ +/* */ /* This function builds a stack frame on the supplied thread's stack. */ /* The stack frame results in a fake interrupt return to the supplied */ -/* function pointer. */ -/* */ -/* INPUT */ -/* */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ /* thread_ptr Pointer to thread control blk */ /* function_ptr Pointer to return function */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* CreateThread Win32 create thread */ -/* ResumeThread Win32 resume thread */ -/* SetThreadPriority Win32 set thread priority */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_thread_create Create thread service */ -/* _tx_thread_reset Reset thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* CreateThread Win32 create thread */ +/* ResumeThread Win32 resume thread */ +/* SetThreadPriority Win32 set thread priority */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* _tx_thread_reset Reset thread service */ /* */ /**************************************************************************/ VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -83,7 +78,7 @@ VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) /* Create a Win32 thread for the application thread. */ thread_ptr -> tx_thread_win32_thread_handle = - CreateThread(NULL, 0, _tx_win32_thread_entry, (LPVOID) thread_ptr, CREATE_SUSPENDED, + CreateThread(NULL, 0, _tx_win32_thread_entry, (LPVOID) thread_ptr, CREATE_SUSPENDED, &(thread_ptr -> tx_thread_win32_thread_id)); /* Check for a good thread create. */ @@ -116,11 +111,11 @@ VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) } } - /* Setup the thread suspension type to solicited thread suspension. + /* Setup the thread suspension type to solicited thread suspension. Pseudo interrupt handlers will suspend with this field set to 1. */ thread_ptr -> tx_thread_win32_suspension_type = 0; - /* Clear the disabled count that will keep track of the + /* Clear the disabled count that will keep track of the tx_interrupt_control nesting. */ thread_ptr -> tx_thread_win32_int_disabled_flag = 0; diff --git a/ports/win32/vs_2019/src/tx_thread_system_return.c b/ports/win32/vs_2019/src/tx_thread_system_return.c index c5870ee2..60176135 100644 --- a/ports/win32/vs_2019/src/tx_thread_system_return.c +++ b/ports/win32/vs_2019/src/tx_thread_system_return.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -30,53 +31,47 @@ #include -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_system_return Win32/Visual */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Win32/Visual */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function is target processor specific. It is used to transfer */ -/* control from a thread back to the system. Only a minimal context */ -/* is saved since the compiler assumes temp registers are going to get */ -/* slicked by a function call anyway. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_win32_critical_section_obtain Obtain critical section */ -/* _tx_win32_critical_section_release Release critical section */ -/* _tx_win32_critical_section_release_all */ -/* Release critical section */ -/* ExitThread Win32 thread exit */ -/* GetCurrentThread Win32 get current thread */ -/* GetCurrentThreadId Win32 get current thread ID */ -/* GetThreadPriority Win32 get thread priority */ -/* ReleaseSemaphore Win32 release semaphore */ -/* WaitForSingleObject Win32 wait on semaphore */ -/* */ -/* CALLED BY */ -/* */ -/* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the system. Only a minimal context */ +/* is saved since the compiler assumes temp registers are going to get */ +/* slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_win32_critical_section_obtain Obtain critical section */ +/* _tx_win32_critical_section_release Release critical section */ +/* _tx_win32_critical_section_release_all */ +/* Release critical section */ +/* ExitThread Win32 thread exit */ +/* GetCurrentThread Win32 get current thread */ +/* GetCurrentThreadId Win32 get current thread ID */ +/* GetThreadPriority Win32 get thread priority */ +/* ReleaseSemaphore Win32 release semaphore */ +/* WaitForSingleObject Win32 wait on semaphore */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ /* */ /**************************************************************************/ VOID _tx_thread_system_return(VOID) @@ -86,7 +81,7 @@ TX_THREAD *temp_thread_ptr; HANDLE temp_run_semaphore; UINT temp_thread_state; HANDLE threadhandle; -int threadpriority; +int threadpriority; DWORD threadid; @@ -102,7 +97,7 @@ DWORD threadid; /* First, determine if the thread was terminated. */ /* Pickup the priority of the current thread. */ - threadpriority = GetThreadPriority(threadhandle); + threadpriority = GetThreadPriority(threadhandle); /* Pickup the ID of the current thread. */ threadid = GetCurrentThreadId(); @@ -110,21 +105,21 @@ DWORD threadid; /* Pickup the current thread pointer. */ temp_thread_ptr = _tx_thread_current_ptr; - /* Determine if this is a thread (THREAD_PRIORITY_LOWEST) and it does not + /* Determine if this is a thread (THREAD_PRIORITY_LOWEST) and it does not match the current thread pointer. */ - if ((threadpriority == THREAD_PRIORITY_LOWEST) && - ((!temp_thread_ptr) || (temp_thread_ptr -> tx_thread_win32_thread_id != threadid))) - { + if ((threadpriority == THREAD_PRIORITY_LOWEST) && + ((!temp_thread_ptr) || (temp_thread_ptr -> tx_thread_win32_thread_id != threadid))) + { - /* This indicates the Win32 thread was actually terminated by ThreadX and is only + /* This indicates the Win32 thread was actually terminated by ThreadX and is only being allowed to run in order to cleanup its resources. */ - + /* Release critical section. */ _tx_win32_critical_section_release_all(&_tx_win32_critical_section); - + /* Exit thread. */ - ExitThread(0); - } + ExitThread(0); + } /* Determine if the time-slice is active. */ if (_tx_timer_time_slice) @@ -181,19 +176,19 @@ DWORD threadid; /* Pickup the current thread pointer. */ temp_thread_ptr = _tx_thread_current_ptr; - /* Determine if this is a thread (THREAD_PRIORITY_LOWEST) and it does not + /* Determine if this is a thread (THREAD_PRIORITY_LOWEST) and it does not match the current thread pointer. */ - if ((threadpriority == THREAD_PRIORITY_LOWEST) && - ((!temp_thread_ptr) || (temp_thread_ptr -> tx_thread_win32_thread_id != threadid))) - { + if ((threadpriority == THREAD_PRIORITY_LOWEST) && + ((!temp_thread_ptr) || (temp_thread_ptr -> tx_thread_win32_thread_id != threadid))) + { /* Leave Win32 critical section. */ _tx_win32_critical_section_release_all(&_tx_win32_critical_section); - /* This indicates the Win32 thread was actually terminated by ThreadX and is only + /* This indicates the Win32 thread was actually terminated by ThreadX and is only being allowed to run in order to cleanup its resources. */ - ExitThread(0); - } + ExitThread(0); + } /* Now determine if the application thread last had interrupts disabled. */ diff --git a/ports/win32/vs_2019/src/tx_timer_interrupt.c b/ports/win32/vs_2019/src/tx_timer_interrupt.c index 7830536d..a60ad144 100644 --- a/ports/win32/vs_2019/src/tx_timer_interrupt.c +++ b/ports/win32/vs_2019/src/tx_timer_interrupt.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Timer */ /** */ @@ -29,48 +30,42 @@ #include "tx_thread.h" -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_timer_interrupt Win32/Visual */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Win32/Visual */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function processes the hardware timer interrupt. This */ -/* processing includes incrementing the system clock and checking for */ -/* time slice and/or timer expiration. If either is found, the */ -/* interrupt context save/restore functions are called along with the */ -/* expiration functions. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_thread_time_slice Time slice interrupted thread */ -/* _tx_timer_expiration_process Timer expiration processing */ -/* _tx_win32_critical_section_obtain Obtain critical section */ -/* _tx_win32_critical_section_release Release critical section */ -/* */ -/* CALLED BY */ -/* */ -/* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_win32_critical_section_obtain Obtain critical section */ +/* _tx_win32_critical_section_release Release critical section */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ /* */ /**************************************************************************/ VOID _tx_timer_interrupt(VOID) diff --git a/ports/xtensa/xcc/example_build/demo_threadx.c b/ports/xtensa/xcc/example_build/demo_threadx.c index 5bec9cc8..72632323 100644 --- a/ports/xtensa/xcc/example_build/demo_threadx.c +++ b/ports/xtensa/xcc/example_build/demo_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include @@ -84,42 +84,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -127,23 +127,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -250,11 +250,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -313,7 +313,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -366,7 +366,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports/xtensa/xcc/inc/tx_api_asm.h b/ports/xtensa/xcc/inc/tx_api_asm.h index 5d4c8003..8eed6752 100644 --- a/ports/xtensa/xcc/inc/tx_api_asm.h +++ b/ports/xtensa/xcc/inc/tx_api_asm.h @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -22,12 +22,6 @@ /* which usually means port-specific since a compiler's struct */ /* packing rules depend on properties of the target architecture. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */ -/* */ /**************************************************************************/ #ifndef TX_API_ASM_H diff --git a/ports/xtensa/xcc/inc/tx_port.h b/ports/xtensa/xcc/inc/tx_port.h index 03517ea0..a8897815 100644 --- a/ports/xtensa/xcc/inc/tx_port.h +++ b/ports/xtensa/xcc/inc/tx_port.h @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -30,18 +30,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 11-09-2020 Cadence Design Systems Initial Version 6.1.2 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s), updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 10-31-2022 Scott Larson Modified comment(s), removed */ -/* EPK extension, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -470,7 +458,7 @@ extern int xt_timer_intnum; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * Azure RTOS Xtensa Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * Azure RTOS Xtensa Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/xtensa/xcc/inc/tx_user.h b/ports/xtensa/xcc/inc/tx_user.h index 38f2ac05..6a1dc181 100644 --- a/ports/xtensa/xcc/inc/tx_user.h +++ b/ports/xtensa/xcc/inc/tx_user.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** User Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_user.h PORTABLE C */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_user.h PORTABLE C */ /* 6.0.1 */ /* */ /* AUTHOR */ @@ -32,18 +33,12 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains user defines for configuring ThreadX in specific */ -/* ways. This file will have an effect only if the application and */ -/* ThreadX library are built with TX_INCLUDE_USER_DEFINE_FILE defined. */ -/* Note that all the defines in this file may also be made on the */ -/* command line when building ThreadX library and application objects. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* This file contains user defines for configuring ThreadX in specific */ +/* ways. This file will have an effect only if the application and */ +/* ThreadX library are built with TX_INCLUDE_USER_DEFINE_FILE defined. */ +/* Note that all the defines in this file may also be made on the */ +/* command line when building ThreadX library and application objects. */ /* */ /**************************************************************************/ @@ -52,12 +47,12 @@ /* Define various build options for the ThreadX port. The application should either make changes - here by commenting or un-commenting the conditional compilation defined OR supply the defines - though the compiler's equivalent of the -D option. - + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. + For maximum speed, the following should be defined: - TX_MAX_PRIORITIES 32 + TX_MAX_PRIORITIES 32 TX_DISABLE_PREEMPTION_THRESHOLD TX_DISABLE_REDUNDANT_CLEARING TX_DISABLE_NOTIFY_CALLBACKS @@ -66,21 +61,21 @@ TX_REACTIVATE_INLINE TX_DISABLE_STACK_FILLING TX_INLINE_THREAD_RESUME_SUSPEND - + For minimum size, the following should be defined: - - TX_MAX_PRIORITIES 32 + + TX_MAX_PRIORITIES 32 TX_DISABLE_PREEMPTION_THRESHOLD TX_DISABLE_REDUNDANT_CLEARING TX_DISABLE_NOTIFY_CALLBACKS TX_NOT_INTERRUPTABLE TX_TIMER_PROCESS_IN_ISR - + Of course, many of these defines reduce functionality and/or change the behavior of the system in ways that may not be worth the trade-off. For example, the TX_TIMER_PROCESS_IN_ISR results in faster and smaller code, however, it increases the amount of processing in the ISR. In addition, some services that are available in timers are not available from ISRs and will - therefore return an error if this option is used. This may or may not be desirable for a + therefore return an error if this option is used. This may or may not be desirable for a given application. */ @@ -88,16 +83,16 @@ to tx_port.h for descriptions on each of these options. */ /* -#define TX_MAX_PRIORITIES 32 -#define TX_MINIMUM_STACK ???? +#define TX_MAX_PRIORITIES 32 +#define TX_MINIMUM_STACK ???? #define TX_THREAD_USER_EXTENSION ???? #define TX_TIMER_THREAD_STACK_SIZE ???? #define TX_TIMER_THREAD_PRIORITY ???? */ -/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls - should be processed within the a system timer thread or directly in the timer ISR. - By default, the timer thread is used. When the following is defined, the timer expiration +/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls + should be processed within the a system timer thread or directly in the timer ISR. + By default, the timer thread is used. When the following is defined, the timer expiration processing is done directly from the timer ISR, thereby eliminating the timer thread control block, stack, and context switching to activate it. */ @@ -108,10 +103,10 @@ /* Determine if in-line timer reactivation should be used within the timer expiration processing. By default, this is disabled and a function call is used. When the following is defined, reactivating is performed in-line resulting in faster timer processing but slightly larger - code size. */ + code size. */ /* -#define TX_REACTIVATE_INLINE +#define TX_REACTIVATE_INLINE */ /* Determine is stack filling is enabled. By default, ThreadX stack filling is enabled, @@ -119,10 +114,10 @@ debuggers with ThreadX-awareness and by the ThreadX run-time stack checking feature. */ /* -#define TX_DISABLE_STACK_FILLING +#define TX_DISABLE_STACK_FILLING */ -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -132,7 +127,7 @@ #define TX_ENABLE_STACK_CHECKING */ -/* Determine if preemption-threshold should be disabled. By default, preemption-threshold is +/* Determine if preemption-threshold should be disabled. By default, preemption-threshold is enabled. If the application does not use preemption-threshold, it may be disabled to reduce code size and improve performance. */ @@ -140,7 +135,7 @@ #define TX_DISABLE_PREEMPTION_THRESHOLD */ -/* Determine if global ThreadX variables should be cleared. If the compiler startup code clears +/* Determine if global ThreadX variables should be cleared. If the compiler startup code clears the .bss section prior to ThreadX running, the define can be used to eliminate unnecessary clearing of ThreadX global variables. */ @@ -148,13 +143,13 @@ #define TX_DISABLE_REDUNDANT_CLEARING */ -/* Determine if no timer processing is required. This option will help eliminate the timer - processing when not needed. The user will also have to comment out the call to - tx_timer_interrupt, which is typically made from assembly language in +/* Determine if no timer processing is required. This option will help eliminate the timer + processing when not needed. The user will also have to comment out the call to + tx_timer_interrupt, which is typically made from assembly language in tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR must also be used. */ -/* +/* #define TX_NO_TIMER #ifndef TX_TIMER_PROCESS_IN_ISR #define TX_TIMER_PROCESS_IN_ISR @@ -170,8 +165,8 @@ */ -/* Determine if the tx_thread_resume and tx_thread_suspend services should have their internal - code in-line. This results in a larger image, but improves the performance of the thread +/* Determine if the tx_thread_resume and tx_thread_suspend services should have their internal + code in-line. This results in a larger image, but improves the performance of the thread resume and suspend services. */ /* @@ -179,7 +174,7 @@ */ -/* Determine if the internal ThreadX code is non-interruptable. This results in smaller code +/* Determine if the internal ThreadX code is non-interruptable. This results in smaller code size and less processing overhead, but increases the interrupt lockout time. */ /* @@ -187,8 +182,8 @@ */ -/* Determine if the trace event logging code should be enabled. This causes slight increases in - code size and overhead, but provides the ability to generate system trace information which +/* Determine if the trace event logging code should be enabled. This causes slight increases in + code size and overhead, but provides the ability to generate system trace information which is available for viewing in TraceX. */ /* diff --git a/ports/xtensa/xcc/inc/xtensa_api.h b/ports/xtensa/xcc/inc/xtensa_api.h index 10255838..28f3e528 100644 --- a/ports/xtensa/xcc/inc/xtensa_api.h +++ b/ports/xtensa/xcc/inc/xtensa_api.h @@ -63,7 +63,7 @@ extern xt_exc_handler xt_set_exception_handler(uint32_t n, xt_exc_handler f); /* ------------------------------------------------------------------------------- Call this function to set a handler for the specified interrupt. - + n - Interrupt number. f - Handler function address, NULL to uninstall handler. arg - Argument to be passed to handler. diff --git a/ports/xtensa/xcc/inc/xtensa_context.h b/ports/xtensa/xcc/inc/xtensa_context.h index 2ec96ecf..11174fff 100644 --- a/ports/xtensa/xcc/inc/xtensa_context.h +++ b/ports/xtensa/xcc/inc/xtensa_context.h @@ -82,16 +82,16 @@ INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT A stack frame of this structure is allocated for any interrupt or exception. - It goes on the current stack. If the RTOS has a system stack for handling - interrupts, every thread stack must allow space for just one interrupt stack + It goes on the current stack. If the RTOS has a system stack for handling + interrupts, every thread stack must allow space for just one interrupt stack frame, then nested interrupt stack frames go on the system stack. - The frame includes basic registers (explicit) and "extra" registers introduced + The frame includes basic registers (explicit) and "extra" registers introduced by user TIE or the use of the MAC16 option in the user's Xtensa config. The frame size is minimized by omitting regs not applicable to user's config. For Windowed ABI, this stack frame includes the interruptee's base save area, - another base save area to manage gcc nested functions, and a little temporary + another base save area to manage gcc nested functions, and a little temporary space to help manage the spilling of the register windows. ------------------------------------------------------------------------------- */ @@ -206,7 +206,7 @@ XSTRUCT_END(XtExcFrame) #else /* No extra storage required */ -#define XT_STK_NEXT2 XT_STK_NEXT1 +#define XT_STK_NEXT2 XT_STK_NEXT1 #endif @@ -252,7 +252,7 @@ XSTRUCT_END(XtExcFrame) and the context switch of that co-processor is then peformed by the handler. Ownership represents which thread's state is currently in the co-processor. - Co-processors may not be used by interrupt or exception handlers. If an + Co-processors may not be used by interrupt or exception handlers. If an co-processor instruction is executed by an interrupt or exception handler, the co-processor exception handler will trigger a kernel panic and freeze. This restriction is introduced to reduce the overhead of saving and restoring @@ -263,7 +263,7 @@ XSTRUCT_END(XtExcFrame) such as in the thread control block or above the thread stack area. It need not be in the interrupt stack frame since interrupts don't use co-processors. - Along with the save area for each co-processor, two bitmasks with flags per + Along with the save area for each co-processor, two bitmasks with flags per co-processor (laid out as in the CPENABLE reg) help manage context-switching co-processors as efficiently as possible: @@ -279,10 +279,10 @@ XSTRUCT_END(XtExcFrame) XT_CPSTORED A bitmask with the same layout as CPENABLE, a bit per co-processor. - Indicates whether the state of each co-processor is saved in the state + Indicates whether the state of each co-processor is saved in the state save area. When a thread enters the kernel, only the state of co-procs - still enabled in CPENABLE is saved. When the co-processor exception - handler assigns ownership of a co-processor to a thread, it restores + still enabled in CPENABLE is saved. When the co-processor exception + handler assigns ownership of a co-processor to a thread, it restores the saved state only if this bit is set, and clears this bit. XT_CP_CS_ST @@ -338,7 +338,7 @@ XSTRUCT_END(XtExcFrame) For framed functions the frame is created and the return address saved at base of frame (Call0 ABI) or as determined by hardware (Windowed ABI). For frameless functions, there is no frame and return address remains in a0. - Note: Because CPP macros expand to a single line, macros requiring multi-line + Note: Because CPP macros expand to a single line, macros requiring multi-line expansions are implemented as assembler macros. ------------------------------------------------------------------------------- */ @@ -351,7 +351,7 @@ XSTRUCT_END(XtExcFrame) addi sp, sp, -\size s32i a0, sp, 0 .endm - #define ENTRY0 + #define ENTRY0 #define RET(sz) ret1 sz .macro ret1 size=0x10 l32i a0, sp, 0 diff --git a/ports/xtensa/xcc/inc/xtensa_rtos.h b/ports/xtensa/xcc/inc/xtensa_rtos.h index 14e6cb22..d8db73bc 100644 --- a/ports/xtensa/xcc/inc/xtensa_rtos.h +++ b/ports/xtensa/xcc/inc/xtensa_rtos.h @@ -33,8 +33,8 @@ Macros in this header map callouts from generic Xtensa files to specific RTOS functions. It may also be included in C source files. - Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa - architecture, using the Xtensa hardware abstraction layer (HAL) to deal + Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa + architecture, using the Xtensa hardware abstraction layer (HAL) to deal with configuration specifics. Should be included by all Xtensa generic and RTOS port-specific sources. @@ -88,7 +88,7 @@ Some of these functions may call back to generic functions in xtensa_context.h . ***************************************************************************/ /* -Inform RTOS of entry into an interrupt handler that will affect it. +Inform RTOS of entry into an interrupt handler that will affect it. Allows RTOS to manage switch to any system stack and count nesting level. Called after minimal context has been saved, with interrupts disabled. RTOS port can call0 _xt_context_save to save the rest of the context. @@ -132,12 +132,12 @@ May be coded in or called from C or assembly, per ABI conventions. #endif /* -Return in a15 the base address of the co-processor state save area for the +Return in a15 the base address of the co-processor state save area for the thread that triggered a co-processor exception, or 0 if no thread was running. -The state save area is structured as defined in xtensa_context.h and has size +The state save area is structured as defined in xtensa_context.h and has size XT_CP_SIZE. Co-processor instructions should only be used in thread code, never in interrupt handlers or the RTOS kernel. May only be called from assembly code -and by the 'call0' instruction. A result of 0 indicates an unrecoverable error. +and by the 'call0' instruction. A result of 0 indicates an unrecoverable error. The implementation may use only a2-4, a15 (all other regs must be preserved). */ // void* XT_RTOS_CP_STATE(void) @@ -153,7 +153,7 @@ and interrupt handlers to facilitate automated testing where each test case can install its own handler for user exceptions and each interrupt priority (level). This consists of an array of function pointers indexed by interrupt priority, with index 0 being the user exception handler hook. -Each entry in the array is initially 0, and may be replaced by a function +Each entry in the array is initially 0, and may be replaced by a function pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0. The handler for low and medium priority obeys ABI conventions so may be coded diff --git a/ports/xtensa/xcc/inc/xtensa_timer.h b/ports/xtensa/xcc/inc/xtensa_timer.h index d5a29ed5..957a42ed 100644 --- a/ports/xtensa/xcc/inc/xtensa_timer.h +++ b/ports/xtensa/xcc/inc/xtensa_timer.h @@ -64,12 +64,12 @@ select timer 0. #else /* XEA2 */ /* -Select timer to use for periodic tick, and determine its interrupt number +Select timer to use for periodic tick, and determine its interrupt number and priority. User may specify a timer by defining XT_TIMER_INDEX with -D, -in which case its validity is checked (it must exist in this core and must +in which case its validity is checked (it must exist in this core and must not be on a high priority interrupt - an error will be reported in invalid). Otherwise select the first low or medium priority interrupt timer available. -*/ +*/ #ifndef XT_TIMER_INDEX #if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED #if XCHAL_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL diff --git a/ports/xtensa/xcc/readme_threadx.txt b/ports/xtensa/xcc/readme_threadx.txt index 29413318..3ad4aec2 100644 --- a/ports/xtensa/xcc/readme_threadx.txt +++ b/ports/xtensa/xcc/readme_threadx.txt @@ -6,7 +6,7 @@ The Xtensa configurable architecture supports a vast space of processor features. This port of ThreadX to the Xtensa architecture is based on -a Cadence Design Systems RTOS porting layer that takes care of Xtensa specifics +a Cadence Design Systems RTOS porting layer that takes care of Xtensa specifics that are common to most embedded real-time operating systems. It supports all Xtensa features (including context-switching custom processor extensions defined in the TIE language) with certain minimum requirements. You @@ -17,7 +17,7 @@ configuration. ThreadX also provides optional thread-safe support for the Xtensa C library and the newlib C library distributed with Xtensa Tools (for use in threads only, not in interrupt handlers). -ThreadX for Xtensa configurable processors requires the following minimum +ThreadX for Xtensa configurable processors requires the following minimum processor configuration options: - Timer interrupt option with at least one interruptible timer for ThreadX. - Interrupt option (implied by the timer interrupt option). @@ -60,10 +60,10 @@ If you wish to build for an evaluation board that is supported by an external package, be sure the appropriate package is installed. See the introduction (section 0) to determine if you need an external package. If you are using an external board package, set the environment variable -XTENSA_BOARDS to the absolute path of the root of the installed support +XTENSA_BOARDS to the absolute path of the root of the installed support package (or you can pass this to xt-make commands on the command line). eg. XTENSA_BOARDS = C:\usr\xtensa\RB-2007.1-xtav60 for Avnet LX60 board. -You do not need to set XTENSA_BOARDS if using a Cadence Design Systems supported +You do not need to set XTENSA_BOARDS if using a Cadence Design Systems supported board with Xtensa Tools RB-2007.2 and up (support is bundled with the tools). Next, change directories to the ThreadX installation directory, as follows: @@ -91,7 +91,7 @@ default when BOARD is defined). eg. BOARD=xtav60 for the Avnet LX60 (XT-AV60) board. > xt-make PLATFORM=raw - + which builds for a raw Xtensa core with no "board support". > xt-make PLATFORM=gdbio @@ -100,11 +100,11 @@ Provides some very slow I/O support through the xt-gdb debugger. For GDBIO to work, xt-gdb must remain connected to the target. If you are building for an Xtensa processor configuration that is not the -default you selected when you installed Xtensa Tools, you need to define the -environment variable XTENSA_CORE. If your configuration is not in the +default you selected when you installed Xtensa Tools, you need to define the +environment variable XTENSA_CORE. If your configuration is not in the default registry you selected when you installed Xtensa Tools, you also need to define the environment variable XTENSA_SYSTEM. See tools manuals. -You can avoid defining these in your environment if you pass the variables +You can avoid defining these in your environment if you pass the variables you need to redefine into xt-make as follows: > xt-make XTENSA_CORE= XTENSA_SYSTEM= ... @@ -120,7 +120,7 @@ defined), for example "sim", "xtkc705". To build ThreadX with thread-safe C library support, define TX_THREAD_SAFE_CLIB in your build, as described in section 5 and in the Makefile. Please note that the C library is only safe for use in threads, not in interrupt handlers. -It may also safely be used in tx_application_define (after tx_kernel_enter, +It may also safely be used in tx_application_define (after tx_kernel_enter, before threads are running). @@ -130,10 +130,10 @@ The ThreadX demonstration is designed to execute under Xtensa instruction set simulator (ISS) or on a supported evaluation board programmed with your Xtensa processor configuration. -Building the demonstration is easy, simply execute the build_threadx_demo.bat +Building the demonstration is easy, simply execute the build_threadx_demo.bat batch file while inside threadx directory, as follows: -> build_threadx_demo.bat +> build_threadx_demo.bat or @@ -143,8 +143,8 @@ Be sure to set or pass into xt-make the variables described in section 2 above for building the ThreadX library, including the PLATFORM or BOARD you want to run on. -This compiles demo_threadx.c (which is the demonstration application) and links -it with the ThreadX objects in tx.a. The resulting file demo_threadx.out is a +This compiles demo_threadx.c (which is the demonstration application) and links +it with the ThreadX objects in tx.a. The resulting file demo_threadx.out is a ELF binary file that can be downloaded and executed on the target. The demo binary appears in the platform specific sub-directory described earlier. @@ -184,7 +184,7 @@ on your xt-make command line - this is the same as "raw" except it links some stubs that communicate through the debugger. It is very slow! WARNING: It is tempting to add printf calls to other threads in the demo. -If you modify the code in any way, you may need adjust affected threads' +If you modify the code in any way, you may need adjust affected threads' stack sizes. This is especially true if you add a printf call. See 4.5. @@ -207,9 +207,9 @@ xtensa_vectors_xea3.S (for XEA3). 4.2 Memory Allocation -In addition, _tx_initialize_low_level also determines the first available -address for use by the application. By default, the first available address -is assumed to be above all linker-allocated sections at symbol _end. This +In addition, _tx_initialize_low_level also determines the first available +address for use by the application. By default, the first available address +is assumed to be above all linker-allocated sections at symbol _end. This is passed to the application definition function, tx_application_define. This is a convenience to the application developer. Ultimately the developer has full control over memory allocation and can choose to use this or not. @@ -223,7 +223,7 @@ top of the system stack is defined by the symbol _xt_interrupt_stack_top. See the file xtensa_intr_asm.S for the default system stack definition. This stack may be resized and/or relocated according to the application needs. The application developer must ensure that the system stack is -sized appropriately for the application. All interrupts handled by +sized appropriately for the application. All interrupts handled by ThreadX will use the system stack. Handlers written in assembly must not switch to the system stack, since it will not be possible to detect whether the stack is currently in use. @@ -232,9 +232,9 @@ The macro TX_SYSTEM_STACK_SIZE defines the size of the system stack. As a convenience, a macro TX_MINIMUM_STACK_SYSTEM is provided with the minimum size required for the system stack. This is based on the maximum possible interrupt nesting level per the Xtensa processor configuration, -assuming very simple C handlers that do not call deeper than one or two +assuming very simple C handlers that do not call deeper than one or two levels. If the application uses more complex handlers, it will be -necessary to add to this value (accounting for nesting) to determine +necessary to add to this value (accounting for nesting) to determine the space required for the system stack. 4.4 Location and Extent of C Library Heap @@ -244,7 +244,7 @@ for the heap is allocated like this: by default, half the space between the first available memory address and the end of system memory is made available to the heap. -The heap location and limit are available in two global variables, and +The heap location and limit are available in two global variables, and can be fully customized in tx_application_define by assigning to them: _tx_clib_heap_start Base address of heap. @@ -254,9 +254,9 @@ This must be done BEFORE any C library calls. It is advised that it be done at the beginning of tx_application_define. Please note that when the thread-safe C library support is used, the heap -is not initialized before tx_kernel_enter has been called, so malloc will +is not initialized before tx_kernel_enter has been called, so malloc will fail. It is recommended to avoid C library calls that use the heap (such -as printf) outside of ThreadX (eg. in main). The C library is NOT safe +as printf) outside of ThreadX (eg. in main). The C library is NOT safe for use in interrupt or exception handlers, so this should be avoided. 4.5 Thread Stack Sizes @@ -265,13 +265,13 @@ The application must ensure that every thread has enough space for its stack. This must account for the deepest call depth and allow for one interrupt stack frame as defined in xtensa_context.h . Several factors influence the size of the stack required, including compiler optimization -level (-O0 is worst), use of TX_ENABLE_STACK_CHECKING option, and of -course your Xtensa configuration. Some stack size guidelines and macros +level (-O0 is worst), use of TX_ENABLE_STACK_CHECKING option, and of +course your Xtensa configuration. Some stack size guidelines and macros are provided in tx_port.h assuming no optimization (default, -O0). Threads that call C library functions may need larger stacks than those that don't. In particular, use of printf requires a very large stack and -will usually cause a stack overflow if inserted in a thread without +will usually cause a stack overflow if inserted in a thread without enlarging its stack size. See DEMO_STACK_SIZE_PRINTF in demo_threadx.c for a guideline. Use printf with care! @@ -288,8 +288,8 @@ Compiler Switch Meaning -g Specifies debug information. -c Specifies object code generation. -On Sets compiler optimization level n (default -O0). - -mlongcalls Allows assembler and linker to convert call - instructions to longer indirect call sequences + -mlongcalls Allows assembler and linker to convert call + instructions to longer indirect call sequences when target is out of range. -x assembler-with-cpp Passes .s and .S files through C preprocessor. -Dmacro Define a preprocessor macro with no value. @@ -300,16 +300,16 @@ Application Defines (preprocessor macros definable with the -D option): TX_THREAD_SAFE_CLIB Enable support for thread-safe C library. Only the Xtensa C library and the newlib library are supported for thread-safe operation. - When this is enabled, half the available memory - space is allocated by default, below the system - stack, for the heap. The heap size and location + When this is enabled, half the available memory + space is allocated by default, below the system + stack, for the heap. The heap size and location can be customized in tx_application_define. Default off. NOTE: Thread safe support for Xtensa C library requires Xtensa Tools version RF-2015.2 or later. - TX_ENABLE_STACK_CHECKING Enable generic ThreadX support for stack + TX_ENABLE_STACK_CHECKING Enable generic ThreadX support for stack overflow checking. This can help avoid long debugging sessions or customer support calls by identifying many crashes caused by stack @@ -327,13 +327,13 @@ Application Defines (preprocessor macros definable with the -D option): All generic ThreadX options in tx_user.h may also be defined with -D. - Note, the above defines are not specific to Xtensa processors, so + Note, the above defines are not specific to Xtensa processors, so their names begin with "TX_". Defines below are unique to the Xtensa port so have names beginning with "XT_". XT_SIMULATOR Set this if building to run on the simulator. Takes advantage of certain simulator control - and reporting facilities, and adjusts timing + and reporting facilities, and adjusts timing of periodic tick to provide a more acceptable performance in simulation (see XT_CLOCK_FREQ). Set by default unless PLATFORM is overridden. @@ -348,33 +348,33 @@ Application Defines (preprocessor macros definable with the -D option): provided Makefile when PLATFORM=board and BOARD is defined (eg. PLATFORM=board BOARD=xtkc705). - XT_CLOCK_FREQ=freq Specifies the target processor's clock - frequency in Hz. Used primarily to set the + XT_CLOCK_FREQ=freq Specifies the target processor's clock + frequency in Hz. Used primarily to set the timer that generates the periodic interrupt. Defaults are provided and may be edited in xtensa_timer.h (see comments there also). Default for simulator provides more acceptable performance, but cannot provide real-time performance due to variation in simulation - speed per host platform and insufficient + speed per host platform and insufficient cycles between interrupts to process them. - Supported board platforms by default leave - this undefined and compute the clock frequency - at initialization unless this is explicitly + Supported board platforms by default leave + this undefined and compute the clock frequency + at initialization unless this is explicitly defined. XT_TICK_PER_SEC=n Specifies the frequency of the periodic tick. XT_TIMER_INDEX=n Specifies which timer to use for ThreadX. - Set this if your Xtensa processor configuration - provides more than one suitable timer and you + Set this if your Xtensa processor configuration + provides more than one suitable timer and you want to override the default. See xtensa_timer.h. XT_INTEXC_HOOKS Enables hooks in interrupt vector handlers to support dynamic installation of exception - and interrupt handlers. Used by automatic + and interrupt handlers. Used by automatic regression test programs. Disabled by default. - + XT_USE_OVLY Enable code overlay support. XT_USE_SWPRI Enable software prioritization of interrupts. @@ -411,7 +411,7 @@ In the windowed ABI the registers of the current window are used as follows: There are no callee-save registers. The windowed hardware automatically saves registers a0-a3 on a call4, a0-a8 on a call8, a0-a12 on a call12, by rotating the register window. Hardware triggers window overflow and -underflow exceptions as necessary when registers outside the current +underflow exceptions as necessary when registers outside the current window need to be spilled to preallocated space in the stack frame, or restored. Complete details are in the Xtensa manuals. The entire windowed register file is saved and restored on interrupt or thread context switch. @@ -453,11 +453,11 @@ As a consequence, the application developer should NOT assume that special registers are preserved over a ThreadX API call such as tx_thread_sleep. If multiple threads use a register, the caller must save and restore it. -The saved context stack frames for context switches that occur as a result -of interrupt handling (interrupt frame) or from thread-level API calls +The saved context stack frames for context switches that occur as a result +of interrupt handling (interrupt frame) or from thread-level API calls (solicited frame) are described in human readable form in xtensa_context.h . All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. An Xtensa architecture port-specific extension to the thread control block tx_thread_solicited contains 1 for a thread that is currently suspended from an API call, otherwise contains 0. @@ -477,7 +477,7 @@ yield better results. See the compiler manual for details. You can eliminate the ThreadX basic API error checking by compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING defined before -tx_api.h is included. +tx_api.h is included. The Xtensa architecture port-specific assembly files are coded with no file-scope labels inside functions (all labels inside functions begin with @@ -510,7 +510,7 @@ vector locations. The XEA2 architecture supports several different classes of exceptions and interrupts. Being a configurable architecture, many of these are optional, and the vector locations are determined by your processor configuration. The handlers provided use conditional -compilation to adapt to your processor configuration and include only +compilation to adapt to your processor configuration and include only the code that is needed. Xtensa vector locations may reside almost anywhere, including in ROM. @@ -596,7 +596,7 @@ mentioned because there is code to handle them in xtensa_vectors.S. calls _tx_thread_context_save, which saves the rest of the interrupt context. After this the handler sets up a C environment and enables the high-priority class of interrupts (which do not interact with - ThreadX), then reads EXCCAUSE and uses the cause (number) to index + ThreadX), then reads EXCCAUSE and uses the cause (number) to index into a table of user-specified handlers. The correct handler is then called. If the handler returns, the context is restored and control is returned to the code that caused the exception. The user-defined @@ -607,7 +607,7 @@ mentioned because there is code to handle them in xtensa_vectors.S. the handler enables all interrupts above that priority level after saving the thread context and switching to the interrupt stack if it is not a nested interrupt. It then sets up the environment for C code - and then calls the handler (found in the handler table) for the + and then calls the handler (found in the handler table) for the interrupt number. If the user has not specified a handler, then the default handler will be called, which will terminate the program. @@ -627,8 +627,8 @@ mentioned because there is code to handle them in xtensa_vectors.S. 8.2 Medium Priority Interrupt Handlers (XEA2) - Medium priority interrupts are those at levels 2 up to XCHAL_EXCM_LEVEL, - a configuration-specific maximum interrupt level affected by the global + Medium priority interrupts are those at levels 2 up to XCHAL_EXCM_LEVEL, + a configuration-specific maximum interrupt level affected by the global 'exception mode' bit in the processor status word (PS.EXCM). Interrupt levels above XCHAL_EXCM_LEVEL are of the high-priority class. The Xtensa hardware documentation considers medium priority interrupts @@ -640,12 +640,12 @@ mentioned because there is code to handle them in xtensa_vectors.S. 8.3 High Priority Interrupt Handlers (XEA2) - High priority interrupts are those strictly above XCHAL_EXCM_LEVEL, - a configuration-specific maximum interrupt level affected by the + High priority interrupts are those strictly above XCHAL_EXCM_LEVEL, + a configuration-specific maximum interrupt level affected by the global 'exception mode' bit in the processor status word (PS.EXCM). High priority handlers may not directly interact with ThreadX at all, and are described here only for the sake of completeness. They must - be coded in assembler (may not be coded in C) and are intended to be + be coded in assembler (may not be coded in C) and are intended to be used for handling extremely high frequency hardware events that need to be handled in only a few cycles. A high priority interrupt handler may trigger a software interrupt at a medium or low priority level to @@ -655,7 +655,7 @@ mentioned because there is code to handle them in xtensa_vectors.S. priority interrupt, providing for fast dispatch and efficient nesting on top of lower priority interrupts. Handlers are templates included only for the vectors that exist in your Xtensa processor configuration. - These templates are written for only one interrupt per high priority + These templates are written for only one interrupt per high priority level to minimize latency servicing very fast time-critical interrupts. The vector code jumps to the corresponding first-level interrupt handler, which then executes application-provided assembler code before returning @@ -665,7 +665,7 @@ mentioned because there is code to handle them in xtensa_vectors.S. Kernel mode is not used in this port of ThreadX, and therefore kernel exceptions should not happen. A stub is provided for the vector that - triggers the debugger (if connected) or calls _xt_panic to freeze the + triggers the debugger (if connected) or calls _xt_panic to freeze the processor should a kernel exception occur. 8.5 Alloca Exception Handler @@ -692,18 +692,18 @@ mentioned because there is code to handle them in xtensa_vectors.S. 8.7 Co-Processor Exception Handler A coprocessor exception is generated when a thread accesses a - coprocessor that it does not "own". Ownership represents which - thread's state is currently in the coprocessor. Co-processors are - context-switched "lazily" (on demand) only when a non-owning thread - uses a coprocessor instruction, otherwise a thread retains ownership + coprocessor that it does not "own". Ownership represents which + thread's state is currently in the coprocessor. Co-processors are + context-switched "lazily" (on demand) only when a non-owning thread + uses a coprocessor instruction, otherwise a thread retains ownership even when it is preempted from the main processor. The coprocessor exception handler performs the context-switch and manages ownership. Co-processors may not be used by any code outside the context of a thread. A coprocessor exception triggered by code that is not part of a running thread is a fatal error and ThreadX/Xtensa will panic. - This restriction is intended to reduce the overhead of saving and - restoring coprocessor state (which can be quite large) and in + This restriction is intended to reduce the overhead of saving and + restoring coprocessor state (which can be quite large) and in particular remove that overhead from interrupt handlers. It also reduces the thread stack size requirement by allowing coprocessor state to be saved in the thread control block rather than the stack. @@ -727,7 +727,7 @@ mentioned because there is code to handle them in xtensa_vectors.S. A double exception is a general exception that happens while the processor is in exception mode (PS.EXCM set), and thus indicates a bug in kernel code. The double exception vector handler triggers - the debugger (if connected) or calls _xt_panic to freeze the + the debugger (if connected) or calls _xt_panic to freeze the processor. 8.10 Window Overflow and Underflow Exception Handlers @@ -755,13 +755,13 @@ mentioned because there is code to handle them in xtensa_vectors.S. 9. Overlay Support (XEA2 only) ThreadX supports the overlay feature of the Xtensa toolsuite. To enable overlay support, -the ThreadX library should be built with XT_USE_OVLY defined. In addition, the linker -command line must use the overlay library via the -loverlay linker option and the +the ThreadX library should be built with XT_USE_OVLY defined. In addition, the linker +command line must use the overlay library via the -loverlay linker option and the xtensa_overlay_os_hook.o object file must be explicitly specified in order to override the overlay libary version. -You will also need to generate a custom LSP for overlay use. Please reference the -Xtensa System Software Reference and Xtenas Linker Support Packages (LSPs) for more +You will also need to generate a custom LSP for overlay use. Please reference the +Xtensa System Software Reference and Xtenas Linker Support Packages (LSPs) for more information on using overlays. diff --git a/ports/xtensa/xcc/src/tx_clib_lock.c b/ports/xtensa/xcc/src/tx_clib_lock.c index b95bf12b..9e308720 100644 --- a/ports/xtensa/xcc/src/tx_clib_lock.c +++ b/ports/xtensa/xcc/src/tx_clib_lock.c @@ -30,16 +30,6 @@ /* operation of the C library. Both newlib and the Xtensa C Library */ /* are supported. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */ -/* 12-31-2023 Xiuwen Cai Modified comment(s), and */ -/* added error handling in */ -/* lock initialization, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #include "tx_api.h" /* TX_THREAD_SAFE_CLIB may be defined by tx_port.h */ @@ -137,7 +127,7 @@ __env_unlock (struct _reent * ptr) #include #include - + #define XT_NUM_CLIB_LOCKS (_MAX_LOCK + FOPEN_MAX) typedef TX_MUTEX * _Rmtx; diff --git a/ports/xtensa/xcc/src/tx_initialize_low_level.c b/ports/xtensa/xcc/src/tx_initialize_low_level.c index eebae217..de2c2b93 100644 --- a/ports/xtensa/xcc/src/tx_initialize_low_level.c +++ b/ports/xtensa/xcc/src/tx_initialize_low_level.c @@ -48,15 +48,6 @@ int32_t xt_timer_intnum = -1; /* available RAM memory address for tx_application_define. */ /* It also sets the default heap region for the optional C library. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */ -/* 04-25-2022 Scott Larson Modified comments and updated */ -/* function names, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ VOID _tx_initialize_low_level(VOID) { @@ -123,8 +114,8 @@ VOID _tx_initialize_low_level(VOID) Initialize co-processor management for threads. Leave CPENABLE alone. This is called from a normal Xtensa single-threaded run-time environment before multi-threading has commenced. All co-processors are enabled. - It is important NOT to clear CPENABLE yet because tx_application_define() - is user code which might use a co-processor. The co-processor exception + It is important NOT to clear CPENABLE yet because tx_application_define() + is user code which might use a co-processor. The co-processor exception handler does not expect to be called outside a thread. */ _xt_coproc_init(); diff --git a/ports/xtensa/xcc/src/tx_thread_context_restore.S b/ports/xtensa/xcc/src/tx_thread_context_restore.S index c36f0a5c..89a66b35 100644 --- a/ports/xtensa/xcc/src/tx_thread_context_restore.S +++ b/ports/xtensa/xcc/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,11 +60,6 @@ /* preemption is necessary. Otherwise, if preemption is necessary or */ /* if no thread was running, the function returns to the scheduler. */ /* */ -/* RELEASE HISTORY */ -/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */ -/* 10-31-2022 Scott Larson Updated EPK definitions, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/xtensa/xcc/src/tx_thread_context_save.S b/ports/xtensa/xcc/src/tx_thread_context_save.S index 109b954f..397ea822 100644 --- a/ports/xtensa/xcc/src/tx_thread_context_save.S +++ b/ports/xtensa/xcc/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -33,8 +34,8 @@ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -49,23 +50,17 @@ .text -/**************************************************************************/ -/* */ -/* DESCRIPTION */ -/* */ -/* This function saves the context of an executing thread in the */ -/* beginning of interrupt processing. The function also ensures that */ -/* the system stack is used upon return to the calling ISR. */ -/* */ -/* Interrupts remain disabled and no exceptions are triggered! */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */ -/* */ -/**************************************************************************/ +/**************************************************************************/ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* Interrupts remain disabled and no exceptions are triggered! */ +/* */ +/**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { @@ -77,13 +72,13 @@ _tx_thread_context_save: /* Please note: Control flow might seem strange. This is because it has been optimized to avoid taken branches in the longest normal path (the critical - one for worst-case latency), presumed to be a non-nested interrupt and + one for worst-case latency), presumed to be a non-nested interrupt and non-idle) and to hide pipeline interlock cycles where possible. */ /* Save a couple of scratch regs to work with that are preserved over the - call to _xt_context_save. The latter assumes the interruptee's values + call to _xt_context_save. The latter assumes the interruptee's values of these are already saved and these regs contain different data to be preserved, so doesn't save them in the stack frame, and thereby requires that its caller have already saved them in the interrupt stack frame. @@ -107,7 +102,7 @@ _tx_thread_context_save: .Ln_tx_thread_not_nested_save: /* Otherwise, not nested, check to see if a thread was running. */ - // else + // else // { // if (_tx_thread_current_ptr) // { @@ -127,10 +122,10 @@ _tx_thread_context_save: .L_tx_thread_idle_system_save: - /* + /* If interrupted in the idle state, it's not necessary to save any context. - But even in the idle case where we are already on the system stack, it is - necessary to reset the (system) stack pointer so a series of consecutive + But even in the idle case where we are already on the system stack, it is + necessary to reset the (system) stack pointer so a series of consecutive interrupts in the idle state do not keep moving the SP downward. */ @@ -146,7 +141,7 @@ _tx_thread_context_save: /* Nested interrupt condition. */ /* Save the rest of the interrupted context and return to ISR. */ call0 _xt_context_save - + mov a0, a12 /* retrieve return address */ ret diff --git a/ports/xtensa/xcc/src/tx_thread_interrupt_control.c b/ports/xtensa/xcc/src/tx_thread_interrupt_control.c index dfc9552d..3a0cae27 100644 --- a/ports/xtensa/xcc/src/tx_thread_interrupt_control.c +++ b/ports/xtensa/xcc/src/tx_thread_interrupt_control.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -33,8 +34,8 @@ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -46,21 +47,15 @@ #include "xtensa_rtos.h" -/**************************************************************************/ -/* */ -/* DESCRIPTION */ -/* */ -/* This function is responsible for changing the interrupt lockout */ -/* posture of the system. */ -/* NOTE: In earlier versions this was implemented in assembly. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */ -/* */ -/**************************************************************************/ +/**************************************************************************/ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* NOTE: In earlier versions this was implemented in assembly. */ +/* */ +/**************************************************************************/ UINT _tx_thread_interrupt_control(UINT new_posture) { diff --git a/ports/xtensa/xcc/src/tx_thread_schedule.S b/ports/xtensa/xcc/src/tx_thread_schedule.S index a98d7495..448dc6d7 100644 --- a/ports/xtensa/xcc/src/tx_thread_schedule.S +++ b/ports/xtensa/xcc/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ /* in the variable, the corresponding thread is resumed. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */ -/* 10-31-2022 Scott Larson Updated EPK definitions, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/xtensa/xcc/src/tx_thread_stack_build.S b/ports/xtensa/xcc/src/tx_thread_stack_build.S index 53d7e1c6..a52fc35e 100644 --- a/ports/xtensa/xcc/src/tx_thread_stack_build.S +++ b/ports/xtensa/xcc/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -33,8 +34,8 @@ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -47,21 +48,15 @@ .text -/**************************************************************************/ -/* */ -/* DESCRIPTION */ -/* */ +/**************************************************************************/ +/* */ +/* DESCRIPTION */ +/* */ /* This function builds a stack frame on the supplied thread's stack. */ /* The stack frame looks like an interrupt frame or a solicited frame */ -/* depending on the exception architecture of the target hardware. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */ -/* */ -/**************************************************************************/ +/* depending on the exception architecture of the target hardware. */ +/* */ +/**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports/xtensa/xcc/src/tx_thread_system_return.S b/ports/xtensa/xcc/src/tx_thread_system_return.S index 38330082..d1fc4a9f 100644 --- a/ports/xtensa/xcc/src/tx_thread_system_return.S +++ b/ports/xtensa/xcc/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,13 +57,6 @@ /* is saved since the compiler assumes temp registers are going to get */ /* slicked by a function call anyway. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */ -/* 10-31-2022 Scott Larson Updated EPK definitions, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/xtensa/xcc/src/tx_timer_interrupt.S b/ports/xtensa/xcc/src/tx_timer_interrupt.S index 7cca247c..d09badde 100644 --- a/ports/xtensa/xcc/src/tx_timer_interrupt.S +++ b/ports/xtensa/xcc/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -33,8 +34,8 @@ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Timer */ /** */ @@ -49,26 +50,17 @@ .text -/**************************************************************************/ -/* */ -/* DESCRIPTION */ -/* */ -/* This function processes the hardware timer interrupt. This */ -/* processing includes incrementing the system clock and checking for */ -/* time slice and/or timer expiration. If either is found, the */ -/* interrupt context save/restore functions are called along with the */ -/* expiration functions. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */ -/* 04-25-2022 Scott Larson Modified comments and updated */ -/* function name, */ -/* resulting in version 6.1.11 */ -/* */ -/**************************************************************************/ +/**************************************************************************/ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { @@ -99,13 +91,13 @@ _tx_timer_interrupt: /* Xtensa timers work by comparing a cycle counter with a preset value. - Once the match occurs an interrupt is generated, and the handler has + Once the match occurs an interrupt is generated, and the handler has to set a new cycle count into the comparator. To avoid clock drift due to interrupt latency, the new cycle count is computed from the old, - not the time the interrupt was serviced. However if a timer interrupt + not the time the interrupt was serviced. However if a timer interrupt is ever serviced more than one tick late, it is necessary to process - multiple ticks until the new cycle count is in the future, otherwise - the next timer interrupt would not occur until after the cycle counter + multiple ticks until the new cycle count is in the future, otherwise + the next timer interrupt would not occur until after the cycle counter had wrapped (2^32 cycles later). do { diff --git a/ports/xtensa/xcc/src/tx_xtensa_stack_error_handler.c b/ports/xtensa/xcc/src/tx_xtensa_stack_error_handler.c index 012b3612..a46f65cc 100644 --- a/ports/xtensa/xcc/src/tx_xtensa_stack_error_handler.c +++ b/ports/xtensa/xcc/src/tx_xtensa_stack_error_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -33,8 +34,8 @@ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Support for Xtensa applications */ /** */ @@ -65,10 +66,10 @@ #include -/**************************************************************************/ -/* */ -/* DESCRIPTION */ -/* */ +/**************************************************************************/ +/* */ +/* DESCRIPTION */ +/* */ /* Callback to notify of a stack overflow when registered with */ /* tx_stack_error_notify and stack checking is enabled (ThreadX */ /* is compiled with TX_ENABLE_STACK_CHECKING defined). */ @@ -85,20 +86,14 @@ /* - Passes control to the debugger (if attached). */ /* - Terminates the simulation (simulator only). */ /* - Panics. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */ -/* */ -/**************************************************************************/ +/* */ +/**************************************************************************/ VOID _tx_xtensa_stack_error_handler(TX_THREAD * thread) { #ifdef XT_SIMULATOR register int32_t sc __asm__ ("a2") = SYS_log_msg; - register char * msg __asm__ ("a3") + register char * msg __asm__ ("a3") = "**** Stack overflow in thread 0x%08x.\n"; register TX_THREAD * thd __asm__ ("a4") = thread; __asm__ volatile ("simcall" :: "a" (sc), "a" (msg), "a" (thd) ); diff --git a/ports/xtensa/xcc/src/xtensa_context.S b/ports/xtensa/xcc/src/xtensa_context.S index af3138aa..e4b9aa0a 100644 --- a/ports/xtensa/xcc/src/xtensa_context.S +++ b/ports/xtensa/xcc/src/xtensa_context.S @@ -41,12 +41,6 @@ /* anyway, and are always restored even in Call0 ABI. Only A14, A15 are */ /* truly handled as callee-save regs. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */ -/* */ /**************************************************************************/ @@ -71,7 +65,7 @@ interrupt stack frame defined in xtensa_rtos.h. Its counterpart is _xt_context_restore (which also restores A12, A13). Caller is expected to have saved PC, PS, A0, A1 (SP), A12, A13 in the frame. -This function preserves A12 & A13 in order to provide the caller with 2 scratch +This function preserves A12 & A13 in order to provide the caller with 2 scratch regs that need not be saved over the call to this function. The choice of which 2 regs to provide is governed by xthal_window_spill_nw and xthal_save_extra_nw, to avoid moving data more than necessary. Caller can assign regs accordingly. @@ -80,7 +74,7 @@ Entry Conditions: A0 = Return address in caller. A1 = Stack pointer of interrupted thread or handler ("interruptee"). Original A12, A13 have already been saved in the interrupt stack frame. - Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as at the + Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as at the point of interruption. If windowed ABI, PS.EXCM = 1 (exceptions disabled). @@ -156,8 +150,8 @@ _xt_context_save: and underflow exceptions disabled (assured by PS.EXCM == 1). */ s32i a12, sp, XT_STK_TMP0 /* temp. save stuff in stack frame */ - s32i a13, sp, XT_STK_TMP1 - s32i a9, sp, XT_STK_TMP2 + s32i a13, sp, XT_STK_TMP1 + s32i a9, sp, XT_STK_TMP2 /* Save the overlay state if we are supporting overlays. Since we just saved @@ -177,12 +171,12 @@ _xt_context_save: call0 xthal_window_spill_nw /* preserves only a4,5,8,9,12,13 */ addi sp, sp, -XT_STK_FRMSZ l32i a12, sp, XT_STK_TMP0 /* recover stuff from stack frame */ - l32i a13, sp, XT_STK_TMP1 - l32i a9, sp, XT_STK_TMP2 + l32i a13, sp, XT_STK_TMP1 + l32i a9, sp, XT_STK_TMP2 #endif #if XCHAL_EXTRA_SA_SIZE > 0 - /* + /* NOTE: Normally the xthal_save_extra_nw macro only affects address registers a2-a5. It is theoretically possible for Xtensa processor designers to write TIE that causes more address registers to be @@ -212,7 +206,7 @@ _xt_context_restore !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !! Restores all Xtensa processor state except PC, PS, A0, A1 (SP) (and in Call0 -ABI, A14, A15 which are preserved by all interrupt handlers) from an interrupt +ABI, A14, A15 which are preserved by all interrupt handlers) from an interrupt stack frame defined in xtensa_rtos.h . Its counterpart is _xt_context_save (whose caller saved A12, A13). @@ -225,7 +219,7 @@ Entry Conditions: Exit conditions: A0 = Return address in caller. A1 = Stack pointer of interrupted thread or handler ("interruptee"). - Other processor state except PC, PS, A0, A1 (SP), is as at the point + Other processor state except PC, PS, A0, A1 (SP), is as at the point of interruption. *******************************************************************************/ @@ -236,7 +230,7 @@ Exit conditions: _xt_context_restore: #if XCHAL_EXTRA_SA_SIZE > 0 - /* + /* NOTE: Normally the xthal_restore_extra_nw macro only affects address registers a2-a5. It is theoretically possible for Xtensa processor designers to write TIE that causes more address registers to be @@ -312,7 +306,7 @@ _xt_context_restore: /* Call0 ABI callee-saved regs a12-15 do not need to be restored here. - However a12-13 were saved for scratch before XT_RTOS_INT_ENTER(), + However a12-13 were saved for scratch before XT_RTOS_INT_ENTER(), so need to be restored anyway, despite being callee-saved in Call0. */ l32i a12, sp, XT_STK_A12 @@ -337,7 +331,7 @@ to "unowned". Leaves CPENABLE as it found it (does NOT clear it). Called during initialization of the RTOS, before any threads run. This may be called from normal Xtensa single-threaded application code which -might use co-processors. The Xtensa run-time initialization enables all +might use co-processors. The Xtensa run-time initialization enables all co-processors. They must remain enabled here, else a co-processor exception might occur outside of a thread, which the exception handler doesn't expect. @@ -378,13 +372,13 @@ _xt_coproc_init: _xt_coproc_release -Releases any and all co-processors owned by a given thread. The thread is +Releases any and all co-processors owned by a given thread. The thread is identified by it's co-processor state save area defined in xtensa_context.h . Must be called before a thread's co-proc save area is deleted to avoid memory corruption when the exception handler tries to save the state. May be called when a thread terminates or completes but does not delete -the co-proc save area, to avoid the exception handler having to save the +the co-proc save area, to avoid the exception handler having to save the thread's co-proc state before another thread can use it (optimization). Entry Conditions: diff --git a/ports/xtensa/xcc/src/xtensa_coproc_handler.S b/ports/xtensa/xcc/src/xtensa_coproc_handler.S index 33de2070..0540d633 100644 --- a/ports/xtensa/xcc/src/xtensa_coproc_handler.S +++ b/ports/xtensa/xcc/src/xtensa_coproc_handler.S @@ -28,12 +28,6 @@ /* Xtensa coprocessor handling routines. This code is only active if */ /* one or more coprocessors are present. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */ -/* */ /**************************************************************************/ @@ -225,7 +219,7 @@ _xt_coproc_handler: _tx_thread_coproc_state: - // return ( _tx_thread_system_state == 0 && _tx_thread_current_ptr != 0 + // return ( _tx_thread_system_state == 0 && _tx_thread_current_ptr != 0 // ? (&_tx_thread_current_ptr->tx_thread_cp_state) : 0 ) movi a15, _tx_thread_system_state // check if interrupt state @@ -512,15 +506,15 @@ _xt_coproc_exc: .global _xt_coproc_exc .type _xt_coproc_exc,@function .align 4 - + _xt_coproc_exc: - + mov a0, sp // Allocate stack frame addi sp, sp, -XT_STK_FRMSZ s32i a0, sp, XT_STK_A1 // save SP #if XCHAL_HAVE_WINDOWED s32e a0, sp, -12 // for debug backtrace -#endif +#endif rsr a0, PS s32i a0, sp, XT_STK_PS // save PS rsr a0, EPC_1 diff --git a/ports/xtensa/xcc/src/xtensa_init.c b/ports/xtensa/xcc/src/xtensa_init.c index 298ca28d..d153ad35 100644 --- a/ports/xtensa/xcc/src/xtensa_init.c +++ b/ports/xtensa/xcc/src/xtensa_init.c @@ -27,12 +27,6 @@ /* */ /* Xtensa initialization routines. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */ -/* */ /**************************************************************************/ @@ -49,7 +43,7 @@ uint32_t xt_tick_divisor = 0; /* cached number of cycles per tick */ /* -Compute and initialize at run-time the tick divisor (the number of +Compute and initialize at run-time the tick divisor (the number of processor clock cycles in an RTOS tick, used to set the tick timer). Called when the processor clock frequency is not known at compile-time. */ diff --git a/ports/xtensa/xcc/src/xtensa_intr_asm.S b/ports/xtensa/xcc/src/xtensa_intr_asm.S index 78fd8a70..e972378a 100644 --- a/ports/xtensa/xcc/src/xtensa_intr_asm.S +++ b/ports/xtensa/xcc/src/xtensa_intr_asm.S @@ -28,12 +28,6 @@ /* Xtensa interrupt handling data and assembly routines. */ /* Also see xtensa_intr.c. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */ -/* */ /**************************************************************************/ diff --git a/ports/xtensa/xcc/src/xtensa_intr_wrapper.c b/ports/xtensa/xcc/src/xtensa_intr_wrapper.c index ff70f4ea..4ccb29f5 100644 --- a/ports/xtensa/xcc/src/xtensa_intr_wrapper.c +++ b/ports/xtensa/xcc/src/xtensa_intr_wrapper.c @@ -27,12 +27,6 @@ /* */ /* Xtensa-specific interrupt handler wrapper. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */ -/* */ /**************************************************************************/ diff --git a/ports/xtensa/xcc/src/xtensa_overlay_os_hook.c b/ports/xtensa/xcc/src/xtensa_overlay_os_hook.c index 8fd92701..4a63479c 100644 --- a/ports/xtensa/xcc/src/xtensa_overlay_os_hook.c +++ b/ports/xtensa/xcc/src/xtensa_overlay_os_hook.c @@ -27,12 +27,6 @@ /* */ /* Xtensa overlay manager OS hooks for ThreadX. XEA2 only. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */ -/* */ /**************************************************************************/ @@ -45,7 +39,7 @@ /* Required to work around a bug in the overlay header. */ #ifdef XT_DISABLE_OVERLAYS #undef xt_overlay_fatal_error -#define xt_overlay_fatal_error(id) +#define xt_overlay_fatal_error(id) #endif @@ -67,7 +61,7 @@ xt_overlay_init_os(void) /* Create the mutex for overlay access. Priority inheritance is * required. */ - UINT status = + UINT status = tx_mutex_create (&xt_overlay_mutex, "xt_overlay_lock", TX_INHERIT); if (status != TX_SUCCESS) { diff --git a/ports/xtensa/xcc/src/xtensa_vectors.S b/ports/xtensa/xcc/src/xtensa_vectors.S index b115abf5..7b09638e 100644 --- a/ports/xtensa/xcc/src/xtensa_vectors.S +++ b/ports/xtensa/xcc/src/xtensa_vectors.S @@ -64,12 +64,6 @@ /* changes to the saved state in the exception frame, the changes will */ /* be applied when restoring the context. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */ -/* */ /**************************************************************************/ @@ -297,7 +291,7 @@ /* -------------------------------------------------------------------------------- Panic handler. - Should be reached by call0 (preferable) or jump only. If call0, a0 says where + Should be reached by call0 (preferable) or jump only. If call0, a0 says where from. If on simulator, display panic message and abort, else loop indefinitely. -------------------------------------------------------------------------------- */ @@ -331,7 +325,7 @@ _xt_panic_message: -------------------------------------------------------------------------------- Hooks to dynamically install handlers for exceptions and interrupts. Allows automated regression frameworks to install handlers per test. - Consists of an array of function pointers indexed by interrupt level, + Consists of an array of function pointers indexed by interrupt level, with index 0 containing the entry for user exceptions. Initialized with all 0s, meaning no handler is installed at each level. See comment in xtensa_rtos.h for more details. @@ -363,7 +357,7 @@ _xt_intexc_hooks: the appropriate stack frame, saves a few vector-specific registers and calls XT_RTOS_INT_ENTER to save the rest of the interrupted context and enter the RTOS, then sets up a C environment. It then calls the - user's interrupt handler code (which may be coded in C) and finally + user's interrupt handler code (which may be coded in C) and finally calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling. While XT_RTOS_INT_EXIT does not return directly to the interruptee, @@ -742,7 +736,7 @@ _xt_syscall_exc: ------------------------------------------------------------------------------- */ - .text + .text .type _xt_lowint1,@function .align 4 @@ -762,12 +756,12 @@ _xt_lowint1: /* Save rest of interrupt context and enter RTOS. */ call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */ - /* !! We are now on the RTOS system stack !! */ + /* !! We are now on the RTOS system stack !! */ /* Set up PS for C, enable interrupts above this level and clear EXCM. */ #ifdef __XTENSA_CALL0_ABI__ movi a0, PS_INTLEVEL(1) | PS_UM - #else + #else movi a0, PS_INTLEVEL(1) | PS_UM | PS_WOE #endif wsr a0, PS @@ -799,7 +793,7 @@ _xt_lowint1: the appropriate stack frame, saves a few vector-specific registers and calls XT_RTOS_INT_ENTER to save the rest of the interrupted context and enter the RTOS, then sets up a C environment. It then calls the - user's interrupt handler code (which may be coded in C) and finally + user's interrupt handler code (which may be coded in C) and finally calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling. While XT_RTOS_INT_EXIT does not return directly to the interruptee, @@ -1181,7 +1175,7 @@ and used for purposes requiring very short service times. Here are templates for high priority (level 2+) interrupt vectors. They assume only one interrupt per level to avoid the burden of identifying -which interrupts at this level are pending and enabled. This allows for +which interrupts at this level are pending and enabled. This allows for minimum latency and avoids having to save/restore a2 in addition to a0. If more than one interrupt per high priority level is configured, this burden is on the handler which in any case must provide a way to save and restore @@ -1444,12 +1438,12 @@ _xt_nmi: WINDOW OVERFLOW AND UNDERFLOW EXCEPTION VECTORS AND ALLOCA EXCEPTION HANDLER -Here is the code for each window overflow/underflow exception vector and +Here is the code for each window overflow/underflow exception vector and (interspersed) efficient code for handling the alloca exception cause. Window exceptions are handled entirely in the vector area and are very -tight for performance. The alloca exception is also handled entirely in +tight for performance. The alloca exception is also handled entirely in the window vector area so comes at essentially no cost in code size. -Users should never need to modify them and Cadence Design Systems recommends +Users should never need to modify them and Cadence Design Systems recommends they do not. Window handlers go at predetermined vector locations according to the diff --git a/ports/xtensa/xcc/src/xtensa_vectors_xea3.S b/ports/xtensa/xcc/src/xtensa_vectors_xea3.S index 9a25dcee..22d9db89 100644 --- a/ports/xtensa/xcc/src/xtensa_vectors_xea3.S +++ b/ports/xtensa/xcc/src/xtensa_vectors_xea3.S @@ -52,12 +52,6 @@ /* changes to the saved state in the exception frame, the changes will */ /* be applied when restoring the context. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */ -/* */ /**************************************************************************/ diff --git a/ports_arch/ARMv7-A/threadx/common/inc/tx_port.h b/ports_arch/ARMv7-A/threadx/common/inc/tx_port.h index f9b96956..f0153046 100644 --- a/ports_arch/ARMv7-A/threadx/common/inc/tx_port.h +++ b/ports_arch/ARMv7-A/threadx/common/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,20 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Updated comments, removed */ -/* unneeded temp variable, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -320,7 +307,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv7-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_context_restore.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_context_restore.S index 6b4a561d..41b0b0d0 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_context_restore.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,23 +80,6 @@ IRQ_MODE = 0x12 // IRQ mode /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_restore .type _tx_thread_context_restore,function diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_context_save.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_context_save.S index eff06283..d2d29d34 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_context_save.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,23 +72,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ .global _tx_thread_context_save .type _tx_thread_context_save,function diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_context_restore.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_context_restore.S index d2fbebe1..921c322c 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_context_restore.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -78,20 +79,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* FIQ ISR Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_restore .type _tx_thread_fiq_context_restore,function diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_context_save.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_context_save.S index 88472a3d..2f1a6c40 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_context_save.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_fiq_context_save .type _tx_thread_fiq_context_save,function diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_nesting_end.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_nesting_end.S index fa3886b8..a7ce701e 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_nesting_end.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_nesting_start.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_nesting_start.S index dbed1cf2..4f095dde 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_nesting_start.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_fiq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_control.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_control.S index d1223cb8..a5bc47f7 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_control.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,20 +69,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_disable.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_disable.S index a87d1a06..d7b53bc2 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_disable.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,20 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_restore.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_restore.S index 53ff2813..3c31e94b 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_restore.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,20 +68,6 @@ FIQ_MASK = 0x040 /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_irq_nesting_end.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_irq_nesting_end.S index 18aebc7c..cc4db3a7 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_irq_nesting_end.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_irq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,20 +80,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_irq_nesting_start.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_irq_nesting_start.S index a2ffd35d..3635874d 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_irq_nesting_start.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_irq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,20 +73,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_schedule.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_schedule.S index 5be10faa..b269dc9f 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_schedule.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_schedule.S @@ -1,11 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * Copyright (C) 2026-present Eclipse ThreadX contributors - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,23 +82,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_stack_build.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_stack_build.S index 3876225a..827554a7 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_stack_build.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,20 +75,6 @@ CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ int /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_system_return.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_system_return.S index 0eed478d..1a17446b 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_system_return.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,23 +69,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_vectored_context_save.S b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_vectored_context_save.S index fe8a98e8..91653b75 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_thread_vectored_context_save.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_thread_vectored_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,20 +67,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_vectored_context_save .type _tx_thread_vectored_context_save,function diff --git a/ports_arch/ARMv7-A/threadx/common/src/tx_timer_interrupt.S b/ports_arch/ARMv7-A/threadx/common/src/tx_timer_interrupt.S index cb0c1fa2..179ac894 100644 --- a/ports_arch/ARMv7-A/threadx/common/src/tx_timer_interrupt.S +++ b/ports_arch/ARMv7-A/threadx/common/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -77,20 +78,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* 12-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_arch/ARMv7-A/threadx/ports/ac5/example_build/tx_initialize_low_level.s b/ports_arch/ARMv7-A/threadx/ports/ac5/example_build/tx_initialize_low_level.s index 13743df7..bed65664 100644 --- a/ports_arch/ARMv7-A/threadx/ports/ac5/example_build/tx_initialize_low_level.s +++ b/ports_arch/ARMv7-A/threadx/ports/ac5/example_build/tx_initialize_low_level.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -126,15 +127,6 @@ Reset_Vector /* CALLED BY */ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ EXPORT _tx_initialize_low_level diff --git a/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/.cproject b/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/.cproject index e75dac72..c34527a9 100644 --- a/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/.cproject +++ b/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/.cproject @@ -1,176 +1,176 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/sample_threadx.scat index d23881cd..66d0d95a 100644 --- a/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 083a57a7..76395459 100644 --- a/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -91,14 +92,6 @@ $_tx_initialize_low_level: /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ .global _tx_initialize_low_level .type _tx_initialize_low_level,function diff --git a/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/tx/.cproject b/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/tx/.cproject index 476321bb..f17f3f56 100644 --- a/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/tx/.cproject +++ b/ports_arch/ARMv7-A/threadx/ports/ac6/example_build/tx/.cproject @@ -1,146 +1,146 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/reset.S b/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/reset.S index 3ce9efb7..f2e0522b 100644 --- a/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/reset.S +++ b/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/reset.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/sample_threadx.ld b/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/sample_threadx.ld index cb42c11c..d43e28f1 100644 --- a/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/sample_threadx.ld +++ b/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/sample_threadx.ld @@ -7,7 +7,7 @@ OUTPUT_ARCH(arm) SECTIONS { . = 0x00000000; - + .vectors : {reset.o(.text) } /* Read-only sections, merged into text segment: */ @@ -94,8 +94,8 @@ SECTIONS *(.gnu.linkonce.t*) *(.glue_7t) *(.glue_7) } =0 - .init : - { + .init : + { KEEP (*(.init)) } =0 _etext = .; @@ -120,7 +120,7 @@ SECTIONS .data1 : { *(.data1) } .eh_frame : { KEEP (*(.eh_frame)) } .gcc_except_table : { *(.gcc_except_table) } - .ctors : + .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is @@ -153,9 +153,9 @@ SECTIONS /* We want the small data sections together, so single-instruction offsets can access them all, and initialized data all before uninitialized, so we can shorten the on-disk segment size. */ - .sdata : + .sdata : { - *(.sdata) + *(.sdata) *(.sdata.*) *(.gnu.linkonce.s.*) } @@ -191,7 +191,7 @@ SECTIONS _stack_bottom = ABSOLUTE(.) ; - /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and + /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and SYS stack if nested interrupts are enabled. */ . = ALIGN(8) ; . += 4096 ; diff --git a/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/v7.h b/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/v7.h index 5a08b43f..c18b945c 100644 --- a/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/v7.h +++ b/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/v7.h @@ -4,7 +4,7 @@ // // Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/v7.s b/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/v7.s index 82c9ab1e..9487ddde 100644 --- a/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/v7.s +++ b/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/v7.s @@ -3,7 +3,7 @@ // // Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ @@ -20,7 +20,7 @@ enableInterrupts: CPSIE i BX lr - + .global disableInterrupts .type disableInterrupts,function @@ -28,7 +28,7 @@ enableInterrupts: disableInterrupts: CPSID i BX lr - + // ------------------------------------------------------------ // Cache Maintenance @@ -44,7 +44,7 @@ enableCaches: MCR p15, 0, r0, c1, c0, 0 // Write System Control Register ISB BX lr - + .global disableCaches @@ -57,7 +57,7 @@ disableCaches: MCR p15, 0, r0, c1, c0, 0 // Write System Control Register ISB BX lr - + .global cleanDCache @@ -114,7 +114,7 @@ clean_dcache_finished: POP {r4-r12} BX lr - + .global cleanInvalidateDCache .type cleanInvalidateDCache,function @@ -170,7 +170,7 @@ clean_invalidate_dcache_finished: POP {r4-r12} BX lr - + .global invalidateCaches @@ -229,7 +229,7 @@ invalidate_caches_skip: invalidate_caches_finished: POP {r4-r12} BX lr - + .global invalidateCaches_IS @@ -284,7 +284,7 @@ invalidate_caches_is_skip: invalidate_caches_is_finished: POP {r4-r12} BX lr - + // ------------------------------------------------------------ // TLB @@ -297,7 +297,7 @@ invalidateUnifiedTLB: MOV r0, #0 MCR p15, 0, r0, c8, c7, 0 // TLBIALL - Invalidate entire unified TLB BX lr - + .global invalidateUnifiedTLB_IS .type invalidateUnifiedTLB_IS,function @@ -306,7 +306,7 @@ invalidateUnifiedTLB_IS: MOV r0, #1 MCR p15, 0, r0, c8, c3, 0 // TLBIALLIS - Invalidate entire unified TLB Inner Shareable BX lr - + // ------------------------------------------------------------ // Branch Prediction @@ -319,7 +319,7 @@ flushBranchTargetCache: MOV r0, #0 MCR p15, 0, r0, c7, c5, 6 // BPIALL - Invalidate entire branch predictor array BX lr - + .global flushBranchTargetCache_IS .type flushBranchTargetCache_IS,function @@ -328,7 +328,7 @@ flushBranchTargetCache_IS: MOV r0, #0 MCR p15, 0, r0, c7, c1, 6 // BPIALLIS - Invalidate entire branch predictor array Inner Shareable BX lr - + // ------------------------------------------------------------ // High Vecs @@ -343,7 +343,7 @@ enableHighVecs: MCR p15, 0, r0, c1, c0, 0 // Write Control Register ISB BX lr - + .global disableHighVecs .type disableHighVecs,function @@ -354,7 +354,7 @@ disableHighVecs: MCR p15, 0, r0, c1, c0, 0 // Write Control Register ISB BX lr - + // ------------------------------------------------------------ // Context ID @@ -366,7 +366,7 @@ disableHighVecs: getContextID: MRC p15, 0, r0, c13, c0, 1 // Read Context ID Register BX lr - + .global setContextID .type setContextID,function @@ -374,7 +374,7 @@ getContextID: setContextID: MCR p15, 0, r0, c13, c0, 1 // Write Context ID Register BX lr - + // ------------------------------------------------------------ // ID registers @@ -386,7 +386,7 @@ setContextID: getMIDR: MRC p15, 0, r0, c0, c0, 0 // Read Main ID Register (MIDR) BX lr - + .global getMPIDR .type getMPIDR,function @@ -394,7 +394,7 @@ getMIDR: getMPIDR: MRC p15, 0, r0, c0 ,c0, 5// Read Multiprocessor ID register (MPIDR) BX lr - + // ------------------------------------------------------------ // CP15 SMP related @@ -407,7 +407,7 @@ getMPIDR: getBaseAddr: MRC p15, 4, r0, c15, c0, 0 // Read peripheral base address BX lr - + // ------------------------------------------------------------ @@ -419,7 +419,7 @@ getCPUID: MRC p15, 0, r0, c0, c0, 5 // Read CPU ID register AND r0, r0, #0x03 // Mask off, leaving the CPU ID field BX lr - + // ------------------------------------------------------------ @@ -431,7 +431,7 @@ goToSleep: WFI // Go into standby B goToSleep // Catch in case of rogue events BX lr - + // ------------------------------------------------------------ @@ -451,7 +451,7 @@ joinSMP: ISB BX lr - + // ------------------------------------------------------------ @@ -469,7 +469,7 @@ leaveSMP: ISB BX lr - + // ------------------------------------------------------------ // End of v7.s diff --git a/ports_arch/ARMv7-A/threadx/ports/iar/example_build/tx_initialize_low_level.s b/ports_arch/ARMv7-A/threadx/ports/iar/example_build/tx_initialize_low_level.s index a1ecbe93..96c5b0a0 100644 --- a/ports_arch/ARMv7-A/threadx/ports/iar/example_build/tx_initialize_low_level.s +++ b/ports_arch/ARMv7-A/threadx/ports/iar/example_build/tx_initialize_low_level.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -93,16 +94,6 @@ __tx_free_memory_start /* CALLED BY */ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* */ -/* */ /**************************************************************************/ //VOID _tx_initialize_low_level(VOID) //{ diff --git a/ports_arch/ARMv7-A/update.ps1 b/ports_arch/ARMv7-A/update.ps1 index c444f1d6..5c3e9905 100644 --- a/ports_arch/ARMv7-A/update.ps1 +++ b/ports_arch/ARMv7-A/update.ps1 @@ -104,7 +104,7 @@ If (-Not (Test-Path -Path $LogDir -PathType Container)) { Function Copy-FilesVerbose { [CmdletBinding()] Param ( - [string] $source, + [string] $source, [string] $destination_directory ) Write-Verbose ("Copying common files...") @@ -126,9 +126,9 @@ ForEach ($PortSet in $PortSets) { $compiler_directory = $core_directory + "\" + $compiler Write-Verbose ("Compiler directory: $compiler_directory") $compiler_directory_object = New-Item -Path $compiler_directory -ItemType "directory" -Force - + $destination_directory = $compiler_directory - + If ($CopyCommonFiles) { Copy-FilesVerbose -source "threadx\common\*" -destination_directory $destination_directory } @@ -136,7 +136,7 @@ ForEach ($PortSet in $PortSets) { If ($CopyPortFiles) { Copy-FilesVerbose -source "threadx\ports\$compiler\*" -destination_directory $destination_directory } - + If ($PortSet -eq 'tx_smp') { If ($CopyCommonFiles) { Copy-FilesVerbose -source "threadx_smp\common\*" -destination_directory $destination_directory diff --git a/ports_arch/ARMv7-M/threadx/ac5/example_build/sample_threadx.c b/ports_arch/ARMv7-M/threadx/ac5/example_build/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports_arch/ARMv7-M/threadx/ac5/example_build/sample_threadx.c +++ b/ports_arch/ARMv7-M/threadx/ac5/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_arch/ARMv7-M/threadx/ac5/example_build/tx_initialize_low_level.s b/ports_arch/ARMv7-M/threadx/ac5/example_build/tx_initialize_low_level.s index 5ebe3739..c51e67cf 100644 --- a/ports_arch/ARMv7-M/threadx/ac5/example_build/tx_initialize_low_level.s +++ b/ports_arch/ARMv7-M/threadx/ac5/example_build/tx_initialize_low_level.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -134,16 +135,6 @@ Reset_Handler /* CALLED BY */ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx/ac5/readme_threadx.txt b/ports_arch/ARMv7-M/threadx/ac5/readme_threadx.txt index b7b7cee9..e261213e 100644 --- a/ports_arch/ARMv7-M/threadx/ac5/readme_threadx.txt +++ b/ports_arch/ARMv7-M/threadx/ac5/readme_threadx.txt @@ -5,14 +5,14 @@ 1. Building the ThreadX run-time Library -Navigate to the "example_build" directory. Ensure that -you have setup your path and other environment variables necessary for the AC5 -compiler. At this point you may run the build_threadx.bat batch file. This will -build the ThreadX run-time environment in the "example_build" directory. +Navigate to the "example_build" directory. Ensure that +you have setup your path and other environment variables necessary for the AC5 +compiler. At this point you may run the build_threadx.bat batch file. This will +build the ThreadX run-time environment in the "example_build" directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. @@ -21,28 +21,28 @@ application in order to use ThreadX. The ThreadX demonstration is designed to execute under the ARM DS Cortex-M simulator. -Building the demonstration is easy; simply execute the build_threadx_sample.bat +Building the demonstration is easy; simply execute the build_threadx_sample.bat batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with tx.a. The resulting file sample_threadx.axf +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.axf is a binary file that can be downloaded and executed on the ARM DS Cortex-M simulator. 3. System Initialization -The entry point in ThreadX for the Cortex-M using AC5 tools is at label -__main. This is defined within the AC5 compiler's startup code. In -addition, this is where all static and global pre-set C variable +The entry point in ThreadX for the Cortex-M using AC5 tools is at label +__main. This is defined within the AC5 compiler's startup code. In +addition, this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. @@ -51,7 +51,7 @@ parameter to your application definition function, tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -134,21 +134,21 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 5. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the ThreadX library project to enable various compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: @@ -187,8 +187,8 @@ your_assembly_isr 7. FPU Support -ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context - no additional setup by the application. diff --git a/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_context_restore.s b/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_context_restore.s index 7b61ef86..37419f33 100644 --- a/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_context_restore.s +++ b/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_context_save.s b/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_context_save.s index e038a391..17f1230a 100644 --- a/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_context_save.s +++ b/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_interrupt_control.s b/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_interrupt_control.s index f3ef40fc..c564ecf1 100644 --- a/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_interrupt_control.s +++ b/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_interrupt_disable.s b/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_interrupt_disable.s index 263a7a73..ffa91327 100644 --- a/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_interrupt_disable.s +++ b/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_interrupt_restore.s b/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_interrupt_restore.s index e96af978..ef5da941 100644 --- a/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_interrupt_restore.s +++ b/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_schedule.s b/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_schedule.s index 2ea9b0bc..12da7d69 100644 --- a/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_schedule.s +++ b/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,17 +68,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 04-25-2022 Scott Larson Added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_stack_build.s b/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_stack_build.s index 0583d81a..136cd319 100644 --- a/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_stack_build.s +++ b/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_system_return.s b/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_system_return.s index 73466e78..4de21997 100644 --- a/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_system_return.s +++ b/ports_arch/ARMv7-M/threadx/ac5/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx/ac5/src/tx_timer_interrupt.s b/ports_arch/ARMv7-M/threadx/ac5/src/tx_timer_interrupt.s index 1245455d..b89a6239 100644 --- a/ports_arch/ARMv7-M/threadx/ac5/src/tx_timer_interrupt.s +++ b/ports_arch/ARMv7-M/threadx/ac5/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,18 +72,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx/ac6/example_build/sample_threadx/sample_threadx.c b/ports_arch/ARMv7-M/threadx/ac6/example_build/sample_threadx/sample_threadx.c index 597f373c..13ffadba 100644 --- a/ports_arch/ARMv7-M/threadx/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_arch/ARMv7-M/threadx/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -81,42 +81,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -124,23 +124,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -243,11 +243,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -306,7 +306,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -359,7 +359,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_arch/ARMv7-M/threadx/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports_arch/ARMv7-M/threadx/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 3546dee5..af332d80 100644 --- a/ports_arch/ARMv7-M/threadx/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports_arch/ARMv7-M/threadx/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -76,15 +77,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx/ac6/example_build/tx/.cproject b/ports_arch/ARMv7-M/threadx/ac6/example_build/tx/.cproject index b7df20f1..4965a680 100644 --- a/ports_arch/ARMv7-M/threadx/ac6/example_build/tx/.cproject +++ b/ports_arch/ARMv7-M/threadx/ac6/example_build/tx/.cproject @@ -1,150 +1,150 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_arch/ARMv7-M/threadx/ac6/readme_threadx.txt b/ports_arch/ARMv7-M/threadx/ac6/readme_threadx.txt index d98c90cb..6447c517 100644 --- a/ports_arch/ARMv7-M/threadx/ac6/readme_threadx.txt +++ b/ports_arch/ARMv7-M/threadx/ac6/readme_threadx.txt @@ -5,12 +5,12 @@ 1. Building the ThreadX run-time Library -In order to build the ThreadX library and the ThreadX demonstration, first import -the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +In order to build the ThreadX library and the ThreadX demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) into your DS workspace. -Building the ThreadX library is easy; simply right-click the Eclipse project -"tx" and then select the "Build Project" button. You should now observe the compilation +Building the ThreadX library is easy; simply right-click the Eclipse project +"tx" and then select the "Build Project" button. You should now observe the compilation and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. @@ -20,27 +20,27 @@ library file tx.a. The ThreadX demonstration is designed to execute under the DS debugger on the MPS2_Cortex_Mx Bare Metal simulator. -Building the demonstration is easy; simply right-click the Eclipse project -"sample_threadx" and then select the "Build Project" button. You should now observe -the compilation and assembly of the ThreadX demonstration. This project build produces -the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder +Building the demonstration is easy; simply right-click the Eclipse project +"sample_threadx" and then select the "Build Project" button. You should now observe +the compilation and assembly of the ThreadX demonstration. This project build produces +the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder in the Project Explorer window, right-click on the 'cortex-mx_tx.launch' file, click 'Debug As', and then click 'cortex-mx_tx' from the submenu. This will cause the -debugger to load the sample_threadx.axf ELF file and run to main. You are now ready +debugger to load the sample_threadx.axf ELF file and run to main. You are now ready to execute the ThreadX demonstration. 3. System Initialization -The entry point in ThreadX for the Cortex-M using AC6 tools uses the standard GNU +The entry point in ThreadX for the Cortex-M using AC6 tools uses the standard GNU Cortex-M reset sequence. From the reset vector the C runtime will be initialized. -The ThreadX tx_initialize_low_level.S file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. +The ThreadX tx_initialize_low_level.S file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. @@ -49,7 +49,7 @@ parameter to your application definition function, tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -132,34 +132,34 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 5. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the ThreadX library project to enable various compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 6.1 Vector Area The Cortex-M vectors start at the label __tx_vectors or similar. The application may modify -the vector area according to its needs. There is code in tx_initialize_low_level() that will -configure the vector base register. +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. 6.2 Managed Interrupts -A ThreadX managed interrupt is defined below. By following these conventions, the +A ThreadX managed interrupt is defined below. By following these conventions, the application ISR is then allowed access to various ThreadX services from the ISR. Here is the standard template for managed ISRs in ThreadX: @@ -181,15 +181,15 @@ __tx_IntHandler: Note: the Cortex-M requires exception handlers to be thumb labels, this implies bit 0 set. To accomplish this, the declaration of the label has to be preceded by the assembler directive -.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to -be inserted in the correct location in the interrupt vector table. This table is typically +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically located in either your runtime startup file or in the tx_initialize_low_level.S file. 7. FPU Support -ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context - no additional setup by the application. diff --git a/ports_arch/ARMv7-M/threadx/ac6/src/tx_misra.S b/ports_arch/ARMv7-M/threadx/ac6/src/tx_misra.S index 8ac0c629..10548671 100644 --- a/ports_arch/ARMv7-M/threadx/ac6/src/tx_misra.S +++ b/ports_arch/ARMv7-M/threadx/ac6/src/tx_misra.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -667,7 +668,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -682,7 +683,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARM_FP /***********************************************************************************************/ @@ -699,8 +700,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -714,9 +715,9 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - + .data .word 0 diff --git a/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_context_restore.S b/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_context_restore.S index f7806505..530ef2ff 100644 --- a/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_context_restore.S +++ b/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_context_save.S b/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_context_save.S index 9e995227..d36f71a0 100644 --- a/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_context_save.S +++ b/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,14 +61,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_interrupt_control.S b/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_interrupt_control.S index f40060d4..6b78eb9d 100644 --- a/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_interrupt_control.S +++ b/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_interrupt_disable.S b/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_interrupt_disable.S index 0b7cb34a..3f4aafc3 100644 --- a/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_interrupt_disable.S +++ b/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_interrupt_restore.S b/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_interrupt_restore.S index 678b6753..07b0134c 100644 --- a/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_interrupt_restore.S +++ b/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_schedule.S b/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_schedule.S index f6a5b271..1aade9e5 100644 --- a/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_schedule.S +++ b/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,16 +71,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 04-25-2022 Scott Larson Added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_stack_build.S b/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_stack_build.S index 17a07275..66427498 100644 --- a/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_stack_build.S +++ b/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_system_return.S b/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_system_return.S index bfcbc652..75d51813 100644 --- a/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_system_return.S +++ b/ports_arch/ARMv7-M/threadx/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx/ac6/src/tx_timer_interrupt.S b/ports_arch/ARMv7-M/threadx/ac6/src/tx_timer_interrupt.S index 67a48265..39bd280f 100644 --- a/ports_arch/ARMv7-M/threadx/ac6/src/tx_timer_interrupt.S +++ b/ports_arch/ARMv7-M/threadx/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,17 +71,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx/ghs/example_build/tx_initialize_low_level.arm b/ports_arch/ARMv7-M/threadx/ghs/example_build/tx_initialize_low_level.arm index 56269d1a..57c964b3 100644 --- a/ports_arch/ARMv7-M/threadx/ghs/example_build/tx_initialize_low_level.arm +++ b/ports_arch/ARMv7-M/threadx/ghs/example_build/tx_initialize_low_level.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_arch/ARMv7-M/threadx/ghs/inc/tx_el.h b/ports_arch/ARMv7-M/threadx/ghs/inc/tx_el.h index b8926921..72e5bbe3 100644 --- a/ports_arch/ARMv7-M/threadx/ghs/inc/tx_el.h +++ b/ports_arch/ARMv7-M/threadx/ghs/inc/tx_el.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,12 +37,6 @@ /* EventAnalyzer. It is assumed that tx_api.h and tx_port.h have */ /* already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_EL_H diff --git a/ports_arch/ARMv7-M/threadx/ghs/inc/tx_port.h b/ports_arch/ARMv7-M/threadx/ghs/inc/tx_port.h index d98914d7..eb5c9daf 100644 --- a/ports_arch/ARMv7-M/threadx/ghs/inc/tx_port.h +++ b/ports_arch/ARMv7-M/threadx/ghs/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,12 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -392,7 +387,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv7-M Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-M Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_arch/ARMv7-M/threadx/ghs/readme_threadx.txt b/ports_arch/ARMv7-M/threadx/ghs/readme_threadx.txt index 2f0cc0ea..784ccf41 100644 --- a/ports_arch/ARMv7-M/threadx/ghs/readme_threadx.txt +++ b/ports_arch/ARMv7-M/threadx/ghs/readme_threadx.txt @@ -4,16 +4,16 @@ 1. Open the ThreadX Project Workspace -In order to build the ThreadX library and the ThreadX demonstration first load -the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the -"example_build" directory. +In order to build the ThreadX library and the ThreadX demonstration first load +the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the +"example_build" directory. 2. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply select the MULTI project file -tx.gpj and then select the build button. You should now observe the -compilation and assembly of the ThreadX library. This project build produces +Building the ThreadX library is easy; simply select the MULTI project file +tx.gpj and then select the build button. You should now observe the +compilation and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. @@ -21,52 +21,52 @@ the ThreadX library file tx.a. The ThreadX demonstration is designed to execute under the MULTI environment on the Green Hills Cortex-M7 simulator. The instructions that follow describe -how to get the ThreadX evaluation running under the MULTI Cortex-M7 simulation +how to get the ThreadX evaluation running under the MULTI Cortex-M7 simulation environment. -Building the demonstration is easy; simply select the MULTI project file -sample_threadx.gpj. At this point, select the "Project Build" button and observe -the compilation, assembly, and linkage of the ThreadX demonstration application. +Building the demonstration is easy; simply select the MULTI project file +sample_threadx.gpj. At this point, select the "Project Build" button and observe +the compilation, assembly, and linkage of the ThreadX demonstration application. -After the demonstration is built, invoke the MULTI ARM simulator by selecting -the simulator connection from within the sample_threadx.con connection file. -Once connected to the simulator, select the "Debug" button. You should now -observe the main function of sample_threadx.c. +After the demonstration is built, invoke the MULTI ARM simulator by selecting +the simulator connection from within the sample_threadx.con connection file. +Once connected to the simulator, select the "Debug" button. You should now +observe the main function of sample_threadx.c. -You are now ready to execute the ThreadX demonstration system. Select -breakpoints and data watches to observe the execution of the sample_threadx.c +You are now ready to execute the ThreadX demonstration system. Select +breakpoints and data watches to observe the execution of the sample_threadx.c application. 4. EventAnalyzer Demonstration -To build a demonstration system that also logs events for the MULTI EventAnalyzer, -perform the same steps as the regular demo, except build the ThreadX library with -txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. -The resulting image will log all system events, which can then be displayed by the +To build a demonstration system that also logs events for the MULTI EventAnalyzer, +perform the same steps as the regular demo, except build the ThreadX library with +txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. +The resulting image will log all system events, which can then be displayed by the MULTI EventAnalyzer. 5. System Initialization -The system entry point using the Green Hills tools is at the label _start. -This is defined within the crt0.arm file supplied by Green Hills. In addition, -this is where all static and global preset C variable initialization +The system entry point using the Green Hills tools is at the label _start. +This is defined within the crt0.arm file supplied by Green Hills. In addition, +this is where all static and global preset C variable initialization processing is called from. After the Green Hills startup function returns, ThreadX initialization is called. The main initialization function is _tx_initialize_low_level and -is located in the file tx_initialize_low_level.arm. This function is responsible -for setting up various system data structures, interrupt vectors, and the +is located in the file tx_initialize_low_level.arm. This function is responsible +for setting up various system data structures, interrupt vectors, and the periodic timer interrupt source of ThreadX. -In addition, _tx_initialize_low_level determines where the first available +In addition, _tx_initialize_low_level determines where the first available RAM memory address is located. This address is supplied to tx_application_define. -By default, the first available RAM memory address is assumed to start at the -beginning of the ThreadX section .free_mem. If changes are made to the -sample_threadx.ld file, the .free_mem section should remain the last allocated -section in the main RAM area. The starting address of this section is passed +By default, the first available RAM memory address is assumed to start at the +beginning of the ThreadX section .free_mem. If changes are made to the +sample_threadx.ld file, the .free_mem section should remain the last allocated +section in the main RAM area. The starting address of this section is passed to tx_application_define. @@ -75,13 +75,13 @@ to tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M7 version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: - Stack Offset Stack Contents + Stack Offset Stack Contents 0x00 r4 0x04 r5 @@ -102,7 +102,7 @@ Non-FPU Stack Frame: FPU Stack Frame (only interrupted thread with FPU enabled): - Stack Offset Stack Contents + Stack Offset Stack Contents 0x00 s0 0x04 s1 @@ -137,41 +137,41 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 0x78 s30 0x7C s31 0x80 fpscr - 0x84 r4 - 0x88 r5 - 0x8C r6 - 0x90 r7 - 0x94 r8 - 0x98 r9 - 0x9C r10 (sl) - 0xA0 r11 + 0x84 r4 + 0x88 r5 + 0x8C r6 + 0x90 r7 + 0x94 r8 + 0x98 r9 + 0x9C r10 (sl) + 0xA0 r11 0xA4 r0 (Hardware stack starts here!!) - 0xA8 r1 - 0xAC r2 - 0xB0 r3 - 0xB4 r12 - 0xB8 lr - 0xBC pc - 0xC0 xPSR + 0xA8 r1 + 0xAC r2 + 0xB0 r3 + 0xB4 r12 + 0xB8 lr + 0xBC pc + 0xC0 xPSR 7. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make ThreadX run faster, you can change the tx.gpj project -to disable debug information and enable the desired optimizations. +to disable debug information and enable the desired optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined before tx_api.h is included. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. 8. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M7 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: @@ -183,7 +183,7 @@ the vector area according to its needs. 8.2 Managed Interrupts -A ThreadX managed interrupt is defined below. By following these conventions, the +A ThreadX managed interrupt is defined below. By following these conventions, the application ISR is then allowed access to various ThreadX services from the ISR. Here is the standard template for managed ISRs in ThreadX: @@ -192,7 +192,7 @@ Here is the standard template for managed ISRs in ThreadX: __tx_IntHandler: PUSH {lr} BL _tx_thread_context_save - + /* Do interrupt handler work here */ B _tx_thread_context_restore @@ -202,7 +202,7 @@ __tx_IntHandler: By default, FPU support is disabled for each thread. If saving the context of the FPU registers is needed, the ThreadX library should be re-built with TX_ENABLE_FPU_SUPPORT defined. In addition, -the following API call must be made from the context of the application thread - before +the following API call must be made from the context of the application thread - before the FPU usage: void tx_thread_fpu_enable(void); @@ -223,7 +223,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -05/19/2020 Initial ThreadX version of Cortex-M7/Green Hills port. +05/19/2020 Initial ThreadX version of Cortex-M7/Green Hills port. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports_arch/ARMv7-M/threadx/ghs/src/tx_el.c b/ports_arch/ARMv7-M/threadx/ghs/src/tx_el.c index 365622cd..b5d3b8b7 100644 --- a/ports_arch/ARMv7-M/threadx/ghs/src/tx_el.c +++ b/ports_arch/ARMv7-M/threadx/ghs/src/tx_el.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,12 +83,6 @@ UINT _tx_thread_interrupt_control(UINT new_posture); /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_el_initialize(VOID) { diff --git a/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_context_restore.arm b/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_context_restore.arm index 3c1e598e..baede5ae 100644 --- a/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_context_restore.arm +++ b/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_context_restore.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_context_save.arm b/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_context_save.arm index 03ae47d3..fe0497e9 100644 --- a/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_context_save.arm +++ b/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_context_save.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_interrupt_control.arm b/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_interrupt_control.arm index a3272bcb..89972e7c 100644 --- a/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_interrupt_control.arm +++ b/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_interrupt_control.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_interrupt_disable.arm b/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_interrupt_disable.arm index feb445a1..e45bd1b7 100644 --- a/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_interrupt_disable.arm +++ b/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_interrupt_disable.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_interrupt_restore.arm b/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_interrupt_restore.arm index f07e4cc7..ccde153e 100644 --- a/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_interrupt_restore.arm +++ b/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_interrupt_restore.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_schedule.arm b/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_schedule.arm index 71ae7209..428c8833 100644 --- a/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_schedule.arm +++ b/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_schedule.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_stack_build.arm b/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_stack_build.arm index 3a6160dc..37b19779 100644 --- a/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_stack_build.arm +++ b/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_stack_build.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_system_return.arm b/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_system_return.arm index 8a0f1758..0f40b87e 100644 --- a/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_system_return.arm +++ b/ports_arch/ARMv7-M/threadx/ghs/src/tx_thread_system_return.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_arch/ARMv7-M/threadx/ghs/src/tx_timer_interrupt.arm b/ports_arch/ARMv7-M/threadx/ghs/src/tx_timer_interrupt.arm index 7cba814e..08a636e3 100644 --- a/ports_arch/ARMv7-M/threadx/ghs/src/tx_timer_interrupt.arm +++ b/ports_arch/ARMv7-M/threadx/ghs/src/tx_timer_interrupt.arm @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_arch/ARMv7-M/threadx/gnu/example_build/cortexm4_crt0.S b/ports_arch/ARMv7-M/threadx/gnu/example_build/cortexm4_crt0.S index 4228fc11..e06430d7 100644 --- a/ports_arch/ARMv7-M/threadx/gnu/example_build/cortexm4_crt0.S +++ b/ports_arch/ARMv7-M/threadx/gnu/example_build/cortexm4_crt0.S @@ -39,7 +39,7 @@ crt0_ctor_loop: beq crt0_ctor_end ldr r2, [r0] add r0, #4 - push {r0-r1} + push {r0-r1} blx r2 pop {r0-r1} b crt0_ctor_loop @@ -88,4 +88,3 @@ memory_set_done: .section .stack, "wa", %nobits .section .stack_process, "wa", %nobits .section .heap, "wa", %nobits - \ No newline at end of file diff --git a/ports_arch/ARMv7-M/threadx/gnu/example_build/cortexm4_vectors.S b/ports_arch/ARMv7-M/threadx/gnu/example_build/cortexm4_vectors.S index 714944d5..7f3832f0 100644 --- a/ports_arch/ARMv7-M/threadx/gnu/example_build/cortexm4_vectors.S +++ b/ports_arch/ARMv7-M/threadx/gnu/example_build/cortexm4_vectors.S @@ -4,8 +4,8 @@ .global __tx_BadHandler .global __tx_SVCallHandler .global __tx_DBGHandler - .global PendSV_Handler - .global __tx_SysTickHandler + .global PendSV_Handler + .global __tx_SysTickHandler .global __tx_BadHandler .syntax unified @@ -15,9 +15,9 @@ .global _vectors _vectors: - .word __stack_end__ - .word reset_handler - .word __tx_NMIHandler + .word __stack_end__ + .word reset_handler + .word __tx_NMIHandler .word __tx_HardfaultHandler .word __tx_BadHandler .word __tx_BadHandler @@ -29,7 +29,7 @@ _vectors: .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // .word __tx_DBGHandler .word 0 // Reserved - .word PendSV_Handler + .word PendSV_Handler .word __tx_SysTickHandler // Used by Threadx timer functionality .word __tx_BadHandler // Populate with user Interrupt handler .word __tx_BadHandler diff --git a/ports_arch/ARMv7-M/threadx/gnu/example_build/sample_threadx.c b/ports_arch/ARMv7-M/threadx/gnu/example_build/sample_threadx.c index 597f373c..13ffadba 100644 --- a/ports_arch/ARMv7-M/threadx/gnu/example_build/sample_threadx.c +++ b/ports_arch/ARMv7-M/threadx/gnu/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -81,42 +81,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -124,23 +124,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -243,11 +243,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -306,7 +306,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -359,7 +359,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_arch/ARMv7-M/threadx/gnu/example_build/sample_threadx.ld b/ports_arch/ARMv7-M/threadx/gnu/example_build/sample_threadx.ld index c65a1346..3f19c29e 100644 --- a/ports_arch/ARMv7-M/threadx/gnu/example_build/sample_threadx.ld +++ b/ports_arch/ARMv7-M/threadx/gnu/example_build/sample_threadx.ld @@ -10,7 +10,7 @@ __HEAPSIZE__ = 128; SECTIONS { - .vectors : + .vectors : { KEEP(*(.vectors .vectors.*)) } > FLASH @@ -45,7 +45,7 @@ SECTIONS KEEP(*(.eh_frame*)) } > FLASH - .ARM.extab : + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH @@ -59,7 +59,7 @@ SECTIONS __data_load_start__ = ALIGN (4); - .data : AT (__data_load_start__) + .data : AT (__data_load_start__) { __data_start__ = .; @@ -89,7 +89,7 @@ SECTIONS KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ - + __data_end__ = .; } > RAM @@ -104,7 +104,7 @@ SECTIONS __bss_end__ = .; } > RAM - + .heap (COPY): { __heap_start__ = ALIGN(4); diff --git a/ports_arch/ARMv7-M/threadx/gnu/example_build/tx_initialize_low_level.S b/ports_arch/ARMv7-M/threadx/gnu/example_build/tx_initialize_low_level.S index afc28b48..8fce83db 100644 --- a/ports_arch/ARMv7-M/threadx/gnu/example_build/tx_initialize_low_level.S +++ b/ports_arch/ARMv7-M/threadx/gnu/example_build/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -73,15 +74,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx/gnu/readme_threadx.txt b/ports_arch/ARMv7-M/threadx/gnu/readme_threadx.txt index d9063d65..58181f85 100644 --- a/ports_arch/ARMv7-M/threadx/gnu/readme_threadx.txt +++ b/ports_arch/ARMv7-M/threadx/gnu/readme_threadx.txt @@ -5,15 +5,15 @@ 1. Building the ThreadX run-time Library -Navigate to the "example_build" directory. Ensure that -you have setup your path and other environment variables necessary for the ARM -GNU compiler. At this point you may run the build_threadx.bat batch file. -This will build the ThreadX run-time environment in the "example_build" -directory. +Navigate to the "example_build" directory. Ensure that +you have setup your path and other environment variables necessary for the ARM +GNU compiler. At this point you may run the build_threadx.bat batch file. +This will build the ThreadX run-time environment in the "example_build" +directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. @@ -22,25 +22,25 @@ application in order to use ThreadX. The ThreadX demonstration is designed to execute on Cortex-M evaluation boards or on a dedicated simulator. -Building the demonstration is easy, simply execute the build_threadx_sample.bat +Building the demonstration is easy, simply execute the build_threadx_sample.bat batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with tx.a. The resulting file sample_threadx.out is a binary +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.out is a binary file that can be downloaded and executed on the a simulator, or downloaded to a board. 3. System Initialization -The entry point in ThreadX for the Cortex-M using gnu tools uses the standard GNU +The entry point in ThreadX for the Cortex-M using gnu tools uses the standard GNU Cortex-M reset sequence. From the reset vector the C runtime will be initialized. -The ThreadX tx_initialize_low_level.S file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. +The ThreadX tx_initialize_low_level.S file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. @@ -49,7 +49,7 @@ parameter to your application definition function, tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -132,34 +132,34 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 5. Improving Performance -The distribution version of ThreadX is built without any compiler optimizations. -This makes it easy to debug because you can trace or set breakpoints inside of -ThreadX itself. Of course, this costs some performance. To make it run faster, -you can change the build_threadx.bat file to remove the -g option and enable -all compiler optimizations. +The distribution version of ThreadX is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX itself. Of course, this costs some performance. To make it run faster, +you can change the build_threadx.bat file to remove the -g option and enable +all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-M -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 6.1 Vector Area The Cortex-M vectors start at the label __tx_vectors or similar. The application may modify -the vector area according to its needs. There is code in tx_initialize_low_level() that will -configure the vector base register. +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. 6.2 Managed Interrupts -A ThreadX managed interrupt is defined below. By following these conventions, the +A ThreadX managed interrupt is defined below. By following these conventions, the application ISR is then allowed access to various ThreadX services from the ISR. Here is the standard template for managed ISRs in ThreadX: @@ -181,15 +181,15 @@ __tx_IntHandler: Note: the Cortex-M requires exception handlers to be thumb labels, this implies bit 0 set. To accomplish this, the declaration of the label has to be preceded by the assembler directive -.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to -be inserted in the correct location in the interrupt vector table. This table is typically +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically located in either your runtime startup file or in the tx_initialize_low_level.S file. 7. FPU Support -ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context - no additional setup by the application. diff --git a/ports_arch/ARMv7-M/threadx/gnu/src/tx_misra.S b/ports_arch/ARMv7-M/threadx/gnu/src/tx_misra.S index 8ac0c629..10548671 100644 --- a/ports_arch/ARMv7-M/threadx/gnu/src/tx_misra.S +++ b/ports_arch/ARMv7-M/threadx/gnu/src/tx_misra.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -667,7 +668,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -682,7 +683,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARM_FP /***********************************************************************************************/ @@ -699,8 +700,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -714,9 +715,9 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - + .data .word 0 diff --git a/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_context_restore.S b/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_context_restore.S index 4c734a07..202da934 100644 --- a/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_context_restore.S +++ b/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_context_save.S b/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_context_save.S index 7d16fdf7..cfd47ebe 100644 --- a/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_context_save.S +++ b/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_interrupt_control.S b/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_interrupt_control.S index fdb3bbb0..5946f28a 100644 --- a/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_interrupt_control.S +++ b/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_interrupt_disable.S b/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_interrupt_disable.S index 666d934e..3c6e0b80 100644 --- a/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_interrupt_disable.S +++ b/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_interrupt_restore.S b/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_interrupt_restore.S index 4adebd17..e8c9ca45 100644 --- a/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_interrupt_restore.S +++ b/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_schedule.S b/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_schedule.S index 474eab0c..65c5ad50 100644 --- a/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_schedule.S +++ b/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,18 +69,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Fixed predefined macro name, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_stack_build.S b/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_stack_build.S index 23563935..bd9718fd 100644 --- a/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_stack_build.S +++ b/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_system_return.S b/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_system_return.S index a0174cc2..8b681747 100644 --- a/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_system_return.S +++ b/ports_arch/ARMv7-M/threadx/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx/gnu/src/tx_timer_interrupt.S b/ports_arch/ARMv7-M/threadx/gnu/src/tx_timer_interrupt.S index 08a75fc1..c966161a 100644 --- a/ports_arch/ARMv7-M/threadx/gnu/src/tx_timer_interrupt.S +++ b/ports_arch/ARMv7-M/threadx/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,17 +71,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx/iar/example_build/cstartup_M.s b/ports_arch/ARMv7-M/threadx/iar/example_build/cstartup_M.s index 8b7fbc0d..a01d262a 100644 --- a/ports_arch/ARMv7-M/threadx/iar/example_build/cstartup_M.s +++ b/ports_arch/ARMv7-M/threadx/iar/example_build/cstartup_M.s @@ -2,16 +2,16 @@ PUBLIC __vector_table SECTION .text:CODE:REORDER(1) - + ;; Keep vector table even if it's not referenced REQUIRE __vector_table - + THUMB - + ;; Forward declaration of sections. SECTION CSTACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) - + DATA __vector_table diff --git a/ports_arch/ARMv7-M/threadx/iar/example_build/sample_threadx.c b/ports_arch/ARMv7-M/threadx/iar/example_build/sample_threadx.c index 60f5a3d3..55b63731 100644 --- a/ports_arch/ARMv7-M/threadx/iar/example_build/sample_threadx.c +++ b/ports_arch/ARMv7-M/threadx/iar/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete description of this demonstration. */ @@ -69,7 +69,7 @@ void thread_6_and_7_entry(ULONG thread_input); int main() { - + /* Please refer to Chapter 6 of the ThreadX User Guide for a complete description of this demonstration. */ @@ -101,41 +101,41 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -143,23 +143,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -262,11 +262,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -325,7 +325,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -378,7 +378,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_arch/ARMv7-M/threadx/iar/example_build/tx_initialize_low_level.s b/ports_arch/ARMv7-M/threadx/iar/example_build/tx_initialize_low_level.s index 585a3dc8..d2c2e07f 100644 --- a/ports_arch/ARMv7-M/threadx/iar/example_build/tx_initialize_low_level.s +++ b/ports_arch/ARMv7-M/threadx/iar/example_build/tx_initialize_low_level.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -69,16 +70,6 @@ __tx_free_memory_start /* CALLED BY */ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx/iar/readme_threadx.txt b/ports_arch/ARMv7-M/threadx/iar/readme_threadx.txt index 28b54e03..388c40e6 100644 --- a/ports_arch/ARMv7-M/threadx/iar/readme_threadx.txt +++ b/ports_arch/ARMv7-M/threadx/iar/readme_threadx.txt @@ -6,45 +6,45 @@ 1. Building the ThreadX run-time Library Building the ThreadX library is easy. First, open the Azure RTOS workspace -azure_rtos.eww. Next, make the TX project the "active project" in the -IAR Embedded Workbench and select the "Make" button. You should observe -assembly and compilation of a series of ThreadX source files. This -results in the ThreadX run-time library file tx.a, which is needed by +azure_rtos.eww. Next, make the TX project the "active project" in the +IAR Embedded Workbench and select the "Make" button. You should observe +assembly and compilation of a series of ThreadX source files. This +results in the ThreadX run-time library file tx.a, which is needed by the application. 2. Demonstration System -The ThreadX demonstration is designed to execute under the IAR debugger under +The ThreadX demonstration is designed to execute under the IAR debugger under simulation. Building the demonstration is easy; simply open the threadx.www workspace file, -make the sample_threadx.ewp project the "active project" in the IAR Embedded +make the sample_threadx.ewp project the "active project" in the IAR Embedded Workbench, and select the "Make" button. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with tx.a. The resulting file sample_threadx.out is a -binary ELF file that can be downloaded and executed on the IAR Windows-based +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.out is a +binary ELF file that can be downloaded and executed on the IAR Windows-based Cortex-M simulator. 3. System Initialization -The entry point in ThreadX for the Cortex-M using IAR tools is at label -__iar_program_start. This is defined within the IAR compiler's startup code. -In addition, this is where all static and global preset C variable +The entry point in ThreadX for the Cortex-M using IAR tools is at label +__iar_program_start. This is defined within the IAR compiler's startup code. +In addition, this is where all static and global preset C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, and a periodic timer interrupt source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. By default, the vector area is defined at the top of cstartup_M.s, which is -a slightly modified from the base IAR file. +a slightly modified from the base IAR file. The _tx_initialize_low_level function inside of tx_initialize_low_level.s -also determines the first available address for use by the application, which -is supplied as the sole input parameter to your application definition function, -tx_application_define. To accomplish this, a section is created in -tx_initialize_low_level.s called FREE_MEM, which must be located after all +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all other RAM sections in memory. @@ -53,7 +53,7 @@ other RAM sections in memory. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-M version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -136,20 +136,20 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 5. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the ThreadX library project to enable various compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling -The Cortex-M vectors start at the label __vector_table and is defined in cstartup_M.s. +The Cortex-M vectors start at the label __vector_table and is defined in cstartup_M.s. The application may modify the vector area according to its needs. @@ -188,14 +188,14 @@ should have the following line added (if not already in place): initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application -The project options "General Options -> Library Configuration" should also have the +The project options "General Options -> Library Configuration" should also have the "Enable thread support in library" box selected. 8. VFP Support -ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-M supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context - no additional setup by the application. diff --git a/ports_arch/ARMv7-M/threadx/iar/src/tx_iar.c b/ports_arch/ARMv7-M/threadx/iar/src/tx_iar.c index ee47f10f..238b485e 100644 --- a/ports_arch/ARMv7-M/threadx/iar/src/tx_iar.c +++ b/ports_arch/ARMv7-M/threadx/iar/src/tx_iar.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports_arch/ARMv7-M/threadx/iar/src/tx_misra.s b/ports_arch/ARMv7-M/threadx/iar/src/tx_misra.s index f86d9a65..642bb89e 100644 --- a/ports_arch/ARMv7-M/threadx/iar/src/tx_misra.s +++ b/ports_arch/ARMv7-M/threadx/iar/src/tx_misra.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -120,7 +121,7 @@ SECTION `.data`:DATA:REORDER:NOROOT(2) DATA -// 51 CHAR _tx_version_id[100] = "Copyright (c) 2024 Microsoft Corporation. * ThreadX 6.1 MISRA C Compliant *"; +// 51 CHAR _tx_version_id[100] = "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX 6.1 MISRA C Compliant *"; _tx_version_id: DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H @@ -707,7 +708,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -722,7 +723,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARMVFP__ /***********************************************************************************************/ @@ -739,8 +740,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -754,10 +755,10 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - - + + SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2) SECTION_TYPE SHT_PROGBITS, 0 DATA diff --git a/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_context_restore.s b/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_context_restore.s index 657e73c6..b77c22bc 100644 --- a/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_context_restore.s +++ b/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_context_save.s b/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_context_save.s index c21720ed..0980c63e 100644 --- a/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_context_save.s +++ b/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_interrupt_control.s b/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_interrupt_control.s index 77311f06..c5de9169 100644 --- a/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_interrupt_control.s +++ b/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_interrupt_disable.s b/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_interrupt_disable.s index 70310f96..24ff7aaa 100644 --- a/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_interrupt_disable.s +++ b/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_interrupt_restore.s b/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_interrupt_restore.s index aaa927c6..528a9759 100644 --- a/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_interrupt_restore.s +++ b/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_schedule.s b/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_schedule.s index 0035d150..d38774b8 100644 --- a/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_schedule.s +++ b/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,17 +68,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 04-25-2022 Scott Larson Added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_stack_build.s b/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_stack_build.s index 3accc5eb..b5e707d9 100644 --- a/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_stack_build.s +++ b/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_system_return.s b/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_system_return.s index b820a534..65bec5a5 100644 --- a/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_system_return.s +++ b/ports_arch/ARMv7-M/threadx/iar/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx/iar/src/tx_timer_interrupt.s b/ports_arch/ARMv7-M/threadx/iar/src/tx_timer_interrupt.s index 7ce6280c..d6101ce4 100644 --- a/ports_arch/ARMv7-M/threadx/iar/src/tx_timer_interrupt.s +++ b/ports_arch/ARMv7-M/threadx/iar/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,18 +72,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx/iar/tx_low_power.c b/ports_arch/ARMv7-M/threadx/iar/tx_low_power.c index b983ed9e..7a463f65 100644 --- a/ports_arch/ARMv7-M/threadx/iar/tx_low_power.c +++ b/ports_arch/ARMv7-M/threadx/iar/tx_low_power.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ UINT tx_low_power_entered; /* */ /* _tx_thread_schedule Thread scheduling loop */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* */ /**************************************************************************/ VOID tx_low_power_enter(VOID) { @@ -88,12 +83,12 @@ ULONG any_expired; /* The below macro is user-defined code to determine if low power mode is beneficial for the application. - Reasons for not entering low power mode include - the overhead associated with entering and exiting low power mode - outweighs the savings given when the next interrupt is expected. - In addition, the application might also be in a state where - responsiveness is more important than power savings. In such - situations, using a "reduced power mode" might make more sense. + Reasons for not entering low power mode include + the overhead associated with entering and exiting low power mode + outweighs the savings given when the next interrupt is expected. + In addition, the application might also be in a state where + responsiveness is more important than power savings. In such + situations, using a "reduced power mode" might make more sense. In any case, if low power mode is not desired, simply return at this point in the code. */ #ifdef TX_LOW_POWER_USER_CHECK @@ -102,45 +97,45 @@ ULONG any_expired; /* Disable interrupts while we prepare for low power mode. */ TX_DISABLE - + /* At this point, we want to enter low power mode, since nothing - meaningful is going on in the system. However, in order to keep - the ThreadX timer services accurate, we must first determine the - next ThreadX timer expiration in terms of ticks. This is + meaningful is going on in the system. However, in order to keep + the ThreadX timer services accurate, we must first determine the + next ThreadX timer expiration in terms of ticks. This is accomplished via the tx_timer_get_next API. */ any_expired = tx_timer_get_next(&tx_low_power_next_expiration); - + /* There are two possibilities: 1: A ThreadX timer is active. tx_timer_get_next returns TX_TRUE. Program the hardware timer source such that the next timer - interrupt is equal to: tx_low_power_next_expiration*tick_frequency. + interrupt is equal to: tx_low_power_next_expiration*tick_frequency. In most applications, the tick_frequency is 10ms, but this is - completely application specific in ThreadX, typically set up + completely application specific in ThreadX, typically set up in tx_low_level_initialize. 2: There are no ThreadX timers active. tx_timer_get_next returns TX_FALSE. - If you don't care about maintaining the ThreadX system clock, you can simply - sleep forever (until an interrupt wakes you up). - If you do want to maintain the ThreadX system clock, + If you don't care about maintaining the ThreadX system clock, you can simply + sleep forever (until an interrupt wakes you up). + If you do want to maintain the ThreadX system clock, program the hardware timer so you can keep track of elapsed time. */ #ifdef TX_LOW_POWER_USER_TIMER_SETUP TX_LOW_POWER_USER_TIMER_SETUP(any_expired, tx_low_power_next_expiration); #endif - - /* Set the flag indicating that low power has been entered. This + + /* Set the flag indicating that low power has been entered. This flag is checked in tx_low_power_exit to determine if the logic used to adjust the ThreadX time is required. */ tx_low_power_entered = TX_TRUE; - + /* Re-enable interrupts before low power mode is entered. */ TX_RESTORE - + /* User code to enter low power mode. */ #ifdef TX_LOW_POWER_USER_ENTER TX_LOW_POWER_USER_ENTER; #endif - /* If the low power code returns, this routine returns to the + /* If the low power code returns, this routine returns to the tx_thread_schedule loop. */ } @@ -198,23 +193,23 @@ ULONG tx_low_power_adjust_ticks; /* Clear the low power entered flag. */ tx_low_power_entered = TX_FALSE; - - /* User code to exit low power mode and reprogram the + + /* User code to exit low power mode and reprogram the timer to the desired interrupt frequency. */ #ifdef TX_LOW_POWER_USER_EXIT TX_LOW_POWER_USER_EXIT; #endif - - /* User code to determine how many timer ticks (interrupts) that - the ThreadX time should be incremented to properly adjust - for the time in low power mode. The result is assumed to be + + /* User code to determine how many timer ticks (interrupts) that + the ThreadX time should be incremented to properly adjust + for the time in low power mode. The result is assumed to be placed in tx_low_power_adjust_ticks. */ #ifdef TX_LOW_POWER_USER_TIMER_ADJUST tx_low_power_adjust_ticks = TX_LOW_POWER_USER_TIMER_ADJUST; #else tx_low_power_adjust_ticks = (ULONG)0; #endif - + /* Determine if the ThreadX timer needs incrementing. */ if (tx_low_power_adjust_ticks) { @@ -330,7 +325,7 @@ ULONG expiration_time = (ULONG) 0xFFFFFFFF; } while (next_timer != *timer_list_head); } - + /* This timer entry is NULL, so just move to the next one. */ timer_list_head++; @@ -438,14 +433,14 @@ TX_TIMER_INTERNAL *temp_list_head; else _tx_timer_time_slice = 1; } - + /* Calculate the proper place to position the timer. */ timer_list_head = _tx_timer_current_ptr; /* Setup the temporary list pointer. */ temp_list_head = TX_NULL; - /* Loop to pull all timers off the timer structure and put on the + /* Loop to pull all timers off the timer structure and put on the the temporary list head. */ for (i = 0; i < TX_TIMER_ENTRIES; i++) { @@ -468,7 +463,7 @@ TX_TIMER_INTERNAL *temp_list_head; { /* Calculate the actual expiration time. */ - next_timer -> tx_timer_internal_remaining_ticks = + next_timer -> tx_timer_internal_remaining_ticks = next_timer -> tx_timer_internal_remaining_ticks - (TX_TIMER_ENTRIES - i) + 1; } else @@ -491,7 +486,7 @@ TX_TIMER_INTERNAL *temp_list_head; if (temp_list_head == TX_NULL) { - /* First item on the list. Move the entire + /* First item on the list. Move the entire linked list. */ temp_list_head = *timer_list_head; } @@ -509,7 +504,7 @@ TX_TIMER_INTERNAL *temp_list_head; /* Now clear the current timer head pointer. */ *timer_list_head = TX_NULL; } - + /* Move to next timer entry. */ timer_list_head++; @@ -535,7 +530,7 @@ TX_TIMER_INTERNAL *temp_list_head; /* Move the temp list head pointer to the next pointer. */ temp_list_head = next_timer -> tx_timer_internal_active_next; - /* Determine if the remaining time is greater than the time increment + /* Determine if the remaining time is greater than the time increment value - this is the normal case. */ if (next_timer -> tx_timer_internal_remaining_ticks > time_increment) { diff --git a/ports_arch/ARMv7-M/threadx/iar/tx_low_power.h b/ports_arch/ARMv7-M/threadx/iar/tx_low_power.h index 8fa7fccb..7b1713d7 100644 --- a/ports_arch/ARMv7-M/threadx/iar/tx_low_power.h +++ b/ports_arch/ARMv7-M/threadx/iar/tx_low_power.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Timer Management */ @@ -20,26 +21,20 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* COMPONENT DEFINITION RELEASE */ -/* */ -/* tx_low_power.h PORTABLE C */ +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_low_power.h PORTABLE C */ /* 6.0 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file defines prototypes for the low-power timer additions */ -/* required for sleep mode. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* This file defines prototypes for the low-power timer additions */ +/* required for sleep mode. */ /* */ /**************************************************************************/ diff --git a/ports_arch/ARMv7-M/threadx/inc/tx_port.h b/ports_arch/ARMv7-M/threadx/inc/tx_port.h index 4d1e34f8..35884cf1 100644 --- a/ports_arch/ARMv7-M/threadx/inc/tx_port.h +++ b/ports_arch/ARMv7-M/threadx/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,23 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comments, updated */ -/* typedef to fix misra */ -/* violation, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -371,7 +355,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -530,7 +514,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #endif @@ -715,7 +699,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-Mx Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-Mx Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_arch/ARMv7-M/threadx_modules/ac5/module_lib/src/txm_module_initialize.s b/ports_arch/ARMv7-M/threadx_modules/ac5/module_lib/src/txm_module_initialize.s index 44d8649e..cfaf64d3 100644 --- a/ports_arch/ARMv7-M/threadx_modules/ac5/module_lib/src/txm_module_initialize.s +++ b/ports_arch/ARMv7-M/threadx_modules/ac5/module_lib/src/txm_module_initialize.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _txm_module_thread_shell_entry Start module thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_initialize(VOID) diff --git a/ports_arch/ARMv7-M/threadx_modules/ac5/module_lib/src/txm_module_thread_shell_entry.c b/ports_arch/ARMv7-M/threadx_modules/ac5/module_lib/src/txm_module_thread_shell_entry.c index 324e14c1..0e46caea 100644 --- a/ports_arch/ARMv7-M/threadx_modules/ac5/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_arch/ARMv7-M/threadx_modules/ac5/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -87,12 +88,6 @@ __align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE]; /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -108,14 +103,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _txm_module_initialize(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -123,7 +118,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_arch/ARMv7-M/threadx_modules/ac5/module_manager/src/tx_thread_schedule.s b/ports_arch/ARMv7-M/threadx_modules/ac5/module_manager/src/tx_thread_schedule.s index 4ffe19d6..c8f6e81d 100644 --- a/ports_arch/ARMv7-M/threadx_modules/ac5/module_manager/src/tx_thread_schedule.s +++ b/ports_arch/ARMv7-M/threadx_modules/ac5/module_manager/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,23 +67,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, optional */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* fixed label syntax, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx_modules/ac5/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_arch/ARMv7-M/threadx_modules/ac5/module_manager/src/txm_module_manager_thread_stack_build.s index 6faefb0d..34a5ff29 100644 --- a/ports_arch/ARMv7-M/threadx_modules/ac5/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_arch/ARMv7-M/threadx_modules/ac5/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_arch/ARMv7-M/threadx_modules/ac5/module_manager/src/txm_module_manager_user_mode_entry.s b/ports_arch/ARMv7-M/threadx_modules/ac5/module_manager/src/txm_module_manager_user_mode_entry.s index 6716970f..8b99dcb1 100644 --- a/ports_arch/ARMv7-M/threadx_modules/ac5/module_manager/src/txm_module_manager_user_mode_entry.s +++ b/ports_arch/ARMv7-M/threadx_modules/ac5/module_manager/src/txm_module_manager_user_mode_entry.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,13 +55,6 @@ /* CALLED BY */ /* */ /* Modules in user mode */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_user_mode_entry(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx_modules/ac6/module_lib/src/txm_module_initialize.S b/ports_arch/ARMv7-M/threadx_modules/ac6/module_lib/src/txm_module_initialize.S index 607f3d2d..d50a73ef 100644 --- a/ports_arch/ARMv7-M/threadx_modules/ac6/module_lib/src/txm_module_initialize.S +++ b/ports_arch/ARMv7-M/threadx_modules/ac6/module_lib/src/txm_module_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* _txm_module_thread_shell_entry Start module thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user configurable, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _txm_module_initialize(VOID) .global _txm_module_initialize diff --git a/ports_arch/ARMv7-M/threadx_modules/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_arch/ARMv7-M/threadx_modules/ac6/module_lib/src/txm_module_thread_shell_entry.c index bbf04817..cd286c2d 100644 --- a/ports_arch/ARMv7-M/threadx_modules/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_arch/ARMv7-M/threadx_modules/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -88,15 +89,6 @@ extern VOID _txm_module_initialize(VOID *heap_base, VOID *heap_top); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user configurable, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -112,14 +104,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _txm_module_initialize(&txm_heap[0], &txm_heap[TXM_MODULE_HEAP_SIZE-1]); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -127,7 +119,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_arch/ARMv7-M/threadx_modules/ac6/module_manager/src/tx_thread_schedule.S b/ports_arch/ARMv7-M/threadx_modules/ac6/module_manager/src/tx_thread_schedule.S index bbf3d62b..1330dde3 100644 --- a/ports_arch/ARMv7-M/threadx_modules/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_arch/ARMv7-M/threadx_modules/ac6/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -69,21 +70,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, optional */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx_modules/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_arch/ARMv7-M/threadx_modules/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index 924bce75..143c2451 100644 --- a/ports_arch/ARMv7-M/threadx_modules/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_arch/ARMv7-M/threadx_modules/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_arch/ARMv7-M/threadx_modules/common/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_arch/ARMv7-M/threadx_modules/common/module_manager/src/txm_module_manager_alignment_adjust.c index e42ce9a4..4b10c367 100644 --- a/ports_arch/ARMv7-M/threadx_modules/common/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_arch/ARMv7-M/threadx_modules/common/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 32. */ if(size <= 32) return 32; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_arch/ARMv7-M/threadx_modules/common/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_arch/ARMv7-M/threadx_modules/common/module_manager/src/txm_module_manager_external_memory_enable.c index 4d408491..fbd3bc43 100644 --- a/ports_arch/ARMv7-M/threadx_modules/common/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_arch/ARMv7-M/threadx_modules/common/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Update defines, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -114,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -124,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -224,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -234,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -246,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_arch/ARMv7-M/threadx_modules/common/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_arch/ARMv7-M/threadx_modules/common/module_manager/src/txm_module_manager_memory_fault_handler.c index 093ec2fc..44c10e6f 100644 --- a/ports_arch/ARMv7-M/threadx_modules/common/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_arch/ARMv7-M/threadx_modules/common/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_arch/ARMv7-M/threadx_modules/common/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_arch/ARMv7-M/threadx_modules/common/module_manager/src/txm_module_manager_memory_fault_notify.c index 982abb8d..f55cc1b1 100644 --- a/ports_arch/ARMv7-M/threadx_modules/common/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_arch/ARMv7-M/threadx_modules/common/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_arch/ARMv7-M/threadx_modules/common/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_arch/ARMv7-M/threadx_modules/common/module_manager/src/txm_module_manager_mm_register_setup.c index 4df21ed1..06418a55 100644 --- a/ports_arch/ARMv7-M/threadx_modules/common/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_arch/ARMv7-M/threadx_modules/common/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -94,16 +95,6 @@ const ULONG txm_module_default_mpu_registers[32] = /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Changed from lookup table to */ -/* calculation and check for */ -/* minumum block size, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { diff --git a/ports_arch/ARMv7-M/threadx_modules/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_arch/ARMv7-M/threadx_modules/gnu/module_lib/src/txm_module_thread_shell_entry.c index e8164503..01f2f909 100644 --- a/ports_arch/ARMv7-M/threadx_modules/gnu/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_arch/ARMv7-M/threadx_modules/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _gcc_setup(thread_info -> txm_module_thread_entry_info_code_base_address); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_arch/ARMv7-M/threadx_modules/gnu/module_manager/src/tx_thread_schedule.S b/ports_arch/ARMv7-M/threadx_modules/gnu/module_manager/src/tx_thread_schedule.S index cfb276c0..dffca713 100644 --- a/ports_arch/ARMv7-M/threadx_modules/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_arch/ARMv7-M/threadx_modules/gnu/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,23 +68,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Fixed predefined macro name, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, optional */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx_modules/gnu/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_arch/ARMv7-M/threadx_modules/gnu/module_manager/src/txm_module_manager_thread_stack_build.s index a9c22b00..5642d252 100644 --- a/ports_arch/ARMv7-M/threadx_modules/gnu/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_arch/ARMv7-M/threadx_modules/gnu/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,13 +55,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_arch/ARMv7-M/threadx_modules/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_arch/ARMv7-M/threadx_modules/iar/module_lib/src/txm_module_thread_shell_entry.c index 4a0fba83..0f892ce5 100644 --- a/ports_arch/ARMv7-M/threadx_modules/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_arch/ARMv7-M/threadx_modules/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID __iar_data_init3(VOID); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ __iar_data_init3(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_arch/ARMv7-M/threadx_modules/iar/module_manager/src/tx_iar.c b/ports_arch/ARMv7-M/threadx_modules/iar/module_manager/src/tx_iar.c index ee47f10f..238b485e 100644 --- a/ports_arch/ARMv7-M/threadx_modules/iar/module_manager/src/tx_iar.c +++ b/ports_arch/ARMv7-M/threadx_modules/iar/module_manager/src/tx_iar.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports_arch/ARMv7-M/threadx_modules/iar/module_manager/src/tx_misra.s b/ports_arch/ARMv7-M/threadx_modules/iar/module_manager/src/tx_misra.s index 72aac789..c79133f5 100644 --- a/ports_arch/ARMv7-M/threadx_modules/iar/module_manager/src/tx_misra.s +++ b/ports_arch/ARMv7-M/threadx_modules/iar/module_manager/src/tx_misra.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -116,7 +117,7 @@ SECTION `.data`:DATA:REORDER:NOROOT(2) DATA -// 51 CHAR _tx_version_id[100] = "Copyright (c) 2024 Microsoft Corporation. * ThreadX 6.1 MISRA C Compliant *"; +// 51 CHAR _tx_version_id[100] = "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX 6.1 MISRA C Compliant *"; _tx_version_id: DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H @@ -703,7 +704,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -718,7 +719,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARMVFP__ /***********************************************************************************************/ @@ -735,8 +736,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -750,10 +751,10 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - - + + SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2) SECTION_TYPE SHT_PROGBITS, 0 DATA diff --git a/ports_arch/ARMv7-M/threadx_modules/iar/module_manager/src/tx_thread_schedule.s b/ports_arch/ARMv7-M/threadx_modules/iar/module_manager/src/tx_thread_schedule.s index b2287ccc..7b30b360 100644 --- a/ports_arch/ARMv7-M/threadx_modules/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_arch/ARMv7-M/threadx_modules/iar/module_manager/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,22 +64,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, optional */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_arch/ARMv7-M/threadx_modules/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_arch/ARMv7-M/threadx_modules/iar/module_manager/src/txm_module_manager_thread_stack_build.s index 315eb7e8..c0061871 100644 --- a/ports_arch/ARMv7-M/threadx_modules/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_arch/ARMv7-M/threadx_modules/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_arch/ARMv7-M/threadx_modules/inc/tx_port.h b/ports_arch/ARMv7-M/threadx_modules/inc/tx_port.h index f7c9c293..b9387932 100644 --- a/ports_arch/ARMv7-M/threadx_modules/inc/tx_port.h +++ b/ports_arch/ARMv7-M/threadx_modules/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,15 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -243,7 +235,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -376,7 +368,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -535,7 +527,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #else #error "Compiler not supported." #endif @@ -719,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-Mx Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-Mx Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_arch/ARMv7-M/threadx_modules/inc/txm_module_port.h b/ports_arch/ARMv7-M/threadx_modules/inc/txm_module_port.h index f95e9f16..b1034eab 100644 --- a/ports_arch/ARMv7-M/threadx_modules/inc/txm_module_port.h +++ b/ports_arch/ARMv7-M/threadx_modules/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,24 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* 07-29-2022 Scott Larson Enabled user-defined and */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Configure heap size, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Set default values for RBAR, */ -/* unify this file for all */ -/* compilers, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -463,6 +446,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-Mx Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-Mx Version 6.5.0.202601 *"; #endif diff --git a/ports_arch/ARMv8-A/threadx/common/inc/tx_port.h b/ports_arch/ARMv8-A/threadx/common/inc/tx_port.h index a8d3fd48..e5352338 100644 --- a/ports_arch/ARMv8-A/threadx/common/inc/tx_port.h +++ b/ports_arch/ARMv8-A/threadx/common/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -369,7 +361,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_arch/ARMv8-A/threadx/common/src/tx_thread_context_restore.S b/ports_arch/ARMv8-A/threadx/common/src/tx_thread_context_restore.S index 8e0d5515..9ba82827 100644 --- a/ports_arch/ARMv8-A/threadx/common/src/tx_thread_context_restore.S +++ b/ports_arch/ARMv8-A/threadx/common/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_arch/ARMv8-A/threadx/common/src/tx_thread_context_save.S b/ports_arch/ARMv8-A/threadx/common/src/tx_thread_context_save.S index 7768efc2..c2395155 100644 --- a/ports_arch/ARMv8-A/threadx/common/src/tx_thread_context_save.S +++ b/ports_arch/ARMv8-A/threadx/common/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_arch/ARMv8-A/threadx/common/src/tx_thread_fp_disable.c b/ports_arch/ARMv8-A/threadx/common/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_arch/ARMv8-A/threadx/common/src/tx_thread_fp_disable.c +++ b/ports_arch/ARMv8-A/threadx/common/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_arch/ARMv8-A/threadx/common/src/tx_thread_fp_enable.c b/ports_arch/ARMv8-A/threadx/common/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_arch/ARMv8-A/threadx/common/src/tx_thread_fp_enable.c +++ b/ports_arch/ARMv8-A/threadx/common/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_arch/ARMv8-A/threadx/common/src/tx_thread_interrupt_control.S b/ports_arch/ARMv8-A/threadx/common/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports_arch/ARMv8-A/threadx/common/src/tx_thread_interrupt_control.S +++ b/ports_arch/ARMv8-A/threadx/common/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_arch/ARMv8-A/threadx/common/src/tx_thread_interrupt_disable.S b/ports_arch/ARMv8-A/threadx/common/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports_arch/ARMv8-A/threadx/common/src/tx_thread_interrupt_disable.S +++ b/ports_arch/ARMv8-A/threadx/common/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_arch/ARMv8-A/threadx/common/src/tx_thread_interrupt_restore.S b/ports_arch/ARMv8-A/threadx/common/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports_arch/ARMv8-A/threadx/common/src/tx_thread_interrupt_restore.S +++ b/ports_arch/ARMv8-A/threadx/common/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_arch/ARMv8-A/threadx/common/src/tx_thread_schedule.S b/ports_arch/ARMv8-A/threadx/common/src/tx_thread_schedule.S index 009a0d5b..d15e7ded 100644 --- a/ports_arch/ARMv8-A/threadx/common/src/tx_thread_schedule.S +++ b/ports_arch/ARMv8-A/threadx/common/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,18 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_arch/ARMv8-A/threadx/common/src/tx_thread_stack_build.S b/ports_arch/ARMv8-A/threadx/common/src/tx_thread_stack_build.S index 6c675d9b..01084da7 100644 --- a/ports_arch/ARMv8-A/threadx/common/src/tx_thread_stack_build.S +++ b/ports_arch/ARMv8-A/threadx/common/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_arch/ARMv8-A/threadx/common/src/tx_thread_system_return.S b/ports_arch/ARMv8-A/threadx/common/src/tx_thread_system_return.S index 780bb128..b7593d79 100644 --- a/ports_arch/ARMv8-A/threadx/common/src/tx_thread_system_return.S +++ b/ports_arch/ARMv8-A/threadx/common/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_arch/ARMv8-A/threadx/common/src/tx_timer_interrupt.S b/ports_arch/ARMv8-A/threadx/common/src/tx_timer_interrupt.S index d84245c6..1b80a7f2 100644 --- a/ports_arch/ARMv8-A/threadx/common/src/tx_timer_interrupt.S +++ b/ports_arch/ARMv8-A/threadx/common/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/sample_threadx/.cproject b/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/sample_threadx/.cproject index 42240200..7e53b3fd 100644 --- a/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/sample_threadx/.cproject +++ b/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/sample_threadx/.cproject @@ -1,158 +1,158 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/sample_threadx/sample_threadx.scat index e5783c7c..d8dfde69 100644 --- a/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/sample_threadx/sample_threadx.scat @@ -2,7 +2,7 @@ ; Scatter file for Armv8-A Startup code on FVP Base model ; Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************** @@ -25,7 +25,7 @@ LOAD 0x80000000 ; in source code for this to work correctly ; ARM_LIB_HEAP +0 ALIGN 64 EMPTY 0xA0000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary diff --git a/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/sample_threadx/v8_aarch64.h b/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/sample_threadx/v8_mmu.h b/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/tx/.cproject b/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/tx/.cproject index 3be714ea..e0d1dda5 100644 --- a/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/tx/.cproject +++ b/ports_arch/ARMv8-A/threadx/ports/ac6/example_build/tx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_arch/ARMv8-A/threadx/ports/ac6/src/tx_initialize_low_level.S b/ports_arch/ARMv8-A/threadx/ports/ac6/src/tx_initialize_low_level.S index f456574e..7d2a4be3 100644 --- a/ports_arch/ARMv8-A/threadx/ports/ac6/src/tx_initialize_low_level.S +++ b/ports_arch/ARMv8-A/threadx/ports/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/.cproject b/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/.cproject index 1c32cb32..40d4912d 100644 --- a/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/.cproject +++ b/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/.cproject @@ -1,170 +1,170 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/sample_threadx.ld b/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/sample_threadx.ld index eec8f12b..3bf47736 100644 --- a/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start diff --git a/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/startup.S b/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/startup.S index b71b45f8..b44806fe 100644 --- a/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/startup.S +++ b/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/startup.S @@ -328,7 +328,7 @@ el1_entry_aarch64: // // Cortex-A processors automatically invalidate their caches on reset // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). - // It is therefore not necessary for software to invalidate the caches + // It is therefore not necessary for software to invalidate the caches // on startup, however, this is done here in case of a warm reset. bl InvalidateUDCaches tlbi VMALLE1 diff --git a/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/v8_aarch64.h b/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/v8_mmu.h b/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/tx/.cproject b/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/tx/.cproject index f1b8ed5b..9e5a975e 100644 --- a/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/tx/.cproject +++ b/ports_arch/ARMv8-A/threadx/ports/gnu/example_build/tx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_arch/ARMv8-A/threadx/ports/gnu/src/tx_initialize_low_level.S b/ports_arch/ARMv8-A/threadx/ports/gnu/src/tx_initialize_low_level.S index 3dce3cea..3025f12b 100644 --- a/ports_arch/ARMv8-A/threadx/ports/gnu/src/tx_initialize_low_level.S +++ b/ports_arch/ARMv8-A/threadx/ports/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -99,4 +89,4 @@ _tx_initialize_low_level: /* Done, return to caller. */ RET // Return to caller -// } +// } diff --git a/ports_arch/ARMv8-A/threadx_modules/common/src/txm_module_manager_port_dispatch.c b/ports_arch/ARMv8-A/threadx_modules/common/src/txm_module_manager_port_dispatch.c index 7dd37868..a0067ee1 100644 --- a/ports_arch/ARMv8-A/threadx_modules/common/src/txm_module_manager_port_dispatch.c +++ b/ports_arch/ARMv8-A/threadx_modules/common/src/txm_module_manager_port_dispatch.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,12 +60,6 @@ /* */ /* _txm_module_manager_kernel_dispatch */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Andres Mlinar Initial Version 6.1.10 */ -/* */ /**************************************************************************/ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) { diff --git a/ports_arch/ARMv8-A/threadx_modules/common/src/txm_module_manager_thread_stack_build.S b/ports_arch/ARMv8-A/threadx_modules/common/src/txm_module_manager_thread_stack_build.S index 8fb96e08..c005f949 100644 --- a/ports_arch/ARMv8-A/threadx_modules/common/src/txm_module_manager_thread_stack_build.S +++ b/ports_arch/ARMv8-A/threadx_modules/common/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Andres Mlinar Initial Version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_arch/ARMv8-A/threadx_smp/common/inc/tx_port.h b/ports_arch/ARMv8-A/threadx_smp/common/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_arch/ARMv8-A/threadx_smp/common/inc/tx_port.h +++ b/ports_arch/ARMv8-A/threadx_smp/common/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_context_restore.S b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_context_restore.S index c16c6dbb..5cd7a9df 100644 --- a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_context_restore.S +++ b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,22 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_context_save.S b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_context_save.S index c8281503..76641067 100644 --- a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_context_save.S +++ b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_schedule.S b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_schedule.S index 52654783..de6b70dd 100644 --- a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_schedule.S +++ b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* added memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_core_get.S b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_core_get.S index 684e317c..ea14c901 100644 --- a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_core_get.S +++ b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_core_preempt.S b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_core_preempt.S index 903a5ab9..1d28907f 100644 --- a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_core_preempt.S +++ b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,18 +62,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_current_state_get.S b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_current_state_get.S index 67b5b6f5..707b41d2 100644 --- a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_current_state_get.S +++ b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_current_thread_get.S b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_current_thread_get.S index 42d5776c..6c4bc9af 100644 --- a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_current_thread_get.S +++ b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_initialize_wait.S b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_initialize_wait.S index f1c067cf..defd791c 100644 --- a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_initialize_wait.S +++ b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_low_level_initialize.S b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_low_level_initialize.S index 101a91f3..99b20d24 100644 --- a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_low_level_initialize.S +++ b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_protect.S b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_protect.S index d2750b7e..1155a3fa 100644 --- a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_protect.S +++ b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,22 +61,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -124,9 +109,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_protection_wait_list_macros.h b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_time_get.S b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_time_get.S index ee4dd40c..335824fb 100644 --- a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_time_get.S +++ b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_unprotect.S b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_unprotect.S index ae700d1e..680e8bc8 100644 --- a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_unprotect.S +++ b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,21 +58,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_stack_build.S b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_stack_build.S index 746bbd42..581e259e 100644 --- a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_stack_build.S +++ b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_system_return.S b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_system_return.S index b889de21..23c75241 100644 --- a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_system_return.S +++ b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_timer_interrupt.S b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_timer_interrupt.S index bad59269..5c6a6bc2 100644 --- a/ports_arch/ARMv8-A/threadx_smp/common/src/tx_timer_interrupt.S +++ b/ports_arch/ARMv8-A/threadx_smp/common/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/.cproject b/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/.cproject index f9c90b21..4a9d74c4 100644 --- a/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/.cproject +++ b/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/sample_threadx.scat index 1288a328..1ed382ae 100644 --- a/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/sample_threadx.scat @@ -12,13 +12,13 @@ LOAD 0x80000000 { startup.o (StartUp, +FIRST) * (+RO, +RW, +ZI) - + } ;XTABLES +0 ALIGN 0x1000 ;{ - ; xtables.o (*) + ; xtables.o (*) ;} - + SYS_STACK +0 ALIGN 8 EMPTY 0x1000 { } @@ -34,13 +34,13 @@ LOAD 0x80000000 ; All stacks and heap are aligned to a cache-line boundary ; ARM_LIB_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary ; HANDLER_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Stacks for EL3 ; @@ -217,34 +217,34 @@ LOAD 0x80000000 ; { ; *( +RO ) ; } -; +; ; XTABLES +0 ALIGN 0x1000 ; { -; xtables.o (*) +; xtables.o (*) ; } ;} ; ;RW AlignExpr(ImageLimit(XTABLES), 0x1000) -;{ +;{ ; RWSEC +0 ; { ; *( +RW ) ; } -; +; ; ZISEC +0 ; { ; *( +ZI ) ; } -; +; ; SYS_STACK +0 ALIGN 8 EMPTY 0x1000 ; { ; } -; +; ; ; 512 MiB heap ; HEAP +0 ALIGN 8 EMPTY 0x10000000 ; { ; } -; +; ; ; Free Memory section ; FREE_MEMORY +0 ALIGN 8 EMPTY 0x10000000 ; { @@ -254,7 +254,7 @@ LOAD 0x80000000 ; TASK_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { ; } -; +; ; ; Per-CPU 128 MiB handler stacks ; HANDLER_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { diff --git a/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/v8_aarch64.h b/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/v8_mmu.h b/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/tx/.cproject b/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/tx/.cproject index 751695e9..56babab8 100644 --- a/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/tx/.cproject +++ b/ports_arch/ARMv8-A/threadx_smp/ports/ac6/example_build/tx/.cproject @@ -1,188 +1,188 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_arch/ARMv8-A/threadx_smp/ports/ac6/src/tx_initialize_low_level.S b/ports_arch/ARMv8-A/threadx_smp/ports/ac6/src/tx_initialize_low_level.S index 7d2cfabf..08986f7b 100644 --- a/ports_arch/ARMv8-A/threadx_smp/ports/ac6/src/tx_initialize_low_level.S +++ b/ports_arch/ARMv8-A/threadx_smp/ports/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/.cproject b/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/.cproject index 34967225..aab1eeaf 100644 --- a/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/.cproject +++ b/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/sample_threadx.ld b/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/sample_threadx.ld index e9b12a82..1c6d45b5 100644 --- a/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start @@ -194,7 +194,7 @@ SECTIONS . = . + 4 * 0x8000; __stack = .; } - + .handler_stack_limit (NOLOAD): { . = ALIGN(64); diff --git a/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/v8_aarch64.h b/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/v8_mmu.h b/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/tx/.cproject b/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/tx/.cproject index 3547a1d3..e3f31405 100644 --- a/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/tx/.cproject +++ b/ports_arch/ARMv8-A/threadx_smp/ports/gnu/example_build/tx/.cproject @@ -1,200 +1,200 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_arch/ARMv8-A/threadx_smp/ports/gnu/src/tx_initialize_low_level.S b/ports_arch/ARMv8-A/threadx_smp/ports/gnu/src/tx_initialize_low_level.S index b171fc0f..efb08b80 100644 --- a/ports_arch/ARMv8-A/threadx_smp/ports/gnu/src/tx_initialize_low_level.S +++ b/ports_arch/ARMv8-A/threadx_smp/ports/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_arch/ARMv8-A/update.ps1 b/ports_arch/ARMv8-A/update.ps1 index 1c7ae53e..0663b603 100644 --- a/ports_arch/ARMv8-A/update.ps1 +++ b/ports_arch/ARMv8-A/update.ps1 @@ -109,7 +109,7 @@ If (-Not (Test-Path -Path $LogDir -PathType Container)) { Function Copy-FilesVerbose { [CmdletBinding()] Param ( - [string] $source, + [string] $source, [string] $destination_directory ) Write-Verbose ("Copying common files...") @@ -131,9 +131,9 @@ ForEach ($PortSet in $PortSets) { $compiler_directory = $core_directory + "\" + $compiler Write-Verbose ("Compiler directory: $compiler_directory") $compiler_directory_object = New-Item -Path $compiler_directory -ItemType "directory" -Force - + $destination_directory = $compiler_directory - + If ($CopyCommonFiles) { Copy-FilesVerbose -source "threadx\common\*" -destination_directory $destination_directory } @@ -141,7 +141,7 @@ ForEach ($PortSet in $PortSets) { If ($CopyPortFiles) { Copy-FilesVerbose -source "threadx\ports\$compiler\*" -destination_directory $destination_directory } - + If ($PortSet -eq 'tx_smp') { If ($CopyCommonFiles) { Copy-FilesVerbose -source "threadx_smp\common\*" -destination_directory $destination_directory diff --git a/ports_arch/ARMv8-M/threadx/ac6/readme_threadx.txt b/ports_arch/ARMv8-M/threadx/ac6/readme_threadx.txt index 5821892f..87556be5 100644 --- a/ports_arch/ARMv8-M/threadx/ac6/readme_threadx.txt +++ b/ports_arch/ARMv8-M/threadx/ac6/readme_threadx.txt @@ -1,46 +1,46 @@ - Microsoft's Azure RTOS ThreadX for Cortex-Mxx + Microsoft's Azure RTOS ThreadX for Cortex-Mxx Using the AC6 Tools in Keil uVision 1. Import the ThreadX Projects -In order to build the ThreadX library and the ThreadX demonstration, first open -the AzureRTOS.uvmpw workspace (located in the "example_build" directory) +In order to build the ThreadX library and the ThreadX demonstration, first open +the AzureRTOS.uvmpw workspace (located in the "example_build" directory) into Keil. 2. Building the ThreadX run-time Library Building the ThreadX library is easy; simply set the ThreadX_Library project -as active, then then build the library. You should now observe the compilation +as active, then then build the library. You should now observe the compilation and assembly of the ThreadX library. This project build produces the ThreadX library file ThreadX_Library.lib. -Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c -replace the common files of the same name. +Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c +replace the common files of the same name. 3. Demonstration System The ThreadX demonstration is designed to execute under the Keil debugger on the FVP_MPS2_Cortex-Mxx_MDK simulator. -Building the demonstration is easy; simply select the "Batch Build" button. -You should now observe the compilation and assembly of the ThreadX demonstration of -both the demo_secure_zone and demo_threadx_non-secure_zone projects. +Building the demonstration is easy; simply select the "Batch Build" button. +You should now observe the compilation and assembly of the ThreadX demonstration of +both the demo_secure_zone and demo_threadx_non-secure_zone projects. Then click the Start/Stop Debug Session button to start the simulator and begin debugging. You are now ready to execute the ThreadX demonstration. 4. System Initialization -The entry point in ThreadX for the Cortex-Mxx using AC6 tools uses the standard AC6 +The entry point in ThreadX for the Cortex-Mxx using AC6 tools uses the standard AC6 Cortex-Mxx reset sequence. From the reset vector the C runtime will be initialized. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. @@ -49,7 +49,7 @@ parameter to your application definition function, tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-Mxx version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -132,26 +132,26 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 6. Improving Performance -To make ThreadX and the application(s) run faster, you can enable -all compiler optimizations. +To make ThreadX and the application(s) run faster, you can enable +all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-Mxx -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-Mxx vectors start at the label __Vectors or similar. The application may modify -the vector area according to its needs. There is code in tx_initialize_low_level() that will -configure the vector base register. +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. 7.2 Managed Interrupts @@ -177,7 +177,7 @@ your_assembly_isr: ; VOID your_assembly_isr(VOID) ; { PUSH {r0, lr} -; +; ; /* Do interrupt handler work here */ ; /* BL */ @@ -187,15 +187,15 @@ your_assembly_isr: Note: the Cortex-Mxx requires exception handlers to be thumb labels, this implies bit 0 set. To accomplish this, the declaration of the label has to be preceded by the assembler directive -.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to -be inserted in the correct location in the interrupt vector table. This table is typically +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically located in either your runtime startup file or in the tx_initialize_low_level.s file. 8. FPU Support -ThreadX for Cortex-Mxx supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-Mxx supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context. diff --git a/ports_arch/ARMv8-M/threadx/ac6/src/tx_initialize_low_level.S b/ports_arch/ARMv8-M/threadx/ac6/src/tx_initialize_low_level.S index 259ef110..9332b7e1 100644 --- a/ports_arch/ARMv8-M/threadx/ac6/src/tx_initialize_low_level.S +++ b/ports_arch/ARMv8-M/threadx/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ HEAP_SIZE = 0x00000000 /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_arch/ARMv8-M/threadx/ac6/src/tx_misra.S b/ports_arch/ARMv8-M/threadx/ac6/src/tx_misra.S index 8ac0c629..10548671 100644 --- a/ports_arch/ARMv8-M/threadx/ac6/src/tx_misra.S +++ b/ports_arch/ARMv8-M/threadx/ac6/src/tx_misra.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -667,7 +668,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -682,7 +683,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARM_FP /***********************************************************************************************/ @@ -699,8 +700,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -714,9 +715,9 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - + .data .word 0 diff --git a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_context_restore.S b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_context_restore.S index 3870a39f..4ed9898d 100644 --- a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_context_restore.S +++ b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_context_save.S b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_context_save.S index fd90eedf..934e7d81 100644 --- a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_context_save.S +++ b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_interrupt_control.S b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_interrupt_control.S index 18e8832a..f8d62ad4 100644 --- a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_interrupt_control.S +++ b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_interrupt_disable.S b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_interrupt_disable.S index 7ba4f731..b04500b5 100644 --- a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_interrupt_disable.S +++ b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_interrupt_restore.S b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_interrupt_restore.S index 74bb88d9..699a8921 100644 --- a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_interrupt_restore.S +++ b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_schedule.S b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_schedule.S index 1debdbb1..40d3282b 100644 --- a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_schedule.S +++ b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,23 +61,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 04-02-2021 Scott Larson Modified comment(s), added */ -/* low power code, */ -/* resulting in version 6.1.6 */ -/* 06-02-2021 Scott Larson Added secure stack initialize */ -/* in SVC handler, */ -/* resulting in version 6.1.7 */ -/* 04-25-2022 Scott Larson Added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 03-08-2023 Scott Larson Added preproc FPU option, */ -/* included tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -354,7 +338,7 @@ SVC_Handler: CMP r1, #2 // Is it a secure stack free request? BEQ _tx_svc_secure_free // Yes, go there - + CMP r1, #3 // Is it a secure stack init request? BEQ _tx_svc_secure_init // Yes, go there diff --git a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_secure_stack.c b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_secure_stack.c index 1ace10bb..73602ca3 100644 --- a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_secure_stack.c +++ b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_secure_stack.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -102,21 +103,6 @@ static INT tx_head_free_index = 0U; /* */ /* _tx_initialize_kernel_enter */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-16-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.1 */ -/* 06-02-2021 Scott Larson Modified comment(s), and */ -/* changed name, execute in */ -/* handler mode, */ -/* resulting in version 6.1.7 */ -/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ -/* secure stack allocation, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_initialize(void) diff --git a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_secure_stack_allocate.S b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_secure_stack_allocate.S index 5fca5fa0..a66c7652 100644 --- a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_secure_stack_allocate.S +++ b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_secure_stack_allocate.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,14 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) // { diff --git a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_secure_stack_free.S b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_secure_stack_free.S index f4d3bfac..99b2fb82 100644 --- a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_secure_stack_free.S +++ b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_secure_stack_free.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) // { diff --git a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_secure_stack_initialize.S b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_secure_stack_initialize.S index d91fa202..60993336 100644 --- a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_secure_stack_initialize.S +++ b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_secure_stack_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,18 +54,6 @@ /* */ /* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) // { diff --git a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_stack_build.S b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_stack_build.S index 4bcad1a4..039c0e56 100644 --- a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_stack_build.S +++ b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_system_return.S b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_system_return.S index a1b998ac..e31c4a55 100644 --- a/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_system_return.S +++ b/ports_arch/ARMv8-M/threadx/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_arch/ARMv8-M/threadx/ac6/src/tx_timer_interrupt.S b/ports_arch/ARMv8-M/threadx/ac6/src/tx_timer_interrupt.S index 655372b2..846ba2c1 100644 --- a/ports_arch/ARMv8-M/threadx/ac6/src/tx_timer_interrupt.S +++ b/ports_arch/ARMv8-M/threadx/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_arch/ARMv8-M/threadx/ac6/src/txe_thread_secure_stack_allocate.c b/ports_arch/ARMv8-M/threadx/ac6/src/txe_thread_secure_stack_allocate.c index 36e954dd..85d2bea5 100644 --- a/ports_arch/ARMv8-M/threadx/ac6/src/txe_thread_secure_stack_allocate.c +++ b/ports_arch/ARMv8-M/threadx/ac6/src/txe_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { @@ -76,10 +71,10 @@ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_siz return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_arch/ARMv8-M/threadx/ac6/src/txe_thread_secure_stack_free.c b/ports_arch/ARMv8-M/threadx/ac6/src/txe_thread_secure_stack_free.c index f3a735fa..c465faab 100644 --- a/ports_arch/ARMv8-M/threadx/ac6/src/txe_thread_secure_stack_free.c +++ b/ports_arch/ARMv8-M/threadx/ac6/src/txe_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { @@ -74,10 +69,10 @@ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_arch/ARMv8-M/threadx/gnu/readme_threadx.txt b/ports_arch/ARMv8-M/threadx/gnu/readme_threadx.txt index 4a6f5660..2cce95a4 100644 --- a/ports_arch/ARMv8-M/threadx/gnu/readme_threadx.txt +++ b/ports_arch/ARMv8-M/threadx/gnu/readme_threadx.txt @@ -1,32 +1,32 @@ - Microsoft's Azure RTOS ThreadX for Cortex-Mxx + Microsoft's Azure RTOS ThreadX for Cortex-Mxx Using the GNU Tools 1. Building the ThreadX run-time Library Import all ThreadX common and port-specific source files into a GNU project. -Configure the project to build a library rather than an executable. This -results in the ThreadX run-time library file tx.a, which is needed by +Configure the project to build a library rather than an executable. This +results in the ThreadX run-time library file tx.a, which is needed by the application. -Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c -replace the common files of the same name. +Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c +replace the common files of the same name. 2. Demonstration System -No demonstration project is provided. +No demonstration project is provided. 3. System Initialization -The entry point in ThreadX for the Cortex-Mxx using gnu tools uses the standard GNU +The entry point in ThreadX for the Cortex-Mxx using gnu tools uses the standard GNU Cortex-Mxx reset sequence. From the reset vector the C runtime will be initialized. -The ThreadX tx_initialize_low_level.S file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. +The ThreadX tx_initialize_low_level.S file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. @@ -35,7 +35,7 @@ parameter to your application definition function, tx_application_define. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-Mxx version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -118,26 +118,26 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 5. Improving Performance -To make ThreadX and the application(s) run faster, you can enable -all compiler optimizations. +To make ThreadX and the application(s) run faster, you can enable +all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-Mxx -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 6.1 Vector Area The Cortex-Mxx vectors start at the label __tx_vectors or similar. The application may modify -the vector area according to its needs. There is code in tx_initialize_low_level() that will -configure the vector base register. +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. 6.2 Managed Interrupts @@ -170,15 +170,15 @@ your_assembly_isr: Note: the Cortex-Mxx requires exception handlers to be thumb labels, this implies bit 0 set. To accomplish this, the declaration of the label has to be preceded by the assembler directive -.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to -be inserted in the correct location in the interrupt vector table. This table is typically +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically located in either your runtime startup file or in the tx_initialize_low_level.S file. 7. FPU Support -ThreadX for Cortex-Mxx supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-Mxx supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context. diff --git a/ports_arch/ARMv8-M/threadx/gnu/src/tx_initialize_low_level.S b/ports_arch/ARMv8-M/threadx/gnu/src/tx_initialize_low_level.S index 6b058a93..842dcdf4 100644 --- a/ports_arch/ARMv8-M/threadx/gnu/src/tx_initialize_low_level.S +++ b/ports_arch/ARMv8-M/threadx/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,16 +66,6 @@ HEAP_SIZE = 0x00000000 /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Fixed predefined macro name, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_arch/ARMv8-M/threadx/gnu/src/tx_misra.S b/ports_arch/ARMv8-M/threadx/gnu/src/tx_misra.S index 8ac0c629..10548671 100644 --- a/ports_arch/ARMv8-M/threadx/gnu/src/tx_misra.S +++ b/ports_arch/ARMv8-M/threadx/gnu/src/tx_misra.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -667,7 +668,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -682,7 +683,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARM_FP /***********************************************************************************************/ @@ -699,8 +700,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -714,9 +715,9 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - + .data .word 0 diff --git a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_context_restore.S b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_context_restore.S index 58a18971..31b62541 100644 --- a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_context_restore.S +++ b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_context_save.S b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_context_save.S index 0c83ee46..bcf9fff5 100644 --- a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_context_save.S +++ b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_interrupt_control.S b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_interrupt_control.S index cf47656b..28f1deff 100644 --- a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_interrupt_control.S +++ b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_interrupt_disable.S b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_interrupt_disable.S index dab73165..44df6a59 100644 --- a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_interrupt_disable.S +++ b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_interrupt_restore.S b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_interrupt_restore.S index 96c00700..19b18805 100644 --- a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_interrupt_restore.S +++ b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_schedule.S b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_schedule.S index 8f1a981a..0a30ab36 100644 --- a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_schedule.S +++ b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,24 +57,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 04-02-2021 Scott Larson Modified comment(s), added */ -/* low power code, */ -/* resulting in version 6.1.6 */ -/* 06-02-2021 Scott Larson Added secure stack initialize */ -/* in SVC handler, */ -/* resulting in version 6.1.7 */ -/* 01-31-2022 Scott Larson Fixed predefined macro name, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -351,7 +334,7 @@ SVC_Handler: CMP r1, #2 // Is it a secure stack free request? BEQ _tx_svc_secure_free // Yes, go there - + CMP r1, #3 // Is it a secure stack init request? BEQ _tx_svc_secure_init // Yes, go there diff --git a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_secure_stack.c b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_secure_stack.c index 79cd6de8..84b378ad 100644 --- a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_secure_stack.c +++ b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_secure_stack.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -98,21 +99,6 @@ static INT tx_head_free_index = 0U; /* */ /* _tx_initialize_kernel_enter */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-16-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.1 */ -/* 06-02-2021 Scott Larson Change name, execute in */ -/* handler mode, */ -/* disable optimizations, */ -/* resulting in version 6.1.7 */ -/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ -/* secure stack allocation, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry, optimize(0))) UINT _tx_thread_secure_mode_stack_initialize(void) diff --git a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_secure_stack_allocate.S b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_secure_stack_allocate.S index cc09fc3f..f0464840 100644 --- a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_secure_stack_allocate.S +++ b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_secure_stack_allocate.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,14 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) // { diff --git a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_secure_stack_free.S b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_secure_stack_free.S index d52e7e23..b9bee09f 100644 --- a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_secure_stack_free.S +++ b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_secure_stack_free.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) // { diff --git a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_secure_stack_initialize.S b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_secure_stack_initialize.S index 81d93f36..d885b375 100644 --- a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_secure_stack_initialize.S +++ b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_secure_stack_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,18 +54,6 @@ /* */ /* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) // { diff --git a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_stack_build.S b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_stack_build.S index c04fc40e..b8a5a3e7 100644 --- a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_stack_build.S +++ b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_system_return.S b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_system_return.S index c136c1f4..1e84582e 100644 --- a/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_system_return.S +++ b/ports_arch/ARMv8-M/threadx/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_arch/ARMv8-M/threadx/gnu/src/tx_timer_interrupt.S b/ports_arch/ARMv8-M/threadx/gnu/src/tx_timer_interrupt.S index d1680f47..5704e60c 100644 --- a/ports_arch/ARMv8-M/threadx/gnu/src/tx_timer_interrupt.S +++ b/ports_arch/ARMv8-M/threadx/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_arch/ARMv8-M/threadx/gnu/src/txe_thread_secure_stack_allocate.c b/ports_arch/ARMv8-M/threadx/gnu/src/txe_thread_secure_stack_allocate.c index 36e954dd..85d2bea5 100644 --- a/ports_arch/ARMv8-M/threadx/gnu/src/txe_thread_secure_stack_allocate.c +++ b/ports_arch/ARMv8-M/threadx/gnu/src/txe_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { @@ -76,10 +71,10 @@ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_siz return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_arch/ARMv8-M/threadx/gnu/src/txe_thread_secure_stack_free.c b/ports_arch/ARMv8-M/threadx/gnu/src/txe_thread_secure_stack_free.c index f3a735fa..c465faab 100644 --- a/ports_arch/ARMv8-M/threadx/gnu/src/txe_thread_secure_stack_free.c +++ b/ports_arch/ARMv8-M/threadx/gnu/src/txe_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { @@ -74,10 +69,10 @@ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_arch/ARMv8-M/threadx/iar/readme_threadx.txt b/ports_arch/ARMv8-M/threadx/iar/readme_threadx.txt index 122b41ef..e0f46665 100644 --- a/ports_arch/ARMv8-M/threadx/iar/readme_threadx.txt +++ b/ports_arch/ARMv8-M/threadx/iar/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX for Cortex-Mxx + Microsoft's Azure RTOS ThreadX for Cortex-Mxx Using the IAR Tools @@ -6,33 +6,33 @@ 1. Building the ThreadX run-time Library Import all ThreadX common and port-specific source files into an IAR project. -Configure the project to build a library rather than an executable. This -results in the ThreadX run-time library file tx.a, which is needed by +Configure the project to build a library rather than an executable. This +results in the ThreadX run-time library file tx.a, which is needed by the application. -Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c -replace the common files of the same name. +Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c +replace the common files of the same name. 2. Demonstration System No demonstration is provided because the IAR EWARM 8.50 simulator does -not simulate the Cortex-Mxx correctly. +not simulate the Cortex-Mxx correctly. 3. System Initialization -The entry point in ThreadX for the Cortex-Mxx using IAR tools is at label -__iar_program_start. This is defined within the IAR compiler's startup code. -In addition, this is where all static and global preset C variable +The entry point in ThreadX for the Cortex-Mxx using IAR tools is at label +__iar_program_start. This is defined within the IAR compiler's startup code. +In addition, this is where all static and global preset C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, and a periodic timer interrupt source. +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. The _tx_initialize_low_level function inside of tx_initialize_low_level.s -also determines the first available address for use by the application, which -is supplied as the sole input parameter to your application definition function, -tx_application_define. To accomplish this, a section is created in -tx_initialize_low_level.s called FREE_MEM, which must be located after all +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all other RAM sections in memory. @@ -41,7 +41,7 @@ other RAM sections in memory. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have the same stack frame in the Cortex-Mxx version of -ThreadX. The top of the suspended thread's stack is pointed to by +ThreadX. The top of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. Non-FPU Stack Frame: @@ -124,17 +124,17 @@ FPU Stack Frame (only interrupted thread with FPU enabled): 5. Improving Performance -To make ThreadX and the application(s) run faster, you can enable -all compiler optimizations. +To make ThreadX and the application(s) run faster, you can enable +all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling -The Cortex-Mxx vectors start at the label __vector_table and is typically defined in a +The Cortex-Mxx vectors start at the label __vector_table and is typically defined in a startup.s file (or similar). The application may modify the vector area according to its needs. @@ -182,14 +182,14 @@ should have the following line added (if not already in place): initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application -The project options "General Options -> Library Configuration" should also have the +The project options "General Options -> Library Configuration" should also have the "Enable thread support in library" box selected. 8. VFP Support -ThreadX for Cortex-Mxx supports automatic ("lazy") VFP support, which means that applications threads -can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +ThreadX for Cortex-Mxx supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread context. diff --git a/ports_arch/ARMv8-M/threadx/iar/src/tx_iar.c b/ports_arch/ARMv8-M/threadx/iar/src/tx_iar.c index ee47f10f..238b485e 100644 --- a/ports_arch/ARMv8-M/threadx/iar/src/tx_iar.c +++ b/ports_arch/ARMv8-M/threadx/iar/src/tx_iar.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports_arch/ARMv8-M/threadx/iar/src/tx_initialize_low_level.s b/ports_arch/ARMv8-M/threadx/iar/src/tx_initialize_low_level.s index 97418669..6d8e07e8 100644 --- a/ports_arch/ARMv8-M/threadx/iar/src/tx_initialize_low_level.s +++ b/ports_arch/ARMv8-M/threadx/iar/src/tx_initialize_low_level.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,13 +75,6 @@ __tx_free_memory_start /* CALLED BY */ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_arch/ARMv8-M/threadx/iar/src/tx_misra.s b/ports_arch/ARMv8-M/threadx/iar/src/tx_misra.s index f86d9a65..642bb89e 100644 --- a/ports_arch/ARMv8-M/threadx/iar/src/tx_misra.s +++ b/ports_arch/ARMv8-M/threadx/iar/src/tx_misra.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -120,7 +121,7 @@ SECTION `.data`:DATA:REORDER:NOROOT(2) DATA -// 51 CHAR _tx_version_id[100] = "Copyright (c) 2024 Microsoft Corporation. * ThreadX 6.1 MISRA C Compliant *"; +// 51 CHAR _tx_version_id[100] = "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX 6.1 MISRA C Compliant *"; _tx_version_id: DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H @@ -707,7 +708,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -722,7 +723,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARMVFP__ /***********************************************************************************************/ @@ -739,8 +740,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -754,10 +755,10 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - - + + SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2) SECTION_TYPE SHT_PROGBITS, 0 DATA diff --git a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_context_restore.s b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_context_restore.s index 87db9651..c8bf3f79 100644 --- a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_context_restore.s +++ b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,13 +56,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_context_save.s b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_context_save.s index 280162dc..f8713910 100644 --- a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_context_save.s +++ b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,13 +56,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_interrupt_control.s b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_interrupt_control.s index 6f317b88..564a9be8 100644 --- a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_interrupt_control.s +++ b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,13 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_interrupt_disable.s b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_interrupt_disable.s index eaa983cb..0a2d54c8 100644 --- a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_interrupt_disable.s +++ b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,13 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_interrupt_restore.s b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_interrupt_restore.s index c22ee789..4743bd46 100644 --- a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_interrupt_restore.s +++ b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,13 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_schedule.s b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_schedule.s index 5d5bb48d..84f2043f 100644 --- a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_schedule.s +++ b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -73,23 +74,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 04-02-2021 Scott Larson Modified comment(s), added */ -/* low power code, */ -/* resulting in version 6.1.6 */ -/* 06-02-2021 Scott Larson Added secure stack initialize */ -/* in SVC handler, */ -/* resulting in version 6.1.7 */ -/* 04-25-2022 Scott Larson Added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 03-08-2023 Scott Larson Added preproc FPU option, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -348,7 +332,7 @@ SVC_Handler: CMP r1, #2 // Is it a secure stack free request? BEQ _tx_svc_secure_free // Yes, go there - + CMP r1, #3 // Is it a secure stack init request? BEQ _tx_svc_secure_init // Yes, go there diff --git a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_secure_stack.c b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_secure_stack.c index 5d8e0865..123f786f 100644 --- a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_secure_stack.c +++ b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_secure_stack.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -102,20 +103,6 @@ static INT tx_head_free_index = 0U; /* */ /* _tx_initialize_kernel_enter */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-16-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.1 */ -/* 06-02-2021 Scott Larson Change name, execute in */ -/* handler mode, */ -/* resulting in version 6.1.7 */ -/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ -/* secure stack allocation, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_initialize(void) diff --git a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_secure_stack_allocate.s b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_secure_stack_allocate.s index fdbdf547..171b129e 100644 --- a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_secure_stack_allocate.s +++ b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_secure_stack_allocate.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,13 +57,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) // { diff --git a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_secure_stack_free.s b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_secure_stack_free.s index fb60d9e1..cbffd110 100644 --- a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_secure_stack_free.s +++ b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_secure_stack_free.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,13 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) // { diff --git a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_secure_stack_initialize.s b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_secure_stack_initialize.s index e0952405..71ba7472 100644 --- a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_secure_stack_initialize.s +++ b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_secure_stack_initialize.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* CALLED BY */ /* */ /* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) // { diff --git a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_stack_build.s b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_stack_build.s index 9aee56ce..a8fab2ca 100644 --- a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_stack_build.s +++ b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,13 +58,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_system_return.s b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_system_return.s index 50006b3e..f2a187ea 100644 --- a/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_system_return.s +++ b/ports_arch/ARMv8-M/threadx/iar/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,13 +58,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_arch/ARMv8-M/threadx/iar/src/tx_timer_interrupt.s b/ports_arch/ARMv8-M/threadx/iar/src/tx_timer_interrupt.s index 971d74b1..25f7f33f 100644 --- a/ports_arch/ARMv8-M/threadx/iar/src/tx_timer_interrupt.s +++ b/ports_arch/ARMv8-M/threadx/iar/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,13 +72,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_arch/ARMv8-M/threadx/iar/src/txe_thread_secure_stack_allocate.c b/ports_arch/ARMv8-M/threadx/iar/src/txe_thread_secure_stack_allocate.c index 36e954dd..85d2bea5 100644 --- a/ports_arch/ARMv8-M/threadx/iar/src/txe_thread_secure_stack_allocate.c +++ b/ports_arch/ARMv8-M/threadx/iar/src/txe_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { @@ -76,10 +71,10 @@ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_siz return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_arch/ARMv8-M/threadx/iar/src/txe_thread_secure_stack_free.c b/ports_arch/ARMv8-M/threadx/iar/src/txe_thread_secure_stack_free.c index f3a735fa..c465faab 100644 --- a/ports_arch/ARMv8-M/threadx/iar/src/txe_thread_secure_stack_free.c +++ b/ports_arch/ARMv8-M/threadx/iar/src/txe_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { @@ -74,10 +69,10 @@ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_arch/ARMv8-M/threadx/inc/tx_port.h b/ports_arch/ARMv8-M/threadx/inc/tx_port.h index 58afa4e6..f0e7b79c 100644 --- a/ports_arch/ARMv8-M/threadx/inc/tx_port.h +++ b/ports_arch/ARMv8-M/threadx/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,39 +46,6 @@ /* This file replaces the previous Cortex-Mxx files. It unifies */ /* the Cortex-Mxx compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-02-2021 Scott Larson Modified comment(s), added */ -/* ULONG64_DEFINED, */ -/* resulting in version 6.1.5 */ -/* 06-02-2021 Scott Larson Modified comment(s), removed */ -/* unneeded header file, funcs */ -/* set_control and get_control */ -/* changed to inline, */ -/* added symbol to enable */ -/* stack error handler, */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ -/* stack check error handling, */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), unified */ -/* this file across compilers, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* 03-08-2023 Scott Larson Removed unneeded #include, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -645,7 +613,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-Mxx Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-Mxx Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_arch/ARMv8-M/threadx/inc/tx_secure_interface.h b/ports_arch/ARMv8-M/threadx/inc/tx_secure_interface.h index 39b5d5fd..5ac37fbf 100644 --- a/ports_arch/ARMv8-M/threadx/inc/tx_secure_interface.h +++ b/ports_arch/ARMv8-M/threadx/inc/tx_secure_interface.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,12 +38,6 @@ /* It is assumed that tx_api.h and tx_port.h have already been */ /* included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_SECURE_INTERFACE_H diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/.cproject b/ports_module/cortex_a35/ac6/example_build/sample_threadx/.cproject index a49dadd2..8a32c271 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/.cproject +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/.cproject @@ -1,174 +1,174 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3.h index 23bc7fd8..dfe37586 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3.h @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef GICV3_h diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicc.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicc.h index 8e6f0acc..beaa9157 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicc.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicc.h @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef GICV3_gicc_h diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicd.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicd.c index 3bfb4a93..2cf1553b 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicd.c +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicd.c @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #include diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicr.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicr.c index 7b437b18..912ab2e4 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicr.c +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicr.c @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #include "GICv3.h" diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.S index e7f95aa7..e8a87f0b 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -4,7 +4,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/PPM_AEM.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx/PPM_AEM.h index 52c9a0fe..f7501eeb 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/PPM_AEM.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/PPM_AEM.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.c index 8898ff39..736722fb 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -87,42 +87,42 @@ UCHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -130,23 +130,23 @@ UCHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -250,11 +250,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -313,7 +313,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -366,7 +366,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.scat index e5783c7c..d8dfde69 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.scat @@ -2,7 +2,7 @@ ; Scatter file for Armv8-A Startup code on FVP Base model ; Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************** @@ -25,7 +25,7 @@ LOAD 0x80000000 ; in source code for this to work correctly ; ARM_LIB_HEAP +0 ALIGN 64 EMPTY 0xA0000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/sp804_timer.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx/sp804_timer.c index 4dc009b2..c2ce6faa 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/sp804_timer.c +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/sp804_timer.c @@ -3,7 +3,7 @@ // // Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/sp804_timer.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx/sp804_timer.h index 777062cc..4d423904 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/sp804_timer.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/sp804_timer.h @@ -4,7 +4,7 @@ // // Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/startup.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx/startup.S index de100e56..9f0fc211 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/startup.S +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/startup.S @@ -7,7 +7,7 @@ // // Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ @@ -328,7 +328,7 @@ el1_entry_aarch64: // // Cortex-A processors automatically invalidate their caches on reset // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). - // It is therefore not necessary for software to invalidate the caches + // It is therefore not necessary for software to invalidate the caches // on startup, however, this is done here in case of a warm reset. bl InvalidateUDCaches tlbi VMALLE1 diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 857c2101..135cd934 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.S index f8db3bfe..45445a98 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.S +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.S @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_mmu.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_mmu.h index ee8834fa..d0c51601 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_mmu.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_system.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_system.h index ff96deff..a62d2a33 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_system.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_system.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_utils.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_utils.S index f0fcef26..888892a0 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_utils.S +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/v8_utils.S @@ -3,7 +3,7 @@ // // Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx/vectors.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx/vectors.S index 9e60e001..7784f98e 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx/vectors.S +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx/vectors.S @@ -3,7 +3,7 @@ // // Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/.cproject b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/.cproject index e75d0d0e..695952e7 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/.cproject +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/.cproject @@ -1,220 +1,220 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/sample_threadx_module.c index 3a3f8159..3476367e 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / sizeof(ULONG)]; @@ -103,7 +103,7 @@ CHAR *pointer; /* Allocate all the objects. In MMU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ status = txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); while (status != TX_SUCCESS); @@ -133,7 +133,7 @@ CHAR *pointer; while (status != TX_SUCCESS); status = txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); while (status != TX_SUCCESS); - + /* Create a byte memory pool from which to allocate the thread stacks. */ status = tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -148,7 +148,7 @@ CHAR *pointer; /* Create the main thread. */ status = tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -156,11 +156,11 @@ CHAR *pointer; status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); while (status != TX_SUCCESS); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ status = tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); while (status != TX_SUCCESS); @@ -169,7 +169,7 @@ CHAR *pointer; while (status != TX_SUCCESS); status = tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); while (status != TX_SUCCESS); @@ -177,10 +177,10 @@ CHAR *pointer; status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); while (status != TX_SUCCESS); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ status = tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -189,7 +189,7 @@ CHAR *pointer; while (status != TX_SUCCESS); status = tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -200,7 +200,7 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ status = tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -210,7 +210,7 @@ CHAR *pointer; /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ status = tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -219,7 +219,7 @@ CHAR *pointer; while (status != TX_SUCCESS); status = tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -276,7 +276,7 @@ void thread_0_entry(ULONG thread_input) { UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -286,7 +286,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -338,11 +338,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -401,7 +401,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -454,7 +454,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/txm_module_preamble.S index f05656c3..ad75e134 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -1,7 +1,7 @@ .text .align 4 .section Init - + // External references .global _txm_module_thread_shell_entry .global _txm_module_callback_request_thread_entry diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/.cproject index 77c12df2..2f54811f 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/.cproject +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/.cproject @@ -1,238 +1,238 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3.h index 23bc7fd8..dfe37586 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3.h @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef GICV3_h diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicc.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicc.h index 8e6f0acc..beaa9157 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicc.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicc.h @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef GICV3_gicc_h diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicd.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicd.c index 3bfb4a93..2cf1553b 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicd.c +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicd.c @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #include diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicr.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicr.c index 7b437b18..912ab2e4 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicr.c +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/GICv3_gicr.c @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #include "GICv3.h" diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/MP_Mutexes.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/MP_Mutexes.S index e7f95aa7..e8a87f0b 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/MP_Mutexes.S +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/MP_Mutexes.S @@ -4,7 +4,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/MP_Mutexes.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/MP_Mutexes.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/PPM_AEM.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/PPM_AEM.h index 52c9a0fe..f7501eeb 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/PPM_AEM.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/PPM_AEM.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat index deb16ebe..54e58dba 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat @@ -2,7 +2,7 @@ ; Scatter file for Armv8-A Startup code on FVP Base model ; Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************** @@ -25,7 +25,7 @@ LOAD 0x80000000 ; in source code for this to work correctly ; ARM_LIB_HEAP +0 ALIGN 64 EMPTY 0xA0000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index c7296646..c0772002 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -115,7 +115,7 @@ void module_manager_entry(ULONG thread_input) /* Load the module with absolute address linkage, in this example it is placed there by the multiple image download. */ txm_module_manager_absolute_load(&my_module, "my module", (void *) MODULE_CODE); - + /* Start the module. */ txm_module_manager_start(&my_module); @@ -127,10 +127,10 @@ void module_manager_entry(ULONG thread_input) tx_thread_sleep(10); } } - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -139,11 +139,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(10); } } diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sp804_timer.c b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sp804_timer.c index 4dc009b2..c2ce6faa 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sp804_timer.c +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sp804_timer.c @@ -3,7 +3,7 @@ // // Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sp804_timer.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sp804_timer.h index 777062cc..4d423904 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sp804_timer.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/sp804_timer.h @@ -4,7 +4,7 @@ // // Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/startup.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/startup.S index de100e56..9f0fc211 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/startup.S +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/startup.S @@ -7,7 +7,7 @@ // // Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ @@ -328,7 +328,7 @@ el1_entry_aarch64: // // Cortex-A processors automatically invalidate their caches on reset // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). - // It is therefore not necessary for software to invalidate the caches + // It is therefore not necessary for software to invalidate the caches // on startup, however, this is done here in case of a warm reset. bl InvalidateUDCaches tlbi VMALLE1 diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S index ebbc5ce3..47bd46e8 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Initialize */ /** */ @@ -21,45 +22,39 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_initialize_low_level Cortex-A35/AC6 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-A35/AC6 */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function is responsible for any low-level processor */ -/* initialization, including setting up interrupt vectors, setting */ -/* up a periodic timer interrupt source, saving the system stack */ -/* pointer for use in ISR processing later, and finding the first */ -/* available RAM memory address for tx_application_define. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ /* */ /**************************************************************************/ /* VOID _tx_initialize_low_level(VOID) diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_aarch64.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_aarch64.S index f8db3bfe..45445a98 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_aarch64.S +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_aarch64.S @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_aarch64.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_aarch64.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_mmu.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_mmu.h index ee8834fa..d0c51601 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_mmu.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_mmu.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_system.h b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_system.h index ff96deff..a62d2a33 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_system.h +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_system.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_utils.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_utils.S index f0fcef26..888892a0 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_utils.S +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/v8_utils.S @@ -3,7 +3,7 @@ // // Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/vectors.S b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/vectors.S index 9e60e001..7784f98e 100644 --- a/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/vectors.S +++ b/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/vectors.S @@ -3,7 +3,7 @@ // // Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/ac6/example_build/tx/.cproject b/ports_module/cortex_a35/ac6/example_build/tx/.cproject index 51f626a6..be84e260 100644 --- a/ports_module/cortex_a35/ac6/example_build/tx/.cproject +++ b/ports_module/cortex_a35/ac6/example_build/tx/.cproject @@ -1,172 +1,172 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_a35/ac6/example_build/txm/.cproject b/ports_module/cortex_a35/ac6/example_build/txm/.cproject index dddf4382..b1d86a47 100644 --- a/ports_module/cortex_a35/ac6/example_build/txm/.cproject +++ b/ports_module/cortex_a35/ac6/example_build/txm/.cproject @@ -1,172 +1,172 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_a35/ac6/inc/tx_port.h b/ports_module/cortex_a35/ac6/inc/tx_port.h index 92dc14f3..657ad451 100644 --- a/ports_module/cortex_a35/ac6/inc/tx_port.h +++ b/ports_module/cortex_a35/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,12 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -59,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -119,19 +114,19 @@ typedef unsigned long long ALIGN_TYPE; #define TX_TIMER_THREAD_STACK_SIZE 4096 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY +#ifndef TX_TIMER_THREAD_PRIORITY #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX Cortex ARMv8 port. */ +/* Define various constants for the ThreadX Cortex ARMv8 port. */ #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ #define TX_INT_ENABLE 0x00 /* Enable IRQ & FIQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -189,7 +184,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -203,7 +198,7 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ #define TX_THREAD_EXTENSION_0 @@ -243,11 +238,11 @@ ULONG _tx_misra_time_stamp_get(VOID); VOID (*tx_timer_module_expiration_function)(ULONG id); -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -255,8 +250,8 @@ ULONG _tx_misra_time_stamp_get(VOID); tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -283,8 +278,8 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -296,7 +291,7 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the internal timer extension to also hold the thread pointer such that _tx_thread_timeout can figure out what thread timeout to process. */ - + #define TX_TIMER_INTERNAL_EXTENSION VOID *tx_timer_internal_thread_timeout_ptr; @@ -312,9 +307,9 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_TIMEOUT_POINTER_SETUP(t) (t) = (TX_THREAD *) _tx_timer_expired_timer_ptr -> tx_timer_internal_thread_timeout_ptr; -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -385,8 +380,8 @@ VOID tx_thread_fp_disable(VOID); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Modules Cortex-A35/AC6 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Modules Cortex-A35/AC6 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a35/ac6/inc/txm_module_port.h b/ports_module/cortex_a35/ac6/inc/txm_module_port.h index 44009c55..cbe6b8e3 100644 --- a/ports_module/cortex_a35/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_a35/ac6/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,12 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -278,6 +273,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-A35/AC6 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-A35/AC6 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_a35/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_a35/ac6/module_lib/src/txm_module_initialize.S index c98ad715..2a04ce86 100644 --- a/ports_module/cortex_a35/ac6/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_a35/ac6/module_lib/src/txm_module_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_module/cortex_a35/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_a35/ac6/module_lib/src/txm_module_thread_shell_entry.c index e24e27be..adf4163f 100644 --- a/ports_module/cortex_a35/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_a35/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -80,12 +81,6 @@ ALIGN_TYPE (*_txm_module_kernel_call_dispatcher)(ULONG type /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -122,7 +117,7 @@ VOID (*entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT type); An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_context_restore.S index 655674de..93c46c88 100644 --- a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { @@ -86,13 +81,13 @@ _tx_thread_context_restore: LDR x3, =_tx_thread_system_state // Pickup address of system state var LDR w2, [x3, #0] // Pickup system state SUB w2, w2, #1 // Decrement the counter - STR w2, [x3, #0] // Store the counter + STR w2, [x3, #0] // Store the counter CMP w2, #0 // Was this the first interrupt? BEQ __tx_thread_not_nested_restore // If so, not a nested restore /* Interrupts are nested. */ - /* Just recover the saved registers and return to the point of + /* Just recover the saved registers and return to the point of interrupt. */ LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_context_save.S index ce4fec26..b2d8af34 100644 --- a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { @@ -68,7 +63,7 @@ _tx_thread_context_save: /* Upon entry to this routine, it is assumed that IRQ/FIQ interrupts are locked - out, x29 (frame pointer), x30 (link register) are saved, we are in EL1, + out, x29 (frame pointer), x30 (link register) are saved, we are in EL1, and all other registers are intact. */ /* Check for a nested interrupt condition. */ @@ -137,7 +132,7 @@ __tx_thread_not_nested_save: LDR x1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR x0, [x1, #0] // Pickup current thread pointer CMP x0, #0 // Is it NULL? - BEQ __tx_thread_idle_system_save // If so, interrupt occurred in + BEQ __tx_thread_idle_system_save // If so, interrupt occurred in // scheduling loop - nothing needs saving! /* Save minimal context of interrupted thread. */ @@ -196,7 +191,7 @@ __tx_thread_idle_system_save: /* Interrupt occurred in the scheduling loop. */ - /* Not much to do here, just adjust the stack pointer, and return to IRQ + /* Not much to do here, just adjust the stack pointer, and return to IRQ processing. */ #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY @@ -209,8 +204,8 @@ __tx_thread_idle_system_save: #endif ADD sp, sp, #48 // Recover saved registers - RET // Continue IRQ processing + RET // Continue IRQ processing // } -// } +// } diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_fp_disable.c b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_fp_disable.c index b045bdab..aa96ffb0 100644 --- a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_fp_disable.c +++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,12 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { @@ -81,11 +76,11 @@ ULONG system_state; /* Make sure it is not NULL. */ if (thread_ptr != TX_NULL) { - + /* Thread is running... make sure the call is from the thread context. */ if (system_state == 0) { - + /* Yes, now set the FP enable flag to false in the TX_THREAD structure. */ thread_ptr -> tx_thread_fp_enable = TX_FALSE; } diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_fp_enable.c b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_fp_enable.c index 80ef1e7e..2cf3ba17 100644 --- a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_fp_enable.c +++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,12 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { @@ -81,11 +76,11 @@ ULONG system_state; /* Make sure it is not NULL. */ if (thread_ptr != TX_NULL) { - + /* Thread is running... make sure the call is from the thread context. */ if (system_state == 0) { - + /* Yes, now setup the FP enable flag in the TX_THREAD structure. */ thread_ptr -> tx_thread_fp_enable = TX_TRUE; } diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_control.S index 0bb03ed4..60cf4982 100644 --- a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_disable.S index f5ee54a2..72742e7a 100644 --- a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_restore.S index 5ed509d8..42643576 100644 --- a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_schedule.S index 1193fdca..f86f4212 100644 --- a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -76,15 +71,15 @@ _tx_thread_schedule: // Wait for a thread to execute. */ // do // { - + LDR x1, =_tx_thread_execute_ptr // Address of thread execute ptr #ifdef TX_ENABLE_WFI __tx_thread_schedule_loop: LDR x0, [x1, #0] // Pickup next thread to execute CMP x0, #0 // Is it NULL? - BNE _tx_thread_schedule_thread // - WFI // + BNE _tx_thread_schedule_thread // + WFI // B __tx_thread_schedule_loop // Keep looking for a thread _tx_thread_schedule_thread: #else @@ -96,7 +91,7 @@ __tx_thread_schedule_loop: // } // while(_tx_thread_execute_ptr == TX_NULL); - + /* Yes! We have a thread to execute. Lockout interrupts and transfer control to it. */ @@ -105,7 +100,7 @@ __tx_thread_schedule_loop: /* Setup the current thread pointer. */ // _tx_thread_current_ptr = _tx_thread_execute_ptr; - LDR x1, =_tx_thread_current_ptr // Pickup address of current thread + LDR x1, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x1, #0] // Setup current thread pointer /* Increment the run count for this thread. */ @@ -119,7 +114,7 @@ __tx_thread_schedule_loop: /* Setup time-slice, if present. */ // _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; - LDR x2, =_tx_timer_time_slice // Pickup address of time slice + LDR x2, =_tx_timer_time_slice // Pickup address of time slice // variable LDR x4, [x0, #8] // Switch stack pointers MOV sp, x4 // diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_stack_build.S index 37c22e90..bacd87eb 100644 --- a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_system_return.S index 4c5af0dc..e4cebb03 100644 --- a/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_a35/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_a35/ac6/module_manager/src/tx_timer_interrupt.S index 895b5a7d..bad45ccd 100644 --- a/ports_module/cortex_a35/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_a35/ac6/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,12 +58,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { @@ -86,7 +81,7 @@ _tx_timer_interrupt: // if (_tx_timer_time_slice) // { - LDR x3, =_tx_timer_time_slice // Pickup address of time-slice + LDR x3, =_tx_timer_time_slice // Pickup address of time-slice LDR w2, [x3, #0] // Pickup time-slice CMP w2, #0 // Is it non-active? BEQ __tx_timer_no_time_slice // Yes, skip time-slice processing @@ -203,7 +198,7 @@ __tx_timer_dont_activate: // if (_tx_timer_expired_time_slice) // { - LDR x3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired + LDR x3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired LDR w2, [x3, #0] // Pickup the actual flag CMP w2, #0 // See if the flag is set BEQ __tx_timer_not_ts_expiration // No, skip time-slice processing diff --git a/ports_module/cortex_a35/ac6/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_a35/ac6/module_manager/src/txm_module_manager_port_dispatch.c index 2a399a17..5cd9edd6 100644 --- a/ports_module/cortex_a35/ac6/module_manager/src/txm_module_manager_port_dispatch.c +++ b/ports_module/cortex_a35/ac6/module_manager/src/txm_module_manager_port_dispatch.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,12 +60,6 @@ /* */ /* _txm_module_manager_kernel_dispatch */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) { @@ -79,6 +74,6 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; break; } } - + return(return_value); } diff --git a/ports_module/cortex_a35/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_a35/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index de09130c..8ecb5044 100644 --- a/ports_module/cortex_a35/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_a35/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_a35/ac6/readme_threadx.txt b/ports_module/cortex_a35/ac6/readme_threadx.txt index e8c6ce96..3c522c31 100644 --- a/ports_module/cortex_a35/ac6/readme_threadx.txt +++ b/ports_module/cortex_a35/ac6/readme_threadx.txt @@ -1,20 +1,20 @@ - Microsoft's Azure RTOS ThreadX Modules for Cortex-A35 + Microsoft's Azure RTOS ThreadX Modules for Cortex-A35 Using the ARM Compiler 6 & DS 1. Import the ThreadX Modules Projects -In order to build the ThreadX library and the ThreadX demonstration, first import +In order to build the ThreadX library and the ThreadX demonstration, first import the 'tx', 'txm', 'sample_threadx', 'sample_threadx_module' and -'sample_thread_module_manager' projects (located in the "example_build" directory) +'sample_thread_module_manager' projects (located in the "example_build" directory) into your DS workspace. 2. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply select the Eclipse project file -"tx" and then select the build button. You should now observe the compilation -and assembly of the ThreadX library. This project build produces the ThreadX +Building the ThreadX library is easy; simply select the Eclipse project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. To bild the ThreadX Module library select the project "txm" and select the build button to produce the file txm.a. @@ -36,8 +36,8 @@ First build the ThreadX sample module project sample_thread_module by selecting clicking the build button. Next built the ThreadX Module Manager sample by selecting sample_threadx_module_manager and clicking the build button. -To run the ThreadX Module Manager demo in the sample_threadx_module_manager project, -right-click on the sample_threadx_module_manager.launch file and select 'Debug As -> sample_threadx'. +To run the ThreadX Module Manager demo in the sample_threadx_module_manager project, +right-click on the sample_threadx_module_manager.launch file and select 'Debug As -> sample_threadx'. The debugger is setup for the Cortex-A35 FVP, so selecting "Debug" will launch the FVP, load the sample_threadx.axf ELF file and run to the entry point. You are now ready to execute the ThreadX demonstration. @@ -45,29 +45,29 @@ the ThreadX demonstration. 4. System Initialization -The entry point in ThreadX for the Cortex-A35 using AC6 tools is at label -"start64". This is defined within the AC6 compiler's startup code. In addition, -this is where all static and global pre-set C variable initialization processing +The entry point in ThreadX for the Cortex-A35 using AC6 tools is at label +"start64". This is defined within the AC6 compiler's startup code. In addition, +this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for determining the -first available RAM address for use by the application, which is supplied as the +The ThreadX tx_initialize_low_level.s file is responsible for determining the +first available RAM address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 5. Register Usage and Stack Frames -The 64-bit AC6 compiler assumes that registers x0-x18 are scratch registers -for each function. All other registers used by a C function must be preserved -by the function. ThreadX takes advantage of this in situations where a context -switch happens as a result of making a ThreadX service call (which is itself a -C function). In such cases, the saved context of a thread is only the +The 64-bit AC6 compiler assumes that registers x0-x18 are scratch registers +for each function. All other registers used by a C function must be preserved +by the function. ThreadX takes advantage of this in situations where a context +switch happens as a result of making a ThreadX service call (which is itself a +C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -108,7 +108,7 @@ FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: 0x0F0 x0 0x0F8 x1 0x100 x29 - 0x108 x30 + 0x108 x30 FP enabled and TX_THREAD.tx_thread_fp_enable == 1: @@ -194,14 +194,14 @@ FP enabled and TX_THREAD.tx_thread_fp_enable == 1: 6. Improving Performance -The distribution version of ThreadX is built without any compiler optimizations. -This makes it easy to debug because you can trace or set breakpoints inside of -ThreadX itself. Of course, this costs some performance. To make it run faster, +The distribution version of ThreadX is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the project settings to the desired compiler optimization level. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling @@ -221,22 +221,22 @@ irq_handler: B _tx_thread_context_restore -By default, ThreadX assumes EL3 level of execution. Running and taking exceptions in EL1 +By default, ThreadX assumes EL3 level of execution. Running and taking exceptions in EL1 and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined. 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, thread sleeps, -timeouts, and application timers. Without such a timer interrupt source, these services -are not functional. However, all other ThreadX services are operational without a +ThreadX requires a periodic interrupt source to manage all time-slicing, thread sleeps, +timeouts, and application timers. Without such a timer interrupt source, these services +are not functional. However, all other ThreadX services are operational without a periodic timer source. 9. ARM FP Support By default, FP support is disabled for each thread. If saving the context of the FP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the FP usage: void tx_thread_fp_enable(void); diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/.cproject b/ports_module/cortex_a35/gnu/example_build/sample_threadx/.cproject index 7eb75c64..0bcc75f1 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/.cproject +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/.cproject @@ -1,252 +1,252 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3.h index 23bc7fd8..dfe37586 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3.h @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef GICV3_h diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_aliases.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_aliases.h index 0928d14c..826ba973 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_aliases.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_aliases.h @@ -3,7 +3,7 @@ // // Copyright (c) 2016-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicc.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicc.h index 2b8a2d3e..998d92b5 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicc.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicc.h @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef GICV3_gicc_h diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicd.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicd.c index 2cf9e843..464ecced 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicd.c +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicd.c @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #include diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicr.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicr.c index b0d22c40..61addaef 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicr.c +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicr.c @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #include "GICv3.h" diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.S index e7f95aa7..e8a87f0b 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -4,7 +4,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/PPM_AEM.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx/PPM_AEM.h index 52c9a0fe..f7501eeb 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/PPM_AEM.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/PPM_AEM.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.c index 8898ff39..736722fb 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -87,42 +87,42 @@ UCHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -130,23 +130,23 @@ UCHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -250,11 +250,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -313,7 +313,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -366,7 +366,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.ld b/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.ld index eec8f12b..3bf47736 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/sp804_timer.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx/sp804_timer.c index 4dc009b2..c2ce6faa 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/sp804_timer.c +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/sp804_timer.c @@ -3,7 +3,7 @@ // // Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/sp804_timer.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx/sp804_timer.h index 777062cc..4d423904 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/sp804_timer.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/sp804_timer.h @@ -4,7 +4,7 @@ // // Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/startup.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx/startup.S index 67dd8a6a..b44806fe 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/startup.S +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/startup.S @@ -7,7 +7,7 @@ // // Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ @@ -328,7 +328,7 @@ el1_entry_aarch64: // // Cortex-A processors automatically invalidate their caches on reset // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). - // It is therefore not necessary for software to invalidate the caches + // It is therefore not necessary for software to invalidate the caches // on startup, however, this is done here in case of a warm reset. bl InvalidateUDCaches tlbi VMALLE1 diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx/tx_initialize_low_level.S index f4e6ea0a..55ec0f9f 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Initialize */ /** */ @@ -21,45 +22,39 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_initialize_low_level Cortex-A35/GNU */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-A35/GNU */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function is responsible for any low-level processor */ -/* initialization, including setting up interrupt vectors, setting */ -/* up a periodic timer interrupt source, saving the system stack */ -/* pointer for use in ISR processing later, and finding the first */ -/* available RAM memory address for tx_application_define. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ /* */ /**************************************************************************/ /* VOID _tx_initialize_low_level(VOID) diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.S index f8db3bfe..45445a98 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.S +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.S @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_mmu.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_mmu.h index ee8834fa..d0c51601 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_mmu.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_system.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_system.h index ff96deff..a62d2a33 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_system.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_system.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_utils.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_utils.S index f0fcef26..888892a0 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_utils.S +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/v8_utils.S @@ -3,7 +3,7 @@ // // Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx/vectors.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx/vectors.S index 9e60e001..7784f98e 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx/vectors.S +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx/vectors.S @@ -3,7 +3,7 @@ // // Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/.cproject b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/.cproject index 296685a7..50726e80 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/.cproject +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/.cproject @@ -1,184 +1,184 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/gcc_setup.s b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/gcc_setup.s index 7c454996..e0569f71 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/gcc_setup.s +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/gcc_setup.s @@ -17,7 +17,7 @@ _gcc_setup: ldr x9, =__RAM_segment_start__ /* Copy GOT table. */ - + ldr x0, =__got_load_start__ sub x0 ,x0, x3 add x0, x0, x5 @@ -51,7 +51,7 @@ got_setup_done: /* Copy initialised sections into RAM if required. */ - + ldr x0, =__data_load_start__ sub x0, x0, x3 add x0, x0, x5 @@ -62,9 +62,9 @@ got_setup_done: sub x2, x2, x4 add x2, x2, x9 bl crt0_memory_copy - + /* Zero bss. */ - + ldr x0, =__bss_start__ sub x0, x0, x4 add x0, x0, x9 @@ -88,12 +88,12 @@ got_setup_done: str x2, [x0] add x0, x0, #4 str x1, [x0] - + ldr x30, [sp] // Restore other preserved registers add sp, sp, 16 ret // Return to caller - + /* Startup helper functions. */ @@ -126,4 +126,4 @@ memory_set_done: /* Setup attibutes of heap section so it doesn't take up room in the elf file */ .section .heap, "wa", %nobits - + diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/sample_threadx_module.c index 3a3f8159..3476367e 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / sizeof(ULONG)]; @@ -103,7 +103,7 @@ CHAR *pointer; /* Allocate all the objects. In MMU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ status = txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); while (status != TX_SUCCESS); @@ -133,7 +133,7 @@ CHAR *pointer; while (status != TX_SUCCESS); status = txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); while (status != TX_SUCCESS); - + /* Create a byte memory pool from which to allocate the thread stacks. */ status = tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -148,7 +148,7 @@ CHAR *pointer; /* Create the main thread. */ status = tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -156,11 +156,11 @@ CHAR *pointer; status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); while (status != TX_SUCCESS); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ status = tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); while (status != TX_SUCCESS); @@ -169,7 +169,7 @@ CHAR *pointer; while (status != TX_SUCCESS); status = tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); while (status != TX_SUCCESS); @@ -177,10 +177,10 @@ CHAR *pointer; status = tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); while (status != TX_SUCCESS); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ status = tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -189,7 +189,7 @@ CHAR *pointer; while (status != TX_SUCCESS); status = tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -200,7 +200,7 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ status = tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -210,7 +210,7 @@ CHAR *pointer; /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ status = tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -219,7 +219,7 @@ CHAR *pointer; while (status != TX_SUCCESS); status = tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); while (status != TX_SUCCESS); @@ -276,7 +276,7 @@ void thread_0_entry(ULONG thread_input) { UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -286,7 +286,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -338,11 +338,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -401,7 +401,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -454,7 +454,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/sample_threadx_module.ld b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/sample_threadx_module.ld index 042b59bf..d117a5df 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/sample_threadx_module.ld +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/sample_threadx_module.ld @@ -110,7 +110,7 @@ SECTIONS KEEP (*(.got*)) . = ALIGN(4); _egot = .; - } + } __got_end__ = __got_load_start__ + SIZEOF(.got); __rodata_load_start__ = ALIGN(__got_end__ , 4); @@ -120,7 +120,7 @@ SECTIONS *(.rodata .rodata.* .gnu.linkonce.r.*) } __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); - + __code_size__ = __rodata_end__ - __FLASH_segment_start__; __fast_load_start__ = ALIGN(__rodata_end__ , 4); diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/txm_module_preamble.S index 616d4165..bb0acb6f 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module/txm_module_preamble.S @@ -1,6 +1,6 @@ .section .txm_module_preamble, "ax" .align 4 - + // External references .global _txm_module_thread_shell_entry .global _txm_module_callback_request_thread_entry diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/.cproject index 79e120b4..b1950eb6 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/.cproject +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/.cproject @@ -1,264 +1,264 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3.h index 23bc7fd8..dfe37586 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3.h @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef GICV3_h diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_aliases.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_aliases.h index 0928d14c..826ba973 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_aliases.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_aliases.h @@ -3,7 +3,7 @@ // // Copyright (c) 2016-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicc.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicc.h index 2b8a2d3e..998d92b5 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicc.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicc.h @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef GICV3_gicc_h diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicd.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicd.c index 2cf9e843..464ecced 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicd.c +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicd.c @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #include diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicr.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicr.c index b0d22c40..61addaef 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicr.c +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/GICv3_gicr.c @@ -3,7 +3,7 @@ * * Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #include "GICv3.h" diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.S index e7f95aa7..e8a87f0b 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.S +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.S @@ -4,7 +4,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/PPM_AEM.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/PPM_AEM.h index 52c9a0fe..f7501eeb 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/PPM_AEM.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/PPM_AEM.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index c7296646..c0772002 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -115,7 +115,7 @@ void module_manager_entry(ULONG thread_input) /* Load the module with absolute address linkage, in this example it is placed there by the multiple image download. */ txm_module_manager_absolute_load(&my_module, "my module", (void *) MODULE_CODE); - + /* Start the module. */ txm_module_manager_start(&my_module); @@ -127,10 +127,10 @@ void module_manager_entry(ULONG thread_input) tx_thread_sleep(10); } } - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -139,11 +139,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(10); } } diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ld b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ld index eec8f12b..3bf47736 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ld +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sp804_timer.c b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sp804_timer.c index 4dc009b2..c2ce6faa 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sp804_timer.c +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sp804_timer.c @@ -3,7 +3,7 @@ // // Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sp804_timer.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sp804_timer.h index 777062cc..4d423904 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sp804_timer.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/sp804_timer.h @@ -4,7 +4,7 @@ // // Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/startup.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/startup.S index 67dd8a6a..b44806fe 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/startup.S +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/startup.S @@ -7,7 +7,7 @@ // // Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ @@ -328,7 +328,7 @@ el1_entry_aarch64: // // Cortex-A processors automatically invalidate their caches on reset // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). - // It is therefore not necessary for software to invalidate the caches + // It is therefore not necessary for software to invalidate the caches // on startup, however, this is done here in case of a warm reset. bl InvalidateUDCaches tlbi VMALLE1 diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/tx_initialize_low_level.S index f4e6ea0a..55ec0f9f 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/tx_initialize_low_level.S +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Initialize */ /** */ @@ -21,45 +22,39 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_initialize_low_level Cortex-A35/GNU */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-A35/GNU */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function is responsible for any low-level processor */ -/* initialization, including setting up interrupt vectors, setting */ -/* up a periodic timer interrupt source, saving the system stack */ -/* pointer for use in ISR processing later, and finding the first */ -/* available RAM memory address for tx_application_define. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ /* */ /**************************************************************************/ /* VOID _tx_initialize_low_level(VOID) diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_aarch64.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_aarch64.S index f8db3bfe..45445a98 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_aarch64.S +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_aarch64.S @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_aarch64.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_aarch64.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_mmu.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_mmu.h index ee8834fa..d0c51601 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_mmu.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_mmu.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_system.h b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_system.h index ff96deff..a62d2a33 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_system.h +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_system.h @@ -3,7 +3,7 @@ // // Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_utils.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_utils.S index f0fcef26..888892a0 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_utils.S +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/v8_utils.S @@ -3,7 +3,7 @@ // // Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // diff --git a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/vectors.S b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/vectors.S index 9e60e001..7784f98e 100644 --- a/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/vectors.S +++ b/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/vectors.S @@ -3,7 +3,7 @@ // // Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_module/cortex_a35/gnu/example_build/tx/.cproject b/ports_module/cortex_a35/gnu/example_build/tx/.cproject index e3b8bf79..ce420cbc 100644 --- a/ports_module/cortex_a35/gnu/example_build/tx/.cproject +++ b/ports_module/cortex_a35/gnu/example_build/tx/.cproject @@ -1,258 +1,258 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_a35/gnu/example_build/txm/.cproject b/ports_module/cortex_a35/gnu/example_build/txm/.cproject index 267cf889..88aec6be 100644 --- a/ports_module/cortex_a35/gnu/example_build/txm/.cproject +++ b/ports_module/cortex_a35/gnu/example_build/txm/.cproject @@ -1,198 +1,198 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_a35/gnu/inc/tx_port.h b/ports_module/cortex_a35/gnu/inc/tx_port.h index 55007b04..edf3ad66 100644 --- a/ports_module/cortex_a35/gnu/inc/tx_port.h +++ b/ports_module/cortex_a35/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,12 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -59,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -119,19 +114,19 @@ typedef unsigned long long ALIGN_TYPE; #define TX_TIMER_THREAD_STACK_SIZE 4096 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY +#ifndef TX_TIMER_THREAD_PRIORITY #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX Cortex ARMv8 port. */ +/* Define various constants for the ThreadX Cortex ARMv8 port. */ #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ #define TX_INT_ENABLE 0x00 /* Enable IRQ & FIQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -189,7 +184,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -203,7 +198,7 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ #define TX_THREAD_EXTENSION_0 @@ -243,11 +238,11 @@ ULONG _tx_misra_time_stamp_get(VOID); VOID (*tx_timer_module_expiration_function)(ULONG id); -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -255,8 +250,8 @@ ULONG _tx_misra_time_stamp_get(VOID); tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -283,8 +278,8 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -296,7 +291,7 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the internal timer extension to also hold the thread pointer such that _tx_thread_timeout can figure out what thread timeout to process. */ - + #define TX_TIMER_INTERNAL_EXTENSION VOID *tx_timer_internal_thread_timeout_ptr; @@ -312,9 +307,9 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_TIMEOUT_POINTER_SETUP(t) (t) = (TX_THREAD *) _tx_timer_expired_timer_ptr -> tx_timer_internal_thread_timeout_ptr; -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -385,8 +380,8 @@ VOID tx_thread_fp_disable(VOID); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Modules Cortex-A35/GNU Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Modules Cortex-A35/GNU Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a35/gnu/inc/txm_module_port.h b/ports_module/cortex_a35/gnu/inc/txm_module_port.h index 847f35c5..e5654cde 100644 --- a/ports_module/cortex_a35/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_a35/gnu/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,12 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -278,6 +273,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-A35/GNU Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-A35/GNU Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_a35/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_a35/gnu/module_lib/src/txm_module_thread_shell_entry.c index 8ac207f0..922b9306 100644 --- a/ports_module/cortex_a35/gnu/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_a35/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -80,12 +81,6 @@ ALIGN_TYPE (*_txm_module_kernel_call_dispatcher)(ULONG type /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -122,7 +117,7 @@ VOID (*entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT type); An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_context_restore.S index 34b0db92..d1ef83ca 100644 --- a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { @@ -87,13 +82,13 @@ _tx_thread_context_restore: LDR x3, =_tx_thread_system_state // Pickup address of system state var LDR w2, [x3, #0] // Pickup system state SUB w2, w2, #1 // Decrement the counter - STR w2, [x3, #0] // Store the counter + STR w2, [x3, #0] // Store the counter CMP w2, #0 // Was this the first interrupt? BEQ __tx_thread_not_nested_restore // If so, not a nested restore /* Interrupts are nested. */ - /* Just recover the saved registers and return to the point of + /* Just recover the saved registers and return to the point of interrupt. */ LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_context_save.S index 349f04f3..c8b3312f 100644 --- a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { @@ -68,7 +63,7 @@ _tx_thread_context_save: /* Upon entry to this routine, it is assumed that IRQ/FIQ interrupts are locked - out, x29 (frame pointer), x30 (link register) are saved, we are in EL1, + out, x29 (frame pointer), x30 (link register) are saved, we are in EL1, and all other registers are intact. */ /* Check for a nested interrupt condition. */ @@ -137,7 +132,7 @@ __tx_thread_not_nested_save: LDR x1, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR x0, [x1, #0] // Pickup current thread pointer CMP x0, #0 // Is it NULL? - BEQ __tx_thread_idle_system_save // If so, interrupt occurred in + BEQ __tx_thread_idle_system_save // If so, interrupt occurred in // scheduling loop - nothing needs saving! /* Save minimal context of interrupted thread. */ @@ -196,7 +191,7 @@ __tx_thread_idle_system_save: /* Interrupt occurred in the scheduling loop. */ - /* Not much to do here, just adjust the stack pointer, and return to IRQ + /* Not much to do here, just adjust the stack pointer, and return to IRQ processing. */ #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY @@ -209,8 +204,8 @@ __tx_thread_idle_system_save: #endif ADD sp, sp, #48 // Recover saved registers - RET // Continue IRQ processing + RET // Continue IRQ processing // } -// } +// } diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_fp_disable.c b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_fp_disable.c index 1bf9d364..d586d241 100644 --- a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_fp_disable.c +++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,12 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { @@ -81,11 +76,11 @@ ULONG system_state; /* Make sure it is not NULL. */ if (thread_ptr != TX_NULL) { - + /* Thread is running... make sure the call is from the thread context. */ if (system_state == 0) { - + /* Yes, now set the FP enable flag to false in the TX_THREAD structure. */ thread_ptr -> tx_thread_fp_enable = TX_FALSE; } diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_fp_enable.c b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_fp_enable.c index 76516b23..ead0c528 100644 --- a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_fp_enable.c +++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,12 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { @@ -81,11 +76,11 @@ ULONG system_state; /* Make sure it is not NULL. */ if (thread_ptr != TX_NULL) { - + /* Thread is running... make sure the call is from the thread context. */ if (system_state == 0) { - + /* Yes, now setup the FP enable flag in the TX_THREAD structure. */ thread_ptr -> tx_thread_fp_enable = TX_TRUE; } diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_control.S index f271084c..fe702a39 100644 --- a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_disable.S index 6c781d55..0add0b6f 100644 --- a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_restore.S index 0ab1b0e3..74cc9266 100644 --- a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_schedule.S index f39d341b..a94a70ef 100644 --- a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -76,15 +71,15 @@ _tx_thread_schedule: // Wait for a thread to execute. */ // do // { - + LDR x1, =_tx_thread_execute_ptr // Address of thread execute ptr #ifdef TX_ENABLE_WFI __tx_thread_schedule_loop: LDR x0, [x1, #0] // Pickup next thread to execute CMP x0, #0 // Is it NULL? - BNE _tx_thread_schedule_thread // - WFI // + BNE _tx_thread_schedule_thread // + WFI // B __tx_thread_schedule_loop // Keep looking for a thread _tx_thread_schedule_thread: #else @@ -96,7 +91,7 @@ __tx_thread_schedule_loop: // } // while(_tx_thread_execute_ptr == TX_NULL); - + /* Yes! We have a thread to execute. Lockout interrupts and transfer control to it. */ @@ -105,7 +100,7 @@ __tx_thread_schedule_loop: /* Setup the current thread pointer. */ // _tx_thread_current_ptr = _tx_thread_execute_ptr; - LDR x1, =_tx_thread_current_ptr // Pickup address of current thread + LDR x1, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x1, #0] // Setup current thread pointer /* Increment the run count for this thread. */ @@ -119,7 +114,7 @@ __tx_thread_schedule_loop: /* Setup time-slice, if present. */ // _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; - LDR x2, =_tx_timer_time_slice // Pickup address of time slice + LDR x2, =_tx_timer_time_slice // Pickup address of time slice // variable LDR x4, [x0, #8] // Switch stack pointers MOV sp, x4 // diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_stack_build.S index d5febaad..2c1c8f5f 100644 --- a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_system_return.S index bd00e697..7e43ba48 100644 --- a/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_a35/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_a35/gnu/module_manager/src/tx_timer_interrupt.S index a0007548..a1eb57bd 100644 --- a/ports_module/cortex_a35/gnu/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_a35/gnu/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,12 +58,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { @@ -86,7 +81,7 @@ _tx_timer_interrupt: // if (_tx_timer_time_slice) // { - LDR x3, =_tx_timer_time_slice // Pickup address of time-slice + LDR x3, =_tx_timer_time_slice // Pickup address of time-slice LDR w2, [x3, #0] // Pickup time-slice CMP w2, #0 // Is it non-active? BEQ __tx_timer_no_time_slice // Yes, skip time-slice processing @@ -203,7 +198,7 @@ __tx_timer_dont_activate: // if (_tx_timer_expired_time_slice) // { - LDR x3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired + LDR x3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired LDR w2, [x3, #0] // Pickup the actual flag CMP w2, #0 // See if the flag is set BEQ __tx_timer_not_ts_expiration // No, skip time-slice processing diff --git a/ports_module/cortex_a35/gnu/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_a35/gnu/module_manager/src/txm_module_manager_port_dispatch.c index cc3296cf..903b30f7 100644 --- a/ports_module/cortex_a35/gnu/module_manager/src/txm_module_manager_port_dispatch.c +++ b/ports_module/cortex_a35/gnu/module_manager/src/txm_module_manager_port_dispatch.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,12 +60,6 @@ /* */ /* _txm_module_manager_kernel_dispatch */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) { @@ -79,6 +74,6 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; break; } } - + return(return_value); } diff --git a/ports_module/cortex_a35/gnu/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_a35/gnu/module_manager/src/txm_module_manager_thread_stack_build.S index 983bd2a7..a9a50ec9 100644 --- a/ports_module/cortex_a35/gnu/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_a35/gnu/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_a35/gnu/readme_threadx.txt b/ports_module/cortex_a35/gnu/readme_threadx.txt index 13c2c9c0..c318db76 100644 --- a/ports_module/cortex_a35/gnu/readme_threadx.txt +++ b/ports_module/cortex_a35/gnu/readme_threadx.txt @@ -1,20 +1,20 @@ - Microsoft's Azure RTOS ThreadX Modules for Cortex-A35 + Microsoft's Azure RTOS ThreadX Modules for Cortex-A35 Using the ARM GNU Compiler & DS 1. Import the ThreadX Modules Projects -In order to build the ThreadX library and the ThreadX demonstration, first import +In order to build the ThreadX library and the ThreadX demonstration, first import the 'tx', 'txm', 'sample_threadx', 'sample_threadx_module' and -'sample_thread_module_manager' projects (located in the "example_build" directory) +'sample_thread_module_manager' projects (located in the "example_build" directory) into your DS workspace. 2. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply select the Eclipse project file -"tx" and then select the build button. You should now observe the compilation -and assembly of the ThreadX library. This project build produces the ThreadX +Building the ThreadX library is easy; simply select the Eclipse project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. To bild the ThreadX Module library select the project "txm" and select the build button to produce the file txm.a. @@ -36,8 +36,8 @@ First build the ThreadX sample module project sample_thread_module by selecting clicking the build button. Next built the ThreadX Module Manager sample by selecting sample_threadx_module_manager and clicking the build button. -To run the ThreadX Module Manager demo in the sample_threadx_module_manager project, -right-click on the sample_threadx_module_manager.launch file and select 'Debug As -> sample_threadx'. +To run the ThreadX Module Manager demo in the sample_threadx_module_manager project, +right-click on the sample_threadx_module_manager.launch file and select 'Debug As -> sample_threadx'. The debugger is setup for the Cortex-A35 FVP, so selecting "Debug" will launch the FVP, load the sample_threadx.axf ELF file and run to the entry point. You are now ready to execute the ThreadX demonstration. @@ -45,29 +45,29 @@ the ThreadX demonstration. 4. System Initialization -The entry point in ThreadX for the Cortex-A35 using GCC tools is at label -"start64". This is defined within the GCC compiler's startup code. In addition, -this is where all static and global pre-set C variable initialization processing +The entry point in ThreadX for the Cortex-A35 using GCC tools is at label +"start64". This is defined within the GCC compiler's startup code. In addition, +this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for determining the -first available RAM address for use by the application, which is supplied as the +The ThreadX tx_initialize_low_level.s file is responsible for determining the +first available RAM address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 5. Register Usage and Stack Frames -The 64-bit GCC compiler assumes that registers x0-x18 are scratch registers -for each function. All other registers used by a C function must be preserved -by the function. ThreadX takes advantage of this in situations where a context -switch happens as a result of making a ThreadX service call (which is itself a -C function). In such cases, the saved context of a thread is only the +The 64-bit GCC compiler assumes that registers x0-x18 are scratch registers +for each function. All other registers used by a C function must be preserved +by the function. ThreadX takes advantage of this in situations where a context +switch happens as a result of making a ThreadX service call (which is itself a +C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -108,7 +108,7 @@ FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: 0x0F0 x0 0x0F8 x1 0x100 x29 - 0x108 x30 + 0x108 x30 FP enabled and TX_THREAD.tx_thread_fp_enable == 1: @@ -194,14 +194,14 @@ FP enabled and TX_THREAD.tx_thread_fp_enable == 1: 6. Improving Performance -The distribution version of ThreadX is built without any compiler optimizations. -This makes it easy to debug because you can trace or set breakpoints inside of -ThreadX itself. Of course, this costs some performance. To make it run faster, +The distribution version of ThreadX is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX itself. Of course, this costs some performance. To make it run faster, you can change the project settings to the desired compiler optimization level. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling @@ -221,22 +221,22 @@ irq_handler: B _tx_thread_context_restore -By default, ThreadX assumes EL3 level of execution. Running and taking exceptions in EL1 +By default, ThreadX assumes EL3 level of execution. Running and taking exceptions in EL1 and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined. 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, thread sleeps, -timeouts, and application timers. Without such a timer interrupt source, these services -are not functional. However, all other ThreadX services are operational without a +ThreadX requires a periodic interrupt source to manage all time-slicing, thread sleeps, +timeouts, and application timers. Without such a timer interrupt source, these services +are not functional. However, all other ThreadX services are operational without a periodic timer source. 9. ARM FP Support By default, FP support is disabled for each thread. If saving the context of the FP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the FP usage: void tx_thread_fp_enable(void); diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/.cproject b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/.cproject index 40b668c4..58ba80a5 100644 --- a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/.cproject +++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.scat index 1288a328..1ed382ae 100644 --- a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.scat @@ -12,13 +12,13 @@ LOAD 0x80000000 { startup.o (StartUp, +FIRST) * (+RO, +RW, +ZI) - + } ;XTABLES +0 ALIGN 0x1000 ;{ - ; xtables.o (*) + ; xtables.o (*) ;} - + SYS_STACK +0 ALIGN 8 EMPTY 0x1000 { } @@ -34,13 +34,13 @@ LOAD 0x80000000 ; All stacks and heap are aligned to a cache-line boundary ; ARM_LIB_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary ; HANDLER_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Stacks for EL3 ; @@ -217,34 +217,34 @@ LOAD 0x80000000 ; { ; *( +RO ) ; } -; +; ; XTABLES +0 ALIGN 0x1000 ; { -; xtables.o (*) +; xtables.o (*) ; } ;} ; ;RW AlignExpr(ImageLimit(XTABLES), 0x1000) -;{ +;{ ; RWSEC +0 ; { ; *( +RW ) ; } -; +; ; ZISEC +0 ; { ; *( +ZI ) ; } -; +; ; SYS_STACK +0 ALIGN 8 EMPTY 0x1000 ; { ; } -; +; ; ; 512 MiB heap ; HEAP +0 ALIGN 8 EMPTY 0x10000000 ; { ; } -; +; ; ; Free Memory section ; FREE_MEMORY +0 ALIGN 8 EMPTY 0x10000000 ; { @@ -254,7 +254,7 @@ LOAD 0x80000000 ; TASK_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { ; } -; +; ; ; Per-CPU 128 MiB handler stacks ; HANDLER_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/.cproject b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/.cproject index c27fce90..e7a98e77 100644 --- a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/.cproject +++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module/.cproject @@ -1,246 +1,246 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/.cproject index 7ff6378d..efbbbaa7 100644 --- a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/.cproject +++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/.cproject @@ -1,244 +1,244 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.scat b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.scat index 1288a328..1ed382ae 100644 --- a/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.scat +++ b/ports_module/cortex_a35_smp/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.scat @@ -12,13 +12,13 @@ LOAD 0x80000000 { startup.o (StartUp, +FIRST) * (+RO, +RW, +ZI) - + } ;XTABLES +0 ALIGN 0x1000 ;{ - ; xtables.o (*) + ; xtables.o (*) ;} - + SYS_STACK +0 ALIGN 8 EMPTY 0x1000 { } @@ -34,13 +34,13 @@ LOAD 0x80000000 ; All stacks and heap are aligned to a cache-line boundary ; ARM_LIB_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary ; HANDLER_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Stacks for EL3 ; @@ -217,34 +217,34 @@ LOAD 0x80000000 ; { ; *( +RO ) ; } -; +; ; XTABLES +0 ALIGN 0x1000 ; { -; xtables.o (*) +; xtables.o (*) ; } ;} ; ;RW AlignExpr(ImageLimit(XTABLES), 0x1000) -;{ +;{ ; RWSEC +0 ; { ; *( +RW ) ; } -; +; ; ZISEC +0 ; { ; *( +ZI ) ; } -; +; ; SYS_STACK +0 ALIGN 8 EMPTY 0x1000 ; { ; } -; +; ; ; 512 MiB heap ; HEAP +0 ALIGN 8 EMPTY 0x10000000 ; { ; } -; +; ; ; Free Memory section ; FREE_MEMORY +0 ALIGN 8 EMPTY 0x10000000 ; { @@ -254,7 +254,7 @@ LOAD 0x80000000 ; TASK_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { ; } -; +; ; ; Per-CPU 128 MiB handler stacks ; HANDLER_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { diff --git a/ports_module/cortex_a35_smp/ac6/example_build/tx/.cproject b/ports_module/cortex_a35_smp/ac6/example_build/tx/.cproject index b5457c00..d1e7ba11 100644 --- a/ports_module/cortex_a35_smp/ac6/example_build/tx/.cproject +++ b/ports_module/cortex_a35_smp/ac6/example_build/tx/.cproject @@ -1,242 +1,242 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_a35_smp/ac6/example_build/txm/.cproject b/ports_module/cortex_a35_smp/ac6/example_build/txm/.cproject index 870444d0..d0d395d6 100644 --- a/ports_module/cortex_a35_smp/ac6/example_build/txm/.cproject +++ b/ports_module/cortex_a35_smp/ac6/example_build/txm/.cproject @@ -1,238 +1,238 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_a35_smp/ac6/inc/tx_port.h b/ports_module/cortex_a35_smp/ac6/inc/tx_port.h index c26962fb..52693754 100644 --- a/ports_module/cortex_a35_smp/ac6/inc/tx_port.h +++ b/ports_module/cortex_a35_smp/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* symbol ULONG64_DEFINED, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -83,12 +75,12 @@ /* Define ThreadX SMP initialization macro. */ -#define TX_PORT_SPECIFIC_PRE_INITIALIZATION +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION /* Define ThreadX SMP pre-scheduler initialization. */ -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION /* Enable the inter-core interrupt logic. */ @@ -129,7 +121,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -190,19 +182,19 @@ typedef unsigned long long ALIGN_TYPE; #define TX_TIMER_THREAD_STACK_SIZE 4096 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY +#ifndef TX_TIMER_THREAD_PRIORITY #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX Cortex ARMv8 port. */ +/* Define various constants for the ThreadX Cortex ARMv8 port. */ #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ #define TX_INT_ENABLE 0x00 /* Enable IRQ & FIQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -260,7 +252,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -274,7 +266,7 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ #define TX_THREAD_EXTENSION_0 @@ -314,11 +306,11 @@ ULONG _tx_misra_time_stamp_get(VOID); VOID (*tx_timer_module_expiration_function)(ULONG id); -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -326,8 +318,8 @@ ULONG _tx_misra_time_stamp_get(VOID); tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -354,8 +346,8 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -367,7 +359,7 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the internal timer extension to also hold the thread pointer such that _tx_thread_timeout can figure out what thread timeout to process. */ - + #define TX_TIMER_INTERNAL_EXTENSION VOID *tx_timer_internal_thread_timeout_ptr; @@ -397,14 +389,14 @@ typedef struct TX_THREAD_SMP_PROTECT_STRUCT ULONG tx_thread_smp_protect_count; ULONG tx_thread_smp_protect_pad_0; ULONG tx_thread_smp_protect_pad_1; - ULONG tx_thread_smp_protect_pad_2; - ULONG tx_thread_smp_protect_pad_3; + ULONG tx_thread_smp_protect_pad_2; + ULONG tx_thread_smp_protect_pad_3; } TX_THREAD_SMP_PROTECT; -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -442,8 +434,8 @@ VOID tx_thread_fp_disable(VOID); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Modules Cortex-A35-SMP/AC6 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Modules Cortex-A35-SMP/AC6 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a35_smp/ac6/inc/txm_module_port.h b/ports_module/cortex_a35_smp/ac6/inc/txm_module_port.h index 6045dcc4..97930b4f 100644 --- a/ports_module/cortex_a35_smp/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_a35_smp/ac6/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,12 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -273,6 +268,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-A35/AC6 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-A35/AC6 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_a35_smp/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_a35_smp/ac6/module_lib/src/txm_module_initialize.S index c98ad715..2a04ce86 100644 --- a/ports_module/cortex_a35_smp/ac6/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_a35_smp/ac6/module_lib/src/txm_module_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_module/cortex_a35_smp/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_a35_smp/ac6/module_lib/src/txm_module_thread_shell_entry.c index 54b8824f..4559ac0e 100644 --- a/ports_module/cortex_a35_smp/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_a35_smp/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -80,12 +81,6 @@ ALIGN_TYPE (*_txm_module_kernel_call_dispatcher)(ULONG type /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_initialize_low_level.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_initialize_low_level.S index 5968a993..4a9a6402 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_initialize_low_level.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_context_restore.S index a590c2ae..6eec8596 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_context_save.S index 51aad705..1372dcb4 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { @@ -68,7 +63,7 @@ _tx_thread_context_save: /* Upon entry to this routine, it is assumed that IRQ/FIQ interrupts are locked - out, x29 (frame pointer), x30 (link register) are saved, we are in the proper EL, + out, x29 (frame pointer), x30 (link register) are saved, we are in the proper EL, and all other registers are intact. */ /* Check for a nested interrupt condition. */ @@ -149,7 +144,7 @@ __tx_thread_not_nested_save: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR x0, [x2, x1, LSL #3] // Pickup current thread pointer CMP x0, #0 // Is it NULL? - BEQ __tx_thread_idle_system_save // If so, interrupt occurred in + BEQ __tx_thread_idle_system_save // If so, interrupt occurred in // scheduling loop - nothing needs saving! /* Save minimal context of interrupted thread. */ @@ -217,7 +212,7 @@ __tx_thread_idle_system_save: /* Interrupt occurred in the scheduling loop. */ - /* Not much to do here, just adjust the stack pointer, and return to IRQ + /* Not much to do here, just adjust the stack pointer, and return to IRQ processing. */ #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY @@ -230,8 +225,8 @@ __tx_thread_idle_system_save: #endif ADD sp, sp, #48 // Recover saved registers - RET // Continue IRQ processing + RET // Continue IRQ processing // } -// } +// } diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_fp_disable.c b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_fp_disable.c index cb234851..61a93ab7 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_fp_disable.c +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,12 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { @@ -81,11 +76,11 @@ ULONG system_state; /* Make sure it is not NULL. */ if (thread_ptr != TX_NULL) { - + /* Thread is running... make sure the call is from the thread context. */ if (system_state == 0) { - + /* Yes, now set the FP enable flag to false in the TX_THREAD structure. */ thread_ptr -> tx_thread_fp_enable = TX_FALSE; } diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_fp_enable.c b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_fp_enable.c index c91b579c..2eb5324a 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_fp_enable.c +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,12 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { @@ -81,11 +76,11 @@ ULONG system_state; /* Make sure it is not NULL. */ if (thread_ptr != TX_NULL) { - + /* Thread is running... make sure the call is from the thread context. */ if (system_state == 0) { - + /* Yes, now setup the FP enable flag in the TX_THREAD structure. */ thread_ptr -> tx_thread_fp_enable = TX_TRUE; } diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_control.S index a60146cc..267c1b20 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_disable.S index 2c7d86d2..e6e5f545 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_restore.S index 44457d25..9d46f67d 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_schedule.S index 42bede20..f1739339 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_core_get.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_core_get.S index 600ecf28..a2e2bd3a 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_core_get.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,15 +53,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_core_preempt.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_core_preempt.S index 777a9981..898a8345 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_core_preempt.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_current_state_get.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_current_state_get.S index 994fe41b..5dad61bd 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_current_state_get.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_current_thread_get.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_current_thread_get.S index 8965f745..0664dde6 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_current_thread_get.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_initialize_wait.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_initialize_wait.S index 4be71ceb..90bbe372 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_initialize_wait.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function @@ -80,7 +75,7 @@ _tx_thread_smp_initialize_wait: ADDS x2, x2, x3, LSL #2 // Calculate CPU ID #endif - /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release + /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release flag. */ LDR w1, =0xF0F0F0F0 // Build TX_INITIALIZE_IN_PROGRESS flag @@ -91,7 +86,7 @@ wait_for_initialize: BNE wait_for_initialize // Not equal, just spin here /* Save the system stack pointer for this core. */ - + LDR x0, =_tx_thread_system_stack_ptr // Pickup address of system stack ptr MOV x1, sp // Pickup SP SUB x1, x1, #15 // @@ -100,30 +95,30 @@ wait_for_initialize: /* Pickup the release cores flag. */ - + LDR x4, =_tx_thread_smp_release_cores_flag // Build address of release cores flag -wait_for_release: +wait_for_release: LDR w0, [x4, #0] // Pickup the flag CMP w0, #0 // Is it set? BEQ wait_for_release // Wait for the flag to be set - + /* Core 0 has released this core. */ - + /* Clear this core's system state variable. */ - + MOV x0, #0 // Build clear value STR w0, [x3, x2, LSL #2] // Set the current system state for this core to zero - + /* Now wait for core 0 to finish it's initialization. */ - + core_0_wait_loop: LDR w0, [x3, #0] // Pickup the current system state for core 0 CMP w0, #0 // Is it 0? BNE core_0_wait_loop // No, keep waiting for core 0 to finish its initialization - + /* Initialization is complete, enter the scheduling loop! */ - - B _tx_thread_schedule // Enter the scheduling loop for this core + + B _tx_thread_schedule // Enter the scheduling loop for this core RET diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_low_level_initialize.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_low_level_initialize.S index dba9a06e..f3e95723 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_low_level_initialize.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protect.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protect.S index af49d3a0..4a48c56c 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protect.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -119,9 +107,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protection_wait_list_macros.h b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_time_get.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_time_get.S index aa24a4e4..002bf59d 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_time_get.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_unprotect.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_unprotect.S index a0bbf64e..4b5bd9a2 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_unprotect.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,18 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_stack_build.S index 5270aba3..880436ad 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_system_return.S index db9a145a..cad938c9 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { @@ -156,13 +151,13 @@ __tx_thread_dont_save_ts: STR x4, [x5, x8, LSL #3] // Clear current thread pointer /* Set ready bit in thread control block. */ - + MOV x3, #1 // Build ready value - STR w3, [x6, #260] // Make the thread ready - DMB ISH // - + STR w3, [x6, #260] // Make the thread ready + DMB ISH // + /* Now clear protection. It is assumed that protection is in force whenever this routine is called. */ - + LDR x3, =_tx_thread_smp_protection // Pickup address of protection structure LDR x1, =_tx_thread_preempt_disable // Build address to preempt disable flag STR w4, [x1, #0] // Clear preempt disable flag diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_timer_interrupt.S index cc5e12de..1319ea07 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,12 +58,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { @@ -175,8 +170,8 @@ __tx_timer_dont_activate: BL _tx_thread_time_slice // Call time-slice processing /* Release inter-core protection. */ - - MOV x0, x28 // Pass the previous status register back + + MOV x0, x28 // Pass the previous status register back BL _tx_thread_smp_unprotect // Release protection LDP x29, x30, [sp], #16 // Recover x29, x30 diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_a35_smp/ac6/module_manager/src/txm_module_manager_port_dispatch.c index dd472506..5cd9edd6 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/txm_module_manager_port_dispatch.c +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/txm_module_manager_port_dispatch.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,12 +60,6 @@ /* */ /* _txm_module_manager_kernel_dispatch */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) { diff --git a/ports_module/cortex_a35_smp/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_a35_smp/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index fc474b6e..5ff9a1e6 100644 --- a/ports_module/cortex_a35_smp/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_a35_smp/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_a35_smp/ac6/readme_threadx.txt b/ports_module/cortex_a35_smp/ac6/readme_threadx.txt index 044d2235..aadf9da2 100644 --- a/ports_module/cortex_a35_smp/ac6/readme_threadx.txt +++ b/ports_module/cortex_a35_smp/ac6/readme_threadx.txt @@ -1,19 +1,19 @@ - Microsoft's Azure RTOS ThreadX SMP for Cortex-A35 + Microsoft's Azure RTOS ThreadX SMP for Cortex-A35 Using the ARM Compiler 6 & DS 1. Import the ThreadX Projects -In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import -the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) into your DS workspace. 2. Building the ThreadX SMP run-time Library -Building the ThreadX SMP library is easy; simply select the Eclipse project file -"tx" and then select the build button. You should now observe the compilation -and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP +Building the ThreadX SMP library is easy; simply select the Eclipse project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP library file tx.a. @@ -33,29 +33,29 @@ ThreadX SMP demonstration. 4. System Initialization -The entry point in ThreadX SMP for the Cortex-A35 using AC6 tools is at label -"start64". This is defined within the AC6 compiler's startup code. In addition, -this is where all static and global pre-set C variable initialization processing +The entry point in ThreadX SMP for the Cortex-A35 using AC6 tools is at label +"start64". This is defined within the AC6 compiler's startup code. In addition, +this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX SMP tx_initialize_low_level.s file is responsible for determining the -first available RAM address for use by the application, which is supplied as the +The ThreadX SMP tx_initialize_low_level.s file is responsible for determining the +first available RAM address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 5. Register Usage and Stack Frames -The 64-bit AC6 compiler assumes that registers x0-x18 are scratch registers -for each function. All other registers used by a C function must be preserved -by the function. ThreadX SMP takes advantage of this in situations where a context -switch happens as a result of making a ThreadX SMP service call (which is itself a -C function). In such cases, the saved context of a thread is only the +The 64-bit AC6 compiler assumes that registers x0-x18 are scratch registers +for each function. All other registers used by a C function must be preserved +by the function. ThreadX SMP takes advantage of this in situations where a context +switch happens as a result of making a ThreadX SMP service call (which is itself a +C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -182,14 +182,14 @@ FP enabled and TX_THREAD.tx_thread_fp_enable == 1: 6. Improving Performance -The distribution version of ThreadX SMP is built without any compiler optimizations. -This makes it easy to debug because you can trace or set breakpoints inside of -ThreadX SMP itself. Of course, this costs some performance. To make it run faster, +The distribution version of ThreadX SMP is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX SMP itself. Of course, this costs some performance. To make it run faster, you can change the project settings to the desired compiler optimization level. -In addition, you can eliminate the ThreadX SMP basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX SMP basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling @@ -209,22 +209,22 @@ irq_handler: B _tx_thread_context_restore -By default, ThreadX SMP assumes EL3 level of execution. Running and taking exceptions in EL1 +By default, ThreadX SMP assumes EL3 level of execution. Running and taking exceptions in EL1 and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined. 8. ThreadX SMP Timer Interrupt -ThreadX SMP requires a periodic interrupt source to manage all time-slicing, thread sleeps, -timeouts, and application timers. Without such a timer interrupt source, these services -are not functional. However, all other ThreadX services are operational without a +ThreadX SMP requires a periodic interrupt source to manage all time-slicing, thread sleeps, +timeouts, and application timers. Without such a timer interrupt source, these services +are not functional. However, all other ThreadX services are operational without a periodic timer source. 9. ARM FP Support By default, FP support is disabled for each thread. If saving the context of the FP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the FP usage: void tx_thread_fp_enable(void); diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/.cproject b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/.cproject index 9ff6439f..8a8670cc 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/.cproject +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/.cproject @@ -1,246 +1,246 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.ld b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.ld index e9b12a82..1c6d45b5 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start @@ -194,7 +194,7 @@ SECTIONS . = . + 4 * 0x8000; __stack = .; } - + .handler_stack_limit (NOLOAD): { . = ALIGN(64); diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/.cproject b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/.cproject index 296685a7..50726e80 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/.cproject +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/.cproject @@ -1,184 +1,184 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/sample_threadx_module.ld b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/sample_threadx_module.ld index 042b59bf..d117a5df 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/sample_threadx_module.ld +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module/sample_threadx_module.ld @@ -110,7 +110,7 @@ SECTIONS KEEP (*(.got*)) . = ALIGN(4); _egot = .; - } + } __got_end__ = __got_load_start__ + SIZEOF(.got); __rodata_load_start__ = ALIGN(__got_end__ , 4); @@ -120,7 +120,7 @@ SECTIONS *(.rodata .rodata.* .gnu.linkonce.r.*) } __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); - + __code_size__ = __rodata_end__ - __FLASH_segment_start__; __fast_load_start__ = ALIGN(__rodata_end__ , 4); diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/.cproject index 572198b3..4d2057f9 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/.cproject +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/.cproject @@ -1,268 +1,268 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ld b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ld index e9b12a82..1c6d45b5 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ld +++ b/ports_module/cortex_a35_smp/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start @@ -194,7 +194,7 @@ SECTIONS . = . + 4 * 0x8000; __stack = .; } - + .handler_stack_limit (NOLOAD): { . = ALIGN(64); diff --git a/ports_module/cortex_a35_smp/gnu/example_build/tx/.cproject b/ports_module/cortex_a35_smp/gnu/example_build/tx/.cproject index a38608a6..765c3509 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/tx/.cproject +++ b/ports_module/cortex_a35_smp/gnu/example_build/tx/.cproject @@ -1,288 +1,288 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_a35_smp/gnu/example_build/txm/.cproject b/ports_module/cortex_a35_smp/gnu/example_build/txm/.cproject index 267cf889..88aec6be 100644 --- a/ports_module/cortex_a35_smp/gnu/example_build/txm/.cproject +++ b/ports_module/cortex_a35_smp/gnu/example_build/txm/.cproject @@ -1,198 +1,198 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_a35_smp/gnu/inc/tx_port.h b/ports_module/cortex_a35_smp/gnu/inc/tx_port.h index 578fd6f5..bc694706 100644 --- a/ports_module/cortex_a35_smp/gnu/inc/tx_port.h +++ b/ports_module/cortex_a35_smp/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* symbol ULONG64_DEFINED, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -83,12 +75,12 @@ /* Define ThreadX SMP initialization macro. */ -#define TX_PORT_SPECIFIC_PRE_INITIALIZATION +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION /* Define ThreadX SMP pre-scheduler initialization. */ -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION /* Enable the inter-core interrupt logic. */ @@ -129,7 +121,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -190,19 +182,19 @@ typedef unsigned long long ALIGN_TYPE; #define TX_TIMER_THREAD_STACK_SIZE 4096 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY +#ifndef TX_TIMER_THREAD_PRIORITY #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX Cortex ARMv8 port. */ +/* Define various constants for the ThreadX Cortex ARMv8 port. */ #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ #define TX_INT_ENABLE 0x00 /* Enable IRQ & FIQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -260,7 +252,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -274,7 +266,7 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ #define TX_THREAD_EXTENSION_0 @@ -314,11 +306,11 @@ ULONG _tx_misra_time_stamp_get(VOID); VOID (*tx_timer_module_expiration_function)(ULONG id); -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -326,8 +318,8 @@ ULONG _tx_misra_time_stamp_get(VOID); tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -354,8 +346,8 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -367,7 +359,7 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the internal timer extension to also hold the thread pointer such that _tx_thread_timeout can figure out what thread timeout to process. */ - + #define TX_TIMER_INTERNAL_EXTENSION VOID *tx_timer_internal_thread_timeout_ptr; @@ -397,14 +389,14 @@ typedef struct TX_THREAD_SMP_PROTECT_STRUCT ULONG tx_thread_smp_protect_count; ULONG tx_thread_smp_protect_pad_0; ULONG tx_thread_smp_protect_pad_1; - ULONG tx_thread_smp_protect_pad_2; - ULONG tx_thread_smp_protect_pad_3; + ULONG tx_thread_smp_protect_pad_2; + ULONG tx_thread_smp_protect_pad_3; } TX_THREAD_SMP_PROTECT; -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -442,8 +434,8 @@ VOID tx_thread_fp_disable(VOID); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Modules Cortex-A35-SMP/GNU Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Modules Cortex-A35-SMP/GNU Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a35_smp/gnu/inc/txm_module_port.h b/ports_module/cortex_a35_smp/gnu/inc/txm_module_port.h index 5eeab1c5..99e7d056 100644 --- a/ports_module/cortex_a35_smp/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_a35_smp/gnu/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,12 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -273,6 +268,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-A35/GNU Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-A35/GNU Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_a35_smp/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_a35_smp/gnu/module_lib/src/txm_module_thread_shell_entry.c index 914d4292..ba56d9e3 100644 --- a/ports_module/cortex_a35_smp/gnu/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_a35_smp/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -80,12 +81,6 @@ ALIGN_TYPE (*_txm_module_kernel_call_dispatcher)(ULONG type /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_initialize_low_level.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_initialize_low_level.S index 68565f3f..be81c11d 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_initialize_low_level.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_context_restore.S index 7ab0f5dc..b2b9240f 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_context_save.S index a7c8a37d..ffb6e1d5 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { @@ -68,7 +63,7 @@ _tx_thread_context_save: /* Upon entry to this routine, it is assumed that IRQ/FIQ interrupts are locked - out, x29 (frame pointer), x30 (link register) are saved, we are in the proper EL, + out, x29 (frame pointer), x30 (link register) are saved, we are in the proper EL, and all other registers are intact. */ /* Check for a nested interrupt condition. */ @@ -149,7 +144,7 @@ __tx_thread_not_nested_save: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR x0, [x2, x1, LSL #3] // Pickup current thread pointer CMP x0, #0 // Is it NULL? - BEQ __tx_thread_idle_system_save // If so, interrupt occurred in + BEQ __tx_thread_idle_system_save // If so, interrupt occurred in // scheduling loop - nothing needs saving! /* Save minimal context of interrupted thread. */ @@ -217,7 +212,7 @@ __tx_thread_idle_system_save: /* Interrupt occurred in the scheduling loop. */ - /* Not much to do here, just adjust the stack pointer, and return to IRQ + /* Not much to do here, just adjust the stack pointer, and return to IRQ processing. */ #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY @@ -230,8 +225,8 @@ __tx_thread_idle_system_save: #endif ADD sp, sp, #48 // Recover saved registers - RET // Continue IRQ processing + RET // Continue IRQ processing // } -// } +// } diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_fp_disable.c b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_fp_disable.c index 6ca98daf..c77c270d 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_fp_disable.c +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,12 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { @@ -81,11 +76,11 @@ ULONG system_state; /* Make sure it is not NULL. */ if (thread_ptr != TX_NULL) { - + /* Thread is running... make sure the call is from the thread context. */ if (system_state == 0) { - + /* Yes, now set the FP enable flag to false in the TX_THREAD structure. */ thread_ptr -> tx_thread_fp_enable = TX_FALSE; } diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_fp_enable.c b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_fp_enable.c index e21e5478..803ed053 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_fp_enable.c +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,12 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { @@ -81,11 +76,11 @@ ULONG system_state; /* Make sure it is not NULL. */ if (thread_ptr != TX_NULL) { - + /* Thread is running... make sure the call is from the thread context. */ if (system_state == 0) { - + /* Yes, now setup the FP enable flag in the TX_THREAD structure. */ thread_ptr -> tx_thread_fp_enable = TX_TRUE; } diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_control.S index 273e6c22..995f66c8 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_disable.S index 73cc0a09..f0c10827 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_restore.S index 3d09ad89..39616622 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_schedule.S index 84f4413e..7b8f660f 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_core_get.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_core_get.S index 0879bea8..936d3e86 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_core_get.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,15 +53,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_core_preempt.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_core_preempt.S index 62888b74..2e78a55d 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_core_preempt.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,12 +59,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_current_state_get.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_current_state_get.S index 25cf7a37..d741f8dc 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_current_state_get.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_current_thread_get.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_current_thread_get.S index 63921407..7c6c1be9 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_current_thread_get.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_initialize_wait.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_initialize_wait.S index 2b518481..ef63c852 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_initialize_wait.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function @@ -80,7 +75,7 @@ _tx_thread_smp_initialize_wait: ADDS x2, x2, x3, LSL #2 // Calculate CPU ID #endif - /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release + /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release flag. */ LDR w1, =0xF0F0F0F0 // Build TX_INITIALIZE_IN_PROGRESS flag @@ -91,7 +86,7 @@ wait_for_initialize: BNE wait_for_initialize // Not equal, just spin here /* Save the system stack pointer for this core. */ - + LDR x0, =_tx_thread_system_stack_ptr // Pickup address of system stack ptr MOV x1, sp // Pickup SP SUB x1, x1, #15 // @@ -100,30 +95,30 @@ wait_for_initialize: /* Pickup the release cores flag. */ - + LDR x4, =_tx_thread_smp_release_cores_flag // Build address of release cores flag -wait_for_release: +wait_for_release: LDR w0, [x4, #0] // Pickup the flag CMP w0, #0 // Is it set? BEQ wait_for_release // Wait for the flag to be set - + /* Core 0 has released this core. */ - + /* Clear this core's system state variable. */ - + MOV x0, #0 // Build clear value STR w0, [x3, x2, LSL #2] // Set the current system state for this core to zero - + /* Now wait for core 0 to finish it's initialization. */ - + core_0_wait_loop: LDR w0, [x3, #0] // Pickup the current system state for core 0 CMP w0, #0 // Is it 0? BNE core_0_wait_loop // No, keep waiting for core 0 to finish its initialization - + /* Initialization is complete, enter the scheduling loop! */ - - B _tx_thread_schedule // Enter the scheduling loop for this core + + B _tx_thread_schedule // Enter the scheduling loop for this core RET diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_low_level_initialize.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_low_level_initialize.S index 8548b723..9a537e87 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_low_level_initialize.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protect.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protect.S index b9a694a9..ebac9e58 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protect.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -119,9 +107,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protection_wait_list_macros.h b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_time_get.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_time_get.S index fdfbfa83..8fbc98f4 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_time_get.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_unprotect.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_unprotect.S index 1ef48e74..3125dab8 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_unprotect.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,18 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_stack_build.S index efb65fa6..0f687fee 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_system_return.S index 9e184023..a5e5f985 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { @@ -156,13 +151,13 @@ __tx_thread_dont_save_ts: STR x4, [x5, x8, LSL #3] // Clear current thread pointer /* Set ready bit in thread control block. */ - + MOV x3, #1 // Build ready value - STR w3, [x6, #260] // Make the thread ready - DMB ISH // - + STR w3, [x6, #260] // Make the thread ready + DMB ISH // + /* Now clear protection. It is assumed that protection is in force whenever this routine is called. */ - + LDR x3, =_tx_thread_smp_protection // Pickup address of protection structure LDR x1, =_tx_thread_preempt_disable // Build address to preempt disable flag STR w4, [x1, #0] // Clear preempt disable flag diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_timer_interrupt.S index d774f388..ba8e8c59 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,12 +58,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { @@ -175,8 +170,8 @@ __tx_timer_dont_activate: BL _tx_thread_time_slice // Call time-slice processing /* Release inter-core protection. */ - - MOV x0, x28 // Pass the previous status register back + + MOV x0, x28 // Pass the previous status register back BL _tx_thread_smp_unprotect // Release protection LDP x29, x30, [sp], #16 // Recover x29, x30 diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_a35_smp/gnu/module_manager/src/txm_module_manager_port_dispatch.c index 2a399a17..5cd9edd6 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/txm_module_manager_port_dispatch.c +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/txm_module_manager_port_dispatch.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,12 +60,6 @@ /* */ /* _txm_module_manager_kernel_dispatch */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) { @@ -79,6 +74,6 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; break; } } - + return(return_value); } diff --git a/ports_module/cortex_a35_smp/gnu/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_a35_smp/gnu/module_manager/src/txm_module_manager_thread_stack_build.S index 835fef69..43d718e8 100644 --- a/ports_module/cortex_a35_smp/gnu/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_a35_smp/gnu/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Andres Mlinar Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_a35_smp/gnu/readme_threadx.txt b/ports_module/cortex_a35_smp/gnu/readme_threadx.txt index de17c068..dca3b84c 100644 --- a/ports_module/cortex_a35_smp/gnu/readme_threadx.txt +++ b/ports_module/cortex_a35_smp/gnu/readme_threadx.txt @@ -4,16 +4,16 @@ 1. Import the ThreadX Projects -In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import -the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) into your DS workspace. 2. Building the ThreadX SMP run-time Library -Building the ThreadX SMP library is easy; simply select the Eclipse project file -"tx" and then select the build button. You should now observe the compilation -and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP +Building the ThreadX SMP library is easy; simply select the Eclipse project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP library file tx.a. @@ -33,29 +33,29 @@ ThreadX SMP demonstration. 4. System Initialization -The entry point in ThreadX SMP for the Cortex-A35 using GCC tools is at label -"start64". This is defined within the GCC compiler's startup code. In addition, -this is where all static and global pre-set C variable initialization processing +The entry point in ThreadX SMP for the Cortex-A35 using GCC tools is at label +"start64". This is defined within the GCC compiler's startup code. In addition, +this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX SMP tx_initialize_low_level.s file is responsible for determining the -first available RAM address for use by the application, which is supplied as the +The ThreadX SMP tx_initialize_low_level.s file is responsible for determining the +first available RAM address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 5. Register Usage and Stack Frames -The 64-bit GCC compiler assumes that registers x0-x18 are scratch registers -for each function. All other registers used by a C function must be preserved -by the function. ThreadX SMP takes advantage of this in situations where a context -switch happens as a result of making a ThreadX SMP service call (which is itself a -C function). In such cases, the saved context of a thread is only the +The 64-bit GCC compiler assumes that registers x0-x18 are scratch registers +for each function. All other registers used by a C function must be preserved +by the function. ThreadX SMP takes advantage of this in situations where a context +switch happens as a result of making a ThreadX SMP service call (which is itself a +C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -182,14 +182,14 @@ FP enabled and TX_THREAD.tx_thread_fp_enable == 1: 6. Improving Performance -The distribution version of ThreadX SMP is built without any compiler optimizations. -This makes it easy to debug because you can trace or set breakpoints inside of -ThreadX SMP itself. Of course, this costs some performance. To make it run faster, +The distribution version of ThreadX SMP is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX SMP itself. Of course, this costs some performance. To make it run faster, you can change the project settings to the desired compiler optimization level. -In addition, you can eliminate the ThreadX SMP basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX SMP basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling @@ -209,22 +209,22 @@ irq_handler: B _tx_thread_context_restore -By default, ThreadX SMP assumes EL3 level of execution. Running and taking exceptions in EL1 +By default, ThreadX SMP assumes EL3 level of execution. Running and taking exceptions in EL1 and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined. 8. ThreadX SMP Timer Interrupt -ThreadX SMP requires a periodic interrupt source to manage all time-slicing, thread sleeps, -timeouts, and application timers. Without such a timer interrupt source, these services -are not functional. However, all other ThreadX services are operational without a +ThreadX SMP requires a periodic interrupt source to manage all time-slicing, thread sleeps, +timeouts, and application timers. Without such a timer interrupt source, these services +are not functional. However, all other ThreadX services are operational without a periodic timer source. 9. ARM FP Support By default, FP support is disabled for each thread. If saving the context of the FP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the FP usage: void tx_thread_fp_enable(void); diff --git a/ports_module/cortex_a7/ac5/example_build/sample_threadx_module.c b/ports_module/cortex_a7/ac5/example_build/sample_threadx_module.c index fce2a3fa..f9ed56eb 100644 --- a/ports_module/cortex_a7/ac5/example_build/sample_threadx_module.c +++ b/ports_module/cortex_a7/ac5/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -101,7 +101,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MMU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void *) &thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void *) &thread_1, sizeof(TX_THREAD)); @@ -117,7 +117,7 @@ CHAR *pointer; txm_module_object_allocate((void *) &event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void *) &byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void *) &block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -129,25 +129,25 @@ CHAR *pointer; /* Create the main thread. */ tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ @@ -156,14 +156,14 @@ CHAR *pointer; /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -172,7 +172,7 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ @@ -180,14 +180,14 @@ CHAR *pointer; /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -237,7 +237,7 @@ UINT status; *(ULONG *) 0x90000000 = 0xdeadbeef; *(ULONG *) 0x90000FFC = 0xfeed0add; *(ULONG *) 0x90001000 = 0xfedcba01; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -247,7 +247,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -300,11 +300,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -363,7 +363,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -416,7 +416,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_a7/ac5/example_build/sample_threadx_module_manager.c b/ports_module/cortex_a7/ac5/example_build/sample_threadx_module_manager.c index 8b17e34a..ac3bbeb5 100644 --- a/ports_module/cortex_a7/ac5/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_a7/ac5/example_build/sample_threadx_module_manager.c @@ -1,4 +1,4 @@ -/* Small demonstration of the ThreadX module manager. This demonstration assumes the program +/* Small demonstration of the ThreadX module manager. This demonstration assumes the program manager is loaded at 0 and that RAM addresses 0x200000 through 0x400000 are available for use. */ @@ -45,7 +45,7 @@ VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) int main() { - + /* Enter the ThreadX kernel. */ tx_kernel_enter(); } @@ -57,8 +57,8 @@ void tx_application_define(void *first_unused_memory) { /* Create the module manager thread. */ - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - first_unused_memory, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + first_unused_memory, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); } @@ -71,46 +71,46 @@ void module_manager_entry(ULONG thread_input) /* Initialize the module manager. */ txm_module_manager_initialize((VOID *) module_data_area, MODULE_DATA_SIZE); - + /* Create a pool for module objects. */ txm_module_manager_object_pool_create(object_memory, sizeof(object_memory)); - + /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Initialize MMU. */ txm_module_manager_mm_initialize(); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module1, "my module1", (VOID *) module_code); - + /* Load a second instance of the module. */ //txm_module_manager_in_place_load(&my_module2, "my module2", (VOID *) module_code); - + /* Enable shared memory regions for one module. */ //txm_module_manager_external_memory_enable(&my_module2, (void*)0x90000000, 0x010000, 0x3F); - + /* Start the modules. */ txm_module_manager_start(&my_module1); //txm_module_manager_start(&my_module2); - + /* Sleep for a while and let the modules run.... */ tx_thread_sleep(50); - + /* Thread 0 in module1 should be terminated due to violating the MMU. */ - + /* Stop the modules. */ txm_module_manager_stop(&my_module1); txm_module_manager_stop(&my_module2); - + /* Unload the modules. */ txm_module_manager_unload(&my_module1); txm_module_manager_unload(&my_module2); - + /* Reload the modules. */ txm_module_manager_in_place_load(&my_module2, "my module2", (VOID *) module_code); txm_module_manager_in_place_load(&my_module1, "my module1", (VOID *) module_code); - + /* Give both modules shared memory. */ txm_module_manager_external_memory_enable(&my_module2, (void*)0x90000000, 0x010000, 0x3F); txm_module_manager_external_memory_enable(&my_module1, (void*)0x90000000, 0x010000, 0x3F); @@ -118,7 +118,7 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module2); txm_module_manager_start(&my_module1); - + /* Now just spin... */ while(1) { diff --git a/ports_module/cortex_a7/ac5/example_build/scatter.scat b/ports_module/cortex_a7/ac5/example_build/scatter.scat index a9e2d1d8..d30f6109 100644 --- a/ports_module/cortex_a7/ac5/example_build/scatter.scat +++ b/ports_module/cortex_a7/ac5/example_build/scatter.scat @@ -6,7 +6,7 @@ ; Using a scatter-file with ARM_LIB_STACKHEAP eliminates the need to set stack-limit or heap-base in the debugger. -SDRAM 0x80000000 +SDRAM 0x80000000 { VECTORS +0 { diff --git a/ports_module/cortex_a7/ac5/example_build/tx_initialize_low_level.s b/ports_module/cortex_a7/ac5/example_build/tx_initialize_low_level.s index d9150dff..9bdd7ba4 100644 --- a/ports_module/cortex_a7/ac5/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_a7/ac5/example_build/tx_initialize_low_level.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Initialize */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -109,45 +109,39 @@ Reset_Vector ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-A7/MMU/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-A7/MMU/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -335,7 +329,7 @@ GIC1_DIST_INTERFACE_BASE EQU 0x2C001000 ; ; ;/* Define initial heap/stack routine for the ARM RealView (and ADS) startup code. This -; routine will set the initial stack to use the ThreadX IRQ & FIQ & +; routine will set the initial stack to use the ThreadX IRQ & FIQ & ; (optionally SYS) stack areas. */ ; EXPORT __user_initial_stackheap @@ -375,7 +369,7 @@ __tx_reserved_handler ; ; EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -383,15 +377,15 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; ; BL _tx_timer_interrupt ; Timer interrupt handler - + ; clear timer interrupt ldr r0, =0x1C110000 eor r1, r1, r1 @@ -399,11 +393,11 @@ __tx_irq_processing_return _tx_not_timer_interrupt ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ IF :DEF:TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -413,7 +407,7 @@ _tx_not_timer_interrupt ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ IF :DEF:TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -429,28 +423,28 @@ _tx_not_timer_interrupt __tx_example_vectored_irq_handler ; ; -; /* Save initial context and call context save to prepare for +; /* Save initial context and call context save to prepare for ; vectored ISR execution. */ ; ; STMDB sp!, {r0-r3} ; Save some scratch registers ; MRS r0, SPSR ; Pickup saved SPSR -; SUB lr, lr, #4 ; Adjust point of interrupt +; SUB lr, lr, #4 ; Adjust point of interrupt ; STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers ; BL _tx_thread_vectored_context_save ; Vectored context save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ; IF :DEF:TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_start @@ -459,7 +453,7 @@ __tx_example_vectored_irq_handler ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ; IF :DEF:TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_end @@ -481,11 +475,11 @@ __tx_fiq_processing_return ; /* At this point execution is still in the FIQ mode. The CPSR, point of ; interrupt, and all C scratch registers are available for use. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start ; from FIQ mode with interrupts disabled. This routine switches to the -; system mode and returns with FIQ interrupts enabled. +; system mode and returns with FIQ interrupts enabled. ; -; NOTE: It is very important to ensure all FIQ interrupts are cleared +; NOTE: It is very important to ensure all FIQ interrupts are cleared ; prior to enabling nested FIQ interrupts. */ IF :DEF:TX_ENABLE_FIQ_NESTING BL _tx_thread_fiq_nesting_start @@ -509,43 +503,43 @@ __tx_fiq_handler B __tx_fiq_handler ; FIQ interrupt handler ENDIF - - -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* __tx_prefetch_handler & __tx_abort_handler Cortex-A7/MMU/AC5 */ + + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* __tx_prefetch_handler & __tx_abort_handler Cortex-A7/MMU/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function handles MMU exceptions and fills the */ -;/* _txm_module_manager_memory_fault_info struct. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _txm_module_manager_memory_fault_handler */ -;/* _tx_execution_thread_exit */ -;/* _tx_thread_schedule */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* MMU exceptions */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function handles MMU exceptions and fills the */ +;/* _txm_module_manager_memory_fault_info struct. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _txm_module_manager_memory_fault_handler */ +;/* _tx_execution_thread_exit */ +;/* _tx_thread_schedule */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* MMU exceptions */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 Scott Larson Initial Version 6.1 */ @@ -561,7 +555,7 @@ __tx_fiq_handler EXTERN _txm_module_manager_memory_fault_handler EXTERN _tx_execution_thread_exit EXTERN _tx_thread_schedule - + EXPORT __tx_prefetch_handler EXPORT __tx_abort_handler __tx_prefetch_handler @@ -589,7 +583,7 @@ __tx_abort_handler STR r0, [r3, #16] ; Save IFAR MRC p15, 0, r0, c5, c0, 1 ; Read IFSR STR r0, [r3, #20] ; Save IFSR - + ; Save registers r0-r12 POP {r0-r2} STR r0, [r3, #28] ; Save r0 @@ -606,7 +600,7 @@ __tx_abort_handler STR r10,[r3, #68] ; Save r10 STR r11,[r3, #72] ; Save r11 STR r12,[r3, #76] ; Save r12 - + CPS #SYS_MODE ; Enter SYS mode MOV r0, lr ; Pickup lr MOV r1, sp ; Pickup sp @@ -618,7 +612,7 @@ __tx_abort_handler ORR r0, r0, #SYS_MODE ; Return into SYS mode BIC r0, r0, #THUMB_MASK ; Clear THUMB mode MSR SPSR_c, r0 ; Save SPSR - + ; Call memory manager fault handler BL _txm_module_manager_memory_fault_handler @@ -633,11 +627,11 @@ __tx_abort_handler LDR r1, [r0] ; Pickup system state SUB r1, r1, #1 ; Decrement STR r1, [r0] ; Store new system state - + MOV r1, #0 ; Build NULL value LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer STR r1, [r0] ; Clear current thread pointer - + ; Return from exception LDR lr, =_tx_thread_schedule ; Load scheduler address MOVS pc, lr ; Return to scheduler diff --git a/ports_module/cortex_a7/ac5/example_build/txm_module_preamble.s b/ports_module/cortex_a7/ac5/example_build/txm_module_preamble.s index 168dad31..953a1d62 100644 --- a/ports_module/cortex_a7/ac5/example_build/txm_module_preamble.s +++ b/ports_module/cortex_a7/ac5/example_build/txm_module_preamble.s @@ -34,7 +34,7 @@ __txm_module_preamble ; 1 -> User mode execution (MMU protection) DCD _txm_module_thread_shell_entry - . + . ; Module Shell Entry Point DCD demo_module_start - . + . ; Module Start Thread Entry Point - DCD 0 ; Module Stop Thread Entry Point + DCD 0 ; Module Stop Thread Entry Point DCD 1 ; Module Start/Stop Thread Priority DCD 2046 ; Module Start/Stop Thread Stack Size DCD _txm_module_callback_request_thread_entry - . + . ; Module Callback Thread Entry diff --git a/ports_module/cortex_a7/ac5/inc/tx_port.h b/ports_module/cortex_a7/ac5/inc/tx_port.h index 1d507b66..fd061c95 100644 --- a/ports_module/cortex_a7/ac5/inc/tx_port.h +++ b/ports_module/cortex_a7/ac5/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Cortex-A7/AC5 */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A7/AC5 */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -75,7 +67,7 @@ #include -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -111,12 +103,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -126,8 +118,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -174,7 +166,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -186,11 +178,11 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ VOID *tx_thread_module_instance_ptr; \ VOID *tx_thread_module_entry_info_ptr; \ @@ -204,7 +196,7 @@ typedef unsigned short USHORT; VOID *tx_thread_module_stack_end; \ ULONG tx_thread_module_stack_size; \ VOID *tx_thread_module_reserved; -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -224,11 +216,11 @@ typedef unsigned short USHORT; VOID (*tx_timer_module_expiration_function)(ULONG id); -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -236,8 +228,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -264,21 +256,21 @@ typedef unsigned short USHORT; #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef __thumb - + #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (ULONG) __clz((unsigned int) m); \ - b = 31 - b; + b = 31 - b; #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -298,7 +290,7 @@ typedef unsigned short USHORT; { \ __enable_irq(); \ __enable_fiq(); \ - } + } #else @@ -307,7 +299,7 @@ typedef unsigned short USHORT; #define TX_RESTORE if (!interrupt_save_disabled) \ { \ __enable_irq(); \ - } + } #endif #else @@ -343,8 +335,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-A7/AC5 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A7/AC5 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a7/ac5/inc/txm_module_port.h b/ports_module/cortex_a7/ac5/inc/txm_module_port.h index 2f930ec9..1102a377 100644 --- a/ports_module/cortex_a7/ac5/inc/txm_module_port.h +++ b/ports_module/cortex_a7/ac5/inc/txm_module_port.h @@ -1,52 +1,47 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Interface (API) */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Interface (API) */ +/** */ +/**************************************************************************/ +/**************************************************************************/ -/**************************************************************************/ -/* */ -/* APPLICATION INTERFACE DEFINITION RELEASE */ -/* */ -/* txm_module_port.h Cortex-A7/MMU/AC5 */ +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-A7/MMU/AC5 */ /* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This file defines the basic module constants, interface structures, */ -/* and function prototypes. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ /* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H #define TXM_MODULE_PORT_H -/* It is assumed that the base ThreadX tx_port.h file has been modified to add the +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the following extensions to the ThreadX thread control block (this code should replace the corresponding macro define in tx_port.h): @@ -86,10 +81,10 @@ The following extensions must also be defined in tx_port.h: #endif /* Defined, this option enables the MMU hardware and requires memory protected - module objects to be allocated from the module manager object pool. - If this is undefined, module objects can be created in the module's data area - or in the module manager object pool. If this is not defined (MMU hardware - is disabled), a module requiring memory protection will not run (the load + module objects to be allocated from the module manager object pool. + If this is undefined, module objects can be created in the module's data area + or in the module manager object pool. If this is not defined (MMU hardware + is disabled), a module requiring memory protection will not run (the load functions will return a TXM_MODULE_INVALID_PROPERTIES error). Default setting for this value is defined. */ #define TXM_MODULE_MEMORY_PROTECTION_ENABLED @@ -296,7 +291,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; /* Define the macro to check the stack available in dispatch. */ -#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE +#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE /* Define the macro to check the code alignment. */ @@ -406,7 +401,7 @@ UINT _txm_module_manager_inside_data_check(ULONG pointer); #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-A7/MMU/AC5 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-A7/MMU/AC5 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_a7/ac5/module_lib/src/txm_module_initialize.s b/ports_module/cortex_a7/ac5/module_lib/src/txm_module_initialize.s index cb838377..1aff12b8 100644 --- a/ports_module/cortex_a7/ac5/module_lib/src/txm_module_initialize.s +++ b/ports_module/cortex_a7/ac5/module_lib/src/txm_module_initialize.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Module */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -31,43 +31,37 @@ ; ; IMPORT __scatterload - + AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _txm_module_initialize Cortex-A7/MMU/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_initialize Cortex-A7/MMU/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function initializes the module c runtime. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* __scatterload Initialize C runtime */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _txm_module_thread_shell_entry Start module thread */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* This function initializes the module c runtime. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* __scatterload Initialize C runtime */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _txm_module_thread_shell_entry Start module thread */ ;/* */ ;/**************************************************************************/ ;VOID _txm_module_initialize(VOID) @@ -75,16 +69,16 @@ EXPORT _txm_module_initialize _txm_module_initialize PUSH {r4-r12,lr} ; Save dregs and LR - + B __scatterload ; Call ARM func to initialize variables ;/* Override __rt_exit function. */ EXPORT __rt_exit __rt_exit - + POP {r4-r12,lr} ; Restore dregs and LR BX lr ; Return to caller ;} - + END diff --git a/ports_module/cortex_a7/ac5/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_a7/ac5/module_lib/src/txm_module_thread_shell_entry.c index f04a1808..4925fe47 100644 --- a/ports_module/cortex_a7/ac5/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_a7/ac5/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -87,12 +88,6 @@ VOID __user_setup_stackheap(VOID){return;} /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_context_restore.s index 92a2311a..515f2820 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_context_restore.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -56,44 +56,38 @@ DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore Cortex-A7/MMU/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-A7/MMU/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -123,13 +117,13 @@ _tx_thread_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3, #0] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3, #0] ; Store the counter + STR r2, [r3, #0] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -189,10 +183,10 @@ __tx_thread_preempt_restore LDMIA sp!, {r0-r3} ; Recover r0-r3 CPS #SYS_MODE ; Enter SYS mode STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack - + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer - + IF {TARGET_FPU_VFP} = {TRUE} LDR r2, [r0, #144] ; Pickup the VFP enabled flag CMP r2, #0 ; Is the VFP enabled? @@ -203,7 +197,7 @@ __tx_thread_preempt_restore VSTMDB sp!, {D0-D15} ; Save D0-D15 _tx_skip_irq_vfp_save ENDIF - + MOV r3, #1 ; Build interrupt stack type STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR STR sp, [r0, #8] ; Save stack pointer in thread control diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_context_save.s index 3993d9f0..7c7be45c 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,43 +39,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -90,7 +84,7 @@ _tx_thread_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers IF :DEF:TX_ENABLE_FIQ_SUPPORT CPSID if ; Disable FIQ interrupts ENDIF @@ -108,7 +102,7 @@ _tx_thread_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -124,7 +118,7 @@ _tx_thread_context_save POP {lr} ; Recover ISR lr ENDIF - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; __tx_thread_not_nested_save ; } @@ -138,13 +132,13 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} ; Store other registers ; ; /* Save the current stack pointer in the thread's control block. */ @@ -164,7 +158,7 @@ __tx_thread_not_nested_save POP {lr} ; Recover ISR lr ENDIF - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ; else @@ -174,7 +168,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit @@ -189,7 +183,7 @@ __tx_thread_idle_system_save ENDIF ADD sp, sp, #16 ; Recover saved registers - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ;} diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_context_restore.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_context_restore.s index 44233091..0258ead2 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_context_restore.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -32,7 +32,7 @@ ; SVC_MODE EQU 0xD3 ; SVC mode FIQ_MODE EQU 0xD1 ; FIQ mode -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; ; @@ -50,44 +50,38 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_restore Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the fiq interrupt context when processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* FIQ ISR Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) @@ -113,13 +107,13 @@ _tx_thread_fiq_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3] ; Store the counter + STR r2, [r3] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -163,7 +157,7 @@ __tx_thread_fiq_no_preempt_restore ; /* Restore interrupted thread or ISR. */ ; ; /* Pickup the saved stack pointer. */ -; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; ; ; /* Recover the saved context and return to the point of interrupt. */ ; @@ -208,7 +202,7 @@ _tx_skip_fiq_vfp_save MOV r3, #1 ; Build interrupt stack type STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR STR sp, [r0, #8] ; Save stack pointer in thread control - ; block + ; block ; ; /* Save the remaining time-slice and disable it. */ ; if (_tx_timer_time_slice) @@ -220,7 +214,7 @@ _tx_skip_fiq_vfp_save BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it ; ; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; -; _tx_timer_time_slice = 0; +; _tx_timer_time_slice = 0; ; STR r2, [r0, #24] ; Save thread's time-slice MOV r2, #0 ; Clear value diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_context_save.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_context_save.s index eb969c1d..7be8a46f 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_context_save.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,43 +39,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_save Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) @@ -90,7 +84,7 @@ _tx_thread_fiq_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state CMP r2, #0 ; Is this the first interrupt? @@ -105,7 +99,7 @@ _tx_thread_fiq_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -121,38 +115,38 @@ _tx_thread_fiq_context_save POP {lr} ; Recover ISR lr ENDIF - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; __tx_thread_fiq_not_nested_save -; } +; } ; ; /* Otherwise, not nested, check to see if a thread was running. */ ; else if (_tx_thread_current_ptr) -; { +; { ; ADD r2, r2, #1 ; Increment the interrupt counter STR r2, [r3] ; Store it back in the variable LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in -; ; scheduling loop - nothing needs saving! + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, lr} ; Store other registers, Note that we don't -; ; need to save sl and ip since FIQ has -; ; copies of these registers. Nested +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested ; ; interrupt processing does need to save ; ; these registers. ; ; /* Save the current stack pointer in the thread's control block. */ -; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; ; ; /* Switch to the system stack. */ -; sp = _tx_thread_system_stack_ptr; +; sp = _tx_thread_system_stack_ptr; ; MOV r10, #0 ; Clear stack limit @@ -165,7 +159,7 @@ __tx_thread_fiq_not_nested_save POP {lr} ; Recover ISR lr ENDIF - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } ; else @@ -185,18 +179,18 @@ __tx_thread_fiq_idle_system_save ENDIF ; ; /* Not much to do here, save the current SPSR and LR for possible -; use in IRQ interrupted in idle system conditions, and return to +; use in IRQ interrupted in idle system conditions, and return to ; FIQ interrupt processing. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, lr} ; Store other registers that will get used -; ; or stripped off the stack in context -; ; restore - B __tx_fiq_processing_return ; Continue FIQ processing +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } -;} +;} ; END diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_nesting_end.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_nesting_end.s index 9062160c..8b2fc70b 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_nesting_end.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,56 +34,50 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_end Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ -;/* processing from system mode back to FIQ mode prior to the ISR */ -;/* calling _tx_thread_fiq_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with FIQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) @@ -94,7 +88,7 @@ _tx_thread_fiq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_c, r0 ; Disable interrupts - LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_nesting_start.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_nesting_start.s index a1456bd1..a94ff890 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_nesting_start.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_fiq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_start Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ -;/* processing to the system mode so nested FIQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with FIQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_interrupt_control.s index 0d422e49..c9d95a58 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,42 +36,36 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_interrupt_disable.s index 5653faf4..de174cb1 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_interrupt_disable.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,41 +29,35 @@ ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(void) @@ -80,7 +74,7 @@ _tx_thread_interrupt_disable IF :DEF:TX_ENABLE_FIQ_SUPPORT CPSID if ; Disable IRQ and FIQ ELSE - CPSID i ; Disable IRQ + CPSID i ; Disable IRQ ENDIF IF {INTER} = {TRUE} diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_interrupt_restore.s index e9f15cc6..c2c32842 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_interrupt_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,42 +29,36 @@ ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function is responsible for restoring interrupts to the state */ ;/* returned by a previous _tx_thread_interrupt_disable call. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_irq_nesting_end.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_irq_nesting_end.s index f458cb21..73a88636 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_irq_nesting_end.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_irq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,56 +34,50 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_end Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -;/* processing from system mode back to IRQ mode prior to the ISR */ -;/* calling _tx_thread_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) @@ -94,7 +88,7 @@ _tx_thread_irq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_c, r0 ; Disable interrupts - LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_irq_nesting_start.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_irq_nesting_start.s index 2f1814f8..d4c1ca06 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_irq_nesting_start.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_irq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_start Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_context_save has been called and switches the IRQ */ -;/* processing to the system mode so nested IRQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_schedule.s index be7a2ca7..994c6964 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_schedule.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -36,7 +36,7 @@ IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY IMPORT _tx_execution_thread_enter ENDIF - + IRQ_MODE EQU 0xD2 ; IRQ mode USR_MODE EQU 0x10 ; USR mode SVC_MODE EQU 0x13 ; SVC mode @@ -48,7 +48,7 @@ ENABLE_INTS EQU 0xC0 ; IRQ & FIQ Interrupts enabled mask ENABLE_INTS EQU 0x80 ; IRQ Interrupts enabled mask ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask THUMB_MASK EQU 0x20 ; Thumb bit mask IMPORT _txm_system_mode_enter @@ -58,52 +58,46 @@ THUMB_MASK EQU 0x20 ; Thumb bit mask ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule Cortex-A7/MMU/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-A7/MMU/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) ;{ EXPORT _tx_thread_schedule _tx_thread_schedule - + ; Enter the scheduler. SVC 0 @@ -138,7 +132,7 @@ __tx_swi_interrupt ; ; The service call is handled here ; - + CMP r0, #0 ; Is it a schedule request? BEQ _tx_handler_svc_schedule ; Yes, go there @@ -147,7 +141,7 @@ __tx_swi_interrupt CMP r0, #2 ; Is it a system mode exit request? BEQ _tx_handler_svc_super_exit ; Yes, go there - + LDR r2, =0x123456 CMP r0, r2 ; Is it an ARM request? BEQ _tx_handler_svc_arm ; Yes, go there @@ -161,14 +155,14 @@ _tx_handler_svc_unrecognized _tx_handler_svc_unrecognized_loop ; We should never get here B _tx_handler_svc_unrecognized_loop - + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; SVC 1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; At this point we have an SVC 1, which means we are entering the system mode to service a kernel call _tx_handler_svc_super_enter ; Make sure that we have been called from the system mode enter location (security) - LDR r2, =_txm_system_mode_enter ; Load the address of the known call point + LDR r2, =_txm_system_mode_enter ; Load the address of the known call point SUB r1, lr, #4 ; Calculate the address of the actual call CMP r1, r2 ; Did we come from txm_module_manager_user_mode_entry? BNE _tx_handler_svc_unrecognized ; Return to where we came @@ -178,7 +172,7 @@ _tx_handler_svc_super_enter LDR r2, [r1] ; Load current thread location from the pointer (pointer indirection) MOV r1, #0 ; Load the new user mode flag value (user mode flag clear -> not user mode -> system) STR r1, [r2, #0x9C] ; Clear tx_thread_module_current_user_mode for thread - + ; Now we enter the system mode and return LDMFD sp!, {r0, r3} ; Get spsr from the stack BIC r0, r0, #MODE_MASK ; clear mode field @@ -198,16 +192,16 @@ _tx_handler_svc_super_enter LDRD r0, r1, [r2, #0xA4] ; Load the module kernel stack start and end STRD r0, r1, [r2, #0x0C] ; Set stack start and end ENDIF - + LDMFD sp!, {r0-r3, r12, pc}^ ; Restore the registers and return - + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; SVC 2 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; At this point we have an SVC 2, which means we are exiting the system mode after servicing a kernel call _tx_handler_svc_super_exit ; Make sure that we have been called from the system mode exit location (security) - LDR r2, =_txm_system_mode_exit ; Load the address of the known call point + LDR r2, =_txm_system_mode_exit ; Load the address of the known call point SUB r1, lr, #4 ; Calculate the address of the actual call CMP r1, r2 ; Did we come from txm_module_manager_user_mode_entry? BNE _tx_handler_svc_unrecognized ; Return to where we came @@ -237,19 +231,19 @@ _tx_handler_svc_super_exit STRD r0, r1, [r2, #0x0C] ; Set stack start and end ENDIF LDMFD sp!, {r0-r3, r12, pc}^ ; Restore the registers and return - + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ARM Semihosting ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; _tx_handler_svc_arm - + ; *** TODO: handle semihosting requests or ARM angel requests *** - + ; just return LDMFD sp!, {r0, r3} ; Get spsr from the stack MSR SPSR_cxsf, r0 ; Restore the spsr LDMFD sp!, {r0-r3, r12, pc}^ ; Restore the registers and return - + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; SVC 0 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -258,10 +252,10 @@ _tx_handler_svc_schedule LDMFD sp!, {r0, r3} ; Get spsr from stack MSR SPSR_cxsf, r0 ; Restore spsr - LDMFD sp!, {r0-r3, r12, lr} ; Restore the registers + LDMFD sp!, {r0-r3, r12, lr} ; Restore the registers - ; This code waits for a thread control block pointer to appear in - ; the _tx_thread_execute_ptr variable. Once a thread pointer appears + ; This code waits for a thread control block pointer to appear in + ; the _tx_thread_execute_ptr variable. Once a thread pointer appears ; in the variable, the corresponding thread is resumed. ; ; /* Enable interrupts. */ @@ -317,7 +311,7 @@ __tx_thread_schedule_loop ; Determine if an interrupt frame or a synchronous task suspension frame is present. CPS #SYS_MODE ; Enter SYS mode - LDR sp, [r0, #8] ; Switch to thread stack pointer + LDR sp, [r0, #8] ; Switch to thread stack pointer LDMIA sp!, {r4, r5} ; Pickup the stack type and saved CPSR CPS #SVC_MODE ; Enter SVC mode @@ -347,7 +341,7 @@ __tx_thread_schedule_loop MOV r3, #14 ADD r1, r1, r2, LSL r3 MCR p15, 0, r1, c2, c0, 0 ; Change TTBR to new value - + ; refresh TLB MOV r2, #0 DSB @@ -356,21 +350,21 @@ __tx_thread_schedule_loop MCR p15, 0, r2, c7, c5, 6 ; Invalidate branch predictor DSB ISB - + ;test address translation ;mcr p15, 0, r0, c7, c8, 0 - + _tx_skip_mmu_update ; ************************************************************************** - + CMP r4, #0 ; Check for synchronous context switch BEQ _tx_solicited_return - + MSR SPSR_cxsf, r5 ; Setup SPSR for return LDR r1, [r0, #8] ; Get thread SP LDR lr, [r1, #0x40] ; Get thread PC CPS #SYS_MODE ; Enter SYS mode - + IF {TARGET_FPU_VFP} = {TRUE} LDR r2, [r0, #144] ; Pickup the VFP enabled flag CMP r2, #0 ; Is the VFP enabled? @@ -384,7 +378,7 @@ _tx_skip_mmu_update CPS #SYS_MODE ; Enter SYS mode _tx_skip_interrupt_vfp_restore ENDIF - + LDMIA sp!, {r0-r12, lr} ; Restore registers ADD sp, sp, #4 ; Fix stack pointer CPS #SVC_MODE ; Enter SVC mode @@ -393,7 +387,7 @@ _tx_skip_interrupt_vfp_restore _tx_solicited_return MOV r2, r5 ; Move CPSR to scratch register CPS #SYS_MODE ; Enter SYS mode - + IF {TARGET_FPU_VFP} = {TRUE} LDR r1, [r0, #144] ; Pickup the VFP enabled flag CMP r1, #0 ; Is the VFP enabled? @@ -404,12 +398,12 @@ _tx_solicited_return VMSR FPSCR, r4 ; Restore FPSCR _tx_skip_solicited_vfp_restore ENDIF - + LDMIA sp!, {r4-r11, lr} ; Restore registers MOV r1, lr ; Copy lr to r1 to preserve across mode change CPS #SVC_MODE ; Enter SVC mode MSR SPSR_cxsf, r2 ; Recover CPSR - MOV lr, r1 ; Deprecated return via r1, so copy r1 to lr and return via lr + MOV lr, r1 ; Deprecated return via r1, so copy r1 to lr and return via lr SUBS pc, lr, #0 ; Return to thread synchronously ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_stack_build.s index 03e24ca7..b85d1b77 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_stack_build.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -42,44 +42,38 @@ THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build Cortex-A7/MMU/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-A7/MMU/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function builds a stack frame on the supplied thread's stack. */ -;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Pointer to thread control blk */ -;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -87,10 +81,10 @@ THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR EXPORT _tx_thread_stack_build _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-A7 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; a1 (r0) Initial value for a1 diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_system_return.s index 01e93435..cfaf4f84 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_system_return.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -33,50 +33,44 @@ IMPORT _tx_timer_time_slice IMPORT _tx_thread_schedule IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY - IMPORT _tx_execution_thread_exit + IMPORT _tx_execution_thread_exit ENDIF ; ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -104,7 +98,7 @@ _tx_skip_solicited_vfp_save MOV r0, #0 ; Build a solicited stack type MRS r1, CPSR ; Pickup the CPSR STMDB sp!, {r0-r1} ; Save type and CPSR -; +; ; /* Lockout interrupts. */ ; IF :DEF:TX_ENABLE_FIQ_SUPPORT diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_vectored_context_save.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_vectored_context_save.s index 1e9a2f82..d52a9776 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_vectored_context_save.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_thread_vectored_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -38,43 +38,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_vectored_context_save Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) @@ -135,7 +129,7 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Note: Minimal context of interrupted thread is already saved. */ @@ -171,7 +165,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports_module/cortex_a7/ac5/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_a7/ac5/module_manager/src/tx_timer_interrupt.s index ce94e6e0..0a2a68f6 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/tx_timer_interrupt.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -44,46 +44,40 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt Cortex-A7/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -107,7 +101,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CMP r2, #0 ; Is it non-active? BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing @@ -225,13 +219,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CMP r2, #0 ; See if the flag is set BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing ; diff --git a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c index 3f32067d..dda03dfc 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,23 +1,24 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -25,45 +26,39 @@ #include "txm_module.h" -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_alignment_adjust Cortex-A7/MMU/AC5 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-A7/MMU/AC5 */ /* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function adjusts the alignment and size of the code and data */ -/* section for a given module implementation. */ -/* */ -/* INPUT */ -/* */ -/* code_size Size of the code area (updated) */ -/* code_alignment Code area alignment (updated) */ -/* data_size Size of data area (updated) */ -/* data_alignment Data area alignment (updated) */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Initial thread stack frame */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment) diff --git a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c index f19534dd..4aa1b941 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,12 +65,6 @@ extern ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_EN /* */ /* _txm_module_manager_external_memory_enable */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ ULONG _txm_level2_page_get(TXM_MODULE_INSTANCE *module_instance, ULONG *page_addr) { diff --git a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c index f5a8b293..00bb9075 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { diff --git a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c index 1cd9f082..cd0535ae 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,23 +1,24 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -33,51 +34,45 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_memory_fault_notify Cortex-A7/MMU/AC5 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-A7/MMU/AC5 */ /* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function registers an application callback when/if a memory */ -/* fault occurs. The supplied thread is automatically terminated, but */ -/* any other threads in the same module may still execute. */ -/* */ -/* INPUT */ -/* */ -/* notify_function Memory fault notification */ -/* function, NULL disables. */ -/* */ -/* OUTPUT */ -/* */ -/* Status */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_mm_initialize.c b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_mm_initialize.c index be7288d1..aa8244cf 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_mm_initialize.c +++ b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_mm_initialize.c @@ -1,23 +1,24 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -51,48 +52,42 @@ TXM_MODULE_INSTANCE *_txm_asid_table[TXM_ASID_TABLE_LENGTH]; __align(16384) ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_ENTRIES]; /* Module start and end level 2 page tables, 2^10 (1kB) alignment. - * First set of 4 tables are the master level 2 tables, the rest are for each module. + * First set of 4 tables are the master level 2 tables, the rest are for each module. * Each module needs two L2 tables for code and two L2 tables for data. */ __align(1024) ULONG _txm_level2_module_page_table[TXM_MAXIMUM_MODULES * 4][TXM_LEVEL_2_PAGE_TABLE_ENTRIES]; /* Module external memory level 2 page tables, 2^10 (1kB) alignment. */ __align(1024) ULONG _txm_level2_external_page_pool[TXM_LEVEL2_EXTERNAL_POOL_PAGES][TXM_LEVEL_2_PAGE_TABLE_ENTRIES]; -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_mm_initialize Cortex-A7/MMU/AC5 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_initialize Cortex-A7/MMU/AC5 */ /* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function performs the initial set up of the the A7 MMU. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* Completion Status */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* This function performs the initial set up of the the A7 MMU. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ /* */ /**************************************************************************/ UINT _txm_module_manager_mm_initialize(VOID) @@ -103,53 +98,53 @@ UINT _txm_module_manager_mm_initialize(VOID) ULONG cp15reg; UINT user_mode_index; UINT counter_limit; - + /* Clear ASID table. */ for (i = 0; i < TXM_ASID_TABLE_LENGTH; i++) { _txm_asid_table[i] = 0; } _txm_asid_table[0] = (TXM_MODULE_INSTANCE *)TXM_ASID_RESERVED; - - + + /********************************************************************************/ /* This is an example showing how to set up the cache attributes. */ /********************************************************************************/ /******************************************************************************* -* PAGE TABLE generation -* Generate the page tables -* Build a flat translation table for the whole address space. -* ie: Create 4096 1MB sections from 0x000xxxxx to 0xFFFxxxxx +* PAGE TABLE generation +* Generate the page tables +* Build a flat translation table for the whole address space. +* ie: Create 4096 1MB sections from 0x000xxxxx to 0xFFFxxxxx * 31 20|19 18|17|16| 15|14 12|11 10|9|8 5|4 |3 2|1 0| * |base address | 0 0|nG| S|AP2|TEX |AP |P|Domain|XN|CB |1 0| * -* Bits[31:20] - Top 12 bits of VA is pointer into table +* Bits[31:20] - Top 12 bits of VA is pointer into table * nG[17]=0 - Non global, enables matching against ASID in the TLB when set. * S[16]=0 - Indicates normal memory is shared when set. -* AP2[15]=0 +* AP2[15]=0 * TEX[14:12]=000 -* AP[11:10]=11 - Configure for full read/write access in all modes +* AP[11:10]=11 - Configure for full read/write access in all modes * IMPP[9]=0 - Ignored * Domain[5:8]=1111 - Set all pages to use domain 15 * XN[4]=0 - Execute never disabled -* CB[3:2]= 00 - Set attributes to Strongly-ordered memory. -* (except for the descriptor where code segment is based, -* see below) -* Bits[1:0]=10 - Indicate entry is a 1MB section +* CB[3:2]= 00 - Set attributes to Strongly-ordered memory. +* (except for the descriptor where code segment is based, +* see below) +* Bits[1:0]=10 - Indicate entry is a 1MB section *******************************************************************************/ /* ---- Parameter setting to level1 descriptor (bits 19:0) ---- */ -/* setting for Strongly-ordered memory +/* setting for Strongly-ordered memory B-00000000000000000000010111100010 */ #define TTB_PARA_STRGLY 0x05E2 -/* setting for Outer and inner not cache normal memory +/* setting for Outer and inner not cache normal memory B-00000000000000000001010111100010 */ #define TTB_PARA_NORMAL_NOT_CACHE 0x15E2 -/* setting for Outer and inner write back, write allocate normal memory - (Cacheable) +/* setting for Outer and inner write back, write allocate normal memory + (Cacheable) B-00000000000000000001010111101110 */ #define TTB_PARA_NORMAL_CACHE 0x15EE //0x15EE @@ -167,98 +162,98 @@ UINT _txm_module_manager_mm_initialize(VOID) #define M_SIZE_RAM_M 10 /* [Area10] Internal RAM (mirror) */ #define M_SIZE_IO_2 2550 /* [Area11] I/O area 2 */ /* Should add to: 4096 */ - + counter_limit = M_SIZE_NOR; for (i = 0; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; } - + counter_limit += M_SIZE_SDRAM; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; } - + counter_limit += M_SIZE_CS45; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; } - + counter_limit += M_SIZE_SPI; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; } - + counter_limit += M_SIZE_RAM; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; } - + counter_limit += M_SIZE_IO_1; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; } - + counter_limit += M_SIZE_NOR_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; } - + counter_limit += M_SIZE_SDRAM_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; } - + counter_limit += M_SIZE_CS45_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; } - + counter_limit += M_SIZE_SPI_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; } - + counter_limit += M_SIZE_RAM_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; } - + counter_limit += M_SIZE_IO_2; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; } - + /********************************************************************************/ /* This is the end of the example showing how to set up the cache attributes. */ /********************************************************************************/ - - + + /* Clear ASID. */ cp15reg = 0; __asm("mcr p15, 0, cp15reg, c13, c0, 1"); __asm("isb"); - + /* Put the page table address in TTBR. */ cp15reg = (int)(VOID*)_txm_ttbr1_page_table; cp15reg |= TTBR0_ATTRIBUTES; __asm("mcr p15, 0, cp15reg, c2, c0, 0"); - + /* Set the domain to client mode. */ cp15reg = DACR_CLIENT_MODE; __asm("mcr p15, 0, cp15reg, c3, c0, 0"); - + /* Level 2 small page attributes: normal memory, cache & buffer enabled, priviledged access. */ #define TTB_LEVEL2_NORMAL_CACHE 0x05E @@ -268,7 +263,7 @@ UINT _txm_module_manager_mm_initialize(VOID) /* Attributes for user mode table entry in level 2 table. */ #define TTB_LEVEL2_USER_MODE_ENTRY 0x06E - + /* Set up Level 2 table for user to kernel mode entry trampoline. */ /* Find which table entry _txm_module_manager_user_mode_entry is in. */ user_mode_index = (ULONG)_txm_module_manager_user_mode_entry >> TXM_MMU_LEVEL1_PAGE_SHIFT; @@ -277,21 +272,21 @@ UINT _txm_module_manager_mm_initialize(VOID) { _txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = ((ULONG)_txm_module_manager_user_mode_entry & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | TTB_LEVEL2_NORMAL_CACHE; } - + /* Enter Level 2 table in to master table. */ _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] = ((ULONG)_txm_level2_module_page_table & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; - + /* Find level 2 entry that holds _txm_module_manager_user_mode_entry. */ user_mode_index = ((ULONG)_txm_module_manager_user_mode_entry & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT; - + /* Set attribute bits for the user mode entry page. */ _txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] = (_txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] & TTB_LEVEL2_AP_CLEAR_MASK) | TTB_LEVEL2_USER_MODE_ENTRY; - + /* Enable the MMU. */ __asm("mrc p15, 0, cp15reg, c1, c0, 0"); cp15reg |= 0x1; __asm("mcr p15, 0, cp15reg, c1, c0, 0"); - + return(TX_SUCCESS); #else diff --git a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c index 4c5d7a09..bdaa548d 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ extern ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_EN /* */ /* TXM_MODULE_MANAGER_DATA_POINTER_CHECK */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_inside_data_check(ULONG pointer) { diff --git a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s index 675b1db6..5ae43a7e 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Module Manager */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module Manager */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -40,44 +40,38 @@ CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints en ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _txm_module_manager_thread_stack_build Cortex-A7/MMU/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_thread_stack_build Cortex-A7/MMU/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function builds a stack frame on the supplied thread's stack. */ -;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Pointer to thread control blk */ -;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) @@ -88,7 +82,7 @@ _txm_module_manager_thread_stack_build ; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-A7 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; r0 Initial value for r0 diff --git a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_user_mode_entry.s b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_user_mode_entry.s index 58da85b9..758c4125 100644 --- a/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_user_mode_entry.s +++ b/ports_module/cortex_a7/ac5/module_manager/src/txm_module_manager_user_mode_entry.s @@ -1,66 +1,60 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Module Manager */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module Manager */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; IMPORT _tx_thread_current_ptr IMPORT _txm_module_manager_kernel_dispatch - - + + AREA ||.text||, CODE, READONLY, ALIGN=12 PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _txm_module_manager_user_mode_entry Cortex-A7/MMU/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_user_mode_entry Cortex-A7/MMU/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function allows modules to enter kernel mode. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* SVC 1 Enter kernel mode */ -;/* SVC 2 Exit kernel mode */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Modules in user mode */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* This function allows modules to enter kernel mode. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* SVC 1 Enter kernel mode */ +;/* SVC 2 Exit kernel mode */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Modules in user mode */ ;/* */ ;/**************************************************************************/ EXPORT _txm_module_manager_user_mode_entry @@ -83,9 +77,9 @@ _txm_system_mode_exit BX lr ; Return to the caller NOP NOP - + ; Fill up 4kB page. ALIGN 4096 _txm_module_manager_user_mode_end - + END diff --git a/ports_module/cortex_a7/gnu/example_build/build_threadx_module_sample.bat b/ports_module/cortex_a7/gnu/example_build/build_threadx_module_sample.bat index 8e6f8286..f0214cfc 100644 --- a/ports_module/cortex_a7/gnu/example_build/build_threadx_module_sample.bat +++ b/ports_module/cortex_a7/gnu/example_build/build_threadx_module_sample.bat @@ -3,4 +3,4 @@ arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -m arm-none-eabi-gcc -c -g -O0 -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork -DTX_ENABLE_VFP_SUPPORT -fpic -fno-plt -mno-pic-data-is-text-relative -msingle-pic-base -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc sample_threadx_module.c rem arm-none-eabi-gcc -g --elf --ro 0 --first txm_module_preamble.o(Init) --entry=_txm_module_thread_shell_entry --ropi --rwpi --remove --map --symbols --list sample_threadx_module.map txm_module_preamble.o sample_threadx_module.o txm.a rem arm-none-eabi-gcc -g -mcpu=cortex-a7 -T sample_threadx_module.ld -mfloat-abi=hard -mfpu=neon-vfpv4 -marm -mthumb-interwork --specs=nosys.specs -e _txm_module_thread_shell_entry -o sample_threadx_module.out -Wl,-Map=sample_threadx_module.map gcc_setup.o txm_module_preamble.o sample_threadx_module.o txm.a -arm-none-eabi-ld -A cortex-a7 -T sample_threadx_module.ld txm_module_preamble.o gcc_setup.o sample_threadx_module.o -e _txm_module_thread_shell_entry txm.a -o sample_threadx_module.axf -M > sample_threadx_module.map \ No newline at end of file +arm-none-eabi-ld -A cortex-a7 -T sample_threadx_module.ld txm_module_preamble.o gcc_setup.o sample_threadx_module.o -e _txm_module_thread_shell_entry txm.a -o sample_threadx_module.axf -M > sample_threadx_module.map \ No newline at end of file diff --git a/ports_module/cortex_a7/gnu/example_build/gcc_setup.S b/ports_module/cortex_a7/gnu/example_build/gcc_setup.S index 22a41727..d0eaeb79 100644 --- a/ports_module/cortex_a7/gnu/example_build/gcc_setup.S +++ b/ports_module/cortex_a7/gnu/example_build/gcc_setup.S @@ -22,7 +22,7 @@ _gcc_setup: mov r5,r0 /* Copy GOT table. */ - + ldr r0, =__got_load_start__ sub r0,r0,r3 add r0,r0,r5 @@ -50,13 +50,13 @@ flash_area: address_built: str r6, [r1] // Store in new GOT table add r0, r0, #4 // Move to next entry - add r1, r1, #4 // + add r1, r1, #4 // b new_got_setup // Continue at the top of the loop got_setup_done: /* Copy initialised sections into RAM if required. */ - + ldr r0, =__data_load_start__ sub r0,r0,r3 add r0,r0,r5 @@ -67,9 +67,9 @@ got_setup_done: sub r2,r2,r4 add r2,r2,r9 bl crt0_memory_copy - + /* Zero bss. */ - + ldr r0, =__bss_start__ sub r0,r0,r4 add r0,r0,r9 @@ -93,10 +93,10 @@ got_setup_done: str r2, [r0] add r0, r0, #4 str r1, [r0] - + LDMIA sp!, {r3, r4, r5, r6, r7, lr} // Store other preserved registers bx lr // Return to caller - + .align 4 /* Startup helper functions. */ @@ -130,4 +130,3 @@ memory_set_done: /* Setup attibutes of heap section so it doesn't take up room in the elf file */ .section .heap, "wa", %nobits - \ No newline at end of file diff --git a/ports_module/cortex_a7/gnu/example_build/module_code.c b/ports_module/cortex_a7/gnu/example_build/module_code.c index 562ecea2..d380dfa9 100644 --- a/ports_module/cortex_a7/gnu/example_build/module_code.c +++ b/ports_module/cortex_a7/gnu/example_build/module_code.c @@ -4,7 +4,7 @@ /* */ /************************************************************************************************/ -/* +/* Input ELF file: .\sample_threadx_module.axf Output C Array file: .\module_code.c */ diff --git a/ports_module/cortex_a7/gnu/example_build/reset.S b/ports_module/cortex_a7/gnu/example_build/reset.S index 3ce9efb7..f2e0522b 100644 --- a/ports_module/cortex_a7/gnu/example_build/reset.S +++ b/ports_module/cortex_a7/gnu/example_build/reset.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_module/cortex_a7/gnu/example_build/sample_threadx.ld b/ports_module/cortex_a7/gnu/example_build/sample_threadx.ld index 3dea4e1c..e940b2b8 100644 --- a/ports_module/cortex_a7/gnu/example_build/sample_threadx.ld +++ b/ports_module/cortex_a7/gnu/example_build/sample_threadx.ld @@ -7,7 +7,7 @@ OUTPUT_ARCH(arm) SECTIONS { . = 0x00000000; - + .vectors : {reset.o(.text) } /* Read-only sections, merged into text segment: */ @@ -94,8 +94,8 @@ SECTIONS *(.gnu.linkonce.t*) *(.glue_7t) *(.glue_7) } =0 - .init : - { + .init : + { KEEP (*(.init)) } =0 _etext = .; @@ -120,7 +120,7 @@ SECTIONS .data1 : { *(.data1) } .eh_frame : { KEEP (*(.eh_frame)) } .gcc_except_table : { *(.gcc_except_table) } - .ctors : + .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is @@ -153,9 +153,9 @@ SECTIONS /* We want the small data sections together, so single-instruction offsets can access them all, and initialized data all before uninitialized, so we can shorten the on-disk segment size. */ - .sdata : + .sdata : { - *(.sdata) + *(.sdata) *(.sdata.*) *(.gnu.linkonce.s.*) } @@ -191,7 +191,7 @@ SECTIONS _stack_bottom = ABSOLUTE(.) ; - /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and + /* Allocate room for stack. This must be big enough for the IRQ, FIQ, and SYS stack if nested interrupts are enabled. */ . = ALIGN(8) ; . += 4096 ; diff --git a/ports_module/cortex_a7/gnu/example_build/sample_threadx_module.c b/ports_module/cortex_a7/gnu/example_build/sample_threadx_module.c index fce2a3fa..f9ed56eb 100644 --- a/ports_module/cortex_a7/gnu/example_build/sample_threadx_module.c +++ b/ports_module/cortex_a7/gnu/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -101,7 +101,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MMU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void *) &thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void *) &thread_1, sizeof(TX_THREAD)); @@ -117,7 +117,7 @@ CHAR *pointer; txm_module_object_allocate((void *) &event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void *) &byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void *) &block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -129,25 +129,25 @@ CHAR *pointer; /* Create the main thread. */ tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ @@ -156,14 +156,14 @@ CHAR *pointer; /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -172,7 +172,7 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ @@ -180,14 +180,14 @@ CHAR *pointer; /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -237,7 +237,7 @@ UINT status; *(ULONG *) 0x90000000 = 0xdeadbeef; *(ULONG *) 0x90000FFC = 0xfeed0add; *(ULONG *) 0x90001000 = 0xfedcba01; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -247,7 +247,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -300,11 +300,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -363,7 +363,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -416,7 +416,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_a7/gnu/example_build/sample_threadx_module.ld b/ports_module/cortex_a7/gnu/example_build/sample_threadx_module.ld index 30c66655..5fa4c680 100644 --- a/ports_module/cortex_a7/gnu/example_build/sample_threadx_module.ld +++ b/ports_module/cortex_a7/gnu/example_build/sample_threadx_module.ld @@ -125,7 +125,7 @@ SECTIONS KEEP (*(.got*)) . = ALIGN(4); _egot = .; - } + } __got_end__ = __got_load_start__ + SIZEOF(.got); __rodata_load_start__ = ALIGN(__got_end__ , 4); @@ -135,7 +135,7 @@ SECTIONS *(.rodata .rodata.* .gnu.linkonce.r.*) } __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); - + __code_size__ = SIZEOF(.data) + __rodata_end__ - __FLASH_segment_start__; __fast_load_start__ = ALIGN(__rodata_end__ , 4); diff --git a/ports_module/cortex_a7/gnu/example_build/sample_threadx_module_manager.c b/ports_module/cortex_a7/gnu/example_build/sample_threadx_module_manager.c index 8b17e34a..ac3bbeb5 100644 --- a/ports_module/cortex_a7/gnu/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_a7/gnu/example_build/sample_threadx_module_manager.c @@ -1,4 +1,4 @@ -/* Small demonstration of the ThreadX module manager. This demonstration assumes the program +/* Small demonstration of the ThreadX module manager. This demonstration assumes the program manager is loaded at 0 and that RAM addresses 0x200000 through 0x400000 are available for use. */ @@ -45,7 +45,7 @@ VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) int main() { - + /* Enter the ThreadX kernel. */ tx_kernel_enter(); } @@ -57,8 +57,8 @@ void tx_application_define(void *first_unused_memory) { /* Create the module manager thread. */ - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - first_unused_memory, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + first_unused_memory, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); } @@ -71,46 +71,46 @@ void module_manager_entry(ULONG thread_input) /* Initialize the module manager. */ txm_module_manager_initialize((VOID *) module_data_area, MODULE_DATA_SIZE); - + /* Create a pool for module objects. */ txm_module_manager_object_pool_create(object_memory, sizeof(object_memory)); - + /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Initialize MMU. */ txm_module_manager_mm_initialize(); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module1, "my module1", (VOID *) module_code); - + /* Load a second instance of the module. */ //txm_module_manager_in_place_load(&my_module2, "my module2", (VOID *) module_code); - + /* Enable shared memory regions for one module. */ //txm_module_manager_external_memory_enable(&my_module2, (void*)0x90000000, 0x010000, 0x3F); - + /* Start the modules. */ txm_module_manager_start(&my_module1); //txm_module_manager_start(&my_module2); - + /* Sleep for a while and let the modules run.... */ tx_thread_sleep(50); - + /* Thread 0 in module1 should be terminated due to violating the MMU. */ - + /* Stop the modules. */ txm_module_manager_stop(&my_module1); txm_module_manager_stop(&my_module2); - + /* Unload the modules. */ txm_module_manager_unload(&my_module1); txm_module_manager_unload(&my_module2); - + /* Reload the modules. */ txm_module_manager_in_place_load(&my_module2, "my module2", (VOID *) module_code); txm_module_manager_in_place_load(&my_module1, "my module1", (VOID *) module_code); - + /* Give both modules shared memory. */ txm_module_manager_external_memory_enable(&my_module2, (void*)0x90000000, 0x010000, 0x3F); txm_module_manager_external_memory_enable(&my_module1, (void*)0x90000000, 0x010000, 0x3F); @@ -118,7 +118,7 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module2); txm_module_manager_start(&my_module1); - + /* Now just spin... */ while(1) { diff --git a/ports_module/cortex_a7/gnu/example_build/tx_initialize_low_level.s b/ports_module/cortex_a7/gnu/example_build/tx_initialize_low_level.s index 6d1ceeff..0c267ac6 100644 --- a/ports_module/cortex_a7/gnu/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_a7/gnu/example_build/tx_initialize_low_level.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -87,18 +88,6 @@ THUMB_MASK = 0x20 // THUMB mode bit /* CALLED BY */ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/example_build/txm_module_preamble.s b/ports_module/cortex_a7/gnu/example_build/txm_module_preamble.s index 0e35f8f0..90c0c338 100644 --- a/ports_module/cortex_a7/gnu/example_build/txm_module_preamble.s +++ b/ports_module/cortex_a7/gnu/example_build/txm_module_preamble.s @@ -28,7 +28,7 @@ __txm_module_preamble: // 1 -> User mode execution .dc.l _txm_module_thread_shell_entry // Module Shell Entry Point .dc.l demo_module_start // Module Start Thread Entry Point - .dc.l 0 // Module Stop Thread Entry Point + .dc.l 0 // Module Stop Thread Entry Point .dc.l 1 // Module Start/Stop Thread Priority .dc.l 2046 // Module Start/Stop Thread Stack Size .dc.l _txm_module_callback_request_thread_entry // Module Callback Thread Entry diff --git a/ports_module/cortex_a7/gnu/inc/tx_port.h b/ports_module/cortex_a7/gnu/inc/tx_port.h index 55400b6f..41040fa9 100644 --- a/ports_module/cortex_a7/gnu/inc/tx_port.h +++ b/ports_module/cortex_a7/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,23 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Updated comments, removed */ -/* unneeded temp variable, */ -/* resulting in version 6.1.12 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -337,7 +321,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv7-A Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-A Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_a7/gnu/inc/txm_module_port.h b/ports_module/cortex_a7/gnu/inc/txm_module_port.h index a0a435b1..9cd5a280 100644 --- a/ports_module/cortex_a7/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_a7/gnu/inc/txm_module_port.h @@ -1,55 +1,47 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Interface (API) */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Interface (API) */ +/** */ +/**************************************************************************/ +/**************************************************************************/ -/**************************************************************************/ -/* */ -/* APPLICATION INTERFACE DEFINITION RELEASE */ -/* */ -/* txm_module_port.h Cortex-A7/MMU/GNU */ +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-A7/MMU/GNU */ /* 6.3.0 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This file defines the basic module constants, interface structures, */ -/* and function prototypes. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ /* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ /* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H #define TXM_MODULE_PORT_H -/* It is assumed that the base ThreadX tx_port.h file has been modified to add the +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the following extensions to the ThreadX thread control block (this code should replace the corresponding macro define in tx_port.h): @@ -89,10 +81,10 @@ The following extensions must also be defined in tx_port.h: #endif /* Defined, this option enables the MMU hardware and requires memory protected - module objects to be allocated from the module manager object pool. - If this is undefined, module objects can be created in the module's data area - or in the module manager object pool. If this is not defined (MMU hardware - is disabled), a module requiring memory protection will not run (the load + module objects to be allocated from the module manager object pool. + If this is undefined, module objects can be created in the module's data area + or in the module manager object pool. If this is not defined (MMU hardware + is disabled), a module requiring memory protection will not run (the load functions will return a TXM_MODULE_INVALID_PROPERTIES error). Default setting for this value is defined. */ #define TXM_MODULE_MEMORY_PROTECTION_ENABLED @@ -299,7 +291,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; /* Define the macro to check the stack available in dispatch. */ -#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE +#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE /* Define the macro to check the code alignment. */ @@ -409,7 +401,7 @@ UINT _txm_module_manager_inside_data_check(ULONG pointer); #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-A7/MMU/GNU Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-A7/MMU/GNU Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_a7/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_a7/gnu/module_lib/src/txm_module_thread_shell_entry.c index 5e22ff15..73a38340 100644 --- a/ports_module/cortex_a7/gnu/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_a7/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -81,12 +82,6 @@ ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kern /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_context_restore.s index 8b55c21d..62b36534 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,21 +72,6 @@ SVC_MODE = 0x13 // SVC mode /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_context_save.s index d29d464f..e124db7a 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -69,21 +70,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_context_restore.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_context_restore.s index 8876a873..a6f5cbeb 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_context_restore.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,21 +75,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* CALLED BY */ /* */ /* FIQ ISR Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_context_save.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_context_save.s index b6ac3bbf..2ce315f9 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_context_save.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,21 +68,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_nesting_end.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_nesting_end.s index e2dbba7d..9938b4e6 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_nesting_end.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_nesting_end.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -75,18 +76,6 @@ FIQ_MODE_BITS = 0x11 // FIQ mode bits /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_nesting_start.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_nesting_start.s index 68cdb6ba..2be8b631 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_nesting_start.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_fiq_nesting_start.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,18 +69,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_control.s index 4d5c7442..15e244f1 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,18 +65,6 @@ FIQ_MASK = 0x040 /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_disable.s index 1fa006d8..7b6d8647 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,18 +58,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_restore.s index 725e4810..ba5fe5b6 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,18 +65,6 @@ FIQ_MASK = 0x040 /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_irq_nesting_end.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_irq_nesting_end.s index 90573977..dfd8b554 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_irq_nesting_end.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_irq_nesting_end.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -75,18 +76,6 @@ IRQ_MODE_BITS = 0x12 // IRQ mode bits /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_irq_nesting_start.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_irq_nesting_start.s index 02be1d75..c87978e7 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_irq_nesting_start.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_irq_nesting_start.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,18 +69,6 @@ SYS_MODE_BITS = 0x1F // System mode bits /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_schedule.s index 9faf80eb..54e2c768 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,16 +87,6 @@ FIQ_MASK = 0x040 /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_stack_build.s index d4dd01c7..f4f0717b 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -73,18 +74,6 @@ CPSR_MASK = 0xBF // Mask initial CPSR, T, IRQ int /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_system_return.s index d2792904..fd8de227 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,21 +67,6 @@ SYS_MODE = 0x1F // SYS mode /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_vectored_context_save.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_vectored_context_save.s index 27465bdf..ce0202d4 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_vectored_context_save.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_thread_vectored_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,21 +67,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* execution profile support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_a7/gnu/module_manager/src/tx_timer_interrupt.s index 8d70c67a..8c9b5186 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -73,18 +74,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-25-2022 Zhen Kong Updated comments, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ #if defined(THUMB_MODE) .thumb_func diff --git a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c index c7178301..4641dcc8 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment) { diff --git a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c index fa79dc8a..bbb9013c 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,12 +65,6 @@ extern ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_EN /* */ /* _txm_module_manager_external_memory_enable */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ ULONG _txm_level2_page_get(TXM_MODULE_INSTANCE *module_instance, ULONG *page_addr) { diff --git a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c index 68bd8e44..303b17ce 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { diff --git a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c index 7b6ea622..df6ca21e 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,12 +67,6 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { diff --git a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_mm_initialize.c b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_mm_initialize.c index dcda0e1c..da8d0904 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_mm_initialize.c +++ b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_mm_initialize.c @@ -1,23 +1,24 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -51,48 +52,42 @@ TXM_MODULE_INSTANCE *_txm_asid_table[TXM_ASID_TABLE_LENGTH]; __attribute__ ((aligned (16384))) ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_ENTRIES]; /* Module start and end level 2 page tables, 2^10 (1kB) alignment. - * First set of 4 tables are the master level 2 tables, the rest are for each module. + * First set of 4 tables are the master level 2 tables, the rest are for each module. * Each module needs two L2 tables for code and two L2 tables for data. */ __attribute__ ((aligned (1024))) ULONG _txm_level2_module_page_table[TXM_MAXIMUM_MODULES * 4][TXM_LEVEL_2_PAGE_TABLE_ENTRIES]; /* Module external memory level 2 page tables, 2^10 (1kB) alignment. */ __attribute__ ((aligned (1024))) ULONG _txm_level2_external_page_pool[TXM_LEVEL2_EXTERNAL_POOL_PAGES][TXM_LEVEL_2_PAGE_TABLE_ENTRIES]; -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_mm_initialize Cortex-A7/MMU/GNU */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_initialize Cortex-A7/MMU/GNU */ /* 6.2.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function performs the initial set up of the the A7 MMU. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* Completion Status */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ /* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ +/* This function performs the initial set up of the the A7 MMU. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ /* */ /**************************************************************************/ UINT _txm_module_manager_mm_initialize(VOID) @@ -103,53 +98,53 @@ UINT _txm_module_manager_mm_initialize(VOID) ULONG cp15reg; UINT user_mode_index; UINT counter_limit; - + /* Clear ASID table. */ for (i = 0; i < TXM_ASID_TABLE_LENGTH; i++) { _txm_asid_table[i] = 0; } _txm_asid_table[0] = (TXM_MODULE_INSTANCE *)TXM_ASID_RESERVED; - - + + /********************************************************************************/ /* This is an example showing how to set up the cache attributes. */ /********************************************************************************/ /******************************************************************************* -* PAGE TABLE generation -* Generate the page tables -* Build a flat translation table for the whole address space. -* ie: Create 4096 1MB sections from 0x000xxxxx to 0xFFFxxxxx +* PAGE TABLE generation +* Generate the page tables +* Build a flat translation table for the whole address space. +* ie: Create 4096 1MB sections from 0x000xxxxx to 0xFFFxxxxx * 31 20|19 18|17|16| 15|14 12|11 10|9|8 5|4 |3 2|1 0| * |base address | 0 0|nG| S|AP2|TEX |AP |P|Domain|XN|CB |1 0| * -* Bits[31:20] - Top 12 bits of VA is pointer into table +* Bits[31:20] - Top 12 bits of VA is pointer into table * nG[17]=0 - Non global, enables matching against ASID in the TLB when set. * S[16]=0 - Indicates normal memory is shared when set. -* AP2[15]=0 +* AP2[15]=0 * TEX[14:12]=000 -* AP[11:10]=11 - Configure for full read/write access in all modes +* AP[11:10]=11 - Configure for full read/write access in all modes * IMPP[9]=0 - Ignored * Domain[5:8]=1111 - Set all pages to use domain 15 * XN[4]=0 - Execute never disabled -* CB[3:2]= 00 - Set attributes to Strongly-ordered memory. -* (except for the descriptor where code segment is based, -* see below) -* Bits[1:0]=10 - Indicate entry is a 1MB section +* CB[3:2]= 00 - Set attributes to Strongly-ordered memory. +* (except for the descriptor where code segment is based, +* see below) +* Bits[1:0]=10 - Indicate entry is a 1MB section *******************************************************************************/ /* ---- Parameter setting to level1 descriptor (bits 19:0) ---- */ -/* setting for Strongly-ordered memory +/* setting for Strongly-ordered memory B-00000000000000000000010111100010 */ #define TTB_PARA_STRGLY 0x05E2 -/* setting for Outer and inner not cache normal memory +/* setting for Outer and inner not cache normal memory B-00000000000000000001010111100010 */ #define TTB_PARA_NORMAL_NOT_CACHE 0x15E2 -/* setting for Outer and inner write back, write allocate normal memory - (Cacheable) +/* setting for Outer and inner write back, write allocate normal memory + (Cacheable) B-00000000000000000001010111101110 */ #define TTB_PARA_NORMAL_CACHE 0x15EE //0x15EE @@ -167,98 +162,98 @@ UINT _txm_module_manager_mm_initialize(VOID) #define M_SIZE_RAM_M 10 /* [Area10] Internal RAM (mirror) */ #define M_SIZE_IO_2 2550 /* [Area11] I/O area 2 */ /* Should add to: 4096 */ - + counter_limit = M_SIZE_NOR; for (i = 0; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; } - + counter_limit += M_SIZE_SDRAM; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; } - + counter_limit += M_SIZE_CS45; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; } - + counter_limit += M_SIZE_SPI; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; } - + counter_limit += M_SIZE_RAM; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; } - + counter_limit += M_SIZE_IO_1; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; } - + counter_limit += M_SIZE_NOR_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; } - + counter_limit += M_SIZE_SDRAM_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; } - + counter_limit += M_SIZE_CS45_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; } - + counter_limit += M_SIZE_SPI_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; } - + counter_limit += M_SIZE_RAM_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; } - + counter_limit += M_SIZE_IO_2; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; } - + /********************************************************************************/ /* This is the end of the example showing how to set up the cache attributes. */ /********************************************************************************/ - - + + /* Clear ASID. */ cp15reg = 0; __asm volatile ("mcr p15, 0, %0, c13, c0, 1" : : "r"(cp15reg) : ); __asm("isb"); - + /* Put the page table address in TTBR. */ cp15reg = (int)(VOID*)_txm_ttbr1_page_table; cp15reg |= TTBR0_ATTRIBUTES; __asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r"(cp15reg) : ); - + /* Set the domain to client mode. */ cp15reg = DACR_CLIENT_MODE; __asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r"(cp15reg) : ); - + /* Level 2 small page attributes: normal memory, cache & buffer enabled, priviledged access. */ #define TTB_LEVEL2_NORMAL_CACHE 0x05E @@ -268,7 +263,7 @@ UINT _txm_module_manager_mm_initialize(VOID) /* Attributes for user mode table entry in level 2 table. */ #define TTB_LEVEL2_USER_MODE_ENTRY 0x06E - + /* Set up Level 2 table for user to kernel mode entry trampoline. */ /* Find which table entry _txm_module_manager_user_mode_entry is in. */ user_mode_index = (ULONG)_txm_module_manager_user_mode_entry >> TXM_MMU_LEVEL1_PAGE_SHIFT; @@ -277,21 +272,21 @@ UINT _txm_module_manager_mm_initialize(VOID) { _txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = ((ULONG)_txm_module_manager_user_mode_entry & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | TTB_LEVEL2_NORMAL_CACHE; } - + /* Enter Level 2 table in to master table. */ _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] = ((ULONG)_txm_level2_module_page_table & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; - + /* Find level 2 entry that holds _txm_module_manager_user_mode_entry. */ user_mode_index = ((ULONG)_txm_module_manager_user_mode_entry & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT; - + /* Set attribute bits for the user mode entry page. */ _txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] = (_txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] & TTB_LEVEL2_AP_CLEAR_MASK) | TTB_LEVEL2_USER_MODE_ENTRY; - + /* Enable the MMU. */ __asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r"(cp15reg) : : ); cp15reg |= 0x1; __asm volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r"(cp15reg) : ); - + return(TX_SUCCESS); #else diff --git a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index 9a049056..60202970 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ extern ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_EN /* */ /* TXM_MODULE_MANAGER_DATA_POINTER_CHECK */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_inside_data_check(ULONG pointer) { diff --git a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s index d62f5cf8..e701846a 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,16 +68,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_user_mode_entry.s b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_user_mode_entry.s index e84bb7f2..b9c59109 100644 --- a/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_user_mode_entry.s +++ b/ports_module/cortex_a7/gnu/module_manager/src/txm_module_manager_user_mode_entry.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,16 +58,6 @@ /* CALLED BY */ /* */ /* Modules in user mode */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* 10-31-2023 Yajun Xia Updated comments, */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .text .align 12 diff --git a/ports_module/cortex_a7/iar/example_build/cstartup.s b/ports_module/cortex_a7/iar/example_build/cstartup.s index 329decce..443be304 100644 --- a/ports_module/cortex_a7/iar/example_build/cstartup.s +++ b/ports_module/cortex_a7/iar/example_build/cstartup.s @@ -1,7 +1,7 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; -;; Part one of the system initialization code, +;; Part one of the system initialization code, ;; contains low-level ;; initialization. ;; @@ -71,13 +71,13 @@ FIQ_Addr: DCD __tx_fiq_handler SECTION .text:CODE:NOROOT(2) -; PUBLIC ?cstartup +; PUBLIC ?cstartup EXTERN ?main REQUIRE __vector - ARM - -__iar_program_start: + ARM + +__iar_program_start: ?cstartup: ; diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx_module.c b/ports_module/cortex_a7/iar/example_build/sample_threadx_module.c index 0cad4a70..33a22445 100644 --- a/ports_module/cortex_a7/iar/example_build/sample_threadx_module.c +++ b/ports_module/cortex_a7/iar/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -101,7 +101,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MMU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void *) &thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void *) &thread_1, sizeof(TX_THREAD)); @@ -117,7 +117,7 @@ CHAR *pointer; txm_module_object_allocate((void *) &event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void *) &byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void *) &block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -128,42 +128,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -171,23 +171,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -241,7 +241,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -261,7 +261,7 @@ UINT status; /* This thread simply sends messages to a queue shared by thread 2. */ while(1) { - + /* Increment the thread counter. */ thread_1_counter++; @@ -287,18 +287,18 @@ UINT status; /* This thread retrieves messages placed on the queue by thread 1. */ while(1) { - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -352,12 +352,12 @@ ULONG actual_flags; /* This thread simply waits for an event in a forever loop. */ while(1) { - + /* Increment the thread counter. */ thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -410,7 +410,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx_module.icf b/ports_module/cortex_a7/iar/example_build/sample_threadx_module.icf index bed79adf..69c8f600 100644 --- a/ports_module/cortex_a7/iar/example_build/sample_threadx_module.icf +++ b/ports_module/cortex_a7/iar/example_build/sample_threadx_module.icf @@ -26,11 +26,11 @@ define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; initialize by copy { readwrite }; do not initialize { section .noinit }; -define movable block ROPI with alignment = 4, fixed order -{ +define movable block ROPI with alignment = 4, fixed order +{ ro object txm_module_preamble.o, - ro, - ro data + ro, + ro data }; define movable block RWPI with alignment = 8, fixed order, static base diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.c index 9aa08e2f..b3a4f2f9 100644 --- a/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.c @@ -1,4 +1,4 @@ -/* Small demonstration of the ThreadX module manager. This demonstration assumes the program +/* Small demonstration of the ThreadX module manager. This demonstration assumes the program manager is loaded at 0 and that RAM addresses 0x200000 through 0x400000 are available for use. */ @@ -47,7 +47,7 @@ VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) int main() { - + /* Enter the ThreadX kernel. */ tx_kernel_enter(); } @@ -59,8 +59,8 @@ void tx_application_define(void *first_unused_memory) { /* Create the module manager thread. */ - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - manager_thread_stack, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + manager_thread_stack, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); } @@ -72,46 +72,46 @@ void module_manager_entry(ULONG thread_input) /* Initialize the module manager. */ txm_module_manager_initialize((VOID *) module_data_area, MODULE_DATA_SIZE); - + /* Create a pool for module objects. */ txm_module_manager_object_pool_create(object_memory, sizeof(object_memory)); - + /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Initialize MMU. */ txm_module_manager_mm_initialize(); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module1, "my module1", (VOID *) 0x00100000); - + /* Load a second instance of the module. */ //txm_module_manager_in_place_load(&my_module2, "my module2", (VOID *) module_code); - + /* Enable shared memory regions for one module. */ //txm_module_manager_external_memory_enable(&my_module2, (void*)0x90000000, 0x010000, 0x3F); - + /* Start the modules. */ txm_module_manager_start(&my_module1); //txm_module_manager_start(&my_module2); - + /* Sleep for a while and let the modules run.... */ tx_thread_sleep(50); - + /* Thread 0 in module1 should be terminated due to violating the MMU. */ - + /* Stop the modules. */ txm_module_manager_stop(&my_module1); txm_module_manager_stop(&my_module2); - + /* Unload the modules. */ txm_module_manager_unload(&my_module1); txm_module_manager_unload(&my_module2); - + /* Reload the modules. */ txm_module_manager_in_place_load(&my_module2, "my module2", (VOID *) 0x00100000); txm_module_manager_in_place_load(&my_module1, "my module1", (VOID *) 0x00100000); - + /* Give both modules shared memory. */ txm_module_manager_external_memory_enable(&my_module2, (void*)0x90000000, 0x010000, 0x3F); txm_module_manager_external_memory_enable(&my_module1, (void*)0x90000000, 0x010000, 0x3F); @@ -119,7 +119,7 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module2); txm_module_manager_start(&my_module1); - + /* Now just spin... */ while(1) { diff --git a/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.icf b/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.icf index f076b002..ea39b4f5 100644 --- a/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.icf +++ b/ports_module/cortex_a7/iar/example_build/sample_threadx_module_manager.icf @@ -7,7 +7,7 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; define symbol __ICFEDIT_region_ROM_start__ = 0x00000040; define symbol __ICFEDIT_region_ROM_end__ = 0x000FFFFF; //Module in 0x00100000-0x0013FFFF define symbol __ICFEDIT_region_RAM_start__ = 0x08000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x081FFFFF; +define symbol __ICFEDIT_region_RAM_end__ = 0x081FFFFF; /*-Sizes-*/ define symbol __ICFEDIT_size_cstack__ = 0x200; define symbol __ICFEDIT_size_svcstack__ = 0x100; @@ -33,7 +33,7 @@ define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; -define block PAGE_ALIGN with alignment = 4096 { section page_align }; +define block PAGE_ALIGN with alignment = 4096 { section page_align }; initialize by copy { readwrite }; initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application diff --git a/ports_module/cortex_a7/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_a7/iar/example_build/tx_initialize_low_level.s index 28ca3030..d3795786 100644 --- a/ports_module/cortex_a7/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_a7/iar/example_build/tx_initialize_low_level.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -62,7 +62,7 @@ SYS_MODE DEFINE 0x1F ; Disable irq,fiq SYS mode ; ; ; -;/* Define the FREE_MEM segment that will specify where free memory is +;/* Define the FREE_MEM segment that will specify where free memory is ; defined. This must also be located in at the end of other RAM segments ; in the linker control file. The value of this segment is what is passed ; to tx_application_define. */ @@ -75,48 +75,39 @@ __tx_free_memory_start ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-A7/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -149,7 +140,7 @@ _tx_initialize_low_level ; LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address STR r0, [r2, #0] ; Save first free memory address -; +; ; /* Setup Timer for periodic interrupts. */ ; ; /* Done, return to caller. */ @@ -177,7 +168,7 @@ __tx_reserved_handler RSEG .text:CODE:NOROOT(2) PUBLIC __tx_irq_handler RSEG .text:CODE:NOROOT(2) - PUBLIC __tx_irq_processing_return + PUBLIC __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -185,17 +176,17 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -210,7 +201,7 @@ __tx_irq_processing_return ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -229,22 +220,22 @@ __tx_irq_processing_return ; /* Jump to context save to save system context. */ ; STMDB sp!, {r0-r3} ; Save some scratch registers ; MRS r0, SPSR ; Pickup saved SPSR -; SUB lr, lr, #4 ; Adjust point of interrupt +; SUB lr, lr, #4 ; Adjust point of interrupt ; STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; BL _tx_thread_vectored_context_save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ;#ifdef TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_start @@ -253,7 +244,7 @@ __tx_irq_processing_return ; /* Application IRQ handler is called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ;#ifdef TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_end @@ -277,11 +268,11 @@ __tx_fiq_processing_return ; /* At this point execution is still in the FIQ mode. The CPSR, point of ; interrupt, and all C scratch registers are available for use. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start ; from FIQ mode with interrupts disabled. This routine switches to the -; system mode and returns with FIQ interrupts enabled. +; system mode and returns with FIQ interrupts enabled. ; -; NOTE: It is very important to ensure all FIQ interrupts are cleared +; NOTE: It is very important to ensure all FIQ interrupts are cleared ; prior to enabling nested FIQ interrupts. */ #ifdef TX_ENABLE_FIQ_NESTING BL _tx_thread_fiq_nesting_start @@ -307,41 +298,41 @@ __tx_fiq_handler #endif -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* __tx_prefetch_handler & __tx_abort_handler Cortex-A7/MMU/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* __tx_prefetch_handler & __tx_abort_handler Cortex-A7/MMU/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function handles MMU exceptions and fills the */ -;/* _txm_module_manager_memory_fault_info struct. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _txm_module_manager_memory_fault_handler */ -;/* _tx_execution_thread_exit */ -;/* _tx_thread_schedule */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* MMU exceptions */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function handles MMU exceptions and fills the */ +;/* _txm_module_manager_memory_fault_info struct. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _txm_module_manager_memory_fault_handler */ +;/* _tx_execution_thread_exit */ +;/* _tx_thread_schedule */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* MMU exceptions */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 Scott Larson Initial Version 6.1 */ @@ -389,7 +380,7 @@ __tx_abort_handler STR r0, [r3, #16] ; Save IFAR MRC p15, 0, r0, c5, c0, 1 ; Read IFSR STR r0, [r3, #20] ; Save IFSR - + ; Save registers r0-r12 POP {r0-r2} STR r0, [r3, #28] ; Save r0 @@ -406,7 +397,7 @@ __tx_abort_handler STR r10,[r3, #68] ; Save r10 STR r11,[r3, #72] ; Save r11 STR r12,[r3, #76] ; Save r12 - + CPS #SYS_MODE ; Enter SYS mode MOV r0, lr ; Pickup lr MOV r1, sp ; Pickup sp @@ -418,7 +409,7 @@ __tx_abort_handler ORR r0, r0, #SYS_MODE ; Return into SYS mode BIC r0, r0, #THUMB_MASK ; Clear THUMB mode MSR SPSR_c, r0 ; Save SPSR - + ; Call memory manager fault handler BL _txm_module_manager_memory_fault_handler @@ -433,11 +424,11 @@ __tx_abort_handler LDR r1, [r0] ; Pickup system state SUB r1, r1, #1 ; Decrement STR r1, [r0] ; Store new system state - + MOV r1, #0 ; Build NULL value LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer STR r1, [r0] ; Clear current thread pointer - + ; Return from exception LDR lr, =_tx_thread_schedule ; Load scheduler address MOVS pc, lr ; Return to scheduler diff --git a/ports_module/cortex_a7/iar/example_build/txm_module_preamble.s b/ports_module/cortex_a7/iar/example_build/txm_module_preamble.s index 343d2a6b..4a42627b 100644 --- a/ports_module/cortex_a7/iar/example_build/txm_module_preamble.s +++ b/ports_module/cortex_a7/iar/example_build/txm_module_preamble.s @@ -26,7 +26,7 @@ __txm_module_preamble: DC32 0x6 ; Module Major Version DC32 0x1 ; Module Minor Version DC32 32 ; Module Preamble Size in 32-bit words - DC32 0x12345678 ; Module ID (application defined) + DC32 0x12345678 ; Module ID (application defined) DC32 0x00000001 ; Module Properties where: ; Bits 31-24: Compiler ID ; 0 -> IAR @@ -41,23 +41,23 @@ __txm_module_preamble: ; 1 -> User mode execution DC32 _txm_module_thread_shell_entry - . - 0 ; Module Shell Entry Point DC32 demo_module_start - . - 0 ; Module Start Thread Entry Point - DC32 0 ; Module Stop Thread Entry Point + DC32 0 ; Module Stop Thread Entry Point DC32 1 ; Module Start/Stop Thread Priority DC32 1022 ; Module Start/Stop Thread Stack Size DC32 _txm_module_callback_request_thread_entry - . - 0 ; Module Callback Thread Entry - DC32 1 ; Module Callback Thread Priority - DC32 1022 ; Module Callback Thread Stack Size + DC32 1 ; Module Callback Thread Priority + DC32 1022 ; Module Callback Thread Stack Size DC32 ROPI$$Length ; Module Code Size DC32 RWPI$$Length ; Module Data Size - DC32 0 ; Reserved 0 + DC32 0 ; Reserved 0 DC32 0 ; Reserved 1 DC32 0 ; Reserved 2 DC32 0 ; Reserved 3 DC32 0 ; Reserved 4 - DC32 0 ; Reserved 5 - DC32 0 ; Reserved 6 - DC32 0 ; Reserved 7 - DC32 0 ; Reserved 8 + DC32 0 ; Reserved 5 + DC32 0 ; Reserved 6 + DC32 0 ; Reserved 7 + DC32 0 ; Reserved 8 DC32 0 ; Reserved 9 DC32 0 ; Reserved 10 DC32 0 ; Reserved 11 diff --git a/ports_module/cortex_a7/iar/inc/tx_port.h b/ports_module/cortex_a7/iar/inc/tx_port.h index 3270eabe..fd21d57b 100644 --- a/ports_module/cortex_a7/iar/inc/tx_port.h +++ b/ports_module/cortex_a7/iar/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Cortex-A7/IAR */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A7/IAR */ /* 6.3.0 */ /* */ /* AUTHOR */ @@ -32,27 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 10-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -65,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -82,7 +71,7 @@ #endif -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -118,12 +107,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -133,8 +122,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -190,7 +179,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_INLINE_INITIALIZATION #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -204,11 +193,11 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ VOID *tx_thread_module_instance_ptr; \ @@ -239,7 +228,7 @@ ULONG _tx_misra_time_stamp_get(VOID); ULONG tx_thread_module_stack_size; \ VOID *tx_thread_module_reserved; #endif -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -259,11 +248,11 @@ ULONG _tx_misra_time_stamp_get(VOID); VOID (*tx_timer_module_expiration_function)(ULONG id); -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -273,23 +262,23 @@ ULONG _tx_misra_time_stamp_get(VOID); #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #if (__VER__ < 8000000) -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #endif #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -322,20 +311,20 @@ void __iar_Initlocks(void); #ifndef TX_DISABLE_INLINE #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (UINT) __CLZ(m); \ - b = 31 - b; + b = 31 - b; #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ /* First, check and see what mode the file is being compiled in. The IAR compiler - defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode + defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode is present. If ARM 32-bit mode is present, the fast CPSR manipulation macros are available. Otherwise, if Thumb mode is present, we must use function calls. */ @@ -393,7 +382,7 @@ void _tx_thread_interrupt_restore(UINT old_posture); thread. */ void tx_thread_vfp_enable(void); -void tx_thread_vfp_disable(void); +void tx_thread_vfp_disable(void); /* Define the interrupt lockout macros for each ThreadX object. */ @@ -409,8 +398,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-A7/IAR Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A7/IAR Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_a7/iar/inc/txm_module_port.h b/ports_module/cortex_a7/iar/inc/txm_module_port.h index 81a8eb17..247868ea 100644 --- a/ports_module/cortex_a7/iar/inc/txm_module_port.h +++ b/ports_module/cortex_a7/iar/inc/txm_module_port.h @@ -1,48 +1,40 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Interface (API) */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Interface (API) */ +/** */ +/**************************************************************************/ +/**************************************************************************/ -/**************************************************************************/ -/* */ -/* APPLICATION INTERFACE DEFINITION RELEASE */ -/* */ -/* txm_module_port.h Cortex-A7/MMU/IAR */ +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-A7/MMU/IAR */ /* 6.3.0 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This file defines the basic module constants, interface structures, */ -/* and function prototypes. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-31-2023 Yajun Xia Modified comment(s), */ -/* Added thumb mode support, */ -/* resulting in version 6.3.0 */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ /* */ /**************************************************************************/ @@ -54,13 +46,13 @@ #ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in txm_module_user.h. The defines in this file may +/* Yes, include the user defines in txm_module_user.h. The defines in this file may alternately be defined on the command line. */ #include "txm_module_user.h" #endif -/* It is assumed that the base ThreadX tx_port.h file has been modified to add the +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the following extensions to the ThreadX thread control block (this code should replace the corresponding macro define in tx_port.h): @@ -100,10 +92,10 @@ The following extensions must also be defined in tx_port.h: #endif /* Defined, this option enables the MMU hardware and requires memory protected - module objects to be allocated from the module manager object pool. - If this is undefined, module objects can be created in the module's data area - or in the module manager object pool. If this is not defined (MMU hardware - is disabled), a module requiring memory protection will not run (the load + module objects to be allocated from the module manager object pool. + If this is undefined, module objects can be created in the module's data area + or in the module manager object pool. If this is not defined (MMU hardware + is disabled), a module requiring memory protection will not run (the load functions will return a TXM_MODULE_INVALID_PROPERTIES error). Default setting for this value is defined. */ #define TXM_MODULE_MEMORY_PROTECTION_ENABLED @@ -310,7 +302,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; /* Define the macro to check the stack available in dispatch. */ -#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE +#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE /* Define the macro to check the code alignment. */ @@ -420,7 +412,7 @@ UINT _txm_module_manager_inside_data_check(ULONG pointer); #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-A7/MMU/iar Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-A7/MMU/iar Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_a7/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_a7/iar/module_lib/src/txm_module_thread_shell_entry.c index e34fdbea..cfe18ef1 100644 --- a/ports_module/cortex_a7/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_a7/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -88,12 +89,6 @@ extern VOID __iar_data_init3(VOID); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_iar.c b/ports_module/cortex_a7/iar/module_manager/src/tx_iar.c index 158738ea..238b485e 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_iar.c +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_iar.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** IAR Multithreaded Library Support */ /** */ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_context_restore.s index 2d4a1428..bf3c0e54 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_context_restore.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; @@ -39,47 +39,38 @@ SYS_MODE EQU 0x1F ; SYS mode ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore Cortex-A7/MMU/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-A7/MMU/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -183,7 +174,7 @@ restore_and_return_from_irq: ; /* The reason for adding this segment is that IAR's simulator ; may not handle PC-relative instructions correctly in thumb mode.*/ STR lr, [sp, #-8] - MRS lr, SPSR + MRS lr, SPSR STR lr, [sp, #-4] SUB lr, sp, #8 RFE lr diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_context_save.s index 51d17e4d..139ae048 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,46 +29,37 @@ ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-A7/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_context_restore.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_context_restore.s index 77425a1e..2e5370ec 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_context_restore.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -21,7 +21,7 @@ SVC_MODE EQU 0xD3 ; SVC mode FIQ_MODE EQU 0xD1 ; FIQ mode -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; ; @@ -36,47 +36,38 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits EXTERN _tx_execution_isr_exit #endif -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_restore Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore Cortex-A7/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the fiq interrupt context when processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* FIQ ISR Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) @@ -108,13 +99,13 @@ _tx_thread_fiq_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3] ; Store the counter + STR r2, [r3] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; POP {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -125,7 +116,7 @@ _tx_thread_fiq_context_restore ; /* The reason for adding this segment is that IAR's simulator ; may not handle PC-relative instructions correctly in thumb mode.*/ STR lr, [sp, #-8] - MRS lr, SPSR + MRS lr, SPSR STR lr, [sp, #-4] SUB lr, sp, #8 RFE lr @@ -169,7 +160,7 @@ __tx_thread_fiq_no_preempt_restore ; /* Restore interrupted thread or ISR. */ ; ; /* Pickup the saved stack pointer. */ -; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; ; ; /* Recover the saved context and return to the point of interrupt. */ ; @@ -181,7 +172,7 @@ __tx_thread_fiq_no_preempt_restore ; /* The reason for adding this segment is that IAR's simulator ; may not handle PC-relative instructions correctly in thumb mode.*/ STR lr, [sp, #-8] - MRS lr, SPSR + MRS lr, SPSR STR lr, [sp, #-4] SUB lr, sp, #8 RFE lr @@ -225,7 +216,7 @@ _tx_skip_fiq_vfp_save MOV r3, #1 ; Build interrupt stack type PUSH {r3, r4} ; Save interrupt stack type and SPSR STR sp, [r0, #8] ; Save stack pointer in thread control - ; block + ; block ; ; /* Save the remaining time-slice and disable it. */ ; if (_tx_timer_time_slice) @@ -237,7 +228,7 @@ _tx_skip_fiq_vfp_save BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it ; ; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; -; _tx_timer_time_slice = 0; +; _tx_timer_time_slice = 0; ; STR r2, [r0, #24] ; Save thread's time-slice MOV r2, #0 ; Clear value diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_context_save.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_context_save.s index 36330436..925c5261 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_context_save.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -26,46 +26,37 @@ EXTERN _tx_execution_isr_enter #endif -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_context_save Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save Cortex-A7/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) @@ -86,7 +77,7 @@ _tx_thread_fiq_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state CMP r2, #0 ; Is this the first interrupt? @@ -101,7 +92,7 @@ _tx_thread_fiq_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -117,38 +108,38 @@ _tx_thread_fiq_context_save POP {lr} ; Recover ISR lr #endif - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; __tx_thread_fiq_not_nested_save -; } +; } ; ; /* Otherwise, not nested, check to see if a thread was running. */ ; else if (_tx_thread_current_ptr) -; { +; { ; ADD r2, r2, #1 ; Increment the interrupt counter STR r2, [r3] ; Store it back in the variable LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in -; ; scheduling loop - nothing needs saving! + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, lr} ; Store other registers, Note that we don't -; ; need to save sl and ip since FIQ has -; ; copies of these registers. Nested +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested ; ; interrupt processing does need to save ; ; these registers. ; ; /* Save the current stack pointer in the thread's control block. */ -; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; ; ; /* Switch to the system stack. */ -; sp = _tx_thread_system_stack_ptr; +; sp = _tx_thread_system_stack_ptr; ; MOV r10, #0 ; Clear stack limit @@ -161,7 +152,7 @@ __tx_thread_fiq_not_nested_save POP {lr} ; Recover ISR lr #endif - B __tx_fiq_processing_return ; Continue FIQ processing + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } ; else @@ -181,18 +172,18 @@ __tx_thread_fiq_idle_system_save #endif ; ; /* Not much to do here, save the current SPSR and LR for possible -; use in IRQ interrupted in idle system conditions, and return to +; use in IRQ interrupted in idle system conditions, and return to ; FIQ interrupt processing. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, lr} ; Store other registers that will get used -; ; or stripped off the stack in context -; ; restore - B __tx_fiq_processing_return ; Continue FIQ processing +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing ; ; } -;} +;} ; END diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_nesting_end.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_nesting_end.s index fe49fea3..d9e92fc4 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_nesting_end.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -24,57 +24,48 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts #else DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts #endif -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_end Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end Cortex-A7/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ -;/* processing from system mode back to FIQ mode prior to the ISR */ -;/* calling _tx_thread_fiq_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with FIQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) @@ -91,7 +82,7 @@ _tx_thread_fiq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_c, r0 ; Disable interrupts - LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_nesting_start.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_nesting_start.s index 75e6b0d7..bde34045 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_nesting_start.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_fiq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -23,51 +23,42 @@ FIQ_DISABLE EQU 0x40 ; FIQ disable bit MODE_MASK EQU 0x1F ; Mode mask SYS_MODE_BITS EQU 0x1F ; System mode bits -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_fiq_nesting_start Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start Cortex-A7/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from FIQ mode after */ -;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ -;/* processing to the system mode so nested FIQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with FIQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_control.s index 94c42a69..1840fb85 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -28,45 +28,36 @@ FIQ_MASK EQU 0x40 ; Interrupt bit mask ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-A7/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_disable.s index 1bbbe754..f965666f 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -21,44 +21,35 @@ -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-A7/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(VOID) @@ -81,7 +72,7 @@ _tx_thread_interrupt_disable #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if ; Disable IRQ and FIQ #else - CPSID i ; Disable IRQ + CPSID i ; Disable IRQ #endif BX lr ; Return to caller diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_restore.s index 65df8b7e..6292bbd6 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -25,45 +25,36 @@ IRQ_MASK EQU 0x80 ; Interrupt bit mask FIQ_MASK EQU 0x40 ; Interrupt bit mask #endif -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-A7/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function is responsible for restoring interrupts to the state */ ;/* returned by a previous _tx_thread_interrupt_disable call. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;void _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_irq_nesting_end.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_irq_nesting_end.s index cbee12f2..ac26b693 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_irq_nesting_end.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_irq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -27,59 +27,50 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts #else DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts #endif -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_end Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-A7/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -;/* processing from system mode back to IRQ mode prior to the ISR */ -;/* calling _tx_thread_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) @@ -96,7 +87,7 @@ _tx_thread_irq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_c, r0 ; Disable interrupts - LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_irq_nesting_start.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_irq_nesting_start.s index 96a7fed4..3c7a5ec1 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_irq_nesting_start.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_irq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -26,51 +26,42 @@ MODE_MASK EQU 0x1F ; Mode mask SYS_MODE_BITS EQU 0x1F ; System mode bits -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_start Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-A7/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_context_save has been called and switches the IRQ */ -;/* processing to the system mode so nested IRQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_schedule.s index 4b92a25b..3b446f04 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_schedule.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; EXTERN _tx_thread_execute_ptr @@ -26,7 +26,7 @@ #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) EXTERN _tx_execution_thread_enter #endif - + IRQ_MODE EQU 0xD2 ; IRQ mode USR_MODE EQU 0x10 ; USR mode SVC_MODE EQU 0x13 ; SVC mode @@ -38,7 +38,7 @@ IRQ_MASK EQU 0x80 ; Interrupt bit mask FIQ_MASK EQU 0x40 ; Interrupt bit mask #endif -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask THUMB_MASK EQU 0x20 ; Thumb bit mask EXTERN _txm_system_mode_enter @@ -47,48 +47,39 @@ THUMB_MASK EQU 0x20 ; Thumb bit mask -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule Cortex-A7/MMU/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-A7/MMU/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -161,11 +152,11 @@ _tx_handler_svc_unrecognized BKPT 0x0000 _tx_handler_svc_unrecognized_loop ; We should never get here B _tx_handler_svc_unrecognized_loop - + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; SVC 1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - ; At this point we have an SVC 1, which means we are entering + ; At this point we have an SVC 1, which means we are entering ; supervisor mode to service a kernel call. _tx_handler_svc_super_enter ; Make sure that we have been called from the system mode enter location (security) @@ -213,7 +204,7 @@ _tx_handler_svc_super_enter ; /* The reason for adding this segment is that IAR's simulator ; may not handle PC-relative instructions correctly in thumb mode.*/ STR lr, [sp, #-8] - MRS lr, SPSR + MRS lr, SPSR STR lr, [sp, #-4] SUB lr, sp, #8 RFE lr @@ -228,7 +219,7 @@ _tx_handler_svc_super_enter ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; SVC 2 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - ; At this point we have an SVC 2, which means we are exiting + ; At this point we have an SVC 2, which means we are exiting ; supervisor mode after servicing a kernel call. _tx_handler_svc_super_exit: ; Make sure that we have been called from the system mode exit location (security) @@ -266,14 +257,14 @@ _tx_handler_svc_super_exit: LDRD r0, r1, [r2, #0xB4] ; Load the module thread stack start and end STRD r0, r1, [r2, #0x0C] ; Set stack start and end #endif - + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ARM Semihosting ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; _tx_handler_svc_arm - + ; *** TODO: handle semihosting requests or ARM angel requests *** - + ; Restore the registers and return #if defined(THUMB_MODE) POP {r0-r3, r12, lr} @@ -282,7 +273,7 @@ _tx_handler_svc_arm ; /* The reason for adding this segment is that IAR's simulator ; may not handle PC-relative instructions correctly in thumb mode.*/ STR lr, [sp, #-8] - MRS lr, SPSR + MRS lr, SPSR STR lr, [sp, #-4] SUB lr, sp, #8 RFE lr @@ -303,8 +294,8 @@ _tx_handler_svc_schedule POP {r0-r3, r12, lr} ; Restore the registers - ; This code waits for a thread control block pointer to appear in - ; the _tx_thread_execute_ptr variable. Once a thread pointer appears + ; This code waits for a thread control block pointer to appear in + ; the _tx_thread_execute_ptr variable. Once a thread pointer appears ; in the variable, the corresponding thread is resumed. ; ; /* Enable interrupts. */ @@ -407,10 +398,10 @@ __tx_thread_schedule_loop ; test address translation ;mcr p15, 0, r0, c7, c8, 0 - + _tx_skip_mmu_update ; ************************************************************************** - + CMP r4, #0 ; Check for synchronous context switch BEQ _tx_solicited_return @@ -442,7 +433,7 @@ _tx_skip_interrupt_vfp_restore ; /* The reason for adding this segment is that IAR's simulator ; may not handle PC-relative instructions correctly in thumb mode.*/ STR lr, [sp, #-8] - MRS lr, SPSR + MRS lr, SPSR STR lr, [sp, #-4] SUB lr, sp, #8 RFE lr @@ -453,7 +444,7 @@ _tx_skip_interrupt_vfp_restore _tx_solicited_return MOV r2, r5 ; Move CPSR to scratch register CPS #SYS_MODE ; Enter SYS mode - + #ifdef __ARMVFP__ LDR r1, [r0, #144] ; Pickup the VFP enabled flag CMP r1, #0 ; Is the VFP enabled? @@ -464,7 +455,7 @@ _tx_solicited_return VMSR FPSCR, r4 ; Restore FPSCR _tx_skip_solicited_vfp_restore #endif - + POP {r4-r11, lr} ; Restore registers MOV r1, lr ; Copy lr to r1 to preserve across mode change CPS #SVC_MODE ; Enter SVC mode @@ -475,7 +466,7 @@ _tx_skip_solicited_vfp_restore ; /* The reason for adding this segment is that IAR's simulator ; may not handle PC-relative instructions correctly in thumb mode.*/ STR lr, [sp, #-8] - MRS lr, SPSR + MRS lr, SPSR STR lr, [sp, #-4] SUB lr, sp, #8 RFE lr @@ -486,7 +477,7 @@ _tx_skip_solicited_vfp_restore ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; End SWI_Handler ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - + #ifdef __ARMVFP__ PUBLIC tx_thread_vfp_enable #ifdef THUMB_MODE diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_stack_build.s index fc692efc..09cecfa8 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_stack_build.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ SVC_MODE EQU 0x13 ; SVC mode SYS_MODE EQU 0x1F ; SYS mode @@ -31,47 +31,38 @@ THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR EXTERN _tx_thread_schedule -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build Cortex-A7/MMU/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-A7/MMU/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function builds a stack frame on the supplied thread's stack. */ -;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Pointer to thread control blk */ -;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -85,10 +76,10 @@ THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR #endif _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-A7 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; a1 (r0) Initial value for a1 diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_system_return.s index 6307c693..f22ca01c 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_system_return.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -23,50 +23,41 @@ EXTERN _tx_timer_time_slice EXTERN _tx_thread_schedule #if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE)) - EXTERN _tx_execution_thread_exit + EXTERN _tx_execution_thread_exit #endif -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-A7/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_vectored_context_save.s b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_vectored_context_save.s index a4c6b041..dcd4ed95 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_thread_vectored_context_save.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_thread_vectored_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -25,46 +25,37 @@ EXTERN _tx_execution_isr_enter #endif -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_vectored_context_save Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-A7/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) @@ -127,7 +118,7 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Note: Minimal context of interrupted thread is already saved. */ @@ -150,12 +141,12 @@ __tx_thread_not_nested_save #endif BX lr ; Return to caller - + __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports_module/cortex_a7/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_a7/iar/module_manager/src/tx_timer_interrupt.s index fd2c46b9..8580a4c7 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_a7/iar/module_manager/src/tx_timer_interrupt.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -33,49 +33,40 @@ ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt Cortex-A7/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-A7/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -105,7 +96,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CMP r2, #0 ; Is it non-active? BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing @@ -223,13 +214,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CMP r2, #0 ; See if the flag is set BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing ; diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_alignment_adjust.c index e22cfc63..e8107c19 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,23 +1,24 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -25,45 +26,39 @@ #include "txm_module.h" -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_alignment_adjust Cortex-A7/MMU/IAR */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-A7/MMU/IAR */ /* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function adjusts the alignment and size of the code and data */ -/* section for a given module implementation. */ -/* */ -/* INPUT */ -/* */ -/* code_size Size of the code area (updated) */ -/* code_alignment Code area alignment (updated) */ -/* data_size Size of data area (updated) */ -/* data_alignment Data area alignment (updated) */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Initial thread stack frame */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment) diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_external_memory_enable.c index 08ab19f7..5361822c 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,12 +65,6 @@ extern ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_EN /* */ /* _txm_module_manager_external_memory_enable */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ ULONG _txm_level2_page_get(TXM_MODULE_INSTANCE *module_instance, ULONG *page_addr) { diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index 94e6e502..46d39bee 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index 32911033..c0a87261 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,23 +1,24 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -33,51 +34,45 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_memory_fault_notify Cortex-A7/MMU/IAR */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-A7/MMU/IAR */ /* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function registers an application callback when/if a memory */ -/* fault occurs. The supplied thread is automatically terminated, but */ -/* any other threads in the same module may still execute. */ -/* */ -/* INPUT */ -/* */ -/* notify_function Memory fault notification */ -/* function, NULL disables. */ -/* */ -/* OUTPUT */ -/* */ -/* status Completion status */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_mm_initialize.c b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_mm_initialize.c index ad70a286..e76ae60a 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_mm_initialize.c +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_mm_initialize.c @@ -1,23 +1,24 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -52,50 +53,44 @@ TXM_MODULE_INSTANCE *_txm_asid_table[TXM_ASID_TABLE_LENGTH]; ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_ENTRIES]; /* Module start and end level 2 page tables, 2^10 (1kB) alignment. - * First set of 4 tables are the master level 2 tables, the rest are for each module. + * First set of 4 tables are the master level 2 tables, the rest are for each module. * Each module needs two L2 tables for code and two L2 tables for data. */ -#pragma data_alignment=1024 +#pragma data_alignment=1024 ULONG _txm_level2_module_page_table[TXM_MAXIMUM_MODULES * 4][TXM_LEVEL_2_PAGE_TABLE_ENTRIES]; /* Module external memory level 2 page tables, 2^10 (1kB) alignment. */ -#pragma data_alignment=1024 +#pragma data_alignment=1024 ULONG _txm_level2_external_page_pool[TXM_LEVEL2_EXTERNAL_POOL_PAGES][TXM_LEVEL_2_PAGE_TABLE_ENTRIES]; -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_mm_initialize Cortex-A7/MMU/IAR */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_initialize Cortex-A7/MMU/IAR */ /* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function performs the initial set up of the the A7 MMU. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* Completion Status */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* This function performs the initial set up of the the A7 MMU. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ /* */ /**************************************************************************/ UINT _txm_module_manager_mm_initialize(VOID) @@ -106,53 +101,53 @@ UINT _txm_module_manager_mm_initialize(VOID) ULONG cp15reg; UINT user_mode_index; UINT counter_limit; - + /* Clear ASID table. */ for (i = 0; i < TXM_ASID_TABLE_LENGTH; i++) { _txm_asid_table[i] = 0; } _txm_asid_table[0] = (TXM_MODULE_INSTANCE *)TXM_ASID_RESERVED; - - + + /********************************************************************************/ /* This is an example showing how to set up the cache attributes. */ /********************************************************************************/ /******************************************************************************* -* PAGE TABLE generation -* Generate the page tables -* Build a flat translation table for the whole address space. -* ie: Create 4096 1MB sections from 0x000xxxxx to 0xFFFxxxxx +* PAGE TABLE generation +* Generate the page tables +* Build a flat translation table for the whole address space. +* ie: Create 4096 1MB sections from 0x000xxxxx to 0xFFFxxxxx * 31 20|19 18|17|16| 15|14 12|11 10|9|8 5|4 |3 2|1 0| * |base address | 0 0|nG| S|AP2|TEX |AP |P|Domain|XN|CB |1 0| * -* Bits[31:20] - Top 12 bits of VA is pointer into table +* Bits[31:20] - Top 12 bits of VA is pointer into table * nG[17]=0 - Non global, enables matching against ASID in the TLB when set. * S[16]=0 - Indicates normal memory is shared when set. -* AP2[15]=0 +* AP2[15]=0 * TEX[14:12]=000 -* AP[11:10]=11 - Configure for full read/write access in all modes +* AP[11:10]=11 - Configure for full read/write access in all modes * IMPP[9]=0 - Ignored * Domain[5:8]=1111 - Set all pages to use domain 15 * XN[4]=0 - Execute never disabled -* CB[3:2]= 00 - Set attributes to Strongly-ordered memory. -* (except for the descriptor where code segment is based, -* see below) -* Bits[1:0]=10 - Indicate entry is a 1MB section +* CB[3:2]= 00 - Set attributes to Strongly-ordered memory. +* (except for the descriptor where code segment is based, +* see below) +* Bits[1:0]=10 - Indicate entry is a 1MB section *******************************************************************************/ /* ---- Parameter setting to level1 descriptor (bits 19:0) ---- */ -/* setting for Strongly-ordered memory +/* setting for Strongly-ordered memory B-00000000000000000000010111100010 */ #define TTB_PARA_STRGLY 0x05E2 -/* setting for Outer and inner not cache normal memory +/* setting for Outer and inner not cache normal memory B-00000000000000000001010111100010 */ #define TTB_PARA_NORMAL_NOT_CACHE 0x15E2 -/* setting for Outer and inner write back, write allocate normal memory - (Cacheable) +/* setting for Outer and inner write back, write allocate normal memory + (Cacheable) B-00000000000000000001010111101110 */ #define TTB_PARA_NORMAL_CACHE 0x15EE //0x15EE @@ -170,98 +165,98 @@ UINT _txm_module_manager_mm_initialize(VOID) #define M_SIZE_RAM_M 10 /* [Area10] Internal RAM (mirror) */ #define M_SIZE_IO_2 2550 /* [Area11] I/O area 2 */ /* Should add to: 4096 */ - + counter_limit = M_SIZE_NOR; for (i = 0; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; } - + counter_limit += M_SIZE_SDRAM; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; } - + counter_limit += M_SIZE_CS45; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; } - + counter_limit += M_SIZE_SPI; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; } - + counter_limit += M_SIZE_RAM; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; } - + counter_limit += M_SIZE_IO_1; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; } - + counter_limit += M_SIZE_NOR_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; } - + counter_limit += M_SIZE_SDRAM_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; } - + counter_limit += M_SIZE_CS45_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; } - + counter_limit += M_SIZE_SPI_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; } - + counter_limit += M_SIZE_RAM_M; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; } - + counter_limit += M_SIZE_IO_2; for (; i < counter_limit; i++) { _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; } - + /********************************************************************************/ /* This is the end of the example showing how to set up the cache attributes. */ /********************************************************************************/ - - + + /* Clear ASID. */ cp15reg = 0; asm volatile ("mcr p15, 0, %0, c13, c0, 1" : : "r"(cp15reg) : ); asm("isb"); - + /* Put the page table address in TTBR. */ cp15reg = (int)(VOID*)_txm_ttbr1_page_table; cp15reg |= TTBR0_ATTRIBUTES; asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r"(cp15reg) : ); - + /* Set the domain to client mode. */ cp15reg = DACR_CLIENT_MODE; asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r"(cp15reg) : ); - + /* Level 2 small page attributes: normal memory, cache & buffer enabled, priviledged access. */ #define TTB_LEVEL2_NORMAL_CACHE 0x05E @@ -271,7 +266,7 @@ UINT _txm_module_manager_mm_initialize(VOID) /* Attributes for user mode table entry in level 2 table. */ #define TTB_LEVEL2_USER_MODE_ENTRY 0x06E - + /* Set up Level 2 table for user to kernel mode entry trampoline. */ /* Find which table entry _txm_module_manager_user_mode_entry is in. */ user_mode_index = (ULONG)_txm_module_manager_user_mode_entry >> TXM_MMU_LEVEL1_PAGE_SHIFT; @@ -280,21 +275,21 @@ UINT _txm_module_manager_mm_initialize(VOID) { _txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = ((ULONG)_txm_module_manager_user_mode_entry & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | TTB_LEVEL2_NORMAL_CACHE; } - + /* Enter Level 2 table in to master table. */ _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] = ((ULONG)_txm_level2_module_page_table & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; - + /* Find level 2 entry that holds _txm_module_manager_user_mode_entry. */ user_mode_index = ((ULONG)_txm_module_manager_user_mode_entry & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT; - + /* Set attribute bits for the user mode entry page. */ _txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] = (_txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] & TTB_LEVEL2_AP_CLEAR_MASK) | TTB_LEVEL2_USER_MODE_ENTRY; - + /* Enable the MMU. */ asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r"(cp15reg) : : ); cp15reg |= 0x1; asm volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r"(cp15reg) : ); - + return(TX_SUCCESS); #else diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_mm_register_setup.c index 1a394c05..3d477a4a 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ extern ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_EN /* */ /* TXM_MODULE_MANAGER_DATA_POINTER_CHECK */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_inside_data_check(ULONG pointer) { diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_thread_stack_build.s index f0018aa0..cedcb217 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Module Manager */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module Manager */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR @@ -29,47 +29,38 @@ CPSR_MASK EQU 0xDF ; Mask initial CPSR, IRQ & FIQ i CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints enabled #endif -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _txm_module_manager_thread_stack_build Cortex-A7/MMU/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_thread_stack_build Cortex-A7/MMU/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function builds a stack frame on the supplied thread's stack. */ -;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Pointer to thread control blk */ -;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) @@ -86,7 +77,7 @@ _txm_module_manager_thread_stack_build ; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-A7 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; r0 Initial value for r0 diff --git a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_user_mode_entry.s b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_user_mode_entry.s index c3eb43da..f25a5ea0 100644 --- a/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_user_mode_entry.s +++ b/ports_module/cortex_a7/iar/module_manager/src/txm_module_manager_user_mode_entry.s @@ -1,66 +1,57 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Module Manager */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module Manager */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; EXTERN _txm_module_manager_kernel_dispatch - -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* tx Cortex-A7/MMU/IAR */ + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* tx Cortex-A7/MMU/IAR */ ;/* 6.3.0 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function allows modules to enter kernel mode. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* SVC 1 Enter kernel mode */ -;/* SVC 2 Exit kernel mode */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Modules in user mode */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ -;/* 10-31-2023 Yajun Xia Modified comment(s), */ -;/* Added thumb mode support, */ -;/* resulting in version 6.3.0 */ +;/* This function allows modules to enter kernel mode. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* SVC 1 Enter kernel mode */ +;/* SVC 2 Exit kernel mode */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Modules in user mode */ ;/* */ ;/**************************************************************************/ RSEG .text:CODE:NOROOT(2) @@ -100,10 +91,10 @@ _txm_system_mode_exit BX lr ; Return to the caller NOP NOP - + ; Fill up 4kB page. SECTION page_align:CONST:ROOT(2) - + _txm_module_manager_user_mode_end - + END diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/.cproject b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/.cproject index 22cf258d..8f5b0d96 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/.cproject +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/.cproject @@ -1,170 +1,170 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/exceptions.c b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/exceptions.c index ac700115..4723699c 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/exceptions.c +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/exceptions.c @@ -1,7 +1,7 @@ /* ** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ** Use, modification and redistribution of this file is subject to your possession of a -** valid End User License Agreement for the Arm Product of which these examples are part of +** valid End User License Agreement for the Arm Product of which these examples are part of ** and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/sample_threadx.c index 597f373c..13ffadba 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -81,42 +81,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -124,23 +124,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -243,11 +243,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -306,7 +306,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -359,7 +359,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/sample_threadx.scat index f093ce05..c307d211 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 0a4f183b..0c6c1e74 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,12 +75,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/.cproject b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/.cproject index 3f9e781c..7388640f 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/.cproject +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/.cproject @@ -1,218 +1,218 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/sample_threadx_module.c index f2647144..dcf73ef9 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -26,7 +26,7 @@ #define EXTERNAL_MEMORY (0x80000) -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -107,7 +107,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -123,7 +123,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -135,42 +135,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -178,23 +178,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -238,7 +238,7 @@ void thread_0_entry(ULONG thread_input) { UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -248,7 +248,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -296,18 +296,18 @@ UINT status; { /* Test external memory sharing. */ *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -366,7 +366,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -419,7 +419,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/txm_module_preamble.S index 1fcc5d15..71914151 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -2,7 +2,7 @@ .align 4 .syntax unified .section Init - + // Define public symbols .global __txm_module_preamble diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/.cproject index d89095b9..e3141bd8 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/.cproject +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/.cproject @@ -1,172 +1,172 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/exceptions.c b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/exceptions.c index ac700115..4723699c 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/exceptions.c +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/exceptions.c @@ -1,7 +1,7 @@ /* ** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ** Use, modification and redistribution of this file is subject to your possession of a -** valid End User License Agreement for the Arm Product of which these examples are part of +** valid End User License Agreement for the Arm Product of which these examples are part of ** and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat index f093ce05..c307d211 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index 210f0be0..4edcee3c 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -71,8 +71,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -92,22 +92,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); - + /* Enable a read/write shared memory region. */ txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -116,11 +116,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S index a9202a6e..dcc369ae 100644 --- a/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S +++ b/ports_module/cortex_m0+/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,12 +75,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_m0+/ac6/example_build/tx/.cproject b/ports_module/cortex_m0+/ac6/example_build/tx/.cproject index 0516ff74..1f5d07d9 100644 --- a/ports_module/cortex_m0+/ac6/example_build/tx/.cproject +++ b/ports_module/cortex_m0+/ac6/example_build/tx/.cproject @@ -1,166 +1,166 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_m0+/ac6/example_build/txm/.cproject b/ports_module/cortex_m0+/ac6/example_build/txm/.cproject index 1cf6986c..0b56c6d7 100644 --- a/ports_module/cortex_m0+/ac6/example_build/txm/.cproject +++ b/ports_module/cortex_m0+/ac6/example_build/txm/.cproject @@ -1,184 +1,184 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_m0+/ac6/inc/tx_port.h b/ports_module/cortex_m0+/ac6/inc/tx_port.h index c25eeac5..374db939 100644 --- a/ports_module/cortex_m0+/ac6/inc/tx_port.h +++ b/ports_module/cortex_m0+/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -61,7 +53,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -110,7 +102,7 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY +#ifndef TX_TIMER_THREAD_PRIORITY #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -121,8 +113,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0 /* Enable interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0x0a800024) @@ -151,7 +143,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -163,7 +155,7 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ #define TX_THREAD_EXTENSION_0 @@ -202,11 +194,11 @@ typedef unsigned short USHORT; VOID (*tx_timer_module_expiration_function)(ULONG id); -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -214,8 +206,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #ifdef TX_ENABLE_FPU_SUPPORT @@ -268,13 +260,13 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ _tx_misra_control_set(_tx_vfp_state); \ } - + #endif /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -347,7 +339,7 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro #else #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) -#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) #endif @@ -375,7 +367,7 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro /* Define the get system state macro. */ - + #ifndef TX_THREAD_GET_SYSTEM_STATE #ifndef TX_MISRA_ENABLE @@ -405,14 +397,14 @@ ULONG _tx_misra_ipsr_get(VOID); #endif -/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to prevent early scheduling on Cortex-M parts. */ - + #define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; -/* This ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* This ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -431,9 +423,9 @@ ULONG _tx_misra_ipsr_get(VOID); #ifndef TX_DISABLE_INLINE -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -482,7 +474,7 @@ unsigned int interrupt_save; interrupt_save = __get_primask_value(); __enable_interrupts(); __restore_interrupts(interrupt_save); - } + } } @@ -516,8 +508,8 @@ void tx_thread_fpu_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M0+/AC6 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0+/AC6 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_m0+/ac6/inc/txm_module_port.h b/ports_module/cortex_m0+/ac6/inc/txm_module_port.h index 7eaf5a31..4ad075ee 100644 --- a/ports_module/cortex_m0+/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m0+/ac6/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,12 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -375,6 +370,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M0+/AC6 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M0+/AC6 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m0+/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_m0+/ac6/module_lib/src/txm_module_initialize.S index dab2dc35..9e439c1f 100644 --- a/ports_module/cortex_m0+/ac6/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_m0+/ac6/module_lib/src/txm_module_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,12 +58,6 @@ /* */ /* _txm_module_thread_shell_entry Start module thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _txm_module_initialize(VOID) .global _txm_module_initialize diff --git a/ports_module/cortex_m0+/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m0+/ac6/module_lib/src/txm_module_thread_shell_entry.c index 09e323c0..13f57b8d 100644 --- a/ports_module/cortex_m0+/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m0+/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID _txm_module_initialize(VOID); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _txm_module_initialize(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_context_restore.S index a2021a26..28245b55 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,12 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_context_save.S index 24eeffb9..cfe953dc 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_control.S index 6100ed57..43bc635a 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_disable.S index 73d5a537..7a69a31e 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_restore.S index 656abc16..972a7ea5 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_schedule.S index a1559844..bc9e27f8 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_stack_build.S index a3892f1e..c8960eaf 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_system_return.S index 0c426bfb..15035d55 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m0+/ac6/module_manager/src/tx_timer_interrupt.S index d0825135..3195b970 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_alignment_adjust.c index c215277c..84f75cdf 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 256. */ if(size <= 256) return 256; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_external_memory_enable.c index 7cf1bf9b..ad1ceaeb 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,12 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -112,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -122,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; - + /* Calculate the region size. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -222,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -232,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -244,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; - + /* Calculate the region size. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c index 8cd0c9f5..7faeea6a 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c index 457734dc..84c26f46 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index bd14368c..83aae591 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { @@ -197,10 +192,10 @@ UINT srd_bit_index; { /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ block_size = block_size >> 3; - + /* Set SRD index into attribute register. */ srd_bit_index = 8; - + /* If subregion overlaps length, move to the next subregion. */ while(length > block_size) { @@ -212,7 +207,7 @@ UINT srd_bit_index; { srd_bit_index++; } - + /* Set unused subregion bits. */ while(srd_bit_index < 16) { @@ -220,7 +215,7 @@ UINT srd_bit_index; srd_bit_index++; } } - + return(srd_bits); } @@ -319,16 +314,16 @@ UINT i; /* Set the attributes, size (256 bytes) and enable bit. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(256) << 1) | TXM_ENABLE_REGION; /* End of kernel mode entry setup. */ - + /* Setup code protection. */ - + /* Initialize the MPU table index. */ mpu_table_index = 1; /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size will be distributed: @@ -336,7 +331,7 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 256. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) { @@ -346,7 +341,7 @@ UINT i; { block_size = _txm_power_of_two_block_size(code_size) >> 2; } - + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ else if (i == 2) { @@ -354,7 +349,7 @@ UINT i; code_size = code_size - (block_size << 1); block_size = _txm_power_of_two_block_size(code_size) >> 1; } - + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 256. */ else { @@ -363,10 +358,10 @@ UINT i; block_size = _txm_power_of_two_block_size(code_size); srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; /* Build the attribute-size register with permissions, SRD, size, enable. */ @@ -374,29 +369,29 @@ UINT i; /* Adjust the code address. */ code_address = code_address + block_size; - + /* Increment MPU table index. */ mpu_table_index++; } /* End of code protection. */ - + /* Setup data protection. */ - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Pickup data starting address and actual size. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -405,7 +400,7 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -413,7 +408,7 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to data size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 256. */ - + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) { @@ -423,7 +418,7 @@ UINT i; { block_size = _txm_power_of_two_block_size(data_size) >> 2; } - + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ else if (i == 2) { @@ -431,7 +426,7 @@ UINT i; data_size = data_size - (block_size << 1); block_size = _txm_power_of_two_block_size(data_size) >> 1; } - + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 256. */ else { @@ -440,10 +435,10 @@ UINT i; block_size = _txm_power_of_two_block_size(data_size); srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; /* Build the attribute-size register with permissions, SRD, size, enable. */ @@ -451,17 +446,17 @@ UINT i; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Increment MPU table index. */ mpu_table_index++; } - + /* Setup MPU for the remaining regions. */ while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) { /* Build the base address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; - + /* Increment MPU table index. */ mpu_table_index++; } @@ -487,11 +482,11 @@ UINT i; /* Setup the first region for the ThreadX trampoline code. */ /* Set base register to user mode entry, which is guaranteed to be at least 256-byte aligned. */ base_address_register = (ULONG) _txm_module_manager_user_mode_entry; - + /* Mask address to proper range, region 0, set Valid bit. */ base_address_register = (base_address_register & 0xFFFFFF00) | mpu_register | 0x10; module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; - + /* Attributes: read only, write-back, shareable, size 256 bytes, region enabled. */ module_instance -> txm_module_instance_mpu_registers[1] = 0x0607000F; @@ -504,7 +499,7 @@ UINT i; /* Setup values for code area. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Check if shared memory was set up. If so, only 3 entries are available for code protection. If not set up, 4 code entries are available. */ if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) @@ -516,7 +511,7 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 256. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) { @@ -526,7 +521,7 @@ UINT i; { block_size = _txm_power_of_two_block_size(code_size) >> 2; } - + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ else if (i == 2) { @@ -534,7 +529,7 @@ UINT i; code_size = code_size - (block_size << 1); block_size = _txm_power_of_two_block_size(code_size) >> 1; } - + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 256. */ else { @@ -543,57 +538,57 @@ UINT i; block_size = _txm_power_of_two_block_size(code_size); srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base address register. */ base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x06070001; - + /* Setup the MPU Base Address Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; /* Adjust the code address. */ code_address = code_address + block_size; - + /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } } - + /* Only 3 code entries available. */ else { /* Calculate block size, one code entry taken up by shared memory. */ block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { /* Build the base address register. */ base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Check if SRD bits need to be set. */ if (code_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x06070000; - + /* Is there still some code? If so set the region enable bit. */ if (code_size) { @@ -602,13 +597,13 @@ UINT i; } /* Setup the MPU Base Address Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - + /* Adjust the code address. */ code_address = code_address + block_size; - + /* Decrement the code size. */ if (code_size > block_size) { @@ -618,34 +613,34 @@ UINT i; { code_size = 0; } - + /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } - + /* Adjust indeces to pass over the shared memory entry. */ /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } - + /* Setup values for data area. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -654,46 +649,46 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) { /* Build the base address register. */ base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Check if SRD bits need to be set. */ if (data_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x13070000; - + /* Is there still some data? If so set the region enable bit. */ if (data_size) { /* Set the region enable bit. */ base_attribute_register = base_attribute_register | 0x1; } - + /* Setup the MPU Base Address Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Decrement the data size. */ if (data_size > block_size) { @@ -703,10 +698,10 @@ UINT i; { data_size = 0; } - + /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } @@ -768,7 +763,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index 7e04f022..5e8190ae 100644 --- a/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m0+/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/.cproject b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/.cproject index 63be6be1..f92a30da 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/.cproject +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/.cproject @@ -1,166 +1,166 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/cortexm_crt0.s b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/cortexm_crt0.s index d4cb1636..61ca8259 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/cortexm_crt0.s +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/cortexm_crt0.s @@ -66,7 +66,7 @@ crt0_ctor_loop: beq crt0_ctor_end ldr r2, [r0] add r0, #4 - push {r0-r1} + push {r0-r1} blx r2 pop {r0-r1} b crt0_ctor_loop @@ -88,7 +88,7 @@ start: /* when main returns, loop forever. */ crt0_exit_loop: b crt0_exit_loop - + /* Startup helper functions. */ @@ -124,4 +124,3 @@ memory_set_done: .section .stack, "wa", %nobits .section .stack_process, "wa", %nobits .section .heap, "wa", %nobits - \ No newline at end of file diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/sample_threadx.c index 597f373c..13ffadba 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -81,42 +81,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -124,23 +124,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -243,11 +243,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -306,7 +306,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -359,7 +359,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_initialize_low_level.S index f5090533..445f77cf 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -76,12 +77,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_simulator_startup.s b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_simulator_startup.s index 73692924..ef3d9314 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_simulator_startup.s +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx/tx_simulator_startup.s @@ -6,9 +6,9 @@ .global _vectors _vectors: - .word __stack_end__ - .word reset_handler - .word __tx_NMIHandler + .word __stack_end__ + .word reset_handler + .word __tx_NMIHandler .word __tx_HardfaultHandler .word MemManage_Handler .word BusFault_Handler @@ -20,7 +20,7 @@ _vectors: .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // .word __tx_DBGHandler .word 0 // Reserved - .word __tx_PendSVHandler + .word __tx_PendSVHandler .word __tx_SysTickHandler // Used by Threadx timer functionality .word __tx_BadHandler // Populate with user Interrupt handler .word __tx_BadHandler diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/.cproject b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/.cproject index 9dc7b2bb..8ceaed84 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/.cproject +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/.cproject @@ -1,178 +1,178 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/gcc_setup.s b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/gcc_setup.s index f055d1c5..013e5825 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/gcc_setup.s +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/gcc_setup.s @@ -16,7 +16,7 @@ _gcc_setup: mov r5,r0 /* Copy GOT table. */ - + ldr r0, =__got_load_start__ subs r0,r0,r3 add r0,r0,r5 @@ -44,13 +44,13 @@ flash_area: address_built: str r6, [r1] // Store in new GOT table adds r0, r0, #4 // Move to next entry - adds r1, r1, #4 // + adds r1, r1, #4 // b new_got_setup // Continue at the top of the loop got_setup_done: /* Copy initialised sections into RAM if required. */ - + ldr r0, =__data_load_start__ subs r0,r0,r3 add r0,r0,r5 @@ -61,9 +61,9 @@ got_setup_done: subs r2,r2,r4 add r2,r2,r9 bl crt0_memory_copy - + /* Zero bss. */ - + ldr r0, =__bss_start__ subs r0,r0,r4 add r0,r0,r9 @@ -87,12 +87,12 @@ got_setup_done: str r2, [r0] adds r0, r0, #4 str r1, [r0] - + /* Store other preserved registers. */ pop {r3-r7} mov lr, r8 bx lr // Return to caller - + .align 4 /* Startup helper functions. */ @@ -128,4 +128,4 @@ memory_set_done: /* Setup attibutes of heap section so it doesn't take up room in the elf file */ .section .heap, "wa", %nobits - + diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/sample_threadx_module.c index f2647144..dcf73ef9 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -26,7 +26,7 @@ #define EXTERNAL_MEMORY (0x80000) -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -107,7 +107,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -123,7 +123,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -135,42 +135,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -178,23 +178,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -238,7 +238,7 @@ void thread_0_entry(ULONG thread_input) { UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -248,7 +248,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -296,18 +296,18 @@ UINT status; { /* Test external memory sharing. */ *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -366,7 +366,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -419,7 +419,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/sample_threadx_module.ld b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/sample_threadx_module.ld index 1efc6ca1..96320525 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/sample_threadx_module.ld +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/sample_threadx_module.ld @@ -130,7 +130,7 @@ SECTIONS KEEP (*(.got*)) . = ALIGN(4); _egot = .; - } + } __got_end__ = __got_load_start__ + SIZEOF(.got); __rodata_load_start__ = ALIGN(__got_end__ , 4); @@ -140,7 +140,7 @@ SECTIONS *(.rodata .rodata.* .gnu.linkonce.r.*) } __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); - + __code_size__ = SIZEOF(.data) + __rodata_end__ - __FLASH_segment_start__; __fast_load_start__ = ALIGN(__rodata_end__ , 4); diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/txm_module_preamble.S index b296ed2a..8ea214ba 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module/txm_module_preamble.S @@ -2,7 +2,7 @@ .align 4 .syntax unified .section .preamble, "ax" - + // Define public symbols .global __txm_module_preamble .global __txm_module_preamble_two diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/.cproject index c243c1fd..d1a7a6cc 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/.cproject +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/.cproject @@ -1,174 +1,174 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/cortexm_crt0.s b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/cortexm_crt0.s index d4cb1636..61ca8259 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/cortexm_crt0.s +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/cortexm_crt0.s @@ -66,7 +66,7 @@ crt0_ctor_loop: beq crt0_ctor_end ldr r2, [r0] add r0, #4 - push {r0-r1} + push {r0-r1} blx r2 pop {r0-r1} b crt0_ctor_loop @@ -88,7 +88,7 @@ start: /* when main returns, loop forever. */ crt0_exit_loop: b crt0_exit_loop - + /* Startup helper functions. */ @@ -124,4 +124,3 @@ memory_set_done: .section .stack, "wa", %nobits .section .stack_process, "wa", %nobits .section .heap, "wa", %nobits - \ No newline at end of file diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index 283dc71a..f47155b8 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -72,8 +72,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -93,22 +93,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); - + /* Enable a read/write shared memory region. */ txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -117,11 +117,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_initialize_low_level.S index 663c92ba..4928d596 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_initialize_low_level.S +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -76,12 +77,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_simulator_startup.s b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_simulator_startup.s index 60662fe3..452c8934 100644 --- a/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_simulator_startup.s +++ b/ports_module/cortex_m0+/gnu/example_build/sample_threadx_module_manager/tx_simulator_startup.s @@ -6,9 +6,9 @@ .global _vectors _vectors: - .word __stack_end__ - .word reset_handler - .word __tx_NMIHandler + .word __stack_end__ + .word reset_handler + .word __tx_NMIHandler .word HardFaultException .word MemManage_Handler .word BusFault_Handler @@ -20,7 +20,7 @@ _vectors: .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // .word __tx_DBGHandler .word 0 // Reserved - .word __tx_PendSVHandler + .word __tx_PendSVHandler .word __tx_SysTickHandler // Used by Threadx timer functionality .word __tx_BadHandler // Populate with user Interrupt handler .word __tx_BadHandler diff --git a/ports_module/cortex_m0+/gnu/example_build/tx/.cproject b/ports_module/cortex_m0+/gnu/example_build/tx/.cproject index a1c0d7ab..4374ece6 100644 --- a/ports_module/cortex_m0+/gnu/example_build/tx/.cproject +++ b/ports_module/cortex_m0+/gnu/example_build/tx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_m0+/gnu/example_build/txm/.cproject b/ports_module/cortex_m0+/gnu/example_build/txm/.cproject index f04340b4..fcae5c35 100644 --- a/ports_module/cortex_m0+/gnu/example_build/txm/.cproject +++ b/ports_module/cortex_m0+/gnu/example_build/txm/.cproject @@ -1,168 +1,168 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_m0+/gnu/inc/tx_port.h b/ports_module/cortex_m0+/gnu/inc/tx_port.h index f2cc8240..0c2e90e5 100644 --- a/ports_module/cortex_m0+/gnu/inc/tx_port.h +++ b/ports_module/cortex_m0+/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -61,7 +53,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -125,7 +117,7 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY +#ifndef TX_TIMER_THREAD_PRIORITY #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -136,8 +128,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0 /* Enable interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0x0a800024) @@ -166,7 +158,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -178,7 +170,7 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ #define TX_THREAD_EXTENSION_0 @@ -217,19 +209,19 @@ typedef unsigned short USHORT; VOID (*tx_timer_module_expiration_function)(ULONG id); -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif /* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #ifdef TX_ENABLE_FPU_SUPPORT @@ -282,13 +274,13 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ _tx_misra_control_set(_tx_vfp_state); \ } - + #endif /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -361,7 +353,7 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro #else #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) -#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) #endif @@ -389,7 +381,7 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro /* Define the get system state macro. */ - + #ifndef TX_THREAD_GET_SYSTEM_STATE #ifndef TX_MISRA_ENABLE @@ -419,14 +411,14 @@ ULONG _tx_misra_ipsr_get(VOID); #endif -/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to prevent early scheduling on Cortex-M parts. */ - + #define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; -/* This ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* This ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -445,9 +437,9 @@ ULONG _tx_misra_ipsr_get(VOID); #ifndef TX_DISABLE_INLINE -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -496,7 +488,7 @@ unsigned int interrupt_save; interrupt_save = __get_primask_value(); __enable_interrupts(); __restore_interrupts(interrupt_save); - } + } } @@ -530,8 +522,8 @@ void tx_thread_fpu_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M0+/AC6 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0+/AC6 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_m0+/gnu/inc/txm_module_port.h b/ports_module/cortex_m0+/gnu/inc/txm_module_port.h index 46f2e60d..3ab998ae 100644 --- a/ports_module/cortex_m0+/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m0+/gnu/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,12 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -375,6 +370,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M0+/GNU Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M0+/GNU Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m0+/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m0+/gnu/module_lib/src/txm_module_thread_shell_entry.c index db33fd67..2bb3bf7e 100644 --- a/ports_module/cortex_m0+/gnu/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m0+/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _gcc_setup(thread_info -> txm_module_thread_entry_info_code_base_address); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_context_restore.S index d68c6c76..dc04a44d 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,12 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_context_save.S index beea2c1b..abd44ea0 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_control.S index 4523a729..9ca7b3c7 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_disable.S index e7c45568..f0584738 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_restore.S index 7230fa3f..2aaaac2d 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_schedule.S index 04d68a14..61865ee5 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_stack_build.S index 49c0a239..653a58a8 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_system_return.S index 94b06b59..2c5c5274 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m0+/gnu/module_manager/src/tx_timer_interrupt.S index 4b7810ff..e1199f1c 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_alignment_adjust.c index c215277c..84f75cdf 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 256. */ if(size <= 256) return 256; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_external_memory_enable.c index 7cf1bf9b..ad1ceaeb 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,12 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -112,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -122,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; - + /* Calculate the region size. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -222,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -232,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -244,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; - + /* Calculate the region size. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c index 8cd0c9f5..7faeea6a 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c index 457734dc..84c26f46 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index bd14368c..83aae591 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { @@ -197,10 +192,10 @@ UINT srd_bit_index; { /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ block_size = block_size >> 3; - + /* Set SRD index into attribute register. */ srd_bit_index = 8; - + /* If subregion overlaps length, move to the next subregion. */ while(length > block_size) { @@ -212,7 +207,7 @@ UINT srd_bit_index; { srd_bit_index++; } - + /* Set unused subregion bits. */ while(srd_bit_index < 16) { @@ -220,7 +215,7 @@ UINT srd_bit_index; srd_bit_index++; } } - + return(srd_bits); } @@ -319,16 +314,16 @@ UINT i; /* Set the attributes, size (256 bytes) and enable bit. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(256) << 1) | TXM_ENABLE_REGION; /* End of kernel mode entry setup. */ - + /* Setup code protection. */ - + /* Initialize the MPU table index. */ mpu_table_index = 1; /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size will be distributed: @@ -336,7 +331,7 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 256. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) { @@ -346,7 +341,7 @@ UINT i; { block_size = _txm_power_of_two_block_size(code_size) >> 2; } - + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ else if (i == 2) { @@ -354,7 +349,7 @@ UINT i; code_size = code_size - (block_size << 1); block_size = _txm_power_of_two_block_size(code_size) >> 1; } - + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 256. */ else { @@ -363,10 +358,10 @@ UINT i; block_size = _txm_power_of_two_block_size(code_size); srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; /* Build the attribute-size register with permissions, SRD, size, enable. */ @@ -374,29 +369,29 @@ UINT i; /* Adjust the code address. */ code_address = code_address + block_size; - + /* Increment MPU table index. */ mpu_table_index++; } /* End of code protection. */ - + /* Setup data protection. */ - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Pickup data starting address and actual size. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -405,7 +400,7 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -413,7 +408,7 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to data size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 256. */ - + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) { @@ -423,7 +418,7 @@ UINT i; { block_size = _txm_power_of_two_block_size(data_size) >> 2; } - + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ else if (i == 2) { @@ -431,7 +426,7 @@ UINT i; data_size = data_size - (block_size << 1); block_size = _txm_power_of_two_block_size(data_size) >> 1; } - + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 256. */ else { @@ -440,10 +435,10 @@ UINT i; block_size = _txm_power_of_two_block_size(data_size); srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; /* Build the attribute-size register with permissions, SRD, size, enable. */ @@ -451,17 +446,17 @@ UINT i; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Increment MPU table index. */ mpu_table_index++; } - + /* Setup MPU for the remaining regions. */ while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) { /* Build the base address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; - + /* Increment MPU table index. */ mpu_table_index++; } @@ -487,11 +482,11 @@ UINT i; /* Setup the first region for the ThreadX trampoline code. */ /* Set base register to user mode entry, which is guaranteed to be at least 256-byte aligned. */ base_address_register = (ULONG) _txm_module_manager_user_mode_entry; - + /* Mask address to proper range, region 0, set Valid bit. */ base_address_register = (base_address_register & 0xFFFFFF00) | mpu_register | 0x10; module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; - + /* Attributes: read only, write-back, shareable, size 256 bytes, region enabled. */ module_instance -> txm_module_instance_mpu_registers[1] = 0x0607000F; @@ -504,7 +499,7 @@ UINT i; /* Setup values for code area. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Check if shared memory was set up. If so, only 3 entries are available for code protection. If not set up, 4 code entries are available. */ if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) @@ -516,7 +511,7 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 256. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) { @@ -526,7 +521,7 @@ UINT i; { block_size = _txm_power_of_two_block_size(code_size) >> 2; } - + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ else if (i == 2) { @@ -534,7 +529,7 @@ UINT i; code_size = code_size - (block_size << 1); block_size = _txm_power_of_two_block_size(code_size) >> 1; } - + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 256. */ else { @@ -543,57 +538,57 @@ UINT i; block_size = _txm_power_of_two_block_size(code_size); srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base address register. */ base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x06070001; - + /* Setup the MPU Base Address Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; /* Adjust the code address. */ code_address = code_address + block_size; - + /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } } - + /* Only 3 code entries available. */ else { /* Calculate block size, one code entry taken up by shared memory. */ block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { /* Build the base address register. */ base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Check if SRD bits need to be set. */ if (code_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x06070000; - + /* Is there still some code? If so set the region enable bit. */ if (code_size) { @@ -602,13 +597,13 @@ UINT i; } /* Setup the MPU Base Address Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - + /* Adjust the code address. */ code_address = code_address + block_size; - + /* Decrement the code size. */ if (code_size > block_size) { @@ -618,34 +613,34 @@ UINT i; { code_size = 0; } - + /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } - + /* Adjust indeces to pass over the shared memory entry. */ /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } - + /* Setup values for data area. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -654,46 +649,46 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) { /* Build the base address register. */ base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Check if SRD bits need to be set. */ if (data_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x13070000; - + /* Is there still some data? If so set the region enable bit. */ if (data_size) { /* Set the region enable bit. */ base_attribute_register = base_attribute_register | 0x1; } - + /* Setup the MPU Base Address Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Decrement the data size. */ if (data_size > block_size) { @@ -703,10 +698,10 @@ UINT i; { data_size = 0; } - + /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } @@ -768,7 +763,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_thread_stack_build.S index 726c6189..19fce081 100644 --- a/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m0+/gnu/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m0+/iar/example_build/cstartup_M.s b/ports_module/cortex_m0+/iar/example_build/cstartup_M.s index da53c200..3ae600b5 100644 --- a/ports_module/cortex_m0+/iar/example_build/cstartup_M.s +++ b/ports_module/cortex_m0+/iar/example_build/cstartup_M.s @@ -2,16 +2,16 @@ PUBLIC __vector_table SECTION .text:CODE:REORDER(1) - + ;; Keep vector table even if it's not referenced REQUIRE __vector_table - + THUMB - + ;; Forward declaration of sections. SECTION CSTACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) - + DATA __vector_table diff --git a/ports_module/cortex_m0+/iar/example_build/sample_threadx.c b/ports_module/cortex_m0+/iar/example_build/sample_threadx.c index c67d75d0..a12160fa 100644 --- a/ports_module/cortex_m0+/iar/example_build/sample_threadx.c +++ b/ports_module/cortex_m0+/iar/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -85,7 +85,7 @@ CHAR *pointer = TX_NULL; #ifdef TX_ENABLE_EVENT_TRACE tx_trace_enable(trace_buffer, sizeof(trace_buffer), 32); #endif - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(&byte_pool_0, "byte pool 0", byte_pool_memory, DEMO_BYTE_POOL_SIZE); @@ -96,42 +96,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -139,23 +139,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -258,11 +258,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -321,7 +321,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -374,7 +374,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_m0+/iar/example_build/sample_threadx_module.c b/ports_module/cortex_m0+/iar/example_build/sample_threadx_module.c index 647dcced..a91c3b8c 100644 --- a/ports_module/cortex_m0+/iar/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m0+/iar/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -105,7 +105,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -121,7 +121,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -133,42 +133,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -176,23 +176,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -237,7 +237,7 @@ void thread_0_entry(ULONG thread_input) UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -247,7 +247,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -295,19 +295,19 @@ UINT status; { /* Test memory handler. */ *(ULONG *)EXTERNAL_MEMORY = 0xCDCDCDCD; - - + + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -366,7 +366,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -419,7 +419,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m0+/iar/example_build/sample_threadx_module.icf b/ports_module/cortex_m0+/iar/example_build/sample_threadx_module.icf index 8cfe4766..167c26fb 100644 --- a/ports_module/cortex_m0+/iar/example_build/sample_threadx_module.icf +++ b/ports_module/cortex_m0+/iar/example_build/sample_threadx_module.icf @@ -35,11 +35,11 @@ do not initialize { section .noinit }; //place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -define movable block ROPI with alignment = 4, fixed order -{ +define movable block ROPI with alignment = 4, fixed order +{ ro object txm_module_preamble.o, - ro, - ro data + ro, + ro data }; define movable block RWPI with alignment = 8, fixed order, static base diff --git a/ports_module/cortex_m0+/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m0+/iar/example_build/sample_threadx_module_manager.c index e928709f..b944f46e 100644 --- a/ports_module/cortex_m0+/iar/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m0+/iar/example_build/sample_threadx_module_manager.c @@ -67,11 +67,11 @@ int main() void tx_application_define(void *first_unused_memory) { -CHAR *pointer = (CHAR*)module_manager_stack; +CHAR *pointer = (CHAR*)module_manager_stack; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -91,22 +91,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (VOID *) MODULE_CODE); - + /* Enable 128 byte read/write shared memory region. */ txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -115,11 +115,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m0+/iar/example_build/sample_threadx_module_manager.icf b/ports_module/cortex_m0+/iar/example_build/sample_threadx_module_manager.icf index 5e6f652e..92334d1e 100644 --- a/ports_module/cortex_m0+/iar/example_build/sample_threadx_module_manager.icf +++ b/ports_module/cortex_m0+/iar/example_build/sample_threadx_module_manager.icf @@ -18,8 +18,8 @@ define symbol __ICFEDIT_size_heap__ = 0x200; define memory mem with size = 4G; define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__]; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; diff --git a/ports_module/cortex_m0+/iar/example_build/startup.s b/ports_module/cortex_m0+/iar/example_build/startup.s index 06de32fb..34ce08e8 100644 --- a/ports_module/cortex_m0+/iar/example_build/startup.s +++ b/ports_module/cortex_m0+/iar/example_build/startup.s @@ -6,10 +6,10 @@ ;* Description : STM32F2xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP -;* - Configure he external SRAM mounted on STM322xG-EVAL board +;* - Configure he external SRAM mounted on STM322xG-EVAL board ;* to be used as data memory (optional, to be enabled by user) ;* - Set the initial PC == __iar_program_start, -;* - Set the vector table entries with the exceptions ISR +;* - Set the vector table entries with the exceptions ISR ;* address. ;* After Reset the Cortex-M3 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. @@ -72,86 +72,86 @@ __vector_table DC32 SysTick_Handler ; SysTick ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FSMC_IRQHandler ; FSMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD CRYP_IRQHandler ; CRYP crypto + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto DCD HASH_RNG_IRQHandler ; Hash and Rng ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -164,7 +164,7 @@ __vector_table Reset_Handler CPSID i ; Disable interrupts LDR R0, =sfe(CSTACK) ; restore original stack pointer - MSR MSP, R0 + MSR MSP, R0 LDR R0, =__iar_program_start ; Jump to ThreadX start, which will call IAR startup code BX R0 @@ -215,47 +215,47 @@ SysTick_Handler PUBWEAK WWDG_IRQHandler SECTION .text:CODE:NOROOT(2) -WWDG_IRQHandler +WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_IRQHandler SECTION .text:CODE:NOROOT(2) -PVD_IRQHandler +PVD_IRQHandler B PVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:NOROOT(2) -TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT(2) +TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:NOROOT(2) -RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:NOROOT(2) -FLASH_IRQHandler +FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:NOROOT(2) -RCC_IRQHandler +RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:NOROOT(2) -EXTI0_IRQHandler +EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:NOROOT(2) -EXTI1_IRQHandler +EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:NOROOT(2) -EXTI2_IRQHandler +EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler @@ -264,358 +264,358 @@ EXTI3_IRQHandler B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT(2) -EXTI4_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:NOROOT(2) -ADC_IRQHandler +ADC_IRQHandler B ADC_IRQHandler PUBWEAK CAN1_TX_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_TX_IRQHandler B CAN1_TX_IRQHandler PUBWEAK CAN1_RX0_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_RX0_IRQHandler B CAN1_RX0_IRQHandler PUBWEAK CAN1_RX1_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_RX1_IRQHandler B CAN1_RX1_IRQHandler PUBWEAK CAN1_SCE_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN1_SCE_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_SCE_IRQHandler B CAN1_SCE_IRQHandler PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:NOROOT(2) -EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_TIM9_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_BRK_TIM9_IRQHandler B TIM1_BRK_TIM9_IRQHandler PUBWEAK TIM1_UP_TIM10_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_UP_TIM10_IRQHandler B TIM1_UP_TIM10_IRQHandler PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_TRG_COM_TIM11_IRQHandler B TIM1_TRG_COM_TIM11_IRQHandler - + PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:NOROOT(2) -TIM2_IRQHandler +TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:NOROOT(2) -TIM3_IRQHandler +TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:NOROOT(2) -TIM4_IRQHandler +TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:NOROOT(2) -SPI1_IRQHandler +SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:NOROOT(2) -SPI2_IRQHandler +SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:NOROOT(2) -USART1_IRQHandler +USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:NOROOT(2) -USART2_IRQHandler +USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:NOROOT(2) -USART3_IRQHandler +USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:NOROOT(2) -EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT(2) -RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT(2) +RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT(2) -OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_FS_WKUP_IRQHandler B OTG_FS_WKUP_IRQHandler - + PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FSMC_IRQHandler SECTION .text:CODE:NOROOT(2) -FSMC_IRQHandler +FSMC_IRQHandler B FSMC_IRQHandler PUBWEAK SDIO_IRQHandler SECTION .text:CODE:NOROOT(2) -SDIO_IRQHandler +SDIO_IRQHandler B SDIO_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:NOROOT(2) -TIM5_IRQHandler +TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:NOROOT(2) -SPI3_IRQHandler +SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:NOROOT(2) -UART4_IRQHandler +UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:NOROOT(2) -UART5_IRQHandler +UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM7_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:NOROOT(2) -ETH_IRQHandler +ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:NOROOT(2) -ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK CAN2_TX_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN2_TX_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_TX_IRQHandler B CAN2_TX_IRQHandler PUBWEAK CAN2_RX0_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN2_RX0_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_RX0_IRQHandler B CAN2_RX0_IRQHandler PUBWEAK CAN2_RX1_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN2_RX1_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_RX1_IRQHandler B CAN2_RX1_IRQHandler PUBWEAK CAN2_SCE_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN2_SCE_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_SCE_IRQHandler B CAN2_SCE_IRQHandler PUBWEAK OTG_FS_IRQHandler SECTION .text:CODE:NOROOT(2) -OTG_FS_IRQHandler +OTG_FS_IRQHandler B OTG_FS_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:NOROOT(2) -USART6_IRQHandler +USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT(2) -OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT(2) -OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT(2) -OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:NOROOT(2) -OTG_HS_IRQHandler +OTG_HS_IRQHandler B OTG_HS_IRQHandler PUBWEAK DCMI_IRQHandler SECTION .text:CODE:NOROOT(2) -DCMI_IRQHandler +DCMI_IRQHandler B DCMI_IRQHandler PUBWEAK CRYP_IRQHandler SECTION .text:CODE:NOROOT(2) -CRYP_IRQHandler +CRYP_IRQHandler B CRYP_IRQHandler PUBWEAK HASH_RNG_IRQHandler - SECTION .text:CODE:NOROOT(2) -HASH_RNG_IRQHandler + SECTION .text:CODE:NOROOT(2) +HASH_RNG_IRQHandler B HASH_RNG_IRQHandler END diff --git a/ports_module/cortex_m0+/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_m0+/iar/example_build/tx_initialize_low_level.s index e26ea7f0..16404d63 100644 --- a/ports_module/cortex_m0+/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_m0+/iar/example_build/tx_initialize_low_level.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -40,11 +40,11 @@ ; SYSTEM_CLOCK EQU 7200000 SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) - + RSEG FREE_MEM:DATA PUBLIC __tx_free_memory_start __tx_free_memory_start - DS32 4 + DS32 4 ; ; SECTION `.text`:CODE:NOROOT(2) @@ -83,12 +83,6 @@ __tx_free_memory_start ;/* */ ;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) ;{ @@ -178,7 +172,7 @@ __tx_SysTickHandler: MOV lr, r1 BX lr ; } - - END - + + END + diff --git a/ports_module/cortex_m0+/iar/inc/tx_port.h b/ports_module/cortex_m0+/iar/inc/tx_port.h index f41b5a6f..2f4abd56 100644 --- a/ports_module/cortex_m0+/iar/inc/tx_port.h +++ b/ports_module/cortex_m0+/iar/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -61,7 +53,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -129,7 +121,7 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY +#ifndef TX_TIMER_THREAD_PRIORITY #define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -140,8 +132,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0 /* Enable interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((volatile ULONG *) 0x0a800024) @@ -180,7 +172,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -194,7 +186,7 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ #define TX_THREAD_EXTENSION_0 @@ -230,10 +222,10 @@ ULONG _tx_misra_time_stamp_get(VOID); VOID *tx_thread_module_reserved; #endif #ifndef TX_ENABLE_EXECUTION_CHANGE_NOTIFY -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -255,11 +247,11 @@ ULONG _tx_misra_time_stamp_get(VOID); VOID (*tx_timer_module_expiration_function)(ULONG id); -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif /* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, @@ -268,23 +260,23 @@ ULONG _tx_misra_time_stamp_get(VOID); #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #if (__VER__ < 8000000) -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #endif #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif #ifdef TX_ENABLE_FPU_SUPPORT @@ -338,13 +330,13 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ _tx_misra_control_set(_tx_vfp_state); \ } - + #endif /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -417,7 +409,7 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro #else #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) -#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) #endif @@ -445,7 +437,7 @@ __attribute__( ( always_inline ) ) static inline void __set_control(ULONG contro /* Define the get system state macro. */ - + #ifndef TX_THREAD_GET_SYSTEM_STATE #ifndef TX_MISRA_ENABLE /* @@ -479,14 +471,14 @@ ULONG _tx_misra_ipsr_get(VOID); #endif -/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to prevent early scheduling on Cortex-M parts. */ - + #define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; -/* This ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* This ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -503,9 +495,9 @@ ULONG _tx_misra_ipsr_get(VOID); #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -566,8 +558,8 @@ void tx_thread_fpu_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M0+/IAR Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M0+/IAR Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m0+/iar/inc/txm_module_port.h b/ports_module/cortex_m0+/iar/inc/txm_module_port.h index 9d3ca242..8561f21e 100644 --- a/ports_module/cortex_m0+/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m0+/iar/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,12 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -375,6 +370,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M0+/IAR Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M0+/IAR Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m0+/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m0+/iar/module_lib/src/txm_module_thread_shell_entry.c index 6d4b4f52..8983b832 100644 --- a/ports_module/cortex_m0+/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m0+/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID __iar_data_init3(VOID); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ __iar_data_init3(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_iar.c b/ports_module/cortex_m0+/iar/module_manager/src/tx_iar.c index ee47f10f..238b485e 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_iar.c +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_iar.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_misra.s b/ports_module/cortex_m0+/iar/module_manager/src/tx_misra.s index ef9d5bea..236515eb 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_misra.s +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_misra.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -106,7 +107,7 @@ SECTION `.data`:DATA:REORDER:NOROOT(2) DATA -// 51 CHAR _tx_version_id[100] = "Copyright (c) 2024 Microsoft Corporation. * ThreadX 6.1 MISRA C Compliant *"; +// 51 CHAR _tx_version_id[100] = "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX 6.1 MISRA C Compliant *"; _tx_version_id: DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H @@ -1014,7 +1015,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR ;; return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -1029,7 +1030,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR ;; return - + #ifdef __ARMVFP__ /***********************************************************************************************/ @@ -1046,8 +1047,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 ; Build FPCCR address LDR r0, [r0] ; Load FPCCR value BX LR ;; return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -1061,10 +1062,10 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR ;; return - + #endif - - + + SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2) SECTION_TYPE SHT_PROGBITS, 0 DATA diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_context_restore.S index 1dd17d7c..229055e2 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_context_save.S index 034a9c0a..3e9eebc7 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_control.S index 7317efa0..434c52c6 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_disable.S index bdca7a0a..3ee1d914 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_restore.S index db969358..d7342b28 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_schedule.S index 4eeeff3e..517d337a 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,20 +64,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* change handler name, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_stack_build.S index 925631ed..5ced33f6 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_system_return.S index 23a71b4a..b485e12b 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m0+/iar/module_manager/src/tx_timer_interrupt.S index cc2680cd..5210c308 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,12 +69,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_alignment_adjust.c index c215277c..84f75cdf 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 256. */ if(size <= 256) return 256; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_external_memory_enable.c index 7cf1bf9b..ad1ceaeb 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,12 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -112,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -122,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; - + /* Calculate the region size. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -222,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -232,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -244,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; - + /* Calculate the region size. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index 8cd0c9f5..7faeea6a 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index 457734dc..84c26f46 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_mm_register_setup.c index bd14368c..83aae591 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { @@ -197,10 +192,10 @@ UINT srd_bit_index; { /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ block_size = block_size >> 3; - + /* Set SRD index into attribute register. */ srd_bit_index = 8; - + /* If subregion overlaps length, move to the next subregion. */ while(length > block_size) { @@ -212,7 +207,7 @@ UINT srd_bit_index; { srd_bit_index++; } - + /* Set unused subregion bits. */ while(srd_bit_index < 16) { @@ -220,7 +215,7 @@ UINT srd_bit_index; srd_bit_index++; } } - + return(srd_bits); } @@ -319,16 +314,16 @@ UINT i; /* Set the attributes, size (256 bytes) and enable bit. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(256) << 1) | TXM_ENABLE_REGION; /* End of kernel mode entry setup. */ - + /* Setup code protection. */ - + /* Initialize the MPU table index. */ mpu_table_index = 1; /* Pickup code starting address and actual size. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size will be distributed: @@ -336,7 +331,7 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 256. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) { @@ -346,7 +341,7 @@ UINT i; { block_size = _txm_power_of_two_block_size(code_size) >> 2; } - + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ else if (i == 2) { @@ -354,7 +349,7 @@ UINT i; code_size = code_size - (block_size << 1); block_size = _txm_power_of_two_block_size(code_size) >> 1; } - + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 256. */ else { @@ -363,10 +358,10 @@ UINT i; block_size = _txm_power_of_two_block_size(code_size); srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; /* Build the attribute-size register with permissions, SRD, size, enable. */ @@ -374,29 +369,29 @@ UINT i; /* Adjust the code address. */ code_address = code_address + block_size; - + /* Increment MPU table index. */ mpu_table_index++; } /* End of code protection. */ - + /* Setup data protection. */ - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Pickup data starting address and actual size. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -405,7 +400,7 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -413,7 +408,7 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to data size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 256. */ - + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) { @@ -423,7 +418,7 @@ UINT i; { block_size = _txm_power_of_two_block_size(data_size) >> 2; } - + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ else if (i == 2) { @@ -431,7 +426,7 @@ UINT i; data_size = data_size - (block_size << 1); block_size = _txm_power_of_two_block_size(data_size) >> 1; } - + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 256. */ else { @@ -440,10 +435,10 @@ UINT i; block_size = _txm_power_of_two_block_size(data_size); srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; /* Build the attribute-size register with permissions, SRD, size, enable. */ @@ -451,17 +446,17 @@ UINT i; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Increment MPU table index. */ mpu_table_index++; } - + /* Setup MPU for the remaining regions. */ while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) { /* Build the base address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; - + /* Increment MPU table index. */ mpu_table_index++; } @@ -487,11 +482,11 @@ UINT i; /* Setup the first region for the ThreadX trampoline code. */ /* Set base register to user mode entry, which is guaranteed to be at least 256-byte aligned. */ base_address_register = (ULONG) _txm_module_manager_user_mode_entry; - + /* Mask address to proper range, region 0, set Valid bit. */ base_address_register = (base_address_register & 0xFFFFFF00) | mpu_register | 0x10; module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; - + /* Attributes: read only, write-back, shareable, size 256 bytes, region enabled. */ module_instance -> txm_module_instance_mpu_registers[1] = 0x0607000F; @@ -504,7 +499,7 @@ UINT i; /* Setup values for code area. */ code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - + /* Check if shared memory was set up. If so, only 3 entries are available for code protection. If not set up, 4 code entries are available. */ if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) @@ -516,7 +511,7 @@ UINT i; 2. 1/4 of the largest power of two that is greater than or equal to code size. 3. Largest power of 2 that fits in the remaining space. 4. Smallest power of 2 that exceeds the remaining space, minimum 256. */ - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) { @@ -526,7 +521,7 @@ UINT i; { block_size = _txm_power_of_two_block_size(code_size) >> 2; } - + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ else if (i == 2) { @@ -534,7 +529,7 @@ UINT i; code_size = code_size - (block_size << 1); block_size = _txm_power_of_two_block_size(code_size) >> 1; } - + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 256. */ else { @@ -543,57 +538,57 @@ UINT i; block_size = _txm_power_of_two_block_size(code_size); srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base address register. */ base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x06070001; - + /* Setup the MPU Base Address Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; /* Adjust the code address. */ code_address = code_address + block_size; - + /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } } - + /* Only 3 code entries available. */ else { /* Calculate block size, one code entry taken up by shared memory. */ block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { /* Build the base address register. */ base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Check if SRD bits need to be set. */ if (code_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); } - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x06070000; - + /* Is there still some code? If so set the region enable bit. */ if (code_size) { @@ -602,13 +597,13 @@ UINT i; } /* Setup the MPU Base Address Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; - + /* Adjust the code address. */ code_address = code_address + block_size; - + /* Decrement the code size. */ if (code_size > block_size) { @@ -618,34 +613,34 @@ UINT i; { code_size = 0; } - + /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } - + /* Adjust indeces to pass over the shared memory entry. */ /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } - + /* Setup values for data area. */ data_address = (ULONG) module_instance -> txm_module_instance_data_start; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; @@ -654,46 +649,46 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); - + /* Reset SRD bitfield. */ srd_bits = 0; - + /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) { /* Build the base address register. */ base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; - + /* Check if SRD bits need to be set. */ if (data_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); } - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x13070000; - + /* Is there still some data? If so set the region enable bit. */ if (data_size) { /* Set the region enable bit. */ base_attribute_register = base_attribute_register | 0x1; } - + /* Setup the MPU Base Address Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; - + /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; /* Adjust the data address. */ data_address = data_address + block_size; - + /* Decrement the data size. */ if (data_size > block_size) { @@ -703,10 +698,10 @@ UINT i; { data_size = 0; } - + /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; - + /* Increment the MPU register index. */ mpu_register++; } @@ -768,7 +763,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_thread_stack_build.S index cf911004..6271f32f 100644 --- a/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m0+/iar/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m23/ac6/example_build/ARMCM23_TZ_config.txt b/ports_module/cortex_m23/ac6/example_build/ARMCM23_TZ_config.txt index 259a3e72..f07f042c 100644 --- a/ports_module/cortex_m23/ac6/example_build/ARMCM23_TZ_config.txt +++ b/ports_module/cortex_m23/ac6/example_build/ARMCM23_TZ_config.txt @@ -2,7 +2,7 @@ # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] diff --git a/ports_module/cortex_m23/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h b/ports_module/cortex_m23/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h index 476361d7..66e03dff 100644 --- a/ports_module/cortex_m23/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h +++ b/ports_module/cortex_m23/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'ThreadX_Library' - * Target: 'ThreadX_Library_Project' + * Project: 'ThreadX_Library' + * Target: 'ThreadX_Library_Project' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM23_TZ.h" diff --git a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h index 2572a044..26bc6b93 100644 --- a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h +++ b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h @@ -326,7 +326,7 @@ // <0=>Secure // <1=>Non-Secure // Value for SCB->ICSR register bit STTNS -// only for single SysTick implementation +// only for single SysTick implementation */ #define SCB_ICSR_STTNS_VAL 0 diff --git a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c index cf78a4ed..a79cb61d 100644 --- a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c +++ b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c @@ -77,7 +77,7 @@ void SystemInit (void) #endif SystemCoreClock = SYSTEM_CLOCK; - + *(uint32_t *)0xE000ED24 = 0x000F0000; /* S: enable secure, usage, bus, mem faults */ *(uint32_t *)0xE002ED24 = 0x000F0000; /* NS: enable secure, usage, bus, mem faults */ } diff --git a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h index a37b412e..40fc81c1 100644 --- a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h +++ b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'demo_secure_zone' - * Target: 'FVP Simulation Model' + * Project: 'demo_secure_zone' + * Target: 'FVP Simulation Model' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM23_TZ.h" diff --git a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/interface.c b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/interface.c index 4e6e8eee..af6533c3 100644 --- a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/interface.c +++ b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/interface.c @@ -31,19 +31,19 @@ typedef funcptr funcptr_NS __attribute__((cmse_nonsecure_call)); /* Non-secure callable (entry) function */ -int func1(int x) __attribute__((cmse_nonsecure_entry)) { - return x+3; +int func1(int x) __attribute__((cmse_nonsecure_entry)) { + return x+3; } /* Non-secure callable (entry) function, calling a non-secure callback function */ int func2(funcptr callback, int x) __attribute__((cmse_nonsecure_entry)) { funcptr_NS callback_NS; // non-secure callback function pointer int y; - + /* return function pointer with cleared LSB */ callback_NS = (funcptr_NS)cmse_nsfptr_create(callback); - + y = callback_NS (x+1); - + return (y+2); } diff --git a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/main_ns.c b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/main_ns.c index a65b6880..04d857ff 100644 --- a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/main_ns.c +++ b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/main_ns.c @@ -63,7 +63,7 @@ void ThreadA (void *argument) { static int callbackB (int val) { uint32_t flags; - + flags = osThreadFlagsWait (1U, osFlagsWaitAny, osWaitForever); if (flags == 1U) { return (val+1); diff --git a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/main_s.c b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/main_s.c index 9ff73190..25da24c8 100644 --- a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/main_s.c +++ b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/main_s.c @@ -24,36 +24,36 @@ * Title: Code template for secure main function * *---------------------------------------------------------------------------*/ - + /* Use CMSE intrinsics */ #include #include #include "RTE_Components.h" #include CMSIS_device_header - + /* TZ_START_NS: Start address of non-secure application */ #ifndef TZ_START_NS #define TZ_START_NS (0x00040000U) #endif - + /* typedef for non-secure callback functions */ typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call)); - + /* Secure main() */ int main(void) { funcptr_void NonSecure_ResetHandler; - + /* Add user setup code for secure part here*/ - + /* Set non-secure main stack (MSP_NS) */ __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS))); - + /* Get non-secure reset handler */ NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U))); - + /* Start non-secure state software application */ NonSecure_ResetHandler(); - + /* Non-secure software does not return, this code is not executed */ while (1) { __NOP(); diff --git a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/tz_context.c b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/tz_context.c index f3152890..ca7f0c56 100644 --- a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/tz_context.c +++ b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/tz_context.c @@ -24,7 +24,7 @@ * Title: Context Management for ARMv8-M TrustZone - Sample implementation * *---------------------------------------------------------------------------*/ - + #include "RTE_Components.h" #include CMSIS_device_header #include "tz_context.h" diff --git a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c index e4871014..d0f6b08b 100644 --- a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c +++ b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c @@ -24,17 +24,17 @@ * * ----------------------------------------------------------------------------- */ - + #include "cmsis_compiler.h" #include "rtx_os.h" - + // OS Idle Thread __WEAK __NO_RETURN void osRtxIdleThread (void *argument) { (void)argument; for (;;) {} } - + // OS Error Callback function __WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { (void)object_id; diff --git a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h index 3021efbc..49fc392e 100644 --- a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h +++ b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h @@ -24,52 +24,52 @@ * * ----------------------------------------------------------------------------- */ - + #ifndef RTX_CONFIG_H_ #define RTX_CONFIG_H_ - + #ifdef _RTE_ #include "RTE_Components.h" #ifdef RTE_RTX_CONFIG_H #include RTE_RTX_CONFIG_H #endif #endif - + //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - + // System Configuration // ======================= - + // Global Dynamic Memory size [bytes] <0-1073741824:8> // Defines the combined global dynamic memory size. // Default: 4096 #ifndef OS_DYNAMIC_MEM_SIZE #define OS_DYNAMIC_MEM_SIZE 4096 #endif - + // Kernel Tick Frequency [Hz] <1-1000000> // Defines base time unit for delays and timeouts. // Default: 1000 (1ms tick) #ifndef OS_TICK_FREQ #define OS_TICK_FREQ 1000 #endif - + // Round-Robin Thread switching // Enables Round-Robin Thread switching. #ifndef OS_ROBIN_ENABLE #define OS_ROBIN_ENABLE 1 #endif - + // Round-Robin Timeout <1-1000> // Defines how many ticks a thread will execute before a thread switch. // Default: 5 #ifndef OS_ROBIN_TIMEOUT #define OS_ROBIN_TIMEOUT 5 #endif - + // - -// ISR FIFO Queue + +// ISR FIFO Queue // <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries // <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries // <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries @@ -78,38 +78,38 @@ #ifndef OS_ISR_FIFO_QUEUE #define OS_ISR_FIFO_QUEUE 16 #endif - + // Object Memory usage counters // Enables object memory usage counters (requires RTX source variant). #ifndef OS_OBJ_MEM_USAGE #define OS_OBJ_MEM_USAGE 0 #endif - + // - + // Thread Configuration // ======================= - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_THREAD_OBJ_MEM #define OS_THREAD_OBJ_MEM 0 #endif - + // Number of user Threads <1-1000> // Defines maximum number of user threads that can be active at the same time. // Applies to user threads with system provided memory for control blocks. #ifndef OS_THREAD_NUM #define OS_THREAD_NUM 1 #endif - + // Number of user Threads with default Stack size <0-1000> // Defines maximum number of user threads with default stack size. // Applies to user threads with zero stack size specified. #ifndef OS_THREAD_DEF_STACK_NUM #define OS_THREAD_DEF_STACK_NUM 0 #endif - + // Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> // Defines the combined stack size for user threads with user-provided stack size. // Applies to user threads with user-provided stack size and system provided memory for stack. @@ -117,23 +117,23 @@ #ifndef OS_THREAD_USER_STACK_SIZE #define OS_THREAD_USER_STACK_SIZE 0 #endif - + // - + // Default Thread Stack size [bytes] <96-1073741824:8> // Defines stack size for threads with zero stack size specified. // Default: 256 #ifndef OS_STACK_SIZE #define OS_STACK_SIZE 256 #endif - + // Idle Thread Stack size [bytes] <72-1073741824:8> // Defines stack size for Idle thread. // Default: 256 #ifndef OS_IDLE_THREAD_STACK_SIZE #define OS_IDLE_THREAD_STACK_SIZE 256 #endif - + // Idle Thread TrustZone Module Identifier // Defines TrustZone Thread Context Management Identifier. // Applies only to cores with TrustZone technology. @@ -141,49 +141,49 @@ #ifndef OS_IDLE_THREAD_TZ_MOD_ID #define OS_IDLE_THREAD_TZ_MOD_ID 0 #endif - + // Stack overrun checking // Enables stack overrun check at thread switch. // Enabling this option increases slightly the execution time of a thread switch. #ifndef OS_STACK_CHECK #define OS_STACK_CHECK 1 #endif - + // Stack usage watermark // Initializes thread stack with watermark pattern for analyzing stack usage. // Enabling this option increases significantly the execution time of thread creation. #ifndef OS_STACK_WATERMARK #define OS_STACK_WATERMARK 0 #endif - -// Processor mode for Thread execution -// <0=> Unprivileged mode + +// Processor mode for Thread execution +// <0=> Unprivileged mode // <1=> Privileged mode // Default: Privileged mode #ifndef OS_PRIVILEGE_MODE #define OS_PRIVILEGE_MODE 1 #endif - + // - + // Timer Configuration // ====================== - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_TIMER_OBJ_MEM #define OS_TIMER_OBJ_MEM 0 #endif - + // Number of Timer objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_TIMER_NUM #define OS_TIMER_NUM 1 #endif - + // - + // Timer Thread Priority // <8=> Low // <16=> Below Normal <24=> Normal <32=> Above Normal @@ -194,7 +194,7 @@ #ifndef OS_TIMER_THREAD_PRIO #define OS_TIMER_THREAD_PRIO 40 #endif - + // Timer Thread Stack size [bytes] <0-1073741824:8> // Defines stack size for Timer thread. // May be set to 0 when timers are not used. @@ -202,7 +202,7 @@ #ifndef OS_TIMER_THREAD_STACK_SIZE #define OS_TIMER_THREAD_STACK_SIZE 256 #endif - + // Timer Thread TrustZone Module Identifier // Defines TrustZone Thread Context Management Identifier. // Applies only to cores with TrustZone technology. @@ -210,7 +210,7 @@ #ifndef OS_TIMER_THREAD_TZ_MOD_ID #define OS_TIMER_THREAD_TZ_MOD_ID 0 #endif - + // Timer Callback Queue entries <0-256> // Number of concurrent active timer callback functions. // May be set to 0 when timers are not used. @@ -218,85 +218,85 @@ #ifndef OS_TIMER_CB_QUEUE #define OS_TIMER_CB_QUEUE 4 #endif - + // - + // Event Flags Configuration // ============================ - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_EVFLAGS_OBJ_MEM #define OS_EVFLAGS_OBJ_MEM 0 #endif - + // Number of Event Flags objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_EVFLAGS_NUM #define OS_EVFLAGS_NUM 1 #endif - + // - + // - + // Mutex Configuration // ====================== - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_MUTEX_OBJ_MEM #define OS_MUTEX_OBJ_MEM 0 #endif - + // Number of Mutex objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_MUTEX_NUM #define OS_MUTEX_NUM 1 #endif - + // - + // - + // Semaphore Configuration // ========================== - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_SEMAPHORE_OBJ_MEM #define OS_SEMAPHORE_OBJ_MEM 0 #endif - + // Number of Semaphore objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_SEMAPHORE_NUM #define OS_SEMAPHORE_NUM 1 #endif - + // - + // - + // Memory Pool Configuration // ============================ - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_MEMPOOL_OBJ_MEM #define OS_MEMPOOL_OBJ_MEM 0 #endif - + // Number of Memory Pool objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_MEMPOOL_NUM #define OS_MEMPOOL_NUM 1 #endif - + // Data Storage Memory size [bytes] <0-1073741824:8> // Defines the combined data storage memory size. // Applies to objects with system provided memory for data storage. @@ -304,27 +304,27 @@ #ifndef OS_MEMPOOL_DATA_SIZE #define OS_MEMPOOL_DATA_SIZE 0 #endif - + // - + // - + // Message Queue Configuration // ============================== - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_MSGQUEUE_OBJ_MEM #define OS_MSGQUEUE_OBJ_MEM 0 #endif - + // Number of Message Queue objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_MSGQUEUE_NUM #define OS_MSGQUEUE_NUM 1 #endif - + // Data Storage Memory size [bytes] <0-1073741824:8> // Defines the combined data storage memory size. // Applies to objects with system provided memory for data storage. @@ -332,26 +332,26 @@ #ifndef OS_MSGQUEUE_DATA_SIZE #define OS_MSGQUEUE_DATA_SIZE 0 #endif - + // - + // - + // Event Recorder Configuration // =============================== - + // Global Initialization // Initialize Event Recorder during 'osKernelInitialize'. #ifndef OS_EVR_INIT #define OS_EVR_INIT 0 #endif - + // Start recording // Start event recording after initialization. #ifndef OS_EVR_START #define OS_EVR_START 1 #endif - + // Global Event Filter Setup // Initial recording level applied to all components. // Error events @@ -362,11 +362,11 @@ #ifndef OS_EVR_LEVEL #define OS_EVR_LEVEL 0x00U #endif - + // RTOS Event Filter Setup // Recording levels for RTX components. // Only applicable if events for the respective component are generated. - + // Memory Management // Recording level for Memory Management events. // Error events @@ -374,10 +374,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_MEMORY_LEVEL +#ifndef OS_EVR_MEMORY_LEVEL #define OS_EVR_MEMORY_LEVEL 0x01U #endif - + // Kernel // Recording level for Kernel events. // Error events @@ -385,10 +385,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_KERNEL_LEVEL +#ifndef OS_EVR_KERNEL_LEVEL #define OS_EVR_KERNEL_LEVEL 0x01U #endif - + // Thread // Recording level for Thread events. // Error events @@ -396,10 +396,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_THREAD_LEVEL +#ifndef OS_EVR_THREAD_LEVEL #define OS_EVR_THREAD_LEVEL 0x05U #endif - + // Generic Wait // Recording level for Generic Wait events. // Error events @@ -407,10 +407,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_WAIT_LEVEL +#ifndef OS_EVR_WAIT_LEVEL #define OS_EVR_WAIT_LEVEL 0x01U #endif - + // Thread Flags // Recording level for Thread Flags events. // Error events @@ -418,10 +418,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_THFLAGS_LEVEL +#ifndef OS_EVR_THFLAGS_LEVEL #define OS_EVR_THFLAGS_LEVEL 0x01U #endif - + // Event Flags // Recording level for Event Flags events. // Error events @@ -429,10 +429,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_EVFLAGS_LEVEL +#ifndef OS_EVR_EVFLAGS_LEVEL #define OS_EVR_EVFLAGS_LEVEL 0x01U #endif - + // Timer // Recording level for Timer events. // Error events @@ -440,10 +440,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_TIMER_LEVEL +#ifndef OS_EVR_TIMER_LEVEL #define OS_EVR_TIMER_LEVEL 0x01U #endif - + // Mutex // Recording level for Mutex events. // Error events @@ -451,10 +451,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_MUTEX_LEVEL +#ifndef OS_EVR_MUTEX_LEVEL #define OS_EVR_MUTEX_LEVEL 0x01U #endif - + // Semaphore // Recording level for Semaphore events. // Error events @@ -462,10 +462,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_SEMAPHORE_LEVEL +#ifndef OS_EVR_SEMAPHORE_LEVEL #define OS_EVR_SEMAPHORE_LEVEL 0x01U #endif - + // Memory Pool // Recording level for Memory Pool events. // Error events @@ -473,10 +473,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_MEMPOOL_LEVEL +#ifndef OS_EVR_MEMPOOL_LEVEL #define OS_EVR_MEMPOOL_LEVEL 0x01U #endif - + // Message Queue // Recording level for Message Queue events. // Error events @@ -484,87 +484,87 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_MSGQUEUE_LEVEL +#ifndef OS_EVR_MSGQUEUE_LEVEL #define OS_EVR_MSGQUEUE_LEVEL 0x01U #endif - + // - + // - + // RTOS Event Generation // Enables event generation for RTX components (requires RTX source variant). - + // Memory Management // Enables Memory Management event generation. #ifndef OS_EVR_MEMORY #define OS_EVR_MEMORY 1 #endif - + // Kernel // Enables Kernel event generation. #ifndef OS_EVR_KERNEL #define OS_EVR_KERNEL 1 #endif - + // Thread // Enables Thread event generation. #ifndef OS_EVR_THREAD #define OS_EVR_THREAD 1 #endif - + // Generic Wait // Enables Generic Wait event generation. #ifndef OS_EVR_WAIT #define OS_EVR_WAIT 1 #endif - + // Thread Flags // Enables Thread Flags event generation. #ifndef OS_EVR_THFLAGS #define OS_EVR_THFLAGS 1 #endif - + // Event Flags // Enables Event Flags event generation. #ifndef OS_EVR_EVFLAGS #define OS_EVR_EVFLAGS 1 #endif - + // Timer // Enables Timer event generation. #ifndef OS_EVR_TIMER #define OS_EVR_TIMER 1 #endif - + // Mutex // Enables Mutex event generation. #ifndef OS_EVR_MUTEX #define OS_EVR_MUTEX 1 #endif - + // Semaphore // Enables Semaphore event generation. #ifndef OS_EVR_SEMAPHORE #define OS_EVR_SEMAPHORE 1 #endif - + // Memory Pool // Enables Memory Pool event generation. #ifndef OS_EVR_MEMPOOL #define OS_EVR_MEMPOOL 1 #endif - + // Message Queue // Enables Message Queue event generation. #ifndef OS_EVR_MSGQUEUE #define OS_EVR_MSGQUEUE 1 #endif - + // - + // - + // Number of Threads which use standard C/C++ library libspace // (when thread specific memory allocation is not used). #if (OS_THREAD_OBJ_MEM == 0) @@ -572,7 +572,7 @@ #else #define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM #endif - + //------------- <<< end of configuration section >>> --------------------------- - + #endif // RTX_CONFIG_H_ diff --git a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct index 2b6482c7..219b6869 100644 --- a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct +++ b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct @@ -70,7 +70,7 @@ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region RW_RAM __RW_BASE __RW_SIZE { ; RW data .ANY (+RW +ZI) } - + SHARED_MEM SHARED_MEM_BASE SHARED_MEM_SIZE { sample_threadx_module_manager.o (sharedmem) } diff --git a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h index 1cde6a79..35f9ceae 100644 --- a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h +++ b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'demo_threadx_non-secure_zone' - * Target: 'FVP Simulation Model' + * Project: 'demo_threadx_non-secure_zone' + * Target: 'FVP Simulation Model' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM23_TZ.h" diff --git a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h index 1eb74752..262dc09b 100644 --- a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h +++ b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'ThreadX_Library' - * Target: 'ThreadX_Library_Project' + * Project: 'ThreadX_Library' + * Target: 'ThreadX_Library_Project' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h" diff --git a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c index 57fcc32f..50a40460 100644 --- a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c +++ b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c @@ -72,8 +72,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -87,9 +87,9 @@ void module_manager_entry(ULONG thread_input) { (void)thread_input; - + tx_thread_secure_stack_allocate(&module_manager, 256); - + /* Initialize the module manager. */ txm_module_manager_initialize((void *) module_data_area, MODULE_DATA_SIZE); @@ -97,22 +97,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); - + /* Enable a read/write shared memory region. */ txm_module_manager_external_memory_enable(&my_module, (void *) shared_memory, SHARED_MEMORY_SIZE, TXM_MODULE_ATTRIBUTE_READ_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -121,11 +121,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/RTE/_FVP_Simulation_Model/RTE_Components.h index 4470aa37..1d498227 100644 --- a/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/RTE/_FVP_Simulation_Model/RTE_Components.h +++ b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'sample_threadx_module' - * Target: 'FVP Simulation Model' + * Project: 'sample_threadx_module' + * Target: 'FVP Simulation Model' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM23_TZ.h" diff --git a/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.c index bc55de5c..cbf252e4 100644 --- a/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -27,7 +27,7 @@ #define EXTERNAL_MEMORY (0x20040000) -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -108,7 +108,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -124,7 +124,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -136,42 +136,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -179,23 +179,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -239,21 +239,21 @@ void thread_0_entry(ULONG thread_input) { UINT status; - + tx_thread_secure_stack_allocate(thread_0, 256); thread_0_counter = func1(thread_0_counter); tx_thread_secure_stack_free(thread_0); - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { /* Increment the thread counter. */ thread_0_counter++; - + /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -302,18 +302,18 @@ UINT status; /* Test external memory sharing. */ // *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; // *(ULONG *)0x20040004 = 0x01010101; - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -372,7 +372,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -425,7 +425,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/txm_module_preamble.S index f6530c9f..302efdf2 100644 --- a/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -2,7 +2,7 @@ .align 4 .syntax unified .section RESET - + // Define public symbols .global __txm_module_preamble diff --git a/ports_module/cortex_m23/ac6/example_build/tx_initialize_low_level.S b/ports_module/cortex_m23/ac6/example_build/tx_initialize_low_level.S index 98e29203..00d7b325 100644 --- a/ports_module/cortex_m23/ac6/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m23/ac6/example_build/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,12 +63,6 @@ HEAP_SIZE = 0x00000000 /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -86,19 +81,19 @@ _tx_initialize_low_level: /* Set base of available memory to end of non-initialised RAM area. */ LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer LDR r1, =Image$$ARM_LIB_STACK$$ZI$$Limit // Build first free address - ADDS r1, r1, #4 // + ADDS r1, r1, #4 // STR r1, [r0] // Setup first unused memory pointer /* Setup Vector Table Offset Register. */ LDR r0, =0xE000ED08 // Build address of NVIC registers LDR r1, =__Vectors // Pickup address of vector table - STR r1, [r0] // Set vector table address + STR r1, [r0] // Set vector table address /* Enable the cycle count register. */ // LDR r0, =0xE0001000 // Build address of DWT register // LDR r1, [r0] // Pickup the current value // ORR r1, r1, #1 // Set the CYCCNTENA bit -// STR r1, [r0] // Enable the cycle count register +// STR r1, [r0] // Enable the cycle count register /* Set system stack pointer from vector value. */ LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer @@ -116,21 +111,21 @@ _tx_initialize_low_level: /* Configure handler priorities. */ LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD18 // - ADD r0, r0, r2 // + LDR r2, =0xD18 // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 4-7 Priority Registers LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD1C // - ADD r0, r0, r2 // + LDR r2, =0xD1C // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 8-11 Priority Registers // Note: SVC must be lowest priority, which is 0xFF LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD20 // - ADD r0, r0, r2 // + LDR r2, =0xD20 // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 12-15 Priority Registers // Note: PnSV must be lowest priority, which is 0xFF @@ -162,7 +157,7 @@ __tx_IntHandler: // VOID InterruptHandler (VOID) // { PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) - + /* Do interrupt handler work here */ /* .... */ @@ -201,7 +196,7 @@ HardFault_Handler: // A stack overflow will trigger a hardfault. // There is no CFSR in M23, so we will not try to // determine if the fault is caused by a stack overflow - // or some other condition. + // or some other condition. B HardFault_Handler .end diff --git a/ports_module/cortex_m23/ac6/example_build/txm/RTE/_ThreadX_Module_Library/RTE_Components.h b/ports_module/cortex_m23/ac6/example_build/txm/RTE/_ThreadX_Module_Library/RTE_Components.h index 74656ec0..0c7e0eba 100644 --- a/ports_module/cortex_m23/ac6/example_build/txm/RTE/_ThreadX_Module_Library/RTE_Components.h +++ b/ports_module/cortex_m23/ac6/example_build/txm/RTE/_ThreadX_Module_Library/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'txm' - * Target: 'ThreadX Module Library' + * Project: 'txm' + * Target: 'ThreadX Module Library' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM23_TZ.h" diff --git a/ports_module/cortex_m23/ac6/inc/tx_port.h b/ports_module/cortex_m23/ac6/inc/tx_port.h index 5686cdd3..30f56817 100644 --- a/ports_module/cortex_m23/ac6/inc/tx_port.h +++ b/ports_module/cortex_m23/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,19 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -63,7 +51,7 @@ /* Determine if the optional ThreadX user define file should be used. */ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -107,24 +95,24 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); #error "Do not define TX_ENABLE_STACK_CHECKING" #endif -/* If user does not want to terminate thread on stack overflow, +/* If user does not want to terminate thread on stack overflow, #define the TX_THREAD_NO_TERMINATE_STACK_ERROR symbol. The thread will be rescheduled and continue to cause the exception. It is suggested user code handle this by registering a notification with the tx_thread_stack_error_notify function. */ /*#define TX_THREAD_NO_TERMINATE_STACK_ERROR */ -/* Define the system API mappings based on the error checking - selected by the user. Note: this section is only applicable to +/* Define the system API mappings based on the error checking + selected by the user. Note: this section is only applicable to application source code, hence the conditional that turns off this stuff when the include file is processed by the ThreadX source. */ #ifndef TX_SOURCE_CODE -/* Determine if error checking is desired. If so, map API functions +/* Determine if error checking is desired. If so, map API functions to the appropriate error checking front-ends. Otherwise, map API - functions to the core functions that actually perform the work. + functions to the core functions that actually perform the work. Note: error checking is enabled by default. */ #ifdef TX_DISABLE_ERROR_CHECKING @@ -380,12 +368,12 @@ static void _set_control(unsigned int _control) _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ _tx_misra_control_set(_tx_vfp_state); \ } - + #endif /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -527,9 +515,9 @@ extern void _tx_thread_secure_stack_initialize(void); #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -576,7 +564,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M23/AC6 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M23/AC6 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m23/ac6/inc/tx_secure_interface.h b/ports_module/cortex_m23/ac6/inc/tx_secure_interface.h index 39b5d5fd..5ac37fbf 100644 --- a/ports_module/cortex_m23/ac6/inc/tx_secure_interface.h +++ b/ports_module/cortex_m23/ac6/inc/tx_secure_interface.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,12 +38,6 @@ /* It is assumed that tx_api.h and tx_port.h have already been */ /* included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_SECURE_INTERFACE_H diff --git a/ports_module/cortex_m23/ac6/inc/txm_module_port.h b/ports_module/cortex_m23/ac6/inc/txm_module_port.h index 1e26542c..9f38a588 100644 --- a/ports_module/cortex_m23/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m23/ac6/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,15 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -356,6 +348,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M23/AC6 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M23/AC6 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m23/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_m23/ac6/module_lib/src/txm_module_initialize.S index f0e6c764..82f6357d 100644 --- a/ports_module/cortex_m23/ac6/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_m23/ac6/module_lib/src/txm_module_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,16 +58,6 @@ /* */ /* _txm_module_thread_shell_entry Start module thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* 01-31-2022 Scott Larson Modified comments, fixed */ -/* scatterload, and made */ -/* heap user configurable, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _txm_module_initialize(VOID) .global _txm_module_initialize @@ -107,7 +98,7 @@ __rt_entry: LDM r0,{r0-r1} BL __rt_lib_init // Call ARM func to initialize library POP {r0-r1} // Restore dregs and LR - MOV r12, r0 + MOV r12, r0 MOV lr, r1 POP {r0-r7} MOV r8, r0 diff --git a/ports_module/cortex_m23/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m23/ac6/module_lib/src/txm_module_thread_shell_entry.c index 5603e5fc..0be91d63 100644 --- a/ports_module/cortex_m23/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m23/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -89,16 +90,6 @@ extern VOID _txm_module_initialize(VOID *heap_base, VOID *heap_top); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* 01-31-2022 Scott Larson Modified comments, fixed */ -/* scatterload, and made */ -/* heap user configurable, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -113,14 +104,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _txm_module_initialize(&txm_heap[0], &txm_heap[TXM_MODULE_HEAP_SIZE-1]); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -128,7 +119,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m23/ac6/module_lib/src/txm_thread_secure_stack_allocate.c b/ports_module/cortex_m23/ac6/module_lib/src/txm_thread_secure_stack_allocate.c index 05a922d4..95c101de 100644 --- a/ports_module/cortex_m23/ac6/module_lib/src/txm_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m23/ac6/module_lib/src/txm_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { diff --git a/ports_module/cortex_m23/ac6/module_lib/src/txm_thread_secure_stack_free.c b/ports_module/cortex_m23/ac6/module_lib/src/txm_thread_secure_stack_free.c index 61c852b5..47c718a0 100644 --- a/ports_module/cortex_m23/ac6/module_lib/src/txm_thread_secure_stack_free.c +++ b/ports_module/cortex_m23/ac6/module_lib/src/txm_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { diff --git a/ports_module/cortex_m23/ac6/module_manager/inc/txm_module_manager_dispatch_port.h b/ports_module/cortex_m23/ac6/module_manager/inc/txm_module_manager_dispatch_port.h index 8bbcd5b3..0575c748 100644 --- a/ports_module/cortex_m23/ac6/module_manager/inc/txm_module_manager_dispatch_port.h +++ b/ports_module/cortex_m23/ac6/module_manager/inc/txm_module_manager_dispatch_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_restore.S index 2b724e21..fac7b4bc 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_save.S index ba7ea70c..e1b624bd 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_control.S index 9adce6f9..950717cd 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,12 +52,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_disable.S index dceff9bc..6a8dafd0 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,12 +52,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_restore.S index fd52f19e..9092edc1 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,12 +52,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_schedule.S index 896204dc..8e4df0c3 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -174,7 +162,7 @@ BusFault_Handler: STR r0, [r2, #88] // Save xPSR MRS r0, CONTROL // Pickup current CONTROL register - MOVW r1, #0x1 // + MOVW r1, #0x1 // BICS r0, r0, r1 // Clear the UNPRIV bit MSR CONTROL, r0 // Setup new CONTROL register @@ -416,7 +404,7 @@ _tx_enable_mpu: MOVS r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU MOV r1, r8 // Get copied thread ptr - + skip_mpu_setup: // Restore the thread context and PSP @@ -528,7 +516,7 @@ _tx_entry_continue: _tx_skip_kernel_stack_enter: MRS r0, CONTROL // Pickup current CONTROL register - MOVW r1, #0x1 // + MOVW r1, #0x1 // BICS r0, r0, r1 // Clear the UNPRIV bit MSR CONTROL, r0 // Setup new CONTROL register BX lr // Return to thread @@ -609,7 +597,7 @@ _tx_alloc_continue: STR r0, [r1] // Store function return value MOV lr, r2 BX lr - + _tx_svc_secure_free: LDR r2, =_tx_free_return // Load address of where we should have come from CMP r1, r2 // Did we come from _tx_thread_secure_stack_free? diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack.c index baae59d8..0073bd47 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -102,21 +103,6 @@ static INT tx_head_free_index = 0U; /* */ /* _tx_initialize_kernel_enter */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-16-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.1 */ -/* 06-02-2021 Scott Larson Modified comment(s), and */ -/* changed name, execute in */ -/* handler mode, */ -/* resulting in version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments, updated */ -/* secure stack allocation, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_initialize(void) diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_allocate.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_allocate.S index 4560e059..8fd91971 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_allocate.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_allocate.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) // { diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_free.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_free.S index 7bec56b3..03476dd0 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_free.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_free.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,12 +51,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) // { diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_initialize.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_initialize.S index 2bb69e1b..3c5fdde6 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_initialize.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,16 +51,6 @@ /* */ /* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) // { diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_build.S index 302e4ad1..b8b83e12 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { @@ -95,7 +90,7 @@ _tx_thread_stack_build: Stack Bottom: (higher memory address) */ LDR r2, [r0, #16] // Pickup end of stack area - MOVW r3, #0x7 // + MOVW r3, #0x7 // BICS r2, r2, r3 // Align frame for 8-byte alignment SUBS r2, r2, #68 // Subtract frame size #ifdef TX_SINGLE_MODE_SECURE diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_system_return.S index c27056bb..22244f01 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_timer_interrupt.S index 1b0dd93b..b8bef35a 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_allocate.c b/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_allocate.c index 6c394cae..9bade139 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { @@ -76,10 +71,10 @@ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_siz return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_free.c b/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_free.c index a2f81e77..75a26945 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_free.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { @@ -74,10 +69,10 @@ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_alignment_adjust.c index c520f155..e1534699 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, @@ -77,7 +72,7 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, /* Round code and data size UP to TXM_MODULE_MPU_ALIGNMENT bytes. */ *code_size = (*code_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); *data_size = (*data_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); - + /* Alignment for code and data is TXM_MODULE_MPU_ALIGNMENT bytes. */ *code_alignment = TXM_MODULE_MPU_ALIGNMENT; *data_alignment = TXM_MODULE_MPU_ALIGNMENT; diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_external_memory_enable.c index 004d5fe1..1c7c1b47 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -105,7 +100,7 @@ ULONG shared_index; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -115,49 +110,49 @@ ULONG shared_index; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address must adhere to Cortex-M23 MPU alignment. */ address = (ULONG) start_address; if(address != (address & ~(TXM_MODULE_MPU_ALIGNMENT - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Set base address register with start address, sanitized attributes and execute never. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_base_address = address | (attributes & TXM_MODULE_ATTRIBUTE_MASK) | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; - + /* Set the limit address (data start + length-1), attribute index, and enable bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_limit_address = (address + length-1) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c index c7107a60..c31c70fc 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c index 6831e0df..3223b566 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index 3adcf647..55abbe5e 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _txm_module_manager_thread_create */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) { @@ -91,27 +86,27 @@ ULONG callback_stack_size; /* Set base address register to module data address, which should be at least 32-byte aligned. Mask address to proper range, inner shareable, read write, execute never. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_base_address = ((ULONG) module_instance -> txm_module_instance_data_start & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE | TXM_MODULE_ATTRIBUTE_READ_WRITE | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Set the limit address (data start + data size-1), attribute index, and enable bit. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_limit_address = (((ULONG) module_instance -> txm_module_instance_data_start + data_size - 1) & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; /* End of module data protection. */ - + /* Remaining MPU entries are disabled for now and can be used for shared memory. */ } @@ -168,7 +163,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_port_dispatch.c index d2c0862e..07a2e9fc 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_port_dispatch.c +++ b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_port_dispatch.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* _txm_module_manager_kernel_dispatch */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) { @@ -88,7 +83,7 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; ); break; } - + case TXM_THREAD_SECURE_STACK_FREE_CALL: { if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) @@ -102,13 +97,13 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; ); break; } - + default: { /* Unhandled kernel request, return an error! */ break; } } - + return(return_value); } diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index 3533a3f5..ef874245 100644 --- a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { @@ -93,7 +88,7 @@ _txm_module_manager_thread_stack_build: Stack Bottom: (higher memory address) */ LDR r2, [r0, #16] // Pickup end of stack area - MOVW r3, #0x7 // + MOVW r3, #0x7 // BICS r2, r2, r3 // Align frame for 8-byte alignment SUBS r2, r2, #68 // Subtract frame size #ifdef TX_SINGLE_MODE_SECURE diff --git a/ports_module/cortex_m23/gnu/example_build/sample_threadx_module.c b/ports_module/cortex_m23/gnu/example_build/sample_threadx_module.c index 52557312..b74d7a35 100644 --- a/ports_module/cortex_m23/gnu/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m23/gnu/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -101,7 +101,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -117,7 +117,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -129,42 +129,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -172,23 +172,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -233,7 +233,7 @@ void thread_0_entry(ULONG thread_input) UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -243,7 +243,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -291,19 +291,19 @@ UINT status; { /* Test memory handler. */ *(ULONG *)0x20010000 = 0xCDCDCDCD; - - + + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -362,7 +362,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -415,7 +415,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m23/gnu/example_build/txm_module_preamble.S b/ports_module/cortex_m23/gnu/example_build/txm_module_preamble.S index ded31277..5f663569 100644 --- a/ports_module/cortex_m23/gnu/example_build/txm_module_preamble.S +++ b/ports_module/cortex_m23/gnu/example_build/txm_module_preamble.S @@ -33,7 +33,7 @@ __txm_module_preamble: // 1 -> User mode execution .dc.l _txm_module_thread_shell_entry - . - 0 // Module Shell Entry Point .dc.l demo_module_start - . - 0 // Module Start Thread Entry Point - .dc.l 0 // Module Stop Thread Entry Point + .dc.l 0 // Module Stop Thread Entry Point .dc.l 1 // Module Start/Stop Thread Priority .dc.l 1024 // Module Start/Stop Thread Stack Size .dc.l _txm_module_callback_request_thread_entry - . - 0 // Module Callback Thread Entry diff --git a/ports_module/cortex_m23/gnu/inc/tx_port.h b/ports_module/cortex_m23/gnu/inc/tx_port.h index 6f122445..0f2de686 100644 --- a/ports_module/cortex_m23/gnu/inc/tx_port.h +++ b/ports_module/cortex_m23/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,29 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 04-02-2021 Scott Larson Modified comment(s), */ -/* remove unneeded headers, */ -/* use builtins, added */ -/* ULONG64_DEFINED,updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 06-02-2021 Scott Larson Modified comment(s), */ -/* added symbol to enable */ -/* stack error handler, */ -/* resulting in version 6.1.7 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -73,7 +51,7 @@ /* Determine if the optional ThreadX user define file should be used. */ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -116,24 +94,24 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); #error "Do not define TX_ENABLE_STACK_CHECKING" #endif -/* If user does not want to terminate thread on stack overflow, +/* If user does not want to terminate thread on stack overflow, #define the TX_THREAD_NO_TERMINATE_STACK_ERROR symbol. The thread will be rescheduled and continue to cause the exception. It is suggested user code handle this by registering a notification with the tx_thread_stack_error_notify function. */ /*#define TX_THREAD_NO_TERMINATE_STACK_ERROR */ -/* Define the system API mappings based on the error checking - selected by the user. Note: this section is only applicable to +/* Define the system API mappings based on the error checking + selected by the user. Note: this section is only applicable to application source code, hence the conditional that turns off this stuff when the include file is processed by the ThreadX source. */ #ifndef TX_SOURCE_CODE -/* Determine if error checking is desired. If so, map API functions +/* Determine if error checking is desired. If so, map API functions to the appropriate error checking front-ends. Otherwise, map API - functions to the core functions that actually perform the work. + functions to the core functions that actually perform the work. Note: error checking is enabled by default. */ #ifdef TX_DISABLE_ERROR_CHECKING @@ -405,9 +383,9 @@ extern void _tx_thread_secure_stack_initialize(void); #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -487,7 +465,7 @@ unsigned int interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M23/GNU Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M23/GNU Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m23/gnu/inc/tx_secure_interface.h b/ports_module/cortex_m23/gnu/inc/tx_secure_interface.h index 66eb089d..63f683c1 100644 --- a/ports_module/cortex_m23/gnu/inc/tx_secure_interface.h +++ b/ports_module/cortex_m23/gnu/inc/tx_secure_interface.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,12 +38,6 @@ /* It is assumed that tx_api.h and tx_port.h have already been */ /* included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_SECURE_INTERFACE_H diff --git a/ports_module/cortex_m23/gnu/inc/txm_module_port.h b/ports_module/cortex_m23/gnu/inc/txm_module_port.h index 1ace4fdf..04e72d0c 100644 --- a/ports_module/cortex_m23/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m23/gnu/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,12 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -346,6 +341,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M23/GNU Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M23/GNU Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m23/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m23/gnu/module_lib/src/txm_module_thread_shell_entry.c index 0d180985..b4e75378 100644 --- a/ports_module/cortex_m23/gnu/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m23/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the GNU C environment. */ _gcc_setup(thread_info -> txm_module_thread_entry_info_code_base_address); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m23/gnu/module_lib/src/txm_thread_secure_stack_allocate.c b/ports_module/cortex_m23/gnu/module_lib/src/txm_thread_secure_stack_allocate.c index 05a922d4..95c101de 100644 --- a/ports_module/cortex_m23/gnu/module_lib/src/txm_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m23/gnu/module_lib/src/txm_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { diff --git a/ports_module/cortex_m23/gnu/module_lib/src/txm_thread_secure_stack_free.c b/ports_module/cortex_m23/gnu/module_lib/src/txm_thread_secure_stack_free.c index 61c852b5..47c718a0 100644 --- a/ports_module/cortex_m23/gnu/module_lib/src/txm_thread_secure_stack_free.c +++ b/ports_module/cortex_m23/gnu/module_lib/src/txm_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { diff --git a/ports_module/cortex_m23/gnu/module_manager/inc/txm_module_manager_dispatch_port.h b/ports_module/cortex_m23/gnu/module_manager/inc/txm_module_manager_dispatch_port.h index 8bbcd5b3..0575c748 100644 --- a/ports_module/cortex_m23/gnu/module_manager/inc/txm_module_manager_dispatch_port.h +++ b/ports_module/cortex_m23/gnu/module_manager/inc/txm_module_manager_dispatch_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_initialize_low_level.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_initialize_low_level.S index 4b4d3b62..d38525bf 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_initialize_low_level.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ HEAP_SIZE = 0x00000000 /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -87,20 +82,20 @@ _tx_initialize_low_level: /* Set base of available memory to end of non-initialised RAM area. */ LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer LDR r1, =Image$$ARM_LIB_STACK$$ZI$$Limit // Build first free address - ADDS r1, r1, #4 // + ADDS r1, r1, #4 // STR r1, [r0] // Setup first unused memory pointer /* Setup Vector Table Offset Register. */ LDR r0, =0xE000ED08 // Build address of NVIC registers LDR r1, =__Vectors // Pickup address of vector table - STR r1, [r0] // Set vector table address + STR r1, [r0] // Set vector table address // /* Enable the cycle count register. */ // // LDR r0, =0xE0001000 // Build address of DWT register // LDR r1, [r0] // Pickup the current value // ORR r1, r1, #1 // Set the CYCCNTENA bit -// STR r1, [r0] // Enable the cycle count register +// STR r1, [r0] // Enable the cycle count register /* Set system stack pointer from vector value. */ LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer @@ -118,21 +113,21 @@ _tx_initialize_low_level: /* Configure handler priorities. */ LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD18 // - ADD r0, r0, r2 // + LDR r2, =0xD18 // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 4-7 Priority Registers LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD1C // - ADD r0, r0, r2 // + LDR r2, =0xD1C // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 8-11 Priority Registers // Note: SVC must be lowest priority, which is 0xFF LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD20 // - ADD r0, r0, r2 // + LDR r2, =0xD20 // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 12-15 Priority Registers // Note: PnSV must be lowest priority, which is 0xFF @@ -164,7 +159,7 @@ __tx_IntHandler: // VOID InterruptHandler (VOID) // { PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) - + /* Do interrupt handler work here */ /* .... */ @@ -203,7 +198,7 @@ HardFault_Handler: // A stack overflow will trigger a hardfault. // There is no CFSR in M23, so we will not try to // determine if the fault is caused by a stack overflow - // or some other condition. + // or some other condition. B HardFault_Handler .end diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_restore.S index f0de20a2..2f9d7165 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_save.S index c7dce4ea..f51cff71 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_control.S index 7fcfa9f4..8bfbbd09 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,12 +52,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_disable.S index addb7915..62b1a017 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,12 +52,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_restore.S index 24174940..7ac71319 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,12 +52,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_schedule.S index dbeecb88..eea9818d 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,19 +54,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -170,7 +158,7 @@ BusFault_Handler: STR r0, [r2, #88] // Save xPSR MRS r0, CONTROL // Pickup current CONTROL register - MOVW r1, #0x1 // + MOVW r1, #0x1 // BICS r0, r0, r1 // Clear the UNPRIV bit MSR CONTROL, r0 // Setup new CONTROL register @@ -412,7 +400,7 @@ _tx_enable_mpu: MOVS r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU MOV r1, r8 // Get copied thread ptr - + skip_mpu_setup: // Restore the thread context and PSP @@ -524,7 +512,7 @@ _tx_entry_continue: _tx_skip_kernel_stack_enter: MRS r0, CONTROL // Pickup current CONTROL register - MOVW r1, #0x1 // + MOVW r1, #0x1 // BICS r0, r0, r1 // Clear the UNPRIV bit MSR CONTROL, r0 // Setup new CONTROL register BX lr // Return to thread @@ -605,7 +593,7 @@ _tx_alloc_continue: STR r0, [r1] // Store function return value MOV lr, r2 BX lr - + _tx_svc_secure_free: LDR r2, =_tx_free_return // Load address of where we should have come from CMP r1, r2 // Did we come from _tx_thread_secure_stack_free? diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack.c index 4f757f90..44376c27 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -98,21 +99,6 @@ static INT tx_head_free_index = 0U; /* */ /* _tx_initialize_kernel_enter */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-16-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.1 */ -/* 06-02-2021 Scott Larson Modified comment(s), changed */ -/* name, execute in handler */ -/* mode, disable optimization, */ -/* resulting in version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments, updated */ -/* secure stack allocation, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry, optimize(0))) UINT _tx_thread_secure_mode_stack_initialize(void) diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_allocate.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_allocate.S index 1e322ad4..a569e07e 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_allocate.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_allocate.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) // { diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_free.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_free.S index 4b51958c..9a1e28c3 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_free.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_free.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,12 +51,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) // { diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_initialize.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_initialize.S index 6cec7c52..ae66a5c5 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_initialize.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,16 +51,6 @@ /* */ /* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) // { diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_build.S index b53609b0..0430d672 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { @@ -95,7 +90,7 @@ _tx_thread_stack_build: Stack Bottom: (higher memory address) */ LDR r2, [r0, #16] // Pickup end of stack area - MOVW r3, #0x7 // + MOVW r3, #0x7 // BICS r2, r2, r3 // Align frame for 8-byte alignment SUBS r2, r2, #68 // Subtract frame size #ifdef TX_SINGLE_MODE_SECURE diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_system_return.S index 85d38e4d..a09ad30d 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_timer_interrupt.S index e1eef248..3bc77594 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_allocate.c b/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_allocate.c index 6c394cae..9bade139 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { @@ -76,10 +71,10 @@ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_siz return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_free.c b/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_free.c index a2f81e77..75a26945 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_free.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { @@ -74,10 +69,10 @@ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_alignment_adjust.c index c520f155..e1534699 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, @@ -77,7 +72,7 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, /* Round code and data size UP to TXM_MODULE_MPU_ALIGNMENT bytes. */ *code_size = (*code_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); *data_size = (*data_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); - + /* Alignment for code and data is TXM_MODULE_MPU_ALIGNMENT bytes. */ *code_alignment = TXM_MODULE_MPU_ALIGNMENT; *data_alignment = TXM_MODULE_MPU_ALIGNMENT; diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_external_memory_enable.c index 004d5fe1..1c7c1b47 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -105,7 +100,7 @@ ULONG shared_index; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -115,49 +110,49 @@ ULONG shared_index; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address must adhere to Cortex-M23 MPU alignment. */ address = (ULONG) start_address; if(address != (address & ~(TXM_MODULE_MPU_ALIGNMENT - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Set base address register with start address, sanitized attributes and execute never. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_base_address = address | (attributes & TXM_MODULE_ATTRIBUTE_MASK) | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; - + /* Set the limit address (data start + length-1), attribute index, and enable bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_limit_address = (address + length-1) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c index c7107a60..c31c70fc 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c index 6831e0df..3223b566 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index 3adcf647..55abbe5e 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _txm_module_manager_thread_create */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) { @@ -91,27 +86,27 @@ ULONG callback_stack_size; /* Set base address register to module data address, which should be at least 32-byte aligned. Mask address to proper range, inner shareable, read write, execute never. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_base_address = ((ULONG) module_instance -> txm_module_instance_data_start & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE | TXM_MODULE_ATTRIBUTE_READ_WRITE | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Set the limit address (data start + data size-1), attribute index, and enable bit. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_limit_address = (((ULONG) module_instance -> txm_module_instance_data_start + data_size - 1) & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; /* End of module data protection. */ - + /* Remaining MPU entries are disabled for now and can be used for shared memory. */ } @@ -168,7 +163,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_port_dispatch.c index d2c0862e..07a2e9fc 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_port_dispatch.c +++ b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_port_dispatch.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* _txm_module_manager_kernel_dispatch */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) { @@ -88,7 +83,7 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; ); break; } - + case TXM_THREAD_SECURE_STACK_FREE_CALL: { if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) @@ -102,13 +97,13 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; ); break; } - + default: { /* Unhandled kernel request, return an error! */ break; } } - + return(return_value); } diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_thread_stack_build.S index aa72b0be..99bfa470 100644 --- a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { @@ -93,7 +88,7 @@ _txm_module_manager_thread_stack_build: Stack Bottom: (higher memory address) */ LDR r2, [r0, #16] // Pickup end of stack area - MOVW r3, #0x7 // + MOVW r3, #0x7 // BICS r2, r2, r3 // Align frame for 8-byte alignment SUBS r2, r2, #68 // Subtract frame size #ifdef TX_SINGLE_MODE_SECURE diff --git a/ports_module/cortex_m23/iar/example_build/sample_threadx_module.c b/ports_module/cortex_m23/iar/example_build/sample_threadx_module.c index 939433cd..e9605af8 100644 --- a/ports_module/cortex_m23/iar/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m23/iar/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -101,7 +101,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -117,7 +117,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -129,42 +129,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -172,23 +172,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -233,7 +233,7 @@ void thread_0_entry(ULONG thread_input) UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -243,7 +243,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -291,19 +291,19 @@ UINT status; { /* Test memory handler. */ *(ULONG *)0x64005000 = 0xCDCDCDCD; - - + + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -362,7 +362,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -415,7 +415,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m23/iar/example_build/sample_threadx_module.icf b/ports_module/cortex_m23/iar/example_build/sample_threadx_module.icf index 8cfe4766..167c26fb 100644 --- a/ports_module/cortex_m23/iar/example_build/sample_threadx_module.icf +++ b/ports_module/cortex_m23/iar/example_build/sample_threadx_module.icf @@ -35,11 +35,11 @@ do not initialize { section .noinit }; //place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -define movable block ROPI with alignment = 4, fixed order -{ +define movable block ROPI with alignment = 4, fixed order +{ ro object txm_module_preamble.o, - ro, - ro data + ro, + ro data }; define movable block RWPI with alignment = 8, fixed order, static base diff --git a/ports_module/cortex_m23/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m23/iar/example_build/sample_threadx_module_manager.c index 28299f6c..59aee1b9 100644 --- a/ports_module/cortex_m23/iar/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m23/iar/example_build/sample_threadx_module_manager.c @@ -53,8 +53,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -74,22 +74,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x080F0000); - + /* Enable 128 byte read/write shared memory region at 0x64005000. */ txm_module_manager_external_memory_enable(&my_module, (void *) 0x64005000, 128, TXM_MODULE_ATTRIBUTE_READ_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -98,7 +98,7 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { diff --git a/ports_module/cortex_m23/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_m23/iar/example_build/tx_initialize_low_level.s index 69bd7e29..fb6a109f 100644 --- a/ports_module/cortex_m23/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_m23/iar/example_build/tx_initialize_low_level.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,13 +71,6 @@ __tx_free_memory_start /* CALLED BY */ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -100,7 +94,7 @@ _tx_initialize_low_level: // LDR r0, =0xE0001000 // Build address of DWT register // LDR r1, [r0] // Pickup the current value // ORR r1, r1, #1 // Set the CYCCNTENA bit -// STR r1, [r0] // Enable the cycle count register +// STR r1, [r0] // Enable the cycle count register /* Set system stack pointer from vector value. */ LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer @@ -118,21 +112,21 @@ _tx_initialize_low_level: /* Configure handler priorities. */ LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD18 // - ADD r0, r0, r2 // + LDR r2, =0xD18 // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 4-7 Priority Registers LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD1C // - ADD r0, r0, r2 // + LDR r2, =0xD1C // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 8-11 Priority Registers // Note: SVC must be lowest priority, which is 0xFF LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM LDR r0, =0xE000E000 // Build address of NVIC registers - LDR r2, =0xD20 // - ADD r0, r0, r2 // + LDR r2, =0xD20 // + ADD r0, r0, r2 // STR r1, [r0] // Setup System Handlers 12-15 Priority Registers // Note: PnSV must be lowest priority, which is 0xFF @@ -191,7 +185,7 @@ HardFault_Handler: // A stack overflow will trigger a hardfault. // There is no CFSR in M23, so we will not try to // determine if the fault is caused by a stack overflow - // or some other condition. + // or some other condition. B HardFault_Handler diff --git a/ports_module/cortex_m23/iar/inc/tx_port.h b/ports_module/cortex_m23/iar/inc/tx_port.h index 14d287ef..9f8547da 100644 --- a/ports_module/cortex_m23/iar/inc/tx_port.h +++ b/ports_module/cortex_m23/iar/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,19 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -118,24 +106,24 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); #error "Do not define TX_ENABLE_STACK_CHECKING" #endif -/* If user does not want to terminate thread on stack overflow, +/* If user does not want to terminate thread on stack overflow, #define the TX_THREAD_NO_TERMINATE_STACK_ERROR symbol. The thread will be rescheduled and continue to cause the exception. It is suggested user code handle this by registering a notification with the tx_thread_stack_error_notify function. */ /*#define TX_THREAD_NO_TERMINATE_STACK_ERROR */ -/* Define the system API mappings based on the error checking - selected by the user. Note: this section is only applicable to +/* Define the system API mappings based on the error checking + selected by the user. Note: this section is only applicable to application source code, hence the conditional that turns off this stuff when the include file is processed by the ThreadX source. */ #ifndef TX_SOURCE_CODE -/* Determine if error checking is desired. If so, map API functions +/* Determine if error checking is desired. If so, map API functions to the appropriate error checking front-ends. Otherwise, map API - functions to the core functions that actually perform the work. + functions to the core functions that actually perform the work. Note: error checking is enabled by default. */ #ifdef TX_DISABLE_ERROR_CHECKING @@ -452,7 +440,7 @@ __attribute__( ( always_inline ) ) static inline void __set_CONTROL(ULONG contro /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -610,7 +598,7 @@ extern void _tx_thread_secure_stack_initialize(void); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __CLZ(__RBIT((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #endif /* Define the interrupt disable/restore macros for each compiler. */ @@ -707,7 +695,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M23/IAR Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M23/IAR Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m23/iar/inc/tx_secure_interface.h b/ports_module/cortex_m23/iar/inc/tx_secure_interface.h index 13cb4b44..ac4a99d4 100644 --- a/ports_module/cortex_m23/iar/inc/tx_secure_interface.h +++ b/ports_module/cortex_m23/iar/inc/tx_secure_interface.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,12 +38,6 @@ /* It is assumed that tx_api.h and tx_port.h have already been */ /* included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_SECURE_INTERFACE_H diff --git a/ports_module/cortex_m23/iar/inc/txm_module_port.h b/ports_module/cortex_m23/iar/inc/txm_module_port.h index 2b5e7b3d..d394aaaf 100644 --- a/ports_module/cortex_m23/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m23/iar/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,12 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -349,6 +344,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M23/IAR Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M23/IAR Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m23/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m23/iar/module_lib/src/txm_module_thread_shell_entry.c index e0c84d32..1bcfe689 100644 --- a/ports_module/cortex_m23/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m23/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID __iar_data_init3(VOID); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the IAR C environment. */ __iar_data_init3(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m23/iar/module_lib/src/txm_thread_secure_stack_allocate.c b/ports_module/cortex_m23/iar/module_lib/src/txm_thread_secure_stack_allocate.c index 05a922d4..95c101de 100644 --- a/ports_module/cortex_m23/iar/module_lib/src/txm_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m23/iar/module_lib/src/txm_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { diff --git a/ports_module/cortex_m23/iar/module_lib/src/txm_thread_secure_stack_free.c b/ports_module/cortex_m23/iar/module_lib/src/txm_thread_secure_stack_free.c index 61c852b5..47c718a0 100644 --- a/ports_module/cortex_m23/iar/module_lib/src/txm_thread_secure_stack_free.c +++ b/ports_module/cortex_m23/iar/module_lib/src/txm_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { diff --git a/ports_module/cortex_m23/iar/module_manager/inc/txm_module_manager_dispatch_port.h b/ports_module/cortex_m23/iar/module_manager/inc/txm_module_manager_dispatch_port.h index 8bbcd5b3..0575c748 100644 --- a/ports_module/cortex_m23/iar/module_manager/inc/txm_module_manager_dispatch_port.h +++ b/ports_module/cortex_m23/iar/module_manager/inc/txm_module_manager_dispatch_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_restore.s index 83ab38c9..11f3d018 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_save.s index 8ea8a775..bb6b9d51 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_control.s index 1e5e1973..5a74b366 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_disable.s index 375c9926..6b95841a 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_restore.s index 3768cfb3..c5a40257 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_schedule.s index 5c7aafaa..f7f933e0 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,20 +69,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -178,7 +165,7 @@ BusFault_Handler: STR r0, [r2, #88] // Save xPSR MRS r0, CONTROL // Pickup current CONTROL register - MOVW r1, #0x1 // + MOVW r1, #0x1 // BICS r0, r0, r1 // Clear the UNPRIV bit MSR CONTROL, r0 // Setup new CONTROL register @@ -413,7 +400,7 @@ _tx_enable_mpu: MOVS r1, #5 // Build enable value with background region enabled STR r1, [r0] // Enable MPU MOV r1, r8 // Get copied thread ptr - + skip_mpu_setup: // Restore the thread context and PSP @@ -519,7 +506,7 @@ _tx_entry_continue: _tx_skip_kernel_stack_enter: MRS r0, CONTROL // Pickup current CONTROL register - MOVW r1, #0x1 // + MOVW r1, #0x1 // BICS r0, r0, r1 // Clear the UNPRIV bit MSR CONTROL, r0 // Setup new CONTROL register BX lr // Return to thread @@ -600,7 +587,7 @@ _tx_alloc_continue: STR r0, [r1] // Store function return value MOV lr, r2 BX lr - + _tx_svc_secure_free: LDR r2, =_tx_free_return-1 // Load address of where we should have come from CMP r1, r2 // Did we come from _tx_thread_secure_stack_free? diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack.c index 099097fb..9ce9ccc3 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack.c +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -102,21 +103,6 @@ static INT tx_head_free_index = 0U; /* */ /* _tx_initialize_kernel_enter */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-16-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.1 */ -/* 06-02-2021 Scott Larson Modified comment(s), changed */ -/* name, execute in handler */ -/* mode, disable optimization, */ -/* resulting in version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments, updated */ -/* secure stack allocation, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_initialize(void) diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_allocate.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_allocate.s index bc935c8b..7c7dfacf 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_allocate.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_allocate.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,13 +53,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) // { diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_free.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_free.s index e99f7bf3..0701c03c 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_free.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_free.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,13 +51,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) // { diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_initialize.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_initialize.s index 95f0c250..325a62bf 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_initialize.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_initialize.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,17 +51,6 @@ /* CALLED BY */ /* */ /* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) // { diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_build.s index bbb60ae6..71d25cec 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { @@ -90,7 +84,7 @@ _tx_thread_stack_build: Stack Bottom: (higher memory address) */ LDR r2, [r0, #16] // Pickup end of stack area - MOVW r3, #0x7 // + MOVW r3, #0x7 // BICS r2, r2, r3 // Align frame for 8-byte alignment SUBS r2, r2, #68 // Subtract frame size #ifdef TX_SINGLE_MODE_SECURE diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_system_return.s index f574ed35..91ef52c7 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m23/iar/module_manager/src/tx_timer_interrupt.s index 9dd72463..eadef8bf 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,13 +68,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_allocate.c b/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_allocate.c index 6c394cae..9bade139 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { @@ -76,10 +71,10 @@ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_siz return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_free.c b/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_free.c index a2f81e77..75a26945 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_free.c +++ b/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { @@ -74,10 +69,10 @@ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_alignment_adjust.c index c520f155..e1534699 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, @@ -77,7 +72,7 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, /* Round code and data size UP to TXM_MODULE_MPU_ALIGNMENT bytes. */ *code_size = (*code_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); *data_size = (*data_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); - + /* Alignment for code and data is TXM_MODULE_MPU_ALIGNMENT bytes. */ *code_alignment = TXM_MODULE_MPU_ALIGNMENT; *data_alignment = TXM_MODULE_MPU_ALIGNMENT; diff --git a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_external_memory_enable.c index 004d5fe1..1c7c1b47 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -105,7 +100,7 @@ ULONG shared_index; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -115,49 +110,49 @@ ULONG shared_index; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address must adhere to Cortex-M23 MPU alignment. */ address = (ULONG) start_address; if(address != (address & ~(TXM_MODULE_MPU_ALIGNMENT - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Set base address register with start address, sanitized attributes and execute never. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_base_address = address | (attributes & TXM_MODULE_ATTRIBUTE_MASK) | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; - + /* Set the limit address (data start + length-1), attribute index, and enable bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_limit_address = (address + length-1) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index c7107a60..c31c70fc 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index 6831e0df..3223b566 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_mm_register_setup.c index 3adcf647..55abbe5e 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _txm_module_manager_thread_create */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) { @@ -91,27 +86,27 @@ ULONG callback_stack_size; /* Set base address register to module data address, which should be at least 32-byte aligned. Mask address to proper range, inner shareable, read write, execute never. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_base_address = ((ULONG) module_instance -> txm_module_instance_data_start & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE | TXM_MODULE_ATTRIBUTE_READ_WRITE | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Set the limit address (data start + data size-1), attribute index, and enable bit. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_limit_address = (((ULONG) module_instance -> txm_module_instance_data_start + data_size - 1) & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; /* End of module data protection. */ - + /* Remaining MPU entries are disabled for now and can be used for shared memory. */ } @@ -168,7 +163,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_port_dispatch.c index d2c0862e..07a2e9fc 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_port_dispatch.c +++ b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_port_dispatch.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* _txm_module_manager_kernel_dispatch */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) { @@ -88,7 +83,7 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; ); break; } - + case TXM_THREAD_SECURE_STACK_FREE_CALL: { if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) @@ -102,13 +97,13 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; ); break; } - + default: { /* Unhandled kernel request, return an error! */ break; } } - + return(return_value); } diff --git a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_thread_stack_build.s index ed95928c..a60e86df 100644 --- a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { @@ -91,7 +85,7 @@ _txm_module_manager_thread_stack_build: Stack Bottom: (higher memory address) */ LDR r2, [r0, #16] // Pickup end of stack area - MOVW r3, #0x7 // + MOVW r3, #0x7 // BICS r2, r2, r3 // Align frame for 8-byte alignment SUBS r2, r2, #68 // Subtract frame size #ifdef TX_SINGLE_MODE_SECURE diff --git a/ports_module/cortex_m3/ac5/example_build/sample_threadx.c b/ports_module/cortex_m3/ac5/example_build/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports_module/cortex_m3/ac5/example_build/sample_threadx.c +++ b/ports_module/cortex_m3/ac5/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_m3/ac5/example_build/sample_threadx_module.c b/ports_module/cortex_m3/ac5/example_build/sample_threadx_module.c index f2647144..dcf73ef9 100644 --- a/ports_module/cortex_m3/ac5/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m3/ac5/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -26,7 +26,7 @@ #define EXTERNAL_MEMORY (0x80000) -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -107,7 +107,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -123,7 +123,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -135,42 +135,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -178,23 +178,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -238,7 +238,7 @@ void thread_0_entry(ULONG thread_input) { UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -248,7 +248,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -296,18 +296,18 @@ UINT status; { /* Test external memory sharing. */ *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -366,7 +366,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -419,7 +419,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m3/ac5/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m3/ac5/example_build/sample_threadx_module_manager.c index 210f0be0..4edcee3c 100644 --- a/ports_module/cortex_m3/ac5/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m3/ac5/example_build/sample_threadx_module_manager.c @@ -71,8 +71,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -92,22 +92,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); - + /* Enable a read/write shared memory region. */ txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -116,11 +116,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m3/ac5/example_build/tx_initialize_low_level.S b/ports_module/cortex_m3/ac5/example_build/tx_initialize_low_level.S index 951a71d8..057ccc9a 100644 --- a/ports_module/cortex_m3/ac5/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m3/ac5/example_build/tx_initialize_low_level.S @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -93,7 +93,7 @@ __tx_vectors DCD __tx_IntHandler ; Int 1 DCD __tx_IntHandler ; Int 2 DCD __tx_IntHandler ; Int 3 - + ; ; AREA ||.text||, CODE, READONLY @@ -111,45 +111,39 @@ Reset_Handler BX r0 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-M3/MPU/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-M3/MPU/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -162,24 +156,24 @@ _tx_initialize_low_level CPSID i ; ; /* Set base of available memory to end of non-initialised RAM area. */ -; +; LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer LDR r1, =|Image$$ZI$$Limit| ; Build first free address - ADD r1, r1, #4 ; + ADD r1, r1, #4 ; STR r1, [r0] ; Setup first unused memory pointer ; ; /* Setup Vector Table Offset Register. */ -; +; MOV r0, #0xE000E000 ; Build address of NVIC registers LDR r1, =__tx_vectors ; Pickup address of vector table - STR r1, [r0, #0xD08] ; Set vector table address + STR r1, [r0, #0xD08] ; Set vector table address ; ; /* Enable the cycle count register. */ ; ; LDR r0, =0xE0001000 ; Build address of DWT register ; LDR r1, [r0] ; Pickup the current value ; ORR r1, r1, #1 ; Set the CYCCNTENA bit -; STR r1, [r0] ; Enable the cycle count register +; STR r1, [r0] ; Enable the cycle count register ; ; /* Set system stack pointer from vector value. */ ; @@ -210,11 +204,11 @@ _tx_initialize_low_level ; Note: PnSV must be lowest priority, which is 0xFF ; ; /* Return to caller. */ -; - BX lr +; + BX lr ;} ; -; +; ;/* Define initial heap/stack routine for the ARM RVCT startup code. ; This routine will set the initial stack and heap locations */ ; @@ -230,19 +224,19 @@ __user_initial_stackheap ;/* Define shells for each of the unused vectors. */ ; EXPORT __tx_BadHandler -__tx_BadHandler +__tx_BadHandler B __tx_BadHandler ; EXPORT __tx_SVCallHandler ;__tx_SVCallHandler -; B __tx_SVCallHandler +; B __tx_SVCallHandler EXPORT __tx_IntHandler __tx_IntHandler ; VOID InterruptHandler (VOID) ; { PUSH {lr} - + ; /* Do interrupt handler work here */ ; /* .... */ @@ -261,7 +255,7 @@ __tx_SysTickHandler BX LR ; } - EXPORT __tx_NMIHandler + EXPORT __tx_NMIHandler __tx_NMIHandler B __tx_NMIHandler @@ -280,5 +274,5 @@ _tx_execution_thread_exit ALIGN LTORG END - + diff --git a/ports_module/cortex_m3/ac5/inc/tx_port.h b/ports_module/cortex_m3/ac5/inc/tx_port.h index b566bda3..eb5c4a30 100644 --- a/ports_module/cortex_m3/ac5/inc/tx_port.h +++ b/ports_module/cortex_m3/ac5/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,15 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -243,7 +235,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -376,7 +368,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -535,7 +527,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #else #error "Compiler not supported." #endif @@ -719,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M3 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m3/ac5/inc/txm_module_port.h b/ports_module/cortex_m3/ac5/inc/txm_module_port.h index 667330d7..a6a619a4 100644 --- a/ports_module/cortex_m3/ac5/inc/txm_module_port.h +++ b/ports_module/cortex_m3/ac5/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,24 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* 07-29-2022 Scott Larson Enabled user-defined and */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Configure heap size, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Set default values for RBAR, */ -/* unify this file for all */ -/* compilers, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -463,6 +446,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M3 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M3 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m3/ac5/module_lib/src/txm_module_initialize.s b/ports_module/cortex_m3/ac5/module_lib/src/txm_module_initialize.s index 0c1a90c4..3e18af11 100644 --- a/ports_module/cortex_m3/ac5/module_lib/src/txm_module_initialize.s +++ b/ports_module/cortex_m3/ac5/module_lib/src/txm_module_initialize.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _txm_module_thread_shell_entry Start module thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_initialize(VOID) diff --git a/ports_module/cortex_m3/ac5/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m3/ac5/module_lib/src/txm_module_thread_shell_entry.c index 8884a54f..b1e803f9 100644 --- a/ports_module/cortex_m3/ac5/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m3/ac5/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -87,12 +88,6 @@ __align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE]; /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -108,14 +103,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _txm_module_initialize(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -123,7 +118,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_restore.s index 23503273..d8c8d6dd 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_save.s index 75a68861..3d59c966 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_control.s index 050d349d..340ef0f6 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_disable.s index 01642018..86308572 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_restore.s index d5b937f6..917db4e4 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_schedule.s index 7313d2ff..e698f259 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,23 +67,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, optional */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* fixed label syntax, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_stack_build.s index fa77e2d6..6639bdf8 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_system_return.s index 53d48047..e10d05c6 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m3/ac5/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m3/ac5/module_manager/src/tx_timer_interrupt.s index b87639de..68b30e98 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m3/ac5/module_manager/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,18 +72,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_alignment_adjust.c index b7d5d1d0..91b9087d 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 32. */ if(size <= 32) return 32; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_external_memory_enable.c index 894098db..baa40100 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Update defines, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -114,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -124,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -224,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -234,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -246,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c index 50305a72..ead02314 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c index 60fd7c07..16ff0dcf 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_mm_register_setup.c index 67422c03..987a6667 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -94,16 +95,6 @@ const ULONG txm_module_default_mpu_registers[32] = /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Changed from lookup table to */ -/* calculation and check for */ -/* minumum block size, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_thread_stack_build.s index f118dc53..d800c32a 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_user_mode_entry.s b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_user_mode_entry.s index fab47c06..d5f331f2 100644 --- a/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_user_mode_entry.s +++ b/ports_module/cortex_m3/ac5/module_manager/src/txm_module_manager_user_mode_entry.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,13 +55,6 @@ /* CALLED BY */ /* */ /* Modules in user mode */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_user_mode_entry(VOID) // { diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx/.cproject b/ports_module/cortex_m3/ac6/example_build/sample_threadx/.cproject index 774d26ab..db508892 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx/.cproject +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx/.cproject @@ -1,192 +1,192 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx/exceptions.c b/ports_module/cortex_m3/ac6/example_build/sample_threadx/exceptions.c index 01dd0b27..4ff00618 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx/exceptions.c +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx/exceptions.c @@ -1,7 +1,7 @@ /* ** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ** Use, modification and redistribution of this file is subject to your possession of a -** valid End User License Agreement for the Arm Product of which these examples are part of +** valid End User License Agreement for the Arm Product of which these examples are part of ** and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.c index 597f373c..13ffadba 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -81,42 +81,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -124,23 +124,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -243,11 +243,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -306,7 +306,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -359,7 +359,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_module/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.scat index f093ce05..c307d211 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 98d3abb0..72f44643 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,12 +75,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/.cproject b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/.cproject index 3c6f49d9..4f468747 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/.cproject +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/.cproject @@ -1,218 +1,218 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/sample_threadx_module.c index f2647144..dcf73ef9 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -26,7 +26,7 @@ #define EXTERNAL_MEMORY (0x80000) -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -107,7 +107,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -123,7 +123,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -135,42 +135,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -178,23 +178,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -238,7 +238,7 @@ void thread_0_entry(ULONG thread_input) { UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -248,7 +248,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -296,18 +296,18 @@ UINT status; { /* Test external memory sharing. */ *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -366,7 +366,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -419,7 +419,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/txm_module_preamble.S index 1fcc5d15..71914151 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -2,7 +2,7 @@ .align 4 .syntax unified .section Init - + // Define public symbols .global __txm_module_preamble diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/.cproject index 08b7a614..109a9c00 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/.cproject +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/.cproject @@ -1,172 +1,172 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/exceptions.c b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/exceptions.c index 0cef25ce..fc26b89c 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/exceptions.c +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/exceptions.c @@ -1,7 +1,7 @@ /* ** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ** Use, modification and redistribution of this file is subject to your possession of a -** valid End User License Agreement for the Arm Product of which these examples are part of +** valid End User License Agreement for the Arm Product of which these examples are part of ** and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat index f093ce05..c307d211 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index 210f0be0..4edcee3c 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -71,8 +71,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -92,22 +92,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); - + /* Enable a read/write shared memory region. */ txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -116,11 +116,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S index 4331ef40..5f263cae 100644 --- a/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S +++ b/ports_module/cortex_m3/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,12 +75,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_m3/ac6/example_build/tx/.cproject b/ports_module/cortex_m3/ac6/example_build/tx/.cproject index 06929bd2..a91b3227 100644 --- a/ports_module/cortex_m3/ac6/example_build/tx/.cproject +++ b/ports_module/cortex_m3/ac6/example_build/tx/.cproject @@ -1,162 +1,162 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_m3/ac6/example_build/txm/.cproject b/ports_module/cortex_m3/ac6/example_build/txm/.cproject index dd64d0bf..a32c52b5 100644 --- a/ports_module/cortex_m3/ac6/example_build/txm/.cproject +++ b/ports_module/cortex_m3/ac6/example_build/txm/.cproject @@ -1,184 +1,184 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_m3/ac6/inc/tx_port.h b/ports_module/cortex_m3/ac6/inc/tx_port.h index b566bda3..eb5c4a30 100644 --- a/ports_module/cortex_m3/ac6/inc/tx_port.h +++ b/ports_module/cortex_m3/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,15 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -243,7 +235,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -376,7 +368,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -535,7 +527,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #else #error "Compiler not supported." #endif @@ -719,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M3 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m3/ac6/inc/txm_module_port.h b/ports_module/cortex_m3/ac6/inc/txm_module_port.h index 667330d7..a6a619a4 100644 --- a/ports_module/cortex_m3/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m3/ac6/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,24 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* 07-29-2022 Scott Larson Enabled user-defined and */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Configure heap size, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Set default values for RBAR, */ -/* unify this file for all */ -/* compilers, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -463,6 +446,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M3 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M3 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m3/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_m3/ac6/module_lib/src/txm_module_initialize.S index 6f184df2..882a7d1c 100644 --- a/ports_module/cortex_m3/ac6/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_m3/ac6/module_lib/src/txm_module_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* _txm_module_thread_shell_entry Start module thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user configurable, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _txm_module_initialize(VOID) .global _txm_module_initialize diff --git a/ports_module/cortex_m3/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m3/ac6/module_lib/src/txm_module_thread_shell_entry.c index 45d8b720..518704d7 100644 --- a/ports_module/cortex_m3/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m3/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -88,15 +89,6 @@ extern VOID _txm_module_initialize(VOID *heap_base, VOID *heap_top); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user configurable, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -112,14 +104,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _txm_module_initialize(&txm_heap[0], &txm_heap[TXM_MODULE_HEAP_SIZE-1]); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -127,7 +119,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_restore.S index 949478b5..bc2b4752 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_save.S index f6a10399..22f46a26 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,14 +61,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_control.S index dcc24d49..c2435528 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_disable.S index a1a0b459..37525e38 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_restore.S index bc5b910a..3c3e2473 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_schedule.S index ed1e99b2..56187f4c 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -69,21 +70,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, optional */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_stack_build.S index d5cc0b49..31303ef8 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S index e7471605..e1c5c2a2 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m3/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m3/ac6/module_manager/src/tx_timer_interrupt.S index ee13bef8..05d5c227 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,17 +71,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_alignment_adjust.c index b7d5d1d0..91b9087d 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 32. */ if(size <= 32) return 32; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_external_memory_enable.c index 894098db..baa40100 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Update defines, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -114,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -124,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -224,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -234,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -246,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c index 50305a72..ead02314 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c index 60fd7c07..16ff0dcf 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index 67422c03..987a6667 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -94,16 +95,6 @@ const ULONG txm_module_default_mpu_registers[32] = /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Changed from lookup table to */ -/* calculation and check for */ -/* minumum block size, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { diff --git a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index de5794dc..3d8485ce 100644 --- a/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m3/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m3/gnu/example_build/cortexm_crt0.s b/ports_module/cortex_m3/gnu/example_build/cortexm_crt0.s index d4cb1636..61ca8259 100644 --- a/ports_module/cortex_m3/gnu/example_build/cortexm_crt0.s +++ b/ports_module/cortex_m3/gnu/example_build/cortexm_crt0.s @@ -66,7 +66,7 @@ crt0_ctor_loop: beq crt0_ctor_end ldr r2, [r0] add r0, #4 - push {r0-r1} + push {r0-r1} blx r2 pop {r0-r1} b crt0_ctor_loop @@ -88,7 +88,7 @@ start: /* when main returns, loop forever. */ crt0_exit_loop: b crt0_exit_loop - + /* Startup helper functions. */ @@ -124,4 +124,3 @@ memory_set_done: .section .stack, "wa", %nobits .section .stack_process, "wa", %nobits .section .heap, "wa", %nobits - \ No newline at end of file diff --git a/ports_module/cortex_m3/gnu/example_build/gcc_setup.s b/ports_module/cortex_m3/gnu/example_build/gcc_setup.s index d7c61892..4a729ffe 100644 --- a/ports_module/cortex_m3/gnu/example_build/gcc_setup.s +++ b/ports_module/cortex_m3/gnu/example_build/gcc_setup.s @@ -14,7 +14,7 @@ _gcc_setup: mov r5,r0 /* Copy GOT table. */ - + ldr r0, =__got_load_start__ sub r0,r0,r3 add r0,r0,r5 @@ -42,13 +42,13 @@ flash_area: address_built: str r6, [r1] // Store in new GOT table add r0, r0, #4 // Move to next entry - add r1, r1, #4 // + add r1, r1, #4 // b new_got_setup // Continue at the top of the loop got_setup_done: /* Copy initialised sections into RAM if required. */ - + ldr r0, =__data_load_start__ sub r0,r0,r3 add r0,r0,r5 @@ -59,9 +59,9 @@ got_setup_done: sub r2,r2,r4 add r2,r2,r9 bl crt0_memory_copy - + /* Zero bss. */ - + ldr r0, =__bss_start__ sub r0,r0,r4 add r0,r0,r9 @@ -85,10 +85,10 @@ got_setup_done: str r2, [r0] add r0, r0, #4 str r1, [r0] - + LDMIA sp!, {r3, r4, r5, r6, r7, lr} // Store other preserved registers bx lr // Return to caller - + .align 4 /* Startup helper functions. */ @@ -124,4 +124,3 @@ memory_set_done: /* Setup attibutes of heap section so it doesn't take up room in the elf file */ .section .heap, "wa", %nobits - \ No newline at end of file diff --git a/ports_module/cortex_m3/gnu/example_build/sample_threadx_module.c b/ports_module/cortex_m3/gnu/example_build/sample_threadx_module.c index 52557312..b74d7a35 100644 --- a/ports_module/cortex_m3/gnu/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m3/gnu/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -101,7 +101,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -117,7 +117,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -129,42 +129,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -172,23 +172,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -233,7 +233,7 @@ void thread_0_entry(ULONG thread_input) UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -243,7 +243,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -291,19 +291,19 @@ UINT status; { /* Test memory handler. */ *(ULONG *)0x20010000 = 0xCDCDCDCD; - - + + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -362,7 +362,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -415,7 +415,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m3/gnu/example_build/sample_threadx_module.ld b/ports_module/cortex_m3/gnu/example_build/sample_threadx_module.ld index 30c66655..5fa4c680 100644 --- a/ports_module/cortex_m3/gnu/example_build/sample_threadx_module.ld +++ b/ports_module/cortex_m3/gnu/example_build/sample_threadx_module.ld @@ -125,7 +125,7 @@ SECTIONS KEEP (*(.got*)) . = ALIGN(4); _egot = .; - } + } __got_end__ = __got_load_start__ + SIZEOF(.got); __rodata_load_start__ = ALIGN(__got_end__ , 4); @@ -135,7 +135,7 @@ SECTIONS *(.rodata .rodata.* .gnu.linkonce.r.*) } __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); - + __code_size__ = SIZEOF(.data) + __rodata_end__ - __FLASH_segment_start__; __fast_load_start__ = ALIGN(__rodata_end__ , 4); diff --git a/ports_module/cortex_m3/gnu/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m3/gnu/example_build/sample_threadx_module_manager.c index 203223be..feaaf2af 100644 --- a/ports_module/cortex_m3/gnu/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m3/gnu/example_build/sample_threadx_module_manager.c @@ -54,8 +54,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -75,22 +75,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_memory_load(&my_module, "my module", (VOID *) 0x00030000); - + /* Enable 128 byte read/write shared memory region at 0x20010000. */ txm_module_manager_external_memory_enable(&my_module, (void *) 0x20010000, 128, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -99,11 +99,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m3/gnu/example_build/tx_initialize_low_level.S b/ports_module/cortex_m3/gnu/example_build/tx_initialize_low_level.S index e9c66cc0..edc1eef3 100644 --- a/ports_module/cortex_m3/gnu/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m3/gnu/example_build/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -73,12 +74,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ //VOID _tx_initialize_low_level(VOID) //{ @@ -91,14 +86,14 @@ _tx_initialize_low_level: /* Set base of available memory to end of non-initialised RAM area. */ LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer - LDR r1, =__RAM_segment_used_end__ @ Build first free address - ADD r1, r1, #4 @ + LDR r1, =__RAM_segment_used_end__ @ Build first free address + ADD r1, r1, #4 @ STR r1, [r0] @ Setup first unused memory pointer /* Setup Vector Table Offset Register. */ MOV r0, #0xE000E000 @ Build address of NVIC registers - LDR r1, =_vectors @ Pickup address of vector table - STR r1, [r0, #0xD08] @ Set vector table address + LDR r1, =_vectors @ Pickup address of vector table + STR r1, [r0, #0xD08] @ Set vector table address /* Set system stack pointer from vector value. */ LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer @@ -110,7 +105,7 @@ _tx_initialize_low_level: LDR r0, =0xE0001000 @ Build address of DWT register LDR r1, [r0] @ Pickup the current value ORR r1, r1, #1 @ Set the CYCCNTENA bit - STR r1, [r0] @ Enable the cycle count register + STR r1, [r0] @ Enable the cycle count register /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ MOV r0, #0xE000E000 @ Build address of NVIC registers @@ -130,10 +125,10 @@ _tx_initialize_low_level: LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers @ Note: PnSV must be lowest priority, which is 0xFF - + /* Return to caller. */ - BX lr + BX lr //} @@ -160,7 +155,7 @@ __tx_IntHandler: PUSH {r0, lr} #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY BL _tx_execution_isr_enter // Call the ISR enter function -#endif +#endif /* Do interrupt handler work here */ /* BL .... */ @@ -196,7 +191,7 @@ SysTick_Handler: /* NMI, DBG handlers */ - .global __tx_NMIHandler + .global __tx_NMIHandler .thumb_func __tx_NMIHandler: B __tx_NMIHandler diff --git a/ports_module/cortex_m3/gnu/example_build/tx_simulator_startup.s b/ports_module/cortex_m3/gnu/example_build/tx_simulator_startup.s index 73692924..ef3d9314 100644 --- a/ports_module/cortex_m3/gnu/example_build/tx_simulator_startup.s +++ b/ports_module/cortex_m3/gnu/example_build/tx_simulator_startup.s @@ -6,9 +6,9 @@ .global _vectors _vectors: - .word __stack_end__ - .word reset_handler - .word __tx_NMIHandler + .word __stack_end__ + .word reset_handler + .word __tx_NMIHandler .word __tx_HardfaultHandler .word MemManage_Handler .word BusFault_Handler @@ -20,7 +20,7 @@ _vectors: .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // .word __tx_DBGHandler .word 0 // Reserved - .word __tx_PendSVHandler + .word __tx_PendSVHandler .word __tx_SysTickHandler // Used by Threadx timer functionality .word __tx_BadHandler // Populate with user Interrupt handler .word __tx_BadHandler diff --git a/ports_module/cortex_m3/gnu/example_build/txm_module_preamble.S b/ports_module/cortex_m3/gnu/example_build/txm_module_preamble.S index 50814cc8..b032a347 100644 --- a/ports_module/cortex_m3/gnu/example_build/txm_module_preamble.S +++ b/ports_module/cortex_m3/gnu/example_build/txm_module_preamble.S @@ -33,7 +33,7 @@ __txm_module_preamble: // 1 -> User mode execution .dc.l _txm_module_thread_shell_entry - . - 0 // Module Shell Entry Point .dc.l demo_module_start - . - 0 // Module Start Thread Entry Point - .dc.l 0 // Module Stop Thread Entry Point + .dc.l 0 // Module Stop Thread Entry Point .dc.l 1 // Module Start/Stop Thread Priority .dc.l 1024 // Module Start/Stop Thread Stack Size .dc.l _txm_module_callback_request_thread_entry - . - 0 // Module Callback Thread Entry diff --git a/ports_module/cortex_m3/gnu/inc/tx_port.h b/ports_module/cortex_m3/gnu/inc/tx_port.h index b566bda3..eb5c4a30 100644 --- a/ports_module/cortex_m3/gnu/inc/tx_port.h +++ b/ports_module/cortex_m3/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,15 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -243,7 +235,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -376,7 +368,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -535,7 +527,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #else #error "Compiler not supported." #endif @@ -719,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M3 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m3/gnu/inc/txm_module_port.h b/ports_module/cortex_m3/gnu/inc/txm_module_port.h index 667330d7..a6a619a4 100644 --- a/ports_module/cortex_m3/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m3/gnu/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,24 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* 07-29-2022 Scott Larson Enabled user-defined and */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Configure heap size, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Set default values for RBAR, */ -/* unify this file for all */ -/* compilers, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -463,6 +446,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M3 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M3 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m3/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m3/gnu/module_lib/src/txm_module_thread_shell_entry.c index eec57f67..e8af97a9 100644 --- a/ports_module/cortex_m3/gnu/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m3/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _gcc_setup(thread_info -> txm_module_thread_entry_info_code_base_address); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_restore.S index f36f0e79..1862bb58 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_save.S index bcc690d0..ac76a239 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_control.S index e7ea870e..a56149e3 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_disable.S index b0169c6d..dee2237f 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_restore.S index ef0298b4..bd00f5f7 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_schedule.S index aeff0993..8336214b 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,23 +68,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Fixed predefined macro name, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, optional */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_stack_build.S index d78ebdc1..5b7d97c4 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_system_return.S index 3fa0c7a2..9d9a32fc 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m3/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m3/gnu/module_manager/src/tx_timer_interrupt.S index fc3e9db3..7f9a4359 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m3/gnu/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,17 +71,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_alignment_adjust.c index b7d5d1d0..91b9087d 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 32. */ if(size <= 32) return 32; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_external_memory_enable.c index 894098db..baa40100 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Update defines, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -114,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -124,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -224,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -234,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -246,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c index 50305a72..ead02314 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c index 60fd7c07..16ff0dcf 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index 67422c03..987a6667 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -94,16 +95,6 @@ const ULONG txm_module_default_mpu_registers[32] = /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Changed from lookup table to */ -/* calculation and check for */ -/* minumum block size, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { diff --git a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_thread_stack_build.s index 068ed64a..d7141d93 100644 --- a/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m3/gnu/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,13 +55,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m3/iar/example_build/cstartup_M.s b/ports_module/cortex_m3/iar/example_build/cstartup_M.s index 75d9369b..d1c5aa3e 100644 --- a/ports_module/cortex_m3/iar/example_build/cstartup_M.s +++ b/ports_module/cortex_m3/iar/example_build/cstartup_M.s @@ -2,16 +2,16 @@ PUBLIC __vector_table SECTION .text:CODE:REORDER(1) - + ;; Keep vector table even if it's not referenced REQUIRE __vector_table - + THUMB - + ;; Forward declaration of sections. SECTION CSTACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) - + DATA __vector_table diff --git a/ports_module/cortex_m3/iar/example_build/sample_threadx.c b/ports_module/cortex_m3/iar/example_build/sample_threadx.c index c67d75d0..a12160fa 100644 --- a/ports_module/cortex_m3/iar/example_build/sample_threadx.c +++ b/ports_module/cortex_m3/iar/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -85,7 +85,7 @@ CHAR *pointer = TX_NULL; #ifdef TX_ENABLE_EVENT_TRACE tx_trace_enable(trace_buffer, sizeof(trace_buffer), 32); #endif - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(&byte_pool_0, "byte pool 0", byte_pool_memory, DEMO_BYTE_POOL_SIZE); @@ -96,42 +96,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -139,23 +139,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -258,11 +258,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -321,7 +321,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -374,7 +374,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_m3/iar/example_build/sample_threadx_module.c b/ports_module/cortex_m3/iar/example_build/sample_threadx_module.c index 939433cd..e9605af8 100644 --- a/ports_module/cortex_m3/iar/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m3/iar/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -101,7 +101,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -117,7 +117,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -129,42 +129,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -172,23 +172,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -233,7 +233,7 @@ void thread_0_entry(ULONG thread_input) UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -243,7 +243,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -291,19 +291,19 @@ UINT status; { /* Test memory handler. */ *(ULONG *)0x64005000 = 0xCDCDCDCD; - - + + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -362,7 +362,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -415,7 +415,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m3/iar/example_build/sample_threadx_module.icf b/ports_module/cortex_m3/iar/example_build/sample_threadx_module.icf index 8cfe4766..167c26fb 100644 --- a/ports_module/cortex_m3/iar/example_build/sample_threadx_module.icf +++ b/ports_module/cortex_m3/iar/example_build/sample_threadx_module.icf @@ -35,11 +35,11 @@ do not initialize { section .noinit }; //place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -define movable block ROPI with alignment = 4, fixed order -{ +define movable block ROPI with alignment = 4, fixed order +{ ro object txm_module_preamble.o, - ro, - ro data + ro, + ro data }; define movable block RWPI with alignment = 8, fixed order, static base diff --git a/ports_module/cortex_m3/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m3/iar/example_build/sample_threadx_module_manager.c index ca18eea6..b7d88a09 100644 --- a/ports_module/cortex_m3/iar/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m3/iar/example_build/sample_threadx_module_manager.c @@ -54,8 +54,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -75,22 +75,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x080F0000); - + /* Enable 128 byte read/write shared memory region at 0x64005000. */ txm_module_manager_external_memory_enable(&my_module, (void *) 0x64005000, 128, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -99,11 +99,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m3/iar/example_build/sample_threadx_module_manager.icf b/ports_module/cortex_m3/iar/example_build/sample_threadx_module_manager.icf index 5e6f652e..92334d1e 100644 --- a/ports_module/cortex_m3/iar/example_build/sample_threadx_module_manager.icf +++ b/ports_module/cortex_m3/iar/example_build/sample_threadx_module_manager.icf @@ -18,8 +18,8 @@ define symbol __ICFEDIT_size_heap__ = 0x200; define memory mem with size = 4G; define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__]; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; diff --git a/ports_module/cortex_m3/iar/example_build/startup.s b/ports_module/cortex_m3/iar/example_build/startup.s index bbe8142b..2eb88dff 100644 --- a/ports_module/cortex_m3/iar/example_build/startup.s +++ b/ports_module/cortex_m3/iar/example_build/startup.s @@ -6,10 +6,10 @@ ;* Description : STM32F2xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP -;* - Configure he external SRAM mounted on STM322xG-EVAL board +;* - Configure he external SRAM mounted on STM322xG-EVAL board ;* to be used as data memory (optional, to be enabled by user) ;* - Set the initial PC == __iar_program_start, -;* - Set the vector table entries with the exceptions ISR +;* - Set the vector table entries with the exceptions ISR ;* address. ;* After Reset the Cortex-M3 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. @@ -72,86 +72,86 @@ __vector_table DC32 SysTick_Handler ; SysTick ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FSMC_IRQHandler ; FSMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD CRYP_IRQHandler ; CRYP crypto + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto DCD HASH_RNG_IRQHandler ; Hash and Rng ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -164,7 +164,7 @@ __vector_table Reset_Handler CPSID i ; Disable interrupts LDR R0, =sfe(CSTACK) ; restore original stack pointer - MSR MSP, R0 + MSR MSP, R0 LDR R0, =__iar_program_start ; Jump to ThreadX start, which will call IAR startup code BX R0 @@ -215,47 +215,47 @@ SysTick_Handler PUBWEAK WWDG_IRQHandler SECTION .text:CODE:NOROOT(2) -WWDG_IRQHandler +WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_IRQHandler SECTION .text:CODE:NOROOT(2) -PVD_IRQHandler +PVD_IRQHandler B PVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:NOROOT(2) -TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT(2) +TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:NOROOT(2) -RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:NOROOT(2) -FLASH_IRQHandler +FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:NOROOT(2) -RCC_IRQHandler +RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:NOROOT(2) -EXTI0_IRQHandler +EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:NOROOT(2) -EXTI1_IRQHandler +EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:NOROOT(2) -EXTI2_IRQHandler +EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler @@ -264,358 +264,358 @@ EXTI3_IRQHandler B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT(2) -EXTI4_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:NOROOT(2) -ADC_IRQHandler +ADC_IRQHandler B ADC_IRQHandler PUBWEAK CAN1_TX_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_TX_IRQHandler B CAN1_TX_IRQHandler PUBWEAK CAN1_RX0_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_RX0_IRQHandler B CAN1_RX0_IRQHandler PUBWEAK CAN1_RX1_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_RX1_IRQHandler B CAN1_RX1_IRQHandler PUBWEAK CAN1_SCE_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN1_SCE_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_SCE_IRQHandler B CAN1_SCE_IRQHandler PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:NOROOT(2) -EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_TIM9_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_BRK_TIM9_IRQHandler B TIM1_BRK_TIM9_IRQHandler PUBWEAK TIM1_UP_TIM10_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_UP_TIM10_IRQHandler B TIM1_UP_TIM10_IRQHandler PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_TRG_COM_TIM11_IRQHandler B TIM1_TRG_COM_TIM11_IRQHandler - + PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:NOROOT(2) -TIM2_IRQHandler +TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:NOROOT(2) -TIM3_IRQHandler +TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:NOROOT(2) -TIM4_IRQHandler +TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:NOROOT(2) -SPI1_IRQHandler +SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:NOROOT(2) -SPI2_IRQHandler +SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:NOROOT(2) -USART1_IRQHandler +USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:NOROOT(2) -USART2_IRQHandler +USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:NOROOT(2) -USART3_IRQHandler +USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:NOROOT(2) -EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT(2) -RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT(2) +RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT(2) -OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_FS_WKUP_IRQHandler B OTG_FS_WKUP_IRQHandler - + PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FSMC_IRQHandler SECTION .text:CODE:NOROOT(2) -FSMC_IRQHandler +FSMC_IRQHandler B FSMC_IRQHandler PUBWEAK SDIO_IRQHandler SECTION .text:CODE:NOROOT(2) -SDIO_IRQHandler +SDIO_IRQHandler B SDIO_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:NOROOT(2) -TIM5_IRQHandler +TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:NOROOT(2) -SPI3_IRQHandler +SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:NOROOT(2) -UART4_IRQHandler +UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:NOROOT(2) -UART5_IRQHandler +UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM7_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:NOROOT(2) -ETH_IRQHandler +ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:NOROOT(2) -ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK CAN2_TX_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN2_TX_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_TX_IRQHandler B CAN2_TX_IRQHandler PUBWEAK CAN2_RX0_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN2_RX0_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_RX0_IRQHandler B CAN2_RX0_IRQHandler PUBWEAK CAN2_RX1_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN2_RX1_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_RX1_IRQHandler B CAN2_RX1_IRQHandler PUBWEAK CAN2_SCE_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN2_SCE_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_SCE_IRQHandler B CAN2_SCE_IRQHandler PUBWEAK OTG_FS_IRQHandler SECTION .text:CODE:NOROOT(2) -OTG_FS_IRQHandler +OTG_FS_IRQHandler B OTG_FS_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:NOROOT(2) -USART6_IRQHandler +USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT(2) -OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT(2) -OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT(2) -OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:NOROOT(2) -OTG_HS_IRQHandler +OTG_HS_IRQHandler B OTG_HS_IRQHandler PUBWEAK DCMI_IRQHandler SECTION .text:CODE:NOROOT(2) -DCMI_IRQHandler +DCMI_IRQHandler B DCMI_IRQHandler PUBWEAK CRYP_IRQHandler SECTION .text:CODE:NOROOT(2) -CRYP_IRQHandler +CRYP_IRQHandler B CRYP_IRQHandler PUBWEAK HASH_RNG_IRQHandler - SECTION .text:CODE:NOROOT(2) -HASH_RNG_IRQHandler + SECTION .text:CODE:NOROOT(2) +HASH_RNG_IRQHandler B HASH_RNG_IRQHandler END diff --git a/ports_module/cortex_m3/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_m3/iar/example_build/tx_initialize_low_level.s index 0491ca43..f3262e15 100644 --- a/ports_module/cortex_m3/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_m3/iar/example_build/tx_initialize_low_level.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -40,11 +40,11 @@ ; SYSTEM_CLOCK EQU 7200000 SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) - + RSEG FREE_MEM:DATA PUBLIC __tx_free_memory_start __tx_free_memory_start - DS32 4 + DS32 4 ; ; SECTION `.text`:CODE:NOROOT(2) @@ -83,12 +83,6 @@ __tx_free_memory_start ;/* */ ;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) ;{ @@ -101,7 +95,7 @@ _tx_initialize_low_level: ; ; ; /* Set base of available memory to end of non-initialised RAM area. */ -; +; LDR r0, =__tx_free_memory_start ; Get end of non-initialized RAM area LDR r2, =_tx_initialize_unused_memory ; Build address of unused memory pointer STR r0, [r2, #0] ; Save first free memory address @@ -111,13 +105,13 @@ _tx_initialize_low_level: LDR r0, =0xE0001000 ; Build address of DWT register LDR r1, [r0] ; Pickup the current value ORR r1, r1, #1 ; Set the CYCCNTENA bit - STR r1, [r0] ; Enable the cycle count register + STR r1, [r0] ; Enable the cycle count register ; ; /* Setup Vector Table Offset Register. */ -; +; MOV r0, #0xE000E000 ; Build address of NVIC registers LDR r1, =__vector_table ; Pickup address of vector table - STR r1, [r0, #0xD08] ; Set vector table address + STR r1, [r0, #0xD08] ; Set vector table address ; ; /* Set system stack pointer from vector value. */ ; @@ -148,8 +142,8 @@ _tx_initialize_low_level: ; Note: PnSV must be lowest priority, which is 0xFF ; ; /* Return to caller. */ -; - BX lr +; + BX lr ;} ; ; @@ -174,7 +168,7 @@ __tx_SysTickHandler: POP {r0, lr} BX LR ; } - - END - + + END + diff --git a/ports_module/cortex_m3/iar/inc/tx_port.h b/ports_module/cortex_m3/iar/inc/tx_port.h index b566bda3..eb5c4a30 100644 --- a/ports_module/cortex_m3/iar/inc/tx_port.h +++ b/ports_module/cortex_m3/iar/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,15 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -243,7 +235,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -376,7 +368,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -535,7 +527,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #else #error "Compiler not supported." #endif @@ -719,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M3 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M3 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m3/iar/inc/txm_module_port.h b/ports_module/cortex_m3/iar/inc/txm_module_port.h index 667330d7..a6a619a4 100644 --- a/ports_module/cortex_m3/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m3/iar/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,24 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* 07-29-2022 Scott Larson Enabled user-defined and */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Configure heap size, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Set default values for RBAR, */ -/* unify this file for all */ -/* compilers, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -463,6 +446,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M3 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M3 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m3/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m3/iar/module_lib/src/txm_module_thread_shell_entry.c index 31434744..d4fd04ec 100644 --- a/ports_module/cortex_m3/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m3/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID __iar_data_init3(VOID); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ __iar_data_init3(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_iar.c b/ports_module/cortex_m3/iar/module_manager/src/tx_iar.c index ee47f10f..238b485e 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_iar.c +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_iar.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_misra.s b/ports_module/cortex_m3/iar/module_manager/src/tx_misra.s index 72aac789..c79133f5 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_misra.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_misra.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -116,7 +117,7 @@ SECTION `.data`:DATA:REORDER:NOROOT(2) DATA -// 51 CHAR _tx_version_id[100] = "Copyright (c) 2024 Microsoft Corporation. * ThreadX 6.1 MISRA C Compliant *"; +// 51 CHAR _tx_version_id[100] = "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX 6.1 MISRA C Compliant *"; _tx_version_id: DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H @@ -703,7 +704,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -718,7 +719,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARMVFP__ /***********************************************************************************************/ @@ -735,8 +736,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -750,10 +751,10 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - - + + SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2) SECTION_TYPE SHT_PROGBITS, 0 DATA diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_restore.s index 35aeaf5b..96b7d2d7 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_save.s index f8bf5036..9d575f8f 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_control.s index a0f3a5d0..75952281 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_disable.s index 999af964..ce7ceb62 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_restore.s index 2e55ed27..3cc26d93 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_schedule.s index 21edb519..f97239f6 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,22 +64,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, optional */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_stack_build.s index 116ba71c..eb2c3ffb 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_system_return.s index a19bd35d..712a6e5c 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m3/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m3/iar/module_manager/src/tx_timer_interrupt.s index a2d8ca32..2801dd7d 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m3/iar/module_manager/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,18 +72,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_alignment_adjust.c index b7d5d1d0..91b9087d 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 32. */ if(size <= 32) return 32; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_external_memory_enable.c index 894098db..baa40100 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Update defines, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -114,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -124,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -224,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -234,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -246,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index 50305a72..ead02314 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index 60fd7c07..16ff0dcf 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c index 67422c03..987a6667 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -94,16 +95,6 @@ const ULONG txm_module_default_mpu_registers[32] = /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Changed from lookup table to */ -/* calculation and check for */ -/* minumum block size, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { diff --git a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_thread_stack_build.s index daaf5cf7..eea5683c 100644 --- a/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m3/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m33/ac6/example_build/ARMCM33_DSP_FP_TZ_config.txt b/ports_module/cortex_m33/ac6/example_build/ARMCM33_DSP_FP_TZ_config.txt index 04e32d1f..b65ba4c8 100644 --- a/ports_module/cortex_m33/ac6/example_build/ARMCM33_DSP_FP_TZ_config.txt +++ b/ports_module/cortex_m33/ac6/example_build/ARMCM33_DSP_FP_TZ_config.txt @@ -14,7 +14,7 @@ cpu0.INITNSVTOR=0x0 # (int , init-time) defa cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set -idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write diff --git a/ports_module/cortex_m33/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h b/ports_module/cortex_m33/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h index 1eb74752..262dc09b 100644 --- a/ports_module/cortex_m33/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h +++ b/ports_module/cortex_m33/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'ThreadX_Library' - * Target: 'ThreadX_Library_Project' + * Project: 'ThreadX_Library' + * Target: 'ThreadX_Library_Project' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h" diff --git a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c index 36cb0c63..6edd89de 100644 --- a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c +++ b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c @@ -96,7 +96,7 @@ void SystemInit (void) #endif SystemCoreClock = SYSTEM_CLOCK; - + *(uint32_t *)0xE000ED24 = 0x000F0000; /* S: enable secure, usage, bus, mem faults */ *(uint32_t *)0xE002ED24 = 0x000F0000; /* NS: enable secure, usage, bus, mem faults */ } diff --git a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h index 65bfdcd7..ebbc79c0 100644 --- a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h +++ b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'demo_secure_zone' - * Target: 'FVP Simulation Model' + * Project: 'demo_secure_zone' + * Target: 'FVP Simulation Model' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h" diff --git a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/interface.c b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/interface.c index 4e6e8eee..af6533c3 100644 --- a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/interface.c +++ b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/interface.c @@ -31,19 +31,19 @@ typedef funcptr funcptr_NS __attribute__((cmse_nonsecure_call)); /* Non-secure callable (entry) function */ -int func1(int x) __attribute__((cmse_nonsecure_entry)) { - return x+3; +int func1(int x) __attribute__((cmse_nonsecure_entry)) { + return x+3; } /* Non-secure callable (entry) function, calling a non-secure callback function */ int func2(funcptr callback, int x) __attribute__((cmse_nonsecure_entry)) { funcptr_NS callback_NS; // non-secure callback function pointer int y; - + /* return function pointer with cleared LSB */ callback_NS = (funcptr_NS)cmse_nsfptr_create(callback); - + y = callback_NS (x+1); - + return (y+2); } diff --git a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/main_ns.c b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/main_ns.c index a65b6880..04d857ff 100644 --- a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/main_ns.c +++ b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/main_ns.c @@ -63,7 +63,7 @@ void ThreadA (void *argument) { static int callbackB (int val) { uint32_t flags; - + flags = osThreadFlagsWait (1U, osFlagsWaitAny, osWaitForever); if (flags == 1U) { return (val+1); diff --git a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/main_s.c b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/main_s.c index 548b383a..6e48de6e 100644 --- a/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/main_s.c +++ b/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/main_s.c @@ -24,36 +24,36 @@ * Title: Code template for secure main function * *---------------------------------------------------------------------------*/ - + /* Use CMSE intrinsics */ #include #include #include "RTE_Components.h" #include CMSIS_device_header - + /* TZ_START_NS: Start address of non-secure application */ #ifndef TZ_START_NS #define TZ_START_NS (0x100000U) #endif - + /* typedef for non-secure callback functions */ typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call)); - + /* Secure main() */ int main(void) { funcptr_void NonSecure_ResetHandler; - + /* Add user setup code for secure part here*/ - + /* Set non-secure main stack (MSP_NS) */ __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS))); - + /* Get non-secure reset handler */ NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U))); - + /* Start non-secure state software application */ NonSecure_ResetHandler(); - + /* Non-secure software does not return, this code is not executed */ while (1) { __NOP(); diff --git a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c index e4871014..d0f6b08b 100644 --- a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c +++ b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c @@ -24,17 +24,17 @@ * * ----------------------------------------------------------------------------- */ - + #include "cmsis_compiler.h" #include "rtx_os.h" - + // OS Idle Thread __WEAK __NO_RETURN void osRtxIdleThread (void *argument) { (void)argument; for (;;) {} } - + // OS Error Callback function __WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { (void)object_id; diff --git a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h index 3021efbc..49fc392e 100644 --- a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h +++ b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h @@ -24,52 +24,52 @@ * * ----------------------------------------------------------------------------- */ - + #ifndef RTX_CONFIG_H_ #define RTX_CONFIG_H_ - + #ifdef _RTE_ #include "RTE_Components.h" #ifdef RTE_RTX_CONFIG_H #include RTE_RTX_CONFIG_H #endif #endif - + //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - + // System Configuration // ======================= - + // Global Dynamic Memory size [bytes] <0-1073741824:8> // Defines the combined global dynamic memory size. // Default: 4096 #ifndef OS_DYNAMIC_MEM_SIZE #define OS_DYNAMIC_MEM_SIZE 4096 #endif - + // Kernel Tick Frequency [Hz] <1-1000000> // Defines base time unit for delays and timeouts. // Default: 1000 (1ms tick) #ifndef OS_TICK_FREQ #define OS_TICK_FREQ 1000 #endif - + // Round-Robin Thread switching // Enables Round-Robin Thread switching. #ifndef OS_ROBIN_ENABLE #define OS_ROBIN_ENABLE 1 #endif - + // Round-Robin Timeout <1-1000> // Defines how many ticks a thread will execute before a thread switch. // Default: 5 #ifndef OS_ROBIN_TIMEOUT #define OS_ROBIN_TIMEOUT 5 #endif - + // - -// ISR FIFO Queue + +// ISR FIFO Queue // <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries // <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries // <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries @@ -78,38 +78,38 @@ #ifndef OS_ISR_FIFO_QUEUE #define OS_ISR_FIFO_QUEUE 16 #endif - + // Object Memory usage counters // Enables object memory usage counters (requires RTX source variant). #ifndef OS_OBJ_MEM_USAGE #define OS_OBJ_MEM_USAGE 0 #endif - + // - + // Thread Configuration // ======================= - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_THREAD_OBJ_MEM #define OS_THREAD_OBJ_MEM 0 #endif - + // Number of user Threads <1-1000> // Defines maximum number of user threads that can be active at the same time. // Applies to user threads with system provided memory for control blocks. #ifndef OS_THREAD_NUM #define OS_THREAD_NUM 1 #endif - + // Number of user Threads with default Stack size <0-1000> // Defines maximum number of user threads with default stack size. // Applies to user threads with zero stack size specified. #ifndef OS_THREAD_DEF_STACK_NUM #define OS_THREAD_DEF_STACK_NUM 0 #endif - + // Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> // Defines the combined stack size for user threads with user-provided stack size. // Applies to user threads with user-provided stack size and system provided memory for stack. @@ -117,23 +117,23 @@ #ifndef OS_THREAD_USER_STACK_SIZE #define OS_THREAD_USER_STACK_SIZE 0 #endif - + // - + // Default Thread Stack size [bytes] <96-1073741824:8> // Defines stack size for threads with zero stack size specified. // Default: 256 #ifndef OS_STACK_SIZE #define OS_STACK_SIZE 256 #endif - + // Idle Thread Stack size [bytes] <72-1073741824:8> // Defines stack size for Idle thread. // Default: 256 #ifndef OS_IDLE_THREAD_STACK_SIZE #define OS_IDLE_THREAD_STACK_SIZE 256 #endif - + // Idle Thread TrustZone Module Identifier // Defines TrustZone Thread Context Management Identifier. // Applies only to cores with TrustZone technology. @@ -141,49 +141,49 @@ #ifndef OS_IDLE_THREAD_TZ_MOD_ID #define OS_IDLE_THREAD_TZ_MOD_ID 0 #endif - + // Stack overrun checking // Enables stack overrun check at thread switch. // Enabling this option increases slightly the execution time of a thread switch. #ifndef OS_STACK_CHECK #define OS_STACK_CHECK 1 #endif - + // Stack usage watermark // Initializes thread stack with watermark pattern for analyzing stack usage. // Enabling this option increases significantly the execution time of thread creation. #ifndef OS_STACK_WATERMARK #define OS_STACK_WATERMARK 0 #endif - -// Processor mode for Thread execution -// <0=> Unprivileged mode + +// Processor mode for Thread execution +// <0=> Unprivileged mode // <1=> Privileged mode // Default: Privileged mode #ifndef OS_PRIVILEGE_MODE #define OS_PRIVILEGE_MODE 1 #endif - + // - + // Timer Configuration // ====================== - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_TIMER_OBJ_MEM #define OS_TIMER_OBJ_MEM 0 #endif - + // Number of Timer objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_TIMER_NUM #define OS_TIMER_NUM 1 #endif - + // - + // Timer Thread Priority // <8=> Low // <16=> Below Normal <24=> Normal <32=> Above Normal @@ -194,7 +194,7 @@ #ifndef OS_TIMER_THREAD_PRIO #define OS_TIMER_THREAD_PRIO 40 #endif - + // Timer Thread Stack size [bytes] <0-1073741824:8> // Defines stack size for Timer thread. // May be set to 0 when timers are not used. @@ -202,7 +202,7 @@ #ifndef OS_TIMER_THREAD_STACK_SIZE #define OS_TIMER_THREAD_STACK_SIZE 256 #endif - + // Timer Thread TrustZone Module Identifier // Defines TrustZone Thread Context Management Identifier. // Applies only to cores with TrustZone technology. @@ -210,7 +210,7 @@ #ifndef OS_TIMER_THREAD_TZ_MOD_ID #define OS_TIMER_THREAD_TZ_MOD_ID 0 #endif - + // Timer Callback Queue entries <0-256> // Number of concurrent active timer callback functions. // May be set to 0 when timers are not used. @@ -218,85 +218,85 @@ #ifndef OS_TIMER_CB_QUEUE #define OS_TIMER_CB_QUEUE 4 #endif - + // - + // Event Flags Configuration // ============================ - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_EVFLAGS_OBJ_MEM #define OS_EVFLAGS_OBJ_MEM 0 #endif - + // Number of Event Flags objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_EVFLAGS_NUM #define OS_EVFLAGS_NUM 1 #endif - + // - + // - + // Mutex Configuration // ====================== - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_MUTEX_OBJ_MEM #define OS_MUTEX_OBJ_MEM 0 #endif - + // Number of Mutex objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_MUTEX_NUM #define OS_MUTEX_NUM 1 #endif - + // - + // - + // Semaphore Configuration // ========================== - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_SEMAPHORE_OBJ_MEM #define OS_SEMAPHORE_OBJ_MEM 0 #endif - + // Number of Semaphore objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_SEMAPHORE_NUM #define OS_SEMAPHORE_NUM 1 #endif - + // - + // - + // Memory Pool Configuration // ============================ - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_MEMPOOL_OBJ_MEM #define OS_MEMPOOL_OBJ_MEM 0 #endif - + // Number of Memory Pool objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_MEMPOOL_NUM #define OS_MEMPOOL_NUM 1 #endif - + // Data Storage Memory size [bytes] <0-1073741824:8> // Defines the combined data storage memory size. // Applies to objects with system provided memory for data storage. @@ -304,27 +304,27 @@ #ifndef OS_MEMPOOL_DATA_SIZE #define OS_MEMPOOL_DATA_SIZE 0 #endif - + // - + // - + // Message Queue Configuration // ============================== - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_MSGQUEUE_OBJ_MEM #define OS_MSGQUEUE_OBJ_MEM 0 #endif - + // Number of Message Queue objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_MSGQUEUE_NUM #define OS_MSGQUEUE_NUM 1 #endif - + // Data Storage Memory size [bytes] <0-1073741824:8> // Defines the combined data storage memory size. // Applies to objects with system provided memory for data storage. @@ -332,26 +332,26 @@ #ifndef OS_MSGQUEUE_DATA_SIZE #define OS_MSGQUEUE_DATA_SIZE 0 #endif - + // - + // - + // Event Recorder Configuration // =============================== - + // Global Initialization // Initialize Event Recorder during 'osKernelInitialize'. #ifndef OS_EVR_INIT #define OS_EVR_INIT 0 #endif - + // Start recording // Start event recording after initialization. #ifndef OS_EVR_START #define OS_EVR_START 1 #endif - + // Global Event Filter Setup // Initial recording level applied to all components. // Error events @@ -362,11 +362,11 @@ #ifndef OS_EVR_LEVEL #define OS_EVR_LEVEL 0x00U #endif - + // RTOS Event Filter Setup // Recording levels for RTX components. // Only applicable if events for the respective component are generated. - + // Memory Management // Recording level for Memory Management events. // Error events @@ -374,10 +374,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_MEMORY_LEVEL +#ifndef OS_EVR_MEMORY_LEVEL #define OS_EVR_MEMORY_LEVEL 0x01U #endif - + // Kernel // Recording level for Kernel events. // Error events @@ -385,10 +385,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_KERNEL_LEVEL +#ifndef OS_EVR_KERNEL_LEVEL #define OS_EVR_KERNEL_LEVEL 0x01U #endif - + // Thread // Recording level for Thread events. // Error events @@ -396,10 +396,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_THREAD_LEVEL +#ifndef OS_EVR_THREAD_LEVEL #define OS_EVR_THREAD_LEVEL 0x05U #endif - + // Generic Wait // Recording level for Generic Wait events. // Error events @@ -407,10 +407,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_WAIT_LEVEL +#ifndef OS_EVR_WAIT_LEVEL #define OS_EVR_WAIT_LEVEL 0x01U #endif - + // Thread Flags // Recording level for Thread Flags events. // Error events @@ -418,10 +418,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_THFLAGS_LEVEL +#ifndef OS_EVR_THFLAGS_LEVEL #define OS_EVR_THFLAGS_LEVEL 0x01U #endif - + // Event Flags // Recording level for Event Flags events. // Error events @@ -429,10 +429,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_EVFLAGS_LEVEL +#ifndef OS_EVR_EVFLAGS_LEVEL #define OS_EVR_EVFLAGS_LEVEL 0x01U #endif - + // Timer // Recording level for Timer events. // Error events @@ -440,10 +440,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_TIMER_LEVEL +#ifndef OS_EVR_TIMER_LEVEL #define OS_EVR_TIMER_LEVEL 0x01U #endif - + // Mutex // Recording level for Mutex events. // Error events @@ -451,10 +451,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_MUTEX_LEVEL +#ifndef OS_EVR_MUTEX_LEVEL #define OS_EVR_MUTEX_LEVEL 0x01U #endif - + // Semaphore // Recording level for Semaphore events. // Error events @@ -462,10 +462,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_SEMAPHORE_LEVEL +#ifndef OS_EVR_SEMAPHORE_LEVEL #define OS_EVR_SEMAPHORE_LEVEL 0x01U #endif - + // Memory Pool // Recording level for Memory Pool events. // Error events @@ -473,10 +473,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_MEMPOOL_LEVEL +#ifndef OS_EVR_MEMPOOL_LEVEL #define OS_EVR_MEMPOOL_LEVEL 0x01U #endif - + // Message Queue // Recording level for Message Queue events. // Error events @@ -484,87 +484,87 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_MSGQUEUE_LEVEL +#ifndef OS_EVR_MSGQUEUE_LEVEL #define OS_EVR_MSGQUEUE_LEVEL 0x01U #endif - + // - + // - + // RTOS Event Generation // Enables event generation for RTX components (requires RTX source variant). - + // Memory Management // Enables Memory Management event generation. #ifndef OS_EVR_MEMORY #define OS_EVR_MEMORY 1 #endif - + // Kernel // Enables Kernel event generation. #ifndef OS_EVR_KERNEL #define OS_EVR_KERNEL 1 #endif - + // Thread // Enables Thread event generation. #ifndef OS_EVR_THREAD #define OS_EVR_THREAD 1 #endif - + // Generic Wait // Enables Generic Wait event generation. #ifndef OS_EVR_WAIT #define OS_EVR_WAIT 1 #endif - + // Thread Flags // Enables Thread Flags event generation. #ifndef OS_EVR_THFLAGS #define OS_EVR_THFLAGS 1 #endif - + // Event Flags // Enables Event Flags event generation. #ifndef OS_EVR_EVFLAGS #define OS_EVR_EVFLAGS 1 #endif - + // Timer // Enables Timer event generation. #ifndef OS_EVR_TIMER #define OS_EVR_TIMER 1 #endif - + // Mutex // Enables Mutex event generation. #ifndef OS_EVR_MUTEX #define OS_EVR_MUTEX 1 #endif - + // Semaphore // Enables Semaphore event generation. #ifndef OS_EVR_SEMAPHORE #define OS_EVR_SEMAPHORE 1 #endif - + // Memory Pool // Enables Memory Pool event generation. #ifndef OS_EVR_MEMPOOL #define OS_EVR_MEMPOOL 1 #endif - + // Message Queue // Enables Message Queue event generation. #ifndef OS_EVR_MSGQUEUE #define OS_EVR_MSGQUEUE 1 #endif - + // - + // - + // Number of Threads which use standard C/C++ library libspace // (when thread specific memory allocation is not used). #if (OS_THREAD_OBJ_MEM == 0) @@ -572,7 +572,7 @@ #else #define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM #endif - + //------------- <<< end of configuration section >>> --------------------------- - + #endif // RTX_CONFIG_H_ diff --git a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h index 78d1b429..62e042d2 100644 --- a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h +++ b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'demo_threadx_non-secure_zone' - * Target: 'FVP Simulation Model' + * Project: 'demo_threadx_non-secure_zone' + * Target: 'FVP Simulation Model' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h" diff --git a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h index 1eb74752..262dc09b 100644 --- a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h +++ b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'ThreadX_Library' - * Target: 'ThreadX_Library_Project' + * Project: 'ThreadX_Library' + * Target: 'ThreadX_Library_Project' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h" diff --git a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c index 93dd8379..756e7032 100644 --- a/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c +++ b/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c @@ -71,8 +71,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -86,9 +86,9 @@ void module_manager_entry(ULONG thread_input) { (void)thread_input; - + tx_thread_secure_stack_allocate(&module_manager, 256); - + /* Initialize the module manager. */ txm_module_manager_initialize((void *) module_data_area, MODULE_DATA_SIZE); @@ -96,22 +96,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); - + /* Enable a read/write shared memory region. */ txm_module_manager_external_memory_enable(&my_module, (void *) shared_memory, SHARED_MEMORY_SIZE, TXM_MODULE_ATTRIBUTE_READ_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -120,11 +120,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/RTE/_FVP_Simulation_Model/RTE_Components.h index c930572b..114b543a 100644 --- a/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/RTE/_FVP_Simulation_Model/RTE_Components.h +++ b/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'sample_threadx_module' - * Target: 'FVP Simulation Model' + * Project: 'sample_threadx_module' + * Target: 'FVP Simulation Model' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h" diff --git a/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/sample_threadx_module.c index e32c4ec6..9a6313ca 100644 --- a/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -28,7 +28,7 @@ #define EXTERNAL_MEMORY (0x00200100) -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -109,7 +109,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -125,7 +125,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -137,42 +137,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -180,23 +180,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -240,21 +240,21 @@ void thread_0_entry(ULONG thread_input) { UINT status; - + tx_thread_secure_stack_allocate(thread_0, 256); thread_0_counter = func1(thread_0_counter); tx_thread_secure_stack_free(thread_0); - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { /* Increment the thread counter. */ thread_0_counter++; - + /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -302,18 +302,18 @@ UINT status; { /* Test external memory sharing. */ // *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -372,7 +372,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -425,7 +425,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/txm_module_preamble.S index f6530c9f..302efdf2 100644 --- a/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_m33/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -2,7 +2,7 @@ .align 4 .syntax unified .section RESET - + // Define public symbols .global __txm_module_preamble diff --git a/ports_module/cortex_m33/ac6/example_build/tx_initialize_low_level.S b/ports_module/cortex_m33/ac6/example_build/tx_initialize_low_level.S index 3d9b5a60..9e6fa804 100644 --- a/ports_module/cortex_m33/ac6/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m33/ac6/example_build/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,12 +63,6 @@ HEAP_SIZE = 0x00000000 /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_m33/ac6/example_build/txm/RTE/_ThreadX_Module_Library/RTE_Components.h b/ports_module/cortex_m33/ac6/example_build/txm/RTE/_ThreadX_Module_Library/RTE_Components.h index 014a2a2b..51ad5ce8 100644 --- a/ports_module/cortex_m33/ac6/example_build/txm/RTE/_ThreadX_Module_Library/RTE_Components.h +++ b/ports_module/cortex_m33/ac6/example_build/txm/RTE/_ThreadX_Module_Library/RTE_Components.h @@ -3,8 +3,8 @@ * Auto generated Run-Time-Environment Configuration File * *** Do not modify ! *** * - * Project: 'txm' - * Target: 'ThreadX Module Library' + * Project: 'txm' + * Target: 'ThreadX Module Library' */ #ifndef RTE_COMPONENTS_H @@ -12,7 +12,7 @@ /* - * Define the Device Header File: + * Define the Device Header File: */ #define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h" diff --git a/ports_module/cortex_m33/ac6/inc/tx_port.h b/ports_module/cortex_m33/ac6/inc/tx_port.h index 7358ef1b..9adb6f01 100644 --- a/ports_module/cortex_m33/ac6/inc/tx_port.h +++ b/ports_module/cortex_m33/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,37 +46,6 @@ /* This file replaces the previous Cortex-M33 files. It unifies */ /* the Cortex-M33 compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-02-2021 Scott Larson Modified comment(s), added */ -/* ULONG64_DEFINED, */ -/* resulting in version 6.1.5 */ -/* 06-02-2021 Scott Larson Modified comment(s), removed */ -/* unneeded header file, funcs */ -/* set_control and get_control */ -/* changed to inline, */ -/* added symbol to enable */ -/* stack error handler, */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ -/* stack check error handling, */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), unified */ -/* this file across compilers, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -705,7 +675,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M33 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M33 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m33/ac6/inc/tx_secure_interface.h b/ports_module/cortex_m33/ac6/inc/tx_secure_interface.h index 39b5d5fd..5ac37fbf 100644 --- a/ports_module/cortex_m33/ac6/inc/tx_secure_interface.h +++ b/ports_module/cortex_m33/ac6/inc/tx_secure_interface.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,12 +38,6 @@ /* It is assumed that tx_api.h and tx_port.h have already been */ /* included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_SECURE_INTERFACE_H diff --git a/ports_module/cortex_m33/ac6/inc/txm_module_port.h b/ports_module/cortex_m33/ac6/inc/txm_module_port.h index 40877124..6d9d326f 100644 --- a/ports_module/cortex_m33/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m33/ac6/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,15 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -356,6 +348,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M33/AC6 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M33/AC6 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m33/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_m33/ac6/module_lib/src/txm_module_initialize.S index c596ac24..fd332fe2 100644 --- a/ports_module/cortex_m33/ac6/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_m33/ac6/module_lib/src/txm_module_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,16 +58,6 @@ /* */ /* _txm_module_thread_shell_entry Start module thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* 01-31-2022 Scott Larson Modified comments, fixed */ -/* scatterload, and made */ -/* heap user configurable, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _txm_module_initialize .thumb_func diff --git a/ports_module/cortex_m33/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m33/ac6/module_lib/src/txm_module_thread_shell_entry.c index db345a0f..bf6fcb5f 100644 --- a/ports_module/cortex_m33/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m33/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -89,16 +90,6 @@ extern VOID _txm_module_initialize(VOID *heap_base, VOID *heap_top); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* 01-31-2022 Scott Larson Modified comments, fixed */ -/* scatterload, and made */ -/* heap user configurable, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -113,14 +104,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _txm_module_initialize(&txm_heap[0], &txm_heap[TXM_MODULE_HEAP_SIZE-1]); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -128,7 +119,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m33/ac6/module_lib/src/txm_thread_secure_stack_allocate.c b/ports_module/cortex_m33/ac6/module_lib/src/txm_thread_secure_stack_allocate.c index a8ce5c8c..51277114 100644 --- a/ports_module/cortex_m33/ac6/module_lib/src/txm_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m33/ac6/module_lib/src/txm_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { diff --git a/ports_module/cortex_m33/ac6/module_lib/src/txm_thread_secure_stack_free.c b/ports_module/cortex_m33/ac6/module_lib/src/txm_thread_secure_stack_free.c index 15d58661..9752991f 100644 --- a/ports_module/cortex_m33/ac6/module_lib/src/txm_thread_secure_stack_free.c +++ b/ports_module/cortex_m33/ac6/module_lib/src/txm_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { diff --git a/ports_module/cortex_m33/ac6/module_manager/inc/txm_module_manager_dispatch_port.h b/ports_module/cortex_m33/ac6/module_manager/inc/txm_module_manager_dispatch_port.h index 8bbcd5b3..0575c748 100644 --- a/ports_module/cortex_m33/ac6/module_manager/inc/txm_module_manager_dispatch_port.h +++ b/ports_module/cortex_m33/ac6/module_manager/inc/txm_module_manager_dispatch_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_restore.S index f1733eff..1938ecd0 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_save.S index 63ccc8fc..6f32dfb0 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_control.S index b354238d..e51c087d 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,12 +52,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_disable.S index b5110d71..1a3e4116 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,12 +52,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_restore.S index 41e6de04..c80e98a1 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,12 +52,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S index 1a3a94e6..707ad4de 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,28 +58,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* 04-02-2021 Scott Larson Modified comments and fixed */ -/* MPU region configuration, */ -/* resulting in version 6.1.6 */ -/* 06-02-2021 Scott Larson Fixed extended stack handling */ -/* when calling kernel APIs, */ -/* resulting in version 6.1.7 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Added preproc FPU option, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -542,7 +521,7 @@ SVC_Handler: ORREQ lr, lr, #0x10 // Set bit, return with standard frame STR r3, [r2, #0xB0] // Save thread stack pointer BIC r3, #1 // Clear possibly OR'd bit - + /* Build kernel stack by copying thread stack two registers at a time */ ADD r3, r3, #32 // Start at bottom of hardware stack LDMDB r3!, {r1-r2} @@ -648,20 +627,20 @@ _tx_svc_secure_alloc: CMP r1, r2 // Did we come from _tx_thread_secure_stack_allocate? IT NE // If no (not equal), then... BXNE lr // return from where we came. - + PUSH {r0, lr} // Save SP and EXC_RETURN LDM r0, {r0-r3} // Load function parameters from stack BL _tx_thread_secure_mode_stack_allocate POP {r12, lr} // Restore SP and EXC_RETURN STR r0, [r12] // Store function return value BX lr - + _tx_svc_secure_free: LDR r2, =_tx_free_return // Load address of where we should have come from CMP r1, r2 // Did we come from _tx_thread_secure_stack_free? IT NE // If no (not equal), then... BXNE lr // return from where we came. - + PUSH {r0, lr} // Save SP and EXC_RETURN LDM r0, {r0-r3} // Load function parameters from stack BL _tx_thread_secure_mode_stack_free diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack.c index 3f585b78..50b85fa1 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -102,21 +103,6 @@ static INT tx_head_free_index = 0U; /* */ /* _tx_initialize_kernel_enter */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-16-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.1 */ -/* 06-02-2021 Scott Larson Modified comment(s), and */ -/* changed name, execute in */ -/* handler mode, */ -/* resulting in version 6.1.7 */ -/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ -/* secure stack allocation, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_initialize(void) diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_allocate.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_allocate.S index 893135f0..a5fc5eb9 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_allocate.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_allocate.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) // { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_free.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_free.S index 3b82681b..83f231a1 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_free.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_free.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,12 +51,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) // { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_initialize.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_initialize.S index 74ac2a29..6ca3be40 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_initialize.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_secure_stack_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,16 +51,6 @@ /* */ /* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) // { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_build.S index a403bb30..17eae110 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_system_return.S index a4f207a6..68865568 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,12 +54,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_timer_interrupt.S index c9c89ad0..06b149ce 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_allocate.c b/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_allocate.c index d6f061c2..344e5fd9 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { @@ -76,10 +71,10 @@ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_siz return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_free.c b/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_free.c index aa452180..76832975 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_free.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/txe_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { @@ -74,10 +69,10 @@ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_alignment_adjust.c index 83487f01..76c52f02 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, @@ -77,7 +72,7 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, /* Round code and data size UP to TXM_MODULE_MPU_ALIGNMENT bytes. */ *code_size = (*code_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); *data_size = (*data_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); - + /* Alignment for code and data is TXM_MODULE_MPU_ALIGNMENT bytes. */ *code_alignment = TXM_MODULE_MPU_ALIGNMENT; *data_alignment = TXM_MODULE_MPU_ALIGNMENT; diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_external_memory_enable.c index becd1da9..6e78d96d 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -105,7 +100,7 @@ ULONG shared_index; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -115,49 +110,49 @@ ULONG shared_index; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address must adhere to Cortex-M33 MPU alignment. */ address = (ULONG) start_address; if(address != (address & ~(TXM_MODULE_MPU_ALIGNMENT - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Set base address register with start address, sanitized attributes and execute never. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_base_address = address | (attributes & TXM_MODULE_ATTRIBUTE_MASK) | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; - + /* Set the limit address (data start + length-1), attribute index, and enable bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_limit_address = (address + length-1) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c index d7dd22de..8048fa57 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c index 8c42b43f..12976ffe 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index 53ae5fcf..b7dba686 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* _txm_module_manager_thread_create */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* 04-02-2021 Scott Larson Modified comments and check */ -/* for overflow, */ -/* resulting 6.1.6 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) { @@ -94,27 +86,27 @@ ULONG callback_stack_size; /* Set base address register to module data address, which should be at least 32-byte aligned. Mask address to proper range, inner shareable, read write, execute never. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_base_address = ((ULONG) module_instance -> txm_module_instance_data_start & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE | TXM_MODULE_ATTRIBUTE_READ_WRITE | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Set the limit address (data start + data size-1), attribute index, and enable bit. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_limit_address = (((ULONG) module_instance -> txm_module_instance_data_start + data_size - 1) & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; /* End of module data protection. */ - + /* Remaining MPU entries are disabled for now and can be used for shared memory. */ } @@ -173,7 +165,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_port_dispatch.c index 0c57bc42..6f0f16e3 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_port_dispatch.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_port_dispatch.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* _txm_module_manager_kernel_dispatch */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ -/* */ /**************************************************************************/ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) { @@ -88,7 +83,7 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; ); break; } - + case TXM_THREAD_SECURE_STACK_FREE_CALL: { if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) @@ -102,13 +97,13 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; ); break; } - + default: { /* Unhandled kernel request, return an error! */ break; } } - + return(return_value); } diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index 8c1fbc5f..95336ff5 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m33/gnu/example_build/gcc_setup.s b/ports_module/cortex_m33/gnu/example_build/gcc_setup.s index d7c61892..4a729ffe 100644 --- a/ports_module/cortex_m33/gnu/example_build/gcc_setup.s +++ b/ports_module/cortex_m33/gnu/example_build/gcc_setup.s @@ -14,7 +14,7 @@ _gcc_setup: mov r5,r0 /* Copy GOT table. */ - + ldr r0, =__got_load_start__ sub r0,r0,r3 add r0,r0,r5 @@ -42,13 +42,13 @@ flash_area: address_built: str r6, [r1] // Store in new GOT table add r0, r0, #4 // Move to next entry - add r1, r1, #4 // + add r1, r1, #4 // b new_got_setup // Continue at the top of the loop got_setup_done: /* Copy initialised sections into RAM if required. */ - + ldr r0, =__data_load_start__ sub r0,r0,r3 add r0,r0,r5 @@ -59,9 +59,9 @@ got_setup_done: sub r2,r2,r4 add r2,r2,r9 bl crt0_memory_copy - + /* Zero bss. */ - + ldr r0, =__bss_start__ sub r0,r0,r4 add r0,r0,r9 @@ -85,10 +85,10 @@ got_setup_done: str r2, [r0] add r0, r0, #4 str r1, [r0] - + LDMIA sp!, {r3, r4, r5, r6, r7, lr} // Store other preserved registers bx lr // Return to caller - + .align 4 /* Startup helper functions. */ @@ -124,4 +124,3 @@ memory_set_done: /* Setup attibutes of heap section so it doesn't take up room in the elf file */ .section .heap, "wa", %nobits - \ No newline at end of file diff --git a/ports_module/cortex_m33/gnu/example_build/sample_threadx_module.c b/ports_module/cortex_m33/gnu/example_build/sample_threadx_module.c index 52557312..b74d7a35 100644 --- a/ports_module/cortex_m33/gnu/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m33/gnu/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -101,7 +101,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -117,7 +117,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -129,42 +129,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -172,23 +172,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -233,7 +233,7 @@ void thread_0_entry(ULONG thread_input) UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -243,7 +243,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -291,19 +291,19 @@ UINT status; { /* Test memory handler. */ *(ULONG *)0x20010000 = 0xCDCDCDCD; - - + + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -362,7 +362,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -415,7 +415,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m33/gnu/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m33/gnu/example_build/sample_threadx_module_manager.c index 19add3d8..de0910d5 100644 --- a/ports_module/cortex_m33/gnu/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m33/gnu/example_build/sample_threadx_module_manager.c @@ -54,8 +54,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -75,22 +75,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_memory_load(&my_module, "my module", (VOID *) 0x00030000); - + /* Enable 128 byte read/write shared memory region at 0x20010000. */ txm_module_manager_external_memory_enable(&my_module, (void *) 0x20010000, 128, TXM_MODULE_ATTRIBUTE_READ_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -99,11 +99,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m33/gnu/example_build/txm_module_preamble.S b/ports_module/cortex_m33/gnu/example_build/txm_module_preamble.S index ded31277..5f663569 100644 --- a/ports_module/cortex_m33/gnu/example_build/txm_module_preamble.S +++ b/ports_module/cortex_m33/gnu/example_build/txm_module_preamble.S @@ -33,7 +33,7 @@ __txm_module_preamble: // 1 -> User mode execution .dc.l _txm_module_thread_shell_entry - . - 0 // Module Shell Entry Point .dc.l demo_module_start - . - 0 // Module Start Thread Entry Point - .dc.l 0 // Module Stop Thread Entry Point + .dc.l 0 // Module Stop Thread Entry Point .dc.l 1 // Module Start/Stop Thread Priority .dc.l 1024 // Module Start/Stop Thread Stack Size .dc.l _txm_module_callback_request_thread_entry - . - 0 // Module Callback Thread Entry diff --git a/ports_module/cortex_m33/gnu/inc/tx_port.h b/ports_module/cortex_m33/gnu/inc/tx_port.h index 7358ef1b..9adb6f01 100644 --- a/ports_module/cortex_m33/gnu/inc/tx_port.h +++ b/ports_module/cortex_m33/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,37 +46,6 @@ /* This file replaces the previous Cortex-M33 files. It unifies */ /* the Cortex-M33 compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-02-2021 Scott Larson Modified comment(s), added */ -/* ULONG64_DEFINED, */ -/* resulting in version 6.1.5 */ -/* 06-02-2021 Scott Larson Modified comment(s), removed */ -/* unneeded header file, funcs */ -/* set_control and get_control */ -/* changed to inline, */ -/* added symbol to enable */ -/* stack error handler, */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ -/* stack check error handling, */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), unified */ -/* this file across compilers, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -705,7 +675,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M33 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M33 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m33/gnu/inc/tx_secure_interface.h b/ports_module/cortex_m33/gnu/inc/tx_secure_interface.h index 39b5d5fd..5ac37fbf 100644 --- a/ports_module/cortex_m33/gnu/inc/tx_secure_interface.h +++ b/ports_module/cortex_m33/gnu/inc/tx_secure_interface.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,12 +38,6 @@ /* It is assumed that tx_api.h and tx_port.h have already been */ /* included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_SECURE_INTERFACE_H diff --git a/ports_module/cortex_m33/gnu/inc/txm_module_port.h b/ports_module/cortex_m33/gnu/inc/txm_module_port.h index 37a644d8..c48d5184 100644 --- a/ports_module/cortex_m33/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m33/gnu/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,14 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* 01-31-2022 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -350,6 +343,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M33/GNU Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M33/GNU Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m33/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m33/gnu/module_lib/src/txm_module_thread_shell_entry.c index 9d2e676b..0fa4f2de 100644 --- a/ports_module/cortex_m33/gnu/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m33/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the GNU C environment. */ _gcc_setup(thread_info -> txm_module_thread_entry_info_code_base_address); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m33/gnu/module_lib/src/txm_thread_secure_stack_allocate.c b/ports_module/cortex_m33/gnu/module_lib/src/txm_thread_secure_stack_allocate.c index 91d90f1f..dc8297c4 100644 --- a/ports_module/cortex_m33/gnu/module_lib/src/txm_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m33/gnu/module_lib/src/txm_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { diff --git a/ports_module/cortex_m33/gnu/module_lib/src/txm_thread_secure_stack_free.c b/ports_module/cortex_m33/gnu/module_lib/src/txm_thread_secure_stack_free.c index 56d9718b..17e7a4da 100644 --- a/ports_module/cortex_m33/gnu/module_lib/src/txm_thread_secure_stack_free.c +++ b/ports_module/cortex_m33/gnu/module_lib/src/txm_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { diff --git a/ports_module/cortex_m33/gnu/module_manager/inc/txm_module_manager_dispatch_port.h b/ports_module/cortex_m33/gnu/module_manager/inc/txm_module_manager_dispatch_port.h index 8bbcd5b3..0575c748 100644 --- a/ports_module/cortex_m33/gnu/module_manager/inc/txm_module_manager_dispatch_port.h +++ b/ports_module/cortex_m33/gnu/module_manager/inc/txm_module_manager_dispatch_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_initialize_low_level.S b/ports_module/cortex_m33/gnu/module_manager/src/tx_initialize_low_level.S index 49415774..c89394c2 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_initialize_low_level.S +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,14 +63,6 @@ HEAP_SIZE = 0x00000000 /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 01-31-2022 Scott Larson Fixed predefined macro name, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_restore.s index 6adf027c..9ac66244 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_save.s index 01a8f2b0..71d42cde 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_control.s index 082f1af0..b9083160 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,13 +51,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_disable.s index 779e5a76..c27e7362 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,13 +51,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_restore.s index dc3d6ad7..506ddf52 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,13 +51,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S index e392380b..16913f57 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,28 +57,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* 04-02-2021 Scott Larson Modified comments and fixed */ -/* MPU region configuration, */ -/* resulting in version 6.1.6 */ -/* 06-02-2021 Scott Larson Fixed extended stack handling */ -/* when calling kernel APIs, */ -/* resulting in version 6.1.7 */ -/* 01-31-2022 Scott Larson Fixed predefined macro name, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -541,7 +520,7 @@ SVC_Handler: ORREQ lr, lr, #0x10 // Set bit, return with standard frame STR r3, [r2, #0xB0] // Save thread stack pointer BIC r3, #1 // Clear possibly OR'd bit - + /* Build kernel stack by copying thread stack two registers at a time */ ADD r3, r3, #32 // Start at bottom of hardware stack LDMDB r3!, {r1-r2} @@ -647,20 +626,20 @@ _tx_svc_secure_alloc: CMP r1, r2 // Did we come from _tx_thread_secure_stack_allocate? IT NE // If no (not equal), then... BXNE lr // return from where we came. - + PUSH {r0, lr} // Save SP and EXC_RETURN LDM r0, {r0-r3} // Load function parameters from stack BL _tx_thread_secure_mode_stack_allocate POP {r12, lr} // Restore SP and EXC_RETURN STR r0, [r12] // Store function return value BX lr - + _tx_svc_secure_free: LDR r2, =_tx_free_return // Load address of where we should have come from CMP r1, r2 // Did we come from _tx_thread_secure_stack_free? IT NE // If no (not equal), then... BXNE lr // return from where we came. - + PUSH {r0, lr} // Save SP and EXC_RETURN LDM r0, {r0-r3} // Load function parameters from stack BL _tx_thread_secure_mode_stack_free diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack.c index ac0e90a1..82acdfbb 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -98,21 +99,6 @@ static INT tx_head_free_index = 0U; /* */ /* _tx_initialize_kernel_enter */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-16-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.1 */ -/* 06-02-2021 Scott Larson Change name, execute in */ -/* handler mode, */ -/* disable optimizations, */ -/* resulting in version 6.1.7 */ -/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ -/* secure stack allocation, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry, optimize(0))) UINT _tx_thread_secure_mode_stack_initialize(void) diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_allocate.S b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_allocate.S index 1509327e..3a59c6e3 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_allocate.S +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_allocate.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,12 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) // { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_free.S b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_free.S index 11b299f1..7e2e1ea5 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_free.S +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_free.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,12 +51,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) // { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_initialize.S b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_initialize.S index a78b1eec..92f92809 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_initialize.S +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_secure_stack_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,16 +51,6 @@ /* */ /* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) // { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_build.s index e7ef020c..370a18da 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,13 +53,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_system_return.s index 6bda9b54..95d8678f 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,13 +53,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m33/gnu/module_manager/src/tx_timer_interrupt.s index 2611dbf9..8acc0744 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txe_thread_secure_stack_allocate.c b/ports_module/cortex_m33/gnu/module_manager/src/txe_thread_secure_stack_allocate.c index d6f061c2..344e5fd9 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/txe_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/txe_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { @@ -76,10 +71,10 @@ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_siz return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txe_thread_secure_stack_free.c b/ports_module/cortex_m33/gnu/module_manager/src/txe_thread_secure_stack_free.c index aa452180..76832975 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/txe_thread_secure_stack_free.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/txe_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { @@ -74,10 +69,10 @@ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_alignment_adjust.c index 718fa052..76c52f02 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, @@ -77,7 +72,7 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, /* Round code and data size UP to TXM_MODULE_MPU_ALIGNMENT bytes. */ *code_size = (*code_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); *data_size = (*data_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); - + /* Alignment for code and data is TXM_MODULE_MPU_ALIGNMENT bytes. */ *code_alignment = TXM_MODULE_MPU_ALIGNMENT; *data_alignment = TXM_MODULE_MPU_ALIGNMENT; diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_external_memory_enable.c index 4a860702..6e78d96d 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -105,7 +100,7 @@ ULONG shared_index; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -115,49 +110,49 @@ ULONG shared_index; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address must adhere to Cortex-M33 MPU alignment. */ address = (ULONG) start_address; if(address != (address & ~(TXM_MODULE_MPU_ALIGNMENT - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Set base address register with start address, sanitized attributes and execute never. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_base_address = address | (attributes & TXM_MODULE_ATTRIBUTE_MASK) | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; - + /* Set the limit address (data start + length-1), attribute index, and enable bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_limit_address = (address + length-1) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c index 7bd60c88..8048fa57 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c index 9be0809a..12976ffe 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index 53ae5fcf..b7dba686 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* _txm_module_manager_thread_create */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* 04-02-2021 Scott Larson Modified comments and check */ -/* for overflow, */ -/* resulting 6.1.6 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) { @@ -94,27 +86,27 @@ ULONG callback_stack_size; /* Set base address register to module data address, which should be at least 32-byte aligned. Mask address to proper range, inner shareable, read write, execute never. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_base_address = ((ULONG) module_instance -> txm_module_instance_data_start & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE | TXM_MODULE_ATTRIBUTE_READ_WRITE | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Set the limit address (data start + data size-1), attribute index, and enable bit. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_limit_address = (((ULONG) module_instance -> txm_module_instance_data_start + data_size - 1) & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; /* End of module data protection. */ - + /* Remaining MPU entries are disabled for now and can be used for shared memory. */ } @@ -173,7 +165,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_port_dispatch.c index 1c774a1c..6f0f16e3 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_port_dispatch.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_port_dispatch.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* _txm_module_manager_kernel_dispatch */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* */ /**************************************************************************/ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) { @@ -88,7 +83,7 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; ); break; } - + case TXM_THREAD_SECURE_STACK_FREE_CALL: { if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) @@ -102,13 +97,13 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; ); break; } - + default: { /* Unhandled kernel request, return an error! */ break; } } - + return(return_value); } diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_thread_stack_build.s index eebe10ad..6c3e0275 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,13 +55,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m33/iar/example_build/sample_threadx_module.c b/ports_module/cortex_m33/iar/example_build/sample_threadx_module.c index 939433cd..e9605af8 100644 --- a/ports_module/cortex_m33/iar/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m33/iar/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -101,7 +101,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -117,7 +117,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -129,42 +129,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -172,23 +172,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -233,7 +233,7 @@ void thread_0_entry(ULONG thread_input) UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -243,7 +243,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -291,19 +291,19 @@ UINT status; { /* Test memory handler. */ *(ULONG *)0x64005000 = 0xCDCDCDCD; - - + + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -362,7 +362,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -415,7 +415,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m33/iar/example_build/sample_threadx_module.icf b/ports_module/cortex_m33/iar/example_build/sample_threadx_module.icf index 8cfe4766..167c26fb 100644 --- a/ports_module/cortex_m33/iar/example_build/sample_threadx_module.icf +++ b/ports_module/cortex_m33/iar/example_build/sample_threadx_module.icf @@ -35,11 +35,11 @@ do not initialize { section .noinit }; //place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -define movable block ROPI with alignment = 4, fixed order -{ +define movable block ROPI with alignment = 4, fixed order +{ ro object txm_module_preamble.o, - ro, - ro data + ro, + ro data }; define movable block RWPI with alignment = 8, fixed order, static base diff --git a/ports_module/cortex_m33/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m33/iar/example_build/sample_threadx_module_manager.c index 28299f6c..59aee1b9 100644 --- a/ports_module/cortex_m33/iar/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m33/iar/example_build/sample_threadx_module_manager.c @@ -53,8 +53,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -74,22 +74,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x080F0000); - + /* Enable 128 byte read/write shared memory region at 0x64005000. */ txm_module_manager_external_memory_enable(&my_module, (void *) 0x64005000, 128, TXM_MODULE_ATTRIBUTE_READ_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -98,7 +98,7 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { diff --git a/ports_module/cortex_m33/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_m33/iar/example_build/tx_initialize_low_level.s index dbf96b9a..43467f18 100644 --- a/ports_module/cortex_m33/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_m33/iar/example_build/tx_initialize_low_level.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,13 +71,6 @@ __tx_free_memory_start /* CALLED BY */ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_m33/iar/inc/tx_port.h b/ports_module/cortex_m33/iar/inc/tx_port.h index 7358ef1b..9adb6f01 100644 --- a/ports_module/cortex_m33/iar/inc/tx_port.h +++ b/ports_module/cortex_m33/iar/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,37 +46,6 @@ /* This file replaces the previous Cortex-M33 files. It unifies */ /* the Cortex-M33 compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-02-2021 Scott Larson Modified comment(s), added */ -/* ULONG64_DEFINED, */ -/* resulting in version 6.1.5 */ -/* 06-02-2021 Scott Larson Modified comment(s), removed */ -/* unneeded header file, funcs */ -/* set_control and get_control */ -/* changed to inline, */ -/* added symbol to enable */ -/* stack error handler, */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 Scott Larson Modified comment(s), improved */ -/* stack check error handling, */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comment(s), unified */ -/* this file across compilers, */ -/* fixed predefined macro, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* described BASEPRI usage, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -705,7 +675,7 @@ VOID _tx_thread_interrupt_restore(UIN #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M33 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M33 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m33/iar/inc/tx_secure_interface.h b/ports_module/cortex_m33/iar/inc/tx_secure_interface.h index 39b5d5fd..5ac37fbf 100644 --- a/ports_module/cortex_m33/iar/inc/tx_secure_interface.h +++ b/ports_module/cortex_m33/iar/inc/tx_secure_interface.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,12 +38,6 @@ /* It is assumed that tx_api.h and tx_port.h have already been */ /* included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_SECURE_INTERFACE_H diff --git a/ports_module/cortex_m33/iar/inc/txm_module_port.h b/ports_module/cortex_m33/iar/inc/txm_module_port.h index 84c62e1e..c84586b2 100644 --- a/ports_module/cortex_m33/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m33/iar/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,14 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* 01-31-2022 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -351,6 +344,6 @@ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instanc #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M33/IAR Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M33/IAR Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m33/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m33/iar/module_lib/src/txm_module_thread_shell_entry.c index ac1a3e29..1d2e1720 100644 --- a/ports_module/cortex_m33/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m33/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID __iar_data_init3(VOID); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the IAR C environment. */ __iar_data_init3(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m33/iar/module_lib/src/txm_thread_secure_stack_allocate.c b/ports_module/cortex_m33/iar/module_lib/src/txm_thread_secure_stack_allocate.c index 91d90f1f..dc8297c4 100644 --- a/ports_module/cortex_m33/iar/module_lib/src/txm_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m33/iar/module_lib/src/txm_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { diff --git a/ports_module/cortex_m33/iar/module_lib/src/txm_thread_secure_stack_free.c b/ports_module/cortex_m33/iar/module_lib/src/txm_thread_secure_stack_free.c index 56d9718b..17e7a4da 100644 --- a/ports_module/cortex_m33/iar/module_lib/src/txm_thread_secure_stack_free.c +++ b/ports_module/cortex_m33/iar/module_lib/src/txm_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* Module application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { diff --git a/ports_module/cortex_m33/iar/module_manager/inc/txm_module_manager_dispatch_port.h b/ports_module/cortex_m33/iar/module_manager/inc/txm_module_manager_dispatch_port.h index 8bbcd5b3..0575c748 100644 --- a/ports_module/cortex_m33/iar/module_manager/inc/txm_module_manager_dispatch_port.h +++ b/ports_module/cortex_m33/iar/module_manager/inc/txm_module_manager_dispatch_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_restore.s index 1f0f001d..3cd737fb 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_save.s index 6cbfd2f6..4456513f 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_control.s index 27acc9bf..ada8e1be 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_disable.s index 405bfd1d..8531dde8 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_restore.s index 78d4624a..0e8bafdf 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s index 19fd6738..3b6a61ce 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,29 +69,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ -/* 04-02-2021 Scott Larson Modified comments and fixed */ -/* MPU region configuration, */ -/* resulting in version 6.1.6 */ -/* 06-02-2021 Scott Larson Fixed extended stack handling */ -/* when calling kernel APIs, */ -/* resulting in version 6.1.7 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Added preproc FPU option, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -533,7 +511,7 @@ SVC_Handler: ORREQ lr, lr, #0x10 // Set bit, return with standard frame STR r3, [r2, #0xB0] // Save thread stack pointer BIC r3, #1 // Clear possibly OR'd bit - + /* Build kernel stack by copying thread stack two registers at a time */ ADD r3, r3, #32 // Start at bottom of hardware stack LDMDB r3!, {r1-r2} @@ -639,20 +617,20 @@ _tx_svc_secure_alloc: CMP r1, r2 // Did we come from _tx_thread_secure_stack_allocate? IT NE // If no (not equal), then... BXNE lr // return from where we came. - + PUSH {r0, lr} // Save SP and EXC_RETURN LDM r0, {r0-r3} // Load function parameters from stack BL _tx_thread_secure_mode_stack_allocate POP {r12, lr} // Restore SP and EXC_RETURN STR r0, [r12] // Store function return value BX lr - + _tx_svc_secure_free: LDR r2, =_tx_free_return-1 // Load address of where we should have come from CMP r1, r2 // Did we come from _tx_thread_secure_stack_free? IT NE // If no (not equal), then... BXNE lr // return from where we came. - + PUSH {r0, lr} // Save SP and EXC_RETURN LDM r0, {r0-r3} // Load function parameters from stack BL _tx_thread_secure_mode_stack_free diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack.c index f2cf79f5..4e4a7803 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack.c +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -102,20 +103,6 @@ static INT tx_head_free_index = 0U; /* */ /* _tx_initialize_kernel_enter */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 10-16-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.1 */ -/* 06-02-2021 Scott Larson Change name, execute in */ -/* handler mode, */ -/* resulting in version 6.1.7 */ -/* 01-31-2022 Himanshu Gupta Modified comments(s), updated */ -/* secure stack allocation, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) UINT _tx_thread_secure_mode_stack_initialize(void) diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_allocate.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_allocate.s index 524f6ec3..f70db3d5 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_allocate.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_allocate.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,15 +53,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-02-2021 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.5 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) // { diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_free.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_free.s index 960a54e1..7a8c0545 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_free.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_free.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,15 +51,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 03-02-2021 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.5 */ -/* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) // { diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_initialize.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_initialize.s index 08200cd9..90b22834 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_initialize.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_secure_stack_initialize.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,17 +51,6 @@ /* CALLED BY */ /* */ /* TX_PORT_SPECIFIC_PRE_INITIALIZATION */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 07-29-2022 Scott Larson Modified comments and changed */ -/* secure stack initialization */ -/* macro to port-specific, */ -/* resulting in version 6.1.12 */ -/* */ /**************************************************************************/ // VOID _tx_thread_secure_stack_initialize(VOID) // { diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_build.s index ea318964..820bbc2e 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_system_return.s index a286567a..d8482053 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m33/iar/module_manager/src/tx_timer_interrupt.s index d79f23c9..d96dbc15 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,13 +68,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_allocate.c b/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_allocate.c index d6f061c2..344e5fd9 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_allocate.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_allocate.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) { @@ -76,10 +71,10 @@ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_siz return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_free.c b/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_free.c index aa452180..76832975 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_free.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txe_thread_secure_stack_free.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) { @@ -74,10 +69,10 @@ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) return(TX_FEATURE_NOT_ENABLED); #else UINT status; - + /* Default status to success. */ status = TX_SUCCESS; - + /* Check for an invalid thread pointer. */ if (thread_ptr == TX_NULL) { @@ -93,7 +88,7 @@ UINT status; /* Thread pointer is invalid, return appropriate error code. */ status = TX_THREAD_ERROR; } - + /* Check for interrupt call. */ if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) { @@ -104,7 +99,7 @@ UINT status; status = TX_CALLER_ERROR; } } - + /* Determine if everything is okay. */ if (status == TX_SUCCESS) { diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_alignment_adjust.c index 83487f01..76c52f02 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, @@ -77,7 +72,7 @@ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, /* Round code and data size UP to TXM_MODULE_MPU_ALIGNMENT bytes. */ *code_size = (*code_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); *data_size = (*data_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); - + /* Alignment for code and data is TXM_MODULE_MPU_ALIGNMENT bytes. */ *code_alignment = TXM_MODULE_MPU_ALIGNMENT; *data_alignment = TXM_MODULE_MPU_ALIGNMENT; diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_external_memory_enable.c index becd1da9..6e78d96d 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -105,7 +100,7 @@ ULONG shared_index; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -115,49 +110,49 @@ ULONG shared_index; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address must adhere to Cortex-M33 MPU alignment. */ address = (ULONG) start_address; if(address != (address & ~(TXM_MODULE_MPU_ALIGNMENT - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Set base address register with start address, sanitized attributes and execute never. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_base_address = address | (attributes & TXM_MODULE_ATTRIBUTE_MASK) | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; - + /* Set the limit address (data start + length-1), attribute index, and enable bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_limit_address = (address + length-1) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index d7dd22de..8048fa57 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index 8c42b43f..12976ffe 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_mm_register_setup.c index 53ae5fcf..b7dba686 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* _txm_module_manager_thread_create */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ -/* 04-02-2021 Scott Larson Modified comments and check */ -/* for overflow, */ -/* resulting 6.1.6 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) { @@ -94,27 +86,27 @@ ULONG callback_stack_size; /* Set base address register to module data address, which should be at least 32-byte aligned. Mask address to proper range, inner shareable, read write, execute never. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_base_address = ((ULONG) module_instance -> txm_module_instance_data_start & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE | TXM_MODULE_ATTRIBUTE_READ_WRITE | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; - + /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside each other without having to align their pointers. Note this only works when they all have the same alignment. */ - + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; - + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - + /* Set the limit address (data start + data size-1), attribute index, and enable bit. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_limit_address = (((ULONG) module_instance -> txm_module_instance_data_start + data_size - 1) & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; /* End of module data protection. */ - + /* Remaining MPU entries are disabled for now and can be used for shared memory. */ } @@ -173,7 +165,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_port_dispatch.c index 0c57bc42..6f0f16e3 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_port_dispatch.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_port_dispatch.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* _txm_module_manager_kernel_dispatch */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ -/* */ /**************************************************************************/ ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) { @@ -88,7 +83,7 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; ); break; } - + case TXM_THREAD_SECURE_STACK_FREE_CALL: { if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) @@ -102,13 +97,13 @@ ALIGN_TYPE return_value = TX_NOT_AVAILABLE; ); break; } - + default: { /* Unhandled kernel request, return an error! */ break; } } - + return(return_value); } diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_thread_stack_build.s index b543af9b..b8387650 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 08-02-2021 Scott Larson Initial Version 6.1.8 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m4/ac5/example_build/sample_threadx.c b/ports_module/cortex_m4/ac5/example_build/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports_module/cortex_m4/ac5/example_build/sample_threadx.c +++ b/ports_module/cortex_m4/ac5/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_m4/ac5/example_build/sample_threadx_module.c b/ports_module/cortex_m4/ac5/example_build/sample_threadx_module.c index f2647144..dcf73ef9 100644 --- a/ports_module/cortex_m4/ac5/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m4/ac5/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -26,7 +26,7 @@ #define EXTERNAL_MEMORY (0x80000) -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -107,7 +107,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -123,7 +123,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -135,42 +135,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -178,23 +178,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -238,7 +238,7 @@ void thread_0_entry(ULONG thread_input) { UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -248,7 +248,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -296,18 +296,18 @@ UINT status; { /* Test external memory sharing. */ *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -366,7 +366,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -419,7 +419,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m4/ac5/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m4/ac5/example_build/sample_threadx_module_manager.c index 210f0be0..4edcee3c 100644 --- a/ports_module/cortex_m4/ac5/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m4/ac5/example_build/sample_threadx_module_manager.c @@ -71,8 +71,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -92,22 +92,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); - + /* Enable a read/write shared memory region. */ txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -116,11 +116,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m4/ac5/example_build/tx_initialize_low_level.S b/ports_module/cortex_m4/ac5/example_build/tx_initialize_low_level.S index e2bdfe26..fb461536 100644 --- a/ports_module/cortex_m4/ac5/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m4/ac5/example_build/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -130,14 +131,6 @@ Reset_Handler /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -145,14 +138,14 @@ Reset_Handler _tx_initialize_low_level /* Disable interrupts during ThreadX initialization. */ - + CPSID i /* Set base of available memory to end of non-initialised RAM area. */ LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer LDR r1, =|Image$$ZI$$Limit| // Build first free address - ADD r1, r1, #4 // + ADD r1, r1, #4 // STR r1, [r0] // Setup first unused memory pointer /* Setup Vector Table Offset Register. */ @@ -166,7 +159,7 @@ _tx_initialize_low_level // LDR r0, =0xE0001000 // Build address of DWT register // LDR r1, [r0] // Pickup the current value // ORR r1, r1, #1 // Set the CYCCNTENA bit -// STR r1, [r0] // Enable the cycle count register +// STR r1, [r0] // Enable the cycle count register /* Set system stack pointer from vector value. */ @@ -198,7 +191,7 @@ _tx_initialize_low_level /* Return to caller. */ - BX lr + BX lr // } @@ -216,12 +209,12 @@ __user_initial_stackheap /* Define shells for each of the unused vectors. */ EXPORT __tx_BadHandler -__tx_BadHandler +__tx_BadHandler B __tx_BadHandler // EXPORT __tx_SVCallHandler //__tx_SVCallHandler -// B __tx_SVCallHandler +// B __tx_SVCallHandler EXPORT __tx_IntHandler __tx_IntHandler @@ -247,7 +240,7 @@ __tx_SysTickHandler BX LR // } - EXPORT __tx_NMIHandler + EXPORT __tx_NMIHandler __tx_NMIHandler B __tx_NMIHandler diff --git a/ports_module/cortex_m4/ac5/inc/tx_port.h b/ports_module/cortex_m4/ac5/inc/tx_port.h index 82a5a506..32f082d5 100644 --- a/ports_module/cortex_m4/ac5/inc/tx_port.h +++ b/ports_module/cortex_m4/ac5/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,15 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -243,7 +235,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -376,7 +368,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -535,7 +527,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #else #error "Compiler not supported." #endif @@ -719,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M4 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m4/ac5/inc/txm_module_port.h b/ports_module/cortex_m4/ac5/inc/txm_module_port.h index 2e5db5d4..617bea35 100644 --- a/ports_module/cortex_m4/ac5/inc/txm_module_port.h +++ b/ports_module/cortex_m4/ac5/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,24 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* 07-29-2022 Scott Larson Enabled user-defined and */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Configure heap size, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Set default values for RBAR, */ -/* unify this file for all */ -/* compilers, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -463,6 +446,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M4 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M4 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m4/ac5/module_lib/src/txm_module_initialize.s b/ports_module/cortex_m4/ac5/module_lib/src/txm_module_initialize.s index c93160a7..2ce68011 100644 --- a/ports_module/cortex_m4/ac5/module_lib/src/txm_module_initialize.s +++ b/ports_module/cortex_m4/ac5/module_lib/src/txm_module_initialize.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _txm_module_thread_shell_entry Start module thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_initialize(VOID) diff --git a/ports_module/cortex_m4/ac5/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m4/ac5/module_lib/src/txm_module_thread_shell_entry.c index 17b178a3..b7bccaa8 100644 --- a/ports_module/cortex_m4/ac5/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m4/ac5/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -87,12 +88,6 @@ __align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE]; /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -108,14 +103,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _txm_module_initialize(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -123,7 +118,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_restore.s index de72ba83..f401e147 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_save.s index 572f40a8..16d7536e 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_control.s index c64bac49..f3e273ed 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_disable.s index 58191f13..555691e4 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_restore.s index 0564cfc5..7eb19d65 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_schedule.s index 3494c7c1..1c82b416 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,23 +67,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, optional */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* fixed label syntax, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_stack_build.s index ce5e27db..5d090bbc 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_system_return.s index b32ebf2e..06d5ccae 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m4/ac5/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m4/ac5/module_manager/src/tx_timer_interrupt.s index 3e66442b..e2682bf3 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m4/ac5/module_manager/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,18 +72,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_alignment_adjust.c index 43357dde..e9e46163 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 32. */ if(size <= 32) return 32; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_external_memory_enable.c index 122d65d7..64c4649c 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Update defines, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -114,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -124,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -224,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -234,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -246,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c index b9f9bec5..b1c79ebf 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c index 27ebd05c..a7fd7f11 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c index d62fa8cb..06e27aed 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -94,16 +95,6 @@ const ULONG txm_module_default_mpu_registers[32] = /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Changed from lookup table to */ -/* calculation and check for */ -/* minumum block size, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_thread_stack_build.s index 3a7e076f..505706da 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_user_mode_entry.s b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_user_mode_entry.s index 4fcddbc5..dceea55a 100644 --- a/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_user_mode_entry.s +++ b/ports_module/cortex_m4/ac5/module_manager/src/txm_module_manager_user_mode_entry.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,13 +55,6 @@ /* CALLED BY */ /* */ /* Modules in user mode */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_user_mode_entry(VOID) // { diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx/.cproject b/ports_module/cortex_m4/ac6/example_build/sample_threadx/.cproject index 8e1efcb8..8af62edd 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx/.cproject +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx/.cproject @@ -1,170 +1,170 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx/exceptions.c b/ports_module/cortex_m4/ac6/example_build/sample_threadx/exceptions.c index 01dd0b27..4ff00618 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx/exceptions.c +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx/exceptions.c @@ -1,7 +1,7 @@ /* ** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ** Use, modification and redistribution of this file is subject to your possession of a -** valid End User License Agreement for the Arm Product of which these examples are part of +** valid End User License Agreement for the Arm Product of which these examples are part of ** and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.c index 597f373c..13ffadba 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -81,42 +81,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -124,23 +124,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -243,11 +243,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -306,7 +306,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -359,7 +359,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_module/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.scat index eb8e0c23..1b489e7d 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S index e615eedb..ccd76ffb 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,12 +75,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/.cproject b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/.cproject index 0a74f9ff..de727955 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/.cproject +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/.cproject @@ -1,218 +1,218 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/sample_threadx_module.c index f2647144..dcf73ef9 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -26,7 +26,7 @@ #define EXTERNAL_MEMORY (0x80000) -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -107,7 +107,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -123,7 +123,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -135,42 +135,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -178,23 +178,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -238,7 +238,7 @@ void thread_0_entry(ULONG thread_input) { UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -248,7 +248,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -296,18 +296,18 @@ UINT status; { /* Test external memory sharing. */ *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -366,7 +366,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -419,7 +419,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/txm_module_preamble.S index 1fcc5d15..71914151 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -2,7 +2,7 @@ .align 4 .syntax unified .section Init - + // Define public symbols .global __txm_module_preamble diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/.cproject index f6ece7e0..212b7e51 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/.cproject +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/.cproject @@ -1,172 +1,172 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/exceptions.c b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/exceptions.c index 0cef25ce..fc26b89c 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/exceptions.c +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/exceptions.c @@ -1,7 +1,7 @@ /* ** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ** Use, modification and redistribution of this file is subject to your possession of a -** valid End User License Agreement for the Arm Product of which these examples are part of +** valid End User License Agreement for the Arm Product of which these examples are part of ** and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat index eb8e0c23..1b489e7d 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index 210f0be0..4edcee3c 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -71,8 +71,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -92,22 +92,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); - + /* Enable a read/write shared memory region. */ txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -116,11 +116,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S index eb3e2f3a..4e457588 100644 --- a/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S +++ b/ports_module/cortex_m4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,14 +75,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -111,7 +104,7 @@ _tx_initialize_low_level: // LDR r0, =0xE0001000 // Build address of DWT register // LDR r1, [r0] // Pickup the current value // ORR r1, r1, #1 // Set the CYCCNTENA bit -// STR r1, [r0] // Enable the cycle count register +// STR r1, [r0] // Enable the cycle count register /* Set system stack pointer from vector value. */ diff --git a/ports_module/cortex_m4/ac6/example_build/tx/.cproject b/ports_module/cortex_m4/ac6/example_build/tx/.cproject index 945d3c88..8f251099 100644 --- a/ports_module/cortex_m4/ac6/example_build/tx/.cproject +++ b/ports_module/cortex_m4/ac6/example_build/tx/.cproject @@ -1,162 +1,162 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_m4/ac6/example_build/txm/.cproject b/ports_module/cortex_m4/ac6/example_build/txm/.cproject index 2ba3d353..ff5b90d7 100644 --- a/ports_module/cortex_m4/ac6/example_build/txm/.cproject +++ b/ports_module/cortex_m4/ac6/example_build/txm/.cproject @@ -1,184 +1,184 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_m4/ac6/inc/tx_port.h b/ports_module/cortex_m4/ac6/inc/tx_port.h index 82a5a506..32f082d5 100644 --- a/ports_module/cortex_m4/ac6/inc/tx_port.h +++ b/ports_module/cortex_m4/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,15 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -243,7 +235,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -376,7 +368,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -535,7 +527,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #else #error "Compiler not supported." #endif @@ -719,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M4 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m4/ac6/inc/txm_module_port.h b/ports_module/cortex_m4/ac6/inc/txm_module_port.h index 2e5db5d4..617bea35 100644 --- a/ports_module/cortex_m4/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m4/ac6/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,24 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* 07-29-2022 Scott Larson Enabled user-defined and */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Configure heap size, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Set default values for RBAR, */ -/* unify this file for all */ -/* compilers, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -463,6 +446,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M4 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M4 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m4/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_m4/ac6/module_lib/src/txm_module_initialize.S index c36f6905..acfcf382 100644 --- a/ports_module/cortex_m4/ac6/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_m4/ac6/module_lib/src/txm_module_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* _txm_module_thread_shell_entry Start module thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user configurable, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _txm_module_initialize(VOID) .global _txm_module_initialize diff --git a/ports_module/cortex_m4/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m4/ac6/module_lib/src/txm_module_thread_shell_entry.c index ba187987..e75e693d 100644 --- a/ports_module/cortex_m4/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m4/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -88,15 +89,6 @@ extern VOID _txm_module_initialize(VOID *heap_base, VOID *heap_top); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user configurable, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -112,14 +104,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _txm_module_initialize(&txm_heap[0], &txm_heap[TXM_MODULE_HEAP_SIZE-1]); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -127,7 +119,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_restore.S index d60cf6b8..330789f4 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_save.S index abc0ac5d..a6c1a053 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,14 +61,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_control.S index 76b114b8..51b0e3fe 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_disable.S index b2fb050d..df262e8c 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_restore.S index 47c8f0f9..d3e167bd 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_schedule.S index 4d52e60c..02431092 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -69,21 +70,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, optional */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_stack_build.S index 8cdaa034..5ae2c8f7 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_system_return.S index f75b1e7a..b4348f9d 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m4/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m4/ac6/module_manager/src/tx_timer_interrupt.S index f1f39c3f..1a52ecda 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,17 +71,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c index 43357dde..e9e46163 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 32. */ if(size <= 32) return 32; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c index 122d65d7..64c4649c 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Update defines, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -114,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -124,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -224,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -234,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -246,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c index b9f9bec5..b1c79ebf 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c index 27ebd05c..a7fd7f11 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index d62fa8cb..06e27aed 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -94,16 +95,6 @@ const ULONG txm_module_default_mpu_registers[32] = /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Changed from lookup table to */ -/* calculation and check for */ -/* minumum block size, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { diff --git a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index 4252a96a..aeec8b21 100644 --- a/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m4/gnu/example_build/cortexm_vectors.S b/ports_module/cortex_m4/gnu/example_build/cortexm_vectors.S index 6ae558e4..dc8d0aad 100644 --- a/ports_module/cortex_m4/gnu/example_build/cortexm_vectors.S +++ b/ports_module/cortex_m4/gnu/example_build/cortexm_vectors.S @@ -4,8 +4,8 @@ .global __tx_BadHandler .global __tx_SVCallHandler .global __tx_DBGHandler - .global __tx_PendSVHandler - .global __tx_SysTickHandler + .global __tx_PendSVHandler + .global __tx_SysTickHandler .global __tx_BadHandler .syntax unified @@ -15,9 +15,9 @@ .global _vectors _vectors: - .word __stack_end__ - .word reset_handler - .word __tx_NMIHandler + .word __stack_end__ + .word reset_handler + .word __tx_NMIHandler .word __tx_HardfaultHandler .word __tx_BadHandler .word __tx_BadHandler @@ -29,7 +29,7 @@ _vectors: .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // .word __tx_DBGHandler .word 0 // Reserved - .word __tx_PendSVHandler + .word __tx_PendSVHandler .word __tx_SysTickHandler // Used by Threadx timer functionality .word __tx_BadHandler // Populate with user Interrupt handler .word __tx_BadHandler diff --git a/ports_module/cortex_m4/gnu/example_build/gcc_setup.s b/ports_module/cortex_m4/gnu/example_build/gcc_setup.s index d7c61892..4a729ffe 100644 --- a/ports_module/cortex_m4/gnu/example_build/gcc_setup.s +++ b/ports_module/cortex_m4/gnu/example_build/gcc_setup.s @@ -14,7 +14,7 @@ _gcc_setup: mov r5,r0 /* Copy GOT table. */ - + ldr r0, =__got_load_start__ sub r0,r0,r3 add r0,r0,r5 @@ -42,13 +42,13 @@ flash_area: address_built: str r6, [r1] // Store in new GOT table add r0, r0, #4 // Move to next entry - add r1, r1, #4 // + add r1, r1, #4 // b new_got_setup // Continue at the top of the loop got_setup_done: /* Copy initialised sections into RAM if required. */ - + ldr r0, =__data_load_start__ sub r0,r0,r3 add r0,r0,r5 @@ -59,9 +59,9 @@ got_setup_done: sub r2,r2,r4 add r2,r2,r9 bl crt0_memory_copy - + /* Zero bss. */ - + ldr r0, =__bss_start__ sub r0,r0,r4 add r0,r0,r9 @@ -85,10 +85,10 @@ got_setup_done: str r2, [r0] add r0, r0, #4 str r1, [r0] - + LDMIA sp!, {r3, r4, r5, r6, r7, lr} // Store other preserved registers bx lr // Return to caller - + .align 4 /* Startup helper functions. */ @@ -124,4 +124,3 @@ memory_set_done: /* Setup attibutes of heap section so it doesn't take up room in the elf file */ .section .heap, "wa", %nobits - \ No newline at end of file diff --git a/ports_module/cortex_m4/gnu/example_build/sample_threadx_module.c b/ports_module/cortex_m4/gnu/example_build/sample_threadx_module.c index 52557312..b74d7a35 100644 --- a/ports_module/cortex_m4/gnu/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m4/gnu/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -101,7 +101,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -117,7 +117,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -129,42 +129,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -172,23 +172,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -233,7 +233,7 @@ void thread_0_entry(ULONG thread_input) UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -243,7 +243,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -291,19 +291,19 @@ UINT status; { /* Test memory handler. */ *(ULONG *)0x20010000 = 0xCDCDCDCD; - - + + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -362,7 +362,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -415,7 +415,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m4/gnu/example_build/sample_threadx_module.ld b/ports_module/cortex_m4/gnu/example_build/sample_threadx_module.ld index 30c66655..5fa4c680 100644 --- a/ports_module/cortex_m4/gnu/example_build/sample_threadx_module.ld +++ b/ports_module/cortex_m4/gnu/example_build/sample_threadx_module.ld @@ -125,7 +125,7 @@ SECTIONS KEEP (*(.got*)) . = ALIGN(4); _egot = .; - } + } __got_end__ = __got_load_start__ + SIZEOF(.got); __rodata_load_start__ = ALIGN(__got_end__ , 4); @@ -135,7 +135,7 @@ SECTIONS *(.rodata .rodata.* .gnu.linkonce.r.*) } __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); - + __code_size__ = SIZEOF(.data) + __rodata_end__ - __FLASH_segment_start__; __fast_load_start__ = ALIGN(__rodata_end__ , 4); diff --git a/ports_module/cortex_m4/gnu/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m4/gnu/example_build/sample_threadx_module_manager.c index 203223be..feaaf2af 100644 --- a/ports_module/cortex_m4/gnu/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m4/gnu/example_build/sample_threadx_module_manager.c @@ -54,8 +54,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -75,22 +75,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_memory_load(&my_module, "my module", (VOID *) 0x00030000); - + /* Enable 128 byte read/write shared memory region at 0x20010000. */ txm_module_manager_external_memory_enable(&my_module, (void *) 0x20010000, 128, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -99,11 +99,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m4/gnu/example_build/tx_initialize_low_level.S b/ports_module/cortex_m4/gnu/example_build/tx_initialize_low_level.S index d32562b4..e922a5b5 100644 --- a/ports_module/cortex_m4/gnu/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m4/gnu/example_build/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -73,14 +74,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -89,18 +82,18 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) _tx_initialize_low_level: /* Disable interrupts during ThreadX initialization. */ - + CPSID i /* Set base of available memory to end of non-initialised RAM area. */ LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer LDR r1, =__RAM_segment_used_end__ // Build first free address - ADD r1, r1, #4 // + ADD r1, r1, #4 // STR r1, [r0] // Setup first unused memory pointer /* Setup Vector Table Offset Register. */ - + MOV r0, #0xE000E000 // Build address of NVIC registers LDR r1, =_vectors // Pickup address of vector table STR r1, [r0, #0xD08] // Set vector table address @@ -110,7 +103,7 @@ _tx_initialize_low_level: // LDR r0, =0xE0001000 // Build address of DWT register // LDR r1, [r0] // Pickup the current value // ORR r1, r1, #1 // Set the CYCCNTENA bit -// STR r1, [r0] // Enable the cycle count register +// STR r1, [r0] // Enable the cycle count register /* Set system stack pointer from vector value. */ @@ -142,7 +135,7 @@ _tx_initialize_low_level: /* Return to caller. */ - BX lr + BX lr // } @@ -169,7 +162,7 @@ __tx_IntHandler: PUSH {r0, lr} #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY BL _tx_execution_isr_enter // Call the ISR enter function -#endif +#endif /* Do interrupt handler work here */ /* BL .... */ @@ -205,7 +198,7 @@ SysTick_Handler: /* NMI, DBG handlers */ - .global __tx_NMIHandler + .global __tx_NMIHandler .thumb_func __tx_NMIHandler: B __tx_NMIHandler diff --git a/ports_module/cortex_m4/gnu/example_build/txm_module_preamble.S b/ports_module/cortex_m4/gnu/example_build/txm_module_preamble.S index ded31277..5f663569 100644 --- a/ports_module/cortex_m4/gnu/example_build/txm_module_preamble.S +++ b/ports_module/cortex_m4/gnu/example_build/txm_module_preamble.S @@ -33,7 +33,7 @@ __txm_module_preamble: // 1 -> User mode execution .dc.l _txm_module_thread_shell_entry - . - 0 // Module Shell Entry Point .dc.l demo_module_start - . - 0 // Module Start Thread Entry Point - .dc.l 0 // Module Stop Thread Entry Point + .dc.l 0 // Module Stop Thread Entry Point .dc.l 1 // Module Start/Stop Thread Priority .dc.l 1024 // Module Start/Stop Thread Stack Size .dc.l _txm_module_callback_request_thread_entry - . - 0 // Module Callback Thread Entry diff --git a/ports_module/cortex_m4/gnu/inc/tx_port.h b/ports_module/cortex_m4/gnu/inc/tx_port.h index 82a5a506..32f082d5 100644 --- a/ports_module/cortex_m4/gnu/inc/tx_port.h +++ b/ports_module/cortex_m4/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,15 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -243,7 +235,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -376,7 +368,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -535,7 +527,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #else #error "Compiler not supported." #endif @@ -719,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M4 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m4/gnu/inc/txm_module_port.h b/ports_module/cortex_m4/gnu/inc/txm_module_port.h index 2e5db5d4..617bea35 100644 --- a/ports_module/cortex_m4/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m4/gnu/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,24 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* 07-29-2022 Scott Larson Enabled user-defined and */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Configure heap size, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Set default values for RBAR, */ -/* unify this file for all */ -/* compilers, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -463,6 +446,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M4 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M4 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m4/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m4/gnu/module_lib/src/txm_module_thread_shell_entry.c index d751fc01..30632c1e 100644 --- a/ports_module/cortex_m4/gnu/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m4/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _gcc_setup(thread_info -> txm_module_thread_entry_info_code_base_address); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_restore.S index af374956..85b1ee2a 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_save.S index 0728d86e..9c0f547a 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_control.S index 38790a85..55791677 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_disable.S index e0ae359a..56c4c4bc 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_restore.S index 32839c40..9d2ba7b0 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_schedule.S index 734b64e7..a5a80868 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,23 +68,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Fixed predefined macro name, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, optional */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_stack_build.S index c62ccf30..0b26d993 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S index 234a2121..8c4a09fd 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m4/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m4/gnu/module_manager/src/tx_timer_interrupt.S index 4d0c8003..6a14a673 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m4/gnu/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,17 +71,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_alignment_adjust.c index 43357dde..e9e46163 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 32. */ if(size <= 32) return 32; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_external_memory_enable.c index 122d65d7..64c4649c 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Update defines, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -114,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -124,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -224,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -234,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -246,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c index b9f9bec5..b1c79ebf 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c index 27ebd05c..a7fd7f11 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index d62fa8cb..06e27aed 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -94,16 +95,6 @@ const ULONG txm_module_default_mpu_registers[32] = /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Changed from lookup table to */ -/* calculation and check for */ -/* minumum block size, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { diff --git a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_thread_stack_build.s index 3803b716..9c6b12e6 100644 --- a/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m4/gnu/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,13 +55,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m4/iar/example_build/cstartup_M.s b/ports_module/cortex_m4/iar/example_build/cstartup_M.s index 75d9369b..d1c5aa3e 100644 --- a/ports_module/cortex_m4/iar/example_build/cstartup_M.s +++ b/ports_module/cortex_m4/iar/example_build/cstartup_M.s @@ -2,16 +2,16 @@ PUBLIC __vector_table SECTION .text:CODE:REORDER(1) - + ;; Keep vector table even if it's not referenced REQUIRE __vector_table - + THUMB - + ;; Forward declaration of sections. SECTION CSTACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) - + DATA __vector_table diff --git a/ports_module/cortex_m4/iar/example_build/sample_threadx.c b/ports_module/cortex_m4/iar/example_build/sample_threadx.c index 60f5a3d3..55b63731 100644 --- a/ports_module/cortex_m4/iar/example_build/sample_threadx.c +++ b/ports_module/cortex_m4/iar/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete description of this demonstration. */ @@ -69,7 +69,7 @@ void thread_6_and_7_entry(ULONG thread_input); int main() { - + /* Please refer to Chapter 6 of the ThreadX User Guide for a complete description of this demonstration. */ @@ -101,41 +101,41 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -143,23 +143,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -262,11 +262,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -325,7 +325,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -378,7 +378,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_m4/iar/example_build/sample_threadx_module.c b/ports_module/cortex_m4/iar/example_build/sample_threadx_module.c index 939433cd..e9605af8 100644 --- a/ports_module/cortex_m4/iar/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m4/iar/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -101,7 +101,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -117,7 +117,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -129,42 +129,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -172,23 +172,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -233,7 +233,7 @@ void thread_0_entry(ULONG thread_input) UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -243,7 +243,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -291,19 +291,19 @@ UINT status; { /* Test memory handler. */ *(ULONG *)0x64005000 = 0xCDCDCDCD; - - + + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -362,7 +362,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -415,7 +415,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m4/iar/example_build/sample_threadx_module.icf b/ports_module/cortex_m4/iar/example_build/sample_threadx_module.icf index 8cfe4766..167c26fb 100644 --- a/ports_module/cortex_m4/iar/example_build/sample_threadx_module.icf +++ b/ports_module/cortex_m4/iar/example_build/sample_threadx_module.icf @@ -35,11 +35,11 @@ do not initialize { section .noinit }; //place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -define movable block ROPI with alignment = 4, fixed order -{ +define movable block ROPI with alignment = 4, fixed order +{ ro object txm_module_preamble.o, - ro, - ro data + ro, + ro data }; define movable block RWPI with alignment = 8, fixed order, static base diff --git a/ports_module/cortex_m4/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m4/iar/example_build/sample_threadx_module_manager.c index aea2c0b1..f925b527 100644 --- a/ports_module/cortex_m4/iar/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m4/iar/example_build/sample_threadx_module_manager.c @@ -53,8 +53,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -74,22 +74,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x080F0000); - + /* Enable 128 byte read/write shared memory region at 0x64005000. */ txm_module_manager_external_memory_enable(&my_module, (void *) 0x64005000, 128, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -98,7 +98,7 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { diff --git a/ports_module/cortex_m4/iar/example_build/startup.s b/ports_module/cortex_m4/iar/example_build/startup.s index ba46e572..feddd8b4 100644 --- a/ports_module/cortex_m4/iar/example_build/startup.s +++ b/ports_module/cortex_m4/iar/example_build/startup.s @@ -7,7 +7,7 @@ ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR +;* - Set the vector table entries with the exceptions ISR ;* address. ;* After Reset the Cortex-M4 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. @@ -68,86 +68,86 @@ __vector_table DCD SysTick_Handler ; SysTick Handler ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FSMC_IRQHandler ; FSMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD CRYP_IRQHandler ; CRYP crypto + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto DCD HASH_RNG_IRQHandler ; Hash and Rng DCD FPU_IRQHandler ; FPU @@ -218,47 +218,47 @@ SysTick_Handler PUBWEAK WWDG_IRQHandler SECTION .text:CODE:NOROOT(2) -WWDG_IRQHandler +WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_IRQHandler SECTION .text:CODE:NOROOT(2) -PVD_IRQHandler +PVD_IRQHandler B PVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:NOROOT(2) -TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT(2) +TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:NOROOT(2) -RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:NOROOT(2) -FLASH_IRQHandler +FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:NOROOT(2) -RCC_IRQHandler +RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:NOROOT(2) -EXTI0_IRQHandler +EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:NOROOT(2) -EXTI1_IRQHandler +EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:NOROOT(2) -EXTI2_IRQHandler +EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler @@ -267,363 +267,363 @@ EXTI3_IRQHandler B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT(2) -EXTI4_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:NOROOT(2) -ADC_IRQHandler +ADC_IRQHandler B ADC_IRQHandler PUBWEAK CAN1_TX_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_TX_IRQHandler B CAN1_TX_IRQHandler PUBWEAK CAN1_RX0_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_RX0_IRQHandler B CAN1_RX0_IRQHandler PUBWEAK CAN1_RX1_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_RX1_IRQHandler B CAN1_RX1_IRQHandler PUBWEAK CAN1_SCE_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN1_SCE_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_SCE_IRQHandler B CAN1_SCE_IRQHandler PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:NOROOT(2) -EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_TIM9_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_BRK_TIM9_IRQHandler B TIM1_BRK_TIM9_IRQHandler PUBWEAK TIM1_UP_TIM10_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_UP_TIM10_IRQHandler B TIM1_UP_TIM10_IRQHandler PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_TRG_COM_TIM11_IRQHandler B TIM1_TRG_COM_TIM11_IRQHandler - + PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:NOROOT(2) -TIM2_IRQHandler +TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:NOROOT(2) -TIM3_IRQHandler +TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:NOROOT(2) -TIM4_IRQHandler +TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:NOROOT(2) -SPI1_IRQHandler +SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:NOROOT(2) -SPI2_IRQHandler +SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:NOROOT(2) -USART1_IRQHandler +USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:NOROOT(2) -USART2_IRQHandler +USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:NOROOT(2) -USART3_IRQHandler +USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:NOROOT(2) -EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT(2) -RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT(2) +RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT(2) -OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_FS_WKUP_IRQHandler B OTG_FS_WKUP_IRQHandler - + PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FSMC_IRQHandler SECTION .text:CODE:NOROOT(2) -FSMC_IRQHandler +FSMC_IRQHandler B FSMC_IRQHandler PUBWEAK SDIO_IRQHandler SECTION .text:CODE:NOROOT(2) -SDIO_IRQHandler +SDIO_IRQHandler B SDIO_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:NOROOT(2) -TIM5_IRQHandler +TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:NOROOT(2) -SPI3_IRQHandler +SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:NOROOT(2) -UART4_IRQHandler +UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:NOROOT(2) -UART5_IRQHandler +UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:NOROOT(2) -TIM7_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:NOROOT(2) -ETH_IRQHandler +ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:NOROOT(2) -ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK CAN2_TX_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN2_TX_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_TX_IRQHandler B CAN2_TX_IRQHandler PUBWEAK CAN2_RX0_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN2_RX0_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_RX0_IRQHandler B CAN2_RX0_IRQHandler PUBWEAK CAN2_RX1_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN2_RX1_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_RX1_IRQHandler B CAN2_RX1_IRQHandler PUBWEAK CAN2_SCE_IRQHandler - SECTION .text:CODE:NOROOT(2) -CAN2_SCE_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_SCE_IRQHandler B CAN2_SCE_IRQHandler PUBWEAK OTG_FS_IRQHandler SECTION .text:CODE:NOROOT(2) -OTG_FS_IRQHandler +OTG_FS_IRQHandler B OTG_FS_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:NOROOT(2) -DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:NOROOT(2) -USART6_IRQHandler +USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:NOROOT(2) -I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT(2) -OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT(2) -OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT(2) -OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:NOROOT(2) -OTG_HS_IRQHandler +OTG_HS_IRQHandler B OTG_HS_IRQHandler PUBWEAK DCMI_IRQHandler SECTION .text:CODE:NOROOT(2) -DCMI_IRQHandler +DCMI_IRQHandler B DCMI_IRQHandler PUBWEAK CRYP_IRQHandler SECTION .text:CODE:NOROOT(2) -CRYP_IRQHandler +CRYP_IRQHandler B CRYP_IRQHandler PUBWEAK HASH_RNG_IRQHandler - SECTION .text:CODE:NOROOT(2) -HASH_RNG_IRQHandler + SECTION .text:CODE:NOROOT(2) +HASH_RNG_IRQHandler B HASH_RNG_IRQHandler PUBWEAK FPU_IRQHandler - SECTION .text:CODE:NOROOT(2) -FPU_IRQHandler + SECTION .text:CODE:NOROOT(2) +FPU_IRQHandler B FPU_IRQHandler END diff --git a/ports_module/cortex_m4/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_m4/iar/example_build/tx_initialize_low_level.s index 625fa222..07afc829 100644 --- a/ports_module/cortex_m4/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_m4/iar/example_build/tx_initialize_low_level.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -29,11 +30,11 @@ SYSTEM_CLOCK EQU 25000000 SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) - + RSEG FREE_MEM:DATA PUBLIC __tx_free_memory_start __tx_free_memory_start - DS32 4 + DS32 4 SECTION `.text`:CODE:NOROOT(2) THUMB @@ -70,15 +71,6 @@ __tx_free_memory_start /* CALLED BY */ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -86,7 +78,7 @@ __tx_free_memory_start _tx_initialize_low_level: /* Disable interrupts during ThreadX initialization. */ - + CPSID i /* Set base of available memory to end of non-initialised RAM area. */ @@ -96,7 +88,7 @@ _tx_initialize_low_level: STR r1, [r0] // Setup first unused memory pointer /* Setup Vector Table Offset Register. */ - + MOV r0, #0xE000E000 // Build address of NVIC registers LDR r1, =__vector_table // Pickup address of vector table STR r1, [r0, #0xD08] // Set vector table address @@ -106,7 +98,7 @@ _tx_initialize_low_level: // LDR r0, =0xE0001000 // Build address of DWT register // LDR r1, [r0] // Pickup the current value // ORR r1, r1, #1 // Set the CYCCNTENA bit -// STR r1, [r0] // Enable the cycle count register +// STR r1, [r0] // Enable the cycle count register /* Set system stack pointer from vector value. */ @@ -138,7 +130,7 @@ _tx_initialize_low_level: /* Return to caller. */ - BX lr + BX lr // } PUBLIC SysTick_Handler diff --git a/ports_module/cortex_m4/iar/inc/tx_port.h b/ports_module/cortex_m4/iar/inc/tx_port.h index 82a5a506..32f082d5 100644 --- a/ports_module/cortex_m4/iar/inc/tx_port.h +++ b/ports_module/cortex_m4/iar/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,15 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -243,7 +235,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -376,7 +368,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -535,7 +527,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #else #error "Compiler not supported." #endif @@ -719,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M4 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M4 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m4/iar/inc/txm_module_port.h b/ports_module/cortex_m4/iar/inc/txm_module_port.h index 2e5db5d4..617bea35 100644 --- a/ports_module/cortex_m4/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m4/iar/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,24 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* 07-29-2022 Scott Larson Enabled user-defined and */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Configure heap size, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Set default values for RBAR, */ -/* unify this file for all */ -/* compilers, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -463,6 +446,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M4 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M4 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m4/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m4/iar/module_lib/src/txm_module_thread_shell_entry.c index 70b4e83a..5d7767ae 100644 --- a/ports_module/cortex_m4/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m4/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID __iar_data_init3(VOID); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ __iar_data_init3(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_iar.c b/ports_module/cortex_m4/iar/module_manager/src/tx_iar.c index ee47f10f..238b485e 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_iar.c +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_iar.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_misra.s b/ports_module/cortex_m4/iar/module_manager/src/tx_misra.s index 72aac789..c79133f5 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_misra.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_misra.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -116,7 +117,7 @@ SECTION `.data`:DATA:REORDER:NOROOT(2) DATA -// 51 CHAR _tx_version_id[100] = "Copyright (c) 2024 Microsoft Corporation. * ThreadX 6.1 MISRA C Compliant *"; +// 51 CHAR _tx_version_id[100] = "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX 6.1 MISRA C Compliant *"; _tx_version_id: DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H @@ -703,7 +704,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -718,7 +719,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARMVFP__ /***********************************************************************************************/ @@ -735,8 +736,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -750,10 +751,10 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - - + + SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2) SECTION_TYPE SHT_PROGBITS, 0 DATA diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_restore.s index ff4f11e0..d0033b5b 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_save.s index c26d32c5..f1291fec 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_control.s index b72bbad3..e0e028c8 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_disable.s index 4002679f..00dab2e2 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_restore.s index b9093f8a..cf834228 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_schedule.s index e618cb7f..b6a8c277 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,22 +64,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, optional */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_stack_build.s index 01213848..a80261c2 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_system_return.s index 3260e917..4f8b9870 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m4/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m4/iar/module_manager/src/tx_timer_interrupt.s index 72cc4f61..fbf9c2ab 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m4/iar/module_manager/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,18 +72,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_alignment_adjust.c index 43357dde..e9e46163 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 32. */ if(size <= 32) return 32; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_external_memory_enable.c index 122d65d7..64c4649c 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Update defines, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -114,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -124,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -224,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -234,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -246,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index b9f9bec5..b1c79ebf 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index 27ebd05c..a7fd7f11 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c index d62fa8cb..06e27aed 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -94,16 +95,6 @@ const ULONG txm_module_default_mpu_registers[32] = /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Changed from lookup table to */ -/* calculation and check for */ -/* minumum block size, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { diff --git a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_thread_stack_build.s index 78dfa784..fab79337 100644 --- a/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m4/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m7/ac5/example_build/sample_threadx.c b/ports_module/cortex_m7/ac5/example_build/sample_threadx.c index 418ec634..8c61de06 100644 --- a/ports_module/cortex_m7/ac5/example_build/sample_threadx.c +++ b/ports_module/cortex_m7/ac5/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -242,11 +242,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -305,7 +305,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -358,7 +358,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_m7/ac5/example_build/sample_threadx_module.c b/ports_module/cortex_m7/ac5/example_build/sample_threadx_module.c index f2647144..dcf73ef9 100644 --- a/ports_module/cortex_m7/ac5/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m7/ac5/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -26,7 +26,7 @@ #define EXTERNAL_MEMORY (0x80000) -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -107,7 +107,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -123,7 +123,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -135,42 +135,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -178,23 +178,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -238,7 +238,7 @@ void thread_0_entry(ULONG thread_input) { UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -248,7 +248,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -296,18 +296,18 @@ UINT status; { /* Test external memory sharing. */ *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -366,7 +366,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -419,7 +419,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m7/ac5/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m7/ac5/example_build/sample_threadx_module_manager.c index 210f0be0..4edcee3c 100644 --- a/ports_module/cortex_m7/ac5/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m7/ac5/example_build/sample_threadx_module_manager.c @@ -71,8 +71,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -92,22 +92,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); - + /* Enable a read/write shared memory region. */ txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -116,11 +116,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m7/ac5/example_build/tx_initialize_low_level.S b/ports_module/cortex_m7/ac5/example_build/tx_initialize_low_level.S index 2ab33a98..62d7eb93 100644 --- a/ports_module/cortex_m7/ac5/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m7/ac5/example_build/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -130,14 +131,6 @@ Reset_Handler /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -145,14 +138,14 @@ Reset_Handler _tx_initialize_low_level /* Disable interrupts during ThreadX initialization. */ - + CPSID i /* Set base of available memory to end of non-initialised RAM area. */ LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer LDR r1, =|Image$$ZI$$Limit| // Build first free address - ADD r1, r1, #4 // + ADD r1, r1, #4 // STR r1, [r0] // Setup first unused memory pointer /* Setup Vector Table Offset Register. */ @@ -166,7 +159,7 @@ _tx_initialize_low_level // LDR r0, =0xE0001000 // Build address of DWT register // LDR r1, [r0] // Pickup the current value // ORR r1, r1, #1 // Set the CYCCNTENA bit -// STR r1, [r0] // Enable the cycle count register +// STR r1, [r0] // Enable the cycle count register /* Set system stack pointer from vector value. */ @@ -198,7 +191,7 @@ _tx_initialize_low_level /* Return to caller. */ - BX lr + BX lr // } @@ -216,12 +209,12 @@ __user_initial_stackheap /* Define shells for each of the unused vectors. */ EXPORT __tx_BadHandler -__tx_BadHandler +__tx_BadHandler B __tx_BadHandler // EXPORT __tx_SVCallHandler //__tx_SVCallHandler -// B __tx_SVCallHandler +// B __tx_SVCallHandler EXPORT __tx_IntHandler __tx_IntHandler @@ -247,7 +240,7 @@ __tx_SysTickHandler BX LR // } - EXPORT __tx_NMIHandler + EXPORT __tx_NMIHandler __tx_NMIHandler B __tx_NMIHandler diff --git a/ports_module/cortex_m7/ac5/inc/tx_port.h b/ports_module/cortex_m7/ac5/inc/tx_port.h index ef0142e7..eed637a1 100644 --- a/ports_module/cortex_m7/ac5/inc/tx_port.h +++ b/ports_module/cortex_m7/ac5/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,15 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -243,7 +235,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -376,7 +368,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -535,7 +527,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #else #error "Compiler not supported." #endif @@ -719,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M7 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m7/ac5/inc/txm_module_port.h b/ports_module/cortex_m7/ac5/inc/txm_module_port.h index 187259f5..0c851699 100644 --- a/ports_module/cortex_m7/ac5/inc/txm_module_port.h +++ b/ports_module/cortex_m7/ac5/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,24 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* 07-29-2022 Scott Larson Enabled user-defined and */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Configure heap size, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Set default values for RBAR, */ -/* unify this file for all */ -/* compilers, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -463,6 +446,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M7 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M7 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m7/ac5/module_lib/src/txm_module_initialize.s b/ports_module/cortex_m7/ac5/module_lib/src/txm_module_initialize.s index 1c0b602d..0dc2b736 100644 --- a/ports_module/cortex_m7/ac5/module_lib/src/txm_module_initialize.s +++ b/ports_module/cortex_m7/ac5/module_lib/src/txm_module_initialize.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _txm_module_thread_shell_entry Start module thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_initialize(VOID) diff --git a/ports_module/cortex_m7/ac5/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m7/ac5/module_lib/src/txm_module_thread_shell_entry.c index 8725edcf..48f5b3a8 100644 --- a/ports_module/cortex_m7/ac5/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m7/ac5/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -87,12 +88,6 @@ __align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE]; /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -108,14 +103,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _txm_module_initialize(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -123,7 +118,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_restore.s index 5e826e21..0fb0e6c9 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_save.s index 0445f04c..12b27e73 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_control.s index 13ad3b6f..760396b3 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_disable.s index f3268762..02506666 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_restore.s index b51e9997..1b099aa2 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_schedule.s index d65a873a..1810905a 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,23 +67,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, optional */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* fixed label syntax, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_stack_build.s index 6f0a830f..d54a8486 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_system_return.s index 98ac59de..ed7165df 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m7/ac5/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m7/ac5/module_manager/src/tx_timer_interrupt.s index ea6286b8..f2393840 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m7/ac5/module_manager/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,18 +72,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c index c27e2255..3256d0b6 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 32. */ if(size <= 32) return 32; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c index 57e04f4a..804d701f 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Update defines, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -114,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -124,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -224,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -234,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -246,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c index 1589e608..12435ad5 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c index 605f50e4..ea010233 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c index 4d924b37..5f444833 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -94,16 +95,6 @@ const ULONG txm_module_default_mpu_registers[32] = /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Changed from lookup table to */ -/* calculation and check for */ -/* minumum block size, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s index 66398049..aba38988 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_user_mode_entry.s b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_user_mode_entry.s index 7d1d9ba1..9f9b6967 100644 --- a/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_user_mode_entry.s +++ b/ports_module/cortex_m7/ac5/module_manager/src/txm_module_manager_user_mode_entry.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,13 +55,6 @@ /* CALLED BY */ /* */ /* Modules in user mode */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_user_mode_entry(VOID) // { diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx/.cproject b/ports_module/cortex_m7/ac6/example_build/sample_threadx/.cproject index fc1cb75e..a8cd64d6 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx/.cproject +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx/.cproject @@ -1,170 +1,170 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx/exceptions.c b/ports_module/cortex_m7/ac6/example_build/sample_threadx/exceptions.c index 01dd0b27..4ff00618 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx/exceptions.c +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx/exceptions.c @@ -1,7 +1,7 @@ /* ** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ** Use, modification and redistribution of this file is subject to your possession of a -** valid End User License Agreement for the Arm Product of which these examples are part of +** valid End User License Agreement for the Arm Product of which these examples are part of ** and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.c index 597f373c..13ffadba 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -81,42 +81,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -124,23 +124,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -243,11 +243,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -306,7 +306,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -359,7 +359,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_module/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.scat index 8b4bb5bd..8be90bfd 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S index fd9f4f76..2837a142 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,12 +75,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/.cproject b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/.cproject index 1e1ea739..0db37787 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/.cproject +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/.cproject @@ -1,218 +1,218 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/sample_threadx_module.c index f2647144..dcf73ef9 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -26,7 +26,7 @@ #define EXTERNAL_MEMORY (0x80000) -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -107,7 +107,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -123,7 +123,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -135,42 +135,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -178,23 +178,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -238,7 +238,7 @@ void thread_0_entry(ULONG thread_input) { UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -248,7 +248,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -296,18 +296,18 @@ UINT status; { /* Test external memory sharing. */ *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -366,7 +366,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -419,7 +419,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/txm_module_preamble.S index 1fcc5d15..71914151 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/txm_module_preamble.S +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -2,7 +2,7 @@ .align 4 .syntax unified .section Init - + // Define public symbols .global __txm_module_preamble diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/.cproject index f6ca2712..c8bb89b5 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/.cproject +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/.cproject @@ -1,174 +1,174 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/exceptions.c b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/exceptions.c index 0cef25ce..fc26b89c 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/exceptions.c +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/exceptions.c @@ -1,7 +1,7 @@ /* ** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ** Use, modification and redistribution of this file is subject to your possession of a -** valid End User License Agreement for the Arm Product of which these examples are part of +** valid End User License Agreement for the Arm Product of which these examples are part of ** and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat index 8b4bb5bd..8be90bfd 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat @@ -1,7 +1,7 @@ ;******************************************************* ; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index 210f0be0..4edcee3c 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -71,8 +71,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -92,22 +92,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); - + /* Enable a read/write shared memory region. */ txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -116,11 +116,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S index 44d7a30d..2df350e5 100644 --- a/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S +++ b/ports_module/cortex_m7/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,14 +75,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -111,7 +104,7 @@ _tx_initialize_low_level: // LDR r0, =0xE0001000 // Build address of DWT register // LDR r1, [r0] // Pickup the current value // ORR r1, r1, #1 // Set the CYCCNTENA bit -// STR r1, [r0] // Enable the cycle count register +// STR r1, [r0] // Enable the cycle count register /* Set system stack pointer from vector value. */ diff --git a/ports_module/cortex_m7/ac6/example_build/tx/.cproject b/ports_module/cortex_m7/ac6/example_build/tx/.cproject index 5115080e..ec8102e7 100644 --- a/ports_module/cortex_m7/ac6/example_build/tx/.cproject +++ b/ports_module/cortex_m7/ac6/example_build/tx/.cproject @@ -1,162 +1,162 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_m7/ac6/example_build/txm/.cproject b/ports_module/cortex_m7/ac6/example_build/txm/.cproject index 02c85d5a..78fcedcb 100644 --- a/ports_module/cortex_m7/ac6/example_build/txm/.cproject +++ b/ports_module/cortex_m7/ac6/example_build/txm/.cproject @@ -1,184 +1,184 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_m7/ac6/inc/tx_port.h b/ports_module/cortex_m7/ac6/inc/tx_port.h index ef0142e7..eed637a1 100644 --- a/ports_module/cortex_m7/ac6/inc/tx_port.h +++ b/ports_module/cortex_m7/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,15 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -243,7 +235,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -376,7 +368,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -535,7 +527,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #else #error "Compiler not supported." #endif @@ -719,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M7 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m7/ac6/inc/txm_module_port.h b/ports_module/cortex_m7/ac6/inc/txm_module_port.h index 187259f5..0c851699 100644 --- a/ports_module/cortex_m7/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_m7/ac6/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,24 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* 07-29-2022 Scott Larson Enabled user-defined and */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Configure heap size, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Set default values for RBAR, */ -/* unify this file for all */ -/* compilers, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -463,6 +446,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M7 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M7 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m7/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_m7/ac6/module_lib/src/txm_module_initialize.S index 37f25b0e..7fb2e60f 100644 --- a/ports_module/cortex_m7/ac6/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_m7/ac6/module_lib/src/txm_module_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* _txm_module_thread_shell_entry Start module thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user configurable, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _txm_module_initialize(VOID) .global _txm_module_initialize diff --git a/ports_module/cortex_m7/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m7/ac6/module_lib/src/txm_module_thread_shell_entry.c index 98302d79..bd3c0c7c 100644 --- a/ports_module/cortex_m7/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m7/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -88,15 +89,6 @@ extern VOID _txm_module_initialize(VOID *heap_base, VOID *heap_top); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user configurable, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -112,14 +104,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _txm_module_initialize(&txm_heap[0], &txm_heap[TXM_MODULE_HEAP_SIZE-1]); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -127,7 +119,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_restore.S index 003bf20d..9ecbaa0c 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_save.S index a88957cc..1fab2a9b 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,14 +61,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_control.S index ddd46eb5..a10c760a 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_disable.S index f58e63d0..ea8bfd4d 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_restore.S index d195b3ff..7ea62177 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S index a07d64f7..a3126bc7 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -69,21 +70,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, optional */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_stack_build.S index fd1aa689..0fd0dc46 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S index 57262ceb..831c00e4 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m7/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m7/ac6/module_manager/src/tx_timer_interrupt.S index 86f2a7f3..a2f1a438 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,17 +71,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_alignment_adjust.c index c27e2255..3256d0b6 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 32. */ if(size <= 32) return 32; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_external_memory_enable.c index 57e04f4a..804d701f 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Update defines, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -114,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -124,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -224,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -234,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -246,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c index 1589e608..12435ad5 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c index 605f50e4..ea010233 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index 4d924b37..5f444833 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -94,16 +95,6 @@ const ULONG txm_module_default_mpu_registers[32] = /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Changed from lookup table to */ -/* calculation and check for */ -/* minumum block size, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { diff --git a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index 4c9a10dd..f18b5ef1 100644 --- a/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_m7/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m7/gnu/example_build/cortexm_crt0.s b/ports_module/cortex_m7/gnu/example_build/cortexm_crt0.s index d4cb1636..61ca8259 100644 --- a/ports_module/cortex_m7/gnu/example_build/cortexm_crt0.s +++ b/ports_module/cortex_m7/gnu/example_build/cortexm_crt0.s @@ -66,7 +66,7 @@ crt0_ctor_loop: beq crt0_ctor_end ldr r2, [r0] add r0, #4 - push {r0-r1} + push {r0-r1} blx r2 pop {r0-r1} b crt0_ctor_loop @@ -88,7 +88,7 @@ start: /* when main returns, loop forever. */ crt0_exit_loop: b crt0_exit_loop - + /* Startup helper functions. */ @@ -124,4 +124,3 @@ memory_set_done: .section .stack, "wa", %nobits .section .stack_process, "wa", %nobits .section .heap, "wa", %nobits - \ No newline at end of file diff --git a/ports_module/cortex_m7/gnu/example_build/gcc_setup.s b/ports_module/cortex_m7/gnu/example_build/gcc_setup.s index d7c61892..4a729ffe 100644 --- a/ports_module/cortex_m7/gnu/example_build/gcc_setup.s +++ b/ports_module/cortex_m7/gnu/example_build/gcc_setup.s @@ -14,7 +14,7 @@ _gcc_setup: mov r5,r0 /* Copy GOT table. */ - + ldr r0, =__got_load_start__ sub r0,r0,r3 add r0,r0,r5 @@ -42,13 +42,13 @@ flash_area: address_built: str r6, [r1] // Store in new GOT table add r0, r0, #4 // Move to next entry - add r1, r1, #4 // + add r1, r1, #4 // b new_got_setup // Continue at the top of the loop got_setup_done: /* Copy initialised sections into RAM if required. */ - + ldr r0, =__data_load_start__ sub r0,r0,r3 add r0,r0,r5 @@ -59,9 +59,9 @@ got_setup_done: sub r2,r2,r4 add r2,r2,r9 bl crt0_memory_copy - + /* Zero bss. */ - + ldr r0, =__bss_start__ sub r0,r0,r4 add r0,r0,r9 @@ -85,10 +85,10 @@ got_setup_done: str r2, [r0] add r0, r0, #4 str r1, [r0] - + LDMIA sp!, {r3, r4, r5, r6, r7, lr} // Store other preserved registers bx lr // Return to caller - + .align 4 /* Startup helper functions. */ @@ -124,4 +124,3 @@ memory_set_done: /* Setup attibutes of heap section so it doesn't take up room in the elf file */ .section .heap, "wa", %nobits - \ No newline at end of file diff --git a/ports_module/cortex_m7/gnu/example_build/sample_threadx_module.c b/ports_module/cortex_m7/gnu/example_build/sample_threadx_module.c index 52557312..b74d7a35 100644 --- a/ports_module/cortex_m7/gnu/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m7/gnu/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -101,7 +101,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -117,7 +117,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -129,42 +129,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -172,23 +172,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -233,7 +233,7 @@ void thread_0_entry(ULONG thread_input) UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -243,7 +243,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -291,19 +291,19 @@ UINT status; { /* Test memory handler. */ *(ULONG *)0x20010000 = 0xCDCDCDCD; - - + + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -362,7 +362,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -415,7 +415,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m7/gnu/example_build/sample_threadx_module.ld b/ports_module/cortex_m7/gnu/example_build/sample_threadx_module.ld index 30c66655..5fa4c680 100644 --- a/ports_module/cortex_m7/gnu/example_build/sample_threadx_module.ld +++ b/ports_module/cortex_m7/gnu/example_build/sample_threadx_module.ld @@ -125,7 +125,7 @@ SECTIONS KEEP (*(.got*)) . = ALIGN(4); _egot = .; - } + } __got_end__ = __got_load_start__ + SIZEOF(.got); __rodata_load_start__ = ALIGN(__got_end__ , 4); @@ -135,7 +135,7 @@ SECTIONS *(.rodata .rodata.* .gnu.linkonce.r.*) } __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); - + __code_size__ = SIZEOF(.data) + __rodata_end__ - __FLASH_segment_start__; __fast_load_start__ = ALIGN(__rodata_end__ , 4); diff --git a/ports_module/cortex_m7/gnu/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m7/gnu/example_build/sample_threadx_module_manager.c index 203223be..feaaf2af 100644 --- a/ports_module/cortex_m7/gnu/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m7/gnu/example_build/sample_threadx_module_manager.c @@ -54,8 +54,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -75,22 +75,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_memory_load(&my_module, "my module", (VOID *) 0x00030000); - + /* Enable 128 byte read/write shared memory region at 0x20010000. */ txm_module_manager_external_memory_enable(&my_module, (void *) 0x20010000, 128, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -99,11 +99,11 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_m7/gnu/example_build/tx_initialize_low_level.S b/ports_module/cortex_m7/gnu/example_build/tx_initialize_low_level.S index 1a1ca0de..e9273cbd 100644 --- a/ports_module/cortex_m7/gnu/example_build/tx_initialize_low_level.S +++ b/ports_module/cortex_m7/gnu/example_build/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -73,14 +74,6 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -89,18 +82,18 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) _tx_initialize_low_level: /* Disable interrupts during ThreadX initialization. */ - + CPSID i /* Set base of available memory to end of non-initialised RAM area. */ LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer LDR r1, =__RAM_segment_used_end__ // Build first free address - ADD r1, r1, #4 // + ADD r1, r1, #4 // STR r1, [r0] // Setup first unused memory pointer /* Setup Vector Table Offset Register. */ - + MOV r0, #0xE000E000 // Build address of NVIC registers LDR r1, =_vectors // Pickup address of vector table STR r1, [r0, #0xD08] // Set vector table address @@ -110,7 +103,7 @@ _tx_initialize_low_level: // LDR r0, =0xE0001000 // Build address of DWT register // LDR r1, [r0] // Pickup the current value // ORR r1, r1, #1 // Set the CYCCNTENA bit -// STR r1, [r0] // Enable the cycle count register +// STR r1, [r0] // Enable the cycle count register /* Set system stack pointer from vector value. */ @@ -142,7 +135,7 @@ _tx_initialize_low_level: /* Return to caller. */ - BX lr + BX lr // } @@ -169,7 +162,7 @@ __tx_IntHandler: PUSH {r0, lr} #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY BL _tx_execution_isr_enter // Call the ISR enter function -#endif +#endif /* Do interrupt handler work here */ /* BL .... */ @@ -205,7 +198,7 @@ SysTick_Handler: /* NMI, DBG handlers */ - .global __tx_NMIHandler + .global __tx_NMIHandler .thumb_func __tx_NMIHandler: B __tx_NMIHandler diff --git a/ports_module/cortex_m7/gnu/example_build/tx_simulator_startup.s b/ports_module/cortex_m7/gnu/example_build/tx_simulator_startup.s index 73692924..ef3d9314 100644 --- a/ports_module/cortex_m7/gnu/example_build/tx_simulator_startup.s +++ b/ports_module/cortex_m7/gnu/example_build/tx_simulator_startup.s @@ -6,9 +6,9 @@ .global _vectors _vectors: - .word __stack_end__ - .word reset_handler - .word __tx_NMIHandler + .word __stack_end__ + .word reset_handler + .word __tx_NMIHandler .word __tx_HardfaultHandler .word MemManage_Handler .word BusFault_Handler @@ -20,7 +20,7 @@ _vectors: .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // .word __tx_DBGHandler .word 0 // Reserved - .word __tx_PendSVHandler + .word __tx_PendSVHandler .word __tx_SysTickHandler // Used by Threadx timer functionality .word __tx_BadHandler // Populate with user Interrupt handler .word __tx_BadHandler diff --git a/ports_module/cortex_m7/gnu/example_build/txm_module_preamble.S b/ports_module/cortex_m7/gnu/example_build/txm_module_preamble.S index ded31277..5f663569 100644 --- a/ports_module/cortex_m7/gnu/example_build/txm_module_preamble.S +++ b/ports_module/cortex_m7/gnu/example_build/txm_module_preamble.S @@ -33,7 +33,7 @@ __txm_module_preamble: // 1 -> User mode execution .dc.l _txm_module_thread_shell_entry - . - 0 // Module Shell Entry Point .dc.l demo_module_start - . - 0 // Module Start Thread Entry Point - .dc.l 0 // Module Stop Thread Entry Point + .dc.l 0 // Module Stop Thread Entry Point .dc.l 1 // Module Start/Stop Thread Priority .dc.l 1024 // Module Start/Stop Thread Stack Size .dc.l _txm_module_callback_request_thread_entry - . - 0 // Module Callback Thread Entry diff --git a/ports_module/cortex_m7/gnu/inc/tx_port.h b/ports_module/cortex_m7/gnu/inc/tx_port.h index ef0142e7..eed637a1 100644 --- a/ports_module/cortex_m7/gnu/inc/tx_port.h +++ b/ports_module/cortex_m7/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,15 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -243,7 +235,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -376,7 +368,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -535,7 +527,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #else #error "Compiler not supported." #endif @@ -719,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M7 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m7/gnu/inc/txm_module_port.h b/ports_module/cortex_m7/gnu/inc/txm_module_port.h index 187259f5..0c851699 100644 --- a/ports_module/cortex_m7/gnu/inc/txm_module_port.h +++ b/ports_module/cortex_m7/gnu/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,24 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* 07-29-2022 Scott Larson Enabled user-defined and */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Configure heap size, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Set default values for RBAR, */ -/* unify this file for all */ -/* compilers, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -463,6 +446,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M7 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M7 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m7/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m7/gnu/module_lib/src/txm_module_thread_shell_entry.c index 01f7c7c5..3eb08b2b 100644 --- a/ports_module/cortex_m7/gnu/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m7/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ _gcc_setup(thread_info -> txm_module_thread_entry_info_code_base_address); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_restore.S index 57b18cf6..63895928 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,14 +62,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_save.S index d118c5bd..96df9ac5 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_control.S index 62301c14..5778d8d4 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_disable.S index f74a3748..19f6f854 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_restore.S index f4be7eba..25f1aac3 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_schedule.S index 46013061..571af2ee 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,23 +68,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Fixed predefined macro name, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, optional */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_stack_build.S index 0c72a44f..d0e2eaf3 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S index 4987b047..ce5a3f46 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,14 +60,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m7/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m7/gnu/module_manager/src/tx_timer_interrupt.S index d9477dea..6cc18b25 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_m7/gnu/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,17 +71,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 03-08-2023 Scott Larson Include tx_user.h, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c index c27e2255..3256d0b6 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 32. */ if(size <= 32) return 32; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c index 57e04f4a..804d701f 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Update defines, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -114,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -124,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -224,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -234,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -246,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c index 1589e608..12435ad5 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c index 605f50e4..ea010233 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index 4d924b37..5f444833 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -94,16 +95,6 @@ const ULONG txm_module_default_mpu_registers[32] = /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Changed from lookup table to */ -/* calculation and check for */ -/* minumum block size, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { diff --git a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s index b6c11663..44b86df5 100644 --- a/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,13 +55,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_m7/iar/example_build/cstartup_M.s b/ports_module/cortex_m7/iar/example_build/cstartup_M.s index 75d9369b..d1c5aa3e 100644 --- a/ports_module/cortex_m7/iar/example_build/cstartup_M.s +++ b/ports_module/cortex_m7/iar/example_build/cstartup_M.s @@ -2,16 +2,16 @@ PUBLIC __vector_table SECTION .text:CODE:REORDER(1) - + ;; Keep vector table even if it's not referenced REQUIRE __vector_table - + THUMB - + ;; Forward declaration of sections. SECTION CSTACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) - + DATA __vector_table diff --git a/ports_module/cortex_m7/iar/example_build/sample_threadx.c b/ports_module/cortex_m7/iar/example_build/sample_threadx.c index 9a626828..f1f4cb87 100644 --- a/ports_module/cortex_m7/iar/example_build/sample_threadx.c +++ b/ports_module/cortex_m7/iar/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete description of this demonstration. */ @@ -65,7 +65,7 @@ void thread_6_and_7_entry(ULONG thread_input); int main() { - + /* Please refer to Chapter 6 of the ThreadX User Guide for a complete description of this demonstration. */ @@ -93,41 +93,41 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -135,23 +135,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -254,11 +254,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -317,7 +317,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -370,7 +370,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_m7/iar/example_build/sample_threadx_module.c b/ports_module/cortex_m7/iar/example_build/sample_threadx_module.c index 34b97d86..7e561048 100644 --- a/ports_module/cortex_m7/iar/example_build/sample_threadx_module.c +++ b/ports_module/cortex_m7/iar/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -101,7 +101,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -117,7 +117,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -129,42 +129,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -172,23 +172,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -233,7 +233,7 @@ void thread_0_entry(ULONG thread_input) UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -243,7 +243,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -291,18 +291,18 @@ UINT status; { /* Test external memory sharing. */ *(ULONG *)0x90000000 = 0xABABABAB; - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -361,7 +361,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -414,7 +414,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_m7/iar/example_build/sample_threadx_module.icf b/ports_module/cortex_m7/iar/example_build/sample_threadx_module.icf index bffaf30d..9b98d2de 100644 --- a/ports_module/cortex_m7/iar/example_build/sample_threadx_module.icf +++ b/ports_module/cortex_m7/iar/example_build/sample_threadx_module.icf @@ -26,11 +26,11 @@ define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; initialize by copy { readwrite }; do not initialize { section .noinit }; -define movable block ROPI with alignment = 4, fixed order -{ +define movable block ROPI with alignment = 4, fixed order +{ ro object txm_module_preamble.o, - ro, - ro data + ro, + ro data }; define movable block RWPI with alignment = 8, fixed order, static base diff --git a/ports_module/cortex_m7/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m7/iar/example_build/sample_threadx_module_manager.c index de3999d9..9fc56315 100644 --- a/ports_module/cortex_m7/iar/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_m7/iar/example_build/sample_threadx_module_manager.c @@ -53,8 +53,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -74,22 +74,22 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x080F0000); - + /* Enable 128 byte read/write shared memory region at 0x90000000. */ txm_module_manager_external_memory_enable(&my_module, (void *) 0x90000000, 128, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); @@ -98,7 +98,7 @@ void module_manager_entry(ULONG thread_input) /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { diff --git a/ports_module/cortex_m7/iar/example_build/startup.s b/ports_module/cortex_m7/iar/example_build/startup.s index b1d725f7..a866a4cd 100644 --- a/ports_module/cortex_m7/iar/example_build/startup.s +++ b/ports_module/cortex_m7/iar/example_build/startup.s @@ -7,14 +7,14 @@ ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR +;* - Set the vector table entries with the exceptions ISR ;* address. ;* - Branches to main in the C library (which eventually ;* calls main()). ;* After Reset the Cortex-M7 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** -;* +;* ;* Redistribution and use in source and binary forms, with or without modification, ;* are permitted provided that the following conditions are met: ;* 1. Redistributions of source code must retain the above copyright notice, @@ -36,7 +36,7 @@ ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;* +;* ;******************************************************************************* ; ; @@ -87,86 +87,86 @@ __vector_table DCD SysTick_Handler ; SysTick Handler ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDMMC1_IRQHandler ; SDMMC1 - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved DCD RNG_IRQHandler ; Rng DCD FPU_IRQHandler ; FPU DCD UART7_IRQHandler ; UART7 @@ -182,8 +182,8 @@ __vector_table DCD QUADSPI_IRQHandler ; QUADSPI DCD LPTIM1_IRQHandler ; LPTIM1 DCD CEC_IRQHandler ; HDMI_CEC - DCD I2C4_EV_IRQHandler ; I2C4 Event - DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error DCD SPDIF_RX_IRQHandler ; SPDIF_RX ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; @@ -244,47 +244,47 @@ SysTick_Handler PUBWEAK WWDG_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_IRQHandler +WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -PVD_IRQHandler +PVD_IRQHandler B PVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FLASH_IRQHandler +FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -RCC_IRQHandler +RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler +EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler +EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler +EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler @@ -293,438 +293,438 @@ EXTI3_IRQHandler B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ADC_IRQHandler +ADC_IRQHandler B ADC_IRQHandler PUBWEAK CAN1_TX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_TX_IRQHandler B CAN1_TX_IRQHandler PUBWEAK CAN1_RX0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX0_IRQHandler B CAN1_RX0_IRQHandler PUBWEAK CAN1_RX1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX1_IRQHandler B CAN1_RX1_IRQHandler PUBWEAK CAN1_SCE_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN1_SCE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_SCE_IRQHandler B CAN1_SCE_IRQHandler PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_TIM9_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_TIM9_IRQHandler B TIM1_BRK_TIM9_IRQHandler PUBWEAK TIM1_UP_TIM10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_TIM10_IRQHandler B TIM1_UP_TIM10_IRQHandler PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_TIM11_IRQHandler B TIM1_TRG_COM_TIM11_IRQHandler - + PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM2_IRQHandler +TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM3_IRQHandler +TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM4_IRQHandler +TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler +SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler +SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler +USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler +USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART3_IRQHandler +USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_WKUP_IRQHandler B OTG_FS_WKUP_IRQHandler - + PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FMC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler +FMC_IRQHandler B FMC_IRQHandler PUBWEAK SDMMC1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC1_IRQHandler +SDMMC1_IRQHandler B SDMMC1_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM5_IRQHandler +TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI3_IRQHandler +SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler +UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART5_IRQHandler +UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ETH_IRQHandler +ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK CAN2_TX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN2_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN2_TX_IRQHandler B CAN2_TX_IRQHandler PUBWEAK CAN2_RX0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN2_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN2_RX0_IRQHandler B CAN2_RX0_IRQHandler PUBWEAK CAN2_RX1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN2_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN2_RX1_IRQHandler B CAN2_RX1_IRQHandler PUBWEAK CAN2_SCE_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN2_SCE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN2_SCE_IRQHandler B CAN2_SCE_IRQHandler PUBWEAK OTG_FS_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_IRQHandler +OTG_FS_IRQHandler B OTG_FS_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART6_IRQHandler +USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_IRQHandler +OTG_HS_IRQHandler B OTG_HS_IRQHandler PUBWEAK DCMI_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -DCMI_IRQHandler +DCMI_IRQHandler B DCMI_IRQHandler PUBWEAK RNG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler B RNG_IRQHandler PUBWEAK FPU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler B FPU_IRQHandler PUBWEAK UART7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART7_IRQHandler - B UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler PUBWEAK UART8_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler B UART8_IRQHandler - + PUBWEAK SPI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) + SECTION .text:CODE:NOROOT:REORDER(1) SPI4_IRQHandler - B SPI4_IRQHandler + B SPI4_IRQHandler PUBWEAK SPI5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI5_IRQHandler - B SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler PUBWEAK SPI6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI6_IRQHandler - B SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler PUBWEAK SAI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI1_IRQHandler - B SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler PUBWEAK LTDC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_IRQHandler - B LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler PUBWEAK LTDC_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_ER_IRQHandler - B LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler PUBWEAK DMA2D_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2D_IRQHandler - B DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler PUBWEAK SAI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI2_IRQHandler - B SAI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_IRQHandler + B SAI2_IRQHandler PUBWEAK QUADSPI_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -QUADSPI_IRQHandler - B QUADSPI_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + PUBWEAK LPTIM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM1_IRQHandler - B LPTIM1_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + PUBWEAK CEC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CEC_IRQHandler - B CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler PUBWEAK I2C4_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_EV_IRQHandler - B I2C4_EV_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + PUBWEAK I2C4_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_ER_IRQHandler - B I2C4_ER_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + PUBWEAK SPDIF_RX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPDIF_RX_IRQHandler - B SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler END /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/ports_module/cortex_m7/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_m7/iar/example_build/tx_initialize_low_level.s index 9789421b..2df2d19f 100644 --- a/ports_module/cortex_m7/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_m7/iar/example_build/tx_initialize_low_level.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -29,11 +30,11 @@ SYSTEM_CLOCK EQU 25000000 SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) - + RSEG FREE_MEM:DATA PUBLIC __tx_free_memory_start __tx_free_memory_start - DS32 4 + DS32 4 SECTION `.text`:CODE:NOROOT(2) THUMB @@ -70,15 +71,6 @@ __tx_free_memory_start /* CALLED BY */ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 11-09-2020 Scott Larson Modified comment(s), */ -/* resulting in version 6.1.2 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { @@ -86,7 +78,7 @@ __tx_free_memory_start _tx_initialize_low_level: /* Disable interrupts during ThreadX initialization. */ - + CPSID i /* Set base of available memory to end of non-initialised RAM area. */ @@ -96,7 +88,7 @@ _tx_initialize_low_level: STR r1, [r0] // Setup first unused memory pointer /* Setup Vector Table Offset Register. */ - + MOV r0, #0xE000E000 // Build address of NVIC registers LDR r1, =__vector_table // Pickup address of vector table STR r1, [r0, #0xD08] // Set vector table address @@ -106,7 +98,7 @@ _tx_initialize_low_level: // LDR r0, =0xE0001000 // Build address of DWT register // LDR r1, [r0] // Pickup the current value // ORR r1, r1, #1 // Set the CYCCNTENA bit -// STR r1, [r0] // Enable the cycle count register +// STR r1, [r0] // Enable the cycle count register /* Set system stack pointer from vector value. */ @@ -138,7 +130,7 @@ _tx_initialize_low_level: /* Return to caller. */ - BX lr + BX lr // } PUBLIC SysTick_Handler diff --git a/ports_module/cortex_m7/iar/inc/tx_port.h b/ports_module/cortex_m7/iar/inc/tx_port.h index ef0142e7..eed637a1 100644 --- a/ports_module/cortex_m7/iar/inc/tx_port.h +++ b/ports_module/cortex_m7/iar/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -45,15 +46,6 @@ /* This file replaces the previous Cortex-M3/M4/M7 files. It unifies */ /* the ARMv7-M architecture and compilers into one common file. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Modified comments and added */ -/* volatile to registers, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -243,7 +235,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_EXTENSION_3 #else #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long long tx_thread_execution_time_last_start; + unsigned long long tx_thread_execution_time_last_start; #endif @@ -376,7 +368,7 @@ void _tx_vfp_access(void); /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating - this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush the lazy FPU save, then restore the CONTROL.FPCA state. */ #ifndef TX_MISRA_ENABLE @@ -535,7 +527,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); #elif defined(__GNUC__) /* GCC and AC6 Compiler */ #define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ - __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); #else #error "Compiler not supported." #endif @@ -719,7 +711,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-M7 Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-M7 Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m7/iar/inc/txm_module_port.h b/ports_module/cortex_m7/iar/inc/txm_module_port.h index 187259f5..0c851699 100644 --- a/ports_module/cortex_m7/iar/inc/txm_module_port.h +++ b/ports_module/cortex_m7/iar/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,24 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 01-31-2022 Scott Larson Modified comments and made */ -/* heap user-configurable, */ -/* resulting in version 6.1.10 */ -/* 07-29-2022 Scott Larson Enabled user-defined and */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Configure heap size, */ -/* resulting in version 6.2.0 */ -/* 03-08-2023 Scott Larson Set default values for RBAR, */ -/* unify this file for all */ -/* compilers, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -463,6 +446,6 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M7 Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-M7 Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_m7/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m7/iar/module_lib/src/txm_module_thread_shell_entry.c index 8d024757..c858fb2b 100644 --- a/ports_module/cortex_m7/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_m7/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID __iar_data_init3(VOID); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the C environment. */ __iar_data_init3(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_iar.c b/ports_module/cortex_m7/iar/module_manager/src/tx_iar.c index ee47f10f..238b485e 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_iar.c +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_iar.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_misra.s b/ports_module/cortex_m7/iar/module_manager/src/tx_misra.s index 72aac789..c79133f5 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_misra.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_misra.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -116,7 +117,7 @@ SECTION `.data`:DATA:REORDER:NOROOT(2) DATA -// 51 CHAR _tx_version_id[100] = "Copyright (c) 2024 Microsoft Corporation. * ThreadX 6.1 MISRA C Compliant *"; +// 51 CHAR _tx_version_id[100] = "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX 6.1 MISRA C Compliant *"; _tx_version_id: DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H @@ -703,7 +704,7 @@ _tx_misra_control_get: MRS R0, CONTROL BX LR // return - + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -718,7 +719,7 @@ _tx_misra_control_set: MSR CONTROL, R0 BX LR // return - + #ifdef __ARMVFP__ /***********************************************************************************************/ @@ -735,8 +736,8 @@ _tx_misra_fpccr_get: LDR r0, =0xE000EF34 // Build FPCCR address LDR r0, [r0] // Load FPCCR value BX LR // return - - + + /***********************************************************************************************/ /***********************************************************************************************/ /** */ @@ -750,10 +751,10 @@ _tx_misra_fpccr_get: _tx_misra_vfp_touch: vmov.f32 s0, s0 BX LR // return - + #endif - - + + SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2) SECTION_TYPE SHT_PROGBITS, 0 DATA diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_restore.s index 52c33328..ccc96ede 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_save.s index f3bca66a..dcf510a6 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_control.s index 8950acd5..f28d5bde 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_disable.s index 76e09a1c..36aaaf0a 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(VOID) // { diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_restore.s index 57102c6d..55aa1d62 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT previous_posture) // { diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s index 1f9229ca..d38c8df7 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,22 +64,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 04-25-2022 Scott Larson Optimized MPU configuration, */ -/* added BASEPRI support, */ -/* resulting in version 6.1.11 */ -/* 07-29-2022 Scott Larson Removed the code path to skip */ -/* MPU reloading, optional */ -/* default MPU settings, */ -/* resulting in version 6.1.12 */ -/* 10-31-2022 Scott Larson Added low power support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_stack_build.s index 04b1479c..2f7ac3ab 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s index 51c85491..0cef80c6 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_module/cortex_m7/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m7/iar/module_manager/src/tx_timer_interrupt.s index 1da9431e..775c0a45 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_m7/iar/module_manager/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,18 +72,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ -/* 01-31-2022 Scott Larson Modified comment(s), added */ -/* TX_NO_TIMER support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Included tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_alignment_adjust.c index c27e2255..3256d0b6 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,23 +57,17 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 32. */ if(size <= 32) return 32; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,7 +77,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,7 +170,7 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ *code_size = local_code_size; *code_alignment = local_code_alignment; @@ -299,15 +294,15 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { @@ -324,7 +319,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { @@ -429,7 +424,7 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) diff --git a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_external_memory_enable.c index 57e04f4a..804d701f 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,14 +66,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Update defines, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -114,7 +107,7 @@ ULONG attributes_check = 0; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -124,71 +117,71 @@ ULONG attributes_check = 0; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MANAGER_MPU_SHARED_ENTRIES) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* No more entries available. */ return(TX_NO_MEMORY); } - + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ - + /* Pick up index into shared memory entries. */ shared_index = TXM_MODULE_MANAGER_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; - + /* Save address register with address, MPU region, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); - + /* Calculate the subregion bits. */ srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Generate SRD, size, and enable attributes. */ size_register = srd_bits | (region_size << 1) | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; - + /* Check for optional write attribute. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Save attribute-size register. */ module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; - + /* Increment counter. */ module_instance -> txm_module_instance_shared_memory_count++; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); - + #else ULONG block_size; @@ -224,7 +217,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -234,7 +227,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble shared mem and mem protection property bits are set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -246,49 +239,49 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ - + block_size = _txm_power_of_two_block_size(length); address = (ULONG) start_address; if(address != (address & ~(block_size - 1))) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* At this point, we have a valid address and block size. Set up MPU registers. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_address = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | TXM_MPU_VALID_BIT; - + /* Calculate the region size. */ region_size = _txm_module_manager_region_size_get(block_size); /* Calculate the subregion bits. */ subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) { attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; } - + /* Build register with attributes. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_REGION].txm_module_mpu_region_attribute_size = (region_size << 1) | subregion_bits | attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL | TXM_ENABLE_REGION; - + /* Keep track of shared memory address and length in module instance. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Recalculate MPU settings. */ _txm_module_manager_mm_register_setup(module_instance); - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); diff --git a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index 1589e608..12435ad5 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index 605f50e4..ea010233 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c index 4d924b37..5f444833 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -94,16 +95,6 @@ const ULONG txm_module_default_mpu_registers[32] = /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* 03-08-2023 Scott Larson Changed from lookup table to */ -/* calculation and check for */ -/* minumum block size, */ -/* resulting in version 6.2.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { diff --git a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_thread_stack_build.s index 2893050b..3ee7dd32 100644 --- a/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_m7/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx/.cproject b/ports_module/cortex_r4/ac6/example_build/sample_threadx/.cproject index 71818fd9..4ceb8982 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx/.cproject +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx/.cproject @@ -1,170 +1,170 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.c index 4a677059..f8e0cecc 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.c +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -58,7 +58,7 @@ void thread_6_and_7_entry(ULONG thread_input); int main() { - + /* Setup the timer. */ timer_init(); @@ -85,42 +85,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -128,23 +128,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -247,11 +247,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -310,7 +310,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -363,7 +363,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex_r4/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 8732358f..44591770 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -103,12 +104,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_initialize_low_level(VOID) { */ diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/.cproject b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/.cproject index ee2634f6..68b87b4b 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/.cproject +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/.cproject @@ -1,184 +1,184 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/sample_threadx_module.c index feb9fb84..74eeb454 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/sample_threadx_module.c +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -102,7 +102,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MMU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void *) &thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void *) &thread_1, sizeof(TX_THREAD)); @@ -118,7 +118,7 @@ CHAR *pointer; txm_module_object_allocate((void *) &event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void *) &byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void *) &block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -130,14 +130,14 @@ CHAR *pointer; /* Create the main thread. */ tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, @@ -157,14 +157,14 @@ CHAR *pointer; /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -173,7 +173,7 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ @@ -181,14 +181,14 @@ CHAR *pointer; /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -236,7 +236,7 @@ UINT status; /* Test external/shared memory. */ *(ULONG *) 0x08025000 = 0xdeadbeef; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -246,7 +246,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -298,11 +298,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -361,7 +361,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -414,7 +414,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/semihosting.c b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/semihosting.c index 29268630..80e5f04f 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/semihosting.c +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module/semihosting.c @@ -9,17 +9,17 @@ void use_no_semihosting(void) __asm(".global __use_no_semihosting\n\t"); } #endif - + char *$Sub$$_sys_command_string(char *cmd, int len) { return 0; } - + __attribute__((noreturn)) void $Sub$$_sys_exit(int return_code) { while(1); } - + __attribute__((noreturn)) int $Sub$$__raise(int signal, int type) { while(1); diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/.cproject index 71818fd9..4ceb8982 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/.cproject +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/.cproject @@ -1,170 +1,170 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/module_code.c b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/module_code.c index 6a92a2ac..78dc1538 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/module_code.c +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/module_code.c @@ -1,4 +1,4 @@ -/* +/* Input ELF file: sample_threadx_module.axf Output C Array file: module_code.c */ diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat index 926647b2..9eb35ca0 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat @@ -18,21 +18,21 @@ SDRAM 0x0 0x40000000 * (+RO-CODE) ; Application RO code (.text) * (+RO-DATA) ; Application RO data (.constdata) } - + IRQ_STACK +0 ALIGN 8 EMPTY 1024 {} - + FIQ_STACK +0 ALIGN 8 EMPTY 512 {} - + SVC_STACK +0 ALIGN 8 EMPTY 2048 {} - + SYS_STACK +0 ALIGN 8 EMPTY 2048 {} - + ABORT_STACK +0 ALIGN 8 EMPTY 2048 {} ; Application RW & ZI data (.data & .bss) DATA +0 0x100000 { - * (+RW,+ZI) + * (+RW,+ZI) } PERIPHERALS 0xA0000000 EMPTY 0x20000000 { }; Peripherals diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c index 99e8fa3e..2e683da2 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -47,7 +47,7 @@ VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) int main() { - + /* Setup the timer. */ timer_init(); @@ -60,8 +60,8 @@ int main() void tx_application_define(void *first_unused_memory) { - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - manager_stack, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + manager_stack, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); } @@ -72,7 +72,7 @@ void tx_application_define(void *first_unused_memory) void module_manager_entry(ULONG thread_input) { - + /* Initialize the module manager. */ txm_module_manager_initialize((VOID *) module_data_area, MODULE_DATA_SIZE); @@ -80,40 +80,40 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x00100000 /*module_code*/); - + /* Enable 128 byte read/write shared memory region at 0x08025000. */ txm_module_manager_external_memory_enable(&my_module, (void *) 0x08025000, 128, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(300); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); /* Load the module that is already there. */ txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x00100000); - + /* Set maximum module priority to 5. */ txm_module_manager_maximum_module_priority_set(&my_module, 5); - /* In this demo, module threads 0 and 5 will not start because their priorities + /* In this demo, module threads 0 and 5 will not start because their priorities * are higher than 5. */ - + /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/startup.S b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/startup.S index cd6479d3..bbd85a4c 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/startup.S +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/startup.S @@ -3,7 +3,7 @@ // // Copyright (c) 2006-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. //---------------------------------------------------------------- @@ -130,7 +130,7 @@ Reset_Handler: CPS #SVC_MODE // Build SVC mode CPSR LDR sp, =Image$$SVC_STACK$$ZI$$Limit // Setup SVC stack pointer - + //---------------------------------------------------------------- // TCM Configuration @@ -196,7 +196,7 @@ Reset_Handler: // Enable Branch prediction //---------------------------------------------------------------- -// In the Cortex-R4, the Z-bit of the SCTLR does not control the program flow prediction. +// In the Cortex-R4, the Z-bit of the SCTLR does not control the program flow prediction. // Some control bits in the ACTLR control the program flow and prefetch features instead. // These are enabled by default, but are shown here for completeness. diff --git a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S index 8732358f..44591770 100644 --- a/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S +++ b/ports_module/cortex_r4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -103,12 +104,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_initialize_low_level(VOID) { */ diff --git a/ports_module/cortex_r4/ac6/example_build/tx/.cproject b/ports_module/cortex_r4/ac6/example_build/tx/.cproject index 9dfee32b..e97c3b82 100644 --- a/ports_module/cortex_r4/ac6/example_build/tx/.cproject +++ b/ports_module/cortex_r4/ac6/example_build/tx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_r4/ac6/example_build/txm/.cproject b/ports_module/cortex_r4/ac6/example_build/txm/.cproject index f9012e60..1e87101d 100644 --- a/ports_module/cortex_r4/ac6/example_build/txm/.cproject +++ b/ports_module/cortex_r4/ac6/example_build/txm/.cproject @@ -1,176 +1,176 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_module/cortex_r4/ac6/inc/tx_port.h b/ports_module/cortex_r4/ac6/inc/tx_port.h index 33b7e737..2b334d2e 100644 --- a/ports_module/cortex_r4/ac6/inc/tx_port.h +++ b/ports_module/cortex_r4/ac6/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Cortex-R4/AC6 */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-R4/AC6 */ /* 6.1 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -78,7 +70,7 @@ #include -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -114,12 +106,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -129,8 +121,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -177,7 +169,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -189,11 +181,11 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ VOID *tx_thread_module_instance_ptr; \ VOID *tx_thread_module_entry_info_ptr; \ @@ -207,7 +199,7 @@ typedef unsigned short USHORT; VOID *tx_thread_module_stack_end; \ ULONG tx_thread_module_stack_size; \ VOID *tx_thread_module_reserved; -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -225,11 +217,11 @@ typedef unsigned short USHORT; VOID (*tx_timer_module_expiration_function)(ULONG id); -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -237,8 +229,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -265,21 +257,21 @@ typedef unsigned short USHORT; #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef __thumb #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (ULONG) __clz((unsigned int) m); \ - b = 31 - b; + b = 31 - b; #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -299,7 +291,7 @@ typedef unsigned short USHORT; { \ __enable_irq(); \ __enable_fiq(); \ - } + } #else @@ -308,7 +300,7 @@ typedef unsigned short USHORT; #define TX_RESTORE if (!interrupt_save_disabled) \ { \ __enable_irq(); \ - } + } #endif #else @@ -344,8 +336,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-R4/AC6 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R4/AC6 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex_r4/ac6/inc/txm_module_port.h b/ports_module/cortex_r4/ac6/inc/txm_module_port.h index 3e6ec271..141a307b 100644 --- a/ports_module/cortex_r4/ac6/inc/txm_module_port.h +++ b/ports_module/cortex_r4/ac6/inc/txm_module_port.h @@ -1,52 +1,47 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ -/**************************************************************************/ -/* */ -/* APPLICATION INTERFACE DEFINITION RELEASE */ -/* */ -/* txm_module_port.h Cortex-R4/MPU/ARM */ +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-R4/MPU/ARM */ /* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This file defines the basic module constants, interface structures, */ -/* and function prototypes. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ /* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H #define TXM_MODULE_PORT_H -/* It is assumed that the base ThreadX tx_port.h file has been modified to add the +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the following extensions to the ThreadX thread control block (this code should replace the corresponding macro define in tx_port.h): @@ -89,9 +84,9 @@ The following extensions must also be defined in tx_port.h: #define TXM_MODULE_KERNEL_STACK_SIZE 1024 #endif -/* Defined, these options allows a memory-protected module to access kernel objects. - For example, when a module needs to send/receive a message from a kernel queue. - This does not allow modules to create or delete objects outside of their memory. +/* Defined, these options allows a memory-protected module to access kernel objects. + For example, when a module needs to send/receive a message from a kernel queue. + This does not allow modules to create or delete objects outside of their memory. Default setting for these values is undefined. */ /* #define TXM_MODULE_ENABLE_KERNEL_BLOCK_POOL_ACCESS */ /* #define TXM_MODULE_ENABLE_KERNEL_BYTE_POOL_ACCESS */ @@ -166,7 +161,7 @@ The following extensions must also be defined in tx_port.h: #define INLINE_DECLARE inline /* Define the number of MPU entries assigned to the code and data sections. - On Cortex-R parts, there are 12 total entries. ThreadX uses one for access + On Cortex-R parts, there are 12 total entries. ThreadX uses one for access to the kernel entry function, thus 11 remain for code and data protection. */ #define TXM_MODULE_MPU_TOTAL_ENTRIES 12 #define TXM_MODULE_MPU_CODE_ENTRIES 4 @@ -234,7 +229,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; /* Define the macro to check the stack available in dispatch. */ -#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE +#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE /* Define the macro to check the module properties. */ @@ -248,7 +243,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT { \ _tx_mutex_put(&_txm_module_manager_mutex); \ return(TXM_MODULE_INVALID_PROPERTIES); \ - } + } /* Define the macro to check the code alignment. */ @@ -359,7 +354,7 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-R4/MPU/ARM Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-R4/MPU/ARM Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_r4/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_r4/ac6/module_lib/src/txm_module_initialize.S index 051f6f66..f4a16554 100644 --- a/ports_module/cortex_r4/ac6/module_lib/src/txm_module_initialize.S +++ b/ports_module/cortex_r4/ac6/module_lib/src/txm_module_initialize.S @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Module */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -43,43 +43,37 @@ .eabi_attribute Tag_ABI_PCS_R9_use, 1 .eabi_attribute Tag_ABI_PCS_RW_data, 2 .arm -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_initialize Cortex-R4/MPU/ARM */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_initialize Cortex-R4/MPU/ARM */ /* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function initializes the module c runtime. */ -/* */ -/* INPUT */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes the module c runtime. */ +/* */ +/* INPUT */ +/* */ /* heap_base Pointer to bottom of heap */ /* heap_top Pointer to top of heap */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ /* __scatterload Initialize C runtime */ /* __rt_lib_init Initialize heap */ -/* */ -/* CALLED BY */ -/* */ -/* _txm_module_thread_shell_entry Start module thread */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* CALLED BY */ +/* */ +/* _txm_module_thread_shell_entry Start module thread */ /* */ /**************************************************************************/ /* VOID _txm_module_initialize(VOID *heap_base, VOID *heap_top) */ @@ -88,7 +82,7 @@ _txm_module_initialize: PUSH {r0-r12,lr} // Save dregs and LR - + B __scatterload // Call ARM func to initialize variables diff --git a/ports_module/cortex_r4/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_r4/ac6/module_lib/src/txm_module_thread_shell_entry.c index b2673994..ec0d81c6 100644 --- a/ports_module/cortex_r4/ac6/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_r4/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -88,12 +89,6 @@ extern VOID _txm_module_initialize(VOID *heap_base, VOID *heap_top); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_context_restore.S index f87614c4..eaf3be37 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_context_restore.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,12 @@ #endif .text .eabi_attribute Tag_ABI_align_preserved, 1 - + /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_context_restore Cortex-R4/MPU/ARM */ +/* _tx_thread_context_restore Cortex-R4/MPU/ARM */ /* 6.1 */ /* AUTHOR */ /* */ @@ -89,12 +90,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_context_restore(VOID) { */ @@ -186,10 +181,10 @@ __tx_thread_preempt_restore: STR r1, [sp, #-4]! // Save point of interrupt STMDB sp!, {r4-r12, lr} // Save registers MOV r4, r3 // Save SPSR in r4 - + CPS #IRQ_MODE // Switch back to IRQ mode LDMIA sp!, {r0-r3} // Recover r0-r3 - + CPS #SYS_MODE // Switch to SYS mode to save remaining context on thread stack STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_context_save.S index 696dc985..68951b08 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_context_save.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -76,12 +77,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_context_save(VOID) { */ diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_context_restore.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_context_restore.S index 94c20b72..7fbcc84a 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_context_restore.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -88,12 +89,6 @@ /* */ /* FIQ ISR Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_fiq_context_restore(VOID) */ /* { */ @@ -186,15 +181,15 @@ __tx_thread_fiq_preempt_restore: LDMIA sp!, {r3, lr} // Recover temporarily saved registers MOV r1, lr // Save lr (point of interrupt) - + CPS #SVC_MODE // Switch to SVC mode to save context on thread stack STR r1, [sp, #-4]! // Save point of interrupt STMDB sp!, {r4-r12, lr} // Save upper half of registers MOV r4, r3 // Save SPSR in r4 - + CPS #FIQ_MODE // Switch back to FIQ mode LDMIA sp!, {r0-r3} // Recover r0-r3 - + CPS #SVC_MODE // Switch to SVC mode to save remaining context on thread stack STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_context_save.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_context_save.S index 1d85abe5..3c1333b3 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_context_save.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -76,12 +77,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_fiq_context_save(VOID) */ /* { */ @@ -90,7 +85,7 @@ .type _tx_thread_fiq_context_save, "function" _tx_thread_fiq_context_save: - /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked out, we are in IRQ mode, and all registers are intact. */ /* Check for a nested interrupt condition. */ diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_nesting_end.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_nesting_end.S index df8a4633..5abbdddf 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_nesting_end.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -77,12 +78,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_fiq_nesting_end(VOID) */ /* { */ @@ -90,13 +85,13 @@ .type _tx_thread_fiq_nesting_end, "function" _tx_thread_fiq_nesting_end: MOV r3, lr // Save ISR return address - + #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if // Disable IRQ and FIQ interrupts #else CPSID i // Disable IRQ interrupts #endif - + LDMIA sp!, {r1, lr} // Pickup saved lr (and r1 throw-away for // 8-byte alignment logic) CPS #FIQ_MODE // Switch back to FIQ mode diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_nesting_start.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_nesting_start.S index f26d9a0c..73564d78 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_nesting_start.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_fiq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,12 +75,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_fiq_nesting_start(VOID) */ /* { */ diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_interrupt_control.S index 11ab4e4f..83aa06c4 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_interrupt_control.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -73,12 +74,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_control(UINT new_posture) */ /* { */ diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_interrupt_disable.S index cd7476a6..d605e034 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_interrupt_disable.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,12 +66,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_disable(void) */ /* { */ diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_interrupt_restore.S index 8e966de6..f9315d7f 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_interrupt_restore.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,12 +67,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_restore(UINT old_posture) */ /* { */ diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_irq_nesting_end.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_irq_nesting_end.S index cf8e0ac1..664e02c5 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_irq_nesting_end.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_irq_nesting_end.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -77,12 +78,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_irq_nesting_end(VOID) */ /* { */ @@ -96,7 +91,7 @@ _tx_thread_irq_nesting_end: #else CPSID i // Disable IRQ interrupts #endif - + LDMIA sp!, {r1, lr} // Pickup saved lr (and r1 throw-away for // 8-byte alignment logic) CPS #IRQ_MODE // Switch back to IRQ mode diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_irq_nesting_start.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_irq_nesting_start.S index b3ebe405..1d50b484 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_irq_nesting_start.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_irq_nesting_start.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -74,12 +75,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_irq_nesting_start(VOID) */ /* { */ diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_schedule.S index 58b94d01..38792e97 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -82,12 +83,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_schedule(VOID) */ /* { */ diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_stack_build.S index eb8e9a90..8f122083 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_stack_build.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -78,12 +79,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) */ /* { */ diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_system_return.S index 2c5f11d6..048b4525 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_system_return.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -77,12 +78,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_system_return(VOID) */ /* { */ diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_vectored_context_save.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_vectored_context_save.S index de49cc0d..dbb40aba 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_vectored_context_save.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_thread_vectored_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -75,12 +76,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_vectored_context_save(VOID) */ /* { */ diff --git a/ports_module/cortex_r4/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_r4/ac6/module_manager/src/tx_timer_interrupt.S index d48313ef..8c3abf90 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/tx_timer_interrupt.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -84,12 +85,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _tx_timer_interrupt(VOID) */ /* { */ diff --git a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c index 4572adab..94a6cfdd 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-R */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) { diff --git a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c index a57590fa..2bd00d08 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,12 +65,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, diff --git a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c index 9962938d..1844c760 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { diff --git a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c index d9ff9c7a..28439101 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,12 +67,6 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { diff --git a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index 8c9b8752..ea4ce4ff 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { @@ -519,7 +514,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S index 4f9daad8..26bf9d51 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,12 +60,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ /* VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { */ diff --git a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_user_mode_entry.S b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_user_mode_entry.S index 7f23c553..f36ee23f 100644 --- a/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_user_mode_entry.S +++ b/ports_module/cortex_r4/ac6/module_manager/src/txm_module_manager_user_mode_entry.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -22,7 +23,7 @@ .global _txm_module_manager_kernel_dispatch .global _txm_system_mode_enter .global _txm_system_mode_exit - + /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -54,12 +55,6 @@ /* */ /* Modules in user mode */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ .text .align 12 diff --git a/ports_module/cortex_r4/iar/example_build/cstartup.s b/ports_module/cortex_r4/iar/example_build/cstartup.s index 6953baa8..c01a67cb 100644 --- a/ports_module/cortex_r4/iar/example_build/cstartup.s +++ b/ports_module/cortex_r4/iar/example_build/cstartup.s @@ -136,19 +136,19 @@ __iar_program_start: MSR cpsr_c, r0 ; Change the mode LDR r1, =SFE(FIQ_STACK) ; End of FIQ_STACK BIC sp,r1,#0x7 ; Make sure SP is 8 aligned - + ;; Set up the SVC stack pointer. CPS #SVC_MODE LDR r1, =SFE(SVC_STACK) ; End of SVC_STACK BIC sp,r1,#0x7 ; Make sure SP is 8 aligned - + ;; Set up the abort stack pointer. CPS #ABT_MODE LDR r1, =SFE(ABT_STACK) ; End of ABT_STACK BIC sp,r1,#0x7 ; Make sure SP is 8 aligned - + ;; Set up the normal stack pointer. BIC r0 ,r0, #MODE_MSK ; Clear the mode bits diff --git a/ports_module/cortex_r4/iar/example_build/sample_threadx.c b/ports_module/cortex_r4/iar/example_build/sample_threadx.c index 983109cc..ca92ff86 100644 --- a/ports_module/cortex_r4/iar/example_build/sample_threadx.c +++ b/ports_module/cortex_r4/iar/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -63,7 +63,7 @@ void thread_6_and_7_entry(ULONG thread_input); int main() { - + /* Enter the ThreadX kernel. */ tx_kernel_enter(); } @@ -87,42 +87,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -130,23 +130,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -249,11 +249,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -312,7 +312,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -365,7 +365,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_module/cortex_r4/iar/example_build/sample_threadx_module.c b/ports_module/cortex_r4/iar/example_build/sample_threadx_module.c index 203cbba2..d4f98a30 100644 --- a/ports_module/cortex_r4/iar/example_build/sample_threadx_module.c +++ b/ports_module/cortex_r4/iar/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -101,7 +101,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -117,7 +117,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -129,42 +129,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -172,23 +172,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -233,7 +233,7 @@ void thread_0_entry(ULONG thread_input) UINT status; - + /* This thread simply sits in while-forever-sleep loop. */ while(1) { @@ -243,7 +243,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -263,7 +263,7 @@ UINT status; /* This thread simply sends messages to a queue shared by thread 2. */ while(1) { - + /* Increment the thread counter. */ thread_1_counter++; @@ -289,18 +289,18 @@ UINT status; /* This thread retrieves messages placed on the queue by thread 1. */ while(1) { - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -354,12 +354,12 @@ ULONG actual_flags; /* This thread simply waits for an event in a forever loop. */ while(1) { - + /* Increment the thread counter. */ thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -412,7 +412,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/cortex_r4/iar/example_build/sample_threadx_module.icf b/ports_module/cortex_r4/iar/example_build/sample_threadx_module.icf index bed79adf..69c8f600 100644 --- a/ports_module/cortex_r4/iar/example_build/sample_threadx_module.icf +++ b/ports_module/cortex_r4/iar/example_build/sample_threadx_module.icf @@ -26,11 +26,11 @@ define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; initialize by copy { readwrite }; do not initialize { section .noinit }; -define movable block ROPI with alignment = 4, fixed order -{ +define movable block ROPI with alignment = 4, fixed order +{ ro object txm_module_preamble.o, - ro, - ro data + ro, + ro data }; define movable block RWPI with alignment = 8, fixed order, static base diff --git a/ports_module/cortex_r4/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex_r4/iar/example_build/sample_threadx_module_manager.c index 8c319878..a0ec49ea 100644 --- a/ports_module/cortex_r4/iar/example_build/sample_threadx_module_manager.c +++ b/ports_module/cortex_r4/iar/example_build/sample_threadx_module_manager.c @@ -40,7 +40,7 @@ VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) int main() { - + /* Enter the ThreadX kernel. */ tx_kernel_enter(); } @@ -50,8 +50,8 @@ int main() void tx_application_define(void *first_unused_memory) { - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - manager_stack, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + manager_stack, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); } @@ -62,7 +62,7 @@ void tx_application_define(void *first_unused_memory) void module_manager_entry(ULONG thread_input) { - + /* Initialize the module manager. */ txm_module_manager_initialize((VOID *) 0x08020000, 0x10000); @@ -70,35 +70,35 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x00100000); - + /* Enable 128 byte read/write shared memory region at 0x08025000. */ txm_module_manager_external_memory_enable(&my_module, (void *) 0x08025000, 128, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); /* Sleep for a while.... */ tx_thread_sleep(300); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); /* Load the module that is already there. */ txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x00100000); - + /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/cortex_r4/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_r4/iar/example_build/tx_initialize_low_level.s index b65b7a82..dd82541b 100644 --- a/ports_module/cortex_r4/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex_r4/iar/example_build/tx_initialize_low_level.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Initialize */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;#define TX_SOURCE_CODE @@ -55,7 +55,7 @@ THUMB_MASK DEFINE 0x20 ; Thumb bit (5) of CPSR/SPSR ; ; ; -;/* Define the FREE_MEM segment that will specify where free memory is +;/* Define the FREE_MEM segment that will specify where free memory is ; defined. This must also be located in at the end of other RAM segments ; in the linker control file. The value of this segment is what is passed ; to tx_application_define. */ @@ -68,45 +68,39 @@ __tx_free_memory_start ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level Cortex-R4/MPU/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-R4/MPU/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -117,7 +111,7 @@ __tx_free_memory_start _tx_initialize_low_level ; ; /****** NOTE ****** The IAR 4.11a and above releases call main in SYS mode. */ -; +; ; /* For modules, stay in SYS mode and disable interrupts. */ CPSID i ; @@ -133,7 +127,7 @@ _tx_initialize_low_level ; LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address STR r0, [r2, #0] ; Save first free memory address -; +; ; /* Setup Timer for periodic interrupts. */ ; ; /* Done, return to caller. */ @@ -166,17 +160,17 @@ IRQ_Handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_start @@ -191,7 +185,7 @@ __tx_irq_processing_return ; /* Application IRQ handlers can be called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ #ifdef TX_ENABLE_IRQ_NESTING BL _tx_thread_irq_nesting_end @@ -210,22 +204,22 @@ __tx_irq_processing_return ; /* Jump to context save to save system context. */ ; STMDB sp!, {r0-r3} ; Save some scratch registers ; MRS r0, SPSR ; Pickup saved SPSR -; SUB lr, lr, #4 ; Adjust point of interrupt +; SUB lr, lr, #4 ; Adjust point of interrupt ; STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; BL _tx_thread_vectored_context_save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. In +; interrupt, and all C scratch registers are available for use. In ; addition, IRQ interrupts may be re-enabled - with certain restrictions - ; if nested IRQ interrupts are desired. Interrupts may be re-enabled over -; small code sequences where lr is saved before enabling interrupts and +; small code sequences where lr is saved before enabling interrupts and ; restored after interrupts are again disabled. */ ; -; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start ; from IRQ mode with interrupts disabled. This routine switches to the -; system mode and returns with IRQ interrupts enabled. -; -; NOTE: It is very important to ensure all IRQ interrupts are cleared +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared ; prior to enabling nested IRQ interrupts. */ ;#ifdef TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_start @@ -234,7 +228,7 @@ __tx_irq_processing_return ; /* Application IRQ handler is called here! */ ; ; /* If interrupt nesting was started earlier, the end of interrupt nesting -; service must be called before returning to _tx_thread_context_restore. +; service must be called before returning to _tx_thread_context_restore. ; This routine returns in processing in IRQ mode with interrupts disabled. */ ;#ifdef TX_ENABLE_IRQ_NESTING ; BL _tx_thread_irq_nesting_end @@ -250,41 +244,41 @@ __tx_irq_processing_return __tx_fiq_handler B __tx_fiq_handler ; FIQ interrupt handler ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* __tx_prefetch_handler & __tx_abort_handler Cortex-R4/MPU/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* __tx_prefetch_handler & __tx_abort_handler Cortex-R4/MPU/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function handles MPU exceptions and fills the */ -;/* _txm_module_manager_memory_fault_info struct. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _txm_module_manager_memory_fault_handler */ -;/* _tx_execution_thread_exit */ -;/* _tx_thread_schedule */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* MMU exceptions */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function handles MPU exceptions and fills the */ +;/* _txm_module_manager_memory_fault_info struct. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _txm_module_manager_memory_fault_handler */ +;/* _tx_execution_thread_exit */ +;/* _tx_thread_schedule */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* MMU exceptions */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 Scott Larson Initial Version 6.1 */ @@ -300,7 +294,7 @@ __tx_fiq_handler EXTERN _txm_module_manager_memory_fault_handler EXTERN _tx_execution_thread_exit EXTERN _tx_thread_schedule - + RSEG .text:CODE:NOROOT(2) PUBLIC Prefetch_Handler PUBLIC Abort_Handler @@ -323,15 +317,15 @@ Abort_Handler LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address LDR r1, [r0] ; Pickup the current thread pointer STR r1, [r3, #0] ; Save current thread pointer - + MRC p15, 0, r0, c6, c0, 0 ; Read DFAR STR r0, [r3, #8] ; Save DFAR - + CMP r0, #0 ; Was it a data or instruction fault? SUBEQ lr, lr, #4 ; Adjust point of exception for instruction SUBNE lr, lr, #8 ; Adjust point of exception for data STR lr, [r3, #4] ; Save point of fault - + MRC p15, 0, r0, c5, c0, 0 ; Read DFSR STR r0, [r3, #12] ; Save DFSR MRC p15, 0, r0, c6, c0, 2 ; Read IFAR @@ -343,7 +337,7 @@ Abort_Handler MCR p15, 0, r0, c5, c0, 0 ; Clear DFSR MCR p15, 0, r0, c6, c0, 2 ; Clear IFAR MCR p15, 0, r0, c5, c0, 1 ; Clear IFSR - + ; Save registers r0-r12 POP {r0-r2} STR r0, [r3, #28] ; Save r0 @@ -360,7 +354,7 @@ Abort_Handler STR r10,[r3, #68] ; Save r10 STR r11,[r3, #72] ; Save r11 STR r12,[r3, #76] ; Save r12 - + CPS #SYS_MODE ; Enter SYS mode MOV r0, lr ; Pickup lr MOV r1, sp ; Pickup sp @@ -372,7 +366,7 @@ Abort_Handler ORR r0, r0, #SYS_MODE ; Return into SYS mode BIC r0, r0, #THUMB_MASK ; Clear THUMB mode MSR SPSR_c, r0 ; Save SPSR - + ; Call memory manager fault handler BL _txm_module_manager_memory_fault_handler @@ -387,11 +381,11 @@ Abort_Handler LDR r1, [r0] ; Pickup system state SUB r1, r1, #1 ; Decrement STR r1, [r0] ; Store new system state - + MOV r1, #0 ; Build NULL value LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer STR r1, [r0] ; Clear current thread pointer - + ; Return from exception LDR lr, =_tx_thread_schedule ; Load scheduler address MOVS pc, lr ; Return to scheduler diff --git a/ports_module/cortex_r4/iar/example_build/txm_module_preamble.s b/ports_module/cortex_r4/iar/example_build/txm_module_preamble.s index 31ccca5b..9b4f1122 100644 --- a/ports_module/cortex_r4/iar/example_build/txm_module_preamble.s +++ b/ports_module/cortex_r4/iar/example_build/txm_module_preamble.s @@ -26,7 +26,7 @@ __txm_module_preamble: DC32 0x6 ; Module Major Version DC32 0x1 ; Module Minor Version DC32 32 ; Module Preamble Size in 32-bit words - DC32 0x12345678 ; Module ID (application defined) + DC32 0x12345678 ; Module ID (application defined) DC32 0x00000001 ; Module Properties where: ; Bits 31-24: Compiler ID ; 0 -> IAR @@ -37,23 +37,23 @@ __txm_module_preamble: ; 1 -> User mode execution (MPU protection) DC32 _txm_module_thread_shell_entry - . - 0 ; Module Shell Entry Point DC32 demo_module_start - . - 0 ; Module Start Thread Entry Point - DC32 0 ; Module Stop Thread Entry Point + DC32 0 ; Module Stop Thread Entry Point DC32 1 ; Module Start/Stop Thread Priority DC32 1022 ; Module Start/Stop Thread Stack Size DC32 _txm_module_callback_request_thread_entry - . - 0 ; Module Callback Thread Entry - DC32 1 ; Module Callback Thread Priority - DC32 1022 ; Module Callback Thread Stack Size + DC32 1 ; Module Callback Thread Priority + DC32 1022 ; Module Callback Thread Stack Size DC32 ROPI$$Length ; Module Code Size DC32 RWPI$$Length ; Module Data Size - DC32 0 ; Reserved 0 + DC32 0 ; Reserved 0 DC32 0 ; Reserved 1 DC32 0 ; Reserved 2 DC32 0 ; Reserved 3 DC32 0 ; Reserved 4 - DC32 0 ; Reserved 5 - DC32 0 ; Reserved 6 - DC32 0 ; Reserved 7 - DC32 0 ; Reserved 8 + DC32 0 ; Reserved 5 + DC32 0 ; Reserved 6 + DC32 0 ; Reserved 7 + DC32 0 ; Reserved 8 DC32 0 ; Reserved 9 DC32 0 ; Reserved 10 DC32 0 ; Reserved 11 diff --git a/ports_module/cortex_r4/iar/inc/tx_port.h b/ports_module/cortex_r4/iar/inc/tx_port.h index 35f50af7..ae9421c8 100644 --- a/ports_module/cortex_r4/iar/inc/tx_port.h +++ b/ports_module/cortex_r4/iar/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Cortex-R4/IAR */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-R4/IAR */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -62,7 +54,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -79,7 +71,7 @@ #endif -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -115,19 +107,19 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -172,7 +164,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -186,11 +178,11 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ VOID *tx_thread_module_instance_ptr; \ @@ -221,7 +213,7 @@ ULONG _tx_misra_time_stamp_get(VOID); ULONG tx_thread_module_stack_size; \ VOID *tx_thread_module_reserved; #endif -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -239,11 +231,11 @@ ULONG _tx_misra_time_stamp_get(VOID); VOID (*tx_timer_module_expiration_function)(ULONG id); -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -253,23 +245,23 @@ ULONG _tx_misra_time_stamp_get(VOID); #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #if (__VER__ < 8000000) -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #endif #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -297,8 +289,8 @@ void __iar_Initlocks(void); #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -309,22 +301,22 @@ void __iar_Initlocks(void); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (UINT) __CLZ(m); \ - b = 31 - b; + b = 31 - b; #endif #endif #endif -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ /* First, check and see what mode the file is being compiled in. The IAR compiler - defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode + defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode is present. If ARM 32-bit mode is present, the fast CPSR manipulation macros are available. Otherwise, if Thumb mode is present, we must use function calls. */ @@ -393,8 +385,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-R4/IAR Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-R4/IAR Version 6.5.0.202601 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_r4/iar/inc/txm_module_port.h b/ports_module/cortex_r4/iar/inc/txm_module_port.h index a4014a7f..9cb72c16 100644 --- a/ports_module/cortex_r4/iar/inc/txm_module_port.h +++ b/ports_module/cortex_r4/iar/inc/txm_module_port.h @@ -1,45 +1,40 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ -/**************************************************************************/ -/* */ -/* APPLICATION INTERFACE DEFINITION RELEASE */ -/* */ -/* txm_module_port.h Cortex-R4/MPU/IAR */ +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-R4/MPU/IAR */ /* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This file defines the basic module constants, interface structures, */ -/* and function prototypes. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ /* */ /**************************************************************************/ @@ -51,13 +46,13 @@ #ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in txm_module_user.h. The defines in this file may +/* Yes, include the user defines in txm_module_user.h. The defines in this file may alternately be defined on the command line. */ #include "txm_module_user.h" #endif -/* It is assumed that the base ThreadX tx_port.h file has been modified to add the +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the following extensions to the ThreadX thread control block (this code should replace the corresponding macro define in tx_port.h): @@ -162,7 +157,7 @@ The following extensions must also be defined in tx_port.h: #define INLINE_DECLARE inline /* Define the number of MPU entries assigned to the code and data sections. - On Cortex-R parts, there are 12 total entries. ThreadX uses one for access + On Cortex-R parts, there are 12 total entries. ThreadX uses one for access to the kernel entry function, thus 11 remain for code and data protection. */ #define TXM_MODULE_MPU_TOTAL_ENTRIES 12 #define TXM_MODULE_MPU_CODE_ENTRIES 4 @@ -230,7 +225,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; /* Define the macro to check the stack available in dispatch. */ -#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE +#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE /* Define the macro to check the code alignment. */ @@ -340,7 +335,7 @@ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-R4/MPU/IAR Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module Cortex-R4/MPU/IAR Version 6.5.0.202601 *"; #endif diff --git a/ports_module/cortex_r4/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_r4/iar/module_lib/src/txm_module_thread_shell_entry.c index 42ae543c..b27e06e3 100644 --- a/ports_module/cortex_r4/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex_r4/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID __iar_data_init3(VOID); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_iar.c b/ports_module/cortex_r4/iar/module_manager/src/tx_iar.c index 158738ea..238b485e 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_iar.c +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_iar.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** IAR Multithreaded Library Support */ /** */ @@ -37,31 +38,31 @@ #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ - thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -90,7 +91,7 @@ void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) { char _DLIB_TLS_MEMORY *p = 0; - + /* Is there a current thread? */ if (_tx_thread_current_ptr) p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; @@ -117,19 +118,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -138,35 +139,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -185,25 +186,25 @@ void __iar_system_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -215,25 +216,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -267,19 +268,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -288,35 +289,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -335,25 +336,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -365,25 +366,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -404,17 +405,17 @@ UINT status; #include "tx_thread.h" #include "tx_mutex.h" -/* This implementation requires that the following macros are defined in the +/* This implementation requires that the following macros are defined in the tx_port.h file and is included with the following code segments: - + #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT #include #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT -#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; #else -#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_2 #endif #ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT @@ -422,17 +423,17 @@ void *_tx_iar_create_per_thread_tls_area(void); void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); void __iar_Initlocks(void); -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); #define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); #define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #endif - This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the - application. + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. */ @@ -456,7 +457,7 @@ void * __aeabi_read_tp(void) TX_THREAD *thread_ptr = _tx_thread_current_ptr; if (thread_ptr) { - p = thread_ptr->tx_thread_iar_tls_pointer; + p = thread_ptr->tx_thread_iar_tls_pointer; } else { @@ -469,9 +470,9 @@ void * __aeabi_read_tp(void) void* _tx_iar_create_per_thread_tls_area() { - UINT tls_size = __iar_tls_size(); - - /* Get memory for TLS. */ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ void *p = malloc(tls_size); /* Initialize TLS-area and run constructors for objects in TLS */ @@ -483,7 +484,7 @@ void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) { /* Destroy objects living in TLS */ __call_thread_dtors(); - free(tls_ptr); + free(tls_ptr); } #ifndef _MAX_LOCK @@ -517,19 +518,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_system_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -538,35 +539,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_system_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_system_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -582,28 +583,28 @@ void __iar_system_Mtxdst(__iar_Rmtx *m) void __iar_system_Mtxlock(__iar_Rmtx *m) { if (*m) - { + { UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -616,25 +617,25 @@ void __iar_system_Mtxunlock(__iar_Rmtx *m) { UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_system_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_system_lock_isr_caller++; } @@ -675,19 +676,19 @@ TX_MUTEX *mutex_ptr; /* Setup a pointer to the start of the next free mutex. */ mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; - + /* Check for wrap-around on the next free mutex. */ if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) { - + /* Yes, set the free index back to 0. */ __tx_iar_file_lock_next_free_mutex = 0; } - + /* Is this mutex free? */ if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) { - + /* Yes, this mutex is free, get out of the loop! */ break; } @@ -696,35 +697,35 @@ TX_MUTEX *mutex_ptr; /* Determine if a free mutex was found. */ if (i >= _MAX_LOCK) { - + /* Error! No more free mutexes! */ - + /* Increment the no mutexes error counter. */ __tx_iar_file_lock_no_mutexes++; - + /* Set return pointer to NULL. */ *m = TX_NULL; - + /* Return. */ return; } - + /* Now create the ThreadX mutex for the IAR library. */ status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); - + /* Determine if the creation was successful. */ if (status == TX_SUCCESS) { - + /* Yes, successful creation, return mutex pointer. */ *m = (VOID *) mutex_ptr; } else { - + /* Increment the internal error counter. */ __tx_iar_file_lock_internal_errors++; - + /* Return a NULL pointer to indicate an error. */ *m = TX_NULL; } @@ -743,25 +744,25 @@ void __iar_file_Mtxlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex locks are only available from initialization and + /* Determine the caller's context. Mutex locks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Get the mutex. */ status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } @@ -773,25 +774,25 @@ void __iar_file_Mtxunlock(__iar_Rmtx *m) UINT status; - /* Determine the caller's context. Mutex unlocks are only available from initialization and + /* Determine the caller's context. Mutex unlocks are only available from initialization and threads. */ if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) { - + /* Release the mutex. */ status = _tx_mutex_put((TX_MUTEX *) *m); - + /* Check the status of the mutex release. */ if (status) { - + /* Internal error, increment the counter. */ __tx_iar_file_lock_internal_errors++; } } else { - + /* Increment the ISR caller error. */ __tx_iar_file_lock_isr_caller++; } diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_context_restore.s index 5234d948..699cfd78 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_context_restore.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; @@ -38,44 +38,38 @@ THUMB_MASK DEFINE 0x20 ; Thumb bit mask ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore Cortex-R4/MPU/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-R4/MPU/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -103,13 +97,13 @@ _tx_thread_context_restore LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3] ; Store the counter + STR r2, [r3] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -169,10 +163,10 @@ __tx_thread_preempt_restore LDMIA sp!, {r0-r3} ; Recover r0-r3 CPS #SYS_MODE ; Enter SYS mode STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack - + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer - + #ifdef __ARMVFP__ LDR r2, [r0, #144] ; Pickup the VFP enabled flag CMP r2, #0 ; Is the VFP enabled? @@ -182,7 +176,7 @@ __tx_thread_preempt_restore VSTMDB sp!, {D0-D15} ; Save D0-D15 _tx_skip_irq_vfp_save #endif - + MOV r3, #1 ; Build interrupt stack type STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR STR sp, [r0, #8] ; Save stack pointer in thread control diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_context_save.s index d8aa33a1..9589e706 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_context_save.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; EXTERN _tx_thread_system_state @@ -26,43 +26,37 @@ EXTERN _tx_execution_isr_enter ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -79,7 +73,7 @@ _tx_thread_context_save ; if (_tx_thread_system_state++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers LDR r3, =_tx_thread_system_state ; Pickup address of system state var LDR r2, [r3, #0] ; Pickup system state CMP r2, #0 ; Is this the first interrupt? @@ -94,7 +88,7 @@ _tx_thread_context_save ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; ; /* Return to the ISR. */ @@ -110,7 +104,7 @@ _tx_thread_context_save POP {lr} ; Recover ISR lr #endif - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; __tx_thread_not_nested_save ; } @@ -124,13 +118,13 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in ; scheduling loop - nothing needs saving! ; ; /* Save minimal context of interrupted thread. */ ; MRS r2, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r2, r10, r12, lr} ; Store other registers ; ; /* Save the current stack pointer in the thread's control block. */ @@ -150,7 +144,7 @@ __tx_thread_not_nested_save POP {lr} ; Recover ISR lr #endif - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ; else @@ -160,7 +154,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit @@ -175,7 +169,7 @@ __tx_thread_idle_system_save #endif ADD sp, sp, #16 ; Recover saved registers - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ;} diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_interrupt_control.s index a6fbb0f8..3eb61e11 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_interrupt_control.s @@ -1,65 +1,59 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; INT_MASK DEFINE 0x80 ; Interrupt bit mask ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) @@ -79,7 +73,7 @@ _tx_thread_interrupt_control ; MSR CPSR_cxsf, r1 ; Setup new CPSR AND r0, r3, #INT_MASK ; Return previous interrupt mask - + BX lr ; Return to caller ; ;} diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_interrupt_disable.s index 7f9a2b2c..c05493d7 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -1,64 +1,58 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_interrupt_restore.s index f862c87d..b1ab3f05 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -1,61 +1,55 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for restoring interrupts to the state */ -;/* returned by a previous _tx_thread_interrupt_disable call. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for restoring interrupts to the state */ +;/* returned by a previous _tx_thread_interrupt_disable call. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;void _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_irq_nesting_end.s b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_irq_nesting_end.s index 85c03c5f..b45a8768 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_irq_nesting_end.s +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_irq_nesting_end.s @@ -1,73 +1,67 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; IRQ_MODE DEFINE 0x12 ; IRQ mode ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_end Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -;/* processing from system mode back to IRQ mode prior to the ISR */ -;/* calling _tx_thread_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_irq_nesting_start.s b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_irq_nesting_start.s index 97bc7029..0fd2c949 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_irq_nesting_start.s +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_irq_nesting_start.s @@ -1,70 +1,64 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; SYS_MODE DEFINE 0x1F ; System mode ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_start Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_context_save has been called and switches the IRQ */ -;/* processing to the system mode so nested IRQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_schedule.s index 72270475..b6bcdfa2 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_schedule.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; EXTERN _tx_thread_execute_ptr @@ -36,45 +36,39 @@ SYS_MODE EQU 0x1F ; SYS mode MODE_MASK EQU 0x1F ; Mode mask ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule Cortex-R4/MPU/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-R4/MPU/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -121,7 +115,7 @@ SWI_Handler ; ; The service call is handled here ; - + CMP r0, #0 ; Is it a schedule request? BEQ _tx_handler_svc_schedule ; Yes, go there @@ -130,7 +124,7 @@ SWI_Handler CMP r0, #2 ; Is it a system mode exit request? BEQ _tx_handler_svc_super_exit ; Yes, go there - + LDR r2, =0x123456 CMP r0, r2 ; Is it an ARM request? BEQ _tx_handler_svc_arm ; Yes, go there @@ -148,11 +142,11 @@ _tx_handler_svc_unrecognized_loop ; We should never get here ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; SVC 1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - ; At this point we have an SVC 1, which means we are entering + ; At this point we have an SVC 1, which means we are entering ; supervisor mode to service a kernel call. _tx_handler_svc_super_enter ; Make sure that we have been called from the system mode enter location (security) - LDR r2, =_txm_system_mode_enter ; Load the address of the known call point + LDR r2, =_txm_system_mode_enter ; Load the address of the known call point SUB r1, lr, #4 ; Calculate the address of the actual call CMP r1, r2 ; Did we come from txm_module_manager_user_mode_entry? BNE _tx_handler_svc_unrecognized ; Return to where we came @@ -162,13 +156,13 @@ _tx_handler_svc_super_enter LDR r2, [r1] ; Load current thread location from the pointer (pointer indirection) MOV r1, #0 ; Load the new user mode flag value (user mode flag clear -> not user mode -> system) STR r1, [r2, #0x9C] ; Clear the current user mode selection for thread - + ; Now we enter the system mode and return LDMFD sp!, {r0, r3} ; Get spsr from the stack BIC r0, r0, #MODE_MASK ; clear mode field ORR r0, r0, #SYS_MODE ; system mode code MSR SPSR_cxsf, r0 ; Restore the spsr - + LDR r1, [r2, #0xA8] ; Load the module kernel stack pointer CPS #SYS_MODE ; Switch to SYS mode MOV r3, sp ; Grab thread stack pointer @@ -182,15 +176,15 @@ _tx_handler_svc_super_enter STRD r0, r1, [r2, #0x0C] ; Set stack start and end #endif LDMFD sp!, {r0-r3, r12, pc}^ ; Restore the registers and return - + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; SVC 2 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - ; At this point we have an SVC 2, which means we are exiting + ; At this point we have an SVC 2, which means we are exiting ; supervisor mode after servicing a kernel call. _tx_handler_svc_super_exit ; Make sure that we have been called from the system mode exit location (security) - LDR r2, =_txm_system_mode_exit ; Load the address of the known call point + LDR r2, =_txm_system_mode_exit ; Load the address of the known call point SUB r1, lr, #4 ; Calculate the address of the actual call CMP r1, r2 ; Did we come from txm_module_manager_user_mode_entry? BNE _tx_handler_svc_unrecognized ; Return to where we came @@ -218,19 +212,19 @@ _tx_handler_svc_super_exit STRD r0, r1, [r2, #0x0C] ; Set stack start and end #endif LDMFD sp!, {r0-r3, r12, pc}^ ; Restore the registers and return - + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ARM Semihosting ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; _tx_handler_svc_arm - + ; *** TODO: handle semihosting requests or ARM angel requests *** - + ; just return LDMFD sp!, {r0, r3} ; Get spsr from the stack MSR SPSR_cxsf, r0 ; Restore the spsr LDMFD sp!, {r0-r3, r12, pc}^ ; Restore the registers and return - + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; SVC 0 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -239,10 +233,10 @@ _tx_handler_svc_schedule LDMFD sp!, {r0, r3} ; Get spsr from stack MSR SPSR_cxsf, r0 ; Restore spsr - LDMFD sp!, {r0-r3, r12, lr} ; Restore the registers + LDMFD sp!, {r0-r3, r12, lr} ; Restore the registers - ; This code waits for a thread control block pointer to appear in - ; the _tx_thread_execute_ptr variable. Once a thread pointer appears + ; This code waits for a thread control block pointer to appear in + ; the _tx_thread_execute_ptr variable. Once a thread pointer appears ; in the variable, the corresponding thread is resumed. ; ; /* Enable interrupts. */ @@ -262,7 +256,7 @@ __tx_thread_schedule_loop ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Lockout interrupts and ; transfer control to it. */ ; @@ -319,7 +313,7 @@ __tx_thread_schedule_loop MRC p15, 0, r3, c6, c1, 0 ; Read DRBAR into r3 CMP r2, r3 ; Is module already loaded? BEQ _tx_end_mpu_update ; Yes - skip memory protection setup - + ; Disable MPU before applying new regions. MRC p15, 0, r2, c1, c0, 0 ; Read SCTLR BIC r2, r2, #1 ; Disable MPU @@ -343,7 +337,7 @@ _tx_mpu_loop ADD r3, r3, #1 ; Increment loop index CMP r3, #0xB ; Check the limit BLE _tx_mpu_loop ; Loop if not finished - + ; Enable MPU with new regions. MRC p15, 0, r2, c1, c0, 0 ; Read SCTLR ORR r2, r2, #1 ; Enable MPU @@ -351,18 +345,18 @@ _tx_mpu_loop DSB MCR p15, 0, r2, c1, c0, 0 ; Write to SCTLR ISB - ; + ; _tx_end_mpu_update ; ************************************************************************** - + CMP r4, #0 ; Check for synchronous context switch BEQ _tx_solicited_return - + MSR SPSR_cxsf, r5 ; Setup SPSR for return LDR r1, [r0, #8] ; Get thread SP LDR lr, [r1, #0x40] ; Get thread PC CPS #SYS_MODE ; Enter SYS mode - + #ifdef __ARMVFP__ LDR r2, [r0, #144] ; Pickup the VFP enabled flag CMP r2, #0 ; Is the VFP enabled? @@ -375,7 +369,7 @@ _tx_end_mpu_update CPS #SYS_MODE ; Enter SYS mode _tx_skip_interrupt_vfp_restore #endif - + LDMIA sp!, {r0-r12, lr} ; Restore registers ADD sp, sp, #4 ; Fix stack pointer CPS #SVC_MODE ; Enter SVC mode @@ -384,7 +378,7 @@ _tx_skip_interrupt_vfp_restore _tx_solicited_return MOV r2, r5 ; Move CPSR to scratch register CPS #SYS_MODE ; Enter SYS mode - + #ifdef __ARMVFP__ LDR r1, [r0, #144] ; Pickup the VFP enabled flag CMP r1, #0 ; Is the VFP enabled? @@ -394,7 +388,7 @@ _tx_solicited_return VMSR FPSCR, r4 ; Restore FPSCR _tx_skip_solicited_vfp_restore #endif - + LDMIA sp!, {r4-r11, lr} ; Restore registers MOV r1, lr ; Copy lr to r1 to preserve across mode change CPS #SVC_MODE ; Enter SVC mode @@ -404,11 +398,11 @@ _tx_skip_solicited_vfp_restore ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; End SWI_Handler ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - + #ifdef __ARMVFP__ PUBLIC tx_thread_vfp_enable CODE32 -tx_thread_vfp_enable??rA +tx_thread_vfp_enable??rA tx_thread_vfp_enable MRS r2, CPSR ; Pickup the CPSR CPSID i ; Disable IRQ interrupts @@ -424,7 +418,7 @@ __tx_no_thread_to_enable: PUBLIC tx_thread_vfp_disable CODE32 -tx_thread_vfp_disable??rA +tx_thread_vfp_disable??rA tx_thread_vfp_disable MRS r2, CPSR ; Pickup the CPSR CPSID i ; Disable IRQ interrupts diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_stack_build.s index 502c3529..1708ede4 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_stack_build.s @@ -1,81 +1,75 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; SYS_MODE DEFINE 0x1F ; SYS mode CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints enabled ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build Cortex-R4/MPU/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-R4/MPU/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function builds a stack frame on the supplied thread's stack. */ -;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Pointer to thread control blk */ -;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) ;{ RSEG .text:CODE:NOROOT(2) PUBLIC _tx_thread_stack_build - + ARM _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-R4 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; a1 (r0) Initial value for a1 diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_system_return.s index af808d42..f9d4c9e3 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_system_return.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; EXTERN _tx_thread_current_ptr @@ -27,44 +27,38 @@ ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -97,7 +91,7 @@ _tx_skip_solicited_vfp_save: MOV r0, #0 ; Build a solicited stack type STMDB sp!, {r0-r1} ; Save type and CPSR -; +; ; #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_vectored_context_save.s b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_vectored_context_save.s index d5f077b2..2f075445 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_thread_vectored_context_save.s +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_thread_vectored_context_save.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; EXTERN _tx_thread_system_state @@ -25,43 +25,37 @@ EXTERN _tx_execution_isr_enter ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_vectored_context_save Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) @@ -118,7 +112,7 @@ __tx_thread_not_nested_save LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in ; scheduling loop - nothing needs saving! ; ; /* Note: Minimal context of interrupted thread is already saved. */ @@ -150,7 +144,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports_module/cortex_r4/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_r4/iar/module_manager/src/tx_timer_interrupt.s index 5d4efcd8..7213e213 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex_r4/iar/module_manager/src/tx_timer_interrupt.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Timer */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; ;Define Assembly language external references... @@ -34,46 +34,40 @@ ; ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt Cortex-R4/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-R4/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* _tx_thread_time_slice Time-slice interrupted thread */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time-slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -99,7 +93,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CMP r2, #0 ; Is it non-active? BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing @@ -217,13 +211,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CMP r2, #0 ; See if the flag is set BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing ; diff --git a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_alignment_adjust.c index 50e0c672..9876d72f 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,23 +1,24 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -25,42 +26,36 @@ #include "txm_module.h" -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_power_of_two_block_size Cortex-R4/MPU/IAR */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_power_of_two_block_size Cortex-R4/MPU/IAR */ /* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function calculates a power of two size at or immediately above*/ -/* the input size and returns it to the caller. */ -/* */ -/* INPUT */ -/* */ -/* size Block size */ -/* */ -/* OUTPUT */ -/* */ -/* calculated size Rounded up to power of two */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-R */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* This function calculates a power of two size at or immediately above*/ +/* the input size and returns it to the caller. */ +/* */ +/* INPUT */ +/* */ +/* size Block size */ +/* */ +/* OUTPUT */ +/* */ +/* calculated size Rounded up to power of two */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-R */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -68,11 +63,11 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 32. */ if(size <= 32) return 32; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -82,58 +77,58 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_alignment_adjust Cortex-R4/MPU/IAR */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-R4/MPU/IAR */ /* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function adjusts the alignment and size of the code and data */ -/* section for a given module implementation. */ -/* */ -/* INPUT */ -/* */ -/* module_preamble Pointer to module preamble */ -/* code_size Size of the code area (updated) */ -/* code_alignment Code area alignment (updated) */ -/* data_size Size of data area (updated) */ -/* data_alignment Data area alignment (updated) */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _txm_power_of_two_block_size Calculate power of two size */ -/* */ -/* CALLED BY */ -/* */ -/* Initial thread stack frame */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* module_preamble Pointer to module preamble */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_power_of_two_block_size Calculate power of two size */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, - ULONG *code_size, - ULONG *code_alignment, - ULONG *data_size, +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, + ULONG *code_size, + ULONG *code_alignment, + ULONG *data_size, ULONG *data_alignment) { @@ -162,7 +157,7 @@ ULONG data_size_accum; code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; - + /* Determine data block sizes. Minimize the alignment requirement. There are 4 MPU data entries available. The following is how the data size will be distributed: @@ -175,9 +170,9 @@ ULONG data_size_accum; data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); local_data_size = data_size_accum; - + /* Return all the information to the caller. */ - *code_size = local_code_size; + *code_size = local_code_size; *code_alignment = local_code_alignment; *data_size = local_data_size; *data_alignment = local_data_alignment; diff --git a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_external_memory_enable.c index 5b61abb8..4f9ced4c 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,12 +65,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, diff --git a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index ea6c2022..e468e239 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { diff --git a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index 5653ee37..21b4a4da 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,23 +1,24 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -33,51 +34,45 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_memory_fault_notify Cortex-R4/MPU/IAR */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-R4/MPU/IAR */ /* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function registers an application callback when/if a memory */ -/* fault occurs. The supplied thread is automatically terminated, but */ -/* any other threads in the same module may still execute. */ -/* */ -/* INPUT */ -/* */ -/* notify_function Memory fault notification */ -/* function, NULL disables. */ -/* */ -/* OUTPUT */ -/* */ -/* status Completion status */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_mm_register_setup.c index 365f2e2d..e8e28bc7 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _txm_module_manager_mm_register_setup */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ -/* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) { @@ -514,7 +509,7 @@ ALIGN_TYPE shared_memory_address_end; { return(TX_FALSE); } - + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_thread_stack_build.s index a2aa765a..9e0efc28 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,23 +1,23 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; THUMB_MASK DEFINE 0x20 ; THUMB bit @@ -26,44 +26,38 @@ SYS_MODE DEFINE 0x1F ; SYS mode CPSR_MASK DEFINE 0xBF ; Mask initial CPSR, IRQ ints enabled ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _txm_module_manager_thread_stack_build Cortex-R4/MPU/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_thread_stack_build Cortex-R4/MPU/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function builds a stack frame on the supplied thread's stack. */ -;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Pointer to thread control blk */ -;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) @@ -76,7 +70,7 @@ _txm_module_manager_thread_stack_build ; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-R4 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; r0 Initial value for r0 diff --git a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_user_mode_entry.s b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_user_mode_entry.s index 263a13cb..07d81f95 100644 --- a/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_user_mode_entry.s +++ b/ports_module/cortex_r4/iar/module_manager/src/txm_module_manager_user_mode_entry.s @@ -1,66 +1,60 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; EXTERN _tx_thread_current_ptr EXTERN _txm_module_manager_kernel_dispatch - - + + RSEG .text:CODE:NOROOT(5) ARM -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _txm_module_manager_user_mode_entry Cortex-R4/MPU/IAR */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_user_mode_entry Cortex-R4/MPU/IAR */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function allows modules to enter kernel mode. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* SVC 1 Enter kernel mode */ -;/* SVC 2 Exit kernel mode */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Modules in user mode */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ +;/* DESCRIPTION */ ;/* */ -;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* This function allows modules to enter kernel mode. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* SVC 1 Enter kernel mode */ +;/* SVC 2 Exit kernel mode */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Modules in user mode */ ;/* */ ;/**************************************************************************/ PUBLIC _txm_module_manager_user_mode_entry @@ -85,5 +79,5 @@ _txm_system_mode_exit NOP NOP _txm_module_manager_user_mode_end - + END diff --git a/ports_module/rxv2/iar/example_build/hwsetup.c b/ports_module/rxv2/iar/example_build/hwsetup.c index ab3e3bac..c03895a5 100644 --- a/ports_module/rxv2/iar/example_build/hwsetup.c +++ b/ports_module/rxv2/iar/example_build/hwsetup.c @@ -1,25 +1,25 @@ /* Adapted for use with IAR Embedded Workbench */ /*********************************************************************************************************************** * DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No -* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM -* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES -* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of -* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the * following link: -* http://www.renesas.com/disclaimer +* http://www.renesas.com/disclaimer * -* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** * File Name : hwsetup.c -* Version : 1.0 +* Version : 1.0 * Device(s) : RX * H/W Platform : RX65N * Description : Defines the initialisation routines used each time the MCU is restarted. @@ -83,34 +83,34 @@ void operating_frequency_set(void) Peripheral Clock Frequency....... 48 MHz USB Clock Frequency.............. 48 MHz External Bus Clock Frequency..... 24 MHz */ - + volatile unsigned int i; - + /* Protect off. */ SYSTEM.PRCR.WORD = 0xA50B; - + /* Uncomment if not using sub-clock */ //SYSTEM.SOSCCR.BYTE = 0x01; /* stop sub-clock */ SYSTEM.SOSCCR.BYTE = 0x00; /* Enable sub-clock for RTC */ - + /* Wait 131,072 cycles * 12 MHz = 10.9 ms */ SYSTEM.MOSCWTCR.BYTE = 0x0D; - + /* x16 @PLL, 2 divisor */ SYSTEM.PLLCR.WORD = 0x0F01; - + /* EXTAL ON */ SYSTEM.MOSCCR.BYTE = 0x00; - + /* PLL ON */ SYSTEM.PLLCR2.BYTE = 0x00; - + for(i = 0;i< 0x168;i++) { /* Wait over 12ms */ __no_operation(); } - + /* Setup system clocks SCKCR - System Clock Control Register b31:b28 FCK[3:0] 0x02 = Flash clock: PLL/4 = (192 / 4) = 48 MHz @@ -120,17 +120,17 @@ void operating_frequency_set(void) b11:b8 PCKB[3:0] 0x02 = Peripheral clock B: PLL/4 = 48 MHz */ SYSTEM.SCKCR.LONG = 0x21031222; /* ICK=PLL/2,BCK,FCK,PCK=PLL/4 */ - + /* Setup IEBUS and USB clocks - SCKCR2 - System Clock Control Register 2 + SCKCR2 - System Clock Control Register 2 b7:b4 UCK[3:0] 0x03 = USB clock is PLL/4 = 48 MHz b3:b0 IEBCK[3:0] 0x01 = IE Bus clock is PLL/2 = 96 MHz */ SYSTEM.SCKCR2.WORD = 0x0031; - + /* ICLK, PCLKB, FCLK, BCLK, IECLK, and USBCLK all come from PLL circuit */ SYSTEM.SCKCR3.WORD = 0x0400; - + /* Protect on. */ SYSTEM.PRCR.WORD = 0xA500; } @@ -146,7 +146,7 @@ void interrupts_configure(void) { /* Protect off. */ SYSTEM.PRCR.WORD = 0xA50B; - + /* Enable the bus error interrupt to catch accesses to illegal/reserved areas of memory. */ @@ -154,9 +154,9 @@ void interrupts_configure(void) IR(BSC,BUSERR) = 0; /* Make this the highest priority interrupt (adjust as necessary for your application) */ - IPR(BSC,BUSERR) = 0x0F; + IPR(BSC,BUSERR) = 0x0F; /* Enable the interrupt in the ICU */ - IEN(BSC,BUSERR) = 1; + IEN(BSC,BUSERR) = 1; /* Enable illegal address interrupt in the BSC */ BSC.BEREN.BIT.IGAEN = 1; } @@ -167,11 +167,11 @@ void interrupts_configure(void) * Description : Sample ISR for bus error (must do hardware setup first!) * By default, this demo code enables the Bus Error Interrupt. * This interrupt will fire if the user tries to access code -* or data from one of the reserved areas in the memory map, +* or data from one of the reserved areas in the memory map, * including the areas covered by disabled chip selects. * A nop statement is included here as a convenient place * to set a breakpoint during debugging and development, and -* further handling should be added by the user for their +* further handling should be added by the user for their * application. * Arguments : none * Return value : none @@ -183,7 +183,7 @@ __interrupt void buserr_isr(void) the register BSC.BERSR2.WORD. The upper 13 bits of this register contain the upper 13-bits of the offending address (in 512K byte units). */ - + /* Add your own code here to handle this interrupt */ __no_operation(); } diff --git a/ports_module/rxv2/iar/example_build/hwsetup.h b/ports_module/rxv2/iar/example_build/hwsetup.h index d2bae5f6..5ff001c0 100644 --- a/ports_module/rxv2/iar/example_build/hwsetup.h +++ b/ports_module/rxv2/iar/example_build/hwsetup.h @@ -1,25 +1,25 @@ /* Adapted for use with IAR Embedded Workbench */ /*********************************************************************************************************************** * DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No -* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM -* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES -* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of -* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the * following link: -* http://www.renesas.com/disclaimer +* http://www.renesas.com/disclaimer * -* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** * File Name : hwsetup.h -* Version : 1.0 +* Version : 1.0 * Description : Hardware setup header file.. ***********************************************************************************************************************/ /*********************************************************************************************************************** diff --git a/ports_module/rxv2/iar/example_build/low_level_init.c b/ports_module/rxv2/iar/example_build/low_level_init.c index 5b89a40a..95069278 100644 --- a/ports_module/rxv2/iar/example_build/low_level_init.c +++ b/ports_module/rxv2/iar/example_build/low_level_init.c @@ -31,7 +31,7 @@ __intrinsic int __low_level_init ( void ) { hardware_setup(); - + /*==================================*/ /* Choose if segment initialization */ /* should be done or not. */ diff --git a/ports_module/rxv2/iar/example_build/sample_module_linker.icf b/ports_module/rxv2/iar/example_build/sample_module_linker.icf index b6187731..d37c93f1 100644 --- a/ports_module/rxv2/iar/example_build/sample_module_linker.icf +++ b/ports_module/rxv2/iar/example_build/sample_module_linker.icf @@ -60,10 +60,10 @@ define block HEAP with alignment = 4, size = _HEAP_SIZE { }; // { ro section .dataflash* }; define movable block ROPI with alignment = 4, fixed order, static base CB -{ +{ ro object txm_module_preamble_rx65n.o, - ro, - ro data + ro, + ro data }; define movable block RWPI with alignment = 8, fixed order, static base SB diff --git a/ports_module/rxv2/iar/example_build/sample_threadx_module.c b/ports_module/rxv2/iar/example_build/sample_threadx_module.c index 51822c10..80d89b01 100644 --- a/ports_module/rxv2/iar/example_build/sample_threadx_module.c +++ b/ports_module/rxv2/iar/example_build/sample_threadx_module.c @@ -1,5 +1,5 @@ -/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes - examples of eight threads of different priorities, using a message queue, semaphore, mutex, +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ /* Specify that this is a module! */ @@ -20,7 +20,7 @@ #define DEMO_QUEUE_SIZE 100 -/* Define the pool space in the bss section of the module. ULONG is used to +/* Define the pool space in the bss section of the module. ULONG is used to get the word alignment. */ ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; @@ -99,7 +99,7 @@ void demo_module_start(ULONG id) CHAR *pointer; /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within - their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting the control block(s). */ txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); @@ -115,7 +115,7 @@ CHAR *pointer; txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); - + /* Create a byte memory pool from which to allocate the thread stacks. */ tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); @@ -127,42 +127,42 @@ CHAR *pointer; tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -170,23 +170,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -196,7 +196,7 @@ CHAR *pointer; tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); tx_queue_send_notify(queue_0, queue_0_notify); - + /* Create the semaphore used by threads 3 and 4. */ tx_semaphore_create(semaphore_0, "module semaphore 0", 1); @@ -241,7 +241,7 @@ UINT status; /* Sleep for 10 ticks. */ tx_thread_sleep(10); - + /* Set event flag 0 to wakeup thread 5. */ status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); @@ -289,18 +289,18 @@ UINT status; { /* Write value to shared memory region. */ // *(ULONG *)0x00020000 = 0xCDCDCDCD; - + /* Increment the thread counter. */ thread_2_counter++; /* Retrieve a message from the queue. */ status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -354,12 +354,12 @@ ULONG actual_flags; /* This thread simply waits for an event in a forever loop. */ while(1) { - + /* Increment the thread counter. */ thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -412,7 +412,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(mutex_0); diff --git a/ports_module/rxv2/iar/example_build/sample_threadx_module_manager.c b/ports_module/rxv2/iar/example_build/sample_threadx_module_manager.c index 4afbbe39..46e3be59 100644 --- a/ports_module/rxv2/iar/example_build/sample_threadx_module_manager.c +++ b/ports_module/rxv2/iar/example_build/sample_threadx_module_manager.c @@ -54,8 +54,8 @@ void tx_application_define(void *first_unused_memory) CHAR *pointer = (CHAR*)first_unused_memory; - tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; } @@ -75,39 +75,39 @@ void module_manager_entry(ULONG thread_input) /* Register a fault handler. */ txm_module_manager_memory_fault_notify(module_fault_handler); - + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0xFFF10400); - - + + /* Enable 128 byte read/write shared memory region at 0x00020000. */ txm_module_manager_external_memory_enable(&my_module, (void *) 0x00020000, 128, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_READ | TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); - + /* Start the module. */ txm_module_manager_start(&my_module); - + /* Sleep for a while.... */ tx_thread_sleep(1000); - + /* Stop the module. */ txm_module_manager_stop(&my_module); - + /* Unload the module. */ txm_module_manager_unload(&my_module); /* Load the module that is already there. */ txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0xFFF10400); - + /* Set maximum module priority to 5. */ txm_module_manager_maximum_module_priority_set(&my_module, 5); - + /* Start the module again. */ txm_module_manager_start(&my_module); - + /* Now just spin... */ while(1) { - + tx_thread_sleep(100); } } diff --git a/ports_module/rxv2/iar/example_build/tx_initialize_low_level.s b/ports_module/rxv2/iar/example_build/tx_initialize_low_level.s index 391e9c5c..b47b1684 100644 --- a/ports_module/rxv2/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/rxv2/iar/example_build/tx_initialize_low_level.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -59,12 +59,6 @@ ;/* */ ;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 01-31-2022 William E. Lamie Initial Version 6.1.10 */ -;/* */ ;/**************************************************************************/ public __tx_initialize_low_level @@ -74,7 +68,7 @@ __tx_initialize_low_level: ; _tx_initialize_unused_memory = (VOID_PTR) &free_mem_start; ; MOV.L #__tx_free_memory_start, R1 ; Pickup unused memory address - MOV.L #__tx_initialize_unused_memory,R2 + MOV.L #__tx_initialize_unused_memory,R2 MOV.L R1,[R2] ; Save first free memory address ; /* Set priority of SWINT to 1. */ diff --git a/ports_module/rxv2/iar/example_build/txm_module_preamble.s b/ports_module/rxv2/iar/example_build/txm_module_preamble.s index bf5bb9fb..13487bc7 100644 --- a/ports_module/rxv2/iar/example_build/txm_module_preamble.s +++ b/ports_module/rxv2/iar/example_build/txm_module_preamble.s @@ -1,7 +1,7 @@ /* Alignment of 4 (16-byte) */ SECTION .text:CODE (4) - - + + /* Define public symbols. */ PUBLIC __txm_module_preamble @@ -25,7 +25,7 @@ __txm_module_preamble: DC32 0x5 // Module Major Version DC32 0x6 // Module Minor Version DC32 32 // Module Preamble Size in 32-bit words - DC32 0x12345678 // Module ID (application defined) + DC32 0x12345678 // Module ID (application defined) DC32 0x00000007 // Module Properties where: // Bits 31-24: Compiler ID // 0 -> IAR @@ -39,23 +39,23 @@ __txm_module_preamble: // 1 -> Enable shared/external memory access DC32 __txm_module_thread_shell_entry - $ // Module Shell Entry Point DC32 _demo_module_start - $ // Module Start Thread Entry Point - DC32 0 // Module Stop Thread Entry Point + DC32 0 // Module Stop Thread Entry Point DC32 1 // Module Start/Stop Thread Priority DC32 1024 // Module Start/Stop Thread Stack Size DC32 __txm_module_callback_request_thread_entry - $ // Module Callback Thread Entry - DC32 1 // Module Callback Thread Priority - DC32 1024 // Module Callback Thread Stack Size + DC32 1 // Module Callback Thread Priority + DC32 1024 // Module Callback Thread Stack Size DC32 ROPI$$Length // Module Code Size DC32 RWPI$$Length // Module Data Size - DC32 0 // Reserved 0 + DC32 0 // Reserved 0 DC32 0 // Reserved 1 DC32 0 // Reserved 2 DC32 0 // Reserved 3 DC32 0 // Reserved 4 - DC32 0 // Reserved 5 - DC32 0 // Reserved 6 - DC32 0 // Reserved 7 - DC32 0 // Reserved 8 + DC32 0 // Reserved 5 + DC32 0 // Reserved 6 + DC32 0 // Reserved 7 + DC32 0 // Reserved 8 DC32 0 // Reserved 9 DC32 0 // Reserved 10 DC32 0 // Reserved 11 diff --git a/ports_module/rxv2/iar/inc/tx_port.h b/ports_module/rxv2/iar/inc/tx_port.h index 1790cd94..cc4bddee 100644 --- a/ports_module/rxv2/iar/inc/tx_port.h +++ b/ports_module/rxv2/iar/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,21 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -/* 06-02-2021 William E. Lamie Modified comments, */ -/* resulting in version 6.1.7 */ -/* 10-15-2021 William E. Lamie Modified comment(s), */ -/* resulting in version 6.1.9 */ -/* 01-31-2022 William E. Lamie Modified comment(s), removed */ -/* system state macro, and */ -/* added missing interrupt */ -/* control defines, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -70,13 +56,13 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" #endif -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -118,8 +104,8 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif @@ -144,7 +130,7 @@ typedef unsigned short USHORT; #define TX_INLINE_INITIALIZATION -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -156,11 +142,11 @@ typedef unsigned short USHORT; /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ VOID *tx_thread_module_entry_info_ptr; \ ULONG tx_thread_module_current_user_mode; \ @@ -174,7 +160,7 @@ typedef unsigned short USHORT; ULONG tx_thread_module_stack_size; \ VOID *tx_thread_module_reserved; \ VOID *tx_thread_iar_tls_pointer; -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -195,11 +181,11 @@ typedef unsigned short USHORT; VOID (*tx_timer_module_expiration_function)(ULONG id); -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -207,8 +193,8 @@ typedef unsigned short USHORT; tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -234,9 +220,9 @@ typedef unsigned short USHORT; #define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -286,8 +272,8 @@ static void _tx_thread_system_return_inline(void) /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX RXv2/IAR Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX RXv2/IAR Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/rxv2/iar/inc/txm_module_port.h b/ports_module/rxv2/iar/inc/txm_module_port.h index fc7520b9..5712f376 100644 --- a/ports_module/rxv2/iar/inc/txm_module_port.h +++ b/ports_module/rxv2/iar/inc/txm_module_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,12 +36,6 @@ /* This file defines the basic module constants, interface structures, */ /* and function prototypes. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H @@ -90,7 +85,7 @@ The following extensions must also be defined in tx_port.h: VOID (*tx_timer_module_expiration_function)(ULONG id); */ -#define TXM_MODULE_THREAD_ENTRY_INFO_USER_EXTENSION +#define TXM_MODULE_THREAD_ENTRY_INFO_USER_EXTENSION /* Define constants specific to the tools the module can be built with for this particular modules port. */ @@ -255,7 +250,7 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT { \ _tx_mutex_put(&_txm_module_manager_mutex); \ return(TXM_MODULE_INVALID_PROPERTIES); \ - } + } /* Define the macro to check the code alignment. */ @@ -395,6 +390,6 @@ VOID _txm_module_manager_setup_mpu_registers(TXM_MODULE_INSTANCE *module_instan #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module RXv2/IAR Version 6.4.2 *"; + "Copyright (c) 2024 Microsoft Corporation. * ThreadX Module RXv2/IAR Version 6.5.0.202601 *"; #endif diff --git a/ports_module/rxv2/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/rxv2/iar/module_lib/src/txm_module_thread_shell_entry.c index 95d085fa..1242184c 100644 --- a/ports_module/rxv2/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/rxv2/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -86,12 +87,6 @@ extern VOID __iar_data_init2(VOID); /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) { @@ -107,14 +102,14 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN { /* Initialize the IAR C environment. */ __iar_data_init2(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { @@ -122,7 +117,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ } - + /* Resume the module's callback thread, already created in the manager. */ _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); } diff --git a/ports_module/rxv2/iar/module_manager/src/tx_initialize_low_level.s b/ports_module/rxv2/iar/module_manager/src/tx_initialize_low_level.s index f3d5293c..3faf9bc9 100644 --- a/ports_module/rxv2/iar/module_manager/src/tx_initialize_low_level.s +++ b/ports_module/rxv2/iar/module_manager/src/tx_initialize_low_level.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,13 +57,6 @@ /* CALLED BY */ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 William E. Lamie Initial Version 6.1.10 */ -/* */ /**************************************************************************/ public __tx_initialize_low_level @@ -72,7 +66,7 @@ __tx_initialize_low_level: // _tx_initialize_unused_memory = (VOID_PTR) &free_mem_start; MOV.L #__tx_free_memory_start, R1 // Pick up unused memory address - MOV.L #__tx_initialize_unused_memory,R2 + MOV.L #__tx_initialize_unused_memory,R2 MOV.L R1,[R2] // Save first free memory address /* Set priority of SWINT to 1. */ @@ -89,7 +83,7 @@ __tx_initialize_low_level: /* Enable SWINT2. */ OR #(1 << 2), r2 MOV.B r2, [r1] - + RTS section FREEMEM:DATA diff --git a/ports_module/rxv2/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/rxv2/iar/module_manager/src/tx_thread_context_restore.s index b9dc97da..f4c5f492 100644 --- a/ports_module/rxv2/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/rxv2/iar/module_manager/src/tx_thread_context_restore.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -72,16 +72,6 @@ ;/* */ ;/* ISRs Interrupt Service Routines */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* removed unnecessary stack */ -;/* type placement, */ -;/* resulting in version 6.1.9 */ -;/* */ ;/**************************************************************************/ public __tx_thread_context_restore @@ -99,7 +89,7 @@ __tx_thread_context_restore: MOV.L [R1], R2 SUB #1, R2 MOV.L R2,[R1] - BEQ __tx_thread_not_nested_restore + BEQ __tx_thread_not_nested_restore ; ; /* Interrupts are nested. */ @@ -121,17 +111,17 @@ __tx_thread_not_nested_restore: ; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)) ; || (_tx_thread_preempt_disable)) ; { - + MOV.L #__tx_thread_current_ptr, R1 ; Pickup current thread ptr address MOV.L [R1], R2 CMP #0, R2 - BEQ __tx_thread_idle_system_restore - + BEQ __tx_thread_idle_system_restore + MOV.L #__tx_thread_preempt_disable, R3 ; Pick up preempt disable flag MOV.L [R3], R3 CMP #0, R3 BNE __tx_thread_no_preempt_restore ; If pre-empt disable flag set, we simply return to the original point of interrupt regardless - + MOV.L #__tx_thread_execute_ptr, R3 ; (_tx_thread_current_ptr != _tx_thread_execute_ptr) CMP [R3], R2 BNE __tx_thread_preempt_restore ; Jump to pre-empt restoring @@ -172,7 +162,7 @@ __tx_thread_dont_save_ts: SETPSW U ; User stack PUSHM R6-R13 - + MVFACGU #0, A1, R4 ; Save accumulators. MVFACHI #0, A1, R5 MVFACLO #0, A1, R6 @@ -181,7 +171,7 @@ __tx_thread_dont_save_ts: MVFACHI #0, A0, R5 MVFACLO #0, A0, R6 PUSHM R4-R6 - + ; ; /* Clear the current task pointer. */ ; _tx_thread_current_ptr = TX_NULL; diff --git a/ports_module/rxv2/iar/module_manager/src/tx_thread_context_save.s b/ports_module/rxv2/iar/module_manager/src/tx_thread_context_save.s index 0d461baa..4e7b8fc3 100644 --- a/ports_module/rxv2/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/rxv2/iar/module_manager/src/tx_thread_context_save.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -65,14 +65,6 @@ ;/* */ ;/* ISRs */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) ;{ @@ -100,7 +92,7 @@ __tx_thread_context_save: BEQ __tx_thread_not_nested_save ; ; /* Nested interrupt condition. */ -; +; ADD #1, r2 ; _tx_thread_system_state++ MOV.L r2, [r1] @@ -126,7 +118,7 @@ __tx_thread_not_nested_save: MOV.L #__tx_thread_current_ptr, R2 ; Pickup current thread pointer MOV.L [R2], R2 - CMP #0,R2 ; Is it NULL? + CMP #0,R2 ; Is it NULL? BEQ __tx_thread_idle_system_save ; Yes, idle system is running - idle restore ; ; /* Move stack frame over to the current threads stack. */ @@ -148,7 +140,7 @@ __tx_thread_not_nested_save: MOV.L R14, [-R1] ; Save R14 on thread stack MVFC FPSW, R3 MOV.L R3, [-R1] ; Save FPSW on thread stack - + POP R2 ; Pick up return address from interrupt stack ADD #16, R0, R0 ; Correct interrupt stack pointer back to the bottom MVTC R1, USP ; Set user/thread stack pointer @@ -167,5 +159,5 @@ __tx_thread_idle_system_save: JMP R1 ; Return to caller ; ; } -;} +;} END diff --git a/ports_module/rxv2/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/rxv2/iar/module_manager/src/tx_thread_interrupt_control.s index 558b9153..b2cb65e4 100644 --- a/ports_module/rxv2/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/rxv2/iar/module_manager/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -59,14 +59,6 @@ ;/* */ ;/* Application Code */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) ;{ @@ -75,20 +67,20 @@ __tx_thread_interrupt_control: ; ; /* Pickup current interrupt lockout posture. */ ; - + MVFC PSW, R2 ; Save PSW to R2 MOV.L R2, R3 ; Make a copy of PSW in r3 - + ; ; /* Apply the new interrupt posture. */ ; - + BTST #16, R1 ; Test I bit of PSW of "new posture" BMNE #16, R2 ; Conditionally set I bit of intermediate posture - + MVTC R2, PSW ; Save intermediate posture to PSW - - MOV.L R3,R1 ; Get original SR + + MOV.L R3,R1 ; Get original SR RTS ; Return to caller ;} END diff --git a/ports_module/rxv2/iar/module_manager/src/tx_thread_schedule.s b/ports_module/rxv2/iar/module_manager/src/tx_thread_schedule.s index fb60efaa..572eff32 100644 --- a/ports_module/rxv2/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/rxv2/iar/module_manager/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,17 +63,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -/* 10-15-2021 William E. Lamie Modified comment(s), and */ -/* removed unnecessary stack */ -/* type checking, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { @@ -134,40 +124,40 @@ __tx_thread_schedule_loop: MOV.L 156[R2],R1 // Pickup user_mode CMP #0,R1 // Is protection required for this thread? BEQ skip_mpu_setup // No, skip MPU setup - + MOV.L #0x00086408,R1 // Region 1 Start Page Register address MOV.L 144[R2],R2 // Address of module instance ptr at offset 144 in TCB ADD #100,R2,R2 // Get address of MPU table in module struct, starting at region 1 - + // Region 0 (Trampoline from User mode to ThreadX) set up in txm_module_manager_setup_mpu_registers.c - + // Build region 1 (User code) MOV.L [R2+],R4 // Pickup region 1 start page, increment to region 1 end page MOV.L R4,[R1+] // Setup region 1 start page reg, increment to region 1 end page reg. MOV.L [R2+],R4 // Pickup region 1 end page, increment to region 2 start page MOV.L R4,[R1+] // Setup region 1 end page reg, increment to region 2 start page reg. - + // Build region 2 (User data) MOV.L [R2+],R4 // Pickup region 2 start page, increment to region 2 end page MOV.L R4,[R1+] // Setup region 2 start page reg, increment to region 2 end page reg. MOV.L [R2+],R4 // Pickup region 2 end page, increment to region 3 start page MOV.L R4,[R1+] // Setup region 2 end page reg, increment to region 3 start page reg. - + // Build region 3 (Shared memory) MOV.L [R2+],R4 // Pickup region 3 start page, increment to region 3 end page MOV.L R4,[R1+] // Setup region 3 start page reg, increment to region 3 end page reg. MOV.L [R2+],R4 // Pickup region 3 end page, increment to region 4 start page MOV.L R4,[R1+] // Setup region 3 end page reg, increment to region 4 start page reg. - + // Region 4-7 unused - + // Setup background region MOV.L #0x00086504,R1 // Pickup MPBAC MOV #0,[R1] // Read/Write/Execute prohibited. // Enable MPU MOV.L #0x00086500,R1 // Pickup MPEN MOV #1,[R1] // Enable MPU - + skip_mpu_setup POPM R1-R3 // Restore accumulators. @@ -180,7 +170,7 @@ skip_mpu_setup MVTACGU R1, A1 POPM R6-R13 // Recover interrupt stack frame - POPC FPSW + POPC FPSW POPM R14-R15 POPM R3-R5 POPM R1-R2 @@ -195,7 +185,7 @@ skip_mpu_setup The priority of this interrupt is set to the lowest priority within tx_initialize_low_level() and triggered by ThreadX when calling _tx_thread_system_return(). */ - + public ___interrupt_27 ___interrupt_27: @@ -206,7 +196,7 @@ ___interrupt_27: BRA __tx_thread_context_restore -/* You may have to modify BSP to use this handler. +/* You may have to modify BSP to use this handler. // MPU Memory access violation PUBLIC ___excep_access_inst PUBLIC ___violation_handler @@ -260,15 +250,15 @@ ___violation_handler MOV.L R3, 32[R1] // Save R1 POP R3 // Recall R2 MOV.L R3, 36[R1] // Save R2 - + BSR __txm_module_manager_memory_fault_handler // Call memory manager fault handler - + // Decrement and save system state MOV.L #__tx_thread_system_state, R1 // Pickup address of system state MOV.L [R1], R2 // Pickup system state SUB #1, R2 // Decrement MOV.L R2, [R1] // Store new system state - + MOV.L #__tx_thread_current_ptr, R2 // Pickup address of current thread pointer MOV.L #0, [R2] // Clear current thread pointer BRA __tx_thread_schedule // Attempt to schedule the next thread @@ -284,15 +274,15 @@ __txm_module_manager_kernel CMP #__txm_module_manager_user_mode_entry+3, R5 // Did we come from user_mode_entry? BEQ __txm_module_manager_entry // If so, continue. RTE // If not, then return from where we came. - + __txm_module_manager_entry // We are entering the kernel from a module thread with user mode selected. - // At this point, we are out of user mode! + // At this point, we are out of user mode! // Clear current user mode. MOV.L #__tx_thread_current_ptr, R5 MOV [R5],R5 MOV #0,152[R5] - + // Switch to kernel stack PUSHM R1-R2 MVFC USP, R1 // Pickup module thread stack pointer @@ -312,7 +302,7 @@ __txm_module_manager_entry MOV.L 4[SP], R5 BCLR #20, R5 MOV.L R5, 4[SP] - + // Return to user_mode_entry where kernel_dispatch will be called. RTE @@ -324,12 +314,12 @@ __txm_module_manager_entry __txm_module_manager_user_mode_entry INT #26 // Enter ThreadX kernel (exit User mode). - + // At this point, we are out of user mode. // Simply call the kernel dispatch function. MOV.L #__txm_module_manager_kernel_dispatch,R5 JSR R5 - + // Restore user mode while inside of ThreadX. MOV.L #__tx_thread_current_ptr, R5 MOV [R5],R5 @@ -348,7 +338,7 @@ __txm_module_manager_user_mode_entry #endif MOV.L 172[R5], R5 // Pickup module thread stack pointer MVTC R5, USP // Set stack pointer - + // USP is set for an RTS, need to set for RTE to set User mode in PSW. // Push return address on SP @@ -359,21 +349,21 @@ __txm_module_manager_user_mode_entry BSET #20,R5 MOV.L R5,4[SP] RTE - + // Fill rest of page with NOPs. NOP NOP NOP NOP - + NOP NOP NOP NOP - + NOP NOP NOP NOP - + END diff --git a/ports_module/rxv2/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/rxv2/iar/module_manager/src/tx_thread_stack_build.s index be33d407..1d8f4593 100644 --- a/ports_module/rxv2/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/rxv2/iar/module_manager/src/tx_thread_stack_build.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -55,26 +55,14 @@ ;/* */ ;/* _tx_thread_create Create thread service */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), and */ -;/* removed unnecessary stack */ -;/* type placement, */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.10 */ -;/* */ ;/**************************************************************************/ public __tx_thread_stack_build __tx_thread_stack_build: ; -; +; ; /* Build an interrupt frame. The form of the fake interrupt stack ; on the Renesas RX should look like the following after it is built: -; +; ; Stack Top: ACC0 ; ACC1 ; R6 @@ -137,11 +125,11 @@ __tx_thread_stack_build: MOV.L R4,[-R3] ; /* Setup stack pointer. */ -; thread_ptr -> tx_thread_stack_ptr = R1; +; thread_ptr -> tx_thread_stack_ptr = R1; MOV.L R3, 8[R1] ; Store initial SP in thread control block RTS - + ;} END diff --git a/ports_module/rxv2/iar/module_manager/src/tx_thread_system_return.s b/ports_module/rxv2/iar/module_manager/src/tx_thread_system_return.s index 714e1276..2c2021f6 100644 --- a/ports_module/rxv2/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/rxv2/iar/module_manager/src/tx_thread_system_return.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -20,7 +20,7 @@ ;/**************************************************************************/ section .text:CODE:ROOT - + ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ @@ -54,14 +54,6 @@ ;/* */ ;/* ThreadX components */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-31-2020 William E. Lamie Initial Version 6.1.3 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* */ ;/**************************************************************************/ public __tx_thread_system_return diff --git a/ports_module/rxv2/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/rxv2/iar/module_manager/src/tx_timer_interrupt.s index 1b736519..cb79535a 100644 --- a/ports_module/rxv2/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/rxv2/iar/module_manager/src/tx_timer_interrupt.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -73,18 +73,6 @@ SWI0 EQU 0x872E0 ;/* */ ;/* interrupt vector */ ;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 12-30-2020 William E. Lamie Initial Version 6.1.3 */ -;/* 10-15-2021 William E. Lamie Modified comment(s), */ -;/* resulting in version 6.1.9 */ -;/* 01-31-2022 William E. Lamie Modified comment(s), and */ -;/* added missing thread */ -;/* preemption logic, */ -;/* resulting in version 6.1.10 */ -;/* */ ;/**************************************************************************/ public __tx_timer_interrupt @@ -147,14 +135,14 @@ __tx_timer_no_time_slice: MOV.L [R2+], R1 ; Pickup timer list entry, _tx_timer_current_ptr++ CMP #0, R1 ; Is timer pointer NULL? BEQ __tx_timer_no_timer ; Yes, no timer has expired - + ; ; /* Set expiration flag. */ ; _tx_timer_expired = TX_TRUE; ; MOV.L #__tx_timer_expired,R2 ; Build address of expired flag MOV.L #1, R1 ; Build expired value - MOV.L R1, [R2] + MOV.L R1, [R2] BRA __tx_timer_done ; Finished with timer processing ; ; } @@ -165,7 +153,7 @@ __tx_timer_no_timer: ; /* No timer expired, increment the timer pointer. */ ; _tx_timer_current_ptr++; ; -; /* R2 already contains __tx_timer_current_ptr++ */ +; /* R2 already contains __tx_timer_current_ptr++ */ ; ; /* Check for wrap-around. */ ; if (_tx_timer_current_ptr == _tx_timer_list_end) @@ -184,9 +172,9 @@ __tx_timer_no_timer: ; } ; __tx_timer_skip_wrap: - MOV.L #__tx_timer_current_ptr,R1 + MOV.L #__tx_timer_current_ptr,R1 MOV.L R2, [R1] ; Store in updated pointer in _tx_timer_current_ptr - + __tx_timer_done: ; ; /* See if anything has expired. */ @@ -220,14 +208,14 @@ __tx_timer_dont_activate: ; /* Did time slice expire? */ ; if (_tx_timer_expired_time_slice) ; { -; +; MOV.L #__tx_timer_expired_time_slice, R1 ; Pickup time-slice expired flag addr MOV.L [R1], R1 ; Pickup actual flag CMP #0,R1 ; Has time-slice expired? BEQ __tx_timer_not_ts_expiration ; No, skip time-slice expiration ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BSR __tx_thread_time_slice ; Call time-slice processing diff --git a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_alignment_adjust.c index a12e5386..c14c1715 100644 --- a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* Initial thread stack frame */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, diff --git a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_external_memory_enable.c index 25d1ea2b..f407249a 100644 --- a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,12 +65,6 @@ /* */ /* Application code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, @@ -106,7 +101,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Invalid module pointer. */ return(TX_PTR_ERROR); } - + /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { @@ -116,7 +111,7 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if the module is not ready. */ return(TX_START_ERROR); } - + /* Check if preamble ext/shared mem property bit set. */ module_preamble = module_instance -> txm_module_instance_preamble_ptr; if(!(module_preamble -> txm_module_preamble_property_flags & TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) @@ -127,24 +122,24 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return error if bit not set. */ return(TXM_MODULE_INVALID_PROPERTIES); } - + /* Start address must be 16-byte aligned. */ address = (ULONG) start_address; if(address != (address & 0xFFFFFFF0)) { /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return alignment error. */ return(TXM_MODULE_ALIGNMENT_ERROR); } - + /* Check length. */ - + /* At this point, we have a valid address and length. */ /* Build region start page register. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address & 0xFFFFFFF0; - + /* Check for valid attributes. */ if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_EXECUTE) { @@ -158,17 +153,17 @@ TXM_MODULE_PREAMBLE *module_preamble; { attributes_check |= TXM_MODULE_MANAGER_ATTRIBUTE_READ_MPU_BIT; } - + /* Build region end page register with attributes, OR in the Valid bit. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = ((address + length - 1) & 0xFFFFFFF0) | attributes_check | 0x01; - + /* Save address and length in module. */ module_instance -> txm_module_instance_shared_memory_address = address; module_instance -> txm_module_instance_shared_memory_length = length; - + /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index 4cc5159e..0ff6baf2 100644 --- a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ TXM_MODULE_MANAGER_FAULT_INFO /* */ /* Fault handler */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) { @@ -89,7 +84,7 @@ TX_THREAD *thread_ptr; /* Initialize the module instance pointer to NULL. */ module_instance_ptr = TX_NULL; - + /* Is there a thread? */ if (thread_ptr) { @@ -99,7 +94,7 @@ TX_THREAD *thread_ptr; /* Terminate the current thread. */ _tx_thread_terminate(_tx_thread_current_ptr); } - + /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { diff --git a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index 405c049f..7fe88dfe 100644 --- a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,18 +67,12 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; - + /* Return success. */ return(TX_SUCCESS); } diff --git a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_setup_mpu_registers.c b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_setup_mpu_registers.c index 9175331b..183f38ae 100644 --- a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_setup_mpu_registers.c +++ b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_setup_mpu_registers.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* _txm_module_manager_thread_create */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 Scott Larson Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _txm_module_manager_setup_mpu_registers(TXM_MODULE_INSTANCE *module_instance) { @@ -73,34 +68,34 @@ ULONG region_end_page_register; region_start_page_register = (ULONG) _txm_module_manager_user_mode_entry; region_start_page_register = region_start_page_register & 0xFFFFFFF0; module_instance -> txm_module_instance_mpu_registers[0] = region_start_page_register; - /* Region 0 End page is 2 pages away (for a total of 3 pages). + /* Region 0 End page is 2 pages away (for a total of 3 pages). * Set reading permitted, writing prohibited, execution permitted, enable region. */ module_instance -> txm_module_instance_mpu_registers[1] = (region_start_page_register + 0x20) | 0x0B; - + /* Place the trampoline protection in the MPU registers */ RSPAGE0 = module_instance -> txm_module_instance_mpu_registers[0]; REPAGE0 = module_instance -> txm_module_instance_mpu_registers[1]; - + /* Setup region 1 for code area. */ /* Set reading permitted, writing prohibited, execution permitted, enable region. */ - region_start_page_register = (ULONG) module_instance -> txm_module_instance_code_start; + region_start_page_register = (ULONG) module_instance -> txm_module_instance_code_start; region_size = (ULONG) module_instance -> txm_module_instance_code_size; - + region_end_page_register = (region_start_page_register + region_size - 1) & 0xFFFFFFF0; region_start_page_register = region_start_page_register & 0xFFFFFFF0; - + module_instance -> txm_module_instance_mpu_registers[2] = region_start_page_register; module_instance -> txm_module_instance_mpu_registers[3] = region_end_page_register | 0x0B; - + /* Setup region 2 for data area. */ /* Set reading permitted, writing permitted, execution prohibited, enable region. */ - region_start_page_register = (ULONG) module_instance -> txm_module_instance_data_start; + region_start_page_register = (ULONG) module_instance -> txm_module_instance_data_start; region_size = (ULONG) module_instance -> txm_module_instance_data_size; - + region_end_page_register = (region_start_page_register + region_size - 1) & 0xFFFFFFF0; region_start_page_register = region_start_page_register & 0xFFFFFFF0; - + module_instance -> txm_module_instance_mpu_registers[4] = region_start_page_register; module_instance -> txm_module_instance_mpu_registers[5] = region_end_page_register | 0x0D; - + } diff --git a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_thread_stack_build.s index 9cf9fa14..fa5bf71d 100644 --- a/ports_module/rxv2/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/rxv2/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,13 +54,6 @@ /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 01-31-2022 Scott Larson Initial Version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) // { @@ -68,7 +62,7 @@ __txm_module_manager_thread_stack_build: /* Build an interrupt frame. The form of the fake interrupt stack on the Renesas RX should look like the following after it is built: - + Stack Top: 1 Interrupt stack frame type ACC0 ACC1 @@ -103,9 +97,9 @@ __txm_module_manager_thread_stack_build: BMC #20,R4 // if user mode, set mode bit of initial PSW MOV.L R4, [-R3] // initial PSW MOV.L R2, [-R3] // initial PC - + MOV.L 8[R1], R4 // Pickup thread entry info pointer, which is in the stack pointer position of the thread control block. - // It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this + // It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this // function with the actual, initial stack pointer. MOV.L R4,[-R3] // initial R2, which is the module entry information. MOV.L R1,[-R3] // initial R1, which is the thread control block. diff --git a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/arc.c b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/arc.c index c5a58751..7ac8ad29 100644 --- a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/arc.c +++ b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/arc.c @@ -79,7 +79,7 @@ void arc_cpu_init(void) { extern char VECT_TABLE_BASE[]; // from sample_threadx.lcf _sr((unsigned int)VECT_TABLE_BASE, AUX_IVT_BASE); - + /* 0xc000_0000 in uncached */ _sr(0xc0000000, AUX_VOL); @@ -141,7 +141,7 @@ void arc_ici_handler(void) __mcip_cmd(CMD_ICI_CHECK_SOURCE, 0); - + senders = _lr(AUX_MCIP_READBK); /* 1,2,4,8... */ /* No support interrupt coalescing yet */ diff --git a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/sample_threadx.c b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/sample_threadx.c index 107b90a7..336ab326 100644 --- a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -87,40 +87,40 @@ CHAR *pointer = TX_NULL; /* Create the main thread. */ tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -128,23 +128,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -246,11 +246,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -309,7 +309,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -362,7 +362,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/sample_threadx.cmd b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/sample_threadx.cmd index ac4f3a6f..13cc8e3a 100644 --- a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/sample_threadx.cmd +++ b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/sample_threadx.cmd @@ -1,25 +1,25 @@ // // This is the linker script example (SRV3-style). // (c) Synopsys, 2013 -// +// // -//number of exceptions and interrupts +//number of exceptions and interrupts NUMBER_OF_EXCEPTIONS = 16;//it is fixed (16) NUMBER_OF_INTERRUPTS = 5;//depends on HW configuration //define Interrupt Vector Table size IVT_SIZE_ITEMS = (NUMBER_OF_EXCEPTIONS + NUMBER_OF_INTERRUPTS);//the total IVT size (in "items") -IVT_SIZE_BYTES = IVT_SIZE_ITEMS * 4;//in bytes +IVT_SIZE_BYTES = IVT_SIZE_ITEMS * 4;//in bytes //define ICCM and DCCM locations MEMORY { - + ICCM: ORIGIN = 0x00000000, LENGTH = 128K DCCM: ORIGIN = 0x80000000, LENGTH = 128K } - -//define sections and groups + +//define sections and groups SECTIONS { GROUP: { VECT_TABLE_BASE = .; @@ -28,18 +28,18 @@ SECTIONS { ___ivt1 = .; * (.ivt) ___ivt2 = .; - // Make the IVT at least IVT_SIZE_BYTES + // Make the IVT at least IVT_SIZE_BYTES . += (___ivt2 - ___ivt1 < IVT_SIZE_BYTES) ? (IVT_SIZE_BYTES - (___ivt2 - ___ivt1)) : 0; } .ivh (TEXT) : // Interrupt handlers - + //TEXT sections .text? : { *('.text$crt*') } * (TEXT): {} //Literals * (LIT): {} } > ICCM - + GROUP: { //data sections .sdata?: {} diff --git a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/tx_initialize_low_level.s b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/tx_initialize_low_level.s index 60fa4f6f..ec940638 100644 --- a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/tx_initialize_low_level.s +++ b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/tx_initialize_low_level.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -24,21 +24,21 @@ ; ; ; /* Define section for placement after all linker allocated RAM memory. This -; is used to calculate the first free address that is passed to +; is used to calculate the first free address that is passed to ; tx_appication_define, soley for the ThreadX application's use. */ ; .section ".free_memory","aw" .align 4 .global _tx_first_free_address _tx_first_free_address: - .space 4 + .space 4 ; ; .text -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_initialize_low_level SMP/ARC_HS/MetaWare */ ;/* 6.1 */ ;/* AUTHOR */ @@ -46,40 +46,34 @@ _tx_first_free_address: ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) ;{ .global _tx_initialize_low_level - .type _tx_initialize_low_level, @function + .type _tx_initialize_low_level, @function _tx_initialize_low_level: ; @@ -108,7 +102,7 @@ _tx_initialize_low_level: ; ; /* Define default vector table entries. */ ; - .global _tx_memory_error + .global _tx_memory_error _tx_memory_error: flag 1 nop @@ -116,7 +110,7 @@ _tx_memory_error: nop b _tx_memory_error - .global _tx_instruction_error + .global _tx_instruction_error _tx_instruction_error: flag 1 nop @@ -124,7 +118,7 @@ _tx_instruction_error: nop b _tx_instruction_error - .global _tx_ev_machine_check + .global _tx_ev_machine_check _tx_ev_machine_check: flag 1 nop @@ -132,7 +126,7 @@ _tx_ev_machine_check: nop b _tx_ev_machine_check - .global _tx_ev_tblmiss_inst + .global _tx_ev_tblmiss_inst _tx_ev_tblmiss_inst: flag 1 nop @@ -140,7 +134,7 @@ _tx_ev_tblmiss_inst: nop b _tx_ev_tblmiss_inst - .global _tx_ev_tblmiss_data + .global _tx_ev_tblmiss_data _tx_ev_tblmiss_data: flag 1 nop @@ -148,7 +142,7 @@ _tx_ev_tblmiss_data: nop b _tx_ev_tblmiss_data - .global _tx_ev_protection_viol + .global _tx_ev_protection_viol _tx_ev_protection_viol: flag 1 nop @@ -156,7 +150,7 @@ _tx_ev_protection_viol: nop b _tx_ev_protection_viol - .global _tx_ev_privilege_viol + .global _tx_ev_privilege_viol _tx_ev_privilege_viol: flag 1 nop @@ -164,7 +158,7 @@ _tx_ev_privilege_viol: nop b _tx_ev_privilege_viol - .global _tx_ev_software_int + .global _tx_ev_software_int _tx_ev_software_int: flag 1 nop @@ -172,7 +166,7 @@ _tx_ev_software_int: nop b _tx_ev_software_int - .global _tx_ev_trap + .global _tx_ev_trap _tx_ev_trap: flag 1 nop @@ -180,7 +174,7 @@ _tx_ev_trap: nop b _tx_ev_trap - .global _tx_ev_extension + .global _tx_ev_extension _tx_ev_extension: flag 1 nop @@ -188,7 +182,7 @@ _tx_ev_extension: nop b _tx_ev_extension - .global _tx_ev_divide_by_zero + .global _tx_ev_divide_by_zero _tx_ev_divide_by_zero: flag 1 nop @@ -196,7 +190,7 @@ _tx_ev_divide_by_zero: nop b _tx_ev_divide_by_zero - .global _tx_ev_dc_error + .global _tx_ev_dc_error _tx_ev_dc_error: flag 1 nop @@ -204,7 +198,7 @@ _tx_ev_dc_error: nop b _tx_ev_dc_error - .global _tx_ev_maligned + .global _tx_ev_maligned _tx_ev_maligned: flag 1 nop @@ -212,7 +206,7 @@ _tx_ev_maligned: nop b _tx_ev_maligned - .global _tx_unsued_0 + .global _tx_unsued_0 _tx_unsued_0: flag 1 nop @@ -220,7 +214,7 @@ _tx_unsued_0: nop b _tx_unsued_0 - .global _tx_unused_1 + .global _tx_unused_1 _tx_unused_1: flag 1 nop @@ -228,7 +222,7 @@ _tx_unused_1: nop b _tx_unused_1 - .global _tx_timer_0 + .global _tx_timer_0 _tx_timer_0: ; ; /* By default, setup Timer 0 as the ThreadX timer interrupt. */ @@ -257,7 +251,7 @@ _tx_timer_0: ; nop ; b _tx_timer_0 - .global _tx_timer_1 + .global _tx_timer_1 _tx_timer_1: flag 1 nop @@ -265,7 +259,7 @@ _tx_timer_1: nop b _tx_timer_1 - .global _tx_undefined_0 + .global _tx_undefined_0 _tx_undefined_0: flag 1 nop @@ -295,7 +289,7 @@ _tx_smp_inter_core: ; nop ; b _tx_undefined_1 - .global _tx_undefined_2 + .global _tx_undefined_2 _tx_undefined_2: flag 1 nop diff --git a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/vectors.s b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/vectors.s index d1fbfa27..3ff8ae37 100644 --- a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/vectors.s +++ b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/vectors.s @@ -1,4 +1,4 @@ - + .file "vectors.s" .section .ivt,text ;; This directive forces this section to stay resident even if stripped out by the -zpurgetext linker option diff --git a/ports_smp/arc_hs_smp/metaware/inc/tx_port.h b/ports_smp/arc_hs_smp/metaware/inc/tx_port.h index 09072ae2..dd223a9c 100644 --- a/ports_smp/arc_hs_smp/metaware/inc/tx_port.h +++ b/ports_smp/arc_hs_smp/metaware/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h SMP/ARC_HS/MetaWare */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h SMP/ARC_HS/MetaWare */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -57,9 +49,9 @@ #define TX_PORT_H -/* Remove volatile for ThreadX source on the ARC. This is because the ARC - compiler generates different non-cache r/w access when using volatile - that is different from the assembly language access of the same +/* Remove volatile for ThreadX source on the ARC. This is because the ARC + compiler generates different non-cache r/w access when using volatile + that is different from the assembly language access of the same global variables in ThreadX. */ #ifdef TX_SOURCE_CODE @@ -106,12 +98,12 @@ /* Define ThreadX SMP initialization macro. */ -#define TX_PORT_SPECIFIC_PRE_INITIALIZATION +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION /* Define ThreadX SMP pre-scheduler initialization. */ -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION /* Enable the inter-core interrupt logic. */ @@ -151,7 +143,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -164,7 +156,7 @@ #include -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -200,19 +192,19 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 2048 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARC HS port. */ +/* Define various constants for the ThreadX ARC HS port. */ #define TX_INT_ENABLE 0x0000001F /* Enable all interrupts */ -#define TX_INT_DISABLE_MASK 0x00000000 /* Disable all interrupts */ +#define TX_INT_DISABLE_MASK 0x00000000 /* Disable all interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -252,7 +244,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -266,15 +258,15 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ #define TX_THREAD_EXTENSION_0 VOID *__mw_threadx_tls; \ int __mw_errnum; \ VOID (*__mw_thread_exit)(struct TX_THREAD_STRUCT *); -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -288,11 +280,11 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -301,16 +293,16 @@ ULONG _tx_misra_time_stamp_get(VOID); #if __HIGHC__ -/* The MetaWare thread safe C/C++ runtime library needs space to +/* The MetaWare thread safe C/C++ runtime library needs space to store thread specific information. In addition, a function pointer - is also supplied so that certain thread-specific resources may be + is also supplied so that certain thread-specific resources may be released upon thread termination and/or thread completion. */ #define TX_THREAD_CREATE_EXTENSION(thread_ptr) \ thread_ptr -> __mw_threadx_tls = 0; \ thread_ptr -> __mw_errnum = 0; \ - thread_ptr -> __mw_thread_exit = TX_NULL; -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) + thread_ptr -> __mw_thread_exit = TX_NULL; +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) \ if (thread_ptr -> __mw_thread_exit) \ (thread_ptr -> __mw_thread_exit) (thread_ptr); @@ -320,10 +312,10 @@ ULONG _tx_misra_time_stamp_get(VOID); #else -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) -#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) -#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) #endif @@ -360,22 +352,22 @@ struct TX_THREAD_STRUCT; typedef struct TX_THREAD_SMP_PROTECT_STRUCT { ULONG tx_thread_smp_protect_in_force; - struct TX_THREAD_STRUCT * + struct TX_THREAD_STRUCT * tx_thread_smp_protect_thread; ULONG tx_thread_smp_protect_core; ULONG tx_thread_smp_protect_count; - + /* Implementation specific information follows. */ - + ULONG tx_thread_smp_protect_get_caller; ULONG tx_thread_smp_protect_status32; ULONG tx_thread_smp_protect_release_caller; } TX_THREAD_SMP_PROTECT; -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -402,8 +394,8 @@ typedef struct TX_THREAD_SMP_PROTECT_STRUCT /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX SMP/ARC_HS/MetaWare Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP/ARC_HS/MetaWare Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/arc_hs_smp/metaware/readme_threadx.txt b/ports_smp/arc_hs_smp/metaware/readme_threadx.txt index 23d477fa..b12aa2f2 100644 --- a/ports_smp/arc_hs_smp/metaware/readme_threadx.txt +++ b/ports_smp/arc_hs_smp/metaware/readme_threadx.txt @@ -4,15 +4,15 @@ 1. Open the ThreadX SMP Workspace -In order to build the ThreadX SMP library and the ThreadX SMP demonstration -first load the Azure RTOS Workspace, which is located inside the "example_build" -directory. +In order to build the ThreadX SMP library and the ThreadX SMP demonstration +first load the Azure RTOS Workspace, which is located inside the "example_build" +directory. 2. Building the ThreadX SMP run-time Library -Building the ThreadX SMP library is easy; simply select the ThreadX library project -file "tx" and then select the build button. You should now observe the compilation +Building the ThreadX SMP library is easy; simply select the ThreadX library project +file "tx" and then select the build button. You should now observe the compilation and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP library file tx.a. @@ -21,52 +21,52 @@ library file tx.a. The ThreadX demonstration is designed to execute under the MetaWare ARC HS SMP simulation. The instructions that follow describe how to get the ThreadX SMP -demonstration running. +demonstration running. -Building the demonstration is easy; simply select the demonstration project file -"sample_threadx." At this point, select the build button and observe the -compilation, assembly, and linkage of the ThreadX SMP demonstration application. +Building the demonstration is easy; simply select the demonstration project file +"sample_threadx." At this point, select the build button and observe the +compilation, assembly, and linkage of the ThreadX SMP demonstration application. After the demonstration is built, execute the "run_threadx_smp_demo.bat" batch file to invoke and load the ThreadX SMP demonstration. -You are now ready to execute the ThreadX demonstration system. Select -breakpoints and data watches to observe the execution of the sample_threadx.c +You are now ready to execute the ThreadX demonstration system. Select +breakpoints and data watches to observe the execution of the sample_threadx.c SMP application. 4. System Initialization -The system entry point using the MetaWare tools is at the label _start. -This is defined within the crt1.s file supplied by MetaWare. In addition, +The system entry point using the MetaWare tools is at the label _start. +This is defined within the crt1.s file supplied by MetaWare. In addition, this is where all static and global preset C variable initialization processing is called from. After the MetaWare startup function completes, ThreadX initialization is called. The main initialization function is _tx_initialize_low_level and -is located in the file tx_initialize_low_level.s. This function is -responsible for setting up various system data structures, and interrupt +is located in the file tx_initialize_low_level.s. This function is +responsible for setting up various system data structures, and interrupt vectors. -By default free memory is assumed to start at the section .free_memory -which is referenced in tx_initialize_low_level.s and located in the -linker control file after all the linker defined RAM addresses. This is +By default free memory is assumed to start at the section .free_memory +which is referenced in tx_initialize_low_level.s and located in the +linker control file after all the linker defined RAM addresses. This is the address passed to the application definition function, tx_application_define. 5. Register Usage and Stack Frames -The ARC compiler assumes that registers r0-r12 are scratch registers for -each function. All other registers used by a C function must be preserved -by the function. ThreadX takes advantage of this in situations where a -context switch happens as a result of making a ThreadX service call (which -is itself a C function). In such cases, the saved context of a thread is +The ARC compiler assumes that registers r0-r12 are scratch registers for +each function. All other registers used by a C function must be preserved +by the function. ThreadX takes advantage of this in situations where a +context switch happens as a result of making a ThreadX service call (which +is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -115,26 +115,26 @@ associated thread control block TX_THREAD. 0x9C bta 0xA0 point of interrupt 0xA4 STATUS32 - + 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make it run faster, you can change the build_threadx.bat -file to remove the -g option and enable all compiler optimizations. +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat +file to remove the -g option and enable all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for the -ARC HS processor, including support for software interrupts and fast +ARC HS processor, including support for software interrupts and fast hardware interrupts. 7.1 Software Interrupt Handling @@ -148,25 +148,25 @@ _tx_interrupt_x: st blink, [sp, 16] ; Save blink (blink must be saved before _tx_thread_context_save) bl _tx_thread_context_save ; Save interrupt context ; -; /* Application ISR processing goes here! Your ISR can be written in +; /* Application ISR processing goes here! Your ISR can be written in ; assembly language or in C. If it is written in C, you must allocate -; 16 bytes of stack space before it is called. This must also be -; recovered once your C ISR return. An example of this is shown below. +; 16 bytes of stack space before it is called. This must also be +; recovered once your C ISR return. An example of this is shown below. ; ; If the ISR is written in assembly language, only the compiler scratch -; registers are available for use without saving/restoring (r0-r12). +; registers are available for use without saving/restoring (r0-r12). ; If use of additional registers are required they must be saved and ; restored. */ ; bl.d your_ISR_written_in_C ; Call an ISR written in C sub sp, sp, 16 ; Allocate stack space (delay slot) add sp, sp, 16 ; Recover stack space - + ; b _tx_thread_context_restore ; Restore interrupt context -The application handles interrupts directly, which necessitates all register +The application handles interrupts directly, which necessitates all register preservation by the application's ISR. ISRs that do not use the ThreadX _tx_thread_context_save and _tx_thread_context_restore routines are not allowed access to the ThreadX API. In addition, custom application ISRs @@ -175,16 +175,16 @@ should be higher priority than all ThreadX-managed ISRs. 8. ThreadX Timer Interrupt -ThreadX SMP requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer -interrupt source, these services are not functional but the remainder of +ThreadX SMP requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of ThreadX will still run. By default, the ThreadX timer interrupt is mapped to the ARC HS auxiliary timer 0, which generates low priority interrupts on interrupt vector 16. -It is easy to change the timer interrupt source and priority by changing the +It is easy to change the timer interrupt source and priority by changing the setup code in tx_initialize_low_level.s. In addition, the ThreadX SMP timer -is mapped to core 0. To change to another core, please edit arc.c and +is mapped to core 0. To change to another core, please edit arc.c and _tx_timer_interrupt.s. Only one core should be used as the ThreadX SMP periodic timer interrupt source. diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_context_restore.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_context_restore.s index 4b50af87..c362b697 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_context_restore.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -31,10 +31,10 @@ ;#include "tx_timer.h" ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_context_restore SMP/ARC_HS/MetaWare */ ;/* 6.1 */ ;/* AUTHOR */ @@ -42,39 +42,33 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) ;{ .global _tx_thread_context_restore - .type _tx_thread_context_restore, @function + .type _tx_thread_context_restore, @function _tx_thread_context_restore: ; ; /* Note: it is assumed that the stack pointer is in the same position now as @@ -105,7 +99,7 @@ _tx_thread_context_restore: .endif asl r3, r3, 2 ; Build index into core arrays mov r0, _tx_thread_system_state ; Build address of system state - add r1, r0, r3 ; + add r1, r0, r3 ; ld r0, [r1] ; Pickup system state sub r0, r0, 1 ; Decrement the system state st r0, [r1] ; Store the new system state @@ -113,7 +107,7 @@ _tx_thread_context_restore: ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; @@ -124,10 +118,10 @@ __tx_thread_nested_restore: sr r0, [LP_START] ; Restore LP_START ld r4, [sp, 8] ; Recover LP_END sr r4, [LP_END] ; Restore LP_END - ld r2, [sp, 12] ; Recover LP_COUNT + ld r2, [sp, 12] ; Recover LP_COUNT mov LP_COUNT, r2 .endif - + ld r2, [sp, 156] ; Pickup BTA sr r2, [BTA] ; Recover BTA .ifdef TX_ENABLE_ACC @@ -148,7 +142,7 @@ __tx_thread_nested_restore: ld r2, [sp, 124] ; Recover r2 ld r1, [sp, 128] ; Recover r1 ld r0, [sp, 132] ; Recover r0 - add sp, sp, 160 ; Recover interrupt stack frame + add sp, sp, 160 ; Recover interrupt stack frame rtie ; Return from interrupt ; ; @@ -156,12 +150,12 @@ __tx_thread_nested_restore: __tx_thread_not_nested_restore: ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr[core]) && (_tx_thread_current_ptr[core] == _tx_thread_execute_ptr[core]) +; else if (((_tx_thread_current_ptr[core]) && (_tx_thread_current_ptr[core] == _tx_thread_execute_ptr[core]) ; || (_tx_thread_preempt_disable)) ; { ; mov r1, _tx_thread_current_ptr ; Build current thread pointer address - add r1, r1, r3 ; + add r1, r1, r3 ; ld r0, [r1] ; Pickup current thread pointer mov r2, _tx_thread_smp_protection ; Build protection address sub.f 0, r0, 0 ; Set condition codes @@ -171,12 +165,12 @@ __tx_thread_not_nested_restore: and r5, r4, r5 ; See if there are any other interrupts present brne r4, r5, __tx_thread_no_preempt_restore ; If more interrupts, just return to the point of interrupt mov r4, _tx_thread_execute_ptr ; Build address of next thread to execute for this core - add r4, r4, r3 ; + add r4, r4, r3 ; ld r4, [r4] ; Pickup next thread to execute ld r2, [r2, 8] ; Pickup core that has protection breq r0, r4, __tx_thread_no_preempt_restore ; If equal, simply restore executing thread ld r5, [gp, _tx_thread_preempt_disable@sda] ; Pickup preempt disable flag - asr r4, r3, 2 ; Shift core index back down for core ID + asr r4, r3, 2 ; Shift core index back down for core ID brne r2, r4, __tx_thread_preempt_restore ; If the core doesn't have protection, preempt thread without looking at preempt disable flag breq r5, 0, __tx_thread_preempt_restore ; If preempt disable not set, preempt executing thread ; @@ -198,7 +192,7 @@ __tx_thread_no_preempt_restore: sr r0, [LP_START] ; Restore LP_START ld r4, [sp, 8] ; Recover LP_END sr r4, [LP_END] ; Restore LP_END - ld r2, [sp, 12] ; Recover LP_COUNT + ld r2, [sp, 12] ; Recover LP_COUNT mov LP_COUNT, r2 .endif @@ -256,7 +250,7 @@ __tx_preempt_save_done: ; { ; mov r5, _tx_timer_time_slice ; Build time-slice address - add r5, r5, r3 ; + add r5, r5, r3 ; ld r2, [r5] ; Pickup time-slice contents mov r7, 0 ; Build clear/NULL value breq r2, 0, __tx_thread_dont_save_ts ; No time-slice, don't need to save it diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_context_save.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_context_save.s index a54c4435..6014bdb2 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_context_save.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -31,10 +31,10 @@ ;#include "tx_timer.h" ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_context_save SMP/ARC_HS/MetaWare */ ;/* 6.1 */ ;/* AUTHOR */ @@ -42,38 +42,32 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) ;{ .global _tx_thread_context_save - .type _tx_thread_context_save, @function + .type _tx_thread_context_save, @function _tx_thread_context_save: ; ; /* Upon entry to this routine, it is assumed that an interrupt stack frame @@ -96,7 +90,7 @@ _tx_thread_context_save: .endif asl r3, r3, 2 ; Build index into core arrays mov r0, _tx_thread_system_state ; Build address of system state - add r1, r0, r3 ; + add r1, r0, r3 ; ld r0, [r1] ; Pickup system state breq r0, 0, __tx_thread_not_nested_save ; If 0, we are not in a nested ; condition @@ -160,7 +154,7 @@ __tx_thread_not_nested_save: add r0, r0, 1 ; Increment the nested interrupt count st r0, [r1] ; Update system state mov r2, _tx_thread_current_ptr ; Build address of current thread pointer - add r2, r2, r3 ; + add r2, r2, r3 ; ld r1, [r2] ; Pickup current thread pointer st r12, [sp, 84] ; Save r12 st r11, [sp, 88] ; Save r11 @@ -210,7 +204,7 @@ __tx_thread_not_nested_save: ; sp = _tx_thread_system_stack_ptr[core]; ; mov r1, _tx_thread_system_stack_ptr ; Build address of system stack pointer - add r1, r1, r3 ; + add r1, r1, r3 ; j_s.d [blink] ; Return to calling ISR ld sp, [r1] ; Switch to system stack ; @@ -242,11 +236,11 @@ __tx_thread_idle_system_save: and r1, r0, r1 ; See if there are any other interrupts present brne r0, r1, __tx_thread_nested_save ; If more interrupts, go into the nested interrupt save logic ; -; /* Not much to do here, just adjust the stack pointer, and return to +; /* Not much to do here, just adjust the stack pointer, and return to ; ISR processing. */ ; j_s.d [blink] ; Return to ISR - add sp, sp, 160 ; Recover stack space + add sp, sp, 160 ; Recover stack space ; ; } ;} diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_interrupt_control.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_interrupt_control.s index 9fe6e34f..f5ab8aa4 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_interrupt_control.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -28,10 +28,10 @@ ;#include "tx_thread.h" ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_interrupt_control SMP/ARC_HS/MetaWare */ ;/* 6.1 */ ;/* AUTHOR */ @@ -39,37 +39,31 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) ;{ .global _tx_thread_interrupt_control - .type _tx_thread_interrupt_control, @function + .type _tx_thread_interrupt_control, @function _tx_thread_interrupt_control: ; ; /* Pickup current interrupt lockout posture. */ diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_schedule.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_schedule.s index 8575464b..4665db5c 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_schedule.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_schedule.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -33,14 +33,14 @@ ; ; ; /* Define the lock for the ARC simulator workaround. The ARC HS SMP -; simulator does not execute cores in a lock-step fashion, i.e., a +; simulator does not execute cores in a lock-step fashion, i.e., a ; core can stall for many cycles while the other core executes. This ; does not happen on actual hardware and thus the need for a schedule -; lock is not required since: 1) ThreadX SMP will not load the same -; thread into two places on the _tx_thread_execute_list, and moving -; a thread from one entry on the _tx_thread_execute_list to another +; lock is not required since: 1) ThreadX SMP will not load the same +; thread into two places on the _tx_thread_execute_list, and moving +; a thread from one entry on the _tx_thread_execute_list to another ; is more than the 5 instructions executed between examination of the -; the _tx_thread_execute_list thread and clearing its ready bit in +; the _tx_thread_execute_list thread and clearing its ready bit in ; preparation for scheduling. */ ; .ifdef TX_ARC_SIMULATOR_WORKAROUND @@ -49,14 +49,14 @@ .type _tx_thread_schedule_lock,@object _tx_thread_schedule_lock: .word 0 - + .endif ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_schedule SMP/ARC_HS/MetaWare */ ;/* 6.1 */ ;/* AUTHOR */ @@ -64,34 +64,28 @@ _tx_thread_schedule_lock: ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr array. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr array. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -105,7 +99,7 @@ _tx_thread_schedule_restart: st r3, [r7] dmb 3 .endif - + .global _tx_thread_schedule .type _tx_thread_schedule, @function _tx_thread_schedule: @@ -128,7 +122,7 @@ _tx_thread_schedule: .endif asl r4, r1, 2 ; Build index into core arrays mov r7, _tx_thread_execute_ptr ; Pickup base of the execute thread pointer - add r7, r7, r4 ; Build address of current thread pointer + add r7, r7, r4 ; Build address of current thread pointer __tx_thread_schedule_loop: ; @@ -146,14 +140,14 @@ _continue: b _tx_thread_schedule _got_lock: .endif - + ld r0, [r7] ; Pickup next thread to execute breq r0, 0, _tx_thread_schedule_restart ; If NULL, keep looking ; ; } ; while(_tx_thread_execute_ptr[core] == TX_NULL); -; -; +; +; ; /* Now make sure the thread's ready bit is set. */ ; ld r5, [r0, 164] ; Pickup the ready bit for this thread to see if it can be executed @@ -175,7 +169,7 @@ _got_lock: ; _tx_thread_current_ptr[core] = _tx_thread_execute_ptr[core]; ; mov r7, _tx_thread_current_ptr ; Build address of current thread pointer - add r7, r7, r4 ; + add r7, r7, r4 ; st r0, [r7] ; Setup current thread pointer ; ; /* Increment the run count for this thread. */ @@ -190,7 +184,7 @@ _got_lock: ; _tx_timer_time_slice[core] = _tx_thread_current_ptr -> tx_thread_time_slice; ; mov r6, _tx_timer_time_slice ; Build address of time-slice for this core - add r6, r6, r4 ; + add r6, r6, r4 ; st r5, [r6] ; Setup time-slice ; .ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY @@ -232,8 +226,8 @@ _got_lock: ld r13, [sp, 64] ; Recover r13 ld r1, [sp, 68] ; Pickup status32 ld r30, [sp, 72] ; Recover r30 - add sp, sp, 76 ; Recover solicited stack frame - j_s.d [blink] ; Return to thread and restore flags + add sp, sp, 76 ; Recover solicited stack frame + j_s.d [blink] ; Return to thread and restore flags seti r1 ; Recover STATUS32 ; __tx_thread_schedule_int_ret: @@ -246,10 +240,10 @@ __tx_thread_schedule_int_ret: sr r0, [LP_START] ; Restore LP_START ld r1, [sp, 8] ; Recover LP_END sr r1, [LP_END] ; Restore LP_END - ld r2, [sp, 12] ; Recover LP_COUNT + ld r2, [sp, 12] ; Recover LP_COUNT mov LP_COUNT, r2 .endif - + ld r0, [sp, 156] ; Pickup saved BTA sr r0, [BTA] ; Recover BTA ld blink, [sp, 16] ; Recover blink @@ -287,8 +281,8 @@ __tx_thread_schedule_int_ret: ld r58, [sp, 140] ; Recover r58 ld r59, [sp, 144] ; Recover r59 .endif - add sp, sp, 160 ; Recover interrupt stack frame - rtie ; Return to point of interrupt + add sp, sp, 160 ; Recover interrupt stack frame + rtie ; Return to point of interrupt ; ;} ; diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_core_get.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_core_get.s index 74818227..6045c4a8 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_core_get.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_core_get.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -30,41 +30,35 @@ ;#include "tx_timer.h" */ ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_smp_core_get SMP/ARC_HS/MetaWare */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_core_get SMP/ARC_HS/MetaWare */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function gets the currently running core number and returns it.*/ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* Core ID */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX Source */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function gets the currently running core number and returns it.*/ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* Core ID */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ ;/* */ ;/**************************************************************************/ .global _tx_thread_smp_core_get @@ -79,7 +73,7 @@ _tx_thread_smp_core_get: .ifndef TX_ZERO_BASED_CORE_ID sub r0, r0, 1 ; Subtract 1 to make 0-based .else - nop ; - .endif + nop ; + .endif .end - + diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_core_preempt.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_core_preempt.s index 35968588..de293416 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_core_preempt.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_core_preempt.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -30,45 +30,39 @@ ;#include "tx_timer.h" */ ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_smp_core_preempt SMP/ARC_HS/MetaWare */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_core_preempt SMP/ARC_HS/MetaWare */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function preempts the specified core in situations where the */ -;/* thread corresponding to this core is no longer ready or when the */ -;/* core must be used for a higher-priority thread. If the specified is */ -;/* the current core, this processing is skipped since the will give up */ -;/* control subsequently on its own. */ -;/* */ -;/* INPUT */ -;/* */ -;/* core The core to preempt */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX Source */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function preempts the specified core in situations where the */ +;/* thread corresponding to this core is no longer ready or when the */ +;/* core must be used for a higher-priority thread. If the specified is */ +;/* the current core, this processing is skipped since the will give up */ +;/* control subsequently on its own. */ +;/* */ +;/* INPUT */ +;/* */ +;/* core The core to preempt */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ ;/* */ ;/**************************************************************************/ .global _tx_thread_smp_core_preempt @@ -79,9 +73,9 @@ _tx_thread_smp_core_preempt: bl.d arc_ici_send ; Call ARC inter-core interrupt routine sub sp, sp, 16 ; Allocate stack space (delay slot) add sp, sp, 16 ; Recover stack space - ld blink, [sp] ; Recover return address + ld blink, [sp] ; Recover return address j_s.d [blink] ; Return to caller with delay slot add sp, sp, 16 ; Recover stack space .end - + diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_current_state_get.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_current_state_get.s index 0d26cb49..eed3b559 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_current_state_get.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_current_state_get.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -30,41 +30,35 @@ ;#include "tx_timer.h" */ ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_smp_current_state_get SMP/ARC_HS/MetaWare */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_current_state_get SMP/ARC_HS/MetaWare */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is gets the current state of the calling core. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX Components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is gets the current state of the calling core. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Components */ ;/* */ ;/**************************************************************************/ .global _tx_thread_smp_current_state_get @@ -79,10 +73,10 @@ _tx_thread_smp_current_state_get: .endif asl r0, r0, 2 ; Build index into _tx_thread_system_state mov r1, _tx_thread_system_state ; Build address of _tx_thread_system_state - add r1, r1, r0 ; + add r1, r1, r0 ; ld r0, [r1] ; Pickup current system state for this core j_s.d [blink] ; Return to caller with delay slot seti r2 ; Restore previous interrupt state - + .end diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_current_thread_get.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_current_thread_get.s index cb981dd0..f66b3081 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_current_thread_get.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_current_thread_get.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -30,41 +30,35 @@ ;#include "tx_timer.h" */ ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_smp_current_thread_get SMP/ARC_HS/MetaWare */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_current_thread_get SMP/ARC_HS/MetaWare */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is gets the current thread of the calling core. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX Components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is gets the current thread of the calling core. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Components */ ;/* */ ;/**************************************************************************/ .global _tx_thread_smp_current_thread_get @@ -79,11 +73,11 @@ _tx_thread_smp_current_thread_get: .endif asl r0, r0, 2 ; Build index into _tx_thread_current_ptr mov r1, _tx_thread_current_ptr ; Build address of _tx_thread_current_ptr - add r1, r1, r0 ; + add r1, r1, r0 ; ld r0, [r1] ; Pickup current thread for this core j_s.d [blink] ; Return to caller with delay slot seti r2 ; Restore previous interrupt state .end - + diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_initialize_wait.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_initialize_wait.s index 5ec92e24..9ce01602 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_initialize_wait.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_initialize_wait.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -30,43 +30,37 @@ ;#include "tx_timer.h" */ ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_smp_initialize_wait SMP/ARC_HS/MetaWare */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_initialize_wait SMP/ARC_HS/MetaWare */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is the place where additional cores wait until */ -;/* initialization is complete before they enter the thread scheduling */ -;/* loop. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Hardware */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is the place where additional cores wait until */ +;/* initialization is complete before they enter the thread scheduling */ +;/* loop. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Hardware */ ;/* */ ;/**************************************************************************/ .global _tx_thread_smp_initialize_wait @@ -86,15 +80,15 @@ _tx_thread_smp_initialize_wait: .endif asl r0, r0, 2 ; Build index into _tx_thread_system_state mov r1, _tx_thread_system_stack_ptr ; Build system stack pointer address - add r1, r1, r0 ; + add r1, r1, r0 ; st sp, [r1] ; Save this core's system address - + mov r1, _tx_thread_system_state ; Build system state pointer address - add r1, r1, r0 ; - mov r3, 0xF0F0F0F0 ; Build TX_INITIALIZE_IN_PROGRESS flag -wait_for_initialize: + add r1, r1, r0 ; + mov r3, 0xF0F0F0F0 ; Build TX_INITIALIZE_IN_PROGRESS flag +wait_for_initialize: ld r0, [r1] ; Pickup current system state for this core - ; Has the TX_INITIALIZE_IN_PROGRESS flag been set yet? + ; Has the TX_INITIALIZE_IN_PROGRESS flag been set yet? brne r3, r0, wait_for_initialize ; No, simply wait here until this value is set ; ; /* Pickup the release cores flag. */ @@ -105,7 +99,7 @@ wait_for_release: breq r3, r0, wait_for_release ; No, simply wait here until this flag is set ; ; /* Core 0 has released this core. */ -; +; ; /* Clear this core's system state variable. */ ; st r3, [r1] ; Clear this core's state value diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_low_level_initialize.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_low_level_initialize.s index a6a0221c..5c5634ee 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_low_level_initialize.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_low_level_initialize.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -30,42 +30,36 @@ ;#include "tx_timer.h" */ ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_smp_low_level_initialize SMP/ARC_HS/MetaWare */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_low_level_initialize SMP/ARC_HS/MetaWare */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function performs low-level initialization of the booting */ -;/* core. */ -;/* */ -;/* INPUT */ -;/* */ -;/* number_of_cores Number of cores */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_high_level ThreadX high-level init */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function performs low-level initialization of the booting */ +;/* core. */ +;/* */ +;/* INPUT */ +;/* */ +;/* number_of_cores Number of cores */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_high_level ThreadX high-level init */ ;/* */ ;/**************************************************************************/ .global _tx_thread_smp_low_level_initialize @@ -73,6 +67,6 @@ _tx_thread_smp_low_level_initialize: j_s.d [blink] ; Return to caller with delay slot - nop ; + nop ; .end diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_protect.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_protect.s index 2d9c1034..0dd1806e 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_protect.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_protect.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -30,43 +30,37 @@ ;#include "tx_timer.h" */ ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_smp_protect SMP/ARC_HS/MetaWare */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_protect SMP/ARC_HS/MetaWare */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function gets protection for running inside the ThreadX */ -;/* source. This is acomplished by a combination of a test-and-set */ -;/* flag and periodically disabling interrupts. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* Previous Status Register */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX Source */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function gets protection for running inside the ThreadX */ +;/* source. This is acomplished by a combination of a test-and-set */ +;/* flag and periodically disabling interrupts. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* Previous Status Register */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ ;/* */ ;/**************************************************************************/ .global _tx_thread_smp_protect diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_time_get.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_time_get.s index 0ff6f0c6..01ee3bdf 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_time_get.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_time_get.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -30,42 +30,36 @@ ;#include "tx_timer.h" */ ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_smp_time_get SMP/ARC_HS/MetaWare */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_time_get SMP/ARC_HS/MetaWare */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function gets the global time value that is used for debug */ -;/* information and event tracing. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* 32-bit time stamp */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX Source */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function gets the global time value that is used for debug */ +;/* information and event tracing. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* 32-bit time stamp */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ ;/* */ ;/**************************************************************************/ .global _tx_thread_smp_time_get @@ -76,4 +70,4 @@ _tx_thread_smp_time_get: lr r0, [COUNT0] ; Return count 0 value .end - + diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_unprotect.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_unprotect.s index 7c5860d1..a1310c66 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_unprotect.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_unprotect.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -30,44 +30,38 @@ ;#include "tx_timer.h" */ ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_smp_unprotect SMP/ARC_HS/MetaWare */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_unprotect SMP/ARC_HS/MetaWare */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function releases previously obtained protection. The supplied */ -;/* previous SR is restored. If the value of _tx_thread_system_state */ -;/* and _tx_thread_preempt_disable are both zero, then multithreading */ -;/* is enabled as well. */ -;/* */ -;/* INPUT */ -;/* */ -;/* Previous Status Register */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX Source */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function releases previously obtained protection. The supplied */ +;/* previous SR is restored. If the value of _tx_thread_system_state */ +;/* and _tx_thread_preempt_disable are both zero, then multithreading */ +;/* is enabled as well. */ +;/* */ +;/* INPUT */ +;/* */ +;/* Previous Status Register */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ ;/* */ ;/**************************************************************************/ .global _tx_thread_smp_unprotect @@ -85,7 +79,7 @@ _tx_thread_smp_unprotect: ld r6, [r4, 12] ; Pickup ownership count breq r6, 0, _still_protected ; If zero, protection is still active sub r6, r6, 1 ; Decrement the ownership count - st r6, [r4, 12] ; Store the ownership count + st r6, [r4, 12] ; Store the ownership count brne r6, 0, _still_protected ; If non-zero, protection is still active ld r6, [gp, _tx_thread_preempt_disable@sda] ; Pickup preempt disable flag brne r6, 0, _still_protected ; If non-zero, don't release the protection @@ -93,14 +87,14 @@ _tx_thread_smp_unprotect: st r2, [r4, 8] ; Set the owning core to an invalid value .ifdef TX_SMP_DEBUG_ENABLE st blink, [r4, 24] ; Save caller of unprotect - .endif + .endif mov r2, 0 ; Build clear value dmb 3 ; Data memory barrier st r2, [r4] ; Release the protection dmb 3 ; Data memory barrier _still_protected: j_s.d [blink] ; Return to caller with delay slot - seti r0 ; Set desired interrupt state + seti r0 ; Set desired interrupt state .end - + diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_stack_build.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_stack_build.s index aca1d5c4..4599ccfd 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_stack_build.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_stack_build.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,14 +29,14 @@ ;#include "tx_thread.h" ; ; - .equ LONG_ALIGN_MASK, 0xFFFFFFFC + .equ LONG_ALIGN_MASK, 0xFFFFFFFC .equ INT_ENABLE_BITS, 0x8000001E ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_stack_build SMP/ARC_HS/MetaWare */ ;/* 6.1 */ ;/* AUTHOR */ @@ -44,33 +44,27 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function builds a stack frame on the supplied thread's stack. */ ;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ ;/* thread_ptr Pointer to thread control blk */ ;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -79,11 +73,11 @@ .type _tx_thread_stack_build, @function _tx_thread_stack_build: ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the ARC HS should look like the following after it is built. ; Note that the extension registers are always assigned space here. -; +; ; Stack Top: 1 Interrupt stack frame type ; LP_START Initial loop start ; LP_END Initial loop end @@ -118,7 +112,7 @@ _tx_thread_stack_build: ; r2 Initial r2 ; r1 Initial r1 ; r0 Initial r0 -; r30 Initial r30 +; r30 Initial r30 ; r58 Initial r58 ; r59 Initial r59 ; 0 Reserved @@ -126,10 +120,10 @@ _tx_thread_stack_build: ; 0 Initial BTA ; 0 Point of Interrupt (thread entry point) ; 0 Initial STATUS32 -; 0 Backtrace -; 0 Backtrace -; 0 Backtrace -; 0 Backtrace +; 0 Backtrace +; 0 Backtrace +; 0 Backtrace +; 0 Backtrace ; ; *: these registers will only be saved and restored if flag -Xxmac_d16 is passed to hcac ; @@ -183,14 +177,14 @@ _tx_thread_stack_build: st r5, [r3, 148] ; Reserved st r5, [r3, 152] ; Reserved st r5, [r3, 156] ; Store initial BTA - st r1, [r3, 160] ; Store initial point of entry + st r1, [r3, 160] ; Store initial point of entry lr r6, [status32] ; Pickup STATUS32 or r6, r6, INT_ENABLE_BITS ; Make sure interrupts are enabled st r6, [r3, 164] ; Store initial STATUS32 - st r5, [r3, 168] ; Backtrace 0 - st r5, [r3, 172] ; Backtrace 0 - st r5, [r3, 176] ; Backtrace 0 - st r5, [r3, 180] ; Backtrace 0 + st r5, [r3, 168] ; Backtrace 0 + st r5, [r3, 172] ; Backtrace 0 + st r5, [r3, 176] ; Backtrace 0 + st r5, [r3, 180] ; Backtrace 0 ; ; /* Set ready bit in thread control block. */ ; diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_system_return.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_system_return.s index 775c0db9..ff2a2cb2 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_system_return.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_system_return.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,10 +29,10 @@ ;#include "tx_timer.h" ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_system_return SMP/ARC_HS/MetaWare */ ;/* 6.1 */ ;/* AUTHOR */ @@ -40,33 +40,27 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -87,7 +81,7 @@ _tx_thread_system_return: .endif asl r4, r1, 2 ; Build index into core arrays mov r7, _tx_thread_current_ptr ; Pickup base of the current thread pointer - add r7, r7, r4 ; Build address of current thread pointer + add r7, r7, r4 ; Build address of current thread pointer ld r0, [r7] ; Pickup current thread ptr sub sp, sp, 76 ; Allocate a solicited stack frame mov r3, 0 ; Build a solicited stack type @@ -115,7 +109,7 @@ _tx_thread_system_return: ; _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; ; sp = _tx_thread_system_stack_ptr[core]; ; -; +; st sp, [r0, 8] ; Save thread's stack pointer mov r6, _tx_thread_system_stack_ptr ; Pickup address of system stack pointer add r6, r6, r4 ; Build address of this core's entry @@ -138,8 +132,8 @@ _tx_thread_system_return: mov r1, r14 ; Recover current core executing mov r7, r15 ; Recover current thread pointer for core mov blink, r16 ; Recover blink - asl r4, r1, 2 ; Build index into core arrays - + asl r4, r1, 2 ; Build index into core arrays + .endif ; ; /* Determine if the time-slice is active. */ @@ -147,7 +141,7 @@ _tx_thread_system_return: ; { ; mov r6, _tx_timer_time_slice ; Build address of current time-slice - add r6, r6, r4 ; + add r6, r6, r4 ; ld r5, [r6] ; Pickup current time-slice breq r5, 0, __tx_thread_dont_save_ts ; If not, skip save processing ; diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_timer_interrupt.s b/ports_smp/arc_hs_smp/metaware/src/tx_timer_interrupt.s index bf013003..58c787e3 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_timer_interrupt.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_timer_interrupt.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -29,10 +29,10 @@ ;#include "tx_thread.h" ; ; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_timer_interrupt SMP/ARC_HS/MetaWare */ ;/* 6.1 */ ;/* AUTHOR */ @@ -40,43 +40,37 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Process timer expiration */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* _tx_thread_context_save Save interrupt context */ -;/* _tx_thread_context_restore Restore interrupt context */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Process timer expiration */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* _tx_thread_context_save Save interrupt context */ +;/* _tx_thread_context_restore Restore interrupt context */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) ;{ .global _tx_timer_interrupt - .type _tx_timer_interrupt, @function + .type _tx_timer_interrupt, @function _tx_timer_interrupt: ; ; /* Upon entry to this routine, it is assumed that context save has already @@ -88,9 +82,9 @@ _tx_timer_interrupt: .ifndef TX_ZERO_BASED_CORE_ID sub r1, r1, 1 ; Subtract 1 to make 0-based .endif - breq r1, 0, __tx_process_timer ; By default if core 0, process timer + breq r1, 0, __tx_process_timer ; By default if core 0, process timer j_s.d [blink] ; Return to caller with delay - nop ; + nop ; __tx_process_timer: sub sp, sp, 16 ; Allocate some stack space @@ -98,7 +92,7 @@ __tx_process_timer: bl.d _tx_thread_smp_protect ; Get SMP protecton sub sp, sp, 16 ; ..allocating some space on the stack add sp, sp, 16 ; Recover the stack space - st r0, [sp, 4] ; Save returned interrupt posture on stack + st r0, [sp, 4] ; Save returned interrupt posture on stack ld r0, [gp,_tx_timer_interrupt_active@sda] ; Pickup current timer active count add r0, r0, 1 ; Increment the active count st r0, [gp,_tx_timer_interrupt_active@sda] ; Store the new timer active count @@ -117,7 +111,7 @@ __tx_process_timer: ; ld r0, [gp, _tx_timer_current_ptr@sda] ; Pickup current timer pointer ld r2, [r0, 0] ; Pickup examine actual list entry - breq r2, 0, __tx_timer_no_timer ; + breq r2, 0, __tx_timer_no_timer ; ; If NULL, no timer has expired, just move to the next entry ; ; /* Set expiration flag. */ @@ -202,4 +196,4 @@ __tx_timer_nothing_expired: ; ;} .end - + diff --git a/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/.cproject b/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/.cproject index aa89d53a..dccae911 100644 --- a/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/sample_threadx.scat index 1288a328..1ed382ae 100644 --- a/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/sample_threadx.scat @@ -12,13 +12,13 @@ LOAD 0x80000000 { startup.o (StartUp, +FIRST) * (+RO, +RW, +ZI) - + } ;XTABLES +0 ALIGN 0x1000 ;{ - ; xtables.o (*) + ; xtables.o (*) ;} - + SYS_STACK +0 ALIGN 8 EMPTY 0x1000 { } @@ -34,13 +34,13 @@ LOAD 0x80000000 ; All stacks and heap are aligned to a cache-line boundary ; ARM_LIB_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary ; HANDLER_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Stacks for EL3 ; @@ -217,34 +217,34 @@ LOAD 0x80000000 ; { ; *( +RO ) ; } -; +; ; XTABLES +0 ALIGN 0x1000 ; { -; xtables.o (*) +; xtables.o (*) ; } ;} ; ;RW AlignExpr(ImageLimit(XTABLES), 0x1000) -;{ +;{ ; RWSEC +0 ; { ; *( +RW ) ; } -; +; ; ZISEC +0 ; { ; *( +ZI ) ; } -; +; ; SYS_STACK +0 ALIGN 8 EMPTY 0x1000 ; { ; } -; +; ; ; 512 MiB heap ; HEAP +0 ALIGN 8 EMPTY 0x10000000 ; { ; } -; +; ; ; Free Memory section ; FREE_MEMORY +0 ALIGN 8 EMPTY 0x10000000 ; { @@ -254,7 +254,7 @@ LOAD 0x80000000 ; TASK_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { ; } -; +; ; ; Per-CPU 128 MiB handler stacks ; HANDLER_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { diff --git a/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/v8_aarch64.h b/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports_smp/cortex_a34_smp/ac6/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_smp/cortex_a34_smp/ac6/example_build/tx/.cproject b/ports_smp/cortex_a34_smp/ac6/example_build/tx/.cproject index 3c1c5962..742b0fa7 100644 --- a/ports_smp/cortex_a34_smp/ac6/example_build/tx/.cproject +++ b/ports_smp/cortex_a34_smp/ac6/example_build/tx/.cproject @@ -1,160 +1,160 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a34_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a34_smp/ac6/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_smp/cortex_a34_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a34_smp/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a34_smp/ac6/src/tx_initialize_low_level.S b/ports_smp/cortex_a34_smp/ac6/src/tx_initialize_low_level.S index 7d2cfabf..08986f7b 100644 --- a/ports_smp/cortex_a34_smp/ac6/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a34_smp/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_context_restore.S index 4ef265e7..991248f5 100644 --- a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,18 +56,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_context_save.S b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_context_save.S index 890987f1..f43809f5 100644 --- a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_fp_disable.c b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_fp_enable.c b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_interrupt_control.S index efc10724..d4235180 100644 --- a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_interrupt_disable.S index 508562ff..08f0e7e1 100644 --- a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,14 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_interrupt_restore.S index af0fdddf..d0191c32 100644 --- a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_schedule.S index c2d30b48..782491cc 100644 --- a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_core_get.S index d4cda1d8..4ffb8cc6 100644 --- a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,15 +53,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_core_preempt.S index ed9217f4..8dc6933c 100644 --- a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_current_state_get.S index 83394dcc..edae94d5 100644 --- a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,15 +53,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_current_thread_get.S index c235e75d..dd740e05 100644 --- a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,15 +53,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_initialize_wait.S index c4df7504..985136b5 100644 --- a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_low_level_initialize.S index 373a79dd..64b854d0 100644 --- a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_protect.S b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_protect.S index f90f77bf..4a48c56c 100644 --- a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -119,9 +107,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_time_get.S index 9b198c75..f3045738 100644 --- a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_unprotect.S index 7223a91c..4b5bd9a2 100644 --- a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,18 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_stack_build.S b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_stack_build.S index 3ded5721..fa11a65c 100644 --- a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,14 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_system_return.S index e500e9e3..4eebb9aa 100644 --- a/ports_smp/cortex_a34_smp/ac6/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a34_smp/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a34_smp/ac6/src/tx_timer_interrupt.S b/ports_smp/cortex_a34_smp/ac6/src/tx_timer_interrupt.S index 7e22857e..6f90e5d1 100644 --- a/ports_smp/cortex_a34_smp/ac6/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a34_smp/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,12 +58,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/.cproject b/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/.cproject index 34967225..aab1eeaf 100644 --- a/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/sample_threadx.ld b/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/sample_threadx.ld index e9b12a82..1c6d45b5 100644 --- a/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start @@ -194,7 +194,7 @@ SECTIONS . = . + 4 * 0x8000; __stack = .; } - + .handler_stack_limit (NOLOAD): { . = ALIGN(64); diff --git a/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/v8_aarch64.h b/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports_smp/cortex_a34_smp/gnu/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_smp/cortex_a34_smp/gnu/example_build/tx/.cproject b/ports_smp/cortex_a34_smp/gnu/example_build/tx/.cproject index e8013d86..11d7c2fe 100644 --- a/ports_smp/cortex_a34_smp/gnu/example_build/tx/.cproject +++ b/ports_smp/cortex_a34_smp/gnu/example_build/tx/.cproject @@ -1,194 +1,194 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a34_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a34_smp/gnu/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_smp/cortex_a34_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a34_smp/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a34_smp/gnu/src/tx_initialize_low_level.S b/ports_smp/cortex_a34_smp/gnu/src/tx_initialize_low_level.S index c8e33bb3..43d87225 100644 --- a/ports_smp/cortex_a34_smp/gnu/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a34_smp/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_context_restore.S index 4ef265e7..991248f5 100644 --- a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,18 +56,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_context_save.S b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_context_save.S index 890987f1..f43809f5 100644 --- a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_fp_disable.c b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_fp_enable.c b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_interrupt_control.S index efc10724..d4235180 100644 --- a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_interrupt_disable.S index 508562ff..08f0e7e1 100644 --- a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,14 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_interrupt_restore.S index af0fdddf..d0191c32 100644 --- a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_schedule.S index c2d30b48..782491cc 100644 --- a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_core_get.S index d4cda1d8..4ffb8cc6 100644 --- a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,15 +53,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_core_preempt.S index ed9217f4..8dc6933c 100644 --- a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_current_state_get.S index 83394dcc..edae94d5 100644 --- a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,15 +53,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_current_thread_get.S index c235e75d..dd740e05 100644 --- a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,15 +53,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_initialize_wait.S index c4df7504..985136b5 100644 --- a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_low_level_initialize.S index 373a79dd..64b854d0 100644 --- a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_protect.S b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_protect.S index f90f77bf..4a48c56c 100644 --- a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -119,9 +107,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_time_get.S index 9b198c75..f3045738 100644 --- a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_unprotect.S index 7223a91c..4b5bd9a2 100644 --- a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,18 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_stack_build.S b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_stack_build.S index 3ded5721..fa11a65c 100644 --- a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,14 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_system_return.S index e500e9e3..4eebb9aa 100644 --- a/ports_smp/cortex_a34_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a34_smp/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a34_smp/gnu/src/tx_timer_interrupt.S b/ports_smp/cortex_a34_smp/gnu/src/tx_timer_interrupt.S index 7e22857e..6f90e5d1 100644 --- a/ports_smp/cortex_a34_smp/gnu/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a34_smp/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,12 +58,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/.cproject b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/.cproject index f9c90b21..4a9d74c4 100644 --- a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.scat index 1288a328..1ed382ae 100644 --- a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.scat @@ -12,13 +12,13 @@ LOAD 0x80000000 { startup.o (StartUp, +FIRST) * (+RO, +RW, +ZI) - + } ;XTABLES +0 ALIGN 0x1000 ;{ - ; xtables.o (*) + ; xtables.o (*) ;} - + SYS_STACK +0 ALIGN 8 EMPTY 0x1000 { } @@ -34,13 +34,13 @@ LOAD 0x80000000 ; All stacks and heap are aligned to a cache-line boundary ; ARM_LIB_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary ; HANDLER_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Stacks for EL3 ; @@ -217,34 +217,34 @@ LOAD 0x80000000 ; { ; *( +RO ) ; } -; +; ; XTABLES +0 ALIGN 0x1000 ; { -; xtables.o (*) +; xtables.o (*) ; } ;} ; ;RW AlignExpr(ImageLimit(XTABLES), 0x1000) -;{ +;{ ; RWSEC +0 ; { ; *( +RW ) ; } -; +; ; ZISEC +0 ; { ; *( +ZI ) ; } -; +; ; SYS_STACK +0 ALIGN 8 EMPTY 0x1000 ; { ; } -; +; ; ; 512 MiB heap ; HEAP +0 ALIGN 8 EMPTY 0x10000000 ; { ; } -; +; ; ; Free Memory section ; FREE_MEMORY +0 ALIGN 8 EMPTY 0x10000000 ; { @@ -254,7 +254,7 @@ LOAD 0x80000000 ; TASK_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { ; } -; +; ; ; Per-CPU 128 MiB handler stacks ; HANDLER_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/v8_aarch64.h b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/tx/.cproject b/ports_smp/cortex_a35_smp/ac6/example_build/tx/.cproject index 751695e9..56babab8 100644 --- a/ports_smp/cortex_a35_smp/ac6/example_build/tx/.cproject +++ b/ports_smp/cortex_a35_smp/ac6/example_build/tx/.cproject @@ -1,188 +1,188 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a35_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a35_smp/ac6/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_smp/cortex_a35_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a35_smp/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a35_smp/ac6/readme_threadx.txt b/ports_smp/cortex_a35_smp/ac6/readme_threadx.txt index 8c35001b..b8633132 100644 --- a/ports_smp/cortex_a35_smp/ac6/readme_threadx.txt +++ b/ports_smp/cortex_a35_smp/ac6/readme_threadx.txt @@ -1,19 +1,19 @@ - Microsoft's Azure RTOS ThreadX SMP for Cortex-A35 + Microsoft's Azure RTOS ThreadX SMP for Cortex-A35 Using the ARM Compiler 6 & DS 1. Import the ThreadX Projects -In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import -the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) into your DS workspace. 2. Building the ThreadX SMP run-time Library -Building the ThreadX SMP library is easy; simply select the Eclipse project file -"tx" and then select the build button. You should now observe the compilation -and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP +Building the ThreadX SMP library is easy; simply select the Eclipse project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP library file tx.a. @@ -33,29 +33,29 @@ ThreadX SMP demonstration. 4. System Initialization -The entry point in ThreadX SMP for the Cortex-A35 using AC6 tools is at label -"start64". This is defined within the AC6 compiler's startup code. In addition, -this is where all static and global pre-set C variable initialization processing +The entry point in ThreadX SMP for the Cortex-A35 using AC6 tools is at label +"start64". This is defined within the AC6 compiler's startup code. In addition, +this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX SMP tx_initialize_low_level.s file is responsible for determining the -first available RAM address for use by the application, which is supplied as the +The ThreadX SMP tx_initialize_low_level.s file is responsible for determining the +first available RAM address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 5. Register Usage and Stack Frames -The 64-bit AC6 compiler assumes that registers x0-x18 are scratch registers -for each function. All other registers used by a C function must be preserved -by the function. ThreadX SMP takes advantage of this in situations where a context -switch happens as a result of making a ThreadX SMP service call (which is itself a -C function). In such cases, the saved context of a thread is only the +The 64-bit AC6 compiler assumes that registers x0-x18 are scratch registers +for each function. All other registers used by a C function must be preserved +by the function. ThreadX SMP takes advantage of this in situations where a context +switch happens as a result of making a ThreadX SMP service call (which is itself a +C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -74,10 +74,10 @@ FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: 0x040 x22 x21 0x048 x23 x22 0x050 x20 x19 - 0x058 x21 x20 - 0x060 x18 x29 - 0x068 x19 x30 - 0x070 x16 + 0x058 x21 x20 + 0x060 x18 x29 + 0x068 x19 x30 + 0x070 x16 0x078 x17 0x080 x14 0x088 x15 @@ -96,7 +96,7 @@ FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: 0x0F0 x0 0x0F8 x1 0x100 x29 - 0x108 x30 + 0x108 x30 FP enabled and TX_THREAD.tx_thread_fp_enable == 1: @@ -145,19 +145,19 @@ FP enabled and TX_THREAD.tx_thread_fp_enable == 1: 0x1F0 q3 0x200 q0 0x210 q1 - 0x220 x28 - 0x228 reserved - 0x230 x26 - 0x238 x27 - 0x240 x24 - 0x248 x25 - 0x250 x22 - 0x258 x23 - 0x260 x20 - 0x268 x21 - 0x270 x18 - 0x278 x19 - 0x280 x16 + 0x220 x28 + 0x228 reserved + 0x230 x26 + 0x238 x27 + 0x240 x24 + 0x248 x25 + 0x250 x22 + 0x258 x23 + 0x260 x20 + 0x268 x21 + 0x270 x18 + 0x278 x19 + 0x280 x16 0x288 x17 0x290 x14 0x298 x15 @@ -176,20 +176,20 @@ FP enabled and TX_THREAD.tx_thread_fp_enable == 1: 0x300 x0 0x308 x1 0x310 x29 - 0x318 x30 + 0x318 x30 6. Improving Performance -The distribution version of ThreadX SMP is built without any compiler optimizations. -This makes it easy to debug because you can trace or set breakpoints inside of -ThreadX SMP itself. Of course, this costs some performance. To make it run faster, +The distribution version of ThreadX SMP is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX SMP itself. Of course, this costs some performance. To make it run faster, you can change the project settings to the desired compiler optimization level. -In addition, you can eliminate the ThreadX SMP basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX SMP basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling @@ -209,22 +209,22 @@ irq_handler: B _tx_thread_context_restore -By default, ThreadX SMP assumes EL3 level of execution. Running and taking exceptions in EL1 +By default, ThreadX SMP assumes EL3 level of execution. Running and taking exceptions in EL1 and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined. 8. ThreadX SMP Timer Interrupt -ThreadX SMP requires a periodic interrupt source to manage all time-slicing, thread sleeps, -timeouts, and application timers. Without such a timer interrupt source, these services -are not functional. However, all other ThreadX services are operational without a +ThreadX SMP requires a periodic interrupt source to manage all time-slicing, thread sleeps, +timeouts, and application timers. Without such a timer interrupt source, these services +are not functional. However, all other ThreadX services are operational without a periodic timer source. 9. ARM FP Support By default, FP support is disabled for each thread. If saving the context of the FP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the FP usage: void tx_thread_fp_enable(void); diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_initialize_low_level.S b/ports_smp/cortex_a35_smp/ac6/src/tx_initialize_low_level.S index 7d2cfabf..08986f7b 100644 --- a/ports_smp/cortex_a35_smp/ac6/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_context_restore.S index c16c6dbb..5cd7a9df 100644 --- a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,22 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_context_save.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_context_save.S index c8281503..76641067 100644 --- a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_fp_disable.c b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_fp_enable.c b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_schedule.S index 52654783..de6b70dd 100644 --- a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* added memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_core_get.S index 684e317c..ea14c901 100644 --- a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_core_preempt.S index 903a5ab9..1d28907f 100644 --- a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,18 +62,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_current_state_get.S index 67b5b6f5..707b41d2 100644 --- a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_current_thread_get.S index 42d5776c..6c4bc9af 100644 --- a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_initialize_wait.S index f1c067cf..defd791c 100644 --- a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_low_level_initialize.S index 101a91f3..99b20d24 100644 --- a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_protect.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_protect.S index d2750b7e..1155a3fa 100644 --- a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,22 +61,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -124,9 +109,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_time_get.S index ee4dd40c..335824fb 100644 --- a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_unprotect.S index ae700d1e..680e8bc8 100644 --- a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,21 +58,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_stack_build.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_stack_build.S index 746bbd42..581e259e 100644 --- a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_system_return.S index b889de21..23c75241 100644 --- a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_timer_interrupt.S b/ports_smp/cortex_a35_smp/ac6/src/tx_timer_interrupt.S index bad59269..5c6a6bc2 100644 --- a/ports_smp/cortex_a35_smp/ac6/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/.cproject b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/.cproject index 34967225..aab1eeaf 100644 --- a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.ld b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.ld index e9b12a82..1c6d45b5 100644 --- a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start @@ -194,7 +194,7 @@ SECTIONS . = . + 4 * 0x8000; __stack = .; } - + .handler_stack_limit (NOLOAD): { . = ALIGN(64); diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/v8_aarch64.h b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/tx/.cproject b/ports_smp/cortex_a35_smp/gnu/example_build/tx/.cproject index 3547a1d3..e3f31405 100644 --- a/ports_smp/cortex_a35_smp/gnu/example_build/tx/.cproject +++ b/ports_smp/cortex_a35_smp/gnu/example_build/tx/.cproject @@ -1,200 +1,200 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a35_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a35_smp/gnu/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_smp/cortex_a35_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a35_smp/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a35_smp/gnu/readme_threadx.txt b/ports_smp/cortex_a35_smp/gnu/readme_threadx.txt index 63010670..a7d23628 100644 --- a/ports_smp/cortex_a35_smp/gnu/readme_threadx.txt +++ b/ports_smp/cortex_a35_smp/gnu/readme_threadx.txt @@ -4,16 +4,16 @@ 1. Import the ThreadX Projects -In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import -the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) into your DS workspace. 2. Building the ThreadX SMP run-time Library -Building the ThreadX SMP library is easy; simply select the Eclipse project file -"tx" and then select the build button. You should now observe the compilation -and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP +Building the ThreadX SMP library is easy; simply select the Eclipse project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP library file tx.a. @@ -33,29 +33,29 @@ ThreadX SMP demonstration. 4. System Initialization -The entry point in ThreadX SMP for the Cortex-A35 using GCC tools is at label -"start64". This is defined within the GCC compiler's startup code. In addition, -this is where all static and global pre-set C variable initialization processing +The entry point in ThreadX SMP for the Cortex-A35 using GCC tools is at label +"start64". This is defined within the GCC compiler's startup code. In addition, +this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX SMP tx_initialize_low_level.s file is responsible for determining the -first available RAM address for use by the application, which is supplied as the +The ThreadX SMP tx_initialize_low_level.s file is responsible for determining the +first available RAM address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 5. Register Usage and Stack Frames -The 64-bit GCC compiler assumes that registers x0-x18 are scratch registers -for each function. All other registers used by a C function must be preserved -by the function. ThreadX SMP takes advantage of this in situations where a context -switch happens as a result of making a ThreadX SMP service call (which is itself a -C function). In such cases, the saved context of a thread is only the +The 64-bit GCC compiler assumes that registers x0-x18 are scratch registers +for each function. All other registers used by a C function must be preserved +by the function. ThreadX SMP takes advantage of this in situations where a context +switch happens as a result of making a ThreadX SMP service call (which is itself a +C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -74,10 +74,10 @@ FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: 0x040 x22 x21 0x048 x23 x22 0x050 x20 x19 - 0x058 x21 x20 - 0x060 x18 x29 - 0x068 x19 x30 - 0x070 x16 + 0x058 x21 x20 + 0x060 x18 x29 + 0x068 x19 x30 + 0x070 x16 0x078 x17 0x080 x14 0x088 x15 @@ -96,7 +96,7 @@ FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: 0x0F0 x0 0x0F8 x1 0x100 x29 - 0x108 x30 + 0x108 x30 FP enabled and TX_THREAD.tx_thread_fp_enable == 1: @@ -145,19 +145,19 @@ FP enabled and TX_THREAD.tx_thread_fp_enable == 1: 0x1F0 q3 0x200 q0 0x210 q1 - 0x220 x28 - 0x228 reserved - 0x230 x26 - 0x238 x27 - 0x240 x24 - 0x248 x25 - 0x250 x22 - 0x258 x23 - 0x260 x20 - 0x268 x21 - 0x270 x18 - 0x278 x19 - 0x280 x16 + 0x220 x28 + 0x228 reserved + 0x230 x26 + 0x238 x27 + 0x240 x24 + 0x248 x25 + 0x250 x22 + 0x258 x23 + 0x260 x20 + 0x268 x21 + 0x270 x18 + 0x278 x19 + 0x280 x16 0x288 x17 0x290 x14 0x298 x15 @@ -176,20 +176,20 @@ FP enabled and TX_THREAD.tx_thread_fp_enable == 1: 0x300 x0 0x308 x1 0x310 x29 - 0x318 x30 + 0x318 x30 6. Improving Performance -The distribution version of ThreadX SMP is built without any compiler optimizations. -This makes it easy to debug because you can trace or set breakpoints inside of -ThreadX SMP itself. Of course, this costs some performance. To make it run faster, +The distribution version of ThreadX SMP is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX SMP itself. Of course, this costs some performance. To make it run faster, you can change the project settings to the desired compiler optimization level. -In addition, you can eliminate the ThreadX SMP basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX SMP basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling @@ -209,22 +209,22 @@ irq_handler: B _tx_thread_context_restore -By default, ThreadX SMP assumes EL3 level of execution. Running and taking exceptions in EL1 +By default, ThreadX SMP assumes EL3 level of execution. Running and taking exceptions in EL1 and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined. 8. ThreadX SMP Timer Interrupt -ThreadX SMP requires a periodic interrupt source to manage all time-slicing, thread sleeps, -timeouts, and application timers. Without such a timer interrupt source, these services -are not functional. However, all other ThreadX services are operational without a +ThreadX SMP requires a periodic interrupt source to manage all time-slicing, thread sleeps, +timeouts, and application timers. Without such a timer interrupt source, these services +are not functional. However, all other ThreadX services are operational without a periodic timer source. 9. ARM FP Support By default, FP support is disabled for each thread. If saving the context of the FP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the FP usage: void tx_thread_fp_enable(void); diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_initialize_low_level.S b/ports_smp/cortex_a35_smp/gnu/src/tx_initialize_low_level.S index b171fc0f..efb08b80 100644 --- a/ports_smp/cortex_a35_smp/gnu/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_context_restore.S index c16c6dbb..5cd7a9df 100644 --- a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,22 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_context_save.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_context_save.S index c8281503..76641067 100644 --- a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_fp_disable.c b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_fp_enable.c b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_schedule.S index 52654783..de6b70dd 100644 --- a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* added memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_core_get.S index 684e317c..ea14c901 100644 --- a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_core_preempt.S index 903a5ab9..1d28907f 100644 --- a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,18 +62,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_current_state_get.S index 67b5b6f5..707b41d2 100644 --- a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_current_thread_get.S index 42d5776c..6c4bc9af 100644 --- a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_initialize_wait.S index f1c067cf..defd791c 100644 --- a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_low_level_initialize.S index 101a91f3..99b20d24 100644 --- a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_protect.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_protect.S index d2750b7e..1155a3fa 100644 --- a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,22 +61,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -124,9 +109,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_time_get.S index ee4dd40c..335824fb 100644 --- a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_unprotect.S index ae700d1e..680e8bc8 100644 --- a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,21 +58,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_stack_build.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_stack_build.S index 746bbd42..581e259e 100644 --- a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_system_return.S index b889de21..23c75241 100644 --- a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_timer_interrupt.S b/ports_smp/cortex_a35_smp/gnu/src/tx_timer_interrupt.S index bad59269..5c6a6bc2 100644 --- a/ports_smp/cortex_a35_smp/gnu/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/.cproject b/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/.cproject index 2569f6b3..68fefa9d 100644 --- a/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/sample_threadx.scat index 1288a328..1ed382ae 100644 --- a/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/sample_threadx.scat @@ -12,13 +12,13 @@ LOAD 0x80000000 { startup.o (StartUp, +FIRST) * (+RO, +RW, +ZI) - + } ;XTABLES +0 ALIGN 0x1000 ;{ - ; xtables.o (*) + ; xtables.o (*) ;} - + SYS_STACK +0 ALIGN 8 EMPTY 0x1000 { } @@ -34,13 +34,13 @@ LOAD 0x80000000 ; All stacks and heap are aligned to a cache-line boundary ; ARM_LIB_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary ; HANDLER_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Stacks for EL3 ; @@ -217,34 +217,34 @@ LOAD 0x80000000 ; { ; *( +RO ) ; } -; +; ; XTABLES +0 ALIGN 0x1000 ; { -; xtables.o (*) +; xtables.o (*) ; } ;} ; ;RW AlignExpr(ImageLimit(XTABLES), 0x1000) -;{ +;{ ; RWSEC +0 ; { ; *( +RW ) ; } -; +; ; ZISEC +0 ; { ; *( +ZI ) ; } -; +; ; SYS_STACK +0 ALIGN 8 EMPTY 0x1000 ; { ; } -; +; ; ; 512 MiB heap ; HEAP +0 ALIGN 8 EMPTY 0x10000000 ; { ; } -; +; ; ; Free Memory section ; FREE_MEMORY +0 ALIGN 8 EMPTY 0x10000000 ; { @@ -254,7 +254,7 @@ LOAD 0x80000000 ; TASK_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { ; } -; +; ; ; Per-CPU 128 MiB handler stacks ; HANDLER_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { diff --git a/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/v8_aarch64.h b/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports_smp/cortex_a53_smp/ac6/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_smp/cortex_a53_smp/ac6/example_build/tx/.cproject b/ports_smp/cortex_a53_smp/ac6/example_build/tx/.cproject index 94c09a8d..0b8ee887 100644 --- a/ports_smp/cortex_a53_smp/ac6/example_build/tx/.cproject +++ b/ports_smp/cortex_a53_smp/ac6/example_build/tx/.cproject @@ -1,188 +1,188 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a53_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a53_smp/ac6/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_smp/cortex_a53_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a53_smp/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a53_smp/ac6/src/tx_initialize_low_level.S b/ports_smp/cortex_a53_smp/ac6/src/tx_initialize_low_level.S index 7d2cfabf..08986f7b 100644 --- a/ports_smp/cortex_a53_smp/ac6/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a53_smp/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_context_restore.S index c16c6dbb..5cd7a9df 100644 --- a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,22 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_context_save.S b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_context_save.S index c8281503..76641067 100644 --- a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_fp_disable.c b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_fp_enable.c b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_schedule.S index 52654783..de6b70dd 100644 --- a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* added memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_core_get.S index 684e317c..ea14c901 100644 --- a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_core_preempt.S index 903a5ab9..1d28907f 100644 --- a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,18 +62,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_current_state_get.S index 67b5b6f5..707b41d2 100644 --- a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_current_thread_get.S index 42d5776c..6c4bc9af 100644 --- a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_initialize_wait.S index f1c067cf..defd791c 100644 --- a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_low_level_initialize.S index 101a91f3..99b20d24 100644 --- a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_protect.S b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_protect.S index d2750b7e..1155a3fa 100644 --- a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,22 +61,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -124,9 +109,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_time_get.S index ee4dd40c..335824fb 100644 --- a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_unprotect.S index ae700d1e..680e8bc8 100644 --- a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,21 +58,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_stack_build.S b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_stack_build.S index 746bbd42..581e259e 100644 --- a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_system_return.S index b889de21..23c75241 100644 --- a/ports_smp/cortex_a53_smp/ac6/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a53_smp/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a53_smp/ac6/src/tx_timer_interrupt.S b/ports_smp/cortex_a53_smp/ac6/src/tx_timer_interrupt.S index bad59269..5c6a6bc2 100644 --- a/ports_smp/cortex_a53_smp/ac6/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a53_smp/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/.cproject b/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/.cproject index 34967225..aab1eeaf 100644 --- a/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/sample_threadx.ld b/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/sample_threadx.ld index e9b12a82..1c6d45b5 100644 --- a/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start @@ -194,7 +194,7 @@ SECTIONS . = . + 4 * 0x8000; __stack = .; } - + .handler_stack_limit (NOLOAD): { . = ALIGN(64); diff --git a/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/v8_aarch64.h b/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports_smp/cortex_a53_smp/gnu/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_smp/cortex_a53_smp/gnu/example_build/tx/.cproject b/ports_smp/cortex_a53_smp/gnu/example_build/tx/.cproject index 3547a1d3..e3f31405 100644 --- a/ports_smp/cortex_a53_smp/gnu/example_build/tx/.cproject +++ b/ports_smp/cortex_a53_smp/gnu/example_build/tx/.cproject @@ -1,200 +1,200 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a53_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a53_smp/gnu/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_smp/cortex_a53_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a53_smp/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a53_smp/gnu/src/tx_initialize_low_level.S b/ports_smp/cortex_a53_smp/gnu/src/tx_initialize_low_level.S index b171fc0f..efb08b80 100644 --- a/ports_smp/cortex_a53_smp/gnu/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a53_smp/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_context_restore.S index c16c6dbb..5cd7a9df 100644 --- a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,22 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_context_save.S b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_context_save.S index c8281503..76641067 100644 --- a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_fp_disable.c b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_fp_enable.c b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_schedule.S index 52654783..de6b70dd 100644 --- a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* added memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_core_get.S index 684e317c..ea14c901 100644 --- a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_core_preempt.S index 903a5ab9..1d28907f 100644 --- a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,18 +62,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_current_state_get.S index 67b5b6f5..707b41d2 100644 --- a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_current_thread_get.S index 42d5776c..6c4bc9af 100644 --- a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_initialize_wait.S index f1c067cf..defd791c 100644 --- a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_low_level_initialize.S index 101a91f3..99b20d24 100644 --- a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_protect.S b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_protect.S index d2750b7e..1155a3fa 100644 --- a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,22 +61,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -124,9 +109,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_time_get.S index ee4dd40c..335824fb 100644 --- a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_unprotect.S index ae700d1e..680e8bc8 100644 --- a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,21 +58,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_stack_build.S b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_stack_build.S index 746bbd42..581e259e 100644 --- a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_system_return.S index b889de21..23c75241 100644 --- a/ports_smp/cortex_a53_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a53_smp/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a53_smp/gnu/src/tx_timer_interrupt.S b/ports_smp/cortex_a53_smp/gnu/src/tx_timer_interrupt.S index bad59269..5c6a6bc2 100644 --- a/ports_smp/cortex_a53_smp/gnu/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a53_smp/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/.cproject b/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/.cproject index 8425e861..a34d235a 100644 --- a/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/sample_threadx.scat index 1288a328..1ed382ae 100644 --- a/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/sample_threadx.scat @@ -12,13 +12,13 @@ LOAD 0x80000000 { startup.o (StartUp, +FIRST) * (+RO, +RW, +ZI) - + } ;XTABLES +0 ALIGN 0x1000 ;{ - ; xtables.o (*) + ; xtables.o (*) ;} - + SYS_STACK +0 ALIGN 8 EMPTY 0x1000 { } @@ -34,13 +34,13 @@ LOAD 0x80000000 ; All stacks and heap are aligned to a cache-line boundary ; ARM_LIB_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary ; HANDLER_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Stacks for EL3 ; @@ -217,34 +217,34 @@ LOAD 0x80000000 ; { ; *( +RO ) ; } -; +; ; XTABLES +0 ALIGN 0x1000 ; { -; xtables.o (*) +; xtables.o (*) ; } ;} ; ;RW AlignExpr(ImageLimit(XTABLES), 0x1000) -;{ +;{ ; RWSEC +0 ; { ; *( +RW ) ; } -; +; ; ZISEC +0 ; { ; *( +ZI ) ; } -; +; ; SYS_STACK +0 ALIGN 8 EMPTY 0x1000 ; { ; } -; +; ; ; 512 MiB heap ; HEAP +0 ALIGN 8 EMPTY 0x10000000 ; { ; } -; +; ; ; Free Memory section ; FREE_MEMORY +0 ALIGN 8 EMPTY 0x10000000 ; { @@ -254,7 +254,7 @@ LOAD 0x80000000 ; TASK_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { ; } -; +; ; ; Per-CPU 128 MiB handler stacks ; HANDLER_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { diff --git a/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/v8_aarch64.h b/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports_smp/cortex_a55_smp/ac6/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_smp/cortex_a55_smp/ac6/example_build/tx/.cproject b/ports_smp/cortex_a55_smp/ac6/example_build/tx/.cproject index 4a457cd0..cc49fd9b 100644 --- a/ports_smp/cortex_a55_smp/ac6/example_build/tx/.cproject +++ b/ports_smp/cortex_a55_smp/ac6/example_build/tx/.cproject @@ -1,188 +1,188 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a55_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a55_smp/ac6/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_smp/cortex_a55_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a55_smp/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a55_smp/ac6/src/tx_initialize_low_level.S b/ports_smp/cortex_a55_smp/ac6/src/tx_initialize_low_level.S index 7d2cfabf..08986f7b 100644 --- a/ports_smp/cortex_a55_smp/ac6/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a55_smp/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_context_restore.S index c16c6dbb..5cd7a9df 100644 --- a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,22 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_context_save.S b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_context_save.S index c8281503..76641067 100644 --- a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_fp_disable.c b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_fp_enable.c b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_schedule.S index 52654783..de6b70dd 100644 --- a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* added memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_core_get.S index 684e317c..ea14c901 100644 --- a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_core_preempt.S index 903a5ab9..1d28907f 100644 --- a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,18 +62,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_current_state_get.S index 67b5b6f5..707b41d2 100644 --- a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_current_thread_get.S index 42d5776c..6c4bc9af 100644 --- a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_initialize_wait.S index f1c067cf..defd791c 100644 --- a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_low_level_initialize.S index 101a91f3..99b20d24 100644 --- a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_protect.S b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_protect.S index d2750b7e..1155a3fa 100644 --- a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,22 +61,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -124,9 +109,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_time_get.S index ee4dd40c..335824fb 100644 --- a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_unprotect.S index ae700d1e..680e8bc8 100644 --- a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,21 +58,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_stack_build.S b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_stack_build.S index 746bbd42..581e259e 100644 --- a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_system_return.S index b889de21..23c75241 100644 --- a/ports_smp/cortex_a55_smp/ac6/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a55_smp/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a55_smp/ac6/src/tx_timer_interrupt.S b/ports_smp/cortex_a55_smp/ac6/src/tx_timer_interrupt.S index bad59269..5c6a6bc2 100644 --- a/ports_smp/cortex_a55_smp/ac6/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a55_smp/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/.cproject b/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/.cproject index 34967225..aab1eeaf 100644 --- a/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/sample_threadx.ld b/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/sample_threadx.ld index e9b12a82..1c6d45b5 100644 --- a/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start @@ -194,7 +194,7 @@ SECTIONS . = . + 4 * 0x8000; __stack = .; } - + .handler_stack_limit (NOLOAD): { . = ALIGN(64); diff --git a/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/v8_aarch64.h b/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports_smp/cortex_a55_smp/gnu/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_smp/cortex_a55_smp/gnu/example_build/tx/.cproject b/ports_smp/cortex_a55_smp/gnu/example_build/tx/.cproject index 3547a1d3..e3f31405 100644 --- a/ports_smp/cortex_a55_smp/gnu/example_build/tx/.cproject +++ b/ports_smp/cortex_a55_smp/gnu/example_build/tx/.cproject @@ -1,200 +1,200 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a55_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a55_smp/gnu/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_smp/cortex_a55_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a55_smp/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a55_smp/gnu/src/tx_initialize_low_level.S b/ports_smp/cortex_a55_smp/gnu/src/tx_initialize_low_level.S index b171fc0f..efb08b80 100644 --- a/ports_smp/cortex_a55_smp/gnu/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a55_smp/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_context_restore.S index c16c6dbb..5cd7a9df 100644 --- a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,22 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_context_save.S b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_context_save.S index c8281503..76641067 100644 --- a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_fp_disable.c b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_fp_enable.c b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_schedule.S index 52654783..de6b70dd 100644 --- a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* added memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_core_get.S index 684e317c..ea14c901 100644 --- a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_core_preempt.S index 903a5ab9..1d28907f 100644 --- a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,18 +62,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_current_state_get.S index 67b5b6f5..707b41d2 100644 --- a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_current_thread_get.S index 42d5776c..6c4bc9af 100644 --- a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_initialize_wait.S index f1c067cf..defd791c 100644 --- a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_low_level_initialize.S index 101a91f3..99b20d24 100644 --- a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_protect.S b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_protect.S index d2750b7e..1155a3fa 100644 --- a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,22 +61,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -124,9 +109,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_time_get.S index ee4dd40c..335824fb 100644 --- a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_unprotect.S index ae700d1e..680e8bc8 100644 --- a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,21 +58,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_stack_build.S b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_stack_build.S index 746bbd42..581e259e 100644 --- a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_system_return.S index b889de21..23c75241 100644 --- a/ports_smp/cortex_a55_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a55_smp/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a55_smp/gnu/src/tx_timer_interrupt.S b/ports_smp/cortex_a55_smp/gnu/src/tx_timer_interrupt.S index bad59269..5c6a6bc2 100644 --- a/ports_smp/cortex_a55_smp/gnu/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a55_smp/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/.cproject b/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/.cproject index 877492ef..52feb63d 100644 --- a/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/sample_threadx.scat index 1288a328..1ed382ae 100644 --- a/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/sample_threadx.scat @@ -12,13 +12,13 @@ LOAD 0x80000000 { startup.o (StartUp, +FIRST) * (+RO, +RW, +ZI) - + } ;XTABLES +0 ALIGN 0x1000 ;{ - ; xtables.o (*) + ; xtables.o (*) ;} - + SYS_STACK +0 ALIGN 8 EMPTY 0x1000 { } @@ -34,13 +34,13 @@ LOAD 0x80000000 ; All stacks and heap are aligned to a cache-line boundary ; ARM_LIB_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary ; HANDLER_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Stacks for EL3 ; @@ -217,34 +217,34 @@ LOAD 0x80000000 ; { ; *( +RO ) ; } -; +; ; XTABLES +0 ALIGN 0x1000 ; { -; xtables.o (*) +; xtables.o (*) ; } ;} ; ;RW AlignExpr(ImageLimit(XTABLES), 0x1000) -;{ +;{ ; RWSEC +0 ; { ; *( +RW ) ; } -; +; ; ZISEC +0 ; { ; *( +ZI ) ; } -; +; ; SYS_STACK +0 ALIGN 8 EMPTY 0x1000 ; { ; } -; +; ; ; 512 MiB heap ; HEAP +0 ALIGN 8 EMPTY 0x10000000 ; { ; } -; +; ; ; Free Memory section ; FREE_MEMORY +0 ALIGN 8 EMPTY 0x10000000 ; { @@ -254,7 +254,7 @@ LOAD 0x80000000 ; TASK_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { ; } -; +; ; ; Per-CPU 128 MiB handler stacks ; HANDLER_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { diff --git a/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/v8_aarch64.h b/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports_smp/cortex_a57_smp/ac6/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_smp/cortex_a57_smp/ac6/example_build/tx/.cproject b/ports_smp/cortex_a57_smp/ac6/example_build/tx/.cproject index 16d28cd0..2de8791d 100644 --- a/ports_smp/cortex_a57_smp/ac6/example_build/tx/.cproject +++ b/ports_smp/cortex_a57_smp/ac6/example_build/tx/.cproject @@ -1,188 +1,188 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a57_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a57_smp/ac6/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_smp/cortex_a57_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a57_smp/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a57_smp/ac6/src/tx_initialize_low_level.S b/ports_smp/cortex_a57_smp/ac6/src/tx_initialize_low_level.S index 7d2cfabf..08986f7b 100644 --- a/ports_smp/cortex_a57_smp/ac6/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a57_smp/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_context_restore.S index c16c6dbb..5cd7a9df 100644 --- a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,22 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_context_save.S b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_context_save.S index c8281503..76641067 100644 --- a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_fp_disable.c b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_fp_enable.c b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_schedule.S index 52654783..de6b70dd 100644 --- a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* added memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_core_get.S index 684e317c..ea14c901 100644 --- a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_core_preempt.S index 903a5ab9..1d28907f 100644 --- a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,18 +62,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_current_state_get.S index 67b5b6f5..707b41d2 100644 --- a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_current_thread_get.S index 42d5776c..6c4bc9af 100644 --- a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_initialize_wait.S index f1c067cf..defd791c 100644 --- a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_low_level_initialize.S index 101a91f3..99b20d24 100644 --- a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_protect.S b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_protect.S index d2750b7e..1155a3fa 100644 --- a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,22 +61,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -124,9 +109,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_time_get.S index ee4dd40c..335824fb 100644 --- a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_unprotect.S index ae700d1e..680e8bc8 100644 --- a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,21 +58,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_stack_build.S b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_stack_build.S index 746bbd42..581e259e 100644 --- a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_system_return.S index b889de21..23c75241 100644 --- a/ports_smp/cortex_a57_smp/ac6/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a57_smp/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a57_smp/ac6/src/tx_timer_interrupt.S b/ports_smp/cortex_a57_smp/ac6/src/tx_timer_interrupt.S index bad59269..5c6a6bc2 100644 --- a/ports_smp/cortex_a57_smp/ac6/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a57_smp/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/.cproject b/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/.cproject index 34967225..aab1eeaf 100644 --- a/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/sample_threadx.ld b/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/sample_threadx.ld index e9b12a82..1c6d45b5 100644 --- a/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start @@ -194,7 +194,7 @@ SECTIONS . = . + 4 * 0x8000; __stack = .; } - + .handler_stack_limit (NOLOAD): { . = ALIGN(64); diff --git a/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/v8_aarch64.h b/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports_smp/cortex_a57_smp/gnu/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_smp/cortex_a57_smp/gnu/example_build/tx/.cproject b/ports_smp/cortex_a57_smp/gnu/example_build/tx/.cproject index 3547a1d3..e3f31405 100644 --- a/ports_smp/cortex_a57_smp/gnu/example_build/tx/.cproject +++ b/ports_smp/cortex_a57_smp/gnu/example_build/tx/.cproject @@ -1,200 +1,200 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a57_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a57_smp/gnu/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_smp/cortex_a57_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a57_smp/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a57_smp/gnu/src/tx_initialize_low_level.S b/ports_smp/cortex_a57_smp/gnu/src/tx_initialize_low_level.S index b171fc0f..efb08b80 100644 --- a/ports_smp/cortex_a57_smp/gnu/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a57_smp/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_context_restore.S index c16c6dbb..5cd7a9df 100644 --- a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,22 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_context_save.S b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_context_save.S index c8281503..76641067 100644 --- a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_fp_disable.c b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_fp_enable.c b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_schedule.S index 52654783..de6b70dd 100644 --- a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* added memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_core_get.S index 684e317c..ea14c901 100644 --- a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_core_preempt.S index 903a5ab9..1d28907f 100644 --- a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,18 +62,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_current_state_get.S index 67b5b6f5..707b41d2 100644 --- a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_current_thread_get.S index 42d5776c..6c4bc9af 100644 --- a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_initialize_wait.S index f1c067cf..defd791c 100644 --- a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_low_level_initialize.S index 101a91f3..99b20d24 100644 --- a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_protect.S b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_protect.S index d2750b7e..1155a3fa 100644 --- a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,22 +61,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -124,9 +109,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_time_get.S index ee4dd40c..335824fb 100644 --- a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_unprotect.S index ae700d1e..680e8bc8 100644 --- a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,21 +58,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_stack_build.S b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_stack_build.S index 746bbd42..581e259e 100644 --- a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_system_return.S index b889de21..23c75241 100644 --- a/ports_smp/cortex_a57_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a57_smp/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a57_smp/gnu/src/tx_timer_interrupt.S b/ports_smp/cortex_a57_smp/gnu/src/tx_timer_interrupt.S index bad59269..5c6a6bc2 100644 --- a/ports_smp/cortex_a57_smp/gnu/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a57_smp/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/.cproject b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/.cproject index de33a4b6..fe6fe7b0 100644 --- a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/.cproject @@ -1,228 +1,228 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/.settings/language.settings.xml b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/.settings/language.settings.xml index 8d860a09..7cf15967 100644 --- a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/.settings/language.settings.xml +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/.settings/language.settings.xml @@ -1,506 +1,506 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_GIC.h b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_GIC.h index bcff9373..f1af87ca 100644 --- a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_GIC.h +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_GIC.h @@ -4,7 +4,7 @@ // // Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_GIC.s b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_GIC.s index a9c4520d..d601c211 100644 --- a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_GIC.s +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_GIC.s @@ -1,13 +1,13 @@ ;---------------------------------------------------------------- ; Copyright (c) 2005-2018 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ; ; Cortex-A5MP SMP example - Startup Code ;---------------------------------------------------------------- - + AREA MP_GIC, CODE, READONLY @@ -40,7 +40,7 @@ enableGIC PROC BX lr ENDP - + ; ------------------------------------------------------------ EXPORT disableGIC @@ -88,7 +88,7 @@ enableIntID PROC ENDP ; ------------------------------------------------------------ - + EXPORT disableIntID ; void disableIntID(unsigned int ID) ; Disables the interrupt source number ID @@ -129,7 +129,7 @@ setIntPriority PROC ; r0 = base addr ; r1 = priority ; r2 = ID - + ; Make sure that priority value is only 5 bits, and convert to expected format AND r1, r1, #0x1F MOV r1, r1, LSL #3 @@ -208,7 +208,7 @@ setPriorityMask PROC BX lr ENDP - + ; ------------------------------------------------------------ EXPORT setBinaryPoint @@ -249,7 +249,7 @@ writeEOI PROC BX lr ENDP - + ;---------------------------------------------------------------- ; SGI ;---------------------------------------------------------------- diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.h b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.h index 27a02dc7..cc0dfbae 100644 --- a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.h +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.h @@ -19,7 +19,7 @@ // r1: Increment value (ignored if auto_increment != 0) void init_global_timer(unsigned int auto_increment, unsigned int increment_value) -// Sets the comparator value for this CPU +// Sets the comparator value for this CPU void set_global_timer_comparator(unsigned int top, unsigned int bottom); // Starts the private timer diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.s b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.s index 17997051..2dd8fe66 100644 --- a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.s +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.s @@ -46,8 +46,8 @@ init_global_timer PROC STR r0, [r2, #0x208] ; Store to control register ; Store increment value - STREQ r1, [r2, #0x218] - + STREQ r1, [r2, #0x218] + ; Clear timer value MOV r0, #0x0 STR r0, [r2, #0x0] @@ -71,12 +71,12 @@ set_global_timer_comparator PROC LDR r1, [r2, #0x208] ; Read control reg BIC r3, r3, #0x02 ; Clear comparator enable bit STR r3, [r2, #0x208] ; Write modified value back - + ; Write the comparator registers STR r1, [r2, #0x210] ; Write lower 32 bits STR r0, [r2, #0x214] ; Write upper 32 bits DMB - + ; Re-enable the comparator ORR r3, r3, #0x02 ; Set comparator enable bit STR r3, [r2, #0x208] ; Write modified value back @@ -141,7 +141,7 @@ get_global_timer_count_loop BX lr ENDP - + ; ------------------------------------------------------------ EXPORT clear_global_timer_irq diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_Mutexes.h index e410677b..dc2cf932 100644 --- a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ // // Copyright (c) 2011-2014 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_Mutexes.s b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_Mutexes.s index 0574eab0..3074bad3 100644 --- a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_Mutexes.s +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_Mutexes.s @@ -3,11 +3,11 @@ ; ; Copyright (c) 2011-2012 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ; ------------------------------------------------------------ - + AREA MP_Mutexes, CODE, READONLY diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_PrivateTimer.s b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_PrivateTimer.s index f8a1eefa..cfd40bc4 100644 --- a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_PrivateTimer.s +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_PrivateTimer.s @@ -94,7 +94,7 @@ get_private_timer_count PROC BX lr ENDP - + ; ------------------------------------------------------------ EXPORT clear_private_timer_irq diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_SCU.h b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_SCU.h index a056bd3f..7465e7b7 100644 --- a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_SCU.h +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_SCU.h @@ -4,7 +4,7 @@ // // Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_SCU.s b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_SCU.s index 2c24df11..e3eb4ded 100644 --- a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_SCU.s +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_SCU.s @@ -1,13 +1,13 @@ ;---------------------------------------------------------------- ; Copyright (c) 2005-2018 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ; ; Cortex-A SMP example - Startup Code ;---------------------------------------------------------------- - + AREA MP_SCU, CODE, READONLY @@ -22,7 +22,7 @@ getNumCPUs PROC ; Get base address of private peripheral space MRC p15, 4, r0, c15, c0, 0 ; Read periph base address - + LDR r0, [r0, #0x004] ; Read SCU Configuration register AND r0, r0, #0x3 ; Bits 1:0 gives the number of cores-1 ADD r0, r0, #1 @@ -112,7 +112,7 @@ disableMaintenanceBroadcast PROC secureSCUInvalidate PROC AND r0, r0, #0x03 ; Mask off unused bits of CPU ID MOV r0, r0, LSL #2 ; Convert into bit offset (four bits per core) - + AND r1, r1, #0x0F ; Mask off unused bits of ways MOV r1, r1, LSL r0 ; Shift ways into the correct CPU field diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/sample_threadx.c index 1b6df7c2..5c1f4a16 100644 --- a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -63,7 +63,7 @@ UCHAR event_buffer[65536]; int main(void) { - + /* Enter ThreadX. */ tx_kernel_enter(); @@ -91,41 +91,41 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); - + /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -133,23 +133,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -252,11 +252,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -315,7 +315,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -368,7 +368,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/sample_threadx.sct b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/sample_threadx.sct index 6cdf755a..b89cd020 100644 --- a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/sample_threadx.sct +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/sample_threadx.sct @@ -1,7 +1,7 @@ ;************************************************** ; Copyright (c) 2012 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;************************************************** diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/startup.s b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/startup.s index ce0e75a3..2563c247 100644 --- a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/startup.s +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/startup.s @@ -3,7 +3,7 @@ ; ; Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ; ------------------------------------------------------------ @@ -159,7 +159,7 @@ by_pass ; MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register ; ANDS r0, r0, #0x03 ; Mask off, leaving the CPU ID field ; BNE by_pass2 -; +; ; MOV r0, #0x04 ; Code for SYS_WRITE0 ; LDR r1, =irq_handler_message1 ; SVC 0x123456 @@ -293,7 +293,7 @@ Reset_Handler PROC {} ; 0 - C 0x0 (Inner Noncachable) LDR r0, =||Image$$PAGETABLES$$ZI$$Base|| MSR TTBR0, r0 - + ; ; Activate VFP/NEON, if required @@ -341,7 +341,7 @@ primaryCPUInit PROC ; Translation tables ; ------------------- - ; The translation tables are generated at boot time. + ; The translation tables are generated at boot time. ; First the table is zeroed. Then the individual valid ; entries are written in ; @@ -434,7 +434,7 @@ ttb_zero_loop MOV r0, #0x1F BL setPriorityMask ; Set priority mask (local) - ; [EL] Change start - don't enable interrupts here! + ; [EL] Change start - don't enable interrupts here! ;CPSIE i ; Clear CPSR I bit ; [EL] Change end @@ -453,7 +453,7 @@ ttb_zero_loop MOV r1, #0x0 BL init_private_timer BL start_private_timer - + ; ; Enable receipt of SGI 0 ; ------------------------ diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/tx_initialize_low_level.s b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/tx_initialize_low_level.s index 1bf6a105..290ffdf8 100644 --- a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/tx_initialize_low_level.s +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/tx_initialize_low_level.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -41,10 +41,10 @@ ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_initialize_low_level SMP/Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -52,34 +52,28 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/v7.h b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/v7.h index 5a08b43f..c18b945c 100644 --- a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/v7.h +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/v7.h @@ -4,7 +4,7 @@ // // Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/v7.s b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/v7.s index 35a94ff8..6154246c 100644 --- a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/v7.s +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/v7.s @@ -3,11 +3,11 @@ ; ; Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ; ------------------------------------------------------------ - + AREA v7Opps,CODE,READONLY diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/tx/.cproject b/ports_smp/cortex_a5_smp/ac5/example_build/tx/.cproject index eff9f4dd..73792f3f 100644 --- a/ports_smp/cortex_a5_smp/ac5/example_build/tx/.cproject +++ b/ports_smp/cortex_a5_smp/ac5/example_build/tx/.cproject @@ -1,202 +1,202 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/tx/.settings/language.settings.xml b/ports_smp/cortex_a5_smp/ac5/example_build/tx/.settings/language.settings.xml index fc1f7590..7b7c2ae3 100644 --- a/ports_smp/cortex_a5_smp/ac5/example_build/tx/.settings/language.settings.xml +++ b/ports_smp/cortex_a5_smp/ac5/example_build/tx/.settings/language.settings.xml @@ -1,506 +1,506 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a5_smp/ac5/inc/tx_port.h b/ports_smp/cortex_a5_smp/ac5/inc/tx_port.h index 39c2b87d..e26d484b 100644 --- a/ports_smp/cortex_a5_smp/ac5/inc/tx_port.h +++ b/ports_smp/cortex_a5_smp/ac5/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h SMP/Cortex-A5/AC5 */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h SMP/Cortex-A5/AC5 */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -80,12 +72,12 @@ /* Define ThreadX SMP initialization macro. */ -#define TX_PORT_SPECIFIC_PRE_INITIALIZATION +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION /* Define ThreadX SMP pre-scheduler initialization. */ -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION /* Enable the inter-core interrupt logic. */ @@ -125,7 +117,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -138,7 +130,7 @@ #include -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -174,12 +166,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -189,8 +181,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -248,7 +240,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -262,13 +254,13 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -282,11 +274,11 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -294,8 +286,8 @@ ULONG _tx_misra_time_stamp_get(VOID); tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -321,17 +313,17 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE #ifndef __thumb - + #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (ULONG) __clz((unsigned int) m); \ - b = 31 - b; + b = 31 - b; #endif #endif @@ -346,22 +338,22 @@ struct TX_THREAD_STRUCT; typedef struct TX_THREAD_SMP_PROTECT_STRUCT { ULONG tx_thread_smp_protect_in_force; - struct TX_THREAD_STRUCT * + struct TX_THREAD_STRUCT * tx_thread_smp_protect_thread; ULONG tx_thread_smp_protect_core; ULONG tx_thread_smp_protect_count; - + /* Implementation specific information follows. */ - + ULONG tx_thread_smp_protect_get_caller; ULONG tx_thread_smp_protect_sr; ULONG tx_thread_smp_protect_release_caller; } TX_THREAD_SMP_PROTECT; -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -395,8 +387,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX SMP/Cortex-A5/AC5 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP/Cortex-A5/AC5 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a5_smp/ac5/readme_threadx.txt b/ports_smp/cortex_a5_smp/ac5/readme_threadx.txt index 4b11e210..73212010 100644 --- a/ports_smp/cortex_a5_smp/ac5/readme_threadx.txt +++ b/ports_smp/cortex_a5_smp/ac5/readme_threadx.txt @@ -6,16 +6,16 @@ 1. Import the ThreadX Projects -In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import -the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) into your DS workspace. 2. Building the ThreadX SMP run-time Library -Building the ThreadX SMP library is easy; simply select the Eclipse project file -"tx" and then select the build button. You should now observe the compilation -and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP +Building the ThreadX SMP library is easy; simply select the Eclipse project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP library file tx.a. @@ -24,49 +24,49 @@ library file tx.a. The ThreadX SMP demonstration is designed to execute under the DS debugger on the VE_Cortex-A5x4 Bare Metal simulator. -Building the demonstration is easy; simply open the workspace file, select the -sample_threadx project, and select the build button. Next, expand the demo ThreadX -project folder in the Project Explorer window, right-click on the 'sample_threadx.launch' +Building the demonstration is easy; simply open the workspace file, select the +sample_threadx project, and select the build button. Next, expand the demo ThreadX +project folder in the Project Explorer window, right-click on the 'sample_threadx.launch' file, click 'Debug As', and then click 'sample_threadx' from the submenu. This will cause the -debugger to load the sample_threadx.axf ELF file and run to main. You are now ready +debugger to load the sample_threadx.axf ELF file and run to main. You are now ready to execute the ThreadX demonstration. 4. System Initialization -The entry point in ThreadX for the Cortex-A5 using AC5 tools is at label +The entry point in ThreadX for the Cortex-A5 using AC5 tools is at label Reset_Handler in startup.s. After the basic core initialization is complete, -control will transfer to __main, which is where all static and global pre-set +control will transfer to __main, which is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. By default, the vector area is defined to be located in the Init area, -which is defined at the top of tx_initialize_low_level.s. This area is typically -located at 0. In situations where this is impossible, the vectors at the beginning +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. By default, the vector area is defined to be located in the Init area, +which is defined at the top of tx_initialize_low_level.s. This area is typically +located at 0. In situations where this is impossible, the vectors at the beginning of the Init area should be copied to address 0. This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 5. Register Usage and Stack Frames -The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -84,39 +84,39 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make it run faster, you can change the build_threadx.bat file to -remove the -g option and enable all compiler optimizations. +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A5 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-A5 vectors start at address zero. The demonstration system startup -Init area contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +Init area contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs @@ -127,12 +127,12 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.s: EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -140,7 +140,7 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -153,7 +153,7 @@ __tx_irq_processing_return 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.s: EXPORT __tx_irq_example_handler @@ -163,12 +163,12 @@ __tx_irq_example_handler STMDB sp!, {r0-r3} ; Save some scratch registers MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers BL _tx_thread_vectored_context_save ; Call the vectored IRQ context save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -185,22 +185,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.s. When nested IRQ interrupts are no longer required, calling the _tx_thread_irq_nesting_end service disables nesting by disabling -IRQ interrupts and switching back to IRQ mode in preparation for the IRQ +IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -208,10 +208,10 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* Enable nested IRQ interrupts. NOTE: Since this service returns -; with IRQ interrupts enabled, all IRQ interrupt sources must be +; with IRQ interrupts enabled, all IRQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start -; +; ; /* Application ISR call(s) go here! */ ; ; /* Disable nested IRQ interrupts. The mode is switched back to @@ -224,12 +224,12 @@ __tx_irq_processing_return 7.3 FIQ Interrupts -By default, Cortex-A5 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, Cortex-A5 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.s. @@ -238,7 +238,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.s. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.s: @@ -266,18 +266,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.s. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -293,7 +293,7 @@ __tx_fiq_processing_return ; interrupt, and all C scratch registers are available for use. */ ; ; /* Enable nested FIQ interrupts. NOTE: Since this service returns -; with FIQ interrupts enabled, all FIQ interrupt sources must be +; with FIQ interrupts enabled, all FIQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start ; @@ -309,29 +309,29 @@ __tx_fiq_processing_return 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.s in the Integrator sub-directories. 9. Thumb/Cortex-A5 Mixed Mode -By default, ThreadX is setup for running in Cortex-A5 32-bit mode. This is -also true for the demonstration system. It is possible to build any -ThreadX file and/or the application in Thumb mode. If any Thumb code -is used the entire ThreadX source- both C and assembly - should be built +By default, ThreadX is setup for running in Cortex-A5 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. If any Thumb code +is used the entire ThreadX source- both C and assembly - should be built with the "-apcs /interwork" option. 10. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_context_restore.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_context_restore.s index c36e57b5..21d63d05 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_context_restore.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -63,10 +63,10 @@ SVC_MODE EQU 0x93 ; SVC mode ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_context_restore SMP/Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -74,33 +74,27 @@ SVC_MODE EQU 0x93 ; SVC mode ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -137,13 +131,13 @@ _tx_thread_context_restore ADD r3, r3, r12 ; Build array offset LDR r2, [r3, #0] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3, #0] ; Store the counter + STR r2, [r3, #0] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -155,7 +149,7 @@ _tx_thread_context_restore __tx_thread_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr[core]) && (_tx_thread_current_ptr[core] == _tx_thread_execute_ptr[core]) +; else if (((_tx_thread_current_ptr[core]) && (_tx_thread_current_ptr[core] == _tx_thread_execute_ptr[core]) ; || (_tx_thread_preempt_disable)) ; { ; @@ -346,7 +340,7 @@ __tx_thread_dont_save_ts ; ; /* Set bit indicating this thread is ready for execution. */ ; - LDR r2, [r0, #152] ; Pickup the ready bit + LDR r2, [r0, #152] ; Pickup the ready bit ORR r2, r2, #0x8000 ; Set ready bit (bit 15) STR r2, [r0, #152] ; Make this thread ready for executing again DMB ; Ensure that accesses to shared resource have completed diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_context_save.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_context_save.s index 1f397a0c..33047893 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_context_save.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,10 +39,10 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_context_save SMP/Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -50,32 +50,26 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -90,13 +84,13 @@ _tx_thread_context_save ; if (_tx_thread_system_state[core]++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers ; ; /* Save the rest of the scratch registers on the stack and return to the ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; IF :DEF:TX_ENABLE_FIQ_SUPPORT @@ -133,7 +127,7 @@ _tx_thread_context_save POP {r12, lr} ; Recover ISR lr & r12 ENDIF - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; __tx_thread_not_nested_save ; } @@ -148,7 +142,7 @@ __tx_thread_not_nested_save ADD r1, r1, r12 ; Build index into current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Save the current stack pointer in the thread's control block. */ @@ -168,7 +162,7 @@ __tx_thread_not_nested_save POP {r12, lr} ; Recover ISR lr & r12 ENDIF - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ; else @@ -178,7 +172,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit @@ -193,7 +187,7 @@ __tx_thread_idle_system_save ENDIF ADD sp, sp, #32 ; Recover saved registers - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ;} diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_control.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_control.s index 2f11cb0d..2d64b0d5 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_control.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,10 +36,10 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_interrupt_control SMP/Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -47,31 +47,25 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_disable.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_disable.s index 74113a37..89eea8fb 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_disable.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_disable.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,10 +29,10 @@ ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_interrupt_disable SMP/Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -40,30 +40,24 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(void) @@ -80,7 +74,7 @@ _tx_thread_interrupt_disable IF :DEF:TX_ENABLE_FIQ_SUPPORT CPSID if ; Disable IRQ and FIQ ELSE - CPSID i ; Disable IRQ + CPSID i ; Disable IRQ ENDIF IF {INTER} = {TRUE} diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_restore.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_restore.s index feb33697..922f377d 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_restore.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,10 +29,10 @@ ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_interrupt_restore SMP/Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -40,31 +40,25 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function is responsible for restoring interrupts to the state */ ;/* returned by a previous _tx_thread_interrupt_disable call. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_irq_nesting_end.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_irq_nesting_end.s index 3be434aa..923aa564 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_irq_nesting_end.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_irq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,15 +34,15 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_irq_nesting_end SMP/Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -50,40 +50,34 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -;/* processing from system mode back to IRQ mode prior to the ISR */ -;/* calling _tx_thread_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) @@ -94,7 +88,7 @@ _tx_thread_irq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_c, r0 ; Disable interrupts - LDMIA sp!, {lr, r1} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {lr, r1} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_irq_nesting_start.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_irq_nesting_start.s index 0b7b2039..e575871e 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_irq_nesting_start.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_irq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,10 +35,10 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_irq_nesting_start SMP/Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -46,37 +46,31 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_context_save has been called and switches the IRQ */ -;/* processing to the system mode so nested IRQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_schedule.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_schedule.s index 9ec7844e..e4c232aa 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_schedule.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_schedule.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -40,45 +40,39 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule SMP/Cortex-A5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule SMP/Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -122,7 +116,7 @@ _tx_thread_schedule ; ; } ; while(_tx_thread_execute_ptr[core] == TX_NULL); -; +; ; ; /* Get the lock for accessing the thread's ready bit. */ ; @@ -186,7 +180,7 @@ _tx_thread_ready_for_execution MOV r1, #0 ; Build clear value STR r1, [r2, #0] ; Clear current thread pointer - LDR r1, [r0, #152] ; Pickup the ready bit + LDR r1, [r0, #152] ; Pickup the ready bit ORR r1, r1, #0x8000 ; Set ready bit (bit 15) STR r1, [r0, #152] ; Make this thread ready for executing again DMB ; Ensure that accesses to shared resource have completed @@ -205,7 +199,7 @@ _execute_pointer_did_not_change ; /* Setup time-slice, if present. */ ; _tx_timer_time_slice[core] = _tx_thread_current_ptr[core] -> tx_thread_time_slice; ; - LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice ; variable ADD r2, r2, r12 ; Build index into the time-slice array LDR sp, [r0, #8] ; Switch stack pointers @@ -241,7 +235,7 @@ _execute_pointer_did_not_change _tx_skip_interrupt_vfp_restore ENDIF LDMIA sp!, {r0-r12, lr, pc}^ ; Return to point of thread interrupt - + _tx_solicited_return IF {TARGET_FPU_VFP} = {TRUE} MSR CPSR_cxsf, r5 ; Recover CPSR diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_core_get.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_core_get.s index fb833b88..90e165eb 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_core_get.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_core_get.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -32,10 +32,10 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_smp_core_get SMP/Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -43,30 +43,24 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function gets the currently running core number and returns it.*/ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* Core ID */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX Source */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function gets the currently running core number and returns it.*/ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* Core ID */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_core_get @@ -81,4 +75,4 @@ _tx_thread_smp_core_get ENDIF END - + diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_core_preempt.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_core_preempt.s index e0dde774..3fc3e846 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_core_preempt.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_core_preempt.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -34,45 +34,39 @@ AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_smp_core_preempt SMP/Cortex-A5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_core_preempt SMP/Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function preempts the specified core in situations where the */ -;/* thread corresponding to this core is no longer ready or when the */ -;/* core must be used for a higher-priority thread. If the specified is */ -;/* the current core, this processing is skipped since the will give up */ -;/* control subsequently on its own. */ -;/* */ -;/* INPUT */ -;/* */ -;/* core The core to preempt */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX Source */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function preempts the specified core in situations where the */ +;/* thread corresponding to this core is no longer ready or when the */ +;/* core must be used for a higher-priority thread. If the specified is */ +;/* the current core, this processing is skipped since the will give up */ +;/* control subsequently on its own. */ +;/* */ +;/* INPUT */ +;/* */ +;/* core The core to preempt */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_core_preempt @@ -82,11 +76,11 @@ _tx_thread_smp_core_preempt ; ; /* Place call to send inter-processor interrupt here! */ ; - DSB ; - MOV r1, #1 ; Build parameter list - LSL r1, r1, r0 ; - MOV r0, #0 ; - MOV r2, #0 ; + DSB ; + MOV r1, #1 ; Build parameter list + LSL r1, r1, r0 ; + MOV r0, #0 ; + MOV r2, #0 ; BL sendSGI ; Make call to send inter-processor interrupt LDMIA sp!, {lr, r4} ; Recover lr register and r4 @@ -97,4 +91,4 @@ _tx_thread_smp_core_preempt ENDIF END - + diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_current_state_get.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_current_state_get.s index 34e33c1f..04d5db85 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_current_state_get.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_current_state_get.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -34,10 +34,10 @@ AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_smp_current_state_get SMP/Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -45,30 +45,24 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is gets the current state of the calling core. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX Components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is gets the current state of the calling core. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Components */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_current_state_get @@ -91,7 +85,7 @@ _tx_thread_smp_current_state_get LDR r1, =_tx_thread_system_state ; Pickup start of the current state array ADD r1, r1, r2 ; Build index into the current state array LDR r0, [r1] ; Pickup state for this core - MSR CPSR_c, r3 ; Restore CPSR + MSR CPSR_c, r3 ; Restore CPSR IF {INTER} = {TRUE} BX lr ; Return to caller ELSE diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_current_thread_get.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_current_thread_get.s index 7f7d3bfd..ef51ef01 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_current_thread_get.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_current_thread_get.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -34,10 +34,10 @@ AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_smp_current_thread_get SMP/Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -45,30 +45,24 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is gets the current thread of the calling core. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX Components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is gets the current thread of the calling core. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Components */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_current_thread_get @@ -91,7 +85,7 @@ _tx_thread_smp_current_thread_get LDR r1, =_tx_thread_current_ptr ; Pickup start of the current thread array ADD r1, r1, r2 ; Build index into the current thread array LDR r0, [r1] ; Pickup current thread for this core - MSR CPSR_c, r3 ; Restore CPSR + MSR CPSR_c, r3 ; Restore CPSR IF {INTER} = {TRUE} BX lr ; Return to caller ELSE diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_initialize_wait.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_initialize_wait.s index 6077bc0b..2fed8a90 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_initialize_wait.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_initialize_wait.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -37,10 +37,10 @@ AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_smp_initialize_wait SMP/Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -48,32 +48,26 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is the place where additional cores wait until */ -;/* initialization is complete before they enter the thread scheduling */ -;/* loop. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Hardware */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is the place where additional cores wait until */ +;/* initialization is complete before they enter the thread scheduling */ +;/* loop. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Hardware */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_initialize_wait @@ -93,7 +87,7 @@ _tx_thread_smp_initialize_wait AND r10, r10, #0x03 ; Mask off, leaving the CPU ID field LSL r10, r10, #2 ; Build offset to array indexes ; -; /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release +; /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release ; flag. */ ; LDR r3, =_tx_thread_system_state ; Build address of system state variable @@ -111,10 +105,10 @@ wait_for_initialize wait_for_release LDR r3, [r2] ; Pickup the flag CMP r3, #0 ; Is it set? - BEQ wait_for_release ; Wait for the flag to be set + BEQ wait_for_release ; Wait for the flag to be set ; ; /* Core 0 has released this core. */ -; +; ; /* Clear this core's system state variable. */ ; LDR r3, =_tx_thread_system_state ; Build address of system state variable @@ -124,7 +118,7 @@ wait_for_release ; ; /* Now wait for core 0 to finish it's initialization. */ ; - LDR r3, =_tx_thread_system_state ; Build address of system state variable of logical 0 + LDR r3, =_tx_thread_system_state ; Build address of system state variable of logical 0 core_0_wait_loop LDR r2, [r3] ; Pickup system state for core 0 diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_low_level_initialize.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_low_level_initialize.s index c74dede1..023c6004 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_low_level_initialize.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_low_level_initialize.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -32,10 +32,10 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_smp_low_level_initialize SMP/Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -43,31 +43,25 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function performs low-level initialization of the booting */ -;/* core. */ -;/* */ -;/* INPUT */ -;/* */ -;/* number_of_cores Number of cores */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_high_level ThreadX high-level init */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function performs low-level initialization of the booting */ +;/* core. */ +;/* */ +;/* INPUT */ +;/* */ +;/* number_of_cores Number of cores */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_high_level ThreadX high-level init */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_low_level_initialize diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_protect.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_protect.s index 9743dc28..a7419c10 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_protect.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_protect.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -45,43 +45,37 @@ AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_smp_protect SMP/Cortex-A5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_protect SMP/Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function gets protection for running inside the ThreadX */ -;/* source. This is acomplished by a combination of a test-and-set */ -;/* flag and periodically disabling interrupts. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* Previous Status Register */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX Source */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function gets protection for running inside the ThreadX */ +;/* source. This is acomplished by a combination of a test-and-set */ +;/* flag and periodically disabling interrupts. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* Previous Status Register */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_protect diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_protection_wait_list_macros.h index 192df07b..fec51581 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_time_get.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_time_get.s index 4dec5889..a378060e 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_time_get.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_time_get.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -33,10 +33,10 @@ AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_smp_time_get SMP/Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -44,31 +44,25 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function gets the global time value that is used for debug */ -;/* information and event tracing. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* 32-bit time stamp */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX Source */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function gets the global time value that is used for debug */ +;/* information and event tracing. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* 32-bit time stamp */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_time_get @@ -84,4 +78,4 @@ _tx_thread_smp_time_get ENDIF END - + diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_unprotect.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_unprotect.s index 96744bd3..61645b3e 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_unprotect.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_unprotect.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -37,44 +37,38 @@ AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_smp_unprotect SMP/Cortex-A5/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_unprotect SMP/Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function releases previously obtained protection. The supplied */ -;/* previous SR is restored. If the value of _tx_thread_system_state */ -;/* and _tx_thread_preempt_disable are both zero, then multithreading */ -;/* is enabled as well. */ -;/* */ -;/* INPUT */ -;/* */ -;/* Previous Status Register */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX Source */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function releases previously obtained protection. The supplied */ +;/* previous SR is restored. If the value of _tx_thread_system_state */ +;/* and _tx_thread_preempt_disable are both zero, then multithreading */ +;/* is enabled as well. */ +;/* */ +;/* INPUT */ +;/* */ +;/* Previous Status Register */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_unprotect diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_stack_build.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_stack_build.s index 826bdadd..c3d13335 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_stack_build.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_stack_build.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -41,10 +41,10 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_stack_build SMP/Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -52,33 +52,27 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function builds a stack frame on the supplied thread's stack. */ ;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ ;/* thread_ptr Pointer to thread control blk */ ;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -86,10 +80,10 @@ THUMB_BIT EQU 0x20 ; Thumb-bit EXPORT _tx_thread_stack_build _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-A5 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; a1 (r0) Initial value for a1 diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_system_return.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_system_return.s index 253c7a15..da21d7c1 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_system_return.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_system_return.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,16 +35,16 @@ IMPORT _tx_thread_preempt_disable IMPORT _tx_thread_smp_protection IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY - IMPORT _tx_execution_thread_exit + IMPORT _tx_execution_thread_exit ENDIF ; ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_system_return SMP/Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -52,33 +52,27 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -112,7 +106,7 @@ _tx_skip_solicited_vfp_save MOV r4, #0 ; Build a solicited stack type MRS r5, CPSR ; Pickup the CPSR STMDB sp!, {r4-r5} ; Save type and CPSR -; +; ; /* Lockout interrupts. */ ; IF :DEF:TX_ENABLE_FIQ_SUPPORT @@ -184,8 +178,8 @@ __tx_thread_dont_save_ts CMP r0, r2 ; Is it the same as the current thread? __error_loop BNE __error_loop ; If not, we have a problem!! - ENDIF - + ENDIF + LDR r1, =_tx_thread_preempt_disable ; Build address to preempt disable flag MOV r2, #0 ; Build clear value STR r2, [r1, #0] ; Clear preempt disable flag diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_vectored_context_save.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_vectored_context_save.s index ffc26813..69a22693 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_vectored_context_save.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_vectored_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -38,10 +38,10 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_vectored_context_save SMP/Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -49,32 +49,26 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) @@ -144,7 +138,7 @@ __tx_thread_not_nested_save ADD r1, r1, r12 ; Build index into current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Note: Minimal context of interrupted thread is already saved. */ @@ -180,7 +174,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_timer_interrupt.s b/ports_smp/cortex_a5_smp/ac5/src/tx_timer_interrupt.s index 525d7257..9a4da253 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_timer_interrupt.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_timer_interrupt.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -49,10 +49,10 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_timer_interrupt SMP/Cortex-A5/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -60,37 +60,31 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* _tx_thread_smp_protect Get SMP protection */ -;/* _tx_thread_smp_unprotect Releast SMP protection */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* _tx_thread_smp_protect Get SMP protection */ +;/* _tx_thread_smp_unprotect Releast SMP protection */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -199,7 +193,7 @@ __tx_timer_done __tx_timer_dont_activate ; ; /* Call time-slice processing. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing ; diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/MP_GIC.S b/ports_smp/cortex_a5_smp/gnu/example_build/MP_GIC.S index 2ff179fb..a3274f21 100644 --- a/ports_smp/cortex_a5_smp/gnu/example_build/MP_GIC.S +++ b/ports_smp/cortex_a5_smp/gnu/example_build/MP_GIC.S @@ -3,7 +3,7 @@ // // Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/MP_GIC.h b/ports_smp/cortex_a5_smp/gnu/example_build/MP_GIC.h index 1d047611..42a96c3d 100644 --- a/ports_smp/cortex_a5_smp/gnu/example_build/MP_GIC.h +++ b/ports_smp/cortex_a5_smp/gnu/example_build/MP_GIC.h @@ -4,7 +4,7 @@ // // Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/MP_Mutexes.S b/ports_smp/cortex_a5_smp/gnu/example_build/MP_Mutexes.S index 771e3321..75bde148 100644 --- a/ports_smp/cortex_a5_smp/gnu/example_build/MP_Mutexes.S +++ b/ports_smp/cortex_a5_smp/gnu/example_build/MP_Mutexes.S @@ -3,13 +3,13 @@ // // Copyright (c) 2011-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ .text - .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame //NOTES diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/MP_Mutexes.h b/ports_smp/cortex_a5_smp/gnu/example_build/MP_Mutexes.h index e410677b..dc2cf932 100644 --- a/ports_smp/cortex_a5_smp/gnu/example_build/MP_Mutexes.h +++ b/ports_smp/cortex_a5_smp/gnu/example_build/MP_Mutexes.h @@ -3,7 +3,7 @@ // // Copyright (c) 2011-2014 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/MP_PrivateTimer.S b/ports_smp/cortex_a5_smp/gnu/example_build/MP_PrivateTimer.S index 2077d917..58e5afd4 100644 --- a/ports_smp/cortex_a5_smp/gnu/example_build/MP_PrivateTimer.S +++ b/ports_smp/cortex_a5_smp/gnu/example_build/MP_PrivateTimer.S @@ -93,7 +93,7 @@ get_private_timer_count: LDR r0, [r0, #0x604] // Read count register BX lr - + // ------------------------------------------------------------ // void clear_private_timer_irq(void) diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/MP_SCU.S b/ports_smp/cortex_a5_smp/gnu/example_build/MP_SCU.S index bd4c667b..be6d8b19 100644 --- a/ports_smp/cortex_a5_smp/gnu/example_build/MP_SCU.S +++ b/ports_smp/cortex_a5_smp/gnu/example_build/MP_SCU.S @@ -4,7 +4,7 @@ // // Copyright (c) 2011-2015 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/MP_SCU.h b/ports_smp/cortex_a5_smp/gnu/example_build/MP_SCU.h index af4ccfb8..b20b3d0f 100644 --- a/ports_smp/cortex_a5_smp/gnu/example_build/MP_SCU.h +++ b/ports_smp/cortex_a5_smp/gnu/example_build/MP_SCU.h @@ -4,7 +4,7 @@ // // Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/sample_threadx.c b/ports_smp/cortex_a5_smp/gnu/example_build/sample_threadx.c index 1b6df7c2..5c1f4a16 100644 --- a/ports_smp/cortex_a5_smp/gnu/example_build/sample_threadx.c +++ b/ports_smp/cortex_a5_smp/gnu/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -63,7 +63,7 @@ UCHAR event_buffer[65536]; int main(void) { - + /* Enter ThreadX. */ tx_kernel_enter(); @@ -91,41 +91,41 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); - + /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -133,23 +133,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -252,11 +252,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -315,7 +315,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -368,7 +368,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/sample_threadx.ld b/ports_smp/cortex_a5_smp/gnu/example_build/sample_threadx.ld index fb1ca03c..6b4f194a 100644 --- a/ports_smp/cortex_a5_smp/gnu/example_build/sample_threadx.ld +++ b/ports_smp/cortex_a5_smp/gnu/example_build/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * Vectors : Entry point - * + * * It defines following symbols, which code can use without definition: * __code_start * __exidx_start @@ -170,7 +170,7 @@ SECTIONS __irq_stack = .; _stack_init_irq = .; } - + _end = .; .pagetable 0x80100000 (NOLOAD): diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/startup.S b/ports_smp/cortex_a5_smp/gnu/example_build/startup.S index 65b1ba90..365e2858 100644 --- a/ports_smp/cortex_a5_smp/gnu/example_build/startup.S +++ b/ports_smp/cortex_a5_smp/gnu/example_build/startup.S @@ -213,7 +213,7 @@ by_pass: // MRC p15, 0, r0, c0, c0, 5 // Read CPU ID register // ANDS r0, r0, #0x03 // Mask off, leaving the CPU ID field // BNE by_pass2 -// +// // MOV r0, #0x04 // Code for SYS_WRITE0 // LDR r1, =irq_handler_message1 // SVC 0x123456 @@ -587,7 +587,7 @@ primaryCPUInit: MOV r0, #0x1F BL setPriorityMask // Set priority mask (local) - // [EL] Change start - don't enable interrupts here! + // [EL] Change start - don't enable interrupts here! //CPSIE i // Clear CPSR I bit // [EL] Change end @@ -606,7 +606,7 @@ primaryCPUInit: MOV r1, #0x0 BL init_private_timer BL start_private_timer - + // // Enable receipt of SGI 0 // ------------------------ diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/tx_initialize_low_level.s b/ports_smp/cortex_a5_smp/gnu/example_build/tx_initialize_low_level.s index 1aa56dae..56066e5d 100644 --- a/ports_smp/cortex_a5_smp/gnu/example_build/tx_initialize_low_level.s +++ b/ports_smp/cortex_a5_smp/gnu/example_build/tx_initialize_low_level.s @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Initialize */ @/** */ @@ -43,10 +43,10 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ @/* _tx_initialize_low_level SMP/Cortex-A5/GNU */ @/* 6.1 */ @/* AUTHOR */ @@ -54,41 +54,35 @@ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is responsible for any low-level processor */ -@/* initialization, including setting up interrupt vectors, setting */ -@/* up a periodic timer interrupt source, saving the system stack */ -@/* pointer for use in ISR processing later, and finding the first */ -@/* available RAM memory address for tx_application_define. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_initialize_kernel_enter ThreadX entry function */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) @{ .global _tx_initialize_low_level .type _tx_initialize_low_level,function -_tx_initialize_low_level: +_tx_initialize_low_level: @ @ /* Save the first available memory address. */ @ _tx_initialize_unused_memory = (VOID_PTR) _end; diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/v7.S b/ports_smp/cortex_a5_smp/gnu/example_build/v7.S index 67ddb163..dbb4552f 100644 --- a/ports_smp/cortex_a5_smp/gnu/example_build/v7.S +++ b/ports_smp/cortex_a5_smp/gnu/example_build/v7.S @@ -3,7 +3,7 @@ // // Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ @@ -20,7 +20,7 @@ .global enableInterrupts // void enableInterrupts(void) .type enableInterrupts, "function" - .cfi_startproc + .cfi_startproc enableInterrupts: CPSIE i BX lr @@ -30,7 +30,7 @@ enableInterrupts: .global disableInterrupts // void disableInterrupts(void) .type disableInterrupts, "function" - .cfi_startproc + .cfi_startproc disableInterrupts: CPSID i BX lr @@ -122,7 +122,7 @@ clean_dcache_skip: CMP r3, r10 BGT clean_dcache_loop1 -clean_dcache_finished: +clean_dcache_finished: POP {r4-r12} BX lr @@ -180,7 +180,7 @@ clean_invalidate_dcache_skip: CMP r3, r10 BGT clean_invalidate_dcache_loop1 -clean_invalidate_dcache_finished: +clean_invalidate_dcache_finished: POP {r4-r12} BX lr diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/v7.h b/ports_smp/cortex_a5_smp/gnu/example_build/v7.h index 5a08b43f..c18b945c 100644 --- a/ports_smp/cortex_a5_smp/gnu/example_build/v7.h +++ b/ports_smp/cortex_a5_smp/gnu/example_build/v7.h @@ -4,7 +4,7 @@ // // Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a5_smp/gnu/inc/tx_port.h index 9fcd1aeb..324e2f54 100644 --- a/ports_smp/cortex_a5_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a5_smp/gnu/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h SMP/Cortex-A5/GNU */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h SMP/Cortex-A5/GNU */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -80,12 +72,12 @@ /* Define ThreadX SMP initialization macro. */ -#define TX_PORT_SPECIFIC_PRE_INITIALIZATION +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION /* Define ThreadX SMP pre-scheduler initialization. */ -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION /* Enable the inter-core interrupt logic. */ @@ -125,7 +117,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -138,7 +130,7 @@ #include -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -174,12 +166,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -189,8 +181,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -248,7 +240,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -262,13 +254,13 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -282,11 +274,11 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -294,8 +286,8 @@ ULONG _tx_misra_time_stamp_get(VOID); tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -321,8 +313,8 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -330,10 +322,10 @@ ULONG _tx_misra_time_stamp_get(VOID); #if __TARGET_ARCH_ARM > 4 #ifndef __thumb__ - + #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ asm volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); \ - b = 31 - b; + b = 31 - b; #endif #endif #endif @@ -349,22 +341,22 @@ struct TX_THREAD_STRUCT; typedef struct TX_THREAD_SMP_PROTECT_STRUCT { ULONG tx_thread_smp_protect_in_force; - struct TX_THREAD_STRUCT * + struct TX_THREAD_STRUCT * tx_thread_smp_protect_thread; ULONG tx_thread_smp_protect_core; ULONG tx_thread_smp_protect_count; - + /* Implementation specific information follows. */ - + ULONG tx_thread_smp_protect_get_caller; ULONG tx_thread_smp_protect_sr; ULONG tx_thread_smp_protect_release_caller; } TX_THREAD_SMP_PROTECT; -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -398,8 +390,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX SMP/Cortex-A5/GNU Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP/Cortex-A5/GNU Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a5_smp/gnu/readme_threadx.txt b/ports_smp/cortex_a5_smp/gnu/readme_threadx.txt index a4f0e412..b4582ecc 100644 --- a/ports_smp/cortex_a5_smp/gnu/readme_threadx.txt +++ b/ports_smp/cortex_a5_smp/gnu/readme_threadx.txt @@ -4,16 +4,16 @@ 1. Building the ThreadX run-time Library -First make sure you are in the "example_build" directory. Also, make sure that -you have setup your path and other environment variables necessary for the GNU -development environment. +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the GNU +development environment. -At this point you may run the build_threadx.bat batch file. This will build the -ThreadX run-time environment in the "example_build" directory. +At this point you may run the build_threadx.bat batch file. This will build the +ThreadX run-time environment in the "example_build" directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. @@ -21,49 +21,49 @@ application in order to use ThreadX. The ThreadX demonstration is designed to execute under the ARM Cortex-A5x4 FVP. -Building the demonstration is easy; simply execute the build_threadx_sample.bat -batch file while inside the "example_build" directory. +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with TX.A. The resulting file DEMO is a binary file +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with TX.A. The resulting file DEMO is a binary file that can be downloaded and executed. 3. System Initialization -The entry point in ThreadX for the Cortex-A5 using GNU tools is at label +The entry point in ThreadX for the Cortex-A5 using GNU tools is at label Reset_Handler in startup.s. After the basic core initialization is complete, -control will transfer to __main, which is where all static and global pre-set +control will transfer to __main, which is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. By default, the vector area is defined to be located in the Init area, -which is defined at the top of tx_initialize_low_level.s. This area is typically -located at 0. In situations where this is impossible, the vectors at the beginning +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. By default, the vector area is defined to be located in the Init area, +which is defined at the top of tx_initialize_low_level.s. This area is typically +located at 0. In situations where this is impossible, the vectors at the beginning of the Init area should be copied to address 0. This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 4. Register Usage and Stack Frames -The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -81,39 +81,39 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 5. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make it run faster, you can change the build_threadx.bat file to -remove the -g option and enable all compiler optimizations. +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A5 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 6.1 Vector Area The Cortex-A5 vectors start at address zero. The demonstration system startup -Init area contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +Init area contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 6.2 IRQ ISRs @@ -124,12 +124,12 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 6.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.s: EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -137,7 +137,7 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -150,7 +150,7 @@ __tx_irq_processing_return 6.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.s: EXPORT __tx_irq_example_handler @@ -160,12 +160,12 @@ __tx_irq_example_handler STMDB sp!, {r0-r3} ; Save some scratch registers MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers BL _tx_thread_vectored_context_save ; Call the vectored IRQ context save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -182,22 +182,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.s. When nested IRQ interrupts are no longer required, calling the _tx_thread_irq_nesting_end service disables nesting by disabling -IRQ interrupts and switching back to IRQ mode in preparation for the IRQ +IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -205,10 +205,10 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* Enable nested IRQ interrupts. NOTE: Since this service returns -; with IRQ interrupts enabled, all IRQ interrupt sources must be +; with IRQ interrupts enabled, all IRQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start -; +; ; /* Application ISR call(s) go here! */ ; ; /* Disable nested IRQ interrupts. The mode is switched back to @@ -221,12 +221,12 @@ __tx_irq_processing_return 6.3 FIQ Interrupts -By default, Cortex-A5 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, Cortex-A5 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.s. @@ -235,7 +235,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.s. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.s: @@ -263,18 +263,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.s. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -290,7 +290,7 @@ __tx_fiq_processing_return ; interrupt, and all C scratch registers are available for use. */ ; ; /* Enable nested FIQ interrupts. NOTE: Since this service returns -; with FIQ interrupts enabled, all FIQ interrupt sources must be +; with FIQ interrupts enabled, all FIQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start ; @@ -306,19 +306,19 @@ __tx_fiq_processing_return 7. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.s in the Integrator sub-directories. 8. VFP Support -VFP support is optional, it can be enabled by building the ThreadX library +VFP support is optional, it can be enabled by building the ThreadX library assembly code with the following command-line option: -mfpu=neon -DTARGET_FPU_VFP diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_context_restore.S index c652d632..53ca2cc2 100644 --- a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_context_restore.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -64,10 +64,10 @@ SVC_MODE = 0x93 @ SVC mode .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ @/* _tx_thread_context_restore SMP/Cortex-A5/GNU */ @/* 6.1 */ @/* AUTHOR */ @@ -75,40 +75,34 @@ SVC_MODE = 0x93 @ SVC mode @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function restores the interrupt context if it is processing a */ -@/* nested interrupt. If not, it returns to the interrupt thread if no */ -@/* preemption is necessary. Otherwise, if preemption is necessary or */ -@/* if no thread was running, the function returns to the scheduler. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling routine */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs Interrupt Service Routines */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) @{ .global _tx_thread_context_restore .type _tx_thread_context_restore,function -_tx_thread_context_restore: +_tx_thread_context_restore: @ @ /* Lockout interrupts. */ @ @@ -139,13 +133,13 @@ _tx_thread_context_restore: ADD r3, r3, r12 @ Build array offset LDR r2, [r3, #0] @ Pickup system state SUB r2, r2, #1 @ Decrement the counter - STR r2, [r3, #0] @ Store the counter + STR r2, [r3, #0] @ Store the counter CMP r2, #0 @ Was this the first interrupt? BEQ __tx_thread_not_nested_restore @ If so, not a nested restore @ @ /* Interrupts are nested. */ @ -@ /* Just recover the saved registers and return to the point of +@ /* Just recover the saved registers and return to the point of @ interrupt. */ @ LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs @@ -154,10 +148,10 @@ _tx_thread_context_restore: MOVS pc, lr @ Return to point of interrupt @ @ } -__tx_thread_not_nested_restore: +__tx_thread_not_nested_restore: @ @ /* Determine if a thread was interrupted and no preemption is required. */ -@ else if (((_tx_thread_current_ptr[core]) && (_tx_thread_current_ptr[core] == _tx_thread_execute_ptr[core]) +@ else if (((_tx_thread_current_ptr[core]) && (_tx_thread_current_ptr[core] == _tx_thread_execute_ptr[core]) @ || (_tx_thread_preempt_disable)) @ { @ @@ -176,7 +170,7 @@ __tx_thread_not_nested_restore: LDR r2, [r3, #0] @ Pickup actual preempt disable flag CMP r2, #0 @ Is it set? BNE __tx_thread_no_preempt_restore @ Yes, don't preempt this thread -__tx_thread_skip_preempt_check: +__tx_thread_skip_preempt_check: LDR r3, =_tx_thread_execute_ptr @ Pickup address of execute thread ptr ADD r3, r3, r12 @ Build index to this core's execute thread ptr @@ -185,7 +179,7 @@ __tx_thread_skip_preempt_check: BNE __tx_thread_preempt_restore @ No, preemption needs to happen @ @ -__tx_thread_no_preempt_restore: +__tx_thread_no_preempt_restore: @ @ /* Restore interrupted thread or ISR. */ @ @@ -203,7 +197,7 @@ __tx_thread_no_preempt_restore: @ else @ { @ -__tx_thread_preempt_restore: +__tx_thread_preempt_restore: @ @ /* Was the thread being preempted waiting for the lock? */ @ if (_tx_thread_smp_protect_wait_counts[this_core] != 0) @@ -237,7 +231,7 @@ __tx_thread_preempt_restore: @ never released it because it saw that there was someone waiting. @ Note this core is not in the list. */ @ -_this_core_has_lock: +_this_core_has_lock: @ @ /* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */ @ _tx_thread_smp_protect_wait_counts[core]--; @@ -274,7 +268,7 @@ _this_core_has_lock: @ } @ -_nobody_waiting_for_lock: +_nobody_waiting_for_lock: LDMIA sp!, {r3, r10, r12, lr} @ Recover temporarily saved registers MOV r1, lr @ Save lr (point of interrupt) @@ -305,7 +299,7 @@ _nobody_waiting_for_lock: STR r2, [sp, #-4]! @ Save FPSCR VSTMDB sp!, {D16-D31} @ Save D16-D31 VSTMDB sp!, {D0-D15} @ Save D0-D15 -_tx_skip_irq_vfp_save: +_tx_skip_irq_vfp_save: #endif MOV r3, #1 @ Build interrupt stack type @@ -318,7 +312,7 @@ _tx_skip_irq_vfp_save: @ { @ LDR r3, =_tx_timer_interrupt_active @ Pickup timer interrupt active flag's address -_tx_wait_for_timer_to_finish: +_tx_wait_for_timer_to_finish: LDR r2, [r3, #0] @ Pickup timer interrupt active flag CMP r2, #0 @ Is the timer interrupt active? BNE _tx_wait_for_timer_to_finish @ If timer interrupt is active, wait until it completes @@ -337,7 +331,7 @@ _tx_wait_for_timer_to_finish: STR r2, [r3, #0] @ Disable global time-slice flag @ @ } -__tx_thread_dont_save_ts: +__tx_thread_dont_save_ts: @ @ @ /* Clear the current task pointer. */ @@ -348,7 +342,7 @@ __tx_thread_dont_save_ts: @ @ /* Set bit indicating this thread is ready for execution. */ @ - LDR r2, [r0, #152] @ Pickup the ready bit + LDR r2, [r0, #152] @ Pickup the ready bit ORR r2, r2, #0x8000 @ Set ready bit (bit 15) STR r2, [r0, #152] @ Make this thread ready for executing again DMB @ Ensure that accesses to shared resource have completed @@ -359,7 +353,7 @@ __tx_thread_dont_save_ts: B _tx_thread_schedule @ Return to scheduler @ } @ -__tx_thread_idle_system_restore: +__tx_thread_idle_system_restore: @ @ /* Just return back to the scheduler! */ @ diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_context_save.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_context_save.S index df84cacf..3148c0f5 100644 --- a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_context_save.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -40,10 +40,10 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ @/* _tx_thread_context_save SMP/Cortex-A5/GNU */ @/* 6.1 */ @/* AUTHOR */ @@ -51,39 +51,33 @@ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function saves the context of an executing thread in the */ -@/* beginning of interrupt processing. The function also ensures that */ -@/* the system stack is used upon return to the calling ISR. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) @{ .global _tx_thread_context_save .type _tx_thread_context_save,function -_tx_thread_context_save: +_tx_thread_context_save: @ @ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked @ out, we are in IRQ mode, and all registers are intact. */ @@ -92,13 +86,13 @@ _tx_thread_context_save: @ if (_tx_thread_system_state[core]++) @ { @ - STMDB sp!, {r0-r3} @ Save some working registers + STMDB sp!, {r0-r3} @ Save some working registers @ @ /* Save the rest of the scratch registers on the stack and return to the @ calling ISR. */ @ MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other registers @ #ifdef TX_ENABLE_FIQ_SUPPORT @@ -135,9 +129,9 @@ _tx_thread_context_save: POP {r12, lr} @ Recover ISR lr & r12 #endif - B __tx_irq_processing_return @ Continue IRQ processing + B __tx_irq_processing_return @ Continue IRQ processing @ -__tx_thread_not_nested_save: +__tx_thread_not_nested_save: @ } @ @ /* Otherwise, not nested, check to see if a thread was running. */ @@ -150,7 +144,7 @@ __tx_thread_not_nested_save: ADD r1, r1, r12 @ Build index into current thread ptr LDR r0, [r1, #0] @ Pickup current thread pointer CMP r0, #0 @ Is it NULL? - BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in @ scheduling loop - nothing needs saving! @ @ /* Save the current stack pointer in the thread's control block. */ @@ -170,17 +164,17 @@ __tx_thread_not_nested_save: POP {r12, lr} @ Recover ISR lr & r12 #endif - B __tx_irq_processing_return @ Continue IRQ processing + B __tx_irq_processing_return @ Continue IRQ processing @ @ } @ else @ { @ -__tx_thread_idle_system_save: +__tx_thread_idle_system_save: @ @ /* Interrupt occurred in the scheduling loop. */ @ -@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ @ processing. */ @ MOV r10, #0 @ Clear stack limit @@ -195,7 +189,7 @@ __tx_thread_idle_system_save: #endif ADD sp, sp, #32 @ Recover saved registers - B __tx_irq_processing_return @ Continue IRQ processing + B __tx_irq_processing_return @ Continue IRQ processing @ @ } @} diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_interrupt_control.S index 22a89af5..be1a1084 100644 --- a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_interrupt_control.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -38,10 +38,10 @@ INT_MASK = 0x80 @ Interrupt bit mask .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ @/* _tx_thread_interrupt_control SMP/Cortex-A5/GNU */ @/* 6.1 */ @/* AUTHOR */ @@ -49,38 +49,32 @@ INT_MASK = 0x80 @ Interrupt bit mask @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is responsible for changing the interrupt lockout */ -@/* posture of the system. */ -@/* */ -@/* INPUT */ -@/* */ -@/* new_posture New interrupt lockout posture */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_control(UINT new_posture) @{ .global _tx_thread_interrupt_control .type _tx_thread_interrupt_control,function -_tx_thread_interrupt_control: +_tx_thread_interrupt_control: @ @ /* Pickup current interrupt lockout posture. */ @ diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_interrupt_disable.S index 166cb9ed..733f77d1 100644 --- a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_interrupt_disable.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -31,10 +31,10 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ @/* _tx_thread_interrupt_disable SMP/Cortex-A5/GNU */ @/* 6.1 */ @/* AUTHOR */ @@ -42,37 +42,31 @@ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is responsible for disabling interrupts */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is responsible for disabling interrupts */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_disable(void) @{ .global _tx_thread_interrupt_disable .type _tx_thread_interrupt_disable,function -_tx_thread_interrupt_disable: +_tx_thread_interrupt_disable: @ @ /* Pickup current interrupt lockout posture. */ @ @@ -83,7 +77,7 @@ _tx_thread_interrupt_disable: #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if @ Disable IRQ and FIQ #else - CPSID i @ Disable IRQ + CPSID i @ Disable IRQ #endif #ifdef __THUMB_INTERWORK diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_interrupt_restore.S index 022a1c6b..5b45b2ea 100644 --- a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_interrupt_restore.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -31,10 +31,10 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ @/* _tx_thread_interrupt_restore SMP/Cortex-A5/GNU */ @/* 6.1 */ @/* AUTHOR */ @@ -42,38 +42,32 @@ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ +@/* */ @/* This function is responsible for restoring interrupts to the state */ @/* returned by a previous _tx_thread_interrupt_disable call. */ -@/* */ -@/* INPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* INPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_restore(UINT old_posture) @{ .global _tx_thread_interrupt_restore .type _tx_thread_interrupt_restore,function -_tx_thread_interrupt_restore: +_tx_thread_interrupt_restore: @ @ /* Apply the new interrupt posture. */ @ diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_irq_nesting_end.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_irq_nesting_end.S index 5408f048..f98f981e 100644 --- a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_irq_nesting_end.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -34,17 +34,17 @@ DISABLE_INTS = 0xC0 @ Disable IRQ & FIQ interrupts #else DISABLE_INTS = 0x80 @ Disable IRQ interrupts #endif -MODE_MASK = 0x1F @ Mode mask +MODE_MASK = 0x1F @ Mode mask IRQ_MODE_BITS = 0x12 @ IRQ mode bits @ @ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ @/* _tx_thread_irq_nesting_end SMP/Cortex-A5/GNU */ @/* 6.1 */ @/* AUTHOR */ @@ -52,52 +52,46 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from IRQ mode after */ -@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -@/* processing from system mode back to IRQ mode prior to the ISR */ -@/* calling _tx_thread_context_restore. Note that this function */ -@/* assumes the system stack pointer is in the same position after */ -@/* nesting start function was called. */ -@/* */ -@/* This function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with IRQ interrupts disabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +@/* processing from system mode back to IRQ mode prior to the ISR */ +@/* calling _tx_thread_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_end(VOID) @{ .global _tx_thread_irq_nesting_end .type _tx_thread_irq_nesting_end,function -_tx_thread_irq_nesting_end: +_tx_thread_irq_nesting_end: MOV r3,lr @ Save ISR return address MRS r0, CPSR @ Pickup the CPSR ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value MSR CPSR_c, r0 @ Disable interrupts - LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for @ 8-byte alignment logic) BIC r0, r0, #MODE_MASK @ Clear mode bits ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_irq_nesting_start.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_irq_nesting_start.S index a8c386f9..68b2baf7 100644 --- a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_irq_nesting_start.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -37,10 +37,10 @@ SYS_MODE_BITS = 0x1F @ System mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ @/* _tx_thread_irq_nesting_start SMP/Cortex-A5/GNU */ @/* 6.1 */ @/* AUTHOR */ @@ -48,44 +48,38 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from IRQ mode after */ -@/* _tx_thread_context_save has been called and switches the IRQ */ -@/* processing to the system mode so nested IRQ interrupt processing */ -@/* is possible (system mode has its own "lr" register). Note that */ -@/* this function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with IRQ interrupts enabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_context_save has been called and switches the IRQ */ +@/* processing to the system mode so nested IRQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_start(VOID) @{ .global _tx_thread_irq_nesting_start .type _tx_thread_irq_nesting_start,function -_tx_thread_irq_nesting_start: +_tx_thread_irq_nesting_start: MOV r3,lr @ Save ISR return address MRS r0, CPSR @ Pickup the CPSR BIC r0, r0, #MODE_MASK @ Clear the mode bits diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_schedule.S index 26ab7c03..00f254dd 100644 --- a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_schedule.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -41,52 +41,46 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_schedule SMP/Cortex-A5/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_schedule SMP/Cortex-A5/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function waits for a thread control block pointer to appear in */ -@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -@/* in the variable, the corresponding thread is resumed. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_initialize_kernel_enter ThreadX entry function */ -@/* _tx_thread_system_return Return to system from thread */ -@/* _tx_thread_context_restore Restore thread's context */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function waits for a thread control block pointer to appear in */ +@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +@/* in the variable, the corresponding thread is resumed. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* _tx_thread_system_return Return to system from thread */ +@/* _tx_thread_context_restore Restore thread's context */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) @{ .global _tx_thread_schedule .type _tx_thread_schedule,function -_tx_thread_schedule: +_tx_thread_schedule: @ @ /* Enable interrupts. */ @ @@ -124,7 +118,7 @@ _tx_thread_schedule: @ @ } @ while(_tx_thread_execute_ptr[core] == TX_NULL); -@ +@ @ @ /* Get the lock for accessing the thread's ready bit. */ @ @@ -153,7 +147,7 @@ _tx_thread_schedule: DMB @ Ensure write to lock completes B _tx_thread_schedule @ Jump back to the scheduler @ -_tx_thread_ready_for_execution: +_tx_thread_ready_for_execution: @ @ /* We have a thread to execute. */ @ @@ -188,14 +182,14 @@ _tx_thread_ready_for_execution: MOV r1, #0 @ Build clear value STR r1, [r2, #0] @ Clear current thread pointer - LDR r1, [r0, #152] @ Pickup the ready bit + LDR r1, [r0, #152] @ Pickup the ready bit ORR r1, r1, #0x8000 @ Set ready bit (bit 15) STR r1, [r0, #152] @ Make this thread ready for executing again DMB @ Ensure that accesses to shared resource have completed B _tx_thread_schedule @ Jump back to the scheduler to schedule the new thread -_execute_pointer_did_not_change: +_execute_pointer_did_not_change: @ /* Increment the run count for this thread. */ @ _tx_thread_current_ptr[core] -> tx_thread_run_count++; @ @@ -207,7 +201,7 @@ _execute_pointer_did_not_change: @ /* Setup time-slice, if present. */ @ _tx_timer_time_slice[core] = _tx_thread_current_ptr[core] -> tx_thread_time_slice; @ - LDR r2, =_tx_timer_time_slice @ Pickup address of time slice + LDR r2, =_tx_timer_time_slice @ Pickup address of time slice @ variable ADD r2, r2, r12 @ Build index into the time-slice array LDR sp, [r0, #8] @ Switch stack pointers @@ -240,11 +234,11 @@ _execute_pointer_did_not_change: VLDMIA sp!, {D16-D31} @ Recover D16-D31 LDR r4, [sp], #4 @ Pickup FPSCR VMSR FPSCR, r4 @ Restore FPSCR -_tx_skip_interrupt_vfp_restore: +_tx_skip_interrupt_vfp_restore: #endif LDMIA sp!, {r0-r12, lr, pc}^ @ Return to point of thread interrupt - -_tx_solicited_return: + +_tx_solicited_return: #ifdef TARGET_FPU_VFP MSR CPSR_cxsf, r5 @ Recover CPSR LDR r1, [r0, #160] @ Pickup the VFP enabled flag @@ -254,7 +248,7 @@ _tx_solicited_return: VLDMIA sp!, {D16-D31} @ Recover D16-D31 LDR r4, [sp], #4 @ Pickup FPSCR VMSR FPSCR, r4 @ Restore FPSCR -_tx_skip_solicited_vfp_restore: +_tx_skip_solicited_vfp_restore: #endif MSR CPSR_cxsf, r5 @ Recover CPSR LDMIA sp!, {r4-r11, lr} @ Return to thread synchronously @@ -265,7 +259,7 @@ _tx_skip_solicited_vfp_restore: #ifdef TARGET_FPU_VFP .global tx_thread_vfp_enable -tx_thread_vfp_enable: +tx_thread_vfp_enable: MRS r2, CPSR @ Pickup the CPSR #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if @ Disable IRQ and FIQ interrupts @@ -282,12 +276,12 @@ tx_thread_vfp_enable: BEQ __tx_no_thread_to_enable @ If NULL, skip VFP enable MOV r0, #1 @ Build enable value STR r0, [r1, #160] @ Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_enable: +__tx_no_thread_to_enable: MSR CPSR_cxsf, r2 @ Recover CPSR BX LR @ Return to caller .global tx_thread_vfp_disable -tx_thread_vfp_disable: +tx_thread_vfp_disable: MRS r2, CPSR @ Pickup the CPSR #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if @ Disable IRQ and FIQ interrupts @@ -304,7 +298,7 @@ tx_thread_vfp_disable: BEQ __tx_no_thread_to_disable @ If NULL, skip VFP disable MOV r0, #0 @ Build disable value STR r0, [r1, #160] @ Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_disable: +__tx_no_thread_to_disable: MSR CPSR_cxsf, r2 @ Recover CPSR BX LR @ Return to caller #endif diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_core_get.S index 20569ffc..81e9cb99 100644 --- a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_core_get.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread - Low Level SMP Support */ @/** */ @@ -33,10 +33,10 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ @/* _tx_thread_smp_core_get SMP/Cortex-A5/GNU */ @/* 6.1 */ @/* AUTHOR */ @@ -44,35 +44,29 @@ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function gets the currently running core number and returns it.*/ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* Core ID */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX Source */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function gets the currently running core number and returns it.*/ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* Core ID */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get,function -_tx_thread_smp_core_get: +_tx_thread_smp_core_get: MRC p15, 0, r0, c0, c0, 5 @ Read CPU ID register AND r0, r0, #0x03 @ Mask off, leaving the CPU ID field @@ -82,4 +76,4 @@ _tx_thread_smp_core_get: MOV pc, lr @ Return to caller #endif - + diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_core_preempt.S index 9e709411..179a6fdb 100644 --- a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_core_preempt.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread - Low Level SMP Support */ @/** */ @@ -35,60 +35,54 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_smp_core_preempt SMP/Cortex-A5/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_core_preempt SMP/Cortex-A5/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function preempts the specified core in situations where the */ -@/* thread corresponding to this core is no longer ready or when the */ -@/* core must be used for a higher-priority thread. If the specified is */ -@/* the current core, this processing is skipped since the will give up */ -@/* control subsequently on its own. */ -@/* */ -@/* INPUT */ -@/* */ -@/* core The core to preempt */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX Source */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function preempts the specified core in situations where the */ +@/* thread corresponding to this core is no longer ready or when the */ +@/* core must be used for a higher-priority thread. If the specified is */ +@/* the current core, this processing is skipped since the will give up */ +@/* control subsequently on its own. */ +@/* */ +@/* INPUT */ +@/* */ +@/* core The core to preempt */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt,function -_tx_thread_smp_core_preempt: +_tx_thread_smp_core_preempt: STMDB sp!, {r4, lr} @ Save the lr and r4 register on the stack @ @ /* Place call to send inter-processor interrupt here! */ @ - DSB @ - MOV r1, #1 @ Build parameter list - LSL r1, r1, r0 @ - MOV r0, #0 @ - MOV r2, #0 @ + DSB @ + MOV r1, #1 @ Build parameter list + LSL r1, r1, r0 @ + MOV r0, #0 @ + MOV r2, #0 @ BL sendSGI @ Make call to send inter-processor interrupt LDMIA sp!, {r4, lr} @ Recover lr register and r4 @@ -98,4 +92,4 @@ _tx_thread_smp_core_preempt: MOV pc, lr @ Return to caller #endif - + diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_current_state_get.S index 193749c6..8b036485 100644 --- a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_current_state_get.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread - Low Level SMP Support */ @/** */ @@ -35,10 +35,10 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ @/* _tx_thread_smp_current_state_get SMP/Cortex-A5/GNU */ @/* 6.1 */ @/* AUTHOR */ @@ -46,35 +46,29 @@ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is gets the current state of the calling core. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX Components */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is gets the current state of the calling core. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Components */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get,function -_tx_thread_smp_current_state_get: +_tx_thread_smp_current_state_get: MRS r3, CPSR @ Pickup current CPSR @@ -93,7 +87,7 @@ _tx_thread_smp_current_state_get: LDR r1, =_tx_thread_system_state @ Pickup start of the current state array ADD r1, r1, r2 @ Build index into the current state array LDR r0, [r1] @ Pickup state for this core - MSR CPSR_c, r3 @ Restore CPSR + MSR CPSR_c, r3 @ Restore CPSR #ifdef __THUMB_INTERWORK BX lr @ Return to caller #else diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_current_thread_get.S index ddb46643..59962814 100644 --- a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_current_thread_get.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread - Low Level SMP Support */ @/** */ @@ -35,10 +35,10 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ @/* _tx_thread_smp_current_thread_get SMP/Cortex-A5/GNU */ @/* 6.1 */ @/* AUTHOR */ @@ -46,35 +46,29 @@ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is gets the current thread of the calling core. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX Components */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is gets the current thread of the calling core. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Components */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get,function -_tx_thread_smp_current_thread_get: +_tx_thread_smp_current_thread_get: MRS r3, CPSR @ Pickup current CPSR @@ -93,7 +87,7 @@ _tx_thread_smp_current_thread_get: LDR r1, =_tx_thread_current_ptr @ Pickup start of the current thread array ADD r1, r1, r2 @ Build index into the current thread array LDR r0, [r1] @ Pickup current thread for this core - MSR CPSR_c, r3 @ Restore CPSR + MSR CPSR_c, r3 @ Restore CPSR #ifdef __THUMB_INTERWORK BX lr @ Return to caller #else diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_initialize_wait.S index 78ff9b9d..dae249c1 100644 --- a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_initialize_wait.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread - Low Level SMP Support */ @/** */ @@ -38,10 +38,10 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ @/* _tx_thread_smp_initialize_wait SMP/Cortex-A5/GNU */ @/* 6.1 */ @/* AUTHOR */ @@ -49,37 +49,31 @@ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is the place where additional cores wait until */ -@/* initialization is complete before they enter the thread scheduling */ -@/* loop. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling loop */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Hardware */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is the place where additional cores wait until */ +@/* initialization is complete before they enter the thread scheduling */ +@/* loop. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Hardware */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait,function -_tx_thread_smp_initialize_wait: +_tx_thread_smp_initialize_wait: @ /* Lockout interrupts. */ @ @@ -95,13 +89,13 @@ _tx_thread_smp_initialize_wait: AND r10, r10, #0x03 @ Mask off, leaving the CPU ID field LSL r10, r10, #2 @ Build offset to array indexes @ -@ /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release +@ /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release @ flag. */ @ LDR r3, =_tx_thread_system_state @ Build address of system state variable ADD r3, r3, r10 @ Build index into the system state array LDR r2, =0xF0F0F0F0 @ Build TX_INITIALIZE_IN_PROGRESS flag -wait_for_initialize: +wait_for_initialize: LDR r1, [r3] @ Pickup system state CMP r1, r2 @ Has initialization completed? BNE wait_for_initialize @ If different, wait here! @@ -110,13 +104,13 @@ wait_for_initialize: @ LDR r2, =_tx_thread_smp_release_cores_flag @ Build address of release cores flag -wait_for_release: +wait_for_release: LDR r3, [r2] @ Pickup the flag CMP r3, #0 @ Is it set? - BEQ wait_for_release @ Wait for the flag to be set + BEQ wait_for_release @ Wait for the flag to be set @ @ /* Core 0 has released this core. */ -@ +@ @ /* Clear this core's system state variable. */ @ LDR r3, =_tx_thread_system_state @ Build address of system state variable @@ -126,9 +120,9 @@ wait_for_release: @ @ /* Now wait for core 0 to finish it's initialization. */ @ - LDR r3, =_tx_thread_system_state @ Build address of system state variable of logical 0 + LDR r3, =_tx_thread_system_state @ Build address of system state variable of logical 0 -core_0_wait_loop: +core_0_wait_loop: LDR r2, [r3] @ Pickup system state for core 0 CMP r2, #0 @ Is it 0? BNE core_0_wait_loop @ No, keep waiting for core 0 to finish its initialization diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_low_level_initialize.S index 629fb07b..c3392ead 100644 --- a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_low_level_initialize.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread - Low Level SMP Support */ @/** */ @@ -33,10 +33,10 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ @/* _tx_thread_smp_low_level_initialize SMP/Cortex-A5/GNU */ @/* 6.1 */ @/* AUTHOR */ @@ -44,36 +44,30 @@ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function performs low-level initialization of the booting */ -@/* core. */ -@/* */ -@/* INPUT */ -@/* */ -@/* number_of_cores Number of cores */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_initialize_high_level ThreadX high-level init */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function performs low-level initialization of the booting */ +@/* core. */ +@/* */ +@/* INPUT */ +@/* */ +@/* number_of_cores Number of cores */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_high_level ThreadX high-level init */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize,function -_tx_thread_smp_low_level_initialize: +_tx_thread_smp_low_level_initialize: #ifdef __THUMB_INTERWORK BX lr @ Return to caller diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_protect.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_protect.S index cb4f7837..db0a2525 100644 --- a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_protect.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread - Low Level SMP Support */ @/** */ @@ -46,48 +46,42 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_smp_protect SMP/Cortex-A5/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_protect SMP/Cortex-A5/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function gets protection for running inside the ThreadX */ -@/* source. This is acomplished by a combination of a test-and-set */ -@/* flag and periodically disabling interrupts. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* Previous Status Register */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX Source */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function gets protection for running inside the ThreadX */ +@/* source. This is acomplished by a combination of a test-and-set */ +@/* flag and periodically disabling interrupts. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* Previous Status Register */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect,function -_tx_thread_smp_protect: +_tx_thread_smp_protect: PUSH {r4-r6} @ Save registers we'll be using @ @@ -124,7 +118,7 @@ _tx_thread_smp_protect: B _return -_protection_not_owned: +_protection_not_owned: @ @ /* Is the lock available? */ @ if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) @@ -162,7 +156,7 @@ _protection_not_owned: B _return -_list_not_empty: +_list_not_empty: @ @ /* Are we at the front of the list? */ @ if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head]) @@ -203,7 +197,7 @@ _list_not_empty: B _return -_start_waiting: +_start_waiting: @ @ /* For one reason or another, we didn't get the lock. */ @ @@ -229,7 +223,7 @@ _start_waiting: @ @ } @ -_already_in_list0: +_already_in_list0: @ @ /* Restore interrupts. */ @ @@ -242,7 +236,7 @@ _already_in_list0: @ while (1) @ { @ -_try_to_get_lock: +_try_to_get_lock: @ @ /* Disable interrupts so we don't get preempted. */ @ @@ -305,7 +299,7 @@ _try_to_get_lock: B _got_lock_after_waiting -_did_not_get_lock: +_did_not_get_lock: @ @ /* For one reason or another, we didn't get the lock. */ @ @@ -334,7 +328,7 @@ _did_not_get_lock: @ @ } @ -_already_in_list1: +_already_in_list1: @ @ /* Restore interrupts and try again. */ @ @@ -344,7 +338,7 @@ _already_in_list1: #endif B _try_to_get_lock @ On waking, restart the protection attempt -_got_lock_after_waiting: +_got_lock_after_waiting: @ @ /* We're no longer waiting. */ @ _tx_thread_smp_protect_wait_counts[this_core]--; @@ -357,7 +351,7 @@ _got_lock_after_waiting: @ @ /* Restore link register and return. */ @ -_return: +_return: POP {r4-r6} @ Restore registers diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h index 7ac4ad4e..f1ad80e8 100644 --- a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,10 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @@ -73,7 +73,7 @@ @ @ } @ -_store_new_head\@: +_store_new_head\@: STR r5, [r4] @ Store the new head @ @@ -90,7 +90,7 @@ _store_new_head\@: @ while (1) @ { @ -_tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@: +_tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@: @ @ /* Is the list lock available? */ @ _tx_thread_smp_protect_wait_list_lock_protect_in_force = load_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force); @@ -158,7 +158,7 @@ _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@: @ @ } @ -_tx_thread_smp_protect_wait_list_add__no_wrap\@: +_tx_thread_smp_protect_wait_list_add__no_wrap\@: STR r4, [r3] @ Store the new tail value. @ @@ -185,7 +185,7 @@ _tx_thread_smp_protect_wait_list_add__no_wrap\@: @ @ { @ -_tx_thread_smp_protect_wait_list_remove__check_cur_core\@: +_tx_thread_smp_protect_wait_list_remove__check_cur_core\@: @ @ /* Is this the core? */ @ if (_tx_thread_smp_protect_wait_list[core_index] == core) @@ -194,7 +194,7 @@ _tx_thread_smp_protect_wait_list_remove__check_cur_core\@: @ LDR r3, [r2, r1, LSL #2] @ Get the value at the current index CMP r3, r0 @ Did we find the core? - BEQ _tx_thread_smp_protect_wait_list_remove__found_core\@ + BEQ _tx_thread_smp_protect_wait_list_remove__found_core\@ @ @ } @ @@ -203,7 +203,7 @@ _tx_thread_smp_protect_wait_list_remove__check_cur_core\@: @ @ } @ -_tx_thread_smp_protect_wait_list_remove__found_core\@: +_tx_thread_smp_protect_wait_list_remove__found_core\@: @ @ /* We're about to modify the list. Get the lock. We need the lock because another @ core could be simultaneously adding (a core is simultaneously trying to get @@ -221,12 +221,12 @@ _tx_thread_smp_protect_wait_list_remove__found_core\@: @ while (core_index != _tx_thread_smp_protect_wait_list_tail) @ { @ -_tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@: +_tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@: LDR r2, =_tx_thread_smp_protect_wait_list_tail @ Load tail address LDR r2, [r2] @ Load tail value CMP r1, r2 @ Compare cur index and tail - BEQ _tx_thread_smp_protect_wait_list_remove__removed\@ + BEQ _tx_thread_smp_protect_wait_list_remove__removed\@ @ @ UINT next_index = core_index + 1; @ @@ -239,7 +239,7 @@ _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@: LDR r3, =_tx_thread_smp_protect_wait_list_size LDR r3, [r3] CMP r2, r3 - BNE _tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@ + BNE _tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@ @ @ next_index = 0; @ @@ -247,7 +247,7 @@ _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@: @ @ } @ -_tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@: +_tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@: @ @ list_cores[core_index] = list_cores[next_index]; @ @@ -259,11 +259,11 @@ _tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@: @ MOV r1, r2 - B _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@ + B _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@ @ @ } @ -_tx_thread_smp_protect_wait_list_remove__removed\@: +_tx_thread_smp_protect_wait_list_remove__removed\@: @ @ /* Now update the tail. */ @ if (_tx_thread_smp_protect_wait_list_tail == 0) @@ -272,7 +272,7 @@ _tx_thread_smp_protect_wait_list_remove__removed\@: LDR r0, =_tx_thread_smp_protect_wait_list_tail @ Load tail address LDR r1, [r0] @ Load tail value CMP r1, #0 - BNE _tx_thread_smp_protect_wait_list_remove__tail_not_zero\@ + BNE _tx_thread_smp_protect_wait_list_remove__tail_not_zero\@ @ @ _tx_thread_smp_protect_wait_list_tail = _tx_thread_smp_protect_wait_list_size; @ @@ -281,7 +281,7 @@ _tx_thread_smp_protect_wait_list_remove__removed\@: @ @ } @ -_tx_thread_smp_protect_wait_list_remove__tail_not_zero\@: +_tx_thread_smp_protect_wait_list_remove__tail_not_zero\@: @ @ _tx_thread_smp_protect_wait_list_tail--; @ diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_time_get.S index 7daa2932..7e399690 100644 --- a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_time_get.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread - Low Level SMP Support */ @/** */ @@ -34,10 +34,10 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ @/* _tx_thread_smp_time_get SMP/Cortex-A5/GNU */ @/* 6.1 */ @/* AUTHOR */ @@ -45,36 +45,30 @@ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function gets the global time value that is used for debug */ -@/* information and event tracing. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* 32-bit time stamp */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX Source */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function gets the global time value that is used for debug */ +@/* information and event tracing. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* 32-bit time stamp */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get,function -_tx_thread_smp_time_get: +_tx_thread_smp_time_get: MRC p15, 4, r0, c15, c0, 0 @ Read periph base address LDR r0, [r0, #0x604] @ Read count register @@ -85,4 +79,4 @@ _tx_thread_smp_time_get: MOV pc, lr @ Return to caller #endif - + diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_unprotect.S index f10efb7e..4cccae92 100644 --- a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_unprotect.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread - Low Level SMP Support */ @/** */ @@ -38,49 +38,43 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_smp_unprotect SMP/Cortex-A5/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_unprotect SMP/Cortex-A5/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function releases previously obtained protection. The supplied */ -@/* previous SR is restored. If the value of _tx_thread_system_state */ -@/* and _tx_thread_preempt_disable are both zero, then multithreading */ -@/* is enabled as well. */ -@/* */ -@/* INPUT */ -@/* */ -@/* Previous Status Register */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX Source */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function releases previously obtained protection. The supplied */ +@/* previous SR is restored. If the value of _tx_thread_system_state */ +@/* and _tx_thread_preempt_disable are both zero, then multithreading */ +@/* is enabled as well. */ +@/* */ +@/* INPUT */ +@/* */ +@/* Previous Status Register */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect,function -_tx_thread_smp_unprotect: +_tx_thread_smp_unprotect: @ @ /* Lockout interrupts. */ @ @@ -130,7 +124,7 @@ _tx_thread_smp_unprotect: SEV @ Send event to other CPUs, wakes anyone waiting on the protection (using WFE) #endif -_still_protected: +_still_protected: MSR CPSR_c, r0 @ Restore CPSR #ifdef __THUMB_INTERWORK diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_stack_build.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_stack_build.S index 88978868..24ec180a 100644 --- a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_stack_build.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -43,10 +43,10 @@ THUMB_BIT = 0x20 @ Thumb-bit .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ @/* _tx_thread_stack_build SMP/Cortex-A5/GNU */ @/* 6.1 */ @/* AUTHOR */ @@ -54,45 +54,39 @@ THUMB_BIT = 0x20 @ Thumb-bit @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ +@/* */ @/* This function builds a stack frame on the supplied thread's stack. */ @/* The stack frame results in a fake interrupt return to the supplied */ -@/* function pointer. */ -@/* */ -@/* INPUT */ -@/* */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ @/* thread_ptr Pointer to thread control blk */ @/* function_ptr Pointer to return function */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_thread_create Create thread service */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @{ .global _tx_thread_stack_build .type _tx_thread_stack_build,function -_tx_thread_stack_build: +_tx_thread_stack_build: +@ @ -@ @ /* Build a fake interrupt frame. The form of the fake interrupt stack @ on the Cortex-A5 should look like the following after it is built: -@ +@ @ Stack Top: 1 Interrupt stack frame type @ CPSR Initial value for CPSR @ a1 (r0) Initial value for a1 diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_system_return.S index f6dad9f4..f49d8324 100644 --- a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_system_return.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -35,17 +35,17 @@ .global _tx_thread_preempt_disable .global _tx_thread_smp_protection #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - .global _tx_execution_thread_exit + .global _tx_execution_thread_exit #endif @ @ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ @/* _tx_thread_system_return SMP/Cortex-A5/GNU */ @/* 6.1 */ @/* AUTHOR */ @@ -53,40 +53,34 @@ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is target processor specific. It is used to transfer */ -@/* control from a thread back to the ThreadX system. Only a */ -@/* minimal context is saved since the compiler assumes temp registers */ -@/* are going to get slicked by a function call anyway. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling loop */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX components */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ @/* */ @/**************************************************************************/ @VOID _tx_thread_system_return(VOID) @{ .global _tx_thread_system_return .type _tx_thread_system_return,function -_tx_thread_system_return: +_tx_thread_system_return: @ @ /* Save minimal context on the stack. */ @ @@ -109,12 +103,12 @@ _tx_thread_system_return: STR r4, [sp, #-4]! @ Save FPSCR VSTMDB sp!, {D16-D31} @ Save D16-D31 VSTMDB sp!, {D8-D15} @ Save D8-D15 -_tx_skip_solicited_vfp_save: +_tx_skip_solicited_vfp_save: #endif MOV r4, #0 @ Build a solicited stack type MRS r5, CPSR @ Pickup the CPSR STMDB sp!, {r4-r5} @ Save type and CPSR -@ +@ @ /* Lockout interrupts. */ @ #ifdef TX_ENABLE_FIQ_SUPPORT @@ -162,7 +156,7 @@ _tx_skip_solicited_vfp_save: STR r1, [r0, #24] @ Save current time-slice @ @ } -__tx_thread_dont_save_ts: +__tx_thread_dont_save_ts: @ @ /* Clear the current thread pointer. */ @ _tx_thread_current_ptr[core] = TX_NULL; @@ -184,10 +178,10 @@ __tx_thread_dont_save_ts: STR lr, [r3, #24] @ Save last caller LDR r2, [r3, #4] @ Pickup owning thread CMP r0, r2 @ Is it the same as the current thread? -__error_loop: +__error_loop: BNE __error_loop @ If not, we have a problem!! -#endif - +#endif + LDR r1, =_tx_thread_preempt_disable @ Build address to preempt disable flag MOV r2, #0 @ Build clear value STR r2, [r1, #0] @ Clear preempt disable flag diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_vectored_context_save.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_vectored_context_save.S index 06fb49c1..aed336ad 100644 --- a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_vectored_context_save.S +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_vectored_context_save.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -39,10 +39,10 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ @/* _tx_thread_vectored_context_save SMP/Cortex-A5/GNU */ @/* 6.1 */ @/* AUTHOR */ @@ -50,39 +50,33 @@ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function saves the context of an executing thread in the */ -@/* beginning of interrupt processing. The function also ensures that */ -@/* the system stack is used upon return to the calling ISR. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_vectored_context_save(VOID) @{ .global _tx_thread_vectored_context_save .type _tx_thread_vectored_context_save,function -_tx_thread_vectored_context_save: +_tx_thread_vectored_context_save: @ @ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked @ out, we are in IRQ mode, and all registers are intact. */ @@ -133,7 +127,7 @@ _tx_thread_vectored_context_save: MOV pc, lr @ Return to caller #endif @ -__tx_thread_not_nested_save: +__tx_thread_not_nested_save: @ } @ @ /* Otherwise, not nested, check to see if a thread was running. */ @@ -146,7 +140,7 @@ __tx_thread_not_nested_save: ADD r1, r1, r12 @ Build index into current thread ptr LDR r0, [r1, #0] @ Pickup current thread pointer CMP r0, #0 @ Is it NULL? - BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in @ scheduling loop - nothing needs saving! @ @ /* Note: Minimal context of interrupted thread is already saved. */ @@ -178,11 +172,11 @@ __tx_thread_not_nested_save: @ else @ { @ -__tx_thread_idle_system_save: +__tx_thread_idle_system_save: @ @ /* Interrupt occurred in the scheduling loop. */ @ -@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ @ processing. */ @ MOV r10, #0 @ Clear stack limit diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_timer_interrupt.S b/ports_smp/cortex_a5_smp/gnu/src/tx_timer_interrupt.S index c72b9619..a0107e28 100644 --- a/ports_smp/cortex_a5_smp/gnu/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_timer_interrupt.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Timer */ @/** */ @@ -50,10 +50,10 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ @/* _tx_timer_interrupt SMP/Cortex-A5/GNU */ @/* 6.1 */ @/* AUTHOR */ @@ -61,44 +61,38 @@ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function processes the hardware timer interrupt. This */ -@/* processing includes incrementing the system clock and checking for */ -@/* time slice and/or timer expiration. If either is found, the */ -@/* interrupt context save/restore functions are called along with the */ -@/* expiration functions. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_time_slice Time slice interrupted thread */ -@/* _tx_thread_smp_protect Get SMP protection */ -@/* _tx_thread_smp_unprotect Releast SMP protection */ -@/* _tx_timer_expiration_process Timer expiration processing */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* interrupt vector */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* _tx_thread_smp_protect Get SMP protection */ +@/* _tx_thread_smp_unprotect Releast SMP protection */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) @{ .global _tx_timer_interrupt .type _tx_timer_interrupt,function -_tx_timer_interrupt: +_tx_timer_interrupt: @ @ /* Upon entry to this routine, it is assumed that context save has already @ been called, and therefore the compiler scratch registers are available @@ -109,7 +103,7 @@ _tx_timer_interrupt: CMP r0, #0 @ Only process timer interrupts from core 0 (to change this simply change the constant!) BEQ __tx_process_timer @ If the same process the interrupt BX lr @ Return to caller if not matched -__tx_process_timer: +__tx_process_timer: STMDB sp!, {r4, lr} @ Save the lr and r4 register on the stack BL _tx_thread_smp_protect @ Get protection @@ -154,7 +148,7 @@ __tx_process_timer: @ } @ else @ { -__tx_timer_no_timer: +__tx_timer_no_timer: @ @ /* No timer expired, increment the timer pointer. */ @ _tx_timer_current_ptr++; @@ -175,12 +169,12 @@ __tx_timer_no_timer: LDR r3, =_tx_timer_list_start @ Pickup addr of timer list start LDR r0, [r3, #0] @ Set current pointer to list start @ -__tx_timer_skip_wrap: +__tx_timer_skip_wrap: @ STR r0, [r1, #0] @ Store new current timer pointer @ } @ -__tx_timer_done: +__tx_timer_done: @ @ @ /* Did a timer expire? */ @@ -198,10 +192,10 @@ __tx_timer_done: BL _tx_timer_expiration_process @ Call the timer expiration handling routine @ @ } -__tx_timer_dont_activate: +__tx_timer_dont_activate: @ @ /* Call time-slice processing. */ -@ _tx_thread_time_slice(); +@ _tx_thread_time_slice(); BL _tx_thread_time_slice @ Call time-slice processing @ diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/.cproject b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/.cproject index 99121e5d..53e52d1d 100644 --- a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/.cproject @@ -1,142 +1,142 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/sample_threadx.sct b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/sample_threadx.sct index 1288a328..1ed382ae 100644 --- a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/sample_threadx.sct +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/sample_threadx.sct @@ -12,13 +12,13 @@ LOAD 0x80000000 { startup.o (StartUp, +FIRST) * (+RO, +RW, +ZI) - + } ;XTABLES +0 ALIGN 0x1000 ;{ - ; xtables.o (*) + ; xtables.o (*) ;} - + SYS_STACK +0 ALIGN 8 EMPTY 0x1000 { } @@ -34,13 +34,13 @@ LOAD 0x80000000 ; All stacks and heap are aligned to a cache-line boundary ; ARM_LIB_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary ; HANDLER_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Stacks for EL3 ; @@ -217,34 +217,34 @@ LOAD 0x80000000 ; { ; *( +RO ) ; } -; +; ; XTABLES +0 ALIGN 0x1000 ; { -; xtables.o (*) +; xtables.o (*) ; } ;} ; ;RW AlignExpr(ImageLimit(XTABLES), 0x1000) -;{ +;{ ; RWSEC +0 ; { ; *( +RW ) ; } -; +; ; ZISEC +0 ; { ; *( +ZI ) ; } -; +; ; SYS_STACK +0 ALIGN 8 EMPTY 0x1000 ; { ; } -; +; ; ; 512 MiB heap ; HEAP +0 ALIGN 8 EMPTY 0x10000000 ; { ; } -; +; ; ; Free Memory section ; FREE_MEMORY +0 ALIGN 8 EMPTY 0x10000000 ; { @@ -254,7 +254,7 @@ LOAD 0x80000000 ; TASK_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { ; } -; +; ; ; Per-CPU 128 MiB handler stacks ; HANDLER_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/tx/.cproject b/ports_smp/cortex_a5x_smp/ac6/example_build/tx/.cproject index 294b7469..3f5d6096 100644 --- a/ports_smp/cortex_a5x_smp/ac6/example_build/tx/.cproject +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/tx/.cproject @@ -1,154 +1,154 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a5x_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a5x_smp/ac6/inc/tx_port.h index 5a0400e0..69cba68f 100644 --- a/ports_smp/cortex_a5x_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a5x_smp/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,18 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* symbol ULONG64_DEFINED, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -423,7 +412,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 1996-2019 Express Logic Inc. * ThreadX Cortex-A5x-SMP/AC6 Version 6.4.2 *"; + "Copyright (c) 1996-2019 Express Logic Inc. * ThreadX Cortex-A5x-SMP/AC6 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a5x_smp/ac6/readme_threadx.txt b/ports_smp/cortex_a5x_smp/ac6/readme_threadx.txt index baec207f..62f17da4 100644 --- a/ports_smp/cortex_a5x_smp/ac6/readme_threadx.txt +++ b/ports_smp/cortex_a5x_smp/ac6/readme_threadx.txt @@ -1,11 +1,11 @@ - Microsoft's Azure RTOS ThreadX SMP for Cortex-A5x + Microsoft's Azure RTOS ThreadX SMP for Cortex-A5x Using the ARM Compiler 6 & DS 1. Import the ThreadX Projects -In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import -the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) into your DS workspace. Note: the projects were made using DS-5, so DS will prompt you to migrate the projects. @@ -14,9 +14,9 @@ This is expected, so please do so. 2. Building the ThreadX SMP run-time Library -Building the ThreadX SMP library is easy; simply select the Eclipse project file -"tx" and then select the build button. You should now observe the compilation -and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP +Building the ThreadX SMP library is easy; simply select the Eclipse project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP library file tx.a. @@ -36,29 +36,29 @@ ThreadX SMP demonstration. 4. System Initialization -The entry point in ThreadX SMP for the Cortex-A5x using AC6 tools is at label -"entry". This is defined within the AC6 compiler's startup code. In addition, -this is where all static and global pre-set C variable initialization processing +The entry point in ThreadX SMP for the Cortex-A5x using AC6 tools is at label +"entry". This is defined within the AC6 compiler's startup code. In addition, +this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX SMP tx_initialize_low_level.s file is responsible for determining the -first available RAM address for use by the application, which is supplied as the +The ThreadX SMP tx_initialize_low_level.s file is responsible for determining the +first available RAM address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 5. Register Usage and Stack Frames -The 64-bit AC6 compiler assumes that registers x0-x18 are scratch registers -for each function. All other registers used by a C function must be preserved -by the function. ThreadX SMP takes advantage of this in situations where a context -switch happens as a result of making a ThreadX SMP service call (which is itself a -C function). In such cases, the saved context of a thread is only the +The 64-bit AC6 compiler assumes that registers x0-x18 are scratch registers +for each function. All other registers used by a C function must be preserved +by the function. ThreadX SMP takes advantage of this in situations where a context +switch happens as a result of making a ThreadX SMP service call (which is itself a +C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -77,10 +77,10 @@ FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: 0x040 x22 x21 0x048 x23 x22 0x050 x20 x19 - 0x058 x21 x20 - 0x060 x18 x29 - 0x068 x19 x30 - 0x070 x16 + 0x058 x21 x20 + 0x060 x18 x29 + 0x068 x19 x30 + 0x070 x16 0x078 x17 0x080 x14 0x088 x15 @@ -99,7 +99,7 @@ FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: 0x0F0 x0 0x0F8 x1 0x100 x29 - 0x108 x30 + 0x108 x30 FP enabled and TX_THREAD.tx_thread_fp_enable == 1: @@ -148,19 +148,19 @@ FP enabled and TX_THREAD.tx_thread_fp_enable == 1: 0x1F0 q3 0x200 q0 0x210 q1 - 0x220 x28 - 0x228 reserved - 0x230 x26 - 0x238 x27 - 0x240 x24 - 0x248 x25 - 0x250 x22 - 0x258 x23 - 0x260 x20 - 0x268 x21 - 0x270 x18 - 0x278 x19 - 0x280 x16 + 0x220 x28 + 0x228 reserved + 0x230 x26 + 0x238 x27 + 0x240 x24 + 0x248 x25 + 0x250 x22 + 0x258 x23 + 0x260 x20 + 0x268 x21 + 0x270 x18 + 0x278 x19 + 0x280 x16 0x288 x17 0x290 x14 0x298 x15 @@ -179,20 +179,20 @@ FP enabled and TX_THREAD.tx_thread_fp_enable == 1: 0x300 x0 0x308 x1 0x310 x29 - 0x318 x30 + 0x318 x30 6. Improving Performance -The distribution version of ThreadX SMP is built without any compiler optimizations. -This makes it easy to debug because you can trace or set breakpoints inside of -ThreadX SMP itself. Of course, this costs some performance. To make it run faster, +The distribution version of ThreadX SMP is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX SMP itself. Of course, this costs some performance. To make it run faster, you can change the project settings to the desired compiler optimization level. -In addition, you can eliminate the ThreadX SMP basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX SMP basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling @@ -212,22 +212,22 @@ irq_handler: B _tx_thread_context_restore -By default, ThreadX SMP assumes EL3 level of execution. Running and taking exceptions in EL1 +By default, ThreadX SMP assumes EL3 level of execution. Running and taking exceptions in EL1 and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined. 8. ThreadX SMP Timer Interrupt -ThreadX SMP requires a periodic interrupt source to manage all time-slicing, thread sleeps, -timeouts, and application timers. Without such a timer interrupt source, these services -are not functional. However, all other ThreadX services are operational without a +ThreadX SMP requires a periodic interrupt source to manage all time-slicing, thread sleeps, +timeouts, and application timers. Without such a timer interrupt source, these services +are not functional. However, all other ThreadX services are operational without a periodic timer source. 9. ARM FP Support By default, FP support is disabled for each thread. If saving the context of the FP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the FP usage: void tx_thread_fp_enable(void); diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_initialize_low_level.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_initialize_low_level.S index 1ac4b92d..dae11acf 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_context_restore.S index 24f2d2ab..f340410f 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,18 +56,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_context_save.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_context_save.S index 12ff35fe..ac820e3c 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_fp_disable.c b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_fp_disable.c index d811f808..d22db802 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_fp_enable.c b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_fp_enable.c index 44af479a..71d04c68 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_control.S index fdf15bb4..e36cf9cc 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_disable.S index f3c76fa5..7210527f 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,14 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_restore.S index cab44db1..6b72a1bb 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_schedule.S index 69b3f59e..56447fac 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_core_get.S index 3cea6a35..2f84315c 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,15 +53,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_core_preempt.S index 63c7a39d..ed1f6f30 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_current_state_get.S index a9bc1446..749bfec0 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,15 +53,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_current_thread_get.S index 2d733269..4d1a9d14 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,15 +53,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_initialize_wait.S index 6ce34d88..81524616 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_low_level_initialize.S index b1891058..b7bc21aa 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_protect.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_protect.S index a79288f3..c99bfb29 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -119,9 +107,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_time_get.S index d99f8aad..efa6d62c 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_unprotect.S index cecab732..1a7898f7 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,18 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_stack_build.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_stack_build.S index e95ddc32..00bc9ef3 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,14 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_system_return.S index bac6905e..299c4aa2 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_timer_interrupt.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_timer_interrupt.S index da9b53bb..a2da7bfc 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/sample_threadx/.cproject b/ports_smp/cortex_a5x_smp/gnu/example_build/sample_threadx/.cproject index af4bd31b..b4bdff46 100644 --- a/ports_smp/cortex_a5x_smp/gnu/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/sample_threadx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/sample_threadx/sample_threadx.ld b/ports_smp/cortex_a5x_smp/gnu/example_build/sample_threadx/sample_threadx.ld index e9b12a82..1c6d45b5 100644 --- a/ports_smp/cortex_a5x_smp/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start @@ -194,7 +194,7 @@ SECTIONS . = . + 4 * 0x8000; __stack = .; } - + .handler_stack_limit (NOLOAD): { . = ALIGN(64); diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/tx/.cproject b/ports_smp/cortex_a5x_smp/gnu/example_build/tx/.cproject index e78b2e67..c792eb9b 100644 --- a/ports_smp/cortex_a5x_smp/gnu/example_build/tx/.cproject +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/tx/.cproject @@ -1,188 +1,188 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a5x_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a5x_smp/gnu/inc/tx_port.h index 32bfb82c..6048a955 100644 --- a/ports_smp/cortex_a5x_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a5x_smp/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* symbol ULONG64_DEFINED, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -420,7 +412,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-A5x-SMP/GNU Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A5x-SMP/GNU Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a5x_smp/gnu/readme_threadx.txt b/ports_smp/cortex_a5x_smp/gnu/readme_threadx.txt index 8bc94fca..d8b4ba99 100644 --- a/ports_smp/cortex_a5x_smp/gnu/readme_threadx.txt +++ b/ports_smp/cortex_a5x_smp/gnu/readme_threadx.txt @@ -4,16 +4,16 @@ 1. Import the ThreadX Projects -In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import -the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) into your DS workspace. 2. Building the ThreadX SMP run-time Library -Building the ThreadX SMP library is easy; simply select the Eclipse project file -"tx" and then select the build button. You should now observe the compilation -and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP +Building the ThreadX SMP library is easy; simply select the Eclipse project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP library file tx.a. @@ -33,29 +33,29 @@ ThreadX SMP demonstration. 4. System Initialization -The entry point in ThreadX SMP for the Cortex-A5x using GCC tools is at label -"start64". This is defined within the GCC compiler's startup code. In addition, -this is where all static and global pre-set C variable initialization processing +The entry point in ThreadX SMP for the Cortex-A5x using GCC tools is at label +"start64". This is defined within the GCC compiler's startup code. In addition, +this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX SMP tx_initialize_low_level.s file is responsible for determining the -first available RAM address for use by the application, which is supplied as the +The ThreadX SMP tx_initialize_low_level.s file is responsible for determining the +first available RAM address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 5. Register Usage and Stack Frames -The 64-bit GCC compiler assumes that registers x0-x18 are scratch registers -for each function. All other registers used by a C function must be preserved -by the function. ThreadX SMP takes advantage of this in situations where a context -switch happens as a result of making a ThreadX SMP service call (which is itself a -C function). In such cases, the saved context of a thread is only the +The 64-bit GCC compiler assumes that registers x0-x18 are scratch registers +for each function. All other registers used by a C function must be preserved +by the function. ThreadX SMP takes advantage of this in situations where a context +switch happens as a result of making a ThreadX SMP service call (which is itself a +C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -74,10 +74,10 @@ FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: 0x040 x22 x21 0x048 x23 x22 0x050 x20 x19 - 0x058 x21 x20 - 0x060 x18 x29 - 0x068 x19 x30 - 0x070 x16 + 0x058 x21 x20 + 0x060 x18 x29 + 0x068 x19 x30 + 0x070 x16 0x078 x17 0x080 x14 0x088 x15 @@ -96,7 +96,7 @@ FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: 0x0F0 x0 0x0F8 x1 0x100 x29 - 0x108 x30 + 0x108 x30 FP enabled and TX_THREAD.tx_thread_fp_enable == 1: @@ -145,19 +145,19 @@ FP enabled and TX_THREAD.tx_thread_fp_enable == 1: 0x1F0 q3 0x200 q0 0x210 q1 - 0x220 x28 - 0x228 reserved - 0x230 x26 - 0x238 x27 - 0x240 x24 - 0x248 x25 - 0x250 x22 - 0x258 x23 - 0x260 x20 - 0x268 x21 - 0x270 x18 - 0x278 x19 - 0x280 x16 + 0x220 x28 + 0x228 reserved + 0x230 x26 + 0x238 x27 + 0x240 x24 + 0x248 x25 + 0x250 x22 + 0x258 x23 + 0x260 x20 + 0x268 x21 + 0x270 x18 + 0x278 x19 + 0x280 x16 0x288 x17 0x290 x14 0x298 x15 @@ -176,20 +176,20 @@ FP enabled and TX_THREAD.tx_thread_fp_enable == 1: 0x300 x0 0x308 x1 0x310 x29 - 0x318 x30 + 0x318 x30 6. Improving Performance -The distribution version of ThreadX SMP is built without any compiler optimizations. -This makes it easy to debug because you can trace or set breakpoints inside of -ThreadX SMP itself. Of course, this costs some performance. To make it run faster, +The distribution version of ThreadX SMP is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX SMP itself. Of course, this costs some performance. To make it run faster, you can change the project settings to the desired compiler optimization level. -In addition, you can eliminate the ThreadX SMP basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX SMP basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling @@ -209,22 +209,22 @@ irq_handler: B _tx_thread_context_restore -By default, ThreadX SMP assumes EL3 level of execution. Running and taking exceptions in EL1 +By default, ThreadX SMP assumes EL3 level of execution. Running and taking exceptions in EL1 and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined. 8. ThreadX SMP Timer Interrupt -ThreadX SMP requires a periodic interrupt source to manage all time-slicing, thread sleeps, -timeouts, and application timers. Without such a timer interrupt source, these services -are not functional. However, all other ThreadX services are operational without a +ThreadX SMP requires a periodic interrupt source to manage all time-slicing, thread sleeps, +timeouts, and application timers. Without such a timer interrupt source, these services +are not functional. However, all other ThreadX services are operational without a periodic timer source. 9. ARM FP Support By default, FP support is disabled for each thread. If saving the context of the FP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the FP usage: void tx_thread_fp_enable(void); diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_initialize_low_level.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_initialize_low_level.S index 92ec2d42..79520af4 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_context_restore.S index f156947a..728c24a4 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,18 +56,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_context_save.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_context_save.S index d990e01d..4b7128a5 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_fp_disable.c b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_fp_disable.c index 74299214..82bcf936 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_fp_enable.c b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_fp_enable.c index 496857a0..63a1d767 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_control.S index 324c82b0..65d991cc 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_disable.S index 6b534269..665d93bd 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,14 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_restore.S index 76306d76..3078d40e 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_schedule.S index 23def2c6..e2832208 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_core_get.S index 5ea6665d..64947c40 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,14 +53,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_core_preempt.S index 2d41d36b..3529917c 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,15 +59,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_current_state_get.S index 17feb11c..f125201e 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,14 +53,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_current_thread_get.S index 06e5aede..57c280bc 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,14 +53,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_initialize_wait.S index 0aacf628..e40c6beb 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,14 +55,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_low_level_initialize.S index 3c3a93a2..c388bba9 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_protect.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_protect.S index d20c3a42..b0225109 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -119,9 +107,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_time_get.S index 4b0936d5..4a98140a 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_unprotect.S index eb45a300..4d7dbf4d 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.9 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_stack_build.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_stack_build.S index a841e0cf..e3793907 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,14 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_system_return.S index 9926fc9f..0a732638 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_timer_interrupt.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_timer_interrupt.S index 6507e0bc..3764cd82 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 Yuxin Zhou Modified comment(s), */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/tx_boot.a64 b/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/tx_boot.a64 index ab759e18..102d8ef2 100644 --- a/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/tx_boot.a64 +++ b/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/tx_boot.a64 @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/tx_zynqmp.h b/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/tx_zynqmp.h index 417f58b1..048622d9 100644 --- a/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/tx_zynqmp.h +++ b/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/tx_zynqmp.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/tx_zynqmp_low_level.c b/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/tx_zynqmp_low_level.c index ca92850a..9fe3dc4a 100644 --- a/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/tx_zynqmp_low_level.c +++ b/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/tx_zynqmp_low_level.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -325,12 +326,6 @@ static void tx_caches_enable(void) /* */ /* _tx_initialize_low_level ThreadX low level initialization */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ void _tx_platform_initialize_low_level(void) { diff --git a/ports_smp/cortex_a5x_smp/green/example_build/tgt/release.gpc b/ports_smp/cortex_a5x_smp/green/example_build/tgt/release.gpc index 8af6070d..e05ff292 100644 --- a/ports_smp/cortex_a5x_smp/green/example_build/tgt/release.gpc +++ b/ports_smp/cortex_a5x_smp/green/example_build/tgt/release.gpc @@ -6,4 +6,4 @@ macro __BINDIR=%expand_path(bin/release) -object_dir=objs/release :outputDir=objs/release :binDir=${__BINDIR} - + diff --git a/ports_smp/cortex_a5x_smp/green/example_build/tgt/resource_readme.txt b/ports_smp/cortex_a5x_smp/green/example_build/tgt/resource_readme.txt index f385e446..aea01291 100644 --- a/ports_smp/cortex_a5x_smp/green/example_build/tgt/resource_readme.txt +++ b/ports_smp/cortex_a5x_smp/green/example_build/tgt/resource_readme.txt @@ -32,7 +32,7 @@ Linker directive files (.ld) are used when your program is linked to define program sections and assign them to specific addresses in memory. The linker directive file from the project file for your executable will -be used when linking. +be used when linking. If the .ld file included in the project for your executable does not suit your hardware configuration or program layout needs, it can be modified or @@ -41,21 +41,21 @@ replaced with a custom .ld file. This resource.gpj contains example linker directives files: ** standalone_ram.ld -- For programs that are linked into and run - out of RAM. + out of RAM. ** standalone_romcopy.ld -- For programs that are linked into ROM, but run out of RAM. ** standalone_romrun.ld -- For programs that are linked into and run - out of ROM. + out of ROM. Some configurations also contain other linker directives files: ** standalone_romdebug.ld -- For programs that are linked into and run out of ROM with enhanced debugging capabilities. ** standalone_pic.ld -- For programs built with position independent - code. + code. ** standalone_pid.ld -- For programs built with position independent data. ** standalone_picpid.ld -- For programs built with position independent code and data. -For more information about linker directives files, see the "MULTI: Building +For more information about linker directives files, see the "MULTI: Building Applications" book for your processor. diff --git a/ports_smp/cortex_a5x_smp/green/example_build/tgt/standalone_ram.ld b/ports_smp/cortex_a5x_smp/green/example_build/tgt/standalone_ram.ld index 2fbaebda..6729fa5b 100644 --- a/ports_smp/cortex_a5x_smp/green/example_build/tgt/standalone_ram.ld +++ b/ports_smp/cortex_a5x_smp/green/example_build/tgt/standalone_ram.ld @@ -66,5 +66,5 @@ SECTIONS // __ghs_romend = MEMENDADDR(flash_rsvd2); __ghs_ramstart = MEMADDR(dram_rsvd1); __ghs_ramend = MEMENDADDR(dram_rsvd2); - + } diff --git a/ports_smp/cortex_a5x_smp/green/example_build/tgt/standalone_romcopy.ld b/ports_smp/cortex_a5x_smp/green/example_build/tgt/standalone_romcopy.ld index af8e0815..4bf15651 100644 --- a/ports_smp/cortex_a5x_smp/green/example_build/tgt/standalone_romcopy.ld +++ b/ports_smp/cortex_a5x_smp/green/example_build/tgt/standalone_romcopy.ld @@ -29,10 +29,10 @@ SECTIONS // ROM startup code sections must be the // same in both the ROM and RAM copies. .ROM.boottext ROM(.boottext ) : > flash_memory - .ROM.syscall ROM(.syscall) : > . + .ROM.syscall ROM(.syscall) : > . .rodata : > flash_memory - .secinfo : > . + .secinfo : > . .fixaddr : > . .fixtype : > . @@ -70,7 +70,7 @@ SECTIONS __ghs_rombootcodestart = ADDR(.ROM.boottext); __ghs_rombootcodeend = ENDADDR(.fixtype); __ghs_rambootcodestart = ADDR(.boottext); - __ghs_rambootcodeend = ENDADDR(.stack); + __ghs_rambootcodeend = ENDADDR(.stack); // // These special symbols mark the bounds of RAM and ROM memory. diff --git a/ports_smp/cortex_a5x_smp/green/example_build/tgt/standalone_romrun.ld b/ports_smp/cortex_a5x_smp/green/example_build/tgt/standalone_romrun.ld index 0f01e6cc..bc3e9b08 100644 --- a/ports_smp/cortex_a5x_smp/green/example_build/tgt/standalone_romrun.ld +++ b/ports_smp/cortex_a5x_smp/green/example_build/tgt/standalone_romrun.ld @@ -31,14 +31,14 @@ SECTIONS .secinfo : > . .fixaddr : > . .fixtype : > . - + .CROM.data CROM(.data) : > . // // RAM SECTIONS // - .data : > dram_memory + .data : > dram_memory .bss : > . .ghcovfz CLEAR : > . .ghcovcz CLEAR : > . diff --git a/ports_smp/cortex_a5x_smp/green/inc/tx_el.h b/ports_smp/cortex_a5x_smp/green/inc/tx_el.h index 63a2f913..497abafe 100644 --- a/ports_smp/cortex_a5x_smp/green/inc/tx_el.h +++ b/ports_smp/cortex_a5x_smp/green/inc/tx_el.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,12 +37,6 @@ /* EventAnalyzer. It is assumed that tx_api.h and tx_port.h have */ /* already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TX_EL_H diff --git a/ports_smp/cortex_a5x_smp/green/inc/tx_port.h b/ports_smp/cortex_a5x_smp/green/inc/tx_port.h index 78eda175..5776b126 100644 --- a/ports_smp/cortex_a5x_smp/green/inc/tx_port.h +++ b/ports_smp/cortex_a5x_smp/green/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h Cortex-A5x-SMP/GHS */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A5x-SMP/GHS */ /* 6.1.9 */ /* */ /* AUTHOR */ @@ -32,27 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* symbol ULONG64_DEFINED, */ -/* resulting in version 6.1.9 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -94,12 +83,12 @@ static inline void _tx_memset(void * ptr, int value, unsigned num) /* Define ThreadX SMP initialization macro. */ -#define TX_PORT_SPECIFIC_PRE_INITIALIZATION +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION /* Define ThreadX SMP pre-scheduler initialization. */ -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION /* Enable the inter-core interrupt logic. */ @@ -140,7 +129,7 @@ static inline void _tx_memset(void * ptr, int value, unsigned num) #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -153,7 +142,7 @@ static inline void _tx_memset(void * ptr, int value, unsigned num) #include -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -202,19 +191,19 @@ typedef unsigned long long ALIGN_TYPE; #define TX_TIMER_THREAD_STACK_SIZE 4096 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ #define TX_INT_ENABLE 0x00 /* Enable IRQ & FIQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -272,7 +261,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -286,11 +275,11 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #define TX_THREAD_EXTENSION_2 ULONG tx_thread_fp_enable; #define TX_THREAD_EXTENSION_3 VOID * tx_thread_eh_globals; \ int Errno; \ @@ -309,11 +298,11 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -321,8 +310,8 @@ ULONG _tx_misra_time_stamp_get(VOID); tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -349,8 +338,8 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -367,7 +356,7 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the internal timer extension to also hold the thread pointer such that _tx_thread_timeout can figure out what thread timeout to process. */ - + #define TX_TIMER_INTERNAL_EXTENSION VOID *tx_timer_internal_extension_ptr; @@ -397,14 +386,14 @@ typedef struct TX_THREAD_SMP_PROTECT_STRUCT ULONG tx_thread_smp_protect_count; ULONG tx_thread_smp_protect_pad_0; ULONG tx_thread_smp_protect_pad_1; - ULONG tx_thread_smp_protect_pad_2; - ULONG tx_thread_smp_protect_pad_3; + ULONG tx_thread_smp_protect_pad_2; + ULONG tx_thread_smp_protect_pad_3; } TX_THREAD_SMP_PROTECT; -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -442,8 +431,8 @@ VOID tx_thread_fp_disable(VOID); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-A5x-SMP/GHS Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A5x-SMP/GHS Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a5x_smp/green/readme_threadx.txt b/ports_smp/cortex_a5x_smp/green/readme_threadx.txt index e2cb3b78..087a0496 100644 --- a/ports_smp/cortex_a5x_smp/green/readme_threadx.txt +++ b/ports_smp/cortex_a5x_smp/green/readme_threadx.txt @@ -1,30 +1,30 @@ - Microsoft's Azure RTOS ThreadX SMP for Cortex-A5x + Microsoft's Azure RTOS ThreadX SMP for Cortex-A5x Using the Green Hills Software Tools 1. Open the ThreadX SMP Project Workspace -In order to build the ThreadX SMP library and the ThreadX SMP demonstration -first load the ThreadX SMP project workspace azure_rtos_workspace.gpj, which is -located inside your ThreadX SMP directory. +In order to build the ThreadX SMP library and the ThreadX SMP demonstration +first load the ThreadX SMP project workspace azure_rtos_workspace.gpj, which is +located inside your ThreadX SMP directory. 2. Building the ThreadX SMP run-time Library -Building the ThreadX SMP library is easy; simply select the MULTI project file -tx.gpj and then select the build button. You should now observe the -compilation and assembly of the ThreadX SMP library. This project build produces +Building the ThreadX SMP library is easy; simply select the MULTI project file +tx.gpj and then select the build button. You should now observe the +compilation and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP library file tx.a. 3. Demonstration System The ThreadX SMP demonstration is designed to execute under the MULTI environment -on the Xilinx UltraScale+ ZCU102 evaluation board. +on the Xilinx UltraScale+ ZCU102 evaluation board. -Building the demonstration is easy; simply select the MULTI project file -sample_threadx.gpj. At this point, select the "Project Build" button and observe -the compilation, assembly, and linkage of the ThreadX SMP demonstration application. +Building the demonstration is easy; simply select the MULTI project file +sample_threadx.gpj. At this point, select the "Project Build" button and observe +the compilation, assembly, and linkage of the ThreadX SMP demonstration application. You are now ready to download the ELF image using the Xilinx tools on the ZCU102 evaluation board. @@ -32,39 +32,39 @@ evaluation board. 4. System Initialization -The system entry point using the Green Hills tools is at the label _boot. -This is defined within the tx_boot.a64 file. In addition, this is where all static +The system entry point using the Green Hills tools is at the label _boot. +This is defined within the tx_boot.a64 file. In addition, this is where all static and global preset C variable initialization processing is called from. After the Green Hills startup function returns, ThreadX SMP initialization is called. The main initialization function is _tx_initialize_low_level and -is located in the file tx_initialize_low_level.a64. This function is responsible -for setting up various system data structures, interrupt vectors, and the +is located in the file tx_initialize_low_level.a64. This function is responsible +for setting up various system data structures, interrupt vectors, and the periodic timer interrupt source of ThreadX SMP. -In addition, _tx_initialize_low_level determines where the first available +In addition, _tx_initialize_low_level determines where the first available RAM memory address is located. This address is supplied to tx_application_define. -By default, the first available RAM memory address is assumed to start at the -beginning of the ThreadX SMP section .free_mem. If changes are made to the -sample_threadx.ld file, the .free_mem section should remain the last allocated -section in the main RAM area. The starting address of this section is passed +By default, the first available RAM memory address is assumed to start at the +beginning of the ThreadX SMP section .free_mem. If changes are made to the +sample_threadx.ld file, the .free_mem section should remain the last allocated +section in the main RAM area. The starting address of this section is passed to tx_application_define. 5. Register Usage and Stack Frames -The 64-bit Green Hills compiler assumes that registers x0-x18 are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX SMP takes advantage of this in -situations where a context switch happens as a result of making a ThreadX SMP -service call (which is itself a C function). In such cases, the saved +The 64-bit Green Hills compiler assumes that registers x0-x18 are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX SMP takes advantage of this in +situations where a context switch happens as a result of making a ThreadX SMP +service call (which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: @@ -82,10 +82,10 @@ FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: 0x040 x22 x21 0x048 x23 x22 0x050 x20 x19 - 0x058 x21 x20 - 0x060 x18 x29 - 0x068 x19 x30 - 0x070 x16 + 0x058 x21 x20 + 0x060 x18 x29 + 0x068 x19 x30 + 0x070 x16 0x078 x17 0x080 x14 0x088 x15 @@ -104,7 +104,7 @@ FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: 0x0F0 x0 0x0F8 x1 0x100 x29 - 0x108 x30 + 0x108 x30 FP enabled and TX_THREAD.tx_thread_fp_enable == 1: @@ -153,19 +153,19 @@ FP enabled and TX_THREAD.tx_thread_fp_enable == 1: 0x1F0 q3 0x200 q0 0x210 q1 - 0x220 x28 - 0x228 reserved - 0x230 x26 - 0x238 x27 - 0x240 x24 - 0x248 x25 - 0x250 x22 - 0x258 x23 - 0x260 x20 - 0x268 x21 - 0x270 x18 - 0x278 x19 - 0x280 x16 + 0x220 x28 + 0x228 reserved + 0x230 x26 + 0x238 x27 + 0x240 x24 + 0x248 x25 + 0x250 x22 + 0x258 x23 + 0x260 x20 + 0x268 x21 + 0x270 x18 + 0x278 x19 + 0x280 x16 0x288 x17 0x290 x14 0x298 x15 @@ -184,20 +184,20 @@ FP enabled and TX_THREAD.tx_thread_fp_enable == 1: 0x300 x0 0x308 x1 0x310 x29 - 0x318 x30 + 0x318 x30 6. Improving Performance -The distribution version of ThreadX SMP is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX SMP itself. Of course, this costs some +The distribution version of ThreadX SMP is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX SMP itself. Of course, this costs some performance. To make ThreadX SMP run faster, you can change the tx.gpj project -to disable debug information and enable the desired optimizations. +to disable debug information and enable the desired optimizations. -In addition, you can eliminate the ThreadX SMP basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined before tx_api.h is included. +In addition, you can eliminate the ThreadX SMP basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. 7. Interrupt Handling @@ -216,25 +216,25 @@ __irq_handler: B _tx_thread_context_restore -By default, ThreadX SMP assumes EL3 level of execution. Running and taking exceptions in EL1 +By default, ThreadX SMP assumes EL3 level of execution. Running and taking exceptions in EL1 and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined. 8. ThreadX SMP Timer Interrupt -ThreadX SMP requires a periodic interrupt source to manage all time-slicing, thread sleeps, -timeouts, and application timers. Without such a timer interrupt source, these services are -not functional. However, all other ThreadX SMP services are operational without a periodic +ThreadX SMP requires a periodic interrupt source to manage all time-slicing, thread sleeps, +timeouts, and application timers. Without such a timer interrupt source, these services are +not functional. However, all other ThreadX SMP services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.a64. 9. FP Support By default, FP support is disabled for each thread. If saving the context of the FP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the FP usage: void tx_thread_fp_enable(void); @@ -257,7 +257,7 @@ information associated with this specific port of ThreadX SMP: 04-02-2021 Release 6.1.6 changes: tx_port.h Updated macro definition -09/30/2020 Initial ThreadX SMP version 6.1 of Cortex-A5x/Green Hills port. +09/30/2020 Initial ThreadX SMP version 6.1 of Cortex-A5x/Green Hills port. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_el.c b/ports_smp/cortex_a5x_smp/green/src/tx_el.c index cab97a67..9eac2d7e 100644 --- a/ports_smp/cortex_a5x_smp/green/src/tx_el.c +++ b/ports_smp/cortex_a5x_smp/green/src/tx_el.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -83,12 +84,6 @@ UINT _tx_thread_interrupt_control(UINT new_posture); /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_el_initialize(VOID) { diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_initialize_low_level.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_initialize_low_level.a64 index 21319b9e..ce69d1f0 100644 --- a/ports_smp/cortex_a5x_smp/green/src/tx_initialize_low_level.a64 +++ b/ports_smp/cortex_a5x_smp/green/src/tx_initialize_low_level.a64 @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_context_restore.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_context_restore.a64 index 7bd2c4d7..9d0c0c6b 100644 --- a/ports_smp/cortex_a5x_smp/green/src/tx_thread_context_restore.a64 +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_context_restore.a64 @@ -1,18 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -25,7 +25,7 @@ /* Include necessary system files. */ -/* +/* #include "tx_api.h" #include "tx_thread.h" #include "tx_timer.h" @@ -35,41 +35,41 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_context_restore Cortex-A5x-SMP/GHS */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-A5x-SMP/GHS */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function restores the interrupt context if it is processing a */ -/* nested interrupt. If not, it returns to the interrupt thread if no */ -/* preemption is necessary. Otherwise, if preemption is necessary or */ -/* if no thread was running, the function returns to the scheduler. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_thread_schedule Thread scheduling routine */ -/* */ -/* CALLED BY */ -/* */ -/* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -93,7 +93,7 @@ _tx_thread_context_restore: #endif /* Pickup the CPU ID. */ - + MRS x8, MPIDR_EL1 // Pickup the core ID UBFX x8, x8, #0, #8 // Isolate and right justify core ID @@ -104,13 +104,13 @@ _tx_thread_context_restore: LDR x3, =_tx_thread_system_state // Pickup address of system state var LDR w2, [x3, x8, LSL #2] // Pickup system state SUB w2, w2, #1 // Decrement the counter - STR w2, [x3, x8, LSL #2] // Store the counter + STR w2, [x3, x8, LSL #2] // Store the counter CMP w2, #0 // Was this the first interrupt? B.EQ __tx_thread_not_nested_restore // If so, not a nested restore /* Interrupts are nested. */ - /* Just recover the saved registers and return to the point of + /* Just recover the saved registers and return to the point of interrupt. */ LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL @@ -143,7 +143,7 @@ _tx_thread_context_restore: __tx_thread_not_nested_restore: /* Determine if a thread was interrupted and no preemption is required. */ - /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) || (_tx_thread_preempt_disable)) { */ @@ -154,7 +154,7 @@ __tx_thread_not_nested_restore: LDR x3, =_tx_thread_execute_ptr // Pickup address of execute thread ptr LDR x2, [x3, x8, LSL #3] // Pickup actual execute thread pointer CMP x0, x2 // Is the same thread highest priority? - B.EQ __tx_thread_no_preempt_restore // Same thread in the execute list, + B.EQ __tx_thread_no_preempt_restore // Same thread in the execute list, // no preemption needs to happen LDR x3, =_tx_thread_smp_protection // Build address to protection structure LDR w3, [x3, #4] // Pickup the owning core @@ -283,7 +283,7 @@ __tx_thread_dont_save_ts: MOV x2, #1 // Build ready flag DMB ISH // Ensure that accesses to shared resource have completed - STR w2, [x0, #260] // Set thread's ready flag + STR w2, [x0, #260] // Set thread's ready flag /* Return to the scheduler. */ /* _tx_thread_schedule(); */ diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_context_save.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_context_save.a64 index bd6ab6c5..254df049 100644 --- a/ports_smp/cortex_a5x_smp/green/src/tx_thread_context_save.a64 +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_context_save.a64 @@ -1,18 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -32,40 +32,40 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_context_save Cortex-A5x-SMP/GHS */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-A5x-SMP/GHS */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function saves the context of an executing thread in the */ -/* beginning of interrupt processing. The function also ensures that */ -/* the system stack is used upon return to the calling ISR. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -78,7 +78,7 @@ _tx_thread_context_save: /* Upon entry to this routine, it is assumed that IRQ/FIQ interrupts are locked - out, x29 (frame pointer), x30 (link register) are saved, we are in the proper EL, + out, x29 (frame pointer), x30 (link register) are saved, we are in the proper EL, and all other registers are intact. */ /* Check for a nested interrupt condition. */ @@ -92,7 +92,7 @@ _tx_thread_context_save: MRS x1, MPIDR_EL1 // Pickup the core ID UBFX x1, x1, #0, #8 // Isolate and right justify core ID - + LDR x3, =_tx_thread_system_state // Pickup address of system state var LDR w2, [x3, x1, LSL #2] // Pickup system state CMP w2, #0 // Is this the first interrupt? @@ -153,7 +153,7 @@ __tx_thread_not_nested_save: LDR x2, =_tx_thread_current_ptr // Pickup address of current thread ptr LDR x0, [x2, x1, LSL #3] // Pickup current thread pointer CMP x0, #0 // Is it NULL? - B.EQ __tx_thread_idle_system_save // If so, interrupt occurred in + B.EQ __tx_thread_idle_system_save // If so, interrupt occurred in // scheduling loop - nothing needs saving! /* Save minimal context of interrupted thread. */ @@ -204,7 +204,7 @@ __tx_thread_not_nested_save: LDP x29, x30, [sp], #16 // Recover x29, x30 #endif - RET // Return to caller + RET // Return to caller /* } else @@ -214,7 +214,7 @@ __tx_thread_idle_system_save: /* Interrupt occurred in the scheduling loop. */ - /* Not much to do here, just adjust the stack pointer, and return to IRQ + /* Not much to do here, just adjust the stack pointer, and return to IRQ processing. */ #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY @@ -227,7 +227,7 @@ __tx_thread_idle_system_save: #endif ADD sp, sp, #48 // Recover saved registers - RET // Continue IRQ processing + RET // Continue IRQ processing /* } } */ diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_fp_disable.c b/ports_smp/cortex_a5x_smp/green/src/tx_thread_fp_disable.c index 6b9db9e6..6b4fd0e9 100644 --- a/ports_smp/cortex_a5x_smp/green/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,12 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_fp_enable.c b/ports_smp/cortex_a5x_smp/green/src/tx_thread_fp_enable.c index 57957285..8180bb85 100644 --- a/ports_smp/cortex_a5x_smp/green/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,12 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_interrupt_control.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_interrupt_control.a64 index c9d4e756..ed7dc70c 100644 --- a/ports_smp/cortex_a5x_smp/green/src/tx_thread_interrupt_control.a64 +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_interrupt_control.a64 @@ -1,18 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -31,39 +31,39 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_interrupt_control Cortex-A5x-SMP/GHS */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-A5x-SMP/GHS */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function is responsible for changing the interrupt lockout */ -/* posture of the system. */ -/* */ -/* INPUT */ -/* */ -/* new_posture New interrupt lockout posture */ -/* */ -/* OUTPUT */ -/* */ -/* old_posture Old interrupt lockout posture */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_interrupt_disable.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_interrupt_disable.a64 index 984ae865..596c6c4d 100644 --- a/ports_smp/cortex_a5x_smp/green/src/tx_thread_interrupt_disable.a64 +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_interrupt_disable.a64 @@ -1,18 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -31,38 +31,38 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_interrupt_disable Cortex-A5x-SMP/GHS */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-A5x-SMP/GHS */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function is responsible for disabling interrupts */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* old_posture Old interrupt lockout posture */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* */ +/* This function is responsible for disabling interrupts */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_interrupt_restore.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_interrupt_restore.a64 index c1d88e1b..b500bbfd 100644 --- a/ports_smp/cortex_a5x_smp/green/src/tx_thread_interrupt_restore.a64 +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_interrupt_restore.a64 @@ -1,18 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -31,39 +31,39 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_interrupt_restore Cortex-A5x-SMP/GHS */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-A5x-SMP/GHS */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ +/* */ /* This function is responsible for restoring interrupts to the state */ /* returned by a previous _tx_thread_interrupt_disable call. */ -/* */ -/* INPUT */ -/* */ -/* old_posture Old interrupt lockout posture */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* */ +/* INPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_schedule.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_schedule.a64 index adf5b115..9bfa402c 100644 --- a/ports_smp/cortex_a5x_smp/green/src/tx_thread_schedule.a64 +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_schedule.a64 @@ -1,18 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -35,42 +35,42 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_schedule Cortex-A5x-SMP/GHS */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-A5x-SMP/GHS */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function waits for a thread control block pointer to appear in */ -/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -/* in the variable, the corresponding thread is resumed. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ /* None */ -/* */ -/* CALLS */ -/* */ +/* */ +/* OUTPUT */ +/* */ /* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_initialize_kernel_enter ThreadX entry function */ -/* _tx_thread_system_return Return to system from thread */ -/* _tx_thread_context_restore Restore thread's context */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -94,7 +94,7 @@ _tx_thread_schedule: /* Wait for a thread to execute. */ /* do { */ - + LDR x1, =_tx_thread_execute_ptr // Address of thread execute ptr #ifdef TX_ENABLE_WFI @@ -102,9 +102,9 @@ __tx_thread_schedule_loop: MSR DAIFSet, 0x3 // Lockout interrupts LDR x0, [x1, x20, LSL #3] // Pickup next thread to execute CMP x0, #0 // Is it NULL? - B.NE _tx_thread_schedule_thread // + B.NE _tx_thread_schedule_thread // MSR DAIFClr, 0x3 // Enable interrupts - WFI // + WFI // B __tx_thread_schedule_loop // Keep looking for a thread _tx_thread_schedule_thread: #else @@ -116,23 +116,23 @@ _tx_thread_schedule_thread: /* } while(_tx_thread_execute_ptr == TX_NULL); */ - + /* Now make sure the thread's ready bit is set. */ - + MOV x3, #0 // Build clear value LDR w2, [x0, #260] // Pickup the ready bit CMP w2, #1 // Is it set? B.NE _tx_thread_schedule // If not, restart the scheduling loop STR w3, [x0, #260] // Clear the ready bit DMB ISH // - + /* Yes! We have a thread to execute. Lockout interrupts and transfer control to it. */ /* Setup the current thread pointer. */ /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ - LDR x1, =_tx_thread_current_ptr // Pickup address of current thread + LDR x1, =_tx_thread_current_ptr // Pickup address of current thread STR x0, [x1, x20, LSL #3] // Setup current thread pointer /* Increment the run count for this thread. */ @@ -146,7 +146,7 @@ _tx_thread_schedule_thread: /* Setup time-slice, if present. */ /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ - LDR x2, =_tx_timer_time_slice // Pickup address of time slice + LDR x2, =_tx_timer_time_slice // Pickup address of time slice // variable LDR x4, [x0, #8] // Switch stack pointers MOV sp, x4 // @@ -247,7 +247,7 @@ _skip_solicited_fp_restore: LDP x19, x20, [sp], #16 // Recover x19, x20 LDP x29, x30, [sp], #16 // Recover x29, x30 MSR DAIF, x4 // Recover DAIF - RET // Return to caller + RET // Return to caller /* } */ diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_core_get.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_core_get.a64 index 634407c9..6744f799 100644 --- a/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_core_get.a64 +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_core_get.a64 @@ -1,18 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread - Low Level SMP Support */ /** */ @@ -35,38 +35,38 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_smp_core_get Cortex-A5x-SMP/GHS */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_core_get Cortex-A5x-SMP/GHS */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function gets the currently running core number and returns it.*/ -/* */ -/* INPUT */ -/* */ +/* */ +/* This function gets the currently running core number and returns it.*/ +/* */ +/* INPUT */ +/* */ /* None */ -/* */ -/* OUTPUT */ -/* */ -/* Core ID */ -/* */ -/* CALLS */ -/* */ +/* */ +/* OUTPUT */ +/* */ +/* Core ID */ +/* */ +/* CALLS */ +/* */ /* None */ -/* */ -/* CALLED BY */ -/* */ +/* */ +/* CALLED BY */ +/* */ /* ThreadX Source */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -78,5 +78,5 @@ _tx_thread_smp_core_get: MRS x0, MPIDR_EL1 // Pickup the core ID UBFX x0, x0, #0, #8 // Isolate and right justify core ID RET - - + + diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_core_preempt.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_core_preempt.a64 index 2dab6ebc..dfdd43f9 100644 --- a/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_core_preempt.a64 +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_core_preempt.a64 @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_current_state_get.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_current_state_get.a64 index 2100c503..e0a91915 100644 --- a/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_current_state_get.a64 +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_current_state_get.a64 @@ -1,18 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread - Low Level SMP Support */ /** */ @@ -35,38 +35,38 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_smp_current_state_get Cortex-A5x-SMP/GHS */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_current_state_get Cortex-A5x-SMP/GHS */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function is gets the current state of the calling core. */ -/* */ -/* INPUT */ -/* */ +/* */ +/* This function is gets the current state of the calling core. */ +/* */ +/* INPUT */ +/* */ /* None */ -/* */ -/* OUTPUT */ -/* */ +/* */ +/* OUTPUT */ +/* */ /* None */ -/* */ -/* CALLS */ -/* */ +/* */ +/* CALLS */ +/* */ /* None */ -/* */ -/* CALLED BY */ -/* */ -/* ThreadX Components */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_current_thread_get.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_current_thread_get.a64 index 2e1b417e..87f70429 100644 --- a/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_current_thread_get.a64 +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_current_thread_get.a64 @@ -1,18 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread - Low Level SMP Support */ /** */ @@ -35,38 +35,38 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_smp_current_thread_get Cortex-A5x-SMP/GHS */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_current_thread_get Cortex-A5x-SMP/GHS */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function is gets the current thread of the calling core. */ -/* */ -/* INPUT */ -/* */ +/* */ +/* This function is gets the current thread of the calling core. */ +/* */ +/* INPUT */ +/* */ /* None */ -/* */ -/* OUTPUT */ -/* */ +/* */ +/* OUTPUT */ +/* */ /* None */ -/* */ -/* CALLS */ -/* */ +/* */ +/* CALLS */ +/* */ /* None */ -/* */ -/* CALLED BY */ -/* */ -/* ThreadX Components */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_initialize_wait.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_initialize_wait.a64 index d8eae3ca..8f6df68f 100644 --- a/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_initialize_wait.a64 +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_initialize_wait.a64 @@ -1,18 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread - Low Level SMP Support */ /** */ @@ -35,40 +35,40 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_smp_initialize_wait Cortex-A5x-SMP/GHS */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_initialize_wait Cortex-A5x-SMP/GHS */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function is the place where additional cores wait until */ -/* initialization is complete before they enter the thread scheduling */ -/* loop. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ +/* */ +/* This function is the place where additional cores wait until */ +/* initialization is complete before they enter the thread scheduling */ +/* loop. */ +/* */ +/* INPUT */ +/* */ /* None */ -/* */ -/* CALLS */ -/* */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ /* _tx_thread_schedule Thread scheduling loop */ -/* */ -/* CALLED BY */ -/* */ -/* Hardware */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* */ +/* CALLED BY */ +/* */ +/* Hardware */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -87,7 +87,7 @@ _tx_thread_smp_initialize_wait: MRS x2, MPIDR_EL1 // Pickup the core ID UBFX x2, x2, #0, #8 // Isolate and right justify core ID - /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release + /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release flag. */ LDR w1, =0xF0F0F0F0 // Build TX_INITIALIZE_IN_PROGRESS flag @@ -98,7 +98,7 @@ wait_for_initialize: B.NE wait_for_initialize // Not equal, just spin here /* Save the system stack pointer for this core. */ - + LDR x0, =_tx_thread_system_stack_ptr // Pickup address of system stack ptr MOV x1, sp // Pickup SP SUB x1, x1, #15 // @@ -107,30 +107,30 @@ wait_for_initialize: /* Pickup the release cores flag. */ - + LDR x4, =_tx_thread_smp_release_cores_flag // Build address of release cores flag -wait_for_release: +wait_for_release: LDR w0, [x4, #0] // Pickup the flag CMP w0, #0 // Is it set? B.EQ wait_for_release // Wait for the flag to be set - + /* Core 0 has released this core. */ - + /* Clear this core's system state variable. */ - + MOV x0, #0 // Build clear value STR w0, [x3, x2, LSL #2] // Set the current system state for this core to zero - + /* Now wait for core 0 to finish it's initialization. */ - + core_0_wait_loop: LDR w0, [x3, #0] // Pickup the current system state for core 0 CMP w0, #0 // Is it 0? B.NE core_0_wait_loop // No, keep waiting for core 0 to finish its initialization - + /* Initialization is complete, enter the scheduling loop! */ - - B _tx_thread_schedule // Enter the scheduling loop for this core + + B _tx_thread_schedule // Enter the scheduling loop for this core RET diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_low_level_initialize.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_low_level_initialize.a64 index 343eacb9..38fa4c02 100644 --- a/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_low_level_initialize.a64 +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_low_level_initialize.a64 @@ -1,18 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread - Low Level SMP Support */ /** */ @@ -34,39 +34,39 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_smp_low_level_initialize Cortex-A5x-SMP/GHS */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_low_level_initialize Cortex-A5x-SMP/GHS */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function performs low-level initialization of the booting */ -/* core. */ -/* */ -/* INPUT */ -/* */ -/* number_of_cores Number of cores */ -/* */ -/* OUTPUT */ -/* */ +/* */ +/* This function performs low-level initialization of the booting */ +/* core. */ +/* */ +/* INPUT */ +/* */ +/* number_of_cores Number of cores */ +/* */ +/* OUTPUT */ +/* */ /* None */ -/* */ -/* CALLS */ -/* */ +/* */ +/* CALLS */ +/* */ /* None */ -/* */ -/* CALLED BY */ -/* */ -/* _tx_initialize_high_level ThreadX high-level init */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_high_level ThreadX high-level init */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_protect.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_protect.a64 index 95b8f799..547d9791 100644 --- a/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_protect.a64 +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_protect.a64 @@ -1,18 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread - Low Level SMP Support */ /** */ @@ -35,40 +35,40 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_smp_protect Cortex-A5x-SMP/GHS */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_protect Cortex-A5x-SMP/GHS */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function gets protection for running inside the ThreadX */ -/* source. This is acomplished by a combination of a test-and-set */ -/* flag and periodically disabling interrupts. */ -/* */ -/* INPUT */ -/* */ +/* */ +/* This function gets protection for running inside the ThreadX */ +/* source. This is acomplished by a combination of a test-and-set */ +/* flag and periodically disabling interrupts. */ +/* */ +/* INPUT */ +/* */ /* None */ -/* */ -/* OUTPUT */ -/* */ -/* Previous Status Register */ -/* */ -/* CALLS */ -/* */ +/* */ +/* OUTPUT */ +/* */ +/* Previous Status Register */ +/* */ +/* CALLS */ +/* */ /* None */ -/* */ -/* CALLED BY */ -/* */ +/* */ +/* CALLED BY */ +/* */ /* ThreadX Source */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -82,10 +82,10 @@ _tx_thread_smp_protect: MSR DAIFSet, 0x3 // Lockout interrupts /* Pickup the CPU ID. */ - + MRS x2, MPIDR_EL1 // Pickup the core ID UBFX x2, x2, #0, #8 // Isolate and right justify core ID - + LDR x1, =_tx_thread_smp_protection // Build address to protection structure LDR w3, [x1, #4] // Pickup the owning core CMP w3, w2 // Is it this core? @@ -94,7 +94,7 @@ _tx_thread_smp_protect: LDAXR w4, [x1, #0] // Pickup the protection flag CBZ w4, _get_protection // Yes, get the protection MSR DAIF, x0 // Restore interrupts - ISB // + ISB // #ifdef TX_ENABLE_WFE WFE // Go into standby #endif @@ -106,9 +106,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count @@ -116,6 +116,6 @@ _owned: STR w5, [x1, #8] // Store ownership count DMB ISH // RET - - + + diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_time_get.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_time_get.a64 index 8043d247..45d286b0 100644 --- a/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_time_get.a64 +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_time_get.a64 @@ -1,18 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread - Low Level SMP Support */ /** */ @@ -35,39 +35,39 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_smp_time_get Cortex-A5x-SMP/GHS */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_time_get Cortex-A5x-SMP/GHS */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function gets the global time value that is used for debug */ -/* information and event tracing. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* 32-bit time stamp */ -/* */ -/* CALLS */ -/* */ +/* */ +/* This function gets the global time value that is used for debug */ +/* information and event tracing. */ +/* */ +/* INPUT */ +/* */ /* None */ -/* */ -/* CALLED BY */ -/* */ +/* */ +/* OUTPUT */ +/* */ +/* 32-bit time stamp */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ /* ThreadX Source */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -79,4 +79,4 @@ _tx_thread_smp_time_get: MOV x0, #0 // Add time source - application specific RET - + diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_unprotect.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_unprotect.a64 index 575b5301..38aaeac4 100644 --- a/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_unprotect.a64 +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_unprotect.a64 @@ -1,18 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread - Low Level SMP Support */ /** */ @@ -35,41 +35,41 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_smp_unprotect Cortex-A5x-SMP/GHS */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_unprotect Cortex-A5x-SMP/GHS */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function releases previously obtained protection. The supplied */ -/* previous SR is restored. If the value of _tx_thread_system_state */ -/* and _tx_thread_preempt_disable are both zero, then multithreading */ -/* is enabled as well. */ -/* */ -/* INPUT */ -/* */ -/* Previous Status Register */ -/* */ -/* OUTPUT */ -/* */ +/* */ +/* This function releases previously obtained protection. The supplied */ +/* previous SR is restored. If the value of _tx_thread_system_state */ +/* and _tx_thread_preempt_disable are both zero, then multithreading */ +/* is enabled as well. */ +/* */ +/* INPUT */ +/* */ +/* Previous Status Register */ +/* */ +/* OUTPUT */ +/* */ /* None */ -/* */ -/* CALLS */ -/* */ +/* */ +/* CALLS */ +/* */ /* None */ -/* */ -/* CALLED BY */ -/* */ +/* */ +/* CALLED BY */ +/* */ /* ThreadX Source */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -97,7 +97,7 @@ _tx_thread_smp_unprotect: LDR x2,=_tx_thread_preempt_disable // Build address of preempt disable flag LDR w3, [x2] // Pickup preempt disable flag CMP w3, #0 // Is the preempt disable flag set? - B.NE _still_protected // Yes, skip the protection release + B.NE _still_protected // Yes, skip the protection release MOV x2, #0xFFFFFFFF // Build invalid value STR w2, [x1, #4] // Mark the protected core as invalid DMB ISH // Ensure that accesses to shared resource have completed @@ -111,4 +111,4 @@ _still_protected: SEV // Send event to other CPUs MSR DAIF, x0 // Restore interrupt posture RET - + diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_stack_build.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_stack_build.a64 index b76b935e..6a41aa5e 100644 --- a/ports_smp/cortex_a5x_smp/green/src/tx_thread_stack_build.a64 +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_stack_build.a64 @@ -1,18 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -33,41 +33,41 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_stack_build Cortex-A5x-SMP/GHS */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-A5x-SMP/GHS */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ +/* */ /* This function builds a stack frame on the supplied thread's stack. */ /* The stack frame results in a fake interrupt return to the supplied */ -/* function pointer. */ -/* */ -/* INPUT */ -/* */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ /* thread_ptr Pointer to thread control blk */ /* function_ptr Pointer to return function */ -/* */ -/* OUTPUT */ -/* */ +/* */ +/* OUTPUT */ +/* */ /* None */ -/* */ -/* CALLS */ -/* */ +/* */ +/* CALLS */ +/* */ /* None */ -/* */ -/* CALLED BY */ -/* */ +/* */ +/* CALLED BY */ +/* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -79,10 +79,10 @@ .type _tx_thread_stack_build, @function _tx_thread_stack_build: - + /* Build a fake interrupt frame. The form of the fake interrupt stack on the Cortex-A5x should look like the following after it is built: - + Stack Top: SSPR Initial SSPR ELR Point of interrupt x28 Initial value for x28 @@ -128,7 +128,7 @@ _tx_thread_stack_build: MOV x2, #0 // Build clear value MOV x3, #0 // - + STP x2, x3, [x4, #-16]! // Set backtrace to 0 STP x2, x3, [x4, #-16]! // Set initial x29, x30 STP x2, x3, [x4, #-16]! // Set initial x0, x1 @@ -163,7 +163,7 @@ _tx_thread_stack_build: STR x4, [x0, #8] // Save stack pointer in thread's MOV x3, #1 // Build ready flag - STR w3, [x0, #260] // Set ready flag + STR w3, [x0, #260] // Set ready flag RET // Return to caller /* } */ diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_system_return.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_system_return.a64 index 0dea1b43..ff0d7b90 100644 --- a/ports_smp/cortex_a5x_smp/green/src/tx_thread_system_return.a64 +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_system_return.a64 @@ -1,18 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Thread */ /** */ @@ -34,41 +34,41 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_thread_system_return Cortex-A5x-SMP/GHS */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-A5x-SMP/GHS */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function is target processor specific. It is used to transfer */ -/* control from a thread back to the ThreadX system. Only a */ -/* minimal context is saved since the compiler assumes temp registers */ -/* are going to get slicked by a function call anyway. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_thread_schedule Thread scheduling loop */ -/* */ -/* CALLED BY */ -/* */ -/* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -162,13 +162,13 @@ __tx_thread_dont_save_ts: STR x4, [x5, x8, LSL #3] // Clear current thread pointer /* Set ready bit in thread control block. */ - + MOV x3, #1 // Build ready value - STR w3, [x6, #260] // Make the thread ready - DMB ISH // - + STR w3, [x6, #260] // Make the thread ready + DMB ISH // + /* Now clear protection. It is assumed that protection is in force whenever this routine is called. */ - + LDR x3, =_tx_thread_smp_protection // Pickup address of protection structure LDR x1, =_tx_thread_preempt_disable // Build address to preempt disable flag STR w4, [x1, #0] // Clear preempt disable flag diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_timer_interrupt.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_timer_interrupt.a64 index b48d00e3..2e868234 100644 --- a/ports_smp/cortex_a5x_smp/green/src/tx_timer_interrupt.a64 +++ b/ports_smp/cortex_a5x_smp/green/src/tx_timer_interrupt.a64 @@ -1,18 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** ThreadX Component */ +/** */ +/** ThreadX Component */ /** */ /** Timer */ /** */ @@ -32,43 +32,43 @@ .text .align 3 -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _tx_timer_interrupt Cortex-A5x-SMP/GHS */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-A5x-SMP/GHS */ /* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This function processes the hardware timer interrupt. This */ -/* processing includes incrementing the system clock and checking for */ -/* time slice and/or timer expiration. If either is found, the */ -/* interrupt context save/restore functions are called along with the */ -/* expiration functions. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_timer_expiration_process Timer expiration processing */ -/* _tx_thread_time_slice Time slice interrupted thread */ -/* */ -/* CALLED BY */ -/* */ -/* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -179,8 +179,8 @@ __tx_timer_dont_activate: /* Release inter-core protection. */ - - MOV x0, x28 // Pass the previous status register back + + MOV x0, x28 // Pass the previous status register back BL _tx_thread_smp_unprotect // Release protection LDP x29, x30, [sp], #16 // Recover x29, x30 diff --git a/ports_smp/cortex_a5x_smp/iar/inc/tx_port.h b/ports_smp/cortex_a5x_smp/iar/inc/tx_port.h index 1f9301c7..f46ceddf 100644 --- a/ports_smp/cortex_a5x_smp/iar/inc/tx_port.h +++ b/ports_smp/cortex_a5x_smp/iar/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,12 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.9 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -446,7 +441,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX Cortex-A5x-SMP/IAR Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX Cortex-A5x-SMP/IAR Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a5x_smp/iar/readme_threadx.txt b/ports_smp/cortex_a5x_smp/iar/readme_threadx.txt index 2e651cec..d1472701 100644 --- a/ports_smp/cortex_a5x_smp/iar/readme_threadx.txt +++ b/ports_smp/cortex_a5x_smp/iar/readme_threadx.txt @@ -1,14 +1,14 @@ - Microsoft's Azure RTOS ThreadX SMP for Cortex-A5x + Microsoft's Azure RTOS ThreadX SMP for Cortex-A5x Using the IAR Tools 1. Building the ThreadX run-time Library Building the ThreadX library is easy. First, open the Azure RTOS workspace -azure_rtos.eww. Next, make the TX project the "active project" in the -IAR Embedded Workbench and select the "Make" button. You should observe -assembly and compilation of a series of ThreadX source files. This -results in the ThreadX run-time library file tx.a, which is needed by +azure_rtos.eww. Next, make the TX project the "active project" in the +IAR Embedded Workbench and select the "Make" button. You should observe +assembly and compilation of a series of ThreadX source files. This +results in the ThreadX run-time library file tx.a, which is needed by the application. @@ -18,39 +18,39 @@ The ThreadX demonstration is designed to execute under the IAR debugger connected to the i.MX 8M Nano board via the I-Jet JTAG debugger. Building the demonstration is easy; simply make the sample_threadx.ewp project -the "active project" in the IAR Embedded Workbench and select the +the "active project" in the IAR Embedded Workbench and select the "Make" button. -You should observe the compilation of sample_threadx.c (which is the demonstration +You should observe the compilation of sample_threadx.c (which is the demonstration application) and linking with tx.a. The resulting file sample_threadx.out is a binary file that can be downloaded and executed on the i.MX 8M Nana board. 3. System Initialization -The entry point in ThreadX SMP for the Cortex-A5x using IAR tools is at label -"setup_entrypoints". This is defined within the IAR compiler's startup code (cstartup.s). -In addition, this is where all static and global pre-set C variable initialization processing +The entry point in ThreadX SMP for the Cortex-A5x using IAR tools is at label +"setup_entrypoints". This is defined within the IAR compiler's startup code (cstartup.s). +In addition, this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX SMP tx_initialize_low_level.s file is responsible for determining the -first available RAM address for use by the application, which is supplied as the +The ThreadX SMP tx_initialize_low_level.s file is responsible for determining the +first available RAM address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 4. Register Usage and Stack Frames -The 64-bit IAR compiler assumes that registers x0-x18 are scratch registers -for each function. All other registers used by a C function must be preserved -by the function. ThreadX SMP takes advantage of this in situations where a context -switch happens as a result of making a ThreadX SMP service call (which is itself a -C function). In such cases, the saved context of a thread is only the +The 64-bit IAR compiler assumes that registers x0-x18 are scratch registers +for each function. All other registers used by a C function must be preserved +by the function. ThreadX SMP takes advantage of this in situations where a context +switch happens as a result of making a ThreadX SMP service call (which is itself a +C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -69,10 +69,10 @@ FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: 0x040 x22 x21 0x048 x23 x22 0x050 x20 x19 - 0x058 x21 x20 - 0x060 x18 x29 - 0x068 x19 x30 - 0x070 x16 + 0x058 x21 x20 + 0x060 x18 x29 + 0x068 x19 x30 + 0x070 x16 0x078 x17 0x080 x14 0x088 x15 @@ -91,7 +91,7 @@ FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: 0x0F0 x0 0x0F8 x1 0x100 x29 - 0x108 x30 + 0x108 x30 FP enabled and TX_THREAD.tx_thread_fp_enable == 1: @@ -140,19 +140,19 @@ FP enabled and TX_THREAD.tx_thread_fp_enable == 1: 0x1F0 q3 0x200 q0 0x210 q1 - 0x220 x28 - 0x228 reserved - 0x230 x26 - 0x238 x27 - 0x240 x24 - 0x248 x25 - 0x250 x22 - 0x258 x23 - 0x260 x20 - 0x268 x21 - 0x270 x18 - 0x278 x19 - 0x280 x16 + 0x220 x28 + 0x228 reserved + 0x230 x26 + 0x238 x27 + 0x240 x24 + 0x248 x25 + 0x250 x22 + 0x258 x23 + 0x260 x20 + 0x268 x21 + 0x270 x18 + 0x278 x19 + 0x280 x16 0x288 x17 0x290 x14 0x298 x15 @@ -171,20 +171,20 @@ FP enabled and TX_THREAD.tx_thread_fp_enable == 1: 0x300 x0 0x308 x1 0x310 x29 - 0x318 x30 + 0x318 x30 5. Improving Performance -The distribution version of ThreadX SMP is built without any compiler optimizations. -This makes it easy to debug because you can trace or set breakpoints inside of -ThreadX SMP itself. Of course, this costs some performance. To make it run faster, +The distribution version of ThreadX SMP is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX SMP itself. Of course, this costs some performance. To make it run faster, you can change the project settings to the desired compiler optimization level. -In addition, you can eliminate the ThreadX SMP basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX SMP basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling @@ -205,22 +205,22 @@ irq_first_handler_aarch64_spX: B _tx_thread_context_restore -By default, ThreadX SMP assumes EL3 level of execution. Running and taking exceptions in EL1 +By default, ThreadX SMP assumes EL3 level of execution. Running and taking exceptions in EL1 and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined. 7. ThreadX SMP Timer Interrupt -ThreadX SMP requires a periodic interrupt source to manage all time-slicing, thread sleeps, -timeouts, and application timers. Without such a timer interrupt source, these services -are not functional. However, all other ThreadX services are operational without a +ThreadX SMP requires a periodic interrupt source to manage all time-slicing, thread sleeps, +timeouts, and application timers. Without such a timer interrupt source, these services +are not functional. However, all other ThreadX services are operational without a periodic timer source. 8. ARM FP Support By default, FP support is disabled for each thread. If saving the context of the FP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the FP usage: void tx_thread_fp_enable(void); diff --git a/ports_smp/cortex_a5x_smp/iar/src/tx_initialize_low_level.S b/ports_smp/cortex_a5x_smp/iar/src/tx_initialize_low_level.S index b0847a19..d3edbc4c 100644 --- a/ports_smp/cortex_a5x_smp/iar/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a5x_smp/iar/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -85,12 +86,6 @@ __tx_free_memory_start /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.9 */ -/* */ /**************************************************************************/ /* VOID _tx_initialize_low_level(VOID) { */ diff --git a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_context_restore.S b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_context_restore.S index 6b25ac5f..aa4aa3a9 100644 --- a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -75,15 +76,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.9 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_context_save.S b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_context_save.S index 5b163bd3..6bae7af7 100644 --- a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,12 +71,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.9 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_context_save(VOID) { */ diff --git a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_fp_disable.c b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_fp_disable.c index ca96cf44..4d8c4ec8 100644 --- a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,12 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_fp_enable.c b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_fp_enable.c index 94f0f44f..7b52a607 100644 --- a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,12 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.9 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_interrupt_control.S index ab89390a..dc19d275 100644 --- a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,12 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.9 */ -/* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_control(UINT new_posture) { */ diff --git a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_interrupt_disable.S index 0a98504d..99c2d527 100644 --- a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.9 */ -/* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_disable(void) { */ diff --git a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_interrupt_restore.S index 8729d01c..f41fdb5c 100644 --- a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,12 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.9 */ -/* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_restore(UINT old_posture) { */ diff --git a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_schedule.S b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_schedule.S index f7022bdd..063f1f12 100644 --- a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -73,12 +74,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.9 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_schedule(VOID) { */ diff --git a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_core_get.S index 016a8545..ed4d7531 100644 --- a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,12 +66,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.9 */ -/* */ /**************************************************************************/ PUBLIC _tx_thread_smp_core_get _tx_thread_smp_core_get: diff --git a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_core_preempt.S index ca2e4e45..e01df964 100644 --- a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,12 +69,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.9 */ -/* */ /**************************************************************************/ PUBLIC _tx_thread_smp_core_preempt _tx_thread_smp_core_preempt: diff --git a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_current_state_get.S index 4e189c00..11f48760 100644 --- a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,12 +69,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.9 */ -/* */ /**************************************************************************/ PUBLIC _tx_thread_smp_current_state_get _tx_thread_smp_current_state_get: diff --git a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_current_thread_get.S index ee019aaa..8af14c72 100644 --- a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,12 +68,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.9 */ -/* */ /**************************************************************************/ PUBLIC _tx_thread_smp_current_thread_get _tx_thread_smp_current_thread_get: diff --git a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_initialize_wait.S index 2f96335e..059b5b4f 100644 --- a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,12 +73,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.9 */ -/* */ /**************************************************************************/ PUBLIC _tx_thread_smp_initialize_wait _tx_thread_smp_initialize_wait: diff --git a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_low_level_initialize.S index 3121661a..13a65416 100644 --- a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,12 +66,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.9 */ -/* */ /**************************************************************************/ PUBLIC _tx_thread_smp_low_level_initialize _tx_thread_smp_low_level_initialize: diff --git a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_protect.S b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_protect.S index 5975b090..ba493358 100644 --- a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -77,15 +78,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.9 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ PUBLIC _tx_thread_smp_protect _tx_thread_smp_protect: @@ -133,9 +125,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_protection_wait_list_macros.h index 59cfebe6..e07cfd31 100644 --- a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_time_get.S index 05a281d7..43834196 100644 --- a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,12 +67,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.9 */ -/* */ /**************************************************************************/ PUBLIC _tx_thread_smp_time_get _tx_thread_smp_time_get: diff --git a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_unprotect.S index dafbbf87..7c8e6c25 100644 --- a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,15 +61,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.9 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* */ /**************************************************************************/ PUBLIC _tx_thread_smp_unprotect _tx_thread_smp_unprotect: diff --git a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_stack_build.S b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_stack_build.S index c0809dd1..ad5c18b1 100644 --- a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,12 +67,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.9 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) { */ diff --git a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_system_return.S b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_system_return.S index 98d9fec8..764a29b9 100644 --- a/ports_smp/cortex_a5x_smp/iar/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a5x_smp/iar/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -73,12 +74,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.9 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_system_return(VOID) { */ diff --git a/ports_smp/cortex_a5x_smp/iar/src/tx_timer_interrupt.S b/ports_smp/cortex_a5x_smp/iar/src/tx_timer_interrupt.S index 2e2589a2..ceb1b285 100644 --- a/ports_smp/cortex_a5x_smp/iar/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a5x_smp/iar/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -79,12 +80,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.9 */ -/* */ /**************************************************************************/ /* VOID _tx_timer_interrupt(VOID) { */ diff --git a/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/.cproject b/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/.cproject index c2ba35b2..22164702 100644 --- a/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/sample_threadx.scat index 1288a328..1ed382ae 100644 --- a/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/sample_threadx.scat @@ -12,13 +12,13 @@ LOAD 0x80000000 { startup.o (StartUp, +FIRST) * (+RO, +RW, +ZI) - + } ;XTABLES +0 ALIGN 0x1000 ;{ - ; xtables.o (*) + ; xtables.o (*) ;} - + SYS_STACK +0 ALIGN 8 EMPTY 0x1000 { } @@ -34,13 +34,13 @@ LOAD 0x80000000 ; All stacks and heap are aligned to a cache-line boundary ; ARM_LIB_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary ; HANDLER_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Stacks for EL3 ; @@ -217,34 +217,34 @@ LOAD 0x80000000 ; { ; *( +RO ) ; } -; +; ; XTABLES +0 ALIGN 0x1000 ; { -; xtables.o (*) +; xtables.o (*) ; } ;} ; ;RW AlignExpr(ImageLimit(XTABLES), 0x1000) -;{ +;{ ; RWSEC +0 ; { ; *( +RW ) ; } -; +; ; ZISEC +0 ; { ; *( +ZI ) ; } -; +; ; SYS_STACK +0 ALIGN 8 EMPTY 0x1000 ; { ; } -; +; ; ; 512 MiB heap ; HEAP +0 ALIGN 8 EMPTY 0x10000000 ; { ; } -; +; ; ; Free Memory section ; FREE_MEMORY +0 ALIGN 8 EMPTY 0x10000000 ; { @@ -254,7 +254,7 @@ LOAD 0x80000000 ; TASK_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { ; } -; +; ; ; Per-CPU 128 MiB handler stacks ; HANDLER_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { diff --git a/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/v8_aarch64.h b/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports_smp/cortex_a65_smp/ac6/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_smp/cortex_a65_smp/ac6/example_build/tx/.cproject b/ports_smp/cortex_a65_smp/ac6/example_build/tx/.cproject index 6366f6ef..5a090cf5 100644 --- a/ports_smp/cortex_a65_smp/ac6/example_build/tx/.cproject +++ b/ports_smp/cortex_a65_smp/ac6/example_build/tx/.cproject @@ -1,188 +1,188 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a65_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a65_smp/ac6/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_smp/cortex_a65_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a65_smp/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a65_smp/ac6/src/tx_initialize_low_level.S b/ports_smp/cortex_a65_smp/ac6/src/tx_initialize_low_level.S index 7d2cfabf..08986f7b 100644 --- a/ports_smp/cortex_a65_smp/ac6/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a65_smp/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_context_restore.S index c16c6dbb..5cd7a9df 100644 --- a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,22 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_context_save.S b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_context_save.S index c8281503..76641067 100644 --- a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_fp_disable.c b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_fp_enable.c b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_schedule.S index 52654783..de6b70dd 100644 --- a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* added memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_core_get.S index 684e317c..ea14c901 100644 --- a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_core_preempt.S index 903a5ab9..1d28907f 100644 --- a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,18 +62,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_current_state_get.S index 67b5b6f5..707b41d2 100644 --- a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_current_thread_get.S index 42d5776c..6c4bc9af 100644 --- a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_initialize_wait.S index f1c067cf..defd791c 100644 --- a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_low_level_initialize.S index 101a91f3..99b20d24 100644 --- a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_protect.S b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_protect.S index d2750b7e..1155a3fa 100644 --- a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,22 +61,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -124,9 +109,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_time_get.S index ee4dd40c..335824fb 100644 --- a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_unprotect.S index ae700d1e..680e8bc8 100644 --- a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,21 +58,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_stack_build.S b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_stack_build.S index 746bbd42..581e259e 100644 --- a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_system_return.S index b889de21..23c75241 100644 --- a/ports_smp/cortex_a65_smp/ac6/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a65_smp/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a65_smp/ac6/src/tx_timer_interrupt.S b/ports_smp/cortex_a65_smp/ac6/src/tx_timer_interrupt.S index bad59269..5c6a6bc2 100644 --- a/ports_smp/cortex_a65_smp/ac6/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a65_smp/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/.cproject b/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/.cproject index 34967225..aab1eeaf 100644 --- a/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/sample_threadx.ld b/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/sample_threadx.ld index e9b12a82..1c6d45b5 100644 --- a/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start @@ -194,7 +194,7 @@ SECTIONS . = . + 4 * 0x8000; __stack = .; } - + .handler_stack_limit (NOLOAD): { . = ALIGN(64); diff --git a/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/v8_aarch64.h b/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports_smp/cortex_a65_smp/gnu/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_smp/cortex_a65_smp/gnu/example_build/tx/.cproject b/ports_smp/cortex_a65_smp/gnu/example_build/tx/.cproject index 3547a1d3..e3f31405 100644 --- a/ports_smp/cortex_a65_smp/gnu/example_build/tx/.cproject +++ b/ports_smp/cortex_a65_smp/gnu/example_build/tx/.cproject @@ -1,200 +1,200 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a65_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a65_smp/gnu/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_smp/cortex_a65_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a65_smp/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a65_smp/gnu/src/tx_initialize_low_level.S b/ports_smp/cortex_a65_smp/gnu/src/tx_initialize_low_level.S index b171fc0f..efb08b80 100644 --- a/ports_smp/cortex_a65_smp/gnu/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a65_smp/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_context_restore.S index c16c6dbb..5cd7a9df 100644 --- a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,22 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_context_save.S b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_context_save.S index c8281503..76641067 100644 --- a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_fp_disable.c b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_fp_enable.c b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_schedule.S index 52654783..de6b70dd 100644 --- a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* added memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_core_get.S index 684e317c..ea14c901 100644 --- a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_core_preempt.S index 903a5ab9..1d28907f 100644 --- a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,18 +62,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_current_state_get.S index 67b5b6f5..707b41d2 100644 --- a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_current_thread_get.S index 42d5776c..6c4bc9af 100644 --- a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_initialize_wait.S index f1c067cf..defd791c 100644 --- a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_low_level_initialize.S index 101a91f3..99b20d24 100644 --- a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_protect.S b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_protect.S index d2750b7e..1155a3fa 100644 --- a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,22 +61,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -124,9 +109,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_time_get.S index ee4dd40c..335824fb 100644 --- a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_unprotect.S index ae700d1e..680e8bc8 100644 --- a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,21 +58,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_stack_build.S b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_stack_build.S index 746bbd42..581e259e 100644 --- a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_system_return.S index b889de21..23c75241 100644 --- a/ports_smp/cortex_a65_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a65_smp/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a65_smp/gnu/src/tx_timer_interrupt.S b/ports_smp/cortex_a65_smp/gnu/src/tx_timer_interrupt.S index bad59269..5c6a6bc2 100644 --- a/ports_smp/cortex_a65_smp/gnu/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a65_smp/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/.cproject b/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/.cproject index 1e79fac9..0386ba1e 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/sample_threadx.scat index 1288a328..1ed382ae 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/sample_threadx.scat @@ -12,13 +12,13 @@ LOAD 0x80000000 { startup.o (StartUp, +FIRST) * (+RO, +RW, +ZI) - + } ;XTABLES +0 ALIGN 0x1000 ;{ - ; xtables.o (*) + ; xtables.o (*) ;} - + SYS_STACK +0 ALIGN 8 EMPTY 0x1000 { } @@ -34,13 +34,13 @@ LOAD 0x80000000 ; All stacks and heap are aligned to a cache-line boundary ; ARM_LIB_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary ; HANDLER_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Stacks for EL3 ; @@ -217,34 +217,34 @@ LOAD 0x80000000 ; { ; *( +RO ) ; } -; +; ; XTABLES +0 ALIGN 0x1000 ; { -; xtables.o (*) +; xtables.o (*) ; } ;} ; ;RW AlignExpr(ImageLimit(XTABLES), 0x1000) -;{ +;{ ; RWSEC +0 ; { ; *( +RW ) ; } -; +; ; ZISEC +0 ; { ; *( +ZI ) ; } -; +; ; SYS_STACK +0 ALIGN 8 EMPTY 0x1000 ; { ; } -; +; ; ; 512 MiB heap ; HEAP +0 ALIGN 8 EMPTY 0x10000000 ; { ; } -; +; ; ; Free Memory section ; FREE_MEMORY +0 ALIGN 8 EMPTY 0x10000000 ; { @@ -254,7 +254,7 @@ LOAD 0x80000000 ; TASK_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { ; } -; +; ; ; Per-CPU 128 MiB handler stacks ; HANDLER_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { diff --git a/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/v8_aarch64.h b/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports_smp/cortex_a65ae_smp/ac6/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_smp/cortex_a65ae_smp/ac6/example_build/tx/.cproject b/ports_smp/cortex_a65ae_smp/ac6/example_build/tx/.cproject index 3d4f1d81..15137e53 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/example_build/tx/.cproject +++ b/ports_smp/cortex_a65ae_smp/ac6/example_build/tx/.cproject @@ -1,188 +1,188 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a65ae_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a65ae_smp/ac6/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a65ae_smp/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a65ae_smp/ac6/src/tx_initialize_low_level.S b/ports_smp/cortex_a65ae_smp/ac6/src/tx_initialize_low_level.S index 7d2cfabf..08986f7b 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a65ae_smp/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_context_restore.S index c16c6dbb..5cd7a9df 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,22 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_context_save.S b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_context_save.S index c8281503..76641067 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_fp_disable.c b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_fp_enable.c b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_schedule.S index 52654783..de6b70dd 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* added memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_core_get.S index 684e317c..ea14c901 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_core_preempt.S index 903a5ab9..1d28907f 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,18 +62,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_current_state_get.S index 67b5b6f5..707b41d2 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_current_thread_get.S index 42d5776c..6c4bc9af 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_initialize_wait.S index f1c067cf..defd791c 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_low_level_initialize.S index 101a91f3..99b20d24 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_protect.S b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_protect.S index d2750b7e..1155a3fa 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,22 +61,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -124,9 +109,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_time_get.S index ee4dd40c..335824fb 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_unprotect.S index ae700d1e..680e8bc8 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,21 +58,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_stack_build.S b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_stack_build.S index 746bbd42..581e259e 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_system_return.S index b889de21..23c75241 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a65ae_smp/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a65ae_smp/ac6/src/tx_timer_interrupt.S b/ports_smp/cortex_a65ae_smp/ac6/src/tx_timer_interrupt.S index bad59269..5c6a6bc2 100644 --- a/ports_smp/cortex_a65ae_smp/ac6/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a65ae_smp/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/.cproject b/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/.cproject index 34967225..aab1eeaf 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/sample_threadx.ld b/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/sample_threadx.ld index e9b12a82..1c6d45b5 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start @@ -194,7 +194,7 @@ SECTIONS . = . + 4 * 0x8000; __stack = .; } - + .handler_stack_limit (NOLOAD): { . = ALIGN(64); diff --git a/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/v8_aarch64.h b/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports_smp/cortex_a65ae_smp/gnu/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_smp/cortex_a65ae_smp/gnu/example_build/tx/.cproject b/ports_smp/cortex_a65ae_smp/gnu/example_build/tx/.cproject index 3547a1d3..e3f31405 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/example_build/tx/.cproject +++ b/ports_smp/cortex_a65ae_smp/gnu/example_build/tx/.cproject @@ -1,200 +1,200 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a65ae_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a65ae_smp/gnu/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a65ae_smp/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a65ae_smp/gnu/src/tx_initialize_low_level.S b/ports_smp/cortex_a65ae_smp/gnu/src/tx_initialize_low_level.S index b171fc0f..efb08b80 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a65ae_smp/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_context_restore.S index c16c6dbb..5cd7a9df 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,22 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_context_save.S b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_context_save.S index c8281503..76641067 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_fp_disable.c b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_fp_enable.c b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_schedule.S index 52654783..de6b70dd 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* added memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_core_get.S index 684e317c..ea14c901 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_core_preempt.S index 903a5ab9..1d28907f 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,18 +62,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_current_state_get.S index 67b5b6f5..707b41d2 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_current_thread_get.S index 42d5776c..6c4bc9af 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_initialize_wait.S index f1c067cf..defd791c 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_low_level_initialize.S index 101a91f3..99b20d24 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_protect.S b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_protect.S index d2750b7e..1155a3fa 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,22 +61,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -124,9 +109,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_time_get.S index ee4dd40c..335824fb 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_unprotect.S index ae700d1e..680e8bc8 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,21 +58,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_stack_build.S b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_stack_build.S index 746bbd42..581e259e 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_system_return.S index b889de21..23c75241 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a65ae_smp/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a65ae_smp/gnu/src/tx_timer_interrupt.S b/ports_smp/cortex_a65ae_smp/gnu/src/tx_timer_interrupt.S index bad59269..5c6a6bc2 100644 --- a/ports_smp/cortex_a65ae_smp/gnu/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a65ae_smp/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/.cproject b/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/.cproject index baabb349..3d4747d7 100644 --- a/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/sample_threadx.scat index 1288a328..1ed382ae 100644 --- a/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/sample_threadx.scat @@ -12,13 +12,13 @@ LOAD 0x80000000 { startup.o (StartUp, +FIRST) * (+RO, +RW, +ZI) - + } ;XTABLES +0 ALIGN 0x1000 ;{ - ; xtables.o (*) + ; xtables.o (*) ;} - + SYS_STACK +0 ALIGN 8 EMPTY 0x1000 { } @@ -34,13 +34,13 @@ LOAD 0x80000000 ; All stacks and heap are aligned to a cache-line boundary ; ARM_LIB_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary ; HANDLER_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Stacks for EL3 ; @@ -217,34 +217,34 @@ LOAD 0x80000000 ; { ; *( +RO ) ; } -; +; ; XTABLES +0 ALIGN 0x1000 ; { -; xtables.o (*) +; xtables.o (*) ; } ;} ; ;RW AlignExpr(ImageLimit(XTABLES), 0x1000) -;{ +;{ ; RWSEC +0 ; { ; *( +RW ) ; } -; +; ; ZISEC +0 ; { ; *( +ZI ) ; } -; +; ; SYS_STACK +0 ALIGN 8 EMPTY 0x1000 ; { ; } -; +; ; ; 512 MiB heap ; HEAP +0 ALIGN 8 EMPTY 0x10000000 ; { ; } -; +; ; ; Free Memory section ; FREE_MEMORY +0 ALIGN 8 EMPTY 0x10000000 ; { @@ -254,7 +254,7 @@ LOAD 0x80000000 ; TASK_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { ; } -; +; ; ; Per-CPU 128 MiB handler stacks ; HANDLER_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { diff --git a/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/v8_aarch64.h b/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports_smp/cortex_a72_smp/ac6/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_smp/cortex_a72_smp/ac6/example_build/tx/.cproject b/ports_smp/cortex_a72_smp/ac6/example_build/tx/.cproject index 421e868e..436c1c0f 100644 --- a/ports_smp/cortex_a72_smp/ac6/example_build/tx/.cproject +++ b/ports_smp/cortex_a72_smp/ac6/example_build/tx/.cproject @@ -1,188 +1,188 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a72_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a72_smp/ac6/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_smp/cortex_a72_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a72_smp/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a72_smp/ac6/src/tx_initialize_low_level.S b/ports_smp/cortex_a72_smp/ac6/src/tx_initialize_low_level.S index 7d2cfabf..08986f7b 100644 --- a/ports_smp/cortex_a72_smp/ac6/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a72_smp/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_context_restore.S index c16c6dbb..5cd7a9df 100644 --- a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,22 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_context_save.S b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_context_save.S index c8281503..76641067 100644 --- a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_fp_disable.c b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_fp_enable.c b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_schedule.S index 52654783..de6b70dd 100644 --- a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* added memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_core_get.S index 684e317c..ea14c901 100644 --- a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_core_preempt.S index 903a5ab9..1d28907f 100644 --- a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,18 +62,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_current_state_get.S index 67b5b6f5..707b41d2 100644 --- a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_current_thread_get.S index 42d5776c..6c4bc9af 100644 --- a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_initialize_wait.S index f1c067cf..defd791c 100644 --- a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_low_level_initialize.S index 101a91f3..99b20d24 100644 --- a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_protect.S b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_protect.S index d2750b7e..1155a3fa 100644 --- a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,22 +61,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -124,9 +109,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_time_get.S index ee4dd40c..335824fb 100644 --- a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_unprotect.S index ae700d1e..680e8bc8 100644 --- a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,21 +58,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_stack_build.S b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_stack_build.S index 746bbd42..581e259e 100644 --- a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_system_return.S index b889de21..23c75241 100644 --- a/ports_smp/cortex_a72_smp/ac6/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a72_smp/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a72_smp/ac6/src/tx_timer_interrupt.S b/ports_smp/cortex_a72_smp/ac6/src/tx_timer_interrupt.S index bad59269..5c6a6bc2 100644 --- a/ports_smp/cortex_a72_smp/ac6/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a72_smp/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a72_smp/gnu/example_build/sample_threadx/.cproject b/ports_smp/cortex_a72_smp/gnu/example_build/sample_threadx/.cproject index 34967225..aab1eeaf 100644 --- a/ports_smp/cortex_a72_smp/gnu/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a72_smp/gnu/example_build/sample_threadx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a72_smp/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a72_smp/gnu/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_smp/cortex_a72_smp/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_smp/cortex_a72_smp/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_smp/cortex_a72_smp/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a72_smp/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_smp/cortex_a72_smp/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a72_smp/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_smp/cortex_a72_smp/gnu/example_build/sample_threadx/sample_threadx.ld b/ports_smp/cortex_a72_smp/gnu/example_build/sample_threadx/sample_threadx.ld index e9b12a82..1c6d45b5 100644 --- a/ports_smp/cortex_a72_smp/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports_smp/cortex_a72_smp/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start @@ -194,7 +194,7 @@ SECTIONS . = . + 4 * 0x8000; __stack = .; } - + .handler_stack_limit (NOLOAD): { . = ALIGN(64); diff --git a/ports_smp/cortex_a72_smp/gnu/example_build/sample_threadx/v8_aarch64.h b/ports_smp/cortex_a72_smp/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_smp/cortex_a72_smp/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports_smp/cortex_a72_smp/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_smp/cortex_a72_smp/gnu/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a72_smp/gnu/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_smp/cortex_a72_smp/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports_smp/cortex_a72_smp/gnu/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_smp/cortex_a72_smp/gnu/example_build/tx/.cproject b/ports_smp/cortex_a72_smp/gnu/example_build/tx/.cproject index 3547a1d3..e3f31405 100644 --- a/ports_smp/cortex_a72_smp/gnu/example_build/tx/.cproject +++ b/ports_smp/cortex_a72_smp/gnu/example_build/tx/.cproject @@ -1,200 +1,200 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a72_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a72_smp/gnu/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_smp/cortex_a72_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a72_smp/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a72_smp/gnu/src/tx_initialize_low_level.S b/ports_smp/cortex_a72_smp/gnu/src/tx_initialize_low_level.S index b171fc0f..efb08b80 100644 --- a/ports_smp/cortex_a72_smp/gnu/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a72_smp/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_context_restore.S index c16c6dbb..5cd7a9df 100644 --- a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,22 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_context_save.S b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_context_save.S index c8281503..76641067 100644 --- a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_fp_disable.c b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_fp_enable.c b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_schedule.S index 52654783..de6b70dd 100644 --- a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* added memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_core_get.S index 684e317c..ea14c901 100644 --- a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_core_preempt.S index 903a5ab9..1d28907f 100644 --- a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,18 +62,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_current_state_get.S index 67b5b6f5..707b41d2 100644 --- a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_current_thread_get.S index 42d5776c..6c4bc9af 100644 --- a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_initialize_wait.S index f1c067cf..defd791c 100644 --- a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_low_level_initialize.S index 101a91f3..99b20d24 100644 --- a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_protect.S b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_protect.S index d2750b7e..1155a3fa 100644 --- a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,22 +61,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -124,9 +109,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_time_get.S index ee4dd40c..335824fb 100644 --- a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_unprotect.S index ae700d1e..680e8bc8 100644 --- a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,21 +58,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_stack_build.S b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_stack_build.S index 746bbd42..581e259e 100644 --- a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_system_return.S index b889de21..23c75241 100644 --- a/ports_smp/cortex_a72_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a72_smp/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a72_smp/gnu/src/tx_timer_interrupt.S b/ports_smp/cortex_a72_smp/gnu/src/tx_timer_interrupt.S index bad59269..5c6a6bc2 100644 --- a/ports_smp/cortex_a72_smp/gnu/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a72_smp/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/.cproject b/ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/.cproject index fa6c026d..715a8f0e 100644 --- a/ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/sample_threadx.scat index 1288a328..1ed382ae 100644 --- a/ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/sample_threadx.scat @@ -12,13 +12,13 @@ LOAD 0x80000000 { startup.o (StartUp, +FIRST) * (+RO, +RW, +ZI) - + } ;XTABLES +0 ALIGN 0x1000 ;{ - ; xtables.o (*) + ; xtables.o (*) ;} - + SYS_STACK +0 ALIGN 8 EMPTY 0x1000 { } @@ -34,13 +34,13 @@ LOAD 0x80000000 ; All stacks and heap are aligned to a cache-line boundary ; ARM_LIB_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary ; HANDLER_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Stacks for EL3 ; @@ -217,34 +217,34 @@ LOAD 0x80000000 ; { ; *( +RO ) ; } -; +; ; XTABLES +0 ALIGN 0x1000 ; { -; xtables.o (*) +; xtables.o (*) ; } ;} ; ;RW AlignExpr(ImageLimit(XTABLES), 0x1000) -;{ +;{ ; RWSEC +0 ; { ; *( +RW ) ; } -; +; ; ZISEC +0 ; { ; *( +ZI ) ; } -; +; ; SYS_STACK +0 ALIGN 8 EMPTY 0x1000 ; { ; } -; +; ; ; 512 MiB heap ; HEAP +0 ALIGN 8 EMPTY 0x10000000 ; { ; } -; +; ; ; Free Memory section ; FREE_MEMORY +0 ALIGN 8 EMPTY 0x10000000 ; { @@ -254,7 +254,7 @@ LOAD 0x80000000 ; TASK_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { ; } -; +; ; ; Per-CPU 128 MiB handler stacks ; HANDLER_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { diff --git a/ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/v8_aarch64.h b/ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports_smp/cortex_a73_smp/ac6/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_smp/cortex_a73_smp/ac6/example_build/tx/.cproject b/ports_smp/cortex_a73_smp/ac6/example_build/tx/.cproject index ba299fce..492c3136 100644 --- a/ports_smp/cortex_a73_smp/ac6/example_build/tx/.cproject +++ b/ports_smp/cortex_a73_smp/ac6/example_build/tx/.cproject @@ -1,188 +1,188 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a73_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a73_smp/ac6/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_smp/cortex_a73_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a73_smp/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a73_smp/ac6/src/tx_initialize_low_level.S b/ports_smp/cortex_a73_smp/ac6/src/tx_initialize_low_level.S index 7d2cfabf..08986f7b 100644 --- a/ports_smp/cortex_a73_smp/ac6/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a73_smp/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_context_restore.S index c16c6dbb..5cd7a9df 100644 --- a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,22 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_context_save.S b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_context_save.S index c8281503..76641067 100644 --- a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_fp_disable.c b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_fp_enable.c b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_schedule.S index 52654783..de6b70dd 100644 --- a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* added memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_core_get.S index 684e317c..ea14c901 100644 --- a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_core_preempt.S index 903a5ab9..1d28907f 100644 --- a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,18 +62,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_current_state_get.S index 67b5b6f5..707b41d2 100644 --- a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_current_thread_get.S index 42d5776c..6c4bc9af 100644 --- a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_initialize_wait.S index f1c067cf..defd791c 100644 --- a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_low_level_initialize.S index 101a91f3..99b20d24 100644 --- a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_protect.S b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_protect.S index d2750b7e..1155a3fa 100644 --- a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,22 +61,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -124,9 +109,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_time_get.S index ee4dd40c..335824fb 100644 --- a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_unprotect.S index ae700d1e..680e8bc8 100644 --- a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,21 +58,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_stack_build.S b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_stack_build.S index 746bbd42..581e259e 100644 --- a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_system_return.S index b889de21..23c75241 100644 --- a/ports_smp/cortex_a73_smp/ac6/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a73_smp/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a73_smp/ac6/src/tx_timer_interrupt.S b/ports_smp/cortex_a73_smp/ac6/src/tx_timer_interrupt.S index bad59269..5c6a6bc2 100644 --- a/ports_smp/cortex_a73_smp/ac6/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a73_smp/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/.cproject b/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/.cproject index 34967225..aab1eeaf 100644 --- a/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/sample_threadx.ld b/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/sample_threadx.ld index e9b12a82..1c6d45b5 100644 --- a/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start @@ -194,7 +194,7 @@ SECTIONS . = . + 4 * 0x8000; __stack = .; } - + .handler_stack_limit (NOLOAD): { . = ALIGN(64); diff --git a/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/v8_aarch64.h b/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports_smp/cortex_a73_smp/gnu/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_smp/cortex_a73_smp/gnu/example_build/tx/.cproject b/ports_smp/cortex_a73_smp/gnu/example_build/tx/.cproject index 3547a1d3..e3f31405 100644 --- a/ports_smp/cortex_a73_smp/gnu/example_build/tx/.cproject +++ b/ports_smp/cortex_a73_smp/gnu/example_build/tx/.cproject @@ -1,200 +1,200 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a73_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a73_smp/gnu/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_smp/cortex_a73_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a73_smp/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a73_smp/gnu/src/tx_initialize_low_level.S b/ports_smp/cortex_a73_smp/gnu/src/tx_initialize_low_level.S index b171fc0f..efb08b80 100644 --- a/ports_smp/cortex_a73_smp/gnu/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a73_smp/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_context_restore.S index c16c6dbb..5cd7a9df 100644 --- a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,22 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_context_save.S b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_context_save.S index c8281503..76641067 100644 --- a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_fp_disable.c b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_fp_enable.c b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_schedule.S index 52654783..de6b70dd 100644 --- a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* added memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_core_get.S index 684e317c..ea14c901 100644 --- a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_core_preempt.S index 903a5ab9..1d28907f 100644 --- a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,18 +62,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_current_state_get.S index 67b5b6f5..707b41d2 100644 --- a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_current_thread_get.S index 42d5776c..6c4bc9af 100644 --- a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_initialize_wait.S index f1c067cf..defd791c 100644 --- a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_low_level_initialize.S index 101a91f3..99b20d24 100644 --- a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_protect.S b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_protect.S index d2750b7e..1155a3fa 100644 --- a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,22 +61,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -124,9 +109,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_time_get.S index ee4dd40c..335824fb 100644 --- a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_unprotect.S index ae700d1e..680e8bc8 100644 --- a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,21 +58,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_stack_build.S b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_stack_build.S index 746bbd42..581e259e 100644 --- a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_system_return.S index b889de21..23c75241 100644 --- a/ports_smp/cortex_a73_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a73_smp/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a73_smp/gnu/src/tx_timer_interrupt.S b/ports_smp/cortex_a73_smp/gnu/src/tx_timer_interrupt.S index bad59269..5c6a6bc2 100644 --- a/ports_smp/cortex_a73_smp/gnu/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a73_smp/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/.cproject b/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/.cproject index d28cd933..db67b393 100644 --- a/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/sample_threadx.scat index 1288a328..1ed382ae 100644 --- a/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/sample_threadx.scat @@ -12,13 +12,13 @@ LOAD 0x80000000 { startup.o (StartUp, +FIRST) * (+RO, +RW, +ZI) - + } ;XTABLES +0 ALIGN 0x1000 ;{ - ; xtables.o (*) + ; xtables.o (*) ;} - + SYS_STACK +0 ALIGN 8 EMPTY 0x1000 { } @@ -34,13 +34,13 @@ LOAD 0x80000000 ; All stacks and heap are aligned to a cache-line boundary ; ARM_LIB_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary ; HANDLER_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Stacks for EL3 ; @@ -217,34 +217,34 @@ LOAD 0x80000000 ; { ; *( +RO ) ; } -; +; ; XTABLES +0 ALIGN 0x1000 ; { -; xtables.o (*) +; xtables.o (*) ; } ;} ; ;RW AlignExpr(ImageLimit(XTABLES), 0x1000) -;{ +;{ ; RWSEC +0 ; { ; *( +RW ) ; } -; +; ; ZISEC +0 ; { ; *( +ZI ) ; } -; +; ; SYS_STACK +0 ALIGN 8 EMPTY 0x1000 ; { ; } -; +; ; ; 512 MiB heap ; HEAP +0 ALIGN 8 EMPTY 0x10000000 ; { ; } -; +; ; ; Free Memory section ; FREE_MEMORY +0 ALIGN 8 EMPTY 0x10000000 ; { @@ -254,7 +254,7 @@ LOAD 0x80000000 ; TASK_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { ; } -; +; ; ; Per-CPU 128 MiB handler stacks ; HANDLER_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { diff --git a/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/v8_aarch64.h b/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports_smp/cortex_a75_smp/ac6/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_smp/cortex_a75_smp/ac6/example_build/tx/.cproject b/ports_smp/cortex_a75_smp/ac6/example_build/tx/.cproject index 9af84557..5681abf0 100644 --- a/ports_smp/cortex_a75_smp/ac6/example_build/tx/.cproject +++ b/ports_smp/cortex_a75_smp/ac6/example_build/tx/.cproject @@ -1,188 +1,188 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a75_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a75_smp/ac6/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_smp/cortex_a75_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a75_smp/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a75_smp/ac6/src/tx_initialize_low_level.S b/ports_smp/cortex_a75_smp/ac6/src/tx_initialize_low_level.S index 7d2cfabf..08986f7b 100644 --- a/ports_smp/cortex_a75_smp/ac6/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a75_smp/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_context_restore.S index c16c6dbb..5cd7a9df 100644 --- a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,22 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_context_save.S b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_context_save.S index c8281503..76641067 100644 --- a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_fp_disable.c b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_fp_enable.c b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_schedule.S index 52654783..de6b70dd 100644 --- a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* added memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_core_get.S index 684e317c..ea14c901 100644 --- a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_core_preempt.S index 903a5ab9..1d28907f 100644 --- a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,18 +62,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_current_state_get.S index 67b5b6f5..707b41d2 100644 --- a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_current_thread_get.S index 42d5776c..6c4bc9af 100644 --- a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_initialize_wait.S index f1c067cf..defd791c 100644 --- a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_low_level_initialize.S index 101a91f3..99b20d24 100644 --- a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_protect.S b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_protect.S index d2750b7e..1155a3fa 100644 --- a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,22 +61,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -124,9 +109,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_time_get.S index ee4dd40c..335824fb 100644 --- a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_unprotect.S index ae700d1e..680e8bc8 100644 --- a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,21 +58,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_stack_build.S b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_stack_build.S index 746bbd42..581e259e 100644 --- a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_system_return.S index b889de21..23c75241 100644 --- a/ports_smp/cortex_a75_smp/ac6/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a75_smp/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a75_smp/ac6/src/tx_timer_interrupt.S b/ports_smp/cortex_a75_smp/ac6/src/tx_timer_interrupt.S index bad59269..5c6a6bc2 100644 --- a/ports_smp/cortex_a75_smp/ac6/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a75_smp/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/.cproject b/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/.cproject index 34967225..aab1eeaf 100644 --- a/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/sample_threadx.ld b/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/sample_threadx.ld index e9b12a82..1c6d45b5 100644 --- a/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start @@ -194,7 +194,7 @@ SECTIONS . = . + 4 * 0x8000; __stack = .; } - + .handler_stack_limit (NOLOAD): { . = ALIGN(64); diff --git a/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/v8_aarch64.h b/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports_smp/cortex_a75_smp/gnu/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_smp/cortex_a75_smp/gnu/example_build/tx/.cproject b/ports_smp/cortex_a75_smp/gnu/example_build/tx/.cproject index 3547a1d3..e3f31405 100644 --- a/ports_smp/cortex_a75_smp/gnu/example_build/tx/.cproject +++ b/ports_smp/cortex_a75_smp/gnu/example_build/tx/.cproject @@ -1,200 +1,200 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a75_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a75_smp/gnu/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_smp/cortex_a75_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a75_smp/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a75_smp/gnu/src/tx_initialize_low_level.S b/ports_smp/cortex_a75_smp/gnu/src/tx_initialize_low_level.S index b171fc0f..efb08b80 100644 --- a/ports_smp/cortex_a75_smp/gnu/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a75_smp/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_context_restore.S index c16c6dbb..5cd7a9df 100644 --- a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,22 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_context_save.S b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_context_save.S index c8281503..76641067 100644 --- a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_fp_disable.c b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_fp_enable.c b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_schedule.S index 52654783..de6b70dd 100644 --- a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* added memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_core_get.S index 684e317c..ea14c901 100644 --- a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_core_preempt.S index 903a5ab9..1d28907f 100644 --- a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,18 +62,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_current_state_get.S index 67b5b6f5..707b41d2 100644 --- a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_current_thread_get.S index 42d5776c..6c4bc9af 100644 --- a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_initialize_wait.S index f1c067cf..defd791c 100644 --- a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_low_level_initialize.S index 101a91f3..99b20d24 100644 --- a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_protect.S b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_protect.S index d2750b7e..1155a3fa 100644 --- a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,22 +61,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -124,9 +109,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_time_get.S index ee4dd40c..335824fb 100644 --- a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_unprotect.S index ae700d1e..680e8bc8 100644 --- a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,21 +58,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_stack_build.S b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_stack_build.S index 746bbd42..581e259e 100644 --- a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_system_return.S index b889de21..23c75241 100644 --- a/ports_smp/cortex_a75_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a75_smp/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a75_smp/gnu/src/tx_timer_interrupt.S b/ports_smp/cortex_a75_smp/gnu/src/tx_timer_interrupt.S index bad59269..5c6a6bc2 100644 --- a/ports_smp/cortex_a75_smp/gnu/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a75_smp/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/.cproject b/ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/.cproject index d30613f5..24b25016 100644 --- a/ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/sample_threadx.scat index 1288a328..1ed382ae 100644 --- a/ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/sample_threadx.scat @@ -12,13 +12,13 @@ LOAD 0x80000000 { startup.o (StartUp, +FIRST) * (+RO, +RW, +ZI) - + } ;XTABLES +0 ALIGN 0x1000 ;{ - ; xtables.o (*) + ; xtables.o (*) ;} - + SYS_STACK +0 ALIGN 8 EMPTY 0x1000 { } @@ -34,13 +34,13 @@ LOAD 0x80000000 ; All stacks and heap are aligned to a cache-line boundary ; ARM_LIB_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary ; HANDLER_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Stacks for EL3 ; @@ -217,34 +217,34 @@ LOAD 0x80000000 ; { ; *( +RO ) ; } -; +; ; XTABLES +0 ALIGN 0x1000 ; { -; xtables.o (*) +; xtables.o (*) ; } ;} ; ;RW AlignExpr(ImageLimit(XTABLES), 0x1000) -;{ +;{ ; RWSEC +0 ; { ; *( +RW ) ; } -; +; ; ZISEC +0 ; { ; *( +ZI ) ; } -; +; ; SYS_STACK +0 ALIGN 8 EMPTY 0x1000 ; { ; } -; +; ; ; 512 MiB heap ; HEAP +0 ALIGN 8 EMPTY 0x10000000 ; { ; } -; +; ; ; Free Memory section ; FREE_MEMORY +0 ALIGN 8 EMPTY 0x10000000 ; { @@ -254,7 +254,7 @@ LOAD 0x80000000 ; TASK_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { ; } -; +; ; ; Per-CPU 128 MiB handler stacks ; HANDLER_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { diff --git a/ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/v8_aarch64.h b/ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports_smp/cortex_a76_smp/ac6/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_smp/cortex_a76_smp/ac6/example_build/tx/.cproject b/ports_smp/cortex_a76_smp/ac6/example_build/tx/.cproject index eb52f21e..0cae9e6a 100644 --- a/ports_smp/cortex_a76_smp/ac6/example_build/tx/.cproject +++ b/ports_smp/cortex_a76_smp/ac6/example_build/tx/.cproject @@ -1,188 +1,188 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a76_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a76_smp/ac6/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_smp/cortex_a76_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a76_smp/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a76_smp/ac6/src/tx_initialize_low_level.S b/ports_smp/cortex_a76_smp/ac6/src/tx_initialize_low_level.S index 7d2cfabf..08986f7b 100644 --- a/ports_smp/cortex_a76_smp/ac6/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a76_smp/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_context_restore.S index c16c6dbb..5cd7a9df 100644 --- a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,22 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_context_save.S b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_context_save.S index c8281503..76641067 100644 --- a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_fp_disable.c b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_fp_enable.c b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_schedule.S index 52654783..de6b70dd 100644 --- a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* added memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_core_get.S index 684e317c..ea14c901 100644 --- a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_core_preempt.S index 903a5ab9..1d28907f 100644 --- a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,18 +62,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_current_state_get.S index 67b5b6f5..707b41d2 100644 --- a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_current_thread_get.S index 42d5776c..6c4bc9af 100644 --- a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_initialize_wait.S index f1c067cf..defd791c 100644 --- a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_low_level_initialize.S index 101a91f3..99b20d24 100644 --- a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_protect.S b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_protect.S index d2750b7e..1155a3fa 100644 --- a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,22 +61,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -124,9 +109,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_time_get.S index ee4dd40c..335824fb 100644 --- a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_unprotect.S index ae700d1e..680e8bc8 100644 --- a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,21 +58,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_stack_build.S b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_stack_build.S index 746bbd42..581e259e 100644 --- a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_system_return.S index b889de21..23c75241 100644 --- a/ports_smp/cortex_a76_smp/ac6/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a76_smp/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a76_smp/ac6/src/tx_timer_interrupt.S b/ports_smp/cortex_a76_smp/ac6/src/tx_timer_interrupt.S index bad59269..5c6a6bc2 100644 --- a/ports_smp/cortex_a76_smp/ac6/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a76_smp/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/.cproject b/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/.cproject index 34967225..aab1eeaf 100644 --- a/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/sample_threadx.ld b/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/sample_threadx.ld index e9b12a82..1c6d45b5 100644 --- a/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start @@ -194,7 +194,7 @@ SECTIONS . = . + 4 * 0x8000; __stack = .; } - + .handler_stack_limit (NOLOAD): { . = ALIGN(64); diff --git a/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/v8_aarch64.h b/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports_smp/cortex_a76_smp/gnu/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_smp/cortex_a76_smp/gnu/example_build/tx/.cproject b/ports_smp/cortex_a76_smp/gnu/example_build/tx/.cproject index 3547a1d3..e3f31405 100644 --- a/ports_smp/cortex_a76_smp/gnu/example_build/tx/.cproject +++ b/ports_smp/cortex_a76_smp/gnu/example_build/tx/.cproject @@ -1,200 +1,200 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a76_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a76_smp/gnu/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_smp/cortex_a76_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a76_smp/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a76_smp/gnu/src/tx_initialize_low_level.S b/ports_smp/cortex_a76_smp/gnu/src/tx_initialize_low_level.S index b171fc0f..efb08b80 100644 --- a/ports_smp/cortex_a76_smp/gnu/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a76_smp/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_context_restore.S index c16c6dbb..5cd7a9df 100644 --- a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,22 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_context_save.S b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_context_save.S index c8281503..76641067 100644 --- a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_fp_disable.c b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_fp_enable.c b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_schedule.S index 52654783..de6b70dd 100644 --- a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* added memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_core_get.S index 684e317c..ea14c901 100644 --- a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_core_preempt.S index 903a5ab9..1d28907f 100644 --- a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,18 +62,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_current_state_get.S index 67b5b6f5..707b41d2 100644 --- a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_current_thread_get.S index 42d5776c..6c4bc9af 100644 --- a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_initialize_wait.S index f1c067cf..defd791c 100644 --- a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_low_level_initialize.S index 101a91f3..99b20d24 100644 --- a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_protect.S b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_protect.S index d2750b7e..1155a3fa 100644 --- a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,22 +61,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -124,9 +109,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_time_get.S index ee4dd40c..335824fb 100644 --- a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_unprotect.S index ae700d1e..680e8bc8 100644 --- a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,21 +58,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_stack_build.S b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_stack_build.S index 746bbd42..581e259e 100644 --- a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_system_return.S index b889de21..23c75241 100644 --- a/ports_smp/cortex_a76_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a76_smp/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a76_smp/gnu/src/tx_timer_interrupt.S b/ports_smp/cortex_a76_smp/gnu/src/tx_timer_interrupt.S index bad59269..5c6a6bc2 100644 --- a/ports_smp/cortex_a76_smp/gnu/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a76_smp/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a76ae_smp/ac6/example_build/sample_threadx/.cproject b/ports_smp/cortex_a76ae_smp/ac6/example_build/sample_threadx/.cproject index 16f9cb2d..5aa5d385 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a76ae_smp/ac6/example_build/sample_threadx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a76ae_smp/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a76ae_smp/ac6/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_smp/cortex_a76ae_smp/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_smp/cortex_a76ae_smp/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a76ae_smp/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a76ae_smp/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_smp/cortex_a76ae_smp/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_smp/cortex_a76ae_smp/ac6/example_build/sample_threadx/sample_threadx.scat index 1288a328..1ed382ae 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_smp/cortex_a76ae_smp/ac6/example_build/sample_threadx/sample_threadx.scat @@ -12,13 +12,13 @@ LOAD 0x80000000 { startup.o (StartUp, +FIRST) * (+RO, +RW, +ZI) - + } ;XTABLES +0 ALIGN 0x1000 ;{ - ; xtables.o (*) + ; xtables.o (*) ;} - + SYS_STACK +0 ALIGN 8 EMPTY 0x1000 { } @@ -34,13 +34,13 @@ LOAD 0x80000000 ; All stacks and heap are aligned to a cache-line boundary ; ARM_LIB_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary ; HANDLER_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Stacks for EL3 ; @@ -217,34 +217,34 @@ LOAD 0x80000000 ; { ; *( +RO ) ; } -; +; ; XTABLES +0 ALIGN 0x1000 ; { -; xtables.o (*) +; xtables.o (*) ; } ;} ; ;RW AlignExpr(ImageLimit(XTABLES), 0x1000) -;{ +;{ ; RWSEC +0 ; { ; *( +RW ) ; } -; +; ; ZISEC +0 ; { ; *( +ZI ) ; } -; +; ; SYS_STACK +0 ALIGN 8 EMPTY 0x1000 ; { ; } -; +; ; ; 512 MiB heap ; HEAP +0 ALIGN 8 EMPTY 0x10000000 ; { ; } -; +; ; ; Free Memory section ; FREE_MEMORY +0 ALIGN 8 EMPTY 0x10000000 ; { @@ -254,7 +254,7 @@ LOAD 0x80000000 ; TASK_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { ; } -; +; ; ; Per-CPU 128 MiB handler stacks ; HANDLER_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { diff --git a/ports_smp/cortex_a76ae_smp/ac6/example_build/sample_threadx/v8_aarch64.h b/ports_smp/cortex_a76ae_smp/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports_smp/cortex_a76ae_smp/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_smp/cortex_a76ae_smp/ac6/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a76ae_smp/ac6/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports_smp/cortex_a76ae_smp/ac6/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_smp/cortex_a76ae_smp/ac6/example_build/tx/.cproject b/ports_smp/cortex_a76ae_smp/ac6/example_build/tx/.cproject index 7286a2e2..91b62675 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/example_build/tx/.cproject +++ b/ports_smp/cortex_a76ae_smp/ac6/example_build/tx/.cproject @@ -1,188 +1,188 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a76ae_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a76ae_smp/ac6/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a76ae_smp/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a76ae_smp/ac6/src/tx_initialize_low_level.S b/ports_smp/cortex_a76ae_smp/ac6/src/tx_initialize_low_level.S index 7d2cfabf..08986f7b 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a76ae_smp/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_context_restore.S index c16c6dbb..5cd7a9df 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,22 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_context_save.S b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_context_save.S index c8281503..76641067 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_fp_disable.c b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_fp_enable.c b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_schedule.S index 52654783..de6b70dd 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* added memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_core_get.S index 684e317c..ea14c901 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_core_preempt.S index 903a5ab9..1d28907f 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,18 +62,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_current_state_get.S index 67b5b6f5..707b41d2 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_current_thread_get.S index 42d5776c..6c4bc9af 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_initialize_wait.S index f1c067cf..defd791c 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_low_level_initialize.S index 101a91f3..99b20d24 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_protect.S b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_protect.S index d2750b7e..1155a3fa 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,22 +61,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -124,9 +109,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_time_get.S index ee4dd40c..335824fb 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_unprotect.S index ae700d1e..680e8bc8 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,21 +58,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_stack_build.S b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_stack_build.S index 746bbd42..581e259e 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_system_return.S index b889de21..23c75241 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a76ae_smp/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a76ae_smp/ac6/src/tx_timer_interrupt.S b/ports_smp/cortex_a76ae_smp/ac6/src/tx_timer_interrupt.S index bad59269..5c6a6bc2 100644 --- a/ports_smp/cortex_a76ae_smp/ac6/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a76ae_smp/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/.cproject b/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/.cproject index 34967225..aab1eeaf 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/sample_threadx.ld b/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/sample_threadx.ld index e9b12a82..1c6d45b5 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start @@ -194,7 +194,7 @@ SECTIONS . = . + 4 * 0x8000; __stack = .; } - + .handler_stack_limit (NOLOAD): { . = ALIGN(64); diff --git a/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/v8_aarch64.h b/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports_smp/cortex_a76ae_smp/gnu/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_smp/cortex_a76ae_smp/gnu/example_build/tx/.cproject b/ports_smp/cortex_a76ae_smp/gnu/example_build/tx/.cproject index 3547a1d3..e3f31405 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/example_build/tx/.cproject +++ b/ports_smp/cortex_a76ae_smp/gnu/example_build/tx/.cproject @@ -1,200 +1,200 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a76ae_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a76ae_smp/gnu/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a76ae_smp/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a76ae_smp/gnu/src/tx_initialize_low_level.S b/ports_smp/cortex_a76ae_smp/gnu/src/tx_initialize_low_level.S index b171fc0f..efb08b80 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a76ae_smp/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_context_restore.S index c16c6dbb..5cd7a9df 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,22 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_context_save.S b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_context_save.S index c8281503..76641067 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_fp_disable.c b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_fp_enable.c b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_schedule.S index 52654783..de6b70dd 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* added memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_core_get.S index 684e317c..ea14c901 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_core_preempt.S index 903a5ab9..1d28907f 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,18 +62,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_current_state_get.S index 67b5b6f5..707b41d2 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_current_thread_get.S index 42d5776c..6c4bc9af 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_initialize_wait.S index f1c067cf..defd791c 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_low_level_initialize.S index 101a91f3..99b20d24 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_protect.S b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_protect.S index d2750b7e..1155a3fa 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,22 +61,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -124,9 +109,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_time_get.S index ee4dd40c..335824fb 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_unprotect.S index ae700d1e..680e8bc8 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,21 +58,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_stack_build.S b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_stack_build.S index 746bbd42..581e259e 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_system_return.S index b889de21..23c75241 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a76ae_smp/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a76ae_smp/gnu/src/tx_timer_interrupt.S b/ports_smp/cortex_a76ae_smp/gnu/src/tx_timer_interrupt.S index bad59269..5c6a6bc2 100644 --- a/ports_smp/cortex_a76ae_smp/gnu/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a76ae_smp/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a77_smp/ac6/example_build/sample_threadx/.cproject b/ports_smp/cortex_a77_smp/ac6/example_build/sample_threadx/.cproject index 0be401c6..d7d91e10 100644 --- a/ports_smp/cortex_a77_smp/ac6/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a77_smp/ac6/example_build/sample_threadx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a77_smp/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a77_smp/ac6/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_smp/cortex_a77_smp/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_smp/cortex_a77_smp/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_smp/cortex_a77_smp/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a77_smp/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_smp/cortex_a77_smp/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a77_smp/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_smp/cortex_a77_smp/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_smp/cortex_a77_smp/ac6/example_build/sample_threadx/sample_threadx.scat index 1288a328..1ed382ae 100644 --- a/ports_smp/cortex_a77_smp/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_smp/cortex_a77_smp/ac6/example_build/sample_threadx/sample_threadx.scat @@ -12,13 +12,13 @@ LOAD 0x80000000 { startup.o (StartUp, +FIRST) * (+RO, +RW, +ZI) - + } ;XTABLES +0 ALIGN 0x1000 ;{ - ; xtables.o (*) + ; xtables.o (*) ;} - + SYS_STACK +0 ALIGN 8 EMPTY 0x1000 { } @@ -34,13 +34,13 @@ LOAD 0x80000000 ; All stacks and heap are aligned to a cache-line boundary ; ARM_LIB_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary ; HANDLER_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Stacks for EL3 ; @@ -217,34 +217,34 @@ LOAD 0x80000000 ; { ; *( +RO ) ; } -; +; ; XTABLES +0 ALIGN 0x1000 ; { -; xtables.o (*) +; xtables.o (*) ; } ;} ; ;RW AlignExpr(ImageLimit(XTABLES), 0x1000) -;{ +;{ ; RWSEC +0 ; { ; *( +RW ) ; } -; +; ; ZISEC +0 ; { ; *( +ZI ) ; } -; +; ; SYS_STACK +0 ALIGN 8 EMPTY 0x1000 ; { ; } -; +; ; ; 512 MiB heap ; HEAP +0 ALIGN 8 EMPTY 0x10000000 ; { ; } -; +; ; ; Free Memory section ; FREE_MEMORY +0 ALIGN 8 EMPTY 0x10000000 ; { @@ -254,7 +254,7 @@ LOAD 0x80000000 ; TASK_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { ; } -; +; ; ; Per-CPU 128 MiB handler stacks ; HANDLER_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { diff --git a/ports_smp/cortex_a77_smp/ac6/example_build/sample_threadx/v8_aarch64.h b/ports_smp/cortex_a77_smp/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_smp/cortex_a77_smp/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports_smp/cortex_a77_smp/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_smp/cortex_a77_smp/ac6/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a77_smp/ac6/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_smp/cortex_a77_smp/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports_smp/cortex_a77_smp/ac6/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_smp/cortex_a77_smp/ac6/example_build/tx/.cproject b/ports_smp/cortex_a77_smp/ac6/example_build/tx/.cproject index cab40401..7a372c34 100644 --- a/ports_smp/cortex_a77_smp/ac6/example_build/tx/.cproject +++ b/ports_smp/cortex_a77_smp/ac6/example_build/tx/.cproject @@ -1,188 +1,188 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a77_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a77_smp/ac6/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_smp/cortex_a77_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a77_smp/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a77_smp/ac6/src/tx_initialize_low_level.S b/ports_smp/cortex_a77_smp/ac6/src/tx_initialize_low_level.S index 7d2cfabf..08986f7b 100644 --- a/ports_smp/cortex_a77_smp/ac6/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a77_smp/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_context_restore.S index c16c6dbb..5cd7a9df 100644 --- a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,22 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_context_save.S b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_context_save.S index c8281503..76641067 100644 --- a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_fp_disable.c b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_fp_enable.c b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_schedule.S index 52654783..de6b70dd 100644 --- a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* added memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_core_get.S index 684e317c..ea14c901 100644 --- a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_core_preempt.S index 903a5ab9..1d28907f 100644 --- a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,18 +62,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_current_state_get.S index 67b5b6f5..707b41d2 100644 --- a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_current_thread_get.S index 42d5776c..6c4bc9af 100644 --- a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_initialize_wait.S index f1c067cf..defd791c 100644 --- a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_low_level_initialize.S index 101a91f3..99b20d24 100644 --- a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_protect.S b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_protect.S index d2750b7e..1155a3fa 100644 --- a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,22 +61,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -124,9 +109,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_time_get.S index ee4dd40c..335824fb 100644 --- a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_unprotect.S index ae700d1e..680e8bc8 100644 --- a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,21 +58,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_stack_build.S b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_stack_build.S index 746bbd42..581e259e 100644 --- a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_system_return.S index b889de21..23c75241 100644 --- a/ports_smp/cortex_a77_smp/ac6/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a77_smp/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a77_smp/ac6/src/tx_timer_interrupt.S b/ports_smp/cortex_a77_smp/ac6/src/tx_timer_interrupt.S index bad59269..5c6a6bc2 100644 --- a/ports_smp/cortex_a77_smp/ac6/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a77_smp/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/.cproject b/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/.cproject index 34967225..aab1eeaf 100644 --- a/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/sample_threadx.ld b/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/sample_threadx.ld index e9b12a82..1c6d45b5 100644 --- a/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start @@ -194,7 +194,7 @@ SECTIONS . = . + 4 * 0x8000; __stack = .; } - + .handler_stack_limit (NOLOAD): { . = ALIGN(64); diff --git a/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/v8_aarch64.h b/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports_smp/cortex_a77_smp/gnu/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_smp/cortex_a77_smp/gnu/example_build/tx/.cproject b/ports_smp/cortex_a77_smp/gnu/example_build/tx/.cproject index 3547a1d3..e3f31405 100644 --- a/ports_smp/cortex_a77_smp/gnu/example_build/tx/.cproject +++ b/ports_smp/cortex_a77_smp/gnu/example_build/tx/.cproject @@ -1,200 +1,200 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a77_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a77_smp/gnu/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_smp/cortex_a77_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a77_smp/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a77_smp/gnu/src/tx_initialize_low_level.S b/ports_smp/cortex_a77_smp/gnu/src/tx_initialize_low_level.S index b171fc0f..efb08b80 100644 --- a/ports_smp/cortex_a77_smp/gnu/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a77_smp/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,17 +59,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_context_restore.S index c16c6dbb..5cd7a9df 100644 --- a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,22 +58,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_context_save.S b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_context_save.S index c8281503..76641067 100644 --- a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_fp_disable.c b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_fp_enable.c b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_interrupt_control.S index d8e70ebb..21ec2dd1 100644 --- a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_interrupt_disable.S index e398d46a..af2ef874 100644 --- a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,17 +55,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_interrupt_restore.S index 7b55fb9f..3e0780d0 100644 --- a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_schedule.S index 52654783..de6b70dd 100644 --- a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,19 +59,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* added memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_core_get.S index 684e317c..ea14c901 100644 --- a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_core_preempt.S index 903a5ab9..1d28907f 100644 --- a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,18 +62,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_current_state_get.S index 67b5b6f5..707b41d2 100644 --- a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_current_thread_get.S index 42d5776c..6c4bc9af 100644 --- a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,18 +55,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_initialize_wait.S index f1c067cf..defd791c 100644 --- a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,18 +57,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_low_level_initialize.S index 101a91f3..99b20d24 100644 --- a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_protect.S b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_protect.S index d2750b7e..1155a3fa 100644 --- a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,22 +61,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function @@ -124,9 +109,9 @@ _get_protection: CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! MSR DAIF, x0 // Restore interrupts B _tx_thread_smp_protect // Restart the protection attempt - + _got_protection: - DMB ISH // + DMB ISH // STR w2, [x1, #4] // Save owning core _owned: LDR w5, [x1, #8] // Pickup ownership count diff --git a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_time_get.S index ee4dd40c..335824fb 100644 --- a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,17 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_unprotect.S index ae700d1e..680e8bc8 100644 --- a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,21 +58,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 04-25-2022 William E. Lamie Modified comments, removed */ -/* FIFO queueing, */ -/* resulting in version 6.1.11 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_stack_build.S b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_stack_build.S index 746bbd42..581e259e 100644 --- a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,17 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_system_return.S index b889de21..23c75241 100644 --- a/ports_smp/cortex_a77_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a77_smp/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,19 +58,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, added */ -/* memory barrier, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a77_smp/gnu/src/tx_timer_interrupt.S b/ports_smp/cortex_a77_smp/gnu/src/tx_timer_interrupt.S index bad59269..5c6a6bc2 100644 --- a/ports_smp/cortex_a77_smp/gnu/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a77_smp/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,15 +60,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2023 Tiejun Zhou Modified comment(s), added */ -/* #include tx_user.h, */ -/* resulting in version 6.3.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/.cproject b/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/.cproject index f79ffe9f..67ef2a0c 100644 --- a/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/.cproject @@ -1,148 +1,148 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/sample_threadx.scat index 1288a328..1ed382ae 100644 --- a/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/sample_threadx.scat +++ b/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/sample_threadx.scat @@ -12,13 +12,13 @@ LOAD 0x80000000 { startup.o (StartUp, +FIRST) * (+RO, +RW, +ZI) - + } ;XTABLES +0 ALIGN 0x1000 ;{ - ; xtables.o (*) + ; xtables.o (*) ;} - + SYS_STACK +0 ALIGN 8 EMPTY 0x1000 { } @@ -34,13 +34,13 @@ LOAD 0x80000000 ; All stacks and heap are aligned to a cache-line boundary ; ARM_LIB_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Handler stacks for all CPUs ; All stacks and heap are aligned to a cache-line boundary ; HANDLER_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} - + ; ; Stacks for EL3 ; @@ -217,34 +217,34 @@ LOAD 0x80000000 ; { ; *( +RO ) ; } -; +; ; XTABLES +0 ALIGN 0x1000 ; { -; xtables.o (*) +; xtables.o (*) ; } ;} ; ;RW AlignExpr(ImageLimit(XTABLES), 0x1000) -;{ +;{ ; RWSEC +0 ; { ; *( +RW ) ; } -; +; ; ZISEC +0 ; { ; *( +ZI ) ; } -; +; ; SYS_STACK +0 ALIGN 8 EMPTY 0x1000 ; { ; } -; +; ; ; 512 MiB heap ; HEAP +0 ALIGN 8 EMPTY 0x10000000 ; { ; } -; +; ; ; Free Memory section ; FREE_MEMORY +0 ALIGN 8 EMPTY 0x10000000 ; { @@ -254,7 +254,7 @@ LOAD 0x80000000 ; TASK_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { ; } -; +; ; ; Per-CPU 128 MiB handler stacks ; HANDLER_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) ; { diff --git a/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/v8_aarch64.h b/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/v8_aarch64.h +++ b/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/v8_mmu.h +++ b/ports_smp/cortex_a78_smp/ac6/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_smp/cortex_a78_smp/ac6/example_build/tx/.cproject b/ports_smp/cortex_a78_smp/ac6/example_build/tx/.cproject index 2eecb412..5896ab3a 100644 --- a/ports_smp/cortex_a78_smp/ac6/example_build/tx/.cproject +++ b/ports_smp/cortex_a78_smp/ac6/example_build/tx/.cproject @@ -1,160 +1,160 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a78_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a78_smp/ac6/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_smp/cortex_a78_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a78_smp/ac6/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a78_smp/ac6/src/tx_initialize_low_level.S b/ports_smp/cortex_a78_smp/ac6/src/tx_initialize_low_level.S index 7d2cfabf..08986f7b 100644 --- a/ports_smp/cortex_a78_smp/ac6/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a78_smp/ac6/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_context_restore.S index a447e2a7..e2c48868 100644 --- a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,15 +59,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_context_save.S b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_context_save.S index 890987f1..f43809f5 100644 --- a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_fp_disable.c b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_fp_enable.c b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_interrupt_control.S index efc10724..d4235180 100644 --- a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_interrupt_disable.S index 508562ff..08f0e7e1 100644 --- a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,14 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_interrupt_restore.S index af0fdddf..d0191c32 100644 --- a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_schedule.S index c2d30b48..782491cc 100644 --- a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_core_get.S index d4cda1d8..4ffb8cc6 100644 --- a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,15 +53,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_core_preempt.S index ed9217f4..8dc6933c 100644 --- a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_current_state_get.S index 83394dcc..edae94d5 100644 --- a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,15 +53,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_current_thread_get.S index c235e75d..dd740e05 100644 --- a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,15 +53,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_initialize_wait.S index c4df7504..985136b5 100644 --- a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_low_level_initialize.S index 373a79dd..64b854d0 100644 --- a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_protect.S b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_protect.S index d6ab7f76..30a43701 100644 --- a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,16 +59,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function diff --git a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_time_get.S index 9b198c75..f3045738 100644 --- a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_unprotect.S index 302edc5b..49af176a 100644 --- a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_stack_build.S b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_stack_build.S index 3ded5721..fa11a65c 100644 --- a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,14 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_system_return.S index e500e9e3..4eebb9aa 100644 --- a/ports_smp/cortex_a78_smp/ac6/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a78_smp/ac6/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a78_smp/ac6/src/tx_timer_interrupt.S b/ports_smp/cortex_a78_smp/ac6/src/tx_timer_interrupt.S index 7e22857e..6f90e5d1 100644 --- a/ports_smp/cortex_a78_smp/ac6/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a78_smp/ac6/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,12 +58,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/.cproject b/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/.cproject index 34967225..aab1eeaf 100644 --- a/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/.cproject @@ -1,164 +1,164 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/MP_Mutexes.S index c787c3f5..e8a87f0b 100644 --- a/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/MP_Mutexes.S +++ b/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -92,7 +92,7 @@ _mutex_release: .type _mutex_acquire, "function" .cfi_startproc _mutex_acquire: - // This uses a "ticket lock". The lock is stored as a 32-bit value: + // This uses a "ticket lock". The lock is stored as a 32-bit value: // - the upper 16-bits record the thread's ticket number ("take a ticket") // - the lower 16-bits record the ticket being served ("now serving") diff --git a/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/MP_Mutexes.h index ec1a1d28..00e9cd60 100644 --- a/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ #ifndef MP_MUTEX_H diff --git a/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/sample_threadx.ld b/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/sample_threadx.ld index e9b12a82..1c6d45b5 100644 --- a/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/sample_threadx.ld +++ b/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * start64 : Entry point - * + * * It defines following symbols, which code can use without definition: * __cs3_peripherals * __code_start @@ -194,7 +194,7 @@ SECTIONS . = . + 4 * 0x8000; __stack = .; } - + .handler_stack_limit (NOLOAD): { . = ALIGN(64); diff --git a/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/v8_aarch64.h b/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/v8_aarch64.h index b09079a4..91ca9653 100644 --- a/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/v8_aarch64.h +++ b/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/v8_aarch64.h @@ -4,7 +4,7 @@ * * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. * Use, modification and redistribution of this file is subject to your possession of a - * valid End User License Agreement for the Arm Product of which these examples are part of + * valid End User License Agreement for the Arm Product of which these examples are part of * and your compliance with all applicable terms and conditions of such licence agreement. */ diff --git a/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/v8_mmu.h index bce62b54..d0c51601 100644 --- a/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/v8_mmu.h +++ b/ports_smp/cortex_a78_smp/gnu/example_build/sample_threadx/v8_mmu.h @@ -101,7 +101,7 @@ #define TT_S1_ATTR_PXN (1 << 53) #define TT_S1_ATTR_UXN (1 << 54) -// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits // for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED #define TT_S1_MAIR_DEV_nGnRnE 0b00000000 diff --git a/ports_smp/cortex_a78_smp/gnu/example_build/tx/.cproject b/ports_smp/cortex_a78_smp/gnu/example_build/tx/.cproject index e8013d86..11d7c2fe 100644 --- a/ports_smp/cortex_a78_smp/gnu/example_build/tx/.cproject +++ b/ports_smp/cortex_a78_smp/gnu/example_build/tx/.cproject @@ -1,194 +1,194 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a78_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a78_smp/gnu/inc/tx_port.h index 8db51aba..262f2ddf 100644 --- a/ports_smp/cortex_a78_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a78_smp/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,15 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -419,7 +411,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv8-A-SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv8-A-SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a78_smp/gnu/src/tx_initialize_low_level.S b/ports_smp/cortex_a78_smp/gnu/src/tx_initialize_low_level.S index c8e33bb3..43d87225 100644 --- a/ports_smp/cortex_a78_smp/gnu/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a78_smp/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,14 +57,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_context_restore.S index a447e2a7..e2c48868 100644 --- a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,15 +59,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_context_save.S b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_context_save.S index 890987f1..f43809f5 100644 --- a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_fp_disable.c b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_fp_disable.c index aa175e83..25233f77 100644 --- a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_fp_disable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) { diff --git a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_fp_enable.c b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_fp_enable.c index 341bb200..7351aee4 100644 --- a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_fp_enable.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,14 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) { diff --git a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_interrupt_control.S index efc10724..d4235180 100644 --- a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_interrupt_disable.S index 508562ff..08f0e7e1 100644 --- a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_interrupt_disable.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,14 +53,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_interrupt_restore.S index af0fdddf..d0191c32 100644 --- a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_interrupt_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_restore(UINT old_posture) // { diff --git a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_schedule.S index c2d30b48..782491cc 100644 --- a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_core_get.S index d4cda1d8..4ffb8cc6 100644 --- a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,15 +53,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function diff --git a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_core_preempt.S index ed9217f4..8dc6933c 100644 --- a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,15 +57,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function diff --git a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_current_state_get.S index 83394dcc..edae94d5 100644 --- a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,15 +53,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get, @function diff --git a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_current_thread_get.S index c235e75d..dd740e05 100644 --- a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,15 +53,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get, @function diff --git a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_initialize_wait.S index c4df7504..985136b5 100644 --- a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,15 +55,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait, @function diff --git a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_low_level_initialize.S index 373a79dd..64b854d0 100644 --- a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize, @function diff --git a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_protect.S b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_protect.S index d6ab7f76..30a43701 100644 --- a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,16 +59,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* improved SMP code, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect, @function diff --git a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h index 1c83a29c..82657cb8 100644 --- a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_time_get.S index 9b198c75..f3045738 100644 --- a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -53,14 +54,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get, @function diff --git a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_unprotect.S index 302edc5b..49af176a 100644 --- a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect, @function diff --git a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_stack_build.S b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_stack_build.S index 3ded5721..fa11a65c 100644 --- a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,14 +56,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_system_return.S index e500e9e3..4eebb9aa 100644 --- a/ports_smp/cortex_a78_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a78_smp/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,15 +56,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 01-31-2022 Andres Mlinar Updated comments, */ -/* added ARMv8.2-A support, */ -/* resulting in version 6.1.10 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_a78_smp/gnu/src/tx_timer_interrupt.S b/ports_smp/cortex_a78_smp/gnu/src/tx_timer_interrupt.S index 7e22857e..6f90e5d1 100644 --- a/ports_smp/cortex_a78_smp/gnu/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a78_smp/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,12 +58,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/.cproject b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/.cproject index 67bd7402..57a11bc4 100644 --- a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/.cproject +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/.cproject @@ -1,228 +1,228 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/.settings/language.settings.xml b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/.settings/language.settings.xml index 4de6dbdb..e90f6514 100644 --- a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/.settings/language.settings.xml +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/.settings/language.settings.xml @@ -1,512 +1,512 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_GIC.h b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_GIC.h index bcff9373..f1af87ca 100644 --- a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_GIC.h +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_GIC.h @@ -4,7 +4,7 @@ // // Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_GIC.s b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_GIC.s index cf11b1e5..9007529e 100644 --- a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_GIC.s +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_GIC.s @@ -1,13 +1,13 @@ ;---------------------------------------------------------------- ; Copyright (c) 2005-2018 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ; ; Cortex-A5MP SMP example - Startup Code ;---------------------------------------------------------------- - + AREA MP_GIC, CODE, READONLY @@ -40,7 +40,7 @@ enableGIC PROC BX lr ENDP - + ; ------------------------------------------------------------ EXPORT disableGIC @@ -88,7 +88,7 @@ enableIntID PROC ENDP ; ------------------------------------------------------------ - + EXPORT disableIntID ; void disableIntID(unsigned int ID) ; Disables the interrupt source number ID @@ -129,7 +129,7 @@ setIntPriority PROC ; r0 = base addr ; r1 = priority ; r2 = ID - + ; Make sure that priority value is only 5 bits, and convert to expected format AND r1, r1, #0x1F MOV r1, r1, LSL #3 @@ -211,7 +211,7 @@ setPriorityMask PROC BX lr ENDP - + ; ------------------------------------------------------------ EXPORT setBinaryPoint @@ -256,7 +256,7 @@ writeEOI PROC BX lr ENDP - + ;---------------------------------------------------------------- ; SGI ;---------------------------------------------------------------- diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_Mutexes.h index e410677b..dc2cf932 100644 --- a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_Mutexes.h @@ -3,7 +3,7 @@ // // Copyright (c) 2011-2014 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_Mutexes.s b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_Mutexes.s index 0574eab0..3074bad3 100644 --- a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_Mutexes.s +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_Mutexes.s @@ -3,11 +3,11 @@ ; ; Copyright (c) 2011-2012 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ; ------------------------------------------------------------ - + AREA MP_Mutexes, CODE, READONLY diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_SCU.h b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_SCU.h index a056bd3f..7465e7b7 100644 --- a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_SCU.h +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_SCU.h @@ -4,7 +4,7 @@ // // Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_SCU.s b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_SCU.s index 2c24df11..e3eb4ded 100644 --- a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_SCU.s +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_SCU.s @@ -1,13 +1,13 @@ ;---------------------------------------------------------------- ; Copyright (c) 2005-2018 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ; ; Cortex-A SMP example - Startup Code ;---------------------------------------------------------------- - + AREA MP_SCU, CODE, READONLY @@ -22,7 +22,7 @@ getNumCPUs PROC ; Get base address of private peripheral space MRC p15, 4, r0, c15, c0, 0 ; Read periph base address - + LDR r0, [r0, #0x004] ; Read SCU Configuration register AND r0, r0, #0x3 ; Bits 1:0 gives the number of cores-1 ADD r0, r0, #1 @@ -112,7 +112,7 @@ disableMaintenanceBroadcast PROC secureSCUInvalidate PROC AND r0, r0, #0x03 ; Mask off unused bits of CPU ID MOV r0, r0, LSL #2 ; Convert into bit offset (four bits per core) - + AND r1, r1, #0x0F ; Mask off unused bits of ways MOV r1, r1, LSL r0 ; Shift ways into the correct CPU field diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/sample_threadx.c index 1b6df7c2..5c1f4a16 100644 --- a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -63,7 +63,7 @@ UCHAR event_buffer[65536]; int main(void) { - + /* Enter ThreadX. */ tx_kernel_enter(); @@ -91,41 +91,41 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); - + /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -133,23 +133,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -252,11 +252,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -315,7 +315,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -368,7 +368,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/sample_threadx.scat b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/sample_threadx.scat index 6cdf755a..b89cd020 100644 --- a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/sample_threadx.scat +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/sample_threadx.scat @@ -1,7 +1,7 @@ ;************************************************** ; Copyright (c) 2012 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;************************************************** diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/startup.s b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/startup.s index ce9018ac..9770fd53 100644 --- a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/startup.s +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/startup.s @@ -3,7 +3,7 @@ ; ; Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ; ------------------------------------------------------------ @@ -157,7 +157,7 @@ by_pass ; MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register ; ANDS r0, r0, #0x03 ; Mask off, leaving the CPU ID field ; BNE by_pass2 -; +; ; MOV r0, #0x04 ; Code for SYS_WRITE0 ; LDR r1, =irq_handler_message1 ; SVC 0x123456 @@ -291,7 +291,7 @@ Reset_Handler PROC {} ; 0 - C 0x0 (Inner Noncachable) LDR r0, =||Image$$PAGETABLES$$ZI$$Base|| MSR TTBR0, r0 - + ; ; Activate VFP/NEON, if required @@ -339,7 +339,7 @@ primaryCPUInit PROC ; Translation tables ; ------------------- - ; The translation tables are generated at boot time. + ; The translation tables are generated at boot time. ; First the table is zeroed. Then the individual valid ; entries are written in ; @@ -432,7 +432,7 @@ ttb_zero_loop MOV r0, #0x1F BL setPriorityMask ; Set priority mask (local) - ; [EL] Change start - don't enable interrupts here! + ; [EL] Change start - don't enable interrupts here! ;CPSIE i ; Clear CPSR I bit ; [EL] Change end @@ -451,7 +451,7 @@ ttb_zero_loop MCR p15, 0, r0, c14, c2, 0 ; Setup timeout value (CNTP_TVAL) MOV r0, #0x1 MCR p15, 0, r0, c14, c2, 1 ; Enable timer (CNTP_CTL) - + ; ; Enable receipt of SGI 0 ; ------------------------ diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/tx_initialize_low_level.s b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/tx_initialize_low_level.s index 21326e78..0169112b 100644 --- a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/tx_initialize_low_level.s +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/tx_initialize_low_level.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ @@ -41,10 +41,10 @@ ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_initialize_low_level SMP/Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -52,34 +52,28 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/v7.h b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/v7.h index 5a08b43f..c18b945c 100644 --- a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/v7.h +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/v7.h @@ -4,7 +4,7 @@ // // Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/v7.s b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/v7.s index 35a94ff8..6154246c 100644 --- a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/v7.s +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/v7.s @@ -3,11 +3,11 @@ ; ; Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ; ------------------------------------------------------------ - + AREA v7Opps,CODE,READONLY diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/tx/.cproject b/ports_smp/cortex_a7_smp/ac5/example_build/tx/.cproject index e0007b68..8f34dc39 100644 --- a/ports_smp/cortex_a7_smp/ac5/example_build/tx/.cproject +++ b/ports_smp/cortex_a7_smp/ac5/example_build/tx/.cproject @@ -1,202 +1,202 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/tx/.settings/language.settings.xml b/ports_smp/cortex_a7_smp/ac5/example_build/tx/.settings/language.settings.xml index 6a1b50ae..cc9276fb 100644 --- a/ports_smp/cortex_a7_smp/ac5/example_build/tx/.settings/language.settings.xml +++ b/ports_smp/cortex_a7_smp/ac5/example_build/tx/.settings/language.settings.xml @@ -1,48 +1,48 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ports_smp/cortex_a7_smp/ac5/inc/tx_port.h b/ports_smp/cortex_a7_smp/ac5/inc/tx_port.h index 4be6a68c..69ac4b0f 100644 --- a/ports_smp/cortex_a7_smp/ac5/inc/tx_port.h +++ b/ports_smp/cortex_a7_smp/ac5/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,10 +21,10 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ /* tx_port.h SMP/Cortex-A7/AC5 */ /* 6.1.6 */ /* */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -80,12 +72,12 @@ /* Define ThreadX SMP initialization macro. */ -#define TX_PORT_SPECIFIC_PRE_INITIALIZATION +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION /* Define ThreadX SMP pre-scheduler initialization. */ -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION /* Enable the inter-core interrupt logic. */ @@ -125,7 +117,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -138,7 +130,7 @@ #include -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -174,12 +166,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -189,8 +181,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -248,7 +240,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -262,13 +254,13 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -282,11 +274,11 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -294,8 +286,8 @@ ULONG _tx_misra_time_stamp_get(VOID); tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -321,17 +313,17 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE #ifndef __thumb - + #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (ULONG) __clz((unsigned int) m); \ - b = 31 - b; + b = 31 - b; #endif #endif @@ -346,22 +338,22 @@ struct TX_THREAD_STRUCT; typedef struct TX_THREAD_SMP_PROTECT_STRUCT { ULONG tx_thread_smp_protect_in_force; - struct TX_THREAD_STRUCT * + struct TX_THREAD_STRUCT * tx_thread_smp_protect_thread; ULONG tx_thread_smp_protect_core; ULONG tx_thread_smp_protect_count; - + /* Implementation specific information follows. */ - + ULONG tx_thread_smp_protect_get_caller; ULONG tx_thread_smp_protect_sr; ULONG tx_thread_smp_protect_release_caller; } TX_THREAD_SMP_PROTECT; -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -395,8 +387,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX SMP/Cortex-A7/AC5 Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP/Cortex-A7/AC5 Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a7_smp/ac5/readme_threadx.txt b/ports_smp/cortex_a7_smp/ac5/readme_threadx.txt index fb2a0b26..c679f956 100644 --- a/ports_smp/cortex_a7_smp/ac5/readme_threadx.txt +++ b/ports_smp/cortex_a7_smp/ac5/readme_threadx.txt @@ -6,16 +6,16 @@ 1. Import the ThreadX Projects -In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import -the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) into your DS workspace. 2. Building the ThreadX SMP run-time Library -Building the ThreadX SMP library is easy; simply select the Eclipse project file -"tx" and then select the build button. You should now observe the compilation -and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP +Building the ThreadX SMP library is easy; simply select the Eclipse project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP library file tx.a. @@ -24,49 +24,49 @@ library file tx.a. The ThreadX SMP demonstration is designed to execute under the DS debugger on the VE_Cortex-A7x4 Bare Metal simulator. -Building the demonstration is easy; simply open the workspace file, select the -sample_threadx project, and select the build button. Next, expand the demo ThreadX -project folder in the Project Explorer window, right-click on the 'sample_threadx.launch' +Building the demonstration is easy; simply open the workspace file, select the +sample_threadx project, and select the build button. Next, expand the demo ThreadX +project folder in the Project Explorer window, right-click on the 'sample_threadx.launch' file, click 'Debug As', and then click 'sample_threadx' from the submenu. This will cause the -debugger to load the sample_threadx.axf ELF file and run to main. You are now ready +debugger to load the sample_threadx.axf ELF file and run to main. You are now ready to execute the ThreadX demonstration. 4. System Initialization -The entry point in ThreadX for the Cortex-A7 using AC5 tools is at label +The entry point in ThreadX for the Cortex-A7 using AC5 tools is at label Reset_Handler in startup.s. After the basic core initialization is complete, -control will transfer to __main, which is where all static and global pre-set +control will transfer to __main, which is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. By default, the vector area is defined to be located in the Init area, -which is defined at the top of tx_initialize_low_level.s. This area is typically -located at 0. In situations where this is impossible, the vectors at the beginning +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. By default, the vector area is defined to be located in the Init area, +which is defined at the top of tx_initialize_low_level.s. This area is typically +located at 0. In situations where this is impossible, the vectors at the beginning of the Init area should be copied to address 0. This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 5. Register Usage and Stack Frames -The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -84,39 +84,39 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make it run faster, you can change the build_threadx.bat file to -remove the -g option and enable all compiler optimizations. +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A7 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-A7 vectors start at address zero. The demonstration system startup -Init area contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +Init area contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 7.2 IRQ ISRs @@ -127,12 +127,12 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.s: EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -140,7 +140,7 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -153,7 +153,7 @@ __tx_irq_processing_return 7.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.s: EXPORT __tx_irq_example_handler @@ -163,12 +163,12 @@ __tx_irq_example_handler STMDB sp!, {r0-r3} ; Save some scratch registers MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers BL _tx_thread_vectored_context_save ; Call the vectored IRQ context save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -185,22 +185,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.s. When nested IRQ interrupts are no longer required, calling the _tx_thread_irq_nesting_end service disables nesting by disabling -IRQ interrupts and switching back to IRQ mode in preparation for the IRQ +IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -208,10 +208,10 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* Enable nested IRQ interrupts. NOTE: Since this service returns -; with IRQ interrupts enabled, all IRQ interrupt sources must be +; with IRQ interrupts enabled, all IRQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start -; +; ; /* Application ISR call(s) go here! */ ; ; /* Disable nested IRQ interrupts. The mode is switched back to @@ -224,12 +224,12 @@ __tx_irq_processing_return 7.3 FIQ Interrupts -By default, Cortex-A7 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, Cortex-A7 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.s. @@ -238,7 +238,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.s. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.s: @@ -266,18 +266,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.s. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -293,7 +293,7 @@ __tx_fiq_processing_return ; interrupt, and all C scratch registers are available for use. */ ; ; /* Enable nested FIQ interrupts. NOTE: Since this service returns -; with FIQ interrupts enabled, all FIQ interrupt sources must be +; with FIQ interrupts enabled, all FIQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start ; @@ -309,29 +309,29 @@ __tx_fiq_processing_return 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.s in the Integrator sub-directories. 9. Thumb/Cortex-A7 Mixed Mode -By default, ThreadX is setup for running in Cortex-A7 32-bit mode. This is -also true for the demonstration system. It is possible to build any -ThreadX file and/or the application in Thumb mode. If any Thumb code -is used the entire ThreadX source- both C and assembly - should be built +By default, ThreadX is setup for running in Cortex-A7 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. If any Thumb code +is used the entire ThreadX source- both C and assembly - should be built with the "-apcs /interwork" option. 10. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_context_restore.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_context_restore.s index 1ba569eb..78ddfee1 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_context_restore.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -63,10 +63,10 @@ SVC_MODE EQU 0x93 ; SVC mode ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_context_restore SMP/Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -74,33 +74,27 @@ SVC_MODE EQU 0x93 ; SVC mode ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -137,13 +131,13 @@ _tx_thread_context_restore ADD r3, r3, r12 ; Build array offset LDR r2, [r3, #0] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3, #0] ; Store the counter + STR r2, [r3, #0] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -155,7 +149,7 @@ _tx_thread_context_restore __tx_thread_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr[core]) && (_tx_thread_current_ptr[core] == _tx_thread_execute_ptr[core]) +; else if (((_tx_thread_current_ptr[core]) && (_tx_thread_current_ptr[core] == _tx_thread_execute_ptr[core]) ; || (_tx_thread_preempt_disable)) ; { ; @@ -344,7 +338,7 @@ __tx_thread_dont_save_ts ; ; /* Set bit indicating this thread is ready for execution. */ ; - LDR r2, [r0, #152] ; Pickup the ready bit + LDR r2, [r0, #152] ; Pickup the ready bit ORR r2, r2, #0x8000 ; Set ready bit (bit 15) STR r2, [r0, #152] ; Make this thread ready for executing again DMB ; Ensure that accesses to shared resource have completed diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_context_save.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_context_save.s index 7a36f4af..acc2de11 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_context_save.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,10 +39,10 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_context_save SMP/Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -50,32 +50,26 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -90,13 +84,13 @@ _tx_thread_context_save ; if (_tx_thread_system_state[core]++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers ; ; /* Save the rest of the scratch registers on the stack and return to the ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; IF :DEF:TX_ENABLE_FIQ_SUPPORT @@ -133,7 +127,7 @@ _tx_thread_context_save POP {r12, lr} ; Recover ISR lr & r12 ENDIF - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; __tx_thread_not_nested_save ; } @@ -148,7 +142,7 @@ __tx_thread_not_nested_save ADD r1, r1, r12 ; Build index into current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Save the current stack pointer in the thread's control block. */ @@ -168,7 +162,7 @@ __tx_thread_not_nested_save POP {r12, lr} ; Recover ISR lr & r12 ENDIF - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ; else @@ -178,7 +172,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit @@ -193,7 +187,7 @@ __tx_thread_idle_system_save ENDIF ADD sp, sp, #32 ; Recover saved registers - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ;} diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_control.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_control.s index 2cfad3fe..a007def2 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_control.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,10 +36,10 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_interrupt_control SMP/Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -47,31 +47,25 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_disable.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_disable.s index 3a22d653..58f20f73 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_disable.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_disable.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,10 +29,10 @@ ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_interrupt_disable SMP/Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -40,30 +40,24 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(void) @@ -80,7 +74,7 @@ _tx_thread_interrupt_disable IF :DEF:TX_ENABLE_FIQ_SUPPORT CPSID if ; Disable IRQ and FIQ ELSE - CPSID i ; Disable IRQ + CPSID i ; Disable IRQ ENDIF IF {INTER} = {TRUE} diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_restore.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_restore.s index 71ecfc9b..4d934f36 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_restore.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,10 +29,10 @@ ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_interrupt_restore SMP/Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -40,31 +40,25 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function is responsible for restoring interrupts to the state */ ;/* returned by a previous _tx_thread_interrupt_disable call. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_irq_nesting_end.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_irq_nesting_end.s index 2f0ff9aa..f8827163 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_irq_nesting_end.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_irq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,15 +34,15 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_irq_nesting_end SMP/Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -50,40 +50,34 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -;/* processing from system mode back to IRQ mode prior to the ISR */ -;/* calling _tx_thread_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) @@ -94,7 +88,7 @@ _tx_thread_irq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_c, r0 ; Disable interrupts - LDMIA sp!, {lr, r1} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {lr, r1} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_irq_nesting_start.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_irq_nesting_start.s index 83b26693..8fabed15 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_irq_nesting_start.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_irq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,10 +35,10 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_irq_nesting_start SMP/Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -46,37 +46,31 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_context_save has been called and switches the IRQ */ -;/* processing to the system mode so nested IRQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_schedule.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_schedule.s index 603ab13f..1ced36e9 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_schedule.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_schedule.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -40,10 +40,10 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_schedule SMP/Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -51,34 +51,28 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -122,7 +116,7 @@ _tx_thread_schedule ; ; } ; while(_tx_thread_execute_ptr[core] == TX_NULL); -; +; ; /* Get the lock for accessing the thread's ready bit. */ ; MOV r2, #172 ; Build offset to the lock @@ -185,7 +179,7 @@ _tx_thread_ready_for_execution MOV r1, #0 ; Build clear value STR r1, [r2, #0] ; Clear current thread pointer - LDR r1, [r0, #152] ; Pickup the ready bit + LDR r1, [r0, #152] ; Pickup the ready bit ORR r1, r1, #0x8000 ; Set ready bit (bit 15) STR r1, [r0, #152] ; Make this thread ready for executing again DMB ; Ensure that accesses to shared resource have completed @@ -205,7 +199,7 @@ _execute_pointer_did_not_change ; /* Setup time-slice, if present. */ ; _tx_timer_time_slice[core] = _tx_thread_current_ptr[core] -> tx_thread_time_slice; ; - LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice ; variable ADD r2, r2, r12 ; Build index into the time-slice array LDR sp, [r0, #8] ; Switch stack pointers @@ -241,7 +235,7 @@ _execute_pointer_did_not_change _tx_skip_interrupt_vfp_restore ENDIF LDMIA sp!, {r0-r12, lr, pc}^ ; Return to point of thread interrupt - + _tx_solicited_return IF {TARGET_FPU_VFP} = {TRUE} MSR CPSR_cxsf, r5 ; Recover CPSR diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_core_get.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_core_get.s index 42f39e4c..b2d1fa6a 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_core_get.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_core_get.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -32,10 +32,10 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_smp_core_get SMP/Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -43,30 +43,24 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function gets the currently running core number and returns it.*/ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* Core ID */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX Source */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function gets the currently running core number and returns it.*/ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* Core ID */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_core_get @@ -81,4 +75,4 @@ _tx_thread_smp_core_get ENDIF END - + diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_core_preempt.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_core_preempt.s index 9a1f6e77..6e40b49b 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_core_preempt.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_core_preempt.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -34,10 +34,10 @@ AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_smp_core_preempt SMP/Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -45,34 +45,28 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function preempts the specified core in situations where the */ -;/* thread corresponding to this core is no longer ready or when the */ -;/* core must be used for a higher-priority thread. If the specified is */ -;/* the current core, this processing is skipped since the will give up */ -;/* control subsequently on its own. */ -;/* */ -;/* INPUT */ -;/* */ -;/* core The core to preempt */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX Source */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function preempts the specified core in situations where the */ +;/* thread corresponding to this core is no longer ready or when the */ +;/* core must be used for a higher-priority thread. If the specified is */ +;/* the current core, this processing is skipped since the will give up */ +;/* control subsequently on its own. */ +;/* */ +;/* INPUT */ +;/* */ +;/* core The core to preempt */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_core_preempt @@ -82,11 +76,11 @@ _tx_thread_smp_core_preempt ; ; /* Place call to send inter-processor interrupt here! */ ; - DSB ; - MOV r1, #1 ; Build parameter list - LSL r1, r1, r0 ; - MOV r0, #0 ; - MOV r2, #0 ; + DSB ; + MOV r1, #1 ; Build parameter list + LSL r1, r1, r0 ; + MOV r0, #0 ; + MOV r2, #0 ; BL sendSGI ; Make call to send inter-processor interrupt LDMIA sp!, {lr, r4} ; Recover lr register and r4 @@ -97,4 +91,4 @@ _tx_thread_smp_core_preempt ENDIF END - + diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_current_state_get.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_current_state_get.s index 3883087a..9578854b 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_current_state_get.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_current_state_get.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -34,10 +34,10 @@ AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_smp_current_state_get SMP/Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -45,30 +45,24 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is gets the current state of the calling core. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX Components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is gets the current state of the calling core. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Components */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_current_state_get @@ -91,7 +85,7 @@ _tx_thread_smp_current_state_get LDR r1, =_tx_thread_system_state ; Pickup start of the current state array ADD r1, r1, r2 ; Build index into the current state array LDR r0, [r1] ; Pickup state for this core - MSR CPSR_c, r3 ; Restore CPSR + MSR CPSR_c, r3 ; Restore CPSR IF {INTER} = {TRUE} BX lr ; Return to caller ELSE diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_current_thread_get.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_current_thread_get.s index 34e1e44b..81a97c5a 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_current_thread_get.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_current_thread_get.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -34,10 +34,10 @@ AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_smp_current_thread_get SMP/Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -45,30 +45,24 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is gets the current thread of the calling core. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX Components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is gets the current thread of the calling core. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Components */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_current_thread_get @@ -91,7 +85,7 @@ _tx_thread_smp_current_thread_get LDR r1, =_tx_thread_current_ptr ; Pickup start of the current thread array ADD r1, r1, r2 ; Build index into the current thread array LDR r0, [r1] ; Pickup current thread for this core - MSR CPSR_c, r3 ; Restore CPSR + MSR CPSR_c, r3 ; Restore CPSR IF {INTER} = {TRUE} BX lr ; Return to caller ELSE diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_initialize_wait.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_initialize_wait.s index 973cb472..164c1f77 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_initialize_wait.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_initialize_wait.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -37,10 +37,10 @@ AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_smp_initialize_wait SMP/Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -48,32 +48,26 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is the place where additional cores wait until */ -;/* initialization is complete before they enter the thread scheduling */ -;/* loop. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Hardware */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is the place where additional cores wait until */ +;/* initialization is complete before they enter the thread scheduling */ +;/* loop. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Hardware */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_initialize_wait @@ -93,7 +87,7 @@ _tx_thread_smp_initialize_wait AND r10, r10, #0x03 ; Mask off, leaving the CPU ID field LSL r10, r10, #2 ; Build offset to array indexes ; -; /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release +; /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release ; flag. */ ; LDR r3, =_tx_thread_system_state ; Build address of system state variable @@ -111,10 +105,10 @@ wait_for_initialize wait_for_release LDR r3, [r2] ; Pickup the flag CMP r3, #0 ; Is it set? - BEQ wait_for_release ; Wait for the flag to be set + BEQ wait_for_release ; Wait for the flag to be set ; ; /* Core 0 has released this core. */ -; +; ; /* Clear this core's system state variable. */ ; LDR r3, =_tx_thread_system_state ; Build address of system state variable @@ -124,7 +118,7 @@ wait_for_release ; ; /* Now wait for core 0 to finish it's initialization. */ ; - LDR r3, =_tx_thread_system_state ; Build address of system state variable of logical 0 + LDR r3, =_tx_thread_system_state ; Build address of system state variable of logical 0 core_0_wait_loop LDR r2, [r3] ; Pickup system state for core 0 diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_low_level_initialize.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_low_level_initialize.s index 93830174..09654e48 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_low_level_initialize.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_low_level_initialize.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -32,10 +32,10 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_smp_low_level_initialize SMP/Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -43,31 +43,25 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function performs low-level initialization of the booting */ -;/* core. */ -;/* */ -;/* INPUT */ -;/* */ -;/* number_of_cores Number of cores */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_high_level ThreadX high-level init */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function performs low-level initialization of the booting */ +;/* core. */ +;/* */ +;/* INPUT */ +;/* */ +;/* number_of_cores Number of cores */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_high_level ThreadX high-level init */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_low_level_initialize diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_protect.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_protect.s index 2ed8aa45..5cc9f04e 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_protect.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_protect.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -43,10 +43,10 @@ AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_smp_protect SMP/Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -54,32 +54,26 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function gets protection for running inside the ThreadX */ -;/* source. This is acomplished by a combination of a test-and-set */ -;/* flag and periodically disabling interrupts. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* Previous Status Register */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX Source */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function gets protection for running inside the ThreadX */ +;/* source. This is acomplished by a combination of a test-and-set */ +;/* flag and periodically disabling interrupts. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* Previous Status Register */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_protect diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_protection_wait_list_macros.h index e06d6e4c..f7581458 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_time_get.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_time_get.s index 2b504ce2..627d36f3 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_time_get.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_time_get.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -33,10 +33,10 @@ AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_smp_time_get SMP/Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -44,31 +44,25 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function gets the global time value that is used for debug */ -;/* information and event tracing. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* 32-bit time stamp */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX Source */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function gets the global time value that is used for debug */ +;/* information and event tracing. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* 32-bit time stamp */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_time_get @@ -84,4 +78,4 @@ _tx_thread_smp_time_get ENDIF END - + diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_unprotect.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_unprotect.s index ef5de38b..260d13dc 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_unprotect.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_unprotect.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -37,10 +37,10 @@ AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_smp_unprotect SMP/Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -48,33 +48,27 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function releases previously obtained protection. The supplied */ -;/* previous SR is restored. If the value of _tx_thread_system_state */ -;/* and _tx_thread_preempt_disable are both zero, then multithreading */ -;/* is enabled as well. */ -;/* */ -;/* INPUT */ -;/* */ -;/* Previous Status Register */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX Source */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function releases previously obtained protection. The supplied */ +;/* previous SR is restored. If the value of _tx_thread_system_state */ +;/* and _tx_thread_preempt_disable are both zero, then multithreading */ +;/* is enabled as well. */ +;/* */ +;/* INPUT */ +;/* */ +;/* Previous Status Register */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_unprotect diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_stack_build.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_stack_build.s index b79f82c7..50534f8c 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_stack_build.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_stack_build.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -41,10 +41,10 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_stack_build SMP/Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -52,33 +52,27 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function builds a stack frame on the supplied thread's stack. */ ;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ ;/* thread_ptr Pointer to thread control blk */ ;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -86,10 +80,10 @@ THUMB_BIT EQU 0x20 ; Thumb-bit EXPORT _tx_thread_stack_build _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-A7 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; a1 (r0) Initial value for a1 diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_system_return.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_system_return.s index f869fcbe..ebd80ae2 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_system_return.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_system_return.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,16 +35,16 @@ IMPORT _tx_thread_preempt_disable IMPORT _tx_thread_smp_protection IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY - IMPORT _tx_execution_thread_exit + IMPORT _tx_execution_thread_exit ENDIF ; ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_system_return SMP/Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -52,33 +52,27 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -112,7 +106,7 @@ _tx_skip_solicited_vfp_save MOV r4, #0 ; Build a solicited stack type MRS r5, CPSR ; Pickup the CPSR STMDB sp!, {r4-r5} ; Save type and CPSR -; +; ; /* Lockout interrupts. */ ; IF :DEF:TX_ENABLE_FIQ_SUPPORT @@ -184,8 +178,8 @@ __tx_thread_dont_save_ts CMP r0, r2 ; Is it the same as the current thread? __error_loop BNE __error_loop ; If not, we have a problem!! - ENDIF - + ENDIF + LDR r1, =_tx_thread_preempt_disable ; Build address to preempt disable flag MOV r2, #0 ; Build clear value STR r2, [r1, #0] ; Clear preempt disable flag diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_vectored_context_save.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_vectored_context_save.s index f73ad98a..86145e1e 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_vectored_context_save.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_vectored_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -38,10 +38,10 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_vectored_context_save SMP/Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -49,32 +49,26 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) @@ -144,7 +138,7 @@ __tx_thread_not_nested_save ADD r1, r1, r12 ; Build index into current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Note: Minimal context of interrupted thread is already saved. */ @@ -180,7 +174,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_timer_interrupt.s b/ports_smp/cortex_a7_smp/ac5/src/tx_timer_interrupt.s index 2192cb99..52da0caa 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_timer_interrupt.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_timer_interrupt.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -49,10 +49,10 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_timer_interrupt SMP/Cortex-A7/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ @@ -60,37 +60,31 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* _tx_thread_smp_protect Get SMP protection */ -;/* _tx_thread_smp_unprotect Releast SMP protection */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* _tx_thread_smp_protect Get SMP protection */ +;/* _tx_thread_smp_unprotect Releast SMP protection */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -199,7 +193,7 @@ __tx_timer_done __tx_timer_dont_activate ; ; /* Call time-slice processing. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing ; diff --git a/ports_smp/cortex_a7_smp/gnu/example_build/sample_threadx.c b/ports_smp/cortex_a7_smp/gnu/example_build/sample_threadx.c index 1b6df7c2..5c1f4a16 100644 --- a/ports_smp/cortex_a7_smp/gnu/example_build/sample_threadx.c +++ b/ports_smp/cortex_a7_smp/gnu/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -63,7 +63,7 @@ UCHAR event_buffer[65536]; int main(void) { - + /* Enter ThreadX. */ tx_kernel_enter(); @@ -91,41 +91,41 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); - + /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -133,23 +133,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -252,11 +252,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -315,7 +315,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -368,7 +368,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_smp/cortex_a7_smp/gnu/example_build/sample_threadx.ld b/ports_smp/cortex_a7_smp/gnu/example_build/sample_threadx.ld index fb1ca03c..6b4f194a 100644 --- a/ports_smp/cortex_a7_smp/gnu/example_build/sample_threadx.ld +++ b/ports_smp/cortex_a7_smp/gnu/example_build/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * Vectors : Entry point - * + * * It defines following symbols, which code can use without definition: * __code_start * __exidx_start @@ -170,7 +170,7 @@ SECTIONS __irq_stack = .; _stack_init_irq = .; } - + _end = .; .pagetable 0x80100000 (NOLOAD): diff --git a/ports_smp/cortex_a7_smp/gnu/example_build/tx_initialize_low_level.S b/ports_smp/cortex_a7_smp/gnu/example_build/tx_initialize_low_level.S index 7612b876..1edd005d 100644 --- a/ports_smp/cortex_a7_smp/gnu/example_build/tx_initialize_low_level.S +++ b/ports_smp/cortex_a7_smp/gnu/example_build/tx_initialize_low_level.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Initialize */ @/** */ @@ -56,7 +56,7 @@ .type $_tx_initialize_low_level,function $_tx_initialize_low_level: BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_initialize_low_level @ Call _tx_initialize_low_level function @@ -66,45 +66,39 @@ $_tx_initialize_low_level: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_initialize_low_level MPCore/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level MPCore/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is responsible for any low-level processor */ -@/* initialization, including setting up interrupt vectors, setting */ -@/* up a periodic timer interrupt source, saving the system stack */ -@/* pointer for use in ISR processing later, and finding the first */ -@/* available RAM memory address for tx_application_define. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_initialize_kernel_enter ThreadX entry function */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) diff --git a/ports_smp/cortex_a7_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a7_smp/gnu/inc/tx_port.h index 891f0ba3..db3f4093 100644 --- a/ports_smp/cortex_a7_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a7_smp/gnu/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h SMP/Cortex-A7/GNU */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h SMP/Cortex-A7/GNU */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -75,12 +67,12 @@ /* Define ThreadX SMP initialization macro. */ -#define TX_PORT_SPECIFIC_PRE_INITIALIZATION +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION /* Define ThreadX SMP pre-scheduler initialization. */ -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION /* Enable the inter-core interrupt logic. */ @@ -120,7 +112,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -133,7 +125,7 @@ #include -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -169,12 +161,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -184,8 +176,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -243,7 +235,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -257,13 +249,13 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -277,11 +269,11 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -289,8 +281,8 @@ ULONG _tx_misra_time_stamp_get(VOID); tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -316,8 +308,8 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -328,7 +320,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ asm volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); \ - b = 31 - b; + b = 31 - b; #endif #endif #endif @@ -344,22 +336,22 @@ struct TX_THREAD_STRUCT; typedef struct TX_THREAD_SMP_PROTECT_STRUCT { ULONG tx_thread_smp_protect_in_force; - struct TX_THREAD_STRUCT * + struct TX_THREAD_STRUCT * tx_thread_smp_protect_thread; ULONG tx_thread_smp_protect_core; ULONG tx_thread_smp_protect_count; - + /* Implementation specific information follows. */ - + ULONG tx_thread_smp_protect_get_caller; ULONG tx_thread_smp_protect_sr; ULONG tx_thread_smp_protect_release_caller; } TX_THREAD_SMP_PROTECT; -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -393,8 +385,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX SMP/Cortex-A7/GNU Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP/Cortex-A7/GNU Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a7_smp/gnu/readme_threadx.txt b/ports_smp/cortex_a7_smp/gnu/readme_threadx.txt index 265a3735..94cc17c2 100644 --- a/ports_smp/cortex_a7_smp/gnu/readme_threadx.txt +++ b/ports_smp/cortex_a7_smp/gnu/readme_threadx.txt @@ -4,16 +4,16 @@ 1. Building the ThreadX run-time Library -First make sure you are in the "example_build" directory. Also, make sure that -you have setup your path and other environment variables necessary for the GNU -development environment. +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the GNU +development environment. -At this point you may run the build_threadx.bat batch file. This will build the -ThreadX run-time environment in the "example_build" directory. +At this point you may run the build_threadx.bat batch file. This will build the +ThreadX run-time environment in the "example_build" directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. @@ -21,49 +21,49 @@ application in order to use ThreadX. The ThreadX demonstration is designed to execute under the ARM Cortex-A7x4 FVP. -Building the demonstration is easy; simply execute the build_threadx_sample.bat -batch file while inside the "example_build" directory. +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with TX.A. The resulting file DEMO is a binary file +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with TX.A. The resulting file DEMO is a binary file that can be downloaded and executed. 3. System Initialization -The entry point in ThreadX for the Cortex-A7 using GNU tools is at label +The entry point in ThreadX for the Cortex-A7 using GNU tools is at label Reset_Handler in startup.s. After the basic core initialization is complete, -control will transfer to __main, which is where all static and global pre-set +control will transfer to __main, which is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. By default, the vector area is defined to be located in the Init area, -which is defined at the top of tx_initialize_low_level.s. This area is typically -located at 0. In situations where this is impossible, the vectors at the beginning +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. By default, the vector area is defined to be located in the Init area, +which is defined at the top of tx_initialize_low_level.s. This area is typically +located at 0. In situations where this is impossible, the vectors at the beginning of the Init area should be copied to address 0. This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 4. Register Usage and Stack Frames -The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -81,39 +81,39 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 5. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make it run faster, you can change the build_threadx.bat file to -remove the -g option and enable all compiler optimizations. +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A7 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 6.1 Vector Area The Cortex-A7 vectors start at address zero. The demonstration system startup -Init area contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +Init area contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 6.2 IRQ ISRs @@ -124,12 +124,12 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 6.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.s: EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -137,7 +137,7 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -150,7 +150,7 @@ __tx_irq_processing_return 6.2.2 Vectored IRQ ISRs The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified -by the particular implementation. The following is an example IRQ handler defined in +by the particular implementation. The following is an example IRQ handler defined in tx_initialize_low_level.s: EXPORT __tx_irq_example_handler @@ -160,12 +160,12 @@ __tx_irq_example_handler STMDB sp!, {r0-r3} ; Save some scratch registers MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers BL _tx_thread_vectored_context_save ; Call the vectored IRQ context save ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -182,22 +182,22 @@ IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING defined. With this defined, two new IRQ interrupt management services are available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. These function should be called between the IRQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_irq_nesting_start and -_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved by switching from IRQ mode to SYS mode and enabling IRQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.s. When nested IRQ interrupts are no longer required, calling the _tx_thread_irq_nesting_end service disables nesting by disabling -IRQ interrupts and switching back to IRQ mode in preparation for the IRQ +IRQ interrupts and switching back to IRQ mode in preparation for the IRQ context restore service. -The following is an example of enabling IRQ nested interrupts in a standard +The following is an example of enabling IRQ nested interrupts in a standard IRQ handler: EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -205,10 +205,10 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* Enable nested IRQ interrupts. NOTE: Since this service returns -; with IRQ interrupts enabled, all IRQ interrupt sources must be +; with IRQ interrupts enabled, all IRQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_irq_nesting_start -; +; ; /* Application ISR call(s) go here! */ ; ; /* Disable nested IRQ interrupts. The mode is switched back to @@ -221,12 +221,12 @@ __tx_irq_processing_return 6.3 FIQ Interrupts -By default, Cortex-A7 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, Cortex-A7 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.s. @@ -235,7 +235,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.s. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.s: @@ -263,18 +263,18 @@ FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING defined. With this defined, two new FIQ interrupt management services are available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. These function should be called between the FIQ context save and restore -calls. +calls. -Execution between the calls to _tx_thread_fiq_nesting_start and -_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved by switching from FIQ mode to SYS mode and enabling FIQ interrupts. -The SYS mode stack is used during the SYS mode operation, which was +The SYS mode stack is used during the SYS mode operation, which was setup in tx_initialize_low_level.s. When nested FIQ interrupts are no longer required, calling the _tx_thread_fiq_nesting_end service disables nesting by disabling -FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ context restore service. -The following is an example of enabling FIQ nested interrupts in the +The following is an example of enabling FIQ nested interrupts in the typical FIQ handler: @@ -290,7 +290,7 @@ __tx_fiq_processing_return ; interrupt, and all C scratch registers are available for use. */ ; ; /* Enable nested FIQ interrupts. NOTE: Since this service returns -; with FIQ interrupts enabled, all FIQ interrupt sources must be +; with FIQ interrupts enabled, all FIQ interrupt sources must be ; cleared prior to calling this service. */ BL _tx_thread_fiq_nesting_start ; @@ -306,19 +306,19 @@ __tx_fiq_processing_return 7. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.s in the Integrator sub-directories. 8. VFP Support -VFP support is optional, it can be enabled by building the ThreadX library +VFP support is optional, it can be enabled by building the ThreadX library assembly code with the following command-line option: -mfpu=neon -DTARGET_FPU_VFP @@ -332,7 +332,7 @@ before their use and restored after. For generic code revision information, please refer to the readme_threadx_generic.txt file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: - + 04-02-2021 Release 6.1.6 changes: tx_port.h Updated macro definition diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_context_restore.S index a678d648..94e85ad3 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_context_restore.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -63,48 +63,42 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @ @/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore @ since it will never be called 16-bit mode. */ -@ +@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_context_restore SMP/Cortex-A7/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore SMP/Cortex-A7/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function restores the interrupt context if it is processing a */ -@/* nested interrupt. If not, it returns to the interrupt thread if no */ -@/* preemption is necessary. Otherwise, if preemption is necessary or */ -@/* if no thread was running, the function returns to the scheduler. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling routine */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs Interrupt Service Routines */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) @@ -142,13 +136,13 @@ _tx_thread_context_restore: ADD r3, r3, r12 @ Build array offset LDR r2, [r3, #0] @ Pickup system state SUB r2, r2, #1 @ Decrement the counter - STR r2, [r3, #0] @ Store the counter + STR r2, [r3, #0] @ Store the counter CMP r2, #0 @ Was this the first interrupt? BEQ __tx_thread_not_nested_restore @ If so, not a nested restore @ @ /* Interrupts are nested. */ @ -@ /* Just recover the saved registers and return to the point of +@ /* Just recover the saved registers and return to the point of @ interrupt. */ @ LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs @@ -160,7 +154,7 @@ _tx_thread_context_restore: __tx_thread_not_nested_restore: @ @ /* Determine if a thread was interrupted and no preemption is required. */ -@ else if (((_tx_thread_current_ptr[core]) && (_tx_thread_current_ptr[core] == _tx_thread_execute_ptr[core]) +@ else if (((_tx_thread_current_ptr[core]) && (_tx_thread_current_ptr[core] == _tx_thread_execute_ptr[core]) @ || (_tx_thread_preempt_disable)) @ { @ @@ -349,7 +343,7 @@ __tx_thread_dont_save_ts: @ @ /* Set bit indicating this thread is ready for execution. */ @ - LDR r2, [r0, #152] @ Pickup the ready bit + LDR r2, [r0, #152] @ Pickup the ready bit ORR r2, r2, #0x8000 @ Set ready bit (bit 15) STR r2, [r0, #152] @ Make this thread ready for executing again DMB @ Ensure that accesses to shared resource have completed diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_context_save.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_context_save.S index c34d4a6d..448b3a5a 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_context_save.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -39,47 +39,41 @@ @ @/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save @ since it will never be called 16-bit mode. */ -@ +@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_context_save SMP/Cortex-A7/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save SMP/Cortex-A7/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function saves the context of an executing thread in the */ -@/* beginning of interrupt processing. The function also ensures that */ -@/* the system stack is used upon return to the calling ISR. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) @@ -95,13 +89,13 @@ _tx_thread_context_save: @ if (_tx_thread_system_state[core]++) @ { @ - STMDB sp!, {r0-r3} @ Save some working registers + STMDB sp!, {r0-r3} @ Save some working registers @ @ /* Save the rest of the scratch registers on the stack and return to the @ calling ISR. */ @ MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other registers @ #ifdef TX_ENABLE_FIQ_SUPPORT @@ -138,7 +132,7 @@ _tx_thread_context_save: POP {r12, lr} @ Recover ISR lr & r12 #endif - B __tx_irq_processing_return @ Continue IRQ processing + B __tx_irq_processing_return @ Continue IRQ processing @ __tx_thread_not_nested_save: @ } @@ -153,7 +147,7 @@ __tx_thread_not_nested_save: ADD r1, r1, r12 @ Build index into current thread ptr LDR r0, [r1, #0] @ Pickup current thread pointer CMP r0, #0 @ Is it NULL? - BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in @ scheduling loop - nothing needs saving! @ @ /* Save the current stack pointer in the thread's control block. */ @@ -173,7 +167,7 @@ __tx_thread_not_nested_save: POP {r12, lr} @ Recover ISR lr & r12 #endif - B __tx_irq_processing_return @ Continue IRQ processing + B __tx_irq_processing_return @ Continue IRQ processing @ @ } @ else @@ -183,7 +177,7 @@ __tx_thread_idle_system_save: @ @ /* Interrupt occurred in the scheduling loop. */ @ -@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ @ processing. */ @ MOV r10, #0 @ Clear stack limit @@ -198,7 +192,7 @@ __tx_thread_idle_system_save: #endif ADD sp, sp, #32 @ Recover saved registers - B __tx_irq_processing_return @ Continue IRQ processing + B __tx_irq_processing_return @ Continue IRQ processing @ @ } @} diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_control.S index 6823ead6..3aacd686 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_control.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -38,42 +38,36 @@ INT_MASK = 0x80 @ Interrupt bit mask .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_interrupt_control SMP/Cortex-A7/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control SMP/Cortex-A7/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is responsible for changing the interrupt lockout */ -@/* posture of the system. */ -@/* */ -@/* INPUT */ -@/* */ -@/* new_posture New interrupt lockout posture */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_disable.S index 46a3ac68..c28f4079 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_disable.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -37,7 +37,7 @@ $_tx_thread_interrupt_disable: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_interrupt_disable @ Call _tx_thread_interrupt_disable function @@ -47,41 +47,35 @@ $_tx_thread_interrupt_disable: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_interrupt_disable SMP/Cortex-A7/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_disable SMP/Cortex-A7/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is responsible for disabling interrupts */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is responsible for disabling interrupts */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_disable(void) @@ -99,7 +93,7 @@ _tx_thread_interrupt_disable: #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if @ Disable IRQ and FIQ #else - CPSID i @ Disable IRQ + CPSID i @ Disable IRQ #endif #ifdef __THUMB_INTERWORK diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_restore.S index 2c10b777..90926f28 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_restore.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -37,7 +37,7 @@ $_tx_thread_interrupt_restore: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_interrupt_restore @ Call _tx_thread_interrupt_restore function @@ -47,42 +47,36 @@ $_tx_thread_interrupt_restore: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_interrupt_restore SMP/Cortex-A7/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_restore SMP/Cortex-A7/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ +@/* */ @/* This function is responsible for restoring interrupts to the state */ @/* returned by a previous _tx_thread_interrupt_disable call. */ -@/* */ -@/* INPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* INPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_irq_nesting_end.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_irq_nesting_end.S index b0fda3ff..af9fa825 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_irq_nesting_end.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -34,7 +34,7 @@ DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts #else DISABLE_INTS = 0x80 @ Disable IRQ interrupts #endif -MODE_MASK = 0x1F @ Mode mask +MODE_MASK = 0x1F @ Mode mask IRQ_MODE_BITS = 0x12 @ IRQ mode bits @ @ @@ -44,51 +44,45 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_irq_nesting_end SMP/Cortex-A7/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_end SMP/Cortex-A7/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from IRQ mode after */ -@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -@/* processing from system mode back to IRQ mode prior to the ISR */ -@/* calling _tx_thread_context_restore. Note that this function */ -@/* assumes the system stack pointer is in the same position after */ -@/* nesting start function was called. */ -@/* */ -@/* This function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with IRQ interrupts disabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +@/* processing from system mode back to IRQ mode prior to the ISR */ +@/* calling _tx_thread_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_end(VOID) @@ -100,7 +94,7 @@ _tx_thread_irq_nesting_end: MRS r0, CPSR @ Pickup the CPSR ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value MSR CPSR_c, r0 @ Disable interrupts - LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for @ 8-byte alignment logic) BIC r0, r0, #MODE_MASK @ Clear mode bits ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_irq_nesting_start.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_irq_nesting_start.S index c275b69c..f8dcba8c 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_irq_nesting_start.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -40,48 +40,42 @@ SYS_MODE_BITS = 0x1F @ System mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_irq_nesting_start SMP/Cortex-A7/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_start SMP/Cortex-A7/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from IRQ mode after */ -@/* _tx_thread_context_save has been called and switches the IRQ */ -@/* processing to the system mode so nested IRQ interrupt processing */ -@/* is possible (system mode has its own "lr" register). Note that */ -@/* this function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with IRQ interrupts enabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_context_save has been called and switches the IRQ */ +@/* processing to the system mode so nested IRQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_schedule.S index 3e9d8c8e..88917752 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_schedule.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -46,7 +46,7 @@ $_tx_thread_schedule: .thumb BX pc @ Switch to 32-bit mode - NOP @ + NOP @ .arm STMFD sp!, {lr} @ Save return address BL _tx_thread_schedule @ Call _tx_thread_schedule function @@ -56,45 +56,39 @@ $_tx_thread_schedule: @ .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_schedule SMP/Cortex-A7/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_schedule SMP/Cortex-A7/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function waits for a thread control block pointer to appear in */ -@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -@/* in the variable, the corresponding thread is resumed. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_initialize_kernel_enter ThreadX entry function */ -@/* _tx_thread_system_return Return to system from thread */ -@/* _tx_thread_context_restore Restore thread's context */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function waits for a thread control block pointer to appear in */ +@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +@/* in the variable, the corresponding thread is resumed. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* _tx_thread_system_return Return to system from thread */ +@/* _tx_thread_context_restore Restore thread's context */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) @@ -139,7 +133,7 @@ _tx_thread_schedule: @ @ } @ while(_tx_thread_execute_ptr[core] == TX_NULL); -@ +@ @ /* Get the lock for accessing the thread's ready bit. */ @ MOV r2, #172 @ Build offset to the lock @@ -202,7 +196,7 @@ _tx_thread_ready_for_execution: MOV r1, #0 @ Build clear value STR r1, [r2, #0] @ Clear current thread pointer - LDR r1, [r0, #152] @ Pickup the ready bit + LDR r1, [r0, #152] @ Pickup the ready bit ORR r1, r1, #0x8000 @ Set ready bit (bit 15) STR r1, [r0, #152] @ Make this thread ready for executing again DMB @ Ensure that accesses to shared resource have completed @@ -222,7 +216,7 @@ _execute_pointer_did_not_change: @ /* Setup time-slice, if present. */ @ _tx_timer_time_slice[core] = _tx_thread_current_ptr[core] -> tx_thread_time_slice; @ - LDR r2, =_tx_timer_time_slice @ Pickup address of time slice + LDR r2, =_tx_timer_time_slice @ Pickup address of time slice @ variable ADD r2, r2, r12 @ Build index into the time-slice array LDR sp, [r0, #8] @ Switch stack pointers diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_core_get.S index a66cefec..6a4f7a16 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_core_get.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread - Low Level SMP Support */ @/** */ @@ -33,41 +33,35 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_smp_core_get SMP/Cortex-A7/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_core_get SMP/Cortex-A7/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function gets the currently running core number and returns it.*/ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* Core ID */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX Source */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function gets the currently running core number and returns it.*/ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* Core ID */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_core_get diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_core_preempt.S index c20c4201..52ef964c 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_core_preempt.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread - Low Level SMP Support */ @/** */ @@ -37,45 +37,39 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_smp_core_preempt SMP/Cortex-A7/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_core_preempt SMP/Cortex-A7/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function preempts the specified core in situations where the */ -@/* thread corresponding to this core is no longer ready or when the */ -@/* core must be used for a higher-priority thread. If the specified is */ -@/* the current core, this processing is skipped since the will give up */ -@/* control subsequently on its own. */ -@/* */ -@/* INPUT */ -@/* */ -@/* core The core to preempt */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX Source */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function preempts the specified core in situations where the */ +@/* thread corresponding to this core is no longer ready or when the */ +@/* core must be used for a higher-priority thread. If the specified is */ +@/* the current core, this processing is skipped since the will give up */ +@/* control subsequently on its own. */ +@/* */ +@/* INPUT */ +@/* */ +@/* core The core to preempt */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_core_preempt @@ -86,11 +80,11 @@ _tx_thread_smp_core_preempt: @ @ /* Place call to send inter-processor interrupt here! */ @ - DSB @ - MOV r1, #1 @ Build parameter list - LSL r1, r1, r0 @ - MOV r0, #0 @ - MOV r2, #0 @ + DSB @ + MOV r1, #1 @ Build parameter list + LSL r1, r1, r0 @ + MOV r0, #0 @ + MOV r2, #0 @ BL sendSGI @ Make call to send inter-processor interrupt LDMIA sp!, {r4, lr} @ Recover lr register and r4 @@ -101,4 +95,4 @@ _tx_thread_smp_core_preempt: #endif - + diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_current_state_get.S index 2dcae8d4..2c81241d 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_current_state_get.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread - Low Level SMP Support */ @/** */ @@ -35,41 +35,35 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_smp_current_state_get SMP/Cortex-A7/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_current_state_get SMP/Cortex-A7/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is gets the current state of the calling core. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX Components */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is gets the current state of the calling core. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Components */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_current_state_get @@ -93,7 +87,7 @@ _tx_thread_smp_current_state_get: LDR r1, =_tx_thread_system_state @ Pickup start of the current state array ADD r1, r1, r2 @ Build index into the current state array LDR r0, [r1] @ Pickup state for this core - MSR CPSR_c, r3 @ Restore CPSR + MSR CPSR_c, r3 @ Restore CPSR #ifdef __THUMB_INTERWORK BX lr @ Return to caller #else diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_current_thread_get.S index dc5ceb9e..b17ab538 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_current_thread_get.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread - Low Level SMP Support */ @/** */ @@ -35,41 +35,35 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_smp_current_thread_get SMP/Cortex-A7/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_current_thread_get SMP/Cortex-A7/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is gets the current thread of the calling core. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX Components */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is gets the current thread of the calling core. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Components */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_current_thread_get @@ -93,7 +87,7 @@ _tx_thread_smp_current_thread_get: LDR r1, =_tx_thread_current_ptr @ Pickup start of the current thread array ADD r1, r1, r2 @ Build index into the current thread array LDR r0, [r1] @ Pickup current thread for this core - MSR CPSR_c, r3 @ Restore CPSR + MSR CPSR_c, r3 @ Restore CPSR #ifdef __THUMB_INTERWORK BX lr @ Return to caller #else diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_initialize_wait.S index f15f1623..07f6a10a 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_initialize_wait.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread - Low Level SMP Support */ @/** */ @@ -38,43 +38,37 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_smp_initialize_wait SMP/Cortex-A7/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_initialize_wait SMP/Cortex-A7/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is the place where additional cores wait until */ -@/* initialization is complete before they enter the thread scheduling */ -@/* loop. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling loop */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Hardware */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is the place where additional cores wait until */ +@/* initialization is complete before they enter the thread scheduling */ +@/* loop. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Hardware */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_initialize_wait @@ -95,7 +89,7 @@ _tx_thread_smp_initialize_wait: AND r10, r10, #0x03 @ Mask off, leaving the CPU ID field LSL r10, r10, #2 @ Build offset to array indexes @ -@ /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release +@ /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release @ flag. */ @ LDR r3, =_tx_thread_system_state @ Build address of system state variable @@ -113,10 +107,10 @@ wait_for_initialize: wait_for_release: LDR r3, [r2] @ Pickup the flag CMP r3, #0 @ Is it set? - BEQ wait_for_release @ Wait for the flag to be set + BEQ wait_for_release @ Wait for the flag to be set @ @ /* Core 0 has released this core. */ -@ +@ @ /* Clear this core's system state variable. */ @ LDR r3, =_tx_thread_system_state @ Build address of system state variable @@ -126,7 +120,7 @@ wait_for_release: @ @ /* Now wait for core 0 to finish it's initialization. */ @ - LDR r3, =_tx_thread_system_state @ Build address of system state variable of logical 0 + LDR r3, =_tx_thread_system_state @ Build address of system state variable of logical 0 core_0_wait_loop: LDR r2, [r3] @ Pickup system state for core 0 diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_low_level_initialize.S index 652056f7..8b74406f 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_low_level_initialize.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread - Low Level SMP Support */ @/** */ @@ -33,42 +33,36 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_smp_low_level_initialize SMP/Cortex-A7/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_low_level_initialize SMP/Cortex-A7/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function performs low-level initialization of the booting */ -@/* core. */ -@/* */ -@/* INPUT */ -@/* */ -@/* number_of_cores Number of cores */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_initialize_high_level ThreadX high-level init */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function performs low-level initialization of the booting */ +@/* core. */ +@/* */ +@/* INPUT */ +@/* */ +@/* number_of_cores Number of cores */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_high_level ThreadX high-level init */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_low_level_initialize diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_protect.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_protect.S index bf19e812..4404585d 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_protect.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread - Low Level SMP Support */ @/** */ @@ -44,45 +44,37 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_smp_protect SMP/Cortex-A7/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_protect SMP/Cortex-A7/GNU */ @/* 6.1.12 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function gets protection for running inside the ThreadX */ -@/* source. This is ccomplished by a combination of a test-and-set */ -@/* flag and periodically disabling interrupts. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* Previous Status Register */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX Source */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* 07-29-2022 Scott Larson Fixed preprocessor statement, */ -@/* resulting in version 6.1.12 */ +@/* This function gets protection for running inside the ThreadX */ +@/* source. This is ccomplished by a combination of a test-and-set */ +@/* flag and periodically disabling interrupts. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* Previous Status Register */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_protect diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h index 19f8a33a..dff747d1 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,10 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_time_get.S index f936b93e..067f50d8 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_time_get.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread - Low Level SMP Support */ @/** */ @@ -34,42 +34,36 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_smp_time_get SMP/Cortex-A7/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_time_get SMP/Cortex-A7/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function gets the global time value that is used for debug */ -@/* information and event tracing. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* 32-bit time stamp */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX Source */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function gets the global time value that is used for debug */ +@/* information and event tracing. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* 32-bit time stamp */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_time_get diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_unprotect.s b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_unprotect.s index d731b82f..5b939a05 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_unprotect.s +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_unprotect.s @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread - Low Level SMP Support */ @/** */ @@ -38,44 +38,38 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_smp_unprotect SMP/Cortex-A7/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_unprotect SMP/Cortex-A7/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function releases previously obtained protection. The supplied */ -@/* previous SR is restored. If the value of _tx_thread_system_state */ -@/* and _tx_thread_preempt_disable are both zero, then multithreading */ -@/* is enabled as well. */ -@/* */ -@/* INPUT */ -@/* */ -@/* Previous Status Register */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX Source */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function releases previously obtained protection. The supplied */ +@/* previous SR is restored. If the value of _tx_thread_system_state */ +@/* and _tx_thread_preempt_disable are both zero, then multithreading */ +@/* is enabled as well. */ +@/* */ +@/* INPUT */ +@/* */ +@/* Previous Status Register */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_unprotect diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_stack_build.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_stack_build.S index 11e860fd..a56d3d20 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_stack_build.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -43,44 +43,38 @@ THUMB_BIT = 0x20 @ Thumb-bit .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_stack_build SMP/Cortex-A7/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build SMP/Cortex-A7/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ +@/* */ @/* This function builds a stack frame on the supplied thread's stack. */ @/* The stack frame results in a fake interrupt return to the supplied */ -@/* function pointer. */ -@/* */ -@/* INPUT */ -@/* */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ @/* thread_ptr Pointer to thread control blk */ @/* function_ptr Pointer to return function */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_thread_create Create thread service */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -89,10 +83,10 @@ THUMB_BIT = 0x20 @ Thumb-bit .type _tx_thread_stack_build,function _tx_thread_stack_build: @ -@ +@ @ /* Build a fake interrupt frame. The form of the fake interrupt stack @ on the Cortex-A7 should look like the following after it is built: -@ +@ @ Stack Top: 1 Interrupt stack frame type @ CPSR Initial value for CPSR @ a1 (r0) Initial value for a1 diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_system_return.S index a6f07a7b..98e64ad1 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_system_return.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -35,51 +35,45 @@ .global _tx_thread_preempt_disable .global _tx_thread_smp_protection #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - .global _tx_execution_thread_exit + .global _tx_execution_thread_exit #endif @ @ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_system_return SMP/Cortex-A7/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return SMP/Cortex-A7/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is target processor specific. It is used to transfer */ -@/* control from a thread back to the ThreadX system. Only a */ -@/* minimal context is saved since the compiler assumes temp registers */ -@/* are going to get slicked by a function call anyway. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling loop */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX components */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ @/* */ @/**************************************************************************/ @VOID _tx_thread_system_return(VOID) @@ -114,7 +108,7 @@ _tx_skip_solicited_vfp_save: MOV r4, #0 @ Build a solicited stack type MRS r5, CPSR @ Pickup the CPSR STMDB sp!, {r4-r5} @ Save type and CPSR -@ +@ @ /* Lockout interrupts. */ @ #ifdef TX_ENABLE_FIQ_SUPPORT @@ -186,8 +180,8 @@ __tx_thread_dont_save_ts: CMP r0, r2 @ Is it the same as the current thread? __error_loop: BNE __error_loop @ If not, we have a problem!! -#endif - +#endif + LDR r1, =_tx_thread_preempt_disable @ Build address to preempt disable flag MOV r2, #0 @ Build clear value STR r2, [r1, #0] @ Clear preempt disable flag diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_vectored_context_save.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_vectored_context_save.S index 5e487f83..0d8aab55 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_vectored_context_save.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_vectored_context_save.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -39,43 +39,37 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_vectored_context_save SMP/Cortex-A7/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_vectored_context_save SMP/Cortex-A7/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function saves the context of an executing thread in the */ -@/* beginning of interrupt processing. The function also ensures that */ -@/* the system stack is used upon return to the calling ISR. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_vectored_context_save(VOID) @@ -146,7 +140,7 @@ __tx_thread_not_nested_save: ADD r1, r1, r12 @ Build index into current thread ptr LDR r0, [r1, #0] @ Pickup current thread pointer CMP r0, #0 @ Is it NULL? - BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in @ scheduling loop - nothing needs saving! @ @ /* Note: Minimal context of interrupted thread is already saved. */ @@ -182,7 +176,7 @@ __tx_thread_idle_system_save: @ @ /* Interrupt occurred in the scheduling loop. */ @ -@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ @ processing. */ @ MOV r10, #0 @ Clear stack limit diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_timer_interrupt.S b/ports_smp/cortex_a7_smp/gnu/src/tx_timer_interrupt.S index 4b072ae4..4effd9f8 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_timer_interrupt.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Timer */ @/** */ @@ -50,48 +50,42 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_timer_interrupt SMP/Cortex-A7/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt SMP/Cortex-A7/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function processes the hardware timer interrupt. This */ -@/* processing includes incrementing the system clock and checking for */ -@/* time slice and/or timer expiration. If either is found, the */ -@/* interrupt context save/restore functions are called along with the */ -@/* expiration functions. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_time_slice Time slice interrupted thread */ -@/* _tx_thread_smp_protect Get SMP protection */ -@/* _tx_thread_smp_unprotect Releast SMP protection */ -@/* _tx_timer_expiration_process Timer expiration processing */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* interrupt vector */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* _tx_thread_smp_protect Get SMP protection */ +@/* _tx_thread_smp_unprotect Releast SMP protection */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) @@ -201,7 +195,7 @@ __tx_timer_done: __tx_timer_dont_activate: @ @ /* Call time-slice processing. */ -@ _tx_thread_time_slice(); +@ _tx_thread_time_slice(); BL _tx_thread_time_slice @ Call time-slice processing @ diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_GIC.h b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_GIC.h index 3c92c541..d075fbea 100644 --- a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_GIC.h +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_GIC.h @@ -41,7 +41,7 @@ void set_irq_priority(unsigned int ID, unsigned int priority); // Enables the processor interface // Must been done one each core seperately -void enable_gic_processor_interface(void); +void enable_gic_processor_interface(void); // Disables the processor interface void disable_gic_processor_interface(void); diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_GIC.s b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_GIC.s index dc5ec273..c6ebf712 100644 --- a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_GIC.s +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_GIC.s @@ -38,7 +38,7 @@ enable_GIC PROC BX lr ENDP - + ; ------------------------------------------------------------ EXPORT disable_GIC @@ -88,7 +88,7 @@ enable_irq_id PROC ENDP ; ------------------------------------------------------------ - + EXPORT disable_irq_id ; void disable_irq_id(unsigned int ID) ; Disables the interrupt source number ID @@ -131,7 +131,7 @@ set_irq_priority PROC ; r0 = base addr ; r1 = priority ; r2 = ID - + ; Make sure that priority value is only 5 bits, and convert to expected format AND r1, r1, #0x1F MOV r1, r1, LSL #3 @@ -207,12 +207,12 @@ set_priority_mask PROC ; Get base address of private perpherial space MOV r1, r0 ; Back up passed in ID value MRC p15, 4, r0, c15, c0, 0 ; Read periph base address - + STR r1, [r0, #0x0104] ; Write the Priority Mask register (ICCPMR/ICCIPMR) BX lr ENDP - + ; ------------------------------------------------------------ EXPORT set_binary_port @@ -255,7 +255,7 @@ write_end_of_irq PROC BX lr ENDP - + ; ------------------------------------------------------------ ; SGI ; ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.h b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.h index 27a02dc7..cc0dfbae 100644 --- a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.h +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.h @@ -19,7 +19,7 @@ // r1: Increment value (ignored if auto_increment != 0) void init_global_timer(unsigned int auto_increment, unsigned int increment_value) -// Sets the comparator value for this CPU +// Sets the comparator value for this CPU void set_global_timer_comparator(unsigned int top, unsigned int bottom); // Starts the private timer diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.s b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.s index 0e9bb3df..e6d92e97 100644 --- a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.s +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.s @@ -46,8 +46,8 @@ init_global_timer PROC STR r0, [r2, #0x208] ; Store to control register ; Store increment value - STREQ r1, [r2, #0x218] - + STREQ r1, [r2, #0x218] + ; Clear timer value MOV r0, #0x0 STR r0, [r2, #0x0] @@ -71,12 +71,12 @@ set_global_timer_comparator PROC LDR r1, [r2, #0x208] ; Read control reg BIC r3, r3, #0x02 ; Clear comparator enable bit STR r3, [r2, #0x208] ; Write modified value back - + ; Write the comparator registers STR r1, [r2, #0x210] ; Write lower 32 bits STR r0, [r2, #0x214] ; Write upper 32 bits DMB - + ; Re-enable the comparator ORR r3, r3, #0x02 ; Set comparator enable bit STR r3, [r2, #0x208] ; Write modified value back @@ -141,7 +141,7 @@ get_global_timer_count_loop BX lr ENDP - + ; ------------------------------------------------------------ EXPORT clear_global_timer_irq diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_Mutexes.h index 0317ddf0..66450ff6 100644 --- a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_Mutexes.h @@ -9,9 +9,9 @@ #define _CORTEXA_MUTEX_ // Struct -// 0xFF=unlocked 0x0 = Locked by CPU 0, -// 0x1 = Locked by CPU 1, -// 0x2 = Locked by CPU 2, +// 0xFF=unlocked 0x0 = Locked by CPU 0, +// 0x1 = Locked by CPU 1, +// 0x2 = Locked by CPU 2, // 0x3 = Locked by CPU 3 typedef struct { diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_Mutexes.s b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_Mutexes.s index 3774d8b9..e9168cd2 100644 --- a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_Mutexes.s +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_Mutexes.s @@ -49,7 +49,7 @@ lock_mutex PROC WFENE ; If mutex is locked, go into standby BNE lock_mutex ; On waking re-check the mutex - + ; Attempt to lock mutex ; ----------------------- MRC p15, 0, r1, c0, c0, 5 ; Read CPU ID register @@ -87,7 +87,7 @@ unlock_mutex PROC MOV r1, #UNLOCKED ; Write "unlocked" into lock field STR r1, [r0] - + DMB ; To ensure update of the mutex occurs before other CPUs awake SEV ; Send event to other CPUs, wakes anyone waiting on a mutex (using WFE) @@ -104,7 +104,7 @@ unlock_mutex PROC ; Returns 0x0 if mutex unlocked, 0x1 is locked ; r0 = address of mutex_t is_mutex_locked PROC - LDR r0, [r0] + LDR r0, [r0] CMP r0, #UNLOCKED MOVEQ r0, #0x0 MOVNE r0, #0x1 diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_PrivateTimer.s b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_PrivateTimer.s index f8a1eefa..cfd40bc4 100644 --- a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_PrivateTimer.s +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_PrivateTimer.s @@ -94,7 +94,7 @@ get_private_timer_count PROC BX lr ENDP - + ; ------------------------------------------------------------ EXPORT clear_private_timer_irq diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_SCU.s b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_SCU.s index 572e2a87..9513cb73 100644 --- a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_SCU.s +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_SCU.s @@ -40,13 +40,13 @@ get_num_cpus PROC ; Get base address of private perpherial space MRC p15, 4, r0, c15, c0, 0 ; Read periph base address - + LDR r0, [r0, #0x004] ; Read SCU Configuration register AND r0, r0, #0x3 ; Bits 1:0 gives the number of cores BX lr ENDP - + ; ------------------------------------------------------------ EXPORT go_to_sleep @@ -170,14 +170,14 @@ disable_maintenance_broadcast PROC secure_SCU_invalidate PROC AND r0, r0, #0x03 ; Mask off unused bits of CPU ID MOV r0, r0, LSL #2 ; Convert into bit offset (four bits per core) - + AND r1, r1, #0x0F ; Mask off unused bits of ways MOV r1, r1, LSL r0 ; Shift ways into the correct CPU field MRC p15, 4, r2, c15, c0, 0 ; Read periph base address STR r1, [r2, #0x0C] ; Write to SCU Invalidate All in Secure State - + BX lr ENDP diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/sample_threadx.c index ce4d3126..9daf05f6 100644 --- a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/sample_threadx.c +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -63,7 +63,7 @@ UCHAR event_buffer[65536]; int main(void) { - + /* Enter ThreadX. */ tx_kernel_enter(); @@ -91,41 +91,41 @@ CHAR *pointer; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); - + /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -133,23 +133,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -252,11 +252,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -315,7 +315,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -368,7 +368,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/sample_threadx.scat b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/sample_threadx.scat index f2a2d1bd..15c83ca6 100644 --- a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/sample_threadx.scat +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/sample_threadx.scat @@ -2,7 +2,7 @@ ;******************************************************* ; Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved. ; Use, modification and redistribution of this file is subject to your possession of a -; valid End User License Agreement for the Arm Product of which these examples are part of +; valid End User License Agreement for the Arm Product of which these examples are part of ; and your compliance with all applicable terms and conditions of such licence agreement. ;******************************************************* @@ -22,7 +22,7 @@ LOAD 0x80000000 { * (+RO) } - + SHARED_DATA +0 { * (+RW,+ZI) diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/startup.s b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/startup.s index 44b7735d..2a3b7317 100644 --- a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/startup.s +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/startup.s @@ -351,7 +351,7 @@ primary_cpu_init PROC ; ; Translation tables ; ; ------------------- -; ; The translation tables are generated at boot time. +; ; The translation tables are generated at boot time. ; ; First the table is zeroed. Then the individual valid ; ; entries are written in ; ; diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/v7.s b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/v7.s index d4948c88..ab2f6feb 100644 --- a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/v7.s +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/v7.s @@ -19,7 +19,7 @@ enable_caches PROC MCR p15, 0, r0, c1, c0, 0 ; Write System Control Register configuration data BX lr ENDP - + EXPORT disable_caches ; void disable_caches(void) @@ -36,7 +36,7 @@ disable_caches PROC ; void clean_dcache(void); clean_dcache PROC PUSH {r4-r12} - + ; ; Based on code example given in section 11.2.4 of ARM DDI 0406B ; @@ -86,12 +86,12 @@ clean_dcache_finished BX lr ENDP - + EXPORT clean_invalidate_dcache ; void clean_invalidate_dcache(void); clean_invalidate_dcache PROC PUSH {r4-r12} - + ; ; Based on code example given in section 11.2.4 of ARM DDI 0406B ; @@ -147,7 +147,7 @@ clean_invalidate_dcache_finished ; void invalidate_caches(void); invalidate_caches PROC PUSH {r4-r12} - + ; ; Based on code example given in section B2.2.4/11.2.4 of ARM DDI 0406B ; @@ -199,7 +199,7 @@ invalidate_caches_finished POP {r4-r12} BX lr ENDP - + EXPORT invalidate_caches_is ; void invalidate_caches_is(void); @@ -295,7 +295,7 @@ disable_branch_prediction PROC MCR p15, 0,r0, c1, c0, 0 ; Write SCTLR BX lr ENDP - + EXPORT invalidate_branch_target_cache ; void invalidate_branch_target_cache(void) invalidate_branch_target_cache PROC @@ -351,7 +351,7 @@ set_context_id PROC MCR p15, 0, r0, c13, c0, 1 ; Write Context ID Register BX lr ENDP - + ; ------------------------------------------------------------ ; ID registers ; ------------------------------------------------------------ @@ -362,7 +362,7 @@ get_MIDR PROC MRC p15, 0, r0, c0, c0, 0 ; Read Main ID Register (MIDR) BX lr ENDP - + EXPORT get_MPIDR ; uint32_t get_MPIDR(void); get_MPIDR PROC diff --git a/ports_smp/cortex_a9_smp/ac5/inc/tx_port.h b/ports_smp/cortex_a9_smp/ac5/inc/tx_port.h index 05f4b3b4..f065d5f2 100644 --- a/ports_smp/cortex_a9_smp/ac5/inc/tx_port.h +++ b/ports_smp/cortex_a9_smp/ac5/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h SMP/Cortex-A9/AC5 */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h SMP/Cortex-A9/AC5 */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -85,12 +77,12 @@ /* Define ThreadX SMP initialization macro. */ -#define TX_PORT_SPECIFIC_PRE_INITIALIZATION +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION /* Define ThreadX SMP pre-scheduler initialization. */ -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION /* Enable the inter-core interrupt logic. */ @@ -130,7 +122,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -143,7 +135,7 @@ #include -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -179,12 +171,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -194,8 +186,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -253,7 +245,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -267,13 +259,13 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -287,11 +279,11 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -299,8 +291,8 @@ ULONG _tx_misra_time_stamp_get(VOID); tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -326,17 +318,17 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE #ifndef __thumb - + #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ b = (ULONG) __clz((unsigned int) m); \ - b = 31 - b; + b = 31 - b; #endif #endif @@ -351,22 +343,22 @@ struct TX_THREAD_STRUCT; typedef struct TX_THREAD_SMP_PROTECT_STRUCT { ULONG tx_thread_smp_protect_in_force; - struct TX_THREAD_STRUCT * + struct TX_THREAD_STRUCT * tx_thread_smp_protect_thread; ULONG tx_thread_smp_protect_core; ULONG tx_thread_smp_protect_count; - + /* Implementation specific information follows. */ - + ULONG tx_thread_smp_protect_get_caller; ULONG tx_thread_smp_protect_sr; ULONG tx_thread_smp_protect_release_caller; } TX_THREAD_SMP_PROTECT; -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -400,8 +392,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX SMP/Cortex-A9/AC5 Version Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP/Cortex-A9/AC5 Version Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a9_smp/ac5/readme_threadx.txt b/ports_smp/cortex_a9_smp/ac5/readme_threadx.txt index 1c3bfe86..9f4982ca 100644 --- a/ports_smp/cortex_a9_smp/ac5/readme_threadx.txt +++ b/ports_smp/cortex_a9_smp/ac5/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX SMP for Cortex-A9 + Microsoft's Azure RTOS ThreadX SMP for Cortex-A9 Thumb & 32-bit Mode @@ -7,8 +7,8 @@ 1. Import the ThreadX Projects -In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import -the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) into your DS workspace. Note: the projects were made using DS-5, so DS will prompt you to migrate the projects. @@ -17,9 +17,9 @@ This is expected, so please do so. 2. Building the ThreadX SMP run-time Library -Building the ThreadX SMP library is easy; simply select the Eclipse project file -"tx" and then select the build button. You should now observe the compilation -and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP +Building the ThreadX SMP library is easy; simply select the Eclipse project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP library file tx.a. @@ -28,39 +28,39 @@ library file tx.a. The ThreadX SMP demonstration is designed to execute under the DS debugger on the VE_Cortex-A9x4 Bare Metal simulator. -Building the demonstration is easy; simply open the workspace file, select the -sample_threadx project, and select the build button. Next, expand the demo ThreadX -project folder in the Project Explorer window, right-click on the 'Cortex-A9x4_tx.launch' +Building the demonstration is easy; simply open the workspace file, select the +sample_threadx project, and select the build button. Next, expand the demo ThreadX +project folder in the Project Explorer window, right-click on the 'Cortex-A9x4_tx.launch' file, click 'Debug As', and then click 'Cortex-A9x4_tx' from the submenu. This will cause the -debugger to load the sample_threadx.axf ELF file and run to main. You are now ready +debugger to load the sample_threadx.axf ELF file and run to main. You are now ready to execute the ThreadX demonstration. 4. System Initialization -The entry point in ThreadX SMP for the Cortex-A9 using ARM tools is at label -"ENTRY". This is defined within the ARM compiler's startup code. In addition, -this is where all static and global pre-set C variable initialization processing +The entry point in ThreadX SMP for the Cortex-A9 using ARM tools is at label +"ENTRY". This is defined within the ARM compiler's startup code. In addition, +this is where all static and global pre-set C variable initialization processing takes place. -The ThreadX SMP tx_initialize_low_level.s file is responsible for determining the -first available RAM address for use by the application, which is supplied as the +The ThreadX SMP tx_initialize_low_level.s file is responsible for determining the +first available RAM address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 5. Register Usage and Stack Frames -The ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -78,39 +78,39 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 6. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make it run faster, you can change the build_threadx.bat file to -remove the -g option and enable all compiler optimizations. +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 7. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A9 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 7.1 Vector Area The Cortex-A9 vectors start at address zero. The demonstration system startup -Init area contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +Init area contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 8.2 IRQ ISRs @@ -121,12 +121,12 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 7.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in startup.s. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in startup.s. The following is the default IRQ handler defined in startup.s: EXPORT IRQ_Handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return IRQ_Handler PROC ; ; /* Jump to context save to save system context. */ @@ -134,7 +134,7 @@ IRQ_Handler PROC __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -146,12 +146,12 @@ __tx_irq_processing_return 7.3 FIQ Interrupts -By default, Cortex-A9 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, Cortex-A9 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.s. @@ -160,7 +160,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.s. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.s: @@ -183,29 +183,29 @@ __tx_fiq_processing_return: 8. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.s in the Integrator sub-directories. 9. Thumb/Cortex-A9 Mixed Mode -By default, ThreadX is setup for running in Cortex-A9 32-bit mode. This is -also true for the demonstration system. It is possible to build any -ThreadX file and/or the application in Thumb mode. If any Thumb code -is used the entire ThreadX source- both C and assembly - should be built +By default, ThreadX is setup for running in Cortex-A9 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. If any Thumb code +is used the entire ThreadX source- both C and assembly - should be built with the "-apcs /interwork" option. 10. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_initialize_low_level.s b/ports_smp/cortex_a9_smp/ac5/src/tx_initialize_low_level.s index cedbc1b3..23a5d804 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_initialize_low_level.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_initialize_low_level.s @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; @@ -41,47 +41,41 @@ ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_initialize_low_level SMP/Cortex-A9/AC5 */ -;/* 6.1 */ -;/* AUTHOR */ -;/* */ -;/* William E. Lamie, Microsoft Corporation */ -;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ -;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -;/* */ -;/**************************************************************************/ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level SMP/Cortex-A9/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) ;{ EXPORT _tx_initialize_low_level diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_context_restore.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_context_restore.s index 54d7df4b..b6c179cd 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_context_restore.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_context_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -63,44 +63,38 @@ SVC_MODE EQU 0x93 ; SVC mode ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_restore SMP/Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore SMP/Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -137,13 +131,13 @@ _tx_thread_context_restore ADD r3, r3, r12 ; Build array offset LDR r2, [r3, #0] ; Pickup system state SUB r2, r2, #1 ; Decrement the counter - STR r2, [r3, #0] ; Store the counter + STR r2, [r3, #0] ; Store the counter CMP r2, #0 ; Was this the first interrupt? BEQ __tx_thread_not_nested_restore ; If so, not a nested restore ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs @@ -155,7 +149,7 @@ _tx_thread_context_restore __tx_thread_not_nested_restore ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr[core]) && (_tx_thread_current_ptr[core] == _tx_thread_execute_ptr[core]) +; else if (((_tx_thread_current_ptr[core]) && (_tx_thread_current_ptr[core] == _tx_thread_execute_ptr[core]) ; || (_tx_thread_preempt_disable)) ; { ; @@ -346,7 +340,7 @@ __tx_thread_dont_save_ts ; ; /* Set bit indicating this thread is ready for execution. */ ; - LDR r2, [r0, #152] ; Pickup the ready bit + LDR r2, [r0, #152] ; Pickup the ready bit ORR r2, r2, #0x8000 ; Set ready bit (bit 15) STR r2, [r0, #152] ; Make this thread ready for executing again DMB ; Ensure that accesses to shared resource have completed diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_context_save.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_context_save.s index 9d1d0e9b..a0e2a5e6 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_context_save.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -39,43 +39,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_context_save SMP/Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save SMP/Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -90,13 +84,13 @@ _tx_thread_context_save ; if (_tx_thread_system_state[core]++) ; { ; - STMDB sp!, {r0-r3} ; Save some working registers + STMDB sp!, {r0-r3} ; Save some working registers ; ; /* Save the rest of the scratch registers on the stack and return to the ; calling ISR. */ ; MRS r0, SPSR ; Pickup saved SPSR - SUB lr, lr, #4 ; Adjust point of interrupt + SUB lr, lr, #4 ; Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} ; Store other registers ; IF :DEF:TX_ENABLE_FIQ_SUPPORT @@ -133,7 +127,7 @@ _tx_thread_context_save POP {r12, lr} ; Recover ISR lr & r12 ENDIF - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; __tx_thread_not_nested_save ; } @@ -148,7 +142,7 @@ __tx_thread_not_nested_save ADD r1, r1, r12 ; Build index into current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Save the current stack pointer in the thread's control block. */ @@ -168,7 +162,7 @@ __tx_thread_not_nested_save POP {r12, lr} ; Recover ISR lr & r12 ENDIF - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ; else @@ -178,7 +172,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit @@ -193,7 +187,7 @@ __tx_thread_idle_system_save ENDIF ADD sp, sp, #32 ; Recover saved registers - B __tx_irq_processing_return ; Continue IRQ processing + B __tx_irq_processing_return ; Continue IRQ processing ; ; } ;} diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_control.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_control.s index 6b1c707e..3314a17d 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_control.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_control.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -36,42 +36,36 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_control SMP/Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control SMP/Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_disable.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_disable.s index d6489ae9..f049bb63 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_disable.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_disable.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,41 +29,35 @@ ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_disable SMP/Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable SMP/Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for disabling interrupts */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(void) @@ -80,7 +74,7 @@ _tx_thread_interrupt_disable IF :DEF:TX_ENABLE_FIQ_SUPPORT CPSID if ; Disable IRQ and FIQ ELSE - CPSID i ; Disable IRQ + CPSID i ; Disable IRQ ENDIF IF {INTER} = {TRUE} diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_restore.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_restore.s index 0253399f..9624a3eb 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_restore.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_restore.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -29,42 +29,36 @@ ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_interrupt_restore SMP/Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore SMP/Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function is responsible for restoring interrupts to the state */ ;/* returned by a previous _tx_thread_interrupt_disable call. */ -;/* */ -;/* INPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_irq_nesting_end.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_irq_nesting_end.s index e42fc534..afe2dd02 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_irq_nesting_end.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_irq_nesting_end.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -34,56 +34,50 @@ DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts ELSE DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts ENDIF -MODE_MASK EQU 0x1F ; Mode mask +MODE_MASK EQU 0x1F ; Mode mask IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_end SMP/Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end SMP/Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -;/* processing from system mode back to IRQ mode prior to the ISR */ -;/* calling _tx_thread_context_restore. Note that this function */ -;/* assumes the system stack pointer is in the same position after */ -;/* nesting start function was called. */ -;/* */ -;/* This function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts disabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) @@ -94,7 +88,7 @@ _tx_thread_irq_nesting_end MRS r0, CPSR ; Pickup the CPSR ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value MSR CPSR_c, r0 ; Disable interrupts - LDMIA sp!, {lr, r1} ; Pickup saved lr (and r1 throw-away for + LDMIA sp!, {lr, r1} ; Pickup saved lr (and r1 throw-away for ; 8-byte alignment logic) BIC r0, r0, #MODE_MASK ; Clear mode bits ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_irq_nesting_start.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_irq_nesting_start.s index 3eff0a0a..67c0d2d2 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_irq_nesting_start.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_irq_nesting_start.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,48 +35,42 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_irq_nesting_start SMP/Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start SMP/Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is called by the application from IRQ mode after */ -;/* _tx_thread_context_save has been called and switches the IRQ */ -;/* processing to the system mode so nested IRQ interrupt processing */ -;/* is possible (system mode has its own "lr" register). Note that */ -;/* this function assumes that the system mode stack pointer was setup */ -;/* during low-level initialization (tx_initialize_low_level.s). */ -;/* */ -;/* This function returns with IRQ interrupts enabled. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_schedule.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_schedule.s index 94b69738..63e7492c 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_schedule.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_schedule.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -40,45 +40,39 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule SMP/Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule SMP/Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -122,7 +116,7 @@ _tx_thread_schedule ; ; } ; while(_tx_thread_execute_ptr[core] == TX_NULL); -; +; ; /* Get the lock for accessing the thread's ready bit. */ ; MOV r2, #172 ; Build offset to the lock @@ -185,7 +179,7 @@ _tx_thread_ready_for_execution MOV r1, #0 ; Build clear value STR r1, [r2, #0] ; Clear current thread pointer - LDR r1, [r0, #152] ; Pickup the ready bit + LDR r1, [r0, #152] ; Pickup the ready bit ORR r1, r1, #0x8000 ; Set ready bit (bit 15) STR r1, [r0, #152] ; Make this thread ready for executing again DMB ; Ensure that accesses to shared resource have completed @@ -205,7 +199,7 @@ _execute_pointer_did_not_change ; /* Setup time-slice, if present. */ ; _tx_timer_time_slice[core] = _tx_thread_current_ptr[core] -> tx_thread_time_slice; ; - LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice ; variable ADD r2, r2, r12 ; Build index into the time-slice array LDR sp, [r0, #8] ; Switch stack pointers @@ -241,7 +235,7 @@ _execute_pointer_did_not_change _tx_skip_interrupt_vfp_restore ENDIF LDMIA sp!, {r0-r12, lr, pc}^ ; Return to point of thread interrupt - + _tx_solicited_return IF {TARGET_FPU_VFP} = {TRUE} MSR CPSR_cxsf, r5 ; Recover CPSR diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_core_get.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_core_get.s index 721d5ca3..fa60e54e 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_core_get.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_core_get.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -32,41 +32,35 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_smp_core_get SMP/Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_core_get SMP/Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function gets the currently running core number and returns it.*/ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* Core ID */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX Source */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function gets the currently running core number and returns it.*/ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* Core ID */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_core_get @@ -81,4 +75,4 @@ _tx_thread_smp_core_get ENDIF END - + diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_core_preempt.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_core_preempt.s index a79a172b..fe32034b 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_core_preempt.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_core_preempt.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -34,45 +34,39 @@ AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_smp_core_preempt SMP/Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_core_preempt SMP/Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function preempts the specified core in situations where the */ -;/* thread corresponding to this core is no longer ready or when the */ -;/* core must be used for a higher-priority thread. If the specified is */ -;/* the current core, this processing is skipped since the will give up */ -;/* control subsequently on its own. */ -;/* */ -;/* INPUT */ -;/* */ -;/* core The core to preempt */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX Source */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function preempts the specified core in situations where the */ +;/* thread corresponding to this core is no longer ready or when the */ +;/* core must be used for a higher-priority thread. If the specified is */ +;/* the current core, this processing is skipped since the will give up */ +;/* control subsequently on its own. */ +;/* */ +;/* INPUT */ +;/* */ +;/* core The core to preempt */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_core_preempt @@ -82,11 +76,11 @@ _tx_thread_smp_core_preempt ; ; /* Place call to send inter-processor interrupt here! */ ; - DSB ; - MOV r1, #1 ; Build parameter list - LSL r1, r1, r0 ; - MOV r0, #0 ; - MOV r2, #0 ; + DSB ; + MOV r1, #1 ; Build parameter list + LSL r1, r1, r0 ; + MOV r0, #0 ; + MOV r2, #0 ; BL send_sgi ; Make call to send inter-processor interrupt LDMIA sp!, {lr, r4} ; Recover lr register and r4 @@ -97,4 +91,4 @@ _tx_thread_smp_core_preempt ENDIF END - + diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_current_state_get.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_current_state_get.s index 64d27e5b..c24221be 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_current_state_get.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_current_state_get.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -34,41 +34,35 @@ AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_smp_current_state_get SMP/Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_current_state_get SMP/Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is gets the current state of the calling core. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX Components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is gets the current state of the calling core. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Components */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_current_state_get @@ -91,7 +85,7 @@ _tx_thread_smp_current_state_get LDR r1, =_tx_thread_system_state ; Pickup start of the current state array ADD r1, r1, r2 ; Build index into the current state array LDR r0, [r1] ; Pickup state for this core - MSR CPSR_c, r3 ; Restore CPSR + MSR CPSR_c, r3 ; Restore CPSR IF {INTER} = {TRUE} BX lr ; Return to caller ELSE diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_current_thread_get.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_current_thread_get.s index 1af00b41..7e69cc77 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_current_thread_get.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_current_thread_get.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -34,41 +34,35 @@ AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_smp_current_thread_get SMP/Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_current_thread_get SMP/Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is gets the current thread of the calling core. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX Components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is gets the current thread of the calling core. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Components */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_current_thread_get @@ -91,7 +85,7 @@ _tx_thread_smp_current_thread_get LDR r1, =_tx_thread_current_ptr ; Pickup start of the current thread array ADD r1, r1, r2 ; Build index into the current thread array LDR r0, [r1] ; Pickup current thread for this core - MSR CPSR_c, r3 ; Restore CPSR + MSR CPSR_c, r3 ; Restore CPSR IF {INTER} = {TRUE} BX lr ; Return to caller ELSE diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_initialize_wait.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_initialize_wait.s index f3485825..b37bfb00 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_initialize_wait.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_initialize_wait.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -37,43 +37,37 @@ AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_smp_initialize_wait SMP/Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_initialize_wait SMP/Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is the place where additional cores wait until */ -;/* initialization is complete before they enter the thread scheduling */ -;/* loop. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Hardware */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is the place where additional cores wait until */ +;/* initialization is complete before they enter the thread scheduling */ +;/* loop. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Hardware */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_initialize_wait @@ -93,7 +87,7 @@ _tx_thread_smp_initialize_wait AND r10, r10, #0x03 ; Mask off, leaving the CPU ID field LSL r10, r10, #2 ; Build offset to array indexes ; -; /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release +; /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release ; flag. */ ; LDR r3, =_tx_thread_system_state ; Build address of system state variable @@ -111,10 +105,10 @@ wait_for_initialize wait_for_release LDR r3, [r2] ; Pickup the flag CMP r3, #0 ; Is it set? - BEQ wait_for_release ; Wait for the flag to be set + BEQ wait_for_release ; Wait for the flag to be set ; ; /* Core 0 has released this core. */ -; +; ; /* Clear this core's system state variable. */ ; LDR r3, =_tx_thread_system_state ; Build address of system state variable @@ -124,7 +118,7 @@ wait_for_release ; ; /* Now wait for core 0 to finish it's initialization. */ ; - LDR r3, =_tx_thread_system_state ; Build address of system state variable of logical 0 + LDR r3, =_tx_thread_system_state ; Build address of system state variable of logical 0 core_0_wait_loop LDR r2, [r3] ; Pickup system state for core 0 diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_low_level_initialize.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_low_level_initialize.s index 11117444..99fd21a7 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_low_level_initialize.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_low_level_initialize.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -32,42 +32,36 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_smp_low_level_initialize SMP/Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_low_level_initialize SMP/Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function performs low-level initialization of the booting */ -;/* core. */ -;/* */ -;/* INPUT */ -;/* */ -;/* number_of_cores Number of cores */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_high_level ThreadX high-level init */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function performs low-level initialization of the booting */ +;/* core. */ +;/* */ +;/* INPUT */ +;/* */ +;/* number_of_cores Number of cores */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_high_level ThreadX high-level init */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_low_level_initialize diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_protect.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_protect.s index 066d84b4..1f2330d9 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_protect.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_protect.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -45,43 +45,37 @@ AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_smp_protect SMP/Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_protect SMP/Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function gets protection for running inside the ThreadX */ -;/* source. This is acomplished by a combination of a test-and-set */ -;/* flag and periodically disabling interrupts. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* Previous Status Register */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX Source */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function gets protection for running inside the ThreadX */ +;/* source. This is acomplished by a combination of a test-and-set */ +;/* flag and periodically disabling interrupts. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* Previous Status Register */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_protect @@ -368,4 +362,4 @@ _return ENDIF END - + diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_protection_wait_list_macros.h index 192df07b..fec51581 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,10 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_time_get.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_time_get.s index cb615404..5b67b283 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_time_get.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_time_get.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -33,42 +33,36 @@ AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_smp_time_get SMP/Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_time_get SMP/Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function gets the global time value that is used for debug */ -;/* information and event tracing. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* 32-bit time stamp */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX Source */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function gets the global time value that is used for debug */ +;/* information and event tracing. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* 32-bit time stamp */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_time_get @@ -84,4 +78,4 @@ _tx_thread_smp_time_get ENDIF END - + diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_unprotect.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_unprotect.s index 10415473..ed3fae48 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_unprotect.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_unprotect.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread - Low Level SMP Support */ ;/** */ @@ -37,44 +37,38 @@ AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_smp_unprotect SMP/Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_unprotect SMP/Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function releases previously obtained protection. The supplied */ -;/* previous SR is restored. If the value of _tx_thread_system_state */ -;/* and _tx_thread_preempt_disable are both zero, then multithreading */ -;/* is enabled as well. */ -;/* */ -;/* INPUT */ -;/* */ -;/* Previous Status Register */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX Source */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function releases previously obtained protection. The supplied */ +;/* previous SR is restored. If the value of _tx_thread_system_state */ +;/* and _tx_thread_preempt_disable are both zero, then multithreading */ +;/* is enabled as well. */ +;/* */ +;/* INPUT */ +;/* */ +;/* Previous Status Register */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_unprotect @@ -129,7 +123,7 @@ _tx_thread_smp_unprotect ENDIF _still_protected - MSR CPSR_c, r0 ; Restore CPSR + MSR CPSR_c, r0 ; Restore CPSR IF {INTER} = {TRUE} BX lr ; Return to caller @@ -138,4 +132,4 @@ _still_protected ENDIF END - + diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_stack_build.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_stack_build.s index b73949d8..95957cb4 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_stack_build.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_stack_build.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -41,44 +41,38 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ; ; AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_stack_build SMP/Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build SMP/Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function builds a stack frame on the supplied thread's stack. */ ;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ ;/* thread_ptr Pointer to thread control blk */ ;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -86,10 +80,10 @@ THUMB_BIT EQU 0x20 ; Thumb-bit EXPORT _tx_thread_stack_build _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-A9 should look like the following after it is built: -; +; ; Stack Top: 1 Interrupt stack frame type ; CPSR Initial value for CPSR ; a1 (r0) Initial value for a1 diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_system_return.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_system_return.s index 526c9deb..f03fc6fe 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_system_return.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_system_return.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -35,50 +35,44 @@ IMPORT _tx_thread_preempt_disable IMPORT _tx_thread_smp_protection IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY - IMPORT _tx_execution_thread_exit + IMPORT _tx_execution_thread_exit ENDIF ; ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_system_return SMP/Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return SMP/Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -112,7 +106,7 @@ _tx_skip_solicited_vfp_save MOV r4, #0 ; Build a solicited stack type MRS r5, CPSR ; Pickup the CPSR STMDB sp!, {r4-r5} ; Save type and CPSR -; +; ; /* Lockout interrupts. */ ; IF :DEF:TX_ENABLE_FIQ_SUPPORT @@ -184,8 +178,8 @@ __tx_thread_dont_save_ts CMP r0, r2 ; Is it the same as the current thread? __error_loop BNE __error_loop ; If not, we have a problem!! - ENDIF - + ENDIF + LDR r1, =_tx_thread_preempt_disable ; Build address to preempt disable flag MOV r2, #0 ; Build clear value STR r2, [r1, #0] ; Clear preempt disable flag diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_vectored_context_save.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_vectored_context_save.s index 986828a4..8102e78b 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_vectored_context_save.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_vectored_context_save.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -38,43 +38,37 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_vectored_context_save SMP/Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save SMP/Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) @@ -144,7 +138,7 @@ __tx_thread_not_nested_save ADD r1, r1, r12 ; Build index into current thread ptr LDR r0, [r1, #0] ; Pickup current thread pointer CMP r0, #0 ; Is it NULL? - BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in ; scheduling loop - nothing needs saving! ; ; /* Note: Minimal context of interrupted thread is already saved. */ @@ -180,7 +174,7 @@ __tx_thread_idle_system_save ; ; /* Interrupt occurred in the scheduling loop. */ ; -; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; /* Not much to do here, just adjust the stack pointer, and return to IRQ ; processing. */ ; MOV r10, #0 ; Clear stack limit diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_timer_interrupt.s b/ports_smp/cortex_a9_smp/ac5/src/tx_timer_interrupt.s index 8be10421..297bc6be 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_timer_interrupt.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_timer_interrupt.s @@ -1,18 +1,18 @@ ;/*************************************************************************** -; * Copyright (c) 2024 Microsoft Corporation -; * +; * Copyright (c) 2024 Microsoft Corporation +; * ; * This program and the accompanying materials are made available under the ; * terms of the MIT License which is available at ; * https://opensource.org/licenses/MIT. -; * +; * ; * SPDX-License-Identifier: MIT ; **************************************************************************/ ; ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ @@ -49,48 +49,42 @@ ; AREA ||.text||, CODE, READONLY PRESERVE8 -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_timer_interrupt SMP/Cortex-A9/AC5 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt SMP/Cortex-A9/AC5 */ ;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* _tx_thread_smp_protect Get SMP protection */ -;/* _tx_thread_smp_unprotect Releast SMP protection */ -;/* _tx_timer_expiration_process Timer expiration processing */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ -;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* _tx_thread_smp_protect Get SMP protection */ +;/* _tx_thread_smp_unprotect Releast SMP protection */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -199,7 +193,7 @@ __tx_timer_done __tx_timer_dont_activate ; ; /* Call time-slice processing. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing ; diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/MP_GIC.S b/ports_smp/cortex_a9_smp/gnu/example_build/MP_GIC.S index 2ff179fb..a3274f21 100644 --- a/ports_smp/cortex_a9_smp/gnu/example_build/MP_GIC.S +++ b/ports_smp/cortex_a9_smp/gnu/example_build/MP_GIC.S @@ -3,7 +3,7 @@ // // Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/MP_GIC.h b/ports_smp/cortex_a9_smp/gnu/example_build/MP_GIC.h index 1d047611..42a96c3d 100644 --- a/ports_smp/cortex_a9_smp/gnu/example_build/MP_GIC.h +++ b/ports_smp/cortex_a9_smp/gnu/example_build/MP_GIC.h @@ -4,7 +4,7 @@ // // Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/MP_Mutexes.S b/ports_smp/cortex_a9_smp/gnu/example_build/MP_Mutexes.S index 771e3321..75bde148 100644 --- a/ports_smp/cortex_a9_smp/gnu/example_build/MP_Mutexes.S +++ b/ports_smp/cortex_a9_smp/gnu/example_build/MP_Mutexes.S @@ -3,13 +3,13 @@ // // Copyright (c) 2011-2017 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ .text - .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame //NOTES diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/MP_Mutexes.h b/ports_smp/cortex_a9_smp/gnu/example_build/MP_Mutexes.h index e410677b..dc2cf932 100644 --- a/ports_smp/cortex_a9_smp/gnu/example_build/MP_Mutexes.h +++ b/ports_smp/cortex_a9_smp/gnu/example_build/MP_Mutexes.h @@ -3,7 +3,7 @@ // // Copyright (c) 2011-2014 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/MP_PrivateTimer.S b/ports_smp/cortex_a9_smp/gnu/example_build/MP_PrivateTimer.S index 2077d917..58e5afd4 100644 --- a/ports_smp/cortex_a9_smp/gnu/example_build/MP_PrivateTimer.S +++ b/ports_smp/cortex_a9_smp/gnu/example_build/MP_PrivateTimer.S @@ -93,7 +93,7 @@ get_private_timer_count: LDR r0, [r0, #0x604] // Read count register BX lr - + // ------------------------------------------------------------ // void clear_private_timer_irq(void) diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/MP_SCU.S b/ports_smp/cortex_a9_smp/gnu/example_build/MP_SCU.S index bd4c667b..be6d8b19 100644 --- a/ports_smp/cortex_a9_smp/gnu/example_build/MP_SCU.S +++ b/ports_smp/cortex_a9_smp/gnu/example_build/MP_SCU.S @@ -4,7 +4,7 @@ // // Copyright (c) 2011-2015 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/MP_SCU.h b/ports_smp/cortex_a9_smp/gnu/example_build/MP_SCU.h index af4ccfb8..b20b3d0f 100644 --- a/ports_smp/cortex_a9_smp/gnu/example_build/MP_SCU.h +++ b/ports_smp/cortex_a9_smp/gnu/example_build/MP_SCU.h @@ -4,7 +4,7 @@ // // Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/sample_threadx.c b/ports_smp/cortex_a9_smp/gnu/example_build/sample_threadx.c index 1b6df7c2..5c1f4a16 100644 --- a/ports_smp/cortex_a9_smp/gnu/example_build/sample_threadx.c +++ b/ports_smp/cortex_a9_smp/gnu/example_build/sample_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -63,7 +63,7 @@ UCHAR event_buffer[65536]; int main(void) { - + /* Enter ThreadX. */ tx_kernel_enter(); @@ -91,41 +91,41 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); - + /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -133,23 +133,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -252,11 +252,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -315,7 +315,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -368,7 +368,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/sample_threadx.ld b/ports_smp/cortex_a9_smp/gnu/example_build/sample_threadx.ld index fb1ca03c..6b4f194a 100644 --- a/ports_smp/cortex_a9_smp/gnu/example_build/sample_threadx.ld +++ b/ports_smp/cortex_a9_smp/gnu/example_build/sample_threadx.ld @@ -1,7 +1,7 @@ /* Linker script to place sections and symbol values. * It references following symbols, which must be defined in code: * Vectors : Entry point - * + * * It defines following symbols, which code can use without definition: * __code_start * __exidx_start @@ -170,7 +170,7 @@ SECTIONS __irq_stack = .; _stack_init_irq = .; } - + _end = .; .pagetable 0x80100000 (NOLOAD): diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/startup.S b/ports_smp/cortex_a9_smp/gnu/example_build/startup.S index 65b1ba90..365e2858 100644 --- a/ports_smp/cortex_a9_smp/gnu/example_build/startup.S +++ b/ports_smp/cortex_a9_smp/gnu/example_build/startup.S @@ -213,7 +213,7 @@ by_pass: // MRC p15, 0, r0, c0, c0, 5 // Read CPU ID register // ANDS r0, r0, #0x03 // Mask off, leaving the CPU ID field // BNE by_pass2 -// +// // MOV r0, #0x04 // Code for SYS_WRITE0 // LDR r1, =irq_handler_message1 // SVC 0x123456 @@ -587,7 +587,7 @@ primaryCPUInit: MOV r0, #0x1F BL setPriorityMask // Set priority mask (local) - // [EL] Change start - don't enable interrupts here! + // [EL] Change start - don't enable interrupts here! //CPSIE i // Clear CPSR I bit // [EL] Change end @@ -606,7 +606,7 @@ primaryCPUInit: MOV r1, #0x0 BL init_private_timer BL start_private_timer - + // // Enable receipt of SGI 0 // ------------------------ diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/tx_initialize_low_level.S b/ports_smp/cortex_a9_smp/gnu/example_build/tx_initialize_low_level.S index 44bb0bc9..9b09275a 100644 --- a/ports_smp/cortex_a9_smp/gnu/example_build/tx_initialize_low_level.S +++ b/ports_smp/cortex_a9_smp/gnu/example_build/tx_initialize_low_level.S @@ -1,10 +1,10 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @@ -43,52 +43,46 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_initialize_low_level SMP/Cortex-A9/GNU */ -@/* 6.1 */ -@/* AUTHOR */ -@/* */ -@/* William E. Lamie, Microsoft Corporation */ -@/* */ -@/* DESCRIPTION */ -@/* */ -@/* This function is responsible for any low-level processor */ -@/* initialization, including setting up interrupt vectors, setting */ -@/* up a periodic timer interrupt source, saving the system stack */ -@/* pointer for use in ISR processing later, and finding the first */ -@/* available RAM memory address for tx_application_define. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_initialize_kernel_enter ThreadX entry function */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -@/* */ -@/**************************************************************************/ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level SMP/Cortex-A9/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* */ +@/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) @{ .global _tx_initialize_low_level .type _tx_initialize_low_level,function -_tx_initialize_low_level: +_tx_initialize_low_level: @ @ /* Save the first available memory address. */ @ _tx_initialize_unused_memory = (VOID_PTR) _end; diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/v7.S b/ports_smp/cortex_a9_smp/gnu/example_build/v7.S index 67ddb163..dbb4552f 100644 --- a/ports_smp/cortex_a9_smp/gnu/example_build/v7.S +++ b/ports_smp/cortex_a9_smp/gnu/example_build/v7.S @@ -3,7 +3,7 @@ // // Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ @@ -20,7 +20,7 @@ .global enableInterrupts // void enableInterrupts(void) .type enableInterrupts, "function" - .cfi_startproc + .cfi_startproc enableInterrupts: CPSIE i BX lr @@ -30,7 +30,7 @@ enableInterrupts: .global disableInterrupts // void disableInterrupts(void) .type disableInterrupts, "function" - .cfi_startproc + .cfi_startproc disableInterrupts: CPSID i BX lr @@ -122,7 +122,7 @@ clean_dcache_skip: CMP r3, r10 BGT clean_dcache_loop1 -clean_dcache_finished: +clean_dcache_finished: POP {r4-r12} BX lr @@ -180,7 +180,7 @@ clean_invalidate_dcache_skip: CMP r3, r10 BGT clean_invalidate_dcache_loop1 -clean_invalidate_dcache_finished: +clean_invalidate_dcache_finished: POP {r4-r12} BX lr diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/v7.h b/ports_smp/cortex_a9_smp/gnu/example_build/v7.h index 5a08b43f..c18b945c 100644 --- a/ports_smp/cortex_a9_smp/gnu/example_build/v7.h +++ b/ports_smp/cortex_a9_smp/gnu/example_build/v7.h @@ -4,7 +4,7 @@ // // Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved. // Use, modification and redistribution of this file is subject to your possession of a -// valid End User License Agreement for the Arm Product of which these examples are part of +// valid End User License Agreement for the Arm Product of which these examples are part of // and your compliance with all applicable terms and conditions of such licence agreement. // ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a9_smp/gnu/inc/tx_port.h index 8d4b00da..a35403c7 100644 --- a/ports_smp/cortex_a9_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a9_smp/gnu/inc/tx_port.h @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** ThreadX Component */ /** */ /** Port Specific */ @@ -20,11 +21,11 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* PORT SPECIFIC C INFORMATION RELEASE */ -/* */ -/* tx_port.h SMP/Cortex-A9/GNU */ +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h SMP/Cortex-A9/GNU */ /* 6.1.6 */ /* */ /* AUTHOR */ @@ -32,24 +33,15 @@ /* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ -/* */ -/* This file contains data type definitions that make the ThreadX */ -/* real-time kernel function identically on a variety of different */ -/* processor architectures. For example, the size or number of bits */ -/* in an "int" data type vary between microprocessor architectures and */ -/* even C compilers for the same microprocessor. ThreadX does not */ -/* directly use native C data types. Instead, ThreadX creates its */ -/* own special types that can be mapped to actual data types by this */ -/* file to guarantee consistency in the interface and functionality. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ /* */ /**************************************************************************/ @@ -75,12 +67,12 @@ /* Define ThreadX SMP initialization macro. */ -#define TX_PORT_SPECIFIC_PRE_INITIALIZATION +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION /* Define ThreadX SMP pre-scheduler initialization. */ -#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION /* Enable the inter-core interrupt logic. */ @@ -120,7 +112,7 @@ #ifdef TX_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in tx_user.h. The defines in this file may +/* Yes, include the user defines in tx_user.h. The defines in this file may alternately be defined on the command line. */ #include "tx_user.h" @@ -133,7 +125,7 @@ #include -/* Define ThreadX basic types for this port. */ +/* Define ThreadX basic types for this port. */ #define VOID void typedef char CHAR; @@ -169,12 +161,12 @@ typedef unsigned short USHORT; #define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ #endif -#ifndef TX_TIMER_THREAD_PRIORITY -#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ #endif -/* Define various constants for the ThreadX ARM port. */ +/* Define various constants for the ThreadX ARM port. */ #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ @@ -184,8 +176,8 @@ typedef unsigned short USHORT; #define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ -/* Define the clock source for trace event entry time stamp. The following two item are port specific. - For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock source constants would be: #define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) @@ -243,7 +235,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #endif -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING define is negated, thereby forcing the stack fill which is necessary for the stack checking @@ -257,13 +249,13 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the TX_THREAD control block extensions for this port. The main reason - for the multiple macros is so that backward compatibility can be maintained with + for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 -#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ @@ -277,11 +269,11 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_TIMER_EXTENSION -/* Define the user extension field of the thread control block. Nothing +/* Define the user extension field of the thread control block. Nothing additional is needed for this port so it is defined as white space. */ #ifndef TX_THREAD_USER_EXTENSION -#define TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION #endif @@ -289,8 +281,8 @@ ULONG _tx_misra_time_stamp_get(VOID); tx_thread_shell_entry, and tx_thread_terminate. */ -#define TX_THREAD_CREATE_EXTENSION(thread_ptr) -#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) #define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) @@ -316,8 +308,8 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) #define TX_TIMER_DELETE_EXTENSION(timer_ptr) -/* Determine if the ARM architecture has the CLZ instruction. This is available on - architectures v5 and above. If available, redefine the macro for calculating the +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ #ifndef TX_DISABLE_INLINE @@ -328,7 +320,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ asm volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); \ - b = 31 - b; + b = 31 - b; #endif #endif #endif @@ -344,22 +336,22 @@ struct TX_THREAD_STRUCT; typedef struct TX_THREAD_SMP_PROTECT_STRUCT { ULONG tx_thread_smp_protect_in_force; - struct TX_THREAD_STRUCT * + struct TX_THREAD_STRUCT * tx_thread_smp_protect_thread; ULONG tx_thread_smp_protect_core; ULONG tx_thread_smp_protect_count; - + /* Implementation specific information follows. */ - + ULONG tx_thread_smp_protect_get_caller; ULONG tx_thread_smp_protect_sr; ULONG tx_thread_smp_protect_release_caller; } TX_THREAD_SMP_PROTECT; -/* Define ThreadX interrupt lockout and restore macros for protection on - access of critical kernel information. The restore interrupt macro must - restore the interrupt posture of the running thread prior to the value +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value present prior to the disable macro. In most cases, the save area macro is used to define a local function save area for the disable and restore macros. */ @@ -393,8 +385,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX SMP/Cortex-A9/GNU Version Version 6.4.2 *"; +CHAR _tx_version_id[] = + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP/Cortex-A9/GNU Version Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a9_smp/gnu/readme_threadx.txt b/ports_smp/cortex_a9_smp/gnu/readme_threadx.txt index d385d559..1c2a7931 100644 --- a/ports_smp/cortex_a9_smp/gnu/readme_threadx.txt +++ b/ports_smp/cortex_a9_smp/gnu/readme_threadx.txt @@ -4,16 +4,16 @@ 1. Building the ThreadX run-time Library -First make sure you are in the "example_build" directory. Also, make sure that -you have setup your path and other environment variables necessary for the GNU -development environment. +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the GNU +development environment. -At this point you may run the build_threadx.bat batch file. This will build the -ThreadX run-time environment in the "example_build" directory. +At this point you may run the build_threadx.bat batch file. This will build the +ThreadX run-time environment in the "example_build" directory. -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. @@ -21,49 +21,49 @@ application in order to use ThreadX. The ThreadX demonstration is designed to execute under the ARM Cortex-A9x4 FVP. -Building the demonstration is easy; simply execute the build_threadx_sample.bat -batch file while inside the "example_build" directory. +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with TX.A. The resulting file DEMO is a binary file +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with TX.A. The resulting file DEMO is a binary file that can be downloaded and executed. 3. System Initialization -The entry point in ThreadX for the Cortex-A9 using GNU tools is at label +The entry point in ThreadX for the Cortex-A9 using GNU tools is at label Reset_Handler in startup.s. After the basic core initialization is complete, -control will transfer to __main, which is where all static and global pre-set +control will transfer to __main, which is where all static and global pre-set C variable initialization processing takes place. -The ThreadX tx_initialize_low_level.s file is responsible for setting up -various system data structures, the vector area, and a periodic timer interrupt -source. By default, the vector area is defined to be located in the Init area, -which is defined at the top of tx_initialize_low_level.s. This area is typically -located at 0. In situations where this is impossible, the vectors at the beginning +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. By default, the vector area is defined to be located in the Init area, +which is defined at the top of tx_initialize_low_level.s. This area is typically +located at 0. In situations where this is impossible, the vectors at the beginning of the Init area should be copied to address 0. This is also where initialization of a periodic timer interrupt source should take place. -In addition, _tx_initialize_low_level determines the first available -address for use by the application, which is supplied as the sole input +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input parameter to your application definition function, tx_application_define. 4. Register Usage and Stack Frames -The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch -registers for each function. All other registers used by a C function must -be preserved by the function. ThreadX takes advantage of this in situations -where a context switch happens as a result of making a ThreadX service call -(which is itself a C function). In such cases, the saved context of a thread +The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -81,39 +81,39 @@ associated thread control block TX_THREAD. 0x20 r6 (v3) r10 (v7) 0x24 r7 (v4) r11 (fp) 0x28 r8 (v5) r14 (lr) - 0x2C r9 (v6) - 0x30 r10 (v7) - 0x34 r11 (fp) - 0x38 r12 (ip) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) 0x3C r14 (lr) - 0x40 PC + 0x40 PC 5. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some -performance. To make it run faster, you can change the build_threadx.bat file to -remove the -g option and enable all compiler optimizations. +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. 6. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for Cortex-A9 -targets. There are a certain set of requirements that are defined in the +targets. There are a certain set of requirements that are defined in the following sub-sections: 6.1 Vector Area The Cortex-A9 vectors start at address zero. The demonstration system startup -Init area contains the vectors and is loaded at address zero. On actual -hardware platforms, this area might have to be copied to address 0. +Init area contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. 6.2 IRQ ISRs @@ -124,12 +124,12 @@ IRQ interrupts. The following sub-sections define the IRQ capabilities. 6.2.1 Standard IRQ ISRs -The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ -interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following is the default IRQ handler defined in tx_initialize_low_level.s: EXPORT __tx_irq_handler - EXPORT __tx_irq_processing_return + EXPORT __tx_irq_processing_return __tx_irq_handler ; ; /* Jump to context save to save system context. */ @@ -137,7 +137,7 @@ __tx_irq_handler __tx_irq_processing_return ; ; /* At this point execution is still in the IRQ mode. The CPSR, point of -; interrupt, and all C scratch registers are available for use. Note +; interrupt, and all C scratch registers are available for use. Note ; that IRQ interrupts are still disabled upon return from the context ; save function. */ ; @@ -149,12 +149,12 @@ __tx_irq_processing_return 6.3 FIQ Interrupts -By default, Cortex-A9 FIQ interrupts are left alone by ThreadX. Of course, this -means that the application is fully responsible for enabling the FIQ interrupt -and saving/restoring any registers used in the FIQ ISR processing. To globally -enable FIQ interrupts, the application should enable FIQ interrupts at the -beginning of each thread or before any threads are created in tx_application_define. -In addition, the application must ensure that no ThreadX service calls are made +By default, Cortex-A9 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made from default FIQ ISRs, which is located in tx_initialize_low_level.s. @@ -163,7 +163,7 @@ from default FIQ ISRs, which is located in tx_initialize_low_level.s. Full ThreadX management of FIQ interrupts is provided if the ThreadX sources are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built this way, the FIQ interrupt handlers are very similar to the IRQ interrupt -handlers defined previously. The following is default FIQ handler +handlers defined previously. The following is default FIQ handler defined in tx_initialize_low_level.s: @@ -186,29 +186,29 @@ __tx_fiq_processing_return: 7. ThreadX Timer Interrupt -ThreadX requires a periodic interrupt source to manage all time-slicing, -thread sleeps, timeouts, and application timers. Without such a timer +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer interrupt source, these services are not functional. However, all other ThreadX services are operational without a periodic timer source. -To add the timer interrupt processing, simply make a call to +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ processing. An example of this can be found in the file tx_initialize_low_level.s in the Integrator sub-directories. 8. Thumb/Cortex-A9 Mixed Mode -By default, ThreadX is setup for running in Cortex-A9 32-bit mode. This is -also true for the demonstration system. It is possible to build any -ThreadX file and/or the application in Thumb mode. If any Thumb code -is used the entire ThreadX source- both C and assembly - should be built +By default, ThreadX is setup for running in Cortex-A9 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. If any Thumb code +is used the entire ThreadX source- both C and assembly - should be built with the "-apcs /interwork" option. 9. VFP Support By default, VFP support is disabled for each thread. If saving the context of the VFP registers -is needed, the following API call must be made from the context of the application thread - before +is needed, the following API call must be made from the context of the application thread - before the VFP usage: void tx_thread_vfp_enable(void); diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_context_restore.S index 31ad1ed4..2fbf25fd 100644 --- a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_context_restore.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -64,51 +64,45 @@ SVC_MODE = 0x93 @ SVC mode .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_context_restore SMP/Cortex-A9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore SMP/Cortex-A9/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function restores the interrupt context if it is processing a */ -@/* nested interrupt. If not, it returns to the interrupt thread if no */ -@/* preemption is necessary. Otherwise, if preemption is necessary or */ -@/* if no thread was running, the function returns to the scheduler. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling routine */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs Interrupt Service Routines */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) @{ .global _tx_thread_context_restore .type _tx_thread_context_restore,function -_tx_thread_context_restore: +_tx_thread_context_restore: @ @ /* Lockout interrupts. */ @ @@ -139,13 +133,13 @@ _tx_thread_context_restore: ADD r3, r3, r12 @ Build array offset LDR r2, [r3, #0] @ Pickup system state SUB r2, r2, #1 @ Decrement the counter - STR r2, [r3, #0] @ Store the counter + STR r2, [r3, #0] @ Store the counter CMP r2, #0 @ Was this the first interrupt? BEQ __tx_thread_not_nested_restore @ If so, not a nested restore @ @ /* Interrupts are nested. */ @ -@ /* Just recover the saved registers and return to the point of +@ /* Just recover the saved registers and return to the point of @ interrupt. */ @ LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs @@ -154,10 +148,10 @@ _tx_thread_context_restore: MOVS pc, lr @ Return to point of interrupt @ @ } -__tx_thread_not_nested_restore: +__tx_thread_not_nested_restore: @ @ /* Determine if a thread was interrupted and no preemption is required. */ -@ else if (((_tx_thread_current_ptr[core]) && (_tx_thread_current_ptr[core] == _tx_thread_execute_ptr[core]) +@ else if (((_tx_thread_current_ptr[core]) && (_tx_thread_current_ptr[core] == _tx_thread_execute_ptr[core]) @ || (_tx_thread_preempt_disable)) @ { @ @@ -176,7 +170,7 @@ __tx_thread_not_nested_restore: LDR r2, [r3, #0] @ Pickup actual preempt disable flag CMP r2, #0 @ Is it set? BNE __tx_thread_no_preempt_restore @ Yes, don't preempt this thread -__tx_thread_skip_preempt_check: +__tx_thread_skip_preempt_check: LDR r3, =_tx_thread_execute_ptr @ Pickup address of execute thread ptr ADD r3, r3, r12 @ Build index to this core's execute thread ptr @@ -185,7 +179,7 @@ __tx_thread_skip_preempt_check: BNE __tx_thread_preempt_restore @ No, preemption needs to happen @ @ -__tx_thread_no_preempt_restore: +__tx_thread_no_preempt_restore: @ @ /* Restore interrupted thread or ISR. */ @ @@ -203,7 +197,7 @@ __tx_thread_no_preempt_restore: @ else @ { @ -__tx_thread_preempt_restore: +__tx_thread_preempt_restore: @ @ /* Was the thread being preempted waiting for the lock? */ @ if (_tx_thread_smp_protect_wait_counts[this_core] != 0) @@ -237,7 +231,7 @@ __tx_thread_preempt_restore: @ never released it because it saw that there was someone waiting. @ Note this core is not in the list. */ @ -_this_core_has_lock: +_this_core_has_lock: @ @ /* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */ @ _tx_thread_smp_protect_wait_counts[core]--; @@ -274,7 +268,7 @@ _this_core_has_lock: @ } @ -_nobody_waiting_for_lock: +_nobody_waiting_for_lock: LDMIA sp!, {r3, r10, r12, lr} @ Recover temporarily saved registers MOV r1, lr @ Save lr (point of interrupt) @@ -305,7 +299,7 @@ _nobody_waiting_for_lock: STR r2, [sp, #-4]! @ Save FPSCR VSTMDB sp!, {D16-D31} @ Save D16-D31 VSTMDB sp!, {D0-D15} @ Save D0-D15 -_tx_skip_irq_vfp_save: +_tx_skip_irq_vfp_save: #endif MOV r3, #1 @ Build interrupt stack type @@ -318,7 +312,7 @@ _tx_skip_irq_vfp_save: @ { @ LDR r3, =_tx_timer_interrupt_active @ Pickup timer interrupt active flag's address -_tx_wait_for_timer_to_finish: +_tx_wait_for_timer_to_finish: LDR r2, [r3, #0] @ Pickup timer interrupt active flag CMP r2, #0 @ Is the timer interrupt active? BNE _tx_wait_for_timer_to_finish @ If timer interrupt is active, wait until it completes @@ -337,7 +331,7 @@ _tx_wait_for_timer_to_finish: STR r2, [r3, #0] @ Disable global time-slice flag @ @ } -__tx_thread_dont_save_ts: +__tx_thread_dont_save_ts: @ @ @ /* Clear the current task pointer. */ @@ -348,7 +342,7 @@ __tx_thread_dont_save_ts: @ @ /* Set bit indicating this thread is ready for execution. */ @ - LDR r2, [r0, #152] @ Pickup the ready bit + LDR r2, [r0, #152] @ Pickup the ready bit ORR r2, r2, #0x8000 @ Set ready bit (bit 15) STR r2, [r0, #152] @ Make this thread ready for executing again DMB @ Ensure that accesses to shared resource have completed @@ -359,7 +353,7 @@ __tx_thread_dont_save_ts: B _tx_thread_schedule @ Return to scheduler @ } @ -__tx_thread_idle_system_restore: +__tx_thread_idle_system_restore: @ @ /* Just return back to the scheduler! */ @ diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_context_save.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_context_save.S index a07a3ca1..ae4065c4 100644 --- a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_context_save.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -40,50 +40,44 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_context_save SMP/Cortex-A9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save SMP/Cortex-A9/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function saves the context of an executing thread in the */ -@/* beginning of interrupt processing. The function also ensures that */ -@/* the system stack is used upon return to the calling ISR. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) @{ .global _tx_thread_context_save .type _tx_thread_context_save,function -_tx_thread_context_save: +_tx_thread_context_save: @ @ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked @ out, we are in IRQ mode, and all registers are intact. */ @@ -92,13 +86,13 @@ _tx_thread_context_save: @ if (_tx_thread_system_state[core]++) @ { @ - STMDB sp!, {r0-r3} @ Save some working registers + STMDB sp!, {r0-r3} @ Save some working registers @ @ /* Save the rest of the scratch registers on the stack and return to the @ calling ISR. */ @ MRS r0, SPSR @ Pickup saved SPSR - SUB lr, lr, #4 @ Adjust point of interrupt + SUB lr, lr, #4 @ Adjust point of interrupt STMDB sp!, {r0, r10, r12, lr} @ Store other registers @ #ifdef TX_ENABLE_FIQ_SUPPORT @@ -135,9 +129,9 @@ _tx_thread_context_save: POP {r12, lr} @ Recover ISR lr & r12 #endif - B __tx_irq_processing_return @ Continue IRQ processing + B __tx_irq_processing_return @ Continue IRQ processing @ -__tx_thread_not_nested_save: +__tx_thread_not_nested_save: @ } @ @ /* Otherwise, not nested, check to see if a thread was running. */ @@ -150,7 +144,7 @@ __tx_thread_not_nested_save: ADD r1, r1, r12 @ Build index into current thread ptr LDR r0, [r1, #0] @ Pickup current thread pointer CMP r0, #0 @ Is it NULL? - BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in @ scheduling loop - nothing needs saving! @ @ /* Save the current stack pointer in the thread's control block. */ @@ -170,17 +164,17 @@ __tx_thread_not_nested_save: POP {r12, lr} @ Recover ISR lr & r12 #endif - B __tx_irq_processing_return @ Continue IRQ processing + B __tx_irq_processing_return @ Continue IRQ processing @ @ } @ else @ { @ -__tx_thread_idle_system_save: +__tx_thread_idle_system_save: @ @ /* Interrupt occurred in the scheduling loop. */ @ -@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ @ processing. */ @ MOV r10, #0 @ Clear stack limit @@ -195,7 +189,7 @@ __tx_thread_idle_system_save: #endif ADD sp, sp, #32 @ Recover saved registers - B __tx_irq_processing_return @ Continue IRQ processing + B __tx_irq_processing_return @ Continue IRQ processing @ @ } @} diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_interrupt_control.S index 7df1ac50..e00b3591 100644 --- a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_interrupt_control.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -38,49 +38,43 @@ INT_MASK = 0x80 @ Interrupt bit mask .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_interrupt_control SMP/Cortex-A9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control SMP/Cortex-A9/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is responsible for changing the interrupt lockout */ -@/* posture of the system. */ -@/* */ -@/* INPUT */ -@/* */ -@/* new_posture New interrupt lockout posture */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_control(UINT new_posture) @{ .global _tx_thread_interrupt_control .type _tx_thread_interrupt_control,function -_tx_thread_interrupt_control: +_tx_thread_interrupt_control: @ @ /* Pickup current interrupt lockout posture. */ @ diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_interrupt_disable.S index f9356ffe..9cd91878 100644 --- a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_interrupt_disable.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -31,48 +31,42 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_interrupt_disable SMP/Cortex-A9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_disable SMP/Cortex-A9/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is responsible for disabling interrupts */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is responsible for disabling interrupts */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_disable(void) @{ .global _tx_thread_interrupt_disable .type _tx_thread_interrupt_disable,function -_tx_thread_interrupt_disable: +_tx_thread_interrupt_disable: @ @ /* Pickup current interrupt lockout posture. */ @ @@ -83,7 +77,7 @@ _tx_thread_interrupt_disable: #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if @ Disable IRQ and FIQ #else - CPSID i @ Disable IRQ + CPSID i @ Disable IRQ #endif #ifdef __THUMB_INTERWORK diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_interrupt_restore.S index 9ab32d22..6d53baad 100644 --- a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_interrupt_restore.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -31,49 +31,43 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_interrupt_restore SMP/Cortex-A9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_restore SMP/Cortex-A9/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ +@/* */ @/* This function is responsible for restoring interrupts to the state */ @/* returned by a previous _tx_thread_interrupt_disable call. */ -@/* */ -@/* INPUT */ -@/* */ -@/* old_posture Old interrupt lockout posture */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Application Code */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* INPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_restore(UINT old_posture) @{ .global _tx_thread_interrupt_restore .type _tx_thread_interrupt_restore,function -_tx_thread_interrupt_restore: +_tx_thread_interrupt_restore: @ @ /* Apply the new interrupt posture. */ @ diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_irq_nesting_end.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_irq_nesting_end.S index 41b6197b..5fb78d19 100644 --- a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_irq_nesting_end.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -34,70 +34,64 @@ DISABLE_INTS = 0xC0 @ Disable IRQ & FIQ interrupts #else DISABLE_INTS = 0x80 @ Disable IRQ interrupts #endif -MODE_MASK = 0x1F @ Mode mask +MODE_MASK = 0x1F @ Mode mask IRQ_MODE_BITS = 0x12 @ IRQ mode bits @ @ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_irq_nesting_end SMP/Cortex-A9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_end SMP/Cortex-A9/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from IRQ mode after */ -@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ -@/* processing from system mode back to IRQ mode prior to the ISR */ -@/* calling _tx_thread_context_restore. Note that this function */ -@/* assumes the system stack pointer is in the same position after */ -@/* nesting start function was called. */ -@/* */ -@/* This function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with IRQ interrupts disabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +@/* processing from system mode back to IRQ mode prior to the ISR */ +@/* calling _tx_thread_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_end(VOID) @{ .global _tx_thread_irq_nesting_end .type _tx_thread_irq_nesting_end,function -_tx_thread_irq_nesting_end: +_tx_thread_irq_nesting_end: MOV r3,lr @ Save ISR return address MRS r0, CPSR @ Pickup the CPSR ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value MSR CPSR_c, r0 @ Disable interrupts - LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for @ 8-byte alignment logic) BIC r0, r0, #MODE_MASK @ Clear mode bits ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_irq_nesting_start.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_irq_nesting_start.S index 040ec492..877c1491 100644 --- a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_irq_nesting_start.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -37,55 +37,49 @@ SYS_MODE_BITS = 0x1F @ System mode bits .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_irq_nesting_start SMP/Cortex-A9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_start SMP/Cortex-A9/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is called by the application from IRQ mode after */ -@/* _tx_thread_context_save has been called and switches the IRQ */ -@/* processing to the system mode so nested IRQ interrupt processing */ -@/* is possible (system mode has its own "lr" register). Note that */ -@/* this function assumes that the system mode stack pointer was setup */ -@/* during low-level initialization (tx_initialize_low_level.s). */ -@/* */ -@/* This function returns with IRQ interrupts enabled. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_context_save has been called and switches the IRQ */ +@/* processing to the system mode so nested IRQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_start(VOID) @{ .global _tx_thread_irq_nesting_start .type _tx_thread_irq_nesting_start,function -_tx_thread_irq_nesting_start: +_tx_thread_irq_nesting_start: MOV r3,lr @ Save ISR return address MRS r0, CPSR @ Pickup the CPSR BIC r0, r0, #MODE_MASK @ Clear the mode bits diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_schedule.S index a41df149..84fec67d 100644 --- a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_schedule.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -41,52 +41,46 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_schedule SMP/Cortex-A9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_schedule SMP/Cortex-A9/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function waits for a thread control block pointer to appear in */ -@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -@/* in the variable, the corresponding thread is resumed. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_initialize_kernel_enter ThreadX entry function */ -@/* _tx_thread_system_return Return to system from thread */ -@/* _tx_thread_context_restore Restore thread's context */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function waits for a thread control block pointer to appear in */ +@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +@/* in the variable, the corresponding thread is resumed. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* _tx_thread_system_return Return to system from thread */ +@/* _tx_thread_context_restore Restore thread's context */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) @{ .global _tx_thread_schedule .type _tx_thread_schedule,function -_tx_thread_schedule: +_tx_thread_schedule: @ @ /* Enable interrupts. */ @ @@ -124,7 +118,7 @@ _tx_thread_schedule: @ @ } @ while(_tx_thread_execute_ptr[core] == TX_NULL); -@ +@ @ /* Get the lock for accessing the thread's ready bit. */ @ MOV r2, #172 @ Build offset to the lock @@ -152,7 +146,7 @@ _tx_thread_schedule: DMB @ Ensure write to lock completes B _tx_thread_schedule @ Jump back to the scheduler @ -_tx_thread_ready_for_execution: +_tx_thread_ready_for_execution: @ @ /* We have a thread to execute. */ @ @@ -187,14 +181,14 @@ _tx_thread_ready_for_execution: MOV r1, #0 @ Build clear value STR r1, [r2, #0] @ Clear current thread pointer - LDR r1, [r0, #152] @ Pickup the ready bit + LDR r1, [r0, #152] @ Pickup the ready bit ORR r1, r1, #0x8000 @ Set ready bit (bit 15) STR r1, [r0, #152] @ Make this thread ready for executing again DMB @ Ensure that accesses to shared resource have completed B _tx_thread_schedule @ Jump back to the scheduler to schedule the new thread -_execute_pointer_did_not_change: +_execute_pointer_did_not_change: @ @ /* Increment the run count for this thread. */ @ _tx_thread_current_ptr[core] -> tx_thread_run_count++; @@ -207,7 +201,7 @@ _execute_pointer_did_not_change: @ /* Setup time-slice, if present. */ @ _tx_timer_time_slice[core] = _tx_thread_current_ptr[core] -> tx_thread_time_slice; @ - LDR r2, =_tx_timer_time_slice @ Pickup address of time slice + LDR r2, =_tx_timer_time_slice @ Pickup address of time slice @ variable ADD r2, r2, r12 @ Build index into the time-slice array LDR sp, [r0, #8] @ Switch stack pointers @@ -240,11 +234,11 @@ _execute_pointer_did_not_change: VLDMIA sp!, {D16-D31} @ Recover D16-D31 LDR r4, [sp], #4 @ Pickup FPSCR VMSR FPSCR, r4 @ Restore FPSCR -_tx_skip_interrupt_vfp_restore: +_tx_skip_interrupt_vfp_restore: #endif LDMIA sp!, {r0-r12, lr, pc}^ @ Return to point of thread interrupt - -_tx_solicited_return: + +_tx_solicited_return: #ifdef TARGET_FPU_VFP MSR CPSR_cxsf, r5 @ Recover CPSR LDR r1, [r0, #160] @ Pickup the VFP enabled flag @@ -254,7 +248,7 @@ _tx_solicited_return: VLDMIA sp!, {D16-D31} @ Recover D16-D31 LDR r4, [sp], #4 @ Pickup FPSCR VMSR FPSCR, r4 @ Restore FPSCR -_tx_skip_solicited_vfp_restore: +_tx_skip_solicited_vfp_restore: #endif MSR CPSR_cxsf, r5 @ Recover CPSR LDMIA sp!, {r4-r11, lr} @ Return to thread synchronously @@ -265,7 +259,7 @@ _tx_skip_solicited_vfp_restore: #ifdef TARGET_FPU_VFP .global tx_thread_vfp_enable -tx_thread_vfp_enable: +tx_thread_vfp_enable: MRS r2, CPSR @ Pickup the CPSR #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if @ Disable IRQ and FIQ interrupts @@ -282,12 +276,12 @@ tx_thread_vfp_enable: BEQ __tx_no_thread_to_enable @ If NULL, skip VFP enable MOV r0, #1 @ Build enable value STR r0, [r1, #160] @ Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_enable: +__tx_no_thread_to_enable: MSR CPSR_cxsf, r2 @ Recover CPSR BX LR @ Return to caller .global tx_thread_vfp_disable -tx_thread_vfp_disable: +tx_thread_vfp_disable: MRS r2, CPSR @ Pickup the CPSR #ifdef TX_ENABLE_FIQ_SUPPORT CPSID if @ Disable IRQ and FIQ interrupts @@ -304,7 +298,7 @@ tx_thread_vfp_disable: BEQ __tx_no_thread_to_disable @ If NULL, skip VFP disable MOV r0, #0 @ Build disable value STR r0, [r1, #160] @ Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) -__tx_no_thread_to_disable: +__tx_no_thread_to_disable: MSR CPSR_cxsf, r2 @ Recover CPSR BX LR @ Return to caller #endif diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_core_get.S index 92e158e5..aff8aba0 100644 --- a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_core_get.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread - Low Level SMP Support */ @/** */ @@ -33,46 +33,40 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_smp_core_get SMP/Cortex-A9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_core_get SMP/Cortex-A9/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function gets the currently running core number and returns it.*/ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* Core ID */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX Source */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function gets the currently running core number and returns it.*/ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* Core ID */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get,function -_tx_thread_smp_core_get: +_tx_thread_smp_core_get: MRC p15, 0, r0, c0, c0, 5 @ Read CPU ID register AND r0, r0, #0x03 @ Mask off, leaving the CPU ID field @@ -82,4 +76,4 @@ _tx_thread_smp_core_get: MOV pc, lr @ Return to caller #endif - + diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_core_preempt.S index 427eb89f..81e86166 100644 --- a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_core_preempt.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread - Low Level SMP Support */ @/** */ @@ -35,60 +35,54 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_smp_core_preempt SMP/Cortex-A9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_core_preempt SMP/Cortex-A9/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function preempts the specified core in situations where the */ -@/* thread corresponding to this core is no longer ready or when the */ -@/* core must be used for a higher-priority thread. If the specified is */ -@/* the current core, this processing is skipped since the will give up */ -@/* control subsequently on its own. */ -@/* */ -@/* INPUT */ -@/* */ -@/* core The core to preempt */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX Source */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function preempts the specified core in situations where the */ +@/* thread corresponding to this core is no longer ready or when the */ +@/* core must be used for a higher-priority thread. If the specified is */ +@/* the current core, this processing is skipped since the will give up */ +@/* control subsequently on its own. */ +@/* */ +@/* INPUT */ +@/* */ +@/* core The core to preempt */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt,function -_tx_thread_smp_core_preempt: +_tx_thread_smp_core_preempt: STMDB sp!, {r4, lr} @ Save the lr and r4 register on the stack @ @ /* Place call to send inter-processor interrupt here! */ @ - DSB @ - MOV r1, #1 @ Build parameter list - LSL r1, r1, r0 @ - MOV r0, #0 @ - MOV r2, #0 @ + DSB @ + MOV r1, #1 @ Build parameter list + LSL r1, r1, r0 @ + MOV r0, #0 @ + MOV r2, #0 @ BL sendSGI @ Make call to send inter-processor interrupt LDMIA sp!, {r4, lr} @ Recover lr register and r4 @@ -98,4 +92,4 @@ _tx_thread_smp_core_preempt: MOV pc, lr @ Return to caller #endif - + diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_current_state_get.S index 4d4d2362..4f6f67a0 100644 --- a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_current_state_get.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread - Low Level SMP Support */ @/** */ @@ -35,46 +35,40 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_smp_current_state_get SMP/Cortex-A9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_current_state_get SMP/Cortex-A9/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is gets the current state of the calling core. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX Components */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is gets the current state of the calling core. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Components */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_current_state_get .type _tx_thread_smp_current_state_get,function -_tx_thread_smp_current_state_get: +_tx_thread_smp_current_state_get: MRS r3, CPSR @ Pickup current CPSR @@ -93,7 +87,7 @@ _tx_thread_smp_current_state_get: LDR r1, =_tx_thread_system_state @ Pickup start of the current state array ADD r1, r1, r2 @ Build index into the current state array LDR r0, [r1] @ Pickup state for this core - MSR CPSR_c, r3 @ Restore CPSR + MSR CPSR_c, r3 @ Restore CPSR #ifdef __THUMB_INTERWORK BX lr @ Return to caller #else diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_current_thread_get.S index c1cb8230..da3dec70 100644 --- a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_current_thread_get.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread - Low Level SMP Support */ @/** */ @@ -35,46 +35,40 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_smp_current_thread_get SMP/Cortex-A9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_current_thread_get SMP/Cortex-A9/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is gets the current thread of the calling core. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX Components */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is gets the current thread of the calling core. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Components */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_current_thread_get .type _tx_thread_smp_current_thread_get,function -_tx_thread_smp_current_thread_get: +_tx_thread_smp_current_thread_get: MRS r3, CPSR @ Pickup current CPSR @@ -93,7 +87,7 @@ _tx_thread_smp_current_thread_get: LDR r1, =_tx_thread_current_ptr @ Pickup start of the current thread array ADD r1, r1, r2 @ Build index into the current thread array LDR r0, [r1] @ Pickup current thread for this core - MSR CPSR_c, r3 @ Restore CPSR + MSR CPSR_c, r3 @ Restore CPSR #ifdef __THUMB_INTERWORK BX lr @ Return to caller #else diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_initialize_wait.S index 2bf7e824..7b05faa6 100644 --- a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_initialize_wait.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread - Low Level SMP Support */ @/** */ @@ -38,48 +38,42 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_smp_initialize_wait SMP/Cortex-A9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_initialize_wait SMP/Cortex-A9/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is the place where additional cores wait until */ -@/* initialization is complete before they enter the thread scheduling */ -@/* loop. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling loop */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* Hardware */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is the place where additional cores wait until */ +@/* initialization is complete before they enter the thread scheduling */ +@/* loop. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Hardware */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_initialize_wait .type _tx_thread_smp_initialize_wait,function -_tx_thread_smp_initialize_wait: +_tx_thread_smp_initialize_wait: @ /* Lockout interrupts. */ @ @@ -95,13 +89,13 @@ _tx_thread_smp_initialize_wait: AND r10, r10, #0x03 @ Mask off, leaving the CPU ID field LSL r10, r10, #2 @ Build offset to array indexes @ -@ /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release +@ /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release @ flag. */ @ LDR r3, =_tx_thread_system_state @ Build address of system state variable ADD r3, r3, r10 @ Build index into the system state array LDR r2, =0xF0F0F0F0 @ Build TX_INITIALIZE_IN_PROGRESS flag -wait_for_initialize: +wait_for_initialize: LDR r1, [r3] @ Pickup system state CMP r1, r2 @ Has initialization completed? BNE wait_for_initialize @ If different, wait here! @@ -110,13 +104,13 @@ wait_for_initialize: @ LDR r2, =_tx_thread_smp_release_cores_flag @ Build address of release cores flag -wait_for_release: +wait_for_release: LDR r3, [r2] @ Pickup the flag CMP r3, #0 @ Is it set? - BEQ wait_for_release @ Wait for the flag to be set + BEQ wait_for_release @ Wait for the flag to be set @ @ /* Core 0 has released this core. */ -@ +@ @ /* Clear this core's system state variable. */ @ LDR r3, =_tx_thread_system_state @ Build address of system state variable @@ -126,9 +120,9 @@ wait_for_release: @ @ /* Now wait for core 0 to finish it's initialization. */ @ - LDR r3, =_tx_thread_system_state @ Build address of system state variable of logical 0 + LDR r3, =_tx_thread_system_state @ Build address of system state variable of logical 0 -core_0_wait_loop: +core_0_wait_loop: LDR r2, [r3] @ Pickup system state for core 0 CMP r2, #0 @ Is it 0? BNE core_0_wait_loop @ No, keep waiting for core 0 to finish its initialization diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_low_level_initialize.S index 2131b648..bdf6fea1 100644 --- a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_low_level_initialize.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread - Low Level SMP Support */ @/** */ @@ -33,47 +33,41 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_smp_low_level_initialize SMP/Cortex-A9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_low_level_initialize SMP/Cortex-A9/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function performs low-level initialization of the booting */ -@/* core. */ -@/* */ -@/* INPUT */ -@/* */ -@/* number_of_cores Number of cores */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_initialize_high_level ThreadX high-level init */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function performs low-level initialization of the booting */ +@/* core. */ +@/* */ +@/* INPUT */ +@/* */ +@/* number_of_cores Number of cores */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_high_level ThreadX high-level init */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_low_level_initialize .type _tx_thread_smp_low_level_initialize,function -_tx_thread_smp_low_level_initialize: +_tx_thread_smp_low_level_initialize: #ifdef __THUMB_INTERWORK BX lr @ Return to caller diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_protect.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_protect.S index f7e7b9d9..e90f73e2 100644 --- a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_protect.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread - Low Level SMP Support */ @/** */ @@ -46,48 +46,42 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_smp_protect SMP/Cortex-A9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_protect SMP/Cortex-A9/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function gets protection for running inside the ThreadX */ -@/* source. This is acomplished by a combination of a test-and-set */ -@/* flag and periodically disabling interrupts. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* Previous Status Register */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX Source */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function gets protection for running inside the ThreadX */ +@/* source. This is acomplished by a combination of a test-and-set */ +@/* flag and periodically disabling interrupts. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* Previous Status Register */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_protect .type _tx_thread_smp_protect,function -_tx_thread_smp_protect: +_tx_thread_smp_protect: @VOID _tx_thread_smp_protect(VOID) @{ @ @@ -126,7 +120,7 @@ _tx_thread_smp_protect: B _return -_protection_not_owned: +_protection_not_owned: @ @ /* Is the lock available? */ @ if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) @@ -164,7 +158,7 @@ _protection_not_owned: B _return -_list_not_empty: +_list_not_empty: @ @ /* Are we at the front of the list? */ @ if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head]) @@ -205,7 +199,7 @@ _list_not_empty: B _return -_start_waiting: +_start_waiting: @ @ /* For one reason or another, we didn't get the lock. */ @ @@ -231,7 +225,7 @@ _start_waiting: @ @ } @ -_already_in_list0: +_already_in_list0: @ @ /* Restore interrupts. */ @ @@ -244,7 +238,7 @@ _already_in_list0: @ while (1) @ { @ -_try_to_get_lock: +_try_to_get_lock: @ @ /* Disable interrupts so we don't get preempted. */ @ @@ -307,7 +301,7 @@ _try_to_get_lock: B _got_lock_after_waiting -_did_not_get_lock: +_did_not_get_lock: @ @ /* For one reason or another, we didn't get the lock. */ @ @@ -336,7 +330,7 @@ _did_not_get_lock: @ @ } @ -_already_in_list1: +_already_in_list1: @ @ /* Restore interrupts and try again. */ @ @@ -346,7 +340,7 @@ _already_in_list1: #endif B _try_to_get_lock @ On waking, restart the protection attempt -_got_lock_after_waiting: +_got_lock_after_waiting: @ @ /* We're no longer waiting. */ @ _tx_thread_smp_protect_wait_counts[this_core]--; @@ -359,7 +353,7 @@ _got_lock_after_waiting: @ @ /* Restore link register and return. */ @ -_return: +_return: POP {r4-r6} @ Restore registers @@ -369,4 +363,4 @@ _return: MOV pc, lr @ Return to caller #endif - + diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h index 7ac4ad4e..f1ad80e8 100644 --- a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h @@ -1,10 +1,10 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @@ -73,7 +73,7 @@ @ @ } @ -_store_new_head\@: +_store_new_head\@: STR r5, [r4] @ Store the new head @ @@ -90,7 +90,7 @@ _store_new_head\@: @ while (1) @ { @ -_tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@: +_tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@: @ @ /* Is the list lock available? */ @ _tx_thread_smp_protect_wait_list_lock_protect_in_force = load_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force); @@ -158,7 +158,7 @@ _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@: @ @ } @ -_tx_thread_smp_protect_wait_list_add__no_wrap\@: +_tx_thread_smp_protect_wait_list_add__no_wrap\@: STR r4, [r3] @ Store the new tail value. @ @@ -185,7 +185,7 @@ _tx_thread_smp_protect_wait_list_add__no_wrap\@: @ @ { @ -_tx_thread_smp_protect_wait_list_remove__check_cur_core\@: +_tx_thread_smp_protect_wait_list_remove__check_cur_core\@: @ @ /* Is this the core? */ @ if (_tx_thread_smp_protect_wait_list[core_index] == core) @@ -194,7 +194,7 @@ _tx_thread_smp_protect_wait_list_remove__check_cur_core\@: @ LDR r3, [r2, r1, LSL #2] @ Get the value at the current index CMP r3, r0 @ Did we find the core? - BEQ _tx_thread_smp_protect_wait_list_remove__found_core\@ + BEQ _tx_thread_smp_protect_wait_list_remove__found_core\@ @ @ } @ @@ -203,7 +203,7 @@ _tx_thread_smp_protect_wait_list_remove__check_cur_core\@: @ @ } @ -_tx_thread_smp_protect_wait_list_remove__found_core\@: +_tx_thread_smp_protect_wait_list_remove__found_core\@: @ @ /* We're about to modify the list. Get the lock. We need the lock because another @ core could be simultaneously adding (a core is simultaneously trying to get @@ -221,12 +221,12 @@ _tx_thread_smp_protect_wait_list_remove__found_core\@: @ while (core_index != _tx_thread_smp_protect_wait_list_tail) @ { @ -_tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@: +_tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@: LDR r2, =_tx_thread_smp_protect_wait_list_tail @ Load tail address LDR r2, [r2] @ Load tail value CMP r1, r2 @ Compare cur index and tail - BEQ _tx_thread_smp_protect_wait_list_remove__removed\@ + BEQ _tx_thread_smp_protect_wait_list_remove__removed\@ @ @ UINT next_index = core_index + 1; @ @@ -239,7 +239,7 @@ _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@: LDR r3, =_tx_thread_smp_protect_wait_list_size LDR r3, [r3] CMP r2, r3 - BNE _tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@ + BNE _tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@ @ @ next_index = 0; @ @@ -247,7 +247,7 @@ _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@: @ @ } @ -_tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@: +_tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@: @ @ list_cores[core_index] = list_cores[next_index]; @ @@ -259,11 +259,11 @@ _tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@: @ MOV r1, r2 - B _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@ + B _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@ @ @ } @ -_tx_thread_smp_protect_wait_list_remove__removed\@: +_tx_thread_smp_protect_wait_list_remove__removed\@: @ @ /* Now update the tail. */ @ if (_tx_thread_smp_protect_wait_list_tail == 0) @@ -272,7 +272,7 @@ _tx_thread_smp_protect_wait_list_remove__removed\@: LDR r0, =_tx_thread_smp_protect_wait_list_tail @ Load tail address LDR r1, [r0] @ Load tail value CMP r1, #0 - BNE _tx_thread_smp_protect_wait_list_remove__tail_not_zero\@ + BNE _tx_thread_smp_protect_wait_list_remove__tail_not_zero\@ @ @ _tx_thread_smp_protect_wait_list_tail = _tx_thread_smp_protect_wait_list_size; @ @@ -281,7 +281,7 @@ _tx_thread_smp_protect_wait_list_remove__removed\@: @ @ } @ -_tx_thread_smp_protect_wait_list_remove__tail_not_zero\@: +_tx_thread_smp_protect_wait_list_remove__tail_not_zero\@: @ @ _tx_thread_smp_protect_wait_list_tail--; @ diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_time_get.S index 9621bebd..9cebe0f2 100644 --- a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_time_get.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread - Low Level SMP Support */ @/** */ @@ -34,47 +34,41 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_smp_time_get SMP/Cortex-A9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_time_get SMP/Cortex-A9/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function gets the global time value that is used for debug */ -@/* information and event tracing. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* 32-bit time stamp */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX Source */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function gets the global time value that is used for debug */ +@/* information and event tracing. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* 32-bit time stamp */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_time_get .type _tx_thread_smp_time_get,function -_tx_thread_smp_time_get: +_tx_thread_smp_time_get: MRC p15, 4, r0, c15, c0, 0 @ Read periph base address LDR r0, [r0, #0x604] @ Read count register @@ -85,4 +79,4 @@ _tx_thread_smp_time_get: MOV pc, lr @ Return to caller #endif - + diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_unprotect.S index 890d34ff..a76677ec 100644 --- a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_unprotect.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread - Low Level SMP Support */ @/** */ @@ -38,49 +38,43 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_smp_unprotect SMP/Cortex-A9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_unprotect SMP/Cortex-A9/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function releases previously obtained protection. The supplied */ -@/* previous SR is restored. If the value of _tx_thread_system_state */ -@/* and _tx_thread_preempt_disable are both zero, then multithreading */ -@/* is enabled as well. */ -@/* */ -@/* INPUT */ -@/* */ -@/* Previous Status Register */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX Source */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function releases previously obtained protection. The supplied */ +@/* previous SR is restored. If the value of _tx_thread_system_state */ +@/* and _tx_thread_preempt_disable are both zero, then multithreading */ +@/* is enabled as well. */ +@/* */ +@/* INPUT */ +@/* */ +@/* Previous Status Register */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_unprotect .type _tx_thread_smp_unprotect,function -_tx_thread_smp_unprotect: +_tx_thread_smp_unprotect: @ @ /* Lockout interrupts. */ @ @@ -130,8 +124,8 @@ _tx_thread_smp_unprotect: SEV @ Send event to other CPUs, wakes anyone waiting on the protection (using WFE) #endif -_still_protected: - MSR CPSR_c, r0 @ Restore CPSR +_still_protected: + MSR CPSR_c, r0 @ Restore CPSR #ifdef __THUMB_INTERWORK BX lr @ Return to caller @@ -139,4 +133,4 @@ _still_protected: MOV pc, lr @ Return to caller #endif - + diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_stack_build.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_stack_build.S index d7daacb3..b90ba924 100644 --- a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_stack_build.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -43,56 +43,50 @@ THUMB_BIT = 0x20 @ Thumb-bit .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_stack_build SMP/Cortex-A9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build SMP/Cortex-A9/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ +@/* */ @/* This function builds a stack frame on the supplied thread's stack. */ @/* The stack frame results in a fake interrupt return to the supplied */ -@/* function pointer. */ -@/* */ -@/* INPUT */ -@/* */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ @/* thread_ptr Pointer to thread control blk */ @/* function_ptr Pointer to return function */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_thread_create Create thread service */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @{ .global _tx_thread_stack_build .type _tx_thread_stack_build,function -_tx_thread_stack_build: +_tx_thread_stack_build: +@ @ -@ @ /* Build a fake interrupt frame. The form of the fake interrupt stack @ on the Cortex-A9 should look like the following after it is built: -@ +@ @ Stack Top: 1 Interrupt stack frame type @ CPSR Initial value for CPSR @ a1 (r0) Initial value for a1 diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_system_return.S index cfba6eb1..6feec05b 100644 --- a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_system_return.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -35,58 +35,52 @@ .global _tx_thread_preempt_disable .global _tx_thread_smp_protection #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - .global _tx_execution_thread_exit + .global _tx_execution_thread_exit #endif @ @ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_system_return SMP/Cortex-A9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return SMP/Cortex-A9/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function is target processor specific. It is used to transfer */ -@/* control from a thread back to the ThreadX system. Only a */ -@/* minimal context is saved since the compiler assumes temp registers */ -@/* are going to get slicked by a function call anyway. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_schedule Thread scheduling loop */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ThreadX components */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ @/* */ @/**************************************************************************/ @VOID _tx_thread_system_return(VOID) @{ .global _tx_thread_system_return .type _tx_thread_system_return,function -_tx_thread_system_return: +_tx_thread_system_return: @ @ /* Save minimal context on the stack. */ @ @@ -109,12 +103,12 @@ _tx_thread_system_return: STR r4, [sp, #-4]! @ Save FPSCR VSTMDB sp!, {D16-D31} @ Save D16-D31 VSTMDB sp!, {D8-D15} @ Save D8-D15 -_tx_skip_solicited_vfp_save: +_tx_skip_solicited_vfp_save: #endif MOV r4, #0 @ Build a solicited stack type MRS r5, CPSR @ Pickup the CPSR STMDB sp!, {r4-r5} @ Save type and CPSR -@ +@ @ /* Lockout interrupts. */ @ #ifdef TX_ENABLE_FIQ_SUPPORT @@ -162,7 +156,7 @@ _tx_skip_solicited_vfp_save: STR r1, [r0, #24] @ Save current time-slice @ @ } -__tx_thread_dont_save_ts: +__tx_thread_dont_save_ts: @ @ /* Clear the current thread pointer. */ @ _tx_thread_current_ptr[core] = TX_NULL; @@ -184,10 +178,10 @@ __tx_thread_dont_save_ts: STR lr, [r3, #24] @ Save last caller LDR r2, [r3, #4] @ Pickup owning thread CMP r0, r2 @ Is it the same as the current thread? -__error_loop: +__error_loop: BNE __error_loop @ If not, we have a problem!! -#endif - +#endif + LDR r1, =_tx_thread_preempt_disable @ Build address to preempt disable flag MOV r2, #0 @ Build clear value STR r2, [r1, #0] @ Clear preempt disable flag diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_vectored_context_save.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_vectored_context_save.S index 3683c560..5991c470 100644 --- a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_vectored_context_save.S +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_vectored_context_save.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Thread */ @/** */ @@ -39,50 +39,44 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_thread_vectored_context_save SMP/Cortex-A9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_vectored_context_save SMP/Cortex-A9/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function saves the context of an executing thread in the */ -@/* beginning of interrupt processing. The function also ensures that */ -@/* the system stack is used upon return to the calling ISR. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* ISRs */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ @/* */ @/**************************************************************************/ @VOID _tx_thread_vectored_context_save(VOID) @{ .global _tx_thread_vectored_context_save .type _tx_thread_vectored_context_save,function -_tx_thread_vectored_context_save: +_tx_thread_vectored_context_save: @ @ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked @ out, we are in IRQ mode, and all registers are intact. */ @@ -133,7 +127,7 @@ _tx_thread_vectored_context_save: MOV pc, lr @ Return to caller #endif @ -__tx_thread_not_nested_save: +__tx_thread_not_nested_save: @ } @ @ /* Otherwise, not nested, check to see if a thread was running. */ @@ -146,7 +140,7 @@ __tx_thread_not_nested_save: ADD r1, r1, r12 @ Build index into current thread ptr LDR r0, [r1, #0] @ Pickup current thread pointer CMP r0, #0 @ Is it NULL? - BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in @ scheduling loop - nothing needs saving! @ @ /* Note: Minimal context of interrupted thread is already saved. */ @@ -178,11 +172,11 @@ __tx_thread_not_nested_save: @ else @ { @ -__tx_thread_idle_system_save: +__tx_thread_idle_system_save: @ @ /* Interrupt occurred in the scheduling loop. */ @ -@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ @ processing. */ @ MOV r10, #0 @ Clear stack limit diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_timer_interrupt.S b/ports_smp/cortex_a9_smp/gnu/src/tx_timer_interrupt.S index 291147b7..8356f4ee 100644 --- a/ports_smp/cortex_a9_smp/gnu/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_timer_interrupt.S @@ -1,18 +1,18 @@ @/*************************************************************************** -@ * Copyright (c) 2024 Microsoft Corporation -@ * +@ * Copyright (c) 2024 Microsoft Corporation +@ * @ * This program and the accompanying materials are made available under the @ * terms of the MIT License which is available at @ * https://opensource.org/licenses/MIT. -@ * +@ * @ * SPDX-License-Identifier: MIT @ **************************************************************************/ @ @ @/**************************************************************************/ @/**************************************************************************/ -@/** */ -@/** ThreadX Component */ +@/** */ +@/** ThreadX Component */ @/** */ @/** Timer */ @/** */ @@ -50,55 +50,49 @@ .arm .text .align 2 -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_timer_interrupt SMP/Cortex-A9/GNU */ +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt SMP/Cortex-A9/GNU */ @/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @/* */ @/* DESCRIPTION */ -@/* */ -@/* This function processes the hardware timer interrupt. This */ -@/* processing includes incrementing the system clock and checking for */ -@/* time slice and/or timer expiration. If either is found, the */ -@/* interrupt context save/restore functions are called along with the */ -@/* expiration functions. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* _tx_thread_time_slice Time slice interrupted thread */ -@/* _tx_thread_smp_protect Get SMP protection */ -@/* _tx_thread_smp_unprotect Releast SMP protection */ -@/* _tx_timer_expiration_process Timer expiration processing */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* interrupt vector */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ @/* */ -@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* _tx_thread_smp_protect Get SMP protection */ +@/* _tx_thread_smp_unprotect Releast SMP protection */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) @{ .global _tx_timer_interrupt .type _tx_timer_interrupt,function -_tx_timer_interrupt: +_tx_timer_interrupt: @ @ /* Upon entry to this routine, it is assumed that context save has already @ been called, and therefore the compiler scratch registers are available @@ -109,7 +103,7 @@ _tx_timer_interrupt: CMP r0, #0 @ Only process timer interrupts from core 0 (to change this simply change the constant!) BEQ __tx_process_timer @ If the same process the interrupt BX lr @ Return to caller if not matched -__tx_process_timer: +__tx_process_timer: STMDB sp!, {r4, lr} @ Save the lr and r4 register on the stack BL _tx_thread_smp_protect @ Get protection @@ -154,7 +148,7 @@ __tx_process_timer: @ } @ else @ { -__tx_timer_no_timer: +__tx_timer_no_timer: @ @ /* No timer expired, increment the timer pointer. */ @ _tx_timer_current_ptr++; @@ -175,12 +169,12 @@ __tx_timer_no_timer: LDR r3, =_tx_timer_list_start @ Pickup addr of timer list start LDR r0, [r3, #0] @ Set current pointer to list start @ -__tx_timer_skip_wrap: +__tx_timer_skip_wrap: @ STR r0, [r1, #0] @ Store new current timer pointer @ } @ -__tx_timer_done: +__tx_timer_done: @ @ @ /* Did a timer expire? */ @@ -198,10 +192,10 @@ __tx_timer_done: BL _tx_timer_expiration_process @ Call the timer expiration handling routine @ @ } -__tx_timer_dont_activate: +__tx_timer_dont_activate: @ @ /* Call time-slice processing. */ -@ _tx_thread_time_slice(); +@ _tx_thread_time_slice(); BL _tx_thread_time_slice @ Call time-slice processing @ diff --git a/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_GIC.S b/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_GIC.S index eb1f366e..fdd077cc 100644 --- a/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_GIC.S +++ b/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_GIC.S @@ -38,7 +38,7 @@ enable_GIC PROC BX lr ENDP - + ; ------------------------------------------------------------ EXPORT disable_GIC @@ -88,7 +88,7 @@ enable_irq_id PROC ENDP ; ------------------------------------------------------------ - + EXPORT disable_irq_id ; void disable_irq_id(unsigned int ID) ; Disables the interrupt source number ID @@ -131,7 +131,7 @@ set_irq_priority PROC ; r0 = base addr ; r1 = priority ; r2 = ID - + ; Make sure that priority value is only 5 bits, and convert to expected format AND r1, r1, #0x1F MOV r1, r1, LSL #3 @@ -207,12 +207,12 @@ set_priority_mask PROC ; Get base address of private perpherial space MOV r1, r0 ; Back up passed in ID value MRC p15, 4, r0, c15, c0, 0 ; Read periph base address - + STR r1, [r0, #0x0104] ; Write the Priority Mask register (ICCPMR/ICCIPMR) BX lr ENDP - + ; ------------------------------------------------------------ EXPORT set_binary_port @@ -255,7 +255,7 @@ write_end_of_irq PROC BX lr ENDP - + ; ------------------------------------------------------------ ; SGI ; ------------------------------------------------------------ diff --git a/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_GIC.h b/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_GIC.h index 81551bee..2465c726 100644 --- a/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_GIC.h +++ b/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_GIC.h @@ -41,7 +41,7 @@ void set_irq_priority(unsigned int ID, unsigned int priority); // Enables the processor interface // Must been done one each core seperately -void enable_gic_processor_interface(void); +void enable_gic_processor_interface(void); // Disables the processor interface void disable_gic_processor_interface(void); diff --git a/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.h b/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.h index 7a272b3e..2b927ec4 100644 --- a/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.h +++ b/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.h @@ -19,7 +19,7 @@ // r1: Increment value (ignored if auto_increment != 0) void init_global_timer(unsigned int auto_increment, unsigned int increment_value) -// Sets the comparator value for this CPU +// Sets the comparator value for this CPU void set_global_timer_comparator(unsigned int top, unsigned int bottom); // Starts the private timer diff --git a/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.s b/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.s index 04245587..0e284041 100644 --- a/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.s +++ b/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.s @@ -46,8 +46,8 @@ init_global_timer PROC STR r0, [r2, #0x208] ; Store to control register ; Store increment value - STREQ r1, [r2, #0x218] - + STREQ r1, [r2, #0x218] + ; Clear timer value MOV r0, #0x0 STR r0, [r2, #0x0] @@ -71,12 +71,12 @@ set_global_timer_comparator PROC LDR r1, [r2, #0x208] ; Read control reg BIC r3, r3, #0x02 ; Clear comparator enable bit STR r3, [r2, #0x208] ; Write modified value back - + ; Write the comparator registers STR r1, [r2, #0x210] ; Write lower 32 bits STR r0, [r2, #0x214] ; Write upper 32 bits DMB - + ; Re-enable the comparator ORR r3, r3, #0x02 ; Set comparator enable bit STR r3, [r2, #0x208] ; Write modified value back @@ -142,7 +142,7 @@ get_global_timer_count_loop BX lr ENDP - + ; ------------------------------------------------------------ EXPORT clear_global_timer_irq diff --git a/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_Mutexes.h index 2a613b7e..b32fc6c6 100644 --- a/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_Mutexes.h +++ b/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_Mutexes.h @@ -9,9 +9,9 @@ #define _CORTEXA_MUTEX_ // Struct -// 0xFF=unlocked 0x0 = Locked by CPU 0, -// 0x1 = Locked by CPU 1, -// 0x2 = Locked by CPU 2, +// 0xFF=unlocked 0x0 = Locked by CPU 0, +// 0x1 = Locked by CPU 1, +// 0x2 = Locked by CPU 2, // 0x3 = Locked by CPU 3 typedef struct { diff --git a/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_Mutexes.s b/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_Mutexes.s index 3c20b253..efe33438 100644 --- a/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_Mutexes.s +++ b/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_Mutexes.s @@ -49,7 +49,7 @@ lock_mutex PROC WFENE ; If mutex is locked, go into standby BNE lock_mutex ; On waking re-check the mutex - + ; Attempt to lock mutex ; ----------------------- MRC p15, 0, r1, c0, c0, 5 ; Read CPU ID register @@ -87,7 +87,7 @@ unlock_mutex PROC MOV r1, #UNLOCKED ; Write "unlocked" into lock field STR r1, [r0] - + DMB ; To ensure update of the mutex occurs before other CPUs awake SEV ; Send event to other CPUs, wakes anyone waiting on a mutex (using WFE) @@ -104,7 +104,7 @@ unlock_mutex PROC ; Returns 0x0 if mutex unlocked, 0x1 is locked ; r0 = address of mutex_t is_mutex_locked PROC - LDR r0, [r0] + LDR r0, [r0] CMP r0, #UNLOCKED MOVEQ r0, #0x0 MOVNE r0, #0x1 diff --git a/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_PrivateTimer.s b/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_PrivateTimer.s index 3be7249b..0d202412 100644 --- a/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_PrivateTimer.s +++ b/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_PrivateTimer.s @@ -94,7 +94,7 @@ get_private_timer_count PROC BX lr ENDP - + ; ------------------------------------------------------------ EXPORT clear_private_timer_irq diff --git a/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_SCU.s b/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_SCU.s index cfed344f..9a77d590 100644 --- a/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_SCU.s +++ b/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/MP_SCU.s @@ -40,13 +40,13 @@ get_num_cpus PROC ; Get base address of private perpherial space MRC p15, 4, r0, c15, c0, 0 ; Read periph base address - + LDR r0, [r0, #0x004] ; Read SCU Configuration register AND r0, r0, #0x3 ; Bits 1:0 gives the number of cores BX lr ENDP - + ; ------------------------------------------------------------ EXPORT go_to_sleep @@ -170,14 +170,14 @@ disable_maintenance_broadcast PROC secure_SCU_invalidate PROC AND r0, r0, #0x03 ; Mask off unused bits of CPU ID MOV r0, r0, LSL #2 ; Convert into bit offset (four bits per core) - + AND r1, r1, #0x0F ; Mask off unused bits of ways MOV r1, r1, LSL r0 ; Shift ways into the correct CPU field MRC p15, 4, r2, c15, c0, 0 ; Read periph base address STR r1, [r2, #0x0C] ; Write to SCU Invalidate All in Secure State - + BX lr ENDP diff --git a/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/demo_threadx.c b/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/demo_threadx.c index 70f1c840..57b2471e 100644 --- a/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/demo_threadx.c +++ b/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/demo_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -63,7 +63,7 @@ UCHAR event_buffer[65536]; int main(void) { - + /* Enter ThreadX. */ tx_kernel_enter(); @@ -91,41 +91,41 @@ CHAR *pointer; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); - + /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -133,23 +133,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -252,11 +252,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -315,7 +315,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -368,7 +368,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/demo_threadx.ld b/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/demo_threadx.ld index c2add4f2..35358bcf 100644 --- a/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/demo_threadx.ld +++ b/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/demo_threadx.ld @@ -6,8 +6,8 @@ ; * (InRoot$$Sections) ; Selects all sections that must be in a root region ; * (+RO) ; } -; -; SHARED_DATA +0x0 +; +; SHARED_DATA +0x0 ; { ; * (+RW,+ZI) ; } @@ -30,7 +30,7 @@ LOAD_ROOT 0x0 { startup.o (StartUp, +FIRST) ;startup code * (InRoot$$Sections) ;All library sections that must be in a root region - + } } LOAD 0x48000000 @@ -39,13 +39,13 @@ LOAD 0x48000000 { demo_threadx.o (+RO) ; Place main() in a root region for the benefit of software breakpoints } - + ; increased from 32k to 64k CODE +0 0x10000 { * (+RO) ; Application code, including C library } - + SHARED_DATA +0 0x4000 { * (+RW,+ZI) ; All RW and ZI Data diff --git a/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/startup.S b/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/startup.S index 58c39a90..0feff3c0 100644 --- a/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/startup.S +++ b/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/startup.S @@ -200,7 +200,7 @@ by_pass ; MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register ; ANDS r0, r0, #0x03 ; Mask off, leaving the CPU ID field ; BNE by_pass2 -; +; ; MOV r0, #0x04 ; Code for SYS_WRITE0 ; LDR r1, =irq_handler_message1 ; SVC 0x123456 @@ -494,7 +494,7 @@ primaryCPUInit PROC MOV r0, #0x1F BL set_priority_mask ; Set priority mask (local) - ; [EL] Change start - don't enable interrupts here! + ; [EL] Change start - don't enable interrupts here! ;CPSIE i ; Clear CPSR I bit ; [EL] Change end @@ -513,7 +513,7 @@ primaryCPUInit PROC MOV r1, #0x0 BL init_private_timer BL start_private_timer - + ; ; Enable receipt of SGI 0 ; ------------------------ diff --git a/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/v7.S b/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/v7.S index dfd65a2c..e732325c 100644 --- a/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/v7.S +++ b/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/v7.S @@ -19,7 +19,7 @@ enable_caches PROC MCR p15, 0, r0, c1, c0, 0 ; Write System Control Register configuration data BX lr ENDP - + EXPORT disable_caches ; void disable_caches(void) @@ -36,7 +36,7 @@ disable_caches PROC ; void clean_dcache(void); clean_dcache PROC PUSH {r4-r12} - + ; ; Based on code example given in section 11.2.4 of ARM DDI 0406B ; @@ -86,12 +86,12 @@ clean_dcache_finished BX lr ENDP - + EXPORT clean_invalidate_dcache ; void clean_invalidate_dcache(void); clean_invalidate_dcache PROC PUSH {r4-r12} - + ; ; Based on code example given in section 11.2.4 of ARM DDI 0406B ; @@ -147,7 +147,7 @@ clean_invalidate_dcache_finished ; void invalidate_caches(void); invalidate_caches PROC PUSH {r4-r12} - + ; ; Based on code example given in section B2.2.4/11.2.4 of ARM DDI 0406B ; @@ -199,7 +199,7 @@ invalidate_caches_finished POP {r4-r12} BX lr ENDP - + EXPORT invalidate_caches_is ; void invalidate_caches_is(void); @@ -295,7 +295,7 @@ disable_branch_prediction PROC MCR p15, 0,r0, c1, c0, 0 ; Write SCTLR BX lr ENDP - + EXPORT invalidate_branch_target_cache ; void invalidate_branch_target_cache(void) invalidate_branch_target_cache PROC @@ -351,7 +351,7 @@ set_context_id PROC MCR p15, 0, r0, c13, c0, 1 ; Write Context ID Register BX lr ENDP - + ; ------------------------------------------------------------ ; ID registers ; ------------------------------------------------------------ @@ -362,7 +362,7 @@ get_MIDR PROC MRC p15, 0, r0, c0, c0, 0 ; Read Main ID Register (MIDR) BX lr ENDP - + EXPORT get_MPIDR ; uint32_t get_MPIDR(void); get_MPIDR PROC diff --git a/ports_smp/cortex_r8_smp/ac5/inc/tx_port.h b/ports_smp/cortex_r8_smp/ac5/inc/tx_port.h index 4aeb4a61..842b16ae 100644 --- a/ports_smp/cortex_r8_smp/ac5/inc/tx_port.h +++ b/ports_smp/cortex_r8_smp/ac5/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,12 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-31-2022 Scott Larson Initial Version 6.2.0 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -398,7 +393,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX ARMv7-R SMP Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX ARMv7-R SMP Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_r8_smp/ac5/src/tx_initialize_low_level.s b/ports_smp/cortex_r8_smp/ac5/src/tx_initialize_low_level.s index 1a56bb28..b6a6acf6 100644 --- a/ports_smp/cortex_r8_smp/ac5/src/tx_initialize_low_level.s +++ b/ports_smp/cortex_r8_smp/ac5/src/tx_initialize_low_level.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,13 +60,6 @@ /* CALLED BY */ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-31-2022 Scott Larson Initial Version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) // { diff --git a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_context_restore.s b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_context_restore.s index ec4e617b..b81f428b 100644 --- a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_context_restore.s +++ b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_context_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -75,13 +76,6 @@ SVC_MODE EQU 0x93 // SVC mode /* CALLED BY */ /* */ /* ISRs Interrupt Service Routines */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-31-2022 Scott Larson Initial Version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) // { diff --git a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_context_save.s b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_context_save.s index ea720373..780a6b0a 100644 --- a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_context_save.s +++ b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,13 +60,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-31-2022 Scott Larson Initial Version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) // { diff --git a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_interrupt_control.s b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_interrupt_control.s index acf9c826..b4344970 100644 --- a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_interrupt_control.s +++ b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_interrupt_control.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,13 +57,6 @@ INT_MASK EQU 0x80 // Interrupt bit mask /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-31-2022 Scott Larson Initial Version 6.2.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) // { diff --git a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_interrupt_disable.s b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_interrupt_disable.s index 734893bb..89947abf 100644 --- a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_interrupt_disable.s +++ b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_interrupt_disable.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -49,13 +50,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-31-2022 Scott Larson Initial Version 6.2.0 */ -/* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(void) // { diff --git a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_interrupt_restore.s b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_interrupt_restore.s index 5965475b..83065af2 100644 --- a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_interrupt_restore.s +++ b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_interrupt_restore.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -50,13 +51,6 @@ /* CALLED BY */ /* */ /* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-31-2022 Scott Larson Initial Version 6.2.0 */ -/* */ /**************************************************************************/ EXPORT _tx_thread_interrupt_restore _tx_thread_interrupt_restore diff --git a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_irq_nesting_end.s b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_irq_nesting_end.s index 5dfb8c00..ca0fd244 100644 --- a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_irq_nesting_end.s +++ b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_irq_nesting_end.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,13 +67,6 @@ IRQ_MODE_BITS EQU 0x12 // IRQ mode bits /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-31-2022 Scott Larson Initial Version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_irq_nesting_end(VOID) // { diff --git a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_irq_nesting_start.s b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_irq_nesting_start.s index d9594ba3..d2331c69 100644 --- a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_irq_nesting_start.s +++ b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_irq_nesting_start.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,13 +61,6 @@ SYS_MODE_BITS EQU 0x1F // System mode bits /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-31-2022 Scott Larson Initial Version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_irq_nesting_start(VOID) // { diff --git a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_schedule.s b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_schedule.s index 24cf373a..c06d7ef3 100644 --- a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_schedule.s +++ b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_schedule.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,13 +62,6 @@ /* _tx_initialize_kernel_enter ThreadX entry function */ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-31-2022 Scott Larson Initial Version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) // { diff --git a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_core_get.s b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_core_get.s index 1243e5b3..265bd658 100644 --- a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_core_get.s +++ b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_core_get.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -49,13 +50,6 @@ /* CALLED BY */ /* */ /* ThreadX Source */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-31-2022 Scott Larson Initial Version 6.2.0 */ -/* */ /**************************************************************************/ EXPORT _tx_thread_smp_core_get _tx_thread_smp_core_get diff --git a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_core_preempt.s b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_core_preempt.s index e1842a39..c18cc5b0 100644 --- a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_core_preempt.s +++ b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_core_preempt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,13 +57,6 @@ /* CALLED BY */ /* */ /* ThreadX Source */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-31-2022 Scott Larson Initial Version 6.2.0 */ -/* */ /**************************************************************************/ EXPORT _tx_thread_smp_core_preempt _tx_thread_smp_core_preempt diff --git a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_current_state_get.s b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_current_state_get.s index 7f95c6e7..e24fe15d 100644 --- a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_current_state_get.s +++ b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_current_state_get.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -52,13 +53,6 @@ /* CALLED BY */ /* */ /* ThreadX Components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-31-2022 Scott Larson Initial Version 6.2.0 */ -/* */ /**************************************************************************/ EXPORT _tx_thread_smp_current_state_get _tx_thread_smp_current_state_get diff --git a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_current_thread_get.s b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_current_thread_get.s index 5b6c3546..fd60692c 100644 --- a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_current_thread_get.s +++ b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_current_thread_get.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* ThreadX Components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-31-2022 Scott Larson Initial Version 6.2.0 */ -/* */ /**************************************************************************/ EXPORT _tx_thread_smp_current_thread_get _tx_thread_smp_current_thread_get diff --git a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_initialize_wait.s b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_initialize_wait.s index a262bccb..ef36dc2b 100644 --- a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_initialize_wait.s +++ b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_initialize_wait.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,13 +58,6 @@ /* CALLED BY */ /* */ /* Hardware */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-31-2022 Scott Larson Initial Version 6.2.0 */ -/* */ /**************************************************************************/ EXPORT _tx_thread_smp_initialize_wait _tx_thread_smp_initialize_wait diff --git a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_low_level_initialize.s b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_low_level_initialize.s index 0e33abd5..d58ec13e 100644 --- a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_low_level_initialize.s +++ b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_low_level_initialize.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* _tx_initialize_high_level ThreadX high-level init */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-31-2022 Scott Larson Initial Version 6.2.0 */ -/* */ /**************************************************************************/ EXPORT _tx_thread_smp_low_level_initialize _tx_thread_smp_low_level_initialize diff --git a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_protect.s b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_protect.s index 17f7a25f..5f8d8f05 100644 --- a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_protect.s +++ b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_protect.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,13 +56,6 @@ /* CALLED BY */ /* */ /* ThreadX Source */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-31-2022 Scott Larson Initial Version 6.2.0 */ -/* */ /**************************************************************************/ EXPORT _tx_thread_smp_protect _tx_thread_smp_protect diff --git a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_time_get.s b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_time_get.s index 2bbe34b4..a43484d7 100644 --- a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_time_get.s +++ b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_time_get.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -51,13 +52,6 @@ /* CALLED BY */ /* */ /* ThreadX Source */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-31-2022 Scott Larson Initial Version 6.2.0 */ -/* */ /**************************************************************************/ EXPORT _tx_thread_smp_time_get _tx_thread_smp_time_get diff --git a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_unprotect.s b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_unprotect.s index fdb4cd4b..9ce98b04 100644 --- a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_unprotect.s +++ b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_smp_unprotect.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,13 +58,6 @@ /* CALLED BY */ /* */ /* ThreadX Source */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-31-2022 Scott Larson Initial Version 6.2.0 */ -/* */ /**************************************************************************/ EXPORT _tx_thread_smp_unprotect _tx_thread_smp_unprotect diff --git a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_stack_build.s b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_stack_build.s index 764e215a..c0b6acde 100644 --- a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_stack_build.s +++ b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_stack_build.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,13 +62,6 @@ THUMB_BIT EQU 0x20 // Thumb-bit /* CALLED BY */ /* */ /* _tx_thread_create Create thread service */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-31-2022 Scott Larson Initial Version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) // { diff --git a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_system_return.s b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_system_return.s index d6212546..2280a351 100644 --- a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_system_return.s +++ b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_system_return.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,13 +63,6 @@ /* CALLED BY */ /* */ /* ThreadX components */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-31-2022 Scott Larson Initial Version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) // { diff --git a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_vectored_context_save.s b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_vectored_context_save.s index 1c80952b..c62297e8 100644 --- a/ports_smp/cortex_r8_smp/ac5/src/tx_thread_vectored_context_save.s +++ b/ports_smp/cortex_r8_smp/ac5/src/tx_thread_vectored_context_save.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,13 +59,6 @@ /* CALLED BY */ /* */ /* ISRs */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-31-2022 Scott Larson Initial Version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_thread_vectored_context_save(VOID) // { diff --git a/ports_smp/cortex_r8_smp/ac5/src/tx_timer_interrupt.s b/ports_smp/cortex_r8_smp/ac5/src/tx_timer_interrupt.s index aab63a43..236fe6b3 100644 --- a/ports_smp/cortex_r8_smp/ac5/src/tx_timer_interrupt.s +++ b/ports_smp/cortex_r8_smp/ac5/src/tx_timer_interrupt.s @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,13 +73,6 @@ /* CALLED BY */ /* */ /* interrupt vector */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-31-2022 Scott Larson Initial Version 6.2.0 */ -/* */ /**************************************************************************/ // VOID _tx_timer_interrupt(VOID) // { diff --git a/ports_smp/linux/gnu/example_build/Makefile b/ports_smp/linux/gnu/example_build/Makefile index 04e19347..4ae0bd9f 100644 --- a/ports_smp/linux/gnu/example_build/Makefile +++ b/ports_smp/linux/gnu/example_build/Makefile @@ -34,7 +34,7 @@ $(OUTPUT_FOLDER): sample_threadx: $(OUTPUT_FOLDER)/sample_threadx.o tx.a echo LD $@ - $(LINK) -o $@ $^ $(LIBS) + $(LINK) -o $@ $^ $(LIBS) tx.a: $(OUTPUT_FOLDER) $(LINUX_OBJS) $(GENERIC_OBJS) echo AR $@ @@ -68,7 +68,7 @@ files: do \ filename=`basename $$file`; \ [ "$$file" == "sample_threadx.c" ] || echo "$$filename \\" >> $(FILE_LIST); \ - done; + done; @printf "\n" >> $(FILE_LIST); @echo 'LINUX_OBJS = $$(LINUX_SRCS:%.c=$(OUTPUT_FOLDER)/%.o)' >> $(FILE_LIST); @printf "\n\n" >> $(FILE_LIST); @@ -77,7 +77,7 @@ files: do \ filename=`basename $$file`; \ [ "$$file" == "sample_threadx.c" ] || echo "$$filename \\" >> $(FILE_LIST); \ - done; + done; @printf "\n" >> $(FILE_LIST); @echo 'GENERIC_OBJS = $$(GENERIC_SRCS:%.c=$(OUTPUT_FOLDER)/generic/%.o)' >> $(FILE_LIST); diff --git a/ports_smp/linux/gnu/example_build/sample_threadx.c b/ports_smp/linux/gnu/example_build/sample_threadx.c index 34bdc481..0947b428 100644 --- a/ports_smp/linux/gnu/example_build/sample_threadx.c +++ b/ports_smp/linux/gnu/example_build/sample_threadx.c @@ -80,42 +80,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -123,23 +123,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -253,11 +253,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -316,7 +316,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -369,7 +369,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_smp/linux/gnu/inc/tx_port.h b/ports_smp/linux/gnu/inc/tx_port.h index 697ee8be..30c94702 100644 --- a/ports_smp/linux/gnu/inc/tx_port.h +++ b/ports_smp/linux/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,18 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ -/* macro definition, */ -/* resulting in version 6.1.6 */ -/* 10-15-2021 William E. Lamie Modified comment(s), added */ -/* symbol ULONG64_DEFINED, */ -/* resulting in version 6.1.9 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -173,7 +162,7 @@ typedef uint64_t ULONG64; #define ULONG64_DEFINED -/* Define automated coverage test extensions... These are required for the +/* Define automated coverage test extensions... These are required for the ThreadX regression test. */ typedef unsigned int TEST_FLAG; @@ -298,7 +287,7 @@ extern UINT priority_change_extension_selection; else \ { \ test_stack_analyze_flag = ((TEST_FLAG) 0); \ - } + } #define TX_INITIALIZE_KERNEL_ENTER_EXTENSION if (test_initialize_flag == ((TEST_FLAG) 1)) \ { \ @@ -633,7 +622,7 @@ void _tx_thread_smp_debug_entry_insert(ULONG id, ULONG su #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX SMP/Linux/gcc Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP/Linux/gcc Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/linux/gnu/readme_threadx.txt b/ports_smp/linux/gnu/readme_threadx.txt index 19d7c5b6..63cc3f34 100644 --- a/ports_smp/linux/gnu/readme_threadx.txt +++ b/ports_smp/linux/gnu/readme_threadx.txt @@ -1,4 +1,4 @@ - Microsoft's Azure RTOS ThreadX SMP for Linux + Microsoft's Azure RTOS ThreadX SMP for Linux Using the GNU GCC Tools @@ -8,29 +8,29 @@ First make sure you are in the "example_build" directory. Also, make sure that you have setup your path and other environment variables necessary for the GNU development environment. The following command retrieves and installs GCC multilib on a Ubuntu system: - + sudo apt-get install gcc-multilib -At this point you may run the GNU make command to build the ThreadX SMP core -library. This will build the ThreadX SMP run-time environment in the -"example_build" directory. +At this point you may run the GNU make command to build the ThreadX SMP core +library. This will build the ThreadX SMP run-time environment in the +"example_build" directory. make tx.a -you should now observe the compilation of the ThreadX SMP library source. At the +you should now observe the compilation of the ThreadX SMP library source. At the end of the make, they are all combined into the run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. - + 2. Demonstration System -Building the demonstration is easy; simply execute the GNU make command while -inside the "example_build" directory. +Building the demonstration is easy; simply execute the GNU make command while +inside the "example_build" directory. make sample_threadx -You should observe the compilation of sample_threadx.c (which is the demonstration -application) and linking with tx.a. The resulting file DEMO is a binary file +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file DEMO is a binary file that can be executed. 2.1 Includes @@ -56,15 +56,15 @@ the tx_port.h header to include tx_user.h. 3. System Initialization -The system entry point is at main(), which is defined in the application. -Once the application calls tx_kernel_enter, ThreadX SMP starts running and -performs various initialization duties prior to starting the scheduler. The +The system entry point is at main(), which is defined in the application. +Once the application calls tx_kernel_enter, ThreadX SMP starts running and +performs various initialization duties prior to starting the scheduler. The Linux-specific initialization is done in the function _tx_initialize_low_level, -which is located in the file tx_initialize_low_level.c. This function is -responsible for setting up various system data structures and simulated +which is located in the file tx_initialize_low_level.c. This function is +responsible for setting up various system data structures and simulated interrupts - including the periodic timer interrupt source for ThreadX. -In addition, _tx_initialize_low_level determines the first available +In addition, _tx_initialize_low_level determines the first available address for use by the application. In Linux, this is basically done by using malloc to get a big block of memory from Linux. @@ -73,12 +73,12 @@ by using malloc to get a big block of memory from Linux. ThreadX SMP for Linux is implemented using POSIX pthreads. Each application thread in ThreadX SMP actually runs as a Linux pthread. The determination of -which application thread to run is made by the ThreadX SMP scheduler, which -itself is a Linux pthread. The ThreadX SMP scheduler is the highest priority +which application thread to run is made by the ThreadX SMP scheduler, which +itself is a Linux pthread. The ThreadX SMP scheduler is the highest priority thread in the system. Interrupts in ThreadX_SMP Linux are also simulated by pthreads. A good example -is the ThreadX SMP system timer interrupt, which can be found in +is the ThreadX SMP system timer interrupt, which can be found in tx_initialize_low_level.c. ThreadX SMP for linux utilizes the API pthread_setschedparam() which requires @@ -89,12 +89,12 @@ to run a ThreadX SMP application: 5. Improving Performance -The distribution version of ThreadX SMP is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX SMP itself. Of course, this costs some -performance. To make it run faster, you can change the makefile to -enable all compiler optimizations. In addition, you can eliminate the -ThreadX SMP basic API error checking by compiling your application code with the +The distribution version of ThreadX SMP is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX SMP itself. Of course, this costs some +performance. To make it run faster, you can change the makefile to +enable all compiler optimizations. In addition, you can eliminate the +ThreadX SMP basic API error checking by compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING defined. @@ -102,7 +102,7 @@ symbol TX_DISABLE_ERROR_CHECKING defined. ThreadX SMP provides simulated interrupt handling with Linux pthreads. Simulated interrupt threads may be created by the application or may be added to the -simulated timer interrupt defined in tx_initialize_low_level.c. The following +simulated timer interrupt defined in tx_initialize_low_level.c. The following format for creating simulated interrupts should be used: 6.1 Data structures @@ -133,7 +133,7 @@ struct sched_param sp; 6.3 Simulated Interrupt Thread Template The following is a template for the simulated interrupt thread. This interrupt will occur on -a periodic basis. +a periodic basis. void *_sample_linux_interrupt_entry(void *p) { @@ -154,7 +154,7 @@ struct timespec ts; /* Call ThreadX SMP context restore for interrupt completion. */ _tx_thread_context_restore(); - } + } } diff --git a/ports_smp/linux/gnu/src/tx_initialize_low_level.c b/ports_smp/linux/gnu/src/tx_initialize_low_level.c index a73d4cfc..f0faf2ce 100644 --- a/ports_smp/linux/gnu/src/tx_initialize_low_level.c +++ b/ports_smp/linux/gnu/src/tx_initialize_low_level.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -222,12 +223,6 @@ extern VOID *_tx_initialize_unused_memory; /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_initialize_low_level(VOID) { diff --git a/ports_smp/linux/gnu/src/tx_thread_context_restore.c b/ports_smp/linux/gnu/src/tx_thread_context_restore.c index e90db8c9..fb921777 100644 --- a/ports_smp/linux/gnu/src/tx_thread_context_restore.c +++ b/ports_smp/linux/gnu/src/tx_thread_context_restore.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,12 +72,6 @@ UINT _tx_linux_timer_waiting = 0; /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_thread_context_restore(VOID) { diff --git a/ports_smp/linux/gnu/src/tx_thread_context_save.c b/ports_smp/linux/gnu/src/tx_thread_context_save.c index 67a91176..fd369cc6 100644 --- a/ports_smp/linux/gnu/src/tx_thread_context_save.c +++ b/ports_smp/linux/gnu/src/tx_thread_context_save.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,12 +66,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_thread_context_save(VOID) { diff --git a/ports_smp/linux/gnu/src/tx_thread_interrupt_control.c b/ports_smp/linux/gnu/src/tx_thread_interrupt_control.c index f8c47bdd..b1b09ec7 100644 --- a/ports_smp/linux/gnu/src/tx_thread_interrupt_control.c +++ b/ports_smp/linux/gnu/src/tx_thread_interrupt_control.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -83,12 +84,6 @@ VOID _tx_thread_interrupt_restore(UINT previous_posture) /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_interrupt_control(UINT new_posture) { diff --git a/ports_smp/linux/gnu/src/tx_thread_schedule.c b/ports_smp/linux/gnu/src/tx_thread_schedule.c index c27ddfc6..0c3e8e32 100644 --- a/ports_smp/linux/gnu/src/tx_thread_schedule.c +++ b/ports_smp/linux/gnu/src/tx_thread_schedule.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -72,12 +73,6 @@ extern pthread_t _tx_linux_timer_id; /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_thread_schedule(VOID) { diff --git a/ports_smp/linux/gnu/src/tx_thread_smp_core_get.c b/ports_smp/linux/gnu/src/tx_thread_smp_core_get.c index d829d848..0d141e81 100644 --- a/ports_smp/linux/gnu/src/tx_thread_smp_core_get.c +++ b/ports_smp/linux/gnu/src/tx_thread_smp_core_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_smp_core_get(void) { diff --git a/ports_smp/linux/gnu/src/tx_thread_smp_core_preempt.c b/ports_smp/linux/gnu/src/tx_thread_smp_core_preempt.c index 759282d2..e0f6c86d 100644 --- a/ports_smp/linux/gnu/src/tx_thread_smp_core_preempt.c +++ b/ports_smp/linux/gnu/src/tx_thread_smp_core_preempt.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -67,12 +68,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ void _tx_thread_smp_core_preempt(UINT core) { diff --git a/ports_smp/linux/gnu/src/tx_thread_smp_current_state_get.c b/ports_smp/linux/gnu/src/tx_thread_smp_current_state_get.c index 29beb817..d460d22e 100644 --- a/ports_smp/linux/gnu/src/tx_thread_smp_current_state_get.c +++ b/ports_smp/linux/gnu/src/tx_thread_smp_current_state_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ ULONG _tx_thread_smp_current_state_get(void) { diff --git a/ports_smp/linux/gnu/src/tx_thread_smp_current_thread_get.c b/ports_smp/linux/gnu/src/tx_thread_smp_current_thread_get.c index faea6218..c6b1a7a7 100644 --- a/ports_smp/linux/gnu/src/tx_thread_smp_current_thread_get.c +++ b/ports_smp/linux/gnu/src/tx_thread_smp_current_thread_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ TX_THREAD *_tx_thread_smp_current_thread_get(void) { diff --git a/ports_smp/linux/gnu/src/tx_thread_smp_initialize_wait.c b/ports_smp/linux/gnu/src/tx_thread_smp_initialize_wait.c index 220c2c2f..a4369ff5 100644 --- a/ports_smp/linux/gnu/src/tx_thread_smp_initialize_wait.c +++ b/ports_smp/linux/gnu/src/tx_thread_smp_initialize_wait.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,12 +66,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ void _tx_thread_smp_initialize_wait(void) { diff --git a/ports_smp/linux/gnu/src/tx_thread_smp_low_level_initialize.c b/ports_smp/linux/gnu/src/tx_thread_smp_low_level_initialize.c index 3f452418..1e1c475f 100644 --- a/ports_smp/linux/gnu/src/tx_thread_smp_low_level_initialize.c +++ b/ports_smp/linux/gnu/src/tx_thread_smp_low_level_initialize.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -64,12 +65,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ void _tx_thread_smp_low_level_initialize(UINT number_of_cores) { diff --git a/ports_smp/linux/gnu/src/tx_thread_smp_protect.c b/ports_smp/linux/gnu/src/tx_thread_smp_protect.c index 88d028ba..8a9aa297 100644 --- a/ports_smp/linux/gnu/src/tx_thread_smp_protect.c +++ b/ports_smp/linux/gnu/src/tx_thread_smp_protect.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -65,12 +66,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ UINT _tx_thread_smp_protect(void) { diff --git a/ports_smp/linux/gnu/src/tx_thread_smp_time_get.c b/ports_smp/linux/gnu/src/tx_thread_smp_time_get.c index ae5e7595..f4095d26 100644 --- a/ports_smp/linux/gnu/src/tx_thread_smp_time_get.c +++ b/ports_smp/linux/gnu/src/tx_thread_smp_time_get.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -61,12 +62,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ ULONG _tx_thread_smp_time_get(void) { diff --git a/ports_smp/linux/gnu/src/tx_thread_smp_unprotect.c b/ports_smp/linux/gnu/src/tx_thread_smp_unprotect.c index 6353ea7a..7428666f 100644 --- a/ports_smp/linux/gnu/src/tx_thread_smp_unprotect.c +++ b/ports_smp/linux/gnu/src/tx_thread_smp_unprotect.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,12 +63,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ void _tx_thread_smp_unprotect(UINT new_interrupt_posture) { diff --git a/ports_smp/linux/gnu/src/tx_thread_stack_build.c b/ports_smp/linux/gnu/src/tx_thread_stack_build.c index 4869b480..1b491a3a 100644 --- a/ports_smp/linux/gnu/src/tx_thread_stack_build.c +++ b/ports_smp/linux/gnu/src/tx_thread_stack_build.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -76,12 +77,6 @@ void *_tx_linux_thread_entry(void *ptr); /* _tx_thread_create Create thread service */ /* _tx_thread_reset Reset thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) { diff --git a/ports_smp/linux/gnu/src/tx_thread_system_return.c b/ports_smp/linux/gnu/src/tx_thread_system_return.c index 9da9b03f..cb961562 100644 --- a/ports_smp/linux/gnu/src/tx_thread_system_return.c +++ b/ports_smp/linux/gnu/src/tx_thread_system_return.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -73,12 +74,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_thread_system_return(VOID) { diff --git a/ports_smp/linux/gnu/src/tx_timer_interrupt.c b/ports_smp/linux/gnu/src/tx_timer_interrupt.c index 29db2e53..ed022291 100644 --- a/ports_smp/linux/gnu/src/tx_timer_interrupt.c +++ b/ports_smp/linux/gnu/src/tx_timer_interrupt.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,12 +67,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ VOID _tx_timer_interrupt(VOID) { diff --git a/ports_smp/mips32_interaptiv_smp/gnu/example_build/demo_threadx.c b/ports_smp/mips32_interaptiv_smp/gnu/example_build/demo_threadx.c index 2f1bb446..c03bad2f 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/example_build/demo_threadx.c +++ b/ports_smp/mips32_interaptiv_smp/gnu/example_build/demo_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -116,49 +116,49 @@ CHAR *pointer; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for LCD thread. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the lcd thread. */ - tx_thread_create(&lcd_thread, "lcd thread", lcd_thread_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&lcd_thread, "lcd thread", lcd_thread_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -166,23 +166,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -211,9 +211,9 @@ CHAR *pointer; /* Release the block back to the pool. */ tx_block_release(pointer); - + /* Indicate that we are ready to start scheduling, which will happen after - this rountine returns. */ + this rountine returns. */ *((ULONG *) MALTA_ASCIIPOS0) = 'T'; *((ULONG *) MALTA_ASCIIPOS1) = 'X'; *((ULONG *) MALTA_ASCIIPOS2) = ' '; @@ -296,7 +296,7 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; @@ -323,7 +323,7 @@ UINT status; thread_3_counter++; else thread_4_counter++; - + /* Get the semaphore with suspension. */ status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); @@ -359,7 +359,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -412,7 +412,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_smp/mips32_interaptiv_smp/gnu/example_build/demo_threadx.ld b/ports_smp/mips32_interaptiv_smp/gnu/example_build/demo_threadx.ld index b515b49e..c09b2a6c 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/example_build/demo_threadx.ld +++ b/ports_smp/mips32_interaptiv_smp/gnu/example_build/demo_threadx.ld @@ -51,15 +51,15 @@ SECTIONS { _fdata = ABSOLUTE(.); /* Start of initialised data */ *(.data*) - + . = ALIGN(8); _gp = ABSOLUTE(. + 0x7ff0); /* Base of small data */ LC8 = ABSOLUTE(. + 0x7ff0); /* Base of small data */ - *(.lit8) - *(.lit4) - *(.sdata*) + *(.lit8) + *(.lit4) + *(.sdata*) . = ALIGN(8); @@ -68,10 +68,10 @@ SECTIONS /**** Uninitialised data ****/ - .sbss : - { + .sbss : + { _start_sbss = .; - *(.sbss*) + *(.sbss*) *(.scommon) _end_sbss = .; } diff --git a/ports_smp/mips32_interaptiv_smp/gnu/example_build/init_CoreFPGA6_mem.S b/ports_smp/mips32_interaptiv_smp/gnu/example_build/init_CoreFPGA6_mem.S index d3932010..a3e9c997 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/example_build/init_CoreFPGA6_mem.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/example_build/init_CoreFPGA6_mem.S @@ -64,6 +64,6 @@ LEAF(init_CoreFPGA6_mem) */ jr ra nop - + END(init_CoreFPGA6_mem) diff --git a/ports_smp/mips32_interaptiv_smp/gnu/example_build/init_mc_denali.S b/ports_smp/mips32_interaptiv_smp/gnu/example_build/init_mc_denali.S index 8e109a7c..2f36931d 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/example_build/init_mc_denali.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/example_build/init_mc_denali.S @@ -3,7 +3,7 @@ * * Created on: Jan 12, 2011 * Author: MIPS TECHNOLOGIES, INC - + Initialization code for Denali memory controller needed for CoreFPGA5 */ /* diff --git a/ports_smp/mips32_interaptiv_smp/gnu/example_build/m32c0.h b/ports_smp/mips32_interaptiv_smp/gnu/example_build/m32c0.h index 4e7e3f6b..131ad1c2 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/example_build/m32c0.h +++ b/ports_smp/mips32_interaptiv_smp/gnu/example_build/m32c0.h @@ -13,13 +13,13 @@ /* * Copyright (c) 1999-2007 MIPS Technologies, Inc. * Copyright (C) 2009 CodeSourcery, LLC. - * + * * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: - * + * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above @@ -30,7 +30,7 @@ * * Neither the name of MIPS Technologies Inc. nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -323,13 +323,13 @@ extern "C" { #define CFG_C_WTHRU_NOALLOC 0 #define CFG_C_WTHRU_ALLOC 1 #define CFG_C_COHERENTXCL 4 -#define CFG_C_COHERENTXCLW 5 +#define CFG_C_COHERENTXCLW 5 #define CFG_C_COHERENTUPD 6 #define CFG_C_UNCACHED_ACCEL 7 #endif -/* +/* * Primary Cache TagLo (CP0 Register 28, Select 0/2) */ #define TAG_PTAG_MASK 0xffffff00 /* Primary Tag */ @@ -412,8 +412,8 @@ extern "C" { #ifdef __ASSEMBLER__ -/* - * MIPS32 Coprocessor 0 register numbers +/* + * MIPS32 Coprocessor 0 register numbers */ #define C0_INDEX $0 #define C0_INX $0 @@ -518,8 +518,8 @@ typedef unsigned long reg_t; typedef signed long sreg_t; #endif -/* - * MIPS32 Coprocessor 0 register numbers +/* + * MIPS32 Coprocessor 0 register numbers */ #define C0_INDEX 0 #define C0_INX 0 @@ -561,7 +561,7 @@ typedef signed long sreg_t; #define C0_DESAVE 31 #define _mips_nop() \ - __asm__ __volatile ("%(ssnop%)" : :) + __asm__ __volatile ("%(ssnop%)" : :) #if ! __mips16 || __force_mips16_asm # define _mips_sync() __asm__ __volatile__ ("sync" : : : "memory") @@ -573,7 +573,7 @@ extern void _mips_sync(void); #define _mips_wait() \ __asm__ __volatile ("wait") -/* +/* * Define macros for accessing the MIPS32 coprocessor 0 registers. * Most apart from "set" return the original register value. */ diff --git a/ports_smp/mips32_interaptiv_smp/gnu/example_build/regdef.h b/ports_smp/mips32_interaptiv_smp/gnu/example_build/regdef.h index 80fa7a6e..01197f47 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/example_build/regdef.h +++ b/ports_smp/mips32_interaptiv_smp/gnu/example_build/regdef.h @@ -9,7 +9,7 @@ #define a1 $5 #define a2 $6 #define a3 $7 -#define t0 $8 +#define t0 $8 #define t1 $9 #define t2 $10 #define t3 $11 @@ -17,7 +17,7 @@ #define t5 $13 #define t6 $14 #define t7 $15 -#define s0 $16 +#define s0 $16 #define s1 $17 #define s2 $18 #define s3 $19 @@ -25,9 +25,9 @@ #define s5 $21 #define s6 $22 #define s7 $23 -#define t8 $24 +#define t8 $24 #define t9 $25 -#define jp $25 +#define jp $25 #define k0 $26 /* reserved for OS */ #define k1 $27 /* reserved for OS */ #define gp $28 /* global pointer */ diff --git a/ports_smp/mips32_interaptiv_smp/gnu/example_build/start.S b/ports_smp/mips32_interaptiv_smp/gnu/example_build/start.S index 85c5d753..d0c2c031 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/example_build/start.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/example_build/start.S @@ -78,17 +78,17 @@ Technologies or an authorized third party. .section ".vector_0x000","ax" .globl tlb_refill_exception -tlb_refill_exception: +tlb_refill_exception: sdbbp .section ".vector_0x100","ax" .globl cache_error_exception -cache_error_exception: +cache_error_exception: sdbbp .section ".vector_0x180","ax" .globl general_exception -general_exception: +general_exception: /* EL Change: Branch to ThreadX error handling. */ @@ -144,10 +144,10 @@ iv1_interrupt: /* EL Change end. */ - + .section ".vector_0x280","ax" .globl xtlb_refill -xtlb_refill: +xtlb_refill: sdbbp .section ".vector_0x300","ax" @@ -205,7 +205,7 @@ init_common_resources: // initializes resources for virtual or physical "cpu". sw v1, 1088(v0) sw v1, 1096(v0) sw v1, 1104(v0) - .globl clear_done + .globl clear_done clear_done: la a2, init_cp0 // Init CP0 Status, Count, Compare, Watch*, and Cause. @@ -298,10 +298,10 @@ init_sys_resources: // We are core0 vpe0. nop /* EL Change. Ensure that the VPE release flag is cleared ahead of BSS clear. */ - + la $8, _tx_thread_smp_release_cores_flag # Build address of release flag sw $0, 0($8) # Clear the flag explicity to make other VPEs don't see it before everything is initialized - + /* EL end Change. */ @@ -346,14 +346,14 @@ init_done: mtc0 r23_cpu_num, $4,2 # Save the logical VPE in UserLocal so we don't have calculate it over and over! */ /* Save the stack pointer in the array indexed by cpu number. */ - + la $8, _tx_thread_system_stack_ptr # Build address of base of system stack array sll $9, r23_cpu_num, 2 # Build offset into array addu $8, $8, $9 # Build address of array entry sw $29, 0($8) # Store system stack for each VPE /* Setup status register in preparation for entering ThreadX. */ - + mfc0 $8, $12 # Pickup SR li $9, 0xFFFFFFF8 # Build mask to clear error, exception bits and $8, $8, $9 # Clear bits @@ -363,46 +363,46 @@ init_done: /* Check for Core 0, VPE 0 for processing ThreadX initialization. All other VPEs will wait until the first VPE has completed initialization before running. */ - + bne r23_cpu_num, $0, _additional_vpe # If non-zero, an additional vpe is present - nop # - + nop # + /* Core 0, VPE 0 processing. */ - + /* Save some information in globals. */ - + la $8, _tx_thread_smp_detected_cores # Build address of total number of cores detected addiu $9, r19_more_cores, 1 # Calculate the total cores sw $9, 0($8) # Save in global variable - + la $8, _tx_thread_smp_detected_vpes_per_core # Build address of VPEs per core detected addiu $9, r20_more_vpes, 1 # Caculate the total vpes per core sw $9, 0($8) # Save in global variable - + /* Simply branch to main to finish initializing ThreadX SMP. */ - + bal main # Branch to main - nop # - + nop # + /* If return, branch to all_done code. */ - + b all_done - nop - - + nop + + _additional_vpe: - + /* Additional VPE, transfer control to ThreadX. */ - + b _tx_thread_smp_initialize_wait # Enter ThreadX for additional VPEs nop .globl all_done all_done: b all_done - + /* Comment out the previous "init_done" code since it is replaced with ThreadX-specfic code. */ #if 0 @@ -441,7 +441,7 @@ all_done: // All cpu spin on atomic potato++ // la a1, potato - + try_again: ll a0, 0(a1) addiu a0, a0, 1 @@ -452,7 +452,7 @@ try_again: b try_again // Success, do again. nop - + b all_done nop #endif diff --git a/ports_smp/mips32_interaptiv_smp/gnu/inc/tx_port.h b/ports_smp/mips32_interaptiv_smp/gnu/inc/tx_port.h index 277c2bf7..a2429d57 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/inc/tx_port.h +++ b/ports_smp/mips32_interaptiv_smp/gnu/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,12 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial release version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -424,7 +419,7 @@ THREAD_SMP_DECLARE ULONG _tx_thread_smp_initial_fpu_control_register; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX SMP MIPS32_interAptiv/GNU Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP MIPS32_interAptiv/GNU Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/mips32_interaptiv_smp/gnu/readme_threadx.txt b/ports_smp/mips32_interaptiv_smp/gnu/readme_threadx.txt index 20ac0134..57e6fe21 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/readme_threadx.txt +++ b/ports_smp/mips32_interaptiv_smp/gnu/readme_threadx.txt @@ -4,17 +4,17 @@ 1. Installation -ThreadX for the MIPS32 interAptiv is delivered on a single CD-ROM compatible disk. +ThreadX for the MIPS32 interAptiv is delivered on a single CD-ROM compatible disk. The entire distribution can be found in the sub-directory: \threadx -To install ThreadX to your hard-disk, either run the supplied installer -program Setup.exe or copy the distribution from the CD manually. +To install ThreadX to your hard-disk, either run the supplied installer +program Setup.exe or copy the distribution from the CD manually. -To copy the ThreadX distribution manually, make a threadx directory on your -hard-disk (we recommend C:\threadx\mips32_interaptiv\gnu) and copy all the contents -of the threadx sub-directory on the distribution disk. The following +To copy the ThreadX distribution manually, make a threadx directory on your +hard-disk (we recommend C:\threadx\mips32_interaptiv\gnu) and copy all the contents +of the threadx sub-directory on the distribution disk. The following is an example MS-DOS copy command from the distribution directory (assuming source is d: and c: is your hard-drive): @@ -24,54 +24,54 @@ d:\threadx> xcopy /S *.* c:\threadx\mips32_interaptiv\gnu 2. Building the ThreadX run-time Library -First make sure you are in the ThreadX directory you have created on your -hard-drive. Also, make sure that you have setup your path and other +First make sure you are in the ThreadX directory you have created on your +hard-drive. Also, make sure that you have setup your path and other environment variables necessary for the GNU development environment. -At this point you may run the build_threadx.bat batch file. This will +At this point you may run the build_threadx.bat batch file. This will build the ThreadX run-time environment in the ThreadX directory. C:\threadx\mips32_interaptiv\gnu> build_threadx -You should observe assembly and compilation of a series of ThreadX source -files. At the end of the batch file, they are all combined into the -run-time library file: tx.a. This file must be linked with your +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your application in order to use ThreadX. 3. Demonstration System -Building the demonstration is easy; simply execute the build_threadx_demo.bat +Building the demonstration is easy; simply execute the build_threadx_demo.bat batch file while inside your ThreadX directory on your hard-disk. C:\threadx\mips32_interaptiv\gnu> build_threadx_demo -You should observe the compilation of demo_threadx.c (which is the demonstration +You should observe the compilation of demo_threadx.c (which is the demonstration application) and linking with tx.a. The resulting file demo_threadx.out is an ELF -binary file that can be downloaded and executed under simulation or on the MIPS +binary file that can be downloaded and executed under simulation or on the MIPS MALTA evaluation board. 4. System Initialization -The system entry point using the GNU tools is at the label _start. -This is defined within the start.S file supplied by MIPS. In addition, -this is where all static and global preset C variable initialization +The system entry point using the GNU tools is at the label _start. +This is defined within the start.S file supplied by MIPS. In addition, +this is where all static and global preset C variable initialization processing is called from. -Once the startup function finishes, main is called, which is also where ThreadX -initialization takes place. The main initialization function for ThreadX is -_tx_initialize_low_level and is located in the file tx_initialize_low_level.S. -This function is responsible for setting up various system data structures, +Once the startup function finishes, main is called, which is also where ThreadX +initialization takes place. The main initialization function for ThreadX is +_tx_initialize_low_level and is located in the file tx_initialize_low_level.S. +This function is responsible for setting up various system data structures, interrupt vectors, and the periodic timer interrupt source of ThreadX. -In addition, _tx_initialize_low_level determines where the first available +In addition, _tx_initialize_low_level determines where the first available RAM memory address is located. This address is supplied to tx_application_define. -By default, the first available RAM memory address is assumed to start at the -beginning of the ThreadX symbol _free_memory. If changes are made to the -demo_threadx.ld file, the _free_memory symbol should remain the last allocated -section in the main RAM area. The starting address of this section is passed +By default, the first available RAM memory address is assumed to start at the +beginning of the ThreadX symbol _free_memory. If changes are made to the +demo_threadx.ld file, the _free_memory symbol should remain the last allocated +section in the main RAM area. The starting address of this section is passed to tx_application_define. @@ -82,17 +82,17 @@ Please reference the ThreadX_SMP_User_Guide.pdf for details on build options. 6. Register Usage and Stack Frames -The GNU MIPS compiler assumes that registers t0-t9 ($8-$15, $24, $25) -are scratch registers for each function. All other registers used by a -C function must be preserved by the function. ThreadX takes advantage -of this in situations where a context switch happens as a result of making a -ThreadX service call (which is itself a C function). In such cases, the +The GNU MIPS compiler assumes that registers t0-t9 ($8-$15, $24, $25) +are scratch registers for each function. All other registers used by a +C function must be preserved by the function. ThreadX takes advantage +of this in situations where a context switch happens as a result of making a +ThreadX service call (which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -124,7 +124,7 @@ associated thread control block TX_THREAD. 0x058 a3 ($7) f27 | 0x05C a2 ($6) | 0x060 a1 ($5) f26 | - 0x064 a0 ($4) + 0x064 a0 ($4) 0x068 v1 ($3) f25 TX_ENABLE_64BIT_FPU_SUPPORT 0x06C v0 ($2) 0x070 at ($1) f24 | @@ -136,14 +136,14 @@ associated thread control block TX_THREAD. 0x090 f29 | f20 | 0x098 f28 | fcr31 <------------+ 0x09C | not used - 0x0A0 f27 | - 0x0A4 | - 0x0A8 f26 | - 0x0AC | - 0x0B0 f25 | - 0x0B4 | - 0x0B8 f24 | - 0x0BC | + 0x0A0 f27 | + 0x0A4 | + 0x0A8 f26 | + 0x0AC | + 0x0B0 f25 | + 0x0B4 | + 0x0B8 f24 | + 0x0BC | 0x0C0 f23 | 0x0C8 f22 | 0x0D0 f21 | @@ -174,50 +174,50 @@ associated thread control block TX_THREAD. 7. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make ThreadX run faster, you can change the tx.gpj project -to disable debug information and enable the desired optimizations. +to disable debug information and enable the desired optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined before tx_api.h is included. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. 8. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for MIPS32 interAptiv targets. The general exception handler is at address: 0x80000180 (0xA0000180 non- -cached). The ThreadX general exception handler is defined in the file -tx_initialize_low_level.S at the label _tx_exception_handler. A small piece of -code to jump to this exception handler is copied to the general exception handler +cached). The ThreadX general exception handler is defined in the file +tx_initialize_low_level.S at the label _tx_exception_handler. A small piece of +code to jump to this exception handler is copied to the general exception handler address during initialization. 8.1 Application ISRs -Multiple exceptions may be processed with a single execution of the exception +Multiple exceptions may be processed with a single execution of the exception handler. This is because the Cause register could indicate more than a single -exception. Processing for each exception is also located in the general -exception handler that starts at the label: _tx_exception_handler. Application +exception. Processing for each exception is also located in the general +exception handler that starts at the label: _tx_exception_handler. Application ISRs can be added into this handler. 9. Theory of Operation - SMP -ThreadX for the MIPS interAptiv brings Symmetric Multi-Processing (SMP) technology to -the MIPS interAptiv. ThreadX application threads (of varying priority) that are "READY" -to run are dynamically allocated to VPEs during scheduling, thus taking full -advantage of all available MIPS interAptiv VPEs. This results in true SMP processing, -including automatic load balancing of application thread execution across all -available MIPS interAptiv VPEs. +ThreadX for the MIPS interAptiv brings Symmetric Multi-Processing (SMP) technology to +the MIPS interAptiv. ThreadX application threads (of varying priority) that are "READY" +to run are dynamically allocated to VPEs during scheduling, thus taking full +advantage of all available MIPS interAptiv VPEs. This results in true SMP processing, +including automatic load balancing of application thread execution across all +available MIPS interAptiv VPEs. Initialization is done exclusively in VPE 0, which is the default running VPE -after reset. The additional VPEs on the interAptiv are initialized by VPE 0 and simply +after reset. The additional VPEs on the interAptiv are initialized by VPE 0 and simply wait until VPE 0 completes the initialization before they start running. -During thread execution, multithreading in the MIPS interAptiv is fully enabled. This -means that application threads may be preempted by higher priority threads, may +During thread execution, multithreading in the MIPS interAptiv is fully enabled. This +means that application threads may be preempted by higher priority threads, may suspend themselves, or may exit the system upon completion of their work. Protection between VPEs is accomplished via a conditional load-store structure (see the variable _tx_thread_smp_protection and the typedef TX_THREAD_SMP_PROTECT found in tx_thread.h). @@ -226,11 +226,11 @@ All VPEs are eligible to handle interrupts under the direction of the applicatio ThreadX timer interrupt is by default assigned to VPE 0 for processing. Please see the code in tx_timer_interrupt.S for the implementation. -ThreadX for the MIPS interAptiv also optionally supports the MIPS interAptiv FPU. +ThreadX for the MIPS interAptiv also optionally supports the MIPS interAptiv FPU. -The number of VPEs is defined by the compile time constant TX_THREAD_SMP_MAX_CORES. -By default, this is set to 2 in tx_port.h. It may be changed to support any number -of cores either in tx_port.h or on the command line via a -D symbol definition. +The number of VPEs is defined by the compile time constant TX_THREAD_SMP_MAX_CORES. +By default, this is set to 2 in tx_port.h. It may be changed to support any number +of cores either in tx_port.h or on the command line via a -D symbol definition. 10. Current Limitations @@ -241,7 +241,7 @@ of cores either in tx_port.h or on the command line via a -D symbol definition. 11. Debug Information -ThreadX SMP for MIPS32 interAptiv has a built-in debug facility to capture SMP scheduling +ThreadX SMP for MIPS32 interAptiv has a built-in debug facility to capture SMP scheduling information. This is enabled by building the system with TX_THREAD_SMP_DEBUG_ENABLE defined. This results in the creation of circular log containing debug information. The log is defined in the variable _tx_thread_smp_debug_info_array. @@ -254,7 +254,7 @@ file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -03-08-2023 Initial ThreadX version 6.2.1 of MIPS32_interAptiv VPE/GNU port. +03-08-2023 Initial ThreadX version 6.2.1 of MIPS32_interAptiv VPE/GNU port. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_initialize_low_level.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_initialize_low_level.S index d9e6dcdf..91d7e9ad 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_initialize_low_level.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_initialize_low_level.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -70,12 +71,6 @@ /* */ /* _tx_initialize_kernel_enter ThreadX entry function */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ /* VOID _tx_initialize_low_level(VOID) { */ @@ -148,7 +143,7 @@ _tx_exception_trampoline_end: .globl _tx_exception_handler _tx_exception_handler: mfc0 $26, $13 # Pickup the cause register - ehb # + ehb # andi $26, $26, 0x3C # Isolate the exception code bne $26, $0, _tx_error_exceptions # If non-zero, an error exception is present nop # Delay slot diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_context_restore.S index 8041530e..68bf8f74 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_context_restore.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* ISRs Interrupt Service Routines */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_context_restore(VOID) { */ diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_context_save.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_context_save.S index 3956627b..29dd34df 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_context_save.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_context_save.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,12 +60,6 @@ /* */ /* ISRs */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_context_save(VOID) { */ diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_interrupt_control.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_interrupt_control.S index 96d08e4d..b3891443 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_interrupt_control.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_interrupt_control.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,12 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_control(UINT new_posture) { */ diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_schedule.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_schedule.S index c07b112e..9a0903e0 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_schedule.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -66,12 +67,6 @@ /* _tx_thread_system_return Return to system from thread */ /* _tx_thread_context_restore Restore thread's context */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_schedule(VOID) { */ diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_core_get.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_core_get.S index 415c8f67..24f6a72b 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_core_get.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_core_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -54,12 +55,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ .globl _tx_thread_smp_core_get _tx_thread_smp_core_get: diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_core_preempt.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_core_preempt.S index ba8d8d32..c8421b38 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_core_preempt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -59,12 +60,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ .globl _tx_thread_smp_core_preempt _tx_thread_smp_core_preempt: diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_current_state_get.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_current_state_get.S index 37129173..2d71d816 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_current_state_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ .globl _tx_thread_smp_current_state_get _tx_thread_smp_current_state_get: diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_current_thread_get.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_current_thread_get.S index e736c01b..d2c935bb 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_current_thread_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* ThreadX Components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ .globl _tx_thread_smp_current_thread_get _tx_thread_smp_current_thread_get: diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_initialize_wait.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_initialize_wait.S index a020eb51..45b4dbf5 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_initialize_wait.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,12 +58,6 @@ /* */ /* Hardware */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ .globl _tx_thread_smp_initialize_wait _tx_thread_smp_initialize_wait: diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_low_level_initialize.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_low_level_initialize.S index a4da322c..cff81460 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_low_level_initialize.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -56,12 +57,6 @@ /* */ /* _tx_initialize_high_level ThreadX high-level init */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ .globl _tx_thread_smp_low_level_initialize _tx_thread_smp_low_level_initialize: diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_protect.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_protect.S index b7f56204..19b8d598 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_protect.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_protect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,12 +58,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ .globl _tx_thread_smp_protect _tx_thread_smp_protect: diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_time_get.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_time_get.S index aab00dd2..de57904f 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_time_get.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_time_get.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -55,12 +56,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ .globl _tx_thread_smp_time_get _tx_thread_smp_time_get: diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_unprotect.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_unprotect.S index 0f267771..847a729e 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_unprotect.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_smp_unprotect.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,12 +59,6 @@ /* */ /* ThreadX Source */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ .globl _tx_thread_smp_unprotect _tx_thread_smp_unprotect: diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_stack_build.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_stack_build.S index b0205f59..d0b84539 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_stack_build.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_stack_build.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,12 +58,6 @@ /* */ /* _tx_thread_create Create thread service */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) { */ diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_system_return.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_system_return.S index d8a82a82..a0ae7af7 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_thread_system_return.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -60,12 +61,6 @@ /* */ /* ThreadX components */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ /* VOID _tx_thread_system_return(VOID) { */ diff --git a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_timer_interrupt.S b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_timer_interrupt.S index e2725297..64ea13a7 100644 --- a/ports_smp/mips32_interaptiv_smp/gnu/src/tx_timer_interrupt.S +++ b/ports_smp/mips32_interaptiv_smp/gnu/src/tx_timer_interrupt.S @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -62,12 +63,6 @@ /* */ /* interrupt vector */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ /* VOID _tx_timer_interrupt(VOID) { */ diff --git a/ports_smp/mips32_interaptiv_smp/green/example_build/demo_threadx.c b/ports_smp/mips32_interaptiv_smp/green/example_build/demo_threadx.c index 85b7ced8..8dcbcf10 100644 --- a/ports_smp/mips32_interaptiv_smp/green/example_build/demo_threadx.c +++ b/ports_smp/mips32_interaptiv_smp/green/example_build/demo_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -116,49 +116,49 @@ CHAR *pointer; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for LCD thread. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the lcd thread. */ - tx_thread_create(&lcd_thread, "lcd thread", lcd_thread_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&lcd_thread, "lcd thread", lcd_thread_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -166,23 +166,23 @@ CHAR *pointer; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -211,9 +211,9 @@ CHAR *pointer; /* Release the block back to the pool. */ tx_block_release(pointer); - + /* Indicate that we are ready to start scheduling, which will happen after - this rountine returns. */ + this rountine returns. */ *((ULONG *) 0xBF000418) = 'T'; *((ULONG *) 0xBF000420) = 'X'; *((ULONG *) 0xBF000428) = ' '; @@ -296,7 +296,7 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; @@ -323,7 +323,7 @@ UINT status; thread_3_counter++; else thread_4_counter++; - + /* Get the semaphore with suspension. */ status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); @@ -359,7 +359,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -412,7 +412,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/ports_smp/mips32_interaptiv_smp/green/example_build/demo_threadx_ram_interAptiv.ld b/ports_smp/mips32_interaptiv_smp/green/example_build/demo_threadx_ram_interAptiv.ld index f4e8e8cf..0cd8e9b3 100644 --- a/ports_smp/mips32_interaptiv_smp/green/example_build/demo_threadx_ram_interAptiv.ld +++ b/ports_smp/mips32_interaptiv_smp/green/example_build/demo_threadx_ram_interAptiv.ld @@ -1,6 +1,6 @@ MEMORY { zero_memory : ORIGIN = 0xffff8000, LENGTH = 64K - + dram_rsvd1 : ORIGIN = 0x80000000, LENGTH = 0 vector_0x000 : ORIGIN = . LENGTH = 0x100 vector_0x100 : ORIGIN = . LENGTH = 0x080 @@ -20,7 +20,7 @@ DEFAULTS { heap_reserve = 2M stack_reserve = 512K - + } // // Program layout for running out of RAM. @@ -71,5 +71,5 @@ _end_bss = . ; __ghs_ramend = MEMENDADDR(dram_rsvd2); __ghs_romstart = MEMADDR(flash_rsvd1); __ghs_romend = MEMENDADDR(flash_rsvd2); - + } diff --git a/ports_smp/mips32_interaptiv_smp/green/example_build/init_CoreFPGA6_mem.mip b/ports_smp/mips32_interaptiv_smp/green/example_build/init_CoreFPGA6_mem.mip index d3932010..a3e9c997 100644 --- a/ports_smp/mips32_interaptiv_smp/green/example_build/init_CoreFPGA6_mem.mip +++ b/ports_smp/mips32_interaptiv_smp/green/example_build/init_CoreFPGA6_mem.mip @@ -64,6 +64,6 @@ LEAF(init_CoreFPGA6_mem) */ jr ra nop - + END(init_CoreFPGA6_mem) diff --git a/ports_smp/mips32_interaptiv_smp/green/example_build/init_mc_denali.mip b/ports_smp/mips32_interaptiv_smp/green/example_build/init_mc_denali.mip index 8e109a7c..2f36931d 100644 --- a/ports_smp/mips32_interaptiv_smp/green/example_build/init_mc_denali.mip +++ b/ports_smp/mips32_interaptiv_smp/green/example_build/init_mc_denali.mip @@ -3,7 +3,7 @@ * * Created on: Jan 12, 2011 * Author: MIPS TECHNOLOGIES, INC - + Initialization code for Denali memory controller needed for CoreFPGA5 */ /* diff --git a/ports_smp/mips32_interaptiv_smp/green/example_build/m32c0.h b/ports_smp/mips32_interaptiv_smp/green/example_build/m32c0.h index 87493e5d..2b247ff0 100644 --- a/ports_smp/mips32_interaptiv_smp/green/example_build/m32c0.h +++ b/ports_smp/mips32_interaptiv_smp/green/example_build/m32c0.h @@ -13,13 +13,13 @@ /* * Copyright (c) 1999-2007 MIPS Technologies, Inc. * Copyright (C) 2009 CodeSourcery, LLC. - * + * * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: - * + * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above @@ -30,7 +30,7 @@ * * Neither the name of MIPS Technologies Inc. nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -323,13 +323,13 @@ extern "C" { #define CFG_C_WTHRU_NOALLOC 0 #define CFG_C_WTHRU_ALLOC 1 #define CFG_C_COHERENTXCL 4 -#define CFG_C_COHERENTXCLW 5 +#define CFG_C_COHERENTXCLW 5 #define CFG_C_COHERENTUPD 6 #define CFG_C_UNCACHED_ACCEL 7 #endif -/* +/* * Primary Cache TagLo (CP0 Register 28, Select 0/2) */ #define TAG_PTAG_MASK 0xffffff00 /* Primary Tag */ @@ -412,8 +412,8 @@ extern "C" { #ifdef __ASSEMBLER__ -/* - * MIPS32 Coprocessor 0 register numbers +/* + * MIPS32 Coprocessor 0 register numbers */ #define C0_INDEX $0 #define C0_INX $0 @@ -518,8 +518,8 @@ typedef unsigned long reg_t; typedef signed long sreg_t; #endif -/* - * MIPS32 Coprocessor 0 register numbers +/* + * MIPS32 Coprocessor 0 register numbers */ #define C0_INDEX 0 #define C0_INX 0 @@ -561,7 +561,7 @@ typedef signed long sreg_t; #define C0_DESAVE 31 #define _mips_nop() \ - __asm__ __volatile ("%(ssnop%)" : :) + __asm__ __volatile ("%(ssnop%)" : :) #if ! __mips16 || __force_mips16_asm # define _mips_sync() __asm__ __volatile__ ("sync" : : : "memory") @@ -573,7 +573,7 @@ extern void _mips_sync(void); #define _mips_wait() \ __asm__ __volatile ("wait") -/* +/* * Define macros for accessing the MIPS32 coprocessor 0 registers. * Most apart from "set" return the original register value. */ diff --git a/ports_smp/mips32_interaptiv_smp/green/example_build/regdef.h b/ports_smp/mips32_interaptiv_smp/green/example_build/regdef.h index 80fa7a6e..01197f47 100644 --- a/ports_smp/mips32_interaptiv_smp/green/example_build/regdef.h +++ b/ports_smp/mips32_interaptiv_smp/green/example_build/regdef.h @@ -9,7 +9,7 @@ #define a1 $5 #define a2 $6 #define a3 $7 -#define t0 $8 +#define t0 $8 #define t1 $9 #define t2 $10 #define t3 $11 @@ -17,7 +17,7 @@ #define t5 $13 #define t6 $14 #define t7 $15 -#define s0 $16 +#define s0 $16 #define s1 $17 #define s2 $18 #define s3 $19 @@ -25,9 +25,9 @@ #define s5 $21 #define s6 $22 #define s7 $23 -#define t8 $24 +#define t8 $24 #define t9 $25 -#define jp $25 +#define jp $25 #define k0 $26 /* reserved for OS */ #define k1 $27 /* reserved for OS */ #define gp $28 /* global pointer */ diff --git a/ports_smp/mips32_interaptiv_smp/green/example_build/start.mip b/ports_smp/mips32_interaptiv_smp/green/example_build/start.mip index 85c5d753..d0c2c031 100644 --- a/ports_smp/mips32_interaptiv_smp/green/example_build/start.mip +++ b/ports_smp/mips32_interaptiv_smp/green/example_build/start.mip @@ -78,17 +78,17 @@ Technologies or an authorized third party. .section ".vector_0x000","ax" .globl tlb_refill_exception -tlb_refill_exception: +tlb_refill_exception: sdbbp .section ".vector_0x100","ax" .globl cache_error_exception -cache_error_exception: +cache_error_exception: sdbbp .section ".vector_0x180","ax" .globl general_exception -general_exception: +general_exception: /* EL Change: Branch to ThreadX error handling. */ @@ -144,10 +144,10 @@ iv1_interrupt: /* EL Change end. */ - + .section ".vector_0x280","ax" .globl xtlb_refill -xtlb_refill: +xtlb_refill: sdbbp .section ".vector_0x300","ax" @@ -205,7 +205,7 @@ init_common_resources: // initializes resources for virtual or physical "cpu". sw v1, 1088(v0) sw v1, 1096(v0) sw v1, 1104(v0) - .globl clear_done + .globl clear_done clear_done: la a2, init_cp0 // Init CP0 Status, Count, Compare, Watch*, and Cause. @@ -298,10 +298,10 @@ init_sys_resources: // We are core0 vpe0. nop /* EL Change. Ensure that the VPE release flag is cleared ahead of BSS clear. */ - + la $8, _tx_thread_smp_release_cores_flag # Build address of release flag sw $0, 0($8) # Clear the flag explicity to make other VPEs don't see it before everything is initialized - + /* EL end Change. */ @@ -346,14 +346,14 @@ init_done: mtc0 r23_cpu_num, $4,2 # Save the logical VPE in UserLocal so we don't have calculate it over and over! */ /* Save the stack pointer in the array indexed by cpu number. */ - + la $8, _tx_thread_system_stack_ptr # Build address of base of system stack array sll $9, r23_cpu_num, 2 # Build offset into array addu $8, $8, $9 # Build address of array entry sw $29, 0($8) # Store system stack for each VPE /* Setup status register in preparation for entering ThreadX. */ - + mfc0 $8, $12 # Pickup SR li $9, 0xFFFFFFF8 # Build mask to clear error, exception bits and $8, $8, $9 # Clear bits @@ -363,46 +363,46 @@ init_done: /* Check for Core 0, VPE 0 for processing ThreadX initialization. All other VPEs will wait until the first VPE has completed initialization before running. */ - + bne r23_cpu_num, $0, _additional_vpe # If non-zero, an additional vpe is present - nop # - + nop # + /* Core 0, VPE 0 processing. */ - + /* Save some information in globals. */ - + la $8, _tx_thread_smp_detected_cores # Build address of total number of cores detected addiu $9, r19_more_cores, 1 # Calculate the total cores sw $9, 0($8) # Save in global variable - + la $8, _tx_thread_smp_detected_vpes_per_core # Build address of VPEs per core detected addiu $9, r20_more_vpes, 1 # Caculate the total vpes per core sw $9, 0($8) # Save in global variable - + /* Simply branch to main to finish initializing ThreadX SMP. */ - + bal main # Branch to main - nop # - + nop # + /* If return, branch to all_done code. */ - + b all_done - nop - - + nop + + _additional_vpe: - + /* Additional VPE, transfer control to ThreadX. */ - + b _tx_thread_smp_initialize_wait # Enter ThreadX for additional VPEs nop .globl all_done all_done: b all_done - + /* Comment out the previous "init_done" code since it is replaced with ThreadX-specfic code. */ #if 0 @@ -441,7 +441,7 @@ all_done: // All cpu spin on atomic potato++ // la a1, potato - + try_again: ll a0, 0(a1) addiu a0, a0, 1 @@ -452,7 +452,7 @@ try_again: b try_again // Success, do again. nop - + b all_done nop #endif diff --git a/ports_smp/mips32_interaptiv_smp/green/inc/tx_el.h b/ports_smp/mips32_interaptiv_smp/green/inc/tx_el.h index 7197bfec..d39c2b4c 100644 --- a/ports_smp/mips32_interaptiv_smp/green/inc/tx_el.h +++ b/ports_smp/mips32_interaptiv_smp/green/inc/tx_el.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -36,12 +37,6 @@ /* EventAnalyzer. It is assumed that tx_api.h and tx_port.h have */ /* already been included. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial Version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TX_EL_H diff --git a/ports_smp/mips32_interaptiv_smp/green/inc/tx_port.h b/ports_smp/mips32_interaptiv_smp/green/inc/tx_port.h index 385201ff..a4b88d1b 100644 --- a/ports_smp/mips32_interaptiv_smp/green/inc/tx_port.h +++ b/ports_smp/mips32_interaptiv_smp/green/inc/tx_port.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -42,12 +43,6 @@ /* own special types that can be mapped to actual data types by this */ /* file to guarantee consistency in the interface and functionality. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Scott Larson Initial release version 6.2.1 */ -/* */ /**************************************************************************/ #ifndef TX_PORT_H @@ -343,7 +338,7 @@ ULONG _tx_misra_time_stamp_get(VOID); extern void __tx_cpp_exception_cleanup(TX_THREAD *thread_ptr); \ __tx_cpp_exception_cleanup(thread_ptr); \ } -#else +#else #define TX_THREAD_DELETE_EXTENSION(thread_ptr) \ { \ #pragma weak __cpp_exception_cleanup \ @@ -514,7 +509,7 @@ THREAD_SMP_DECLARE ULONG _tx_thread_smp_initial_fpu_control_register; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 2024 Microsoft Corporation. * ThreadX SMP MIPS32_interAptiv/Green Hills Version 6.4.2 *"; + "(c) 2024 Microsoft Corp. (c) 2026-present Eclipse ThreadX contributors. * ThreadX SMP MIPS32_interAptiv/Green Hills Version 6.5.0.202601 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/mips32_interaptiv_smp/green/readme_threadx.txt b/ports_smp/mips32_interaptiv_smp/green/readme_threadx.txt index 20365485..08d88409 100644 --- a/ports_smp/mips32_interaptiv_smp/green/readme_threadx.txt +++ b/ports_smp/mips32_interaptiv_smp/green/readme_threadx.txt @@ -4,17 +4,17 @@ 1. Installation -ThreadX for the MIPS32 interAptiv is delivered on a single CD-ROM compatible disk. +ThreadX for the MIPS32 interAptiv is delivered on a single CD-ROM compatible disk. The entire distribution can be found in the sub-directory: \threadx -To install ThreadX to your hard-disk, either run the supplied installer -program Setup.exe or copy the distribution from the CD manually. +To install ThreadX to your hard-disk, either run the supplied installer +program Setup.exe or copy the distribution from the CD manually. -To copy the ThreadX distribution manually, make a threadx directory on your -hard-disk (we recommend C:\threadx\mips32_interaptiv\green) and copy all the contents -of the threadx sub-directory on the distribution disk. The following +To copy the ThreadX distribution manually, make a threadx directory on your +hard-disk (we recommend C:\threadx\mips32_interaptiv\green) and copy all the contents +of the threadx sub-directory on the distribution disk. The following is an example MS-DOS copy command from the distribution directory (assuming source is d: and c: is your hard-drive): @@ -25,7 +25,7 @@ d:\threadx> xcopy /S *.* c:\threadx\mips32_interaptiv\green 2. Open the ThreadX Project Workspace In order to build the ThreadX library and the ThreadX demonstration first -load the ThreadX project workspace threadx_project_workspace.gpj, which is +load the ThreadX project workspace threadx_project_workspace.gpj, which is located inside your ThreadX directory: C:\threadx\mips32_interaptiv\green\threadx_project_workspace.gpj @@ -33,40 +33,40 @@ C:\threadx\mips32_interaptiv\green\threadx_project_workspace.gpj 3. Building the ThreadX run-time Library -Building the ThreadX library is easy; simply select the MULTI project file -tx.gpj and then select the build button. You should now observe the -compilation and assembly of the ThreadX library. This project build produces +Building the ThreadX library is easy; simply select the MULTI project file +tx.gpj and then select the build button. You should now observe the +compilation and assembly of the ThreadX library. This project build produces the ThreadX library file tx.a. 4. Demonstration System The ThreadX demonstration is designed to execute under the MULTI environment -on the MIPS interAptiv MALTA board. By default, the demonstration is setup for a +on the MIPS interAptiv MALTA board. By default, the demonstration is setup for a 3 core (6 VPE) interAptiv configuration. The instructions that follow describe how to get the ThreadX evaluation running under the MIPS interAptiv MALTA board. -Building the demonstration is easy; simply select the MULTI project file -demo_threadx.gpj. At this point, select the "Project Build" button and observe -the compilation, assembly, and linkage of the ThreadX demonstration application. +Building the demonstration is easy; simply select the MULTI project file +demo_threadx.gpj. At this point, select the "Project Build" button and observe +the compilation, assembly, and linkage of the ThreadX demonstration application. After the demonstration is built, follow these steps to download and execute the ThreadX SMP interAptiv demonstration: -A. Select the "demo_threadx_ram_interAptiv_3c2v4t.ghsmc" multi-core configuration - file and then the debug button (or [F5] key). You should observe a debugger +A. Select the "demo_threadx_ram_interAptiv_3c2v4t.ghsmc" multi-core configuration + file and then the debug button (or [F5] key). You should observe a debugger window with 6 unconnected demo_threadx.elf executables. - -B. Select the first of the 6 unconnected demo_threadx.elf images and click the + +B. Select the first of the 6 unconnected demo_threadx.elf images and click the "prepare target" button (or right-click -> prepare target). You should now get a "Connection Chooser" dialog box. - + C. Connect to the "GHS_Probe_interAptive_3c2v4t" target. You should observe the - "prepare target" dialog. - -D. In the "prepare target" dialog, select "download". You should now see a + "prepare target" dialog. + +D. In the "prepare target" dialog, select "download". You should now see a connection to 12 threads, as follows: - + Id 0 -> c0v0t0 boot_mips.elf @ _start ) (code and data are loaded on Id 0) Id 1 -> c0v1t1 boot_mips.elf @ 0xdeadbeef (scripted indication of uninitialized vpe1) Id 2 -> c0v1t2 (not used) @@ -80,39 +80,39 @@ D. In the "prepare target" dialog, select "download". You should now see a Id 10 -> c2v1t2 (not used) Id 11 -> c2v1t3 (not used) -E. To start execution, select and run Id 0, Id 4, and Id 8. All the cores are now +E. To start execution, select and run Id 0, Id 4, and Id 8. All the cores are now running and you should observe messages being displayed on the MALTA board. 5. EventAnalyzer Demonstration -To build a demonstration system that also logs events for the MULTI EventAnalyzer, -perform the same steps as the regular demo, except build the ThreadX library with -txe.gpj file and use the demo_threadx_el.gpj build file to build the demonstration. -The resulting image will log all system events, which can then be displayed by the +To build a demonstration system that also logs events for the MULTI EventAnalyzer, +perform the same steps as the regular demo, except build the ThreadX library with +txe.gpj file and use the demo_threadx_el.gpj build file to build the demonstration. +The resulting image will log all system events, which can then be displayed by the MULTI EventAnalyzer. 6. System Initialization -The system entry point using the Green Hills tools is at the label _start. -This is defined within the start.mip file supplied by MIPS. In addition, -this is where all static and global preset C variable initialization +The system entry point using the Green Hills tools is at the label _start. +This is defined within the start.mip file supplied by MIPS. In addition, +this is where all static and global preset C variable initialization processing is called from. -Once the startup function finishes, main is called, which is also where ThreadX -initialization takes place. The main initialization function for ThreadX is -_tx_initialize_low_level and is located in the file tx_initialize_low_level.mip. -This function is responsible for setting up various system data structures, +Once the startup function finishes, main is called, which is also where ThreadX +initialization takes place. The main initialization function for ThreadX is +_tx_initialize_low_level and is located in the file tx_initialize_low_level.mip. +This function is responsible for setting up various system data structures, interrupt vectors, and the periodic timer interrupt source of ThreadX. -In addition, _tx_initialize_low_level determines where the first available +In addition, _tx_initialize_low_level determines where the first available RAM memory address is located. This address is supplied to tx_application_define. -By default, the first available RAM memory address is assumed to start at the -beginning of the ThreadX section .free_mem. If changes are made to the -demo_threadx.ld file, the .free_mem section should remain the last allocated -section in the main RAM area. The starting address of this section is passed +By default, the first available RAM memory address is assumed to start at the +beginning of the ThreadX section .free_mem. If changes are made to the +demo_threadx.ld file, the .free_mem section should remain the last allocated +section in the main RAM area. The starting address of this section is passed to tx_application_define. @@ -123,17 +123,17 @@ Please reference the ThreadX_SMP_User_Guide.pdf for details on build options. 8. Register Usage and Stack Frames -The Green Hills MIPS compiler assumes that registers t0-t9 ($8-$15, $24, $25) -are scratch registers for each function. All other registers used by a -C function must be preserved by the function. ThreadX takes advantage -of this in situations where a context switch happens as a result of making a -ThreadX service call (which is itself a C function). In such cases, the +The Green Hills MIPS compiler assumes that registers t0-t9 ($8-$15, $24, $25) +are scratch registers for each function. All other registers used by a +C function must be preserved by the function. ThreadX takes advantage +of this in situations where a context switch happens as a result of making a +ThreadX service call (which is itself a C function). In such cases, the saved context of a thread is only the non-scratch registers. The following defines the saved context stack frames for context switches that occur as a result of interrupt handling or from thread-level API calls. All suspended threads have one of these two types of stack frames. The top -of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the associated thread control block TX_THREAD. @@ -165,7 +165,7 @@ associated thread control block TX_THREAD. 0x058 a3 ($7) f27 | 0x05C a2 ($6) | 0x060 a1 ($5) f26 | - 0x064 a0 ($4) + 0x064 a0 ($4) 0x068 v1 ($3) f25 TX_ENABLE_64BIT_FPU_SUPPORT 0x06C v0 ($2) 0x070 at ($1) f24 | @@ -177,14 +177,14 @@ associated thread control block TX_THREAD. 0x090 f29 | f20 | 0x098 f28 | fcr31 <------------+ 0x09C | not used - 0x0A0 f27 | - 0x0A4 | - 0x0A8 f26 | - 0x0AC | - 0x0B0 f25 | - 0x0B4 | - 0x0B8 f24 | - 0x0BC | + 0x0A0 f27 | + 0x0A4 | + 0x0A8 f26 | + 0x0AC | + 0x0B0 f25 | + 0x0B4 | + 0x0B8 f24 | + 0x0BC | 0x0C0 f23 | 0x0C8 f22 | 0x0D0 f21 | @@ -215,50 +215,50 @@ associated thread control block TX_THREAD. 9. Improving Performance -The distribution version of ThreadX is built without any compiler -optimizations. This makes it easy to debug because you can trace or set -breakpoints inside of ThreadX itself. Of course, this costs some +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. To make ThreadX run faster, you can change the tx.gpj project -to disable debug information and enable the desired optimizations. +to disable debug information and enable the desired optimizations. -In addition, you can eliminate the ThreadX basic API error checking by -compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING -defined before tx_api.h is included. +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. 10. Interrupt Handling ThreadX provides complete and high-performance interrupt handling for MIPS32 interAptiv targets. The general exception handler is at address: 0x80000180 (0xA0000180 non- -cached). The ThreadX general exception handler is defined in the file -tx_initialize_low_level.mip at the label _tx_exception_handler. A small piece of -code to jump to this exception handler is copied to the general exception handler +cached). The ThreadX general exception handler is defined in the file +tx_initialize_low_level.mip at the label _tx_exception_handler. A small piece of +code to jump to this exception handler is copied to the general exception handler address during initialization. 10.1 Application ISRs -Multiple exceptions may be processed with a single execution of the exception +Multiple exceptions may be processed with a single execution of the exception handler. This is because the Cause register could indicate more than a single -exception. Processing for each exception is also located in the general -exception handler that starts at the label: _tx_exception_handler. Application +exception. Processing for each exception is also located in the general +exception handler that starts at the label: _tx_exception_handler. Application ISRs can be added into this handler. 11. Theory of Operation - SMP -ThreadX for the MIPS interAptiv brings Symmetric Multi-Processing (SMP) technology to -the MIPS interAptiv. ThreadX application threads (of varying priority) that are "READY" -to run are dynamically allocated to VPEs during scheduling, thus taking full -advantage of all available MIPS interAptiv VPEs. This results in true SMP processing, -including automatic load balancing of application thread execution across all -available MIPS interAptiv VPEs. +ThreadX for the MIPS interAptiv brings Symmetric Multi-Processing (SMP) technology to +the MIPS interAptiv. ThreadX application threads (of varying priority) that are "READY" +to run are dynamically allocated to VPEs during scheduling, thus taking full +advantage of all available MIPS interAptiv VPEs. This results in true SMP processing, +including automatic load balancing of application thread execution across all +available MIPS interAptiv VPEs. Initialization is done exclusively in VPE 0, which is the default running VPE -after reset. The additional VPEs on the interAptiv are initialized by VPE 0 and simply +after reset. The additional VPEs on the interAptiv are initialized by VPE 0 and simply wait until VPE 0 completes the initialization before they start running. -During thread execution, multithreading in the MIPS interAptiv is fully enabled. This -means that application threads may be preempted by higher priority threads, may +During thread execution, multithreading in the MIPS interAptiv is fully enabled. This +means that application threads may be preempted by higher priority threads, may suspend themselves, or may exit the system upon completion of their work. Protection between VPEs is accomplished via a conditional load-store structure (see the variable _tx_thread_smp_protection and the typedef TX_THREAD_SMP_PROTECT found in tx_thread.h). @@ -267,11 +267,11 @@ All VPEs are eligible to handle interrupts under the direction of the applicatio ThreadX timer interrupt is by default assigned to VPE 0 for processing. Please see the code in tx_timer_interrupt.mip for the implementation. -ThreadX for the MIPS interAptiv also optionally supports the MIPS interAptiv FPU. +ThreadX for the MIPS interAptiv also optionally supports the MIPS interAptiv FPU. -The number of VPEs is defined by the compile time constant TX_THREAD_SMP_MAX_CORES. -By default, this is set to 2 in tx_port.h. It may be changed to support any number -of cores either in tx_port.h or on the command line via a -D symbol definition. +The number of VPEs is defined by the compile time constant TX_THREAD_SMP_MAX_CORES. +By default, this is set to 2 in tx_port.h. It may be changed to support any number +of cores either in tx_port.h or on the command line via a -D symbol definition. 12. Current Limitations @@ -282,7 +282,7 @@ of cores either in tx_port.h or on the command line via a -D symbol definition. 13. Debug Information -ThreadX SMP for MIPS32 interAptiv has a built-in debug facility to capture SMP scheduling +ThreadX SMP for MIPS32 interAptiv has a built-in debug facility to capture SMP scheduling information. This is enabled by building the system with TX_THREAD_SMP_DEBUG_ENABLE defined. This results in the creation of circular log containing debug information. The log is defined in the variable _tx_thread_smp_debug_info_array. @@ -295,7 +295,7 @@ file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -03-08-2023 Initial ThreadX version 6.2.1 of MIPS32_interAptiv VPE/Green Hills port. +03-08-2023 Initial ThreadX version 6.2.1 of MIPS32_interAptiv VPE/Green Hills port. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_el.c b/ports_smp/mips32_interaptiv_smp/green/src/tx_el.c index 3078db9a..04dbfd9e 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_el.c +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_el.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -83,12 +84,6 @@ UINT _tx_thread_interrupt_control(UINT new_posture); /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-08-2023 Cindy Deng Initial Version 6.2.1 */ -/* */ /**************************************************************************/ VOID _tx_el_initialize(VOID) { diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_ghs.c b/ports_smp/mips32_interaptiv_smp/green/src/tx_ghs.c index f89dfe37..48384595 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_ghs.c +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_ghs.c @@ -57,7 +57,7 @@ extern TX_THREAD *_tx_thread_created_ptr; If you customize the System Library, you should remove ind_thrd.c from the libsys.gpj subproject. - + */ /* Provide global __eh_globals value to support C++ exception handling diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_initialize_low_level.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_initialize_low_level.mip index 5798aa68..a5d2f590 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_initialize_low_level.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_initialize_low_level.mip @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -148,7 +148,7 @@ _tx_exception_trampoline_end: .globl _tx_exception_handler _tx_exception_handler: mfc0 $26, $13 # Pickup the cause register - ehb # + ehb # andi $26, $26, 0x3C # Isolate the exception code bne $26, $0, _tx_error_exceptions # If non-zero, an error exception is present nop # Delay slot @@ -267,7 +267,7 @@ _tx_not_interrupt_4: li $4,0 # Build interrupt type la $9, _tx_el_interrupt # Build interrupt start logging address jal $9 # Call interrupt start event logging - nop # + nop # #endif #ifdef TX_ENABLE_EVENT_TRACE diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_context_restore.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_context_restore.mip index 1d949f28..d02d0e11 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_context_restore.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_context_restore.mip @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_context_save.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_context_save.mip index dea34eb0..297e5253 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_context_save.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_context_save.mip @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_interrupt_control.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_interrupt_control.mip index da217b66..96895c39 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_interrupt_control.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_interrupt_control.mip @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_schedule.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_schedule.mip index 2f7d3930..58571a67 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_schedule.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_schedule.mip @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_core_get.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_core_get.mip index 50585988..5d687408 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_core_get.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_core_get.mip @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_core_preempt.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_core_preempt.mip index 6289bb47..679a2aff 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_core_preempt.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_core_preempt.mip @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_current_state_get.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_current_state_get.mip index 062d2b21..77f007ce 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_current_state_get.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_current_state_get.mip @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_current_thread_get.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_current_thread_get.mip index 565213f1..b084c9fb 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_current_thread_get.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_current_thread_get.mip @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_initialize_wait.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_initialize_wait.mip index 56fbf835..a5758265 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_initialize_wait.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_initialize_wait.mip @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_low_level_initialize.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_low_level_initialize.mip index 17a78b00..b3f26229 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_low_level_initialize.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_low_level_initialize.mip @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_protect.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_protect.mip index c49dfa1b..4563cac5 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_protect.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_protect.mip @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_time_get.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_time_get.mip index 016118ef..72d5e1fa 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_time_get.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_time_get.mip @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_unprotect.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_unprotect.mip index 3c7d5224..8aac48e8 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_unprotect.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_smp_unprotect.mip @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_stack_build.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_stack_build.mip index 51df30b3..03f907df 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_stack_build.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_stack_build.mip @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_system_return.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_system_return.mip index df9f8db5..becb061a 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_system_return.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_thread_system_return.mip @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/ports_smp/mips32_interaptiv_smp/green/src/tx_timer_interrupt.mip b/ports_smp/mips32_interaptiv_smp/green/src/tx_timer_interrupt.mip index b6573db1..50b16eb4 100644 --- a/ports_smp/mips32_interaptiv_smp/green/src/tx_timer_interrupt.mip +++ b/ports_smp/mips32_interaptiv_smp/green/src/tx_timer_interrupt.mip @@ -1,10 +1,10 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ diff --git a/samples/demo_threadx.c b/samples/demo_threadx.c index 597f373c..13ffadba 100644 --- a/samples/demo_threadx.c +++ b/samples/demo_threadx.c @@ -1,5 +1,5 @@ /* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight - threads of different priorities, using a message queue, semaphore, mutex, event flags group, + threads of different priorities, using a message queue, semaphore, mutex, event flags group, byte pool, and block pool. */ #include "tx_api.h" @@ -81,42 +81,42 @@ CHAR *pointer = TX_NULL; tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 1. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 1 and 2. These threads pass information through a ThreadX + /* Create threads 1 and 2. These threads pass information through a ThreadX message queue. It is also interesting to note that these threads have a time slice. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 2. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 16, 16, 4, TX_AUTO_START); /* Allocate the stack for thread 3. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. An interesting thing here is that both threads share the same instruction area. */ - tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 4. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 5. */ @@ -124,23 +124,23 @@ CHAR *pointer = TX_NULL; /* Create thread 5. This thread simply pends on an event flag which will be set by thread_0. */ - tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 6. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ - tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the stack for thread 7. */ tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); - tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); /* Allocate the message queue. */ @@ -243,11 +243,11 @@ UINT status; /* Retrieve a message from the queue. */ status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); - /* Check completion status and make sure the message is what we + /* Check completion status and make sure the message is what we expected. */ if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) break; - + /* Otherwise, all is okay. Increment the received message count. */ thread_2_messages_received++; } @@ -306,7 +306,7 @@ ULONG actual_flags; thread_5_counter++; /* Wait for event flag 0. */ - status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, &actual_flags, TX_WAIT_FOREVER); /* Check status. */ @@ -359,7 +359,7 @@ UINT status; if (status != TX_SUCCESS) break; - /* Release the mutex again. This will actually + /* Release the mutex again. This will actually release ownership since it was obtained twice. */ status = tx_mutex_put(&mutex_0); diff --git a/scripts/cmake_bootstrap.sh b/scripts/cmake_bootstrap.sh index c5d59ac0..b7b314fa 100755 --- a/scripts/cmake_bootstrap.sh +++ b/scripts/cmake_bootstrap.sh @@ -37,7 +37,7 @@ function build_libs() { function test() { pushd build/$1 [ -z "${CTEST_PARALLEL_LEVEL}" ] && parallel="-j$2" - if [ -z "${CTEST_REPEAT_FAIL}" ]; + if [ -z "${CTEST_REPEAT_FAIL}" ]; then repeat_fail=2 else diff --git a/scripts/copy_module_armv7_m.sh b/scripts/copy_module_armv7_m.sh index 8dbd834c..a0ddcd27 100755 --- a/scripts/copy_module_armv7_m.sh +++ b/scripts/copy_module_armv7_m.sh @@ -44,7 +44,7 @@ do echo "$source_inc_folder -> $target" cp -rf $source_inc_folder/* $target find $target -type f -exec sed -i "s/$source_string/$target_string_pre${mcu: -1}/g" {} \; - + # Copy common files source=$source_folder/$source_common_folder; target=$ports_module_folder/$mcu/$ide/$target_common_folder diff --git a/test/ports/README.old.md b/test/ports/README.old.md index 746d1d74..5af6bef8 100644 --- a/test/ports/README.old.md +++ b/test/ports/README.old.md @@ -12,19 +12,19 @@ These are batch scripts and auxiliary files (expected test results, etc). * Test_FVP: test the example using the ARM FVP platform. ## azrtos_cicd.old.bat -This is the main entry point for operations to be performed on several examples at the same time. -This script can be called from any location, it will automatically perform the requested operations on the examples of the repository where it is located. -This file outputs a summary to the screen and a detailed log file with all the output called azrtos_do.all.log -Call this scripts without parameters to get usage information. -The script parameters are case insensitive. +This is the main entry point for operations to be performed on several examples at the same time. +This script can be called from any location, it will automatically perform the requested operations on the examples of the repository where it is located. +This file outputs a summary to the screen and a detailed log file with all the output called azrtos_do.all.log +Call this scripts without parameters to get usage information. +The script parameters are case insensitive. ## Examples: -`azrtos_cicd.old.bat build tx ghs iar` +`azrtos_cicd.old.bat build tx ghs iar` This will build all GHS and IAR example projects. -`azrtos_cicd.old.bat clean tx all` +`azrtos_cicd.old.bat clean tx all` This cleans all ThreadX examples -`azrtos_cicd.old.bat build txm iar` +`azrtos_cicd.old.bat build txm iar` This builds all ThreadX Modules IAR examples. diff --git a/test/ports/azrtos_cicd.ps1 b/test/ports/azrtos_cicd.ps1 index e932bed1..a43032cb 100644 --- a/test/ports/azrtos_cicd.ps1 +++ b/test/ports/azrtos_cicd.ps1 @@ -219,7 +219,7 @@ ForEach ($f in $CsvFile) { If (-not ($i.Name -match $m)) { Write-Verbose ("Name mismatch: " + $m) $match = $false; - } + } } } @@ -229,11 +229,11 @@ ForEach ($f in $CsvFile) { Write-Verbose ("Matching " + $m) If (-not ($i.Keywords -match $m)) { Write-Verbose ("Keywords mismatch: " + $m) - $match = $false - } + $match = $false + } } } - + If ($MatchPath.Count -ne 0) { Write-Verbose ("Matching path...") ForEach ($m in $MatchPath) { @@ -241,7 +241,7 @@ ForEach ($f in $CsvFile) { If (-not ($i.Path -match $m)) { Write-Verbose ("Path mismatch: " + $m) $match = $false - } + } } } @@ -281,7 +281,7 @@ ForEach ($f in $CsvFile) { } If ($Clean -and ($i.CleanScript -ne "")) { - Write-Progress -Activity $f -Status ($Stats.CurrentCsv.ToString() + "/" + $t.Count.ToString()) -CurrentOperation $i.Name -PercentComplete (1.0 * $Stats.CurrentCsv / $t.Count * 100) + Write-Progress -Activity $f -Status ($Stats.CurrentCsv.ToString() + "/" + $t.Count.ToString()) -CurrentOperation $i.Name -PercentComplete (1.0 * $Stats.CurrentCsv / $t.Count * 100) $result = Invoke-CustomScript "Clean" $i.Name (Join-Path $ScriptDir $i.CleanEnvScript) (Join-Path $ScriptDir $i.CleanScript) if ($result -ne 0) { $Stats.CleanScriptERROR++ @@ -291,7 +291,7 @@ ForEach ($f in $CsvFile) { } If ($Build -and ($i.BuildScript -ne "")) { - Write-Progress -Activity $f -Status ($Stats.CurrentCsv.ToString() + "/" + $t.Count.ToString()) -CurrentOperation $i.Name -PercentComplete (1.0 * $Stats.CurrentCsv / $t.Count * 100) + Write-Progress -Activity $f -Status ($Stats.CurrentCsv.ToString() + "/" + $t.Count.ToString()) -CurrentOperation $i.Name -PercentComplete (1.0 * $Stats.CurrentCsv / $t.Count * 100) $result = Invoke-CustomScript "Build" $i.Name (Join-Path $ScriptDir $i.BuildEnvScript) (Join-Path $ScriptDir $i.BuildScript) if ($result -ne 0) { $Stats.BuildScriptERROR++ @@ -301,7 +301,7 @@ ForEach ($f in $CsvFile) { } If ($Test -and ($i.TestScript -ne "")) { - Write-Progress -Activity $f -Status ($Stats.CurrentCsv.ToString() + "/" + $t.Count.ToString()) -CurrentOperation $i.Name -PercentComplete (1.0 * $Stats.CurrentCsv / $t.Count * 100) + Write-Progress -Activity $f -Status ($Stats.CurrentCsv.ToString() + "/" + $t.Count.ToString()) -CurrentOperation $i.Name -PercentComplete (1.0 * $Stats.CurrentCsv / $t.Count * 100) $result = Invoke-CustomScript "Test" $i.Name (Join-Path $ScriptDir $i.TestEnvScript) (Join-Path $ScriptDir $i.TestScript) if ($result -ne 0) { $Stats.TestScriptERROR++ diff --git a/test/ports/azrtos_test_tx_ghs_cortex_m3.valid.log b/test/ports/azrtos_test_tx_ghs_cortex_m3.valid.log index f0f7a19d..fc46fd6b 100644 --- a/test/ports/azrtos_test_tx_ghs_cortex_m3.valid.log +++ b/test/ports/azrtos_test_tx_ghs_cortex_m3.valid.log @@ -27,4 +27,4 @@ thread_4_counter = 0x0000000d thread_5_counter = 0x00000005 thread_6_counter = 0x0000000d thread_7_counter = 0x0000000d -MULTI> +MULTI> diff --git a/test/smp/cmake/threadx_smp/CMakeLists.txt b/test/smp/cmake/threadx_smp/CMakeLists.txt index d142d790..f6596253 100644 --- a/test/smp/cmake/threadx_smp/CMakeLists.txt +++ b/test/smp/cmake/threadx_smp/CMakeLists.txt @@ -2,7 +2,7 @@ cmake_minimum_required(VERSION 3.13 FATAL_ERROR) # Set up the project project(threadx_smp - VERSION 6.0.0 + VERSION 6.0.0 LANGUAGES C ASM ) @@ -37,10 +37,10 @@ if (NOT TX_USER_FILE) set(TX_USER_FILE ${PROJECT_DIR}/common_smp/inc/tx_user_sample.h) else() message(STATUS "Using custom tx_user.h file from ${TX_USER_FILE}") -endif() +endif() configure_file(${TX_USER_FILE} ${CUSTOM_INC_DIR}/tx_user.h COPYONLY) -target_include_directories(${PROJECT_NAME} - PUBLIC +target_include_directories(${PROJECT_NAME} + PUBLIC ${CUSTOM_INC_DIR} ) target_compile_definitions(${PROJECT_NAME} PUBLIC "TX_INCLUDE_USER_DEFINE_FILE" ) diff --git a/test/smp/cmake/threadx_smp/common_smp/CMakeLists.txt b/test/smp/cmake/threadx_smp/common_smp/CMakeLists.txt index f7e35fde..646b200b 100644 --- a/test/smp/cmake/threadx_smp/common_smp/CMakeLists.txt +++ b/test/smp/cmake/threadx_smp/common_smp/CMakeLists.txt @@ -213,8 +213,8 @@ target_sources(${PROJECT_NAME} ) # Add the Common/inc directory to the project include list -target_include_directories(${PROJECT_NAME} - PUBLIC +target_include_directories(${PROJECT_NAME} + PUBLIC ${CURRENT_DIR}/inc ) diff --git a/test/smp/regression/testcontrol.c b/test/smp/regression/testcontrol.c index e63930d2..6b45750d 100644 --- a/test/smp/regression/testcontrol.c +++ b/test/smp/regression/testcontrol.c @@ -53,7 +53,7 @@ TEST_FLAG threadx_delete_timer_thread; #endif TX_TIMER_INTERNAL **_timer_list_start_backup; TEST_FLAG test_stack_analyze_flag; -TEST_FLAG test_initialize_flag; +TEST_FLAG test_initialize_flag; TX_BLOCK_POOL fake_block_pool; TX_BYTE_POOL fake_byte_pool; TX_EVENT_FLAGS_GROUP fake_event_flags; @@ -113,7 +113,7 @@ VOID (*test_isr_dispatch)(void); UCHAR test_control_memory[0x60000]; UCHAR tests_memory[0x60000]; -UINT mutex_priority_change_extension_selection; +UINT mutex_priority_change_extension_selection; UINT priority_change_extension_selection; TEST_FLAG test_forced_mutex_timeout; TEST_FLAG threadx_byte_allocate_loop_test; @@ -263,7 +263,7 @@ void test_application_define(void *first_unused_memory); /* Define the array of test entry points. */ -TEST_ENTRY test_control_tests[] = +TEST_ENTRY test_control_tests[] = { #if CTEST test_application_define, @@ -297,7 +297,7 @@ TEST_ENTRY test_control_tests[] = threadx_byte_memory_thread_terminate_application_define, threadx_byte_memory_prioritize_application_define, threadx_byte_memory_thread_contention_application_define, - threadx_byte_memory_information_application_define, + threadx_byte_memory_information_application_define, threadx_event_flag_basic_application_define, threadx_event_flag_suspension_application_define, @@ -380,14 +380,14 @@ TEST_ENTRY test_control_tests[] = threadx_thread_stack_checking_application_define, threadx_time_get_set_application_define, - + threadx_timer_simple_application_define, threadx_timer_activate_deactivate_application_define, threadx_timer_deactivate_accuracy_application_define, threadx_timer_large_timer_accuracy_application_define, threadx_timer_multiple_application_define, threadx_timer_multiple_accuracy_application_define, - threadx_timer_information_application_define, + threadx_timer_information_application_define, threadx_trace_basic_application_define, #endif @@ -452,7 +452,7 @@ void test_interrupt_dispatch(void) if (test_isr_dispatch) { - (test_isr_dispatch)(); + (test_isr_dispatch)(); } } @@ -490,7 +490,7 @@ void main() /* Test the pre-initialize path through _tx_initialize_kernel_enter. */ _tx_thread_system_state[0] = TX_INITIALIZE_ALMOST_DONE; test_initialize_flag = 1; - + /* Call the internal kernel enter function to exercise two paths. */ _tx_initialize_kernel_enter(); _tx_thread_system_state[0] = 0; @@ -532,27 +532,27 @@ TX_THREAD *thread_ptr; test_control_system_errors = 0; /* Create two equal priority threads. */ - status = tx_thread_create(&test_thread4, "test thread 4", test_thread_entry1, 4, + status = tx_thread_create(&test_thread4, "test thread 4", test_thread_entry1, 4, test_thread4_stack, sizeof(test_thread4_stack), 15, 15, TX_NO_TIME_SLICE, TX_DONT_START); - status += tx_thread_create(&test_thread5, "test thread 5", test_thread_entry1, 5, + status += tx_thread_create(&test_thread5, "test thread 5", test_thread_entry1, 5, test_thread5_stack, sizeof(test_thread5_stack), 15, 15, TX_NO_TIME_SLICE, TX_DONT_START); - status += tx_thread_create(&test_thread6, "test thread 6", test_thread_entry1, 6, + status += tx_thread_create(&test_thread6, "test thread 6", test_thread_entry1, 6, test_thread6_stack, sizeof(test_thread6_stack), 16, 16, TX_NO_TIME_SLICE, TX_DONT_START); - status += tx_thread_create(&test_thread7, "test thread 7", test_thread_entry1, 7, + status += tx_thread_create(&test_thread7, "test thread 7", test_thread_entry1, 7, test_thread7_stack, sizeof(test_thread7_stack), 17, 17, TX_NO_TIME_SLICE, TX_DONT_START); - status += tx_thread_create(&test_thread8, "test thread 8", test_thread_entry1, 8, + status += tx_thread_create(&test_thread8, "test thread 8", test_thread_entry1, 8, test_thread8_stack, sizeof(test_thread8_stack), 18, 18, TX_NO_TIME_SLICE, TX_DONT_START); - status += tx_thread_create(&test_thread9, "test thread 9", test_thread_entry1, 9, + status += tx_thread_create(&test_thread9, "test thread 9", test_thread_entry1, 9, test_thread9_stack, sizeof(test_thread9_stack), 19, 19, TX_NO_TIME_SLICE, TX_DONT_START); - status += tx_thread_create(&test_thread10, "test thread 10", test_thread_entry1, 10, + status += tx_thread_create(&test_thread10, "test thread 10", test_thread_entry1, 10, test_thread10_stack, sizeof(test_thread10_stack), 20, 20, TX_NO_TIME_SLICE, TX_DONT_START); - status += tx_thread_create(&test_thread11, "test thread 11", test_thread_entry1, 11, + status += tx_thread_create(&test_thread11, "test thread 11", test_thread_entry1, 11, test_thread11_stack, sizeof(test_thread11_stack), 20, 20, TX_NO_TIME_SLICE, TX_DONT_START); - status += tx_thread_create(&test_thread12, "test thread 12", test_thread_entry1, 12, + status += tx_thread_create(&test_thread12, "test thread 12", test_thread_entry1, 12, test_thread12_stack, sizeof(test_thread12_stack), 20, 20, TX_NO_TIME_SLICE, TX_DONT_START); - status += tx_thread_create(&test_thread13, "test thread 13", test_thread_entry1, 13, + status += tx_thread_create(&test_thread13, "test thread 13", test_thread_entry1, 13, test_thread13_stack, sizeof(test_thread13_stack), 20, 20, TX_NO_TIME_SLICE, TX_DONT_START); - status += tx_thread_create(&test_thread14, "test thread 14", test_thread_entry1, 14, + status += tx_thread_create(&test_thread14, "test thread 14", test_thread_entry1, 14, test_thread14_stack, sizeof(test_thread14_stack), 20, 20, TX_NO_TIME_SLICE, TX_DONT_START); status += tx_thread_smp_core_exclude(&test_thread4, 0xD); status += tx_thread_smp_core_exclude(&test_thread5, 0xD); @@ -604,29 +604,29 @@ TX_THREAD *thread_ptr; status += tx_thread_suspend(&test_thread4); /* Setup a pointer to the first unused memory. */ - pointer = (UCHAR *) &test_control_memory[0]; //first_unused_memory; + pointer = (UCHAR *) &test_control_memory[0]; //first_unused_memory; /* Create the test control thread. */ - tx_thread_create(&test_control_thread, "test control thread", test_control_thread_entry, 0, - pointer, TEST_STACK_SIZE, + tx_thread_create(&test_control_thread, "test control thread", test_control_thread_entry, 0, + pointer, TEST_STACK_SIZE, 17, 15, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE; /* Create the test thread. */ - tx_thread_create(&test_thread, "test thread", test_thread_entry, 0, - pointer, TEST_STACK_SIZE, + tx_thread_create(&test_thread, "test thread", test_thread_entry, 0, + pointer, TEST_STACK_SIZE, 15, 15, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE; /* Create the second test thread. */ - tx_thread_create(&test_thread1, "test thread 1", test_thread_entry1, 0, - pointer, TEST_STACK_SIZE, + tx_thread_create(&test_thread1, "test thread 1", test_thread_entry1, 0, + pointer, TEST_STACK_SIZE, 15, 15, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE; /* Suspend the test thread temporarily. */ tx_thread_suspend(&test_thread); - + /* Resume the test thread again to exercise the resume code fully. */ tx_thread_resume(&test_thread); @@ -645,26 +645,26 @@ TX_THREAD *thread_ptr; test_mutex_from_init += tx_mutex_get(&init_mutex_inherit, TX_NO_WAIT); test_mutex_from_init += tx_mutex_put(&init_mutex_inherit); test_mutex_from_init += tx_mutex_put(&init_mutex_inherit); - + #ifndef TX_DISABLE_ERROR_CHECKING /* Test timer create from initialization. */ test_block_pool_create_init = tx_block_pool_create(&init_block_pool, "init block pool", 10, init_block_pool_area, sizeof(init_block_pool_area)); - + /* Test byte pool create from initialization. */ test_byte_pool_create_init = tx_byte_pool_create(&init_byte_pool, "init byte pool", init_byte_pool_area, sizeof(init_byte_pool_area)); test_byte_pool_create_init += tx_byte_allocate(&init_byte_pool, (VOID **) &pointer, 20, TX_NO_WAIT); test_byte_pool_create_init += tx_byte_release(pointer); - + /* Test event flag create from initialization. */ test_event_flags_from_init = tx_event_flags_create(&init_event_flags, "init events"); - + /* Test queue create from initialization. */ test_queue_from_init = tx_queue_create(&init_queue, "init queue", TX_1_ULONG, init_queue_area, sizeof(init_queue_area)); - + /* Test semaphore create from initialization. */ test_semaphore_from_init = tx_semaphore_create(&init_semaphore, "init semaphore", 0); - + /* Test timer creat from initialization. */ test_timer_create_init = tx_timer_create(&init_timer, "init timer", init_timer_entry, 0x5678, 100, 200, TX_AUTO_ACTIVATE); @@ -675,7 +675,7 @@ TX_THREAD *thread_ptr; /* Remember the free memory pointer. */ test_free_memory_ptr = &tests_memory[0]; //pointer; - + /* Clear the ISR dispatch. */ test_isr_dispatch = TX_NULL; @@ -685,12 +685,12 @@ TX_THREAD *thread_ptr; /* Test to make sure _tx_thread_time_slice can handle a none-ready thread. */ init_test_thread.tx_thread_state = TX_IO_DRIVER; init_test_thread.tx_thread_new_time_slice = 0; - init_test_thread.tx_thread_suspend_cleanup = TX_NULL; + init_test_thread.tx_thread_suspend_cleanup = TX_NULL; init_test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; init_test_thread.tx_thread_suspending = TX_TRUE; - _tx_thread_current_ptr[0] = &init_test_thread; + _tx_thread_current_ptr[0] = &init_test_thread; _tx_thread_time_slice(); - + /* Test to make sure _tx_thread_time_slice can handle preemption-threshold set. */ init_test_thread.tx_thread_state = TX_READY; init_test_thread.tx_thread_new_time_slice = 0; @@ -706,7 +706,7 @@ TX_THREAD *thread_ptr; temp_thread = _tx_thread_execute_ptr[0]; _tx_thread_mutex_release = TX_NULL; init_test_thread.tx_thread_state = TX_READY; - init_test_thread.tx_thread_suspend_cleanup = TX_NULL; + init_test_thread.tx_thread_suspend_cleanup = TX_NULL; init_test_thread.tx_thread_new_time_slice = 0; init_test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; init_test_thread.tx_thread_suspending = TX_FALSE; @@ -715,15 +715,15 @@ TX_THREAD *thread_ptr; _tx_thread_current_ptr[0] = &init_test_thread; _tx_thread_execute_ptr[0] = &init_test_thread; _tx_thread_entry_exit_notify(&init_test_thread, test_exit_notify); - _tx_thread_shell_entry(); + _tx_thread_shell_entry(); _tx_thread_current_ptr[0] = TX_NULL; _tx_thread_execute_ptr[0] = temp_thread; _tx_thread_mutex_release = temp_mutex_release; /* Recover Mutex release pointer. */ - + /* Test _tx_thread_system_suspend when not current, preemption is needed but disabled. */ temp_thread = _tx_thread_execute_ptr[0]; init_test_thread.tx_thread_state = TX_READY; - init_test_thread.tx_thread_suspend_cleanup = TX_NULL; + init_test_thread.tx_thread_suspend_cleanup = TX_NULL; init_test_thread.tx_thread_new_time_slice = 0; init_test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; init_test_thread.tx_thread_suspending = TX_FALSE; @@ -733,13 +733,13 @@ TX_THREAD *thread_ptr; #ifndef TX_NOT_INTERRUPTABLE _tx_thread_preempt_disable++; #endif - _tx_thread_system_suspend(&init_test_thread); + _tx_thread_system_suspend(&init_test_thread); _tx_thread_execute_ptr[0] = temp_thread; - + /* Test _tx_thread_system_resume when not current, suspending and in a COMPLETED state. */ temp_thread = _tx_thread_execute_ptr[0]; init_test_thread.tx_thread_state = TX_COMPLETED; - init_test_thread.tx_thread_suspend_cleanup = TX_NULL; + init_test_thread.tx_thread_suspend_cleanup = TX_NULL; init_test_thread.tx_thread_new_time_slice = 0; init_test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; init_test_thread.tx_thread_suspending = TX_TRUE; @@ -749,14 +749,14 @@ TX_THREAD *thread_ptr; _tx_thread_preempt_disable++; #endif _tx_thread_execute_ptr[0] = &init_test_thread; - _tx_thread_system_resume(&init_test_thread); + _tx_thread_system_resume(&init_test_thread); _tx_thread_execute_ptr[0] = temp_thread; - + /* Test _tx_thread_system_resume when not current, not suspending and already in a TX_READY state. */ temp_thread = _tx_thread_execute_ptr[0]; init_test_thread.tx_thread_state = TX_READY; - init_test_thread.tx_thread_suspend_cleanup = TX_NULL; + init_test_thread.tx_thread_suspend_cleanup = TX_NULL; init_test_thread.tx_thread_new_time_slice = 0; init_test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; init_test_thread.tx_thread_suspending = TX_FALSE; @@ -766,13 +766,13 @@ TX_THREAD *thread_ptr; _tx_thread_preempt_disable++; #endif _tx_thread_execute_ptr[0] = &init_test_thread; - _tx_thread_system_resume(&init_test_thread); + _tx_thread_system_resume(&init_test_thread); _tx_thread_execute_ptr[0] = temp_thread; /* Test _tx_thread_system_resume when not current, suspending and in a TERMINATED state. */ temp_thread = _tx_thread_execute_ptr[0]; init_test_thread.tx_thread_state = TX_TERMINATED; - init_test_thread.tx_thread_suspend_cleanup = TX_NULL; + init_test_thread.tx_thread_suspend_cleanup = TX_NULL; init_test_thread.tx_thread_new_time_slice = 0; init_test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; init_test_thread.tx_thread_suspending = TX_TRUE; @@ -782,9 +782,9 @@ TX_THREAD *thread_ptr; _tx_thread_preempt_disable++; #endif _tx_thread_execute_ptr[0] = &init_test_thread; - _tx_thread_system_resume(&init_test_thread); + _tx_thread_system_resume(&init_test_thread); _tx_thread_execute_ptr[0] = temp_thread; - + /* Test tx_thread_resume to test the saved_thread_ptr being NULL. */ temp_thread = _tx_thread_execute_ptr[0]; _tx_thread_execute_ptr[0] = TX_NULL; @@ -794,7 +794,7 @@ TX_THREAD *thread_ptr; /* Test preemption change when the new priority is the same as the threshold. */ init_test_thread.tx_thread_state = TX_SUSPENDED; - init_test_thread.tx_thread_suspend_cleanup = TX_NULL; + init_test_thread.tx_thread_suspend_cleanup = TX_NULL; init_test_thread.tx_thread_new_time_slice = 0; init_test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; init_test_thread.tx_thread_suspending = TX_FALSE; @@ -805,9 +805,9 @@ TX_THREAD *thread_ptr; init_test_thread.tx_thread_preempt_threshold = 10; init_test_thread.tx_thread_entry = test_thread_entry1; _tx_thread_preemption_change(&init_test_thread, 10, &old_preemption); - + #ifndef TX_NOT_INTERRUPTABLE - + /* Test semaphore cleanup with an invalid semaphore ID. */ init_test_thread.tx_thread_suspend_control_block = (VOID *) &cleanup_semaphore; init_test_thread.tx_thread_suspend_cleanup = &(_tx_semaphore_cleanup); @@ -823,7 +823,7 @@ TX_THREAD *thread_ptr; cleanup_semaphore.tx_semaphore_suspended_count = 0; init_test_thread.tx_thread_suspension_sequence = 0; _tx_semaphore_cleanup(&init_test_thread, 1); - + /* Test semaphore cleanup with a NULL semaphore pointer. */ init_test_thread.tx_thread_suspend_control_block = TX_NULL; init_test_thread.tx_thread_suspend_cleanup = &(_tx_semaphore_cleanup); @@ -871,7 +871,7 @@ TX_THREAD *thread_ptr; cleanup_queue.tx_queue_suspended_count = 0; init_test_thread.tx_thread_suspension_sequence = 0; _tx_queue_cleanup(&init_test_thread, 1); - + /* Test queue cleanup with an valid queue ID but a suspension count of 0. */ init_test_thread.tx_thread_suspend_control_block = (VOID *) &cleanup_queue; init_test_thread.tx_thread_suspend_cleanup = &(_tx_queue_cleanup); @@ -911,7 +911,7 @@ TX_THREAD *thread_ptr; cleanup_mutex.tx_mutex_suspended_count = 0; init_test_thread.tx_thread_suspension_sequence = 0; _tx_mutex_cleanup(&init_test_thread, 1); - + /* Test mutex cleanup with an valid mutex ID but a suspension count of 0. */ init_test_thread.tx_thread_suspend_control_block = (VOID *) &cleanup_mutex; init_test_thread.tx_thread_suspend_cleanup = &(_tx_mutex_cleanup); @@ -919,7 +919,7 @@ TX_THREAD *thread_ptr; cleanup_mutex.tx_mutex_suspended_count = 0; init_test_thread.tx_thread_suspension_sequence = 0; _tx_mutex_cleanup(&init_test_thread, 0); - + /* Test event flag cleanup with a NULL cleanup pointer. */ init_test_thread.tx_thread_suspend_control_block = (VOID *) &cleanup_event_flags; init_test_thread.tx_thread_suspend_cleanup = TX_NULL; @@ -943,7 +943,7 @@ TX_THREAD *thread_ptr; cleanup_event_flags.tx_event_flags_group_suspended_count = 0; init_test_thread.tx_thread_suspension_sequence = 0; _tx_event_flags_cleanup(&init_test_thread, 0); - + /* Test event flag cleanup with an invalid suspension sequence. */ init_test_thread.tx_thread_suspend_control_block = (VOID *) &cleanup_event_flags; init_test_thread.tx_thread_suspend_cleanup = &(_tx_event_flags_cleanup); @@ -959,7 +959,7 @@ TX_THREAD *thread_ptr; cleanup_event_flags.tx_event_flags_group_suspended_count = 0; init_test_thread.tx_thread_suspension_sequence = 0; _tx_event_flags_cleanup(&init_test_thread, 0); - + /* Test block pool cleanup with a NULL cleanup pointer. */ init_test_thread.tx_thread_suspend_control_block = (VOID *) &cleanup_block_pool; init_test_thread.tx_thread_suspend_cleanup = TX_NULL; @@ -991,7 +991,7 @@ TX_THREAD *thread_ptr; cleanup_block_pool.tx_block_pool_suspended_count = 0; init_test_thread.tx_thread_suspension_sequence = 0; _tx_block_pool_cleanup(&init_test_thread, 1); - + /* Test block pool cleanup with an valid ID but a suspension count of 0. */ init_test_thread.tx_thread_suspend_control_block = (VOID *) &cleanup_block_pool; init_test_thread.tx_thread_suspend_cleanup = &(_tx_block_pool_cleanup); @@ -1031,7 +1031,7 @@ TX_THREAD *thread_ptr; cleanup_byte_pool.tx_byte_pool_suspended_count = 0; init_test_thread.tx_thread_suspension_sequence = 0; _tx_byte_pool_cleanup(&init_test_thread, 1); - + /* Test byte pool cleanup with an valid ID but a suspension count of 0. */ init_test_thread.tx_thread_suspend_control_block = (VOID *) &cleanup_byte_pool; init_test_thread.tx_thread_suspend_cleanup = &(_tx_byte_pool_cleanup); @@ -1040,7 +1040,7 @@ TX_THREAD *thread_ptr; init_test_thread.tx_thread_suspension_sequence = 0; _tx_byte_pool_cleanup(&init_test_thread, 0); #endif - + #ifndef TX_ENABLE_EVENT_TRACE /* Call ISR trace events when trace is not enabled. */ @@ -1071,10 +1071,10 @@ TX_THREAD *thread_ptr; _tx_timer_delete(&test_timer); /* Test the stack analyze function with a dummy thread. */ - + /* Clear the test stack analyze flag. */ test_stack_analyze_flag = 0; - + /* Make a fake thread with a fake stack. */ test_thread2.tx_thread_id = TX_THREAD_ID; #if defined(TX_ENABLE_RANDOM_NUMBER_STACK_FILLING) && defined(TX_ENABLE_STACK_CHECKING) @@ -1091,30 +1091,30 @@ TX_THREAD *thread_ptr; /* Set the fake thread stack to the fill pattern. */ test_thread2_stack[i] = TX_STACK_FILL; } - + /* Setup index to last point. */ i = (sizeof(test_thread2_stack)/sizeof(ULONG)) - 1; - + /* Setup the stack start and end pointers. */ test_thread2.tx_thread_stack_start = &(test_thread2_stack[0]); test_thread2.tx_thread_stack_end = &(test_thread2_stack[i]); test_thread2.tx_thread_stack_size = sizeof(test_thread2_stack); test_thread2.tx_thread_stack_highest_ptr = test_thread2.tx_thread_stack_end; test_thread2.tx_thread_stack_ptr = test_thread2.tx_thread_stack_start; - + /* Fill 20 words of stack. */ for (j = 0; j < 20; j++) { /* Fill the stack with 0s. */ test_thread2_stack[i--] = 0; } - + /* Call the analyze stack function. */ _tx_thread_stack_analyze(&test_thread2); - + /* Call it again for no change coverage. */ _tx_thread_stack_analyze(&test_thread2); - + /* Fill 99 words of stack. */ for (j = 0; j < 99; j++) { @@ -1124,40 +1124,40 @@ TX_THREAD *thread_ptr; /* Call the analyze stack function. */ _tx_thread_stack_analyze(&test_thread2); - + /* Call it again for no change coverage. */ _tx_thread_stack_analyze(&test_thread2); #ifndef TX_MANUAL_TEST - + /* Now set the flag to 1 to cause the thread ID to be cleared. */ test_stack_analyze_flag = 1; - + /* Call stack analyze with an ID that is cleared in the middle. */ _tx_thread_stack_analyze(&test_thread2); - + /* Restore the ID. */ test_thread2.tx_thread_id = TX_THREAD_ID; - + /* Now set the flag to 2 to cause the stack ptr to be equal to the start of the stack. */ test_stack_analyze_flag = 2; - + /* Call stack analyze with an ID that is cleared in the middle. */ _tx_thread_stack_analyze(&test_thread2); test_thread2.tx_thread_stack_highest_ptr = test_thread2.tx_thread_stack_end; /* Now set the flag to 3 to cause the stack pointer to not have the fill pattern. */ test_stack_analyze_flag = 3; - + /* Call stack analyze with an ID that is cleared in the middle. */ _tx_thread_stack_analyze(&test_thread2); #endif - + /* Test error condition on _tx_queue_flush. */ test_queue.tx_queue_enqueued = 1; test_queue.tx_queue_suspended_count = 1; test_queue.tx_queue_suspension_list = TX_NULL; - + /* Call _tx_queue_flush to test the thread NULL check. */ _tx_queue_flush(&test_queue); @@ -1168,8 +1168,8 @@ TX_THREAD *thread_ptr; /* Increment the preempt disable flag. */ _tx_thread_preempt_disable++; - - /* Build a thread control block with fake info. */ + + /* Build a thread control block with fake info. */ test_thread3.tx_thread_suspending = TX_TRUE; test_thread3.tx_thread_state = TX_SUSPENDED; test_thread3.tx_thread_delayed_suspend = TX_FALSE; @@ -1186,25 +1186,25 @@ TX_THREAD *thread_ptr; /* Increment the preempt disable flag. */ _tx_thread_preempt_disable++; - + /* Test block pool suspenson safeguard. */ fake_block_pool.tx_block_pool_available = 0; status = _tx_block_allocate(&fake_block_pool, (VOID **) &pointer, TX_WAIT_FOREVER); if (status != TX_NO_MEMORY) - test_control_system_errors++; + test_control_system_errors++; /* Test byte pool suspension safeguard. */ fake_byte_pool.tx_byte_pool_fragments = 2; fake_byte_pool.tx_byte_pool_available = 0; status = _tx_byte_allocate(&fake_byte_pool, (VOID **) &pointer, 1000, TX_WAIT_FOREVER); if (status != TX_NO_MEMORY) - test_control_system_errors++; + test_control_system_errors++; /* Test event flags suspension safeguard. */ fake_event_flags.tx_event_flags_group_current = 0; status = _tx_event_flags_get(&fake_event_flags, 1, TX_AND, &flags, TX_WAIT_FOREVER); if (status != TX_NO_EVENTS) - test_control_system_errors++; + test_control_system_errors++; /* Test mutex suspension safeguard. */ fake_mutex.tx_mutex_ownership_count = 1; @@ -1212,31 +1212,31 @@ TX_THREAD *thread_ptr; fake_mutex.tx_mutex_owner = &init_test_thread; status = _tx_mutex_get(&fake_mutex, TX_WAIT_FOREVER); if (status != TX_NOT_AVAILABLE) - test_control_system_errors++; + test_control_system_errors++; /* Test queue front send suspension safeguard. */ fake_queue.tx_queue_available_storage = 0; status = _tx_queue_front_send(&fake_queue, (VOID *) pointer, TX_WAIT_FOREVER); if (status != TX_QUEUE_FULL) - test_control_system_errors++; - + test_control_system_errors++; + /* Test queue receive suspension safeguard. */ fake_queue.tx_queue_enqueued = 0; status = _tx_queue_receive(&fake_queue, (VOID **) &pointer, TX_WAIT_FOREVER); if (status != TX_QUEUE_EMPTY) - test_control_system_errors++; + test_control_system_errors++; /* Test queue send suspension safeguard. */ fake_queue.tx_queue_available_storage = 0; status = _tx_queue_send(&fake_queue, (VOID *) pointer, TX_WAIT_FOREVER); if (status != TX_QUEUE_FULL) - test_control_system_errors++; - + test_control_system_errors++; + /* Test semaphore suspension safeguard. */ fake_semaphore.tx_semaphore_count = 0; status = _tx_semaphore_get(&fake_semaphore, TX_WAIT_FOREVER); if (status != TX_NO_INSTANCE) - test_control_system_errors++; + test_control_system_errors++; /* Test thread sleep suspension safeguard. */ _tx_thread_current_ptr[0] = &init_test_thread; @@ -1244,13 +1244,13 @@ TX_THREAD *thread_ptr; _tx_thread_system_state[0] = 0; status = _tx_thread_sleep(10); if (status != TX_CALLER_ERROR) - test_control_system_errors++; + test_control_system_errors++; /* Test thread suspend suspension safeguard. */ init_test_thread.tx_thread_state = TX_READY; status = _tx_thread_suspend(&init_test_thread); if (status != TX_SUSPEND_ERROR) - test_control_system_errors++; + test_control_system_errors++; _tx_thread_system_state[0] = temp; _tx_thread_current_ptr[0] = TX_NULL; @@ -1261,9 +1261,9 @@ TX_THREAD *thread_ptr; /* Move the test thread form core 0. */ tx_thread_smp_core_exclude(&test_thread, 0x1); - /* Restore the core exclusion for the test thread. */ + /* Restore the core exclusion for the test thread. */ tx_thread_smp_core_exclude(&test_thread, temp); - + /* Test some code paths in the tx_thread_smp_utilities file. */ temp_thread = _tx_thread_current_ptr[3]; _tx_thread_current_ptr[3] = &init_test_thread; @@ -1275,7 +1275,7 @@ TX_THREAD *thread_ptr; _tx_thread_execute_ptr[0] = temp_thread; _tx_thread_smp_schedule_list[0] = TX_NULL; _tx_thread_smp_remap_solution_find(&init_test_thread, 1, 1, 1); - + /* Test a corner case in time-slice change. */ init_test_thread.tx_thread_smp_core_mapped = TX_THREAD_SMP_MAX_CORES; _tx_thread_time_slice_change(&init_test_thread, 3, &old_time_slice); @@ -1298,7 +1298,7 @@ TX_THREAD *thread_ptr; _tx_timer_time_slice[2] = 0; _tx_timer_time_slice[3] = 1; _tx_thread_time_slice(); - + _tx_timer_time_slice[0] = 1; _tx_timer_time_slice[1] = 0; _tx_timer_time_slice[2] = 0; @@ -1317,14 +1317,14 @@ TX_THREAD *thread_ptr; _tx_thread_current_ptr[0] = temp_thread; _tx_thread_time_slice(); _tx_thread_current_ptr[0] = TX_NULL; - + /* Decrement the preempt disable flag. */ _tx_thread_preempt_disable--; } -/* Define the test control thread. This thread is responsible for dispatching all of the +/* Define the test control thread. This thread is responsible for dispatching all of the tests in the ThreadX test suite. */ void test_control_thread_entry(ULONG thread_input) @@ -1363,7 +1363,7 @@ UINT i; /* Suspend control test to allow test to run. */ tx_thread_suspend(&test_control_thread); - + /* Test finished, cleanup in preparation for the next test. */ test_control_cleanup(); } @@ -1375,7 +1375,7 @@ UINT i; exit(test_control_failed_tests + test_control_system_errors); #else external_exit(test_control_failed_tests + test_control_system_errors); -#endif +#endif } @@ -1404,11 +1404,11 @@ UINT old_posture = TX_INT_ENABLE; /* Get protection for examination of preempt disable and system state variables. */ TX_DISABLE - + /* Is preempt disable flag set? */ if (_tx_thread_preempt_disable) { - + /* System error - preempt disable should never be set inside of a thread! */ printf(" ***** SYSTEM ERROR ***** _tx_thread_preempt_disable is non-zero!\n"); test_control_system_errors++; @@ -1417,7 +1417,7 @@ UINT old_posture = TX_INT_ENABLE; /* Is system state set? */ if (_tx_thread_system_state[0]) { - + /* System error - system state should never be set inside of a thread! */ printf(" ***** SYSTEM ERROR ***** _tx_thread_system_state is non-zero!\n"); test_control_system_errors++; @@ -1426,10 +1426,10 @@ UINT old_posture = TX_INT_ENABLE; /* Release protection. */ TX_RESTORE - /* Are interrupts disabled? */ + /* Are interrupts disabled? */ if (old_posture == TX_INT_DISABLE) { - + /* System error - interrupts should alwasy be enabled in our test threads! */ printf(" ***** SYSTEM ERROR ***** test returned with interrupts disabled!\n"); test_control_system_errors++; @@ -1580,16 +1580,16 @@ void test_thread_entry(ULONG thread_input) /* Suspend this thread but with preemption disabled, so we will actually return. */ _tx_thread_preempt_disable++; tx_thread_suspend(&test_thread); - + /* Now perform a fake thread resume to cause preemption and exercise the path in _tx_thread_system_resume that returns to the scheduler. */ init_test_thread.tx_thread_state = TX_TERMINATED; - init_test_thread.tx_thread_suspend_cleanup = TX_NULL; + init_test_thread.tx_thread_suspend_cleanup = TX_NULL; init_test_thread.tx_thread_new_time_slice = 0; init_test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; init_test_thread.tx_thread_suspending = TX_TRUE; init_test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; init_test_thread.tx_thread_entry = test_thread_entry1; - _tx_thread_system_resume(&init_test_thread); + _tx_thread_system_resume(&init_test_thread); #ifdef TX_NOT_INTERRUPTABLE _tx_thread_preempt_disable--; #endif @@ -1607,7 +1607,7 @@ void test_exit_notify(TX_THREAD *thread_ptr, UINT type) { /* Clear the suspending flag to short-circuit the suspension. */ - thread_ptr -> tx_thread_suspending = TX_FALSE; + thread_ptr -> tx_thread_suspending = TX_FALSE; } __attribute__((weak)) void abort_all_threads_suspended_on_mutex(void) diff --git a/test/smp/regression/threadx_block_memory_basic_test.c b/test/smp/regression/threadx_block_memory_basic_test.c index 5f2afa01..12e301d1 100644 --- a/test/smp/regression/threadx_block_memory_basic_test.c +++ b/test/smp/regression/threadx_block_memory_basic_test.c @@ -1,4 +1,4 @@ -/* This test is designed to test simple memory block pool creation, deletion, and +/* This test is designed to test simple memory block pool creation, deletion, and allocates and releases. */ #include @@ -79,7 +79,7 @@ CHAR *pointer; /* Determine if calling block pool create from initialization was successful. */ if (test_block_pool_create_init != TX_SUCCESS) { - + /* Error! */ error++; } @@ -87,7 +87,7 @@ CHAR *pointer; /* Attempt to create a block pool from a timer. */ pointer = (CHAR *) 0x30000; status = tx_block_pool_create(&pool_3, "pool 3", 100, pointer, 320); - + /* Check status. */ if (status != TX_CALLER_ERROR) { @@ -98,7 +98,7 @@ CHAR *pointer; /* Attempt to delete a block pool. */ status = tx_block_pool_delete(&pool_0); - + /* Check status. */ if (status != TX_CALLER_ERROR) { @@ -106,7 +106,7 @@ CHAR *pointer; /* Error! */ error++; } - + timer_executed = 1; /* Attempt to allocate a block with suspension from a timer. */ @@ -190,8 +190,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -203,8 +203,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -278,7 +278,7 @@ unsigned long fake_block[20]; block_memory.second_middle= 0x61718191; block_memory.next_to_last = 0x99aabbcc; block_memory.last = 0xddeeff00; - + /* Create the block pool. */ status = tx_block_pool_create(&block_memory.pool, "pool memory", 16, &block_memory.pool_area[0], (2048*sizeof(ULONG))/sizeof(ULONG)); tx_block_pool_delete(&block_memory.pool); @@ -304,7 +304,7 @@ unsigned long fake_block[20]; fake_block[0] = 0; fake_block[1] = 0; status = tx_block_release(&fake_block[2]); - + /* Check status. */ if (status != TX_PTR_ERROR) { @@ -318,7 +318,7 @@ unsigned long fake_block[20]; fake_block[0] = 0; fake_block[1] = (unsigned long) &fake_block[0]; status = tx_block_release(&fake_block[2]); - + /* Check status. */ if (status != TX_PTR_ERROR) { @@ -328,7 +328,7 @@ unsigned long fake_block[20]; test_control_return(1); } #endif - + /* Allocate first block from the pool. */ status = tx_block_allocate(&pool_0, (VOID **) &pointer_1, TX_NO_WAIT); @@ -504,10 +504,10 @@ unsigned long fake_block[20]; /* Sleep for a bit... */ tx_thread_sleep(3); - + /* Now resume the background thread. */ tx_thread_resume(&thread_1); - + /* Sleep for a bit... */ tx_thread_sleep(3); @@ -517,7 +517,7 @@ unsigned long fake_block[20]; /* Test for error. */ if ((error) || (timer_executed != 1) || (isr_executed != 1)) { - + /* Block memory error. */ printf("ERROR #20\n"); test_control_return(1); @@ -549,7 +549,7 @@ unsigned long fake_block[20]; } else { - + /* Successful test. */ printf("SUCCESS!\n"); test_control_return(0); @@ -562,7 +562,7 @@ static void thread_1_entry(ULONG thread_input) while(1) { - - tx_thread_relinquish(); + + tx_thread_relinquish(); } } diff --git a/test/smp/regression/threadx_block_memory_error_detection_test.c b/test/smp/regression/threadx_block_memory_error_detection_test.c index de28012f..7b7f2f61 100644 --- a/test/smp/regression/threadx_block_memory_error_detection_test.c +++ b/test/smp/regression/threadx_block_memory_error_detection_test.c @@ -1,5 +1,5 @@ /* This test is designed to test error detection for simple memory block operations. */ - + #include #include "tx_api.h" @@ -43,8 +43,8 @@ INT status; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -160,7 +160,7 @@ INT i; printf("ERROR #8\n"); test_control_return(1); } - + /* Allocate with bad pool pointer. */ pool_2.tx_block_pool_id = 0; status = tx_block_allocate(&pool_2, (VOID **) TX_NULL, TX_NO_WAIT); @@ -379,7 +379,7 @@ INT i; thread_0_counter++; #endif /* TX_DISABLE_ERROR_CHECKING */ - + /* All is good! */ printf("SUCCESS!\n"); test_control_return(0); diff --git a/test/smp/regression/threadx_block_memory_information_test.c b/test/smp/regression/threadx_block_memory_information_test.c index d6416bc2..20e34d88 100644 --- a/test/smp/regression/threadx_block_memory_information_test.c +++ b/test/smp/regression/threadx_block_memory_information_test.c @@ -39,7 +39,7 @@ static TX_THREAD thread_6; static TX_BLOCK_POOL block_pool_0; static TX_BLOCK_POOL block_pool_2; -#ifdef TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO +#ifdef TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO static TX_BLOCK_POOL block_pool_1; #endif @@ -57,8 +57,8 @@ static void thread_5_entry(ULONG thread_input); static void thread_6_entry(ULONG thread_input); /* Direct core function to bypass the error checking shell. */ -UINT _tx_block_pool_info_get(TX_BLOCK_POOL *pool_ptr, CHAR **name, ULONG *available_blocks, - ULONG *total_blocks, TX_THREAD **first_suspended, +UINT _tx_block_pool_info_get(TX_BLOCK_POOL *pool_ptr, CHAR **name, ULONG *available_blocks, + ULONG *total_blocks, TX_THREAD **first_suspended, ULONG *suspended_count, TX_BLOCK_POOL **next_pool); /* Prototype for test control return. */ @@ -78,7 +78,7 @@ static void test_isr(void) tx_thread_wait_abort(&thread_3); /* End the ISR processing. */ - test_status = 2; + test_status = 2; test_isr_dispatch = TX_NULL; } } @@ -103,8 +103,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -116,8 +116,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -129,8 +129,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -142,8 +142,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 3, 3, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -155,8 +155,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 4, 4, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -168,8 +168,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, TEST_STACK_SIZE_PRINTF, 5, 5, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -181,8 +181,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, + pointer, TEST_STACK_SIZE_PRINTF, 6, 6, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -197,7 +197,7 @@ CHAR *pointer; /* Create the block_pool with one block. */ status = tx_block_pool_create(&block_pool_0, "block_pool 0", 30, pointer, 40); pointer = pointer + 40; - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -282,7 +282,7 @@ ULONG timeouts; tx_thread_resume(&thread_4); tx_thread_resume(&thread_5); tx_thread_resume(&thread_6); - + /* Prioritize the block pool suspension list. */ status = tx_block_pool_prioritize(&block_pool_0); @@ -294,10 +294,10 @@ ULONG timeouts; printf("ERROR #12\n"); test_control_return(1); } - + /* Now loop to test the interrupt of the prioritize loop logic. */ test_status = 1; - test_isr_dispatch = test_isr; + test_isr_dispatch = test_isr; do { @@ -314,10 +314,10 @@ ULONG timeouts; } } while (test_status == 1); - + /* Now determine if thread 4 is at the front of the list... It should be! */ if (block_pool_0.tx_block_pool_suspension_list != &thread_4) - { + { /* Block Pool error. */ printf("ERROR #14\n"); @@ -352,13 +352,13 @@ ULONG timeouts; } #endif - + /* Now use the information services in order to test them. */ status = tx_block_pool_info_get(&block_pool_0, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_block_pool_info_get(&block_pool_0, &name, &available, &total_blocks, &first_suspended, &suspended_count, &next_pool); - + /* Check for an error condition. */ - if ((status) || (available != block_pool_0.tx_block_pool_available) || (total_blocks != block_pool_0.tx_block_pool_total) || + if ((status) || (available != block_pool_0.tx_block_pool_available) || (total_blocks != block_pool_0.tx_block_pool_total) || (first_suspended != &thread_4) || (suspended_count != block_pool_0.tx_block_pool_suspended_count) || (next_pool != &block_pool_0)) { @@ -367,11 +367,11 @@ ULONG timeouts; test_control_return(1); } -#ifdef TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO +#ifdef TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO /* Call the core block pool info get function with a NULL pointer. */ status = _tx_block_pool_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); - + /* Check for the proper error code. */ if (status != TX_PTR_ERROR) { @@ -383,7 +383,7 @@ ULONG timeouts; /* Call the core block pool info get function with a non-initialized pool. */ status = _tx_block_pool_performance_info_get(&block_pool_1, TX_NULL, TX_NULL, TX_NULL, TX_NULL); - + /* Check for the proper error code. */ if (status != TX_PTR_ERROR) { @@ -396,11 +396,11 @@ ULONG timeouts; /* Now get the pool performance information. */ status = tx_block_pool_performance_info_get(&block_pool_0, TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_block_pool_performance_info_get(&block_pool_0, &allocates, &releases, &suspensions, &timeouts); - + /* Check for an error condition. */ - if ((status) || (allocates != block_pool_0.tx_block_pool_performance_allocate_count) || - (releases != block_pool_0.tx_block_pool_performance_release_count) || - (suspensions != block_pool_0.tx_block_pool_performance_suspension_count) || + if ((status) || (allocates != block_pool_0.tx_block_pool_performance_allocate_count) || + (releases != block_pool_0.tx_block_pool_performance_release_count) || + (suspensions != block_pool_0.tx_block_pool_performance_suspension_count) || (timeouts != block_pool_0.tx_block_pool_performance_timeout_count)) { @@ -412,9 +412,9 @@ ULONG timeouts; /* Now get the system pool performance information. */ status = tx_block_pool_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_block_pool_performance_system_info_get(&allocates, &releases, &suspensions, &timeouts); - + /* Check for an error condition. */ - if ((status) || (allocates != _tx_block_pool_performance_allocate_count) || (releases != _tx_block_pool_performance_release_count) || + if ((status) || (allocates != _tx_block_pool_performance_allocate_count) || (releases != _tx_block_pool_performance_release_count) || (suspensions != _tx_block_pool_performance_suspension_count) || (timeouts != _tx_block_pool_performance_timeout_count)) { @@ -433,7 +433,7 @@ ULONG timeouts; /* Call the block pool performance info get function. */ status = tx_block_pool_performance_info_get(&block_pool_0, &allocates, &releases, &suspensions, &timeouts); - + /* Check for the proper error code. */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -445,7 +445,7 @@ ULONG timeouts; /* Call the block pool performance info get function. */ status = tx_block_pool_performance_info_get(TX_NULL, &allocates, &releases, &suspensions, &timeouts); - + /* Check for the proper error code. */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -457,7 +457,7 @@ ULONG timeouts; /* Call the block pool performance info get function. */ status = tx_block_pool_performance_info_get(TX_NULL, TX_NULL, &releases, &suspensions, &timeouts); - + /* Check for the proper error code. */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -469,7 +469,7 @@ ULONG timeouts; /* Call the block pool performance info get function. */ status = tx_block_pool_performance_info_get(TX_NULL, TX_NULL, TX_NULL, &suspensions, &timeouts); - + /* Check for the proper error code. */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -481,7 +481,7 @@ ULONG timeouts; /* Call the block pool performance info get function. */ status = tx_block_pool_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, &timeouts); - + /* Check for the proper error code. */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -493,7 +493,7 @@ ULONG timeouts; /* Call the block pool performance info get function. */ status = tx_block_pool_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); - + /* Check for the proper error code. */ if (status != TX_FEATURE_NOT_ENABLED) { diff --git a/test/smp/regression/threadx_block_memory_prioritize_test.c b/test/smp/regression/threadx_block_memory_prioritize_test.c index 274daa01..6238aef8 100644 --- a/test/smp/regression/threadx_block_memory_prioritize_test.c +++ b/test/smp/regression/threadx_block_memory_prioritize_test.c @@ -76,12 +76,12 @@ static void test_isr(void) } else { - + /* Abort the wait of thread 5. */ tx_thread_wait_abort(&thread_5); /* End the ISR processing. */ - test_status = 2; + test_status = 2; test_isr_dispatch = TX_NULL; } } @@ -107,8 +107,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -120,8 +120,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -133,8 +133,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -146,8 +146,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 3, 3, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -159,8 +159,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 4, 4, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -172,8 +172,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, TEST_STACK_SIZE_PRINTF, 5, 5, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -185,8 +185,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, + pointer, TEST_STACK_SIZE_PRINTF, 6, 6, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -201,7 +201,7 @@ CHAR *pointer; /* Create the block_pool with one block. */ status = tx_block_pool_create(&block_pool_0, "block_pool 0", 30, pointer, 40); pointer = pointer + 40; - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -229,7 +229,7 @@ VOID *pointer; /* Attempt to prioritize with a NULL pointer. */ status = tx_block_pool_prioritize(TX_NULL); - + /* Check for an error condition. */ if (status != TX_POOL_ERROR) { @@ -242,7 +242,7 @@ VOID *pointer; /* Attempt to prioritize with a bad pool pointer. */ block_pool_1.tx_block_pool_id = 0; status = tx_block_pool_prioritize(&block_pool_1); - + /* Check for an error condition. */ if (status != TX_POOL_ERROR) { @@ -296,7 +296,7 @@ VOID *pointer; printf("ERROR #13\n"); test_control_return(1); } - + /* Call block pool prioritize again to test the don't-do-anything path in tx_block_pool_prioritize. */ status += tx_block_pool_prioritize(&block_pool_0); @@ -307,7 +307,7 @@ VOID *pointer; tx_thread_resume(&thread_4); tx_thread_resume(&thread_5); tx_thread_resume(&thread_6); - + /* Prioritize the block pool suspension list. */ status = tx_block_pool_prioritize(&block_pool_0); @@ -319,10 +319,10 @@ VOID *pointer; printf("ERROR #14\n"); test_control_return(1); } - + /* Now loop to test the interrupt of the prioritize loop logic. */ test_status = 1; - test_isr_dispatch = test_isr; + test_isr_dispatch = test_isr; do { @@ -339,10 +339,10 @@ VOID *pointer; } } while (test_status == 1); - + /* Now determine if thread 4 is at the front of the list... It should be! */ if (block_pool_0.tx_block_pool_suspension_list != &thread_4) - { + { /* Block Pool error. */ printf("ERROR #16\n"); diff --git a/test/smp/regression/threadx_block_memory_suspension_test.c b/test/smp/regression/threadx_block_memory_suspension_test.c index 6f2d635c..da14f454 100644 --- a/test/smp/regression/threadx_block_memory_suspension_test.c +++ b/test/smp/regression/threadx_block_memory_suspension_test.c @@ -43,8 +43,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -56,8 +56,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -69,8 +69,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -186,7 +186,7 @@ CHAR *pointer_3; } /* At this point the other thread has run and there is one block free. */ - + /* Get the last block again. */ status = tx_block_allocate(&pool_0, (VOID **) &pointer_3, TX_NO_WAIT); @@ -201,13 +201,13 @@ CHAR *pointer_3; /* Set all the memory of the blocks. */ TX_MEMSET(pointer_3, (CHAR) 0xEF, 100); - + /* Resume the second thread. */ tx_thread_resume(&thread_2); - + /* Let both threads suspend on the block pool via relinquish. */ tx_thread_relinquish(); - + /* Now release the block. */ status = tx_block_release(pointer_3); @@ -219,13 +219,13 @@ CHAR *pointer_3; printf("ERROR #10\n"); test_control_return(1); } - + /* Let thread 1 release the block. */ tx_thread_relinquish(); - + /* Let thread 2 get the block and release the block. */ tx_thread_relinquish(); - + /* Check status and run counter. */ if ((thread_1_counter != 3) || (thread_2_counter != 1)) { diff --git a/test/smp/regression/threadx_block_memory_suspension_timeout_test.c b/test/smp/regression/threadx_block_memory_suspension_timeout_test.c index f290f01a..dc460662 100644 --- a/test/smp/regression/threadx_block_memory_suspension_timeout_test.c +++ b/test/smp/regression/threadx_block_memory_suspension_timeout_test.c @@ -44,8 +44,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -57,8 +57,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -70,8 +70,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -116,7 +116,7 @@ CHAR *pointer_3; status = tx_block_allocate(&pool_0, (VOID **) &pointer_1, TX_NO_WAIT); status += tx_block_allocate(&pool_0, (VOID **) &pointer_2, TX_NO_WAIT); status += tx_block_allocate(&pool_0, (VOID **) &pointer_3, TX_NO_WAIT); - + /* Check status. */ if (status != TX_SUCCESS) { @@ -152,7 +152,7 @@ CHAR *pointer_3; } else { - + /* Successful test. */ printf("SUCCESS!\n"); test_control_return(0); diff --git a/test/smp/regression/threadx_block_memory_thread_terminate_test.c b/test/smp/regression/threadx_block_memory_thread_terminate_test.c index c9221af9..6064891d 100644 --- a/test/smp/regression/threadx_block_memory_thread_terminate_test.c +++ b/test/smp/regression/threadx_block_memory_thread_terminate_test.c @@ -42,8 +42,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -55,8 +55,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -101,7 +101,7 @@ CHAR *pointer_3; status = tx_block_allocate(&pool_0, (VOID **) &pointer_1, TX_NO_WAIT); status += tx_block_allocate(&pool_0, (VOID **) &pointer_2, TX_NO_WAIT); status += tx_block_allocate(&pool_0, (VOID **) &pointer_3, TX_NO_WAIT); - + /* Increment the run counter. */ thread_0_counter++; @@ -118,7 +118,7 @@ CHAR *pointer_3; TX_MEMSET(pointer_1, (CHAR) 0xEF, 100); TX_MEMSET(pointer_2, (CHAR) 0xEF, 100); TX_MEMSET(pointer_3, (CHAR) 0xEF, 100); - + /* Let other thread suspend on block pool. */ tx_thread_relinquish(); diff --git a/test/smp/regression/threadx_byte_memory_basic_test.c b/test/smp/regression/threadx_byte_memory_basic_test.c index 9fffc840..36f41331 100644 --- a/test/smp/regression/threadx_byte_memory_basic_test.c +++ b/test/smp/regression/threadx_byte_memory_basic_test.c @@ -1,4 +1,4 @@ -/* This test is designed to test simple memory byte pool creation, deletion, and +/* This test is designed to test simple memory byte pool creation, deletion, and allocates and releases. */ #include @@ -84,7 +84,7 @@ CHAR *pointer; /* Determine if calling byte pool create from initialization was successful. */ if (test_byte_pool_create_init != TX_SUCCESS) { - + /* Error! */ error++; } @@ -92,7 +92,7 @@ CHAR *pointer; /* Attempt to create a byte pool from a timer. */ pointer = (CHAR *) 0x30000; status = tx_byte_pool_create(&pool_2, "pool 2", pointer, 108); - + /* Check status. */ if (status != TX_CALLER_ERROR) { @@ -138,14 +138,14 @@ CHAR *pointer; /* Attempt to release byte memory from timer. */ pointer = (CHAR *) 0x30000; status = tx_byte_release(pointer); - + /* Check for error status! */ if (status != TX_CALLER_ERROR) { - + /* Error! */ error++; - } + } timer_executed = 1; #endif @@ -209,14 +209,14 @@ UINT status; /* Attempt to release byte memory from ISR. */ pointer = (CHAR *) 0x30000; status = tx_byte_release(pointer); - + /* Check for error status! */ if (status != TX_CALLER_ERROR) { - + /* Error! */ error++; - } + } isr_executed = 1; #endif @@ -235,15 +235,15 @@ void threadx_byte_memory_basic_application_define(void *first_unused_memory) UINT status; CHAR *pointer; - + /* Put first available memory address into a character pointer. */ pointer = (CHAR *) first_unused_memory; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -290,44 +290,44 @@ CHAR *pointer; printf("Running Byte Memory Basic Test...................................... ERROR #3a\n"); test_control_return(1); } - + /* Allocate first block. */ status += tx_byte_allocate(&pool_4, (VOID **) &block_0, 80, TX_NO_WAIT); - + /* Save next search pointer. */ search_ptr_1 = pool_4.tx_byte_pool_search; - + /* Clear the allocatged memory. */ TX_MEMSET(block_0, 0, 80); - + /* Allocate another block. */ status += tx_byte_allocate(&pool_4, (VOID **) &block_1, 80, TX_NO_WAIT); - + /* Clear the allocated block. */ TX_MEMSET(block_1, 0, 80); - + /* Allocate the third and final block. */ status += tx_byte_allocate(&pool_4, (VOID **) &block_2, 80, TX_NO_WAIT); - + /* Clear the allocated block. */ TX_MEMSET(block_2, 0, 80); /* Release the first block. */ status += tx_byte_release(block_0); - + /* Release the second block. */ status += tx_byte_release(block_1); - + /* Manually move the search pointer to create the case where the search wraps and a merge happens on the search pointer necessitating its update. */ pool_4.tx_byte_pool_search = search_ptr_1; /* Point to the middle block. */ /* Allocate a larger block that will wrap the search and require moving as well as an update of the search pointer. */ status += tx_byte_allocate(&pool_4, (VOID **) &block_3, 120, TX_NO_WAIT); - - /* Clear the newly allocated block. */ + + /* Clear the newly allocated block. */ TX_MEMSET(block_3, 0, 120); - + /* At this point, verify the search pointer was properly updated in the previous allocation. */ status += tx_byte_allocate(&pool_4, (VOID **) &block_4, 40, TX_NO_WAIT); /* Should fail since search pointer is now invalid! */ @@ -367,7 +367,7 @@ UCHAR *save_search; byte_memory.second_middle= 0x61718191; byte_memory.next_to_last = 0x99aabbcc; byte_memory.last = 0xddeeff00; - + /* Create the byte pool. */ status = tx_byte_pool_create(&byte_memory.pool, "pool memory", &byte_memory.pool_area[0], (2048*sizeof(ULONG))/sizeof(ULONG)); tx_byte_pool_delete(&byte_memory.pool); @@ -477,7 +477,7 @@ UCHAR *save_search; printf("ERROR #11\n"); test_control_return(1); } - + /* Test non-created pool pointer. */ pool_2.tx_byte_pool_id = 0; status = tx_byte_allocate(&pool_2, (VOID **) &pointer_1, 24, TX_NO_WAIT); @@ -530,15 +530,15 @@ UCHAR *save_search; /* Test NULL pointer release. */ status = tx_byte_release(TX_NULL); - + /* Check for error status! */ if (status != TX_PTR_ERROR) { - + /* Byte memory error. */ printf("ERROR #16\n"); test_control_return(1); - } + } /* Allocate memory from the pool. */ status = tx_byte_allocate(&pool_0, (VOID **) &pointer_1, 24, TX_NO_WAIT); @@ -599,30 +599,30 @@ UCHAR *save_search; /* Test the byte release with a bad block pointer. */ status = _tx_byte_release(TX_NULL); - + /* Check for error status! */ if (status != TX_PTR_ERROR) { - + /* Byte memory error. */ printf("ERROR #21\n"); test_control_return(1); - } + } /* Test another bad block release... no pool pointer! */ array[0] = 0; array[1] = 0; array[2] = 0; status = _tx_byte_release(&array[2]); - + /* Check for error status! */ if (status != TX_PTR_ERROR) { - + /* Byte memory error. */ printf("ERROR #22\n"); test_control_return(1); - } + } /* Test another bad block release.... pool pointer is not a valid pool! */ array[0] = 0; @@ -630,16 +630,16 @@ UCHAR *save_search; array[2] = 0; array[3] = 0; status = _tx_byte_release(&array[2]); - + /* Check for error status! */ if (status != TX_PTR_ERROR) { - + /* Byte memory error. */ printf("ERROR #22\n"); test_control_return(1); - } - + } + /* Now release each of the blocks. */ status = tx_byte_release(pointer_1); @@ -776,7 +776,7 @@ UCHAR *save_search; test_control_return(1); } - /* Now allocate a block that should cause all of the blocks to merge + /* Now allocate a block that should cause all of the blocks to merge together. */ status = tx_byte_allocate(&pool_0, (VOID **) &pointer_3, 88, TX_NO_WAIT); @@ -813,9 +813,9 @@ UCHAR *save_search; printf("ERROR #36\n"); test_control_return(1); } - + /* Now ensure the search pointer update in the byte search algorithm is updated. */ - + /* Allocate memory from the pool. */ status = tx_byte_allocate(&pool_0, (VOID **) &pointer_1, 24, TX_NO_WAIT); @@ -851,10 +851,10 @@ UCHAR *save_search; printf("ERROR #39\n"); test_control_return(1); } - + /* Release the middle block. */ - status = tx_byte_release(pointer_2); - + status = tx_byte_release(pointer_2); + /* Check status. */ if (status != TX_SUCCESS) { @@ -883,7 +883,7 @@ UCHAR *save_search; status = tx_byte_release(pointer_3); status += tx_byte_release(pointer_2); status += tx_byte_release(pointer_1); - + /* Move the search pointer to the third block to exercise that code in the byte search algorithm. */ pool_0.tx_byte_pool_search = (UCHAR *) pointer_3-8; @@ -898,8 +898,8 @@ UCHAR *save_search; printf("ERROR #42\n"); test_control_return(1); } - - + + #ifndef TX_DISABLE_ERROR_CHECKING /* Create a timer for the test. */ @@ -917,14 +917,14 @@ UCHAR *save_search; /* Test for error. */ if ((error) || (timer_executed != 1) || (isr_executed != 1)) { - + /* Byte memory error. */ printf("ERROR #43\n"); test_control_return(1); } #endif - + /* Delete both byte pools. */ status = tx_byte_pool_delete(&pool_0); @@ -950,7 +950,7 @@ UCHAR *save_search; /* Delete pool 4. */ status = tx_byte_pool_delete(&pool_4); - + /* Check status. */ if (status != TX_SUCCESS) { @@ -959,10 +959,10 @@ UCHAR *save_search; printf("ERROR #46\n"); test_control_return(1); } - + /* Create pool 4. */ status = tx_byte_pool_create(&pool_4, "pool 4", pool_4_memory, 300); - + /* Check status. */ if (status != TX_SUCCESS) { @@ -985,15 +985,15 @@ UCHAR *save_search; printf("ERROR #48\n"); test_control_return(1); } - + /* At this point, there should be three allocated blocks and the reserved block at the end. */ - + /* Now release all the blocks in reverse order. This should leave the search pointer at the last block. */ status = tx_byte_release(pointer_3); save_search = pool_4.tx_byte_pool_search; status += tx_byte_release(pointer_2); status += tx_byte_release(pointer_1); - + /* Move the search pointer back to the last block. */ pool_4.tx_byte_pool_search = save_search; @@ -1004,12 +1004,12 @@ UCHAR *save_search; /* Byte memory error. */ printf("ERROR #49\n"); test_control_return(1); - } + } - /* Now attempt to allocate a block that requires a merge, which should exercise the branch in byte search that does not + /* Now attempt to allocate a block that requires a merge, which should exercise the branch in byte search that does not result in a search pointer change. */ status = tx_byte_allocate(&pool_4, (VOID **) &pointer_1, 168, TX_NO_WAIT); - + /* Check status. */ if (status != TX_SUCCESS) { @@ -1017,21 +1017,21 @@ UCHAR *save_search; /* Byte memory error. */ printf("ERROR #50\n"); test_control_return(1); - } - + } + /* Release the last block. */ status = tx_byte_release(pointer_1); - + /* Allocate all the blocks. */ status = tx_byte_allocate(&pool_4, (VOID **) &pointer_1, 84, TX_NO_WAIT); status += tx_byte_allocate(&pool_4, (VOID **) &pointer_2, 84, TX_NO_WAIT); status += tx_byte_allocate(&pool_4, (VOID **) &pointer_3, 84, TX_NO_WAIT); - + /* Release all of the blocks in order. */ status += tx_byte_release(pointer_1); status += tx_byte_release(pointer_2); status += tx_byte_release(pointer_3); - + /* Check status. */ if (status != TX_SUCCESS) { @@ -1039,7 +1039,7 @@ UCHAR *save_search; /* Byte memory error. */ printf("ERROR #50\n"); test_control_return(1); - } + } /* Now setup a special test to exercise the examine blocks equal to 0 path in the byte pool search. */ pool_4.tx_byte_pool_search = save_search; @@ -1047,7 +1047,7 @@ UCHAR *save_search; /* Call byte allocate to execise the examine blocks equal to 0 path on non-merge block condition. */ status = tx_byte_allocate(&pool_4, (VOID **) &pointer_1, 168, TX_NO_WAIT); - + /* Check status. */ if (status != TX_NO_MEMORY) { @@ -1055,8 +1055,8 @@ UCHAR *save_search; /* Byte memory error. */ printf("ERROR #51\n"); test_control_return(1); - } - + } + /* Successful test. */ printf("SUCCESS!\n"); test_control_return(0); diff --git a/test/smp/regression/threadx_byte_memory_information_test.c b/test/smp/regression/threadx_byte_memory_information_test.c index 2d1c20bc..8a619269 100644 --- a/test/smp/regression/threadx_byte_memory_information_test.c +++ b/test/smp/regression/threadx_byte_memory_information_test.c @@ -76,7 +76,7 @@ static void test_isr(void) tx_thread_wait_abort(&thread_3); /* End the ISR processing. */ - test_status = 2; + test_status = 2; test_isr_dispatch = TX_NULL; } } @@ -101,8 +101,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -114,8 +114,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -127,8 +127,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -140,8 +140,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 3, 3, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -153,8 +153,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 4, 4, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -166,8 +166,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, TEST_STACK_SIZE_PRINTF, 5, 5, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -179,8 +179,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, + pointer, TEST_STACK_SIZE_PRINTF, 6, 6, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -195,7 +195,7 @@ CHAR *pointer; /* Create the byte_pool with one byte. */ status = tx_byte_pool_create(&byte_pool_0, "byte_pool 0", pointer, 100); pointer = pointer + 100; - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -274,7 +274,7 @@ ULONG timeouts; printf("ERROR #11\n"); test_control_return(1); } - + /* At this point we are going to get more than 2 threads suspended. */ tx_thread_resume(&thread_1); tx_thread_resume(&thread_2); @@ -285,7 +285,7 @@ ULONG timeouts; /* Prioritize the byte pool suspension list. */ status = tx_byte_pool_prioritize(&byte_pool_0); - + /* Check status and make sure thread 3 is now at the front of the suspension list. */ if ((status != TX_SUCCESS) || (byte_pool_0.tx_byte_pool_suspension_list != &thread_3)) { @@ -297,7 +297,7 @@ ULONG timeouts; /* Now loop to test the interrupt of the prioritize loop logic. */ test_status = 1; - test_isr_dispatch = test_isr; + test_isr_dispatch = test_isr; do { @@ -357,7 +357,7 @@ ULONG timeouts; status += tx_byte_pool_info_get(&byte_pool_0, &name, &available, &fragments, &first_suspended, &suspended_count, &next_pool); /* Check the status. */ - if ((status != TX_SUCCESS) || (available != byte_pool_0.tx_byte_pool_available) || (fragments != byte_pool_0.tx_byte_pool_fragments) || + if ((status != TX_SUCCESS) || (available != byte_pool_0.tx_byte_pool_available) || (fragments != byte_pool_0.tx_byte_pool_fragments) || (first_suspended != &thread_4) || (suspended_count != byte_pool_0.tx_byte_pool_suspended_count) || (next_pool != &byte_pool_0)) { @@ -371,7 +371,7 @@ ULONG timeouts; /* Get the byte pool performance information. */ status = tx_byte_pool_performance_info_get(TX_NULL, &allocates, &releases, &fragments_searched, &merges, &splits, &suspensions, &timeouts); - + /* Check the status. */ if (status != TX_PTR_ERROR) { @@ -380,10 +380,10 @@ ULONG timeouts; printf("ERROR #18\n"); test_control_return(1); } - + /* Get the byte pool performance information. */ status = tx_byte_pool_performance_info_get(&byte_pool_1, &allocates, &releases, &fragments_searched, &merges, &splits, &suspensions, &timeouts); - + /* Check the status. */ if (status != TX_PTR_ERROR) { @@ -395,11 +395,11 @@ ULONG timeouts; /* Get the byte pool performance information. */ status = tx_byte_pool_performance_info_get(&byte_pool_0, &allocates, &releases, &fragments_searched, &merges, &splits, &suspensions, &timeouts); - + /* Check the status. */ - if ((status != TX_SUCCESS) || (allocates != byte_pool_0.tx_byte_pool_performance_allocate_count) || (releases != byte_pool_0.tx_byte_pool_performance_release_count) || - (fragments_searched != byte_pool_0.tx_byte_pool_performance_search_count) || (merges != byte_pool_0.tx_byte_pool_performance_merge_count) || - (splits != byte_pool_0.tx_byte_pool_performance_split_count) || (suspensions != byte_pool_0.tx_byte_pool_performance_suspension_count) || + if ((status != TX_SUCCESS) || (allocates != byte_pool_0.tx_byte_pool_performance_allocate_count) || (releases != byte_pool_0.tx_byte_pool_performance_release_count) || + (fragments_searched != byte_pool_0.tx_byte_pool_performance_search_count) || (merges != byte_pool_0.tx_byte_pool_performance_merge_count) || + (splits != byte_pool_0.tx_byte_pool_performance_split_count) || (suspensions != byte_pool_0.tx_byte_pool_performance_suspension_count) || (timeouts != byte_pool_0.tx_byte_pool_performance_timeout_count)) { @@ -410,11 +410,11 @@ ULONG timeouts; /* Get the byte pool system performance information. */ status = tx_byte_pool_performance_system_info_get(&allocates, &releases, &fragments_searched, &merges, &splits, &suspensions, &timeouts); - + /* Check the status. */ - if ((status != TX_SUCCESS) || (allocates != _tx_byte_pool_performance_allocate_count) || (releases != _tx_byte_pool_performance_release_count) || - (fragments_searched != _tx_byte_pool_performance_search_count) || (merges != _tx_byte_pool_performance_merge_count) || - (splits != _tx_byte_pool_performance_split_count) || (suspensions != _tx_byte_pool_performance_suspension_count) || + if ((status != TX_SUCCESS) || (allocates != _tx_byte_pool_performance_allocate_count) || (releases != _tx_byte_pool_performance_release_count) || + (fragments_searched != _tx_byte_pool_performance_search_count) || (merges != _tx_byte_pool_performance_merge_count) || + (splits != _tx_byte_pool_performance_split_count) || (suspensions != _tx_byte_pool_performance_suspension_count) || (timeouts != _tx_byte_pool_performance_timeout_count)) { diff --git a/test/smp/regression/threadx_byte_memory_prioritize_test.c b/test/smp/regression/threadx_byte_memory_prioritize_test.c index f06d5cd3..29407135 100644 --- a/test/smp/regression/threadx_byte_memory_prioritize_test.c +++ b/test/smp/regression/threadx_byte_memory_prioritize_test.c @@ -74,12 +74,12 @@ static void test_isr(void) } else { - + /* Abort the wait of thread 5. */ tx_thread_wait_abort(&thread_5); /* End the ISR processing. */ - test_status = 2; + test_status = 2; test_isr_dispatch = TX_NULL; } } @@ -105,8 +105,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -118,8 +118,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -131,8 +131,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -144,8 +144,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 3, 3, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -157,8 +157,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 4, 4, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -170,8 +170,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, TEST_STACK_SIZE_PRINTF, 5, 5, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -183,8 +183,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, + pointer, TEST_STACK_SIZE_PRINTF, 6, 6, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -199,7 +199,7 @@ CHAR *pointer; /* Create the byte_pool with one byte. */ status = tx_byte_pool_create(&byte_pool_0, "byte_pool 0", pointer, 100); pointer = pointer + 100; - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -296,7 +296,7 @@ VOID *pointer; /* Call byte pool prioritize again to test the don't-do-anything path in tx_byte_pool_prioritize. */ status += tx_byte_pool_prioritize(&byte_pool_0); - + /* At this point we are going to get more than 2 threads suspended. */ tx_thread_resume(&thread_1); tx_thread_resume(&thread_2); @@ -307,7 +307,7 @@ VOID *pointer; /* Prioritize the byte pool suspension list. */ status = tx_byte_pool_prioritize(&byte_pool_0); - + /* Check status and make sure thread 3 is now at the front of the suspension list. */ if ((status != TX_SUCCESS) || (byte_pool_0.tx_byte_pool_suspension_list != &thread_3)) { @@ -319,7 +319,7 @@ VOID *pointer; /* Now loop to test the interrupt of the prioritize loop logic. */ test_status = 1; - test_isr_dispatch = test_isr; + test_isr_dispatch = test_isr; do { diff --git a/test/smp/regression/threadx_byte_memory_suspension_test.c b/test/smp/regression/threadx_byte_memory_suspension_test.c index 069410c5..ba159894 100644 --- a/test/smp/regression/threadx_byte_memory_suspension_test.c +++ b/test/smp/regression/threadx_byte_memory_suspension_test.c @@ -43,12 +43,12 @@ UCHAR *search_ptr; /* Adjust the search pointer to avoid the search pointer change for this test. */ search_ptr = pool_0.tx_byte_pool_search; while (search_ptr >= pool_0.tx_byte_pool_search) - + { search_ptr = *((UCHAR **) ((VOID *) search_ptr)); } pool_0.tx_byte_pool_search = search_ptr; - + tx_thread_wait_abort(&thread_3); tx_thread_resume(&thread_3); } @@ -77,8 +77,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -90,8 +90,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -103,12 +103,12 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -146,7 +146,7 @@ CHAR *pointer; /* Inform user. */ printf("Running Byte Memory Suspension Test................................. "); - + /* Increment the thread counter. */ thread_0_counter++; @@ -188,7 +188,7 @@ CHAR *pointer; printf("ERROR #7\n"); test_control_return(1); } - + /* Now allocate the memory again. Only one block of this size will fit. */ status = tx_byte_allocate(&pool_0, (VOID **) &pointer, 60, TX_NO_WAIT); @@ -200,15 +200,15 @@ CHAR *pointer; printf("ERROR #8\n"); test_control_return(1); } - + /* Resume the second thread. */ tx_thread_resume(&thread_2); - + /* Now relinquish to let both thread 1 and 2 suspend. */ tx_thread_relinquish(); - + /* At this point both threads should be suspended on the byte pool. */ - + /* Release the memory again. */ status = tx_byte_release(pointer); @@ -220,11 +220,11 @@ CHAR *pointer; printf("ERROR #9\n"); test_control_return(1); } - + /* Now relinquish to get the other threads to run once. */ tx_thread_relinquish(); tx_thread_relinquish(); - + /* At this point both threads 1 and 2 are suspended on the byte pool again. */ if ((thread_1_counter != 3) && (thread_2_counter != 1)) { @@ -233,7 +233,7 @@ CHAR *pointer; printf("ERROR #10\n"); test_control_return(1); } - + /* Now allocate the memory again. Only one block of this size will fit. */ status = tx_byte_allocate(&pool_0, (VOID **) &pointer, 60, TX_NO_WAIT); @@ -245,25 +245,25 @@ CHAR *pointer; printf("ERROR #10a\n"); test_control_return(1); } - + /* Resume thread 3 to get it suspended on the the pool. */ tx_thread_resume(&thread_3); #ifdef TX_MANUAL_TEST /* Set BP hear. Now release the memory and step into the code. After byte search issue IRQ2 mannually, which will - make thread 3 abort the first request and make another request of a different size. This is the path we are trying + make thread 3 abort the first request and make another request of a different size. This is the path we are trying to generate in the test. */ status = tx_byte_release(pointer); #else - /* Set the flag that will make thread 3 abort the first request and make another request of a different size. This tests the memory size change path + /* Set the flag that will make thread 3 abort the first request and make another request of a different size. This tests the memory size change path in the byte release loop logic. */ threadx_byte_release_loop_test = 1; status = tx_byte_release(pointer); #endif - + /* Check status. */ if (status != TX_SUCCESS) { @@ -273,7 +273,7 @@ CHAR *pointer; test_control_return(1); } else - { + { /* Successful test. */ printf("SUCCESS!\n"); @@ -307,7 +307,7 @@ CHAR *pointer; /* Check for status. */ if (status != TX_SUCCESS) return; - + /* Let thread 0 run again. */ tx_thread_relinquish(); } @@ -339,7 +339,7 @@ CHAR *pointer; /* Check for status. */ if (status != TX_SUCCESS) return; - + /* Let thread 0 run again. */ tx_thread_relinquish(); } @@ -370,7 +370,7 @@ CHAR *pointer; threadx_byte_allocate_loop_test = 1; status = tx_byte_allocate(&pool_0, (VOID **) &pointer, 90, TX_WAIT_FOREVER); #endif - + /* Check for status. */ if (status != TX_SUCCESS) return; @@ -384,7 +384,7 @@ CHAR *pointer; /* Check for status. */ if (status != TX_SUCCESS) return; - + /* suspend this thread. */ tx_thread_suspend(&thread_3); } diff --git a/test/smp/regression/threadx_byte_memory_suspension_timeout_test.c b/test/smp/regression/threadx_byte_memory_suspension_timeout_test.c index ed122dab..5e94df97 100644 --- a/test/smp/regression/threadx_byte_memory_suspension_timeout_test.c +++ b/test/smp/regression/threadx_byte_memory_suspension_timeout_test.c @@ -44,8 +44,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -57,8 +57,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -71,8 +71,8 @@ CHAR *pointer; } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -110,7 +110,7 @@ CHAR *pointer; /* Inform user. */ printf("Running Byte Memory Suspension Timeout Test......................... "); - + /* Increment the thread counter. */ thread_0_counter++; @@ -126,7 +126,7 @@ CHAR *pointer; test_control_return(1); } - /* Sleep to allow the other thread to suspend and timeout on the memory + /* Sleep to allow the other thread to suspend and timeout on the memory pool once. */ tx_thread_sleep(64); @@ -140,7 +140,7 @@ CHAR *pointer; } else { - + /* Successful test. */ printf("SUCCESS!\n"); test_control_return(0); diff --git a/test/smp/regression/threadx_byte_memory_thread_contention_test.c b/test/smp/regression/threadx_byte_memory_thread_contention_test.c index 55f7f4f3..899ed269 100644 --- a/test/smp/regression/threadx_byte_memory_thread_contention_test.c +++ b/test/smp/regression/threadx_byte_memory_thread_contention_test.c @@ -1,6 +1,6 @@ /* This test is designed to test contention of two threads on a single memory byte pool. */ - + #include #include "tx_api.h" @@ -49,8 +49,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 1, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -62,8 +62,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 1, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -75,8 +75,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 1, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -91,7 +91,7 @@ CHAR *pointer; /* Create byte pool 0. */ status = tx_byte_pool_create(&pool_0, "pool 0", pointer, 108); pointer = pointer + 108; - + /* Save off the intial pool size. */ initial_pool_size = pool_0.tx_byte_pool_available; @@ -128,7 +128,7 @@ CHAR *pointer; { /* Allocate memory from the pool. This size will cause merge activity - because the search pointer will sit in this large block about half + because the search pointer will sit in this large block about half the time. */ status = tx_byte_allocate(&pool_0, (VOID **) &pointer, 60, TX_WAIT_FOREVER); @@ -158,7 +158,7 @@ CHAR *pointer; /* Check the time. */ if (tx_time_get() > 1280) - break; + break; /* Increment the thread counter. */ thread_0_counter++; @@ -166,7 +166,7 @@ CHAR *pointer; /* Set the done flag. */ test_done = TX_TRUE; - + /* Sleep to let the other threads finish up! */ tx_thread_sleep(2); @@ -215,7 +215,7 @@ CHAR *pointer; /* Check for status. */ if (status != TX_SUCCESS) return; - + /* Increment the thread counter. */ thread_1_counter++; } @@ -248,7 +248,7 @@ CHAR *pointer; /* Check for status. */ if (status != TX_SUCCESS) return; - + /* Increment the thread counter. */ thread_2_counter++; } diff --git a/test/smp/regression/threadx_byte_memory_thread_terminate_test.c b/test/smp/regression/threadx_byte_memory_thread_terminate_test.c index 29fec0c0..4805ba57 100644 --- a/test/smp/regression/threadx_byte_memory_thread_terminate_test.c +++ b/test/smp/regression/threadx_byte_memory_thread_terminate_test.c @@ -41,8 +41,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -54,8 +54,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -96,7 +96,7 @@ CHAR *pointer; /* Increment the thread counter. */ thread_0_counter++; - + /* Allocate memory from the pool. Only one block of this size will fit. */ status = tx_byte_allocate(&pool_0, (VOID **) &pointer, 60, TX_NO_WAIT); @@ -114,7 +114,7 @@ CHAR *pointer; /* Terminate the other thread. */ status = tx_thread_terminate(&thread_1); - + /* Check status. */ if (status != TX_SUCCESS) { @@ -147,7 +147,7 @@ CHAR *pointer; printf("ERROR #7\n"); test_control_return(1); } - + /* Successful test. */ printf("SUCCESS!\n"); test_control_return(0); diff --git a/test/smp/regression/threadx_event_flag_basic_test.c b/test/smp/regression/threadx_event_flag_basic_test.c index 9c19f9bd..3261f67f 100644 --- a/test/smp/regression/threadx_event_flag_basic_test.c +++ b/test/smp/regression/threadx_event_flag_basic_test.c @@ -75,14 +75,14 @@ ULONG actual_events; /* Determine if calling event flag create from initialization was successful. */ if (test_event_flags_from_init != TX_SUCCESS) { - + /* Error! */ error++; } /* Attempt to create an event flag group from a timer. */ status = tx_event_flags_create(&group_2, "group 2"); - + /* Check status. */ if (status != TX_CALLER_ERROR) { @@ -185,8 +185,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -198,8 +198,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -213,7 +213,7 @@ CHAR *pointer; /* Create event flag group 0 and 1. */ status = tx_event_flags_create(&group_0, "group 0"); - + /* Check status. */ if (status != TX_SUCCESS) { @@ -231,7 +231,7 @@ CHAR *pointer; printf("Running Event Flag Basic Test....................................... ERROR #4\n"); test_control_return(1); } - + /* Register the event set notify function. */ status = tx_event_flags_set_notify(&group_0, event_set_notify); @@ -278,7 +278,7 @@ CHAR *pointer; test_control_return(1); } #endif - + } @@ -300,11 +300,11 @@ ULONG actual_events; event_flag_memory.second = 0x55667788; event_flag_memory.next_to_last = 0x99aabbcc; event_flag_memory.last = 0xddeeff00; - + /* Create the event flag group. */ status = tx_event_flags_create(&event_flag_memory.event_flags, "group memory"); tx_event_flags_delete(&event_flag_memory.event_flags); - + /* Check for status. */ if ((status != TX_SUCCESS) || (event_flag_memory.first != 0x11223344) || @@ -312,7 +312,7 @@ ULONG actual_events; (event_flag_memory.next_to_last != 0x99aabbcc) || (event_flag_memory.last != 0xddeeff00)) { - + /* Event flag error. */ printf("ERROR #7\n"); test_control_return(1); @@ -324,7 +324,7 @@ ULONG actual_events; /* Try to create with a NULL pointer. */ status = tx_event_flags_create(TX_NULL, "group 0"); - + /* Check status. */ if (status != TX_GROUP_ERROR) { @@ -333,10 +333,10 @@ ULONG actual_events; printf("ERROR #8\n"); test_control_return(1); } - + /* Try to create with a bad size. */ status = _txe_event_flags_create(&group_3, "group 3", (sizeof(TX_EVENT_FLAGS_GROUP)+1)); - + /* Check status. */ if (status != TX_GROUP_ERROR) { @@ -345,10 +345,10 @@ ULONG actual_events; printf("ERROR #9\n"); test_control_return(1); } - + /* Try to create an already created group. */ status = tx_event_flags_create(&group_0, "group 0"); - + /* Check status. */ if (status != TX_GROUP_ERROR) { @@ -369,7 +369,7 @@ ULONG actual_events; printf("ERROR #11\n"); test_control_return(1); } - + /* Delete with a non-created pointer. */ group_2.tx_event_flags_group_id = 0; status = tx_event_flags_delete(&group_2); @@ -518,7 +518,7 @@ ULONG actual_events; printf("ERROR #23\n"); test_control_return(1); } - + /* Attempt to get events from an empty event flag group. AND CLEAR option. */ status = tx_event_flags_get(&group_0, 0x80008000, TX_AND_CLEAR, &actual_events, TX_NO_WAIT); @@ -604,7 +604,7 @@ ULONG actual_events; printf("ERROR #30\n"); test_control_return(1); } - + /* Attempt to get events from event flag group. AND CLEAR option. */ status = tx_event_flags_get(&group_0, 0x80008000, TX_AND_CLEAR, &actual_events, TX_NO_WAIT); @@ -691,7 +691,7 @@ ULONG actual_events; /* Test for error. */ if ((error) || (timer_executed != 1) || (isr_executed != 1)) { - + /* Block memory error. */ printf("ERROR #36\n"); test_control_return(1); @@ -737,7 +737,7 @@ static void thread_1_entry(ULONG thread_input) while(1) { - tx_thread_relinquish(); + tx_thread_relinquish(); } } diff --git a/test/smp/regression/threadx_event_flag_information_test.c b/test/smp/regression/threadx_event_flag_information_test.c index 1f03fdf3..d2404081 100644 --- a/test/smp/regression/threadx_event_flag_information_test.c +++ b/test/smp/regression/threadx_event_flag_information_test.c @@ -54,8 +54,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -69,7 +69,7 @@ CHAR *pointer; /* Create event flag group 0 and 1. */ status = tx_event_flags_create(&group_0, "group 0"); - + /* Check status. */ if (status != TX_SUCCESS) { @@ -87,10 +87,10 @@ CHAR *pointer; printf("Running Event Flag Information Test................................. ERROR #3\n"); test_control_return(1); } - + /* Register the event set notify function. */ status = tx_event_flags_set_notify(&group_0, event_set_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check status. */ @@ -162,7 +162,7 @@ ULONG timeouts; printf("ERROR #7\n"); test_control_return(1); } - + /* Attempt to get events from an empty event flag group. AND CLEAR option. */ status = tx_event_flags_get(&group_0, 0x80008000, TX_AND_CLEAR, &actual_events, TX_NO_WAIT); @@ -248,7 +248,7 @@ ULONG timeouts; printf("ERROR #14\n"); test_control_return(1); } - + /* Attempt to get events from event flag group. AND CLEAR option. */ status = tx_event_flags_get(&group_0, 0x80008000, TX_AND_CLEAR, &actual_events, TX_NO_WAIT); @@ -343,7 +343,7 @@ ULONG timeouts; /* Get information about the event flag group. */ status = tx_event_flags_info_get(&group_0, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_event_flags_info_get(&group_0, &name, ¤t_flags, &first_suspended, &suspended_count, &next_group); - + /* Check the status. */ if ((status != TX_SUCCESS) || (current_flags != group_0.tx_event_flags_group_current) || (first_suspended != TX_NULL) || (suspended_count != 0) || (next_group != &group_1)) { @@ -357,7 +357,7 @@ ULONG timeouts; /* Get performance information with NULL pointer. */ status = _tx_event_flags_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); - + /* Check the status. */ if (status != TX_PTR_ERROR) { @@ -370,9 +370,9 @@ ULONG timeouts; /* Get performance information on the event flag group. */ status = tx_event_flags_performance_info_get(&group_0, TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_event_flags_performance_info_get(&group_0, &sets, &gets, &suspensions, &timeouts); - + /* Check the status. */ - if ((status != TX_SUCCESS) || (sets != group_0.tx_event_flags_group_performance_set_count) || (gets != group_0.tx_event_flags_group__performance_get_count) || + if ((status != TX_SUCCESS) || (sets != group_0.tx_event_flags_group_performance_set_count) || (gets != group_0.tx_event_flags_group__performance_get_count) || (suspensions != group_0.tx_event_flags_group___performance_suspension_count) || (timeouts != group_0.tx_event_flags_group____performance_timeout_count)) { @@ -384,9 +384,9 @@ ULONG timeouts; /* Get system performance information on all event flags groups. */ status = tx_event_flags_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_event_flags_performance_system_info_get(&sets, &gets, &suspensions, &timeouts); - + /* Check the status. */ - if ((status != TX_SUCCESS) || (sets != _tx_event_flags_performance_set_count) || (gets != _tx_event_flags_performance_get_count) || + if ((status != TX_SUCCESS) || (sets != _tx_event_flags_performance_set_count) || (gets != _tx_event_flags_performance_get_count) || (suspensions != _tx_event_flags_performance_suspension_count) || (timeouts != _tx_event_flags_performance_timeout_count)) { diff --git a/test/smp/regression/threadx_event_flag_isr_set_clear_test.c b/test/smp/regression/threadx_event_flag_isr_set_clear_test.c index 394bd601..b1420d76 100644 --- a/test/smp/regression/threadx_event_flag_isr_set_clear_test.c +++ b/test/smp/regression/threadx_event_flag_isr_set_clear_test.c @@ -64,7 +64,7 @@ static volatile UINT miss_count = 0; condition_count++; } - /* + /* It is possible for this test to get into a resonance condition in which the ISR never occurs while preemption is disabled (especially if the ISR is installed in the periodic timer interrupt handler, which is @@ -88,10 +88,10 @@ static volatile UINT miss_count = 0; /* Setup some event flags just so we can clear them. */ status += tx_event_flags_set(&event_flags_0, 0x30000, TX_OR); - + /* Clear the same flags immediately. */ status += tx_event_flags_set(&event_flags_0, 0xFFFEFFFF, TX_AND); - + /* Clear the same flags immediately. */ status += tx_event_flags_set(&event_flags_0, 0xFFFDFFFC, TX_AND); @@ -101,11 +101,11 @@ static volatile UINT miss_count = 0; /* Get the events from an ISR. */ status = tx_event_flags_get(&event_flags_0, 0x30000, TX_OR, &actual, TX_NO_WAIT); - + /* Check to make sure this results in an error. */ if (status != TX_NO_EVENTS) return; - + /* Do a set and a get consume from an ISR. */ status = tx_event_flags_set(&event_flags_0, 0x000000C0, TX_OR); @@ -141,8 +141,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -154,8 +154,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -167,8 +167,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -182,7 +182,7 @@ CHAR *pointer; /* Create event flags group. */ status = tx_event_flags_create(&event_flags_0, "event_flags 0"); - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -201,7 +201,7 @@ CHAR *pointer; printf("Running Event Flag Set/Clear from ISR Test.......................... ERROR #5\n"); test_control_return(1); } - + /* Register the event set notify function. */ status = tx_event_flags_set_notify(&event_flags_0, event_set_notify); @@ -242,7 +242,7 @@ ULONG actual; printf("Running Event Flag Set/Clear from ISR Test.......................... "); /* Setup the test ISR. */ - test_isr_dispatch = test_isr; + test_isr_dispatch = test_isr; /* Loop to exploit the probability window inside tx_event_flags_set call. */ while (condition_count < 40) @@ -252,7 +252,7 @@ ULONG actual; status = tx_event_flags_get(&event_flags_0, 2, TX_OR_CLEAR, &actual, 4); /* Determine if we have an unexpected result. */ - if (status != TX_SUCCESS) + if (status != TX_SUCCESS) { /* Test error! */ @@ -279,7 +279,7 @@ ULONG actual; } /* Setup the test ISR. */ - test_isr_dispatch = TX_NULL; + test_isr_dispatch = TX_NULL; /* Let the other threads run once more... */ tx_thread_relinquish(); @@ -318,7 +318,7 @@ ULONG actual; status = tx_event_flags_get(&event_flags_0, 1, TX_OR_CLEAR, &actual, 4); /* Determine if we have an unexpected result. */ - if (status != TX_SUCCESS) + if (status != TX_SUCCESS) { break; diff --git a/test/smp/regression/threadx_event_flag_isr_wait_abort_test.c b/test/smp/regression/threadx_event_flag_isr_wait_abort_test.c index 1382ea29..95d3b5ab 100644 --- a/test/smp/regression/threadx_event_flag_isr_wait_abort_test.c +++ b/test/smp/regression/threadx_event_flag_isr_wait_abort_test.c @@ -63,7 +63,7 @@ static volatile UINT miss_count = 0; condition_count++; } - /* + /* It is possible for this test to get into a resonance condition in which the ISR never occurs while preemption is disabled (especially if the ISR is installed in the periodic timer interrupt handler, which is @@ -85,10 +85,10 @@ static volatile UINT miss_count = 0; /* Abort the threads 1 and 2. */ status += tx_thread_wait_abort(&thread_0); status += tx_thread_wait_abort(&thread_1); - + if (status == TX_SUCCESS) { - + event_flags_wait_abort_counter++; } } @@ -114,8 +114,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -127,8 +127,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -140,8 +140,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -155,7 +155,7 @@ CHAR *pointer; /* Create event flags group. */ status = tx_event_flags_create(&event_flags_0, "event_flags 0"); - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -174,10 +174,10 @@ CHAR *pointer; printf("Running Event Flag Wait Abort from ISR Test......................... ERROR #5\n"); test_control_return(1); } - + /* Register the event set notify function. */ status = tx_event_flags_set_notify(&event_flags_0, event_set_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check status. */ @@ -216,7 +216,7 @@ ULONG actual; printf("Running Event Flag Wait Abort from ISR Test......................... "); /* Setup the test ISR. */ - test_isr_dispatch = test_isr; + test_isr_dispatch = test_isr; /* Loop to exploit the probability window inside tx_event_flags_set call. */ while (condition_count < 40) @@ -226,7 +226,7 @@ ULONG actual; status = tx_event_flags_get(&event_flags_0, 2, TX_OR_CLEAR, &actual, 4); /* Determine if we have an unexpected result. */ - if (status != TX_WAIT_ABORTED) + if (status != TX_WAIT_ABORTED) { /* Test error! */ @@ -253,7 +253,7 @@ ULONG actual; } /* Setup the test ISR. */ - test_isr_dispatch = TX_NULL; + test_isr_dispatch = TX_NULL; /* Let the other threads run once more... */ tx_thread_relinquish(); @@ -292,7 +292,7 @@ ULONG actual; status = tx_event_flags_get(&event_flags_0, 1, TX_OR_CLEAR, &actual, 4); /* Determine if we have an unexpected result. */ - if (status != TX_WAIT_ABORTED) + if (status != TX_WAIT_ABORTED) { break; diff --git a/test/smp/regression/threadx_event_flag_single_thread_terminate_test.c b/test/smp/regression/threadx_event_flag_single_thread_terminate_test.c index a5db6e41..86675890 100644 --- a/test/smp/regression/threadx_event_flag_single_thread_terminate_test.c +++ b/test/smp/regression/threadx_event_flag_single_thread_terminate_test.c @@ -54,8 +54,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -67,8 +67,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -80,8 +80,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -106,7 +106,7 @@ CHAR *pointer; /* Register the event set notify function. */ status = tx_event_flags_set_notify(&group_0, event_set_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check status. */ @@ -160,7 +160,7 @@ UINT status; printf("ERROR #7\n"); test_control_return(1); } - + /* Now terminate thread 1. */ status = tx_thread_terminate(&thread_1); @@ -206,9 +206,9 @@ UINT status; test_control_return(1); } - /* At this point, thread 2 is suspended on the flags again. Or some flags that are + /* At this point, thread 2 is suspended on the flags again. Or some flags that are not needed. */ - + /* Set an event flag that is not needed. */ status = tx_event_flags_set(&group_0, 0x00000001, TX_OR); @@ -231,7 +231,7 @@ UINT status; tx_thread_sleep(5); /* Check status and run counters. */ - if ((status != TX_SUCCESS) || (thread_1_counter != 1) || (thread_2_counter != 3) || + if ((status != TX_SUCCESS) || (thread_1_counter != 1) || (thread_2_counter != 3) || (_tx_thread_preempt_disable)) { @@ -280,7 +280,7 @@ UINT status; /* Check status. */ if (status != TX_SUCCESS) { - thread_1_counter = 0; /* Make an error! */ + thread_1_counter = 0; /* Make an error! */ return; } } diff --git a/test/smp/regression/threadx_event_flag_suspension_consume_test.c b/test/smp/regression/threadx_event_flag_suspension_consume_test.c index b83a8123..aae8f1b9 100644 --- a/test/smp/regression/threadx_event_flag_suspension_consume_test.c +++ b/test/smp/regression/threadx_event_flag_suspension_consume_test.c @@ -55,8 +55,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -68,8 +68,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -81,8 +81,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -94,8 +94,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -120,7 +120,7 @@ CHAR *pointer; /* Register the event set notify function. */ status = tx_event_flags_set_notify(&group_0, event_set_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check status. */ diff --git a/test/smp/regression/threadx_event_flag_suspension_different_bits_consume_test.c b/test/smp/regression/threadx_event_flag_suspension_different_bits_consume_test.c index fa4a985a..595e60ed 100644 --- a/test/smp/regression/threadx_event_flag_suspension_different_bits_consume_test.c +++ b/test/smp/regression/threadx_event_flag_suspension_different_bits_consume_test.c @@ -51,8 +51,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -64,8 +64,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -78,8 +78,8 @@ CHAR *pointer; } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -101,10 +101,10 @@ CHAR *pointer; printf("Running Event Flag Suspension/Consumption Unique Bit Test........... ERROR #4\n"); test_control_return(1); } - + /* Register the event set notify function. */ status = tx_event_flags_set_notify(&group_0, event_set_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check status. */ @@ -140,7 +140,7 @@ UINT status; /* Inform user. */ printf("Running Event Flag Suspension/Consumption Unique Bit Test........... "); - + /* Increment run counter. */ thread_0_counter++; diff --git a/test/smp/regression/threadx_event_flag_suspension_different_bits_test.c b/test/smp/regression/threadx_event_flag_suspension_different_bits_test.c index 92505744..f9e43cad 100644 --- a/test/smp/regression/threadx_event_flag_suspension_different_bits_test.c +++ b/test/smp/regression/threadx_event_flag_suspension_different_bits_test.c @@ -51,8 +51,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -64,8 +64,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -78,8 +78,8 @@ CHAR *pointer; } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -104,7 +104,7 @@ CHAR *pointer; /* Register the event set notify function. */ status = tx_event_flags_set_notify(&group_0, event_set_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check status. */ @@ -140,7 +140,7 @@ UINT status; /* Inform user. */ printf("Running Event Flag Suspension Unique Bit Test....................... "); - + /* Increment run counter. */ thread_0_counter++; diff --git a/test/smp/regression/threadx_event_flag_suspension_test.c b/test/smp/regression/threadx_event_flag_suspension_test.c index 3587fadd..915e33db 100644 --- a/test/smp/regression/threadx_event_flag_suspension_test.c +++ b/test/smp/regression/threadx_event_flag_suspension_test.c @@ -58,8 +58,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -71,8 +71,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -84,8 +84,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -97,8 +97,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -110,8 +110,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -136,7 +136,7 @@ CHAR *pointer; /* Register the event set notify function. */ status = tx_event_flags_set_notify(&group_0, event_set_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check status. */ @@ -223,11 +223,11 @@ int i; /* Resume thread 4 so it can suspend on the event flag group too. */ status += tx_thread_resume(&thread_4); - + /* Determine if there was an error. */ if ((status != TX_SUCCESS) || (thread_4_counter != 1)) { - + /* Event flag error. */ printf("ERROR #11\n"); test_control_return(1); @@ -239,7 +239,7 @@ int i; /* Determine if there was an error. */ if ((status != TX_SUCCESS) || (thread_4_counter != 2)) { - + /* Event flag error. */ printf("ERROR #12\n"); test_control_return(1); diff --git a/test/smp/regression/threadx_event_flag_suspension_timeout_test.c b/test/smp/regression/threadx_event_flag_suspension_timeout_test.c index 2fed61c0..2772d391 100644 --- a/test/smp/regression/threadx_event_flag_suspension_timeout_test.c +++ b/test/smp/regression/threadx_event_flag_suspension_timeout_test.c @@ -54,8 +54,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -67,12 +67,12 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -84,8 +84,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -110,7 +110,7 @@ CHAR *pointer; /* Register the event set notify function. */ status = tx_event_flags_set_notify(&group_0, event_set_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check status. */ @@ -140,7 +140,7 @@ CHAR *pointer; static void thread_0_entry(ULONG thread_input) { - + ULONG actual_events; UINT status; @@ -200,7 +200,7 @@ UINT status; ULONG actual_events; - + /* Wait for event flags. */ while(1) { diff --git a/test/smp/regression/threadx_event_flag_thread_terminate_test.c b/test/smp/regression/threadx_event_flag_thread_terminate_test.c index eecb76e6..166711f5 100644 --- a/test/smp/regression/threadx_event_flag_thread_terminate_test.c +++ b/test/smp/regression/threadx_event_flag_thread_terminate_test.c @@ -52,8 +52,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -65,8 +65,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -78,8 +78,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -101,7 +101,7 @@ CHAR *pointer; printf("Running Event Flag Thread Terminate Test............................ ERROR #4\n"); test_control_return(1); } - + /* Register the event set notify function. */ status = tx_event_flags_set_notify(&group_0, event_set_notify); diff --git a/test/smp/regression/threadx_initialize_kernel_setup_test.c b/test/smp/regression/threadx_initialize_kernel_setup_test.c index fbdee6fe..a1172ded 100644 --- a/test/smp/regression/threadx_initialize_kernel_setup_test.c +++ b/test/smp/regression/threadx_initialize_kernel_setup_test.c @@ -10,7 +10,7 @@ TEST_FLAG test_forced_mutex_timeout; TEST_FLAG threadx_mutex_suspension_put_test; TEST_FLAG threadx_mutex_suspension_priority_test; TEST_FLAG threadx_byte_allocate_loop_test; -TEST_FLAG test_initialize_flag; +TEST_FLAG test_initialize_flag; TEST_FLAG threadx_byte_release_loop_test; TEST_FLAG test_stack_analyze_flag; @@ -29,7 +29,7 @@ UINT test_event_flags_from_init; UINT test_byte_pool_create_init; UINT test_block_pool_create_init; UINT test_timer_create_init; -UINT mutex_priority_change_extension_selection; +UINT mutex_priority_change_extension_selection; UINT priority_change_extension_selection; diff --git a/test/smp/regression/threadx_interrupt_control_test.c b/test/smp/regression/threadx_interrupt_control_test.c index d58ceba3..c573c098 100644 --- a/test/smp/regression/threadx_interrupt_control_test.c +++ b/test/smp/regression/threadx_interrupt_control_test.c @@ -1,4 +1,4 @@ -/* This test is designed to test the interrupt control service call avaialbe to the +/* This test is designed to test the interrupt control service call avaialbe to the application. */ #include @@ -36,8 +36,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; diff --git a/test/smp/regression/threadx_mutex_basic_test.c b/test/smp/regression/threadx_mutex_basic_test.c index 2e784961..419813d3 100644 --- a/test/smp/regression/threadx_mutex_basic_test.c +++ b/test/smp/regression/threadx_mutex_basic_test.c @@ -77,7 +77,7 @@ UINT status; /* Attempt to create a mutex from a timer. */ status = tx_mutex_create(&mutex_4, "mutex 4", TX_NO_INHERIT); - + /* Check status. */ if (status != TX_CALLER_ERROR) { @@ -96,7 +96,7 @@ UINT status; /* Error! */ error++; } - + /* Attempt to get from mutex from a timer with suspension. */ status = tx_mutex_get(&mutex_2, 100); @@ -124,7 +124,7 @@ UINT status; /* Attempt to create a mutex from an ISR. */ status = tx_mutex_create(&mutex_4, "mutex 4", TX_NO_INHERIT); - + /* Check status. */ if (status != TX_CALLER_ERROR) { @@ -201,29 +201,29 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_3, "thread 3", thread_3_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_3, "thread 3", thread_3_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_4, "thread 4", thread_4_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_4, "thread 4", thread_4_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -309,11 +309,11 @@ UINT status; mutex_memory.second = 0x55667788; mutex_memory.next_to_last = 0x99aabbcc; mutex_memory.last = 0xddeeff00; - + /* Create the semaphore. */ status = tx_mutex_create(&mutex_memory.mutex, "mutex memory", TX_INHERIT); tx_mutex_delete(&mutex_memory.mutex); - + /* Check for status. */ if ((status != TX_SUCCESS) || (mutex_memory.first != 0x11223344) || @@ -326,7 +326,7 @@ UINT status; printf("ERROR #6\n"); test_control_return(1); } - + /* Increment thread 0 counter. */ thread_0_counter++; @@ -334,7 +334,7 @@ UINT status; /* Attempt to create a mutex with a NULL pointer. */ status = tx_mutex_create(TX_NULL, "mutex 2", TX_INHERIT); - + /* Check status. */ if (status != TX_MUTEX_ERROR) { @@ -346,7 +346,7 @@ UINT status; /* Attempt to create a mutex with a bad size. */ status = _txe_mutex_create(&mutex_5, "mutex 5", TX_INHERIT, (sizeof(TX_MUTEX)+1)); - + /* Check status. */ if (status != TX_MUTEX_ERROR) { @@ -358,7 +358,7 @@ UINT status; /* Attempt to create a mutex that has already been created. */ status = tx_mutex_create(&mutex_2, "mutex 2", TX_INHERIT); - + /* Check status. */ if (status != TX_MUTEX_ERROR) { @@ -370,7 +370,7 @@ UINT status; /* Attempt to create a mutex with a bad inheritance option. */ status = tx_mutex_create(&mutex_4, "mutex 4", 14); - + /* Check status. */ if (status != TX_INHERIT_ERROR) { @@ -509,7 +509,7 @@ UINT status; /* Attempt to get the mutex. Should be unsuccessful. */ status = tx_mutex_get(&mutex_1, TX_NO_WAIT); - + /* Check status. */ if (status != TX_NOT_AVAILABLE) { @@ -535,7 +535,7 @@ UINT status; } status = tx_mutex_delete(&mutex_1); - + /* Check status. */ if (status != TX_SUCCESS) { @@ -592,7 +592,7 @@ UINT status; /* Test for error. */ if ((error) || (timer_executed != 1) || (isr_executed != 1)) { - + /* Block memory error. */ printf("ERROR #26\n"); test_control_return(1); @@ -603,7 +603,7 @@ UINT status; /* Release mutex multiple times. */ status = tx_mutex_put(&mutex_2); status += tx_mutex_put(&mutex_2); - + /* Check status. */ if (status != TX_NOT_OWNED) { @@ -624,7 +624,7 @@ UINT status; printf("ERROR #28\n"); test_control_return(1); } - + /* Delete mutex. */ status = tx_mutex_delete(&mutex_2); @@ -639,14 +639,14 @@ UINT status; /* Get mutex 8. */ status = tx_mutex_get(&mutex_8, TX_WAIT_FOREVER); - + /* Start thread 3 and 4. */ status += tx_thread_resume(&thread_3); status += tx_thread_resume(&thread_4); - + /* Sleep to let thread 3 suspend on the mutex. */ tx_thread_sleep(2); - + /* Now, put the mutex to give it to thread 3. */ status += tx_mutex_put(&mutex_8); @@ -660,7 +660,7 @@ UINT status; } status = tx_mutex_delete(&mutex_3); - + /* Check status. */ if (status != TX_SUCCESS) { @@ -713,14 +713,14 @@ UINT status; test_control_return(1); } - /* Create and obtain a couple mutexes so the thread completion can release them. */ + /* Create and obtain a couple mutexes so the thread completion can release them. */ status = tx_mutex_create(&mutex_6, "mutex 6", TX_NO_INHERIT); status += tx_mutex_create(&mutex_7, "mutex 7", TX_NO_INHERIT); status += tx_mutex_get(&mutex_6, TX_NO_WAIT); status += tx_mutex_get(&mutex_7, TX_NO_WAIT); status += tx_mutex_get(&mutex_6, TX_NO_WAIT); status += tx_mutex_get(&mutex_7, TX_NO_WAIT); - + /* Check status. */ if (status != TX_SUCCESS) { @@ -738,7 +738,7 @@ static void thread_2_entry(ULONG thread_input) while(1) { - tx_thread_relinquish(); + tx_thread_relinquish(); } } @@ -748,7 +748,7 @@ static void thread_3_entry(ULONG thread_input) while(1) { - + tx_mutex_get(&mutex_8, TX_WAIT_FOREVER); tx_mutex_put(&mutex_8); } @@ -760,7 +760,7 @@ static void thread_4_entry(ULONG thread_input) while(1) { - + tx_mutex_get(&mutex_8, TX_WAIT_FOREVER); tx_mutex_put(&mutex_8); } diff --git a/test/smp/regression/threadx_mutex_delete_test.c b/test/smp/regression/threadx_mutex_delete_test.c index 28676f4b..af501488 100644 --- a/test/smp/regression/threadx_mutex_delete_test.c +++ b/test/smp/regression/threadx_mutex_delete_test.c @@ -47,8 +47,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -60,8 +60,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -73,8 +73,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; diff --git a/test/smp/regression/threadx_mutex_information_test.c b/test/smp/regression/threadx_mutex_information_test.c index e95c16c6..55503002 100644 --- a/test/smp/regression/threadx_mutex_information_test.c +++ b/test/smp/regression/threadx_mutex_information_test.c @@ -50,14 +50,14 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -196,7 +196,7 @@ ULONG inheritances; /* Attempt to get the mutex. Should be unsuccessful. */ status = tx_mutex_get(&mutex_1, TX_NO_WAIT); - + /* Check status. */ if (status != TX_NOT_AVAILABLE) { @@ -222,7 +222,7 @@ ULONG inheritances; } status = tx_mutex_delete(&mutex_1); - + /* Check status. */ if (status != TX_SUCCESS) { @@ -289,7 +289,7 @@ ULONG inheritances; status += tx_mutex_info_get(&mutex_2, &name, &count, &owner, &first_suspended, &suspended_count, &next_mutex); /* Check status. */ - if ((status != TX_SUCCESS) || (count != mutex_2.tx_mutex_ownership_count) || (owner != mutex_2.tx_mutex_owner) || + if ((status != TX_SUCCESS) || (count != mutex_2.tx_mutex_ownership_count) || (owner != mutex_2.tx_mutex_owner) || (first_suspended != mutex_2.tx_mutex_suspension_list) || (suspended_count != mutex_2.tx_mutex_suspended_count) || (next_mutex != mutex_2.tx_mutex_created_next)) { @@ -314,7 +314,7 @@ ULONG inheritances; /* Now get the performance inforamtion. */ status = tx_mutex_performance_info_get(&mutex_2, &puts, &gets, &suspensions, &timeouts, &inversions, &inheritances); - + /* Check status. */ if ((status != TX_SUCCESS) || (puts != mutex_2.tx_mutex_performance_put_count) || (gets != mutex_2.tx_mutex_performance_get_count) || (suspensions != mutex_2.tx_mutex_performance_suspension_count) || (timeouts != mutex_2.tx_mutex_performance_timeout_count) || @@ -325,10 +325,10 @@ ULONG inheritances; printf("ERROR #19\n"); test_control_return(1); } - + /* Now get the system performance inforamtion. */ status = tx_mutex_performance_system_info_get(&puts, &gets, &suspensions, &timeouts, &inversions, &inheritances); - + /* Check status. */ if ((status != TX_SUCCESS) || (puts != _tx_mutex_performance_put_count) || (gets != _tx_mutex_performance_get_count) || (suspensions != _tx_mutex_performance_suspension_count) || (timeouts != _tx_mutex_performance_timeout_count) || @@ -537,7 +537,7 @@ ULONG inheritances; } status = tx_mutex_delete(&mutex_3); - + /* Check status. */ if (status != TX_SUCCESS) { diff --git a/test/smp/regression/threadx_mutex_nested_priority_inheritance_test.c b/test/smp/regression/threadx_mutex_nested_priority_inheritance_test.c index 7397b4e2..1439ca85 100644 --- a/test/smp/regression/threadx_mutex_nested_priority_inheritance_test.c +++ b/test/smp/regression/threadx_mutex_nested_priority_inheritance_test.c @@ -9,7 +9,7 @@ /* Define the ThreadX object control blocks... */ static TX_THREAD thread_0; -#ifndef TX_DISABLE_PREEMPTION_THRESHOLD +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD static TX_THREAD thread_1; static TX_THREAD thread_2; static TX_THREAD thread_3; @@ -37,7 +37,7 @@ static ULONG thread_6_counter; /* Define thread prototypes. */ static void thread_0_entry(ULONG thread_input); -#ifndef TX_DISABLE_PREEMPTION_THRESHOLD +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD static void thread_1_entry(ULONG thread_input); static void thread_2_entry(ULONG thread_input); static void thread_3_entry(ULONG thread_input); @@ -66,8 +66,8 @@ UINT status; pointer = (CHAR *) first_unused_memory; /* Create thread. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 16, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; @@ -79,11 +79,11 @@ UINT status; test_control_return(1); } -#ifndef TX_DISABLE_PREEMPTION_THRESHOLD - +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD + /* Create thread. */ - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + DEMO_STACK_SIZE; @@ -96,8 +96,8 @@ UINT status; } /* Create thread. */ - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + DEMO_STACK_SIZE; @@ -110,8 +110,8 @@ UINT status; } /* Create thread. */ - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, DEMO_STACK_SIZE, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, DEMO_STACK_SIZE, 30, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; @@ -124,8 +124,8 @@ UINT status; } /* Create thread. */ - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, DEMO_STACK_SIZE, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + DEMO_STACK_SIZE; @@ -138,8 +138,8 @@ UINT status; } /* Create thread. */ - status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 2, 2, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + DEMO_STACK_SIZE; @@ -152,8 +152,8 @@ UINT status; } /* Create thread. */ - status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, - pointer, DEMO_STACK_SIZE, + status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, + pointer, DEMO_STACK_SIZE, 30, 30, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + DEMO_STACK_SIZE; @@ -188,7 +188,7 @@ UINT status; static void thread_0_entry(ULONG thread_input) { -#ifdef TX_DISABLE_PREEMPTION_THRESHOLD +#ifdef TX_DISABLE_PREEMPTION_THRESHOLD /* Preemption threshold is not enabled, skip this test. */ @@ -196,8 +196,8 @@ static void thread_0_entry(ULONG thread_input) printf("Running Mutex Nested Priority Inheritance Test...................... SUCCESS!\n"); test_control_return(0); -#else - +#else + UINT test_case = 0; UINT loop_count = 0; UINT priority; @@ -238,7 +238,7 @@ UINT status; test_control_return(1); } - /* Release the mutexes... Depending on the order they are released should dictate + /* Release the mutexes... Depending on the order they are released should dictate the thread's returned to priority. */ if (test_case == 0) { @@ -267,7 +267,7 @@ UINT status; } tx_mutex_put(&mutex_0); - + /* No change. */ if (thread_0.tx_thread_priority != 15) { @@ -281,7 +281,7 @@ UINT status; { priority = thread_0.tx_thread_priority; - tx_mutex_put(&mutex_0); + tx_mutex_put(&mutex_0); /* Should have no change in priority since nothing was inherited for this mutex. */ if (thread_0.tx_thread_priority != priority) @@ -292,7 +292,7 @@ UINT status; test_control_return(4); } - tx_mutex_put(&mutex_1); + tx_mutex_put(&mutex_1); /* Should not do anything since mutex 2 elevated to a higher priority. */ if (thread_0.tx_thread_priority != priority) @@ -303,7 +303,7 @@ UINT status; test_control_return(5); } - tx_mutex_put(&mutex_2); + tx_mutex_put(&mutex_2); /* Should go back to priority 15. */ if (thread_0.tx_thread_priority != 15) @@ -317,7 +317,7 @@ UINT status; else if (test_case == 2) { - tx_mutex_put(&mutex_2); + tx_mutex_put(&mutex_2); /* Should go back to priority 8. */ if (thread_0.tx_thread_priority != 8) @@ -328,7 +328,7 @@ UINT status; test_control_return(7); } - tx_mutex_put(&mutex_0); + tx_mutex_put(&mutex_0); /* Should not do anything. */ if (thread_0.tx_thread_priority != 8) @@ -339,7 +339,7 @@ UINT status; test_control_return(8); } - tx_mutex_put(&mutex_1); + tx_mutex_put(&mutex_1); /* Should go back to priority 15. */ if (thread_0.tx_thread_priority != 15) @@ -354,7 +354,7 @@ UINT status; { priority = thread_0.tx_thread_priority; - tx_mutex_put(&mutex_1); + tx_mutex_put(&mutex_1); /* Should not do anything since mutex 2 is still owned. */ if (thread_0.tx_thread_priority != priority) @@ -366,7 +366,7 @@ UINT status; } tx_mutex_put(&mutex_0); - + /* Should not do anything. */ if (thread_0.tx_thread_priority != priority) { @@ -376,7 +376,7 @@ UINT status; test_control_return(11); } - tx_mutex_put(&mutex_2); + tx_mutex_put(&mutex_2); /* Should finally go back to priority 15. */ if (thread_0.tx_thread_priority != 15) @@ -391,7 +391,7 @@ UINT status; { priority = thread_0.tx_thread_priority; - tx_mutex_put(&mutex_1); + tx_mutex_put(&mutex_1); /* Should not do anything since mutex 2 is still owned. */ if (thread_0.tx_thread_priority != priority) @@ -402,7 +402,7 @@ UINT status; test_control_return(13); } - tx_mutex_put(&mutex_2); + tx_mutex_put(&mutex_2); /* Should reurn us back to priority 15. */ if (thread_0.tx_thread_priority != 15) @@ -413,7 +413,7 @@ UINT status; test_control_return(14); } - tx_mutex_put(&mutex_0); + tx_mutex_put(&mutex_0); /* Should not do anything. */ if (thread_0.tx_thread_priority != 15) @@ -428,7 +428,7 @@ UINT status; { priority = thread_0.tx_thread_priority; - tx_mutex_put(&mutex_0); + tx_mutex_put(&mutex_0); /* Should not do anything since mutex 2 is still owned. */ if (thread_0.tx_thread_priority != priority) @@ -439,7 +439,7 @@ UINT status; test_control_return(16); } - tx_mutex_put(&mutex_2); + tx_mutex_put(&mutex_2); /* Should reurn us back to priority 8. */ if (thread_0.tx_thread_priority != 8) @@ -451,7 +451,7 @@ UINT status; } tx_mutex_put(&mutex_1); - + /* Should return us back to priority 15. */ if (thread_0.tx_thread_priority != 15) { @@ -470,60 +470,60 @@ UINT status; /* Check for thread 3 running... this should not happen! */ if (thread_3_counter != 50) { - + printf("ERROR #25\n"); test_control_return(19); } /* At this point, mutex 3 owned by this thread. */ - + /* Resume thread 6, lowest priority thread. */ status = tx_thread_resume(&thread_6); - + /* Check for an error. */ if ((status != TX_SUCCESS) || (thread_0.tx_thread_priority != 15) || (thread_6_counter != 0)) { - + printf("ERROR #27\n"); test_control_return(19); } - + /* Now resume thread 4. */ status = tx_thread_resume(&thread_4); - + /* Check for an error. */ if ((status != TX_SUCCESS) || (thread_0.tx_thread_priority != 4) || (thread_6_counter != 0)) { - + printf("ERROR #28\n"); test_control_return(19); } - + /* Now resume thread 5. */ status = tx_thread_resume(&thread_5); - + /* Check for an error. */ if ((status != TX_SUCCESS) || (thread_0.tx_thread_priority != 2) || (thread_6_counter != 0)) { - + printf("ERROR #29\n"); test_control_return(19); } - + /* Sleep to let thread 6 run, which is lower priority. */ tx_thread_sleep(1); - + /* Now release the mutex. */ status = tx_mutex_put(&mutex_3); /* Check for an error. */ if ((status != TX_SUCCESS) || (thread_0.tx_thread_priority != 15) || (thread_6_counter != 0) || (thread_4_counter != 1) || (thread_5_counter != 1)) { - + printf("ERROR #30\n"); test_control_return(19); } - + /* Sleep to let thread 6 run and release the mutex. */ tx_thread_sleep(2); @@ -534,7 +534,7 @@ UINT status; #endif } -#ifndef TX_DISABLE_PREEMPTION_THRESHOLD +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD static void thread_1_entry(ULONG thread_input) { @@ -551,8 +551,8 @@ UINT old_threshold; /* Update the thread priority and thread preemption-threshold of thread 0. */ tx_thread_priority_change(&thread_0, 15, &old_priority); - tx_thread_preemption_change(&thread_0, 14, &old_threshold); - + tx_thread_preemption_change(&thread_0, 14, &old_threshold); + /* Get mutex. */ tx_mutex_get(&mutex_1, TX_WAIT_FOREVER); tx_mutex_put(&mutex_1); @@ -564,8 +564,8 @@ UINT old_threshold; /* Update the thread priority and thread preemption-threshold of thread 0. */ tx_thread_priority_change(&thread_0, 15, &old_priority); - tx_thread_preemption_change(&thread_0, 8, &old_threshold); - + tx_thread_preemption_change(&thread_0, 8, &old_threshold); + /* Get mutex. */ tx_mutex_get(&mutex_1, TX_WAIT_FOREVER); tx_mutex_put(&mutex_1); @@ -638,7 +638,7 @@ static void thread_4_entry(ULONG thread_input) while(1) { - + /* Get priority inherit mutex. */ tx_mutex_get(&mutex_3, TX_WAIT_FOREVER); diff --git a/test/smp/regression/threadx_mutex_no_preemption_test.c b/test/smp/regression/threadx_mutex_no_preemption_test.c index c26c3651..3cc21b62 100644 --- a/test/smp/regression/threadx_mutex_no_preemption_test.c +++ b/test/smp/regression/threadx_mutex_no_preemption_test.c @@ -43,8 +43,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -56,8 +56,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; diff --git a/test/smp/regression/threadx_mutex_preemption_test.c b/test/smp/regression/threadx_mutex_preemption_test.c index 238dda03..495ae13c 100644 --- a/test/smp/regression/threadx_mutex_preemption_test.c +++ b/test/smp/regression/threadx_mutex_preemption_test.c @@ -43,8 +43,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -56,8 +56,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; diff --git a/test/smp/regression/threadx_mutex_priority_inheritance_test.c b/test/smp/regression/threadx_mutex_priority_inheritance_test.c index 7a82206f..87cc334c 100644 --- a/test/smp/regression/threadx_mutex_priority_inheritance_test.c +++ b/test/smp/regression/threadx_mutex_priority_inheritance_test.c @@ -1,4 +1,4 @@ -/* This test is designed to test the mutex suspension and priority inheritance with another +/* This test is designed to test the mutex suspension and priority inheritance with another thread resuming the higher priority thread by doing a mutex put. Higher-priority thread should preempt. */ #include @@ -74,16 +74,16 @@ CHAR *pointer; /* Test for an error creating/using a mutex from initialization. */ if (test_mutex_from_init != TX_SUCCESS) { - + printf("Running Mutex Priority Inheritance Test............................. ERROR #0\n"); test_control_return(1); - } + } /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -95,8 +95,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -108,8 +108,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 14, 14, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -123,8 +123,8 @@ CHAR *pointer; /* Create a high-priority thread that will get all the priority inheritance mutexes and return from it's entry function in order to test the auto delete feature. */ - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 10, 10, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -137,8 +137,8 @@ CHAR *pointer; } /* Create a higher-priority thread that is used to get thread 4 into a priority inheritance state. */ - status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, TEST_STACK_SIZE_PRINTF, 8, 8, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -152,8 +152,8 @@ CHAR *pointer; /* Create a higher-priority thread that is used to suspend on priority inheritance mutex 3. */ - status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, + pointer, TEST_STACK_SIZE_PRINTF, 6, 6, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -167,8 +167,8 @@ CHAR *pointer; /* Create a higher-priority thread that is used to suspend on priority inheritance mutex 3. */ - status = tx_thread_create(&thread_7, "thread 7", thread_7_entry, 7, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_7, "thread 7", thread_7_entry, 7, + pointer, TEST_STACK_SIZE_PRINTF, 7, 7, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -246,7 +246,7 @@ UINT status; /* Resume thread 4 to test the automatic release of the mutexes. */ tx_thread_resume(&thread_4); - + /* Determine if thread 4 was able to get the mutexes before completion... and have its original priority restored after the priority inheritance. */ if ((thread_4_counter != 1) || (thread_5_counter != 1) || (thread_4.tx_thread_priority != 10) || @@ -274,10 +274,10 @@ UINT status; printf("ERROR #13\n"); test_control_return(1); } - + /* Release mutex 2 to be compatible with original test. */ tx_mutex_put(&mutex_2); - + /* Now resume the higher priority thread to cause suspension. */ tx_thread_resume(&thread_1); @@ -314,8 +314,8 @@ UINT status; printf("ERROR #16\n"); test_control_return(1); } - - /* Now sleep for 20 ticks in order to test the priority inheritance change of a + + /* Now sleep for 20 ticks in order to test the priority inheritance change of a non-ready thread. */ tx_thread_sleep(20); @@ -330,10 +330,10 @@ UINT status; /* Resume thread 2 in order to get two threads suspended on the mutex. */ tx_thread_resume(&thread_2); - + /* Now do a mutex put to release both threads suspended on this mutex. */ status = tx_mutex_put(&mutex_0); - + /* The other thread should now be suspended on the mutex. */ if ((status != TX_SUCCESS) || (thread_1_counter != 4) || (thread_2_counter != 2) || (thread_0.tx_thread_priority != 16)) { @@ -342,7 +342,7 @@ UINT status; printf("ERROR #18\n"); test_control_return(1); } - + /* At this point, get the mutex again. */ status = tx_mutex_get(&mutex_0, TX_NO_WAIT); @@ -354,7 +354,7 @@ UINT status; printf("ERROR #19\n"); test_control_return(1); } - + /* Abort the sleep. */ tx_thread_wait_abort(&thread_1); tx_thread_wait_abort(&thread_2); @@ -362,10 +362,10 @@ UINT status; /* Now both threads are suspended again on mutex... and then terminate them. */ tx_thread_terminate(&thread_1); tx_thread_terminate(&thread_2); - + /* Now do a mutex put to release both threads suspended on this mutex. */ status = tx_mutex_put(&mutex_0); - + /* The other thread should now be suspended on the mutex. */ if ((status != TX_SUCCESS) || (thread_1_counter != 5) || (thread_2_counter != 3) || (thread_0.tx_thread_priority != 16)) { @@ -376,21 +376,21 @@ UINT status; } /* Now test the timeout on the suspension list of a priority inheritance mutex. */ - + /* First, obtain priority inheritance mutex 3. */ status = tx_mutex_get(&mutex_3, TX_WAIT_FOREVER); - + /* Next resume threads 6 and 7 so they will block on trying to get this mutex forever. */ status += tx_thread_resume(&thread_7); status += tx_thread_resume(&thread_6); - + /* Now set the flag which will cause the last thread in the suspension list to timeout (abort) resulting in a NULL suspension list and covering that branch condition in tx_mutex_put */ test_forced_mutex_timeout = 1; - + /* Perform a mutex put to release the mutex. */ status += tx_mutex_put(&mutex_3); - + /* Now check for errors. */ #ifndef TX_MISRA_ENABLE #ifndef TX_MANUAL_TEST @@ -404,9 +404,9 @@ UINT status; #endif #else if ((status != TX_SUCCESS) || (thread_6_counter != 1)) -#endif +#endif { - + /* Mutex error. */ printf("ERROR #21\n"); test_control_return(1); @@ -429,7 +429,7 @@ UINT status; while(1) { - + /* Increment thread run counter. */ thread_1_counter++; @@ -440,9 +440,9 @@ UINT status; /* Did we get the right status? */ if (status == TX_SUCCESS) thread_1_counter++; - + /* Sleep for 10 ticks... to delay. */ - tx_thread_sleep(10); + tx_thread_sleep(10); } } @@ -458,7 +458,7 @@ UINT status; while(1) { - + /* Increment thread run counter. */ thread_2_counter++; @@ -469,9 +469,9 @@ UINT status; /* Did we get the right status? */ if (status == TX_SUCCESS) thread_2_counter++; - + /* Sleep for 10 ticks... to delay. */ - tx_thread_sleep(10); + tx_thread_sleep(10); } } @@ -482,7 +482,7 @@ static void thread_4_entry(ULONG thread_input) UINT status; UINT old_priority; - + /* Get mutex to cause additional ownership linked-list processing. */ status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); status += tx_mutex_get(&mutex_1, TX_WAIT_FOREVER); @@ -493,7 +493,7 @@ UINT old_priority; /* Resume thread 5 to get into priority inheritance. */ tx_thread_resume(&thread_5); - /* Determine if all the mutex gets were successful... and we have + /* Determine if all the mutex gets were successful... and we have inherited priority 8. */ if ((status == TX_SUCCESS) && (thread_4.tx_thread_priority == 8)) { @@ -501,10 +501,10 @@ UINT old_priority; /* Yes, increment the thread counter. */ thread_4_counter++; } - + /* Now, attempt to manually set this thread's priority to the same priority. */ status = tx_thread_priority_change(&thread_4, 8, &old_priority); - + /* Determine if there is an error. */ if ((status != TX_SUCCESS) || (thread_4.tx_thread_user_priority != 8) || (old_priority != 10)) { @@ -515,7 +515,7 @@ UINT old_priority; /* Now attempt to manually set the same thread priority. */ status = tx_thread_priority_change(&thread_4, 8, &old_priority); - + /* Determine if there is an error. */ if ((status != TX_SUCCESS) || (thread_4.tx_thread_user_priority != 8) || (old_priority != 8)) { @@ -523,10 +523,10 @@ UINT old_priority; /* Clear the counter, which will signal an error to the thread above. */ thread_4_counter = 0; } - + /* Now restore the original user priority of 10. */ status = tx_thread_priority_change(&thread_4, 10, &old_priority); - + /* Determine if there is an error. */ if ((status != TX_SUCCESS) || (thread_4.tx_thread_user_priority != 10) || (old_priority != 8)) { @@ -535,7 +535,7 @@ UINT old_priority; thread_4_counter = 0; } - /* Now fall through and make sure the mutex cleanup function + /* Now fall through and make sure the mutex cleanup function releases all the mutexes. */ } @@ -545,7 +545,7 @@ static void thread_5_entry(ULONG thread_input) UINT status; - + /* Get mutex to cause priority inheritance in thread 4. */ status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); @@ -557,7 +557,7 @@ UINT status; thread_5_counter++; } - /* Now fall through and make sure the mutex cleanup function + /* Now fall through and make sure the mutex cleanup function releases all the mutexes. */ } @@ -567,7 +567,7 @@ static void thread_6_entry(ULONG thread_input) UINT status; - + /* Get mutex to cause priority inheritance in thread 0. */ status = tx_mutex_get(&mutex_3, TX_WAIT_FOREVER); @@ -579,7 +579,7 @@ UINT status; thread_6_counter++; } - /* Now fall through and make sure the mutex cleanup function + /* Now fall through and make sure the mutex cleanup function releases all the mutexes. */ } @@ -589,7 +589,7 @@ static void thread_7_entry(ULONG thread_input) UINT status; - + /* Get mutex to cause priority inheritance in thread 0. */ status = tx_mutex_get(&mutex_3, TX_WAIT_FOREVER); @@ -601,7 +601,7 @@ UINT status; thread_7_counter++; } - /* Now fall through and make sure the mutex cleanup function + /* Now fall through and make sure the mutex cleanup function releases all the mutexes. */ } diff --git a/test/smp/regression/threadx_mutex_proritize_test.c b/test/smp/regression/threadx_mutex_proritize_test.c index 4e25673f..bbc2845b 100644 --- a/test/smp/regression/threadx_mutex_proritize_test.c +++ b/test/smp/regression/threadx_mutex_proritize_test.c @@ -76,12 +76,12 @@ static void test_isr(void) } else { - + /* Abort the wait of thread 5. */ tx_thread_wait_abort(&thread_5); /* End the ISR processing. */ - test_status = 2; + test_status = 2; test_isr_dispatch = TX_NULL; } } @@ -107,8 +107,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -120,8 +120,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -133,8 +133,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 14, 14, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -146,8 +146,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 3, 3, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -159,8 +159,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 4, 4, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -172,8 +172,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, TEST_STACK_SIZE_PRINTF, 5, 5, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -185,8 +185,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, + pointer, TEST_STACK_SIZE_PRINTF, 6, 6, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -323,7 +323,7 @@ UINT status; tx_thread_resume(&thread_4); tx_thread_resume(&thread_5); tx_thread_resume(&thread_6); - + /* Prioritize the block pool suspension list. */ status = tx_mutex_prioritize(&mutex_0); @@ -338,7 +338,7 @@ UINT status; /* Now loop to test the interrupt of the prioritize loop logic. */ test_status = 1; - test_isr_dispatch = test_isr; + test_isr_dispatch = test_isr; do { @@ -355,10 +355,10 @@ UINT status; } } while (test_status == 1); - + /* Now determine if thread 4 is at the front of the list... It should be! */ if (mutex_0.tx_mutex_suspension_list != &thread_4) - { + { /* Mutex error. */ printf("ERROR #17\n"); @@ -382,19 +382,19 @@ UINT status; while (1) { - + /* Suspend on the mutex. */ status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); /* Release the mutex. */ status += tx_mutex_put(&mutex_0); - + /* Did we get the right status? */ if (status == TX_SUCCESS) thread_1_counter++; /* Self suspend. */ - tx_thread_suspend(&thread_1); + tx_thread_suspend(&thread_1); } } @@ -407,19 +407,19 @@ UINT status; while (1) { - + /* Suspend on the mutex. */ status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); /* Release the mutex. */ status += tx_mutex_put(&mutex_0); - + /* Did we get the right status? */ if (status == TX_SUCCESS) thread_2_counter++; /* Self suspend. */ - tx_thread_suspend(&thread_2); + tx_thread_suspend(&thread_2); } } @@ -432,19 +432,19 @@ UINT status; while (1) { - + /* Suspend on the mutex. */ status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); /* Release the mutex. */ status += tx_mutex_put(&mutex_0); - + /* Did we get the right status? */ if (status == TX_SUCCESS) thread_3_counter++; /* Self suspend. */ - tx_thread_suspend(&thread_3); + tx_thread_suspend(&thread_3); } } @@ -457,19 +457,19 @@ UINT status; while (1) { - + /* Suspend on the mutex. */ status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); /* Release the mutex. */ status += tx_mutex_put(&mutex_0); - + /* Did we get the right status? */ if (status == TX_SUCCESS) thread_4_counter++; /* Self suspend. */ - tx_thread_suspend(&thread_4); + tx_thread_suspend(&thread_4); } } @@ -482,19 +482,19 @@ UINT status; while (1) { - + /* Suspend on the mutex. */ status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); /* Release the mutex. */ status += tx_mutex_put(&mutex_0); - + /* Did we get the right status? */ if (status == TX_SUCCESS) thread_5_counter++; /* Self suspend. */ - tx_thread_suspend(&thread_5); + tx_thread_suspend(&thread_5); } } @@ -507,19 +507,19 @@ UINT status; while (1) { - + /* Suspend on the mutex. */ status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); /* Release the mutex. */ status += tx_mutex_put(&mutex_0); - + /* Did we get the right status? */ if (status == TX_SUCCESS) thread_6_counter++; /* Self suspend. */ - tx_thread_suspend(&thread_6); + tx_thread_suspend(&thread_6); } } diff --git a/test/smp/regression/threadx_mutex_suspension_timeout_test.c b/test/smp/regression/threadx_mutex_suspension_timeout_test.c index 8e1b79ea..7460d367 100644 --- a/test/smp/regression/threadx_mutex_suspension_timeout_test.c +++ b/test/smp/regression/threadx_mutex_suspension_timeout_test.c @@ -17,7 +17,7 @@ static TX_THREAD low_priority; static TX_MUTEX mutex_0; static TX_MUTEX mutex_1; -extern UINT mutex_priority_change_extension_selection; +extern UINT mutex_priority_change_extension_selection; /* Define thread prototypes. */ @@ -44,7 +44,7 @@ extern TEST_FLAG threadx_mutex_suspension_priority_test; #endif -/* This test routine is used to get NULL suspension lists in various parts of tx_mutex_put. This is hooked up to IRQ 0 on this simulation and is entered manually at the +/* This test routine is used to get NULL suspension lists in various parts of tx_mutex_put. This is hooked up to IRQ 0 on this simulation and is entered manually at the correct time. */ void abort_all_threads_suspended_on_mutex(void) { @@ -56,7 +56,7 @@ TX_THREAD *thread_ptr; { if (thread_ptr -> tx_thread_state == TX_MUTEX_SUSP) tx_thread_wait_abort(thread_ptr); - + thread_ptr = thread_ptr -> tx_thread_created_next; if (thread_ptr == _tx_thread_created_ptr) break; @@ -64,7 +64,7 @@ TX_THREAD *thread_ptr; } -/* This test routine is used to get a thread of a non ready state into _tx_mutex_change, called froim _tx_mutex_put. This is hooked up to IRQ 1 on this simulation and is entered manually at the +/* This test routine is used to get a thread of a non ready state into _tx_mutex_change, called froim _tx_mutex_put. This is hooked up to IRQ 1 on this simulation and is entered manually at the correct time. */ void suspend_lowest_priority(void) { @@ -77,7 +77,7 @@ TX_THREAD *thread_ptr; /* Determine which extension to perform... to get to the different error checks in _tx_mutex_priority_change. */ if (mutex_priority_change_extension_selection == 0) { - + /* Setup the thread pointer. */ thread_ptr = &thread_0; @@ -114,7 +114,7 @@ TX_THREAD *thread_ptr; } else if (mutex_priority_change_extension_selection == 1) { - + /* Make the mapped core field to be invalid to exercise the error checking branch for core_index. */ thread_0.tx_thread_smp_core_mapped = TX_THREAD_SMP_MAX_CORES; } @@ -140,28 +140,28 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 1, 1, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 2, 2, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 3, 3, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 4, 4, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&low_priority, "low priority", low_priority_entry, 30, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&low_priority, "low priority", low_priority_entry, 30, + pointer, TEST_STACK_SIZE_PRINTF, 30, 30, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -225,7 +225,7 @@ UINT status; /* Get the mutex. */ status = tx_mutex_get(&mutex_1, TX_WAIT_FOREVER); - + /* Make sure the three higher priority threads suspend on the mutex. */ tx_thread_resume(&thread_4); tx_thread_resume(&thread_3); @@ -245,16 +245,16 @@ UINT status; #endif /* Now some hand testing for tx_mutex_priority_change. */ - - /* Resume the low priority thread. */ + + /* Resume the low priority thread. */ tx_thread_resume(&low_priority); - + /* Disable interrupts. */ TX_DISABLE /* Simulate a call from inside of mutex put, but doing it here makes life easier. */ _tx_thread_preempt_disable++; - + /* Move the current thread to a lower priority. */ _tx_mutex_priority_change(&thread_0, 15); _tx_mutex_priority_change(&thread_0, 16); @@ -263,16 +263,16 @@ UINT status; _tx_mutex_priority_change(&low_priority, 28); _tx_mutex_priority_change(&low_priority, 29); _tx_mutex_priority_change(&low_priority, 30); - + /* Change the priority of the current thread, such that we should have reverse the preemption-threshold issue. */ thread_0.tx_thread_user_priority = 30; thread_0.tx_thread_user_preempt_threshold = 30; - _tx_mutex_priority_change(&thread_0, 30); + _tx_mutex_priority_change(&thread_0, 30); /* Change to an even lower priority. */ thread_0.tx_thread_user_priority = 31; thread_0.tx_thread_user_preempt_threshold = 31; - _tx_mutex_priority_change(&thread_0, 31); + _tx_mutex_priority_change(&thread_0, 31); /* Move back to a higher-priority. */ thread_0.tx_thread_user_priority = 30; @@ -284,31 +284,31 @@ UINT status; /* Set BP here and step into code and step through the code until the internal thread resume function returns, then issue an IRQ 1 to cause an ISR to suspend the thread and test the first condition. */ _tx_mutex_priority_change(&thread_0, 30); #else - + /* Set the flag to suspend the thread and test the first condition after internal resume is called. */ mutex_priority_change_extension_selection = 0; threadx_mutex_suspension_priority_test = 1; _tx_mutex_priority_change(&thread_0, 30); #endif - + /* Resume this thread. */ tx_thread_resume(&thread_0); _tx_mutex_priority_change(&thread_0, 16); - + /* Change to an even lower priority. */ thread_0.tx_thread_user_priority = 27; thread_0.tx_thread_user_preempt_threshold = 27; - _tx_mutex_priority_change(&thread_0, 28); + _tx_mutex_priority_change(&thread_0, 28); /* Setup the low priority thread infromation. */ low_priority.tx_thread_user_priority = 30; low_priority.tx_thread_user_preempt_threshold = 29; _tx_mutex_priority_change(&low_priority, 31); - + /* Change to an even lower priority. */ thread_0.tx_thread_user_priority = 30; thread_0.tx_thread_user_preempt_threshold = 29; - _tx_mutex_priority_change(&thread_0, 26); + _tx_mutex_priority_change(&thread_0, 26); #ifdef TX_MANUAL_TEST @@ -317,30 +317,30 @@ UINT status; _tx_mutex_priority_change(&thread_0, 30); thread_0.tx_thread_smp_core_mapped = 0; #else - + /* Set the flag to suspend the thread and test the first condition after internal resume is called. */ mutex_priority_change_extension_selection = 1; threadx_mutex_suspension_priority_test = 1; _tx_mutex_priority_change(&thread_0, 30); thread_0.tx_thread_smp_core_mapped = 0; -#endif +#endif /* Move the thread back to priority 28. */ _tx_mutex_priority_change(&thread_0, 28); - + #ifdef TX_MANUAL_TEST /* Set BP here and step into code and step through the code until the internal thread resume function returns, and then issue the IRQ that modifies the original priority. */ mutex_priority_change_extension_selection = 2; _tx_mutex_priority_change(&thread_0, 29); #else - + /* Set the flag to suspend the thread and test the first condition after internal resume is called. */ mutex_priority_change_extension_selection = 2; threadx_mutex_suspension_priority_test = 1; _tx_mutex_priority_change(&thread_0, 29); _tx_thread_execute_ptr[0] = &thread_0; -#endif +#endif #ifdef TX_MANUAL_TEST @@ -348,12 +348,12 @@ UINT status; mutex_priority_change_extension_selection = 3; _tx_mutex_priority_change(&thread_0, 30); #else - + /* Set the flag to suspend the thread and test the first condition after internal resume is called. */ mutex_priority_change_extension_selection = 3; threadx_mutex_suspension_priority_test = 1; _tx_mutex_priority_change(&thread_0, 30); -#endif +#endif #ifdef TX_MANUAL_TEST @@ -363,14 +363,14 @@ UINT status; _tx_mutex_priority_change(&thread_0, 31); _tx_thread_preemption__threshold_scheduled = temp_thread; #else - + /* Set the flag to suspend the thread and test the first condition after internal resume is called. */ temp_thread = _tx_thread_preemption__threshold_scheduled; mutex_priority_change_extension_selection = 4; threadx_mutex_suspension_priority_test = 1; _tx_mutex_priority_change(&thread_0, 31); _tx_thread_preemption__threshold_scheduled = temp_thread; -#endif +#endif /* Just change to same priority to ensure that path is executed. */ mutex_priority_change_extension_selection = 0; @@ -378,18 +378,18 @@ UINT status; thread_0.tx_thread_user_priority = 31; thread_0.tx_thread_user_preempt_threshold = 30; thread_0.tx_thread_priority = 31; - thread_0.tx_thread_preempt_threshold = 30; + thread_0.tx_thread_preempt_threshold = 30; _tx_mutex_priority_change(&thread_0, 31); thread_0.tx_thread_user_priority = 31; thread_0.tx_thread_user_preempt_threshold = 31; thread_0.tx_thread_priority = 31; - thread_0.tx_thread_preempt_threshold = 31; + thread_0.tx_thread_preempt_threshold = 31; _tx_mutex_priority_change(&thread_0, 31); tx_thread_resume(&thread_0); - /* Restore the preempt disable flag. */ + /* Restore the preempt disable flag. */ _tx_thread_preempt_disable--; - + /* Restore interrupts. */ TX_RESTORE diff --git a/test/smp/regression/threadx_mutex_thread_terminate_test.c b/test/smp/regression/threadx_mutex_thread_terminate_test.c index 9b552f54..ef21b92d 100644 --- a/test/smp/regression/threadx_mutex_thread_terminate_test.c +++ b/test/smp/regression/threadx_mutex_thread_terminate_test.c @@ -47,8 +47,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -60,8 +60,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -73,8 +73,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; diff --git a/test/smp/regression/threadx_queue_basic_eight_word_test.c b/test/smp/regression/threadx_queue_basic_eight_word_test.c index c201fdee..fb4640cc 100644 --- a/test/smp/regression/threadx_queue_basic_eight_word_test.c +++ b/test/smp/regression/threadx_queue_basic_eight_word_test.c @@ -1,5 +1,5 @@ /* This test is designed to test immediate response queue services including create - and delete. This test is for queue sizes of 8 ULONG. Two queues are used one with + and delete. This test is for queue sizes of 8 ULONG. Two queues are used one with a capacity of 1 message and another with a capacity of 3 messages. */ #include @@ -40,8 +40,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -111,9 +111,9 @@ ULONG expected_message[8]; printf("ERROR #4\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -163,9 +163,9 @@ ULONG expected_message[8]; printf("ERROR #8\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -218,7 +218,7 @@ ULONG expected_message[8]; status += tx_queue_send(&queue_1, source_message, TX_NO_WAIT); source_message[0]++; source_message[7]++; - + if (status != TX_SUCCESS) { @@ -227,9 +227,9 @@ ULONG expected_message[8]; printf("ERROR #12\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -320,9 +320,9 @@ ULONG expected_message[8]; printf("ERROR #18\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) diff --git a/test/smp/regression/threadx_queue_basic_four_word_test.c b/test/smp/regression/threadx_queue_basic_four_word_test.c index 5e01bc5b..4c54d8bd 100644 --- a/test/smp/regression/threadx_queue_basic_four_word_test.c +++ b/test/smp/regression/threadx_queue_basic_four_word_test.c @@ -1,5 +1,5 @@ /* This test is designed to test immediate response queue services including create - and delete. This test is for queue sizes of 4 ULONG. Two queues are used one with + and delete. This test is for queue sizes of 4 ULONG. Two queues are used one with a capacity of 1 message and another with a capacity of 3 messages. */ #include @@ -40,8 +40,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -111,9 +111,9 @@ ULONG expected_message[4]; printf("ERROR #4\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -163,9 +163,9 @@ ULONG expected_message[4]; printf("ERROR #8\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -218,7 +218,7 @@ ULONG expected_message[4]; status += tx_queue_send(&queue_1, source_message, TX_NO_WAIT); source_message[0]++; source_message[3]++; - + if (status != TX_SUCCESS) { @@ -227,9 +227,9 @@ ULONG expected_message[4]; printf("ERROR #12\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -320,9 +320,9 @@ ULONG expected_message[4]; printf("ERROR #18\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) diff --git a/test/smp/regression/threadx_queue_basic_max_message_size_test.c b/test/smp/regression/threadx_queue_basic_max_message_size_test.c index 30afa190..d62e80ff 100644 --- a/test/smp/regression/threadx_queue_basic_max_message_size_test.c +++ b/test/smp/regression/threadx_queue_basic_max_message_size_test.c @@ -1,5 +1,5 @@ /* This test is designed to test immediate response queue services including create - and delete. This test is for queue sizes of 16 ULONG. Two queues are used one with + and delete. This test is for queue sizes of 16 ULONG. Two queues are used one with a capacity of 1 message and another with a capacity of 3 messages. */ #include @@ -40,8 +40,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -110,9 +110,9 @@ ULONG expected_message[TX_QUEUE_MESSAGE_MAX_SIZE]; printf("ERROR #4\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -162,9 +162,9 @@ ULONG expected_message[TX_QUEUE_MESSAGE_MAX_SIZE]; printf("ERROR #8\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -217,7 +217,7 @@ ULONG expected_message[TX_QUEUE_MESSAGE_MAX_SIZE]; status += tx_queue_send(&queue_1, source_message, TX_NO_WAIT); source_message[0]++; source_message[TX_QUEUE_MESSAGE_MAX_SIZE - 1]++; - + if (status != TX_SUCCESS) { @@ -226,9 +226,9 @@ ULONG expected_message[TX_QUEUE_MESSAGE_MAX_SIZE]; printf("ERROR #12\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -319,9 +319,9 @@ ULONG expected_message[TX_QUEUE_MESSAGE_MAX_SIZE]; printf("ERROR #18\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) diff --git a/test/smp/regression/threadx_queue_basic_one_word_test.c b/test/smp/regression/threadx_queue_basic_one_word_test.c index 142a9b60..0e2f1fbc 100644 --- a/test/smp/regression/threadx_queue_basic_one_word_test.c +++ b/test/smp/regression/threadx_queue_basic_one_word_test.c @@ -1,5 +1,5 @@ /* This test is designed to test immediate response queue services including create - and delete. This test is for queue sizes of 1 ULONG. Two queues are used one with + and delete. This test is for queue sizes of 1 ULONG. Two queues are used one with a capacity of 1 message and another with a capacity of 3 messages. */ #include @@ -40,7 +40,7 @@ static void thread_0_entry(ULONG thread_input); static void thread_1_entry(ULONG thread_input); -UINT _txe_queue_create(TX_QUEUE *queue_ptr, CHAR *name_ptr, UINT message_size, +UINT _txe_queue_create(TX_QUEUE *queue_ptr, CHAR *name_ptr, UINT message_size, VOID *queue_start, ULONG queue_size, UINT queue_control_block_size); @@ -65,7 +65,7 @@ ULONG destination; /* Determine if calling queue create from initialization was successful. */ if (test_queue_from_init != TX_SUCCESS) { - + /* Error! */ error++; } @@ -84,7 +84,7 @@ ULONG destination; /* Attempt to delete a queue from a timer. */ status = tx_queue_delete(&queue_0); - + /* Check for status. */ if (status != TX_CALLER_ERROR) { @@ -95,7 +95,7 @@ ULONG destination; /* Attempt to send something with suspension from a timer. */ status = tx_queue_front_send(&queue_0, &source, 100); - + /* Check for status. */ if (status != TX_WAIT_ERROR) { @@ -106,7 +106,7 @@ ULONG destination; /* Attempt to send something with suspension from a timer. */ status = tx_queue_send(&queue_0, &source, 100); - + /* Check for status. */ if (status != TX_WAIT_ERROR) { @@ -117,7 +117,7 @@ ULONG destination; /* Attempt to receive something with suspension from a timer. */ status = tx_queue_receive(&queue_0, &destination, 100); - + /* Check for status. */ if (status != TX_WAIT_ERROR) { @@ -158,7 +158,7 @@ ULONG destination; /* Attempt to delete a queue from an ISR. */ status = tx_queue_delete(&queue_0); - + /* Check for status. */ if (status != TX_CALLER_ERROR) { @@ -169,7 +169,7 @@ ULONG destination; /* Attempt to send something with suspension from an ISR. */ status = tx_queue_front_send(&queue_0, &source, 100); - + /* Check for status. */ if (status != TX_WAIT_ERROR) { @@ -180,7 +180,7 @@ ULONG destination; /* Attempt to send something with suspension from an ISR. */ status = tx_queue_send(&queue_0, &source, 100); - + /* Check for status. */ if (status != TX_WAIT_ERROR) { @@ -191,7 +191,7 @@ ULONG destination; /* Attempt to receive something with suspension from an ISR. */ status = tx_queue_receive(&queue_0, &destination, 100); - + /* Check for status. */ if (status != TX_WAIT_ERROR) { @@ -224,13 +224,13 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -380,7 +380,7 @@ CHAR *pointer; /* Attempt to delete a NULL pointer. */ status = tx_queue_delete(TX_NULL); - + /* Check for status. */ if (status != TX_QUEUE_ERROR) { @@ -393,7 +393,7 @@ CHAR *pointer; /* Attempt to delete a non-created queue. */ queue_2.tx_queue_id = 0; status = tx_queue_delete(&queue_2); - + /* Check for status. */ if (status != TX_QUEUE_ERROR) { @@ -405,7 +405,7 @@ CHAR *pointer; /* Attempt to flush a NULL pointer. */ status = tx_queue_flush(TX_NULL); - + /* Check for status. */ if (status != TX_QUEUE_ERROR) { @@ -418,7 +418,7 @@ CHAR *pointer; /* Attempt to flush a non-created queue. */ queue_2.tx_queue_id = 0; status = tx_queue_flush(&queue_2); - + /* Check for status. */ if (status != TX_QUEUE_ERROR) { @@ -430,7 +430,7 @@ CHAR *pointer; /* Attempt to send something to the front of a non-queue. */ status = tx_queue_front_send(TX_NULL, &source_message, TX_NO_WAIT); - + /* Check for status. */ if (status != TX_QUEUE_ERROR) { @@ -439,11 +439,11 @@ CHAR *pointer; printf("ERROR #15\n"); test_control_return(1); } - + /* Attempt to send something to the front of a non-created queue. */ queue_2.tx_queue_id = 0; status = tx_queue_front_send(&queue_2, &source_message, TX_NO_WAIT); - + /* Check for status. */ if (status != TX_QUEUE_ERROR) { @@ -455,7 +455,7 @@ CHAR *pointer; /* Attempt to send something with a NULL source pointer. */ status = tx_queue_front_send(&queue_0, TX_NULL, TX_NO_WAIT); - + /* Check for status. */ if (status != TX_PTR_ERROR) { @@ -467,7 +467,7 @@ CHAR *pointer; /* Attempt to send something to a non-queue. */ status = tx_queue_send(TX_NULL, &source_message, TX_NO_WAIT); - + /* Check for status. */ if (status != TX_QUEUE_ERROR) { @@ -476,11 +476,11 @@ CHAR *pointer; printf("ERROR #18\n"); test_control_return(1); } - + /* Attempt to send something to a non-created queue. */ queue_2.tx_queue_id = 0; status = tx_queue_send(&queue_2, &source_message, TX_NO_WAIT); - + /* Check for status. */ if (status != TX_QUEUE_ERROR) { @@ -492,7 +492,7 @@ CHAR *pointer; /* Attempt to send something with a NULL source pointer. */ status = tx_queue_send(&queue_0, TX_NULL, TX_NO_WAIT); - + /* Check for status. */ if (status != TX_PTR_ERROR) { @@ -504,7 +504,7 @@ CHAR *pointer; /* Attempt to receive something from a non-queue. */ status = tx_queue_receive(TX_NULL, &dest_message, TX_NO_WAIT); - + /* Check for status. */ if (status != TX_QUEUE_ERROR) { @@ -517,7 +517,7 @@ CHAR *pointer; /* Attempt to receive something from a non-created queue. */ queue_2.tx_queue_id = 0; status = tx_queue_receive(&queue_2, &dest_message, TX_NO_WAIT); - + /* Check for status. */ if (status != TX_QUEUE_ERROR) { @@ -529,7 +529,7 @@ CHAR *pointer; /* Attempt to receive something to a NULL destination. */ status = tx_queue_receive(&queue_0, TX_NULL, TX_NO_WAIT); - + /* Check for status. */ if (status != TX_PTR_ERROR) { @@ -550,9 +550,9 @@ CHAR *pointer; printf("ERROR #24\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_0, &source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_0, &source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -602,7 +602,7 @@ CHAR *pointer; } /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_0, &source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_0, &source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -649,7 +649,7 @@ CHAR *pointer; source_message++; status += tx_queue_send(&queue_1, &source_message, TX_NO_WAIT); source_message++; - + if (status != TX_SUCCESS) { @@ -657,9 +657,9 @@ CHAR *pointer; printf("ERROR #32\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_1, &source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_1, &source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -735,9 +735,9 @@ CHAR *pointer; printf("ERROR #38\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_1, &source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_1, &source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -810,7 +810,7 @@ CHAR *pointer; /* Resume thread 1 so that we can take an interrupt on top of it. */ tx_thread_resume(&thread_1); - + /* Sleep for a bit... */ tx_thread_sleep(3); @@ -820,7 +820,7 @@ CHAR *pointer; /* Test for error. */ if ((error) || (timer_executed != 1) || (isr_executed != 1)) { - + /* Queue error. */ printf("ERROR #44\n"); test_control_return(1); diff --git a/test/smp/regression/threadx_queue_basic_sixteen_word_test.c b/test/smp/regression/threadx_queue_basic_sixteen_word_test.c index 703a1cf4..de3ede98 100644 --- a/test/smp/regression/threadx_queue_basic_sixteen_word_test.c +++ b/test/smp/regression/threadx_queue_basic_sixteen_word_test.c @@ -1,5 +1,5 @@ /* This test is designed to test immediate response queue services including create - and delete. This test is for queue sizes of 16 ULONG. Two queues are used one with + and delete. This test is for queue sizes of 16 ULONG. Two queues are used one with a capacity of 1 message and another with a capacity of 3 messages. */ #include @@ -40,8 +40,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -111,9 +111,9 @@ ULONG expected_message[16]; printf("ERROR #4\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -163,9 +163,9 @@ ULONG expected_message[16]; printf("ERROR #8\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -218,7 +218,7 @@ ULONG expected_message[16]; status += tx_queue_send(&queue_1, source_message, TX_NO_WAIT); source_message[0]++; source_message[15]++; - + if (status != TX_SUCCESS) { @@ -227,9 +227,9 @@ ULONG expected_message[16]; printf("ERROR #12\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -320,9 +320,9 @@ ULONG expected_message[16]; printf("ERROR #18\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) diff --git a/test/smp/regression/threadx_queue_basic_two_word_test.c b/test/smp/regression/threadx_queue_basic_two_word_test.c index ab24d08e..46d85a6d 100644 --- a/test/smp/regression/threadx_queue_basic_two_word_test.c +++ b/test/smp/regression/threadx_queue_basic_two_word_test.c @@ -1,5 +1,5 @@ /* This test is designed to test immediate response queue services including create - and delete. This test is for queue sizes of 2 ULONG. Two queues are used one with + and delete. This test is for queue sizes of 2 ULONG. Two queues are used one with a capacity of 1 message and another with a capacity of 3 messages. */ #include @@ -54,8 +54,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -116,7 +116,7 @@ ULONG expected_message[2]; queue_memory.second_middle= 0x61718191; queue_memory.next_to_last = 0x99aabbcc; queue_memory.last = 0xddeeff00; - + /* Create the queue. */ status = tx_queue_create(&queue_memory.queue, "queue memory", TX_2_ULONG, &queue_memory.queue_area[0], (2048*sizeof(ULONG))/sizeof(ULONG)); tx_queue_delete(&queue_memory.queue); @@ -151,9 +151,9 @@ ULONG expected_message[2]; printf("ERROR #5\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -203,9 +203,9 @@ ULONG expected_message[2]; printf("ERROR #9\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -258,7 +258,7 @@ ULONG expected_message[2]; status += tx_queue_send(&queue_1, source_message, TX_NO_WAIT); source_message[0]++; source_message[1]++; - + if (status != TX_SUCCESS) { @@ -267,9 +267,9 @@ ULONG expected_message[2]; printf("ERROR #13\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -360,9 +360,9 @@ ULONG expected_message[2]; printf("ERROR #19\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) diff --git a/test/smp/regression/threadx_queue_empty_suspension_test.c b/test/smp/regression/threadx_queue_empty_suspension_test.c index 59d53e70..c63b1715 100644 --- a/test/smp/regression/threadx_queue_empty_suspension_test.c +++ b/test/smp/regression/threadx_queue_empty_suspension_test.c @@ -54,8 +54,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -67,8 +67,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -80,8 +80,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -107,7 +107,7 @@ CHAR *pointer; /* Setup queue send notification. */ status = tx_queue_send_notify(&queue_0, queue_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check for status. */ @@ -117,7 +117,7 @@ CHAR *pointer; printf("Running Queue Empty Suspension Test................................. ERROR #5\n"); test_control_return(1); } - + #else /* Check for status. */ @@ -128,7 +128,7 @@ CHAR *pointer; test_control_return(1); } -#endif +#endif } @@ -193,12 +193,12 @@ ULONG source_message[2] = {0x12345678, 0}; /* Now resume thread 2 to get another thread suspended on an empty queue. */ tx_thread_resume(&thread_2); - + /* Now send 2 messages to wakeup both threads! */ source_message[0]++; status = tx_queue_send(&queue_0, &source_message[0], TX_NO_WAIT); status += tx_queue_send(&queue_0, &source_message[0], TX_NO_WAIT); - + /* Check status and run count of other thread - it should have got the message already. */ if ((status != TX_SUCCESS) || (thread_1_counter != 2) || (thread_2_counter != 1)) diff --git a/test/smp/regression/threadx_queue_flush_no_suspension_test.c b/test/smp/regression/threadx_queue_flush_no_suspension_test.c index 940259f2..95bd5fed 100644 --- a/test/smp/regression/threadx_queue_flush_no_suspension_test.c +++ b/test/smp/regression/threadx_queue_flush_no_suspension_test.c @@ -44,8 +44,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -73,7 +73,7 @@ CHAR *pointer; status = tx_queue_send_notify(&queue_0, queue_notify); #ifndef TX_DISABLE_NOTIFY_CALLBACKS - + /* Check for status. */ if (status != TX_SUCCESS) { diff --git a/test/smp/regression/threadx_queue_flush_test.c b/test/smp/regression/threadx_queue_flush_test.c index 6d65c971..77f8d2d5 100644 --- a/test/smp/regression/threadx_queue_flush_test.c +++ b/test/smp/regression/threadx_queue_flush_test.c @@ -52,8 +52,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -65,8 +65,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -78,8 +78,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -108,7 +108,7 @@ CHAR *pointer; status = tx_queue_send_notify(&queue_0, queue_notify); #ifndef TX_DISABLE_NOTIFY_CALLBACKS - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -203,7 +203,7 @@ UINT status; } else { - + /* Queue Flush error. */ printf("ERROR #11\n"); test_control_return(1); diff --git a/test/smp/regression/threadx_queue_front_send_test.c b/test/smp/regression/threadx_queue_front_send_test.c index 5329670b..d03e7ac2 100644 --- a/test/smp/regression/threadx_queue_front_send_test.c +++ b/test/smp/regression/threadx_queue_front_send_test.c @@ -60,8 +60,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -73,12 +73,12 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status = tx_thread_create(&thread_1a, "thread 1a", thread_1a_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1a, "thread 1a", thread_1a_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -90,12 +90,12 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status = tx_thread_create(&thread_2a, "thread 2a", thread_2a_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2a, "thread 2a", thread_2a_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -125,7 +125,7 @@ CHAR *pointer; status = tx_queue_send_notify(&queue_0, queue_notify); #ifndef TX_DISABLE_NOTIFY_CALLBACKS - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -164,7 +164,7 @@ ULONG temp[2]; printf("Running Queue Front Test............................................ "); /* Perform the 1 word queue front send test. */ - + /* Increment thread 0 counter. */ thread_0_counter++; @@ -178,7 +178,7 @@ ULONG temp[2]; printf("ERROR #7a\n"); test_control_return(1); } - + /* Place a new message on the front of the queue. */ temp[0] = 0xF000001; status = tx_queue_front_send(&queue_0a, &temp[0], TX_NO_WAIT); @@ -226,17 +226,17 @@ ULONG temp[2]; printf("ERROR #11a\n"); test_control_return(1); } - - /* At this point the queue is empty. Resume another thread to + + /* At this point the queue is empty. Resume another thread to suspend on an empty queue. */ tx_thread_resume(&thread_1a); - + /* Relinquish to get this thread suspended on the empty queue. */ tx_thread_relinquish(); - + /* Resume thread 2a to get another thread suspended on the empty queue. */ tx_thread_resume(&thread_2a); - + /* Now send something to the front of the queue, which will resume the first waiting thread. */ temp[0] = 0xFF00002; @@ -262,10 +262,10 @@ ULONG temp[2]; printf("ERROR #13a\n"); test_control_return(1); } - + /* Now relinquish again to let the other thread process the message. */ tx_thread_relinquish(); - + /* At this point, the other thread should have placed 2 messages on the queue so we will now send to the front, but without suspension. */ temp[0] = 0xFF00003; @@ -293,11 +293,11 @@ ULONG temp[2]; /* Now resume thread 2a to get another thread suspended on the queue. */ tx_thread_resume(&thread_2a); - + temp[0] = 0xFF00004; status = tx_queue_front_send(&queue_0a, &temp[0], TX_WAIT_FOREVER); - - /* When we get back, the other thread has received all the messages and + + /* When we get back, the other thread has received all the messages and verified they are in order AND relinquished. */ if ((status != TX_SUCCESS) || (thread_1a_counter != 1)) { @@ -307,7 +307,7 @@ ULONG temp[2]; test_control_return(1); } - + /* Perform the multiword queue front send test. */ @@ -328,7 +328,7 @@ ULONG temp[2]; printf("ERROR #7\n"); test_control_return(1); } - + /* Place a new message on the front of the queue. */ temp[0] = 0xF000001; status = tx_queue_front_send(&queue_0, &temp[0], TX_NO_WAIT); @@ -376,17 +376,17 @@ ULONG temp[2]; printf("ERROR #11\n"); test_control_return(1); } - - /* At this point the queue is empty. Resume another thread to + + /* At this point the queue is empty. Resume another thread to suspend on an empty queue. */ tx_thread_resume(&thread_1); - + /* Relinquish to get this thread suspended on the empty queue. */ tx_thread_relinquish(); - + /* Resume thread 2 to get another thread suspended on the empty queue. */ tx_thread_resume(&thread_2); - + /* Now send something to the front of the queue, which will resume the first waiting thread. */ temp[0] = 0xFF00002; @@ -412,10 +412,10 @@ ULONG temp[2]; printf("ERROR #13\n"); test_control_return(1); } - + /* Now relinquish again to let the other thread process the message. */ tx_thread_relinquish(); - + /* At this point, the other thread should have placed 2 messages on the queue so we will now send to the front, but without suspension. */ temp[0] = 0xFF00003; @@ -443,11 +443,11 @@ ULONG temp[2]; /* Now resume thread 2 to get another thread suspended on the queue. */ tx_thread_resume(&thread_2); - + temp[0] = 0xFF00004; status = tx_queue_front_send(&queue_0, &temp[0], TX_WAIT_FOREVER); - - /* When we get back, the other thread has received all the messages and + + /* When we get back, the other thread has received all the messages and verified they are in order AND relinquished. */ if ((status != TX_SUCCESS) || (thread_1_counter != 1)) { @@ -480,18 +480,18 @@ ULONG dest_message[2]; /* Determine if the message is good. */ if ((status != TX_SUCCESS) || (dest_message[0] != 0xFF00002)) return; - + /* Now fill the queue with two messages. */ status = tx_queue_send(&queue_0, &source_message[0], TX_WAIT_FOREVER); source_message[0]++; status += tx_queue_front_send(&queue_0, &source_message[0], TX_WAIT_FOREVER); - + if (status != TX_SUCCESS) return; /* Now let thread 0 send to the front of the queue with suspension. */ tx_thread_relinquish(); - + /* Attempt to receive three messages from the queue. */ status = tx_queue_receive(&queue_0, &dest_message[0], TX_NO_WAIT); @@ -518,10 +518,10 @@ ULONG dest_message[2]; status = tx_queue_send(&queue_0, &source_message[0], TX_WAIT_FOREVER); source_message[0]++; status += tx_queue_front_send(&queue_0, &source_message[0], TX_WAIT_FOREVER); - + if (status != TX_SUCCESS) return; - + /* Now let thread 0 send to the front of the queue with suspension. */ tx_thread_relinquish(); @@ -552,11 +552,11 @@ ULONG dest_message[2]; /* Should be an error. */ if ((status != TX_SUCCESS) || (dest_message[0] != 0xEE000003)) return; - + /* Increment this threads counter. */ thread_1_counter++; } - + static void thread_2_entry(ULONG thread_input) { @@ -567,7 +567,7 @@ ULONG destination_message[2]; /* Receive message. */ tx_queue_receive(&queue_0, &destination_message[0], TX_WAIT_FOREVER); - + /* Self suspend. */ tx_thread_suspend(&thread_2); @@ -590,18 +590,18 @@ ULONG dest_message[2]; /* Determine if the message is good. */ if ((status != TX_SUCCESS) || (dest_message[0] != 0xFF00002)) return; - + /* Now fill the queue with two messages. */ status = tx_queue_send(&queue_0a, &source_message[0], TX_WAIT_FOREVER); source_message[0]++; status += tx_queue_front_send(&queue_0a, &source_message[0], TX_WAIT_FOREVER); - + if (status != TX_SUCCESS) return; /* Now let thread 0 send to the front of the queue with suspension. */ tx_thread_relinquish(); - + /* Attempt to receive three messages from the queue. */ status = tx_queue_receive(&queue_0a, &dest_message[0], TX_NO_WAIT); @@ -628,10 +628,10 @@ ULONG dest_message[2]; status = tx_queue_send(&queue_0a, &source_message[0], TX_WAIT_FOREVER); source_message[0]++; status += tx_queue_front_send(&queue_0a, &source_message[0], TX_WAIT_FOREVER); - + if (status != TX_SUCCESS) return; - + /* Now let thread 0 send to the front of the queue with suspension. */ tx_thread_relinquish(); @@ -662,11 +662,11 @@ ULONG dest_message[2]; /* Should be an error. */ if ((status != TX_SUCCESS) || (dest_message[0] != 0xEE000003)) return; - + /* Increment this threads counter. */ thread_1a_counter++; } - + static void thread_2a_entry(ULONG thread_input) { @@ -677,7 +677,7 @@ ULONG destination_message[2]; /* Receive message. */ tx_queue_receive(&queue_0a, &destination_message[0], TX_WAIT_FOREVER); - + /* Self suspend. */ tx_thread_suspend(&thread_2a); diff --git a/test/smp/regression/threadx_queue_full_suspension_test.c b/test/smp/regression/threadx_queue_full_suspension_test.c index 556a4c77..687ef04a 100644 --- a/test/smp/regression/threadx_queue_full_suspension_test.c +++ b/test/smp/regression/threadx_queue_full_suspension_test.c @@ -66,8 +66,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -79,12 +79,12 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_1a, "thread 1a", thread_1a_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_1a, "thread 1a", thread_1a_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -96,12 +96,12 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_2a, "thread 2a", thread_2a_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_2a, "thread 2a", thread_2a_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -131,7 +131,7 @@ CHAR *pointer; status = tx_queue_send_notify(&queue_0, queue_notify); #ifndef TX_DISABLE_NOTIFY_CALLBACKS - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -167,7 +167,7 @@ ULONG dest_message[2]; /* Inform user. */ printf("Running Queue Full Suspension Test.................................. "); - + /* Perform the one word queue version. */ /* Suspend to get thread 1a to pend on the queue. */ @@ -179,14 +179,14 @@ ULONG dest_message[2]; tx_queue_delete(&queue_0a); status += tx_queue_create(&queue_0a, "queue 0a", TX_1_ULONG, queue_area, sizeof(queue_area)); - + /* Fill the queue with an initial 3 messages! */ status += tx_queue_send(&queue_0a, &source_message[0], TX_NO_WAIT); status += tx_queue_send(&queue_0a, &source_message[0], TX_NO_WAIT); status += tx_queue_send(&queue_0a, &source_message[0], TX_NO_WAIT); source_message[0]++; - /* Receive two of the messages back to put the first received message at the end + /* Receive two of the messages back to put the first received message at the end of the queue. */ status += tx_queue_receive(&queue_0a, &dest_message[0], TX_NO_WAIT); status += tx_queue_receive(&queue_0a, &dest_message[0], TX_NO_WAIT); @@ -219,12 +219,12 @@ ULONG dest_message[2]; test_control_return(1); } - /* Perform the two word queue version. */ - + /* Perform the two word queue version. */ + /* Reset the source message. */ source_message[0] = 0x12345678; - source_message[1] = 0; - + source_message[1] = 0; + /* Resume threads 1 and 2. */ tx_thread_resume(&thread_1); tx_thread_resume(&thread_2); @@ -235,7 +235,7 @@ ULONG dest_message[2]; status += tx_queue_send(&queue_0, &source_message[0], TX_NO_WAIT); source_message[0]++; - /* Receive two of the messages back to put the first received message at the end + /* Receive two of the messages back to put the first received message at the end of the queue. */ status += tx_queue_receive(&queue_0, &dest_message[0], TX_NO_WAIT); status += tx_queue_receive(&queue_0, &dest_message[0], TX_NO_WAIT); diff --git a/test/smp/regression/threadx_queue_information_test.c b/test/smp/regression/threadx_queue_information_test.c index c1db82ca..5fcdbb8f 100644 --- a/test/smp/regression/threadx_queue_information_test.c +++ b/test/smp/regression/threadx_queue_information_test.c @@ -43,8 +43,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -147,9 +147,9 @@ ULONG timeouts; printf("ERROR #5\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_0, &source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_0, &source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -199,7 +199,7 @@ ULONG timeouts; } /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_0, &source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_0, &source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -246,7 +246,7 @@ ULONG timeouts; source_message++; status += tx_queue_send(&queue_1, &source_message, TX_NO_WAIT); source_message++; - + if (status != TX_SUCCESS) { @@ -254,9 +254,9 @@ ULONG timeouts; printf("ERROR #13\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_1, &source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_1, &source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -332,9 +332,9 @@ ULONG timeouts; printf("ERROR #19\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_1, &source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_1, &source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -397,9 +397,9 @@ ULONG timeouts; status = tx_queue_info_get(&queue_0, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_queue_info_get(&queue_0, &name, &enqueued, &available_storage, &first_suspended, &suspended_count, &next_queue); - /* Check for errors. */ - if ((status != TX_SUCCESS) || (enqueued != queue_0.tx_queue_enqueued) || (available_storage != queue_0.tx_queue_available_storage) || - (first_suspended != queue_0.tx_queue_suspension_list) || (suspended_count != queue_0.tx_queue_suspended_count) || + /* Check for errors. */ + if ((status != TX_SUCCESS) || (enqueued != queue_0.tx_queue_enqueued) || (available_storage != queue_0.tx_queue_available_storage) || + (first_suspended != queue_0.tx_queue_suspension_list) || (suspended_count != queue_0.tx_queue_suspended_count) || (next_queue != queue_0.tx_queue_created_next)) { @@ -413,7 +413,7 @@ ULONG timeouts; /* Test null pointer for queue performance info get. */ status = _tx_queue_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_PTR_ERROR) { @@ -426,9 +426,9 @@ ULONG timeouts; status = tx_queue_performance_info_get(&queue_0, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_queue_performance_info_get(&queue_0, &messages_sent, &messages_received, &empty_suspensions, &full_suspensions, &full_errors, &timeouts); - /* Check for errors. */ - if ((status != TX_SUCCESS) || (messages_sent != queue_0.tx_queue_performance_messages_sent_count) || (messages_received != queue_0.tx_queue_performance_messages_received_count) || - (empty_suspensions != queue_0.tx_queue_performance_empty_suspension_count) || (full_suspensions != queue_0.tx_queue_performance_full_suspension_count) || + /* Check for errors. */ + if ((status != TX_SUCCESS) || (messages_sent != queue_0.tx_queue_performance_messages_sent_count) || (messages_received != queue_0.tx_queue_performance_messages_received_count) || + (empty_suspensions != queue_0.tx_queue_performance_empty_suspension_count) || (full_suspensions != queue_0.tx_queue_performance_full_suspension_count) || (full_errors != queue_0.tx_queue_performance_full_error_count) || (timeouts != queue_0.tx_queue_performance_timeout_count)) { @@ -441,9 +441,9 @@ ULONG timeouts; status = tx_queue_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_queue_performance_system_info_get(&messages_sent, &messages_received, &empty_suspensions, &full_suspensions, &full_errors, &timeouts); - /* Check for errors. */ - if ((status != TX_SUCCESS) || (messages_sent != _tx_queue_performance_messages_sent_count) || (messages_received != _tx_queue_performance__messages_received_count) || - (empty_suspensions != _tx_queue_performance_empty_suspension_count) || (full_suspensions != _tx_queue_performance_full_suspension_count) || + /* Check for errors. */ + if ((status != TX_SUCCESS) || (messages_sent != _tx_queue_performance_messages_sent_count) || (messages_received != _tx_queue_performance__messages_received_count) || + (empty_suspensions != _tx_queue_performance_empty_suspension_count) || (full_suspensions != _tx_queue_performance_full_suspension_count) || (full_errors != _tx_queue_performance_full_error_count) || (timeouts != _tx_queue_performance_timeout_count)) { @@ -457,7 +457,7 @@ ULONG timeouts; /* Get performance information. */ status = tx_queue_performance_info_get(&queue_0, &messages_sent, &messages_received, &empty_suspensions, &full_suspensions, &full_errors, &timeouts); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -469,7 +469,7 @@ ULONG timeouts; /* Get performance information. */ status = tx_queue_performance_info_get(TX_NULL, &messages_sent, &messages_received, &empty_suspensions, &full_suspensions, &full_errors, &timeouts); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -481,7 +481,7 @@ ULONG timeouts; /* Get performance information. */ status = tx_queue_performance_info_get(TX_NULL, TX_NULL, &messages_received, &empty_suspensions, &full_suspensions, &full_errors, &timeouts); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -493,7 +493,7 @@ ULONG timeouts; /* Get performance information. */ status = tx_queue_performance_info_get(TX_NULL, TX_NULL, TX_NULL, &empty_suspensions, &full_suspensions, &full_errors, &timeouts); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -505,7 +505,7 @@ ULONG timeouts; /* Get performance information. */ status = tx_queue_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, &full_suspensions, &full_errors, &timeouts); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -517,7 +517,7 @@ ULONG timeouts; /* Get performance information. */ status = tx_queue_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &full_errors, &timeouts); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -529,7 +529,7 @@ ULONG timeouts; /* Get performance information. */ status = tx_queue_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &timeouts); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -541,7 +541,7 @@ ULONG timeouts; /* Get performance information. */ status = tx_queue_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -553,7 +553,7 @@ ULONG timeouts; /* Get system performance information. */ status = tx_queue_performance_system_info_get(&messages_sent, &messages_received, &empty_suspensions, &full_suspensions, &full_errors, &timeouts); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -565,7 +565,7 @@ ULONG timeouts; /* Get system performance information. */ status = tx_queue_performance_system_info_get(TX_NULL, &messages_received, &empty_suspensions, &full_suspensions, &full_errors, &timeouts); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -577,7 +577,7 @@ ULONG timeouts; /* Get system performance information. */ status = tx_queue_performance_system_info_get(TX_NULL, TX_NULL, &empty_suspensions, &full_suspensions, &full_errors, &timeouts); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -589,7 +589,7 @@ ULONG timeouts; /* Get system performance information. */ status = tx_queue_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, &full_suspensions, &full_errors, &timeouts); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -601,7 +601,7 @@ ULONG timeouts; /* Get system performance information. */ status = tx_queue_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, &full_errors, &timeouts); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -613,7 +613,7 @@ ULONG timeouts; /* Get system performance information. */ status = tx_queue_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &timeouts); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -625,7 +625,7 @@ ULONG timeouts; /* Get system performance information. */ status = tx_queue_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { diff --git a/test/smp/regression/threadx_queue_prioritize.c b/test/smp/regression/threadx_queue_prioritize.c index 7a9d2b44..53c19275 100644 --- a/test/smp/regression/threadx_queue_prioritize.c +++ b/test/smp/regression/threadx_queue_prioritize.c @@ -81,12 +81,12 @@ static void test_isr(void) } else { - + /* Abort the wait of thread 5. */ tx_thread_wait_abort(&thread_5); /* End the ISR processing. */ - test_status = 2; + test_status = 2; test_isr_dispatch = TX_NULL; } } @@ -112,8 +112,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -125,8 +125,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -138,8 +138,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -152,8 +152,8 @@ CHAR *pointer; } - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 3, 3, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -165,8 +165,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 4, 4, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -178,8 +178,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, TEST_STACK_SIZE_PRINTF, 5, 5, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -191,8 +191,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, + pointer, TEST_STACK_SIZE_PRINTF, 6, 6, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -220,7 +220,7 @@ CHAR *pointer; status = tx_queue_send_notify(&queue_0, queue_notify); #ifndef TX_DISABLE_NOTIFY_CALLBACKS - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -335,7 +335,7 @@ UINT status; printf("ERROR #15\n"); test_control_return(1); } - + /* At this point we are going to get more than 2 threads suspended. */ tx_thread_resume(&thread_1); tx_thread_resume(&thread_2); @@ -343,7 +343,7 @@ UINT status; tx_thread_resume(&thread_4); tx_thread_resume(&thread_5); tx_thread_resume(&thread_6); - + /* Prioritize the queue suspension list. */ status = tx_queue_prioritize(&queue_0); @@ -355,10 +355,10 @@ UINT status; printf("ERROR #16\n"); test_control_return(1); } - + /* Now loop to test the interrupt of the prioritize loop logic. */ test_status = 1; - test_isr_dispatch = test_isr; + test_isr_dispatch = test_isr; do { @@ -375,10 +375,10 @@ UINT status; } } while (test_status == 1); - + /* Now determine if thread 4 is at the front of the list... It should be! */ if (queue_0.tx_queue_suspension_list != &thread_4) - { + { /* Queue error. */ printf("ERROR #18\n"); diff --git a/test/smp/regression/threadx_queue_suspension_timeout_test.c b/test/smp/regression/threadx_queue_suspension_timeout_test.c index a3c390ed..92dca991 100644 --- a/test/smp/regression/threadx_queue_suspension_timeout_test.c +++ b/test/smp/regression/threadx_queue_suspension_timeout_test.c @@ -54,8 +54,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -67,8 +67,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -80,8 +80,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -120,7 +120,7 @@ CHAR *pointer; status = tx_queue_send_notify(&queue_0, queue_notify); #ifndef TX_DISABLE_NOTIFY_CALLBACKS - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -184,7 +184,7 @@ ULONG source_message[2] = {0x12345678, 0}; printf("ERROR #9a\n"); test_control_return(1); } - + /* Send message that should cause this thread to suspend. The timeout should cause it to resume with a TX_QUEUE_FULL error code. */ status = tx_queue_send(&queue_0, &source_message[0], 32); @@ -217,7 +217,7 @@ ULONG dest_message[2]; { - /* Receive message from empty queue with suspension and timeout. + /* Receive message from empty queue with suspension and timeout. We should wakeup after the timeout expires with an empty status. */ status = tx_queue_receive(&queue_1, &dest_message[0], 20); @@ -241,7 +241,7 @@ ULONG dest_message[2]; { - /* Receive message from empty queue with suspension and timeout. + /* Receive message from empty queue with suspension and timeout. We should wakeup after the timeout expires with an empty status. */ status = tx_queue_receive(&queue_1, &dest_message[0], 20); diff --git a/test/smp/regression/threadx_queue_thread_terminate_test.c b/test/smp/regression/threadx_queue_thread_terminate_test.c index d0834704..97d8a569 100644 --- a/test/smp/regression/threadx_queue_thread_terminate_test.c +++ b/test/smp/regression/threadx_queue_thread_terminate_test.c @@ -48,8 +48,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -61,8 +61,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -85,10 +85,10 @@ CHAR *pointer; printf("Running Queue Thread Terminate Test................................. ERROR #3\n"); test_control_return(1); } - + /* Setup queue send notification. */ status = tx_queue_send_notify(&queue_0, queue_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check for status. */ diff --git a/test/smp/regression/threadx_semaphore_basic_test.c b/test/smp/regression/threadx_semaphore_basic_test.c index f554257d..33ee3257 100644 --- a/test/smp/regression/threadx_semaphore_basic_test.c +++ b/test/smp/regression/threadx_semaphore_basic_test.c @@ -72,7 +72,7 @@ UINT status; /* Determine if calling semaphore create from initialization was successful. */ if (test_semaphore_from_init != TX_SUCCESS) { - + /* Error! */ error++; } @@ -182,13 +182,13 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -240,11 +240,11 @@ UINT status; semaphore_memory.second = 0x55667788; semaphore_memory.next_to_last = 0x99aabbcc; semaphore_memory.last = 0xddeeff00; - + /* Create the semaphore. */ status = tx_semaphore_create(&semaphore_memory.semaphore, "semaphore memory", 0); tx_semaphore_delete(&semaphore_memory.semaphore); - + /* Check for status. */ if ((status != TX_SUCCESS) || (semaphore_memory.first != 0x11223344) || @@ -463,7 +463,7 @@ UINT status; /* Attempt to get from semaphore with an instance. Should be successful. */ status = tx_semaphore_get(&semaphore_1, TX_NO_WAIT); - + /* Check status. */ if (status != TX_SUCCESS) { @@ -496,7 +496,7 @@ UINT status; /* Test for error. */ if ((error) || (timer_executed != 1) || (isr_executed != 1)) { - + /* Semaphore error. */ printf("ERROR #22\n"); test_control_return(1); @@ -539,7 +539,7 @@ static void thread_1_entry(ULONG thread_input) while(1) { - + tx_thread_relinquish(); } } \ No newline at end of file diff --git a/test/smp/regression/threadx_semaphore_ceiling_put_test.c b/test/smp/regression/threadx_semaphore_ceiling_put_test.c index 5364d2d9..7d4f5832 100644 --- a/test/smp/regression/threadx_semaphore_ceiling_put_test.c +++ b/test/smp/regression/threadx_semaphore_ceiling_put_test.c @@ -55,8 +55,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -68,8 +68,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -81,8 +81,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -108,7 +108,7 @@ CHAR *pointer; /* Setup the semaphore notify callback. */ status = tx_semaphore_put_notify(&semaphore_0, put_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check for status. */ @@ -205,15 +205,15 @@ UINT status; /* At this point, we need to resume thread 2 and relinquish in order to get that thread suspended on the semaphore as well. */ tx_thread_resume(&thread_2); - tx_thread_relinquish(); - + tx_thread_relinquish(); + /* Perform 2 semaphore put operations to resume both threads. */ status = tx_semaphore_ceiling_put(&semaphore_0, 2); status += tx_semaphore_ceiling_put(&semaphore_0, 2); /* Let both threads run again. */ - tx_thread_relinquish(); - + tx_thread_relinquish(); + /* Check the status and the run counter of the other thread. */ if ((status != TX_SUCCESS) || (thread_1_counter != 5) || (thread_2_counter != 3)) { @@ -222,7 +222,7 @@ UINT status; printf("ERROR #11\n"); test_control_return(1); } - + /* Now turn off the semaphore notification. */ status = tx_semaphore_put_notify(&semaphore_0, TX_NULL); @@ -234,7 +234,7 @@ UINT status; /* Put a semaphore on a semaphore that does not have suspension. */ status += tx_semaphore_ceiling_put(&semaphore_1, 2); - + /* Repeat the semaphore ceiling put without notification process! */ /* Place an instance on the semaphore, this should resume the other thread @@ -265,15 +265,15 @@ UINT status; /* At this point, we need to resume thread 2 and relinquish in order to get that thread suspended on the semaphore as well. */ tx_thread_resume(&thread_2); - tx_thread_relinquish(); - + tx_thread_relinquish(); + /* Perform 2 semaphore put operations to resume both threads. */ status = tx_semaphore_ceiling_put(&semaphore_0, 2); status += tx_semaphore_ceiling_put(&semaphore_0, 2); /* Let both threads run again. */ - tx_thread_relinquish(); - + tx_thread_relinquish(); + /* Check the status and the run counter of the other thread. */ if ((status != TX_SUCCESS) || (thread_1_counter != 9) || (thread_2_counter != 5)) { @@ -281,7 +281,7 @@ UINT status; /* Semaphore error. */ printf("ERROR #11a\n"); test_control_return(1); - } + } else { @@ -299,7 +299,7 @@ UINT status; while(1) { - + /* Increment thread run counter. */ thread_1_counter++; @@ -320,7 +320,7 @@ UINT status; while(1) { - + /* Increment thread run counter. */ thread_2_counter++; diff --git a/test/smp/regression/threadx_semaphore_delete_test.c b/test/smp/regression/threadx_semaphore_delete_test.c index f18d31dc..2c9bc1aa 100644 --- a/test/smp/regression/threadx_semaphore_delete_test.c +++ b/test/smp/regression/threadx_semaphore_delete_test.c @@ -54,8 +54,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -67,8 +67,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -80,8 +80,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -106,7 +106,7 @@ CHAR *pointer; /* Setup the semaphore notify callback. */ status = tx_semaphore_put_notify(&semaphore_0, put_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check for status. */ diff --git a/test/smp/regression/threadx_semaphore_information_test.c b/test/smp/regression/threadx_semaphore_information_test.c index a8f6d242..d2e9bd57 100644 --- a/test/smp/regression/threadx_semaphore_information_test.c +++ b/test/smp/regression/threadx_semaphore_information_test.c @@ -45,8 +45,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -185,7 +185,7 @@ ULONG timeouts; /* Attempt to get from semaphore with an instance. Should be successful. */ status = tx_semaphore_get(&semaphore_1, TX_NO_WAIT); - + /* Check status. */ if (status != TX_SUCCESS) { @@ -198,10 +198,10 @@ ULONG timeouts; /* Get semaphore information. */ status = tx_semaphore_info_get(&semaphore_0, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_semaphore_info_get(&semaphore_0, &name, ¤t_value, &first_suspended, &suspended_count, &next_semaphore); - + /* Check status. */ - if ((status != TX_SUCCESS) || (current_value != semaphore_0.tx_semaphore_count) || - (first_suspended != semaphore_0.tx_semaphore_suspension_list) || (suspended_count != semaphore_0.tx_semaphore_suspended_count) || + if ((status != TX_SUCCESS) || (current_value != semaphore_0.tx_semaphore_count) || + (first_suspended != semaphore_0.tx_semaphore_suspension_list) || (suspended_count != semaphore_0.tx_semaphore_suspended_count) || (next_semaphore != semaphore_0.tx_semaphore_created_next)) { @@ -227,9 +227,9 @@ ULONG timeouts; /* Get semaphore performance information. */ status = tx_semaphore_performance_info_get(&semaphore_0, TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_semaphore_performance_info_get(&semaphore_0, &puts, &gets, &suspensions, &timeouts); - + /* Check status. */ - if ((status != TX_SUCCESS) || (puts != semaphore_0.tx_semaphore_performance_put_count) || (gets != semaphore_0.tx_semaphore_performance_get_count) || + if ((status != TX_SUCCESS) || (puts != semaphore_0.tx_semaphore_performance_put_count) || (gets != semaphore_0.tx_semaphore_performance_get_count) || (suspensions != semaphore_0.tx_semaphore_performance_suspension_count) || (timeouts != semaphore_0.tx_semaphore_performance_timeout_count)) { @@ -237,13 +237,13 @@ ULONG timeouts; printf("ERROR #13\n"); test_control_return(1); } - + /* Get semaphore system performance information. */ status = tx_semaphore_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_semaphore_performance_system_info_get(&puts, &gets, &suspensions, &timeouts); - + /* Check status. */ - if ((status != TX_SUCCESS) || (puts != _tx_semaphore_performance_put_count) || (gets != _tx_semaphore_performance_get_count) || + if ((status != TX_SUCCESS) || (puts != _tx_semaphore_performance_put_count) || (gets != _tx_semaphore_performance_get_count) || (suspensions != _tx_semaphore_performance_suspension_count) || (timeouts != _tx_semaphore_performance_timeout_count)) { diff --git a/test/smp/regression/threadx_semaphore_non_preemption_test.c b/test/smp/regression/threadx_semaphore_non_preemption_test.c index 40219546..c075b16c 100644 --- a/test/smp/regression/threadx_semaphore_non_preemption_test.c +++ b/test/smp/regression/threadx_semaphore_non_preemption_test.c @@ -55,8 +55,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -68,8 +68,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -81,8 +81,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -107,7 +107,7 @@ CHAR *pointer; /* Setup the semaphore notify callback. */ status = tx_semaphore_put_notify(&semaphore_0, put_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check for status. */ @@ -201,15 +201,15 @@ UINT status; /* At this point, we need to resume thread 2 and relinquish in order to get that thread suspended on the semaphore as well. */ tx_thread_resume(&thread_2); - tx_thread_relinquish(); - + tx_thread_relinquish(); + /* Perform 2 semaphore put operations to resume both threads. */ status = tx_semaphore_put(&semaphore_0); status += tx_semaphore_put(&semaphore_0); /* Let both threads run again. */ - tx_thread_relinquish(); - + tx_thread_relinquish(); + /* Check the status and the run counter of the other thread. */ if ((status != TX_SUCCESS) || (thread_1_counter != 5) || (thread_2_counter != 3)) { @@ -235,7 +235,7 @@ UINT status; while(1) { - + /* Increment thread run counter. */ thread_1_counter++; @@ -256,7 +256,7 @@ UINT status; while(1) { - + /* Increment thread run counter. */ thread_2_counter++; diff --git a/test/smp/regression/threadx_semaphore_preemption_test.c b/test/smp/regression/threadx_semaphore_preemption_test.c index 347042bc..f14193a2 100644 --- a/test/smp/regression/threadx_semaphore_preemption_test.c +++ b/test/smp/regression/threadx_semaphore_preemption_test.c @@ -51,8 +51,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -64,8 +64,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -90,7 +90,7 @@ CHAR *pointer; /* Setup the semaphore notify callback. */ status = tx_semaphore_put_notify(&semaphore_0, put_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check for status. */ diff --git a/test/smp/regression/threadx_semaphore_prioritize.c b/test/smp/regression/threadx_semaphore_prioritize.c index 79622667..6bee4656 100644 --- a/test/smp/regression/threadx_semaphore_prioritize.c +++ b/test/smp/regression/threadx_semaphore_prioritize.c @@ -75,12 +75,12 @@ static void test_isr(void) } else { - + /* Abort the wait of thread 5. */ tx_thread_wait_abort(&thread_5); /* End the ISR processing. */ - test_status = 2; + test_status = 2; test_isr_dispatch = TX_NULL; } } @@ -113,8 +113,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -126,8 +126,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -139,8 +139,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -152,8 +152,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 3, 3, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -165,8 +165,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 4, 4, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -178,8 +178,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, TEST_STACK_SIZE_PRINTF, 5, 5, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -191,8 +191,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, + pointer, TEST_STACK_SIZE_PRINTF, 6, 6, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -206,7 +206,7 @@ CHAR *pointer; /* Create the semaphore with no instances. */ status = tx_semaphore_create(&semaphore_0, "semaphore 0", 0); - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -217,7 +217,7 @@ CHAR *pointer; /* Setup the semaphore notify callback. */ status = tx_semaphore_put_notify(&semaphore_0, put_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check for status. */ @@ -334,7 +334,7 @@ UINT status; printf("ERROR #15a\n"); test_control_return(1); } - + /* At this point we are going to get more than 2 threads suspended. */ tx_thread_resume(&thread_1); tx_thread_resume(&thread_2); @@ -345,7 +345,7 @@ UINT status; /* Prioritize the semaphore suspension list. */ status = tx_semaphore_prioritize(&semaphore_0); - + /* Check status and make sure thread 3 is now at the front of the suspension list. */ if ((status != TX_SUCCESS) || (semaphore_0.tx_semaphore_suspension_list != &thread_3)) { @@ -354,10 +354,10 @@ UINT status; printf("ERROR #16\n"); test_control_return(1); } - + /* Now loop to test the interrupt of the prioritize loop logic. */ test_status = 1; - test_isr_dispatch = test_isr; + test_isr_dispatch = test_isr; do { diff --git a/test/smp/regression/threadx_semaphore_thread_terminate_test.c b/test/smp/regression/threadx_semaphore_thread_terminate_test.c index b8beeff2..a15f5963 100644 --- a/test/smp/regression/threadx_semaphore_thread_terminate_test.c +++ b/test/smp/regression/threadx_semaphore_thread_terminate_test.c @@ -55,8 +55,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -68,8 +68,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -81,8 +81,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -104,10 +104,10 @@ CHAR *pointer; printf("Running Semaphore Thread Terminate Test............................. ERROR #4\n"); test_control_return(1); } - + /* Setup the semaphore notify callback. */ status = tx_semaphore_put_notify(&semaphore_0, put_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check for status. */ diff --git a/test/smp/regression/threadx_semaphore_timeout_test.c b/test/smp/regression/threadx_semaphore_timeout_test.c index 55cd8a96..660891c9 100644 --- a/test/smp/regression/threadx_semaphore_timeout_test.c +++ b/test/smp/regression/threadx_semaphore_timeout_test.c @@ -45,8 +45,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -68,10 +68,10 @@ CHAR *pointer; printf("Running Semaphore Suspension Timeout Test........................... ERROR #2\n"); test_control_return(1); } - + /* Setup the semaphore notify callback. */ status = tx_semaphore_put_notify(&semaphore_0, put_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check for status. */ diff --git a/test/smp/regression/threadx_smp_multiple_threads_one_core_test.c b/test/smp/regression/threadx_smp_multiple_threads_one_core_test.c index 2ca5b947..533837bb 100644 --- a/test/smp/regression/threadx_smp_multiple_threads_one_core_test.c +++ b/test/smp/regression/threadx_smp_multiple_threads_one_core_test.c @@ -67,8 +67,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 0, 0, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_0, 0xE); /* Core 0 only! */ @@ -81,8 +81,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 1, 1, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_1, 0xD); /* Only core 1! */ @@ -95,8 +95,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 2, 2, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_2, 0xB); /* Only core 2! */ @@ -109,8 +109,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 2, 2, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_3, 0x7); /* Only core 3! */ @@ -123,8 +123,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 2, 2, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_4, 0xE); /* Only core 0! */ @@ -137,8 +137,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 2, 2, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_5, 0xD); /* Only core 1! */ @@ -151,8 +151,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 2, 2, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_6, 0xB); /* Only core 2! */ @@ -165,8 +165,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_7, "thread 7", thread_7_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_7, "thread 7", thread_7_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 2, 2, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_7, 0x7); /* Only core 3! */ @@ -219,7 +219,7 @@ UINT status; /* Determine if the test was successful or there was an error. */ if ((status != TX_SUCCESS) || (error) || (thread_1_counter != 1) || (tx_thread_smp_core_get() != 0) || - (thread_2_counter != 1) || (thread_3_counter != 1) || (thread_4_counter != 1) || + (thread_2_counter != 1) || (thread_3_counter != 1) || (thread_4_counter != 1) || (thread_5_counter != 1) || (thread_6_counter != 1) || (thread_7_counter != 1)) { @@ -229,7 +229,7 @@ UINT status; } else { - + /* Successful test. */ printf("SUCCESS!\n"); test_control_return(0); @@ -245,7 +245,7 @@ static void thread_1_entry(ULONG thread_input) /* Ensure this thread is on the correct core. */ if (tx_thread_smp_core_get() != 1) error++; - + thread_1_counter++; tx_thread_suspend(&thread_1); } @@ -257,7 +257,7 @@ static void thread_2_entry(ULONG thread_input) while(1) { - + /* Ensure this thread is on the correct core. */ if (tx_thread_smp_core_get() != 2) error++; @@ -273,7 +273,7 @@ static void thread_3_entry(ULONG thread_input) while(1) { - + /* Ensure this thread is on the correct core. */ if (tx_thread_smp_core_get() != 3) error++; @@ -289,7 +289,7 @@ static void thread_4_entry(ULONG thread_input) while(1) { - + /* Ensure this thread is on the correct core. */ if (tx_thread_smp_core_get() != 0) error++; @@ -305,7 +305,7 @@ static void thread_5_entry(ULONG thread_input) while(1) { - + /* Ensure this thread is on the correct core. */ if (tx_thread_smp_core_get() != 1) error++; @@ -321,7 +321,7 @@ static void thread_6_entry(ULONG thread_input) while(1) { - + /* Ensure this thread is on the correct core. */ if (tx_thread_smp_core_get() != 2) error++; @@ -337,7 +337,7 @@ static void thread_7_entry(ULONG thread_input) while(1) { - + /* Ensure this thread is on the correct core. */ if (tx_thread_smp_core_get() != 3) error++; diff --git a/test/smp/regression/threadx_smp_non_trivial_scheduling_test.c b/test/smp/regression/threadx_smp_non_trivial_scheduling_test.c index ded600da..4a0feec2 100644 --- a/test/smp/regression/threadx_smp_non_trivial_scheduling_test.c +++ b/test/smp/regression/threadx_smp_non_trivial_scheduling_test.c @@ -57,8 +57,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 0, 0, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_0, 0xE); /* Only allow core 0 for now */ @@ -71,8 +71,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 1, 1, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_1, 0x9); /* Exclude core 2 and 1 */ @@ -85,8 +85,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 2, 2, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_2, 0xB); /* Exclude core 3, 1 and 0 */ @@ -99,8 +99,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 3, 3, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_3, 0xE); /* Exclude core 0 */ @@ -156,7 +156,7 @@ UINT original_threshold; /* Determine if the test was successful or there was an error. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) { /* Execution error. */ @@ -169,7 +169,7 @@ UINT original_threshold; /* Determine if the test was successful or there was an error. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != TX_NULL)) { /* Execution error. */ @@ -182,7 +182,7 @@ UINT original_threshold; /* Determine if the test was successful or there was an error. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != TX_NULL)) { /* Execution error. */ @@ -195,7 +195,7 @@ UINT original_threshold; /* Determine if the test was successful or there was an error. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_3) || (_tx_thread_execute_ptr[1] != &thread_0) - || (_tx_thread_execute_ptr[2] != &thread_1) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != &thread_1) || (_tx_thread_execute_ptr[3] != TX_NULL)) { /* Execution error. */ @@ -206,21 +206,21 @@ UINT original_threshold; /* Now suspend threads 3 and 1. */ status = tx_thread_suspend(&thread_3); status += tx_thread_suspend(&thread_1); - + /* Use preemption-threshold to test the rebalance routine. */ status += tx_thread_preemption_change(&thread_3, 2, &original_threshold); /* Move thread 0 back to core 0 and then allow core 1 again. */ status += tx_thread_smp_core_exclude(&thread_0, 0xE); status += tx_thread_smp_core_exclude(&thread_0, 0xC); - + /* Make sure threads 1 defaults to core 1. */ status += tx_thread_smp_core_exclude(&thread_1, 0xD); status += tx_thread_smp_core_exclude(&thread_1, 0x9); /* Determine if the test was successful or there was an error. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != TX_NULL) - || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) { /* Execution error. */ @@ -233,7 +233,7 @@ UINT original_threshold; /* Determine if the test was successful or there was an error. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) { /* Execution error. */ @@ -246,7 +246,7 @@ UINT original_threshold; /* Determine if the test was successful or there was an error. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != TX_NULL)) { /* Execution error. */ @@ -259,7 +259,7 @@ UINT original_threshold; /* Determine if the test was successful or there was an error. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != TX_NULL)) { /* Execution error. */ @@ -270,16 +270,16 @@ UINT original_threshold; /* Suspend thread 2 and cause a rebalance of the execution list. */ status = tx_thread_suspend(&thread_2); - /* With preemption-threshold disabled, thread_3 can not run since preemption-threshold is set to 0 and there is already a + /* With preemption-threshold disabled, thread_3 can not run since preemption-threshold is set to 0 and there is already a zero priority thread running. */ -#ifndef TX_DISABLE_PREEMPTION_THRESHOLD +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD /* Determine if the test was successful or there was an error. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_3) || (_tx_thread_execute_ptr[1] != &thread_0) - || (_tx_thread_execute_ptr[2] != &thread_1) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != &thread_1) || (_tx_thread_execute_ptr[3] != TX_NULL)) #else /* Determine if the test was successful or there was an error. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) #endif { @@ -292,14 +292,14 @@ UINT original_threshold; status = tx_thread_suspend(&thread_3); status += tx_thread_suspend(&thread_1); -#ifndef TX_DISABLE_PREEMPTION_THRESHOLD +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD /* Determine if the test was successful or there was an error. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != TX_NULL) || (_tx_thread_execute_ptr[1] != &thread_0) - || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) #else /* Determine if the test was successful or there was an error. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != TX_NULL) - || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) #endif { @@ -309,7 +309,7 @@ UINT original_threshold; } else { - + /* Successful test. */ printf("SUCCESS!\n"); test_control_return(0); diff --git a/test/smp/regression/threadx_smp_one_thread_dynamic_exclusion_test.c b/test/smp/regression/threadx_smp_one_thread_dynamic_exclusion_test.c index 82caeefa..34a6f9e4 100644 --- a/test/smp/regression/threadx_smp_one_thread_dynamic_exclusion_test.c +++ b/test/smp/regression/threadx_smp_one_thread_dynamic_exclusion_test.c @@ -46,8 +46,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 0, 0, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_0, 0x0); /* No exclusions! */ @@ -136,7 +136,7 @@ UINT status; } else { - + /* Successful test. */ printf("SUCCESS!\n"); test_control_return(0); diff --git a/test/smp/regression/threadx_smp_preemption_threshold_test.c b/test/smp/regression/threadx_smp_preemption_threshold_test.c index 920c89b1..50a696a4 100644 --- a/test/smp/regression/threadx_smp_preemption_threshold_test.c +++ b/test/smp/regression/threadx_smp_preemption_threshold_test.c @@ -64,8 +64,8 @@ UINT i; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 0, 0, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_0, 0xE); /* Core 0 only! */ @@ -78,8 +78,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 1, 1, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_1, 0); /* Any core! */ @@ -92,8 +92,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_5, "thread 5", thread_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_5, "thread 5", thread_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 5, 5, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_5, 0); /* Any core! */ @@ -106,8 +106,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_16, "thread 16", thread_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_16, "thread 16", thread_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_16, 0); /* Any core! */ @@ -120,8 +120,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_16_pt5, "thread 16 PT5", thread_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_16_pt5, "thread 16 PT5", thread_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 16, 5, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_16_pt5, 0); /* Any core! */ @@ -134,8 +134,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_18, "thread 18", thread_entry, 5, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_18, "thread 18", thread_entry, 5, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_18, 0); /* Any core! */ @@ -148,8 +148,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_23_pt17, "thread 23 PT17", thread_entry, 6, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_23_pt17, "thread 23 PT17", thread_entry, 6, + pointer, TEST_STACK_SIZE_PRINTF, 23, 17, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_23_pt17, 0); /* Any core! */ @@ -162,8 +162,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_25, "thread 25", thread_entry, 7, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_25, "thread 25", thread_entry, 7, + pointer, TEST_STACK_SIZE_PRINTF, 25, 25, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_25, 0); /* Any core! */ @@ -176,8 +176,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_27_pt24, "thread 27 PT24", thread_entry, 8, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_27_pt24, "thread 27 PT24", thread_entry, 8, + pointer, TEST_STACK_SIZE_PRINTF, 27, 24, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_27_pt24, 0); /* Any core! */ @@ -190,8 +190,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_31, "thread 31", thread_entry, 9, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_31, "thread 31", thread_entry, 9, + pointer, TEST_STACK_SIZE_PRINTF, 31, 31, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_31, 0); /* Any core! */ @@ -237,27 +237,27 @@ UINT status; printf("Running SMP Preemption-Threshold Test............................... "); /* This test is only useful when preemption-threshold is enabled. */ -#ifndef TX_DISABLE_PREEMPTION_THRESHOLD +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD /* Resume thread. */ status = tx_thread_resume(&thread_31); delay(9); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_31) - || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) { /* Execution error. */ printf("ERROR #12\n"); test_control_return(1); } - + /* Resume thread. */ status = tx_thread_resume(&thread_27_pt24); delay(8); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_27_pt24) - || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) { /* Execution error. */ @@ -270,7 +270,7 @@ UINT status; delay(6); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_23_pt17) - || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) { /* Execution error. */ @@ -283,7 +283,7 @@ UINT status; delay(4); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_16_pt5) - || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) { /* Execution error. */ @@ -295,7 +295,7 @@ UINT status; status = tx_thread_resume(&thread_16); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_16_pt5) - || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) { /* Execution error. */ @@ -307,7 +307,7 @@ UINT status; status = tx_thread_resume(&thread_25); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_16_pt5) - || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) { /* Execution error. */ @@ -319,7 +319,7 @@ UINT status; status = tx_thread_resume(&thread_18); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_16_pt5) - || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) { /* Execution error. */ @@ -331,7 +331,7 @@ UINT status; status = tx_thread_resume(&thread_5); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_16_pt5) - || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) { /* Execution error. */ @@ -343,7 +343,7 @@ UINT status; status = tx_thread_resume(&thread_1); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_16_pt5) - || (_tx_thread_execute_ptr[2] != &thread_1) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != &thread_1) || (_tx_thread_execute_ptr[3] != TX_NULL)) { /* Execution error. */ @@ -353,29 +353,29 @@ UINT status; /* Suspend Thread 16 pt5. */ status = tx_thread_suspend(&thread_16_pt5); - + delay(2); delay(3); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_5) - || (_tx_thread_execute_ptr[2] != &thread_1) || (_tx_thread_execute_ptr[3] != &thread_16)) + || (_tx_thread_execute_ptr[2] != &thread_1) || (_tx_thread_execute_ptr[3] != &thread_16)) { /* Execution error. */ printf("ERROR #21\n"); test_control_return(1); } - + /* Suspend Thread 16. */ status = tx_thread_suspend(&thread_16); - + delay(6); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_5) - || (_tx_thread_execute_ptr[2] != &thread_1) || (_tx_thread_execute_ptr[3] != &thread_23_pt17)) + || (_tx_thread_execute_ptr[2] != &thread_1) || (_tx_thread_execute_ptr[3] != &thread_23_pt17)) { /* Execution error. */ @@ -385,12 +385,12 @@ UINT status; /* Suspend Thread 23 pt 17. */ status = tx_thread_suspend(&thread_23_pt17); - + delay(5); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_5) - || (_tx_thread_execute_ptr[2] != &thread_1) || (_tx_thread_execute_ptr[3] != &thread_18)) + || (_tx_thread_execute_ptr[2] != &thread_1) || (_tx_thread_execute_ptr[3] != &thread_18)) { /* Execution error. */ @@ -401,12 +401,12 @@ UINT status; /* Suspend Thread 18. */ status = tx_thread_suspend(&thread_18); - + delay(8); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_5) - || (_tx_thread_execute_ptr[2] != &thread_1) || (_tx_thread_execute_ptr[3] != &thread_27_pt24)) + || (_tx_thread_execute_ptr[2] != &thread_1) || (_tx_thread_execute_ptr[3] != &thread_27_pt24)) { /* Execution error. */ @@ -416,12 +416,12 @@ UINT status; /* Suspend Thread 27 pt 24. */ status = tx_thread_suspend(&thread_27_pt24); - + delay(7); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_5) - || (_tx_thread_execute_ptr[2] != &thread_1) || (_tx_thread_execute_ptr[3] != &thread_25)) + || (_tx_thread_execute_ptr[2] != &thread_1) || (_tx_thread_execute_ptr[3] != &thread_25)) { /* Execution error. */ @@ -431,12 +431,12 @@ UINT status; /* Suspend Thread 25. */ status = tx_thread_suspend(&thread_25); - + delay(9); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_5) - || (_tx_thread_execute_ptr[2] != &thread_1) || (_tx_thread_execute_ptr[3] != &thread_31)) + || (_tx_thread_execute_ptr[2] != &thread_1) || (_tx_thread_execute_ptr[3] != &thread_31)) { /* Execution error. */ @@ -446,23 +446,23 @@ UINT status; /* Resume thread 16 pt 5. */ status = tx_thread_resume(&thread_16_pt5); - + /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_5) - || (_tx_thread_execute_ptr[2] != &thread_1) || (_tx_thread_execute_ptr[3] != &thread_31)) + || (_tx_thread_execute_ptr[2] != &thread_1) || (_tx_thread_execute_ptr[3] != &thread_31)) { /* Execution error. */ printf("ERROR #27\n"); test_control_return(1); } - + /* Suspend thread 16 pt 5. */ status = tx_thread_suspend(&thread_16_pt5); - + /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_5) - || (_tx_thread_execute_ptr[2] != &thread_1) || (_tx_thread_execute_ptr[3] != &thread_31)) + || (_tx_thread_execute_ptr[2] != &thread_1) || (_tx_thread_execute_ptr[3] != &thread_31)) { /* Execution error. */ @@ -472,10 +472,10 @@ UINT status; /* Suspend thread 31. */ status = tx_thread_suspend(&thread_31); - + /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_5) - || (_tx_thread_execute_ptr[2] != &thread_1) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != &thread_1) || (_tx_thread_execute_ptr[3] != TX_NULL)) { /* Execution error. */ @@ -485,10 +485,10 @@ UINT status; /* Suspend thread 1. */ status = tx_thread_suspend(&thread_1); - + /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_5) - || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) { /* Execution error. */ @@ -498,10 +498,10 @@ UINT status; /* Suspend thread 5. */ status = tx_thread_suspend(&thread_5); - + /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != TX_NULL) - || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) { /* Execution error. */ @@ -512,7 +512,7 @@ UINT status; /* Successful test. */ printf("SUCCESS!\n"); - + test_control_return(0); } @@ -525,8 +525,8 @@ static void thread_entry(ULONG thread_input) while(1) { - - tx_thread_identify(); + + tx_thread_identify(); /* Indicate the thread is running... */ thread_run_counter[thread_input]++; diff --git a/test/smp/regression/threadx_smp_random_resume_suspend_exclusion_pt_test.c b/test/smp/regression/threadx_smp_random_resume_suspend_exclusion_pt_test.c index cc2ecca0..db174ef2 100644 --- a/test/smp/regression/threadx_smp_random_resume_suspend_exclusion_pt_test.c +++ b/test/smp/regression/threadx_smp_random_resume_suspend_exclusion_pt_test.c @@ -2119,9 +2119,9 @@ UINT status; pointer = (CHAR *) first_unused_memory; /* Create a control thread to run the test. */ - status = tx_thread_create(&control_thread, "control thread", control_thread_entry, 0, - pointer, 1024, - 0, 0, TX_NO_TIME_SLICE, TX_AUTO_START); + status = tx_thread_create(&control_thread, "control thread", control_thread_entry, 0, + pointer, 1024, + 0, 0, TX_NO_TIME_SLICE, TX_AUTO_START); /* Check status. */ if (status != TX_SUCCESS) @@ -2153,7 +2153,7 @@ UINT status; /* Clear mapping error flag. */ mapping_error = TX_FALSE; - + /* Clear the preemption-threshold error flag. */ preemption_threshold_error = TX_FALSE; @@ -2168,10 +2168,10 @@ UINT status; { /* Create each thread. */ - status += tx_thread_create(_smp_randomized_source_array[i], "test thread", thread_entry, i, -// (void *) pointer, 512, + status += tx_thread_create(_smp_randomized_source_array[i], "test thread", thread_entry, i, +// (void *) pointer, 512, malloc(1024), 1024, - priority, priority, TX_NO_TIME_SLICE, TX_DONT_START); + priority, priority, TX_NO_TIME_SLICE, TX_DONT_START); // pointer = pointer + 512; /* Check status. */ @@ -2186,7 +2186,7 @@ UINT status; /* Move to next entry/priority. */ i++; priority++; - + /* Should priority be reset? */ if (priority >= TX_MAX_PRIORITIES) { @@ -2209,21 +2209,21 @@ UINT status; status += tx_thread_resume(&thread_4); status += tx_thread_resume(&thread_22); status += tx_thread_resume(&thread_2); - + /* Call rebalance directly. */ TX_DISABLE _tx_thread_smp_rebalance_execute_list(0); TX_RESTORE - + status += tx_thread_sleep(4); - + /* Check status and make sure all the threads ran and suspended. */ - if ((status != TX_SUCCESS) || (thread_2.tx_thread_run_count == 0) || + if ((status != TX_SUCCESS) || (thread_2.tx_thread_run_count == 0) || (thread_4.tx_thread_run_count == 0) || (thread_16.tx_thread_run_count == 0) || (thread_22.tx_thread_run_count == 0)) { - + printf("ERROR #3\n"); test_control_return(1); } @@ -2234,18 +2234,18 @@ UINT status; status += tx_thread_smp_core_exclude(&thread_16, 0); status += tx_thread_smp_core_exclude(&thread_22, 0); status += tx_thread_preemption_change(&thread_4, 4, &original_threshold); - status += tx_thread_preemption_change(&thread_16, 16, &original_threshold); - + status += tx_thread_preemption_change(&thread_16, 16, &original_threshold); + /* Clear the run counters. */ thread_2.tx_thread_run_count = 0; thread_4.tx_thread_run_count = 0; thread_16.tx_thread_run_count = 0; thread_22.tx_thread_run_count = 0; - + /* Check status. */ - if (status != TX_SUCCESS) + if (status != TX_SUCCESS) { - + printf("ERROR #4\n"); test_control_return(1); } @@ -2256,20 +2256,20 @@ UINT status; end_pass = start_pass + MAX_PASSES; do { - + /* Clear the randomized test array. */ for (i = 0; i < (TX_THREAD_SMP_MAX_CORES*2); i++) { _smp_randomized_test_array[i] = TX_NULL; - } - + } + /* Build the randomized test array. */ for (i = 0; i < (TX_THREAD_SMP_MAX_CORES*2); i++) { do { source_index = (rand())%1024; - + /* Determine if this index has repeated. */ thread_ptr = _smp_randomized_source_array[source_index]; @@ -2282,19 +2282,19 @@ UINT status; { j = (TX_THREAD_SMP_MAX_CORES*2); } - + /* Determine if we have a duplicate. */ if (_smp_randomized_test_array[j] == thread_ptr) thread_ptr = TX_NULL; - + j++; } - + } while (thread_ptr == TX_NULL); - + /* Clear run counter. */ thread_ptr -> tx_thread_run_count = 0; - + /* Setup the exclusion for this thread. */ exclusions = (ULONG) (rand()%15); tx_thread_smp_core_exclude(thread_ptr, exclusions); @@ -2310,44 +2310,44 @@ UINT status; /* Save the thread pointer. */ _smp_randomized_test_array[i] = thread_ptr; } - + /* Now make all the random threads ready. */ for (i = 0; i < (TX_THREAD_SMP_MAX_CORES*2); i++) { status = tx_thread_resume(_smp_randomized_test_array[i]); - /* Check for an error. */ + /* Check for an error. */ if (status != TX_SUCCESS) { - + printf("ERROR #5\n"); test_control_return(1); break; - } + } } - + /* Check the status. */ if (status) break; - + /* Move to the lowest priority. */ status += tx_thread_priority_change(current_thread, TX_MAX_PRIORITIES-1, &original_priority); tx_thread_relinquish(); - + /* At this point all the threads have run, or should have. */ - + /* Restore priority. */ status += tx_thread_priority_change(current_thread, original_priority, &original_priority); - + /* Was there an error? */ if (status != TX_SUCCESS) { - + printf("ERROR #6\n"); test_control_return(1); break; - } - + } + /* Determine if all the threads in the the random sample ran. */ for (i = 0; i < (TX_THREAD_SMP_MAX_CORES*2); i++) { @@ -2379,10 +2379,10 @@ UINT status; /* Wait for the thread to complete! */ tx_thread_relinquish(); } - + /* Reset the exclusion for this thread. */ tx_thread_smp_core_exclude(thread_ptr, 0); - + /* Reset preemption-threshold if needed. */ if (thread_ptr -> tx_thread_priority != thread_ptr -> tx_thread_preempt_threshold) { @@ -2390,11 +2390,11 @@ UINT status; /* Change preemption-threshold to enable it. */ tx_thread_preemption_change(thread_ptr, thread_ptr -> tx_thread_priority, &original_threshold); } - + /* Check for mapping error. */ if (mapping_error) { - + /* No, a thread ran on inccorect core! */ printf("ERROR #8\n"); test_control_return(1); @@ -2404,15 +2404,15 @@ UINT status; /* Check for preemption-threshold error. */ if (preemption_threshold_error) { - + /* No, a thread's preemption-threshold was violated! */ printf("ERROR #9\n"); test_control_return(1); break; } - } - + } + /* Increment the pass counter. */ pass++; @@ -2444,17 +2444,17 @@ TX_THREAD *other_thread; /* Get thread. */ thread_ptr = _smp_randomized_source_array[id]; - + /* Determine if this thread is running on a valid core. */ core = tx_thread_smp_core_get(); - + /* Build a bit map for this core. */ core_bit_map = (((ULONG) 1) << core); - + /* Is this a valid core? */ if (core_bit_map & thread_ptr -> tx_thread_smp_cores_excluded) { - + /* Invalid core, set error flag. */ mapping_error = TX_TRUE; } @@ -2462,26 +2462,26 @@ TX_THREAD *other_thread; /* Now check for a preemption-threshold error. */ if (thread_ptr -> tx_thread_priority != thread_ptr -> tx_thread_preempt_threshold) { - + /* Loop through the execute list to determine if any other threads have a priority or preemption-threshold less than this thread. */ for (i = 0; i < TX_THREAD_SMP_MAX_CORES; i++) { - + /* Pickup thread for the core. */ other_thread = _tx_thread_execute_ptr[i]; - + /* Is it this thread? */ if ((other_thread == TX_NULL) || (other_thread == thread_ptr)) continue; - + /* Does this thread violate the preemption-thread of the current thread? */ if (other_thread -> tx_thread_preempt_threshold >= thread_ptr -> tx_thread_preempt_threshold) { - + /* This violated preemption-threshold. Set the flag. */ preemption_threshold_error = TX_TRUE; } - } + } } /* Suspend thread! */ diff --git a/test/smp/regression/threadx_smp_random_resume_suspend_exclusion_test.c b/test/smp/regression/threadx_smp_random_resume_suspend_exclusion_test.c index 6c2f885f..1a02cf19 100644 --- a/test/smp/regression/threadx_smp_random_resume_suspend_exclusion_test.c +++ b/test/smp/regression/threadx_smp_random_resume_suspend_exclusion_test.c @@ -2114,9 +2114,9 @@ UINT status; pointer = (CHAR *) first_unused_memory; /* Create a control thread to run the test. */ - status = tx_thread_create(&control_thread, "control thread", control_thread_entry, 0, - pointer, 1024, - 0, 0, TX_NO_TIME_SLICE, TX_AUTO_START); + status = tx_thread_create(&control_thread, "control thread", control_thread_entry, 0, + pointer, 1024, + 0, 0, TX_NO_TIME_SLICE, TX_AUTO_START); /* Check status. */ if (status != TX_SUCCESS) @@ -2157,10 +2157,10 @@ UINT status; { /* Create each thread. */ - status += tx_thread_create(_smp_randomized_source_array[i], "test thread", thread_entry, i, -// (void *) pointer, 512, + status += tx_thread_create(_smp_randomized_source_array[i], "test thread", thread_entry, i, +// (void *) pointer, 512, malloc(1024), 1024, - priority, priority, TX_NO_TIME_SLICE, TX_DONT_START); + priority, priority, TX_NO_TIME_SLICE, TX_DONT_START); // pointer = pointer + 512; /* Check status. */ @@ -2175,7 +2175,7 @@ UINT status; /* Move to next entry/priority. */ i++; priority++; - + /* Should priority be reset? */ if (priority >= TX_MAX_PRIORITIES) { @@ -2199,8 +2199,8 @@ UINT status; for (i = 0; i < (TX_THREAD_SMP_MAX_CORES*2); i++) { _smp_randomized_test_array[i] = TX_NULL; - } - + } + /* Build the randomized test array. */ for (i = 0; i < (TX_THREAD_SMP_MAX_CORES*2); i++) { @@ -2208,7 +2208,7 @@ UINT status; { source_index = (rand())%1024; - + /* Determine if this index has repeated. */ thread_ptr = _smp_randomized_source_array[source_index]; @@ -2222,19 +2222,19 @@ UINT status; { j = (TX_THREAD_SMP_MAX_CORES*2); } - + /* Determine if we have a duplicate. */ if (_smp_randomized_test_array[j] == thread_ptr) thread_ptr = TX_NULL; - + j++; } - + } while (thread_ptr == TX_NULL); - + /* Clear run counter. */ thread_ptr -> tx_thread_run_count = 0; - + /* Setup the exclusion for this thread. */ exclusions = (ULONG) (rand()%15); tx_thread_smp_core_exclude(thread_ptr, exclusions); @@ -2242,44 +2242,44 @@ UINT status; /* Save the thread pointer. */ _smp_randomized_test_array[i] = thread_ptr; } - + /* Now make all the random threads ready. */ for (i = 0; i < (TX_THREAD_SMP_MAX_CORES*2); i++) { status = tx_thread_resume(_smp_randomized_test_array[i]); - /* Check for an error. */ + /* Check for an error. */ if (status != TX_SUCCESS) { - + printf("ERROR #3\n"); test_control_return(1); break; - } + } } - + /* Check the status. */ if (status) break; - + /* Move to the lowest priority. */ status += tx_thread_priority_change(current_thread, TX_MAX_PRIORITIES-1, &original_priority); tx_thread_relinquish(); - + /* At this point all the threads have run, or should have. */ - + /* Restore priority. */ status += tx_thread_priority_change(current_thread, original_priority, &original_priority); - + /* Was there an error? */ if (status != TX_SUCCESS) { - + printf("ERROR #4\n"); test_control_return(1); break; - } - + } + /* Determine if all the threads in the the random sample ran. */ for (i = 0; i < (TX_THREAD_SMP_MAX_CORES*2); i++) { @@ -2312,21 +2312,21 @@ UINT status; /* Wait for the thread to complete! */ tx_thread_relinquish(); } - + /* Reset the exclusion for this thread. */ tx_thread_smp_core_exclude(thread_ptr, 0); - + /* Check for mapping error. */ if (mapping_error) { - + /* No, this thread ran on inccorect core! */ printf("ERROR #6\n"); test_control_return(1); break; } - } - + } + /* Increment the pass counter. */ pass++; @@ -2351,17 +2351,17 @@ TX_THREAD *thread_ptr; /* Get thread. */ thread_ptr = _smp_randomized_source_array[id]; - + /* Determine if this thread is running on a valid core. */ core = tx_thread_smp_core_get(); - + /* Build a bit map for this core. */ core_bit_map = (((ULONG) 1) << core); - + /* Is this a valid core? */ if (core_bit_map & thread_ptr -> tx_thread_smp_cores_excluded) { - + /* Invalid core, set error flag. */ mapping_error = TX_TRUE; } diff --git a/test/smp/regression/threadx_smp_random_resume_suspend_test.c b/test/smp/regression/threadx_smp_random_resume_suspend_test.c index e7a6dc2c..8098dfe7 100644 --- a/test/smp/regression/threadx_smp_random_resume_suspend_test.c +++ b/test/smp/regression/threadx_smp_random_resume_suspend_test.c @@ -2114,9 +2114,9 @@ UINT status; pointer = (CHAR *) first_unused_memory; /* Create a control thread to run the test. */ - status = tx_thread_create(&control_thread, "control thread", control_thread_entry, 0, - pointer, 1024, - 0, 0, TX_NO_TIME_SLICE, TX_AUTO_START); + status = tx_thread_create(&control_thread, "control thread", control_thread_entry, 0, + pointer, 1024, + 0, 0, TX_NO_TIME_SLICE, TX_AUTO_START); /* Check status. */ if (status != TX_SUCCESS) @@ -2153,10 +2153,10 @@ UINT status; { /* Create each thread. */ - status += tx_thread_create(_smp_randomized_source_array[i], "test thread", thread_entry, i, -// (void *) pointer, 512, + status += tx_thread_create(_smp_randomized_source_array[i], "test thread", thread_entry, i, +// (void *) pointer, 512, malloc(1024), 1024, - priority, priority, TX_NO_TIME_SLICE, TX_DONT_START); + priority, priority, TX_NO_TIME_SLICE, TX_DONT_START); // pointer = pointer + 512; /* Check status. */ @@ -2171,7 +2171,7 @@ UINT status; /* Move to next entry/priority. */ i++; priority++; - + /* Should priority be reset? */ if (priority >= TX_MAX_PRIORITIES) { @@ -2190,20 +2190,20 @@ UINT status; end_pass = start_pass + MAX_PASSES; do { - + /* Clear the randomized test array. */ for (i = 0; i < (TX_THREAD_SMP_MAX_CORES*2); i++) { _smp_randomized_test_array[i] = TX_NULL; - } - + } + /* Build the randomized test array. */ for (i = 0; i < (TX_THREAD_SMP_MAX_CORES*2); i++) { do { source_index = (rand())%1024; - + /* Determine if this index has repeated. */ thread_ptr = _smp_randomized_source_array[source_index]; @@ -2216,60 +2216,60 @@ UINT status; { j = (TX_THREAD_SMP_MAX_CORES*2); } - + /* Determine if we have a duplicate. */ if (_smp_randomized_test_array[j] == thread_ptr) thread_ptr = TX_NULL; - + j++; } - + } while (thread_ptr == TX_NULL); - + /* Clear run counter. */ thread_ptr -> tx_thread_run_count = 0; - + /* Save the thread pointer. */ _smp_randomized_test_array[i] = thread_ptr; } - + /* Now make all the random threads ready. */ for (i = 0; i < (TX_THREAD_SMP_MAX_CORES*2); i++) { status = tx_thread_resume(_smp_randomized_test_array[i]); - /* Check for an error. */ + /* Check for an error. */ if (status != TX_SUCCESS) { - + printf("ERROR #3\n"); test_control_return(1); break; - } + } } - + /* Check the status. */ if (status) break; - + /* Move to the lowest priority. */ status += tx_thread_priority_change(current_thread, TX_MAX_PRIORITIES-1, &original_priority); tx_thread_relinquish(); - + /* At this point all the threads have run, or should have. */ - + /* Restore priority. */ status += tx_thread_priority_change(current_thread, original_priority, &original_priority); - + /* Was there an error? */ if (status != TX_SUCCESS) { - + printf("ERROR #4\n"); test_control_return(1); break; - } - + } + /* Determine if all the threads in the the random sample ran. */ for (i = 0; i < (TX_THREAD_SMP_MAX_CORES*2); i++) { @@ -2301,8 +2301,8 @@ UINT status; /* Wait for the thread to complete! */ tx_thread_relinquish(); } - } - + } + /* Increment the pass counter. */ pass++; diff --git a/test/smp/regression/threadx_smp_rebalance_exclusion_test.c b/test/smp/regression/threadx_smp_rebalance_exclusion_test.c index 9c03c8bd..9fe04bcf 100644 --- a/test/smp/regression/threadx_smp_rebalance_exclusion_test.c +++ b/test/smp/regression/threadx_smp_rebalance_exclusion_test.c @@ -55,8 +55,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 0, 0, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_0, 0x0); /* No exclusions! */ @@ -69,8 +69,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 1, 1, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_1, 0x0); /* No exclusions! */ @@ -83,8 +83,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 2, 2, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_2, 0x0); /* No exclusions! */ @@ -97,8 +97,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_31k, "thread 31k", thread_31k_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_31k, "thread 31k", thread_31k_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 31, 15, 16, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_31k, 0xE); /* Core 0 only! */ @@ -146,7 +146,7 @@ UINT status; tx_thread_sleep(5); /* Determine if the test was successful or there was an error. */ - if ((status != TX_SUCCESS) || (error) || (thread_1_counter != 1) || + if ((status != TX_SUCCESS) || (error) || (thread_1_counter != 1) || (thread_2_counter != 1) || (thread_31k_counter != 1)) { @@ -156,7 +156,7 @@ UINT status; } else { - + /* Successful test. */ printf("SUCCESS!\n"); test_control_return(0); @@ -169,7 +169,7 @@ static void thread_1_entry(ULONG thread_input) while(1) { - + thread_1_counter++; tx_thread_suspend(&thread_1); } @@ -181,7 +181,7 @@ static void thread_2_entry(ULONG thread_input) while(1) { - + thread_2_counter++; tx_thread_suspend(&thread_2); } @@ -193,11 +193,11 @@ static void thread_31k_entry(ULONG thread_input) while(1) { - + /* Ensure this thread is on the correct core. */ if (tx_thread_smp_core_get() != 0) error++; - + thread_31k_counter++; tx_thread_suspend(&thread_31k); } diff --git a/test/smp/regression/threadx_smp_relinquish_test.c b/test/smp/regression/threadx_smp_relinquish_test.c index d7aac1ca..dddb13c2 100644 --- a/test/smp/regression/threadx_smp_relinquish_test.c +++ b/test/smp/regression/threadx_smp_relinquish_test.c @@ -65,8 +65,8 @@ UINT i; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 0, 0, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_0, 0xE); /* Core 0 only! */ @@ -79,8 +79,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_31a, "thread 31a", thread_31a_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_31a, "thread 31a", thread_31a_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 31, 31, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_31a, 0); /* Any core. */ @@ -93,8 +93,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_31b, "thread 31b", thread_31b_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_31b, "thread 31b", thread_31b_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 31, 31, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_31b, 0); /* Any core. */ @@ -108,8 +108,8 @@ UINT i; } - status = tx_thread_create(&thread_31c, "thread 31c", thread_31c_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_31c, "thread 31c", thread_31c_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 31, 31, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_31c, 0); /* Any core. */ @@ -123,8 +123,8 @@ UINT i; } - status = tx_thread_create(&thread_31d, "thread 31d", thread_31d_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_31d, "thread 31d", thread_31d_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 31, 31, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_31d, 0); /* Any core. */ @@ -137,8 +137,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_31e, "thread 31e", thread_31e_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_31e, "thread 31e", thread_31e_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 31, 31, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_31e, 0); /* Any core. */ @@ -151,8 +151,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_31f, "thread 31f", thread_31f_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_31f, "thread 31f", thread_31f_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 31, 31, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_31f, 0); /* Any core. */ @@ -166,8 +166,8 @@ UINT i; } - status = tx_thread_create(&thread_31g, "thread 31g", thread_31g_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_31g, "thread 31g", thread_31g_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 31, 31, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_31g, 0); /* Any core. */ @@ -180,8 +180,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_31h, "thread 31h", thread_31h_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_31h, "thread 31h", thread_31h_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 31, 31, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_31h, 0); /* Any core. */ @@ -242,7 +242,7 @@ UINT status; /* Now sleep for 10 ticks to let see if all the threads execute. */ tx_thread_sleep(10); - + /* Now check and make sure all the threads ran. */ if ((status != TX_SUCCESS) || (thread_31a_counter == 0) || (thread_31b_counter == 0) || (thread_31c_counter == 0) || (thread_31d_counter == 0) || (thread_31e_counter == 0) || (thread_31f_counter == 0) || (thread_31g_counter == 0) || (thread_31h_counter == 0)) @@ -252,10 +252,10 @@ UINT status; printf("ERROR #31\n"); test_control_return(1); } - + /* Successful test. */ printf("SUCCESS!\n"); - + test_control_return(0); } @@ -265,8 +265,8 @@ static void thread_31a_entry(ULONG thread_input) while(1) { - - tx_thread_relinquish(); + + tx_thread_relinquish(); thread_31a_counter++; } @@ -278,8 +278,8 @@ static void thread_31b_entry(ULONG thread_input) while(1) { - - tx_thread_relinquish(); + + tx_thread_relinquish(); thread_31b_counter++; } @@ -291,8 +291,8 @@ static void thread_31c_entry(ULONG thread_input) while(1) { - - tx_thread_relinquish(); + + tx_thread_relinquish(); thread_31c_counter++; } @@ -304,8 +304,8 @@ static void thread_31d_entry(ULONG thread_input) while(1) { - - tx_thread_relinquish(); + + tx_thread_relinquish(); thread_31d_counter++; } @@ -317,8 +317,8 @@ static void thread_31e_entry(ULONG thread_input) while(1) { - - tx_thread_relinquish(); + + tx_thread_relinquish(); thread_31e_counter++; } @@ -330,8 +330,8 @@ static void thread_31f_entry(ULONG thread_input) while(1) { - - tx_thread_relinquish(); + + tx_thread_relinquish(); thread_31f_counter++; } @@ -343,8 +343,8 @@ static void thread_31g_entry(ULONG thread_input) while(1) { - - tx_thread_relinquish(); + + tx_thread_relinquish(); thread_31g_counter++; } @@ -356,8 +356,8 @@ static void thread_31h_entry(ULONG thread_input) while(1) { - - tx_thread_relinquish(); + + tx_thread_relinquish(); thread_31h_counter++; } diff --git a/test/smp/regression/threadx_smp_resume_suspend_accending_order_test.c b/test/smp/regression/threadx_smp_resume_suspend_accending_order_test.c index 3a845878..fe55660a 100644 --- a/test/smp/regression/threadx_smp_resume_suspend_accending_order_test.c +++ b/test/smp/regression/threadx_smp_resume_suspend_accending_order_test.c @@ -86,8 +86,8 @@ UINT i; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 0, 0, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_0, 0xE); /* Core 0 only! */ @@ -100,8 +100,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 1, 1, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_1, 0x0); /* No exclusions! */ @@ -114,8 +114,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 2, 2, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_2, 0x0); /* No exclusions! */ @@ -128,8 +128,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_3, "thread 3", thread_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 3, 3, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_3, 0x0); /* No exclusions! */ @@ -142,8 +142,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_4, "thread 4", thread_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 4, 4, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_4, 0x0); /* No exclusions! */ @@ -156,8 +156,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_5, "thread 5", thread_entry, 5, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_5, "thread 5", thread_entry, 5, + pointer, TEST_STACK_SIZE_PRINTF, 5, 5, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_5, 0x0); /* No exclusions! */ @@ -170,8 +170,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_6, "thread 6", thread_entry, 6, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_6, "thread 6", thread_entry, 6, + pointer, TEST_STACK_SIZE_PRINTF, 6, 6, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_6, 0x0); /* No exclusions! */ @@ -184,8 +184,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_7, "thread 7", thread_entry, 7, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_7, "thread 7", thread_entry, 7, + pointer, TEST_STACK_SIZE_PRINTF, 7, 7, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_7, 0x0); /* No exclusions! */ @@ -198,8 +198,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_8, "thread 8", thread_entry, 8, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_8, "thread 8", thread_entry, 8, + pointer, TEST_STACK_SIZE_PRINTF, 8, 8, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_8, 0x0); /* No exclusions! */ @@ -212,8 +212,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_9, "thread 9", thread_entry, 9, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_9, "thread 9", thread_entry, 9, + pointer, TEST_STACK_SIZE_PRINTF, 9, 9, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_9, 0x0); /* No exclusions! */ @@ -226,8 +226,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_10, "thread 10", thread_entry, 10, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_10, "thread 10", thread_entry, 10, + pointer, TEST_STACK_SIZE_PRINTF, 10, 10, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_10, 0x0); /* No exclusions! */ @@ -240,8 +240,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_11, "thread 11", thread_entry, 11, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_11, "thread 11", thread_entry, 11, + pointer, TEST_STACK_SIZE_PRINTF, 11, 11, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_11, 0x0); /* No exclusions! */ @@ -254,8 +254,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_12, "thread 12", thread_entry, 12, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_12, "thread 12", thread_entry, 12, + pointer, TEST_STACK_SIZE_PRINTF, 12, 12, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_12, 0x0); /* No exclusions! */ @@ -268,8 +268,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_13, "thread 13", thread_entry, 13, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_13, "thread 13", thread_entry, 13, + pointer, TEST_STACK_SIZE_PRINTF, 13, 13, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_13, 0x0); /* No exclusions! */ @@ -282,8 +282,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_14, "thread 14", thread_entry, 14, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_14, "thread 14", thread_entry, 14, + pointer, TEST_STACK_SIZE_PRINTF, 14, 14, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_14, 0x0); /* No exclusions! */ @@ -296,8 +296,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_15, "thread 15", thread_entry, 15, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_15, "thread 15", thread_entry, 15, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_15, 0x0); /* No exclusions! */ @@ -310,8 +310,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_16, "thread 16", thread_entry, 16, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_16, "thread 16", thread_entry, 16, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_16, 0x0); /* No exclusions! */ @@ -324,8 +324,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_17, "thread 17", thread_entry, 17, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_17, "thread 17", thread_entry, 17, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_17, 0x0); /* No exclusions! */ @@ -338,8 +338,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_18, "thread 18", thread_entry, 18, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_18, "thread 18", thread_entry, 18, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_18, 0x0); /* No exclusions! */ @@ -352,8 +352,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_19, "thread 19", thread_entry, 19, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_19, "thread 19", thread_entry, 19, + pointer, TEST_STACK_SIZE_PRINTF, 19, 19, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_19, 0x0); /* No exclusions! */ @@ -366,8 +366,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_20, "thread 20", thread_entry, 20, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_20, "thread 20", thread_entry, 20, + pointer, TEST_STACK_SIZE_PRINTF, 20, 20, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_20, 0x0); /* No exclusions! */ @@ -380,8 +380,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_21, "thread 21", thread_entry, 21, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_21, "thread 21", thread_entry, 21, + pointer, TEST_STACK_SIZE_PRINTF, 21, 21, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_21, 0x0); /* No exclusions! */ @@ -394,8 +394,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_22, "thread 22", thread_entry, 22, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_22, "thread 22", thread_entry, 22, + pointer, TEST_STACK_SIZE_PRINTF, 22, 22, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_22, 0x0); /* No exclusions! */ @@ -408,8 +408,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_23, "thread 23", thread_entry, 23, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_23, "thread 23", thread_entry, 23, + pointer, TEST_STACK_SIZE_PRINTF, 23, 23, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_23, 0x0); /* No exclusions! */ @@ -422,8 +422,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_24, "thread 24", thread_entry, 24, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_24, "thread 24", thread_entry, 24, + pointer, TEST_STACK_SIZE_PRINTF, 24, 24, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_24, 0x0); /* No exclusions! */ @@ -436,8 +436,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_25, "thread 25", thread_entry, 25, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_25, "thread 25", thread_entry, 25, + pointer, TEST_STACK_SIZE_PRINTF, 25, 25, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_25, 0x0); /* No exclusions! */ @@ -450,8 +450,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_26, "thread 26", thread_entry, 26, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_26, "thread 26", thread_entry, 26, + pointer, TEST_STACK_SIZE_PRINTF, 26, 26, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_26, 0x0); /* No exclusions! */ @@ -464,8 +464,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_27, "thread 27", thread_entry, 27, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_27, "thread 27", thread_entry, 27, + pointer, TEST_STACK_SIZE_PRINTF, 27, 27, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_27, 0x0); /* No exclusions! */ @@ -478,8 +478,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_28, "thread 28", thread_entry, 28, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_28, "thread 28", thread_entry, 28, + pointer, TEST_STACK_SIZE_PRINTF, 28, 28, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_28, 0x0); /* No exclusions! */ @@ -492,8 +492,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_29, "thread 29", thread_entry, 29, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_29, "thread 29", thread_entry, 29, + pointer, TEST_STACK_SIZE_PRINTF, 29, 29, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_29, 0x0); /* No exclusions! */ @@ -506,8 +506,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_30, "thread 30", thread_entry, 30, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_30, "thread 30", thread_entry, 30, + pointer, TEST_STACK_SIZE_PRINTF, 30, 30, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_30, 0x0); /* No exclusions! */ @@ -520,8 +520,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_31, "thread 31", thread_entry, 31, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_31, "thread 31", thread_entry, 31, + pointer, TEST_STACK_SIZE_PRINTF, 31, 31, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_31, 0x0); /* No exclusions! */ @@ -571,20 +571,20 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) { /* Execution error. */ printf("ERROR #34\n"); test_control_return(1); } - + /* Resume all the threads. */ status = tx_thread_resume(&thread_2); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != TX_NULL)) { /* Execution error. */ @@ -597,7 +597,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -610,7 +610,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -623,7 +623,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -636,7 +636,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -649,7 +649,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -662,7 +662,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -675,7 +675,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -688,7 +688,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -701,7 +701,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -714,7 +714,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -727,7 +727,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -740,7 +740,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -753,7 +753,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -766,7 +766,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -779,7 +779,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -792,7 +792,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -805,7 +805,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -818,7 +818,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -831,7 +831,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -844,7 +844,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -857,7 +857,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -870,7 +870,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -883,7 +883,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -896,7 +896,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -909,20 +909,20 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ printf("ERROR #60\n"); test_control_return(1); } - + /* Resume all the threads. */ status = tx_thread_resume(&thread_28); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -935,7 +935,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -948,7 +948,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -961,7 +961,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -975,21 +975,21 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_4) - || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_2) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ printf("ERROR #65\n"); test_control_return(1); } - + /* Suspend thread in accending priority. */ delay(2); status = tx_thread_suspend(&thread_2); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_4) - || (_tx_thread_execute_ptr[2] != &thread_5) || (_tx_thread_execute_ptr[3] != &thread_3)) + || (_tx_thread_execute_ptr[2] != &thread_5) || (_tx_thread_execute_ptr[3] != &thread_3)) { /* Execution error. */ @@ -1003,7 +1003,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_4) - || (_tx_thread_execute_ptr[2] != &thread_5) || (_tx_thread_execute_ptr[3] != &thread_6)) + || (_tx_thread_execute_ptr[2] != &thread_5) || (_tx_thread_execute_ptr[3] != &thread_6)) { /* Execution error. */ @@ -1017,7 +1017,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_7) - || (_tx_thread_execute_ptr[2] != &thread_5) || (_tx_thread_execute_ptr[3] != &thread_6)) + || (_tx_thread_execute_ptr[2] != &thread_5) || (_tx_thread_execute_ptr[3] != &thread_6)) { /* Execution error. */ @@ -1031,7 +1031,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_7) - || (_tx_thread_execute_ptr[2] != &thread_8) || (_tx_thread_execute_ptr[3] != &thread_6)) + || (_tx_thread_execute_ptr[2] != &thread_8) || (_tx_thread_execute_ptr[3] != &thread_6)) { /* Execution error. */ @@ -1045,7 +1045,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_7) - || (_tx_thread_execute_ptr[2] != &thread_8) || (_tx_thread_execute_ptr[3] != &thread_9)) + || (_tx_thread_execute_ptr[2] != &thread_8) || (_tx_thread_execute_ptr[3] != &thread_9)) { /* Execution error. */ @@ -1059,7 +1059,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_10) - || (_tx_thread_execute_ptr[2] != &thread_8) || (_tx_thread_execute_ptr[3] != &thread_9)) + || (_tx_thread_execute_ptr[2] != &thread_8) || (_tx_thread_execute_ptr[3] != &thread_9)) { /* Execution error. */ @@ -1073,7 +1073,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_10) - || (_tx_thread_execute_ptr[2] != &thread_11) || (_tx_thread_execute_ptr[3] != &thread_9)) + || (_tx_thread_execute_ptr[2] != &thread_11) || (_tx_thread_execute_ptr[3] != &thread_9)) { /* Execution error. */ @@ -1087,7 +1087,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_10) - || (_tx_thread_execute_ptr[2] != &thread_11) || (_tx_thread_execute_ptr[3] != &thread_12)) + || (_tx_thread_execute_ptr[2] != &thread_11) || (_tx_thread_execute_ptr[3] != &thread_12)) { /* Execution error. */ @@ -1101,7 +1101,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_13) - || (_tx_thread_execute_ptr[2] != &thread_11) || (_tx_thread_execute_ptr[3] != &thread_12)) + || (_tx_thread_execute_ptr[2] != &thread_11) || (_tx_thread_execute_ptr[3] != &thread_12)) { /* Execution error. */ @@ -1115,7 +1115,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_13) - || (_tx_thread_execute_ptr[2] != &thread_14) || (_tx_thread_execute_ptr[3] != &thread_12)) + || (_tx_thread_execute_ptr[2] != &thread_14) || (_tx_thread_execute_ptr[3] != &thread_12)) { /* Execution error. */ @@ -1129,7 +1129,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_13) - || (_tx_thread_execute_ptr[2] != &thread_14) || (_tx_thread_execute_ptr[3] != &thread_15)) + || (_tx_thread_execute_ptr[2] != &thread_14) || (_tx_thread_execute_ptr[3] != &thread_15)) { /* Execution error. */ @@ -1143,49 +1143,49 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_16) - || (_tx_thread_execute_ptr[2] != &thread_14) || (_tx_thread_execute_ptr[3] != &thread_15)) + || (_tx_thread_execute_ptr[2] != &thread_14) || (_tx_thread_execute_ptr[3] != &thread_15)) { /* Execution error. */ printf("ERROR #77\n"); test_control_return(1); } - + /* Suspend thread in accending priority. */ delay(14); status = tx_thread_suspend(&thread_14); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_16) - || (_tx_thread_execute_ptr[2] != &thread_17) || (_tx_thread_execute_ptr[3] != &thread_15)) + || (_tx_thread_execute_ptr[2] != &thread_17) || (_tx_thread_execute_ptr[3] != &thread_15)) { /* Execution error. */ printf("ERROR #78\n"); test_control_return(1); } - + /* Suspend thread in accending priority. */ delay(15); status = tx_thread_suspend(&thread_15); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_16) - || (_tx_thread_execute_ptr[2] != &thread_17) || (_tx_thread_execute_ptr[3] != &thread_18)) + || (_tx_thread_execute_ptr[2] != &thread_17) || (_tx_thread_execute_ptr[3] != &thread_18)) { /* Execution error. */ printf("ERROR #79\n"); test_control_return(1); } - + /* Suspend thread in accending priority. */ delay(16); status = tx_thread_suspend(&thread_16); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_19) - || (_tx_thread_execute_ptr[2] != &thread_17) || (_tx_thread_execute_ptr[3] != &thread_18)) + || (_tx_thread_execute_ptr[2] != &thread_17) || (_tx_thread_execute_ptr[3] != &thread_18)) { /* Execution error. */ @@ -1199,21 +1199,21 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_19) - || (_tx_thread_execute_ptr[2] != &thread_20) || (_tx_thread_execute_ptr[3] != &thread_18)) + || (_tx_thread_execute_ptr[2] != &thread_20) || (_tx_thread_execute_ptr[3] != &thread_18)) { /* Execution error. */ printf("ERROR #81\n"); test_control_return(1); } - + /* Suspend thread in accending priority. */ delay(18); status = tx_thread_suspend(&thread_18); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_19) - || (_tx_thread_execute_ptr[2] != &thread_20) || (_tx_thread_execute_ptr[3] != &thread_21)) + || (_tx_thread_execute_ptr[2] != &thread_20) || (_tx_thread_execute_ptr[3] != &thread_21)) { /* Execution error. */ @@ -1227,7 +1227,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_22) - || (_tx_thread_execute_ptr[2] != &thread_20) || (_tx_thread_execute_ptr[3] != &thread_21)) + || (_tx_thread_execute_ptr[2] != &thread_20) || (_tx_thread_execute_ptr[3] != &thread_21)) { /* Execution error. */ @@ -1241,7 +1241,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_22) - || (_tx_thread_execute_ptr[2] != &thread_23) || (_tx_thread_execute_ptr[3] != &thread_21)) + || (_tx_thread_execute_ptr[2] != &thread_23) || (_tx_thread_execute_ptr[3] != &thread_21)) { /* Execution error. */ @@ -1255,7 +1255,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_22) - || (_tx_thread_execute_ptr[2] != &thread_23) || (_tx_thread_execute_ptr[3] != &thread_24)) + || (_tx_thread_execute_ptr[2] != &thread_23) || (_tx_thread_execute_ptr[3] != &thread_24)) { /* Execution error. */ @@ -1269,7 +1269,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_25) - || (_tx_thread_execute_ptr[2] != &thread_23) || (_tx_thread_execute_ptr[3] != &thread_24)) + || (_tx_thread_execute_ptr[2] != &thread_23) || (_tx_thread_execute_ptr[3] != &thread_24)) { /* Execution error. */ @@ -1283,7 +1283,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_25) - || (_tx_thread_execute_ptr[2] != &thread_26) || (_tx_thread_execute_ptr[3] != &thread_24)) + || (_tx_thread_execute_ptr[2] != &thread_26) || (_tx_thread_execute_ptr[3] != &thread_24)) { /* Execution error. */ @@ -1297,7 +1297,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_25) - || (_tx_thread_execute_ptr[2] != &thread_26) || (_tx_thread_execute_ptr[3] != &thread_27)) + || (_tx_thread_execute_ptr[2] != &thread_26) || (_tx_thread_execute_ptr[3] != &thread_27)) { /* Execution error. */ @@ -1311,7 +1311,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_28) - || (_tx_thread_execute_ptr[2] != &thread_26) || (_tx_thread_execute_ptr[3] != &thread_27)) + || (_tx_thread_execute_ptr[2] != &thread_26) || (_tx_thread_execute_ptr[3] != &thread_27)) { /* Execution error. */ @@ -1325,7 +1325,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_28) - || (_tx_thread_execute_ptr[2] != &thread_29) || (_tx_thread_execute_ptr[3] != &thread_27)) + || (_tx_thread_execute_ptr[2] != &thread_29) || (_tx_thread_execute_ptr[3] != &thread_27)) { /* Execution error. */ @@ -1339,7 +1339,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_28) - || (_tx_thread_execute_ptr[2] != &thread_29) || (_tx_thread_execute_ptr[3] != &thread_30)) + || (_tx_thread_execute_ptr[2] != &thread_29) || (_tx_thread_execute_ptr[3] != &thread_30)) { /* Execution error. */ @@ -1353,7 +1353,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_31) - || (_tx_thread_execute_ptr[2] != &thread_29) || (_tx_thread_execute_ptr[3] != &thread_30)) + || (_tx_thread_execute_ptr[2] != &thread_29) || (_tx_thread_execute_ptr[3] != &thread_30)) { /* Execution error. */ @@ -1367,7 +1367,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_31) - || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != &thread_30)) + || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != &thread_30)) { /* Execution error. */ @@ -1381,7 +1381,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_31) - || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) { /* Execution error. */ @@ -1392,10 +1392,10 @@ UINT status; /* Suspend thread in accending priority. */ delay(31); status = tx_thread_suspend(&thread_31); - + /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != TX_NULL) - || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) { /* Execution error. */ @@ -1403,10 +1403,10 @@ UINT status; test_control_return(1); } - + /* Successful test. */ printf("SUCCESS!\n"); - + test_control_return(0); } @@ -1419,8 +1419,8 @@ static void thread_entry(ULONG thread_input) while(1) { - - tx_thread_identify(); + + tx_thread_identify(); /* Indicate the thread is running... */ thread_run_counter[thread_input]++; diff --git a/test/smp/regression/threadx_smp_resume_suspend_decending_order_test.c b/test/smp/regression/threadx_smp_resume_suspend_decending_order_test.c index 6eae504e..83b6f141 100644 --- a/test/smp/regression/threadx_smp_resume_suspend_decending_order_test.c +++ b/test/smp/regression/threadx_smp_resume_suspend_decending_order_test.c @@ -86,8 +86,8 @@ UINT i; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 0, 0, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_0, 0xE); /* Core 0 only! */ @@ -100,8 +100,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 1, 1, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_1, 0x0); /* No exclusions! */ @@ -114,8 +114,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 2, 2, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_2, 0x0); /* No exclusions! */ @@ -128,8 +128,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_3, "thread 3", thread_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 3, 3, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_3, 0x0); /* No exclusions! */ @@ -142,8 +142,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_4, "thread 4", thread_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 4, 4, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_4, 0x0); /* No exclusions! */ @@ -156,8 +156,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_5, "thread 5", thread_entry, 5, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_5, "thread 5", thread_entry, 5, + pointer, TEST_STACK_SIZE_PRINTF, 5, 5, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_5, 0x0); /* No exclusions! */ @@ -170,8 +170,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_6, "thread 6", thread_entry, 6, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_6, "thread 6", thread_entry, 6, + pointer, TEST_STACK_SIZE_PRINTF, 6, 6, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_6, 0x0); /* No exclusions! */ @@ -184,8 +184,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_7, "thread 7", thread_entry, 7, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_7, "thread 7", thread_entry, 7, + pointer, TEST_STACK_SIZE_PRINTF, 7, 7, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_7, 0x0); /* No exclusions! */ @@ -198,8 +198,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_8, "thread 8", thread_entry, 8, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_8, "thread 8", thread_entry, 8, + pointer, TEST_STACK_SIZE_PRINTF, 8, 8, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_8, 0x0); /* No exclusions! */ @@ -212,8 +212,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_9, "thread 9", thread_entry, 9, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_9, "thread 9", thread_entry, 9, + pointer, TEST_STACK_SIZE_PRINTF, 9, 9, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_9, 0x0); /* No exclusions! */ @@ -226,8 +226,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_10, "thread 10", thread_entry, 10, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_10, "thread 10", thread_entry, 10, + pointer, TEST_STACK_SIZE_PRINTF, 10, 10, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_10, 0x0); /* No exclusions! */ @@ -240,8 +240,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_11, "thread 11", thread_entry, 11, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_11, "thread 11", thread_entry, 11, + pointer, TEST_STACK_SIZE_PRINTF, 11, 11, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_11, 0x0); /* No exclusions! */ @@ -254,8 +254,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_12, "thread 12", thread_entry, 12, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_12, "thread 12", thread_entry, 12, + pointer, TEST_STACK_SIZE_PRINTF, 12, 12, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_12, 0x0); /* No exclusions! */ @@ -268,8 +268,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_13, "thread 13", thread_entry, 13, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_13, "thread 13", thread_entry, 13, + pointer, TEST_STACK_SIZE_PRINTF, 13, 13, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_13, 0x0); /* No exclusions! */ @@ -282,8 +282,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_14, "thread 14", thread_entry, 14, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_14, "thread 14", thread_entry, 14, + pointer, TEST_STACK_SIZE_PRINTF, 14, 14, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_14, 0x0); /* No exclusions! */ @@ -296,8 +296,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_15, "thread 15", thread_entry, 15, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_15, "thread 15", thread_entry, 15, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_15, 0x0); /* No exclusions! */ @@ -310,8 +310,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_16, "thread 16", thread_entry, 16, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_16, "thread 16", thread_entry, 16, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_16, 0x0); /* No exclusions! */ @@ -324,8 +324,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_17, "thread 17", thread_entry, 17, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_17, "thread 17", thread_entry, 17, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_17, 0x0); /* No exclusions! */ @@ -338,8 +338,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_18, "thread 18", thread_entry, 18, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_18, "thread 18", thread_entry, 18, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_18, 0x0); /* No exclusions! */ @@ -352,8 +352,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_19, "thread 19", thread_entry, 19, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_19, "thread 19", thread_entry, 19, + pointer, TEST_STACK_SIZE_PRINTF, 19, 19, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_19, 0x0); /* No exclusions! */ @@ -366,8 +366,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_20, "thread 20", thread_entry, 20, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_20, "thread 20", thread_entry, 20, + pointer, TEST_STACK_SIZE_PRINTF, 20, 20, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_20, 0x0); /* No exclusions! */ @@ -380,8 +380,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_21, "thread 21", thread_entry, 21, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_21, "thread 21", thread_entry, 21, + pointer, TEST_STACK_SIZE_PRINTF, 21, 21, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_21, 0x0); /* No exclusions! */ @@ -394,8 +394,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_22, "thread 22", thread_entry, 22, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_22, "thread 22", thread_entry, 22, + pointer, TEST_STACK_SIZE_PRINTF, 22, 22, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_22, 0x0); /* No exclusions! */ @@ -408,8 +408,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_23, "thread 23", thread_entry, 23, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_23, "thread 23", thread_entry, 23, + pointer, TEST_STACK_SIZE_PRINTF, 23, 23, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_23, 0x0); /* No exclusions! */ @@ -422,8 +422,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_24, "thread 24", thread_entry, 24, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_24, "thread 24", thread_entry, 24, + pointer, TEST_STACK_SIZE_PRINTF, 24, 24, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_24, 0x0); /* No exclusions! */ @@ -436,8 +436,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_25, "thread 25", thread_entry, 25, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_25, "thread 25", thread_entry, 25, + pointer, TEST_STACK_SIZE_PRINTF, 25, 25, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_25, 0x0); /* No exclusions! */ @@ -450,8 +450,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_26, "thread 26", thread_entry, 26, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_26, "thread 26", thread_entry, 26, + pointer, TEST_STACK_SIZE_PRINTF, 26, 26, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_26, 0x0); /* No exclusions! */ @@ -464,8 +464,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_27, "thread 27", thread_entry, 27, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_27, "thread 27", thread_entry, 27, + pointer, TEST_STACK_SIZE_PRINTF, 27, 27, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_27, 0x0); /* No exclusions! */ @@ -478,8 +478,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_28, "thread 28", thread_entry, 28, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_28, "thread 28", thread_entry, 28, + pointer, TEST_STACK_SIZE_PRINTF, 28, 28, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_28, 0x0); /* No exclusions! */ @@ -492,8 +492,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_29, "thread 29", thread_entry, 29, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_29, "thread 29", thread_entry, 29, + pointer, TEST_STACK_SIZE_PRINTF, 29, 29, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_29, 0x0); /* No exclusions! */ @@ -506,8 +506,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_30, "thread 30", thread_entry, 30, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_30, "thread 30", thread_entry, 30, + pointer, TEST_STACK_SIZE_PRINTF, 30, 30, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_30, 0x0); /* No exclusions! */ @@ -520,8 +520,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_31, "thread 31", thread_entry, 31, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_31, "thread 31", thread_entry, 31, + pointer, TEST_STACK_SIZE_PRINTF, 31, 31, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_31, 0x0); /* No exclusions! */ @@ -571,21 +571,21 @@ UINT status; delay(31); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_31) - || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) { /* Execution error. */ printf("ERROR #34\n"); test_control_return(1); } - + /* Resume all the threads. */ status = tx_thread_resume(&thread_30); delay(30); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_31) - || (_tx_thread_execute_ptr[2] != &thread_30) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != &thread_30) || (_tx_thread_execute_ptr[3] != TX_NULL)) { /* Execution error. */ @@ -599,7 +599,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_31) - || (_tx_thread_execute_ptr[2] != &thread_30) || (_tx_thread_execute_ptr[3] != &thread_29)) + || (_tx_thread_execute_ptr[2] != &thread_30) || (_tx_thread_execute_ptr[3] != &thread_29)) { /* Execution error. */ @@ -613,7 +613,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_28) - || (_tx_thread_execute_ptr[2] != &thread_30) || (_tx_thread_execute_ptr[3] != &thread_29)) + || (_tx_thread_execute_ptr[2] != &thread_30) || (_tx_thread_execute_ptr[3] != &thread_29)) { /* Execution error. */ @@ -627,7 +627,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_28) - || (_tx_thread_execute_ptr[2] != &thread_27) || (_tx_thread_execute_ptr[3] != &thread_29)) + || (_tx_thread_execute_ptr[2] != &thread_27) || (_tx_thread_execute_ptr[3] != &thread_29)) { /* Execution error. */ @@ -641,7 +641,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_28) - || (_tx_thread_execute_ptr[2] != &thread_27) || (_tx_thread_execute_ptr[3] != &thread_26)) + || (_tx_thread_execute_ptr[2] != &thread_27) || (_tx_thread_execute_ptr[3] != &thread_26)) { /* Execution error. */ @@ -655,7 +655,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_25) - || (_tx_thread_execute_ptr[2] != &thread_27) || (_tx_thread_execute_ptr[3] != &thread_26)) + || (_tx_thread_execute_ptr[2] != &thread_27) || (_tx_thread_execute_ptr[3] != &thread_26)) { /* Execution error. */ @@ -669,7 +669,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_25) - || (_tx_thread_execute_ptr[2] != &thread_24) || (_tx_thread_execute_ptr[3] != &thread_26)) + || (_tx_thread_execute_ptr[2] != &thread_24) || (_tx_thread_execute_ptr[3] != &thread_26)) { /* Execution error. */ @@ -683,7 +683,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_25) - || (_tx_thread_execute_ptr[2] != &thread_24) || (_tx_thread_execute_ptr[3] != &thread_23)) + || (_tx_thread_execute_ptr[2] != &thread_24) || (_tx_thread_execute_ptr[3] != &thread_23)) { /* Execution error. */ @@ -697,7 +697,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_22) - || (_tx_thread_execute_ptr[2] != &thread_24) || (_tx_thread_execute_ptr[3] != &thread_23)) + || (_tx_thread_execute_ptr[2] != &thread_24) || (_tx_thread_execute_ptr[3] != &thread_23)) { /* Execution error. */ @@ -711,7 +711,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_22) - || (_tx_thread_execute_ptr[2] != &thread_21) || (_tx_thread_execute_ptr[3] != &thread_23)) + || (_tx_thread_execute_ptr[2] != &thread_21) || (_tx_thread_execute_ptr[3] != &thread_23)) { /* Execution error. */ @@ -725,7 +725,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_22) - || (_tx_thread_execute_ptr[2] != &thread_21) || (_tx_thread_execute_ptr[3] != &thread_20)) + || (_tx_thread_execute_ptr[2] != &thread_21) || (_tx_thread_execute_ptr[3] != &thread_20)) { /* Execution error. */ @@ -739,7 +739,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_19) - || (_tx_thread_execute_ptr[2] != &thread_21) || (_tx_thread_execute_ptr[3] != &thread_20)) + || (_tx_thread_execute_ptr[2] != &thread_21) || (_tx_thread_execute_ptr[3] != &thread_20)) { /* Execution error. */ @@ -753,7 +753,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_19) - || (_tx_thread_execute_ptr[2] != &thread_18) || (_tx_thread_execute_ptr[3] != &thread_20)) + || (_tx_thread_execute_ptr[2] != &thread_18) || (_tx_thread_execute_ptr[3] != &thread_20)) { /* Execution error. */ @@ -767,7 +767,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_19) - || (_tx_thread_execute_ptr[2] != &thread_18) || (_tx_thread_execute_ptr[3] != &thread_17)) + || (_tx_thread_execute_ptr[2] != &thread_18) || (_tx_thread_execute_ptr[3] != &thread_17)) { /* Execution error. */ @@ -781,7 +781,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_16) - || (_tx_thread_execute_ptr[2] != &thread_18) || (_tx_thread_execute_ptr[3] != &thread_17)) + || (_tx_thread_execute_ptr[2] != &thread_18) || (_tx_thread_execute_ptr[3] != &thread_17)) { /* Execution error. */ @@ -795,7 +795,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_16) - || (_tx_thread_execute_ptr[2] != &thread_15) || (_tx_thread_execute_ptr[3] != &thread_17)) + || (_tx_thread_execute_ptr[2] != &thread_15) || (_tx_thread_execute_ptr[3] != &thread_17)) { /* Execution error. */ @@ -809,7 +809,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_16) - || (_tx_thread_execute_ptr[2] != &thread_15) || (_tx_thread_execute_ptr[3] != &thread_14)) + || (_tx_thread_execute_ptr[2] != &thread_15) || (_tx_thread_execute_ptr[3] != &thread_14)) { /* Execution error. */ @@ -823,7 +823,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_13) - || (_tx_thread_execute_ptr[2] != &thread_15) || (_tx_thread_execute_ptr[3] != &thread_14)) + || (_tx_thread_execute_ptr[2] != &thread_15) || (_tx_thread_execute_ptr[3] != &thread_14)) { /* Execution error. */ @@ -837,7 +837,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_13) - || (_tx_thread_execute_ptr[2] != &thread_12) || (_tx_thread_execute_ptr[3] != &thread_14)) + || (_tx_thread_execute_ptr[2] != &thread_12) || (_tx_thread_execute_ptr[3] != &thread_14)) { /* Execution error. */ @@ -851,7 +851,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_13) - || (_tx_thread_execute_ptr[2] != &thread_12) || (_tx_thread_execute_ptr[3] != &thread_11)) + || (_tx_thread_execute_ptr[2] != &thread_12) || (_tx_thread_execute_ptr[3] != &thread_11)) { /* Execution error. */ @@ -865,7 +865,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_10) - || (_tx_thread_execute_ptr[2] != &thread_12) || (_tx_thread_execute_ptr[3] != &thread_11)) + || (_tx_thread_execute_ptr[2] != &thread_12) || (_tx_thread_execute_ptr[3] != &thread_11)) { /* Execution error. */ @@ -879,7 +879,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_10) - || (_tx_thread_execute_ptr[2] != &thread_9) || (_tx_thread_execute_ptr[3] != &thread_11)) + || (_tx_thread_execute_ptr[2] != &thread_9) || (_tx_thread_execute_ptr[3] != &thread_11)) { /* Execution error. */ @@ -893,7 +893,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_10) - || (_tx_thread_execute_ptr[2] != &thread_9) || (_tx_thread_execute_ptr[3] != &thread_8)) + || (_tx_thread_execute_ptr[2] != &thread_9) || (_tx_thread_execute_ptr[3] != &thread_8)) { /* Execution error. */ @@ -907,7 +907,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_7) - || (_tx_thread_execute_ptr[2] != &thread_9) || (_tx_thread_execute_ptr[3] != &thread_8)) + || (_tx_thread_execute_ptr[2] != &thread_9) || (_tx_thread_execute_ptr[3] != &thread_8)) { /* Execution error. */ @@ -921,7 +921,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_7) - || (_tx_thread_execute_ptr[2] != &thread_6) || (_tx_thread_execute_ptr[3] != &thread_8)) + || (_tx_thread_execute_ptr[2] != &thread_6) || (_tx_thread_execute_ptr[3] != &thread_8)) { /* Execution error. */ @@ -935,21 +935,21 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_7) - || (_tx_thread_execute_ptr[2] != &thread_6) || (_tx_thread_execute_ptr[3] != &thread_5)) + || (_tx_thread_execute_ptr[2] != &thread_6) || (_tx_thread_execute_ptr[3] != &thread_5)) { /* Execution error. */ printf("ERROR #60\n"); test_control_return(1); } - + /* Resume all the threads. */ status = tx_thread_resume(&thread_4); delay(4); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_4) - || (_tx_thread_execute_ptr[2] != &thread_6) || (_tx_thread_execute_ptr[3] != &thread_5)) + || (_tx_thread_execute_ptr[2] != &thread_6) || (_tx_thread_execute_ptr[3] != &thread_5)) { /* Execution error. */ @@ -963,7 +963,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_4) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_5)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_5)) { /* Execution error. */ @@ -977,7 +977,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_4) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ @@ -991,7 +991,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ @@ -1004,20 +1004,20 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ printf("ERROR #65\n"); test_control_return(1); } - + /* Suspend thread in accending priority. */ status = tx_thread_suspend(&thread_30); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ @@ -1030,7 +1030,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ @@ -1043,7 +1043,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ @@ -1056,7 +1056,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ @@ -1069,7 +1069,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ @@ -1082,7 +1082,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ @@ -1095,7 +1095,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ @@ -1108,7 +1108,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ @@ -1121,7 +1121,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ @@ -1134,7 +1134,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ @@ -1147,7 +1147,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ @@ -1160,46 +1160,46 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ printf("ERROR #77\n"); test_control_return(1); } - + /* Suspend thread in accending priority. */ status = tx_thread_suspend(&thread_18); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ printf("ERROR #78\n"); test_control_return(1); } - + /* Suspend thread in accending priority. */ status = tx_thread_suspend(&thread_17); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ printf("ERROR #79\n"); test_control_return(1); } - + /* Suspend thread in accending priority. */ status = tx_thread_suspend(&thread_16); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ @@ -1212,20 +1212,20 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ printf("ERROR #81\n"); test_control_return(1); } - + /* Suspend thread in accending priority. */ status = tx_thread_suspend(&thread_14); /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ @@ -1238,7 +1238,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ @@ -1251,7 +1251,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ @@ -1264,7 +1264,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ @@ -1277,7 +1277,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ @@ -1290,7 +1290,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ @@ -1303,7 +1303,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ @@ -1316,7 +1316,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ @@ -1329,7 +1329,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ @@ -1342,7 +1342,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ @@ -1355,7 +1355,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != &thread_3) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ @@ -1368,7 +1368,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != &thread_2)) + || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != &thread_2)) { /* Execution error. */ @@ -1381,7 +1381,7 @@ UINT status; /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != &thread_1) - || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) { /* Execution error. */ @@ -1391,10 +1391,10 @@ UINT status; /* Suspend thread in accending priority. */ status = tx_thread_suspend(&thread_1); - + /* Check for the correct results. */ if ((status != TX_SUCCESS) || (_tx_thread_execute_ptr[0] != &thread_0) || (_tx_thread_execute_ptr[1] != TX_NULL) - || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) + || (_tx_thread_execute_ptr[2] != TX_NULL) || (_tx_thread_execute_ptr[3] != TX_NULL)) { /* Execution error. */ @@ -1402,10 +1402,10 @@ UINT status; test_control_return(1); } - + /* Successful test. */ printf("SUCCESS!\n"); - + test_control_return(0); } @@ -1418,8 +1418,8 @@ static void thread_entry(ULONG thread_input) while(1) { - - tx_thread_identify(); + + tx_thread_identify(); /* Indicate the thread is running... */ thread_run_counter[thread_input]++; diff --git a/test/smp/regression/threadx_smp_time_slice_test.c b/test/smp/regression/threadx_smp_time_slice_test.c index b58f789f..fe97590a 100644 --- a/test/smp/regression/threadx_smp_time_slice_test.c +++ b/test/smp/regression/threadx_smp_time_slice_test.c @@ -65,8 +65,8 @@ UINT i; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 0, 0, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_0, 0xE); /* Core 0 only! */ @@ -79,8 +79,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_31a, "thread 31a", thread_31a_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_31a, "thread 31a", thread_31a_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 31, 31, 1, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_31a, 0); /* Any core. */ @@ -93,8 +93,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_31b, "thread 31b", thread_31b_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_31b, "thread 31b", thread_31b_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 31, 31, 1, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_31b, 0); /* Any core. */ @@ -108,8 +108,8 @@ UINT i; } - status = tx_thread_create(&thread_31c, "thread 31c", thread_31c_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_31c, "thread 31c", thread_31c_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 31, 31, 1, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_31c, 0); /* Any core. */ @@ -123,8 +123,8 @@ UINT i; } - status = tx_thread_create(&thread_31d, "thread 31d", thread_31d_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_31d, "thread 31d", thread_31d_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 31, 31, 1, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_31d, 0); /* Any core. */ @@ -137,8 +137,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_31e, "thread 31e", thread_31e_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_31e, "thread 31e", thread_31e_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 31, 31, 1, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_31e, 0); /* Any core. */ @@ -151,8 +151,8 @@ UINT i; test_control_return(1); } - status = tx_thread_create(&thread_31f, "thread 31f", thread_31f_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_31f, "thread 31f", thread_31f_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 31, 31, 1, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_31f, 0); /* Any core. */ @@ -166,8 +166,8 @@ UINT i; } - status = tx_thread_create(&thread_31g, "thread 31g", thread_31g_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_31g, "thread 31g", thread_31g_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 31, 31, 1, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_31g, 0); /* Any core. */ @@ -183,8 +183,8 @@ UINT i; /* Enable preemption-threshold for this thread to hit branch in tx_thread_time_slice where the expired time-slice thread is replaced by a thread with preemption-threshold enabled. */ - status = tx_thread_create(&thread_31h, "thread 31h", thread_31h_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_31h, "thread 31h", thread_31h_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 31, 30, 1, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_31h, 0); /* Any core. */ @@ -245,7 +245,7 @@ UINT status; /* Now sleep for 20 ticks to let see if all the threads execute. */ tx_thread_sleep(20); - + /* Now check and make sure all the threads ran. */ if ((status != TX_SUCCESS) || (thread_31a_counter == 0) || (thread_31b_counter == 0) || (thread_31c_counter == 0) || (thread_31d_counter == 0) || (thread_31e_counter == 0) || (thread_31f_counter == 0) || (thread_31g_counter == 0) || (thread_31h_counter == 0)) @@ -257,11 +257,11 @@ UINT status; } else { - + /* Successful test. */ printf("SUCCESS!\n"); test_control_return(0); - } + } } @@ -281,8 +281,8 @@ static void thread_31b_entry(ULONG thread_input) while(1) { - - tx_thread_identify(); + + tx_thread_identify(); thread_31b_counter++; } } @@ -293,8 +293,8 @@ static void thread_31c_entry(ULONG thread_input) while(1) { - - tx_thread_identify(); + + tx_thread_identify(); thread_31c_counter++; } } @@ -305,8 +305,8 @@ static void thread_31d_entry(ULONG thread_input) while(1) { - - tx_thread_identify(); + + tx_thread_identify(); thread_31d_counter++; } } @@ -317,8 +317,8 @@ static void thread_31e_entry(ULONG thread_input) while(1) { - - tx_thread_identify(); + + tx_thread_identify(); thread_31e_counter++; } } @@ -329,8 +329,8 @@ static void thread_31f_entry(ULONG thread_input) while(1) { - - tx_thread_identify(); + + tx_thread_identify(); thread_31f_counter++; } } @@ -341,8 +341,8 @@ static void thread_31g_entry(ULONG thread_input) while(1) { - - tx_thread_identify(); + + tx_thread_identify(); thread_31g_counter++; } } @@ -353,8 +353,8 @@ static void thread_31h_entry(ULONG thread_input) while(1) { - - tx_thread_identify(); + + tx_thread_identify(); thread_31h_counter++; } } diff --git a/test/smp/regression/threadx_smp_two_threads_one_core_test.c b/test/smp/regression/threadx_smp_two_threads_one_core_test.c index a6dc1c80..66ed9478 100644 --- a/test/smp/regression/threadx_smp_two_threads_one_core_test.c +++ b/test/smp/regression/threadx_smp_two_threads_one_core_test.c @@ -55,8 +55,8 @@ ULONG exclusion_map; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 0, 0, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_0, 0x0); /* No exclusions! */ @@ -69,8 +69,8 @@ ULONG exclusion_map; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 1, 1, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_1, 0xD); /* Only core 1! */ @@ -83,8 +83,8 @@ ULONG exclusion_map; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 2, 2, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; status += tx_thread_smp_core_exclude(&thread_2, 0xD); /* Only core 1! */ @@ -110,7 +110,7 @@ ULONG exclusion_map; /* Attempt to call the core-exclusion API with a NULL pointer. */ status = tx_thread_smp_core_exclude(TX_NULL, 1); - + /* Check status. */ if (status != TX_THREAD_ERROR) { @@ -118,11 +118,11 @@ ULONG exclusion_map; printf("Running SMP Two Threads One Core Test............................... ERROR #5\n"); test_control_return(1); } - + /* Attempt to call the core-exclusion API with a bad thread pointer. */ thread_3.tx_thread_id = 0; status = tx_thread_smp_core_exclude(&thread_3, 1); - + /* Check status. */ if (status != TX_THREAD_ERROR) { @@ -130,10 +130,10 @@ ULONG exclusion_map; printf("Running SMP Two Threads One Core Test............................... ERROR #6\n"); test_control_return(1); } - + /* Test the core exclusion get API. */ status = tx_thread_smp_core_exclude_get(TX_NULL, TX_NULL); - + /* Check status. */ if (status != TX_THREAD_ERROR) { @@ -144,7 +144,7 @@ ULONG exclusion_map; /* Test the core exclusion get API with a bad thread pointer. */ status = tx_thread_smp_core_exclude_get(&thread_3, TX_NULL); - + /* Check status. */ if (status != TX_THREAD_ERROR) { @@ -155,7 +155,7 @@ ULONG exclusion_map; /* Test the core exclusion get API with a good thread pointer, but a bad return pointer. */ status = tx_thread_smp_core_exclude_get(&thread_2, TX_NULL); - + /* Check status. */ if (status != TX_PTR_ERROR) { @@ -166,14 +166,14 @@ ULONG exclusion_map; /* Now test the proper usage for the core exclusiong get API. */ status = tx_thread_smp_core_exclude_get(&thread_2, &exclusion_map); - + /* Check status. */ if ((status != TX_SUCCESS) || (exclusion_map != 0xD)) { printf("Running SMP Two Threads One Core Test............................... ERROR #10\n"); test_control_return(1); - } + } } @@ -198,7 +198,7 @@ UINT status; tx_thread_sleep(10); /* Determine if the test was successful or there was an error. */ - if ((status != TX_SUCCESS) || (error) || (thread_1_counter != 1) || + if ((status != TX_SUCCESS) || (error) || (thread_1_counter != 1) || (thread_2_counter != 1)) { @@ -208,7 +208,7 @@ UINT status; } else { - + /* Successful test. */ printf("SUCCESS!\n"); test_control_return(0); @@ -224,7 +224,7 @@ static void thread_1_entry(ULONG thread_input) /* Ensure this thread is on the correct core. */ if (tx_thread_smp_core_get() != 1) error++; - + thread_1_counter++; tx_thread_suspend(&thread_1); } @@ -238,31 +238,31 @@ TX_INTERRUPT_SAVE_AREA while(1) { - + /* Ensure this thread is on the correct core. */ if (tx_thread_smp_core_get() != 1) error++; thread_2_counter++; - - + + /* Disable interrupts. */ TX_DISABLE - + /* Increment the preempt disable flag. */ _tx_thread_preempt_disable++; - + /* Now call the exclude routine to exclude core 1 - move the thread. */ if (tx_thread_smp_core_exclude(&thread_2, 0x2)) error++; - + /* Decrement the preempt disable flag. */ _tx_thread_preempt_disable--; - + /* Restore interrupts. */ TX_RESTORE - - /* Suspend thread. */ + + /* Suspend thread. */ tx_thread_suspend(&thread_2); } } diff --git a/test/smp/regression/threadx_thread_basic_execution_test.c b/test/smp/regression/threadx_thread_basic_execution_test.c index 02e18d24..5772f97e 100644 --- a/test/smp/regression/threadx_thread_basic_execution_test.c +++ b/test/smp/regression/threadx_thread_basic_execution_test.c @@ -1,5 +1,5 @@ -/* This test is designed to see if one thread can be created and executed. - It thread_0_entry is hit, then the thread was successfully scheduled. +/* This test is designed to see if one thread can be created and executed. + It thread_0_entry is hit, then the thread was successfully scheduled. On success, thread_0_counter gets incremented. */ #include @@ -56,10 +56,10 @@ static unsigned long isr_executed = 0; static void thread_0_entry(ULONG task_input); -UINT _txe_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr, +UINT _txe_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr, VOID (*entry_function)(ULONG), ULONG entry_input, - VOID *stack_start, ULONG stack_size, - UINT priority, UINT preempt_threshold, + VOID *stack_start, ULONG stack_size, + UINT priority, UINT preempt_threshold, ULONG time_slice, UINT auto_start, UINT thread_control_block_size); @@ -80,8 +80,8 @@ CHAR *pointer; /* Attempt to create a thread from a timer. */ pointer = (CHAR *) 0x3000; - status = tx_thread_create(&thread_1, "thread 1", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_DONT_START); /* Check for status. */ @@ -125,8 +125,8 @@ ULONG old_time_slice; /* Attempt to create a thread from a timer. */ pointer = (CHAR *) not_used_stack; - status = tx_thread_create(&thread_1, "thread 1", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_DONT_START); /* Check for status. */ @@ -139,7 +139,7 @@ ULONG old_time_slice; /* Attempt to delete a thread from an ISR. */ status = tx_thread_delete(&thread_0); - + /* Check for status. */ if (status != TX_CALLER_ERROR) { @@ -150,7 +150,7 @@ ULONG old_time_slice; /* Attempt to change preemption from an ISR. */ status = tx_thread_preemption_change(&thread_0, 1, &old_value); - + /* Check for status. */ if (status != TX_CALLER_ERROR) { @@ -161,7 +161,7 @@ ULONG old_time_slice; /* Attempt to change priority from an ISR. */ status = tx_thread_priority_change(&thread_0, 1, &old_value); - + /* Check for status. */ if (status != TX_CALLER_ERROR) { @@ -241,15 +241,15 @@ TX_THREAD fake_thread; /* Setup a pointer. */ pointer = (CHAR *) first_unused_memory; - + /* Adjust it forward just to make sure there is some space for the test below. */ pointer = pointer + 200; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); /* Check for status. */ @@ -298,7 +298,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Setup test thread to make sure _tx_thread_wait_abort can handle a NULL cleanup. */ test_thread.tx_thread_state = TX_IO_DRIVER; - test_thread.tx_thread_suspend_cleanup = TX_NULL; + test_thread.tx_thread_suspend_cleanup = TX_NULL; test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; test_thread.tx_thread_suspending = TX_TRUE; test_thread.tx_thread_delayed_suspend = TX_TRUE; @@ -310,7 +310,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Setup test thread to make sure _tx_thread_timeout can handle a NULL cleanup. */ test_thread.tx_thread_state = TX_IO_DRIVER; - test_thread.tx_thread_suspend_cleanup = TX_NULL; + test_thread.tx_thread_suspend_cleanup = TX_NULL; test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; test_thread.tx_thread_suspending = TX_TRUE; test_thread.tx_thread_delayed_suspend = TX_TRUE; @@ -320,12 +320,12 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); temp_mutex_release = _tx_thread_mutex_release; _tx_thread_mutex_release = TX_NULL; test_thread.tx_thread_state = TX_TERMINATED; - test_thread.tx_thread_suspend_cleanup = TX_NULL; + test_thread.tx_thread_suspend_cleanup = TX_NULL; test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; test_thread.tx_thread_suspending = TX_TRUE; test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; test_thread.tx_thread_delayed_suspend = TX_TRUE; - status = _tx_thread_terminate(&test_thread); + status = _tx_thread_terminate(&test_thread); _tx_thread_mutex_release = temp_mutex_release; /* Recover Mutex release pointer. */ /* Perform thread memory test. */ @@ -335,10 +335,10 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); thread_memory.second_middle= 0x61718191; thread_memory.next_to_last = 0x99aabbcc; thread_memory.last = 0xddeeff00; - + /* Create the thread. */ - status += tx_thread_create(&thread_memory.thread_block, "thread memory", thread_0_entry, 1, - &thread_memory.stack[0], (2048*sizeof(ULONG))/sizeof(ULONG), + status += tx_thread_create(&thread_memory.thread_block, "thread memory", thread_0_entry, 1, + &thread_memory.stack[0], (2048*sizeof(ULONG))/sizeof(ULONG), 16, 16, TX_NO_TIME_SLICE, TX_DONT_START); tx_thread_delete(&thread_memory.thread_block); @@ -351,7 +351,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); (thread_memory.next_to_last != 0x99aabbcc) || (thread_memory.last != 0xddeeff00)) { - + /* Memory overwrite error. */ printf("ERROR #2\n"); test_control_return(1); @@ -363,8 +363,8 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to create a thread with a null pointer. */ pointer = (CHAR *) not_used_stack; - status = tx_thread_create(TX_NULL, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(TX_NULL, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); /* Check for status. */ @@ -377,8 +377,8 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to create a thread with a bad control block size. */ pointer = (CHAR *) not_used_stack; - status = _txe_thread_create(&thread_3, "thread 3", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = _txe_thread_create(&thread_3, "thread 3", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START, (sizeof(TX_THREAD)+1)); /* Check for status. */ @@ -391,8 +391,8 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to create a thread with a NULL entry function. */ pointer = (CHAR *) not_used_stack; - status = tx_thread_create(&thread_3, "thread 3", TX_NULL, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", TX_NULL, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); /* Check for status. */ @@ -405,8 +405,8 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to create a thread that has already been created. */ pointer = (CHAR *) not_used_stack; - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); /* Check for status. */ @@ -418,8 +418,8 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); } /* Attempt to create a thread with an overlapping stack. */ - status = tx_thread_create(&thread_1, "thread 1", thread_0_entry, 1, - thread_0.tx_thread_stack_ptr, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_0_entry, 1, + thread_0.tx_thread_stack_ptr, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); /* Check for status. */ @@ -433,8 +433,8 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to create a thread with another variation of an overlapping stack. */ pointer = thread_0.tx_thread_stack_start; pointer = pointer - 20; - status = tx_thread_create(&thread_1, "thread 1", TX_NULL, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", TX_NULL, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); /* Check for status. */ @@ -447,8 +447,8 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to create a thread an extra small stack. */ pointer = (CHAR *) not_used_stack; - status = tx_thread_create(&thread_1, "thread 1", thread_0_entry, 1, - pointer, 1, + status = tx_thread_create(&thread_1, "thread 1", thread_0_entry, 1, + pointer, 1, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); /* Check for status. */ @@ -461,8 +461,8 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to create a thread with an invalid thread priority. */ pointer = (CHAR *) not_used_stack; - status = tx_thread_create(&thread_1, "thread 1", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 5000, 5000, TX_NO_TIME_SLICE, TX_AUTO_START); /* Check for status. */ @@ -475,8 +475,8 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to create a thread with an invalid preemption-threshold. */ pointer = (CHAR *) not_used_stack; - status = tx_thread_create(&thread_1, "thread 1", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 17, TX_NO_TIME_SLICE, TX_AUTO_START); /* Check for status. */ @@ -489,8 +489,8 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to create a thread with an invalid auto start. */ pointer = (CHAR *) not_used_stack; - status = tx_thread_create(&thread_1, "thread 1", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, 3456); /* Check for status. */ @@ -526,7 +526,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to register a entry/exit callback on a non-thread. */ status = tx_thread_entry_exit_notify(TX_NULL, TX_NULL); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -538,7 +538,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to register a entry/exit callback on a non-created thread. */ thread_2.tx_thread_id = 0; status = tx_thread_entry_exit_notify(&thread_2, TX_NULL); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -549,7 +549,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to get info on a non-thread. */ status = tx_thread_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -561,7 +561,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to get info on a non-created thread. */ thread_2.tx_thread_id = 0; status = tx_thread_info_get(&thread_2, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -572,7 +572,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to change preemption of a non-thread. */ status = tx_thread_preemption_change(TX_NULL, 1, TX_NULL); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -580,11 +580,11 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); printf("ERROR #19\n"); test_control_return(1); } - + /* Attempt to change preemption of a non-created thread. */ thread_2.tx_thread_id = 0; status = tx_thread_preemption_change(&thread_2, 1, TX_NULL); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -595,7 +595,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to change preemption with a NULL return value. */ status = tx_thread_preemption_change(&thread_0, 1, TX_NULL); - + /* Check for status. */ if (status != TX_PTR_ERROR) { @@ -603,10 +603,10 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); printf("ERROR #21\n"); test_control_return(1); } - + /* Attempt to change preemption with a bad threshold value. */ status = tx_thread_preemption_change(&thread_0, 17, &old_value); - + /* Check for status. */ if (status != TX_THRESH_ERROR) { @@ -618,7 +618,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to change priority of a non-thread. */ status = tx_thread_priority_change(TX_NULL, 1, TX_NULL); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -626,11 +626,11 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); printf("ERROR #23\n"); test_control_return(1); } - + /* Attempt to change priority of a non-created thread. */ thread_2.tx_thread_id = 0; status = tx_thread_priority_change(&thread_2, 1, TX_NULL); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -641,7 +641,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to change priority with a NULL return value. */ status = tx_thread_priority_change(&thread_0, 1, TX_NULL); - + /* Check for status. */ if (status != TX_PTR_ERROR) { @@ -649,10 +649,10 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); printf("ERROR #25\n"); test_control_return(1); } - + /* Attempt to change priority with a bad priority value. */ status = tx_thread_priority_change(&thread_0, 2046, &old_value); - + /* Check for status. */ if (status != TX_PRIORITY_ERROR) { @@ -697,7 +697,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt a thread resume with a NULL pointer. */ status = tx_thread_resume(TX_NULL); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -705,11 +705,11 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); printf("ERROR #30\n"); test_control_return(1); } - + /* Attempt a thread resume on a non-created thread. */ thread_2.tx_thread_id = 0; status = tx_thread_resume(&thread_2); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -720,7 +720,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt a thread suspend with a NULL pointer. */ status = tx_thread_suspend(TX_NULL); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -728,11 +728,11 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); printf("ERROR #32\n"); test_control_return(1); } - + /* Attempt a thread suspend on a non-created thread. */ thread_2.tx_thread_id = 0; status = tx_thread_suspend(&thread_2); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -743,7 +743,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt a thread termiante with a NULL pointer. */ status = tx_thread_terminate(TX_NULL); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -751,11 +751,11 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); printf("ERROR #34\n"); test_control_return(1); } - + /* Attempt a thread terminate on a non-created thread. */ thread_2.tx_thread_id = 0; status = tx_thread_terminate(&thread_2); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -766,7 +766,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt a thread time-slice chagne with a NULL pointer. */ status = tx_thread_time_slice_change(TX_NULL, 1, &old_time_slice); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -774,11 +774,11 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); printf("ERROR #36\n"); test_control_return(1); } - + /* Attempt a thread time-slice change on a non-created thread. */ thread_2.tx_thread_id = 0; status = tx_thread_time_slice_change(&thread_2, 1, &old_time_slice); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -789,7 +789,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt a thread time-slice change with a null return pointer. */ status = tx_thread_time_slice_change(&thread_0, 1, TX_NULL); - + /* Check for status. */ if (status != TX_PTR_ERROR) { @@ -800,7 +800,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt a thread wait abort with a NULL pointer. */ status = tx_thread_wait_abort(TX_NULL); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -808,11 +808,11 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); printf("ERROR #39\n"); test_control_return(1); } - + /* Attempt a thread wait abort on a non-created thread. */ thread_2.tx_thread_id = 0; status = tx_thread_wait_abort(&thread_2); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -836,7 +836,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Test for error. */ if ((error) || (timer_executed != 1) || (isr_executed != 1)) { - + /* Thread error. */ printf("ERROR #41\n"); test_control_return(1); @@ -854,7 +854,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); } else { - + /* Successful test. */ printf("SUCCESS!\n"); test_control_return(0); diff --git a/test/smp/regression/threadx_thread_basic_time_slice_test.c b/test/smp/regression/threadx_thread_basic_time_slice_test.c index 9a4f4373..bb848b11 100644 --- a/test/smp/regression/threadx_thread_basic_time_slice_test.c +++ b/test/smp/regression/threadx_thread_basic_time_slice_test.c @@ -1,4 +1,4 @@ -/* This test is designed to see if a thread can be created with a time-slice. +/* This test is designed to see if a thread can be created with a time-slice. No time-slice occurs, only the processing to check for time-slicing. */ #include @@ -32,18 +32,18 @@ void threadx_thread_basic_time_slice_application_define(void *first_unused_me UINT status; UCHAR *memory; - + memory = (UCHAR *) first_unused_memory; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - memory, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + memory, TEST_STACK_SIZE_PRINTF, 16, 16, 1, TX_AUTO_START); memory = memory + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - memory, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + memory, TEST_STACK_SIZE_PRINTF, 16, 16, 1, TX_DONT_START); status += tx_thread_smp_core_exclude(&thread_1, 0xF); status += tx_thread_resume(&thread_1); @@ -87,7 +87,7 @@ ULONG target_time; /* Determine if thread 1 executed. */ if (thread_1_counter != 0) { - + /* Error, thread 1 has all cores excluded so it should never run. */ printf("ERROR #2\n"); test_control_return(0); @@ -112,6 +112,6 @@ static void thread_1_entry(ULONG thread_input) { /* Increment counter. */ - thread_1_counter++; + thread_1_counter++; } } diff --git a/test/smp/regression/threadx_thread_completed_test.c b/test/smp/regression/threadx_thread_completed_test.c index 068058d0..adaf1683 100644 --- a/test/smp/regression/threadx_thread_completed_test.c +++ b/test/smp/regression/threadx_thread_completed_test.c @@ -1,5 +1,5 @@ -/* This test is designed to see if one thread can be created, executed, and - return to the thread shell function. The thread shell function places +/* This test is designed to see if one thread can be created, executed, and + return to the thread shell function. The thread shell function places the thread in a finished state. */ #include @@ -36,7 +36,7 @@ static void entry_exit_notify(TX_THREAD *thread_ptr, UINT type) /* Check for the appropriate thread. */ if (thread_ptr != &thread_0) return; - + /* Check for type. */ if (type == TX_THREAD_ENTRY) thread_0_enter++; @@ -64,8 +64,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -94,8 +94,8 @@ CHAR *pointer; #endif - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -107,8 +107,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -154,11 +154,11 @@ UINT status; /* Attempt to delete thread 2, which is in the wrong stat for deleting. */ status = tx_thread_delete(&thread_2); - + /* Check for the proper status. */ if (status != TX_DELETE_ERROR) { - + /* Thread delete error. */ printf("ERROR #5\n"); test_control_return(1); @@ -166,11 +166,11 @@ UINT status; /* Attempt to suspend thread 0, which is in a completed state. */ status = tx_thread_suspend(&thread_0); - + /* Check for the correct status. */ if (status != TX_SUSPEND_ERROR) { - + /* Thread suspend error. */ printf("ERROR #6\n"); test_control_return(1); @@ -178,11 +178,11 @@ UINT status; /* Attempt to delete thread 0. */ status = tx_thread_delete(&thread_0); - + /* Check for the proper status. */ if (status != TX_SUCCESS) { - + /* Thread delete error. */ printf("ERROR #7\n"); test_control_return(1); @@ -190,32 +190,32 @@ UINT status; /* Sleep to let thread 2 run. */ tx_thread_sleep(2); - + /* Save the created count. */ saved_count = _tx_thread_created_count; - + /* Now setup things so we can fake a delete of one thread. */ _tx_thread_created_ptr = &thread_2; thread_2.tx_thread_created_next = &thread_2; thread_2.tx_thread_created_previous = &thread_2; _tx_thread_created_count = 1; - + /* Attempt to delete thread 2. */ status = tx_thread_delete(&thread_2); - + /* Check for the proper status. */ if (status != TX_SUCCESS) { - + /* Thread delete error. */ printf("ERROR #8\n"); test_control_return(1); } - + /* if still okay, restore the saved thread pointer. */ if (saved_ptr -> tx_thread_id == TX_THREAD_ID) - { - /* Restore. */ + { + /* Restore. */ _tx_thread_created_ptr = saved_ptr; /* Setup the link pointers again. */ @@ -242,7 +242,7 @@ UINT status; } else { - + /* Thread Finish error. */ printf("ERROR #9\n"); test_control_return(1); diff --git a/test/smp/regression/threadx_thread_create_preemption_threshold_test.c b/test/smp/regression/threadx_thread_create_preemption_threshold_test.c index ad0d1d4e..58ce79fe 100644 --- a/test/smp/regression/threadx_thread_create_preemption_threshold_test.c +++ b/test/smp/regression/threadx_thread_create_preemption_threshold_test.c @@ -43,8 +43,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 17, 0, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -56,8 +56,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 0, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -69,8 +69,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 15, 0, 100, TX_DONT_START); status += tx_thread_resume(&thread_0); pointer = pointer + TEST_STACK_SIZE_PRINTF; diff --git a/test/smp/regression/threadx_thread_delayed_suspension_test.c b/test/smp/regression/threadx_thread_delayed_suspension_test.c index 6d6d27d0..91128f83 100644 --- a/test/smp/regression/threadx_thread_delayed_suspension_test.c +++ b/test/smp/regression/threadx_thread_delayed_suspension_test.c @@ -97,7 +97,7 @@ ULONG i; if (loop_count < min_loop_count) min_loop_count = loop_count; if (loop_count > max_loop_count) - max_loop_count = loop_count; + max_loop_count = loop_count; lower_bound = loop_count - 1; upper_bound = loop_count + 1; @@ -108,38 +108,38 @@ ULONG i; if ((current_itterations < lower_bound) || (current_itterations > upper_bound)) current_itterations = lower_bound; - + #ifdef DEBUG_1 /* Last loop count. */ last_loop_count = loop_count; #endif - + /* Reset the loop count to all ones! */ loop_count = 0xFFFFFFFF; } count++; for (i = 0; i < (count%32); i++) - destination++; + destination++; /* Check to see if the interrupt occurred in the middle of the suspension. */ if ((thread_2.tx_thread_suspending) && (delayed_suspend_set == 0)) { - + /* Yes, we have taken the interrupt in the middle of a thread suspension. */ - + /* Indicate we have got the condition. */ delayed_suspend_set = 1; /* Capture the current thread 2 counter. */ thread_2_counter_capture = thread_2_counter; - + /* Now attempt to set the delayed suspension. */ tx_thread_suspend(&thread_2); - + /* Check for the delayed suspension flag being set. */ if (thread_2.tx_thread_delayed_suspend != 1) { - + /* Error! Setup the counters to indicate an error. */ thread_2_counter = 0xEEEEEEEE; thread_2_counter_capture = 0xFFFFFFFF; @@ -147,11 +147,11 @@ ULONG i; /* Now, abort the suspension for thread 2... the thread should switch to a pure suspended state. */ tx_thread_wait_abort(&thread_2); - + /* Check for the proper state. */ if (thread_2.tx_thread_state != TX_SUSPENDED) { - + /* Error! Setup the counters to indicate an error. */ thread_2_counter = 0xEEEEEEEE; thread_2_counter_capture = 0xFFFFFFFF; @@ -181,14 +181,14 @@ CHAR *pointer; create information. */ /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 2, 2, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; /* Create threads 1 and 2. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 2, 2, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; @@ -197,8 +197,8 @@ CHAR *pointer; #ifndef TX_NOT_INTERRUPTABLE - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + DEMO_STACK_SIZE; @@ -232,7 +232,7 @@ UINT status; tx_thread_relinquish(); /* At this point thread 1 has suspended on the semaphore. */ - + /* Suspend the already suspended thread. */ tx_thread_suspend(&thread_1); @@ -277,20 +277,20 @@ UINT status; /* Just relinquish. */ tx_thread_relinquish(); } - + /* Relinquish one more time to make sure thread 2 could run if it is ready. */ tx_thread_relinquish(); - + /* At this point, check for an error. */ if (thread_2_counter != thread_2_counter_capture) { - + /* Delayed suspension error... thread kept running! */ printf("ERROR #2\n"); test_control_return(1); } #endif - + /* Successful test. */ printf("SUCCESS!\n"); test_control_return(0); @@ -327,10 +327,10 @@ ULONG i; /* Callibrate the loop count from thread sleep. */ for (i = 0; i < 10; i++) { - + /* Sleep to get a fresh time. */ tx_thread_sleep(1); - + start_time = _tx_timer_system_clock; do { @@ -339,7 +339,7 @@ ULONG i; delay_function(); loop_count++; } while (start_time == _tx_timer_system_clock); - + /* Wait to reset the loop count. */ tx_thread_sleep(1); } @@ -358,7 +358,7 @@ ULONG i; /* Sleep to get a fresh starting time. */ tx_thread_sleep(1); - + loop_count = 0; start_time = _tx_timer_system_clock; do @@ -366,7 +366,7 @@ ULONG i; /* Call delay function. */ delay_function(); loop_count++; - } while (loop_count < current_itterations); + } while (loop_count < current_itterations); /* Suspend this thread. */ tx_semaphore_get(&semaphore_1, TX_WAIT_FOREVER); diff --git a/test/smp/regression/threadx_thread_information_test.c b/test/smp/regression/threadx_thread_information_test.c index b72a2363..19107742 100644 --- a/test/smp/regression/threadx_thread_information_test.c +++ b/test/smp/regression/threadx_thread_information_test.c @@ -31,8 +31,8 @@ INT status; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - first_unused_memory, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + first_unused_memory, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); /* Check for status. */ @@ -83,9 +83,9 @@ ULONG idle_returns; /* Get information about this thread. */ status = tx_thread_info_get(&thread_0, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_thread_info_get(&thread_0, &name, &state, &run_count, &priority, &preemption_threshold, &time_slice, &next_thread, &suspended_thread); - + /* Check for error status. */ - if ((status != TX_SUCCESS) || (state != TX_READY) || (run_count != thread_0.tx_thread_run_count) || (priority != 16) || (preemption_threshold != 16) || + if ((status != TX_SUCCESS) || (state != TX_READY) || (run_count != thread_0.tx_thread_run_count) || (priority != 16) || (preemption_threshold != 16) || (time_slice != 0) || (next_thread != thread_0.tx_thread_created_next) || (suspended_thread != thread_0.tx_thread_suspended_next)) { @@ -103,7 +103,7 @@ ULONG idle_returns; /* Check status. */ if (status != TX_PTR_ERROR) { - + /* Thread error. */ printf("ERROR #3\n"); test_control_return(1); @@ -111,7 +111,7 @@ ULONG idle_returns; /* Get the performance information about this thread. */ status = tx_thread_performance_info_get(&thread_0, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); - status += tx_thread_performance_info_get(&thread_0, &resumptions, &suspensions, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, + status += tx_thread_performance_info_get(&thread_0, &resumptions, &suspensions, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, &relinquishes, &timeouts, &wait_aborts, &last_preempted_by); /* Check for error. */ @@ -129,7 +129,7 @@ ULONG idle_returns; /* Get the system performance information. */ status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); - status += tx_thread_performance_system_info_get(&resumptions, &suspensions, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, + status += tx_thread_performance_system_info_get(&resumptions, &suspensions, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, &relinquishes, &timeouts, &wait_aborts, &non_idle_returns, &idle_returns); /* Check for error. */ @@ -146,7 +146,7 @@ ULONG idle_returns; } else { - + /* Success! */ printf("SUCCESS!\n"); test_control_return(0); @@ -154,312 +154,312 @@ ULONG idle_returns; #else /* Get the performance information about this thread. */ - status = tx_thread_performance_info_get(&thread_0, &resumptions, &suspensions, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, + status = tx_thread_performance_info_get(&thread_0, &resumptions, &suspensions, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, &relinquishes, &timeouts, &wait_aborts, &last_preempted_by); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #6\n"); test_control_return(1); } /* Get the performance information about this thread. */ - status = tx_thread_performance_info_get(TX_NULL, &resumptions, &suspensions, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, + status = tx_thread_performance_info_get(TX_NULL, &resumptions, &suspensions, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, &relinquishes, &timeouts, &wait_aborts, &last_preempted_by); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #7\n"); test_control_return(1); } /* Get the performance information about this thread. */ - status = tx_thread_performance_info_get(TX_NULL, TX_NULL, &suspensions, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, + status = tx_thread_performance_info_get(TX_NULL, TX_NULL, &suspensions, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, &relinquishes, &timeouts, &wait_aborts, &last_preempted_by); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #8\n"); test_control_return(1); } /* Get the performance information about this thread. */ - status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, + status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, &relinquishes, &timeouts, &wait_aborts, &last_preempted_by); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #9\n"); test_control_return(1); } /* Get the performance information about this thread. */ - status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, &interrupt_preemptions, &priority_inversions, &time_slices, + status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, &interrupt_preemptions, &priority_inversions, &time_slices, &relinquishes, &timeouts, &wait_aborts, &last_preempted_by); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #10\n"); test_control_return(1); } /* Get the performance information about this thread. */ - status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &priority_inversions, &time_slices, + status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &priority_inversions, &time_slices, &relinquishes, &timeouts, &wait_aborts, &last_preempted_by); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #11\n"); test_control_return(1); } /* Get the performance information about this thread. */ - status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &time_slices, + status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &time_slices, &relinquishes, &timeouts, &wait_aborts, &last_preempted_by); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #12\n"); test_control_return(1); } /* Get the performance information about this thread. */ - status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, + status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &relinquishes, &timeouts, &wait_aborts, &last_preempted_by); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #13\n"); test_control_return(1); } /* Get the performance information about this thread. */ - status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, + status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &timeouts, &wait_aborts, &last_preempted_by); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #14\n"); test_control_return(1); } /* Get the performance information about this thread. */ - status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, + status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &wait_aborts, &last_preempted_by); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #15\n"); test_control_return(1); } /* Get the performance information about this thread. */ - status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, + status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &last_preempted_by); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #16\n"); test_control_return(1); } /* Get the performance information about this thread. */ - status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, + status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #17\n"); test_control_return(1); } /* Get the system performance information. */ - status = tx_thread_performance_system_info_get(&resumptions, &suspensions, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, + status = tx_thread_performance_system_info_get(&resumptions, &suspensions, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, &relinquishes, &timeouts, &wait_aborts, &non_idle_returns, &idle_returns); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #18\n"); test_control_return(1); } /* Get the system performance information. */ - status = tx_thread_performance_system_info_get(TX_NULL, &suspensions, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, + status = tx_thread_performance_system_info_get(TX_NULL, &suspensions, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, &relinquishes, &timeouts, &wait_aborts, &non_idle_returns, &idle_returns); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #19\n"); test_control_return(1); } /* Get the system performance information. */ - status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, + status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, &relinquishes, &timeouts, &wait_aborts, &non_idle_returns, &idle_returns); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #20\n"); test_control_return(1); } /* Get the system performance information. */ - status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, &interrupt_preemptions, &priority_inversions, &time_slices, + status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, &interrupt_preemptions, &priority_inversions, &time_slices, &relinquishes, &timeouts, &wait_aborts, &non_idle_returns, &idle_returns); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #21\n"); test_control_return(1); } /* Get the system performance information. */ - status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, &priority_inversions, &time_slices, + status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, &priority_inversions, &time_slices, &relinquishes, &timeouts, &wait_aborts, &non_idle_returns, &idle_returns); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #22\n"); test_control_return(1); } /* Get the system performance information. */ - status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &time_slices, + status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &time_slices, &relinquishes, &timeouts, &wait_aborts, &non_idle_returns, &idle_returns); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #23\n"); test_control_return(1); } /* Get the system performance information. */ - status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, + status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &relinquishes, &timeouts, &wait_aborts, &non_idle_returns, &idle_returns); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #24\n"); test_control_return(1); } /* Get the system performance information. */ - status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, + status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &timeouts, &wait_aborts, &non_idle_returns, &idle_returns); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #25\n"); test_control_return(1); } /* Get the system performance information. */ - status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, + status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &wait_aborts, &non_idle_returns, &idle_returns); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #26\n"); test_control_return(1); } /* Get the system performance information. */ - status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, + status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &non_idle_returns, &idle_returns); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #27\n"); test_control_return(1); } /* Get the system performance information. */ - status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, + status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &idle_returns); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #28\n"); test_control_return(1); } /* Get the system performance information. */ - status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, + status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #29\n"); test_control_return(1); diff --git a/test/smp/regression/threadx_thread_multi_level_preemption_threshold_test.c b/test/smp/regression/threadx_thread_multi_level_preemption_threshold_test.c index 034d4f56..1e18820b 100644 --- a/test/smp/regression/threadx_thread_multi_level_preemption_threshold_test.c +++ b/test/smp/regression/threadx_thread_multi_level_preemption_threshold_test.c @@ -1,4 +1,4 @@ -/* This test is designed to test multi-level preemption threshold. The protection placed +/* This test is designed to test multi-level preemption threshold. The protection placed by a thread must be preserved after higher-priority thread preemption that is above the threshold. */ #include @@ -139,8 +139,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, (TX_MAX_PRIORITIES-1), (TX_MAX_PRIORITIES/2), TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -154,8 +154,8 @@ CHAR *pointer; #ifndef TX_DISABLE_PREEMPTION_THRESHOLD /* skip this test and pretend it passed */ - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, (TX_MAX_PRIORITIES/2), (TX_MAX_PRIORITIES/2), TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -167,8 +167,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 15, 10, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -180,8 +180,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2a, "thread 2a", thread_2a_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2a, "thread 2a", thread_2a_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -193,8 +193,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 11, 11, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -206,8 +206,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 9, 9, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -221,8 +221,8 @@ CHAR *pointer; /* Create new cascading preemption-threshold test threads. */ - status = tx_thread_create(&thread_30_29, "thread 30-29", thread_30_29_entry, 30, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_30_29, "thread 30-29", thread_30_29_entry, 30, + pointer, TEST_STACK_SIZE_PRINTF, 30, 29, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -234,8 +234,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_28_27, "thread 28-27", thread_28_27_entry, 28, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_28_27, "thread 28-27", thread_28_27_entry, 28, + pointer, TEST_STACK_SIZE_PRINTF, 28, 27, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -247,8 +247,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_26_25, "thread 26-25", thread_26_25_entry, 26, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_26_25, "thread 26-25", thread_26_25_entry, 26, + pointer, TEST_STACK_SIZE_PRINTF, 26, 25, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -260,8 +260,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_24_23, "thread 24-23", thread_24_23_entry, 24, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_24_23, "thread 24-23", thread_24_23_entry, 24, + pointer, TEST_STACK_SIZE_PRINTF, 24, 23, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -273,8 +273,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_22_21, "thread 22-21", thread_22_21_entry, 22, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_22_21, "thread 22-21", thread_22_21_entry, 22, + pointer, TEST_STACK_SIZE_PRINTF, 22, 21, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -286,8 +286,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_20_19, "thread 20-19", thread_20_19_entry, 20, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_20_19, "thread 20-19", thread_20_19_entry, 20, + pointer, TEST_STACK_SIZE_PRINTF, 20,19, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -299,8 +299,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_18_17, "thread 18-17", thread_18_17_entry, 18, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_18_17, "thread 18-17", thread_18_17_entry, 18, + pointer, TEST_STACK_SIZE_PRINTF, 18, 17, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -312,8 +312,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_16_15, "thread 16-15", thread_16_15_entry, 16, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_16_15, "thread 16-15", thread_16_15_entry, 16, + pointer, TEST_STACK_SIZE_PRINTF, 16, 15, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -325,8 +325,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_14_13, "thread 14-13", thread_14_13_entry, 14, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_14_13, "thread 14-13", thread_14_13_entry, 14, + pointer, TEST_STACK_SIZE_PRINTF, 14, 13, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -338,8 +338,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_12_11, "thread 12-11", thread_12_11_entry, 12, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_12_11, "thread 12-11", thread_12_11_entry, 12, + pointer, TEST_STACK_SIZE_PRINTF, 12, 11, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -352,7 +352,7 @@ CHAR *pointer; } status = tx_thread_create(&thread_10_9, "thread 10-9", thread_10_9_entry, 10, - pointer, TEST_STACK_SIZE_PRINTF, + pointer, TEST_STACK_SIZE_PRINTF, 10, 9, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -364,8 +364,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_8_7, "thread 8-7", thread_8_7_entry, 8, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_8_7, "thread 8-7", thread_8_7_entry, 8, + pointer, TEST_STACK_SIZE_PRINTF, 8, 7, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -377,8 +377,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_6_5, "thread 6-5", thread_6_5_entry, 6, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_6_5, "thread 6-5", thread_6_5_entry, 6, + pointer, TEST_STACK_SIZE_PRINTF, 6, 5, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -390,8 +390,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_4_3, "thread 4-3", thread_4_3_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4_3, "thread 4-3", thread_4_3_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 4, 3, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -403,8 +403,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_3_2, "thread 3-2", thread_3_2_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3_2, "thread 3-2", thread_3_2_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 3, 2, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -416,8 +416,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2_1, "thread 2-1", thread_2_1_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2_1, "thread 2-1", thread_2_1_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 2, 1, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -429,8 +429,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1_0, "thread 1-0", thread_1_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1_0, "thread 1-0", thread_1_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 1, 1, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -443,7 +443,7 @@ CHAR *pointer; } status = tx_timer_create(&timer_0, "timer 0", timer_0_entry, 0, 1, 0, TX_NO_ACTIVATE); - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -451,7 +451,7 @@ CHAR *pointer; printf("Running Thread Multi-Level Preemption Threshold Test................ ERROR #24\n"); test_control_return(1); } - + #endif } @@ -522,7 +522,7 @@ UINT old_preempt; /* Set preemption threshold to keep new test threads from running. */ status = tx_thread_preemption_change(&thread_0, 17, &old_preempt); - + /* Now wakup the lowest priority preemption-threshold thread. */ status += tx_thread_resume(&thread_30_29); @@ -537,7 +537,7 @@ UINT old_preempt; /* Now, self suspend. */ status = tx_thread_suspend(&thread_0); - + /* Check to make sure all the preemption-threshold threads ran. */ if ((thread_1_0_counter != 1) || (thread_2_1_counter != 1) || @@ -606,7 +606,7 @@ UINT status; (thread_4_counter != 1)) return; - /* Relinquish to the other thread at this priority level. This should + /* Relinquish to the other thread at this priority level. This should clear the preemption threshold condition and allow thread 3 to run. */ tx_thread_relinquish(); @@ -648,7 +648,7 @@ static void timer_0_entry(ULONG id) /* Pretend like a preemption occurred on a thread priority of 1 with preemption-threshold set to 0. */ _tx_thread_preempted_maps[0] = _tx_thread_preempted_maps[0] | 2; - + /* Set the thread's preemption threshold as well. */ thread_1_0.tx_thread_preempt_threshold = 0; @@ -665,16 +665,16 @@ UINT status; /* Activate the timer to force a priority 0 thread to interrupt. */ status = tx_timer_activate(&timer_0); - + /* Loop to wait until timer 0 runs. */ while (timer_0_counter == 0) { } - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_1_0_counter++; } @@ -697,11 +697,11 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_1_0); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_3_2_counter++; } @@ -716,11 +716,11 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_2_1); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_4_3_counter++; } @@ -736,16 +736,16 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_4_3); - /* In this particular case, we have two different preemptions to make + /* In this particular case, we have two different preemptions to make sure we exercise all the code. */ /* Now resume next highest priority thread. */ status = tx_thread_resume(&thread_3_2); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_6_5_counter++; } @@ -760,11 +760,11 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_6_5); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_8_7_counter++; } @@ -779,11 +779,11 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_8_7); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_10_9_counter++; } @@ -797,11 +797,11 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_10_9); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_12_11_counter++; } @@ -816,11 +816,11 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_12_11); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_14_13_counter++; } @@ -835,11 +835,11 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_14_13); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_16_15_counter++; } @@ -854,11 +854,11 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_16_15); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_18_17_counter++; } @@ -873,11 +873,11 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_18_17); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_20_19_counter++; } @@ -892,11 +892,11 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_20_19); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_22_21_counter++; } @@ -911,11 +911,11 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_22_21); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_24_23_counter++; } @@ -929,11 +929,11 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_24_23); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_26_25_counter++; } @@ -947,11 +947,11 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_26_25); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_28_27_counter++; } @@ -965,15 +965,15 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_28_27); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_30_29_counter++; } - + /* Resume thread_0. */ tx_thread_resume(&thread_0); } diff --git a/test/smp/regression/threadx_thread_multiple_non_current_test.c b/test/smp/regression/threadx_thread_multiple_non_current_test.c index 51212b3b..50ed17a0 100644 --- a/test/smp/regression/threadx_thread_multiple_non_current_test.c +++ b/test/smp/regression/threadx_thread_multiple_non_current_test.c @@ -1,6 +1,6 @@ -/* This test is designed to see if multiple non-current threads can be suspended. - The order the suspension and resumption occurs makes sure everything is working - right. Thread execution should remain predictable even after suspension and +/* This test is designed to see if multiple non-current threads can be suspended. + The order the suspension and resumption occurs makes sure everything is working + right. Thread execution should remain predictable even after suspension and resumption of threads within a priority group. */ #include @@ -54,8 +54,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -67,8 +67,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -80,8 +80,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -93,8 +93,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -106,8 +106,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; diff --git a/test/smp/regression/threadx_thread_multiple_sleep_test.c b/test/smp/regression/threadx_thread_multiple_sleep_test.c index 9a876295..f2ae3b99 100644 --- a/test/smp/regression/threadx_thread_multiple_sleep_test.c +++ b/test/smp/regression/threadx_thread_multiple_sleep_test.c @@ -43,8 +43,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 3, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -56,8 +56,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 3, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -69,8 +69,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 3, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -82,8 +82,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 3, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; diff --git a/test/smp/regression/threadx_thread_multiple_suspension_test.c b/test/smp/regression/threadx_thread_multiple_suspension_test.c index 0e4e5c06..01c42e8f 100644 --- a/test/smp/regression/threadx_thread_multiple_suspension_test.c +++ b/test/smp/regression/threadx_thread_multiple_suspension_test.c @@ -1,5 +1,5 @@ -/* This test is designed to see if multiple threads can be created and suspend. - The order the suspension and resumption occurs makes sure everything is working +/* This test is designed to see if multiple threads can be created and suspend. + The order the suspension and resumption occurs makes sure everything is working right. All the counters should increment at the same rate. */ #include @@ -59,8 +59,8 @@ CHAR *pointer; create information. */ /* Create thread 0. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 13, 13, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -73,8 +73,8 @@ CHAR *pointer; } /* Create thread 1. */ - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, (TX_MAX_PRIORITIES/2), (TX_MAX_PRIORITIES/2), TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -87,8 +87,8 @@ CHAR *pointer; } /* Create thread 2. */ - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, (TX_MAX_PRIORITIES/2), (TX_MAX_PRIORITIES/2), TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -101,8 +101,8 @@ CHAR *pointer; } /* Create thread 3. */ - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, (TX_MAX_PRIORITIES/2), (TX_MAX_PRIORITIES/2), TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -115,8 +115,8 @@ CHAR *pointer; } /* Create thread 4. */ - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -129,8 +129,8 @@ CHAR *pointer; } /* Create thread 5. Make this thread non-preemptable for the range of priorities here... */ - status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, (TX_MAX_PRIORITIES-1), 13, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -160,7 +160,7 @@ static void thread_0_entry(ULONG thread_input) /* Suspend this thread... */ tx_thread_suspend(&thread_0); - + /* Resume thread 5... */ tx_thread_resume(&thread_5); } @@ -252,7 +252,7 @@ UINT status; } /* Make sure that each thread has run once. */ - if ((thread_0_counter != 1) || (thread_1_counter != 1) || + if ((thread_0_counter != 1) || (thread_1_counter != 1) || (thread_2_counter != 1) || (thread_3_counter != 1) || (thread_4_counter != 1)) { @@ -277,7 +277,7 @@ UINT status; } /* Make sure that each thread has run once. */ - if ((thread_0_counter != 1) || (thread_1_counter != 1) || + if ((thread_0_counter != 1) || (thread_1_counter != 1) || (thread_2_counter != 1) || (thread_3_counter != 1) || (thread_4_counter != 1)) { @@ -301,7 +301,7 @@ UINT status; } /* Make sure that each thread has run once. */ - if ((thread_0_counter != 1) || (thread_1_counter != 1) || + if ((thread_0_counter != 1) || (thread_1_counter != 1) || (thread_2_counter != 1) || (thread_3_counter != 1) || (thread_4_counter != 1)) { @@ -325,7 +325,7 @@ UINT status; } /* Make sure that each thread has run once. */ - if ((thread_0_counter != 1) || (thread_1_counter != 1) || + if ((thread_0_counter != 1) || (thread_1_counter != 1) || (thread_2_counter != 1) || (thread_3_counter != 1) || (thread_4_counter != 1)) { @@ -349,7 +349,7 @@ UINT status; } /* Make sure that each thread has run once. */ - if ((thread_0_counter != 1) || (thread_1_counter != 1) || + if ((thread_0_counter != 1) || (thread_1_counter != 1) || (thread_2_counter != 1) || (thread_3_counter != 1) || (thread_4_counter != 1)) { @@ -373,7 +373,7 @@ UINT status; } /* Make sure that each thread has run once. */ - if ((thread_0_counter != 1) || (thread_1_counter != 1) || + if ((thread_0_counter != 1) || (thread_1_counter != 1) || (thread_2_counter != 1) || (thread_3_counter != 1) || (thread_4_counter != 1)) { @@ -398,7 +398,7 @@ UINT status; } /* Make sure that each thread has run twice. */ - if ((thread_0_counter != 2) || (thread_1_counter != 2) || + if ((thread_0_counter != 2) || (thread_1_counter != 2) || (thread_2_counter != 2) || (thread_3_counter != 2) || (thread_4_counter != 2)) { @@ -410,7 +410,7 @@ UINT status; /* Suspend a thread that is already suspended. */ status = tx_thread_suspend(&thread_4); - + /* Check for error condition. */ if (status != TX_SUCCESS) { @@ -420,7 +420,7 @@ UINT status; } else { - + /* Increment thread 5 counter. */ thread_5_counter++; diff --git a/test/smp/regression/threadx_thread_multiple_time_slice_test.c b/test/smp/regression/threadx_thread_multiple_time_slice_test.c index 6e1f61fd..f3e9fbf0 100644 --- a/test/smp/regression/threadx_thread_multiple_time_slice_test.c +++ b/test/smp/regression/threadx_thread_multiple_time_slice_test.c @@ -1,4 +1,4 @@ -/* This test is designed to see if two threads can be created and execute with a time-slice. +/* This test is designed to see if two threads can be created and execute with a time-slice. Thread 7 should run twice as long because it has more of a time-slice. */ #include @@ -50,8 +50,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 2, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -63,8 +63,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 4, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -77,8 +77,8 @@ CHAR *pointer; } /* Create control thread. */ - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -92,10 +92,10 @@ CHAR *pointer; #ifndef TX_DISABLE_PREEMPTION_THRESHOLD - /* Create threads with preemption-threshold and time-slice, such and make sure time-slice is defeated by + /* Create threads with preemption-threshold and time-slice, such and make sure time-slice is defeated by preemption-threshold. */ - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 18, 17, 2, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -107,8 +107,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, 4, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -161,7 +161,7 @@ static void thread_1_entry(ULONG thread_input) static void thread_2_entry(ULONG thread_input) { - + unsigned long counter_sum; #ifndef TX_DISABLE_PREEMPTION_THRESHOLD UINT status; @@ -177,7 +177,7 @@ UINT status; /* Increment thread 2 counter. */ thread_2_counter++; - /* Compute the delta. Should be twice as much, but some test environments (Windows/Linux) are + /* Compute the delta. Should be twice as much, but some test environments (Windows/Linux) are not as good in terms of real time processing. */ counter_sum = thread_0_counter; counter_sum = counter_sum + (thread_0_counter/4); @@ -187,19 +187,19 @@ UINT status; /* Thread Time-slice error. */ printf("ERROR #6\n"); test_control_return(1); - } + } #ifdef TX_DISABLE_PREEMPTION_THRESHOLD else { /* Successful Thread Time-slice test. */ printf("SUCCESS!\n"); test_control_return(0); - } + } #else /* Now suspend threads 0 and 1 so we can let 3 and 4 run. */ status = tx_thread_suspend(&thread_0); status += tx_thread_suspend(&thread_1); - + /* Check status. */ if (status) { @@ -207,7 +207,7 @@ UINT status; printf("ERROR #7\n"); test_control_return(1); } - + /* Now sleep and see if thread 4 ever runs. */ tx_thread_sleep(4); @@ -257,7 +257,7 @@ static void thread_4_entry(ULONG thread_input) { /* We should never get here! */ - + /* Increment thread 4 counter. */ thread_4_counter++; diff --git a/test/smp/regression/threadx_thread_preemptable_suspension_test.c b/test/smp/regression/threadx_thread_preemptable_suspension_test.c index b1c1bc52..8e4dbdd6 100644 --- a/test/smp/regression/threadx_thread_preemptable_suspension_test.c +++ b/test/smp/regression/threadx_thread_preemptable_suspension_test.c @@ -1,6 +1,6 @@ -/* This test is designed to see if multiple threads can be created and suspended. - The order the suspension and resumption occurs makes sure everything is working right. - All the counters should increment at the same rate. This test differs from test 4 in +/* This test is designed to see if multiple threads can be created and suspended. + The order the suspension and resumption occurs makes sure everything is working right. + All the counters should increment at the same rate. This test differs from test 4 in that thread 5 is preemptable. */ #include @@ -58,8 +58,8 @@ CHAR *pointer; create information. */ /* Create thread 0. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 13, 13, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -72,8 +72,8 @@ CHAR *pointer; } /* Create thread 1. */ - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -86,8 +86,8 @@ CHAR *pointer; } /* Create thread 2. */ - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -100,8 +100,8 @@ CHAR *pointer; } /* Create thread 3. */ - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -114,8 +114,8 @@ CHAR *pointer; } /* Create thread 4. */ - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -128,8 +128,8 @@ CHAR *pointer; } /* Create thread 5. Make this thread fully preemptable... */ - status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -159,7 +159,7 @@ static void thread_0_entry(ULONG thread_input) /* Suspend this thread... */ tx_thread_suspend(&thread_0); - + /* Resume thread 5... */ tx_thread_resume(&thread_5); } @@ -251,7 +251,7 @@ UINT status; } /* Make sure that each thread has run once. */ - if ((thread_0_counter != 1) || (thread_1_counter != 1) || + if ((thread_0_counter != 1) || (thread_1_counter != 1) || (thread_2_counter != 1) || (thread_3_counter != 1) || (thread_4_counter != 1)) { @@ -276,7 +276,7 @@ UINT status; } /* Make sure that each thread has run the proper amount. */ - if ((thread_0_counter != 2) || (thread_1_counter != 1) || + if ((thread_0_counter != 2) || (thread_1_counter != 1) || (thread_2_counter != 1) || (thread_3_counter != 1) || (thread_4_counter != 1)) { @@ -300,7 +300,7 @@ UINT status; } /* Make sure that each thread has run the proper amount. */ - if ((thread_0_counter != 2) || (thread_1_counter != 2) || + if ((thread_0_counter != 2) || (thread_1_counter != 2) || (thread_2_counter != 1) || (thread_3_counter != 1) || (thread_4_counter != 1)) { @@ -324,7 +324,7 @@ UINT status; } /* Make sure that each thread has the proper amount. */ - if ((thread_0_counter != 2) || (thread_1_counter != 2) || + if ((thread_0_counter != 2) || (thread_1_counter != 2) || (thread_2_counter != 2) || (thread_3_counter != 1) || (thread_4_counter != 1)) { @@ -348,7 +348,7 @@ UINT status; } /* Make sure that each thread has run the proper amount. */ - if ((thread_0_counter != 2) || (thread_1_counter != 2) || + if ((thread_0_counter != 2) || (thread_1_counter != 2) || (thread_2_counter != 2) || (thread_3_counter != 2) || (thread_4_counter != 1)) { @@ -372,7 +372,7 @@ UINT status; } /* Make sure that each thread has run once. */ - if ((thread_0_counter != 2) || (thread_1_counter != 2) || + if ((thread_0_counter != 2) || (thread_1_counter != 2) || (thread_2_counter != 2) || (thread_3_counter != 2) || (thread_4_counter != 2)) { @@ -397,7 +397,7 @@ UINT status; } /* Make sure that each thread has run twice. */ - if ((thread_0_counter != 2) || (thread_1_counter != 2) || + if ((thread_0_counter != 2) || (thread_1_counter != 2) || (thread_2_counter != 2) || (thread_3_counter != 2) || (thread_4_counter != 2)) { diff --git a/test/smp/regression/threadx_thread_preemption_change_test.c b/test/smp/regression/threadx_thread_preemption_change_test.c index a16b2633..5f9726c0 100644 --- a/test/smp/regression/threadx_thread_preemption_change_test.c +++ b/test/smp/regression/threadx_thread_preemption_change_test.c @@ -51,8 +51,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 15, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -66,8 +66,8 @@ CHAR *pointer; #ifndef TX_DISABLE_PREEMPTION_THRESHOLD /* skip this test and pretend it passed */ - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -79,8 +79,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 14, 14, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -126,7 +126,7 @@ UINT i; /* Increment thread 0 counter. */ thread_0_counter++; - /* Resume thread 1, which has a higher priority. Preemption is disabled + /* Resume thread 1, which has a higher priority. Preemption is disabled though so thread 1 should not run yet. */ status = tx_thread_resume(&thread_1); @@ -169,7 +169,7 @@ UINT i; } /* Change the preemption threshold back to 15. */ - status = tx_thread_preemption_change(&thread_0, 15, &old_threshold); + status = tx_thread_preemption_change(&thread_0, 15, &old_threshold); /* Check status and run counters of other threads. */ if ((status != TX_SUCCESS) || (thread_1_counter != 1) || (thread_2_counter != 0) || @@ -181,7 +181,7 @@ UINT i; test_control_return(1); } - /* Resume thread 2. This should preempt because it is priority 14 and the + /* Resume thread 2. This should preempt because it is priority 14 and the current preemption threshold is 15. */ status = tx_thread_resume(&thread_2); @@ -194,16 +194,16 @@ UINT i; test_control_return(1); } - /* At this point, we are going to loop through preemption changes that result in + /* At this point, we are going to loop through preemption changes that result in preemption. */ for (i = 0; i < (TX_THREAD_EXECUTE_LOG_SIZE*3); i++) { /* Change the preemption threshold back to 14. */ - status = tx_thread_preemption_change(&thread_0, 14, &old_threshold); + status = tx_thread_preemption_change(&thread_0, 14, &old_threshold); /* Check status. */ - if (status != TX_SUCCESS) + if (status != TX_SUCCESS) { /* Thread error. */ @@ -213,7 +213,7 @@ UINT i; /* Resume thread 2 again. */ status = tx_thread_resume(&thread_2); - + /* Check status an thread 2 run counter. */ if ((status != TX_SUCCESS) && (thread_2_counter != (i+1))) { @@ -222,9 +222,9 @@ UINT i; printf("ERROR #11\n"); test_control_return(1); } - + /* Change the preemption threshold back to 15 to allow thread 2 to run. */ - status = tx_thread_preemption_change(&thread_0, 15, &old_threshold); + status = tx_thread_preemption_change(&thread_0, 15, &old_threshold); /* Check status an thread 2 run counter. */ if ((status != TX_SUCCESS) && (thread_2_counter != (i+2))) @@ -237,21 +237,21 @@ UINT i; } /* Change the priority of threads 0 and 1. */ - status = tx_thread_priority_change(&thread_0, 7, &old_threshold); - status += tx_thread_priority_change(&thread_1, 5, &old_threshold); + status = tx_thread_priority_change(&thread_0, 7, &old_threshold); + status += tx_thread_priority_change(&thread_1, 5, &old_threshold); /* Check status. */ - if (status != TX_SUCCESS) + if (status != TX_SUCCESS) { /* Thread error. */ printf("ERROR #13\n"); test_control_return(1); - } + } /* Change the preemption-threshold of this thread. */ status = tx_thread_preemption_change(&thread_0, 0, &old_threshold); - + /* Check status. */ if ((status != TX_SUCCESS) || (old_threshold != 7)) { @@ -259,29 +259,29 @@ UINT i; /* Thread error. */ printf("ERROR #14\n"); test_control_return(1); - } - + } + /* Get the mutex that has priority inheritance. */ status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); /* Check status. */ - if (status != TX_SUCCESS) + if (status != TX_SUCCESS) { /* Thread error. */ printf("ERROR #15\n"); test_control_return(1); - } - + } + /* Resume thread 1 so that it can suspend on the mutex and automatically raise its priority. */ tx_thread_resume(&thread_1); - + /* Self suspend so that thread 1 and run. */ tx_thread_suspend(&thread_0); - + /* Restore the preemption-threshold of this thread. */ status = tx_thread_preemption_change(&thread_0, old_threshold, &old_threshold); - + /* Check status. */ if ((status != TX_SUCCESS) || (old_threshold != 0) || (thread_0.tx_thread_priority != 5) || (thread_0.tx_thread_preempt_threshold != 5)) { @@ -289,7 +289,7 @@ UINT i; /* Thread error. */ printf("ERROR #16\n"); test_control_return(1); - } + } /* Ensure thread 0's entries in these lists were removed. */ if (_tx_thread_preempted_maps[0] != 0 || @@ -302,7 +302,7 @@ UINT i; } /* Let thread 1 run again so it can release the mutex and undo the priority inheritance. */ - status = tx_mutex_put(&mutex_0); + status = tx_mutex_put(&mutex_0); /* Check status. */ if ((status != TX_SUCCESS) || (thread_0.tx_thread_priority != 7) || (thread_0.tx_thread_preempt_threshold != 7)) @@ -311,7 +311,7 @@ UINT i; /* Thread error. */ printf("ERROR #18\n"); test_control_return(1); - } + } /* Test direct call to the thread preemption change routine with a threshold greater than the current priority. */ status = _tx_thread_preemption_change(&thread_0, 8, &old_threshold); @@ -345,7 +345,7 @@ UINT old_threshold; /* Self suspend after initial run. */ tx_thread_suspend(&thread_1); - + /* Increment the thread counter. */ thread_1_counter++; @@ -359,7 +359,7 @@ UINT old_threshold; tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); /* Release the mutex. */ - tx_mutex_put(&mutex_0); + tx_mutex_put(&mutex_0); } @@ -368,10 +368,10 @@ static void thread_2_entry(ULONG thread_input) while(1) { - + /* Increment thread counter. */ thread_2_counter++; - + /* Self suspend. */ tx_thread_suspend(&thread_2); } diff --git a/test/smp/regression/threadx_thread_priority_change.c b/test/smp/regression/threadx_thread_priority_change.c index af65c5e0..63863544 100644 --- a/test/smp/regression/threadx_thread_priority_change.c +++ b/test/smp/regression/threadx_thread_priority_change.c @@ -49,7 +49,7 @@ void test_control_return(UINT status); VOID _tx_thread_smp_simple_priority_change(TX_THREAD *thread_ptr,UINT new_priority); -/* This test routine is used to get a thread of a non ready state. */ +/* This test routine is used to get a thread of a non ready state. */ void suspend_thread(void) { @@ -57,7 +57,7 @@ TX_INTERRUPT_SAVE_AREA TX_THREAD *thread_ptr; - + /* Setup the thread pointer. */ thread_ptr = &thread_0; @@ -104,7 +104,7 @@ UINT saved_preempt_disable; #ifndef TX_NOT_INTERRUPTABLE /* Determine if we have the interrupt condition we are looking for. */ - if ((thread_3.tx_thread_priority == 6) && + if ((thread_3.tx_thread_priority == 6) && (thread_3.tx_thread_state == TX_READY) && (_tx_thread_priority_list[6] != &thread_3) && (thread_3_counter > 100)) @@ -112,16 +112,16 @@ UINT saved_preempt_disable; /* Save the preempt disable flag. */ saved_preempt_disable = _tx_thread_preempt_disable; - + /* Clear the preempt disable flag to ensure the API works correctly. */ _tx_thread_preempt_disable = 0; /* Suspend the thread to generate the condition. */ tx_thread_suspend(&thread_3); - + /* Restore the preempt disable flag. */ _tx_thread_preempt_disable = saved_preempt_disable; - + /* Done trying to generate this test condition. */ test_isr_dispatch = TX_NULL; } @@ -130,7 +130,7 @@ UINT saved_preempt_disable; /* Can't get the interrupt inside the code wit TX_NOT_INTERRUPTABLE defined, so simply stop after thread_3_counter > 100. */ if (thread_3_counter > 100) { - + /* Done trying to generate this test condition. */ test_isr_dispatch = TX_NULL; } @@ -155,8 +155,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -168,8 +168,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 22, 22, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -181,20 +181,20 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 30, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 5, 5, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 6, 6, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, TEST_STACK_SIZE_PRINTF, 16, 15, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -232,11 +232,11 @@ TX_THREAD *temp_thread; /* Increment thread 0 counter. */ thread_0_counter++; - /* Change priority to 22, to match that of the next highest priority ready thread. - This is to test the update of the priority list when a thread is moved to a + /* Change priority to 22, to match that of the next highest priority ready thread. + This is to test the update of the priority list when a thread is moved to a priority with already ready threads. */ status = tx_thread_priority_change(&thread_0, 22, &old_priority); - + /* Check status, return priority, and run count of other thread. */ if ((status != TX_SUCCESS) || (old_priority != 16) || (thread_1_counter != 0)) { @@ -247,7 +247,7 @@ TX_THREAD *temp_thread; } /* Restore original priority. */ - tx_thread_priority_change(&thread_0, old_priority, &old_priority); + tx_thread_priority_change(&thread_0, old_priority, &old_priority); /* See if we can change priority of this thread. */ status = tx_thread_priority_change(&thread_0, 7, &old_priority); @@ -285,7 +285,7 @@ TX_THREAD *temp_thread; test_control_return(1); } - /* Thread 1 should have run already... Raise this threads priority + /* Thread 1 should have run already... Raise this threads priority back up. */ status = tx_thread_priority_change(&thread_0, 8, &old_priority); @@ -345,10 +345,10 @@ TX_THREAD *temp_thread; printf("ERROR #11\n"); test_control_return(1); } - + /* Now thread 1 should be suspended. Let's change thread 0's priority and make sure thread 2 doesn't run yet! */ status = tx_thread_priority_change(&thread_0, 7, &old_priority); - + /* Check status, return priority, and run count of other thread. */ if ((status != TX_SUCCESS) || (old_priority != 8) || (thread_1_counter != 2) || (thread_2_counter != 0)) { @@ -357,13 +357,13 @@ TX_THREAD *temp_thread; printf("ERROR #12\n"); test_control_return(1); } - + /* Now resume thread 1, it won't run because it's priority is less than this thread. */ status = tx_thread_resume(&thread_1); - + /* Change the priority of thread 1 - the non executing thread to test that path. */ status += tx_thread_priority_change(&thread_1, 23, &old_priority); - + /* Check status, return priority, and run count of other thread. */ if ((status != TX_SUCCESS) || (old_priority != 7) || (thread_1_counter != 2) || (thread_2_counter != 0)) { @@ -376,7 +376,7 @@ TX_THREAD *temp_thread; #ifndef TX_DISABLE_PREEMPTION_THRESHOLD /* Now setup the preemption-threshold for thread 1. */ status = tx_thread_preemption_change(&thread_1, 14, &old_threshold); - + /* Check status, return priority, and run count of other thread. */ if ((status != TX_SUCCESS) || (old_threshold != 23) || (thread_1_counter != 2) || (thread_2_counter != 0)) { @@ -385,13 +385,13 @@ TX_THREAD *temp_thread; printf("ERROR #14\n"); test_control_return(1); } - + /* Resume a higher priority preemption-threshold thread. */ status = tx_thread_resume(&thread_5); /* Now lower this thread's priority. */ status += tx_thread_priority_change(&thread_0, 15, &old_priority); - + /* Check status, return priority, and run count of other thread. */ if ((status != TX_SUCCESS) || (old_priority != 7) || (thread_1_counter != 2) || (thread_2_counter != 0) || (thread_5_counter != 0)) { @@ -413,26 +413,26 @@ TX_THREAD *temp_thread; /* Suspend thread 0. */ suspend_thread(); - + /* Resume thread 0. */ tx_thread_resume(&thread_0); - + /* Change priority to get avoid the reset of the priority list. */ tx_thread_priority_change(&thread_0, 16, &old_priority); - + /* Move the priority back so we have some room to test. */ tx_thread_priority_change(&thread_0, 7, &old_priority); - + /* Now create the invalid core index situation. */ priority_change_extension_selection = 1; tx_thread_priority_change(&thread_0, 8, &old_priority); thread_0.tx_thread_smp_core_mapped = 0; - + /* Now fiddle with the original priority to satisfy that branch. */ priority_change_extension_selection = 2; tx_thread_priority_change(&thread_0, 9, &old_priority); _tx_thread_execute_ptr[0] = &thread_0; - + /* Create the condition where original pt thread is same as the current thread. */ temp_thread = _tx_thread_preemption__threshold_scheduled; priority_change_extension_selection = 3; @@ -446,11 +446,11 @@ TX_THREAD *temp_thread; temp_thread = _tx_thread_preemption__threshold_scheduled; priority_change_extension_selection = 4; tx_thread_priority_change(&thread_0, 15, &old_priority); - _tx_thread_preemption__threshold_scheduled = temp_thread; + _tx_thread_preemption__threshold_scheduled = temp_thread; /* Decrement the preempt disable count. */ _tx_thread_preempt_disable--; - + /* Restore interrupts. */ TX_RESTORE @@ -458,7 +458,7 @@ TX_THREAD *temp_thread; new priority is less than the inheritance priority. */ thread_0.tx_thread_inherit_priority = 0; _tx_thread_smp_simple_priority_change(&thread_0, 16); - + /* Successful test. */ printf("SUCCESS!\n"); test_control_return(0); @@ -484,12 +484,12 @@ static void thread_2_entry(ULONG thread_input) while(1) { - + /* This thread should never run! */ /* Increment the thread counter. */ thread_2_counter++; - + /* Self suspend. */ tx_thread_suspend(&thread_2); } @@ -520,12 +520,12 @@ UINT loop; /* Raise priority of thread 3 for code coverage. */ tx_thread_priority_change(&thread_3, 6, &old_priority); tx_thread_priority_change(&thread_3, 5, &old_priority); - + /* Check to see if thread 4 has run... it should not have executed yet. If it does, set the thread_1_counter to indicate an error! */ if (thread_4_counter) thread_1_counter++; - + } while (test_isr_dispatch); } diff --git a/test/smp/regression/threadx_thread_relinquish_test.c b/test/smp/regression/threadx_thread_relinquish_test.c index 2a48717b..7b46c820 100644 --- a/test/smp/regression/threadx_thread_relinquish_test.c +++ b/test/smp/regression/threadx_thread_relinquish_test.c @@ -73,8 +73,8 @@ CHAR *pointer; create information. */ /* Create thread 0. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -87,8 +87,8 @@ CHAR *pointer; } /* Create thread 1. */ - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -101,8 +101,8 @@ CHAR *pointer; } /* Create thread 2. */ - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -115,8 +115,8 @@ CHAR *pointer; } /* Create thread 3. */ - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -129,8 +129,8 @@ CHAR *pointer; } /* Create thread 4. */ - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 31, 31, 1, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -143,8 +143,8 @@ CHAR *pointer; } /* Create thread 5. */ - status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, TEST_STACK_SIZE_PRINTF, 31, 15, 1, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -157,8 +157,8 @@ CHAR *pointer; } /* Create thread 6. */ - status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, + pointer, TEST_STACK_SIZE_PRINTF, 31, 31, 1, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -171,8 +171,8 @@ CHAR *pointer; } /* Create thread 7. */ - status = tx_thread_create(&thread_7, "thread 7", thread_7_entry, 7, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_7, "thread 7", thread_7_entry, 7, + pointer, TEST_STACK_SIZE_PRINTF, 31, 31, 1, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -185,8 +185,8 @@ CHAR *pointer; } /* Create thread 8. */ - status = tx_thread_create(&thread_8, "thread 8", thread_8_entry, 8, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_8, "thread 8", thread_8_entry, 8, + pointer, TEST_STACK_SIZE_PRINTF, 31, 31, 1, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -199,8 +199,8 @@ CHAR *pointer; } /* Create thread 9. */ - status = tx_thread_create(&thread_9, "thread 9", thread_9_entry, 9, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_9, "thread 9", thread_9_entry, 9, + pointer, TEST_STACK_SIZE_PRINTF, 31, 31, 1, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -280,7 +280,7 @@ UINT old_priority; (thread_2_counter != 1) || (thread_0.tx_thread_state != TX_READY) || (thread_1.tx_thread_state != TX_READY) || (thread_2.tx_thread_state != TX_READY)) { - + /* Thread Relinquish error. */ printf("ERROR #11\n"); test_control_return(1); @@ -291,7 +291,7 @@ UINT old_priority; /* Immediate response relinquish. */ tx_thread_relinquish(); - + /* All other threads should be completed now. */ if ((thread_0.tx_thread_state != TX_COMPLETED) || (thread_1.tx_thread_state != TX_COMPLETED) || (thread_2.tx_thread_state != TX_COMPLETED)) @@ -304,20 +304,20 @@ UINT old_priority; /* Execute immediate response relinquish. */ tx_thread_relinquish(); - + /* Move to the lowest default priority. */ - status = tx_thread_priority_change(&thread_3, 31, &old_priority); - + status = tx_thread_priority_change(&thread_3, 31, &old_priority); + /* Temporarily make enable preemption-threshold with this thread. */ status += tx_thread_preemption_change(&thread_3, 3, &old_threshold); - + /* Execute immediate response, bypassing the error checking. */ _tx_thread_preemption__threshold_scheduled = TX_NULL; _tx_thread_relinquish(); /* Restore the preemtion-threshold and priority. */ status += tx_thread_preemption_change(&thread_3, old_threshold, &old_threshold); - + /* Enable all cores for all threads. */ status += tx_thread_smp_core_exclude(&thread_4, 0); status += tx_thread_smp_core_exclude(&thread_5, 0); @@ -325,8 +325,8 @@ UINT old_priority; status += tx_thread_smp_core_exclude(&thread_7, 0); status += tx_thread_smp_core_exclude(&thread_8, 0); status += tx_thread_smp_core_exclude(&thread_9, 0); - - /* Now lets resume threads 4 through 9. Thread 5 has preemption-threshold set which will excercise + + /* Now lets resume threads 4 through 9. Thread 5 has preemption-threshold set which will excercise the preemption-threshold logic. */ status += tx_thread_resume(&thread_4); status += tx_thread_resume(&thread_5); @@ -334,17 +334,17 @@ UINT old_priority; status += tx_thread_resume(&thread_7); status += tx_thread_resume(&thread_8); status += tx_thread_resume(&thread_9); - + /* Now relinquish to let these other threads run. */ tx_thread_relinquish(); - + /* Sleep for 20 ticks to test the paths. */ tx_thread_sleep(20); - + /* Now see if the results are as expected. */ if (status != TX_SUCCESS) { - + /* Thread Relinquish error. */ printf("ERROR #13\n"); test_control_return(1); diff --git a/test/smp/regression/threadx_thread_reset_test.c b/test/smp/regression/threadx_thread_reset_test.c index ff3531a5..a709d163 100644 --- a/test/smp/regression/threadx_thread_reset_test.c +++ b/test/smp/regression/threadx_thread_reset_test.c @@ -35,7 +35,7 @@ static void entry_exit_notify(TX_THREAD *thread_ptr, UINT type) /* Check for the appropriate thread. */ if (thread_ptr != &thread_0) return; - + /* Check for type. */ if (type == TX_THREAD_ENTRY) thread_0_enter++; @@ -63,8 +63,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -94,8 +94,8 @@ CHAR *pointer; #endif - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -107,8 +107,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -150,11 +150,11 @@ UINT status; /* Attempt to delete thread 2, which is in the wrong stat for deleting. */ status = tx_thread_delete(&thread_2); - + /* Check for the proper status. */ if (status != TX_DELETE_ERROR) { - + /* Thread delete error. */ printf("ERROR #5\n"); test_control_return(1); @@ -177,11 +177,11 @@ UINT status; /* Call thread reset on thread 2, which should result in an error. */ status = tx_thread_reset(&thread_2); - + /* Check for proper status. */ if (status != TX_NOT_DONE) { - + /* Thread reset error. */ printf("ERROR #7\n"); test_control_return(1); @@ -206,12 +206,12 @@ UINT status; /* Terminate thread 0. */ status = tx_thread_terminate(&thread_0); - status += tx_thread_reset(&thread_0); - - + status += tx_thread_reset(&thread_0); + + /* Now resume thread 0 to let it run. */ status += tx_thread_resume(&thread_0); - + /* Determine if the first Thread has run and if it's current state is finished. */ if ((thread_0.tx_thread_state != TX_COMPLETED) || (thread_0_counter != 2) || @@ -228,7 +228,7 @@ UINT status; } else { - + /* Successful thread finish test. */ printf("SUCCESS!\n"); diff --git a/test/smp/regression/threadx_thread_simple_sleep_non_clear_test.c b/test/smp/regression/threadx_thread_simple_sleep_non_clear_test.c index 5713e41d..67a2cf00 100644 --- a/test/smp/regression/threadx_thread_simple_sleep_non_clear_test.c +++ b/test/smp/regression/threadx_thread_simple_sleep_non_clear_test.c @@ -32,15 +32,15 @@ CHAR *pointer; /* Put first available memory address into a character pointer. */ pointer = (CHAR *) first_unused_memory; - /* Place a 1 in the thread control block to simulate a control block created in + /* Place a 1 in the thread control block to simulate a control block created in random memory. */ thread_0.tx_thread_timer.tx_timer_internal_re_initialize_ticks = 1; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 3, TX_AUTO_START); /* Check for status. */ diff --git a/test/smp/regression/threadx_thread_simple_sleep_test.c b/test/smp/regression/threadx_thread_simple_sleep_test.c index b87bd82d..5b8b12b3 100644 --- a/test/smp/regression/threadx_thread_simple_sleep_test.c +++ b/test/smp/regression/threadx_thread_simple_sleep_test.c @@ -35,8 +35,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 3, TX_AUTO_START); /* Check for status. */ diff --git a/test/smp/regression/threadx_thread_simple_suspend_test.c b/test/smp/regression/threadx_thread_simple_suspend_test.c index 52215a75..a05797ec 100644 --- a/test/smp/regression/threadx_thread_simple_suspend_test.c +++ b/test/smp/regression/threadx_thread_simple_suspend_test.c @@ -1,4 +1,4 @@ -/* This test is designed to see if a thread can successfully suspend itself in a single +/* This test is designed to see if a thread can successfully suspend itself in a single thread system. This also tests a thread created that is not automatically enabled. */ #include @@ -39,8 +39,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -52,8 +52,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; diff --git a/test/smp/regression/threadx_thread_sleep_for_100ticks_test.c b/test/smp/regression/threadx_thread_sleep_for_100ticks_test.c index 69eadbc6..d5c335f0 100644 --- a/test/smp/regression/threadx_thread_sleep_for_100ticks_test.c +++ b/test/smp/regression/threadx_thread_sleep_for_100ticks_test.c @@ -99,7 +99,7 @@ ULONG i; if (loop_count < min_loop_count) min_loop_count = loop_count; if (loop_count > max_loop_count) - max_loop_count = loop_count; + max_loop_count = loop_count; lower_bound = loop_count - 1; upper_bound = loop_count + 1; @@ -110,18 +110,18 @@ ULONG i; if ((current_itterations < lower_bound) || (current_itterations > upper_bound)) current_itterations = lower_bound; - + #ifdef DEBUG_1 /* Last loop count. */ last_loop_count = loop_count; #endif - + /* Reset the loop count to all ones! */ loop_count = 0xFFFFFFFF; } count++; for (i = 0; i < (count%32); i++) - destination++; + destination++; /* Determine if the ISR is in the mode to wakeup the thread suspending with a timeout. */ if (isr_test_suspend_interrupt) @@ -135,26 +135,26 @@ ULONG i; if ((_tx_thread_preempt_disable) && (thread_0.tx_thread_timer.tx_timer_internal_list_head == TX_NULL)) { - + /* Set the flag showing the condition is present. */ isr_test_suspend_interrupted_condition = TX_TRUE; - + /* All done with the test. */ isr_test_suspend_interrupt = TX_FALSE; } - + /* Post to the semaphore to wakeup the thread. */ tx_semaphore_put(&test_semaphore); - } - + } + return; } #endif #endif - + /* Increment the ISR count. */ isr_count++; - + /* Call sleep from ISR to check for error! */ status = tx_thread_sleep(100); @@ -165,7 +165,7 @@ ULONG i; error = 1; } - + /* End the ISR. */ test_isr_dispatch = TX_NULL; } @@ -190,8 +190,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 3, TX_AUTO_START); /* Check for status. */ @@ -221,7 +221,7 @@ CHAR *pointer; current_itterations = 0; #ifdef DEBUG_1 last_loop_count = 0x0; -#endif +#endif #endif #endif } @@ -246,11 +246,11 @@ volatile ULONG value = 0; /* Call sleep with an expiration of 0 and test error code. */ status = tx_thread_sleep(0); - + /* Check error code. */ if (status != TX_SUCCESS) { - + /* Thread Simple Sleep error. */ printf("ERROR #3\n"); test_control_return(1); @@ -274,10 +274,10 @@ volatile ULONG value = 0; /* Callibrate the loop count from thread sleep. */ for (i = 0; i < 180; i++) { - + /* Sleep to get a fresh time. */ tx_thread_sleep(1); - + /* Set the loop count to 0 and start counting.... */ loop_count = 0; start_time = _tx_timer_system_clock; @@ -288,7 +288,7 @@ volatile ULONG value = 0; delay_function(); loop_count++; } while (start_time == _tx_timer_system_clock); - + /* Wait to reset the loop count. */ tx_thread_sleep(1); } @@ -323,7 +323,7 @@ volatile ULONG value = 0; /* Call delay function. */ delay_function(); loop_count++; - } while (loop_count < current_itterations); + } while (loop_count < current_itterations); /* Check for a timer interrupt... if so, just skip the semaphore get. */ if (start_time != _tx_timer_system_clock) @@ -331,7 +331,7 @@ volatile ULONG value = 0; /* Suspend on the semaphore for 20 ticks... */ tx_semaphore_get(&test_semaphore, 20); - + /* Adjust the current itterations. */ current_itterations++; if (current_itterations > upper_bound) @@ -391,14 +391,14 @@ volatile ULONG value = 0; /* Check for error. */ if (tx_time_get() < 100) { - + /* Thread Simple Sleep error. */ printf("ERROR #4\n"); test_control_return(1); - } + } #endif #endif - + /* Clear the tick count. */ tx_time_set(0); @@ -419,12 +419,12 @@ volatile ULONG value = 0; /* Check to make sure the ISR happened and the proper return value was present. */ if ((isr_count == 0) || (error)) { - + /* Thread Simple Sleep error. */ printf("ERROR #6\n"); test_control_return(1); } - else + else { /* Successful Simple Sleep test. */ diff --git a/test/smp/regression/threadx_thread_sleep_terminate_test.c b/test/smp/regression/threadx_thread_sleep_terminate_test.c index 871fc6e2..98862051 100644 --- a/test/smp/regression/threadx_thread_sleep_terminate_test.c +++ b/test/smp/regression/threadx_thread_sleep_terminate_test.c @@ -30,7 +30,7 @@ static void entry_exit_notify(TX_THREAD *thread_ptr, UINT type) /* Check for the appropriate thread. */ if (thread_ptr != &thread_1) return; - + /* Check for type. */ if (type == TX_THREAD_ENTRY) thread_1_enter++; @@ -58,8 +58,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -71,8 +71,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -144,7 +144,7 @@ UINT status; /* Now try to suspend a terminated thread. */ status = tx_thread_suspend(&thread_1); - + /* Check status. */ if (status != TX_SUSPEND_ERROR) { @@ -153,7 +153,7 @@ UINT status; printf("ERROR #6\n"); test_control_return(1); } - + /* Successful test. */ printf("SUCCESS!\n"); test_control_return(0); @@ -178,7 +178,7 @@ UINT status; /* Check status. */ if (status != TX_SUCCESS) { - thread_1_counter = 0; /* Make an error! */ + thread_1_counter = 0; /* Make an error! */ return; } } diff --git a/test/smp/regression/threadx_thread_stack_checking_test.c b/test/smp/regression/threadx_thread_stack_checking_test.c index 3ffe3841..940b6c6b 100644 --- a/test/smp/regression/threadx_thread_stack_checking_test.c +++ b/test/smp/regression/threadx_thread_stack_checking_test.c @@ -62,11 +62,11 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -75,8 +75,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -88,8 +88,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, TX_NO_TIME_SLICE, TX_DONT_START); thread_2_stack_start = pointer; pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -137,7 +137,7 @@ UINT status; /* Resume thread 1 to get the stack checking to take place. */ status = tx_thread_resume(&thread_1); - + /* Suspend to allow thread 1 to run. */ tx_thread_suspend(&thread_0); @@ -158,7 +158,7 @@ UINT status; } else { - + /* Success! */ printf("SUCCESS!\n"); test_control_return(0); @@ -201,10 +201,10 @@ TX_THREAD fake_thread; /* Increment thread 1 counter. */ thread_1_counter++; - /* Now, deregister the stack error handler and get into a spin condition. We will then + /* Now, deregister the stack error handler and get into a spin condition. We will then want to terminate thread 1 from thread 0 when it awakes! */ tx_thread_stack_error_notify(TX_NULL); - + /* Now resume thread 2 again to cause the stack error! */ tx_thread_resume(&thread_2); @@ -218,7 +218,7 @@ TX_THREAD fake_thread; static void thread_2_entry(ULONG thread_input) { - + /* Increment thread 1 counter. */ thread_2_counter++; } diff --git a/test/smp/regression/threadx_thread_terminate_delete_test.c b/test/smp/regression/threadx_thread_terminate_delete_test.c index dbe919f3..63fd6a69 100644 --- a/test/smp/regression/threadx_thread_terminate_delete_test.c +++ b/test/smp/regression/threadx_thread_terminate_delete_test.c @@ -42,7 +42,7 @@ static void entry_exit_notify(TX_THREAD *thread_ptr, UINT type) /* Check for the appropriate thread. */ if (thread_ptr != &thread_1) return; - + /* Check for type. */ if (type == TX_THREAD_ENTRY) thread_1_enter++; @@ -57,7 +57,7 @@ static void entry_exit_notify3(TX_THREAD *thread_ptr, UINT type) /* Check for the appropriate thread. */ if (thread_ptr != &thread_3) return; - + /* Check for type. */ if (type == TX_THREAD_ENTRY) thread_3_enter++; @@ -84,8 +84,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -97,8 +97,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -136,8 +136,8 @@ CHAR *pointer; #endif - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -149,8 +149,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 12, 12, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -231,7 +231,7 @@ UINT status; test_control_return(1); } - /* At this point, terminate thread 2 which should be in a suspended state + /* At this point, terminate thread 2 which should be in a suspended state right now. */ status = tx_thread_terminate(&thread_2); @@ -267,7 +267,7 @@ UINT status; test_control_return(1); } - /* At this point, terminate thread 3 which should be in a suspended state + /* At this point, terminate thread 3 which should be in a suspended state on the semaphore right now. */ status = tx_thread_terminate(&thread_3); diff --git a/test/smp/regression/threadx_thread_time_slice_change_test.c b/test/smp/regression/threadx_thread_time_slice_change_test.c index 8ee7df3b..0122fc2a 100644 --- a/test/smp/regression/threadx_thread_time_slice_change_test.c +++ b/test/smp/regression/threadx_thread_time_slice_change_test.c @@ -39,8 +39,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -52,8 +52,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 22, 22, 200, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -138,7 +138,7 @@ static void thread_1_entry(ULONG thread_input) while(1) { - + /* Identify. */ tx_thread_identify(); diff --git a/test/smp/regression/threadx_thread_wait_abort_and_isr_test.c b/test/smp/regression/threadx_thread_wait_abort_and_isr_test.c index 073151ac..5a65fced 100644 --- a/test/smp/regression/threadx_thread_wait_abort_and_isr_test.c +++ b/test/smp/regression/threadx_thread_wait_abort_and_isr_test.c @@ -54,7 +54,7 @@ static volatile UINT miss_count = 0; /* Check for proper error status. */ if (status != TX_CALLER_ERROR) { - + /* Blow up the test to force an error. */ condition_count = 10000000; semaphore_put_counter = 0xFFFF0000; @@ -68,7 +68,7 @@ static volatile UINT miss_count = 0; condition_count++; } - /* + /* It is possible for this test to get into a resonance condition in which the ISR never occurs while preemption is disabled (especially if the ISR is installed in the periodic timer interrupt handler, which is @@ -106,8 +106,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -119,8 +119,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -134,7 +134,7 @@ CHAR *pointer; /* Create semaphore - consumer producer semaphore. */ status = tx_semaphore_create(&semaphore_0, "semaphore 0", 0); - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -191,7 +191,7 @@ UINT status; } /* Check for the preempt disable flag being set. */ - if (_tx_thread_preempt_disable) + if (_tx_thread_preempt_disable) { /* Test error! */ @@ -208,13 +208,13 @@ UINT status; #ifdef TX_NOT_INTERRUPTABLE - /* Determine if we have a non-interruptable build of ThreadX. If so, just + /* Determine if we have a non-interruptable build of ThreadX. If so, just get out of this loop after 100 passes. */ if (thread_0_counter >= 100) break; #endif - + } } @@ -224,7 +224,7 @@ UINT status; #ifdef TX_NOT_INTERRUPTABLE /* At this point, check to see if we got all the semaphores! */ if ((thread_0_counter != (semaphore_put_counter - semaphore_0.tx_semaphore_count)) || - (condition_count != 0)) + (condition_count != 0)) #else /* At this point, check to see if we got all the semaphores! */ if (thread_0_counter != (semaphore_put_counter - semaphore_0.tx_semaphore_count)) diff --git a/test/smp/regression/threadx_thread_wait_abort_test.c b/test/smp/regression/threadx_thread_wait_abort_test.c index a2e8e42d..49852ec1 100644 --- a/test/smp/regression/threadx_thread_wait_abort_test.c +++ b/test/smp/regression/threadx_thread_wait_abort_test.c @@ -39,8 +39,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -52,8 +52,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; diff --git a/test/smp/regression/threadx_time_get_set_test.c b/test/smp/regression/threadx_time_get_set_test.c index 486294e9..8279cbd5 100644 --- a/test/smp/regression/threadx_time_get_set_test.c +++ b/test/smp/regression/threadx_time_get_set_test.c @@ -35,8 +35,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 3, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -67,7 +67,7 @@ ULONG current_time; /* Sleep for 1 tick to get a fresh timer. */ tx_thread_sleep(1); - + /* Set time to 0. */ tx_time_set(0); diff --git a/test/smp/regression/threadx_timer_activate_deactivate_test.c b/test/smp/regression/threadx_timer_activate_deactivate_test.c index a238ea33..69f9b38f 100644 --- a/test/smp/regression/threadx_timer_activate_deactivate_test.c +++ b/test/smp/regression/threadx_timer_activate_deactivate_test.c @@ -46,8 +46,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 3, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -89,13 +89,13 @@ TX_TIMER_INTERNAL **current_list_head; /* Call the timer thread entry function with an invalid value to make sure the code simply returns. */ _tx_timer_thread_entry(0); -#endif - +#endif + #ifndef TX_TIMER_PROCESS_IN_ISR tx_thread_resume(&_tx_timer_thread); #endif - + /* Call the internal timer activate function with 0 remaining time. */ test_timer.tx_timer_internal_remaining_ticks = 0; _tx_timer_system_activate(&test_timer); @@ -105,7 +105,7 @@ TX_TIMER_INTERNAL **current_list_head; list_head = TX_NULL; test_timer.tx_timer_internal_list_head = &list_head; _tx_timer_system_activate(&test_timer); - + /* Call the internal timer deactivate function to ensure the list head is not updated unless valid. */ list_head = TX_NULL; test_timer.tx_timer_internal_list_head = &list_head; @@ -115,8 +115,8 @@ TX_TIMER_INTERNAL **current_list_head; /* Call timer info get with a timer setup to exercise a path not possible, in order to exercise all conditionals. */ test_app_timer.tx_timer_internal.tx_timer_internal_list_head = (_tx_timer_list_end + 1); - status = _tx_timer_info_get(&test_app_timer, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); - + status = _tx_timer_info_get(&test_app_timer, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); + /* Deactivate and activate the timer. */ test_app_timer.tx_timer_internal.tx_timer_internal_active_next = &test_app_timer.tx_timer_internal; status += _tx_timer_deactivate(&test_app_timer); @@ -160,7 +160,7 @@ TX_TIMER_INTERNAL **current_list_head; /* Sleep for a 14 ticks. */ tx_thread_sleep(14); - /* At this point the initial expiration of the timer should have + /* At this point the initial expiration of the timer should have happened. */ if (timer_0_counter != 1) { @@ -174,7 +174,7 @@ TX_TIMER_INTERNAL **current_list_head; again! */ tx_thread_sleep(24); - /* At this point the timer counter should still be 1. */ + /* At this point the timer counter should still be 1. */ if (timer_0_counter != 1) { @@ -205,27 +205,27 @@ TX_TIMER_INTERNAL **current_list_head; timer_2.tx_timer_id = TX_TIMER_ID; timer_2.tx_timer_internal.tx_timer_internal_list_head = (TX_TIMER_INTERNAL **) ¤t_list_head; current_list_head = (struct TX_TIMER_INTERNAL_STRUCT **) &(timer_2.tx_timer_internal); - timer_2.tx_timer_internal.tx_timer_internal_remaining_ticks = TX_TIMER_ENTRIES*2; + timer_2.tx_timer_internal.tx_timer_internal_remaining_ticks = TX_TIMER_ENTRIES*2; timer_2.tx_timer_internal.tx_timer_internal_active_next = &(timer_2.tx_timer_internal); status = tx_timer_deactivate(&timer_2); /* Check for error. */ if ((status != TX_SUCCESS) || (timer_2.tx_timer_internal.tx_timer_internal_remaining_ticks != TX_TIMER_ENTRIES)) { - + /* Application timer error. */ printf("ERROR #8a\n"); test_control_return(1); } - /* Sleep for twice the expiration time to make sure the timer + /* Sleep for twice the expiration time to make sure the timer doesn't automatically reschedule. */ tx_thread_sleep(47); /* Check for an error. */ - /* At this point the timer counter should still be 1. */ + /* At this point the timer counter should still be 1. */ if (timer_0_counter != 1) { diff --git a/test/smp/regression/threadx_timer_deactivate_accuracy_test.c b/test/smp/regression/threadx_timer_deactivate_accuracy_test.c index 6af4bde4..625b82a6 100644 --- a/test/smp/regression/threadx_timer_deactivate_accuracy_test.c +++ b/test/smp/regression/threadx_timer_deactivate_accuracy_test.c @@ -41,8 +41,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 3, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -144,7 +144,7 @@ UINT status; printf("ERROR #7\n"); test_control_return(1); } - + /* Sleep */ tx_thread_sleep(4); diff --git a/test/smp/regression/threadx_timer_information_test.c b/test/smp/regression/threadx_timer_information_test.c index 4dbc3c9b..7954de2c 100644 --- a/test/smp/regression/threadx_timer_information_test.c +++ b/test/smp/regression/threadx_timer_information_test.c @@ -48,8 +48,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 3, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -119,7 +119,7 @@ TX_TIMER_INTERNAL **list_head; /* Application timer error. */ printf("ERROR #4\n"); test_control_return(1); - } + } /* Deactivate the timer. */ status = tx_timer_deactivate(&timer_0); @@ -143,7 +143,7 @@ TX_TIMER_INTERNAL **list_head; /* Application timer error. */ printf("ERROR #6\n"); test_control_return(1); - } + } /* Modify the timer. */ status = tx_timer_change(&timer_0, 100, 1); @@ -194,12 +194,12 @@ TX_TIMER_INTERNAL **list_head; /* Check for successful completion. */ if ((status != TX_SUCCESS) || (active != TX_TRUE) || (remaining_ticks != 1) || (reschedule_ticks != 1) || (next_timer != &timer_1)) { - + /* Application timer error. */ printf("ERROR #10\n"); test_control_return(1); - } - + } + /* Now, deactivate timer 0 to get another path through the info get service. */ status = tx_timer_deactivate(&timer_0); status += tx_timer_info_get(&timer_0, &name, &active, &remaining_ticks, &reschedule_ticks, &next_timer); @@ -207,26 +207,26 @@ TX_TIMER_INTERNAL **list_head; /* Check for successful completion. */ if ((status != TX_SUCCESS) || (active != TX_FALSE) || (remaining_ticks != 1) || (reschedule_ticks != 1) || (next_timer != &timer_1)) { - + /* Application timer error. */ printf("ERROR #11\n"); test_control_return(1); - } + } - /* Change timer 0 to a large value and get the information again. */ + /* Change timer 0 to a large value and get the information again. */ status = tx_timer_change(&timer_0, 100, 200); status += tx_timer_activate(&timer_0); - + status += tx_timer_info_get(&timer_0, &name, &active, &remaining_ticks, &reschedule_ticks, &next_timer); /* Check for successful completion. */ if ((status != TX_SUCCESS) || (active != TX_TRUE) || (remaining_ticks != 100) || (reschedule_ticks != 200) || (next_timer != &timer_1)) { - + /* Application timer error. */ printf("ERROR #12\n"); test_control_return(1); - } + } #ifdef TX_TIMER_ENABLE_PERFORMANCE_INFO @@ -236,7 +236,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if (status != TX_PTR_ERROR) { - + /* Application timer error. */ printf("ERROR #13\n"); test_control_return(1); @@ -245,30 +245,30 @@ TX_TIMER_INTERNAL **list_head; /* Now get the performance information. */ status = tx_timer_performance_info_get(&timer_0, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_timer_performance_info_get(&timer_0, &activates, &reactivates, &deactivates, &expirations, &expiration_adjusts); - + /* Check for successful completion. */ - if ((status != TX_SUCCESS) || (activates != timer_0.tx_timer_performance_activate_count) || (reactivates != timer_0.tx_timer_performance_reactivate_count) || + if ((status != TX_SUCCESS) || (activates != timer_0.tx_timer_performance_activate_count) || (reactivates != timer_0.tx_timer_performance_reactivate_count) || (deactivates != timer_0.tx_timer_performance_deactivate_count) || (expirations != timer_0.tx_timer_performance_expiration_count) || (expiration_adjusts != timer_0.tx_timer_performance__expiration_adjust_count)) { - + /* Application timer error. */ printf("ERROR #14\n"); test_control_return(1); - } + } /* Now get the system performance information. */ status = tx_timer_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_timer_performance_system_info_get(&activates, &reactivates, &deactivates, &expirations, &expiration_adjusts); - + /* Check for successful completion. */ - if ((status != TX_SUCCESS) || (activates != _tx_timer_performance_activate_count) || (reactivates != _tx_timer_performance_reactivate_count) || + if ((status != TX_SUCCESS) || (activates != _tx_timer_performance_activate_count) || (reactivates != _tx_timer_performance_reactivate_count) || (deactivates != _tx_timer_performance_deactivate_count) || (expirations != _tx_timer_performance_expiration_count) || (expiration_adjusts != _tx_timer_performance__expiration_adjust_count)) { - + /* Application timer error. */ printf("ERROR #15\n"); test_control_return(1); - } + } #else @@ -278,7 +278,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Application timer error. */ printf("ERROR #16\n"); test_control_return(1); @@ -290,7 +290,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Application timer error. */ printf("ERROR #17\n"); test_control_return(1); @@ -302,7 +302,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Application timer error. */ printf("ERROR #18\n"); test_control_return(1); @@ -314,7 +314,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Application timer error. */ printf("ERROR #19\n"); test_control_return(1); @@ -326,7 +326,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Application timer error. */ printf("ERROR #20\n"); test_control_return(1); @@ -338,7 +338,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Application timer error. */ printf("ERROR #21\n"); test_control_return(1); @@ -350,7 +350,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Application timer error. */ printf("ERROR #22\n"); test_control_return(1); @@ -362,7 +362,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Application timer error. */ printf("ERROR #23\n"); test_control_return(1); @@ -374,7 +374,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Application timer error. */ printf("ERROR #24\n"); test_control_return(1); @@ -386,7 +386,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Application timer error. */ printf("ERROR #25\n"); test_control_return(1); @@ -398,7 +398,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Application timer error. */ printf("ERROR #26\n"); test_control_return(1); @@ -410,7 +410,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Application timer error. */ printf("ERROR #27\n"); test_control_return(1); @@ -422,7 +422,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Application timer error. */ printf("ERROR #28\n"); test_control_return(1); @@ -432,18 +432,18 @@ TX_TIMER_INTERNAL **list_head; /* Test timer that is in the process of expiration - on temporary "expired" list. */ TX_MEMSET(&timer_2, 0, (sizeof(TX_TIMER))); - + /* Setup fake timer and test for no-reactivate condition. */ timer_2.tx_timer_id = TX_TIMER_ID; timer_2.tx_timer_internal.tx_timer_internal_list_head = (TX_TIMER_INTERNAL **) &list_head; list_head = (struct TX_TIMER_INTERNAL_STRUCT **) &(timer_2.tx_timer_internal); - timer_2.tx_timer_internal.tx_timer_internal_remaining_ticks = 10; + timer_2.tx_timer_internal.tx_timer_internal_remaining_ticks = 10; status = tx_timer_info_get(&timer_2, TX_NULL, TX_NULL, &remaining_ticks, &reschedule_ticks, TX_NULL); /* Check for error. */ if ((status != TX_SUCCESS) || (remaining_ticks != 0) || (reschedule_ticks != 0)) { - + /* Application timer error. */ printf("ERROR #28a\n"); test_control_return(1); @@ -453,13 +453,13 @@ TX_TIMER_INTERNAL **list_head; timer_2.tx_timer_id = TX_TIMER_ID; timer_2.tx_timer_internal.tx_timer_internal_list_head = (TX_TIMER_INTERNAL **) &list_head; list_head = (struct TX_TIMER_INTERNAL_STRUCT **) &(timer_2.tx_timer_internal); - timer_2.tx_timer_internal.tx_timer_internal_remaining_ticks = TX_TIMER_ENTRIES * 2; + timer_2.tx_timer_internal.tx_timer_internal_remaining_ticks = TX_TIMER_ENTRIES * 2; status = tx_timer_info_get(&timer_2, TX_NULL, TX_NULL, &remaining_ticks, &reschedule_ticks, TX_NULL); /* Check for error. */ if ((status != TX_SUCCESS) || (remaining_ticks != TX_TIMER_ENTRIES) || (reschedule_ticks != 0)) { - + /* Application timer error. */ printf("ERROR #28a\n"); test_control_return(1); @@ -473,7 +473,7 @@ TX_TIMER_INTERNAL **list_head; timer_2.tx_timer_id = TX_TIMER_ID; timer_2.tx_timer_internal.tx_timer_internal_list_head = (TX_TIMER_INTERNAL **) &list_head; list_head = (struct TX_TIMER_INTERNAL_STRUCT **) &(timer_2.tx_timer_internal); - timer_2.tx_timer_internal.tx_timer_internal_remaining_ticks = 13; + timer_2.tx_timer_internal.tx_timer_internal_remaining_ticks = 13; _tx_timer_expired_timer_ptr = &timer_2.tx_timer_internal; status = tx_timer_info_get(&timer_2, TX_NULL, TX_NULL, &remaining_ticks, &reschedule_ticks, TX_NULL); _tx_timer_expired_timer_ptr = TX_NULL; @@ -484,7 +484,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if ((status != TX_SUCCESS) || (remaining_ticks != 0) || (reschedule_ticks != 0)) { - + /* Application timer error. */ printf("ERROR #28b\n"); test_control_return(1); diff --git a/test/smp/regression/threadx_timer_large_timer_accuracy_test.c b/test/smp/regression/threadx_timer_large_timer_accuracy_test.c index dde97fe4..726523b9 100644 --- a/test/smp/regression/threadx_timer_large_timer_accuracy_test.c +++ b/test/smp/regression/threadx_timer_large_timer_accuracy_test.c @@ -41,8 +41,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 3, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -144,7 +144,7 @@ UINT status; printf("ERROR #7\n"); test_control_return(1); } - + /* Sleep */ tx_thread_sleep(2); diff --git a/test/smp/regression/threadx_timer_multiple_accuracy_test.c b/test/smp/regression/threadx_timer_multiple_accuracy_test.c index a7be91e2..af9957d8 100644 --- a/test/smp/regression/threadx_timer_multiple_accuracy_test.c +++ b/test/smp/regression/threadx_timer_multiple_accuracy_test.c @@ -43,8 +43,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 3, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; diff --git a/test/smp/regression/threadx_timer_multiple_test.c b/test/smp/regression/threadx_timer_multiple_test.c index 3f02d5a7..688a7d5b 100644 --- a/test/smp/regression/threadx_timer_multiple_test.c +++ b/test/smp/regression/threadx_timer_multiple_test.c @@ -1,4 +1,4 @@ -/* This test is designed to test a simple application timer services, +/* This test is designed to test a simple application timer services, including create, activate, deactivate, change, and delete with multiple timers. */ #include @@ -46,8 +46,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 3, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; diff --git a/test/smp/regression/threadx_timer_simple_test.c b/test/smp/regression/threadx_timer_simple_test.c index ec3ff235..b763ad55 100644 --- a/test/smp/regression/threadx_timer_simple_test.c +++ b/test/smp/regression/threadx_timer_simple_test.c @@ -1,4 +1,4 @@ -/* This test is designed to test a simple application timer services, including create, +/* This test is designed to test a simple application timer services, including create, activate, deactivate, change, and delete. */ #include @@ -52,7 +52,7 @@ static void thread_1_entry(ULONG thread_input); static void timer_0_expiration(ULONG timer_input); static void timer_1_expiration(ULONG timer_input); -UINT _txe_timer_create(TX_TIMER *timer_ptr, CHAR *name_ptr, +UINT _txe_timer_create(TX_TIMER *timer_ptr, CHAR *name_ptr, VOID (*expiration_function)(ULONG), ULONG expiration_input, ULONG initial_ticks, ULONG reschedule_ticks, UINT auto_activate, UINT timer_control_block_size); @@ -75,18 +75,18 @@ UINT status; /* Determine if the timer was able to be created durning initialization. */ if (test_timer_create_init != TX_SUCCESS) { - + /* Error! */ error++; } /* Attempt to delete a timer from a timer. */ status = tx_timer_delete(&timer_0); - + /* Check status. */ if (status != TX_CALLER_ERROR) { - + /* Error! */ error++; } @@ -98,7 +98,7 @@ UINT status; /* Check status. */ if (status != TX_CALLER_ERROR) { - + /* Error! */ error++; } @@ -124,11 +124,11 @@ UINT status; /* Attempt to delete a timer from an ISR. */ status = tx_timer_delete(&timer_0); - + /* Check status. */ if (status != TX_CALLER_ERROR) { - + /* Error! */ error++; } @@ -140,7 +140,7 @@ UINT status; /* Check status. */ if (status != TX_CALLER_ERROR) { - + /* Error! */ error++; } @@ -168,13 +168,13 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 3, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, 3, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -236,7 +236,7 @@ ULONG exclusion_map; timer_memory.second = 0x55667788; timer_memory.next_to_last = 0x99aabbcc; timer_memory.last = 0xddeeff00; - + /* Create the timer. */ status = tx_timer_create(&timer_memory.timer, "timer memory", timer_0_expiration, 0x1234, 1000000, 100000, TX_NO_ACTIVATE); @@ -249,7 +249,7 @@ ULONG exclusion_map; (timer_memory.next_to_last != 0x99aabbcc) || (timer_memory.last != 0xddeeff00)) { - + /* Memory overwrite error. */ printf("ERROR #4\n"); test_control_return(1); @@ -259,11 +259,11 @@ ULONG exclusion_map; /* Attempt to activate a non-timer. */ status = tx_timer_activate(TX_NULL); - + /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #5\n"); test_control_return(1); @@ -272,11 +272,11 @@ ULONG exclusion_map; /* Attempt to activate a non-created timer. */ timer_2.tx_timer_id = 0; status = tx_timer_activate(&timer_2); - + /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #6\n"); test_control_return(1); @@ -287,11 +287,11 @@ ULONG exclusion_map; timer_2.tx_timer_internal.tx_timer_internal_list_head = TX_NULL; timer_2.tx_timer_internal.tx_timer_internal_remaining_ticks = 0; status = tx_timer_activate(&timer_2); - + /* Check status. */ if (status != TX_ACTIVATE_ERROR) { - + /* Application timer error. */ printf("ERROR #7\n"); test_control_return(1); @@ -303,11 +303,11 @@ ULONG exclusion_map; timer_2.tx_timer_internal.tx_timer_internal_list_head = TX_NULL; timer_2.tx_timer_internal.tx_timer_internal_remaining_ticks = TX_WAIT_FOREVER; status = tx_timer_activate(&timer_2); - + /* Check status. */ if (status != TX_SUCCESS) { - + /* Application timer error. */ printf("ERROR #8\n"); test_control_return(1); @@ -317,11 +317,11 @@ ULONG exclusion_map; /* Attempt to deactivate a non-timer. */ status = tx_timer_deactivate(TX_NULL); - + /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #9\n"); test_control_return(1); @@ -330,11 +330,11 @@ ULONG exclusion_map; /* Attempt to deactivate a non-created timer. */ timer_2.tx_timer_id = 0; status = tx_timer_deactivate(&timer_2); - + /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #10\n"); test_control_return(1); @@ -342,11 +342,11 @@ ULONG exclusion_map; /* Attempt to change a non-timer. */ status = tx_timer_change(TX_NULL, 1, 1); - + /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #11\n"); test_control_return(1); @@ -355,11 +355,11 @@ ULONG exclusion_map; /* Attempt to change a non-created timer. */ timer_2.tx_timer_id = 0; status = tx_timer_change(&timer_2, 1, 1); - + /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #12\n"); test_control_return(1); @@ -367,11 +367,11 @@ ULONG exclusion_map; /* Attempt to change a timer with a 0 initial ticks. */ status = tx_timer_change(&timer_0, 0, 1); - + /* Check status. */ if (status != TX_TICK_ERROR) { - + /* Application timer error. */ printf("ERROR #13\n"); test_control_return(1); @@ -379,11 +379,11 @@ ULONG exclusion_map; /* Attempt to delete a non-time. */ status = tx_timer_delete(TX_NULL); - + /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #14\n"); test_control_return(1); @@ -392,11 +392,11 @@ ULONG exclusion_map; /* Attempt to delete a non-created time. */ timer_2.tx_timer_id = 0; status = tx_timer_delete(&timer_2); - + /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #15\n"); test_control_return(1); @@ -404,11 +404,11 @@ ULONG exclusion_map; /* Attempt to get info from a non-timer. */ status = tx_timer_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); - + /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #16\n"); test_control_return(1); @@ -417,11 +417,11 @@ ULONG exclusion_map; /* Attempt to get info from a non-created timer. */ timer_2.tx_timer_id = 0; status = tx_timer_info_get(&timer_2, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); - + /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #17\n"); test_control_return(1); @@ -434,7 +434,7 @@ ULONG exclusion_map; /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #18\n"); test_control_return(1); @@ -447,7 +447,7 @@ ULONG exclusion_map; /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #19\n"); test_control_return(1); @@ -460,7 +460,7 @@ ULONG exclusion_map; /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #20\n"); test_control_return(1); @@ -473,7 +473,7 @@ ULONG exclusion_map; /* Check status. */ if (status != TX_TICK_ERROR) { - + /* Application timer error. */ printf("ERROR #21\n"); test_control_return(1); @@ -486,7 +486,7 @@ ULONG exclusion_map; /* Check status. */ if (status != TX_ACTIVATE_ERROR) { - + /* Application timer error. */ printf("ERROR #22\n"); test_control_return(1); @@ -504,7 +504,7 @@ ULONG exclusion_map; /* Application timer error. */ printf("ERROR #23\n"); test_control_return(1); - } + } /* Deactivate the timer. */ status = tx_timer_deactivate(&timer_0); @@ -528,7 +528,7 @@ ULONG exclusion_map; /* Application timer error. */ printf("ERROR #25\n"); test_control_return(1); - } + } /* Modify the timer. */ status = tx_timer_change(&timer_0, 100, 1); @@ -615,7 +615,7 @@ ULONG exclusion_map; /* Test for error. */ if ((error) || (timer_executed != 1) || (isr_executed != 1)) { - + /* Thread error. */ printf("ERROR #30\n"); test_control_return(1); @@ -628,7 +628,7 @@ ULONG exclusion_map; /* Check status. */ if (status != TX_SUCCESS) { - + /* Application timer error. */ printf("ERROR #31\n"); test_control_return(1); @@ -639,58 +639,58 @@ ULONG exclusion_map; /* Check for ISR errors. */ if (error) { - + /* Thread error. */ printf("ERROR #32\n"); test_control_return(1); } - + /* Test the SMP timer exclusion get routines with bad values. */ status = tx_timer_smp_core_exclude_get(TX_NULL, TX_NULL); - + /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #33\n"); test_control_return(1); } - + status = tx_timer_smp_core_exclude_get(&timer_0, TX_NULL); - + /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #34\n"); test_control_return(1); } - + /* Test the SMP timer exclusion set routines with bad values. */ status = tx_timer_smp_core_exclude(TX_NULL, 0); - + /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #35\n"); test_control_return(1); } - + status = tx_timer_smp_core_exclude(&timer_0, 0); - + /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #36\n"); test_control_return(1); - } - + } + /* Create two timers and exclude them from core 0. */ status = tx_timer_create(&timer_0, "timer 0", timer_0_expiration, 0x1234, 10, 10, TX_NO_ACTIVATE); @@ -698,60 +698,60 @@ ULONG exclusion_map; /* Check status. */ if (status != TX_SUCCESS) { - + /* Application timer error. */ printf("ERROR #37\n"); test_control_return(1); } - + status = tx_timer_create(&timer_1, "timer 1", timer_1_expiration, 0x1234, 10, 10, TX_NO_ACTIVATE); /* Check status. */ if (status != TX_SUCCESS) { - + /* Application timer error. */ printf("ERROR #38\n"); test_control_return(1); } - + /* Now test the exclusion get with a valid timer, but with a NULL destination. */ status = tx_timer_smp_core_exclude_get(&timer_0, TX_NULL); - + /* Check status. */ if (status != TX_PTR_ERROR) { - + /* Application timer error. */ printf("ERROR #39\n"); test_control_return(1); - } - + } + /* Now exclude the processing of each timer from executing on core 0. */ status = tx_timer_smp_core_exclude(&timer_0, 0x1); status += tx_timer_smp_core_exclude(&timer_1, 0x1); - + /* Check status. */ if (status != TX_SUCCESS) { - + /* Application timer error. */ printf("ERROR #40\n"); test_control_return(1); - } + } /* Now test the exclusion get with a valid timer. */ status = tx_timer_smp_core_exclude_get(&timer_0, &exclusion_map); - + /* Check status. */ if ((status != TX_SUCCESS) || (exclusion_map != 0x1)) { - + /* Application timer error. */ printf("ERROR #41\n"); test_control_return(1); - } + } /* Clear the timer counters. */ timer_0_counter = 0; @@ -766,34 +766,34 @@ ULONG exclusion_map; tx_interrupt_save = _tx_thread_smp_protect(); _tx_timer_system_deactivate(&timer_1.tx_timer_internal); _tx_thread_smp_unprotect(tx_interrupt_save); - + /* Check status. */ if (status != TX_SUCCESS) { - + /* Application timer error. */ printf("ERROR #42\n"); test_control_return(1); - } + } /* Now sleep for 20 ticks to ensure the timer works when excluded from core 0. */ tx_thread_sleep(20); /* Deactivate timer 0. */ status = tx_timer_deactivate(&timer_0); - + /* Delete both timers. */ status += tx_timer_delete(&timer_0); status += tx_timer_delete(&timer_1); - + /* Check status. */ if ((status != TX_SUCCESS) || (timer_0_counter == 0) || (timer_1_counter != 0)) { - + /* Application timer error. */ printf("ERROR #43\n"); test_control_return(1); - } + } else { @@ -805,11 +805,11 @@ ULONG exclusion_map; static void thread_1_entry(ULONG thread_input) { - + while(1) { - - tx_thread_relinquish(); + + tx_thread_relinquish(); } } @@ -824,7 +824,7 @@ static void timer_0_expiration(ULONG timer_input) static void timer_1_expiration(ULONG timer_input) { - + /* Process timer expiration. */ timer_1_counter++; } diff --git a/test/smp/regression/threadx_trace_basic_test.c b/test/smp/regression/threadx_trace_basic_test.c index c6bc9be4..2f3227f8 100644 --- a/test/smp/regression/threadx_trace_basic_test.c +++ b/test/smp/regression/threadx_trace_basic_test.c @@ -102,9 +102,9 @@ UINT old_interrupt; /* If win32, we can actually dump the file! */ trace_dump_file = fopen(trace_dump_file_name, "wb+"); - + fwrite(trace_buffer, 1, sizeof(trace_buffer), trace_dump_file); - + fclose(trace_dump_file); /* Restore interrupts. */ @@ -116,7 +116,7 @@ UINT old_interrupt; { trace_dump_file_name[11] = '0'; trace_dump_file_name[10]++; - + if (trace_dump_file_name[10] > '9') { trace_dump_file_name[10] = '0'; @@ -158,8 +158,8 @@ static void test_isr(void) /* Make ISR entry event. */ tx_trace_isr_enter_insert(1); - } - + } + /* Resume thread 2. */ tx_thread_resume(&thread_2); @@ -171,7 +171,7 @@ static void test_isr(void) /* Make ISR entry event. */ tx_trace_isr_exit_insert(0); - + } @@ -201,7 +201,7 @@ CHAR *pointer; /* Setup a pointer. */ pointer = (CHAR *) first_unused_memory; - + /* Adjust it forward just to make sure there is some space for the test below. */ pointer = pointer + 200; @@ -229,7 +229,7 @@ CHAR *pointer; /* Check status. */ if (status != TX_SUCCESS) { - + printf("Running Trace Basic Test............................................ ERROR #1\n"); test_control_return(1); } @@ -238,7 +238,7 @@ CHAR *pointer; /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + printf("Running Trace Basic Test............................................ ERROR #2\n"); test_control_return(1); } @@ -246,9 +246,9 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -260,8 +260,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -273,8 +273,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 14, 14, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -389,7 +389,7 @@ ULONG object; /* Check status. */ if (status != TX_NOT_DONE) { - + printf("ERROR #6\n"); test_control_return(1); } @@ -398,7 +398,7 @@ ULONG object; /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + printf("ERROR #7\n"); test_control_return(1); } @@ -409,7 +409,7 @@ ULONG object; /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + printf("ERROR #8\n"); test_control_return(1); } @@ -420,7 +420,7 @@ ULONG object; /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + printf("ERROR #9\n"); test_control_return(1); } @@ -431,7 +431,7 @@ ULONG object; /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + printf("ERROR #10\n"); test_control_return(1); } @@ -461,7 +461,7 @@ ULONG object; printf("ERROR #12\n"); test_control_return(1); } - + /* Filter all events. */ status = tx_trace_event_filter(0); @@ -473,7 +473,7 @@ ULONG object; printf("ERROR #13\n"); test_control_return(1); } - + #endif /* Unfilter all events. */ @@ -513,7 +513,7 @@ ULONG object; } #endif - + /* Register the trace buffer full notification routine. */ status = tx_trace_buffer_full_notify(trace_buffer_full); @@ -537,7 +537,7 @@ ULONG object; printf("ERROR #18\n"); test_control_return(1); } - + /* Check the NULL path with trace disabled. */ status = tx_trace_buffer_full_notify(TX_NULL); @@ -549,7 +549,7 @@ ULONG object; printf("ERROR #19\n"); test_control_return(1); } - + #endif /* Create a timer for the test. */ @@ -582,7 +582,7 @@ if ((_tx_thread_smp_protection.tx_thread_smp_protect_in_force != 0) || (_tx_win32_critical_section.tx_win32_critical_section_nested_count != 0)) test_isr_dispatch = test_isr; } - + /* Insert user event. */ status = tx_trace_user_event_insert(1027, 1, 2, 3, 4); @@ -674,7 +674,7 @@ if ((_tx_thread_smp_protection.tx_thread_smp_protect_in_force != 0) || break; #endif - } + } /* Clear the ISR. */ test_isr_dispatch = TX_NULL; @@ -706,7 +706,7 @@ if ((_tx_thread_smp_protection.tx_thread_smp_protect_in_force != 0) || /* Attempt to disable again, just to get the TX_NOT_DONE error code. */ status = tx_trace_disable(); - + #ifdef TX_ENABLE_EVENT_TRACE /* Check status. */ @@ -728,7 +728,7 @@ if ((_tx_thread_smp_protection.tx_thread_smp_protect_in_force != 0) || test_control_return(1); } #endif - + /* Attempt to enable event tracing with a bogus size. */ status = tx_trace_enable(trace_buffer, 1, 8); @@ -737,7 +737,7 @@ if ((_tx_thread_smp_protection.tx_thread_smp_protect_in_force != 0) || /* Check status. */ if (status != TX_SIZE_ERROR) { - + /* Trace error. */ printf("ERROR #31\n"); test_control_return(1); @@ -747,7 +747,7 @@ if ((_tx_thread_smp_protection.tx_thread_smp_protect_in_force != 0) || /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Trace error. */ printf("ERROR #32\n"); test_control_return(1); @@ -763,7 +763,7 @@ if ((_tx_thread_smp_protection.tx_thread_smp_protect_in_force != 0) || /* Check status. */ if (status != TX_NOT_DONE) { - + /* Trace error. */ printf("ERROR #33\n"); test_control_return(1); @@ -773,7 +773,7 @@ if ((_tx_thread_smp_protection.tx_thread_smp_protect_in_force != 0) || /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Trace error. */ printf("ERROR #34\n"); test_control_return(1); @@ -791,7 +791,7 @@ if ((_tx_thread_smp_protection.tx_thread_smp_protect_in_force != 0) || } else { - + /* Successful test. */ printf("SUCCESS!\n"); test_control_return(0); @@ -804,9 +804,9 @@ static void thread_1_entry(ULONG task_input) while(1) { - + thread_1_counter++; - tx_thread_suspend(&thread_1); + tx_thread_suspend(&thread_1); } } @@ -817,8 +817,8 @@ static void thread_2_entry(ULONG task_input) while(1) { - + thread_2_counter++; - tx_thread_suspend(&thread_2); + tx_thread_suspend(&thread_2); } } diff --git a/test/tx/regression/testcontrol.c b/test/tx/regression/testcontrol.c index 8203ece5..3d33bc7f 100644 --- a/test/tx/regression/testcontrol.c +++ b/test/tx/regression/testcontrol.c @@ -21,7 +21,7 @@ #error "THREADX_MAJOR_VERSION" #endif /* Check THREADX_MAJOR_VERSION */ -#if defined(EXPECTED_MINOR_VERSION) && ( !defined(THREADX_MINOR_VERSION) || THREADX_MINOR_VERSION != EXPECTED_MINOR_VERSION) +#if defined(EXPECTED_MINOR_VERSION) && ( !defined(THREADX_MINOR_VERSION) || THREADX_MINOR_VERSION != EXPECTED_MINOR_VERSION) #error "THREADX_MINOR_VERSION" #endif /* Check THREADX_MINOR_VERSION */ @@ -64,7 +64,7 @@ TEST_FLAG threadx_delete_timer_thread; #endif TX_TIMER_INTERNAL **_timer_list_start_backup; TEST_FLAG test_stack_analyze_flag; -TEST_FLAG test_initialize_flag; +TEST_FLAG test_initialize_flag; TX_BLOCK_POOL fake_block_pool; TX_BYTE_POOL fake_byte_pool; TX_EVENT_FLAGS_GROUP fake_event_flags; @@ -236,7 +236,7 @@ void test_application_define(void *first_unused_memory); /* Define the array of test entry points. */ -TEST_ENTRY test_control_tests[] = +TEST_ENTRY test_control_tests[] = { #if CTEST test_application_define, @@ -256,7 +256,7 @@ TEST_ENTRY test_control_tests[] = threadx_byte_memory_thread_terminate_application_define, threadx_byte_memory_prioritize_application_define, threadx_byte_memory_thread_contention_application_define, - threadx_byte_memory_information_application_define, + threadx_byte_memory_information_application_define, threadx_event_flag_basic_application_define, threadx_event_flag_suspension_application_define, @@ -339,14 +339,14 @@ TEST_ENTRY test_control_tests[] = threadx_thread_stack_checking_application_define, threadx_time_get_set_application_define, - + threadx_timer_simple_application_define, threadx_timer_activate_deactivate_application_define, threadx_timer_deactivate_accuracy_application_define, threadx_timer_large_timer_accuracy_application_define, threadx_timer_multiple_application_define, threadx_timer_multiple_accuracy_application_define, - threadx_timer_information_application_define, + threadx_timer_information_application_define, threadx_trace_basic_application_define, #endif @@ -411,7 +411,7 @@ void test_interrupt_dispatch(void) if (test_isr_dispatch) { - (test_isr_dispatch)(); + (test_isr_dispatch)(); } } @@ -449,7 +449,7 @@ void main() /* Test the pre-initialize path through _tx_initialize_kernel_enter. */ _tx_thread_system_state = TX_INITIALIZE_ALMOST_DONE; test_initialize_flag = 1; - + /* Call the internal kernel enter function to exercise two paths. */ _tx_initialize_kernel_enter(); _tx_thread_system_state = 0; @@ -490,29 +490,29 @@ TX_THREAD *thread_ptr; test_control_system_errors = 0; /* Setup a pointer to the first unused memory. */ - pointer = (UCHAR *) &test_control_memory[0]; //first_unused_memory; + pointer = (UCHAR *) &test_control_memory[0]; //first_unused_memory; /* Create the test control thread. */ - tx_thread_create(&test_control_thread, "test control thread", test_control_thread_entry, 0, - pointer, TEST_STACK_SIZE, + tx_thread_create(&test_control_thread, "test control thread", test_control_thread_entry, 0, + pointer, TEST_STACK_SIZE, 17, 15, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE; /* Create the test thread. */ - tx_thread_create(&test_thread, "test thread", test_thread_entry, 0, - pointer, TEST_STACK_SIZE, + tx_thread_create(&test_thread, "test thread", test_thread_entry, 0, + pointer, TEST_STACK_SIZE, 15, 15, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE; /* Create the second test thread. */ - tx_thread_create(&test_thread1, "test thread 1", test_thread_entry1, 0, - pointer, TEST_STACK_SIZE, + tx_thread_create(&test_thread1, "test thread 1", test_thread_entry1, 0, + pointer, TEST_STACK_SIZE, 15, 15, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE; /* Suspend the test thread temporarily. */ tx_thread_suspend(&test_thread); - + /* Resume the test thread again to exercise the resume code fully. */ tx_thread_resume(&test_thread); @@ -531,26 +531,26 @@ TX_THREAD *thread_ptr; test_mutex_from_init += tx_mutex_get(&init_mutex_inherit, TX_NO_WAIT); test_mutex_from_init += tx_mutex_put(&init_mutex_inherit); test_mutex_from_init += tx_mutex_put(&init_mutex_inherit); - + #ifndef TX_DISABLE_ERROR_CHECKING /* Test timer create from initialization. */ test_block_pool_create_init = tx_block_pool_create(&init_block_pool, "init block pool", 10, init_block_pool_area, sizeof(init_block_pool_area)); - + /* Test byte pool create from initialization. */ test_byte_pool_create_init = tx_byte_pool_create(&init_byte_pool, "init byte pool", init_byte_pool_area, sizeof(init_byte_pool_area)); test_byte_pool_create_init += tx_byte_allocate(&init_byte_pool, (VOID **) &pointer, 20, TX_NO_WAIT); test_byte_pool_create_init += tx_byte_release(pointer); - + /* Test event flag create from initialization. */ test_event_flags_from_init = tx_event_flags_create(&init_event_flags, "init events"); - + /* Test queue create from initialization. */ test_queue_from_init = tx_queue_create(&init_queue, "init queue", TX_1_ULONG, init_queue_area, sizeof(init_queue_area)); - + /* Test semaphore create from initialization. */ test_semaphore_from_init = tx_semaphore_create(&init_semaphore, "init semaphore", 0); - + /* Test timer creat from initialization. */ test_timer_create_init = tx_timer_create(&init_timer, "init timer", init_timer_entry, 0x5678, 100, 200, TX_AUTO_ACTIVATE); @@ -561,7 +561,7 @@ TX_THREAD *thread_ptr; /* Remember the free memory pointer. */ test_free_memory_ptr = &tests_memory[0]; //pointer; - + /* Clear the ISR dispatch. */ test_isr_dispatch = TX_NULL; @@ -571,12 +571,12 @@ TX_THREAD *thread_ptr; /* Test to make sure _tx_thread_time_slice can handle a none-ready thread. */ init_test_thread.tx_thread_state = TX_IO_DRIVER; init_test_thread.tx_thread_new_time_slice = 0; - init_test_thread.tx_thread_suspend_cleanup = TX_NULL; + init_test_thread.tx_thread_suspend_cleanup = TX_NULL; init_test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; init_test_thread.tx_thread_suspending = TX_TRUE; - _tx_thread_current_ptr = &init_test_thread; + _tx_thread_current_ptr = &init_test_thread; _tx_thread_time_slice(); - + /* Test to make sure _tx_thread_time_slice can handle preemption-threshold set. */ init_test_thread.tx_thread_state = TX_READY; init_test_thread.tx_thread_new_time_slice = 0; @@ -592,7 +592,7 @@ TX_THREAD *thread_ptr; temp_thread = _tx_thread_execute_ptr; _tx_thread_mutex_release = TX_NULL; init_test_thread.tx_thread_state = TX_READY; - init_test_thread.tx_thread_suspend_cleanup = TX_NULL; + init_test_thread.tx_thread_suspend_cleanup = TX_NULL; init_test_thread.tx_thread_new_time_slice = 0; init_test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; init_test_thread.tx_thread_suspending = TX_FALSE; @@ -601,15 +601,15 @@ TX_THREAD *thread_ptr; _tx_thread_current_ptr = &init_test_thread; _tx_thread_execute_ptr = &init_test_thread; _tx_thread_entry_exit_notify(&init_test_thread, test_exit_notify); - _tx_thread_shell_entry(); + _tx_thread_shell_entry(); _tx_thread_current_ptr = TX_NULL; _tx_thread_execute_ptr = temp_thread; _tx_thread_mutex_release = temp_mutex_release; /* Recover Mutex release pointer. */ - + /* Test _tx_thread_system_suspend when not current, preemption is needed but disabled. */ temp_thread = _tx_thread_execute_ptr; init_test_thread.tx_thread_state = TX_READY; - init_test_thread.tx_thread_suspend_cleanup = TX_NULL; + init_test_thread.tx_thread_suspend_cleanup = TX_NULL; init_test_thread.tx_thread_new_time_slice = 0; init_test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; init_test_thread.tx_thread_suspending = TX_FALSE; @@ -619,13 +619,13 @@ TX_THREAD *thread_ptr; #ifndef TX_NOT_INTERRUPTABLE _tx_thread_preempt_disable++; #endif - _tx_thread_system_suspend(&init_test_thread); + _tx_thread_system_suspend(&init_test_thread); _tx_thread_execute_ptr = temp_thread; - + /* Test _tx_thread_system_resume when not current, suspending and in a COMPLETED state. */ temp_thread = _tx_thread_execute_ptr; init_test_thread.tx_thread_state = TX_COMPLETED; - init_test_thread.tx_thread_suspend_cleanup = TX_NULL; + init_test_thread.tx_thread_suspend_cleanup = TX_NULL; init_test_thread.tx_thread_new_time_slice = 0; init_test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; init_test_thread.tx_thread_suspending = TX_TRUE; @@ -633,14 +633,14 @@ TX_THREAD *thread_ptr; init_test_thread.tx_thread_entry = test_thread_entry1; _tx_thread_preempt_disable++; _tx_thread_execute_ptr = &init_test_thread; - _tx_thread_system_resume(&init_test_thread); + _tx_thread_system_resume(&init_test_thread); _tx_thread_execute_ptr = temp_thread; - + /* Test _tx_thread_system_resume when not current, not suspending and already in a TX_READY state. */ temp_thread = _tx_thread_execute_ptr; init_test_thread.tx_thread_state = TX_READY; - init_test_thread.tx_thread_suspend_cleanup = TX_NULL; + init_test_thread.tx_thread_suspend_cleanup = TX_NULL; init_test_thread.tx_thread_new_time_slice = 0; init_test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; init_test_thread.tx_thread_suspending = TX_FALSE; @@ -648,13 +648,13 @@ TX_THREAD *thread_ptr; init_test_thread.tx_thread_entry = test_thread_entry1; _tx_thread_preempt_disable++; _tx_thread_execute_ptr = &init_test_thread; - _tx_thread_system_resume(&init_test_thread); + _tx_thread_system_resume(&init_test_thread); _tx_thread_execute_ptr = temp_thread; /* Test _tx_thread_system_resume when not current, suspending and in a TERMINATED state. */ temp_thread = _tx_thread_execute_ptr; init_test_thread.tx_thread_state = TX_TERMINATED; - init_test_thread.tx_thread_suspend_cleanup = TX_NULL; + init_test_thread.tx_thread_suspend_cleanup = TX_NULL; init_test_thread.tx_thread_new_time_slice = 0; init_test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; init_test_thread.tx_thread_suspending = TX_TRUE; @@ -662,9 +662,9 @@ TX_THREAD *thread_ptr; init_test_thread.tx_thread_entry = test_thread_entry1; _tx_thread_preempt_disable++; _tx_thread_execute_ptr = &init_test_thread; - _tx_thread_system_resume(&init_test_thread); + _tx_thread_system_resume(&init_test_thread); _tx_thread_execute_ptr = temp_thread; - + /* Test tx_thread_resume to test the saved_thread_ptr being NULL. */ temp_thread = _tx_thread_execute_ptr; _tx_thread_execute_ptr = TX_NULL; @@ -674,7 +674,7 @@ TX_THREAD *thread_ptr; /* Test preemption change when the new priority is the same as the threshold. */ init_test_thread.tx_thread_state = TX_SUSPENDED; - init_test_thread.tx_thread_suspend_cleanup = TX_NULL; + init_test_thread.tx_thread_suspend_cleanup = TX_NULL; init_test_thread.tx_thread_new_time_slice = 0; init_test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; init_test_thread.tx_thread_suspending = TX_FALSE; @@ -685,9 +685,9 @@ TX_THREAD *thread_ptr; init_test_thread.tx_thread_preempt_threshold = 10; init_test_thread.tx_thread_entry = test_thread_entry1; _tx_thread_preemption_change(&init_test_thread, 10, &old_preemption); - + #ifndef TX_NOT_INTERRUPTABLE - + /* Test semaphore cleanup with an invalid semaphore ID. */ init_test_thread.tx_thread_suspend_control_block = (VOID *) &cleanup_semaphore; init_test_thread.tx_thread_suspend_cleanup = &(_tx_semaphore_cleanup); @@ -703,7 +703,7 @@ TX_THREAD *thread_ptr; cleanup_semaphore.tx_semaphore_suspended_count = 0; init_test_thread.tx_thread_suspension_sequence = 0; _tx_semaphore_cleanup(&init_test_thread, 1); - + /* Test semaphore cleanup with a NULL semaphore pointer. */ init_test_thread.tx_thread_suspend_control_block = TX_NULL; init_test_thread.tx_thread_suspend_cleanup = &(_tx_semaphore_cleanup); @@ -751,7 +751,7 @@ TX_THREAD *thread_ptr; cleanup_queue.tx_queue_suspended_count = 0; init_test_thread.tx_thread_suspension_sequence = 0; _tx_queue_cleanup(&init_test_thread, 1); - + /* Test queue cleanup with an valid queue ID but a suspension count of 0. */ init_test_thread.tx_thread_suspend_control_block = (VOID *) &cleanup_queue; init_test_thread.tx_thread_suspend_cleanup = &(_tx_queue_cleanup); @@ -791,7 +791,7 @@ TX_THREAD *thread_ptr; cleanup_mutex.tx_mutex_suspended_count = 0; init_test_thread.tx_thread_suspension_sequence = 0; _tx_mutex_cleanup(&init_test_thread, 1); - + /* Test mutex cleanup with an valid mutex ID but a suspension count of 0. */ init_test_thread.tx_thread_suspend_control_block = (VOID *) &cleanup_mutex; init_test_thread.tx_thread_suspend_cleanup = &(_tx_mutex_cleanup); @@ -799,7 +799,7 @@ TX_THREAD *thread_ptr; cleanup_mutex.tx_mutex_suspended_count = 0; init_test_thread.tx_thread_suspension_sequence = 0; _tx_mutex_cleanup(&init_test_thread, 0); - + /* Test event flag cleanup with a NULL cleanup pointer. */ init_test_thread.tx_thread_suspend_control_block = (VOID *) &cleanup_event_flags; init_test_thread.tx_thread_suspend_cleanup = TX_NULL; @@ -823,7 +823,7 @@ TX_THREAD *thread_ptr; cleanup_event_flags.tx_event_flags_group_suspended_count = 0; init_test_thread.tx_thread_suspension_sequence = 0; _tx_event_flags_cleanup(&init_test_thread, 0); - + /* Test event flag cleanup with an invalid suspension sequence. */ init_test_thread.tx_thread_suspend_control_block = (VOID *) &cleanup_event_flags; init_test_thread.tx_thread_suspend_cleanup = &(_tx_event_flags_cleanup); @@ -839,7 +839,7 @@ TX_THREAD *thread_ptr; cleanup_event_flags.tx_event_flags_group_suspended_count = 0; init_test_thread.tx_thread_suspension_sequence = 0; _tx_event_flags_cleanup(&init_test_thread, 0); - + /* Test block pool cleanup with a NULL cleanup pointer. */ init_test_thread.tx_thread_suspend_control_block = (VOID *) &cleanup_block_pool; init_test_thread.tx_thread_suspend_cleanup = TX_NULL; @@ -871,7 +871,7 @@ TX_THREAD *thread_ptr; cleanup_block_pool.tx_block_pool_suspended_count = 0; init_test_thread.tx_thread_suspension_sequence = 0; _tx_block_pool_cleanup(&init_test_thread, 1); - + /* Test block pool cleanup with an valid ID but a suspension count of 0. */ init_test_thread.tx_thread_suspend_control_block = (VOID *) &cleanup_block_pool; init_test_thread.tx_thread_suspend_cleanup = &(_tx_block_pool_cleanup); @@ -911,7 +911,7 @@ TX_THREAD *thread_ptr; cleanup_byte_pool.tx_byte_pool_suspended_count = 0; init_test_thread.tx_thread_suspension_sequence = 0; _tx_byte_pool_cleanup(&init_test_thread, 1); - + /* Test byte pool cleanup with an valid ID but a suspension count of 0. */ init_test_thread.tx_thread_suspend_control_block = (VOID *) &cleanup_byte_pool; init_test_thread.tx_thread_suspend_cleanup = &(_tx_byte_pool_cleanup); @@ -920,7 +920,7 @@ TX_THREAD *thread_ptr; init_test_thread.tx_thread_suspension_sequence = 0; _tx_byte_pool_cleanup(&init_test_thread, 0); #endif - + #ifndef TX_ENABLE_EVENT_TRACE /* Call ISR trace events when trace is not enabled. */ @@ -945,10 +945,10 @@ TX_THREAD *thread_ptr; _tx_timer_delete(&test_timer); /* Test the stack analyze function with a dummy thread. */ - + /* Clear the test stack analyze flag. */ test_stack_analyze_flag = 0; - + /* Make a fake thread with a fake stack. */ test_thread2.tx_thread_id = TX_THREAD_ID; #if defined(TX_ENABLE_RANDOM_NUMBER_STACK_FILLING) && defined(TX_ENABLE_STACK_CHECKING) @@ -965,30 +965,30 @@ TX_THREAD *thread_ptr; /* Set the fake thread stack to the fill pattern. */ test_thread2_stack[i] = TX_STACK_FILL; } - + /* Setup index to last point. */ i = (sizeof(test_thread2_stack)/sizeof(ULONG)) - 1; - + /* Setup the stack start and end pointers. */ test_thread2.tx_thread_stack_start = &(test_thread2_stack[0]); test_thread2.tx_thread_stack_end = &(test_thread2_stack[i]); test_thread2.tx_thread_stack_size = sizeof(test_thread2_stack); test_thread2.tx_thread_stack_highest_ptr = test_thread2.tx_thread_stack_end; test_thread2.tx_thread_stack_ptr = test_thread2.tx_thread_stack_start; - + /* Fill 20 words of stack. */ for (j = 0; j < 20; j++) { /* Fill the stack with 0s. */ test_thread2_stack[i--] = 0; } - + /* Call the analyze stack function. */ _tx_thread_stack_analyze(&test_thread2); - + /* Call it again for no change coverage. */ _tx_thread_stack_analyze(&test_thread2); - + /* Fill 99 words of stack. */ for (j = 0; j < 99; j++) { @@ -998,40 +998,40 @@ TX_THREAD *thread_ptr; /* Call the analyze stack function. */ _tx_thread_stack_analyze(&test_thread2); - + /* Call it again for no change coverage. */ _tx_thread_stack_analyze(&test_thread2); #ifndef TX_MANUAL_TEST - + /* Now set the flag to 1 to cause the thread ID to be cleared. */ test_stack_analyze_flag = 1; - + /* Call stack analyze with an ID that is cleared in the middle. */ _tx_thread_stack_analyze(&test_thread2); - + /* Restore the ID. */ test_thread2.tx_thread_id = TX_THREAD_ID; - + /* Now set the flag to 2 to cause the stack ptr to be equal to the start of the stack. */ test_stack_analyze_flag = 2; - + /* Call stack analyze with an ID that is cleared in the middle. */ _tx_thread_stack_analyze(&test_thread2); test_thread2.tx_thread_stack_highest_ptr = test_thread2.tx_thread_stack_end; /* Now set the flag to 3 to cause the stack pointer to not have the fill pattern. */ test_stack_analyze_flag = 3; - + /* Call stack analyze with an ID that is cleared in the middle. */ _tx_thread_stack_analyze(&test_thread2); #endif - + /* Test error condition on _tx_queue_flush. */ test_queue.tx_queue_enqueued = 1; test_queue.tx_queue_suspended_count = 1; test_queue.tx_queue_suspension_list = TX_NULL; - + /* Call _tx_queue_flush to test the thread NULL check. */ _tx_queue_flush(&test_queue); @@ -1042,8 +1042,8 @@ TX_THREAD *thread_ptr; /* Increment the preempt disable flag. */ _tx_thread_preempt_disable++; - - /* Build a thread control block with fake info. */ + + /* Build a thread control block with fake info. */ test_thread3.tx_thread_suspending = TX_TRUE; test_thread3.tx_thread_state = TX_SUSPENDED; test_thread3.tx_thread_delayed_suspend = TX_FALSE; @@ -1060,25 +1060,25 @@ TX_THREAD *thread_ptr; /* Increment the preempt disable flag. */ _tx_thread_preempt_disable++; - + /* Test block pool suspenson safeguard. */ fake_block_pool.tx_block_pool_available = 0; status = _tx_block_allocate(&fake_block_pool, (VOID **) &pointer, TX_WAIT_FOREVER); if (status != TX_NO_MEMORY) - test_control_system_errors++; + test_control_system_errors++; /* Test byte pool suspension safeguard. */ fake_byte_pool.tx_byte_pool_fragments = 2; fake_byte_pool.tx_byte_pool_available = 0; status = _tx_byte_allocate(&fake_byte_pool, (VOID **) &pointer, 1000, TX_WAIT_FOREVER); if (status != TX_NO_MEMORY) - test_control_system_errors++; + test_control_system_errors++; /* Test event flags suspension safeguard. */ fake_event_flags.tx_event_flags_group_current = 0; status = _tx_event_flags_get(&fake_event_flags, 1, TX_AND, &flags, TX_WAIT_FOREVER); if (status != TX_NO_EVENTS) - test_control_system_errors++; + test_control_system_errors++; /* Test mutex suspension safeguard. */ fake_mutex.tx_mutex_ownership_count = 1; @@ -1086,31 +1086,31 @@ TX_THREAD *thread_ptr; fake_mutex.tx_mutex_owner = &init_test_thread; status = _tx_mutex_get(&fake_mutex, TX_WAIT_FOREVER); if (status != TX_NOT_AVAILABLE) - test_control_system_errors++; + test_control_system_errors++; /* Test queue front send suspension safeguard. */ fake_queue.tx_queue_available_storage = 0; status = _tx_queue_front_send(&fake_queue, (VOID *) pointer, TX_WAIT_FOREVER); if (status != TX_QUEUE_FULL) - test_control_system_errors++; - + test_control_system_errors++; + /* Test queue receive suspension safeguard. */ fake_queue.tx_queue_enqueued = 0; status = _tx_queue_receive(&fake_queue, (VOID **) &pointer, TX_WAIT_FOREVER); if (status != TX_QUEUE_EMPTY) - test_control_system_errors++; + test_control_system_errors++; /* Test queue send suspension safeguard. */ fake_queue.tx_queue_available_storage = 0; status = _tx_queue_send(&fake_queue, (VOID *) pointer, TX_WAIT_FOREVER); if (status != TX_QUEUE_FULL) - test_control_system_errors++; - + test_control_system_errors++; + /* Test semaphore suspension safeguard. */ fake_semaphore.tx_semaphore_count = 0; status = _tx_semaphore_get(&fake_semaphore, TX_WAIT_FOREVER); if (status != TX_NO_INSTANCE) - test_control_system_errors++; + test_control_system_errors++; /* Test thread sleep suspension safeguard. */ _tx_thread_current_ptr = &init_test_thread; @@ -1118,24 +1118,24 @@ TX_THREAD *thread_ptr; _tx_thread_system_state = 0; status = _tx_thread_sleep(10); if (status != TX_CALLER_ERROR) - test_control_system_errors++; + test_control_system_errors++; /* Test thread suspend suspension safeguard. */ init_test_thread.tx_thread_state = TX_READY; status = _tx_thread_suspend(&init_test_thread); if (status != TX_SUSPEND_ERROR) - test_control_system_errors++; + test_control_system_errors++; _tx_thread_system_state = temp; _tx_thread_current_ptr = TX_NULL; - + /* Decrement the preempt disable flag. */ _tx_thread_preempt_disable--; } -/* Define the test control thread. This thread is responsible for dispatching all of the +/* Define the test control thread. This thread is responsible for dispatching all of the tests in the ThreadX test suite. */ void test_control_thread_entry(ULONG thread_input) @@ -1174,7 +1174,7 @@ UINT i; /* Suspend control test to allow test to run. */ tx_thread_suspend(&test_control_thread); - + /* Test finished, cleanup in preparation for the next test. */ test_control_cleanup(); } @@ -1186,7 +1186,7 @@ UINT i; exit(test_control_failed_tests + test_control_system_errors); #else external_exit(test_control_failed_tests + test_control_system_errors); -#endif +#endif } @@ -1210,11 +1210,11 @@ UINT old_posture = TX_INT_ENABLE; test_control_successful_tests++; /* Now check for system errors. */ - + /* Is preempt disable flag set? */ if (_tx_thread_preempt_disable) { - + /* System error - preempt disable should never be set inside of a thread! */ printf(" ***** SYSTEM ERROR ***** _tx_thread_preempt_disable is non-zero!\n"); test_control_system_errors++; @@ -1223,16 +1223,16 @@ UINT old_posture = TX_INT_ENABLE; /* Is system state set? */ if (_tx_thread_system_state) { - + /* System error - system state should never be set inside of a thread! */ printf(" ***** SYSTEM ERROR ***** _tx_thread_system_state is non-zero!\n"); test_control_system_errors++; } - /* Are interrupts disabled? */ + /* Are interrupts disabled? */ if (old_posture == TX_INT_DISABLE) { - + /* System error - interrupts should alwasy be enabled in our test threads! */ printf(" ***** SYSTEM ERROR ***** test returned with interrupts disabled!\n"); test_control_system_errors++; @@ -1383,18 +1383,18 @@ void test_thread_entry(ULONG thread_input) /* Suspend this thread but with preemption disabled, so we will actually return. */ _tx_thread_preempt_disable++; tx_thread_suspend(&test_thread); - + /* Now perform a fake thread resume to cause preemption and exercise the path in _tx_thread_system_resume that returns to the scheduler. */ init_test_thread.tx_thread_state = TX_TERMINATED; - init_test_thread.tx_thread_suspend_cleanup = TX_NULL; + init_test_thread.tx_thread_suspend_cleanup = TX_NULL; init_test_thread.tx_thread_new_time_slice = 0; init_test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; init_test_thread.tx_thread_suspending = TX_TRUE; init_test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; init_test_thread.tx_thread_entry = test_thread_entry1; - _tx_thread_system_resume(&init_test_thread); + _tx_thread_system_resume(&init_test_thread); - /* We should not get back here! */ + /* We should not get back here! */ } @@ -1409,7 +1409,7 @@ void test_exit_notify(TX_THREAD *thread_ptr, UINT type) { /* Clear the suspending flag to short-circuit the suspension. */ - thread_ptr -> tx_thread_suspending = TX_FALSE; + thread_ptr -> tx_thread_suspending = TX_FALSE; } diff --git a/test/tx/regression/threadx_block_memory_basic_test.c b/test/tx/regression/threadx_block_memory_basic_test.c index 5f2afa01..12e301d1 100644 --- a/test/tx/regression/threadx_block_memory_basic_test.c +++ b/test/tx/regression/threadx_block_memory_basic_test.c @@ -1,4 +1,4 @@ -/* This test is designed to test simple memory block pool creation, deletion, and +/* This test is designed to test simple memory block pool creation, deletion, and allocates and releases. */ #include @@ -79,7 +79,7 @@ CHAR *pointer; /* Determine if calling block pool create from initialization was successful. */ if (test_block_pool_create_init != TX_SUCCESS) { - + /* Error! */ error++; } @@ -87,7 +87,7 @@ CHAR *pointer; /* Attempt to create a block pool from a timer. */ pointer = (CHAR *) 0x30000; status = tx_block_pool_create(&pool_3, "pool 3", 100, pointer, 320); - + /* Check status. */ if (status != TX_CALLER_ERROR) { @@ -98,7 +98,7 @@ CHAR *pointer; /* Attempt to delete a block pool. */ status = tx_block_pool_delete(&pool_0); - + /* Check status. */ if (status != TX_CALLER_ERROR) { @@ -106,7 +106,7 @@ CHAR *pointer; /* Error! */ error++; } - + timer_executed = 1; /* Attempt to allocate a block with suspension from a timer. */ @@ -190,8 +190,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -203,8 +203,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -278,7 +278,7 @@ unsigned long fake_block[20]; block_memory.second_middle= 0x61718191; block_memory.next_to_last = 0x99aabbcc; block_memory.last = 0xddeeff00; - + /* Create the block pool. */ status = tx_block_pool_create(&block_memory.pool, "pool memory", 16, &block_memory.pool_area[0], (2048*sizeof(ULONG))/sizeof(ULONG)); tx_block_pool_delete(&block_memory.pool); @@ -304,7 +304,7 @@ unsigned long fake_block[20]; fake_block[0] = 0; fake_block[1] = 0; status = tx_block_release(&fake_block[2]); - + /* Check status. */ if (status != TX_PTR_ERROR) { @@ -318,7 +318,7 @@ unsigned long fake_block[20]; fake_block[0] = 0; fake_block[1] = (unsigned long) &fake_block[0]; status = tx_block_release(&fake_block[2]); - + /* Check status. */ if (status != TX_PTR_ERROR) { @@ -328,7 +328,7 @@ unsigned long fake_block[20]; test_control_return(1); } #endif - + /* Allocate first block from the pool. */ status = tx_block_allocate(&pool_0, (VOID **) &pointer_1, TX_NO_WAIT); @@ -504,10 +504,10 @@ unsigned long fake_block[20]; /* Sleep for a bit... */ tx_thread_sleep(3); - + /* Now resume the background thread. */ tx_thread_resume(&thread_1); - + /* Sleep for a bit... */ tx_thread_sleep(3); @@ -517,7 +517,7 @@ unsigned long fake_block[20]; /* Test for error. */ if ((error) || (timer_executed != 1) || (isr_executed != 1)) { - + /* Block memory error. */ printf("ERROR #20\n"); test_control_return(1); @@ -549,7 +549,7 @@ unsigned long fake_block[20]; } else { - + /* Successful test. */ printf("SUCCESS!\n"); test_control_return(0); @@ -562,7 +562,7 @@ static void thread_1_entry(ULONG thread_input) while(1) { - - tx_thread_relinquish(); + + tx_thread_relinquish(); } } diff --git a/test/tx/regression/threadx_block_memory_error_detection_test.c b/test/tx/regression/threadx_block_memory_error_detection_test.c index de28012f..7b7f2f61 100644 --- a/test/tx/regression/threadx_block_memory_error_detection_test.c +++ b/test/tx/regression/threadx_block_memory_error_detection_test.c @@ -1,5 +1,5 @@ /* This test is designed to test error detection for simple memory block operations. */ - + #include #include "tx_api.h" @@ -43,8 +43,8 @@ INT status; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -160,7 +160,7 @@ INT i; printf("ERROR #8\n"); test_control_return(1); } - + /* Allocate with bad pool pointer. */ pool_2.tx_block_pool_id = 0; status = tx_block_allocate(&pool_2, (VOID **) TX_NULL, TX_NO_WAIT); @@ -379,7 +379,7 @@ INT i; thread_0_counter++; #endif /* TX_DISABLE_ERROR_CHECKING */ - + /* All is good! */ printf("SUCCESS!\n"); test_control_return(0); diff --git a/test/tx/regression/threadx_block_memory_information_test.c b/test/tx/regression/threadx_block_memory_information_test.c index d6416bc2..20e34d88 100644 --- a/test/tx/regression/threadx_block_memory_information_test.c +++ b/test/tx/regression/threadx_block_memory_information_test.c @@ -39,7 +39,7 @@ static TX_THREAD thread_6; static TX_BLOCK_POOL block_pool_0; static TX_BLOCK_POOL block_pool_2; -#ifdef TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO +#ifdef TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO static TX_BLOCK_POOL block_pool_1; #endif @@ -57,8 +57,8 @@ static void thread_5_entry(ULONG thread_input); static void thread_6_entry(ULONG thread_input); /* Direct core function to bypass the error checking shell. */ -UINT _tx_block_pool_info_get(TX_BLOCK_POOL *pool_ptr, CHAR **name, ULONG *available_blocks, - ULONG *total_blocks, TX_THREAD **first_suspended, +UINT _tx_block_pool_info_get(TX_BLOCK_POOL *pool_ptr, CHAR **name, ULONG *available_blocks, + ULONG *total_blocks, TX_THREAD **first_suspended, ULONG *suspended_count, TX_BLOCK_POOL **next_pool); /* Prototype for test control return. */ @@ -78,7 +78,7 @@ static void test_isr(void) tx_thread_wait_abort(&thread_3); /* End the ISR processing. */ - test_status = 2; + test_status = 2; test_isr_dispatch = TX_NULL; } } @@ -103,8 +103,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -116,8 +116,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -129,8 +129,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -142,8 +142,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 3, 3, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -155,8 +155,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 4, 4, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -168,8 +168,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, TEST_STACK_SIZE_PRINTF, 5, 5, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -181,8 +181,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, + pointer, TEST_STACK_SIZE_PRINTF, 6, 6, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -197,7 +197,7 @@ CHAR *pointer; /* Create the block_pool with one block. */ status = tx_block_pool_create(&block_pool_0, "block_pool 0", 30, pointer, 40); pointer = pointer + 40; - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -282,7 +282,7 @@ ULONG timeouts; tx_thread_resume(&thread_4); tx_thread_resume(&thread_5); tx_thread_resume(&thread_6); - + /* Prioritize the block pool suspension list. */ status = tx_block_pool_prioritize(&block_pool_0); @@ -294,10 +294,10 @@ ULONG timeouts; printf("ERROR #12\n"); test_control_return(1); } - + /* Now loop to test the interrupt of the prioritize loop logic. */ test_status = 1; - test_isr_dispatch = test_isr; + test_isr_dispatch = test_isr; do { @@ -314,10 +314,10 @@ ULONG timeouts; } } while (test_status == 1); - + /* Now determine if thread 4 is at the front of the list... It should be! */ if (block_pool_0.tx_block_pool_suspension_list != &thread_4) - { + { /* Block Pool error. */ printf("ERROR #14\n"); @@ -352,13 +352,13 @@ ULONG timeouts; } #endif - + /* Now use the information services in order to test them. */ status = tx_block_pool_info_get(&block_pool_0, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_block_pool_info_get(&block_pool_0, &name, &available, &total_blocks, &first_suspended, &suspended_count, &next_pool); - + /* Check for an error condition. */ - if ((status) || (available != block_pool_0.tx_block_pool_available) || (total_blocks != block_pool_0.tx_block_pool_total) || + if ((status) || (available != block_pool_0.tx_block_pool_available) || (total_blocks != block_pool_0.tx_block_pool_total) || (first_suspended != &thread_4) || (suspended_count != block_pool_0.tx_block_pool_suspended_count) || (next_pool != &block_pool_0)) { @@ -367,11 +367,11 @@ ULONG timeouts; test_control_return(1); } -#ifdef TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO +#ifdef TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO /* Call the core block pool info get function with a NULL pointer. */ status = _tx_block_pool_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); - + /* Check for the proper error code. */ if (status != TX_PTR_ERROR) { @@ -383,7 +383,7 @@ ULONG timeouts; /* Call the core block pool info get function with a non-initialized pool. */ status = _tx_block_pool_performance_info_get(&block_pool_1, TX_NULL, TX_NULL, TX_NULL, TX_NULL); - + /* Check for the proper error code. */ if (status != TX_PTR_ERROR) { @@ -396,11 +396,11 @@ ULONG timeouts; /* Now get the pool performance information. */ status = tx_block_pool_performance_info_get(&block_pool_0, TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_block_pool_performance_info_get(&block_pool_0, &allocates, &releases, &suspensions, &timeouts); - + /* Check for an error condition. */ - if ((status) || (allocates != block_pool_0.tx_block_pool_performance_allocate_count) || - (releases != block_pool_0.tx_block_pool_performance_release_count) || - (suspensions != block_pool_0.tx_block_pool_performance_suspension_count) || + if ((status) || (allocates != block_pool_0.tx_block_pool_performance_allocate_count) || + (releases != block_pool_0.tx_block_pool_performance_release_count) || + (suspensions != block_pool_0.tx_block_pool_performance_suspension_count) || (timeouts != block_pool_0.tx_block_pool_performance_timeout_count)) { @@ -412,9 +412,9 @@ ULONG timeouts; /* Now get the system pool performance information. */ status = tx_block_pool_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_block_pool_performance_system_info_get(&allocates, &releases, &suspensions, &timeouts); - + /* Check for an error condition. */ - if ((status) || (allocates != _tx_block_pool_performance_allocate_count) || (releases != _tx_block_pool_performance_release_count) || + if ((status) || (allocates != _tx_block_pool_performance_allocate_count) || (releases != _tx_block_pool_performance_release_count) || (suspensions != _tx_block_pool_performance_suspension_count) || (timeouts != _tx_block_pool_performance_timeout_count)) { @@ -433,7 +433,7 @@ ULONG timeouts; /* Call the block pool performance info get function. */ status = tx_block_pool_performance_info_get(&block_pool_0, &allocates, &releases, &suspensions, &timeouts); - + /* Check for the proper error code. */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -445,7 +445,7 @@ ULONG timeouts; /* Call the block pool performance info get function. */ status = tx_block_pool_performance_info_get(TX_NULL, &allocates, &releases, &suspensions, &timeouts); - + /* Check for the proper error code. */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -457,7 +457,7 @@ ULONG timeouts; /* Call the block pool performance info get function. */ status = tx_block_pool_performance_info_get(TX_NULL, TX_NULL, &releases, &suspensions, &timeouts); - + /* Check for the proper error code. */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -469,7 +469,7 @@ ULONG timeouts; /* Call the block pool performance info get function. */ status = tx_block_pool_performance_info_get(TX_NULL, TX_NULL, TX_NULL, &suspensions, &timeouts); - + /* Check for the proper error code. */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -481,7 +481,7 @@ ULONG timeouts; /* Call the block pool performance info get function. */ status = tx_block_pool_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, &timeouts); - + /* Check for the proper error code. */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -493,7 +493,7 @@ ULONG timeouts; /* Call the block pool performance info get function. */ status = tx_block_pool_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); - + /* Check for the proper error code. */ if (status != TX_FEATURE_NOT_ENABLED) { diff --git a/test/tx/regression/threadx_block_memory_prioritize_test.c b/test/tx/regression/threadx_block_memory_prioritize_test.c index 274daa01..6238aef8 100644 --- a/test/tx/regression/threadx_block_memory_prioritize_test.c +++ b/test/tx/regression/threadx_block_memory_prioritize_test.c @@ -76,12 +76,12 @@ static void test_isr(void) } else { - + /* Abort the wait of thread 5. */ tx_thread_wait_abort(&thread_5); /* End the ISR processing. */ - test_status = 2; + test_status = 2; test_isr_dispatch = TX_NULL; } } @@ -107,8 +107,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -120,8 +120,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -133,8 +133,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -146,8 +146,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 3, 3, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -159,8 +159,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 4, 4, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -172,8 +172,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, TEST_STACK_SIZE_PRINTF, 5, 5, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -185,8 +185,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, + pointer, TEST_STACK_SIZE_PRINTF, 6, 6, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -201,7 +201,7 @@ CHAR *pointer; /* Create the block_pool with one block. */ status = tx_block_pool_create(&block_pool_0, "block_pool 0", 30, pointer, 40); pointer = pointer + 40; - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -229,7 +229,7 @@ VOID *pointer; /* Attempt to prioritize with a NULL pointer. */ status = tx_block_pool_prioritize(TX_NULL); - + /* Check for an error condition. */ if (status != TX_POOL_ERROR) { @@ -242,7 +242,7 @@ VOID *pointer; /* Attempt to prioritize with a bad pool pointer. */ block_pool_1.tx_block_pool_id = 0; status = tx_block_pool_prioritize(&block_pool_1); - + /* Check for an error condition. */ if (status != TX_POOL_ERROR) { @@ -296,7 +296,7 @@ VOID *pointer; printf("ERROR #13\n"); test_control_return(1); } - + /* Call block pool prioritize again to test the don't-do-anything path in tx_block_pool_prioritize. */ status += tx_block_pool_prioritize(&block_pool_0); @@ -307,7 +307,7 @@ VOID *pointer; tx_thread_resume(&thread_4); tx_thread_resume(&thread_5); tx_thread_resume(&thread_6); - + /* Prioritize the block pool suspension list. */ status = tx_block_pool_prioritize(&block_pool_0); @@ -319,10 +319,10 @@ VOID *pointer; printf("ERROR #14\n"); test_control_return(1); } - + /* Now loop to test the interrupt of the prioritize loop logic. */ test_status = 1; - test_isr_dispatch = test_isr; + test_isr_dispatch = test_isr; do { @@ -339,10 +339,10 @@ VOID *pointer; } } while (test_status == 1); - + /* Now determine if thread 4 is at the front of the list... It should be! */ if (block_pool_0.tx_block_pool_suspension_list != &thread_4) - { + { /* Block Pool error. */ printf("ERROR #16\n"); diff --git a/test/tx/regression/threadx_block_memory_suspension_test.c b/test/tx/regression/threadx_block_memory_suspension_test.c index 6f2d635c..da14f454 100644 --- a/test/tx/regression/threadx_block_memory_suspension_test.c +++ b/test/tx/regression/threadx_block_memory_suspension_test.c @@ -43,8 +43,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -56,8 +56,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -69,8 +69,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -186,7 +186,7 @@ CHAR *pointer_3; } /* At this point the other thread has run and there is one block free. */ - + /* Get the last block again. */ status = tx_block_allocate(&pool_0, (VOID **) &pointer_3, TX_NO_WAIT); @@ -201,13 +201,13 @@ CHAR *pointer_3; /* Set all the memory of the blocks. */ TX_MEMSET(pointer_3, (CHAR) 0xEF, 100); - + /* Resume the second thread. */ tx_thread_resume(&thread_2); - + /* Let both threads suspend on the block pool via relinquish. */ tx_thread_relinquish(); - + /* Now release the block. */ status = tx_block_release(pointer_3); @@ -219,13 +219,13 @@ CHAR *pointer_3; printf("ERROR #10\n"); test_control_return(1); } - + /* Let thread 1 release the block. */ tx_thread_relinquish(); - + /* Let thread 2 get the block and release the block. */ tx_thread_relinquish(); - + /* Check status and run counter. */ if ((thread_1_counter != 3) || (thread_2_counter != 1)) { diff --git a/test/tx/regression/threadx_block_memory_suspension_timeout_test.c b/test/tx/regression/threadx_block_memory_suspension_timeout_test.c index f290f01a..dc460662 100644 --- a/test/tx/regression/threadx_block_memory_suspension_timeout_test.c +++ b/test/tx/regression/threadx_block_memory_suspension_timeout_test.c @@ -44,8 +44,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -57,8 +57,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -70,8 +70,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -116,7 +116,7 @@ CHAR *pointer_3; status = tx_block_allocate(&pool_0, (VOID **) &pointer_1, TX_NO_WAIT); status += tx_block_allocate(&pool_0, (VOID **) &pointer_2, TX_NO_WAIT); status += tx_block_allocate(&pool_0, (VOID **) &pointer_3, TX_NO_WAIT); - + /* Check status. */ if (status != TX_SUCCESS) { @@ -152,7 +152,7 @@ CHAR *pointer_3; } else { - + /* Successful test. */ printf("SUCCESS!\n"); test_control_return(0); diff --git a/test/tx/regression/threadx_block_memory_thread_terminate_test.c b/test/tx/regression/threadx_block_memory_thread_terminate_test.c index c9221af9..6064891d 100644 --- a/test/tx/regression/threadx_block_memory_thread_terminate_test.c +++ b/test/tx/regression/threadx_block_memory_thread_terminate_test.c @@ -42,8 +42,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -55,8 +55,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -101,7 +101,7 @@ CHAR *pointer_3; status = tx_block_allocate(&pool_0, (VOID **) &pointer_1, TX_NO_WAIT); status += tx_block_allocate(&pool_0, (VOID **) &pointer_2, TX_NO_WAIT); status += tx_block_allocate(&pool_0, (VOID **) &pointer_3, TX_NO_WAIT); - + /* Increment the run counter. */ thread_0_counter++; @@ -118,7 +118,7 @@ CHAR *pointer_3; TX_MEMSET(pointer_1, (CHAR) 0xEF, 100); TX_MEMSET(pointer_2, (CHAR) 0xEF, 100); TX_MEMSET(pointer_3, (CHAR) 0xEF, 100); - + /* Let other thread suspend on block pool. */ tx_thread_relinquish(); diff --git a/test/tx/regression/threadx_byte_memory_basic_test.c b/test/tx/regression/threadx_byte_memory_basic_test.c index 9fffc840..36f41331 100644 --- a/test/tx/regression/threadx_byte_memory_basic_test.c +++ b/test/tx/regression/threadx_byte_memory_basic_test.c @@ -1,4 +1,4 @@ -/* This test is designed to test simple memory byte pool creation, deletion, and +/* This test is designed to test simple memory byte pool creation, deletion, and allocates and releases. */ #include @@ -84,7 +84,7 @@ CHAR *pointer; /* Determine if calling byte pool create from initialization was successful. */ if (test_byte_pool_create_init != TX_SUCCESS) { - + /* Error! */ error++; } @@ -92,7 +92,7 @@ CHAR *pointer; /* Attempt to create a byte pool from a timer. */ pointer = (CHAR *) 0x30000; status = tx_byte_pool_create(&pool_2, "pool 2", pointer, 108); - + /* Check status. */ if (status != TX_CALLER_ERROR) { @@ -138,14 +138,14 @@ CHAR *pointer; /* Attempt to release byte memory from timer. */ pointer = (CHAR *) 0x30000; status = tx_byte_release(pointer); - + /* Check for error status! */ if (status != TX_CALLER_ERROR) { - + /* Error! */ error++; - } + } timer_executed = 1; #endif @@ -209,14 +209,14 @@ UINT status; /* Attempt to release byte memory from ISR. */ pointer = (CHAR *) 0x30000; status = tx_byte_release(pointer); - + /* Check for error status! */ if (status != TX_CALLER_ERROR) { - + /* Error! */ error++; - } + } isr_executed = 1; #endif @@ -235,15 +235,15 @@ void threadx_byte_memory_basic_application_define(void *first_unused_memory) UINT status; CHAR *pointer; - + /* Put first available memory address into a character pointer. */ pointer = (CHAR *) first_unused_memory; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -290,44 +290,44 @@ CHAR *pointer; printf("Running Byte Memory Basic Test...................................... ERROR #3a\n"); test_control_return(1); } - + /* Allocate first block. */ status += tx_byte_allocate(&pool_4, (VOID **) &block_0, 80, TX_NO_WAIT); - + /* Save next search pointer. */ search_ptr_1 = pool_4.tx_byte_pool_search; - + /* Clear the allocatged memory. */ TX_MEMSET(block_0, 0, 80); - + /* Allocate another block. */ status += tx_byte_allocate(&pool_4, (VOID **) &block_1, 80, TX_NO_WAIT); - + /* Clear the allocated block. */ TX_MEMSET(block_1, 0, 80); - + /* Allocate the third and final block. */ status += tx_byte_allocate(&pool_4, (VOID **) &block_2, 80, TX_NO_WAIT); - + /* Clear the allocated block. */ TX_MEMSET(block_2, 0, 80); /* Release the first block. */ status += tx_byte_release(block_0); - + /* Release the second block. */ status += tx_byte_release(block_1); - + /* Manually move the search pointer to create the case where the search wraps and a merge happens on the search pointer necessitating its update. */ pool_4.tx_byte_pool_search = search_ptr_1; /* Point to the middle block. */ /* Allocate a larger block that will wrap the search and require moving as well as an update of the search pointer. */ status += tx_byte_allocate(&pool_4, (VOID **) &block_3, 120, TX_NO_WAIT); - - /* Clear the newly allocated block. */ + + /* Clear the newly allocated block. */ TX_MEMSET(block_3, 0, 120); - + /* At this point, verify the search pointer was properly updated in the previous allocation. */ status += tx_byte_allocate(&pool_4, (VOID **) &block_4, 40, TX_NO_WAIT); /* Should fail since search pointer is now invalid! */ @@ -367,7 +367,7 @@ UCHAR *save_search; byte_memory.second_middle= 0x61718191; byte_memory.next_to_last = 0x99aabbcc; byte_memory.last = 0xddeeff00; - + /* Create the byte pool. */ status = tx_byte_pool_create(&byte_memory.pool, "pool memory", &byte_memory.pool_area[0], (2048*sizeof(ULONG))/sizeof(ULONG)); tx_byte_pool_delete(&byte_memory.pool); @@ -477,7 +477,7 @@ UCHAR *save_search; printf("ERROR #11\n"); test_control_return(1); } - + /* Test non-created pool pointer. */ pool_2.tx_byte_pool_id = 0; status = tx_byte_allocate(&pool_2, (VOID **) &pointer_1, 24, TX_NO_WAIT); @@ -530,15 +530,15 @@ UCHAR *save_search; /* Test NULL pointer release. */ status = tx_byte_release(TX_NULL); - + /* Check for error status! */ if (status != TX_PTR_ERROR) { - + /* Byte memory error. */ printf("ERROR #16\n"); test_control_return(1); - } + } /* Allocate memory from the pool. */ status = tx_byte_allocate(&pool_0, (VOID **) &pointer_1, 24, TX_NO_WAIT); @@ -599,30 +599,30 @@ UCHAR *save_search; /* Test the byte release with a bad block pointer. */ status = _tx_byte_release(TX_NULL); - + /* Check for error status! */ if (status != TX_PTR_ERROR) { - + /* Byte memory error. */ printf("ERROR #21\n"); test_control_return(1); - } + } /* Test another bad block release... no pool pointer! */ array[0] = 0; array[1] = 0; array[2] = 0; status = _tx_byte_release(&array[2]); - + /* Check for error status! */ if (status != TX_PTR_ERROR) { - + /* Byte memory error. */ printf("ERROR #22\n"); test_control_return(1); - } + } /* Test another bad block release.... pool pointer is not a valid pool! */ array[0] = 0; @@ -630,16 +630,16 @@ UCHAR *save_search; array[2] = 0; array[3] = 0; status = _tx_byte_release(&array[2]); - + /* Check for error status! */ if (status != TX_PTR_ERROR) { - + /* Byte memory error. */ printf("ERROR #22\n"); test_control_return(1); - } - + } + /* Now release each of the blocks. */ status = tx_byte_release(pointer_1); @@ -776,7 +776,7 @@ UCHAR *save_search; test_control_return(1); } - /* Now allocate a block that should cause all of the blocks to merge + /* Now allocate a block that should cause all of the blocks to merge together. */ status = tx_byte_allocate(&pool_0, (VOID **) &pointer_3, 88, TX_NO_WAIT); @@ -813,9 +813,9 @@ UCHAR *save_search; printf("ERROR #36\n"); test_control_return(1); } - + /* Now ensure the search pointer update in the byte search algorithm is updated. */ - + /* Allocate memory from the pool. */ status = tx_byte_allocate(&pool_0, (VOID **) &pointer_1, 24, TX_NO_WAIT); @@ -851,10 +851,10 @@ UCHAR *save_search; printf("ERROR #39\n"); test_control_return(1); } - + /* Release the middle block. */ - status = tx_byte_release(pointer_2); - + status = tx_byte_release(pointer_2); + /* Check status. */ if (status != TX_SUCCESS) { @@ -883,7 +883,7 @@ UCHAR *save_search; status = tx_byte_release(pointer_3); status += tx_byte_release(pointer_2); status += tx_byte_release(pointer_1); - + /* Move the search pointer to the third block to exercise that code in the byte search algorithm. */ pool_0.tx_byte_pool_search = (UCHAR *) pointer_3-8; @@ -898,8 +898,8 @@ UCHAR *save_search; printf("ERROR #42\n"); test_control_return(1); } - - + + #ifndef TX_DISABLE_ERROR_CHECKING /* Create a timer for the test. */ @@ -917,14 +917,14 @@ UCHAR *save_search; /* Test for error. */ if ((error) || (timer_executed != 1) || (isr_executed != 1)) { - + /* Byte memory error. */ printf("ERROR #43\n"); test_control_return(1); } #endif - + /* Delete both byte pools. */ status = tx_byte_pool_delete(&pool_0); @@ -950,7 +950,7 @@ UCHAR *save_search; /* Delete pool 4. */ status = tx_byte_pool_delete(&pool_4); - + /* Check status. */ if (status != TX_SUCCESS) { @@ -959,10 +959,10 @@ UCHAR *save_search; printf("ERROR #46\n"); test_control_return(1); } - + /* Create pool 4. */ status = tx_byte_pool_create(&pool_4, "pool 4", pool_4_memory, 300); - + /* Check status. */ if (status != TX_SUCCESS) { @@ -985,15 +985,15 @@ UCHAR *save_search; printf("ERROR #48\n"); test_control_return(1); } - + /* At this point, there should be three allocated blocks and the reserved block at the end. */ - + /* Now release all the blocks in reverse order. This should leave the search pointer at the last block. */ status = tx_byte_release(pointer_3); save_search = pool_4.tx_byte_pool_search; status += tx_byte_release(pointer_2); status += tx_byte_release(pointer_1); - + /* Move the search pointer back to the last block. */ pool_4.tx_byte_pool_search = save_search; @@ -1004,12 +1004,12 @@ UCHAR *save_search; /* Byte memory error. */ printf("ERROR #49\n"); test_control_return(1); - } + } - /* Now attempt to allocate a block that requires a merge, which should exercise the branch in byte search that does not + /* Now attempt to allocate a block that requires a merge, which should exercise the branch in byte search that does not result in a search pointer change. */ status = tx_byte_allocate(&pool_4, (VOID **) &pointer_1, 168, TX_NO_WAIT); - + /* Check status. */ if (status != TX_SUCCESS) { @@ -1017,21 +1017,21 @@ UCHAR *save_search; /* Byte memory error. */ printf("ERROR #50\n"); test_control_return(1); - } - + } + /* Release the last block. */ status = tx_byte_release(pointer_1); - + /* Allocate all the blocks. */ status = tx_byte_allocate(&pool_4, (VOID **) &pointer_1, 84, TX_NO_WAIT); status += tx_byte_allocate(&pool_4, (VOID **) &pointer_2, 84, TX_NO_WAIT); status += tx_byte_allocate(&pool_4, (VOID **) &pointer_3, 84, TX_NO_WAIT); - + /* Release all of the blocks in order. */ status += tx_byte_release(pointer_1); status += tx_byte_release(pointer_2); status += tx_byte_release(pointer_3); - + /* Check status. */ if (status != TX_SUCCESS) { @@ -1039,7 +1039,7 @@ UCHAR *save_search; /* Byte memory error. */ printf("ERROR #50\n"); test_control_return(1); - } + } /* Now setup a special test to exercise the examine blocks equal to 0 path in the byte pool search. */ pool_4.tx_byte_pool_search = save_search; @@ -1047,7 +1047,7 @@ UCHAR *save_search; /* Call byte allocate to execise the examine blocks equal to 0 path on non-merge block condition. */ status = tx_byte_allocate(&pool_4, (VOID **) &pointer_1, 168, TX_NO_WAIT); - + /* Check status. */ if (status != TX_NO_MEMORY) { @@ -1055,8 +1055,8 @@ UCHAR *save_search; /* Byte memory error. */ printf("ERROR #51\n"); test_control_return(1); - } - + } + /* Successful test. */ printf("SUCCESS!\n"); test_control_return(0); diff --git a/test/tx/regression/threadx_byte_memory_information_test.c b/test/tx/regression/threadx_byte_memory_information_test.c index 2d1c20bc..8a619269 100644 --- a/test/tx/regression/threadx_byte_memory_information_test.c +++ b/test/tx/regression/threadx_byte_memory_information_test.c @@ -76,7 +76,7 @@ static void test_isr(void) tx_thread_wait_abort(&thread_3); /* End the ISR processing. */ - test_status = 2; + test_status = 2; test_isr_dispatch = TX_NULL; } } @@ -101,8 +101,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -114,8 +114,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -127,8 +127,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -140,8 +140,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 3, 3, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -153,8 +153,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 4, 4, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -166,8 +166,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, TEST_STACK_SIZE_PRINTF, 5, 5, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -179,8 +179,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, + pointer, TEST_STACK_SIZE_PRINTF, 6, 6, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -195,7 +195,7 @@ CHAR *pointer; /* Create the byte_pool with one byte. */ status = tx_byte_pool_create(&byte_pool_0, "byte_pool 0", pointer, 100); pointer = pointer + 100; - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -274,7 +274,7 @@ ULONG timeouts; printf("ERROR #11\n"); test_control_return(1); } - + /* At this point we are going to get more than 2 threads suspended. */ tx_thread_resume(&thread_1); tx_thread_resume(&thread_2); @@ -285,7 +285,7 @@ ULONG timeouts; /* Prioritize the byte pool suspension list. */ status = tx_byte_pool_prioritize(&byte_pool_0); - + /* Check status and make sure thread 3 is now at the front of the suspension list. */ if ((status != TX_SUCCESS) || (byte_pool_0.tx_byte_pool_suspension_list != &thread_3)) { @@ -297,7 +297,7 @@ ULONG timeouts; /* Now loop to test the interrupt of the prioritize loop logic. */ test_status = 1; - test_isr_dispatch = test_isr; + test_isr_dispatch = test_isr; do { @@ -357,7 +357,7 @@ ULONG timeouts; status += tx_byte_pool_info_get(&byte_pool_0, &name, &available, &fragments, &first_suspended, &suspended_count, &next_pool); /* Check the status. */ - if ((status != TX_SUCCESS) || (available != byte_pool_0.tx_byte_pool_available) || (fragments != byte_pool_0.tx_byte_pool_fragments) || + if ((status != TX_SUCCESS) || (available != byte_pool_0.tx_byte_pool_available) || (fragments != byte_pool_0.tx_byte_pool_fragments) || (first_suspended != &thread_4) || (suspended_count != byte_pool_0.tx_byte_pool_suspended_count) || (next_pool != &byte_pool_0)) { @@ -371,7 +371,7 @@ ULONG timeouts; /* Get the byte pool performance information. */ status = tx_byte_pool_performance_info_get(TX_NULL, &allocates, &releases, &fragments_searched, &merges, &splits, &suspensions, &timeouts); - + /* Check the status. */ if (status != TX_PTR_ERROR) { @@ -380,10 +380,10 @@ ULONG timeouts; printf("ERROR #18\n"); test_control_return(1); } - + /* Get the byte pool performance information. */ status = tx_byte_pool_performance_info_get(&byte_pool_1, &allocates, &releases, &fragments_searched, &merges, &splits, &suspensions, &timeouts); - + /* Check the status. */ if (status != TX_PTR_ERROR) { @@ -395,11 +395,11 @@ ULONG timeouts; /* Get the byte pool performance information. */ status = tx_byte_pool_performance_info_get(&byte_pool_0, &allocates, &releases, &fragments_searched, &merges, &splits, &suspensions, &timeouts); - + /* Check the status. */ - if ((status != TX_SUCCESS) || (allocates != byte_pool_0.tx_byte_pool_performance_allocate_count) || (releases != byte_pool_0.tx_byte_pool_performance_release_count) || - (fragments_searched != byte_pool_0.tx_byte_pool_performance_search_count) || (merges != byte_pool_0.tx_byte_pool_performance_merge_count) || - (splits != byte_pool_0.tx_byte_pool_performance_split_count) || (suspensions != byte_pool_0.tx_byte_pool_performance_suspension_count) || + if ((status != TX_SUCCESS) || (allocates != byte_pool_0.tx_byte_pool_performance_allocate_count) || (releases != byte_pool_0.tx_byte_pool_performance_release_count) || + (fragments_searched != byte_pool_0.tx_byte_pool_performance_search_count) || (merges != byte_pool_0.tx_byte_pool_performance_merge_count) || + (splits != byte_pool_0.tx_byte_pool_performance_split_count) || (suspensions != byte_pool_0.tx_byte_pool_performance_suspension_count) || (timeouts != byte_pool_0.tx_byte_pool_performance_timeout_count)) { @@ -410,11 +410,11 @@ ULONG timeouts; /* Get the byte pool system performance information. */ status = tx_byte_pool_performance_system_info_get(&allocates, &releases, &fragments_searched, &merges, &splits, &suspensions, &timeouts); - + /* Check the status. */ - if ((status != TX_SUCCESS) || (allocates != _tx_byte_pool_performance_allocate_count) || (releases != _tx_byte_pool_performance_release_count) || - (fragments_searched != _tx_byte_pool_performance_search_count) || (merges != _tx_byte_pool_performance_merge_count) || - (splits != _tx_byte_pool_performance_split_count) || (suspensions != _tx_byte_pool_performance_suspension_count) || + if ((status != TX_SUCCESS) || (allocates != _tx_byte_pool_performance_allocate_count) || (releases != _tx_byte_pool_performance_release_count) || + (fragments_searched != _tx_byte_pool_performance_search_count) || (merges != _tx_byte_pool_performance_merge_count) || + (splits != _tx_byte_pool_performance_split_count) || (suspensions != _tx_byte_pool_performance_suspension_count) || (timeouts != _tx_byte_pool_performance_timeout_count)) { diff --git a/test/tx/regression/threadx_byte_memory_prioritize_test.c b/test/tx/regression/threadx_byte_memory_prioritize_test.c index f06d5cd3..29407135 100644 --- a/test/tx/regression/threadx_byte_memory_prioritize_test.c +++ b/test/tx/regression/threadx_byte_memory_prioritize_test.c @@ -74,12 +74,12 @@ static void test_isr(void) } else { - + /* Abort the wait of thread 5. */ tx_thread_wait_abort(&thread_5); /* End the ISR processing. */ - test_status = 2; + test_status = 2; test_isr_dispatch = TX_NULL; } } @@ -105,8 +105,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -118,8 +118,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -131,8 +131,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -144,8 +144,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 3, 3, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -157,8 +157,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 4, 4, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -170,8 +170,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, TEST_STACK_SIZE_PRINTF, 5, 5, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -183,8 +183,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, + pointer, TEST_STACK_SIZE_PRINTF, 6, 6, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -199,7 +199,7 @@ CHAR *pointer; /* Create the byte_pool with one byte. */ status = tx_byte_pool_create(&byte_pool_0, "byte_pool 0", pointer, 100); pointer = pointer + 100; - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -296,7 +296,7 @@ VOID *pointer; /* Call byte pool prioritize again to test the don't-do-anything path in tx_byte_pool_prioritize. */ status += tx_byte_pool_prioritize(&byte_pool_0); - + /* At this point we are going to get more than 2 threads suspended. */ tx_thread_resume(&thread_1); tx_thread_resume(&thread_2); @@ -307,7 +307,7 @@ VOID *pointer; /* Prioritize the byte pool suspension list. */ status = tx_byte_pool_prioritize(&byte_pool_0); - + /* Check status and make sure thread 3 is now at the front of the suspension list. */ if ((status != TX_SUCCESS) || (byte_pool_0.tx_byte_pool_suspension_list != &thread_3)) { @@ -319,7 +319,7 @@ VOID *pointer; /* Now loop to test the interrupt of the prioritize loop logic. */ test_status = 1; - test_isr_dispatch = test_isr; + test_isr_dispatch = test_isr; do { diff --git a/test/tx/regression/threadx_byte_memory_suspension_test.c b/test/tx/regression/threadx_byte_memory_suspension_test.c index 069410c5..ba159894 100644 --- a/test/tx/regression/threadx_byte_memory_suspension_test.c +++ b/test/tx/regression/threadx_byte_memory_suspension_test.c @@ -43,12 +43,12 @@ UCHAR *search_ptr; /* Adjust the search pointer to avoid the search pointer change for this test. */ search_ptr = pool_0.tx_byte_pool_search; while (search_ptr >= pool_0.tx_byte_pool_search) - + { search_ptr = *((UCHAR **) ((VOID *) search_ptr)); } pool_0.tx_byte_pool_search = search_ptr; - + tx_thread_wait_abort(&thread_3); tx_thread_resume(&thread_3); } @@ -77,8 +77,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -90,8 +90,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -103,12 +103,12 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -146,7 +146,7 @@ CHAR *pointer; /* Inform user. */ printf("Running Byte Memory Suspension Test................................. "); - + /* Increment the thread counter. */ thread_0_counter++; @@ -188,7 +188,7 @@ CHAR *pointer; printf("ERROR #7\n"); test_control_return(1); } - + /* Now allocate the memory again. Only one block of this size will fit. */ status = tx_byte_allocate(&pool_0, (VOID **) &pointer, 60, TX_NO_WAIT); @@ -200,15 +200,15 @@ CHAR *pointer; printf("ERROR #8\n"); test_control_return(1); } - + /* Resume the second thread. */ tx_thread_resume(&thread_2); - + /* Now relinquish to let both thread 1 and 2 suspend. */ tx_thread_relinquish(); - + /* At this point both threads should be suspended on the byte pool. */ - + /* Release the memory again. */ status = tx_byte_release(pointer); @@ -220,11 +220,11 @@ CHAR *pointer; printf("ERROR #9\n"); test_control_return(1); } - + /* Now relinquish to get the other threads to run once. */ tx_thread_relinquish(); tx_thread_relinquish(); - + /* At this point both threads 1 and 2 are suspended on the byte pool again. */ if ((thread_1_counter != 3) && (thread_2_counter != 1)) { @@ -233,7 +233,7 @@ CHAR *pointer; printf("ERROR #10\n"); test_control_return(1); } - + /* Now allocate the memory again. Only one block of this size will fit. */ status = tx_byte_allocate(&pool_0, (VOID **) &pointer, 60, TX_NO_WAIT); @@ -245,25 +245,25 @@ CHAR *pointer; printf("ERROR #10a\n"); test_control_return(1); } - + /* Resume thread 3 to get it suspended on the the pool. */ tx_thread_resume(&thread_3); #ifdef TX_MANUAL_TEST /* Set BP hear. Now release the memory and step into the code. After byte search issue IRQ2 mannually, which will - make thread 3 abort the first request and make another request of a different size. This is the path we are trying + make thread 3 abort the first request and make another request of a different size. This is the path we are trying to generate in the test. */ status = tx_byte_release(pointer); #else - /* Set the flag that will make thread 3 abort the first request and make another request of a different size. This tests the memory size change path + /* Set the flag that will make thread 3 abort the first request and make another request of a different size. This tests the memory size change path in the byte release loop logic. */ threadx_byte_release_loop_test = 1; status = tx_byte_release(pointer); #endif - + /* Check status. */ if (status != TX_SUCCESS) { @@ -273,7 +273,7 @@ CHAR *pointer; test_control_return(1); } else - { + { /* Successful test. */ printf("SUCCESS!\n"); @@ -307,7 +307,7 @@ CHAR *pointer; /* Check for status. */ if (status != TX_SUCCESS) return; - + /* Let thread 0 run again. */ tx_thread_relinquish(); } @@ -339,7 +339,7 @@ CHAR *pointer; /* Check for status. */ if (status != TX_SUCCESS) return; - + /* Let thread 0 run again. */ tx_thread_relinquish(); } @@ -370,7 +370,7 @@ CHAR *pointer; threadx_byte_allocate_loop_test = 1; status = tx_byte_allocate(&pool_0, (VOID **) &pointer, 90, TX_WAIT_FOREVER); #endif - + /* Check for status. */ if (status != TX_SUCCESS) return; @@ -384,7 +384,7 @@ CHAR *pointer; /* Check for status. */ if (status != TX_SUCCESS) return; - + /* suspend this thread. */ tx_thread_suspend(&thread_3); } diff --git a/test/tx/regression/threadx_byte_memory_suspension_timeout_test.c b/test/tx/regression/threadx_byte_memory_suspension_timeout_test.c index ed122dab..5e94df97 100644 --- a/test/tx/regression/threadx_byte_memory_suspension_timeout_test.c +++ b/test/tx/regression/threadx_byte_memory_suspension_timeout_test.c @@ -44,8 +44,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -57,8 +57,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -71,8 +71,8 @@ CHAR *pointer; } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -110,7 +110,7 @@ CHAR *pointer; /* Inform user. */ printf("Running Byte Memory Suspension Timeout Test......................... "); - + /* Increment the thread counter. */ thread_0_counter++; @@ -126,7 +126,7 @@ CHAR *pointer; test_control_return(1); } - /* Sleep to allow the other thread to suspend and timeout on the memory + /* Sleep to allow the other thread to suspend and timeout on the memory pool once. */ tx_thread_sleep(64); @@ -140,7 +140,7 @@ CHAR *pointer; } else { - + /* Successful test. */ printf("SUCCESS!\n"); test_control_return(0); diff --git a/test/tx/regression/threadx_byte_memory_thread_contention_test.c b/test/tx/regression/threadx_byte_memory_thread_contention_test.c index a3e689c8..da2634e3 100644 --- a/test/tx/regression/threadx_byte_memory_thread_contention_test.c +++ b/test/tx/regression/threadx_byte_memory_thread_contention_test.c @@ -1,6 +1,6 @@ /* This test is designed to test contention of two threads on a single memory byte pool. */ - + #include #include "tx_api.h" @@ -49,8 +49,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 1, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -62,8 +62,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 1, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -75,8 +75,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 1, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -91,7 +91,7 @@ CHAR *pointer; /* Create byte pool 0. */ status = tx_byte_pool_create(&pool_0, "pool 0", pointer, 108); pointer = pointer + 108; - + /* Save off the intial pool size. */ initial_pool_size = pool_0.tx_byte_pool_available; @@ -128,7 +128,7 @@ CHAR *pointer; { /* Allocate memory from the pool. This size will cause merge activity - because the search pointer will sit in this large block about half + because the search pointer will sit in this large block about half the time. */ status = tx_byte_allocate(&pool_0, (VOID **) &pointer, 60, TX_WAIT_FOREVER); @@ -158,7 +158,7 @@ CHAR *pointer; /* Check the time. */ if (tx_time_get() > 128) - break; + break; /* Increment the thread counter. */ thread_0_counter++; @@ -166,7 +166,7 @@ CHAR *pointer; /* Set the done flag. */ test_done = TX_TRUE; - + /* Sleep to let the other threads finish up! */ tx_thread_sleep(2); @@ -215,7 +215,7 @@ CHAR *pointer; /* Check for status. */ if (status != TX_SUCCESS) return; - + /* Increment the thread counter. */ thread_1_counter++; } @@ -248,7 +248,7 @@ CHAR *pointer; /* Check for status. */ if (status != TX_SUCCESS) return; - + /* Increment the thread counter. */ thread_2_counter++; } diff --git a/test/tx/regression/threadx_byte_memory_thread_terminate_test.c b/test/tx/regression/threadx_byte_memory_thread_terminate_test.c index 29fec0c0..4805ba57 100644 --- a/test/tx/regression/threadx_byte_memory_thread_terminate_test.c +++ b/test/tx/regression/threadx_byte_memory_thread_terminate_test.c @@ -41,8 +41,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -54,8 +54,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -96,7 +96,7 @@ CHAR *pointer; /* Increment the thread counter. */ thread_0_counter++; - + /* Allocate memory from the pool. Only one block of this size will fit. */ status = tx_byte_allocate(&pool_0, (VOID **) &pointer, 60, TX_NO_WAIT); @@ -114,7 +114,7 @@ CHAR *pointer; /* Terminate the other thread. */ status = tx_thread_terminate(&thread_1); - + /* Check status. */ if (status != TX_SUCCESS) { @@ -147,7 +147,7 @@ CHAR *pointer; printf("ERROR #7\n"); test_control_return(1); } - + /* Successful test. */ printf("SUCCESS!\n"); test_control_return(0); diff --git a/test/tx/regression/threadx_event_flag_basic_test.c b/test/tx/regression/threadx_event_flag_basic_test.c index 9c19f9bd..3261f67f 100644 --- a/test/tx/regression/threadx_event_flag_basic_test.c +++ b/test/tx/regression/threadx_event_flag_basic_test.c @@ -75,14 +75,14 @@ ULONG actual_events; /* Determine if calling event flag create from initialization was successful. */ if (test_event_flags_from_init != TX_SUCCESS) { - + /* Error! */ error++; } /* Attempt to create an event flag group from a timer. */ status = tx_event_flags_create(&group_2, "group 2"); - + /* Check status. */ if (status != TX_CALLER_ERROR) { @@ -185,8 +185,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -198,8 +198,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -213,7 +213,7 @@ CHAR *pointer; /* Create event flag group 0 and 1. */ status = tx_event_flags_create(&group_0, "group 0"); - + /* Check status. */ if (status != TX_SUCCESS) { @@ -231,7 +231,7 @@ CHAR *pointer; printf("Running Event Flag Basic Test....................................... ERROR #4\n"); test_control_return(1); } - + /* Register the event set notify function. */ status = tx_event_flags_set_notify(&group_0, event_set_notify); @@ -278,7 +278,7 @@ CHAR *pointer; test_control_return(1); } #endif - + } @@ -300,11 +300,11 @@ ULONG actual_events; event_flag_memory.second = 0x55667788; event_flag_memory.next_to_last = 0x99aabbcc; event_flag_memory.last = 0xddeeff00; - + /* Create the event flag group. */ status = tx_event_flags_create(&event_flag_memory.event_flags, "group memory"); tx_event_flags_delete(&event_flag_memory.event_flags); - + /* Check for status. */ if ((status != TX_SUCCESS) || (event_flag_memory.first != 0x11223344) || @@ -312,7 +312,7 @@ ULONG actual_events; (event_flag_memory.next_to_last != 0x99aabbcc) || (event_flag_memory.last != 0xddeeff00)) { - + /* Event flag error. */ printf("ERROR #7\n"); test_control_return(1); @@ -324,7 +324,7 @@ ULONG actual_events; /* Try to create with a NULL pointer. */ status = tx_event_flags_create(TX_NULL, "group 0"); - + /* Check status. */ if (status != TX_GROUP_ERROR) { @@ -333,10 +333,10 @@ ULONG actual_events; printf("ERROR #8\n"); test_control_return(1); } - + /* Try to create with a bad size. */ status = _txe_event_flags_create(&group_3, "group 3", (sizeof(TX_EVENT_FLAGS_GROUP)+1)); - + /* Check status. */ if (status != TX_GROUP_ERROR) { @@ -345,10 +345,10 @@ ULONG actual_events; printf("ERROR #9\n"); test_control_return(1); } - + /* Try to create an already created group. */ status = tx_event_flags_create(&group_0, "group 0"); - + /* Check status. */ if (status != TX_GROUP_ERROR) { @@ -369,7 +369,7 @@ ULONG actual_events; printf("ERROR #11\n"); test_control_return(1); } - + /* Delete with a non-created pointer. */ group_2.tx_event_flags_group_id = 0; status = tx_event_flags_delete(&group_2); @@ -518,7 +518,7 @@ ULONG actual_events; printf("ERROR #23\n"); test_control_return(1); } - + /* Attempt to get events from an empty event flag group. AND CLEAR option. */ status = tx_event_flags_get(&group_0, 0x80008000, TX_AND_CLEAR, &actual_events, TX_NO_WAIT); @@ -604,7 +604,7 @@ ULONG actual_events; printf("ERROR #30\n"); test_control_return(1); } - + /* Attempt to get events from event flag group. AND CLEAR option. */ status = tx_event_flags_get(&group_0, 0x80008000, TX_AND_CLEAR, &actual_events, TX_NO_WAIT); @@ -691,7 +691,7 @@ ULONG actual_events; /* Test for error. */ if ((error) || (timer_executed != 1) || (isr_executed != 1)) { - + /* Block memory error. */ printf("ERROR #36\n"); test_control_return(1); @@ -737,7 +737,7 @@ static void thread_1_entry(ULONG thread_input) while(1) { - tx_thread_relinquish(); + tx_thread_relinquish(); } } diff --git a/test/tx/regression/threadx_event_flag_information_test.c b/test/tx/regression/threadx_event_flag_information_test.c index 1f03fdf3..d2404081 100644 --- a/test/tx/regression/threadx_event_flag_information_test.c +++ b/test/tx/regression/threadx_event_flag_information_test.c @@ -54,8 +54,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -69,7 +69,7 @@ CHAR *pointer; /* Create event flag group 0 and 1. */ status = tx_event_flags_create(&group_0, "group 0"); - + /* Check status. */ if (status != TX_SUCCESS) { @@ -87,10 +87,10 @@ CHAR *pointer; printf("Running Event Flag Information Test................................. ERROR #3\n"); test_control_return(1); } - + /* Register the event set notify function. */ status = tx_event_flags_set_notify(&group_0, event_set_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check status. */ @@ -162,7 +162,7 @@ ULONG timeouts; printf("ERROR #7\n"); test_control_return(1); } - + /* Attempt to get events from an empty event flag group. AND CLEAR option. */ status = tx_event_flags_get(&group_0, 0x80008000, TX_AND_CLEAR, &actual_events, TX_NO_WAIT); @@ -248,7 +248,7 @@ ULONG timeouts; printf("ERROR #14\n"); test_control_return(1); } - + /* Attempt to get events from event flag group. AND CLEAR option. */ status = tx_event_flags_get(&group_0, 0x80008000, TX_AND_CLEAR, &actual_events, TX_NO_WAIT); @@ -343,7 +343,7 @@ ULONG timeouts; /* Get information about the event flag group. */ status = tx_event_flags_info_get(&group_0, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_event_flags_info_get(&group_0, &name, ¤t_flags, &first_suspended, &suspended_count, &next_group); - + /* Check the status. */ if ((status != TX_SUCCESS) || (current_flags != group_0.tx_event_flags_group_current) || (first_suspended != TX_NULL) || (suspended_count != 0) || (next_group != &group_1)) { @@ -357,7 +357,7 @@ ULONG timeouts; /* Get performance information with NULL pointer. */ status = _tx_event_flags_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); - + /* Check the status. */ if (status != TX_PTR_ERROR) { @@ -370,9 +370,9 @@ ULONG timeouts; /* Get performance information on the event flag group. */ status = tx_event_flags_performance_info_get(&group_0, TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_event_flags_performance_info_get(&group_0, &sets, &gets, &suspensions, &timeouts); - + /* Check the status. */ - if ((status != TX_SUCCESS) || (sets != group_0.tx_event_flags_group_performance_set_count) || (gets != group_0.tx_event_flags_group__performance_get_count) || + if ((status != TX_SUCCESS) || (sets != group_0.tx_event_flags_group_performance_set_count) || (gets != group_0.tx_event_flags_group__performance_get_count) || (suspensions != group_0.tx_event_flags_group___performance_suspension_count) || (timeouts != group_0.tx_event_flags_group____performance_timeout_count)) { @@ -384,9 +384,9 @@ ULONG timeouts; /* Get system performance information on all event flags groups. */ status = tx_event_flags_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_event_flags_performance_system_info_get(&sets, &gets, &suspensions, &timeouts); - + /* Check the status. */ - if ((status != TX_SUCCESS) || (sets != _tx_event_flags_performance_set_count) || (gets != _tx_event_flags_performance_get_count) || + if ((status != TX_SUCCESS) || (sets != _tx_event_flags_performance_set_count) || (gets != _tx_event_flags_performance_get_count) || (suspensions != _tx_event_flags_performance_suspension_count) || (timeouts != _tx_event_flags_performance_timeout_count)) { diff --git a/test/tx/regression/threadx_event_flag_isr_set_clear_test.c b/test/tx/regression/threadx_event_flag_isr_set_clear_test.c index 2d2f28af..7f89a06f 100644 --- a/test/tx/regression/threadx_event_flag_isr_set_clear_test.c +++ b/test/tx/regression/threadx_event_flag_isr_set_clear_test.c @@ -65,7 +65,7 @@ static volatile UINT miss_count = 0; condition_count++; } - /* + /* It is possible for this test to get into a resonance condition in which the ISR never occurs while preemption is disabled (especially if the ISR is installed in the periodic timer interrupt handler, which is @@ -89,10 +89,10 @@ static volatile UINT miss_count = 0; /* Setup some event flags just so we can clear them. */ status += tx_event_flags_set(&event_flags_0, 0x30000, TX_OR); - + /* Clear the same flags immediately. */ status += tx_event_flags_set(&event_flags_0, 0xFFFEFFFF, TX_AND); - + /* Clear the same flags immediately. */ status += tx_event_flags_set(&event_flags_0, 0xFFFDFFFC, TX_AND); @@ -102,11 +102,11 @@ static volatile UINT miss_count = 0; /* Get the events from an ISR. */ status = tx_event_flags_get(&event_flags_0, 0x30000, TX_OR, &actual, TX_NO_WAIT); - + /* Check to make sure this results in an error. */ if (status != TX_NO_EVENTS) return; - + /* Do a set and a get consume from an ISR. */ status = tx_event_flags_set(&event_flags_0, 0x000000C0, TX_OR); @@ -142,8 +142,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -155,8 +155,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -168,8 +168,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -183,7 +183,7 @@ CHAR *pointer; /* Create event flags group. */ status = tx_event_flags_create(&event_flags_0, "event_flags 0"); - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -202,7 +202,7 @@ CHAR *pointer; printf("Running Event Flag Set/Clear from ISR Test.......................... ERROR #5\n"); test_control_return(1); } - + /* Register the event set notify function. */ status = tx_event_flags_set_notify(&event_flags_0, event_set_notify); @@ -243,7 +243,7 @@ ULONG actual; printf("Running Event Flag Set/Clear from ISR Test.......................... "); /* Setup the test ISR. */ - test_isr_dispatch = test_isr; + test_isr_dispatch = test_isr; /* Loop to exploit the probability window inside tx_event_flags_set call. */ while (condition_count < 40) @@ -253,7 +253,7 @@ ULONG actual; status = tx_event_flags_get(&event_flags_0, 2, TX_OR_CLEAR, &actual, 4); /* Determine if we have an unexpected result. */ - if (status != TX_SUCCESS) + if (status != TX_SUCCESS) { /* Test error! */ @@ -280,7 +280,7 @@ ULONG actual; } /* Setup the test ISR. */ - test_isr_dispatch = TX_NULL; + test_isr_dispatch = TX_NULL; /* Let the other threads run once more... */ tx_thread_relinquish(); @@ -319,7 +319,7 @@ ULONG actual; status = tx_event_flags_get(&event_flags_0, 1, TX_OR_CLEAR, &actual, 4); /* Determine if we have an unexpected result. */ - if (status != TX_SUCCESS) + if (status != TX_SUCCESS) { break; diff --git a/test/tx/regression/threadx_event_flag_isr_wait_abort_test.c b/test/tx/regression/threadx_event_flag_isr_wait_abort_test.c index 1c9bf5d2..e1ec4e7c 100644 --- a/test/tx/regression/threadx_event_flag_isr_wait_abort_test.c +++ b/test/tx/regression/threadx_event_flag_isr_wait_abort_test.c @@ -64,7 +64,7 @@ static volatile UINT miss_count = 0; condition_count++; } - /* + /* It is possible for this test to get into a resonance condition in which the ISR never occurs while preemption is disabled (especially if the ISR is installed in the periodic timer interrupt handler, which is @@ -86,10 +86,10 @@ static volatile UINT miss_count = 0; /* Abort the threads 1 and 2. */ status += tx_thread_wait_abort(&thread_0); status += tx_thread_wait_abort(&thread_1); - + if (status == TX_SUCCESS) { - + event_flags_wait_abort_counter++; } } @@ -115,8 +115,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -128,8 +128,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -141,8 +141,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -156,7 +156,7 @@ CHAR *pointer; /* Create event flags group. */ status = tx_event_flags_create(&event_flags_0, "event_flags 0"); - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -175,10 +175,10 @@ CHAR *pointer; printf("Running Event Flag Wait Abort from ISR Test......................... ERROR #5\n"); test_control_return(1); } - + /* Register the event set notify function. */ status = tx_event_flags_set_notify(&event_flags_0, event_set_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check status. */ @@ -217,7 +217,7 @@ ULONG actual; printf("Running Event Flag Wait Abort from ISR Test......................... "); /* Setup the test ISR. */ - test_isr_dispatch = test_isr; + test_isr_dispatch = test_isr; /* Loop to exploit the probability window inside tx_event_flags_set call. */ while (condition_count < 40) @@ -227,7 +227,7 @@ ULONG actual; status = tx_event_flags_get(&event_flags_0, 2, TX_OR_CLEAR, &actual, 4); /* Determine if we have an unexpected result. */ - if (status != TX_WAIT_ABORTED) + if (status != TX_WAIT_ABORTED) { /* Test error! */ @@ -254,7 +254,7 @@ ULONG actual; } /* Setup the test ISR. */ - test_isr_dispatch = TX_NULL; + test_isr_dispatch = TX_NULL; /* Let the other threads run once more... */ tx_thread_relinquish(); @@ -293,7 +293,7 @@ ULONG actual; status = tx_event_flags_get(&event_flags_0, 1, TX_OR_CLEAR, &actual, 4); /* Determine if we have an unexpected result. */ - if (status != TX_WAIT_ABORTED) + if (status != TX_WAIT_ABORTED) { break; diff --git a/test/tx/regression/threadx_event_flag_single_thread_terminate_test.c b/test/tx/regression/threadx_event_flag_single_thread_terminate_test.c index a5db6e41..86675890 100644 --- a/test/tx/regression/threadx_event_flag_single_thread_terminate_test.c +++ b/test/tx/regression/threadx_event_flag_single_thread_terminate_test.c @@ -54,8 +54,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -67,8 +67,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -80,8 +80,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -106,7 +106,7 @@ CHAR *pointer; /* Register the event set notify function. */ status = tx_event_flags_set_notify(&group_0, event_set_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check status. */ @@ -160,7 +160,7 @@ UINT status; printf("ERROR #7\n"); test_control_return(1); } - + /* Now terminate thread 1. */ status = tx_thread_terminate(&thread_1); @@ -206,9 +206,9 @@ UINT status; test_control_return(1); } - /* At this point, thread 2 is suspended on the flags again. Or some flags that are + /* At this point, thread 2 is suspended on the flags again. Or some flags that are not needed. */ - + /* Set an event flag that is not needed. */ status = tx_event_flags_set(&group_0, 0x00000001, TX_OR); @@ -231,7 +231,7 @@ UINT status; tx_thread_sleep(5); /* Check status and run counters. */ - if ((status != TX_SUCCESS) || (thread_1_counter != 1) || (thread_2_counter != 3) || + if ((status != TX_SUCCESS) || (thread_1_counter != 1) || (thread_2_counter != 3) || (_tx_thread_preempt_disable)) { @@ -280,7 +280,7 @@ UINT status; /* Check status. */ if (status != TX_SUCCESS) { - thread_1_counter = 0; /* Make an error! */ + thread_1_counter = 0; /* Make an error! */ return; } } diff --git a/test/tx/regression/threadx_event_flag_suspension_consume_test.c b/test/tx/regression/threadx_event_flag_suspension_consume_test.c index b83a8123..aae8f1b9 100644 --- a/test/tx/regression/threadx_event_flag_suspension_consume_test.c +++ b/test/tx/regression/threadx_event_flag_suspension_consume_test.c @@ -55,8 +55,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -68,8 +68,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -81,8 +81,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -94,8 +94,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -120,7 +120,7 @@ CHAR *pointer; /* Register the event set notify function. */ status = tx_event_flags_set_notify(&group_0, event_set_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check status. */ diff --git a/test/tx/regression/threadx_event_flag_suspension_different_bits_consume_test.c b/test/tx/regression/threadx_event_flag_suspension_different_bits_consume_test.c index fa4a985a..595e60ed 100644 --- a/test/tx/regression/threadx_event_flag_suspension_different_bits_consume_test.c +++ b/test/tx/regression/threadx_event_flag_suspension_different_bits_consume_test.c @@ -51,8 +51,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -64,8 +64,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -78,8 +78,8 @@ CHAR *pointer; } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -101,10 +101,10 @@ CHAR *pointer; printf("Running Event Flag Suspension/Consumption Unique Bit Test........... ERROR #4\n"); test_control_return(1); } - + /* Register the event set notify function. */ status = tx_event_flags_set_notify(&group_0, event_set_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check status. */ @@ -140,7 +140,7 @@ UINT status; /* Inform user. */ printf("Running Event Flag Suspension/Consumption Unique Bit Test........... "); - + /* Increment run counter. */ thread_0_counter++; diff --git a/test/tx/regression/threadx_event_flag_suspension_different_bits_test.c b/test/tx/regression/threadx_event_flag_suspension_different_bits_test.c index 92505744..f9e43cad 100644 --- a/test/tx/regression/threadx_event_flag_suspension_different_bits_test.c +++ b/test/tx/regression/threadx_event_flag_suspension_different_bits_test.c @@ -51,8 +51,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -64,8 +64,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -78,8 +78,8 @@ CHAR *pointer; } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -104,7 +104,7 @@ CHAR *pointer; /* Register the event set notify function. */ status = tx_event_flags_set_notify(&group_0, event_set_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check status. */ @@ -140,7 +140,7 @@ UINT status; /* Inform user. */ printf("Running Event Flag Suspension Unique Bit Test....................... "); - + /* Increment run counter. */ thread_0_counter++; diff --git a/test/tx/regression/threadx_event_flag_suspension_test.c b/test/tx/regression/threadx_event_flag_suspension_test.c index 3587fadd..915e33db 100644 --- a/test/tx/regression/threadx_event_flag_suspension_test.c +++ b/test/tx/regression/threadx_event_flag_suspension_test.c @@ -58,8 +58,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -71,8 +71,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -84,8 +84,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -97,8 +97,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -110,8 +110,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -136,7 +136,7 @@ CHAR *pointer; /* Register the event set notify function. */ status = tx_event_flags_set_notify(&group_0, event_set_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check status. */ @@ -223,11 +223,11 @@ int i; /* Resume thread 4 so it can suspend on the event flag group too. */ status += tx_thread_resume(&thread_4); - + /* Determine if there was an error. */ if ((status != TX_SUCCESS) || (thread_4_counter != 1)) { - + /* Event flag error. */ printf("ERROR #11\n"); test_control_return(1); @@ -239,7 +239,7 @@ int i; /* Determine if there was an error. */ if ((status != TX_SUCCESS) || (thread_4_counter != 2)) { - + /* Event flag error. */ printf("ERROR #12\n"); test_control_return(1); diff --git a/test/tx/regression/threadx_event_flag_suspension_timeout_test.c b/test/tx/regression/threadx_event_flag_suspension_timeout_test.c index c689c755..149cb58f 100644 --- a/test/tx/regression/threadx_event_flag_suspension_timeout_test.c +++ b/test/tx/regression/threadx_event_flag_suspension_timeout_test.c @@ -54,8 +54,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -67,12 +67,12 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -84,8 +84,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -110,7 +110,7 @@ CHAR *pointer; /* Register the event set notify function. */ status = tx_event_flags_set_notify(&group_0, event_set_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check status. */ @@ -140,7 +140,7 @@ CHAR *pointer; static void thread_0_entry(ULONG thread_input) { - + ULONG actual_events; UINT status; @@ -209,7 +209,7 @@ UINT status; ULONG actual_events; - + /* Wait for event flags. */ while(1) { diff --git a/test/tx/regression/threadx_event_flag_thread_terminate_test.c b/test/tx/regression/threadx_event_flag_thread_terminate_test.c index eecb76e6..166711f5 100644 --- a/test/tx/regression/threadx_event_flag_thread_terminate_test.c +++ b/test/tx/regression/threadx_event_flag_thread_terminate_test.c @@ -52,8 +52,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -65,8 +65,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -78,8 +78,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -101,7 +101,7 @@ CHAR *pointer; printf("Running Event Flag Thread Terminate Test............................ ERROR #4\n"); test_control_return(1); } - + /* Register the event set notify function. */ status = tx_event_flags_set_notify(&group_0, event_set_notify); diff --git a/test/tx/regression/threadx_initialize_kernel_setup_test.c b/test/tx/regression/threadx_initialize_kernel_setup_test.c index f248694d..2ef8e158 100644 --- a/test/tx/regression/threadx_initialize_kernel_setup_test.c +++ b/test/tx/regression/threadx_initialize_kernel_setup_test.c @@ -10,7 +10,7 @@ TEST_FLAG test_forced_mutex_timeout; TEST_FLAG threadx_mutex_suspension_put_test; TEST_FLAG threadx_mutex_suspension_priority_test; TEST_FLAG threadx_byte_allocate_loop_test; -TEST_FLAG test_initialize_flag; +TEST_FLAG test_initialize_flag; TEST_FLAG threadx_byte_release_loop_test; TEST_FLAG test_stack_analyze_flag; diff --git a/test/tx/regression/threadx_interrupt_control_test.c b/test/tx/regression/threadx_interrupt_control_test.c index d58ceba3..c573c098 100644 --- a/test/tx/regression/threadx_interrupt_control_test.c +++ b/test/tx/regression/threadx_interrupt_control_test.c @@ -1,4 +1,4 @@ -/* This test is designed to test the interrupt control service call avaialbe to the +/* This test is designed to test the interrupt control service call avaialbe to the application. */ #include @@ -36,8 +36,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; diff --git a/test/tx/regression/threadx_mutex_basic_test.c b/test/tx/regression/threadx_mutex_basic_test.c index 2e784961..419813d3 100644 --- a/test/tx/regression/threadx_mutex_basic_test.c +++ b/test/tx/regression/threadx_mutex_basic_test.c @@ -77,7 +77,7 @@ UINT status; /* Attempt to create a mutex from a timer. */ status = tx_mutex_create(&mutex_4, "mutex 4", TX_NO_INHERIT); - + /* Check status. */ if (status != TX_CALLER_ERROR) { @@ -96,7 +96,7 @@ UINT status; /* Error! */ error++; } - + /* Attempt to get from mutex from a timer with suspension. */ status = tx_mutex_get(&mutex_2, 100); @@ -124,7 +124,7 @@ UINT status; /* Attempt to create a mutex from an ISR. */ status = tx_mutex_create(&mutex_4, "mutex 4", TX_NO_INHERIT); - + /* Check status. */ if (status != TX_CALLER_ERROR) { @@ -201,29 +201,29 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_3, "thread 3", thread_3_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_3, "thread 3", thread_3_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_4, "thread 4", thread_4_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_4, "thread 4", thread_4_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -309,11 +309,11 @@ UINT status; mutex_memory.second = 0x55667788; mutex_memory.next_to_last = 0x99aabbcc; mutex_memory.last = 0xddeeff00; - + /* Create the semaphore. */ status = tx_mutex_create(&mutex_memory.mutex, "mutex memory", TX_INHERIT); tx_mutex_delete(&mutex_memory.mutex); - + /* Check for status. */ if ((status != TX_SUCCESS) || (mutex_memory.first != 0x11223344) || @@ -326,7 +326,7 @@ UINT status; printf("ERROR #6\n"); test_control_return(1); } - + /* Increment thread 0 counter. */ thread_0_counter++; @@ -334,7 +334,7 @@ UINT status; /* Attempt to create a mutex with a NULL pointer. */ status = tx_mutex_create(TX_NULL, "mutex 2", TX_INHERIT); - + /* Check status. */ if (status != TX_MUTEX_ERROR) { @@ -346,7 +346,7 @@ UINT status; /* Attempt to create a mutex with a bad size. */ status = _txe_mutex_create(&mutex_5, "mutex 5", TX_INHERIT, (sizeof(TX_MUTEX)+1)); - + /* Check status. */ if (status != TX_MUTEX_ERROR) { @@ -358,7 +358,7 @@ UINT status; /* Attempt to create a mutex that has already been created. */ status = tx_mutex_create(&mutex_2, "mutex 2", TX_INHERIT); - + /* Check status. */ if (status != TX_MUTEX_ERROR) { @@ -370,7 +370,7 @@ UINT status; /* Attempt to create a mutex with a bad inheritance option. */ status = tx_mutex_create(&mutex_4, "mutex 4", 14); - + /* Check status. */ if (status != TX_INHERIT_ERROR) { @@ -509,7 +509,7 @@ UINT status; /* Attempt to get the mutex. Should be unsuccessful. */ status = tx_mutex_get(&mutex_1, TX_NO_WAIT); - + /* Check status. */ if (status != TX_NOT_AVAILABLE) { @@ -535,7 +535,7 @@ UINT status; } status = tx_mutex_delete(&mutex_1); - + /* Check status. */ if (status != TX_SUCCESS) { @@ -592,7 +592,7 @@ UINT status; /* Test for error. */ if ((error) || (timer_executed != 1) || (isr_executed != 1)) { - + /* Block memory error. */ printf("ERROR #26\n"); test_control_return(1); @@ -603,7 +603,7 @@ UINT status; /* Release mutex multiple times. */ status = tx_mutex_put(&mutex_2); status += tx_mutex_put(&mutex_2); - + /* Check status. */ if (status != TX_NOT_OWNED) { @@ -624,7 +624,7 @@ UINT status; printf("ERROR #28\n"); test_control_return(1); } - + /* Delete mutex. */ status = tx_mutex_delete(&mutex_2); @@ -639,14 +639,14 @@ UINT status; /* Get mutex 8. */ status = tx_mutex_get(&mutex_8, TX_WAIT_FOREVER); - + /* Start thread 3 and 4. */ status += tx_thread_resume(&thread_3); status += tx_thread_resume(&thread_4); - + /* Sleep to let thread 3 suspend on the mutex. */ tx_thread_sleep(2); - + /* Now, put the mutex to give it to thread 3. */ status += tx_mutex_put(&mutex_8); @@ -660,7 +660,7 @@ UINT status; } status = tx_mutex_delete(&mutex_3); - + /* Check status. */ if (status != TX_SUCCESS) { @@ -713,14 +713,14 @@ UINT status; test_control_return(1); } - /* Create and obtain a couple mutexes so the thread completion can release them. */ + /* Create and obtain a couple mutexes so the thread completion can release them. */ status = tx_mutex_create(&mutex_6, "mutex 6", TX_NO_INHERIT); status += tx_mutex_create(&mutex_7, "mutex 7", TX_NO_INHERIT); status += tx_mutex_get(&mutex_6, TX_NO_WAIT); status += tx_mutex_get(&mutex_7, TX_NO_WAIT); status += tx_mutex_get(&mutex_6, TX_NO_WAIT); status += tx_mutex_get(&mutex_7, TX_NO_WAIT); - + /* Check status. */ if (status != TX_SUCCESS) { @@ -738,7 +738,7 @@ static void thread_2_entry(ULONG thread_input) while(1) { - tx_thread_relinquish(); + tx_thread_relinquish(); } } @@ -748,7 +748,7 @@ static void thread_3_entry(ULONG thread_input) while(1) { - + tx_mutex_get(&mutex_8, TX_WAIT_FOREVER); tx_mutex_put(&mutex_8); } @@ -760,7 +760,7 @@ static void thread_4_entry(ULONG thread_input) while(1) { - + tx_mutex_get(&mutex_8, TX_WAIT_FOREVER); tx_mutex_put(&mutex_8); } diff --git a/test/tx/regression/threadx_mutex_delete_test.c b/test/tx/regression/threadx_mutex_delete_test.c index 28676f4b..af501488 100644 --- a/test/tx/regression/threadx_mutex_delete_test.c +++ b/test/tx/regression/threadx_mutex_delete_test.c @@ -47,8 +47,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -60,8 +60,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -73,8 +73,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; diff --git a/test/tx/regression/threadx_mutex_information_test.c b/test/tx/regression/threadx_mutex_information_test.c index e95c16c6..55503002 100644 --- a/test/tx/regression/threadx_mutex_information_test.c +++ b/test/tx/regression/threadx_mutex_information_test.c @@ -50,14 +50,14 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -196,7 +196,7 @@ ULONG inheritances; /* Attempt to get the mutex. Should be unsuccessful. */ status = tx_mutex_get(&mutex_1, TX_NO_WAIT); - + /* Check status. */ if (status != TX_NOT_AVAILABLE) { @@ -222,7 +222,7 @@ ULONG inheritances; } status = tx_mutex_delete(&mutex_1); - + /* Check status. */ if (status != TX_SUCCESS) { @@ -289,7 +289,7 @@ ULONG inheritances; status += tx_mutex_info_get(&mutex_2, &name, &count, &owner, &first_suspended, &suspended_count, &next_mutex); /* Check status. */ - if ((status != TX_SUCCESS) || (count != mutex_2.tx_mutex_ownership_count) || (owner != mutex_2.tx_mutex_owner) || + if ((status != TX_SUCCESS) || (count != mutex_2.tx_mutex_ownership_count) || (owner != mutex_2.tx_mutex_owner) || (first_suspended != mutex_2.tx_mutex_suspension_list) || (suspended_count != mutex_2.tx_mutex_suspended_count) || (next_mutex != mutex_2.tx_mutex_created_next)) { @@ -314,7 +314,7 @@ ULONG inheritances; /* Now get the performance inforamtion. */ status = tx_mutex_performance_info_get(&mutex_2, &puts, &gets, &suspensions, &timeouts, &inversions, &inheritances); - + /* Check status. */ if ((status != TX_SUCCESS) || (puts != mutex_2.tx_mutex_performance_put_count) || (gets != mutex_2.tx_mutex_performance_get_count) || (suspensions != mutex_2.tx_mutex_performance_suspension_count) || (timeouts != mutex_2.tx_mutex_performance_timeout_count) || @@ -325,10 +325,10 @@ ULONG inheritances; printf("ERROR #19\n"); test_control_return(1); } - + /* Now get the system performance inforamtion. */ status = tx_mutex_performance_system_info_get(&puts, &gets, &suspensions, &timeouts, &inversions, &inheritances); - + /* Check status. */ if ((status != TX_SUCCESS) || (puts != _tx_mutex_performance_put_count) || (gets != _tx_mutex_performance_get_count) || (suspensions != _tx_mutex_performance_suspension_count) || (timeouts != _tx_mutex_performance_timeout_count) || @@ -537,7 +537,7 @@ ULONG inheritances; } status = tx_mutex_delete(&mutex_3); - + /* Check status. */ if (status != TX_SUCCESS) { diff --git a/test/tx/regression/threadx_mutex_nested_priority_inheritance_test.c b/test/tx/regression/threadx_mutex_nested_priority_inheritance_test.c index 7397b4e2..1439ca85 100644 --- a/test/tx/regression/threadx_mutex_nested_priority_inheritance_test.c +++ b/test/tx/regression/threadx_mutex_nested_priority_inheritance_test.c @@ -9,7 +9,7 @@ /* Define the ThreadX object control blocks... */ static TX_THREAD thread_0; -#ifndef TX_DISABLE_PREEMPTION_THRESHOLD +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD static TX_THREAD thread_1; static TX_THREAD thread_2; static TX_THREAD thread_3; @@ -37,7 +37,7 @@ static ULONG thread_6_counter; /* Define thread prototypes. */ static void thread_0_entry(ULONG thread_input); -#ifndef TX_DISABLE_PREEMPTION_THRESHOLD +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD static void thread_1_entry(ULONG thread_input); static void thread_2_entry(ULONG thread_input); static void thread_3_entry(ULONG thread_input); @@ -66,8 +66,8 @@ UINT status; pointer = (CHAR *) first_unused_memory; /* Create thread. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 16, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; @@ -79,11 +79,11 @@ UINT status; test_control_return(1); } -#ifndef TX_DISABLE_PREEMPTION_THRESHOLD - +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD + /* Create thread. */ - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 8, 8, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + DEMO_STACK_SIZE; @@ -96,8 +96,8 @@ UINT status; } /* Create thread. */ - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + DEMO_STACK_SIZE; @@ -110,8 +110,8 @@ UINT status; } /* Create thread. */ - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, DEMO_STACK_SIZE, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, DEMO_STACK_SIZE, 30, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; @@ -124,8 +124,8 @@ UINT status; } /* Create thread. */ - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, DEMO_STACK_SIZE, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, DEMO_STACK_SIZE, 4, 4, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + DEMO_STACK_SIZE; @@ -138,8 +138,8 @@ UINT status; } /* Create thread. */ - status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, DEMO_STACK_SIZE, + status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, 2, 2, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + DEMO_STACK_SIZE; @@ -152,8 +152,8 @@ UINT status; } /* Create thread. */ - status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, - pointer, DEMO_STACK_SIZE, + status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, + pointer, DEMO_STACK_SIZE, 30, 30, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + DEMO_STACK_SIZE; @@ -188,7 +188,7 @@ UINT status; static void thread_0_entry(ULONG thread_input) { -#ifdef TX_DISABLE_PREEMPTION_THRESHOLD +#ifdef TX_DISABLE_PREEMPTION_THRESHOLD /* Preemption threshold is not enabled, skip this test. */ @@ -196,8 +196,8 @@ static void thread_0_entry(ULONG thread_input) printf("Running Mutex Nested Priority Inheritance Test...................... SUCCESS!\n"); test_control_return(0); -#else - +#else + UINT test_case = 0; UINT loop_count = 0; UINT priority; @@ -238,7 +238,7 @@ UINT status; test_control_return(1); } - /* Release the mutexes... Depending on the order they are released should dictate + /* Release the mutexes... Depending on the order they are released should dictate the thread's returned to priority. */ if (test_case == 0) { @@ -267,7 +267,7 @@ UINT status; } tx_mutex_put(&mutex_0); - + /* No change. */ if (thread_0.tx_thread_priority != 15) { @@ -281,7 +281,7 @@ UINT status; { priority = thread_0.tx_thread_priority; - tx_mutex_put(&mutex_0); + tx_mutex_put(&mutex_0); /* Should have no change in priority since nothing was inherited for this mutex. */ if (thread_0.tx_thread_priority != priority) @@ -292,7 +292,7 @@ UINT status; test_control_return(4); } - tx_mutex_put(&mutex_1); + tx_mutex_put(&mutex_1); /* Should not do anything since mutex 2 elevated to a higher priority. */ if (thread_0.tx_thread_priority != priority) @@ -303,7 +303,7 @@ UINT status; test_control_return(5); } - tx_mutex_put(&mutex_2); + tx_mutex_put(&mutex_2); /* Should go back to priority 15. */ if (thread_0.tx_thread_priority != 15) @@ -317,7 +317,7 @@ UINT status; else if (test_case == 2) { - tx_mutex_put(&mutex_2); + tx_mutex_put(&mutex_2); /* Should go back to priority 8. */ if (thread_0.tx_thread_priority != 8) @@ -328,7 +328,7 @@ UINT status; test_control_return(7); } - tx_mutex_put(&mutex_0); + tx_mutex_put(&mutex_0); /* Should not do anything. */ if (thread_0.tx_thread_priority != 8) @@ -339,7 +339,7 @@ UINT status; test_control_return(8); } - tx_mutex_put(&mutex_1); + tx_mutex_put(&mutex_1); /* Should go back to priority 15. */ if (thread_0.tx_thread_priority != 15) @@ -354,7 +354,7 @@ UINT status; { priority = thread_0.tx_thread_priority; - tx_mutex_put(&mutex_1); + tx_mutex_put(&mutex_1); /* Should not do anything since mutex 2 is still owned. */ if (thread_0.tx_thread_priority != priority) @@ -366,7 +366,7 @@ UINT status; } tx_mutex_put(&mutex_0); - + /* Should not do anything. */ if (thread_0.tx_thread_priority != priority) { @@ -376,7 +376,7 @@ UINT status; test_control_return(11); } - tx_mutex_put(&mutex_2); + tx_mutex_put(&mutex_2); /* Should finally go back to priority 15. */ if (thread_0.tx_thread_priority != 15) @@ -391,7 +391,7 @@ UINT status; { priority = thread_0.tx_thread_priority; - tx_mutex_put(&mutex_1); + tx_mutex_put(&mutex_1); /* Should not do anything since mutex 2 is still owned. */ if (thread_0.tx_thread_priority != priority) @@ -402,7 +402,7 @@ UINT status; test_control_return(13); } - tx_mutex_put(&mutex_2); + tx_mutex_put(&mutex_2); /* Should reurn us back to priority 15. */ if (thread_0.tx_thread_priority != 15) @@ -413,7 +413,7 @@ UINT status; test_control_return(14); } - tx_mutex_put(&mutex_0); + tx_mutex_put(&mutex_0); /* Should not do anything. */ if (thread_0.tx_thread_priority != 15) @@ -428,7 +428,7 @@ UINT status; { priority = thread_0.tx_thread_priority; - tx_mutex_put(&mutex_0); + tx_mutex_put(&mutex_0); /* Should not do anything since mutex 2 is still owned. */ if (thread_0.tx_thread_priority != priority) @@ -439,7 +439,7 @@ UINT status; test_control_return(16); } - tx_mutex_put(&mutex_2); + tx_mutex_put(&mutex_2); /* Should reurn us back to priority 8. */ if (thread_0.tx_thread_priority != 8) @@ -451,7 +451,7 @@ UINT status; } tx_mutex_put(&mutex_1); - + /* Should return us back to priority 15. */ if (thread_0.tx_thread_priority != 15) { @@ -470,60 +470,60 @@ UINT status; /* Check for thread 3 running... this should not happen! */ if (thread_3_counter != 50) { - + printf("ERROR #25\n"); test_control_return(19); } /* At this point, mutex 3 owned by this thread. */ - + /* Resume thread 6, lowest priority thread. */ status = tx_thread_resume(&thread_6); - + /* Check for an error. */ if ((status != TX_SUCCESS) || (thread_0.tx_thread_priority != 15) || (thread_6_counter != 0)) { - + printf("ERROR #27\n"); test_control_return(19); } - + /* Now resume thread 4. */ status = tx_thread_resume(&thread_4); - + /* Check for an error. */ if ((status != TX_SUCCESS) || (thread_0.tx_thread_priority != 4) || (thread_6_counter != 0)) { - + printf("ERROR #28\n"); test_control_return(19); } - + /* Now resume thread 5. */ status = tx_thread_resume(&thread_5); - + /* Check for an error. */ if ((status != TX_SUCCESS) || (thread_0.tx_thread_priority != 2) || (thread_6_counter != 0)) { - + printf("ERROR #29\n"); test_control_return(19); } - + /* Sleep to let thread 6 run, which is lower priority. */ tx_thread_sleep(1); - + /* Now release the mutex. */ status = tx_mutex_put(&mutex_3); /* Check for an error. */ if ((status != TX_SUCCESS) || (thread_0.tx_thread_priority != 15) || (thread_6_counter != 0) || (thread_4_counter != 1) || (thread_5_counter != 1)) { - + printf("ERROR #30\n"); test_control_return(19); } - + /* Sleep to let thread 6 run and release the mutex. */ tx_thread_sleep(2); @@ -534,7 +534,7 @@ UINT status; #endif } -#ifndef TX_DISABLE_PREEMPTION_THRESHOLD +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD static void thread_1_entry(ULONG thread_input) { @@ -551,8 +551,8 @@ UINT old_threshold; /* Update the thread priority and thread preemption-threshold of thread 0. */ tx_thread_priority_change(&thread_0, 15, &old_priority); - tx_thread_preemption_change(&thread_0, 14, &old_threshold); - + tx_thread_preemption_change(&thread_0, 14, &old_threshold); + /* Get mutex. */ tx_mutex_get(&mutex_1, TX_WAIT_FOREVER); tx_mutex_put(&mutex_1); @@ -564,8 +564,8 @@ UINT old_threshold; /* Update the thread priority and thread preemption-threshold of thread 0. */ tx_thread_priority_change(&thread_0, 15, &old_priority); - tx_thread_preemption_change(&thread_0, 8, &old_threshold); - + tx_thread_preemption_change(&thread_0, 8, &old_threshold); + /* Get mutex. */ tx_mutex_get(&mutex_1, TX_WAIT_FOREVER); tx_mutex_put(&mutex_1); @@ -638,7 +638,7 @@ static void thread_4_entry(ULONG thread_input) while(1) { - + /* Get priority inherit mutex. */ tx_mutex_get(&mutex_3, TX_WAIT_FOREVER); diff --git a/test/tx/regression/threadx_mutex_no_preemption_test.c b/test/tx/regression/threadx_mutex_no_preemption_test.c index c26c3651..3cc21b62 100644 --- a/test/tx/regression/threadx_mutex_no_preemption_test.c +++ b/test/tx/regression/threadx_mutex_no_preemption_test.c @@ -43,8 +43,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -56,8 +56,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; diff --git a/test/tx/regression/threadx_mutex_preemption_test.c b/test/tx/regression/threadx_mutex_preemption_test.c index 238dda03..495ae13c 100644 --- a/test/tx/regression/threadx_mutex_preemption_test.c +++ b/test/tx/regression/threadx_mutex_preemption_test.c @@ -43,8 +43,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -56,8 +56,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; diff --git a/test/tx/regression/threadx_mutex_priority_inheritance_test.c b/test/tx/regression/threadx_mutex_priority_inheritance_test.c index 68a7f0ce..0b76aba6 100644 --- a/test/tx/regression/threadx_mutex_priority_inheritance_test.c +++ b/test/tx/regression/threadx_mutex_priority_inheritance_test.c @@ -1,4 +1,4 @@ -/* This test is designed to test the mutex suspension and priority inheritance with another +/* This test is designed to test the mutex suspension and priority inheritance with another thread resuming the higher priority thread by doing a mutex put. Higher-priority thread should preempt. */ #include @@ -74,16 +74,16 @@ CHAR *pointer; /* Test for an error creating/using a mutex from initialization. */ if (test_mutex_from_init != TX_SUCCESS) { - + printf("Running Mutex Priority Inheritance Test............................. ERROR #0\n"); test_control_return(1); - } + } /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -95,8 +95,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -108,8 +108,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 14, 14, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -123,8 +123,8 @@ CHAR *pointer; /* Create a high-priority thread that will get all the priority inheritance mutexes and return from it's entry function in order to test the auto delete feature. */ - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 10, 10, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -137,8 +137,8 @@ CHAR *pointer; } /* Create a higher-priority thread that is used to get thread 4 into a priority inheritance state. */ - status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, TEST_STACK_SIZE_PRINTF, 8, 8, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -152,8 +152,8 @@ CHAR *pointer; /* Create a higher-priority thread that is used to suspend on priority inheritance mutex 3. */ - status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, + pointer, TEST_STACK_SIZE_PRINTF, 6, 6, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -167,8 +167,8 @@ CHAR *pointer; /* Create a higher-priority thread that is used to suspend on priority inheritance mutex 3. */ - status = tx_thread_create(&thread_7, "thread 7", thread_7_entry, 7, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_7, "thread 7", thread_7_entry, 7, + pointer, TEST_STACK_SIZE_PRINTF, 7, 7, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -246,7 +246,7 @@ UINT status; /* Resume thread 4 to test the automatic release of the mutexes. */ tx_thread_resume(&thread_4); - + /* Determine if thread 4 was able to get the mutexes before completion... and have its original priority restored after the priority inheritance. */ if ((thread_4_counter != 1) || (thread_5_counter != 1) || (thread_4.tx_thread_priority != 10) || @@ -274,10 +274,10 @@ UINT status; printf("ERROR #13\n"); test_control_return(1); } - + /* Release mutex 2 to be compatible with original test. */ tx_mutex_put(&mutex_2); - + /* Now resume the higher priority thread to cause suspension. */ tx_thread_resume(&thread_1); @@ -314,8 +314,8 @@ UINT status; printf("ERROR #16\n"); test_control_return(1); } - - /* Now sleep for 20 ticks in order to test the priority inheritance change of a + + /* Now sleep for 20 ticks in order to test the priority inheritance change of a non-ready thread. */ tx_thread_sleep(20); @@ -330,10 +330,10 @@ UINT status; /* Resume thread 2 in order to get two threads suspended on the mutex. */ tx_thread_resume(&thread_2); - + /* Now do a mutex put to release both threads suspended on this mutex. */ status = tx_mutex_put(&mutex_0); - + /* The other thread should now be suspended on the mutex. */ if ((status != TX_SUCCESS) || (thread_1_counter != 4) || (thread_2_counter != 2) || (thread_0.tx_thread_priority != 16)) { @@ -342,7 +342,7 @@ UINT status; printf("ERROR #18\n"); test_control_return(1); } - + /* At this point, get the mutex again. */ status = tx_mutex_get(&mutex_0, TX_NO_WAIT); @@ -354,7 +354,7 @@ UINT status; printf("ERROR #19\n"); test_control_return(1); } - + /* Abort the sleep. */ tx_thread_wait_abort(&thread_1); tx_thread_wait_abort(&thread_2); @@ -362,10 +362,10 @@ UINT status; /* Now both threads are suspended again on mutex... and then terminate them. */ tx_thread_terminate(&thread_1); tx_thread_terminate(&thread_2); - + /* Now do a mutex put to release both threads suspended on this mutex. */ status = tx_mutex_put(&mutex_0); - + /* The other thread should now be suspended on the mutex. */ if ((status != TX_SUCCESS) || (thread_1_counter != 5) || (thread_2_counter != 3) || (thread_0.tx_thread_priority != 16)) { @@ -376,21 +376,21 @@ UINT status; } /* Now test the timeout on the suspension list of a priority inheritance mutex. */ - + /* First, obtain priority inheritance mutex 3. */ status = tx_mutex_get(&mutex_3, TX_WAIT_FOREVER); - + /* Next resume threads 6 and 7 so they will block on trying to get this mutex forever. */ status += tx_thread_resume(&thread_7); status += tx_thread_resume(&thread_6); - + /* Now set the flag which will cause the last thread in the suspension list to timeout (abort) resulting in a NULL suspension list and covering that branch condition in tx_mutex_put */ test_forced_mutex_timeout = 1; - + /* Perform a mutex put to release the mutex. */ status += tx_mutex_put(&mutex_3); - + /* Now check for errors. */ #ifndef TX_MISRA_ENABLE #ifndef TX_MANUAL_TEST @@ -404,9 +404,9 @@ UINT status; #endif #else if ((status != TX_SUCCESS) || (thread_6_counter != 1)) -#endif +#endif { - + /* Mutex error. */ printf("ERROR #21\n"); test_control_return(1); @@ -429,7 +429,7 @@ UINT status; while(1) { - + /* Increment thread run counter. */ thread_1_counter++; @@ -440,9 +440,9 @@ UINT status; /* Did we get the right status? */ if (status == TX_SUCCESS) thread_1_counter++; - + /* Sleep for 10 ticks... to delay. */ - tx_thread_sleep(10); + tx_thread_sleep(10); } } @@ -458,7 +458,7 @@ UINT status; while(1) { - + /* Increment thread run counter. */ thread_2_counter++; @@ -469,9 +469,9 @@ UINT status; /* Did we get the right status? */ if (status == TX_SUCCESS) thread_2_counter++; - + /* Sleep for 10 ticks... to delay. */ - tx_thread_sleep(10); + tx_thread_sleep(10); } } @@ -481,7 +481,7 @@ static void thread_4_entry(ULONG thread_input) UINT status; - + /* Get mutex to cause additional ownership linked-list processing. */ status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); status += tx_mutex_get(&mutex_1, TX_WAIT_FOREVER); @@ -492,7 +492,7 @@ UINT status; /* Resume thread 5 to get into priority inheritance. */ tx_thread_resume(&thread_5); - /* Determine if all the mutex gets were successful... and we have + /* Determine if all the mutex gets were successful... and we have inherited priority 8. */ if ((status == TX_SUCCESS) && (thread_4.tx_thread_priority == 8)) { @@ -501,7 +501,7 @@ UINT status; thread_4_counter++; } - /* Now fall through and make sure the mutex cleanup function + /* Now fall through and make sure the mutex cleanup function releases all the mutexes. */ } @@ -511,7 +511,7 @@ static void thread_5_entry(ULONG thread_input) UINT status; - + /* Get mutex to cause priority inheritance in thread 4. */ status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); @@ -523,7 +523,7 @@ UINT status; thread_5_counter++; } - /* Now fall through and make sure the mutex cleanup function + /* Now fall through and make sure the mutex cleanup function releases all the mutexes. */ } @@ -533,7 +533,7 @@ static void thread_6_entry(ULONG thread_input) UINT status; - + /* Get mutex to cause priority inheritance in thread 0. */ status = tx_mutex_get(&mutex_3, TX_WAIT_FOREVER); @@ -545,7 +545,7 @@ UINT status; thread_6_counter++; } - /* Now fall through and make sure the mutex cleanup function + /* Now fall through and make sure the mutex cleanup function releases all the mutexes. */ } @@ -555,7 +555,7 @@ static void thread_7_entry(ULONG thread_input) UINT status; - + /* Get mutex to cause priority inheritance in thread 0. */ status = tx_mutex_get(&mutex_3, TX_WAIT_FOREVER); @@ -567,7 +567,7 @@ UINT status; thread_7_counter++; } - /* Now fall through and make sure the mutex cleanup function + /* Now fall through and make sure the mutex cleanup function releases all the mutexes. */ } diff --git a/test/tx/regression/threadx_mutex_proritize_test.c b/test/tx/regression/threadx_mutex_proritize_test.c index 4e25673f..bbc2845b 100644 --- a/test/tx/regression/threadx_mutex_proritize_test.c +++ b/test/tx/regression/threadx_mutex_proritize_test.c @@ -76,12 +76,12 @@ static void test_isr(void) } else { - + /* Abort the wait of thread 5. */ tx_thread_wait_abort(&thread_5); /* End the ISR processing. */ - test_status = 2; + test_status = 2; test_isr_dispatch = TX_NULL; } } @@ -107,8 +107,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -120,8 +120,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -133,8 +133,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 14, 14, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -146,8 +146,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 3, 3, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -159,8 +159,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 4, 4, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -172,8 +172,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, TEST_STACK_SIZE_PRINTF, 5, 5, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -185,8 +185,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, + pointer, TEST_STACK_SIZE_PRINTF, 6, 6, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -323,7 +323,7 @@ UINT status; tx_thread_resume(&thread_4); tx_thread_resume(&thread_5); tx_thread_resume(&thread_6); - + /* Prioritize the block pool suspension list. */ status = tx_mutex_prioritize(&mutex_0); @@ -338,7 +338,7 @@ UINT status; /* Now loop to test the interrupt of the prioritize loop logic. */ test_status = 1; - test_isr_dispatch = test_isr; + test_isr_dispatch = test_isr; do { @@ -355,10 +355,10 @@ UINT status; } } while (test_status == 1); - + /* Now determine if thread 4 is at the front of the list... It should be! */ if (mutex_0.tx_mutex_suspension_list != &thread_4) - { + { /* Mutex error. */ printf("ERROR #17\n"); @@ -382,19 +382,19 @@ UINT status; while (1) { - + /* Suspend on the mutex. */ status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); /* Release the mutex. */ status += tx_mutex_put(&mutex_0); - + /* Did we get the right status? */ if (status == TX_SUCCESS) thread_1_counter++; /* Self suspend. */ - tx_thread_suspend(&thread_1); + tx_thread_suspend(&thread_1); } } @@ -407,19 +407,19 @@ UINT status; while (1) { - + /* Suspend on the mutex. */ status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); /* Release the mutex. */ status += tx_mutex_put(&mutex_0); - + /* Did we get the right status? */ if (status == TX_SUCCESS) thread_2_counter++; /* Self suspend. */ - tx_thread_suspend(&thread_2); + tx_thread_suspend(&thread_2); } } @@ -432,19 +432,19 @@ UINT status; while (1) { - + /* Suspend on the mutex. */ status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); /* Release the mutex. */ status += tx_mutex_put(&mutex_0); - + /* Did we get the right status? */ if (status == TX_SUCCESS) thread_3_counter++; /* Self suspend. */ - tx_thread_suspend(&thread_3); + tx_thread_suspend(&thread_3); } } @@ -457,19 +457,19 @@ UINT status; while (1) { - + /* Suspend on the mutex. */ status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); /* Release the mutex. */ status += tx_mutex_put(&mutex_0); - + /* Did we get the right status? */ if (status == TX_SUCCESS) thread_4_counter++; /* Self suspend. */ - tx_thread_suspend(&thread_4); + tx_thread_suspend(&thread_4); } } @@ -482,19 +482,19 @@ UINT status; while (1) { - + /* Suspend on the mutex. */ status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); /* Release the mutex. */ status += tx_mutex_put(&mutex_0); - + /* Did we get the right status? */ if (status == TX_SUCCESS) thread_5_counter++; /* Self suspend. */ - tx_thread_suspend(&thread_5); + tx_thread_suspend(&thread_5); } } @@ -507,19 +507,19 @@ UINT status; while (1) { - + /* Suspend on the mutex. */ status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); /* Release the mutex. */ status += tx_mutex_put(&mutex_0); - + /* Did we get the right status? */ if (status == TX_SUCCESS) thread_6_counter++; /* Self suspend. */ - tx_thread_suspend(&thread_6); + tx_thread_suspend(&thread_6); } } diff --git a/test/tx/regression/threadx_mutex_suspension_timeout_test.c b/test/tx/regression/threadx_mutex_suspension_timeout_test.c index cae257b5..f1a9dfd0 100644 --- a/test/tx/regression/threadx_mutex_suspension_timeout_test.c +++ b/test/tx/regression/threadx_mutex_suspension_timeout_test.c @@ -44,7 +44,7 @@ extern TEST_FLAG threadx_mutex_suspension_priority_test; #endif -/* This test routine is used to get NULL suspension lists in various parts of tx_mutex_put. This is hooked up to IRQ 0 on this simulation and is entered manually at the +/* This test routine is used to get NULL suspension lists in various parts of tx_mutex_put. This is hooked up to IRQ 0 on this simulation and is entered manually at the correct time. */ void abort_all_threads_suspended_on_mutex(void) { @@ -56,7 +56,7 @@ TX_THREAD *thread_ptr; { if (thread_ptr -> tx_thread_state == TX_MUTEX_SUSP) tx_thread_wait_abort(thread_ptr); - + thread_ptr = thread_ptr -> tx_thread_created_next; if (thread_ptr == _tx_thread_created_ptr) break; @@ -64,7 +64,7 @@ TX_THREAD *thread_ptr; } -/* This test routine is used to get a thread of a non ready state into _tx_mutex_change, called froim _tx_mutex_put. This is hooked up to IRQ 1 on this simulation and is entered manually at the +/* This test routine is used to get a thread of a non ready state into _tx_mutex_change, called froim _tx_mutex_put. This is hooked up to IRQ 1 on this simulation and is entered manually at the correct time. */ void suspend_lowest_priority(void) { @@ -92,28 +92,28 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 1, 1, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 2, 2, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 3, 3, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 4, 4, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&low_priority, "low priority", low_priority_entry, 30, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&low_priority, "low priority", low_priority_entry, 30, + pointer, TEST_STACK_SIZE_PRINTF, 30, 30, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -176,7 +176,7 @@ UINT old_priority; /* Get the mutex. */ status = tx_mutex_get(&mutex_1, TX_WAIT_FOREVER); - + /* Make sure the three higher priority threads suspend on the mutex. */ tx_thread_resume(&thread_4); tx_thread_resume(&thread_3); @@ -196,48 +196,48 @@ UINT old_priority; #endif /* Now some hand testing for tx_mutex_priority_change. */ - - /* Resume the low priority thread. */ + + /* Resume the low priority thread. */ tx_thread_resume(&low_priority); - + /* Simulate a call from inside of mutex put, but doing it here makes life easier. */ _tx_thread_preempt_disable++; - + #ifdef TX_MANUAL_TEST /* Set BP here and step into code and step through the code until the internal thread resume function returns, then issue an IRQ 1 to cause an ISR to suspend the thread and test the first condition. */ _tx_mutex_priority_change(&low_priority, 30); #else - + /* Set the flag to suspend the thread and test the first condition after internal resume is called. */ threadx_mutex_suspension_priority_test = 1; _tx_mutex_priority_change(&low_priority, 30); #endif - - /* Resume the low priority thread. */ + + /* Resume the low priority thread. */ tx_thread_resume(&low_priority); /* Now call internal _tx_mutex_priority_change, this should test the preemption-threshold throw-away path. */ _tx_mutex_priority_change(&low_priority, 30); - + /* Now make it so we can have a higher-priority thread ready but not the execute pointer because of preemption-threshold. */ tx_thread_preemption_change(&thread_0, 10, &old_preempt); tx_thread_priority_change(&low_priority, 10, &old_priority); - + /* Now call the internal mutex priority change on this thread to get the throw-away path on original priority being the same when execute ptr is different. */ _tx_thread_execute_ptr = &low_priority; _tx_mutex_priority_change(&low_priority, 10); _tx_thread_execute_ptr = &thread_0; - + /* Now make the low priority thread lower again, but with a preemption-threshold equal to thread_0. This will test yet another throw away condition. */ low_priority.tx_thread_inherit_priority = ((UINT) TX_MAX_PRIORITIES); tx_thread_priority_change(&low_priority, 30, &old_priority); tx_thread_preemption_change(&low_priority, 10, &old_preempt); - + /* Now call the internal mutex priority change on this thread with the same priority. */ _tx_mutex_priority_change(&low_priority, 30); _tx_thread_preempt_disable--; - + /* Successful test. */ printf("SUCCESS!\n"); test_control_return(0); diff --git a/test/tx/regression/threadx_mutex_thread_terminate_test.c b/test/tx/regression/threadx_mutex_thread_terminate_test.c index 9b552f54..ef21b92d 100644 --- a/test/tx/regression/threadx_mutex_thread_terminate_test.c +++ b/test/tx/regression/threadx_mutex_thread_terminate_test.c @@ -47,8 +47,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -60,8 +60,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -73,8 +73,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; diff --git a/test/tx/regression/threadx_queue_basic_eight_word_test.c b/test/tx/regression/threadx_queue_basic_eight_word_test.c index c201fdee..fb4640cc 100644 --- a/test/tx/regression/threadx_queue_basic_eight_word_test.c +++ b/test/tx/regression/threadx_queue_basic_eight_word_test.c @@ -1,5 +1,5 @@ /* This test is designed to test immediate response queue services including create - and delete. This test is for queue sizes of 8 ULONG. Two queues are used one with + and delete. This test is for queue sizes of 8 ULONG. Two queues are used one with a capacity of 1 message and another with a capacity of 3 messages. */ #include @@ -40,8 +40,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -111,9 +111,9 @@ ULONG expected_message[8]; printf("ERROR #4\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -163,9 +163,9 @@ ULONG expected_message[8]; printf("ERROR #8\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -218,7 +218,7 @@ ULONG expected_message[8]; status += tx_queue_send(&queue_1, source_message, TX_NO_WAIT); source_message[0]++; source_message[7]++; - + if (status != TX_SUCCESS) { @@ -227,9 +227,9 @@ ULONG expected_message[8]; printf("ERROR #12\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -320,9 +320,9 @@ ULONG expected_message[8]; printf("ERROR #18\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) diff --git a/test/tx/regression/threadx_queue_basic_four_word_test.c b/test/tx/regression/threadx_queue_basic_four_word_test.c index 5e01bc5b..4c54d8bd 100644 --- a/test/tx/regression/threadx_queue_basic_four_word_test.c +++ b/test/tx/regression/threadx_queue_basic_four_word_test.c @@ -1,5 +1,5 @@ /* This test is designed to test immediate response queue services including create - and delete. This test is for queue sizes of 4 ULONG. Two queues are used one with + and delete. This test is for queue sizes of 4 ULONG. Two queues are used one with a capacity of 1 message and another with a capacity of 3 messages. */ #include @@ -40,8 +40,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -111,9 +111,9 @@ ULONG expected_message[4]; printf("ERROR #4\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -163,9 +163,9 @@ ULONG expected_message[4]; printf("ERROR #8\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -218,7 +218,7 @@ ULONG expected_message[4]; status += tx_queue_send(&queue_1, source_message, TX_NO_WAIT); source_message[0]++; source_message[3]++; - + if (status != TX_SUCCESS) { @@ -227,9 +227,9 @@ ULONG expected_message[4]; printf("ERROR #12\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -320,9 +320,9 @@ ULONG expected_message[4]; printf("ERROR #18\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) diff --git a/test/tx/regression/threadx_queue_basic_max_message_size_test.c b/test/tx/regression/threadx_queue_basic_max_message_size_test.c index 30afa190..d62e80ff 100644 --- a/test/tx/regression/threadx_queue_basic_max_message_size_test.c +++ b/test/tx/regression/threadx_queue_basic_max_message_size_test.c @@ -1,5 +1,5 @@ /* This test is designed to test immediate response queue services including create - and delete. This test is for queue sizes of 16 ULONG. Two queues are used one with + and delete. This test is for queue sizes of 16 ULONG. Two queues are used one with a capacity of 1 message and another with a capacity of 3 messages. */ #include @@ -40,8 +40,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -110,9 +110,9 @@ ULONG expected_message[TX_QUEUE_MESSAGE_MAX_SIZE]; printf("ERROR #4\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -162,9 +162,9 @@ ULONG expected_message[TX_QUEUE_MESSAGE_MAX_SIZE]; printf("ERROR #8\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -217,7 +217,7 @@ ULONG expected_message[TX_QUEUE_MESSAGE_MAX_SIZE]; status += tx_queue_send(&queue_1, source_message, TX_NO_WAIT); source_message[0]++; source_message[TX_QUEUE_MESSAGE_MAX_SIZE - 1]++; - + if (status != TX_SUCCESS) { @@ -226,9 +226,9 @@ ULONG expected_message[TX_QUEUE_MESSAGE_MAX_SIZE]; printf("ERROR #12\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -319,9 +319,9 @@ ULONG expected_message[TX_QUEUE_MESSAGE_MAX_SIZE]; printf("ERROR #18\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) diff --git a/test/tx/regression/threadx_queue_basic_one_word_test.c b/test/tx/regression/threadx_queue_basic_one_word_test.c index 142a9b60..0e2f1fbc 100644 --- a/test/tx/regression/threadx_queue_basic_one_word_test.c +++ b/test/tx/regression/threadx_queue_basic_one_word_test.c @@ -1,5 +1,5 @@ /* This test is designed to test immediate response queue services including create - and delete. This test is for queue sizes of 1 ULONG. Two queues are used one with + and delete. This test is for queue sizes of 1 ULONG. Two queues are used one with a capacity of 1 message and another with a capacity of 3 messages. */ #include @@ -40,7 +40,7 @@ static void thread_0_entry(ULONG thread_input); static void thread_1_entry(ULONG thread_input); -UINT _txe_queue_create(TX_QUEUE *queue_ptr, CHAR *name_ptr, UINT message_size, +UINT _txe_queue_create(TX_QUEUE *queue_ptr, CHAR *name_ptr, UINT message_size, VOID *queue_start, ULONG queue_size, UINT queue_control_block_size); @@ -65,7 +65,7 @@ ULONG destination; /* Determine if calling queue create from initialization was successful. */ if (test_queue_from_init != TX_SUCCESS) { - + /* Error! */ error++; } @@ -84,7 +84,7 @@ ULONG destination; /* Attempt to delete a queue from a timer. */ status = tx_queue_delete(&queue_0); - + /* Check for status. */ if (status != TX_CALLER_ERROR) { @@ -95,7 +95,7 @@ ULONG destination; /* Attempt to send something with suspension from a timer. */ status = tx_queue_front_send(&queue_0, &source, 100); - + /* Check for status. */ if (status != TX_WAIT_ERROR) { @@ -106,7 +106,7 @@ ULONG destination; /* Attempt to send something with suspension from a timer. */ status = tx_queue_send(&queue_0, &source, 100); - + /* Check for status. */ if (status != TX_WAIT_ERROR) { @@ -117,7 +117,7 @@ ULONG destination; /* Attempt to receive something with suspension from a timer. */ status = tx_queue_receive(&queue_0, &destination, 100); - + /* Check for status. */ if (status != TX_WAIT_ERROR) { @@ -158,7 +158,7 @@ ULONG destination; /* Attempt to delete a queue from an ISR. */ status = tx_queue_delete(&queue_0); - + /* Check for status. */ if (status != TX_CALLER_ERROR) { @@ -169,7 +169,7 @@ ULONG destination; /* Attempt to send something with suspension from an ISR. */ status = tx_queue_front_send(&queue_0, &source, 100); - + /* Check for status. */ if (status != TX_WAIT_ERROR) { @@ -180,7 +180,7 @@ ULONG destination; /* Attempt to send something with suspension from an ISR. */ status = tx_queue_send(&queue_0, &source, 100); - + /* Check for status. */ if (status != TX_WAIT_ERROR) { @@ -191,7 +191,7 @@ ULONG destination; /* Attempt to receive something with suspension from an ISR. */ status = tx_queue_receive(&queue_0, &destination, 100); - + /* Check for status. */ if (status != TX_WAIT_ERROR) { @@ -224,13 +224,13 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -380,7 +380,7 @@ CHAR *pointer; /* Attempt to delete a NULL pointer. */ status = tx_queue_delete(TX_NULL); - + /* Check for status. */ if (status != TX_QUEUE_ERROR) { @@ -393,7 +393,7 @@ CHAR *pointer; /* Attempt to delete a non-created queue. */ queue_2.tx_queue_id = 0; status = tx_queue_delete(&queue_2); - + /* Check for status. */ if (status != TX_QUEUE_ERROR) { @@ -405,7 +405,7 @@ CHAR *pointer; /* Attempt to flush a NULL pointer. */ status = tx_queue_flush(TX_NULL); - + /* Check for status. */ if (status != TX_QUEUE_ERROR) { @@ -418,7 +418,7 @@ CHAR *pointer; /* Attempt to flush a non-created queue. */ queue_2.tx_queue_id = 0; status = tx_queue_flush(&queue_2); - + /* Check for status. */ if (status != TX_QUEUE_ERROR) { @@ -430,7 +430,7 @@ CHAR *pointer; /* Attempt to send something to the front of a non-queue. */ status = tx_queue_front_send(TX_NULL, &source_message, TX_NO_WAIT); - + /* Check for status. */ if (status != TX_QUEUE_ERROR) { @@ -439,11 +439,11 @@ CHAR *pointer; printf("ERROR #15\n"); test_control_return(1); } - + /* Attempt to send something to the front of a non-created queue. */ queue_2.tx_queue_id = 0; status = tx_queue_front_send(&queue_2, &source_message, TX_NO_WAIT); - + /* Check for status. */ if (status != TX_QUEUE_ERROR) { @@ -455,7 +455,7 @@ CHAR *pointer; /* Attempt to send something with a NULL source pointer. */ status = tx_queue_front_send(&queue_0, TX_NULL, TX_NO_WAIT); - + /* Check for status. */ if (status != TX_PTR_ERROR) { @@ -467,7 +467,7 @@ CHAR *pointer; /* Attempt to send something to a non-queue. */ status = tx_queue_send(TX_NULL, &source_message, TX_NO_WAIT); - + /* Check for status. */ if (status != TX_QUEUE_ERROR) { @@ -476,11 +476,11 @@ CHAR *pointer; printf("ERROR #18\n"); test_control_return(1); } - + /* Attempt to send something to a non-created queue. */ queue_2.tx_queue_id = 0; status = tx_queue_send(&queue_2, &source_message, TX_NO_WAIT); - + /* Check for status. */ if (status != TX_QUEUE_ERROR) { @@ -492,7 +492,7 @@ CHAR *pointer; /* Attempt to send something with a NULL source pointer. */ status = tx_queue_send(&queue_0, TX_NULL, TX_NO_WAIT); - + /* Check for status. */ if (status != TX_PTR_ERROR) { @@ -504,7 +504,7 @@ CHAR *pointer; /* Attempt to receive something from a non-queue. */ status = tx_queue_receive(TX_NULL, &dest_message, TX_NO_WAIT); - + /* Check for status. */ if (status != TX_QUEUE_ERROR) { @@ -517,7 +517,7 @@ CHAR *pointer; /* Attempt to receive something from a non-created queue. */ queue_2.tx_queue_id = 0; status = tx_queue_receive(&queue_2, &dest_message, TX_NO_WAIT); - + /* Check for status. */ if (status != TX_QUEUE_ERROR) { @@ -529,7 +529,7 @@ CHAR *pointer; /* Attempt to receive something to a NULL destination. */ status = tx_queue_receive(&queue_0, TX_NULL, TX_NO_WAIT); - + /* Check for status. */ if (status != TX_PTR_ERROR) { @@ -550,9 +550,9 @@ CHAR *pointer; printf("ERROR #24\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_0, &source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_0, &source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -602,7 +602,7 @@ CHAR *pointer; } /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_0, &source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_0, &source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -649,7 +649,7 @@ CHAR *pointer; source_message++; status += tx_queue_send(&queue_1, &source_message, TX_NO_WAIT); source_message++; - + if (status != TX_SUCCESS) { @@ -657,9 +657,9 @@ CHAR *pointer; printf("ERROR #32\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_1, &source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_1, &source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -735,9 +735,9 @@ CHAR *pointer; printf("ERROR #38\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_1, &source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_1, &source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -810,7 +810,7 @@ CHAR *pointer; /* Resume thread 1 so that we can take an interrupt on top of it. */ tx_thread_resume(&thread_1); - + /* Sleep for a bit... */ tx_thread_sleep(3); @@ -820,7 +820,7 @@ CHAR *pointer; /* Test for error. */ if ((error) || (timer_executed != 1) || (isr_executed != 1)) { - + /* Queue error. */ printf("ERROR #44\n"); test_control_return(1); diff --git a/test/tx/regression/threadx_queue_basic_sixteen_word_test.c b/test/tx/regression/threadx_queue_basic_sixteen_word_test.c index 703a1cf4..de3ede98 100644 --- a/test/tx/regression/threadx_queue_basic_sixteen_word_test.c +++ b/test/tx/regression/threadx_queue_basic_sixteen_word_test.c @@ -1,5 +1,5 @@ /* This test is designed to test immediate response queue services including create - and delete. This test is for queue sizes of 16 ULONG. Two queues are used one with + and delete. This test is for queue sizes of 16 ULONG. Two queues are used one with a capacity of 1 message and another with a capacity of 3 messages. */ #include @@ -40,8 +40,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -111,9 +111,9 @@ ULONG expected_message[16]; printf("ERROR #4\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -163,9 +163,9 @@ ULONG expected_message[16]; printf("ERROR #8\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -218,7 +218,7 @@ ULONG expected_message[16]; status += tx_queue_send(&queue_1, source_message, TX_NO_WAIT); source_message[0]++; source_message[15]++; - + if (status != TX_SUCCESS) { @@ -227,9 +227,9 @@ ULONG expected_message[16]; printf("ERROR #12\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -320,9 +320,9 @@ ULONG expected_message[16]; printf("ERROR #18\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) diff --git a/test/tx/regression/threadx_queue_basic_two_word_test.c b/test/tx/regression/threadx_queue_basic_two_word_test.c index ab24d08e..46d85a6d 100644 --- a/test/tx/regression/threadx_queue_basic_two_word_test.c +++ b/test/tx/regression/threadx_queue_basic_two_word_test.c @@ -1,5 +1,5 @@ /* This test is designed to test immediate response queue services including create - and delete. This test is for queue sizes of 2 ULONG. Two queues are used one with + and delete. This test is for queue sizes of 2 ULONG. Two queues are used one with a capacity of 1 message and another with a capacity of 3 messages. */ #include @@ -54,8 +54,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -116,7 +116,7 @@ ULONG expected_message[2]; queue_memory.second_middle= 0x61718191; queue_memory.next_to_last = 0x99aabbcc; queue_memory.last = 0xddeeff00; - + /* Create the queue. */ status = tx_queue_create(&queue_memory.queue, "queue memory", TX_2_ULONG, &queue_memory.queue_area[0], (2048*sizeof(ULONG))/sizeof(ULONG)); tx_queue_delete(&queue_memory.queue); @@ -151,9 +151,9 @@ ULONG expected_message[2]; printf("ERROR #5\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -203,9 +203,9 @@ ULONG expected_message[2]; printf("ERROR #9\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_0, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -258,7 +258,7 @@ ULONG expected_message[2]; status += tx_queue_send(&queue_1, source_message, TX_NO_WAIT); source_message[0]++; source_message[1]++; - + if (status != TX_SUCCESS) { @@ -267,9 +267,9 @@ ULONG expected_message[2]; printf("ERROR #13\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -360,9 +360,9 @@ ULONG expected_message[2]; printf("ERROR #19\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_1, source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) diff --git a/test/tx/regression/threadx_queue_empty_suspension_test.c b/test/tx/regression/threadx_queue_empty_suspension_test.c index 59d53e70..c63b1715 100644 --- a/test/tx/regression/threadx_queue_empty_suspension_test.c +++ b/test/tx/regression/threadx_queue_empty_suspension_test.c @@ -54,8 +54,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -67,8 +67,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -80,8 +80,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -107,7 +107,7 @@ CHAR *pointer; /* Setup queue send notification. */ status = tx_queue_send_notify(&queue_0, queue_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check for status. */ @@ -117,7 +117,7 @@ CHAR *pointer; printf("Running Queue Empty Suspension Test................................. ERROR #5\n"); test_control_return(1); } - + #else /* Check for status. */ @@ -128,7 +128,7 @@ CHAR *pointer; test_control_return(1); } -#endif +#endif } @@ -193,12 +193,12 @@ ULONG source_message[2] = {0x12345678, 0}; /* Now resume thread 2 to get another thread suspended on an empty queue. */ tx_thread_resume(&thread_2); - + /* Now send 2 messages to wakeup both threads! */ source_message[0]++; status = tx_queue_send(&queue_0, &source_message[0], TX_NO_WAIT); status += tx_queue_send(&queue_0, &source_message[0], TX_NO_WAIT); - + /* Check status and run count of other thread - it should have got the message already. */ if ((status != TX_SUCCESS) || (thread_1_counter != 2) || (thread_2_counter != 1)) diff --git a/test/tx/regression/threadx_queue_flush_no_suspension_test.c b/test/tx/regression/threadx_queue_flush_no_suspension_test.c index 940259f2..95bd5fed 100644 --- a/test/tx/regression/threadx_queue_flush_no_suspension_test.c +++ b/test/tx/regression/threadx_queue_flush_no_suspension_test.c @@ -44,8 +44,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -73,7 +73,7 @@ CHAR *pointer; status = tx_queue_send_notify(&queue_0, queue_notify); #ifndef TX_DISABLE_NOTIFY_CALLBACKS - + /* Check for status. */ if (status != TX_SUCCESS) { diff --git a/test/tx/regression/threadx_queue_flush_test.c b/test/tx/regression/threadx_queue_flush_test.c index 6d65c971..77f8d2d5 100644 --- a/test/tx/regression/threadx_queue_flush_test.c +++ b/test/tx/regression/threadx_queue_flush_test.c @@ -52,8 +52,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -65,8 +65,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -78,8 +78,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -108,7 +108,7 @@ CHAR *pointer; status = tx_queue_send_notify(&queue_0, queue_notify); #ifndef TX_DISABLE_NOTIFY_CALLBACKS - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -203,7 +203,7 @@ UINT status; } else { - + /* Queue Flush error. */ printf("ERROR #11\n"); test_control_return(1); diff --git a/test/tx/regression/threadx_queue_front_send_test.c b/test/tx/regression/threadx_queue_front_send_test.c index 5329670b..d03e7ac2 100644 --- a/test/tx/regression/threadx_queue_front_send_test.c +++ b/test/tx/regression/threadx_queue_front_send_test.c @@ -60,8 +60,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -73,12 +73,12 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status = tx_thread_create(&thread_1a, "thread 1a", thread_1a_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1a, "thread 1a", thread_1a_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -90,12 +90,12 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status = tx_thread_create(&thread_2a, "thread 2a", thread_2a_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2a, "thread 2a", thread_2a_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -125,7 +125,7 @@ CHAR *pointer; status = tx_queue_send_notify(&queue_0, queue_notify); #ifndef TX_DISABLE_NOTIFY_CALLBACKS - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -164,7 +164,7 @@ ULONG temp[2]; printf("Running Queue Front Test............................................ "); /* Perform the 1 word queue front send test. */ - + /* Increment thread 0 counter. */ thread_0_counter++; @@ -178,7 +178,7 @@ ULONG temp[2]; printf("ERROR #7a\n"); test_control_return(1); } - + /* Place a new message on the front of the queue. */ temp[0] = 0xF000001; status = tx_queue_front_send(&queue_0a, &temp[0], TX_NO_WAIT); @@ -226,17 +226,17 @@ ULONG temp[2]; printf("ERROR #11a\n"); test_control_return(1); } - - /* At this point the queue is empty. Resume another thread to + + /* At this point the queue is empty. Resume another thread to suspend on an empty queue. */ tx_thread_resume(&thread_1a); - + /* Relinquish to get this thread suspended on the empty queue. */ tx_thread_relinquish(); - + /* Resume thread 2a to get another thread suspended on the empty queue. */ tx_thread_resume(&thread_2a); - + /* Now send something to the front of the queue, which will resume the first waiting thread. */ temp[0] = 0xFF00002; @@ -262,10 +262,10 @@ ULONG temp[2]; printf("ERROR #13a\n"); test_control_return(1); } - + /* Now relinquish again to let the other thread process the message. */ tx_thread_relinquish(); - + /* At this point, the other thread should have placed 2 messages on the queue so we will now send to the front, but without suspension. */ temp[0] = 0xFF00003; @@ -293,11 +293,11 @@ ULONG temp[2]; /* Now resume thread 2a to get another thread suspended on the queue. */ tx_thread_resume(&thread_2a); - + temp[0] = 0xFF00004; status = tx_queue_front_send(&queue_0a, &temp[0], TX_WAIT_FOREVER); - - /* When we get back, the other thread has received all the messages and + + /* When we get back, the other thread has received all the messages and verified they are in order AND relinquished. */ if ((status != TX_SUCCESS) || (thread_1a_counter != 1)) { @@ -307,7 +307,7 @@ ULONG temp[2]; test_control_return(1); } - + /* Perform the multiword queue front send test. */ @@ -328,7 +328,7 @@ ULONG temp[2]; printf("ERROR #7\n"); test_control_return(1); } - + /* Place a new message on the front of the queue. */ temp[0] = 0xF000001; status = tx_queue_front_send(&queue_0, &temp[0], TX_NO_WAIT); @@ -376,17 +376,17 @@ ULONG temp[2]; printf("ERROR #11\n"); test_control_return(1); } - - /* At this point the queue is empty. Resume another thread to + + /* At this point the queue is empty. Resume another thread to suspend on an empty queue. */ tx_thread_resume(&thread_1); - + /* Relinquish to get this thread suspended on the empty queue. */ tx_thread_relinquish(); - + /* Resume thread 2 to get another thread suspended on the empty queue. */ tx_thread_resume(&thread_2); - + /* Now send something to the front of the queue, which will resume the first waiting thread. */ temp[0] = 0xFF00002; @@ -412,10 +412,10 @@ ULONG temp[2]; printf("ERROR #13\n"); test_control_return(1); } - + /* Now relinquish again to let the other thread process the message. */ tx_thread_relinquish(); - + /* At this point, the other thread should have placed 2 messages on the queue so we will now send to the front, but without suspension. */ temp[0] = 0xFF00003; @@ -443,11 +443,11 @@ ULONG temp[2]; /* Now resume thread 2 to get another thread suspended on the queue. */ tx_thread_resume(&thread_2); - + temp[0] = 0xFF00004; status = tx_queue_front_send(&queue_0, &temp[0], TX_WAIT_FOREVER); - - /* When we get back, the other thread has received all the messages and + + /* When we get back, the other thread has received all the messages and verified they are in order AND relinquished. */ if ((status != TX_SUCCESS) || (thread_1_counter != 1)) { @@ -480,18 +480,18 @@ ULONG dest_message[2]; /* Determine if the message is good. */ if ((status != TX_SUCCESS) || (dest_message[0] != 0xFF00002)) return; - + /* Now fill the queue with two messages. */ status = tx_queue_send(&queue_0, &source_message[0], TX_WAIT_FOREVER); source_message[0]++; status += tx_queue_front_send(&queue_0, &source_message[0], TX_WAIT_FOREVER); - + if (status != TX_SUCCESS) return; /* Now let thread 0 send to the front of the queue with suspension. */ tx_thread_relinquish(); - + /* Attempt to receive three messages from the queue. */ status = tx_queue_receive(&queue_0, &dest_message[0], TX_NO_WAIT); @@ -518,10 +518,10 @@ ULONG dest_message[2]; status = tx_queue_send(&queue_0, &source_message[0], TX_WAIT_FOREVER); source_message[0]++; status += tx_queue_front_send(&queue_0, &source_message[0], TX_WAIT_FOREVER); - + if (status != TX_SUCCESS) return; - + /* Now let thread 0 send to the front of the queue with suspension. */ tx_thread_relinquish(); @@ -552,11 +552,11 @@ ULONG dest_message[2]; /* Should be an error. */ if ((status != TX_SUCCESS) || (dest_message[0] != 0xEE000003)) return; - + /* Increment this threads counter. */ thread_1_counter++; } - + static void thread_2_entry(ULONG thread_input) { @@ -567,7 +567,7 @@ ULONG destination_message[2]; /* Receive message. */ tx_queue_receive(&queue_0, &destination_message[0], TX_WAIT_FOREVER); - + /* Self suspend. */ tx_thread_suspend(&thread_2); @@ -590,18 +590,18 @@ ULONG dest_message[2]; /* Determine if the message is good. */ if ((status != TX_SUCCESS) || (dest_message[0] != 0xFF00002)) return; - + /* Now fill the queue with two messages. */ status = tx_queue_send(&queue_0a, &source_message[0], TX_WAIT_FOREVER); source_message[0]++; status += tx_queue_front_send(&queue_0a, &source_message[0], TX_WAIT_FOREVER); - + if (status != TX_SUCCESS) return; /* Now let thread 0 send to the front of the queue with suspension. */ tx_thread_relinquish(); - + /* Attempt to receive three messages from the queue. */ status = tx_queue_receive(&queue_0a, &dest_message[0], TX_NO_WAIT); @@ -628,10 +628,10 @@ ULONG dest_message[2]; status = tx_queue_send(&queue_0a, &source_message[0], TX_WAIT_FOREVER); source_message[0]++; status += tx_queue_front_send(&queue_0a, &source_message[0], TX_WAIT_FOREVER); - + if (status != TX_SUCCESS) return; - + /* Now let thread 0 send to the front of the queue with suspension. */ tx_thread_relinquish(); @@ -662,11 +662,11 @@ ULONG dest_message[2]; /* Should be an error. */ if ((status != TX_SUCCESS) || (dest_message[0] != 0xEE000003)) return; - + /* Increment this threads counter. */ thread_1a_counter++; } - + static void thread_2a_entry(ULONG thread_input) { @@ -677,7 +677,7 @@ ULONG destination_message[2]; /* Receive message. */ tx_queue_receive(&queue_0a, &destination_message[0], TX_WAIT_FOREVER); - + /* Self suspend. */ tx_thread_suspend(&thread_2a); diff --git a/test/tx/regression/threadx_queue_full_suspension_test.c b/test/tx/regression/threadx_queue_full_suspension_test.c index 556a4c77..687ef04a 100644 --- a/test/tx/regression/threadx_queue_full_suspension_test.c +++ b/test/tx/regression/threadx_queue_full_suspension_test.c @@ -66,8 +66,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -79,12 +79,12 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_1a, "thread 1a", thread_1a_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_1a, "thread 1a", thread_1a_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -96,12 +96,12 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_2a, "thread 2a", thread_2a_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_2a, "thread 2a", thread_2a_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -131,7 +131,7 @@ CHAR *pointer; status = tx_queue_send_notify(&queue_0, queue_notify); #ifndef TX_DISABLE_NOTIFY_CALLBACKS - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -167,7 +167,7 @@ ULONG dest_message[2]; /* Inform user. */ printf("Running Queue Full Suspension Test.................................. "); - + /* Perform the one word queue version. */ /* Suspend to get thread 1a to pend on the queue. */ @@ -179,14 +179,14 @@ ULONG dest_message[2]; tx_queue_delete(&queue_0a); status += tx_queue_create(&queue_0a, "queue 0a", TX_1_ULONG, queue_area, sizeof(queue_area)); - + /* Fill the queue with an initial 3 messages! */ status += tx_queue_send(&queue_0a, &source_message[0], TX_NO_WAIT); status += tx_queue_send(&queue_0a, &source_message[0], TX_NO_WAIT); status += tx_queue_send(&queue_0a, &source_message[0], TX_NO_WAIT); source_message[0]++; - /* Receive two of the messages back to put the first received message at the end + /* Receive two of the messages back to put the first received message at the end of the queue. */ status += tx_queue_receive(&queue_0a, &dest_message[0], TX_NO_WAIT); status += tx_queue_receive(&queue_0a, &dest_message[0], TX_NO_WAIT); @@ -219,12 +219,12 @@ ULONG dest_message[2]; test_control_return(1); } - /* Perform the two word queue version. */ - + /* Perform the two word queue version. */ + /* Reset the source message. */ source_message[0] = 0x12345678; - source_message[1] = 0; - + source_message[1] = 0; + /* Resume threads 1 and 2. */ tx_thread_resume(&thread_1); tx_thread_resume(&thread_2); @@ -235,7 +235,7 @@ ULONG dest_message[2]; status += tx_queue_send(&queue_0, &source_message[0], TX_NO_WAIT); source_message[0]++; - /* Receive two of the messages back to put the first received message at the end + /* Receive two of the messages back to put the first received message at the end of the queue. */ status += tx_queue_receive(&queue_0, &dest_message[0], TX_NO_WAIT); status += tx_queue_receive(&queue_0, &dest_message[0], TX_NO_WAIT); diff --git a/test/tx/regression/threadx_queue_information_test.c b/test/tx/regression/threadx_queue_information_test.c index c1db82ca..5fcdbb8f 100644 --- a/test/tx/regression/threadx_queue_information_test.c +++ b/test/tx/regression/threadx_queue_information_test.c @@ -43,8 +43,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -147,9 +147,9 @@ ULONG timeouts; printf("ERROR #5\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_0, &source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_0, &source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -199,7 +199,7 @@ ULONG timeouts; } /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_0, &source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_0, &source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -246,7 +246,7 @@ ULONG timeouts; source_message++; status += tx_queue_send(&queue_1, &source_message, TX_NO_WAIT); source_message++; - + if (status != TX_SUCCESS) { @@ -254,9 +254,9 @@ ULONG timeouts; printf("ERROR #13\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_1, &source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_1, &source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -332,9 +332,9 @@ ULONG timeouts; printf("ERROR #19\n"); test_control_return(1); } - + /* Attempt to place something on a full queue. */ - status = tx_queue_send(&queue_1, &source_message, TX_NO_WAIT); + status = tx_queue_send(&queue_1, &source_message, TX_NO_WAIT); /* Should be an error. */ if (status != TX_QUEUE_FULL) @@ -397,9 +397,9 @@ ULONG timeouts; status = tx_queue_info_get(&queue_0, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_queue_info_get(&queue_0, &name, &enqueued, &available_storage, &first_suspended, &suspended_count, &next_queue); - /* Check for errors. */ - if ((status != TX_SUCCESS) || (enqueued != queue_0.tx_queue_enqueued) || (available_storage != queue_0.tx_queue_available_storage) || - (first_suspended != queue_0.tx_queue_suspension_list) || (suspended_count != queue_0.tx_queue_suspended_count) || + /* Check for errors. */ + if ((status != TX_SUCCESS) || (enqueued != queue_0.tx_queue_enqueued) || (available_storage != queue_0.tx_queue_available_storage) || + (first_suspended != queue_0.tx_queue_suspension_list) || (suspended_count != queue_0.tx_queue_suspended_count) || (next_queue != queue_0.tx_queue_created_next)) { @@ -413,7 +413,7 @@ ULONG timeouts; /* Test null pointer for queue performance info get. */ status = _tx_queue_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_PTR_ERROR) { @@ -426,9 +426,9 @@ ULONG timeouts; status = tx_queue_performance_info_get(&queue_0, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_queue_performance_info_get(&queue_0, &messages_sent, &messages_received, &empty_suspensions, &full_suspensions, &full_errors, &timeouts); - /* Check for errors. */ - if ((status != TX_SUCCESS) || (messages_sent != queue_0.tx_queue_performance_messages_sent_count) || (messages_received != queue_0.tx_queue_performance_messages_received_count) || - (empty_suspensions != queue_0.tx_queue_performance_empty_suspension_count) || (full_suspensions != queue_0.tx_queue_performance_full_suspension_count) || + /* Check for errors. */ + if ((status != TX_SUCCESS) || (messages_sent != queue_0.tx_queue_performance_messages_sent_count) || (messages_received != queue_0.tx_queue_performance_messages_received_count) || + (empty_suspensions != queue_0.tx_queue_performance_empty_suspension_count) || (full_suspensions != queue_0.tx_queue_performance_full_suspension_count) || (full_errors != queue_0.tx_queue_performance_full_error_count) || (timeouts != queue_0.tx_queue_performance_timeout_count)) { @@ -441,9 +441,9 @@ ULONG timeouts; status = tx_queue_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_queue_performance_system_info_get(&messages_sent, &messages_received, &empty_suspensions, &full_suspensions, &full_errors, &timeouts); - /* Check for errors. */ - if ((status != TX_SUCCESS) || (messages_sent != _tx_queue_performance_messages_sent_count) || (messages_received != _tx_queue_performance__messages_received_count) || - (empty_suspensions != _tx_queue_performance_empty_suspension_count) || (full_suspensions != _tx_queue_performance_full_suspension_count) || + /* Check for errors. */ + if ((status != TX_SUCCESS) || (messages_sent != _tx_queue_performance_messages_sent_count) || (messages_received != _tx_queue_performance__messages_received_count) || + (empty_suspensions != _tx_queue_performance_empty_suspension_count) || (full_suspensions != _tx_queue_performance_full_suspension_count) || (full_errors != _tx_queue_performance_full_error_count) || (timeouts != _tx_queue_performance_timeout_count)) { @@ -457,7 +457,7 @@ ULONG timeouts; /* Get performance information. */ status = tx_queue_performance_info_get(&queue_0, &messages_sent, &messages_received, &empty_suspensions, &full_suspensions, &full_errors, &timeouts); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -469,7 +469,7 @@ ULONG timeouts; /* Get performance information. */ status = tx_queue_performance_info_get(TX_NULL, &messages_sent, &messages_received, &empty_suspensions, &full_suspensions, &full_errors, &timeouts); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -481,7 +481,7 @@ ULONG timeouts; /* Get performance information. */ status = tx_queue_performance_info_get(TX_NULL, TX_NULL, &messages_received, &empty_suspensions, &full_suspensions, &full_errors, &timeouts); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -493,7 +493,7 @@ ULONG timeouts; /* Get performance information. */ status = tx_queue_performance_info_get(TX_NULL, TX_NULL, TX_NULL, &empty_suspensions, &full_suspensions, &full_errors, &timeouts); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -505,7 +505,7 @@ ULONG timeouts; /* Get performance information. */ status = tx_queue_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, &full_suspensions, &full_errors, &timeouts); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -517,7 +517,7 @@ ULONG timeouts; /* Get performance information. */ status = tx_queue_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &full_errors, &timeouts); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -529,7 +529,7 @@ ULONG timeouts; /* Get performance information. */ status = tx_queue_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &timeouts); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -541,7 +541,7 @@ ULONG timeouts; /* Get performance information. */ status = tx_queue_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -553,7 +553,7 @@ ULONG timeouts; /* Get system performance information. */ status = tx_queue_performance_system_info_get(&messages_sent, &messages_received, &empty_suspensions, &full_suspensions, &full_errors, &timeouts); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -565,7 +565,7 @@ ULONG timeouts; /* Get system performance information. */ status = tx_queue_performance_system_info_get(TX_NULL, &messages_received, &empty_suspensions, &full_suspensions, &full_errors, &timeouts); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -577,7 +577,7 @@ ULONG timeouts; /* Get system performance information. */ status = tx_queue_performance_system_info_get(TX_NULL, TX_NULL, &empty_suspensions, &full_suspensions, &full_errors, &timeouts); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -589,7 +589,7 @@ ULONG timeouts; /* Get system performance information. */ status = tx_queue_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, &full_suspensions, &full_errors, &timeouts); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -601,7 +601,7 @@ ULONG timeouts; /* Get system performance information. */ status = tx_queue_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, &full_errors, &timeouts); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -613,7 +613,7 @@ ULONG timeouts; /* Get system performance information. */ status = tx_queue_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &timeouts); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { @@ -625,7 +625,7 @@ ULONG timeouts; /* Get system performance information. */ status = tx_queue_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); - /* Should be an error! */ + /* Should be an error! */ if (status != TX_FEATURE_NOT_ENABLED) { diff --git a/test/tx/regression/threadx_queue_prioritize.c b/test/tx/regression/threadx_queue_prioritize.c index 7a9d2b44..53c19275 100644 --- a/test/tx/regression/threadx_queue_prioritize.c +++ b/test/tx/regression/threadx_queue_prioritize.c @@ -81,12 +81,12 @@ static void test_isr(void) } else { - + /* Abort the wait of thread 5. */ tx_thread_wait_abort(&thread_5); /* End the ISR processing. */ - test_status = 2; + test_status = 2; test_isr_dispatch = TX_NULL; } } @@ -112,8 +112,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -125,8 +125,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -138,8 +138,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -152,8 +152,8 @@ CHAR *pointer; } - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 3, 3, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -165,8 +165,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 4, 4, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -178,8 +178,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, TEST_STACK_SIZE_PRINTF, 5, 5, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -191,8 +191,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, + pointer, TEST_STACK_SIZE_PRINTF, 6, 6, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -220,7 +220,7 @@ CHAR *pointer; status = tx_queue_send_notify(&queue_0, queue_notify); #ifndef TX_DISABLE_NOTIFY_CALLBACKS - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -335,7 +335,7 @@ UINT status; printf("ERROR #15\n"); test_control_return(1); } - + /* At this point we are going to get more than 2 threads suspended. */ tx_thread_resume(&thread_1); tx_thread_resume(&thread_2); @@ -343,7 +343,7 @@ UINT status; tx_thread_resume(&thread_4); tx_thread_resume(&thread_5); tx_thread_resume(&thread_6); - + /* Prioritize the queue suspension list. */ status = tx_queue_prioritize(&queue_0); @@ -355,10 +355,10 @@ UINT status; printf("ERROR #16\n"); test_control_return(1); } - + /* Now loop to test the interrupt of the prioritize loop logic. */ test_status = 1; - test_isr_dispatch = test_isr; + test_isr_dispatch = test_isr; do { @@ -375,10 +375,10 @@ UINT status; } } while (test_status == 1); - + /* Now determine if thread 4 is at the front of the list... It should be! */ if (queue_0.tx_queue_suspension_list != &thread_4) - { + { /* Queue error. */ printf("ERROR #18\n"); diff --git a/test/tx/regression/threadx_queue_suspension_timeout_test.c b/test/tx/regression/threadx_queue_suspension_timeout_test.c index a3c390ed..92dca991 100644 --- a/test/tx/regression/threadx_queue_suspension_timeout_test.c +++ b/test/tx/regression/threadx_queue_suspension_timeout_test.c @@ -54,8 +54,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -67,8 +67,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -80,8 +80,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -120,7 +120,7 @@ CHAR *pointer; status = tx_queue_send_notify(&queue_0, queue_notify); #ifndef TX_DISABLE_NOTIFY_CALLBACKS - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -184,7 +184,7 @@ ULONG source_message[2] = {0x12345678, 0}; printf("ERROR #9a\n"); test_control_return(1); } - + /* Send message that should cause this thread to suspend. The timeout should cause it to resume with a TX_QUEUE_FULL error code. */ status = tx_queue_send(&queue_0, &source_message[0], 32); @@ -217,7 +217,7 @@ ULONG dest_message[2]; { - /* Receive message from empty queue with suspension and timeout. + /* Receive message from empty queue with suspension and timeout. We should wakeup after the timeout expires with an empty status. */ status = tx_queue_receive(&queue_1, &dest_message[0], 20); @@ -241,7 +241,7 @@ ULONG dest_message[2]; { - /* Receive message from empty queue with suspension and timeout. + /* Receive message from empty queue with suspension and timeout. We should wakeup after the timeout expires with an empty status. */ status = tx_queue_receive(&queue_1, &dest_message[0], 20); diff --git a/test/tx/regression/threadx_queue_thread_terminate_test.c b/test/tx/regression/threadx_queue_thread_terminate_test.c index d0834704..97d8a569 100644 --- a/test/tx/regression/threadx_queue_thread_terminate_test.c +++ b/test/tx/regression/threadx_queue_thread_terminate_test.c @@ -48,8 +48,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -61,8 +61,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -85,10 +85,10 @@ CHAR *pointer; printf("Running Queue Thread Terminate Test................................. ERROR #3\n"); test_control_return(1); } - + /* Setup queue send notification. */ status = tx_queue_send_notify(&queue_0, queue_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check for status. */ diff --git a/test/tx/regression/threadx_semaphore_basic_test.c b/test/tx/regression/threadx_semaphore_basic_test.c index f554257d..33ee3257 100644 --- a/test/tx/regression/threadx_semaphore_basic_test.c +++ b/test/tx/regression/threadx_semaphore_basic_test.c @@ -72,7 +72,7 @@ UINT status; /* Determine if calling semaphore create from initialization was successful. */ if (test_semaphore_from_init != TX_SUCCESS) { - + /* Error! */ error++; } @@ -182,13 +182,13 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -240,11 +240,11 @@ UINT status; semaphore_memory.second = 0x55667788; semaphore_memory.next_to_last = 0x99aabbcc; semaphore_memory.last = 0xddeeff00; - + /* Create the semaphore. */ status = tx_semaphore_create(&semaphore_memory.semaphore, "semaphore memory", 0); tx_semaphore_delete(&semaphore_memory.semaphore); - + /* Check for status. */ if ((status != TX_SUCCESS) || (semaphore_memory.first != 0x11223344) || @@ -463,7 +463,7 @@ UINT status; /* Attempt to get from semaphore with an instance. Should be successful. */ status = tx_semaphore_get(&semaphore_1, TX_NO_WAIT); - + /* Check status. */ if (status != TX_SUCCESS) { @@ -496,7 +496,7 @@ UINT status; /* Test for error. */ if ((error) || (timer_executed != 1) || (isr_executed != 1)) { - + /* Semaphore error. */ printf("ERROR #22\n"); test_control_return(1); @@ -539,7 +539,7 @@ static void thread_1_entry(ULONG thread_input) while(1) { - + tx_thread_relinquish(); } } \ No newline at end of file diff --git a/test/tx/regression/threadx_semaphore_ceiling_put_test.c b/test/tx/regression/threadx_semaphore_ceiling_put_test.c index 5364d2d9..7d4f5832 100644 --- a/test/tx/regression/threadx_semaphore_ceiling_put_test.c +++ b/test/tx/regression/threadx_semaphore_ceiling_put_test.c @@ -55,8 +55,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -68,8 +68,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -81,8 +81,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -108,7 +108,7 @@ CHAR *pointer; /* Setup the semaphore notify callback. */ status = tx_semaphore_put_notify(&semaphore_0, put_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check for status. */ @@ -205,15 +205,15 @@ UINT status; /* At this point, we need to resume thread 2 and relinquish in order to get that thread suspended on the semaphore as well. */ tx_thread_resume(&thread_2); - tx_thread_relinquish(); - + tx_thread_relinquish(); + /* Perform 2 semaphore put operations to resume both threads. */ status = tx_semaphore_ceiling_put(&semaphore_0, 2); status += tx_semaphore_ceiling_put(&semaphore_0, 2); /* Let both threads run again. */ - tx_thread_relinquish(); - + tx_thread_relinquish(); + /* Check the status and the run counter of the other thread. */ if ((status != TX_SUCCESS) || (thread_1_counter != 5) || (thread_2_counter != 3)) { @@ -222,7 +222,7 @@ UINT status; printf("ERROR #11\n"); test_control_return(1); } - + /* Now turn off the semaphore notification. */ status = tx_semaphore_put_notify(&semaphore_0, TX_NULL); @@ -234,7 +234,7 @@ UINT status; /* Put a semaphore on a semaphore that does not have suspension. */ status += tx_semaphore_ceiling_put(&semaphore_1, 2); - + /* Repeat the semaphore ceiling put without notification process! */ /* Place an instance on the semaphore, this should resume the other thread @@ -265,15 +265,15 @@ UINT status; /* At this point, we need to resume thread 2 and relinquish in order to get that thread suspended on the semaphore as well. */ tx_thread_resume(&thread_2); - tx_thread_relinquish(); - + tx_thread_relinquish(); + /* Perform 2 semaphore put operations to resume both threads. */ status = tx_semaphore_ceiling_put(&semaphore_0, 2); status += tx_semaphore_ceiling_put(&semaphore_0, 2); /* Let both threads run again. */ - tx_thread_relinquish(); - + tx_thread_relinquish(); + /* Check the status and the run counter of the other thread. */ if ((status != TX_SUCCESS) || (thread_1_counter != 9) || (thread_2_counter != 5)) { @@ -281,7 +281,7 @@ UINT status; /* Semaphore error. */ printf("ERROR #11a\n"); test_control_return(1); - } + } else { @@ -299,7 +299,7 @@ UINT status; while(1) { - + /* Increment thread run counter. */ thread_1_counter++; @@ -320,7 +320,7 @@ UINT status; while(1) { - + /* Increment thread run counter. */ thread_2_counter++; diff --git a/test/tx/regression/threadx_semaphore_delete_test.c b/test/tx/regression/threadx_semaphore_delete_test.c index f18d31dc..2c9bc1aa 100644 --- a/test/tx/regression/threadx_semaphore_delete_test.c +++ b/test/tx/regression/threadx_semaphore_delete_test.c @@ -54,8 +54,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -67,8 +67,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -80,8 +80,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -106,7 +106,7 @@ CHAR *pointer; /* Setup the semaphore notify callback. */ status = tx_semaphore_put_notify(&semaphore_0, put_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check for status. */ diff --git a/test/tx/regression/threadx_semaphore_information_test.c b/test/tx/regression/threadx_semaphore_information_test.c index a8f6d242..d2e9bd57 100644 --- a/test/tx/regression/threadx_semaphore_information_test.c +++ b/test/tx/regression/threadx_semaphore_information_test.c @@ -45,8 +45,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -185,7 +185,7 @@ ULONG timeouts; /* Attempt to get from semaphore with an instance. Should be successful. */ status = tx_semaphore_get(&semaphore_1, TX_NO_WAIT); - + /* Check status. */ if (status != TX_SUCCESS) { @@ -198,10 +198,10 @@ ULONG timeouts; /* Get semaphore information. */ status = tx_semaphore_info_get(&semaphore_0, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_semaphore_info_get(&semaphore_0, &name, ¤t_value, &first_suspended, &suspended_count, &next_semaphore); - + /* Check status. */ - if ((status != TX_SUCCESS) || (current_value != semaphore_0.tx_semaphore_count) || - (first_suspended != semaphore_0.tx_semaphore_suspension_list) || (suspended_count != semaphore_0.tx_semaphore_suspended_count) || + if ((status != TX_SUCCESS) || (current_value != semaphore_0.tx_semaphore_count) || + (first_suspended != semaphore_0.tx_semaphore_suspension_list) || (suspended_count != semaphore_0.tx_semaphore_suspended_count) || (next_semaphore != semaphore_0.tx_semaphore_created_next)) { @@ -227,9 +227,9 @@ ULONG timeouts; /* Get semaphore performance information. */ status = tx_semaphore_performance_info_get(&semaphore_0, TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_semaphore_performance_info_get(&semaphore_0, &puts, &gets, &suspensions, &timeouts); - + /* Check status. */ - if ((status != TX_SUCCESS) || (puts != semaphore_0.tx_semaphore_performance_put_count) || (gets != semaphore_0.tx_semaphore_performance_get_count) || + if ((status != TX_SUCCESS) || (puts != semaphore_0.tx_semaphore_performance_put_count) || (gets != semaphore_0.tx_semaphore_performance_get_count) || (suspensions != semaphore_0.tx_semaphore_performance_suspension_count) || (timeouts != semaphore_0.tx_semaphore_performance_timeout_count)) { @@ -237,13 +237,13 @@ ULONG timeouts; printf("ERROR #13\n"); test_control_return(1); } - + /* Get semaphore system performance information. */ status = tx_semaphore_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_semaphore_performance_system_info_get(&puts, &gets, &suspensions, &timeouts); - + /* Check status. */ - if ((status != TX_SUCCESS) || (puts != _tx_semaphore_performance_put_count) || (gets != _tx_semaphore_performance_get_count) || + if ((status != TX_SUCCESS) || (puts != _tx_semaphore_performance_put_count) || (gets != _tx_semaphore_performance_get_count) || (suspensions != _tx_semaphore_performance_suspension_count) || (timeouts != _tx_semaphore_performance_timeout_count)) { diff --git a/test/tx/regression/threadx_semaphore_non_preemption_test.c b/test/tx/regression/threadx_semaphore_non_preemption_test.c index 40219546..c075b16c 100644 --- a/test/tx/regression/threadx_semaphore_non_preemption_test.c +++ b/test/tx/regression/threadx_semaphore_non_preemption_test.c @@ -55,8 +55,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -68,8 +68,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -81,8 +81,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -107,7 +107,7 @@ CHAR *pointer; /* Setup the semaphore notify callback. */ status = tx_semaphore_put_notify(&semaphore_0, put_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check for status. */ @@ -201,15 +201,15 @@ UINT status; /* At this point, we need to resume thread 2 and relinquish in order to get that thread suspended on the semaphore as well. */ tx_thread_resume(&thread_2); - tx_thread_relinquish(); - + tx_thread_relinquish(); + /* Perform 2 semaphore put operations to resume both threads. */ status = tx_semaphore_put(&semaphore_0); status += tx_semaphore_put(&semaphore_0); /* Let both threads run again. */ - tx_thread_relinquish(); - + tx_thread_relinquish(); + /* Check the status and the run counter of the other thread. */ if ((status != TX_SUCCESS) || (thread_1_counter != 5) || (thread_2_counter != 3)) { @@ -235,7 +235,7 @@ UINT status; while(1) { - + /* Increment thread run counter. */ thread_1_counter++; @@ -256,7 +256,7 @@ UINT status; while(1) { - + /* Increment thread run counter. */ thread_2_counter++; diff --git a/test/tx/regression/threadx_semaphore_preemption_test.c b/test/tx/regression/threadx_semaphore_preemption_test.c index 347042bc..f14193a2 100644 --- a/test/tx/regression/threadx_semaphore_preemption_test.c +++ b/test/tx/regression/threadx_semaphore_preemption_test.c @@ -51,8 +51,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -64,8 +64,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -90,7 +90,7 @@ CHAR *pointer; /* Setup the semaphore notify callback. */ status = tx_semaphore_put_notify(&semaphore_0, put_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check for status. */ diff --git a/test/tx/regression/threadx_semaphore_prioritize.c b/test/tx/regression/threadx_semaphore_prioritize.c index 79622667..6bee4656 100644 --- a/test/tx/regression/threadx_semaphore_prioritize.c +++ b/test/tx/regression/threadx_semaphore_prioritize.c @@ -75,12 +75,12 @@ static void test_isr(void) } else { - + /* Abort the wait of thread 5. */ tx_thread_wait_abort(&thread_5); /* End the ISR processing. */ - test_status = 2; + test_status = 2; test_isr_dispatch = TX_NULL; } } @@ -113,8 +113,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -126,8 +126,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -139,8 +139,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -152,8 +152,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 3, 3, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -165,8 +165,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 4, 4, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -178,8 +178,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, TEST_STACK_SIZE_PRINTF, 5, 5, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -191,8 +191,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_6, "thread 6", thread_6_entry, 6, + pointer, TEST_STACK_SIZE_PRINTF, 6, 6, 100, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -206,7 +206,7 @@ CHAR *pointer; /* Create the semaphore with no instances. */ status = tx_semaphore_create(&semaphore_0, "semaphore 0", 0); - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -217,7 +217,7 @@ CHAR *pointer; /* Setup the semaphore notify callback. */ status = tx_semaphore_put_notify(&semaphore_0, put_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check for status. */ @@ -334,7 +334,7 @@ UINT status; printf("ERROR #15a\n"); test_control_return(1); } - + /* At this point we are going to get more than 2 threads suspended. */ tx_thread_resume(&thread_1); tx_thread_resume(&thread_2); @@ -345,7 +345,7 @@ UINT status; /* Prioritize the semaphore suspension list. */ status = tx_semaphore_prioritize(&semaphore_0); - + /* Check status and make sure thread 3 is now at the front of the suspension list. */ if ((status != TX_SUCCESS) || (semaphore_0.tx_semaphore_suspension_list != &thread_3)) { @@ -354,10 +354,10 @@ UINT status; printf("ERROR #16\n"); test_control_return(1); } - + /* Now loop to test the interrupt of the prioritize loop logic. */ test_status = 1; - test_isr_dispatch = test_isr; + test_isr_dispatch = test_isr; do { diff --git a/test/tx/regression/threadx_semaphore_thread_terminate_test.c b/test/tx/regression/threadx_semaphore_thread_terminate_test.c index b8beeff2..a15f5963 100644 --- a/test/tx/regression/threadx_semaphore_thread_terminate_test.c +++ b/test/tx/regression/threadx_semaphore_thread_terminate_test.c @@ -55,8 +55,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -68,8 +68,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -81,8 +81,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -104,10 +104,10 @@ CHAR *pointer; printf("Running Semaphore Thread Terminate Test............................. ERROR #4\n"); test_control_return(1); } - + /* Setup the semaphore notify callback. */ status = tx_semaphore_put_notify(&semaphore_0, put_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check for status. */ diff --git a/test/tx/regression/threadx_semaphore_timeout_test.c b/test/tx/regression/threadx_semaphore_timeout_test.c index ec16a7c0..96585337 100644 --- a/test/tx/regression/threadx_semaphore_timeout_test.c +++ b/test/tx/regression/threadx_semaphore_timeout_test.c @@ -45,8 +45,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -68,10 +68,10 @@ CHAR *pointer; printf("Running Semaphore Suspension Timeout Test........................... ERROR #2\n"); test_control_return(1); } - + /* Setup the semaphore notify callback. */ status = tx_semaphore_put_notify(&semaphore_0, put_notify); - + #ifndef TX_DISABLE_NOTIFY_CALLBACKS /* Check for status. */ diff --git a/test/tx/regression/threadx_thread_basic_execution_test.c b/test/tx/regression/threadx_thread_basic_execution_test.c index 7a5ae864..9949eac8 100644 --- a/test/tx/regression/threadx_thread_basic_execution_test.c +++ b/test/tx/regression/threadx_thread_basic_execution_test.c @@ -1,5 +1,5 @@ -/* This test is designed to see if one thread can be created and executed. - It thread_0_entry is hit, then the thread was successfully scheduled. +/* This test is designed to see if one thread can be created and executed. + It thread_0_entry is hit, then the thread was successfully scheduled. On success, thread_0_counter gets incremented. */ #include @@ -56,10 +56,10 @@ static unsigned long isr_executed = 0; static void thread_0_entry(ULONG task_input); -UINT _txe_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr, +UINT _txe_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr, VOID (*entry_function)(ULONG), ULONG entry_input, - VOID *stack_start, ULONG stack_size, - UINT priority, UINT preempt_threshold, + VOID *stack_start, ULONG stack_size, + UINT priority, UINT preempt_threshold, ULONG time_slice, UINT auto_start, UINT thread_control_block_size); #ifndef TX_INLINE_THREAD_RESUME_SUSPEND @@ -92,8 +92,8 @@ CHAR *pointer; /* Attempt to create a thread from a timer. */ pointer = (CHAR *) 0x3000; - status = tx_thread_create(&thread_1, "thread 1", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_DONT_START); /* Check for status. */ @@ -137,8 +137,8 @@ ULONG old_time_slice; /* Attempt to create a thread from a timer. */ pointer = (CHAR *) not_used_stack; - status = tx_thread_create(&thread_1, "thread 1", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_DONT_START); /* Check for status. */ @@ -151,7 +151,7 @@ ULONG old_time_slice; /* Attempt to delete a thread from an ISR. */ status = tx_thread_delete(&thread_0); - + /* Check for status. */ if (status != TX_CALLER_ERROR) { @@ -162,7 +162,7 @@ ULONG old_time_slice; /* Attempt to change preemption from an ISR. */ status = tx_thread_preemption_change(&thread_0, 1, &old_value); - + /* Check for status. */ if (status != TX_CALLER_ERROR) { @@ -173,7 +173,7 @@ ULONG old_time_slice; /* Attempt to change priority from an ISR. */ status = tx_thread_priority_change(&thread_0, 1, &old_value); - + /* Check for status. */ if (status != TX_CALLER_ERROR) { @@ -235,7 +235,7 @@ ULONG old_time_slice; static void test_isr1(void) { - + UINT status; TX_THREAD *current_thread; @@ -247,31 +247,31 @@ TX_THREAD *current_thread; /* Pickup the current thread. */ current_thread = tx_thread_identify(); - + /* Determine if the condition is present. */ if ((current_thread == &thread_4) && (_tx_thread_preempt_disable) && (thread_4.tx_thread_state == TX_READY)) { - /* Suspend the currently running thread 4 with the preemption-threshold flag set to ensure tx_thread_suspend from an ISR works + /* Suspend the currently running thread 4 with the preemption-threshold flag set to ensure tx_thread_suspend from an ISR works in this case. */ status = tx_thread_suspend(&thread_4); - + /* Check for error. */ if (status != TX_SUCCESS) { - + /* Set error flag. */ error++; } /* Resume thread 4. */ tx_thread_resume(&thread_4); - + /* Indicate the test case has been found. */ test_case_found = TX_TRUE; - } + } } - + #endif #endif @@ -299,30 +299,30 @@ TX_THREAD fake_thread; /* Setup a pointer. */ pointer = (CHAR *) first_unused_memory; - + /* Adjust it forward just to make sure there is some space for the test below. */ pointer = pointer + 200; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - + #ifndef TX_INLINE_THREAD_RESUME_SUSPEND #ifndef TX_NOT_INTERRUPTABLE - status += tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - + #endif -#endif - - +#endif + + /* Check for status. */ if (status != TX_SUCCESS) { @@ -331,7 +331,7 @@ TX_THREAD fake_thread; test_control_return(1); } - + #ifndef TX_NOT_INTERRUPTABLE /* Now setup a fake thread to generate the other NULL pointer test in the cleanup routines. */ @@ -370,7 +370,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Setup test thread to make sure _tx_thread_wait_abort can handle a NULL cleanup. */ test_thread.tx_thread_state = TX_IO_DRIVER; - test_thread.tx_thread_suspend_cleanup = TX_NULL; + test_thread.tx_thread_suspend_cleanup = TX_NULL; test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; test_thread.tx_thread_suspending = TX_TRUE; test_thread.tx_thread_delayed_suspend = TX_TRUE; @@ -382,7 +382,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Setup test thread to make sure _tx_thread_timeout can handle a NULL cleanup. */ test_thread.tx_thread_state = TX_IO_DRIVER; - test_thread.tx_thread_suspend_cleanup = TX_NULL; + test_thread.tx_thread_suspend_cleanup = TX_NULL; test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; test_thread.tx_thread_suspending = TX_TRUE; test_thread.tx_thread_delayed_suspend = TX_TRUE; @@ -392,12 +392,12 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); temp_mutex_release = _tx_thread_mutex_release; _tx_thread_mutex_release = TX_NULL; test_thread.tx_thread_state = TX_TERMINATED; - test_thread.tx_thread_suspend_cleanup = TX_NULL; + test_thread.tx_thread_suspend_cleanup = TX_NULL; test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; test_thread.tx_thread_suspending = TX_TRUE; test_thread.tx_thread_timer.tx_timer_internal_list_head = TX_NULL; test_thread.tx_thread_delayed_suspend = TX_TRUE; - status = _tx_thread_terminate(&test_thread); + status = _tx_thread_terminate(&test_thread); _tx_thread_mutex_release = temp_mutex_release; /* Recover Mutex release pointer. */ /* Perform thread memory test. */ @@ -407,10 +407,10 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); thread_memory.second_middle= 0x61718191; thread_memory.next_to_last = 0x99aabbcc; thread_memory.last = 0xddeeff00; - + /* Create the thread. */ - status += tx_thread_create(&thread_memory.thread_block, "thread memory", thread_0_entry, 1, - &thread_memory.stack[0], (2048*sizeof(ULONG))/sizeof(ULONG), + status += tx_thread_create(&thread_memory.thread_block, "thread memory", thread_0_entry, 1, + &thread_memory.stack[0], (2048*sizeof(ULONG))/sizeof(ULONG), 16, 16, TX_NO_TIME_SLICE, TX_DONT_START); tx_thread_delete(&thread_memory.thread_block); @@ -423,7 +423,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); (thread_memory.next_to_last != 0x99aabbcc) || (thread_memory.last != 0xddeeff00)) { - + /* Memory overwrite error. */ printf("ERROR #2\n"); test_control_return(1); @@ -435,8 +435,8 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to create a thread with a null pointer. */ pointer = (CHAR *) not_used_stack; - status = tx_thread_create(TX_NULL, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(TX_NULL, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); /* Check for status. */ @@ -449,8 +449,8 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to create a thread with a bad control block size. */ pointer = (CHAR *) not_used_stack; - status = _txe_thread_create(&thread_3, "thread 3", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = _txe_thread_create(&thread_3, "thread 3", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START, (sizeof(TX_THREAD)+1)); /* Check for status. */ @@ -463,8 +463,8 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to create a thread with a NULL entry function. */ pointer = (CHAR *) not_used_stack; - status = tx_thread_create(&thread_3, "thread 3", TX_NULL, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", TX_NULL, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); /* Check for status. */ @@ -477,8 +477,8 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to create a thread that has already been created. */ pointer = (CHAR *) not_used_stack; - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); /* Check for status. */ @@ -490,8 +490,8 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); } /* Attempt to create a thread with an overlapping stack. */ - status = tx_thread_create(&thread_1, "thread 1", thread_0_entry, 1, - thread_0.tx_thread_stack_ptr, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_0_entry, 1, + thread_0.tx_thread_stack_ptr, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); /* Check for status. */ @@ -505,8 +505,8 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to create a thread with another variation of an overlapping stack. */ pointer = thread_0.tx_thread_stack_start; pointer = pointer - 20; - status = tx_thread_create(&thread_1, "thread 1", TX_NULL, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", TX_NULL, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); /* Check for status. */ @@ -519,8 +519,8 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to create a thread an extra small stack. */ pointer = (CHAR *) not_used_stack; - status = tx_thread_create(&thread_1, "thread 1", thread_0_entry, 1, - pointer, 1, + status = tx_thread_create(&thread_1, "thread 1", thread_0_entry, 1, + pointer, 1, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); /* Check for status. */ @@ -533,8 +533,8 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to create a thread with an invalid thread priority. */ pointer = (CHAR *) not_used_stack; - status = tx_thread_create(&thread_1, "thread 1", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 5000, 5000, TX_NO_TIME_SLICE, TX_AUTO_START); /* Check for status. */ @@ -547,8 +547,8 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to create a thread with an invalid preemption-threshold. */ pointer = (CHAR *) not_used_stack; - status = tx_thread_create(&thread_1, "thread 1", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 17, TX_NO_TIME_SLICE, TX_AUTO_START); /* Check for status. */ @@ -561,8 +561,8 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to create a thread with an invalid auto start. */ pointer = (CHAR *) not_used_stack; - status = tx_thread_create(&thread_1, "thread 1", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, 3456); /* Check for status. */ @@ -598,7 +598,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to register a entry/exit callback on a non-thread. */ status = tx_thread_entry_exit_notify(TX_NULL, TX_NULL); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -610,7 +610,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to register a entry/exit callback on a non-created thread. */ thread_2.tx_thread_id = 0; status = tx_thread_entry_exit_notify(&thread_2, TX_NULL); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -621,7 +621,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to get info on a non-thread. */ status = tx_thread_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -633,7 +633,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to get info on a non-created thread. */ thread_2.tx_thread_id = 0; status = tx_thread_info_get(&thread_2, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -644,7 +644,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to change preemption of a non-thread. */ status = tx_thread_preemption_change(TX_NULL, 1, TX_NULL); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -652,11 +652,11 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); printf("ERROR #19\n"); test_control_return(1); } - + /* Attempt to change preemption of a non-created thread. */ thread_2.tx_thread_id = 0; status = tx_thread_preemption_change(&thread_2, 1, TX_NULL); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -667,7 +667,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to change preemption with a NULL return value. */ status = tx_thread_preemption_change(&thread_0, 1, TX_NULL); - + /* Check for status. */ if (status != TX_PTR_ERROR) { @@ -675,10 +675,10 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); printf("ERROR #21\n"); test_control_return(1); } - + /* Attempt to change preemption with a bad threshold value. */ status = tx_thread_preemption_change(&thread_0, 17, &old_value); - + /* Check for status. */ if (status != TX_THRESH_ERROR) { @@ -690,7 +690,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to change priority of a non-thread. */ status = tx_thread_priority_change(TX_NULL, 1, TX_NULL); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -698,11 +698,11 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); printf("ERROR #23\n"); test_control_return(1); } - + /* Attempt to change priority of a non-created thread. */ thread_2.tx_thread_id = 0; status = tx_thread_priority_change(&thread_2, 1, TX_NULL); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -713,7 +713,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt to change priority with a NULL return value. */ status = tx_thread_priority_change(&thread_0, 1, TX_NULL); - + /* Check for status. */ if (status != TX_PTR_ERROR) { @@ -721,10 +721,10 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); printf("ERROR #25\n"); test_control_return(1); } - + /* Attempt to change priority with a bad priority value. */ status = tx_thread_priority_change(&thread_0, 2046, &old_value); - + /* Check for status. */ if (status != TX_PRIORITY_ERROR) { @@ -769,7 +769,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt a thread resume with a NULL pointer. */ status = tx_thread_resume(TX_NULL); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -777,11 +777,11 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); printf("ERROR #30\n"); test_control_return(1); } - + /* Attempt a thread resume on a non-created thread. */ thread_2.tx_thread_id = 0; status = tx_thread_resume(&thread_2); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -792,7 +792,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt a thread suspend with a NULL pointer. */ status = tx_thread_suspend(TX_NULL); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -800,11 +800,11 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); printf("ERROR #32\n"); test_control_return(1); } - + /* Attempt a thread suspend on a non-created thread. */ thread_2.tx_thread_id = 0; status = tx_thread_suspend(&thread_2); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -815,7 +815,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt a thread termiante with a NULL pointer. */ status = tx_thread_terminate(TX_NULL); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -823,11 +823,11 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); printf("ERROR #34\n"); test_control_return(1); } - + /* Attempt a thread terminate on a non-created thread. */ thread_2.tx_thread_id = 0; status = tx_thread_terminate(&thread_2); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -838,7 +838,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt a thread time-slice chagne with a NULL pointer. */ status = tx_thread_time_slice_change(TX_NULL, 1, &old_time_slice); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -846,11 +846,11 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); printf("ERROR #36\n"); test_control_return(1); } - + /* Attempt a thread time-slice change on a non-created thread. */ thread_2.tx_thread_id = 0; status = tx_thread_time_slice_change(&thread_2, 1, &old_time_slice); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -861,7 +861,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt a thread time-slice change with a null return pointer. */ status = tx_thread_time_slice_change(&thread_0, 1, TX_NULL); - + /* Check for status. */ if (status != TX_PTR_ERROR) { @@ -872,7 +872,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Attempt a thread wait abort with a NULL pointer. */ status = tx_thread_wait_abort(TX_NULL); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -880,11 +880,11 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); printf("ERROR #39\n"); test_control_return(1); } - + /* Attempt a thread wait abort on a non-created thread. */ thread_2.tx_thread_id = 0; status = tx_thread_wait_abort(&thread_2); - + /* Check for status. */ if (status != TX_THREAD_ERROR) { @@ -908,7 +908,7 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* Test for error. */ if ((error) || (timer_executed != 1) || (isr_executed != 1)) { - + /* Thread error. */ printf("ERROR #41\n"); test_control_return(1); @@ -921,25 +921,25 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); /* At this point setup the ISR. */ test_isr_dispatch = test_isr1; - + /* Resume thread 4. */ - tx_thread_resume(&thread_4); - + tx_thread_resume(&thread_4); + /* Clear the ISR. */ - test_isr_dispatch = TX_NULL; - + test_isr_dispatch = TX_NULL; + /* Now check for an error. */ if ((error) || (test_case_found == TX_FALSE)) { - + /* Basic execution error. */ printf("ERROR #42\n"); test_control_return(1); } - + #endif -#endif - +#endif + /* Successful test. */ printf("SUCCESS!\n"); test_control_return(0); @@ -952,13 +952,13 @@ VOID (*temp_mutex_release)(TX_THREAD *thread_ptr); static void thread_4_entry(ULONG thread_input) { -TX_INTERRUPT_SAVE_AREA +TX_INTERRUPT_SAVE_AREA /* Loop until we achieve as suspend request while inside of the tx_thread_resume API. */ while (test_case_found == TX_FALSE) { - + /* Temporarily disable preemption for the test. */ TX_DISABLE _tx_thread_preempt_disable++; @@ -966,7 +966,7 @@ TX_INTERRUPT_SAVE_AREA /* Increment the run counter for this test. */ thread_4_counter++; - + TX_DISABLE _tx_thread_preempt_disable--; TX_RESTORE @@ -974,6 +974,6 @@ TX_INTERRUPT_SAVE_AREA } #endif -#endif +#endif diff --git a/test/tx/regression/threadx_thread_basic_time_slice_test.c b/test/tx/regression/threadx_thread_basic_time_slice_test.c index 9da8350c..7c83a715 100644 --- a/test/tx/regression/threadx_thread_basic_time_slice_test.c +++ b/test/tx/regression/threadx_thread_basic_time_slice_test.c @@ -1,4 +1,4 @@ -/* This test is designed to see if a thread can be created with a time-slice. +/* This test is designed to see if a thread can be created with a time-slice. No time-slice occurs, only the processing to check for time-slicing. */ #include @@ -30,8 +30,8 @@ UINT status; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - first_unused_memory, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + first_unused_memory, TEST_STACK_SIZE_PRINTF, 16, 16, 1, TX_AUTO_START); /* Check for status. */ diff --git a/test/tx/regression/threadx_thread_completed_test.c b/test/tx/regression/threadx_thread_completed_test.c index 068058d0..adaf1683 100644 --- a/test/tx/regression/threadx_thread_completed_test.c +++ b/test/tx/regression/threadx_thread_completed_test.c @@ -1,5 +1,5 @@ -/* This test is designed to see if one thread can be created, executed, and - return to the thread shell function. The thread shell function places +/* This test is designed to see if one thread can be created, executed, and + return to the thread shell function. The thread shell function places the thread in a finished state. */ #include @@ -36,7 +36,7 @@ static void entry_exit_notify(TX_THREAD *thread_ptr, UINT type) /* Check for the appropriate thread. */ if (thread_ptr != &thread_0) return; - + /* Check for type. */ if (type == TX_THREAD_ENTRY) thread_0_enter++; @@ -64,8 +64,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -94,8 +94,8 @@ CHAR *pointer; #endif - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -107,8 +107,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -154,11 +154,11 @@ UINT status; /* Attempt to delete thread 2, which is in the wrong stat for deleting. */ status = tx_thread_delete(&thread_2); - + /* Check for the proper status. */ if (status != TX_DELETE_ERROR) { - + /* Thread delete error. */ printf("ERROR #5\n"); test_control_return(1); @@ -166,11 +166,11 @@ UINT status; /* Attempt to suspend thread 0, which is in a completed state. */ status = tx_thread_suspend(&thread_0); - + /* Check for the correct status. */ if (status != TX_SUSPEND_ERROR) { - + /* Thread suspend error. */ printf("ERROR #6\n"); test_control_return(1); @@ -178,11 +178,11 @@ UINT status; /* Attempt to delete thread 0. */ status = tx_thread_delete(&thread_0); - + /* Check for the proper status. */ if (status != TX_SUCCESS) { - + /* Thread delete error. */ printf("ERROR #7\n"); test_control_return(1); @@ -190,32 +190,32 @@ UINT status; /* Sleep to let thread 2 run. */ tx_thread_sleep(2); - + /* Save the created count. */ saved_count = _tx_thread_created_count; - + /* Now setup things so we can fake a delete of one thread. */ _tx_thread_created_ptr = &thread_2; thread_2.tx_thread_created_next = &thread_2; thread_2.tx_thread_created_previous = &thread_2; _tx_thread_created_count = 1; - + /* Attempt to delete thread 2. */ status = tx_thread_delete(&thread_2); - + /* Check for the proper status. */ if (status != TX_SUCCESS) { - + /* Thread delete error. */ printf("ERROR #8\n"); test_control_return(1); } - + /* if still okay, restore the saved thread pointer. */ if (saved_ptr -> tx_thread_id == TX_THREAD_ID) - { - /* Restore. */ + { + /* Restore. */ _tx_thread_created_ptr = saved_ptr; /* Setup the link pointers again. */ @@ -242,7 +242,7 @@ UINT status; } else { - + /* Thread Finish error. */ printf("ERROR #9\n"); test_control_return(1); diff --git a/test/tx/regression/threadx_thread_create_preemption_threshold_test.c b/test/tx/regression/threadx_thread_create_preemption_threshold_test.c index ad0d1d4e..58ce79fe 100644 --- a/test/tx/regression/threadx_thread_create_preemption_threshold_test.c +++ b/test/tx/regression/threadx_thread_create_preemption_threshold_test.c @@ -43,8 +43,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 17, 0, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -56,8 +56,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 0, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -69,8 +69,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 15, 0, 100, TX_DONT_START); status += tx_thread_resume(&thread_0); pointer = pointer + TEST_STACK_SIZE_PRINTF; diff --git a/test/tx/regression/threadx_thread_delayed_suspension_test.c b/test/tx/regression/threadx_thread_delayed_suspension_test.c index 6d6d27d0..91128f83 100644 --- a/test/tx/regression/threadx_thread_delayed_suspension_test.c +++ b/test/tx/regression/threadx_thread_delayed_suspension_test.c @@ -97,7 +97,7 @@ ULONG i; if (loop_count < min_loop_count) min_loop_count = loop_count; if (loop_count > max_loop_count) - max_loop_count = loop_count; + max_loop_count = loop_count; lower_bound = loop_count - 1; upper_bound = loop_count + 1; @@ -108,38 +108,38 @@ ULONG i; if ((current_itterations < lower_bound) || (current_itterations > upper_bound)) current_itterations = lower_bound; - + #ifdef DEBUG_1 /* Last loop count. */ last_loop_count = loop_count; #endif - + /* Reset the loop count to all ones! */ loop_count = 0xFFFFFFFF; } count++; for (i = 0; i < (count%32); i++) - destination++; + destination++; /* Check to see if the interrupt occurred in the middle of the suspension. */ if ((thread_2.tx_thread_suspending) && (delayed_suspend_set == 0)) { - + /* Yes, we have taken the interrupt in the middle of a thread suspension. */ - + /* Indicate we have got the condition. */ delayed_suspend_set = 1; /* Capture the current thread 2 counter. */ thread_2_counter_capture = thread_2_counter; - + /* Now attempt to set the delayed suspension. */ tx_thread_suspend(&thread_2); - + /* Check for the delayed suspension flag being set. */ if (thread_2.tx_thread_delayed_suspend != 1) { - + /* Error! Setup the counters to indicate an error. */ thread_2_counter = 0xEEEEEEEE; thread_2_counter_capture = 0xFFFFFFFF; @@ -147,11 +147,11 @@ ULONG i; /* Now, abort the suspension for thread 2... the thread should switch to a pure suspended state. */ tx_thread_wait_abort(&thread_2); - + /* Check for the proper state. */ if (thread_2.tx_thread_state != TX_SUSPENDED) { - + /* Error! Setup the counters to indicate an error. */ thread_2_counter = 0xEEEEEEEE; thread_2_counter_capture = 0xFFFFFFFF; @@ -181,14 +181,14 @@ CHAR *pointer; create information. */ /* Create the main thread. */ - tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, 2, 2, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; /* Create threads 1 and 2. */ - tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, 2, 2, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + DEMO_STACK_SIZE; @@ -197,8 +197,8 @@ CHAR *pointer; #ifndef TX_NOT_INTERRUPTABLE - tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, DEMO_STACK_SIZE, + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, 1, 1, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + DEMO_STACK_SIZE; @@ -232,7 +232,7 @@ UINT status; tx_thread_relinquish(); /* At this point thread 1 has suspended on the semaphore. */ - + /* Suspend the already suspended thread. */ tx_thread_suspend(&thread_1); @@ -277,20 +277,20 @@ UINT status; /* Just relinquish. */ tx_thread_relinquish(); } - + /* Relinquish one more time to make sure thread 2 could run if it is ready. */ tx_thread_relinquish(); - + /* At this point, check for an error. */ if (thread_2_counter != thread_2_counter_capture) { - + /* Delayed suspension error... thread kept running! */ printf("ERROR #2\n"); test_control_return(1); } #endif - + /* Successful test. */ printf("SUCCESS!\n"); test_control_return(0); @@ -327,10 +327,10 @@ ULONG i; /* Callibrate the loop count from thread sleep. */ for (i = 0; i < 10; i++) { - + /* Sleep to get a fresh time. */ tx_thread_sleep(1); - + start_time = _tx_timer_system_clock; do { @@ -339,7 +339,7 @@ ULONG i; delay_function(); loop_count++; } while (start_time == _tx_timer_system_clock); - + /* Wait to reset the loop count. */ tx_thread_sleep(1); } @@ -358,7 +358,7 @@ ULONG i; /* Sleep to get a fresh starting time. */ tx_thread_sleep(1); - + loop_count = 0; start_time = _tx_timer_system_clock; do @@ -366,7 +366,7 @@ ULONG i; /* Call delay function. */ delay_function(); loop_count++; - } while (loop_count < current_itterations); + } while (loop_count < current_itterations); /* Suspend this thread. */ tx_semaphore_get(&semaphore_1, TX_WAIT_FOREVER); diff --git a/test/tx/regression/threadx_thread_information_test.c b/test/tx/regression/threadx_thread_information_test.c index b72a2363..19107742 100644 --- a/test/tx/regression/threadx_thread_information_test.c +++ b/test/tx/regression/threadx_thread_information_test.c @@ -31,8 +31,8 @@ INT status; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - first_unused_memory, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + first_unused_memory, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); /* Check for status. */ @@ -83,9 +83,9 @@ ULONG idle_returns; /* Get information about this thread. */ status = tx_thread_info_get(&thread_0, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_thread_info_get(&thread_0, &name, &state, &run_count, &priority, &preemption_threshold, &time_slice, &next_thread, &suspended_thread); - + /* Check for error status. */ - if ((status != TX_SUCCESS) || (state != TX_READY) || (run_count != thread_0.tx_thread_run_count) || (priority != 16) || (preemption_threshold != 16) || + if ((status != TX_SUCCESS) || (state != TX_READY) || (run_count != thread_0.tx_thread_run_count) || (priority != 16) || (preemption_threshold != 16) || (time_slice != 0) || (next_thread != thread_0.tx_thread_created_next) || (suspended_thread != thread_0.tx_thread_suspended_next)) { @@ -103,7 +103,7 @@ ULONG idle_returns; /* Check status. */ if (status != TX_PTR_ERROR) { - + /* Thread error. */ printf("ERROR #3\n"); test_control_return(1); @@ -111,7 +111,7 @@ ULONG idle_returns; /* Get the performance information about this thread. */ status = tx_thread_performance_info_get(&thread_0, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); - status += tx_thread_performance_info_get(&thread_0, &resumptions, &suspensions, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, + status += tx_thread_performance_info_get(&thread_0, &resumptions, &suspensions, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, &relinquishes, &timeouts, &wait_aborts, &last_preempted_by); /* Check for error. */ @@ -129,7 +129,7 @@ ULONG idle_returns; /* Get the system performance information. */ status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); - status += tx_thread_performance_system_info_get(&resumptions, &suspensions, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, + status += tx_thread_performance_system_info_get(&resumptions, &suspensions, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, &relinquishes, &timeouts, &wait_aborts, &non_idle_returns, &idle_returns); /* Check for error. */ @@ -146,7 +146,7 @@ ULONG idle_returns; } else { - + /* Success! */ printf("SUCCESS!\n"); test_control_return(0); @@ -154,312 +154,312 @@ ULONG idle_returns; #else /* Get the performance information about this thread. */ - status = tx_thread_performance_info_get(&thread_0, &resumptions, &suspensions, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, + status = tx_thread_performance_info_get(&thread_0, &resumptions, &suspensions, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, &relinquishes, &timeouts, &wait_aborts, &last_preempted_by); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #6\n"); test_control_return(1); } /* Get the performance information about this thread. */ - status = tx_thread_performance_info_get(TX_NULL, &resumptions, &suspensions, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, + status = tx_thread_performance_info_get(TX_NULL, &resumptions, &suspensions, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, &relinquishes, &timeouts, &wait_aborts, &last_preempted_by); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #7\n"); test_control_return(1); } /* Get the performance information about this thread. */ - status = tx_thread_performance_info_get(TX_NULL, TX_NULL, &suspensions, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, + status = tx_thread_performance_info_get(TX_NULL, TX_NULL, &suspensions, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, &relinquishes, &timeouts, &wait_aborts, &last_preempted_by); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #8\n"); test_control_return(1); } /* Get the performance information about this thread. */ - status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, + status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, &relinquishes, &timeouts, &wait_aborts, &last_preempted_by); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #9\n"); test_control_return(1); } /* Get the performance information about this thread. */ - status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, &interrupt_preemptions, &priority_inversions, &time_slices, + status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, &interrupt_preemptions, &priority_inversions, &time_slices, &relinquishes, &timeouts, &wait_aborts, &last_preempted_by); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #10\n"); test_control_return(1); } /* Get the performance information about this thread. */ - status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &priority_inversions, &time_slices, + status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &priority_inversions, &time_slices, &relinquishes, &timeouts, &wait_aborts, &last_preempted_by); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #11\n"); test_control_return(1); } /* Get the performance information about this thread. */ - status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &time_slices, + status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &time_slices, &relinquishes, &timeouts, &wait_aborts, &last_preempted_by); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #12\n"); test_control_return(1); } /* Get the performance information about this thread. */ - status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, + status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &relinquishes, &timeouts, &wait_aborts, &last_preempted_by); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #13\n"); test_control_return(1); } /* Get the performance information about this thread. */ - status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, + status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &timeouts, &wait_aborts, &last_preempted_by); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #14\n"); test_control_return(1); } /* Get the performance information about this thread. */ - status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, + status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &wait_aborts, &last_preempted_by); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #15\n"); test_control_return(1); } /* Get the performance information about this thread. */ - status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, + status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &last_preempted_by); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #16\n"); test_control_return(1); } /* Get the performance information about this thread. */ - status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, + status = tx_thread_performance_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #17\n"); test_control_return(1); } /* Get the system performance information. */ - status = tx_thread_performance_system_info_get(&resumptions, &suspensions, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, + status = tx_thread_performance_system_info_get(&resumptions, &suspensions, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, &relinquishes, &timeouts, &wait_aborts, &non_idle_returns, &idle_returns); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #18\n"); test_control_return(1); } /* Get the system performance information. */ - status = tx_thread_performance_system_info_get(TX_NULL, &suspensions, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, + status = tx_thread_performance_system_info_get(TX_NULL, &suspensions, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, &relinquishes, &timeouts, &wait_aborts, &non_idle_returns, &idle_returns); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #19\n"); test_control_return(1); } /* Get the system performance information. */ - status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, + status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, &solicited_preemptions, &interrupt_preemptions, &priority_inversions, &time_slices, &relinquishes, &timeouts, &wait_aborts, &non_idle_returns, &idle_returns); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #20\n"); test_control_return(1); } /* Get the system performance information. */ - status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, &interrupt_preemptions, &priority_inversions, &time_slices, + status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, &interrupt_preemptions, &priority_inversions, &time_slices, &relinquishes, &timeouts, &wait_aborts, &non_idle_returns, &idle_returns); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #21\n"); test_control_return(1); } /* Get the system performance information. */ - status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, &priority_inversions, &time_slices, + status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, &priority_inversions, &time_slices, &relinquishes, &timeouts, &wait_aborts, &non_idle_returns, &idle_returns); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #22\n"); test_control_return(1); } /* Get the system performance information. */ - status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &time_slices, + status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &time_slices, &relinquishes, &timeouts, &wait_aborts, &non_idle_returns, &idle_returns); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #23\n"); test_control_return(1); } /* Get the system performance information. */ - status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, + status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &relinquishes, &timeouts, &wait_aborts, &non_idle_returns, &idle_returns); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #24\n"); test_control_return(1); } /* Get the system performance information. */ - status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, + status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &timeouts, &wait_aborts, &non_idle_returns, &idle_returns); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #25\n"); test_control_return(1); } /* Get the system performance information. */ - status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, + status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &wait_aborts, &non_idle_returns, &idle_returns); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #26\n"); test_control_return(1); } /* Get the system performance information. */ - status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, + status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &non_idle_returns, &idle_returns); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #27\n"); test_control_return(1); } /* Get the system performance information. */ - status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, + status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, &idle_returns); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #28\n"); test_control_return(1); } /* Get the system performance information. */ - status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, + status = tx_thread_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Thread error. */ printf("ERROR #29\n"); test_control_return(1); diff --git a/test/tx/regression/threadx_thread_multi_level_preemption_threshold_test.c b/test/tx/regression/threadx_thread_multi_level_preemption_threshold_test.c index a65410fa..8944da46 100644 --- a/test/tx/regression/threadx_thread_multi_level_preemption_threshold_test.c +++ b/test/tx/regression/threadx_thread_multi_level_preemption_threshold_test.c @@ -1,4 +1,4 @@ -/* This test is designed to test multi-level preemption threshold. The protection placed +/* This test is designed to test multi-level preemption threshold. The protection placed by a thread must be preserved after higher-priority thread preemption that is above the threshold. */ #include @@ -139,8 +139,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, (TX_MAX_PRIORITIES-1), (TX_MAX_PRIORITIES/2), TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -154,8 +154,8 @@ CHAR *pointer; #ifndef TX_DISABLE_PREEMPTION_THRESHOLD /* skip this test and pretend it passed */ - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, (TX_MAX_PRIORITIES/2), (TX_MAX_PRIORITIES/2), TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -167,8 +167,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 15, 10, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -180,8 +180,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2a, "thread 2a", thread_2a_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2a, "thread 2a", thread_2a_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -193,8 +193,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 11, 11, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -206,8 +206,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 9, 9, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -221,8 +221,8 @@ CHAR *pointer; /* Create new cascading preemption-threshold test threads. */ - status = tx_thread_create(&thread_30_29, "thread 30-29", thread_30_29_entry, 30, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_30_29, "thread 30-29", thread_30_29_entry, 30, + pointer, TEST_STACK_SIZE_PRINTF, 30, 29, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -234,8 +234,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_28_27, "thread 28-27", thread_28_27_entry, 28, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_28_27, "thread 28-27", thread_28_27_entry, 28, + pointer, TEST_STACK_SIZE_PRINTF, 28, 27, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -247,8 +247,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_26_25, "thread 26-25", thread_26_25_entry, 26, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_26_25, "thread 26-25", thread_26_25_entry, 26, + pointer, TEST_STACK_SIZE_PRINTF, 26, 25, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -260,8 +260,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_24_23, "thread 24-23", thread_24_23_entry, 24, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_24_23, "thread 24-23", thread_24_23_entry, 24, + pointer, TEST_STACK_SIZE_PRINTF, 24, 23, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -273,8 +273,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_22_21, "thread 22-21", thread_22_21_entry, 22, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_22_21, "thread 22-21", thread_22_21_entry, 22, + pointer, TEST_STACK_SIZE_PRINTF, 22, 21, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -286,8 +286,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_20_19, "thread 20-19", thread_20_19_entry, 20, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_20_19, "thread 20-19", thread_20_19_entry, 20, + pointer, TEST_STACK_SIZE_PRINTF, 20,19, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -299,8 +299,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_18_17, "thread 18-17", thread_18_17_entry, 18, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_18_17, "thread 18-17", thread_18_17_entry, 18, + pointer, TEST_STACK_SIZE_PRINTF, 18, 17, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -312,8 +312,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_16_15, "thread 16-15", thread_16_15_entry, 16, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_16_15, "thread 16-15", thread_16_15_entry, 16, + pointer, TEST_STACK_SIZE_PRINTF, 16, 15, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -325,8 +325,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_14_13, "thread 14-13", thread_14_13_entry, 14, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_14_13, "thread 14-13", thread_14_13_entry, 14, + pointer, TEST_STACK_SIZE_PRINTF, 14, 13, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -338,8 +338,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_12_11, "thread 12-11", thread_12_11_entry, 12, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_12_11, "thread 12-11", thread_12_11_entry, 12, + pointer, TEST_STACK_SIZE_PRINTF, 12, 11, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -352,7 +352,7 @@ CHAR *pointer; } status = tx_thread_create(&thread_10_9, "thread 10-9", thread_10_9_entry, 10, - pointer, TEST_STACK_SIZE_PRINTF, + pointer, TEST_STACK_SIZE_PRINTF, 10, 9, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -364,8 +364,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_8_7, "thread 8-7", thread_8_7_entry, 8, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_8_7, "thread 8-7", thread_8_7_entry, 8, + pointer, TEST_STACK_SIZE_PRINTF, 8, 7, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -377,8 +377,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_6_5, "thread 6-5", thread_6_5_entry, 6, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_6_5, "thread 6-5", thread_6_5_entry, 6, + pointer, TEST_STACK_SIZE_PRINTF, 6, 5, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -390,8 +390,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_4_3, "thread 4-3", thread_4_3_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4_3, "thread 4-3", thread_4_3_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 4, 3, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -403,8 +403,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_3_2, "thread 3-2", thread_3_2_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3_2, "thread 3-2", thread_3_2_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 3, 2, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -416,8 +416,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2_1, "thread 2-1", thread_2_1_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2_1, "thread 2-1", thread_2_1_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 2, 1, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -429,8 +429,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1_0, "thread 1-0", thread_1_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1_0, "thread 1-0", thread_1_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 1, 1, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -443,7 +443,7 @@ CHAR *pointer; } status = tx_timer_create(&timer_0, "timer 0", timer_0_entry, 0, 1, 0, TX_NO_ACTIVATE); - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -451,7 +451,7 @@ CHAR *pointer; printf("Running Thread Multi-Level Preemption Threshold Test................ ERROR #24\n"); test_control_return(1); } - + #endif } @@ -522,7 +522,7 @@ UINT old_preempt; /* Set preemption threshold to keep new test threads from running. */ status = tx_thread_preemption_change(&thread_0, 17, &old_preempt); - + /* Now wakup the lowest priority preemption-threshold thread. */ status += tx_thread_resume(&thread_30_29); @@ -537,7 +537,7 @@ UINT old_preempt; /* Now, self suspend. */ status = tx_thread_suspend(&thread_0); - + /* Check to make sure all the preemption-threshold threads ran. */ if ((thread_1_0_counter != 1) || (thread_2_1_counter != 1) || @@ -606,7 +606,7 @@ UINT status; (thread_4_counter != 1)) return; - /* Relinquish to the other thread at this priority level. This should + /* Relinquish to the other thread at this priority level. This should clear the preemption threshold condition and allow thread 3 to run. */ tx_thread_relinquish(); @@ -648,7 +648,7 @@ static void timer_0_entry(ULONG id) /* Pretend like a preemption occurred on a thread priority of 1 with preemption-threshold set to 0. */ _tx_thread_preempted_maps[0] = _tx_thread_preempted_maps[0] | 2; - + /* Set the thread's preemption threshold as well. */ thread_1_0.tx_thread_preempt_threshold = 0; @@ -665,16 +665,16 @@ UINT status; /* Activate the timer to force a priority 0 thread to interrupt. */ status = tx_timer_activate(&timer_0); - + /* Loop to wait until timer 0 runs. */ while (timer_0_counter == 0) { } - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_1_0_counter++; } @@ -697,11 +697,11 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_1_0); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_3_2_counter++; } @@ -716,11 +716,11 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_2_1); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_4_3_counter++; } @@ -736,16 +736,16 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_4_3); - /* In this particular case, we have two different preemptions to make + /* In this particular case, we have two different preemptions to make sure we exercise all the code. */ /* Now resume next highest priority thread. */ status = tx_thread_resume(&thread_3_2); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_6_5_counter++; } @@ -760,11 +760,11 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_6_5); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_8_7_counter++; } @@ -779,11 +779,11 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_8_7); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_10_9_counter++; } @@ -797,11 +797,11 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_10_9); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_12_11_counter++; } @@ -816,11 +816,11 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_12_11); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_14_13_counter++; } @@ -835,11 +835,11 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_14_13); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_16_15_counter++; } @@ -854,11 +854,11 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_16_15); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_18_17_counter++; } @@ -873,11 +873,11 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_18_17); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_20_19_counter++; } @@ -892,11 +892,11 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_20_19); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_22_21_counter++; } @@ -911,11 +911,11 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_22_21); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_24_23_counter++; } @@ -929,11 +929,11 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_24_23); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_26_25_counter++; } @@ -947,11 +947,11 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_26_25); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_28_27_counter++; } @@ -965,15 +965,15 @@ UINT status; /* Resume next highest priority thread. */ status = tx_thread_resume(&thread_28_27); - + /* Check for good status. */ if (status == TX_SUCCESS) { - + /* Increment this thread's counter. */ thread_30_29_counter++; } - + /* Resume thread_0. */ tx_thread_resume(&thread_0); } diff --git a/test/tx/regression/threadx_thread_multiple_non_current_test.c b/test/tx/regression/threadx_thread_multiple_non_current_test.c index 51212b3b..50ed17a0 100644 --- a/test/tx/regression/threadx_thread_multiple_non_current_test.c +++ b/test/tx/regression/threadx_thread_multiple_non_current_test.c @@ -1,6 +1,6 @@ -/* This test is designed to see if multiple non-current threads can be suspended. - The order the suspension and resumption occurs makes sure everything is working - right. Thread execution should remain predictable even after suspension and +/* This test is designed to see if multiple non-current threads can be suspended. + The order the suspension and resumption occurs makes sure everything is working + right. Thread execution should remain predictable even after suspension and resumption of threads within a priority group. */ #include @@ -54,8 +54,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -67,8 +67,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -80,8 +80,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -93,8 +93,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -106,8 +106,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; diff --git a/test/tx/regression/threadx_thread_multiple_sleep_test.c b/test/tx/regression/threadx_thread_multiple_sleep_test.c index 9a876295..f2ae3b99 100644 --- a/test/tx/regression/threadx_thread_multiple_sleep_test.c +++ b/test/tx/regression/threadx_thread_multiple_sleep_test.c @@ -43,8 +43,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 3, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -56,8 +56,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 3, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -69,8 +69,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 3, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -82,8 +82,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, 3, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; diff --git a/test/tx/regression/threadx_thread_multiple_suspension_test.c b/test/tx/regression/threadx_thread_multiple_suspension_test.c index 0e4e5c06..01c42e8f 100644 --- a/test/tx/regression/threadx_thread_multiple_suspension_test.c +++ b/test/tx/regression/threadx_thread_multiple_suspension_test.c @@ -1,5 +1,5 @@ -/* This test is designed to see if multiple threads can be created and suspend. - The order the suspension and resumption occurs makes sure everything is working +/* This test is designed to see if multiple threads can be created and suspend. + The order the suspension and resumption occurs makes sure everything is working right. All the counters should increment at the same rate. */ #include @@ -59,8 +59,8 @@ CHAR *pointer; create information. */ /* Create thread 0. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 13, 13, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -73,8 +73,8 @@ CHAR *pointer; } /* Create thread 1. */ - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, (TX_MAX_PRIORITIES/2), (TX_MAX_PRIORITIES/2), TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -87,8 +87,8 @@ CHAR *pointer; } /* Create thread 2. */ - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, (TX_MAX_PRIORITIES/2), (TX_MAX_PRIORITIES/2), TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -101,8 +101,8 @@ CHAR *pointer; } /* Create thread 3. */ - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, (TX_MAX_PRIORITIES/2), (TX_MAX_PRIORITIES/2), TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -115,8 +115,8 @@ CHAR *pointer; } /* Create thread 4. */ - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -129,8 +129,8 @@ CHAR *pointer; } /* Create thread 5. Make this thread non-preemptable for the range of priorities here... */ - status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, (TX_MAX_PRIORITIES-1), 13, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -160,7 +160,7 @@ static void thread_0_entry(ULONG thread_input) /* Suspend this thread... */ tx_thread_suspend(&thread_0); - + /* Resume thread 5... */ tx_thread_resume(&thread_5); } @@ -252,7 +252,7 @@ UINT status; } /* Make sure that each thread has run once. */ - if ((thread_0_counter != 1) || (thread_1_counter != 1) || + if ((thread_0_counter != 1) || (thread_1_counter != 1) || (thread_2_counter != 1) || (thread_3_counter != 1) || (thread_4_counter != 1)) { @@ -277,7 +277,7 @@ UINT status; } /* Make sure that each thread has run once. */ - if ((thread_0_counter != 1) || (thread_1_counter != 1) || + if ((thread_0_counter != 1) || (thread_1_counter != 1) || (thread_2_counter != 1) || (thread_3_counter != 1) || (thread_4_counter != 1)) { @@ -301,7 +301,7 @@ UINT status; } /* Make sure that each thread has run once. */ - if ((thread_0_counter != 1) || (thread_1_counter != 1) || + if ((thread_0_counter != 1) || (thread_1_counter != 1) || (thread_2_counter != 1) || (thread_3_counter != 1) || (thread_4_counter != 1)) { @@ -325,7 +325,7 @@ UINT status; } /* Make sure that each thread has run once. */ - if ((thread_0_counter != 1) || (thread_1_counter != 1) || + if ((thread_0_counter != 1) || (thread_1_counter != 1) || (thread_2_counter != 1) || (thread_3_counter != 1) || (thread_4_counter != 1)) { @@ -349,7 +349,7 @@ UINT status; } /* Make sure that each thread has run once. */ - if ((thread_0_counter != 1) || (thread_1_counter != 1) || + if ((thread_0_counter != 1) || (thread_1_counter != 1) || (thread_2_counter != 1) || (thread_3_counter != 1) || (thread_4_counter != 1)) { @@ -373,7 +373,7 @@ UINT status; } /* Make sure that each thread has run once. */ - if ((thread_0_counter != 1) || (thread_1_counter != 1) || + if ((thread_0_counter != 1) || (thread_1_counter != 1) || (thread_2_counter != 1) || (thread_3_counter != 1) || (thread_4_counter != 1)) { @@ -398,7 +398,7 @@ UINT status; } /* Make sure that each thread has run twice. */ - if ((thread_0_counter != 2) || (thread_1_counter != 2) || + if ((thread_0_counter != 2) || (thread_1_counter != 2) || (thread_2_counter != 2) || (thread_3_counter != 2) || (thread_4_counter != 2)) { @@ -410,7 +410,7 @@ UINT status; /* Suspend a thread that is already suspended. */ status = tx_thread_suspend(&thread_4); - + /* Check for error condition. */ if (status != TX_SUCCESS) { @@ -420,7 +420,7 @@ UINT status; } else { - + /* Increment thread 5 counter. */ thread_5_counter++; diff --git a/test/tx/regression/threadx_thread_multiple_time_slice_test.c b/test/tx/regression/threadx_thread_multiple_time_slice_test.c index 6e1f61fd..f3e9fbf0 100644 --- a/test/tx/regression/threadx_thread_multiple_time_slice_test.c +++ b/test/tx/regression/threadx_thread_multiple_time_slice_test.c @@ -1,4 +1,4 @@ -/* This test is designed to see if two threads can be created and execute with a time-slice. +/* This test is designed to see if two threads can be created and execute with a time-slice. Thread 7 should run twice as long because it has more of a time-slice. */ #include @@ -50,8 +50,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 2, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -63,8 +63,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 4, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -77,8 +77,8 @@ CHAR *pointer; } /* Create control thread. */ - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -92,10 +92,10 @@ CHAR *pointer; #ifndef TX_DISABLE_PREEMPTION_THRESHOLD - /* Create threads with preemption-threshold and time-slice, such and make sure time-slice is defeated by + /* Create threads with preemption-threshold and time-slice, such and make sure time-slice is defeated by preemption-threshold. */ - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 18, 17, 2, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -107,8 +107,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, 4, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -161,7 +161,7 @@ static void thread_1_entry(ULONG thread_input) static void thread_2_entry(ULONG thread_input) { - + unsigned long counter_sum; #ifndef TX_DISABLE_PREEMPTION_THRESHOLD UINT status; @@ -177,7 +177,7 @@ UINT status; /* Increment thread 2 counter. */ thread_2_counter++; - /* Compute the delta. Should be twice as much, but some test environments (Windows/Linux) are + /* Compute the delta. Should be twice as much, but some test environments (Windows/Linux) are not as good in terms of real time processing. */ counter_sum = thread_0_counter; counter_sum = counter_sum + (thread_0_counter/4); @@ -187,19 +187,19 @@ UINT status; /* Thread Time-slice error. */ printf("ERROR #6\n"); test_control_return(1); - } + } #ifdef TX_DISABLE_PREEMPTION_THRESHOLD else { /* Successful Thread Time-slice test. */ printf("SUCCESS!\n"); test_control_return(0); - } + } #else /* Now suspend threads 0 and 1 so we can let 3 and 4 run. */ status = tx_thread_suspend(&thread_0); status += tx_thread_suspend(&thread_1); - + /* Check status. */ if (status) { @@ -207,7 +207,7 @@ UINT status; printf("ERROR #7\n"); test_control_return(1); } - + /* Now sleep and see if thread 4 ever runs. */ tx_thread_sleep(4); @@ -257,7 +257,7 @@ static void thread_4_entry(ULONG thread_input) { /* We should never get here! */ - + /* Increment thread 4 counter. */ thread_4_counter++; diff --git a/test/tx/regression/threadx_thread_preemptable_suspension_test.c b/test/tx/regression/threadx_thread_preemptable_suspension_test.c index b1c1bc52..8e4dbdd6 100644 --- a/test/tx/regression/threadx_thread_preemptable_suspension_test.c +++ b/test/tx/regression/threadx_thread_preemptable_suspension_test.c @@ -1,6 +1,6 @@ -/* This test is designed to see if multiple threads can be created and suspended. - The order the suspension and resumption occurs makes sure everything is working right. - All the counters should increment at the same rate. This test differs from test 4 in +/* This test is designed to see if multiple threads can be created and suspended. + The order the suspension and resumption occurs makes sure everything is working right. + All the counters should increment at the same rate. This test differs from test 4 in that thread 5 is preemptable. */ #include @@ -58,8 +58,8 @@ CHAR *pointer; create information. */ /* Create thread 0. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 13, 13, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -72,8 +72,8 @@ CHAR *pointer; } /* Create thread 1. */ - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -86,8 +86,8 @@ CHAR *pointer; } /* Create thread 2. */ - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -100,8 +100,8 @@ CHAR *pointer; } /* Create thread 3. */ - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -114,8 +114,8 @@ CHAR *pointer; } /* Create thread 4. */ - status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_4, "thread 4", thread_4_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -128,8 +128,8 @@ CHAR *pointer; } /* Create thread 5. Make this thread fully preemptable... */ - status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -159,7 +159,7 @@ static void thread_0_entry(ULONG thread_input) /* Suspend this thread... */ tx_thread_suspend(&thread_0); - + /* Resume thread 5... */ tx_thread_resume(&thread_5); } @@ -251,7 +251,7 @@ UINT status; } /* Make sure that each thread has run once. */ - if ((thread_0_counter != 1) || (thread_1_counter != 1) || + if ((thread_0_counter != 1) || (thread_1_counter != 1) || (thread_2_counter != 1) || (thread_3_counter != 1) || (thread_4_counter != 1)) { @@ -276,7 +276,7 @@ UINT status; } /* Make sure that each thread has run the proper amount. */ - if ((thread_0_counter != 2) || (thread_1_counter != 1) || + if ((thread_0_counter != 2) || (thread_1_counter != 1) || (thread_2_counter != 1) || (thread_3_counter != 1) || (thread_4_counter != 1)) { @@ -300,7 +300,7 @@ UINT status; } /* Make sure that each thread has run the proper amount. */ - if ((thread_0_counter != 2) || (thread_1_counter != 2) || + if ((thread_0_counter != 2) || (thread_1_counter != 2) || (thread_2_counter != 1) || (thread_3_counter != 1) || (thread_4_counter != 1)) { @@ -324,7 +324,7 @@ UINT status; } /* Make sure that each thread has the proper amount. */ - if ((thread_0_counter != 2) || (thread_1_counter != 2) || + if ((thread_0_counter != 2) || (thread_1_counter != 2) || (thread_2_counter != 2) || (thread_3_counter != 1) || (thread_4_counter != 1)) { @@ -348,7 +348,7 @@ UINT status; } /* Make sure that each thread has run the proper amount. */ - if ((thread_0_counter != 2) || (thread_1_counter != 2) || + if ((thread_0_counter != 2) || (thread_1_counter != 2) || (thread_2_counter != 2) || (thread_3_counter != 2) || (thread_4_counter != 1)) { @@ -372,7 +372,7 @@ UINT status; } /* Make sure that each thread has run once. */ - if ((thread_0_counter != 2) || (thread_1_counter != 2) || + if ((thread_0_counter != 2) || (thread_1_counter != 2) || (thread_2_counter != 2) || (thread_3_counter != 2) || (thread_4_counter != 2)) { @@ -397,7 +397,7 @@ UINT status; } /* Make sure that each thread has run twice. */ - if ((thread_0_counter != 2) || (thread_1_counter != 2) || + if ((thread_0_counter != 2) || (thread_1_counter != 2) || (thread_2_counter != 2) || (thread_3_counter != 2) || (thread_4_counter != 2)) { diff --git a/test/tx/regression/threadx_thread_preemption_change_test.c b/test/tx/regression/threadx_thread_preemption_change_test.c index 1633ef92..ca0a3c72 100644 --- a/test/tx/regression/threadx_thread_preemption_change_test.c +++ b/test/tx/regression/threadx_thread_preemption_change_test.c @@ -51,8 +51,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 15, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -66,8 +66,8 @@ CHAR *pointer; #ifndef TX_DISABLE_PREEMPTION_THRESHOLD /* skip this test and pretend it passed */ - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -79,8 +79,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 14, 14, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -126,7 +126,7 @@ UINT i; /* Increment thread 0 counter. */ thread_0_counter++; - /* Resume thread 1, which has a higher priority. Preemption is disabled + /* Resume thread 1, which has a higher priority. Preemption is disabled though so thread 1 should not run yet. */ status = tx_thread_resume(&thread_1); @@ -169,7 +169,7 @@ UINT i; } /* Change the preemption threshold back to 15. */ - status = tx_thread_preemption_change(&thread_0, 15, &old_threshold); + status = tx_thread_preemption_change(&thread_0, 15, &old_threshold); /* Check status and run counters of other threads. */ if ((status != TX_SUCCESS) || (thread_1_counter != 1) || (thread_2_counter != 0) || @@ -181,7 +181,7 @@ UINT i; test_control_return(1); } - /* Resume thread 2. This should preempt because it is priority 14 and the + /* Resume thread 2. This should preempt because it is priority 14 and the current preemption threshold is 15. */ status = tx_thread_resume(&thread_2); @@ -194,16 +194,16 @@ UINT i; test_control_return(1); } - /* At this point, we are going to loop through preemption changes that result in + /* At this point, we are going to loop through preemption changes that result in preemption. */ for (i = 0; i < (TX_THREAD_EXECUTE_LOG_SIZE*3); i++) { /* Change the preemption threshold back to 14. */ - status = tx_thread_preemption_change(&thread_0, 14, &old_threshold); + status = tx_thread_preemption_change(&thread_0, 14, &old_threshold); /* Check status. */ - if (status != TX_SUCCESS) + if (status != TX_SUCCESS) { /* Thread error. */ @@ -213,7 +213,7 @@ UINT i; /* Resume thread 2 again. */ status = tx_thread_resume(&thread_2); - + /* Check status an thread 2 run counter. */ if ((status != TX_SUCCESS) && (thread_2_counter != (i+1))) { @@ -222,9 +222,9 @@ UINT i; printf("ERROR #11\n"); test_control_return(1); } - + /* Change the preemption threshold back to 15 to allow thread 2 to run. */ - status = tx_thread_preemption_change(&thread_0, 15, &old_threshold); + status = tx_thread_preemption_change(&thread_0, 15, &old_threshold); /* Check status an thread 2 run counter. */ if ((status != TX_SUCCESS) && (thread_2_counter != (i+2))) @@ -237,21 +237,21 @@ UINT i; } /* Change the priority of threads 0 and 1. */ - status = tx_thread_priority_change(&thread_0, 7, &old_threshold); - status += tx_thread_priority_change(&thread_1, 5, &old_threshold); + status = tx_thread_priority_change(&thread_0, 7, &old_threshold); + status += tx_thread_priority_change(&thread_1, 5, &old_threshold); /* Check status. */ - if (status != TX_SUCCESS) + if (status != TX_SUCCESS) { /* Thread error. */ printf("ERROR #13\n"); test_control_return(1); - } + } /* Change the preemption-threshold of this thread. */ status = tx_thread_preemption_change(&thread_0, 0, &old_threshold); - + /* Check status. */ if ((status != TX_SUCCESS) || (old_threshold != 7)) { @@ -259,29 +259,29 @@ UINT i; /* Thread error. */ printf("ERROR #14\n"); test_control_return(1); - } - + } + /* Get the mutex that has priority inheritance. */ status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); /* Check status. */ - if (status != TX_SUCCESS) + if (status != TX_SUCCESS) { /* Thread error. */ printf("ERROR #15\n"); test_control_return(1); - } - + } + /* Resume thread 1 so that it can suspend on the mutex and automatically raise its priority. */ tx_thread_resume(&thread_1); - + /* Self suspend so that thread 1 and run. */ tx_thread_suspend(&thread_0); - + /* Restore the preemption-threshold of this thread. */ status = tx_thread_preemption_change(&thread_0, old_threshold, &old_threshold); - + /* Check status. */ if ((status != TX_SUCCESS) || (old_threshold != 0) || (thread_0.tx_thread_priority != 5) || (thread_0.tx_thread_preempt_threshold != 5)) { @@ -289,10 +289,10 @@ UINT i; /* Thread error. */ printf("ERROR #16\n"); test_control_return(1); - } + } /* Let thread 1 run again so it can release the mutex and undo the priority inheritance. */ - status = tx_mutex_put(&mutex_0); + status = tx_mutex_put(&mutex_0); /* Check status. */ if ((status != TX_SUCCESS) || (thread_0.tx_thread_priority != 7) || (thread_0.tx_thread_preempt_threshold != 7)) @@ -301,7 +301,7 @@ UINT i; /* Thread error. */ printf("ERROR #17\n"); test_control_return(1); - } + } /* Test direct call to the thread preemption change routine with a threshold greater than the current priority. */ status = _tx_thread_preemption_change(&thread_0, 8, &old_threshold); @@ -313,7 +313,7 @@ UINT i; /* Thread error. */ printf("ERROR #18\n"); test_control_return(1); - } + } #endif @@ -329,7 +329,7 @@ static void thread_1_entry(ULONG thread_input) /* Self suspend after initial run. */ tx_thread_suspend(&thread_1); - + /* Increment the thread counter. */ thread_1_counter++; @@ -343,7 +343,7 @@ static void thread_1_entry(ULONG thread_input) tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); /* Release the mutex. */ - tx_mutex_put(&mutex_0); + tx_mutex_put(&mutex_0); } @@ -352,10 +352,10 @@ static void thread_2_entry(ULONG thread_input) while(1) { - + /* Increment thread counter. */ thread_2_counter++; - + /* Self suspend. */ tx_thread_suspend(&thread_2); } diff --git a/test/tx/regression/threadx_thread_priority_change.c b/test/tx/regression/threadx_thread_priority_change.c index a7649b8e..6a61e2cf 100644 --- a/test/tx/regression/threadx_thread_priority_change.c +++ b/test/tx/regression/threadx_thread_priority_change.c @@ -51,7 +51,7 @@ UINT saved_preempt_disable; #ifndef TX_NOT_INTERRUPTABLE /* Determine if we have the interrupt condition we are looking for. */ - if ((thread_3.tx_thread_priority == 6) && + if ((thread_3.tx_thread_priority == 6) && (thread_3.tx_thread_state == TX_READY) && (_tx_thread_priority_list[6] != &thread_3) && (thread_3_counter > 100)) @@ -59,16 +59,16 @@ UINT saved_preempt_disable; /* Save the preempt disable flag. */ saved_preempt_disable = _tx_thread_preempt_disable; - + /* Clear the preempt disable flag to ensure the API works correctly. */ _tx_thread_preempt_disable = 0; /* Suspend the thread to generate the condition. */ tx_thread_suspend(&thread_3); - + /* Restore the preempt disable flag. */ _tx_thread_preempt_disable = saved_preempt_disable; - + /* Done trying to generate this test condition. */ test_isr_dispatch = TX_NULL; } @@ -77,7 +77,7 @@ UINT saved_preempt_disable; /* Can't get the interrupt inside the code wit TX_NOT_INTERRUPTABLE defined, so simply stop after thread_3_counter > 100. */ if (thread_3_counter > 100) { - + /* Done trying to generate this test condition. */ test_isr_dispatch = TX_NULL; } @@ -102,8 +102,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -115,8 +115,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 22, 22, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -128,16 +128,16 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 30, 1, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 5, 5, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_4, "thread 4", thread_4_entry, 4, + pointer, TEST_STACK_SIZE_PRINTF, 6, 6, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -171,11 +171,11 @@ UINT status; /* Increment thread 0 counter. */ thread_0_counter++; - /* Change priority to 22, to match that of the next highest priority ready thread. - This is to test the update of the priority list when a thread is moved to a + /* Change priority to 22, to match that of the next highest priority ready thread. + This is to test the update of the priority list when a thread is moved to a priority with already ready threads. */ status = tx_thread_priority_change(&thread_0, 22, &old_priority); - + /* Check status, return priority, and run count of other thread. */ if ((status != TX_SUCCESS) || (old_priority != 16) || (thread_1_counter != 0)) { @@ -186,7 +186,7 @@ UINT status; } /* Restore original priority. */ - tx_thread_priority_change(&thread_0, old_priority, &old_priority); + tx_thread_priority_change(&thread_0, old_priority, &old_priority); /* See if we can change priority of this thread. */ status = tx_thread_priority_change(&thread_0, 7, &old_priority); @@ -224,7 +224,7 @@ UINT status; test_control_return(1); } - /* Thread 1 should have run already... Raise this threads priority + /* Thread 1 should have run already... Raise this threads priority back up. */ status = tx_thread_priority_change(&thread_0, 8, &old_priority); @@ -284,10 +284,10 @@ UINT status; printf("ERROR #11\n"); test_control_return(1); } - + /* Now thread 1 should be suspended. Let's change thread 0's priority and make sure thread 2 doesn't run yet! */ status = tx_thread_priority_change(&thread_0, 7, &old_priority); - + /* Check status, return priority, and run count of other thread. */ if ((status != TX_SUCCESS) || (old_priority != 8) || (thread_1_counter != 2) || (thread_2_counter != 0)) { @@ -325,12 +325,12 @@ static void thread_2_entry(ULONG thread_input) while(1) { - + /* This thread should never run! */ /* Increment the thread counter. */ thread_2_counter++; - + /* Self suspend. */ tx_thread_suspend(&thread_2); } @@ -361,12 +361,12 @@ UINT loop; /* Raise priority of thread 3 for code coverage. */ tx_thread_priority_change(&thread_3, 6, &old_priority); tx_thread_priority_change(&thread_3, 5, &old_priority); - + /* Check to see if thread 4 has run... it should not have executed yet. If it does, set the thread_1_counter to indicate an error! */ if (thread_4_counter) thread_1_counter++; - + } while (test_isr_dispatch); } diff --git a/test/tx/regression/threadx_thread_relinquish_test.c b/test/tx/regression/threadx_thread_relinquish_test.c index e8b4ada7..5b180d84 100644 --- a/test/tx/regression/threadx_thread_relinquish_test.c +++ b/test/tx/regression/threadx_thread_relinquish_test.c @@ -47,8 +47,8 @@ CHAR *pointer; create information. */ /* Create thread 0. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -61,8 +61,8 @@ CHAR *pointer; } /* Create thread 1. */ - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -75,8 +75,8 @@ CHAR *pointer; } /* Create thread 2. */ - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -89,8 +89,8 @@ CHAR *pointer; } /* Create thread 3. */ - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -172,7 +172,7 @@ static void thread_3_entry(ULONG thread_input) /* Immediate response relinquish. */ tx_thread_relinquish(); - + /* All other threads should be completed now. */ if ((thread_0.tx_thread_state != TX_COMPLETED) || (thread_1.tx_thread_state != TX_COMPLETED) || (thread_2.tx_thread_state != TX_COMPLETED)) diff --git a/test/tx/regression/threadx_thread_reset_test.c b/test/tx/regression/threadx_thread_reset_test.c index ff3531a5..a709d163 100644 --- a/test/tx/regression/threadx_thread_reset_test.c +++ b/test/tx/regression/threadx_thread_reset_test.c @@ -35,7 +35,7 @@ static void entry_exit_notify(TX_THREAD *thread_ptr, UINT type) /* Check for the appropriate thread. */ if (thread_ptr != &thread_0) return; - + /* Check for type. */ if (type == TX_THREAD_ENTRY) thread_0_enter++; @@ -63,8 +63,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -94,8 +94,8 @@ CHAR *pointer; #endif - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -107,8 +107,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -150,11 +150,11 @@ UINT status; /* Attempt to delete thread 2, which is in the wrong stat for deleting. */ status = tx_thread_delete(&thread_2); - + /* Check for the proper status. */ if (status != TX_DELETE_ERROR) { - + /* Thread delete error. */ printf("ERROR #5\n"); test_control_return(1); @@ -177,11 +177,11 @@ UINT status; /* Call thread reset on thread 2, which should result in an error. */ status = tx_thread_reset(&thread_2); - + /* Check for proper status. */ if (status != TX_NOT_DONE) { - + /* Thread reset error. */ printf("ERROR #7\n"); test_control_return(1); @@ -206,12 +206,12 @@ UINT status; /* Terminate thread 0. */ status = tx_thread_terminate(&thread_0); - status += tx_thread_reset(&thread_0); - - + status += tx_thread_reset(&thread_0); + + /* Now resume thread 0 to let it run. */ status += tx_thread_resume(&thread_0); - + /* Determine if the first Thread has run and if it's current state is finished. */ if ((thread_0.tx_thread_state != TX_COMPLETED) || (thread_0_counter != 2) || @@ -228,7 +228,7 @@ UINT status; } else { - + /* Successful thread finish test. */ printf("SUCCESS!\n"); diff --git a/test/tx/regression/threadx_thread_simple_sleep_non_clear_test.c b/test/tx/regression/threadx_thread_simple_sleep_non_clear_test.c index f406924c..df8bb62b 100644 --- a/test/tx/regression/threadx_thread_simple_sleep_non_clear_test.c +++ b/test/tx/regression/threadx_thread_simple_sleep_non_clear_test.c @@ -32,15 +32,15 @@ CHAR *pointer; /* Put first available memory address into a character pointer. */ pointer = (CHAR *) first_unused_memory; - /* Place a 1 in the thread control block to simulate a control block created in + /* Place a 1 in the thread control block to simulate a control block created in random memory. */ thread_0.tx_thread_timer.tx_timer_internal_re_initialize_ticks = 1; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 3, TX_AUTO_START); /* Check for status. */ diff --git a/test/tx/regression/threadx_thread_simple_sleep_test.c b/test/tx/regression/threadx_thread_simple_sleep_test.c index 6b7afbe1..f038fafd 100644 --- a/test/tx/regression/threadx_thread_simple_sleep_test.c +++ b/test/tx/regression/threadx_thread_simple_sleep_test.c @@ -35,8 +35,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 3, TX_AUTO_START); /* Check for status. */ diff --git a/test/tx/regression/threadx_thread_simple_suspend_test.c b/test/tx/regression/threadx_thread_simple_suspend_test.c index 52215a75..a05797ec 100644 --- a/test/tx/regression/threadx_thread_simple_suspend_test.c +++ b/test/tx/regression/threadx_thread_simple_suspend_test.c @@ -1,4 +1,4 @@ -/* This test is designed to see if a thread can successfully suspend itself in a single +/* This test is designed to see if a thread can successfully suspend itself in a single thread system. This also tests a thread created that is not automatically enabled. */ #include @@ -39,8 +39,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -52,8 +52,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; diff --git a/test/tx/regression/threadx_thread_sleep_for_100ticks_test.c b/test/tx/regression/threadx_thread_sleep_for_100ticks_test.c index 69eadbc6..d5c335f0 100644 --- a/test/tx/regression/threadx_thread_sleep_for_100ticks_test.c +++ b/test/tx/regression/threadx_thread_sleep_for_100ticks_test.c @@ -99,7 +99,7 @@ ULONG i; if (loop_count < min_loop_count) min_loop_count = loop_count; if (loop_count > max_loop_count) - max_loop_count = loop_count; + max_loop_count = loop_count; lower_bound = loop_count - 1; upper_bound = loop_count + 1; @@ -110,18 +110,18 @@ ULONG i; if ((current_itterations < lower_bound) || (current_itterations > upper_bound)) current_itterations = lower_bound; - + #ifdef DEBUG_1 /* Last loop count. */ last_loop_count = loop_count; #endif - + /* Reset the loop count to all ones! */ loop_count = 0xFFFFFFFF; } count++; for (i = 0; i < (count%32); i++) - destination++; + destination++; /* Determine if the ISR is in the mode to wakeup the thread suspending with a timeout. */ if (isr_test_suspend_interrupt) @@ -135,26 +135,26 @@ ULONG i; if ((_tx_thread_preempt_disable) && (thread_0.tx_thread_timer.tx_timer_internal_list_head == TX_NULL)) { - + /* Set the flag showing the condition is present. */ isr_test_suspend_interrupted_condition = TX_TRUE; - + /* All done with the test. */ isr_test_suspend_interrupt = TX_FALSE; } - + /* Post to the semaphore to wakeup the thread. */ tx_semaphore_put(&test_semaphore); - } - + } + return; } #endif #endif - + /* Increment the ISR count. */ isr_count++; - + /* Call sleep from ISR to check for error! */ status = tx_thread_sleep(100); @@ -165,7 +165,7 @@ ULONG i; error = 1; } - + /* End the ISR. */ test_isr_dispatch = TX_NULL; } @@ -190,8 +190,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 3, TX_AUTO_START); /* Check for status. */ @@ -221,7 +221,7 @@ CHAR *pointer; current_itterations = 0; #ifdef DEBUG_1 last_loop_count = 0x0; -#endif +#endif #endif #endif } @@ -246,11 +246,11 @@ volatile ULONG value = 0; /* Call sleep with an expiration of 0 and test error code. */ status = tx_thread_sleep(0); - + /* Check error code. */ if (status != TX_SUCCESS) { - + /* Thread Simple Sleep error. */ printf("ERROR #3\n"); test_control_return(1); @@ -274,10 +274,10 @@ volatile ULONG value = 0; /* Callibrate the loop count from thread sleep. */ for (i = 0; i < 180; i++) { - + /* Sleep to get a fresh time. */ tx_thread_sleep(1); - + /* Set the loop count to 0 and start counting.... */ loop_count = 0; start_time = _tx_timer_system_clock; @@ -288,7 +288,7 @@ volatile ULONG value = 0; delay_function(); loop_count++; } while (start_time == _tx_timer_system_clock); - + /* Wait to reset the loop count. */ tx_thread_sleep(1); } @@ -323,7 +323,7 @@ volatile ULONG value = 0; /* Call delay function. */ delay_function(); loop_count++; - } while (loop_count < current_itterations); + } while (loop_count < current_itterations); /* Check for a timer interrupt... if so, just skip the semaphore get. */ if (start_time != _tx_timer_system_clock) @@ -331,7 +331,7 @@ volatile ULONG value = 0; /* Suspend on the semaphore for 20 ticks... */ tx_semaphore_get(&test_semaphore, 20); - + /* Adjust the current itterations. */ current_itterations++; if (current_itterations > upper_bound) @@ -391,14 +391,14 @@ volatile ULONG value = 0; /* Check for error. */ if (tx_time_get() < 100) { - + /* Thread Simple Sleep error. */ printf("ERROR #4\n"); test_control_return(1); - } + } #endif #endif - + /* Clear the tick count. */ tx_time_set(0); @@ -419,12 +419,12 @@ volatile ULONG value = 0; /* Check to make sure the ISR happened and the proper return value was present. */ if ((isr_count == 0) || (error)) { - + /* Thread Simple Sleep error. */ printf("ERROR #6\n"); test_control_return(1); } - else + else { /* Successful Simple Sleep test. */ diff --git a/test/tx/regression/threadx_thread_sleep_terminate_test.c b/test/tx/regression/threadx_thread_sleep_terminate_test.c index 871fc6e2..98862051 100644 --- a/test/tx/regression/threadx_thread_sleep_terminate_test.c +++ b/test/tx/regression/threadx_thread_sleep_terminate_test.c @@ -30,7 +30,7 @@ static void entry_exit_notify(TX_THREAD *thread_ptr, UINT type) /* Check for the appropriate thread. */ if (thread_ptr != &thread_1) return; - + /* Check for type. */ if (type == TX_THREAD_ENTRY) thread_1_enter++; @@ -58,8 +58,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -71,8 +71,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -144,7 +144,7 @@ UINT status; /* Now try to suspend a terminated thread. */ status = tx_thread_suspend(&thread_1); - + /* Check status. */ if (status != TX_SUSPEND_ERROR) { @@ -153,7 +153,7 @@ UINT status; printf("ERROR #6\n"); test_control_return(1); } - + /* Successful test. */ printf("SUCCESS!\n"); test_control_return(0); @@ -178,7 +178,7 @@ UINT status; /* Check status. */ if (status != TX_SUCCESS) { - thread_1_counter = 0; /* Make an error! */ + thread_1_counter = 0; /* Make an error! */ return; } } diff --git a/test/tx/regression/threadx_thread_stack_checking_test.c b/test/tx/regression/threadx_thread_stack_checking_test.c index 3ffe3841..940b6c6b 100644 --- a/test/tx/regression/threadx_thread_stack_checking_test.c +++ b/test/tx/regression/threadx_thread_stack_checking_test.c @@ -62,11 +62,11 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -75,8 +75,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -88,8 +88,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, TX_NO_TIME_SLICE, TX_DONT_START); thread_2_stack_start = pointer; pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -137,7 +137,7 @@ UINT status; /* Resume thread 1 to get the stack checking to take place. */ status = tx_thread_resume(&thread_1); - + /* Suspend to allow thread 1 to run. */ tx_thread_suspend(&thread_0); @@ -158,7 +158,7 @@ UINT status; } else { - + /* Success! */ printf("SUCCESS!\n"); test_control_return(0); @@ -201,10 +201,10 @@ TX_THREAD fake_thread; /* Increment thread 1 counter. */ thread_1_counter++; - /* Now, deregister the stack error handler and get into a spin condition. We will then + /* Now, deregister the stack error handler and get into a spin condition. We will then want to terminate thread 1 from thread 0 when it awakes! */ tx_thread_stack_error_notify(TX_NULL); - + /* Now resume thread 2 again to cause the stack error! */ tx_thread_resume(&thread_2); @@ -218,7 +218,7 @@ TX_THREAD fake_thread; static void thread_2_entry(ULONG thread_input) { - + /* Increment thread 1 counter. */ thread_2_counter++; } diff --git a/test/tx/regression/threadx_thread_terminate_delete_test.c b/test/tx/regression/threadx_thread_terminate_delete_test.c index dbe919f3..63fd6a69 100644 --- a/test/tx/regression/threadx_thread_terminate_delete_test.c +++ b/test/tx/regression/threadx_thread_terminate_delete_test.c @@ -42,7 +42,7 @@ static void entry_exit_notify(TX_THREAD *thread_ptr, UINT type) /* Check for the appropriate thread. */ if (thread_ptr != &thread_1) return; - + /* Check for type. */ if (type == TX_THREAD_ENTRY) thread_1_enter++; @@ -57,7 +57,7 @@ static void entry_exit_notify3(TX_THREAD *thread_ptr, UINT type) /* Check for the appropriate thread. */ if (thread_ptr != &thread_3) return; - + /* Check for type. */ if (type == TX_THREAD_ENTRY) thread_3_enter++; @@ -84,8 +84,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -97,8 +97,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -136,8 +136,8 @@ CHAR *pointer; #endif - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -149,8 +149,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_3, "thread 3", thread_3_entry, 3, + pointer, TEST_STACK_SIZE_PRINTF, 12, 12, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -231,7 +231,7 @@ UINT status; test_control_return(1); } - /* At this point, terminate thread 2 which should be in a suspended state + /* At this point, terminate thread 2 which should be in a suspended state right now. */ status = tx_thread_terminate(&thread_2); @@ -267,7 +267,7 @@ UINT status; test_control_return(1); } - /* At this point, terminate thread 3 which should be in a suspended state + /* At this point, terminate thread 3 which should be in a suspended state on the semaphore right now. */ status = tx_thread_terminate(&thread_3); diff --git a/test/tx/regression/threadx_thread_time_slice_change_test.c b/test/tx/regression/threadx_thread_time_slice_change_test.c index 8ee7df3b..0122fc2a 100644 --- a/test/tx/regression/threadx_thread_time_slice_change_test.c +++ b/test/tx/regression/threadx_thread_time_slice_change_test.c @@ -39,8 +39,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -52,8 +52,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 22, 22, 200, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -138,7 +138,7 @@ static void thread_1_entry(ULONG thread_input) while(1) { - + /* Identify. */ tx_thread_identify(); diff --git a/test/tx/regression/threadx_thread_wait_abort_and_isr_test.c b/test/tx/regression/threadx_thread_wait_abort_and_isr_test.c index 56fef596..bc7446f7 100644 --- a/test/tx/regression/threadx_thread_wait_abort_and_isr_test.c +++ b/test/tx/regression/threadx_thread_wait_abort_and_isr_test.c @@ -53,7 +53,7 @@ static volatile UINT miss_count = 0; /* Check for proper error status. */ if (status != TX_CALLER_ERROR) { - + /* Blow up the test to force an error. */ condition_count = 10000000; semaphore_put_counter = 0xFFFF0000; @@ -67,7 +67,7 @@ static volatile UINT miss_count = 0; condition_count++; } - /* + /* It is possible for this test to get into a resonance condition in which the ISR never occurs while preemption is disabled (especially if the ISR is installed in the periodic timer interrupt handler, which is @@ -105,8 +105,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -118,8 +118,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 17, 17, 100, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -133,7 +133,7 @@ CHAR *pointer; /* Create semaphore - consumer producer semaphore. */ status = tx_semaphore_create(&semaphore_0, "semaphore 0", 0); - + /* Check for status. */ if (status != TX_SUCCESS) { @@ -190,7 +190,7 @@ UINT status; } /* Check for the preempt disable flag being set. */ - if (_tx_thread_preempt_disable) + if (_tx_thread_preempt_disable) { /* Test error! */ @@ -207,13 +207,13 @@ UINT status; #ifdef TX_NOT_INTERRUPTABLE - /* Determine if we have a non-interruptable build of ThreadX. If so, just + /* Determine if we have a non-interruptable build of ThreadX. If so, just get out of this loop after 100 passes. */ if (thread_0_counter >= 100) break; #endif - + } } @@ -223,7 +223,7 @@ UINT status; #ifdef TX_NOT_INTERRUPTABLE /* At this point, check to see if we got all the semaphores! */ if ((thread_0_counter != (semaphore_put_counter - semaphore_0.tx_semaphore_count)) || - (condition_count != 0)) + (condition_count != 0)) #else /* At this point, check to see if we got all the semaphores! */ if (thread_0_counter != (semaphore_put_counter - semaphore_0.tx_semaphore_count)) diff --git a/test/tx/regression/threadx_thread_wait_abort_test.c b/test/tx/regression/threadx_thread_wait_abort_test.c index a2e8e42d..49852ec1 100644 --- a/test/tx/regression/threadx_thread_wait_abort_test.c +++ b/test/tx/regression/threadx_thread_wait_abort_test.c @@ -39,8 +39,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -52,8 +52,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; diff --git a/test/tx/regression/threadx_time_get_set_test.c b/test/tx/regression/threadx_time_get_set_test.c index 6bc2ddc1..06b8e6f5 100644 --- a/test/tx/regression/threadx_time_get_set_test.c +++ b/test/tx/regression/threadx_time_get_set_test.c @@ -34,8 +34,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 3, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -66,7 +66,7 @@ ULONG current_time; /* Sleep for 1 tick to get a fresh timer. */ tx_thread_sleep(1); - + /* Set time to 0. */ tx_time_set(0); diff --git a/test/tx/regression/threadx_timer_activate_deactivate_test.c b/test/tx/regression/threadx_timer_activate_deactivate_test.c index a238ea33..69f9b38f 100644 --- a/test/tx/regression/threadx_timer_activate_deactivate_test.c +++ b/test/tx/regression/threadx_timer_activate_deactivate_test.c @@ -46,8 +46,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 3, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -89,13 +89,13 @@ TX_TIMER_INTERNAL **current_list_head; /* Call the timer thread entry function with an invalid value to make sure the code simply returns. */ _tx_timer_thread_entry(0); -#endif - +#endif + #ifndef TX_TIMER_PROCESS_IN_ISR tx_thread_resume(&_tx_timer_thread); #endif - + /* Call the internal timer activate function with 0 remaining time. */ test_timer.tx_timer_internal_remaining_ticks = 0; _tx_timer_system_activate(&test_timer); @@ -105,7 +105,7 @@ TX_TIMER_INTERNAL **current_list_head; list_head = TX_NULL; test_timer.tx_timer_internal_list_head = &list_head; _tx_timer_system_activate(&test_timer); - + /* Call the internal timer deactivate function to ensure the list head is not updated unless valid. */ list_head = TX_NULL; test_timer.tx_timer_internal_list_head = &list_head; @@ -115,8 +115,8 @@ TX_TIMER_INTERNAL **current_list_head; /* Call timer info get with a timer setup to exercise a path not possible, in order to exercise all conditionals. */ test_app_timer.tx_timer_internal.tx_timer_internal_list_head = (_tx_timer_list_end + 1); - status = _tx_timer_info_get(&test_app_timer, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); - + status = _tx_timer_info_get(&test_app_timer, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); + /* Deactivate and activate the timer. */ test_app_timer.tx_timer_internal.tx_timer_internal_active_next = &test_app_timer.tx_timer_internal; status += _tx_timer_deactivate(&test_app_timer); @@ -160,7 +160,7 @@ TX_TIMER_INTERNAL **current_list_head; /* Sleep for a 14 ticks. */ tx_thread_sleep(14); - /* At this point the initial expiration of the timer should have + /* At this point the initial expiration of the timer should have happened. */ if (timer_0_counter != 1) { @@ -174,7 +174,7 @@ TX_TIMER_INTERNAL **current_list_head; again! */ tx_thread_sleep(24); - /* At this point the timer counter should still be 1. */ + /* At this point the timer counter should still be 1. */ if (timer_0_counter != 1) { @@ -205,27 +205,27 @@ TX_TIMER_INTERNAL **current_list_head; timer_2.tx_timer_id = TX_TIMER_ID; timer_2.tx_timer_internal.tx_timer_internal_list_head = (TX_TIMER_INTERNAL **) ¤t_list_head; current_list_head = (struct TX_TIMER_INTERNAL_STRUCT **) &(timer_2.tx_timer_internal); - timer_2.tx_timer_internal.tx_timer_internal_remaining_ticks = TX_TIMER_ENTRIES*2; + timer_2.tx_timer_internal.tx_timer_internal_remaining_ticks = TX_TIMER_ENTRIES*2; timer_2.tx_timer_internal.tx_timer_internal_active_next = &(timer_2.tx_timer_internal); status = tx_timer_deactivate(&timer_2); /* Check for error. */ if ((status != TX_SUCCESS) || (timer_2.tx_timer_internal.tx_timer_internal_remaining_ticks != TX_TIMER_ENTRIES)) { - + /* Application timer error. */ printf("ERROR #8a\n"); test_control_return(1); } - /* Sleep for twice the expiration time to make sure the timer + /* Sleep for twice the expiration time to make sure the timer doesn't automatically reschedule. */ tx_thread_sleep(47); /* Check for an error. */ - /* At this point the timer counter should still be 1. */ + /* At this point the timer counter should still be 1. */ if (timer_0_counter != 1) { diff --git a/test/tx/regression/threadx_timer_deactivate_accuracy_test.c b/test/tx/regression/threadx_timer_deactivate_accuracy_test.c index 6af4bde4..625b82a6 100644 --- a/test/tx/regression/threadx_timer_deactivate_accuracy_test.c +++ b/test/tx/regression/threadx_timer_deactivate_accuracy_test.c @@ -41,8 +41,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 3, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -144,7 +144,7 @@ UINT status; printf("ERROR #7\n"); test_control_return(1); } - + /* Sleep */ tx_thread_sleep(4); diff --git a/test/tx/regression/threadx_timer_information_test.c b/test/tx/regression/threadx_timer_information_test.c index 4dbc3c9b..7954de2c 100644 --- a/test/tx/regression/threadx_timer_information_test.c +++ b/test/tx/regression/threadx_timer_information_test.c @@ -48,8 +48,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 3, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -119,7 +119,7 @@ TX_TIMER_INTERNAL **list_head; /* Application timer error. */ printf("ERROR #4\n"); test_control_return(1); - } + } /* Deactivate the timer. */ status = tx_timer_deactivate(&timer_0); @@ -143,7 +143,7 @@ TX_TIMER_INTERNAL **list_head; /* Application timer error. */ printf("ERROR #6\n"); test_control_return(1); - } + } /* Modify the timer. */ status = tx_timer_change(&timer_0, 100, 1); @@ -194,12 +194,12 @@ TX_TIMER_INTERNAL **list_head; /* Check for successful completion. */ if ((status != TX_SUCCESS) || (active != TX_TRUE) || (remaining_ticks != 1) || (reschedule_ticks != 1) || (next_timer != &timer_1)) { - + /* Application timer error. */ printf("ERROR #10\n"); test_control_return(1); - } - + } + /* Now, deactivate timer 0 to get another path through the info get service. */ status = tx_timer_deactivate(&timer_0); status += tx_timer_info_get(&timer_0, &name, &active, &remaining_ticks, &reschedule_ticks, &next_timer); @@ -207,26 +207,26 @@ TX_TIMER_INTERNAL **list_head; /* Check for successful completion. */ if ((status != TX_SUCCESS) || (active != TX_FALSE) || (remaining_ticks != 1) || (reschedule_ticks != 1) || (next_timer != &timer_1)) { - + /* Application timer error. */ printf("ERROR #11\n"); test_control_return(1); - } + } - /* Change timer 0 to a large value and get the information again. */ + /* Change timer 0 to a large value and get the information again. */ status = tx_timer_change(&timer_0, 100, 200); status += tx_timer_activate(&timer_0); - + status += tx_timer_info_get(&timer_0, &name, &active, &remaining_ticks, &reschedule_ticks, &next_timer); /* Check for successful completion. */ if ((status != TX_SUCCESS) || (active != TX_TRUE) || (remaining_ticks != 100) || (reschedule_ticks != 200) || (next_timer != &timer_1)) { - + /* Application timer error. */ printf("ERROR #12\n"); test_control_return(1); - } + } #ifdef TX_TIMER_ENABLE_PERFORMANCE_INFO @@ -236,7 +236,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if (status != TX_PTR_ERROR) { - + /* Application timer error. */ printf("ERROR #13\n"); test_control_return(1); @@ -245,30 +245,30 @@ TX_TIMER_INTERNAL **list_head; /* Now get the performance information. */ status = tx_timer_performance_info_get(&timer_0, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_timer_performance_info_get(&timer_0, &activates, &reactivates, &deactivates, &expirations, &expiration_adjusts); - + /* Check for successful completion. */ - if ((status != TX_SUCCESS) || (activates != timer_0.tx_timer_performance_activate_count) || (reactivates != timer_0.tx_timer_performance_reactivate_count) || + if ((status != TX_SUCCESS) || (activates != timer_0.tx_timer_performance_activate_count) || (reactivates != timer_0.tx_timer_performance_reactivate_count) || (deactivates != timer_0.tx_timer_performance_deactivate_count) || (expirations != timer_0.tx_timer_performance_expiration_count) || (expiration_adjusts != timer_0.tx_timer_performance__expiration_adjust_count)) { - + /* Application timer error. */ printf("ERROR #14\n"); test_control_return(1); - } + } /* Now get the system performance information. */ status = tx_timer_performance_system_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); status += tx_timer_performance_system_info_get(&activates, &reactivates, &deactivates, &expirations, &expiration_adjusts); - + /* Check for successful completion. */ - if ((status != TX_SUCCESS) || (activates != _tx_timer_performance_activate_count) || (reactivates != _tx_timer_performance_reactivate_count) || + if ((status != TX_SUCCESS) || (activates != _tx_timer_performance_activate_count) || (reactivates != _tx_timer_performance_reactivate_count) || (deactivates != _tx_timer_performance_deactivate_count) || (expirations != _tx_timer_performance_expiration_count) || (expiration_adjusts != _tx_timer_performance__expiration_adjust_count)) { - + /* Application timer error. */ printf("ERROR #15\n"); test_control_return(1); - } + } #else @@ -278,7 +278,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Application timer error. */ printf("ERROR #16\n"); test_control_return(1); @@ -290,7 +290,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Application timer error. */ printf("ERROR #17\n"); test_control_return(1); @@ -302,7 +302,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Application timer error. */ printf("ERROR #18\n"); test_control_return(1); @@ -314,7 +314,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Application timer error. */ printf("ERROR #19\n"); test_control_return(1); @@ -326,7 +326,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Application timer error. */ printf("ERROR #20\n"); test_control_return(1); @@ -338,7 +338,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Application timer error. */ printf("ERROR #21\n"); test_control_return(1); @@ -350,7 +350,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Application timer error. */ printf("ERROR #22\n"); test_control_return(1); @@ -362,7 +362,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Application timer error. */ printf("ERROR #23\n"); test_control_return(1); @@ -374,7 +374,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Application timer error. */ printf("ERROR #24\n"); test_control_return(1); @@ -386,7 +386,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Application timer error. */ printf("ERROR #25\n"); test_control_return(1); @@ -398,7 +398,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Application timer error. */ printf("ERROR #26\n"); test_control_return(1); @@ -410,7 +410,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Application timer error. */ printf("ERROR #27\n"); test_control_return(1); @@ -422,7 +422,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Application timer error. */ printf("ERROR #28\n"); test_control_return(1); @@ -432,18 +432,18 @@ TX_TIMER_INTERNAL **list_head; /* Test timer that is in the process of expiration - on temporary "expired" list. */ TX_MEMSET(&timer_2, 0, (sizeof(TX_TIMER))); - + /* Setup fake timer and test for no-reactivate condition. */ timer_2.tx_timer_id = TX_TIMER_ID; timer_2.tx_timer_internal.tx_timer_internal_list_head = (TX_TIMER_INTERNAL **) &list_head; list_head = (struct TX_TIMER_INTERNAL_STRUCT **) &(timer_2.tx_timer_internal); - timer_2.tx_timer_internal.tx_timer_internal_remaining_ticks = 10; + timer_2.tx_timer_internal.tx_timer_internal_remaining_ticks = 10; status = tx_timer_info_get(&timer_2, TX_NULL, TX_NULL, &remaining_ticks, &reschedule_ticks, TX_NULL); /* Check for error. */ if ((status != TX_SUCCESS) || (remaining_ticks != 0) || (reschedule_ticks != 0)) { - + /* Application timer error. */ printf("ERROR #28a\n"); test_control_return(1); @@ -453,13 +453,13 @@ TX_TIMER_INTERNAL **list_head; timer_2.tx_timer_id = TX_TIMER_ID; timer_2.tx_timer_internal.tx_timer_internal_list_head = (TX_TIMER_INTERNAL **) &list_head; list_head = (struct TX_TIMER_INTERNAL_STRUCT **) &(timer_2.tx_timer_internal); - timer_2.tx_timer_internal.tx_timer_internal_remaining_ticks = TX_TIMER_ENTRIES * 2; + timer_2.tx_timer_internal.tx_timer_internal_remaining_ticks = TX_TIMER_ENTRIES * 2; status = tx_timer_info_get(&timer_2, TX_NULL, TX_NULL, &remaining_ticks, &reschedule_ticks, TX_NULL); /* Check for error. */ if ((status != TX_SUCCESS) || (remaining_ticks != TX_TIMER_ENTRIES) || (reschedule_ticks != 0)) { - + /* Application timer error. */ printf("ERROR #28a\n"); test_control_return(1); @@ -473,7 +473,7 @@ TX_TIMER_INTERNAL **list_head; timer_2.tx_timer_id = TX_TIMER_ID; timer_2.tx_timer_internal.tx_timer_internal_list_head = (TX_TIMER_INTERNAL **) &list_head; list_head = (struct TX_TIMER_INTERNAL_STRUCT **) &(timer_2.tx_timer_internal); - timer_2.tx_timer_internal.tx_timer_internal_remaining_ticks = 13; + timer_2.tx_timer_internal.tx_timer_internal_remaining_ticks = 13; _tx_timer_expired_timer_ptr = &timer_2.tx_timer_internal; status = tx_timer_info_get(&timer_2, TX_NULL, TX_NULL, &remaining_ticks, &reschedule_ticks, TX_NULL); _tx_timer_expired_timer_ptr = TX_NULL; @@ -484,7 +484,7 @@ TX_TIMER_INTERNAL **list_head; /* Check for error. */ if ((status != TX_SUCCESS) || (remaining_ticks != 0) || (reschedule_ticks != 0)) { - + /* Application timer error. */ printf("ERROR #28b\n"); test_control_return(1); diff --git a/test/tx/regression/threadx_timer_large_timer_accuracy_test.c b/test/tx/regression/threadx_timer_large_timer_accuracy_test.c index dde97fe4..726523b9 100644 --- a/test/tx/regression/threadx_timer_large_timer_accuracy_test.c +++ b/test/tx/regression/threadx_timer_large_timer_accuracy_test.c @@ -41,8 +41,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 3, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -144,7 +144,7 @@ UINT status; printf("ERROR #7\n"); test_control_return(1); } - + /* Sleep */ tx_thread_sleep(2); diff --git a/test/tx/regression/threadx_timer_multiple_accuracy_test.c b/test/tx/regression/threadx_timer_multiple_accuracy_test.c index a7be91e2..af9957d8 100644 --- a/test/tx/regression/threadx_timer_multiple_accuracy_test.c +++ b/test/tx/regression/threadx_timer_multiple_accuracy_test.c @@ -43,8 +43,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 3, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; diff --git a/test/tx/regression/threadx_timer_multiple_test.c b/test/tx/regression/threadx_timer_multiple_test.c index 3f02d5a7..688a7d5b 100644 --- a/test/tx/regression/threadx_timer_multiple_test.c +++ b/test/tx/regression/threadx_timer_multiple_test.c @@ -1,4 +1,4 @@ -/* This test is designed to test a simple application timer services, +/* This test is designed to test a simple application timer services, including create, activate, deactivate, change, and delete with multiple timers. */ #include @@ -46,8 +46,8 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 3, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; diff --git a/test/tx/regression/threadx_timer_simple_test.c b/test/tx/regression/threadx_timer_simple_test.c index 3df62caa..7fdf022e 100644 --- a/test/tx/regression/threadx_timer_simple_test.c +++ b/test/tx/regression/threadx_timer_simple_test.c @@ -1,4 +1,4 @@ -/* This test is designed to test a simple application timer services, including create, +/* This test is designed to test a simple application timer services, including create, activate, deactivate, change, and delete. */ #include @@ -52,7 +52,7 @@ static void thread_1_entry(ULONG thread_input); static void timer_0_expiration(ULONG timer_input); static void timer_1_expiration(ULONG timer_input); -UINT _txe_timer_create(TX_TIMER *timer_ptr, CHAR *name_ptr, +UINT _txe_timer_create(TX_TIMER *timer_ptr, CHAR *name_ptr, VOID (*expiration_function)(ULONG), ULONG expiration_input, ULONG initial_ticks, ULONG reschedule_ticks, UINT auto_activate, UINT timer_control_block_size); @@ -75,18 +75,18 @@ UINT status; /* Determine if the timer was able to be created durning initialization. */ if (test_timer_create_init != TX_SUCCESS) { - + /* Error! */ error++; } /* Attempt to delete a timer from a timer. */ status = tx_timer_delete(&timer_0); - + /* Check status. */ if (status != TX_CALLER_ERROR) { - + /* Error! */ error++; } @@ -98,7 +98,7 @@ UINT status; /* Check status. */ if (status != TX_CALLER_ERROR) { - + /* Error! */ error++; } @@ -124,11 +124,11 @@ UINT status; /* Attempt to delete a timer from an ISR. */ status = tx_timer_delete(&timer_0); - + /* Check status. */ if (status != TX_CALLER_ERROR) { - + /* Error! */ error++; } @@ -140,7 +140,7 @@ UINT status; /* Check status. */ if (status != TX_CALLER_ERROR) { - + /* Error! */ error++; } @@ -168,13 +168,13 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, 3, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; - status += tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status += tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 18, 18, 3, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -234,7 +234,7 @@ UINT status; timer_memory.second = 0x55667788; timer_memory.next_to_last = 0x99aabbcc; timer_memory.last = 0xddeeff00; - + /* Create the timer. */ status = tx_timer_create(&timer_memory.timer, "timer memory", timer_0_expiration, 0x1234, 1000000, 100000, TX_NO_ACTIVATE); @@ -247,7 +247,7 @@ UINT status; (timer_memory.next_to_last != 0x99aabbcc) || (timer_memory.last != 0xddeeff00)) { - + /* Memory overwrite error. */ printf("ERROR #4\n"); test_control_return(1); @@ -257,11 +257,11 @@ UINT status; /* Attempt to activate a non-timer. */ status = tx_timer_activate(TX_NULL); - + /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #5\n"); test_control_return(1); @@ -270,11 +270,11 @@ UINT status; /* Attempt to activate a non-created timer. */ timer_2.tx_timer_id = 0; status = tx_timer_activate(&timer_2); - + /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #6\n"); test_control_return(1); @@ -285,11 +285,11 @@ UINT status; timer_2.tx_timer_internal.tx_timer_internal_list_head = TX_NULL; timer_2.tx_timer_internal.tx_timer_internal_remaining_ticks = 0; status = tx_timer_activate(&timer_2); - + /* Check status. */ if (status != TX_ACTIVATE_ERROR) { - + /* Application timer error. */ printf("ERROR #7\n"); test_control_return(1); @@ -301,11 +301,11 @@ UINT status; timer_2.tx_timer_internal.tx_timer_internal_list_head = TX_NULL; timer_2.tx_timer_internal.tx_timer_internal_remaining_ticks = TX_WAIT_FOREVER; status = tx_timer_activate(&timer_2); - + /* Check status. */ if (status != TX_SUCCESS) { - + /* Application timer error. */ printf("ERROR #8\n"); test_control_return(1); @@ -315,11 +315,11 @@ UINT status; /* Attempt to deactivate a non-timer. */ status = tx_timer_deactivate(TX_NULL); - + /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #9\n"); test_control_return(1); @@ -328,11 +328,11 @@ UINT status; /* Attempt to deactivate a non-created timer. */ timer_2.tx_timer_id = 0; status = tx_timer_deactivate(&timer_2); - + /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #10\n"); test_control_return(1); @@ -340,11 +340,11 @@ UINT status; /* Attempt to change a non-timer. */ status = tx_timer_change(TX_NULL, 1, 1); - + /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #11\n"); test_control_return(1); @@ -353,11 +353,11 @@ UINT status; /* Attempt to change a non-created timer. */ timer_2.tx_timer_id = 0; status = tx_timer_change(&timer_2, 1, 1); - + /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #12\n"); test_control_return(1); @@ -365,11 +365,11 @@ UINT status; /* Attempt to change a timer with a 0 initial ticks. */ status = tx_timer_change(&timer_0, 0, 1); - + /* Check status. */ if (status != TX_TICK_ERROR) { - + /* Application timer error. */ printf("ERROR #13\n"); test_control_return(1); @@ -377,11 +377,11 @@ UINT status; /* Attempt to delete a non-time. */ status = tx_timer_delete(TX_NULL); - + /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #14\n"); test_control_return(1); @@ -390,11 +390,11 @@ UINT status; /* Attempt to delete a non-created time. */ timer_2.tx_timer_id = 0; status = tx_timer_delete(&timer_2); - + /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #15\n"); test_control_return(1); @@ -402,11 +402,11 @@ UINT status; /* Attempt to get info from a non-timer. */ status = tx_timer_info_get(TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); - + /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #16\n"); test_control_return(1); @@ -415,11 +415,11 @@ UINT status; /* Attempt to get info from a non-created timer. */ timer_2.tx_timer_id = 0; status = tx_timer_info_get(&timer_2, TX_NULL, TX_NULL, TX_NULL, TX_NULL, TX_NULL); - + /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #17\n"); test_control_return(1); @@ -432,7 +432,7 @@ UINT status; /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #18\n"); test_control_return(1); @@ -445,7 +445,7 @@ UINT status; /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #19\n"); test_control_return(1); @@ -458,7 +458,7 @@ UINT status; /* Check status. */ if (status != TX_TIMER_ERROR) { - + /* Application timer error. */ printf("ERROR #20\n"); test_control_return(1); @@ -471,7 +471,7 @@ UINT status; /* Check status. */ if (status != TX_TICK_ERROR) { - + /* Application timer error. */ printf("ERROR #21\n"); test_control_return(1); @@ -484,7 +484,7 @@ UINT status; /* Check status. */ if (status != TX_ACTIVATE_ERROR) { - + /* Application timer error. */ printf("ERROR #22\n"); test_control_return(1); @@ -502,7 +502,7 @@ UINT status; /* Application timer error. */ printf("ERROR #23\n"); test_control_return(1); - } + } /* Deactivate the timer. */ status = tx_timer_deactivate(&timer_0); @@ -526,7 +526,7 @@ UINT status; /* Application timer error. */ printf("ERROR #25\n"); test_control_return(1); - } + } /* Modify the timer. */ status = tx_timer_change(&timer_0, 100, 1); @@ -613,7 +613,7 @@ UINT status; /* Test for error. */ if ((error) || (timer_executed != 1) || (isr_executed != 1)) { - + /* Thread error. */ printf("ERROR #30\n"); test_control_return(1); @@ -623,7 +623,7 @@ UINT status; if (error) { - + /* Thread error. */ printf("ERROR #31\n"); test_control_return(1); @@ -639,11 +639,11 @@ UINT status; static void thread_1_entry(ULONG thread_input) { - + while(1) { - - tx_thread_relinquish(); + + tx_thread_relinquish(); } } @@ -658,7 +658,7 @@ static void timer_0_expiration(ULONG timer_input) static void timer_1_expiration(ULONG timer_input) { - + /* Process timer expiration. */ timer_1_counter++; } diff --git a/test/tx/regression/threadx_trace_basic_test.c b/test/tx/regression/threadx_trace_basic_test.c index bd6ca72f..0914650f 100644 --- a/test/tx/regression/threadx_trace_basic_test.c +++ b/test/tx/regression/threadx_trace_basic_test.c @@ -95,9 +95,9 @@ UINT old_interrupt; /* If win32, we can actually dump the file! */ trace_dump_file = fopen(trace_dump_file_name, "wb+"); - + fwrite(trace_buffer, 1, sizeof(trace_buffer), trace_dump_file); - + fclose(trace_dump_file); /* Restore interrupts. */ @@ -109,7 +109,7 @@ UINT old_interrupt; { trace_dump_file_name[11] = '0'; trace_dump_file_name[10]++; - + if (trace_dump_file_name[10] > '9') { trace_dump_file_name[10] = '0'; @@ -141,7 +141,7 @@ static void test_isr(void) /* Make ISR entry event. */ tx_trace_isr_enter_insert(1); - + /* Resume thread 2. */ tx_thread_resume(&thread_2); @@ -176,7 +176,7 @@ CHAR *pointer; /* Setup a pointer. */ pointer = (CHAR *) first_unused_memory; - + /* Adjust it forward just to make sure there is some space for the test below. */ pointer = pointer + 200; @@ -204,7 +204,7 @@ CHAR *pointer; /* Check status. */ if (status != TX_SUCCESS) { - + printf("Running Trace Basic Test............................................ ERROR #1\n"); test_control_return(1); } @@ -213,7 +213,7 @@ CHAR *pointer; /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + printf("Running Trace Basic Test............................................ ERROR #2\n"); test_control_return(1); } @@ -221,9 +221,9 @@ CHAR *pointer; /* Put system definition stuff in here, e.g. thread creates and other assorted create information. */ - - status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, - pointer, TEST_STACK_SIZE_PRINTF, + + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, TEST_STACK_SIZE_PRINTF, 16, 16, TX_NO_TIME_SLICE, TX_AUTO_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -235,8 +235,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, TEST_STACK_SIZE_PRINTF, 15, 15, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -248,8 +248,8 @@ CHAR *pointer; test_control_return(1); } - status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, - pointer, TEST_STACK_SIZE_PRINTF, + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, TEST_STACK_SIZE_PRINTF, 14, 14, TX_NO_TIME_SLICE, TX_DONT_START); pointer = pointer + TEST_STACK_SIZE_PRINTF; @@ -361,7 +361,7 @@ ULONG object; /* Check status. */ if (status != TX_NOT_DONE) { - + printf("ERROR #6\n"); test_control_return(1); } @@ -370,7 +370,7 @@ ULONG object; /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + printf("ERROR #7\n"); test_control_return(1); } @@ -381,7 +381,7 @@ ULONG object; /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + printf("ERROR #8\n"); test_control_return(1); } @@ -392,7 +392,7 @@ ULONG object; /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + printf("ERROR #9\n"); test_control_return(1); } @@ -403,7 +403,7 @@ ULONG object; /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + printf("ERROR #10\n"); test_control_return(1); } @@ -433,7 +433,7 @@ ULONG object; printf("ERROR #12\n"); test_control_return(1); } - + /* Filter all events. */ status = tx_trace_event_filter(0); @@ -445,7 +445,7 @@ ULONG object; printf("ERROR #13\n"); test_control_return(1); } - + #endif /* Unfilter all events. */ @@ -485,7 +485,7 @@ ULONG object; } #endif - + /* Register the trace buffer full notification routine. */ status = tx_trace_buffer_full_notify(trace_buffer_full); @@ -509,7 +509,7 @@ ULONG object; printf("ERROR #18\n"); test_control_return(1); } - + /* Check the NULL path with trace disabled. */ status = tx_trace_buffer_full_notify(TX_NULL); @@ -521,7 +521,7 @@ ULONG object; printf("ERROR #19\n"); test_control_return(1); } - + #endif /* Create a timer for the test. */ @@ -542,7 +542,7 @@ ULONG object; /* Restore interrupts. */ tx_interrupt_control(old_interrupt); } - + /* Insert user event. */ status = tx_trace_user_event_insert(1027, 1, 2, 3, 4); @@ -629,7 +629,7 @@ ULONG object; break; #endif - } + } /* Clear the ISR. */ test_isr_dispatch = TX_NULL; @@ -661,7 +661,7 @@ ULONG object; /* Attempt to disable again, just to get the TX_NOT_DONE error code. */ status = tx_trace_disable(); - + #ifdef TX_ENABLE_EVENT_TRACE /* Check status. */ @@ -683,7 +683,7 @@ ULONG object; test_control_return(1); } #endif - + /* Attempt to enable event tracing with a bogus size. */ status = tx_trace_enable(trace_buffer, 1, 8); @@ -692,7 +692,7 @@ ULONG object; /* Check status. */ if (status != TX_SIZE_ERROR) { - + /* Trace error. */ printf("ERROR #31\n"); test_control_return(1); @@ -702,7 +702,7 @@ ULONG object; /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Trace error. */ printf("ERROR #32\n"); test_control_return(1); @@ -718,7 +718,7 @@ ULONG object; /* Check status. */ if (status != TX_NOT_DONE) { - + /* Trace error. */ printf("ERROR #33\n"); test_control_return(1); @@ -728,7 +728,7 @@ ULONG object; /* Check status. */ if (status != TX_FEATURE_NOT_ENABLED) { - + /* Trace error. */ printf("ERROR #34\n"); test_control_return(1); @@ -746,7 +746,7 @@ ULONG object; } else { - + /* Successful test. */ printf("SUCCESS!\n"); test_control_return(0); @@ -759,9 +759,9 @@ static void thread_1_entry(ULONG task_input) while(1) { - + thread_1_counter++; - tx_thread_suspend(&thread_1); + tx_thread_suspend(&thread_1); } } @@ -772,8 +772,8 @@ static void thread_2_entry(ULONG task_input) while(1) { - + thread_2_counter++; - tx_thread_suspend(&thread_2); + tx_thread_suspend(&thread_2); } } diff --git a/utility/benchmarks/thread_metric/thread_metric_readme.txt b/utility/benchmarks/thread_metric/thread_metric_readme.txt index 70896efb..044f7ee2 100644 --- a/utility/benchmarks/thread_metric/thread_metric_readme.txt +++ b/utility/benchmarks/thread_metric/thread_metric_readme.txt @@ -1,4 +1,4 @@ - Thread-Metric RTOS Test Suite + Thread-Metric RTOS Test Suite 1. Thread-Metric Test Suite @@ -6,46 +6,46 @@ The Thread-Metric test suite consists of 8 distinct RTOS tests that are designed to highlight commonly used aspects of an RTOS. The test measures the total number of RTOS events -that can be processed during a specific timer interval. A 30 -second time interval is recommended. +that can be processed during a specific timer interval. A 30 +second time interval is recommended. -1.1. Basic Processing Test +1.1. Basic Processing Test -This is the baseline test consisting of a single thread. This -should execute the same on every operating system. Test values -from testing with different RTOS products should be scaled +This is the baseline test consisting of a single thread. This +should execute the same on every operating system. Test values +from testing with different RTOS products should be scaled relative to the difference between the values of this test. 1.2. Cooperative Scheduling Test -This test consists of 5 threads created at the same priority that -voluntarily release control to each other in a round-robin fashion. -Each thread will increment its run counter and then relinquish to -the next thread. At the end of the test the counters will be verified -to make sure they are valid (should all be within 1 of the same -value). If valid, the numbers will be summed and presented as the +This test consists of 5 threads created at the same priority that +voluntarily release control to each other in a round-robin fashion. +Each thread will increment its run counter and then relinquish to +the next thread. At the end of the test the counters will be verified +to make sure they are valid (should all be within 1 of the same +value). If valid, the numbers will be summed and presented as the result of the cooperative scheduling test. 1.3. Preemptive Scheduling Test -This test consists of 5 threads that each have a unique priority. -In this test, all threads except the lowest priority thread are -left in a suspended state. The lowest priority thread will resume -the next highest priority thread. That thread will resume the -next highest priority thread and so on until the highest priority -thread executes. Each thread will increment its run count and then -call thread suspend. Eventually the processing will return to the -lowest priority thread, which is still in the middle of the thread -resume call. Once processing returns to the lowest priority thread, -it will increment its run counter and once again resume the next +This test consists of 5 threads that each have a unique priority. +In this test, all threads except the lowest priority thread are +left in a suspended state. The lowest priority thread will resume +the next highest priority thread. That thread will resume the +next highest priority thread and so on until the highest priority +thread executes. Each thread will increment its run count and then +call thread suspend. Eventually the processing will return to the +lowest priority thread, which is still in the middle of the thread +resume call. Once processing returns to the lowest priority thread, +it will increment its run counter and once again resume the next highest priority thread - starting the whole process over once again. 1.4. Interrupt Processing Test -This test consists of a single thread. The thread will cause an -interrupt (typically implemented as a trap), which will result in -a call to the interrupt handler. The interrupt handler will -increment a counter and then post to a semaphore. After the +This test consists of a single thread. The thread will cause an +interrupt (typically implemented as a trap), which will result in +a call to the interrupt handler. The interrupt handler will +increment a counter and then post to a semaphore. After the interrupt handler completes, processing returns to the test thread that initiated the interrupt. The thread then retrieves the semaphore set by the interrupt handler, increments a counter @@ -54,26 +54,26 @@ and then generates another interrupt. 1.5. Interrupt Preemption Processing Test This test is similar to the previous interrupt test. The big -difference is the interrupt handler in this test resumes a -higher priority thread, which causes thread preemption. +difference is the interrupt handler in this test resumes a +higher priority thread, which causes thread preemption. 1.6. Message Processing Test -This test consists of a thread sending a 16 byte message to a -queue and retrieving the same 16 byte message from the queue. -After the send/receive sequence is complete, the thread will +This test consists of a thread sending a 16 byte message to a +queue and retrieving the same 16 byte message from the queue. +After the send/receive sequence is complete, the thread will increment its run counter. 1.4. Synchronization Processing Test -This test consists of a thread getting a semaphore and then -immediately releasing it. After the get/put cycle completes, +This test consists of a thread getting a semaphore and then +immediately releasing it. After the get/put cycle completes, the thread will increment its run counter. 1.5. RTOS Memory allocation -This test consists of a thread allocating a 128-byte block and -releasing the same block. After the block is released, the thread +This test consists of a thread allocating a 128-byte block and +releasing the same block. After the block is released, the thread will increment its run counter. @@ -104,8 +104,8 @@ tm_message_processing_test.c Message exchange processing test tm_synchronization_processing_test.c Semaphore get/put processing test tm_memory_allocation_test.c Basic memory allocation test tm_porting_layer.h Port specific information, including - in-line assembly instruction to - cause an interrupt for the + in-line assembly instruction to + cause an interrupt for the interrupt processing tests tm_porting_layer_template.c Generic template for RTOS porting layer @@ -114,93 +114,93 @@ tm_porting_layer_threadx.c Specific porting layer source 2.1 Porting Layer -As for the porting layer defined in tm_porting_layer_template.c, this file contain -shell services of the generic RTOS services used by the actual tests. The -shell services provide the mapping between the tests and the underlying RTOS. -The following generic API's are required to map any RTOS to the performance +As for the porting layer defined in tm_porting_layer_template.c, this file contain +shell services of the generic RTOS services used by the actual tests. The +shell services provide the mapping between the tests and the underlying RTOS. +The following generic API's are required to map any RTOS to the performance measurement tests: void tm_initialize(void (*test_initialization_function)(void)); - This function is typically called by the application from its - main() function. It is responsible for providing all the RTOS - initialization, calling the test initialization function as + This function is typically called by the application from its + main() function. It is responsible for providing all the RTOS + initialization, calling the test initialization function as specified, and then starting the RTOS. int tm_thread_create(int thread_id, int priority, void (*entry_function)(void)); - This function creates a thread of the specified priority where 1 is - the highest and 16 is the lowest. If successful, TM_SUCCESS - returned. If an error occurs, TM_ERROR is returned. The created thread + This function creates a thread of the specified priority where 1 is + the highest and 16 is the lowest. If successful, TM_SUCCESS + returned. If an error occurs, TM_ERROR is returned. The created thread is not started. int tm_thread_resume(int thread_id); - This function resumes the previously created thread specified by + This function resumes the previously created thread specified by thread_id. If successful, a TM_SUCCESS is returned. int tm_thread_suspend(int thread_id); - This function suspend the previously created thread specified by + This function suspend the previously created thread specified by thread_id. If successful, a TM_SUCCESS is returned. void tm_thread_relinquish(void); - This function lets all other threads of same priority execute + This function lets all other threads of same priority execute before the calling thread runs again. void tm_thread_sleep(int seconds); - This function suspends the calling thread for the specified + This function suspends the calling thread for the specified number of seconds. int tm_queue_create(int queue_id); - This function creates a queue with a capacity to hold at least + This function creates a queue with a capacity to hold at least one 16-byte message. If successful, a TM_SUCCESS is returned. int tm_queue_send(int queue_id, unsigned long *message_ptr); - This function sends a message to the previously created queue. + This function sends a message to the previously created queue. If successful, a TM_SUCCESS is returned. int tm_queue_receive(int queue_id, unsigned long *message_ptr); - This function receives a message from the previously created + This function receives a message from the previously created queue. If successful, a TM_SUCCESS is returned. int tm_semaphore_create(int semaphore_id); - This function creates a binary semaphore. If successful, a + This function creates a binary semaphore. If successful, a TM_SUCCESS is returned. int tm_semaphore_get(int semaphore_id); - This function gets the previously created binary semaphore. + This function gets the previously created binary semaphore. If successful, a TM_SUCCESS is returned. int tm_semaphore_put(int semaphore_id); - This function puts the previously created binary semaphore. + This function puts the previously created binary semaphore. If successful, a TM_SUCCESS is returned. int tm_memory_pool_create(int pool_id); - This function creates a memory pool able to satisfy at least one + This function creates a memory pool able to satisfy at least one 128-byte block of memory. If successful, a TM_SUCCESS is returned. int tm_memory_pool_allocate(int pool_id, unsigned char **memory_ptr); - This function allocates a 128-byte block of memory from the - previously created memory pool. If successful, a TM_SUCCESS - is returned along with the pointer to the allocated memory + This function allocates a 128-byte block of memory from the + previously created memory pool. If successful, a TM_SUCCESS + is returned along with the pointer to the allocated memory in the "memory_ptr" variable. int tm_memory_pool_deallocate(int pool_id, unsigned char *memory_ptr); - This function releases the previously allocated 128-byte block - of memory. If successful, a TM_SUCCESS is returned. + This function releases the previously allocated 128-byte block + of memory. If successful, a TM_SUCCESS is returned. 2.2 Porting Requirements @@ -208,20 +208,20 @@ measurement tests: The following requirements are made in order to ensure fair benchmarks are achieved on each RTOS performing the test: - 1. Time period should be 30 seconds. This will ensure the printf + 1. Time period should be 30 seconds. This will ensure the printf processing in the reporting thread is insignificant. - 2. The porting layer services are implemented inside of + 2. The porting layer services are implemented inside of tm_porting_layer_[RTOS].c and NOT as macros. 3. The tm_thread_sleep service is implemented by a 10ms RTOS periodic interrupt source. - 4. Locking regions of the tests and/or the RTOS in cache is + 4. Locking regions of the tests and/or the RTOS in cache is not allowed. 5. The Interrupt Processing and Interrupt Preemption Processing tests - require an instruction that generates an interrupt. Please refer - to tm_porting_layer.h for an example implementation. + require an instruction that generates an interrupt. Please refer + to tm_porting_layer.h for an example implementation. diff --git a/utility/benchmarks/thread_metric/threadx_example/tm_porting_layer_threadx.c b/utility/benchmarks/thread_metric/threadx_example/tm_porting_layer_threadx.c index 405d9223..7490da44 100644 --- a/utility/benchmarks/thread_metric/threadx_example/tm_porting_layer_threadx.c +++ b/utility/benchmarks/thread_metric/threadx_example/tm_porting_layer_threadx.c @@ -1,16 +1,17 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** Thread-Metric Component */ /** */ /** Porting Layer (ThreadX Example) */ @@ -26,7 +27,7 @@ #endif -/* For smallest size, the ThreadX library and application code should be built +/* For smallest size, the ThreadX library and application code should be built with the following options defined (easiest to add in tx_port.h): #define TX_ENABLE_EXECUTION_CHANGE_NOTIFY @@ -110,7 +111,7 @@ void (*tm_initialization_function)(void); VOID tm_thread_entry(ULONG thread_input); -/* This function called from main performs basic RTOS initialization, +/* This function called from main performs basic RTOS initialization, calls the test initialization function, and then starts the RTOS function. */ void tm_initialize(void (*test_initialization_function)(void)) { @@ -119,13 +120,13 @@ void tm_initialize(void (*test_initialization_function)(void)) tm_initialization_function = test_initialization_function; /* Call the previously defined initialization function. */ - (tm_initialization_function)(); + (tm_initialization_function)(); } /* This function takes a thread ID and priority and attempts to create the - file in the underlying RTOS. Valid priorities range from 1 through 31, - where 1 is the highest priority and 31 is the lowest. If successful, + file in the underlying RTOS. Valid priorities range from 1 through 31, + where 1 is the highest priority and 31 is the lowest. If successful, the function should return TM_SUCCESS. Otherwise, TM_ERROR should be returned. */ int tm_thread_create(int thread_id, int priority, void (*entry_function)(void)) { @@ -197,7 +198,7 @@ void tm_thread_relinquish(void) /* This function suspends the specified thread for the specified number - of seconds. If successful, the function should return TM_SUCCESS. + of seconds. If successful, the function should return TM_SUCCESS. Otherwise, TM_ERROR should be returned. */ void tm_thread_sleep(int seconds) { @@ -216,7 +217,7 @@ UINT status; /* Create the specified queue with 16-byte messages. */ - status = tx_queue_create(&tm_queue_array[queue_id], "Thread-Metric test", TX_4_ULONG, + status = tx_queue_create(&tm_queue_array[queue_id], "Thread-Metric test", TX_4_ULONG, &tm_queue_memory_area[queue_id*TM_THREADX_QUEUE_SIZE], TM_THREADX_QUEUE_SIZE); /* Determine if the queue create was successful. */ @@ -227,7 +228,7 @@ UINT status; } -/* This function sends a 16-byte message to the specified queue. If successful, +/* This function sends a 16-byte message to the specified queue. If successful, the function should return TM_SUCCESS. Otherwise, TM_ERROR should be returned. */ int tm_queue_send(int queue_id, unsigned long *message_ptr) { @@ -246,7 +247,7 @@ UINT status; } -/* This function receives a 16-byte message from the specified queue. If successful, +/* This function receives a 16-byte message from the specified queue. If successful, the function should return TM_SUCCESS. Otherwise, TM_ERROR should be returned. */ int tm_queue_receive(int queue_id, unsigned long *message_ptr) { @@ -342,8 +343,8 @@ UINT status; } -/* This function allocates a 128 byte block from the specified memory pool. - If successful, the function should return TM_SUCCESS. Otherwise, TM_ERROR +/* This function allocates a 128 byte block from the specified memory pool. + If successful, the function should return TM_SUCCESS. Otherwise, TM_ERROR should be returned. */ int tm_memory_pool_allocate(int pool_id, unsigned char **memory_ptr) { @@ -362,8 +363,8 @@ UINT status; } -/* This function releases a previously allocated 128 byte block from the specified - memory pool. If successful, the function should return TM_SUCCESS. Otherwise, TM_ERROR +/* This function releases a previously allocated 128 byte block from the specified + memory pool. If successful, the function should return TM_SUCCESS. Otherwise, TM_ERROR should be returned. */ int tm_memory_pool_deallocate(int pool_id, unsigned char *memory_ptr) { diff --git a/utility/benchmarks/thread_metric/tm_api.h b/utility/benchmarks/thread_metric/tm_api.h index 85c8982c..74ac6b11 100644 --- a/utility/benchmarks/thread_metric/tm_api.h +++ b/utility/benchmarks/thread_metric/tm_api.h @@ -1,16 +1,17 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** Thread-Metric Component */ /** */ /** Application Interface (API) */ @@ -19,31 +20,25 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* APPLICATION INTERFACE DEFINITION RELEASE */ -/* */ -/* tm_api.h PORTABLE C */ -/* 6.1.7 */ -/* AUTHOR */ -/* */ -/* William E. Lamie, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This file defines the basic Application Interface (API) */ +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* tm_api.h PORTABLE C */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic Application Interface (API) */ /* implementation source code for the Thread-Metrics performance */ /* test suite. All service prototypes and data structure definitions */ -/* are defined in this file. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ -/**************************************************************************/ - +/* are defined in this file. */ +/* */ +/**************************************************************************/ + #ifndef TM_API_H #define TM_API_H diff --git a/utility/benchmarks/thread_metric/tm_basic_processing_test.c b/utility/benchmarks/thread_metric/tm_basic_processing_test.c index 27f3e48e..f1c4fa22 100644 --- a/utility/benchmarks/thread_metric/tm_basic_processing_test.c +++ b/utility/benchmarks/thread_metric/tm_basic_processing_test.c @@ -1,16 +1,17 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** Thread-Metric Component */ /** */ /** Basic Processing Test */ @@ -19,28 +20,22 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* tm_basic_processing_test PORTABLE C */ -/* 6.1.7 */ -/* AUTHOR */ -/* */ -/* William E. Lamie, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* tm_basic_processing_test PORTABLE C */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ /* This file defines the basic test for determining board processing */ /* capabilities */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ -/**************************************************************************/ +/* */ +/**************************************************************************/ #include "tm_api.h" @@ -49,8 +44,8 @@ unsigned long tm_basic_processing_counter; -/* Test array. We will just do a series of calculations on the - test array to eat up processing bandwidth. The idea is that +/* Test array. We will just do a series of calculations on the + test array to eat up processing bandwidth. The idea is that all RTOSes should produce the same metric here if everything else is equal, e.g. processor speed, memory speed, etc. */ @@ -92,7 +87,7 @@ void tm_basic_processing_initialize(void) /* Resume thread 0. */ tm_thread_resume(0); - /* Create the reporting thread. It will preempt the other + /* Create the reporting thread. It will preempt the other threads and print out the test results. */ tm_thread_create(5, 2, tm_basic_processing_thread_report); tm_thread_resume(5); @@ -116,9 +111,9 @@ int i; while(1) { - /* Loop through the basic processing array, add the previous + /* Loop through the basic processing array, add the previous contents with the contents of the tm_basic_processing_counter - and xor the result with the previous value... just to eat + and xor the result with the previous value... just to eat up some time. */ for (i = 0; i < 1024; i++) { diff --git a/utility/benchmarks/thread_metric/tm_cooperative_scheduling_test.c b/utility/benchmarks/thread_metric/tm_cooperative_scheduling_test.c index b444c723..31d18c18 100644 --- a/utility/benchmarks/thread_metric/tm_cooperative_scheduling_test.c +++ b/utility/benchmarks/thread_metric/tm_cooperative_scheduling_test.c @@ -1,16 +1,17 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** Thread-Metric Component */ /** */ /** Cooperative Scheduling Test */ @@ -18,27 +19,21 @@ /**************************************************************************/ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* tm_cooperative_scheduling_test PORTABLE C */ -/* 6.1.7 */ -/* AUTHOR */ -/* */ -/* William E. Lamie, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* tm_cooperative_scheduling_test PORTABLE C */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ /* This file defines the cooperative scheduling test. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ -/**************************************************************************/ +/* */ +/**************************************************************************/ #include "tm_api.h" @@ -99,7 +94,7 @@ void tm_cooperative_scheduling_initialize(void) tm_thread_resume(3); tm_thread_resume(4); - /* Create the reporting thread. It will preempt the other + /* Create the reporting thread. It will preempt the other threads and print out the test results. */ tm_thread_create(5, 2, tm_cooperative_thread_report); tm_thread_resume(5); @@ -112,7 +107,7 @@ void tm_cooperative_thread_0_entry(void) while(1) { - + /* Relinquish to all other threads at same priority. */ tm_thread_relinquish(); @@ -217,7 +212,7 @@ unsigned long average; /* Calculate the average of all the counters. */ average = total/5; - + /* WCC - integrity check */ printf("tm_cooperative_thread_0_counter: %d\n", tm_cooperative_thread_0_counter); printf("tm_cooperative_thread_1_counter: %d\n", tm_cooperative_thread_1_counter); @@ -226,15 +221,15 @@ unsigned long average; printf("tm_cooperative_thread_4_counter: %d\n", tm_cooperative_thread_4_counter); /* See if there are any errors. */ - if ((tm_cooperative_thread_0_counter < (average - 1)) || + if ((tm_cooperative_thread_0_counter < (average - 1)) || (tm_cooperative_thread_0_counter > (average + 1)) || - (tm_cooperative_thread_1_counter < (average - 1)) || + (tm_cooperative_thread_1_counter < (average - 1)) || (tm_cooperative_thread_1_counter > (average + 1)) || - (tm_cooperative_thread_2_counter < (average - 1)) || + (tm_cooperative_thread_2_counter < (average - 1)) || (tm_cooperative_thread_2_counter > (average + 1)) || - (tm_cooperative_thread_3_counter < (average - 1)) || + (tm_cooperative_thread_3_counter < (average - 1)) || (tm_cooperative_thread_3_counter > (average + 1)) || - (tm_cooperative_thread_4_counter < (average - 1)) || + (tm_cooperative_thread_4_counter < (average - 1)) || (tm_cooperative_thread_4_counter > (average + 1))) { diff --git a/utility/benchmarks/thread_metric/tm_interrupt_preemption_processing_test.c b/utility/benchmarks/thread_metric/tm_interrupt_preemption_processing_test.c index 3ed64a78..5b6aeec2 100644 --- a/utility/benchmarks/thread_metric/tm_interrupt_preemption_processing_test.c +++ b/utility/benchmarks/thread_metric/tm_interrupt_preemption_processing_test.c @@ -1,16 +1,17 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** Thread-Metric Component */ /** */ /** Interrupt Preemption Processing Test */ @@ -19,27 +20,21 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* tm_interrupt_preemption_processing_test PORTABLE C */ -/* 6.1.7 */ -/* AUTHOR */ -/* */ -/* William E. Lamie, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* tm_interrupt_preemption_processing_test PORTABLE C */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ /* This file defines the preemptive scheduling test. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ -/**************************************************************************/ +/* */ +/**************************************************************************/ #include "tm_api.h" @@ -97,14 +92,14 @@ void tm_interrupt_preemption_processing_initialize(void) /* Resume just thread 1. */ tm_thread_resume(1); - /* Create the reporting thread. It will preempt the other + /* Create the reporting thread. It will preempt the other threads and print out the test results. */ tm_thread_create(5, 2, tm_interrupt_preemption_thread_report); tm_thread_resume(5); } -/* Define the interrupt thread. This thread is resumed from the +/* Define the interrupt thread. This thread is resumed from the interrupt handler. It runs and suspends. */ void tm_interrupt_preemption_thread_0_entry(void) { @@ -115,7 +110,7 @@ void tm_interrupt_preemption_thread_0_entry(void) /* Increment this thread's counter. */ tm_interrupt_preemption_thread_0_counter++; - /* Suspend. This will allow the thread generating the + /* Suspend. This will allow the thread generating the interrupt to run again. */ tm_thread_suspend(0); } @@ -128,7 +123,7 @@ void tm_interrupt_preemption_thread_1_entry(void) while(1) { - /* Force an interrupt. The underlying RTOS must see that the + /* Force an interrupt. The underlying RTOS must see that the the interrupt handler is called from the appropriate software interrupt or trap. */ TM_CAUSE_INTERRUPT @@ -192,11 +187,11 @@ unsigned long average; average = total/3; /* See if there are any errors. */ - if ((tm_interrupt_preemption_thread_0_counter < (average - 1)) || + if ((tm_interrupt_preemption_thread_0_counter < (average - 1)) || (tm_interrupt_preemption_thread_0_counter > (average + 1)) || - (tm_interrupt_preemption_thread_1_counter < (average - 1)) || + (tm_interrupt_preemption_thread_1_counter < (average - 1)) || (tm_interrupt_preemption_thread_1_counter > (average + 1)) || - (tm_interrupt_preemption_handler_counter < (average - 1)) || + (tm_interrupt_preemption_handler_counter < (average - 1)) || (tm_interrupt_preemption_handler_counter > (average + 1))) { diff --git a/utility/benchmarks/thread_metric/tm_interrupt_processing_test.c b/utility/benchmarks/thread_metric/tm_interrupt_processing_test.c index 6591593e..69d156d9 100644 --- a/utility/benchmarks/thread_metric/tm_interrupt_processing_test.c +++ b/utility/benchmarks/thread_metric/tm_interrupt_processing_test.c @@ -1,16 +1,17 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** Thread-Metric Component */ /** */ /** Interrupt Processing Test */ @@ -18,27 +19,21 @@ /**************************************************************************/ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* tm_interrupt_processing_test PORTABLE C */ -/* 6.1.7 */ -/* AUTHOR */ -/* */ -/* William E. Lamie, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* tm_interrupt_processing_test PORTABLE C */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ /* This file defines the No-preemption interrupt processing test. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ -/**************************************************************************/ +/* */ +/**************************************************************************/ #include "tm_api.h" @@ -87,14 +82,14 @@ void tm_interrupt_processing_initialize(void) /* Create thread that generates the interrupt at priority 10. */ tm_thread_create(0, 10, tm_interrupt_thread_0_entry); - /* Create a semaphore that will be posted from the interrupt + /* Create a semaphore that will be posted from the interrupt handler. */ tm_semaphore_create(0); /* Resume just thread 0. */ tm_thread_resume(0); - /* Create the reporting thread. It will preempt the other + /* Create the reporting thread. It will preempt the other threads and print out the test results. */ tm_thread_create(5, 2, tm_interrupt_thread_report); tm_thread_resume(5); @@ -118,13 +113,13 @@ int status; while(1) { - /* Force an interrupt. The underlying RTOS must see that the + /* Force an interrupt. The underlying RTOS must see that the the interrupt handler is called from the appropriate software interrupt or trap. */ TM_CAUSE_INTERRUPT /* We won't get back here until the interrupt processing is complete, - including the setting of the semaphore from the interrupt + including the setting of the semaphore from the interrupt handler. */ /* Pickup the semaphore set by the interrupt handler. */ @@ -189,9 +184,9 @@ unsigned long average; average = total/2; /* See if there are any errors. */ - if ((tm_interrupt_thread_0_counter < (average - 1)) || + if ((tm_interrupt_thread_0_counter < (average - 1)) || (tm_interrupt_thread_0_counter > (average + 1)) || - (tm_interrupt_handler_counter < (average - 1)) || + (tm_interrupt_handler_counter < (average - 1)) || (tm_interrupt_handler_counter > (average + 1))) { diff --git a/utility/benchmarks/thread_metric/tm_memory_allocation_test.c b/utility/benchmarks/thread_metric/tm_memory_allocation_test.c index 9e88861f..fc1c40d7 100644 --- a/utility/benchmarks/thread_metric/tm_memory_allocation_test.c +++ b/utility/benchmarks/thread_metric/tm_memory_allocation_test.c @@ -1,16 +1,17 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** Thread-Metric Component */ /** */ /** Memory Allocation Test */ @@ -18,27 +19,21 @@ /**************************************************************************/ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* tm_memory_allocation_test PORTABLE C */ -/* 6.1.7 */ -/* AUTHOR */ -/* */ -/* William E. Lamie, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* tm_memory_allocation_test PORTABLE C */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ /* This file defines the Message exchange processing test. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ -/**************************************************************************/ +/* */ +/**************************************************************************/ #include "tm_api.h" @@ -86,7 +81,7 @@ void tm_memory_allocation_initialize(void) /* Create a memory pool. */ tm_memory_pool_create(0); - /* Create the reporting thread. It will preempt the other + /* Create the reporting thread. It will preempt the other threads and print out the test results. */ tm_thread_create(5, 2, tm_memory_allocation_thread_report); tm_thread_resume(5); diff --git a/utility/benchmarks/thread_metric/tm_message_processing_test.c b/utility/benchmarks/thread_metric/tm_message_processing_test.c index c709252b..f82da79e 100644 --- a/utility/benchmarks/thread_metric/tm_message_processing_test.c +++ b/utility/benchmarks/thread_metric/tm_message_processing_test.c @@ -1,16 +1,17 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** Thread-Metric Component */ /** */ /** Message Processing Test */ @@ -19,27 +20,21 @@ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* FUCTION RELEASE */ -/* */ -/* tm_message_processing_test PORTABLE C */ -/* 6.1.7 */ -/* AUTHOR */ -/* */ -/* William E. Lamie, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ +/**************************************************************************/ +/* */ +/* FUCTION RELEASE */ +/* */ +/* tm_message_processing_test PORTABLE C */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ /* Basic test for message exchange processing. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ -/**************************************************************************/ +/* */ +/**************************************************************************/ #include "tm_api.h" @@ -89,7 +84,7 @@ void tm_message_processing_initialize(void) /* Create a queue for the message passing. */ tm_queue_create(0); - /* Create the reporting thread. It will preempt the other + /* Create the reporting thread. It will preempt the other threads and print out the test results. */ tm_thread_create(5, 2, tm_message_processing_thread_report); tm_thread_resume(5); @@ -107,7 +102,7 @@ void tm_message_processing_thread_0_entry(void) tm_message_sent[3] = 0x77778888; while(1) - { + { /* Send a message to the queue. */ tm_queue_send(0, tm_message_sent); diff --git a/utility/benchmarks/thread_metric/tm_porting_layer.h b/utility/benchmarks/thread_metric/tm_porting_layer.h index 3e9e2d63..ec1b7a26 100644 --- a/utility/benchmarks/thread_metric/tm_porting_layer.h +++ b/utility/benchmarks/thread_metric/tm_porting_layer.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -14,9 +15,9 @@ #include -/* Define the TRAP instruction. This is used by the Interrupt Processing and Interrupt Preemption Processing tests. - The SVC instruction below is for Cortex-M architectures using IAR tools. This will likely need to be modified - for different processors and/or development tools. +/* Define the TRAP instruction. This is used by the Interrupt Processing and Interrupt Preemption Processing tests. + The SVC instruction below is for Cortex-M architectures using IAR tools. This will likely need to be modified + for different processors and/or development tools. Note also that for the Interrupt Processing test there is the assumption that the SVC ISR looks like: diff --git a/utility/benchmarks/thread_metric/tm_porting_layer_template.c b/utility/benchmarks/thread_metric/tm_porting_layer_template.c index c0460802..fcbc59a8 100644 --- a/utility/benchmarks/thread_metric/tm_porting_layer_template.c +++ b/utility/benchmarks/thread_metric/tm_porting_layer_template.c @@ -1,16 +1,17 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** Thread-Metric Component */ /** */ /** Porting Layer (Must be completed with RTOS specifics) */ @@ -24,7 +25,7 @@ #include "tm_api.h" -/* This function called from main performs basic RTOS initialization, +/* This function called from main performs basic RTOS initialization, calls the test initialization function, and then starts the RTOS function. */ void tm_initialize(void (*test_initialization_function)(void)) { @@ -33,8 +34,8 @@ void tm_initialize(void (*test_initialization_function)(void)) /* This function takes a thread ID and priority and attempts to create the - file in the underlying RTOS. Valid priorities range from 1 through 31, - where 1 is the highest priority and 31 is the lowest. If successful, + file in the underlying RTOS. Valid priorities range from 1 through 31, + where 1 is the highest priority and 31 is the lowest. If successful, the function should return TM_SUCCESS. Otherwise, TM_ERROR should be returned. */ int tm_thread_create(int thread_id, int priority, void (*entry_function)(void)) { @@ -67,7 +68,7 @@ void tm_thread_relinquish(void) /* This function suspends the specified thread for the specified number - of seconds. If successful, the function should return TM_SUCCESS. + of seconds. If successful, the function should return TM_SUCCESS. Otherwise, TM_ERROR should be returned. */ void tm_thread_sleep(int seconds) { @@ -83,7 +84,7 @@ int tm_queue_create(int queue_id) } -/* This function sends a 16-byte message to the specified queue. If successful, +/* This function sends a 16-byte message to the specified queue. If successful, the function should return TM_SUCCESS. Otherwise, TM_ERROR should be returned. */ int tm_queue_send(int queue_id, unsigned long *message_ptr) { @@ -91,7 +92,7 @@ int tm_queue_send(int queue_id, unsigned long *message_ptr) } -/* This function receives a 16-byte message from the specified queue. If successful, +/* This function receives a 16-byte message from the specified queue. If successful, the function should return TM_SUCCESS. Otherwise, TM_ERROR should be returned. */ int tm_queue_receive(int queue_id, unsigned long *message_ptr) { @@ -132,8 +133,8 @@ int tm_memory_pool_create(int pool_id) } -/* This function allocates a 128 byte block from the specified memory pool. - If successful, the function should return TM_SUCCESS. Otherwise, TM_ERROR +/* This function allocates a 128 byte block from the specified memory pool. + If successful, the function should return TM_SUCCESS. Otherwise, TM_ERROR should be returned. */ int tm_memory_pool_allocate(int pool_id, unsigned char **memory_ptr) { @@ -141,8 +142,8 @@ int tm_memory_pool_allocate(int pool_id, unsigned char **memory_ptr) } -/* This function releases a previously allocated 128 byte block from the specified - memory pool. If successful, the function should return TM_SUCCESS. Otherwise, TM_ERROR +/* This function releases a previously allocated 128 byte block from the specified + memory pool. If successful, the function should return TM_SUCCESS. Otherwise, TM_ERROR should be returned. */ int tm_memory_pool_deallocate(int pool_id, unsigned char *memory_ptr) { diff --git a/utility/benchmarks/thread_metric/tm_preemptive_scheduling_test.c b/utility/benchmarks/thread_metric/tm_preemptive_scheduling_test.c index 95ee4be8..ef3222f3 100644 --- a/utility/benchmarks/thread_metric/tm_preemptive_scheduling_test.c +++ b/utility/benchmarks/thread_metric/tm_preemptive_scheduling_test.c @@ -1,16 +1,17 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** Thread-Metric Component */ /** */ /** Preemptive Scheduling Test */ @@ -18,27 +19,21 @@ /**************************************************************************/ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* tm_preemptive_scheduling_test PORTABLE C */ -/* 6.1.7 */ -/* AUTHOR */ -/* */ -/* William E. Lamie, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* tm_preemptive_scheduling_test PORTABLE C */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ /* This file defines the preemptive scheduling test. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ -/**************************************************************************/ +/* */ +/**************************************************************************/ #include "tm_api.h" @@ -103,7 +98,7 @@ void tm_preemptive_scheduling_initialize(void) /* Resume just thread 0. */ tm_thread_resume(0); - /* Create the reporting thread. It will preempt the other + /* Create the reporting thread. It will preempt the other threads and print out the test results. */ tm_thread_create(5, 2, tm_preemptive_thread_report); tm_thread_resume(5); @@ -245,15 +240,15 @@ unsigned long average; average = total/5; /* See if there are any errors. */ - if ((tm_preemptive_thread_0_counter < (average - 1)) || + if ((tm_preemptive_thread_0_counter < (average - 1)) || (tm_preemptive_thread_0_counter > (average + 1)) || - (tm_preemptive_thread_1_counter < (average - 1)) || + (tm_preemptive_thread_1_counter < (average - 1)) || (tm_preemptive_thread_1_counter > (average + 1)) || - (tm_preemptive_thread_2_counter < (average - 1)) || + (tm_preemptive_thread_2_counter < (average - 1)) || (tm_preemptive_thread_2_counter > (average + 1)) || - (tm_preemptive_thread_3_counter < (average - 1)) || + (tm_preemptive_thread_3_counter < (average - 1)) || (tm_preemptive_thread_3_counter > (average + 1)) || - (tm_preemptive_thread_4_counter < (average - 1)) || + (tm_preemptive_thread_4_counter < (average - 1)) || (tm_preemptive_thread_4_counter > (average + 1))) { diff --git a/utility/benchmarks/thread_metric/tm_synchronization_processing_test.c b/utility/benchmarks/thread_metric/tm_synchronization_processing_test.c index 103ad7ea..6fa2a187 100644 --- a/utility/benchmarks/thread_metric/tm_synchronization_processing_test.c +++ b/utility/benchmarks/thread_metric/tm_synchronization_processing_test.c @@ -1,16 +1,17 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ +/** */ /** Thread-Metric Component */ /** */ /** Synchronization Processing Test */ @@ -18,27 +19,21 @@ /**************************************************************************/ /**************************************************************************/ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* tm_synchronization_processing_test PORTABLE C */ -/* 6.1.7 */ -/* AUTHOR */ -/* */ -/* William E. Lamie, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* tm_synchronization_processing_test PORTABLE C */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ /* This file defines the Semaphore get/put processing test. */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 10-15-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ -/**************************************************************************/ +/* */ +/**************************************************************************/ #include "tm_api.h" @@ -86,7 +81,7 @@ void tm_synchronization_processing_initialize(void) /* Create a semaphore for the test. */ tm_semaphore_create(0); - /* Create the reporting thread. It will preempt the other + /* Create the reporting thread. It will preempt the other threads and print out the test results. */ tm_thread_create(5, 2, tm_synchronization_processing_thread_report); tm_thread_resume(5); diff --git a/utility/execution_profile_kit/smp_version/tx_execution_profile.c b/utility/execution_profile_kit/smp_version/tx_execution_profile.c index 3b5c05a2..735dbf14 100644 --- a/utility/execution_profile_kit/smp_version/tx_execution_profile.c +++ b/utility/execution_profile_kit/smp_version/tx_execution_profile.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -27,44 +28,44 @@ #include "tx_api.h" #include "tx_execution_profile.h" -/* The thread execution profile kit is designed to track thread execution time - based on the hardware timer defined by TX_EXECUTION_TIME_SOURCE and - TX_EXECUTION_MAX_TIME_SOURCE below. When the thread's total time reaches +/* The thread execution profile kit is designed to track thread execution time + based on the hardware timer defined by TX_EXECUTION_TIME_SOURCE and + TX_EXECUTION_MAX_TIME_SOURCE below. When the thread's total time reaches the maximum value, it remains there until the time is reset to 0 via a call - to tx_thread_execution_time_reset. There are several assumptions to the + to tx_thread_execution_time_reset. There are several assumptions to the operation of this kit, as follows: 1. In tx_port.h replace: - - #define TX_THREAD_EXTENSION_3" - + + #define TX_THREAD_EXTENSION_3" + with: - + #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long tx_thread_execution_time_last_start; - + unsigned long tx_thread_execution_time_last_start; + Note: if 64-bit time source is present, the tx_thread_execution_time_last_start type should be unsigned long long. - 2. The TX_EXECUTION_TIME_SOURCE and TX_EXECUTION_MAX_TIME_SOURCE macros are + 2. The TX_EXECUTION_TIME_SOURCE and TX_EXECUTION_MAX_TIME_SOURCE macros are defined to utilize a local hardware time source. - + 3. ThreadX 5.4 (or later) is being used, with the assembly code enabled to call the following routines from assembly code: - + VOID _tx_execution_thread_enter(void); VOID _tx_execution_thread_exit(void); VOID _tx_execution_isr_enter(void); VOID _tx_execution_isr_exit(void); - - 4. The ThreadX library assembly code must be rebuilt with TX_ENABLE_EXECUTION_CHANGE_NOTIFY so - that these macros are expanded in the TX_THREAD structure and so the assembly code macros - are enabled to call the execution profile routines. + + 4. The ThreadX library assembly code must be rebuilt with TX_ENABLE_EXECUTION_CHANGE_NOTIFY so + that these macros are expanded in the TX_THREAD structure and so the assembly code macros + are enabled to call the execution profile routines. 5. Add tx_execution_profile.c to the application build. */ /* Externally reference several internal ThreadX variables. */ - + extern ULONG _tx_thread_system_state[TX_THREAD_SMP_MAX_CORES]; extern UINT _tx_thread_preempt_disable; extern TX_THREAD *_tx_thread_current_ptr[TX_THREAD_SMP_MAX_CORES]; @@ -83,11 +84,11 @@ EXECUTION_TIME _tx_execution_thread_time_total[TX_THREAD_SM and _tx_thread_context_restore are tracked by this utility. */ EXECUTION_TIME _tx_execution_isr_time_total[TX_THREAD_SMP_MAX_CORES]; -EXECUTION_TIME_SOURCE_TYPE _tx_execution_isr_time_last_start[TX_THREAD_SMP_MAX_CORES]; +EXECUTION_TIME_SOURCE_TYPE _tx_execution_isr_time_last_start[TX_THREAD_SMP_MAX_CORES]; /* Define the system idle time gathering information. For idle time that exceeds the range of the timer - source, another timer source may be needed. In addition, the total thread execution time added to the + source, another timer source may be needed. In addition, the total thread execution time added to the total ISR time, less the total system time is also a measure of idle time. */ EXECUTION_TIME _tx_execution_idle_time_total[TX_THREAD_SMP_MAX_CORES]; @@ -124,12 +125,6 @@ EXECUTION_TIME_SOURCE_TYPE _tx_execution_idle_time_last_start[TX_THREAD /* */ /* _tx_thread_schedule Thread scheduling */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 07-29-2022 William E. Lamie Initial Version 6.1.12 */ -/* */ /**************************************************************************/ VOID _tx_execution_thread_enter(void) { @@ -155,10 +150,10 @@ UINT core; /* This thread is being scheduled. Simply setup the last start time in the thread control block. */ thread_ptr -> tx_thread_execution_time_last_start = current_time; - + /* Pickup the last idle start time. */ last_start_time = _tx_execution_idle_time_last_start[core]; - + /* Determine if idle time is being measured. */ if (last_start_time) { @@ -166,34 +161,34 @@ UINT core; /* Determine how to calculate the difference. */ if (current_time >= last_start_time) { - + /* Simply subtract. */ delta_time = (EXECUTION_TIME) (current_time - last_start_time); - } + } else { - + /* Timer wrapped, compute the delta assuming incrementing time counter. */ delta_time = (EXECUTION_TIME) (current_time + (((EXECUTION_TIME_SOURCE_TYPE) TX_EXECUTION_MAX_TIME_SOURCE) - last_start_time)); } - + /* Pickup the total time. */ total_time = _tx_execution_idle_time_total[core]; /* Now compute the new total time. */ new_total_time = total_time + delta_time; - + /* Determine if a rollover on the total time is present. */ if (new_total_time < total_time) { - + /* Rollover. Set the total time to max value. */ new_total_time = (EXECUTION_TIME) TX_EXECUTION_MAX_TIME_SOURCE; } - + /* Now store back the total idle time. */ - _tx_execution_idle_time_total[core] = new_total_time; - + _tx_execution_idle_time_total[core] = new_total_time; + /* Disable the idle time measurement. */ _tx_execution_idle_time_last_start[core] = 0; } @@ -258,7 +253,7 @@ UINT core; /* Determine if there is a thread. */ if (thread_ptr) { - + /* Pickup the current time. */ current_time = TX_EXECUTION_TIME_SOURCE; @@ -271,17 +266,17 @@ UINT core; /* Clear the last start time. */ thread_ptr -> tx_thread_execution_time_last_start = 0; - + /* Determine how to calculate the difference. */ if (current_time >= last_start_time) { - + /* Simply subtract. */ delta_time = (EXECUTION_TIME) (current_time - last_start_time); - } + } else { - + /* Timer wrapped, compute the delta assuming incrementing time counter. */ delta_time = (EXECUTION_TIME) (current_time + (((EXECUTION_TIME_SOURCE_TYPE) TX_EXECUTION_MAX_TIME_SOURCE) - last_start_time)); } @@ -291,37 +286,37 @@ UINT core; /* Now compute the new total time. */ new_total_time = total_time + delta_time; - + /* Determine if a rollover on the total time is present. */ if (new_total_time < total_time) { - + /* Rollover. Set the total time to max value. */ new_total_time = (EXECUTION_TIME) TX_EXECUTION_MAX_TIME_SOURCE; } - + /* Store back the new total time. */ thread_ptr -> tx_thread_execution_time_total = new_total_time; - + /* Now accumulate this thread's execution time into the total thread execution time. */ new_total_time = _tx_execution_thread_time_total[core] + delta_time; - + /* Determine if a rollover on the total time is present. */ if (new_total_time < _tx_execution_thread_time_total[core]) { - + /* Rollover. Set the total time to max value. */ new_total_time = (EXECUTION_TIME) TX_EXECUTION_MAX_TIME_SOURCE; - } + } /* Store back the new total time. */ _tx_execution_thread_time_total[core] = new_total_time; } - + /* Is the system now idle? */ if (_tx_thread_execute_ptr[core] == TX_NULL) { - + /* Yes, idle system. Pickup the start of idle time. */ _tx_execution_idle_time_last_start[core] = TX_EXECUTION_TIME_SOURCE; } @@ -381,7 +376,7 @@ UINT core; /* Pickup the core index. */ core = TX_SMP_CORE_ID; - /* Determine if this is the first interrupt. Nested interrupts are all treated as + /* Determine if this is the first interrupt. Nested interrupts are all treated as general interrupt processing. */ if (_tx_thread_system_state[core] == 1) { @@ -394,7 +389,7 @@ UINT core; /* Determine if a thread was interrupted. */ if (thread_ptr) { - + /* Pickup the last start time. */ last_start_time = thread_ptr -> tx_thread_execution_time_last_start; @@ -404,17 +399,17 @@ UINT core; /* Clear the last start time. */ thread_ptr -> tx_thread_execution_time_last_start = 0; - + /* Determine how to calculate the difference. */ if (current_time >= last_start_time) { - + /* Simply subtract. */ delta_time = (EXECUTION_TIME) (current_time - last_start_time); - } + } else { - + /* Timer wrapped, compute the delta assuming incrementing time counter. */ delta_time = (EXECUTION_TIME) (current_time + (((EXECUTION_TIME_SOURCE_TYPE) TX_EXECUTION_MAX_TIME_SOURCE) - last_start_time)); } @@ -424,72 +419,72 @@ UINT core; /* Now compute the new total time. */ new_total_time = total_time + delta_time; - + /* Determine if a rollover on the total time is present. */ if (new_total_time < total_time) { - + /* Rollover. Set the total time to max value. */ new_total_time = (EXECUTION_TIME) TX_EXECUTION_MAX_TIME_SOURCE; } - + /* Store back the new total time. */ thread_ptr -> tx_thread_execution_time_total = new_total_time; /* Now accumulate this thread's execution time into the total thread execution time. */ new_total_time = _tx_execution_thread_time_total[core] + delta_time; - + /* Determine if a rollover on the total time is present. */ if (new_total_time < _tx_execution_thread_time_total[core]) { - + /* Rollover. Set the total time to max value. */ new_total_time = (EXECUTION_TIME) TX_EXECUTION_MAX_TIME_SOURCE; - } + } /* Store back the new total time. */ _tx_execution_thread_time_total[core] = new_total_time; } } - + /* Has idle time started? */ else if (_tx_execution_idle_time_last_start[core]) { - + /* Pickup the last idle start time. */ last_start_time = _tx_execution_idle_time_last_start[core]; - + /* Determine how to calculate the difference. */ if (current_time >= last_start_time) { - + /* Simply subtract. */ delta_time = (EXECUTION_TIME) (current_time - last_start_time); - } + } else { - + /* Timer wrapped, compute the delta assuming incrementing time counter. */ delta_time = (EXECUTION_TIME) (current_time + (((EXECUTION_TIME_SOURCE_TYPE) TX_EXECUTION_MAX_TIME_SOURCE) - last_start_time)); } - + /* Pickup the total time. */ total_time = _tx_execution_idle_time_total[core]; /* Now compute the new total time. */ new_total_time = total_time + delta_time; - + /* Determine if a rollover on the total time is present. */ if (new_total_time < total_time) { - + /* Rollover. Set the total time to max value. */ new_total_time = (EXECUTION_TIME) TX_EXECUTION_MAX_TIME_SOURCE; } - + /* Now store back the total idle time. */ - _tx_execution_idle_time_total[core] = new_total_time; - + _tx_execution_idle_time_total[core] = new_total_time; + /* Disable the idle time measurement. */ _tx_execution_idle_time_last_start[core] = 0; } @@ -552,7 +547,7 @@ UINT core; /* Pickup the core index. */ core = TX_SMP_CORE_ID; - /* Determine if this is the first interrupt. Nested interrupts are all treated as + /* Determine if this is the first interrupt. Nested interrupts are all treated as general interrupt processing. */ if (_tx_thread_system_state[core] == 1) { @@ -562,17 +557,17 @@ UINT core; /* Pickup the last start time. */ last_start_time = _tx_execution_isr_time_last_start[core]; - + /* Determine how to calculate the difference. */ if (current_time >= last_start_time) { - + /* Simply subtract. */ delta_time = (EXECUTION_TIME) (current_time - last_start_time); } else { - + /* Timer wrapped, compute the delta assuming incrementing time counter. */ delta_time = (EXECUTION_TIME) (current_time + (((EXECUTION_TIME_SOURCE_TYPE) TX_EXECUTION_MAX_TIME_SOURCE) - last_start_time)); } @@ -582,18 +577,18 @@ UINT core; /* Now compute the new total time. */ new_total_time = total_time + delta_time; - + /* Determine if a rollover on the total time is present. */ if (new_total_time < total_time) { - + /* Rollover. Set the total time to max value. */ new_total_time = (EXECUTION_TIME) TX_EXECUTION_MAX_TIME_SOURCE; } - + /* Store back the new total time. */ _tx_execution_isr_time_total[core] = new_total_time; - + /* Pickup the current thread control block. */ thread_ptr = _tx_thread_current_ptr[core]; @@ -604,16 +599,16 @@ UINT core; /* Now determine if the thread will execution is going to occur immediately. */ if ((thread_ptr == _tx_thread_execute_ptr[core]) || (_tx_thread_preempt_disable)) { - + /* Yes, setup the thread last start time in the thread control block. */ thread_ptr -> tx_thread_execution_time_last_start = current_time; } } - + /* Determine if the system is now idle. */ if (_tx_thread_execute_ptr[core] == TX_NULL) { - + /* Yes, idle system. Pickup the start of idle time. */ _tx_execution_idle_time_last_start[core] = TX_EXECUTION_TIME_SOURCE; } @@ -710,8 +705,8 @@ UINT _tx_execution_thread_total_time_reset(void) { TX_INTERRUPT_SAVE_AREA - -TX_THREAD *thread_ptr; + +TX_THREAD *thread_ptr; UINT total_threads; UINT core; @@ -722,7 +717,7 @@ UINT core; /* Reset the total time for all cores. */ for (core = 0; core < TX_THREAD_SMP_MAX_CORES; core++) { - + _tx_execution_thread_time_total[core] = 0; } @@ -799,7 +794,7 @@ UINT core; /* Restore interrupts. */ TX_RESTORE - + /* Return success. */ return(TX_SUCCESS); } @@ -969,10 +964,10 @@ UINT core; *total_time = _tx_execution_thread_time_total[core]; } - + /* Restore interrupts. */ TX_RESTORE - + /* Return success. */ return(TX_SUCCESS); } @@ -1032,7 +1027,7 @@ UINT core; /* Return the total time. */ *total_time = _tx_execution_isr_time_total[core]; } - + /* Restore interrupts. */ TX_RESTORE @@ -1149,14 +1144,14 @@ UINT _tx_execution_core_thread_total_time_get(UINT core, EXECUTION_TIME *total_ /* Determine if the core is valid. */ if (core >= TX_THREAD_SMP_MAX_CORES) { - + /* Invalid core, return an error. */ return(TX_NOT_DONE); } /* Return the total thread time for the core. */ *total_time = _tx_execution_thread_time_total[core]; - + /* Return success. */ return(TX_SUCCESS); } @@ -1207,7 +1202,7 @@ UINT _tx_execution_core_isr_time_get(UINT core, EXECUTION_TIME *total_time) /* Determine if the core is valid. */ if (core >= TX_THREAD_SMP_MAX_CORES) { - + /* Invalid core, return an error. */ return(TX_NOT_DONE); } @@ -1264,7 +1259,7 @@ UINT _tx_execution_core_idle_time_get(UINT core, EXECUTION_TIME *total_time) /* Determine if the core is valid. */ if (core >= TX_THREAD_SMP_MAX_CORES) { - + /* Invalid core, return an error. */ return(TX_NOT_DONE); } diff --git a/utility/execution_profile_kit/smp_version/tx_execution_profile.h b/utility/execution_profile_kit/smp_version/tx_execution_profile.h index 1d1ac587..fee0e17c 100644 --- a/utility/execution_profile_kit/smp_version/tx_execution_profile.h +++ b/utility/execution_profile_kit/smp_version/tx_execution_profile.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -24,20 +25,20 @@ #define TX_EXECUTION_PROFILE_H -/* The thread execution profile kit is designed to track thread execution time - based on the hardware timer defined by TX_EXECUTION_TIME_SOURCE and - TX_EXECUTION_MAX_TIME_SOURCE below. When the thread's total time reaches +/* The thread execution profile kit is designed to track thread execution time + based on the hardware timer defined by TX_EXECUTION_TIME_SOURCE and + TX_EXECUTION_MAX_TIME_SOURCE below. When the thread's total time reaches the maximum value, it remains there until the time is reset to 0 via a call - to tx_thread_execution_time_reset. There are several assumptions to the + to tx_thread_execution_time_reset. There are several assumptions to the operation of this kit, as follows: 1. In tx_port.h replace: #define TX_THREAD_EXTENSION_3" with: #define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ - unsigned long tx_thread_execution_time_last_start; + unsigned long tx_thread_execution_time_last_start; - 2. The TX_EXECUTION_TIME_SOURCE and TX_EXECUTION_MAX_TIME_SOURCE macros are + 2. The TX_EXECUTION_TIME_SOURCE and TX_EXECUTION_MAX_TIME_SOURCE macros are defined to utilize a local hardware time source. 3. The following routines are called from assembly code: @@ -46,9 +47,9 @@ VOID _tx_execution_isr_enter(void); VOID _tx_execution_isr_exit(void); - 4. The ThreadX library must be rebuilt with TX_ENABLE_EXECUTION_CHANGE_NOTIFY so - that these macros are expanded in the TX_THREAD structure and so the assembly code macros - are enabled to call the execution profile routines. + 4. The ThreadX library must be rebuilt with TX_ENABLE_EXECUTION_CHANGE_NOTIFY so + that these macros are expanded in the TX_THREAD structure and so the assembly code macros + are enabled to call the execution profile routines. 5. Add tx_execution_profile.c to the application build. */ diff --git a/utility/execution_profile_kit/tx_execution_profile.c b/utility/execution_profile_kit/tx_execution_profile.c index 284e0ccd..e0427307 100644 --- a/utility/execution_profile_kit/tx_execution_profile.c +++ b/utility/execution_profile_kit/tx_execution_profile.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -49,15 +50,15 @@ 1. The TX_EXECUTION_TIME_SOURCE and TX_EXECUTION_MAX_TIME_SOURCE macros are defined to utilize a local hardware time source. - + 2. ThreadX 5.4 (or later) is being used, with the assembly code enabled to call the following routines from assembly code: - + VOID _tx_execution_thread_enter(void); VOID _tx_execution_thread_exit(void); VOID _tx_execution_isr_enter(void); VOID _tx_execution_isr_exit(void); - + 3. The ThreadX library assembly code must be rebuilt with TX_EXECUTION_PROFILE_ENABLE so that these macros are expanded in the TX_THREAD structure and so the assembly code macros are enabled to call the execution profile routines. @@ -66,7 +67,7 @@ /* Externally reference several internal ThreadX variables. */ - + extern ULONG _tx_thread_system_state; extern UINT _tx_thread_preempt_disable; extern TX_THREAD *_tx_thread_current_ptr; @@ -89,7 +90,7 @@ EXECUTION_TIME_SOURCE_TYPE _tx_execution_isr_time_last_start; /* Define the system idle time gathering information. For idle time that exceeds the range of the timer - source, another timer source may be needed. In addition, the total thread execution time added to the + source, another timer source may be needed. In addition, the total thread execution time added to the total ISR time, less the total system time is also a measure of idle time. */ EXECUTION_TIME _tx_execution_idle_time_total; @@ -132,12 +133,6 @@ ULONG _tx_execution_isr_nest_counter = 0; /* */ /* xxx xxx */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 04-25-2022 Scott Larson Initial Version 6.1.11 */ -/* */ /**************************************************************************/ VOID _tx_execution_initialize(void) { @@ -209,10 +204,10 @@ EXECUTION_TIME new_total_time; /* This thread is being scheduled. Simply setup the last start time in the thread control block. */ thread_ptr -> tx_thread_execution_time_last_start = current_time; - + /* Pickup the last idle start time. */ last_start_time = _tx_execution_idle_time_last_start; - + /* Determine if idle time is being measured. */ if (_tx_execution_idle_active) { @@ -220,34 +215,34 @@ EXECUTION_TIME new_total_time; /* Determine how to calculate the difference. */ if (current_time >= last_start_time) { - + /* Simply subtract. */ delta_time = (EXECUTION_TIME) (current_time - last_start_time); } else { - + /* Timer wrapped, compute the delta assuming incrementing time counter. */ delta_time = (EXECUTION_TIME) (current_time + ((((EXECUTION_TIME_SOURCE_TYPE) TX_EXECUTION_MAX_TIME_SOURCE) + 1) - last_start_time)); } - + /* Pickup the total time. */ total_time = _tx_execution_idle_time_total; /* Now compute the new total time. */ new_total_time = total_time + delta_time; - + /* Determine if a rollover on the total time is present. */ if (new_total_time < total_time) { - + /* Rollover. Set the total time to max value. */ new_total_time = (EXECUTION_TIME) TX_EXECUTION_MAX_TIME_SOURCE; } - + /* Now store back the total idle time. */ _tx_execution_idle_time_total = new_total_time; - + /* Disable the idle time measurement. */ _tx_execution_idle_active = TX_FALSE; } @@ -311,7 +306,7 @@ EXECUTION_TIME delta_time; /* Determine if there is a thread. */ if (thread_ptr) { - + /* Pickup the current time. */ current_time = TX_EXECUTION_TIME_SOURCE; @@ -324,17 +319,17 @@ EXECUTION_TIME delta_time; /* Clear the last start time. */ thread_ptr -> tx_thread_execution_time_last_start = 0; - + /* Determine how to calculate the difference. */ if (current_time >= last_start_time) { - + /* Simply subtract. */ delta_time = (EXECUTION_TIME) (current_time - last_start_time); - } + } else { - + /* Timer wrapped, compute the delta assuming incrementing time counter. */ delta_time = (EXECUTION_TIME) (current_time + ((((EXECUTION_TIME_SOURCE_TYPE) TX_EXECUTION_MAX_TIME_SOURCE) + 1) - last_start_time)); } @@ -344,25 +339,25 @@ EXECUTION_TIME delta_time; /* Now compute the new total time. */ new_total_time = total_time + delta_time; - + /* Determine if a rollover on the total time is present. */ if (new_total_time < total_time) { - + /* Rollover. Set the total time to max value. */ new_total_time = (EXECUTION_TIME) TX_EXECUTION_MAX_TIME_SOURCE; } - + /* Store back the new total time. */ thread_ptr -> tx_thread_execution_time_total = new_total_time; - + /* Now accumulate this thread's execution time into the total thread execution time. */ new_total_time = _tx_execution_thread_time_total + delta_time; - + /* Determine if a rollover on the total time is present. */ if (new_total_time < _tx_execution_thread_time_total) { - + /* Rollover. Set the total time to max value. */ new_total_time = (EXECUTION_TIME) TX_EXECUTION_MAX_TIME_SOURCE; } @@ -454,7 +449,7 @@ EXECUTION_TIME delta_time; /* Determine if a thread was interrupted. */ if (thread_ptr) { - + /* Pickup the last start time. */ last_start_time = thread_ptr -> tx_thread_execution_time_last_start; @@ -464,17 +459,17 @@ EXECUTION_TIME delta_time; /* Clear the last start time. */ thread_ptr -> tx_thread_execution_time_last_start = 0; - + /* Determine how to calculate the difference. */ if (current_time >= last_start_time) { - + /* Simply subtract. */ delta_time = (EXECUTION_TIME) (current_time - last_start_time); - } + } else { - + /* Timer wrapped, compute the delta assuming incrementing time counter. */ delta_time = (EXECUTION_TIME) (current_time + ((((EXECUTION_TIME_SOURCE_TYPE) TX_EXECUTION_MAX_TIME_SOURCE) + 1) - last_start_time)); } @@ -484,72 +479,72 @@ EXECUTION_TIME delta_time; /* Now compute the new total time. */ new_total_time = total_time + delta_time; - + /* Determine if a rollover on the total time is present. */ if (new_total_time < total_time) { - + /* Rollover. Set the total time to max value. */ new_total_time = (EXECUTION_TIME) TX_EXECUTION_MAX_TIME_SOURCE; } - + /* Store back the new total time. */ thread_ptr -> tx_thread_execution_time_total = new_total_time; /* Now accumulate this thread's execution time into the total thread execution time. */ new_total_time = _tx_execution_thread_time_total + delta_time; - + /* Determine if a rollover on the total time is present. */ if (new_total_time < _tx_execution_thread_time_total) { - + /* Rollover. Set the total time to max value. */ new_total_time = (EXECUTION_TIME) TX_EXECUTION_MAX_TIME_SOURCE; - } + } /* Store back the new total time. */ _tx_execution_thread_time_total = new_total_time; } } - + /* Has idle time started? */ else if (_tx_execution_idle_active) { - + /* Pickup the last idle start time. */ last_start_time = _tx_execution_idle_time_last_start; - + /* Determine how to calculate the difference. */ if (current_time >= last_start_time) { - + /* Simply subtract. */ delta_time = (EXECUTION_TIME) (current_time - last_start_time); - } + } else { - + /* Timer wrapped, compute the delta assuming incrementing time counter. */ delta_time = (EXECUTION_TIME) (current_time + ((((EXECUTION_TIME_SOURCE_TYPE) TX_EXECUTION_MAX_TIME_SOURCE) + 1) - last_start_time)); } - + /* Pickup the total time. */ total_time = _tx_execution_idle_time_total; /* Now compute the new total time. */ new_total_time = total_time + delta_time; - + /* Determine if a rollover on the total time is present. */ if (new_total_time < total_time) { - + /* Rollover. Set the total time to max value. */ new_total_time = (EXECUTION_TIME) TX_EXECUTION_MAX_TIME_SOURCE; } - + /* Now store back the total idle time. */ - _tx_execution_idle_time_total = new_total_time; - + _tx_execution_idle_time_total = new_total_time; + /* Disable the idle time measurement. */ _tx_execution_idle_active = TX_FALSE; } @@ -611,7 +606,7 @@ EXECUTION_TIME_SOURCE_TYPE current_time; EXECUTION_TIME delta_time; - /* Determine if this is the first interrupt. Nested interrupts are all treated as + /* Determine if this is the first interrupt. Nested interrupts are all treated as general interrupt processing. */ #ifdef TX_CORTEX_M_EPK if ((TX_THREAD_GET_SYSTEM_STATE()) && (_tx_execution_isr_nest_counter == 1)) @@ -625,17 +620,17 @@ EXECUTION_TIME delta_time; /* Pickup the last start time. */ last_start_time = _tx_execution_isr_time_last_start; - + /* Determine how to calculate the difference. */ if (current_time >= last_start_time) { - + /* Simply subtract. */ delta_time = (EXECUTION_TIME) (current_time - last_start_time); } else { - + /* Timer wrapped, compute the delta assuming incrementing time counter. */ delta_time = (EXECUTION_TIME) (current_time + (((EXECUTION_TIME_SOURCE_TYPE) TX_EXECUTION_MAX_TIME_SOURCE) - last_start_time)); } @@ -645,18 +640,18 @@ EXECUTION_TIME delta_time; /* Now compute the new total time. */ new_total_time = total_time + delta_time; - + /* Determine if a rollover on the total time is present. */ if (new_total_time < total_time) { - + /* Rollover. Set the total time to max value. */ new_total_time = (EXECUTION_TIME) TX_EXECUTION_MAX_TIME_SOURCE; } - + /* Store back the new total time. */ _tx_execution_isr_time_total = new_total_time; - + /* Pickup the current thread control block. */ thread_ptr = _tx_thread_current_ptr; @@ -667,22 +662,22 @@ EXECUTION_TIME delta_time; /* Now determine if the thread will execution is going to occur immediately. */ if ((thread_ptr == _tx_thread_execute_ptr) || (_tx_thread_preempt_disable)) { - + /* Yes, setup the thread last start time in the thread control block. */ thread_ptr -> tx_thread_execution_time_last_start = current_time; } } - + /* Determine if the system is now idle. */ if (_tx_thread_execute_ptr == TX_NULL) { - + /* Yes, idle system. Pickup the start of idle time. */ _tx_execution_idle_time_last_start = TX_EXECUTION_TIME_SOURCE; _tx_execution_idle_active = TX_TRUE; } } - + #ifdef TX_CORTEX_M_EPK /* Decrement the nested interrupt counter. */ _tx_execution_isr_nest_counter--; @@ -779,8 +774,8 @@ UINT _tx_execution_thread_total_time_reset(void) { TX_INTERRUPT_SAVE_AREA - -TX_THREAD *thread_ptr; + +TX_THREAD *thread_ptr; UINT total_threads; diff --git a/utility/execution_profile_kit/tx_execution_profile.h b/utility/execution_profile_kit/tx_execution_profile.h index 5bd34892..fa09ac2e 100644 --- a/utility/execution_profile_kit/tx_execution_profile.h +++ b/utility/execution_profile_kit/tx_execution_profile.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -24,14 +25,14 @@ #define TX_EXECUTION_PROFILE_H -/* The thread execution profile kit is designed to track thread execution time - based on the hardware timer defined by TX_EXECUTION_TIME_SOURCE and - TX_EXECUTION_MAX_TIME_SOURCE below. When the thread's total time reaches +/* The thread execution profile kit is designed to track thread execution time + based on the hardware timer defined by TX_EXECUTION_TIME_SOURCE and + TX_EXECUTION_MAX_TIME_SOURCE below. When the thread's total time reaches the maximum value, it remains there until the time is reset to 0 via a call - to tx_thread_execution_time_reset. There are several assumptions to the + to tx_thread_execution_time_reset. There are several assumptions to the operation of this kit, as follows: - 1. The TX_EXECUTION_TIME_SOURCE and TX_EXECUTION_MAX_TIME_SOURCE macros are + 1. The TX_EXECUTION_TIME_SOURCE and TX_EXECUTION_MAX_TIME_SOURCE macros are defined to utilize a local hardware time source. 2. The following routines are called from assembly code: @@ -40,8 +41,8 @@ VOID _tx_execution_isr_enter(void); VOID _tx_execution_isr_exit(void); - 3. The ThreadX library must be rebuilt with TX_EXECUTION_PROFILE_ENABLE so - the assembly code macros are enabled to call the execution profile routines. + 3. The ThreadX library must be rebuilt with TX_EXECUTION_PROFILE_ENABLE so + the assembly code macros are enabled to call the execution profile routines. 4. Add tx_execution_profile.c to the application build. */ diff --git a/utility/low_power/tx_low_power.c b/utility/low_power/tx_low_power.c index f9c07ee6..540a2bf8 100644 --- a/utility/low_power/tx_low_power.c +++ b/utility/low_power/tx_low_power.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -71,15 +72,6 @@ UINT tx_low_power_entered; /* */ /* _tx_thread_schedule Thread scheduling loop */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 William E. Lamie Initial Version 6.1.5 */ -/* 04-02-2021 Scott Larson Modified comments and fixed */ -/* compiler warning, */ -/* resulting in version 6.1.6 */ -/* */ /**************************************************************************/ VOID tx_low_power_enter(VOID) { @@ -111,10 +103,10 @@ ULONG timers_active; Program the hardware timer source such that the next timer interrupt is equal to: tx_low_power_next_expiration*tick_frequency. In most applications, the tick_frequency is 10ms, but this is - completely application specific in ThreadX, typically set up + completely application specific in ThreadX, typically set up in tx_low_level_initialize. Note that in this situation, a low power clock must be used in order to wake up the CPU for the next timeout - event. Therefore an alternative clock must be programmed. + event. Therefore an alternative clock must be programmed. 2: There are no ThreadX timers active. tx_timer_get_next returns TX_FALSE. 2.a: application may choose not to keep the ThreadX internal tick count updated (define TX_LOW_POWER_TICKLESS), therefore no need @@ -142,7 +134,7 @@ ULONG timers_active; #endif /* TX_LOW_POWER_TIMER_SETUP */ - /* Set the flag indicating that low power has been entered. This + /* Set the flag indicating that low power has been entered. This flag is checked in tx_low_power_exit to determine if the logic used to adjust the ThreadX time is required. */ tx_low_power_entered = TX_TRUE; @@ -505,7 +497,7 @@ TX_TIMER_INTERNAL *temp_list_head; /* Now clear the current timer head pointer. */ *timer_list_head = TX_NULL; } - + /* Move to next timer entry. */ timer_list_head++; diff --git a/utility/low_power/tx_low_power.h b/utility/low_power/tx_low_power.h index 36c4b87a..f31cf5d2 100644 --- a/utility/low_power/tx_low_power.h +++ b/utility/low_power/tx_low_power.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -35,12 +36,6 @@ /* This file defines prototypes for the low-power timer additions */ /* required for sleep mode. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 03-02-2021 William E. Lamie Initial Version 6.1.5 */ -/* */ /**************************************************************************/ #ifndef TX_LOW_POWER_H diff --git a/utility/rtos_compatibility_layers/FreeRTOS/FreeRTOS.h b/utility/rtos_compatibility_layers/FreeRTOS/FreeRTOS.h index 3245c8c6..18831299 100644 --- a/utility/rtos_compatibility_layers/FreeRTOS/FreeRTOS.h +++ b/utility/rtos_compatibility_layers/FreeRTOS/FreeRTOS.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -17,14 +18,6 @@ /** */ /**************************************************************************/ /**************************************************************************/ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 03-02-2021 Andres Mlinar Modified comment(s), fixed */ -/* interrupt macros, */ -/* resulting in version 6.1.5 */ /**************************************************************************/ #ifndef FREERTOS_H @@ -311,7 +304,7 @@ UINT _tx_thread_interrupt_disable(VOID); #elif defined(__ARMCC_VERSION) #define portENABLE_INTERRUPTS() __enable_irq() #else -VOID _tx_thread_interrupt_restore(UINT previous_posture); +VOID _tx_thread_interrupt_restore(UINT previous_posture); #define portENABLE_INTERRUPTS() _tx_thread_interrupt_restore(TX_INT_ENABLE) #endif #endif diff --git a/utility/rtos_compatibility_layers/FreeRTOS/config_template/FreeRTOSConfig.h b/utility/rtos_compatibility_layers/FreeRTOS/config_template/FreeRTOSConfig.h index d4a0df91..e31c0cdc 100644 --- a/utility/rtos_compatibility_layers/FreeRTOS/config_template/FreeRTOSConfig.h +++ b/utility/rtos_compatibility_layers/FreeRTOS/config_template/FreeRTOSConfig.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -17,15 +18,6 @@ /** */ /**************************************************************************/ /**************************************************************************/ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-31-2022 Scott Larson Change configSTACK_DEPTH_TYPE */ -/* to 32 bit instead of 16 bit, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ #ifndef FREERTOS_CONFIG_H diff --git a/utility/rtos_compatibility_layers/FreeRTOS/event_groups.h b/utility/rtos_compatibility_layers/FreeRTOS/event_groups.h index f034ea5a..67af88a2 100644 --- a/utility/rtos_compatibility_layers/FreeRTOS/event_groups.h +++ b/utility/rtos_compatibility_layers/FreeRTOS/event_groups.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -17,12 +18,6 @@ /** */ /**************************************************************************/ /**************************************************************************/ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef EVENT_GROUPS_H diff --git a/utility/rtos_compatibility_layers/FreeRTOS/queue.h b/utility/rtos_compatibility_layers/FreeRTOS/queue.h index 5d0695d3..9090b612 100644 --- a/utility/rtos_compatibility_layers/FreeRTOS/queue.h +++ b/utility/rtos_compatibility_layers/FreeRTOS/queue.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -17,12 +18,6 @@ /** */ /**************************************************************************/ /**************************************************************************/ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef QUEUE_H diff --git a/utility/rtos_compatibility_layers/FreeRTOS/readme.md b/utility/rtos_compatibility_layers/FreeRTOS/readme.md index 52936fee..172309af 100644 --- a/utility/rtos_compatibility_layers/FreeRTOS/readme.md +++ b/utility/rtos_compatibility_layers/FreeRTOS/readme.md @@ -48,7 +48,7 @@ For simplicity only a selected set of the usual configuration defines are suppor | configMAX_PRIORITIES | - | Maximum number of priorities. Must be less than or equal to the configured number of ThreadX priorities. | | configMINIMAL_STACK_SIZE | 512u | Minimum stack size, used as the stack size of the idle task if `TX_FREERTOS_IDLE_STACK` is not defined. | configTOTAL_HEAP_SIZE | - | Amount of internal memory allocated to the adaptation layer when creating FreeRTOS objects. Can be set to 0 to disable dynamic allocation. | -| INCLUDE_vTaskDelete | 1 | Set to 0 to disable the task delete API. When disabled the adaptation layer will not create the idle task to save resources. | +| INCLUDE_vTaskDelete | 1 | Set to 0 to disable the task delete API. When disabled the adaptation layer will not create the idle task to save resources. | | TX_FREERTOS_IDLE_STACK | 512u | Stack size of the idle task. | | TX_FREERTOS_ASSERT_FAIL | | Define to a macro invoked on internal assertion failures from within the adaptation layer | | configASSERT | | Define to a macro invoked for invalid arguments | @@ -148,16 +148,16 @@ The task API represents the core of the adaptation layer enabling creation and c | Name | Notes | |------|-------| | taskSCHEDULER_SUSPENDED -| taskSCHEDULER_NOT_STARTED -| taskSCHEDULER_RUNNING -| taskENTER_CRITICAL() -| taskEXIT_CRITICAL() -| taskENTER_CRITICAL_FROM_ISR() -| taskEXIT_CRITICAL_FROM_ISR() -| taskDISABLE_INTERRUPTS() -| taskENABLE_INTERRUPTS() -| tskIDLE_PRIORITY -| taskYIELD() +| taskSCHEDULER_NOT_STARTED +| taskSCHEDULER_RUNNING +| taskENTER_CRITICAL() +| taskEXIT_CRITICAL() +| taskENTER_CRITICAL_FROM_ISR() +| taskEXIT_CRITICAL_FROM_ISR() +| taskDISABLE_INTERRUPTS() +| taskENABLE_INTERRUPTS() +| tskIDLE_PRIORITY +| taskYIELD() | taskYIELD_FROM_ISR() | Has no effect, ThreadX will automatically pre-empt when a higher priority task is available to run upon returning from an ISR. | ### Functions @@ -171,18 +171,18 @@ The task API represents the core of the adaptation layer enabling creation and c | xTaskCreate() | uxTaskGetNumberOfTasks() | Only returns the number of task created by either `xTaskCreate()` or `xTaskcreateStatic()`. Task created internally by ThreadX or by the application using `tx_thread_create()` are not counted. | | vTaskDelete() -| vTaskDelay() +| vTaskDelay() | vTaskDelayUntil() | The implementation of `vTaskDelayUntil()` cannot perform a wait in an atomic fashion. As such there might be additional jitter when using this function with the adaptation layer. The implementation will, however, not accumulate any drift. | | xTaskGetCurrentTaskHandle() | This will only work when called from a task created by either `xTaskCreate()` or `xTaskcreateStatic()`. | | vTaskSuspend() -| vTaskResume() -| xTaskResumeFromISR() -| xTaskAbortDelay() -| uxTaskPriorityGet() -| uxTaskPriorityGetFromISR() -| vTaskPrioritySet() -| pcTaskGetName() -| eTaskGetState() +| vTaskResume() +| xTaskResumeFromISR() +| xTaskAbortDelay() +| uxTaskPriorityGet() +| uxTaskPriorityGetFromISR() +| vTaskPrioritySet() +| pcTaskGetName() +| eTaskGetState() | uxTaskGetStackHighWaterMark() | Not implemented. | | uxTaskGetStackHighWaterMark2() | Not implemented. | | xTaskCallApplicationTaskHook() | Not implemented. | @@ -197,68 +197,68 @@ Task notifications are fully implemented. | Name | Notes | |------|-------| -| xTaskNotifyGive() -| vTaskNotifyGiveFromISR() -| ulTaskNotifyTake() -| xTaskNotifyWait() -| xTaskNotify() -| xTaskNotifyFromISR() -| xTaskNotifyAndQuery() -| xTaskGenericNotify() -| xTaskNotifyAndQueryFromISR() -| xTaskGenericNotifyFromISR() -| xTaskNotifyStateClear() -| ulTaskNotifyValueClear() +| xTaskNotifyGive() +| vTaskNotifyGiveFromISR() +| ulTaskNotifyTake() +| xTaskNotifyWait() +| xTaskNotify() +| xTaskNotifyFromISR() +| xTaskNotifyAndQuery() +| xTaskGenericNotify() +| xTaskNotifyAndQueryFromISR() +| xTaskGenericNotifyFromISR() +| xTaskNotifyStateClear() +| ulTaskNotifyValueClear() ## Semaphore and Mutex Semaphores, either counting or binary as well as Mutexes are fully implemented. Mutexes under the adaptation layer cannot be taken or given from an ISR as this is not allowed in ThreadX as well as recent version of FreeRTOS. Due to differences between ThreadX and FreeRTOS it is possible that the ordering task wakeup may slightly differ. | Name | Notes | |------|-------| -| xSemaphoreCreateCounting() -| xSemaphoreCreateCountingStatic() -| xSemaphoreCreateBinary() -| xSemaphoreCreateBinaryStatic() -| xSemaphoreCreateMutex() -| xSemaphoreCreateMutexStatic() -| xSemaphoreCreateRecursiveMutex() -| xSemaphoreCreateRecursiveMutexStatic() -| vSemaphoreDelete() -| xSemaphoreTake() +| xSemaphoreCreateCounting() +| xSemaphoreCreateCountingStatic() +| xSemaphoreCreateBinary() +| xSemaphoreCreateBinaryStatic() +| xSemaphoreCreateMutex() +| xSemaphoreCreateMutexStatic() +| xSemaphoreCreateRecursiveMutex() +| xSemaphoreCreateRecursiveMutexStatic() +| vSemaphoreDelete() +| xSemaphoreTake() | xSemaphoreTakeFromISR() | It’s not possible to take a mutex from an ISR. | -| xSemaphoreTakeRecursive() -| xSemaphoreGive() -| xSemaphoreGiveFromISR() +| xSemaphoreTakeRecursive() +| xSemaphoreGive() +| xSemaphoreGiveFromISR() | xSemaphoreGiveRecursive() | It’s not possible to give a mutex from an ISR. | | uxSemaphoreGetCount() -| xSemaphoreGetMutexHolder() -| xSemaphoreGetMutexHolderFromISR() +| xSemaphoreGetMutexHolder() +| xSemaphoreGetMutexHolderFromISR() | vSemaphoreCreateBinary() | Not implemented since it’s marked as deprecated in the FreeRTOS documentation. | ## Queue -The FreeRTOS queue API is implemented with the help of ThreadX semaphores and is designed to mimic the behaviour of FreeRTOS queues. Due to differences between ThreadX and FreeRTOS it is possible that the ordering task wakeup may slightly differ. +The FreeRTOS queue API is implemented with the help of ThreadX semaphores and is designed to mimic the behaviour of FreeRTOS queues. Due to differences between ThreadX and FreeRTOS it is possible that the ordering task wakeup may slightly differ. | Name | Notes | |------|-------| | xQueueCreate() | | xQueueCreateStatic() | -| vQueueDelete() -| xQueueSend() -| xQueueSendFromISR() -| xQueueSendToBack() -| xQueueSendToBackFromISR() +| vQueueDelete() +| xQueueSend() +| xQueueSendFromISR() +| xQueueSendToBack() +| xQueueSendToBackFromISR() | xQueueSendToFront() | | xQueueSendToFrontFromISR() | | xQueueReceive() -| xQueueReceiveFromISR() +| xQueueReceiveFromISR() | xQueuePeek() | | xQueuePeekFromISR() | | uxQueueMessagesWaiting() | | uxQueueMessagesWaitingFromISR() | | uxQueueSpacesAvailable() | -| xQueueIsQueueEmptyFromISR() -| xQueueIsQueueFullFromISR() -| xQueueReset() +| xQueueIsQueueEmptyFromISR() +| xQueueIsQueueFullFromISR() +| xQueueReset() | xQueueOverwrite() | | xQueueOverwriteFromISR() | | pcQueueGetName() | Not implemented. | @@ -268,27 +268,27 @@ Queue sets are implemented with support for adding queues, semaphores and mutexe | Name | Notes | |------|-------| -| xQueueCreateSet() -| xQueueAddToSet() -| xQueueRemoveFromSet() -| xQueueSelectFromSet() -| xQueueSelectFromSetFromISR() +| xQueueCreateSet() +| xQueueAddToSet() +| xQueueRemoveFromSet() +| xQueueSelectFromSet() +| xQueueSelectFromSetFromISR() ## Event Group Event groups are implemented using ThreadX’s event flags. It is important to note however that `xEventGroupSync()` is not atomic. | Name | Notes| |------|-------| -| xEventGroupCreate() -| xEventGroupCreateStatic() -| vEventGroupDelete() -| xEventGroupWaitBits() -| xEventGroupSetBits() -| xEventGroupSetBitsFromISR() -| xEventGroupClearBits() -| xEventGroupClearBitsFromISR() -| xEventGroupGetBits() -| xEventGroupGetBitsFromISR() +| xEventGroupCreate() +| xEventGroupCreateStatic() +| vEventGroupDelete() +| xEventGroupWaitBits() +| xEventGroupSetBits() +| xEventGroupSetBitsFromISR() +| xEventGroupClearBits() +| xEventGroupClearBitsFromISR() +| xEventGroupGetBits() +| xEventGroupGetBitsFromISR() | xEventGroupSync() | Not atomic. | ## Timer @@ -296,25 +296,25 @@ The timer API is fully implemented except for the pend function all functionalit | Name | Notes | |------|-------| -| xTimerCreate() -| xTimerCreateStatic() -| xTimerDelete() -| xTimerIsTimerActive() -| xTimerStart() -| xTimerStop() -| xTimerChangePeriod() -| xTimerReset() -| xTimerStartFromISR() -| xTimerStopFromISR() -| xTimerChangePeriodFromISR() -| xTimerResetFromISR() -| pvTimerGetTimerID() -| vTimerSetTimerID() -| vTimerSetReloadMode() -| pcTimerGetName() -| xTimerGetPeriod() -| xTimerGetExpiryTime() -| uxTimerGetReloadMode() +| xTimerCreate() +| xTimerCreateStatic() +| xTimerDelete() +| xTimerIsTimerActive() +| xTimerStart() +| xTimerStop() +| xTimerChangePeriod() +| xTimerReset() +| xTimerStartFromISR() +| xTimerStopFromISR() +| xTimerChangePeriodFromISR() +| xTimerResetFromISR() +| pvTimerGetTimerID() +| vTimerSetTimerID() +| vTimerSetReloadMode() +| pcTimerGetName() +| xTimerGetPeriod() +| xTimerGetExpiryTime() +| uxTimerGetReloadMode() | xTimerPendFunctionCall() | Not implemented. | | xTimerPendFunctionCallFromISR() | Not implemented. | | xTimerGetTimerDaemonTaskHandle() | Not implemented. | diff --git a/utility/rtos_compatibility_layers/FreeRTOS/revision_history.txt b/utility/rtos_compatibility_layers/FreeRTOS/revision_history.txt index 1cbc90b6..8357c2a8 100644 --- a/utility/rtos_compatibility_layers/FreeRTOS/revision_history.txt +++ b/utility/rtos_compatibility_layers/FreeRTOS/revision_history.txt @@ -1,10 +1,10 @@ -Copyright (c) 2024 Microsoft Corporation - +Copyright (c) 2024 Microsoft Corporation + This program and the accompanying materials are made available under the terms of the MIT License which is available at https://opensource.org/licenses/MIT. - + SPDX-License-Identifier: MIT diff --git a/utility/rtos_compatibility_layers/FreeRTOS/semphr.h b/utility/rtos_compatibility_layers/FreeRTOS/semphr.h index c8341d34..9e5be62a 100644 --- a/utility/rtos_compatibility_layers/FreeRTOS/semphr.h +++ b/utility/rtos_compatibility_layers/FreeRTOS/semphr.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -17,12 +18,6 @@ /** */ /**************************************************************************/ /**************************************************************************/ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ diff --git a/utility/rtos_compatibility_layers/FreeRTOS/task.h b/utility/rtos_compatibility_layers/FreeRTOS/task.h index f77dc7c5..33cee40f 100644 --- a/utility/rtos_compatibility_layers/FreeRTOS/task.h +++ b/utility/rtos_compatibility_layers/FreeRTOS/task.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -17,12 +18,6 @@ /** */ /**************************************************************************/ /**************************************************************************/ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TASK_H diff --git a/utility/rtos_compatibility_layers/FreeRTOS/timers.h b/utility/rtos_compatibility_layers/FreeRTOS/timers.h index 9c94eb33..7e35d20e 100644 --- a/utility/rtos_compatibility_layers/FreeRTOS/timers.h +++ b/utility/rtos_compatibility_layers/FreeRTOS/timers.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -17,12 +18,6 @@ /** */ /**************************************************************************/ /**************************************************************************/ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* */ /**************************************************************************/ #ifndef TIMERS_H diff --git a/utility/rtos_compatibility_layers/FreeRTOS/tx_freertos.c b/utility/rtos_compatibility_layers/FreeRTOS/tx_freertos.c index b400cf86..acac53cc 100644 --- a/utility/rtos_compatibility_layers/FreeRTOS/tx_freertos.c +++ b/utility/rtos_compatibility_layers/FreeRTOS/tx_freertos.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -17,26 +18,6 @@ /** */ /**************************************************************************/ /**************************************************************************/ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ -/* 10-15-2021 William E. Lamie Modified comment(s), and */ -/* fixed compiler warnings, */ -/* resulting in version 6.1.7 */ -/* 01-31-2022 William E. Lamie Modified comment(s), and */ -/* fixed compiler warnings, */ -/* resulting in version 6.1.10 */ -/* 07-29-2022 Cindy Deng Added simple static scheduler */ -/* start flag, corrected stack */ -/* allocation size, */ -/* resulting in version 6.1.12 */ -/* 12-31-2023 Xiuwen Cai Modified comment(s), and */ -/* added check for overflow in */ -/* queue size calculation, */ -/* resulting in version 6.4.0 */ -/* */ /**************************************************************************/ #include diff --git a/utility/rtos_compatibility_layers/OSEK/demo_osek.c b/utility/rtos_compatibility_layers/OSEK/demo_osek.c index 625282eb..2e104d31 100644 --- a/utility/rtos_compatibility_layers/OSEK/demo_osek.c +++ b/utility/rtos_compatibility_layers/OSEK/demo_osek.c @@ -51,7 +51,7 @@ TX_TIMER demo_isr_timer; VOID demo_isr_timer_entry(ULONG arg); -/* Main function. */ +/* Main function. */ int main() { @@ -67,8 +67,8 @@ CHAR * pointer; /* Put the first available address into character pointer. */ pointer = (CHAR * )free_memory; - - /* Setup hook pointers (optional). */ + + /* Setup hook pointers (optional). */ Application1.shutdown_hook_handler = ShutdownHook; Application1.pretask_hook_handler = PreTaskHook; Application1.posttask_hook_handler = PostTaskHook; @@ -77,7 +77,7 @@ CHAR * pointer; /* Initialize a pointer. */ osek_initialize(pointer,&Application1); - + /* Create the system counter */ SystemTimer = CreateCounter("SystemTimer", 0x7FFFFFFF, 2, 2, 0); DefineSystemCounter(SystemTimer); @@ -87,13 +87,13 @@ CHAR * pointer; /* Create an event. */ Event1 = CreateEvent(); - + /* Register Event1 to Task1. */ RegisterEventtoTask(Event1 , Task1); /* Create a resource. */ Resource1 = CreateResource("Resource1", STANDARD, 0); - + /* Register Resource1 to Task1. */ RegisterTasktoResource(Resource1, Task1); @@ -103,10 +103,10 @@ CHAR * pointer; /* Create a ThreadX timer to simulate an ISR. */ tx_timer_create(&demo_isr_timer, "Demo ISR timer", demo_isr_timer_entry, DemoISR, 1000, 1000, TX_AUTO_ACTIVATE); - + /* Start OSEK */ StartOS(OSDEFAULTAPPMODE); - + } /* Task body. */ diff --git a/utility/rtos_compatibility_layers/OSEK/os.h b/utility/rtos_compatibility_layers/OSEK/os.h index eda727b4..f88bfce7 100644 --- a/utility/rtos_compatibility_layers/OSEK/os.h +++ b/utility/rtos_compatibility_layers/OSEK/os.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -34,13 +35,6 @@ /* This file defines the constants, structures, etc. needed for the */ /* OSEK implementation. */ /* */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ #ifndef TX_OSEK_H diff --git a/utility/rtos_compatibility_layers/OSEK/osek_user.h b/utility/rtos_compatibility_layers/OSEK/osek_user.h index 27b73ecd..45f4d7b6 100644 --- a/utility/rtos_compatibility_layers/OSEK/osek_user.h +++ b/utility/rtos_compatibility_layers/OSEK/osek_user.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -34,12 +35,6 @@ /* This files contains user configurable compile time paramteres for */ /* the OSEK implementation. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ #ifndef OSEK_USER_H diff --git a/utility/rtos_compatibility_layers/OSEK/threadx_osek_readme.txt b/utility/rtos_compatibility_layers/OSEK/threadx_osek_readme.txt index dd1e1209..6f19db6d 100644 --- a/utility/rtos_compatibility_layers/OSEK/threadx_osek_readme.txt +++ b/utility/rtos_compatibility_layers/OSEK/threadx_osek_readme.txt @@ -9,46 +9,46 @@ to the ThreadX readme file for installation instructions for ThreadX. 2. Building -Building the OSEK layer should be as simple as including the tx_osek.c and os.h file to +Building the OSEK layer should be as simple as including the tx_osek.c and os.h file to an existing ThreadX project, making sure that the location of the os.h header is in the -include paths. The OSEK layer requires that the ThreadX headers such as tx_api.h are +include paths. The OSEK layer requires that the ThreadX headers such as tx_api.h are reachable in the include paths as well. 3. Initialization -The OSEK layer initialization can be performed either from the tx_application_define() -during the ThreadX initialization or from a running ThreadX thread. It is strongly -recommended to initialize and start the OSEK layer as soon as possible. Once started -other ThreadX tasks and API call should not be used to prevent resource conflicts with +The OSEK layer initialization can be performed either from the tx_application_define() +during the ThreadX initialization or from a running ThreadX thread. It is strongly +recommended to initialize and start the OSEK layer as soon as possible. Once started +other ThreadX tasks and API call should not be used to prevent resource conflicts with OSEK. -The OSEK initialization has three phases. First the osek internal initialization which -must be performed before calling any other OSEK API functions, by calling +The OSEK initialization has three phases. First the osek internal initialization which +must be performed before calling any other OSEK API functions, by calling osek_initialize() passing it a pointer to the OSEK memory and the application structure. The size of the memory region passed to osek_initialize() must be set at compile time by adjusting the OSEK_MEMORY_SIZE define in osek_uart.h. -After having initialized the OSEK internally, the application can now create OSEK objects +After having initialized the OSEK internally, the application can now create OSEK objects and link or assigned them as needed. See below for a list of object creation functions. -Finally, after all the objects are created and configured the OSEK layer can be started -using StartOS(). Once started it is no longer possible to create or change any OSEK +Finally, after all the objects are created and configured the OSEK layer can be started +using StartOS(). Once started it is no longer possible to create or change any OSEK objects. 4. OSEK shutdown and restart -The OSEK layer can be shutdown using the standard OSEK API ShutdownOS(). As an extension -to the OSEK layer offers an osek_cleanup() function which can be used to cleanup and -reset the OSEK layer allowing a subsequent restart without having to reset the CPU. This +The OSEK layer can be shutdown using the standard OSEK API ShutdownOS(). As an extension +to the OSEK layer offers an osek_cleanup() function which can be used to cleanup and +reset the OSEK layer allowing a subsequent restart without having to reset the CPU. This is primarily intended for testing. 5. Hooks -The various hook routines available within OSEK can be set during initialization by -setting the various handler members of the APPLICATION_INFO structure passed to +The various hook routines available within OSEK can be set during initialization by +setting the various handler members of the APPLICATION_INFO structure passed to osek_initialize(). See the OSEK documentation for the signature of those hook functions. For example: @@ -62,15 +62,15 @@ For example: 6. Interrupts -As per the OSEK specification, category 1 ISRs are not affected by the OSEK layer +As per the OSEK specification, category 1 ISRs are not affected by the OSEK layer execution and are not allowed to call any of the OSEK API. Those ISR are configured and -processed just like any other interrupts under ThreadX. Category 2 ISR have to be +processed just like any other interrupts under ThreadX. Category 2 ISR have to be created using CreateISR() as well as being registered and enable like a category 1 ISR. In the body of the low level ISR process_ISR2() must be called with the return value of -the corresponding CreateISR() in argument. This will instruct the OSEK layer to schedule +the corresponding CreateISR() in argument. This will instruct the OSEK layer to schedule the category 2 ISR as soon as possible. -A category 2 ISR is made of two handlers, the one that process the hardware interrupt +A category 2 ISR is made of two handlers, the one that process the hardware interrupt and the OSEK ISR body. To define a category 2 ISR body use the standard ISR() macro as follows: @@ -104,7 +104,7 @@ void demo_isr_hardware_handler(void) 7. Implementation specific information -Since OSEK requires a static allocation methodology, the number of available OSEK object +Since OSEK requires a static allocation methodology, the number of available OSEK object has to be limited at compile time. By default the following limits apply: Maximum number of tasks: 32 @@ -121,10 +121,10 @@ Maximum task activation count: 8 8. Supported OSEK API -The ThreadX OSEK layer supports all the mandatory APIs specified in version 2.2.3 of +The ThreadX OSEK layer supports all the mandatory APIs specified in version 2.2.3 of the OSEK/VDK Operating System Specification. -Summary of the supported API, see the OSEK specification and tx_osek.c for the full +Summary of the supported API, see the OSEK specification and tx_osek.c for the full details of each API. TASK MANAGEMENT @@ -191,22 +191,22 @@ detailed description of each function. ---- CreateTask – Creates an OSEK task, the task is returned if successful. - TaskType CreateTask(CHAR *name, - void(*entry_function)(), - UINT priority, - UINT max_activation, - ULONG stack_size, - SCHEDULE policy, - AUTOSTART start, - UINT type, + TaskType CreateTask(CHAR *name, + void(*entry_function)(), + UINT priority, + UINT max_activation, + ULONG stack_size, + SCHEDULE policy, + AUTOSTART start, + UINT type, AppModeType mode); ---- CreateResource - Creates an OSEK resource, the resource is returned if successful. - ResourceType CreateResource(const CHAR *name, - StatusType type, + ResourceType CreateResource(const CHAR *name, + StatusType type, ResourceType linked_res); @@ -214,49 +214,49 @@ CreateResource - Creates an OSEK resource, the resource is returned if successfu RegisterTasktoResource - Registers a task to a resource. The resource will be accessible by the registered task. - StatusType RegisterTasktoResource(ResourceType Resource, + StatusType RegisterTasktoResource(ResourceType Resource, TaskType TaskID); ---- -CreateEvent - Creates an event, the created event is returned if successful. Note that +CreateEvent - Creates an event, the created event is returned if successful. Note that per the OSEK specification an absolute maximum of 32 events can be created. EventMaskType CreateEvent(void); ---- -RegisterEventtoTask - Register an event to a task. The event is now usable from that +RegisterEventtoTask - Register an event to a task. The event is now usable from that task. Note that an event can only be registered to a single task. - StatusType RegisterEventtoTask(EventType eventid, + StatusType RegisterEventtoTask(EventType eventid, TaskType TaskID); ---- CreateISR - Creates an ISR. - ISRType CreateISR(const CHAR *name, - void(*entry_function)(), - UINT category, + ISRType CreateISR(const CHAR *name, + void(*entry_function)(), + UINT category, ULONG stack_size); ---- -RegisterISRtoResource - Register an ISR to a resource. Note that ISR cannot be registered +RegisterISRtoResource - Register an ISR to a resource. Note that ISR cannot be registered to category 1 ISRS. - StatusType RegisterISRtoResource(ResourceType Resource, + StatusType RegisterISRtoResource(ResourceType Resource, ISRType ISRID); ---- CreateCounter - Creates a new counter. - CounterType CreateCounter(CHAR *name, - TickType max_allowed_value, - TickType ticks_per_base, - TickType min_cycle, + CounterType CreateCounter(CHAR *name, + TickType max_allowed_value, + TickType ticks_per_base, + TickType min_cycle, TickType start_value); ---- @@ -267,11 +267,11 @@ DefineSystemCounter - Assign a counter to be used as the system counter. --- CreateAlarm - Creates an alarm. -AlarmType CreateAlarm(CHAR *name, - CounterType cntr, - UINT action, - ULONG events, - TaskType task, - void (*callback)(), - UINT Startup, TickType Alarmtime, +AlarmType CreateAlarm(CHAR *name, + CounterType cntr, + UINT action, + ULONG events, + TaskType task, + void (*callback)(), + UINT Startup, TickType Alarmtime, TickType Cycle); diff --git a/utility/rtos_compatibility_layers/OSEK/tx_osek.c b/utility/rtos_compatibility_layers/OSEK/tx_osek.c index bf5f482c..fe778f32 100644 --- a/utility/rtos_compatibility_layers/OSEK/tx_osek.c +++ b/utility/rtos_compatibility_layers/OSEK/tx_osek.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -268,12 +269,6 @@ static StatusType ActivateISR(ISRType ISRID); /* */ /* Application */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ void StartOS(StatusType os_mode) { diff --git a/utility/rtos_compatibility_layers/posix/errno.h b/utility/rtos_compatibility_layers/posix/errno.h index 65077d9a..2b01c34c 100644 --- a/utility/rtos_compatibility_layers/posix/errno.h +++ b/utility/rtos_compatibility_layers/posix/errno.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -33,13 +34,6 @@ /* This file defines the constants, structures, etc.needed to */ /* implement the Evacuation Kit for POSIX Users (POSIX) */ /* */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ #ifndef _ERRNO_H @@ -96,7 +90,7 @@ #define EDQUOT 213 -#define EEXIST 17 +#define EEXIST 17 #define EFAULT 214 diff --git a/utility/rtos_compatibility_layers/posix/fcntl.h b/utility/rtos_compatibility_layers/posix/fcntl.h index 8c362bec..db943625 100644 --- a/utility/rtos_compatibility_layers/posix/fcntl.h +++ b/utility/rtos_compatibility_layers/posix/fcntl.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -33,13 +34,6 @@ /* This file defines the constants, structures, etc.needed to */ /* implement the Evacuation Kit for POSIX Users (POSIX) */ /* */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ #ifndef _FCNTL_H @@ -52,39 +46,39 @@ #define O_APPEND 0x0008 #define O_SYNC 0x0010 #define O_NONBLOCK 0x0080 -#define O_CREAT 0x0100 -#define O_TRUNC 0x0200 -#define O_EXCL 0x0400 -#define O_NOCTTY 0x0800 -#define FASYNC 0x1000 -#define O_LARGEFILE 0x2000 -#define O_DIRECT 0x8000 -#define O_DIRECTORY 0x10000 -#define O_NOFOLLOW 0x20000 +#define O_CREAT 0x0100 +#define O_TRUNC 0x0200 +#define O_EXCL 0x0400 +#define O_NOCTTY 0x0800 +#define FASYNC 0x1000 +#define O_LARGEFILE 0x2000 +#define O_DIRECT 0x8000 +#define O_DIRECTORY 0x10000 +#define O_NOFOLLOW 0x20000 #define O_NDELAY O_NONBLOCK -#define F_DUPFD 0 -#define F_GETFD 1 -#define F_SETFD 2 -#define F_GETFL 3 -#define F_SETFL 4 +#define F_DUPFD 0 +#define F_GETFD 1 +#define F_SETFD 2 +#define F_GETFL 3 +#define F_SETFL 4 #define F_GETLK 14 #define F_SETLK 6 #define F_SETLKW 7 -#define F_SETOWN 24 -#define F_GETOWN 23 -#define F_SETSIG 10 -#define F_GETSIG 11 +#define F_SETOWN 24 +#define F_GETOWN 23 +#define F_SETSIG 10 +#define F_GETSIG 11 -#define FD_CLOEXEC 1 +#define FD_CLOEXEC 1 -# define POSIX_FADV_NORMAL 0 -# define POSIX_FADV_RANDOM 1 -# define POSIX_FADV_SEQUENTIAL 2 -# define POSIX_FADV_WILLNEED 3 -# define POSIX_FADV_DONTNEED 4 +# define POSIX_FADV_NORMAL 0 +# define POSIX_FADV_RANDOM 1 +# define POSIX_FADV_SEQUENTIAL 2 +# define POSIX_FADV_WILLNEED 3 +# define POSIX_FADV_DONTNEED 4 # define POSIX_FADV_NOREUSE 5 /* no flock structure for Threadx at this time */ diff --git a/utility/rtos_compatibility_layers/posix/posix_demo.c b/utility/rtos_compatibility_layers/posix/posix_demo.c index 339ad9bb..7adeb9c3 100644 --- a/utility/rtos_compatibility_layers/posix/posix_demo.c +++ b/utility/rtos_compatibility_layers/posix/posix_demo.c @@ -94,7 +94,7 @@ struct sched_param param; queue_atrr.mq_maxmsg = 124; queue_atrr.mq_msgsize = MAX_MESSAGE_SIZE; - + /* Init POSIX Wrapper */ storage_ptr = (VOID*) posix_initialize(free_memory); @@ -107,54 +107,54 @@ struct sched_param param; pthread_attr_init(&ptattr2); pthread_attr_init(&ptattr3); pthread_attr_init(&ptattr4); - pthread_attr_init(&ptattr5); + pthread_attr_init(&ptattr5); /* Create a sched_param structure */ memset(¶m, 0, sizeof(param)); - + /* Now create all pthreads , firstly modify respective ptheread attribute with desired priority and stack start address and then create the pthread */ - + /* Create pthread 0. */ param.sched_priority = 10; pthread_attr_setschedparam(&ptattr0, ¶m); pthread_attr_setstackaddr(&ptattr0, storage_ptr ); - storage_ptr = (int *) storage_ptr + DEMO_STACK_SIZE; + storage_ptr = (int *) storage_ptr + DEMO_STACK_SIZE; pthread_create (&pthread_0, &ptattr0,pthread_0_entry,NULL); - + /* Create pthread 1. */ param.sched_priority = 15; pthread_attr_setschedparam(&ptattr1, ¶m); pthread_attr_setstackaddr(&ptattr1, (VOID*) storage_ptr ); - storage_ptr = (int *) storage_ptr + DEMO_STACK_SIZE; + storage_ptr = (int *) storage_ptr + DEMO_STACK_SIZE; pthread_create (&pthread_1, &ptattr1,pthread_1_entry,NULL); - + /* Create pthread 2. */ param.sched_priority = 20; pthread_attr_setschedparam(&ptattr2, ¶m); pthread_attr_setstackaddr(&ptattr2, (VOID*) storage_ptr ); - storage_ptr = (int *) storage_ptr + DEMO_STACK_SIZE; + storage_ptr = (int *) storage_ptr + DEMO_STACK_SIZE; pthread_create (&pthread_2, &ptattr2,pthread_2_entry,NULL); /* Create pthread 3. */ param.sched_priority = 25; pthread_attr_setschedparam(&ptattr3, ¶m); pthread_attr_setstackaddr(&ptattr3, (VOID*) storage_ptr ); - storage_ptr = (int *) storage_ptr + DEMO_STACK_SIZE; + storage_ptr = (int *) storage_ptr + DEMO_STACK_SIZE; pthread_create (&pthread_3, &ptattr3,pthread_3_entry,NULL); - + /* Create pthread 4. */ param.sched_priority = 30; pthread_attr_setschedparam(&ptattr4, ¶m); pthread_attr_setstackaddr(&ptattr4, (VOID*) storage_ptr ); - storage_ptr = (int *) storage_ptr + DEMO_STACK_SIZE; + storage_ptr = (int *) storage_ptr + DEMO_STACK_SIZE; pthread_create (&pthread_4, &ptattr4,pthread_4_entry,NULL); - + /* Create pthread 5. */ param.sched_priority = 5; pthread_attr_setschedparam(&ptattr5, ¶m); pthread_attr_setstackaddr(&ptattr5, (VOID*) storage_ptr ); - storage_ptr = (int *) storage_ptr + DEMO_STACK_SIZE; + storage_ptr = (int *) storage_ptr + DEMO_STACK_SIZE; pthread_create (&pthread_5, &ptattr5,pthread_5_entry,NULL); /* Create a Message queue. */ @@ -165,7 +165,7 @@ struct sched_param param; /* Create a Mutex */ pthread_mutex_init(&mutex1, NULL); - + } /* Define the test pthreads */ @@ -176,8 +176,8 @@ VOID *pthread_0_entry(VOID *pthread0_input) struct timespec thread_0_sleep_time={0,0}; - /* This pthread simply sits in while-forever-sleep loop */ - while(1) + /* This pthread simply sits in while-forever-sleep loop */ + while(1) { /* Increment the pthread counter.*/ pthread_0_counter++; @@ -197,13 +197,13 @@ INT pt1_status=0; VOID *pthread_1_entry(VOID *pthread1_input) { - + struct timespec thread_1_sleep_time={0,0}; /* This thread simply sends a messages to a queue shared by pthread 2. */ while(1) { - + /* Increment the thread counter. */ pthread_1_counter++; /* Send message to queue 0. */ @@ -229,7 +229,7 @@ INT pt2_status; VOID *pthread_2_entry(VOID *pthread2_input) { -CHAR msgr0[MAX_MESSAGE_SIZE]; +CHAR msgr0[MAX_MESSAGE_SIZE]; ULONG priority; struct timespec thread_2_sleep_time={0,0}; @@ -239,7 +239,7 @@ struct timespec thread_2_sleep_time={0,0}; /* Increment the thread counter. */ pthread_2_counter++; pt2_status = mq_receive(q_des,msgr0,MAX_MESSAGE_SIZE,&priority); - + if(pt2_status == ERROR) break; @@ -266,7 +266,7 @@ struct timespec thread_3_sleep_time={0,0}; /* Increment the thread counter. */ pthread_3_counter++; - /* Get the semaphore with suspension. */ + /* Get the semaphore with suspension. */ pt3_status = sem_wait(sem); /* Check status. */ diff --git a/utility/rtos_compatibility_layers/posix/posix_signal_nested_test.c b/utility/rtos_compatibility_layers/posix/posix_signal_nested_test.c index 70fb4887..6f5b6478 100644 --- a/utility/rtos_compatibility_layers/posix/posix_signal_nested_test.c +++ b/utility/rtos_compatibility_layers/posix/posix_signal_nested_test.c @@ -56,7 +56,7 @@ VOID tx_application_define(VOID *first_unused_memory) struct sched_param param; - + /* Init POSIX Wrapper */ storage_ptr = (VOID*) posix_initialize((VOID* )free_memory); @@ -68,15 +68,15 @@ struct sched_param param; /* Create a sched_param structure */ memset(¶m, 0, sizeof(param)); - + /* Now create all pthreads , firstly modify respective ptheread attribute with desired priority and stack start address and then create the pthread */ - + /* Create pthread 0. */ param.sched_priority = 10; pthread_attr_setschedparam(&ptattr0, ¶m); pthread_attr_setstackaddr(&ptattr0, storage_ptr ); - storage_ptr = (int *) storage_ptr + DEMO_STACK_SIZE; + storage_ptr = (int *) storage_ptr + DEMO_STACK_SIZE; pthread_create (&pthread_0, &ptattr0,pthread_0_entry,NULL); } @@ -100,7 +100,7 @@ VOID pthread_0_signal_handler13(int signo) called from pthread 0. */ if (pthread_self() != pthread_0) { - + /* Call error handler. */ error_handler(); } @@ -108,7 +108,7 @@ VOID pthread_0_signal_handler13(int signo) /* Check for proper signal. */ if (signo != 13) { - + /* Call error handler. */ error_handler(); } @@ -125,7 +125,7 @@ VOID pthread_0_signal_handler14(int signo) called from pthread 0. */ if (pthread_self() != pthread_0) { - + /* Call error handler. */ error_handler(); } @@ -133,7 +133,7 @@ VOID pthread_0_signal_handler14(int signo) /* Check for proper signal. */ if (signo != 14) { - + /* Call error handler. */ error_handler(); } @@ -153,7 +153,7 @@ VOID pthread_0_signal_handler15(int signo) called from pthread 0. */ if (pthread_self() != pthread_0) { - + /* Call error handler. */ error_handler(); } @@ -161,7 +161,7 @@ VOID pthread_0_signal_handler15(int signo) /* Check for proper signal. */ if (signo != 15) { - + /* Call error handler. */ error_handler(); } @@ -202,18 +202,18 @@ VOID *pthread_0_entry(VOID *pthread0_input) if (pt0_status) error_handler(); - /* This pthread simply sits in while-forever-sleep loop */ - while(1) + /* This pthread simply sits in while-forever-sleep loop */ + while(1) { /* Increment the pthread counter.*/ pthread_0_counter++; /* Raise the signal. */ pt0_status = pthread_kill(pthread_0, 15); - + /* Check for errors. */ - if ((pt0_status) || - (pthread_0_counter != pthread_0_signal_counter15) || + if ((pt0_status) || + (pthread_0_counter != pthread_0_signal_counter15) || (pthread_0_counter != pthread_0_signal_counter14) || (pthread_0_counter != pthread_0_signal_counter13)) { diff --git a/utility/rtos_compatibility_layers/posix/posix_signal_resume_thread_test.c b/utility/rtos_compatibility_layers/posix/posix_signal_resume_thread_test.c index d2548056..90878158 100644 --- a/utility/rtos_compatibility_layers/posix/posix_signal_resume_thread_test.c +++ b/utility/rtos_compatibility_layers/posix/posix_signal_resume_thread_test.c @@ -66,7 +66,7 @@ VOID tx_application_define(VOID *first_unused_memory) struct sched_param param; - + /* Init POSIX Wrapper */ storage_ptr = (VOID*) posix_initialize((VOID*)free_memory); @@ -79,15 +79,15 @@ struct sched_param param; /* Create a sched_param structure */ memset(¶m, 0, sizeof(param)); - + /* Now create all pthreads , firstly modify respective ptheread attribute with desired priority and stack start address and then create the pthread */ - + /* Create pthread 0. */ param.sched_priority = 15; pthread_attr_setschedparam(&ptattr0, ¶m); pthread_attr_setstackaddr(&ptattr0, storage_ptr ); - storage_ptr = (int *) storage_ptr + DEMO_STACK_SIZE; + storage_ptr = (int *) storage_ptr + DEMO_STACK_SIZE; pthread_create (&pthread_0, &ptattr0,pthread_0_entry,NULL); @@ -95,7 +95,7 @@ struct sched_param param; param.sched_priority = 10; pthread_attr_setschedparam(&ptattr1, ¶m); pthread_attr_setstackaddr(&ptattr1, (VOID*) storage_ptr ); - storage_ptr = (int *) storage_ptr + DEMO_STACK_SIZE; + storage_ptr = (int *) storage_ptr + DEMO_STACK_SIZE; pthread_create (&pthread_1, &ptattr1,pthread_1_entry,NULL); @@ -124,7 +124,7 @@ VOID pthread_0_signal_handler13(int signo) called from pthread 0. */ if (pthread_self() != pthread_0) { - + /* Call error handler. */ error_handler(); } @@ -132,7 +132,7 @@ VOID pthread_0_signal_handler13(int signo) /* Check for proper signal. */ if (signo != 13) { - + /* Call error handler. */ error_handler(); } @@ -152,7 +152,7 @@ VOID pthread_0_signal_handler14(int signo) called from pthread 0. */ if (pthread_self() != pthread_0) { - + /* Call error handler. */ error_handler(); } @@ -160,7 +160,7 @@ VOID pthread_0_signal_handler14(int signo) /* Check for proper signal. */ if (signo != 14) { - + /* Call error handler. */ error_handler(); } @@ -180,7 +180,7 @@ VOID pthread_0_signal_handler15(int signo) called from pthread 0. */ if (pthread_self() != pthread_0) { - + /* Call error handler. */ error_handler(); } @@ -188,7 +188,7 @@ VOID pthread_0_signal_handler15(int signo) /* Check for proper signal. */ if (signo != 15) { - + /* Call error handler. */ error_handler(); } @@ -230,30 +230,30 @@ VOID *pthread_0_entry(VOID *pthread0_input) error_handler(); - /* Get the semaphore with suspension. */ + /* Get the semaphore with suspension. */ pt0_status = sem_wait(sem); - /* This pthread simply sits in while-forever-sleep loop */ - while(1) + /* This pthread simply sits in while-forever-sleep loop */ + while(1) { /* Increment the pthread counter.*/ pthread_0_counter++; - /* Get the semaphore with suspension. */ + /* Get the semaphore with suspension. */ pt0_status = sem_wait(sem); /* Check for errors. */ - if ((pt0_status) || - (pthread_0_counter != pthread_0_signal_counter15) || + if ((pt0_status) || + (pthread_0_counter != pthread_0_signal_counter15) || (pthread_0_counter != pthread_0_signal_counter14) || (pthread_0_counter != pthread_0_signal_counter13)) { - + /* In this test, this thread should never resume! */ error_handler(); /* Break out of the loop. */ - break; + break; } } @@ -265,12 +265,12 @@ INT pt1_status=0; VOID *pthread_1_entry(VOID *pthread1_input) { - + /* This thread simply sends a messages to a queue shared by pthread 2. */ while(1) { - + /* Increment the thread counter. */ pthread_1_counter++; @@ -278,9 +278,9 @@ VOID *pthread_1_entry(VOID *pthread1_input) pt1_status = pthread_kill(pthread_0, 15); /* Check for errors. */ - if ((pt1_status) || + if ((pt1_status) || (pthread_0_counter != (pthread_1_counter+1)) || - (pthread_1_counter != pthread_0_signal_counter15) || + (pthread_1_counter != pthread_0_signal_counter15) || (pthread_1_counter != pthread_0_signal_counter14) || (pthread_1_counter != pthread_0_signal_counter13)) { @@ -289,7 +289,7 @@ VOID *pthread_1_entry(VOID *pthread1_input) break; } } - + return(&pt1_status); } diff --git a/utility/rtos_compatibility_layers/posix/posix_signal_self_send_test.c b/utility/rtos_compatibility_layers/posix/posix_signal_self_send_test.c index 24e86b95..bbeb419f 100644 --- a/utility/rtos_compatibility_layers/posix/posix_signal_self_send_test.c +++ b/utility/rtos_compatibility_layers/posix/posix_signal_self_send_test.c @@ -116,7 +116,7 @@ struct sched_param param; queue_atrr.mq_maxmsg = 124; queue_atrr.mq_msgsize = MAX_MESSAGE_SIZE; #endif - + /* Init POSIX Wrapper */ storage_ptr = (VOID*) posix_initialize((VOID*)free_memory); @@ -130,56 +130,56 @@ queue_atrr.mq_msgsize = MAX_MESSAGE_SIZE; pthread_attr_init(&ptattr2); pthread_attr_init(&ptattr3); pthread_attr_init(&ptattr4); - pthread_attr_init(&ptattr5); + pthread_attr_init(&ptattr5); #endif /* Create a sched_param structure */ memset(¶m, 0, sizeof(param)); - + /* Now create all pthreads , firstly modify respective ptheread attribute with desired priority and stack start address and then create the pthread */ - + /* Create pthread 0. */ param.sched_priority = 10; pthread_attr_setschedparam(&ptattr0, ¶m); pthread_attr_setstackaddr(&ptattr0, storage_ptr ); - storage_ptr = (int *) storage_ptr + DEMO_STACK_SIZE; + storage_ptr = (int *) storage_ptr + DEMO_STACK_SIZE; pthread_create (&pthread_0, &ptattr0,pthread_0_entry,NULL); - + #if 0 /* Create pthread 1. */ param.sched_priority = 15; pthread_attr_setschedparam(&ptattr1, ¶m); pthread_attr_setstackaddr(&ptattr1, (VOID*) storage_ptr ); - storage_ptr = storage_ptr + DEMO_STACK_SIZE; + storage_ptr = storage_ptr + DEMO_STACK_SIZE; pthread_create (&pthread_1, &ptattr1,pthread_1_entry,NULL); - + /* Create pthread 2. */ param.sched_priority = 20; pthread_attr_setschedparam(&ptattr2, ¶m); pthread_attr_setstackaddr(&ptattr2, (VOID*) storage_ptr ); - storage_ptr = storage_ptr + DEMO_STACK_SIZE; + storage_ptr = storage_ptr + DEMO_STACK_SIZE; pthread_create (&pthread_2, &ptattr2,pthread_2_entry,NULL); /* Create pthread 3. */ param.sched_priority = 25; pthread_attr_setschedparam(&ptattr3, ¶m); pthread_attr_setstackaddr(&ptattr3, (VOID*) storage_ptr ); - storage_ptr = storage_ptr + DEMO_STACK_SIZE; + storage_ptr = storage_ptr + DEMO_STACK_SIZE; pthread_create (&pthread_3, &ptattr3,pthread_3_entry,NULL); - + /* Create pthread 4. */ param.sched_priority = 30; pthread_attr_setschedparam(&ptattr4, ¶m); pthread_attr_setstackaddr(&ptattr4, (VOID*) storage_ptr ); - storage_ptr = storage_ptr + DEMO_STACK_SIZE; + storage_ptr = storage_ptr + DEMO_STACK_SIZE; pthread_create (&pthread_4, &ptattr4,pthread_4_entry,NULL); - + /* Create pthread 5. */ param.sched_priority = 5; pthread_attr_setschedparam(&ptattr5, ¶m); pthread_attr_setstackaddr(&ptattr5, (VOID*) storage_ptr ); - storage_ptr = storage_ptr + DEMO_STACK_SIZE; + storage_ptr = storage_ptr + DEMO_STACK_SIZE; pthread_create (&pthread_5, &ptattr5,pthread_5_entry,NULL); /* Create a Message queue. */ @@ -191,7 +191,7 @@ queue_atrr.mq_msgsize = MAX_MESSAGE_SIZE; /* Create a Mutex */ pthread_mutex_init(&mutex1, NULL); #endif - + } VOID error_handler(void) @@ -213,7 +213,7 @@ VOID pthread_0_signal_handler(int signo) called from pthread 0. */ if (pthread_self() != pthread_0) { - + /* Call error handler. */ error_handler(); } @@ -221,7 +221,7 @@ VOID pthread_0_signal_handler(int signo) /* Check for proper signal. */ if (signo != 15) { - + /* Call error handler. */ error_handler(); } @@ -251,23 +251,23 @@ VOID *pthread_0_entry(VOID *pthread0_input) if (pt0_status) error_handler(); - /* This pthread simply sits in while-forever-sleep loop */ - while(1) + /* This pthread simply sits in while-forever-sleep loop */ + while(1) { /* Increment the pthread counter.*/ pthread_0_counter++; /* Raise the signal. */ pt0_status = pthread_kill(pthread_0, 15); - + /* Check for errors. */ if ((pt0_status) || (pthread_0_counter != pthread_0_signal_counter)) { error_handler(); break; } - -#if 0 + +#if 0 /* sleep for a while */ thread_0_sleep_time.tv_nsec = 999999999; thread_0_sleep_time.tv_sec = 4; @@ -288,13 +288,13 @@ INT pt1_status=0; VOID *pthread_1_entry(VOID *pthread1_input) { - + struct timespec thread_1_sleep_time={0,0}; /* This thread simply sends a messages to a queue shared by pthread 2. */ while(1) { - + /* Increment the thread counter. */ pthread_1_counter++; /* Send message to queue 0. */ @@ -320,7 +320,7 @@ INT pt2_status; VOID *pthread_2_entry(VOID *pthread2_input) { -CHAR msgr0[MAX_MESSAGE_SIZE]; +CHAR msgr0[MAX_MESSAGE_SIZE]; ULONG priority; struct timespec thread_2_sleep_time={0,0}; @@ -330,7 +330,7 @@ struct timespec thread_2_sleep_time={0,0}; /* Increment the thread counter. */ pthread_2_counter++; pt2_status = mq_receive(q_des,msgr0,MAX_MESSAGE_SIZE,&priority); - + if(pt2_status != 0) break; @@ -357,7 +357,7 @@ struct timespec thread_3_sleep_time={0,0}; /* Increment the thread counter. */ pthread_3_counter++; - /* Get the semaphore with suspension. */ + /* Get the semaphore with suspension. */ pt3_status = sem_wait(sem); /* Check status. */ diff --git a/utility/rtos_compatibility_layers/posix/posix_signal_sigmask_test.c b/utility/rtos_compatibility_layers/posix/posix_signal_sigmask_test.c index 2a7cf069..1f9c690b 100644 --- a/utility/rtos_compatibility_layers/posix/posix_signal_sigmask_test.c +++ b/utility/rtos_compatibility_layers/posix/posix_signal_sigmask_test.c @@ -61,7 +61,7 @@ VOID tx_application_define(VOID *first_unused_memory) struct sched_param param; - + /* Init POSIX Wrapper */ storage_ptr = (VOID*) posix_initialize((VOID*)free_memory); @@ -74,15 +74,15 @@ struct sched_param param; /* Create a sched_param structure */ memset(¶m, 0, sizeof(param)); - + /* Now create all pthreads , firstly modify respective ptheread attribute with desired priority and stack start address and then create the pthread */ - + /* Create pthread 0. */ param.sched_priority = 15; pthread_attr_setschedparam(&ptattr0, ¶m); pthread_attr_setstackaddr(&ptattr0, storage_ptr ); - storage_ptr = (UINT *) storage_ptr + DEMO_STACK_SIZE; + storage_ptr = (UINT *) storage_ptr + DEMO_STACK_SIZE; pthread_create (&pthread_0, &ptattr0,pthread_0_entry,NULL); @@ -90,7 +90,7 @@ struct sched_param param; param.sched_priority = 10; pthread_attr_setschedparam(&ptattr1, ¶m); pthread_attr_setstackaddr(&ptattr1, (VOID*) storage_ptr ); - storage_ptr = (UINT *) storage_ptr + DEMO_STACK_SIZE; + storage_ptr = (UINT *) storage_ptr + DEMO_STACK_SIZE; pthread_create (&pthread_1, &ptattr1,pthread_1_entry,NULL); } @@ -118,7 +118,7 @@ int status; called from pthread 0. */ if (pthread_self() != pthread_0) { - + /* Call error handler. */ error_handler(); } @@ -126,7 +126,7 @@ int status; /* Check for proper signal. */ if (signo != 13) { - + /* Call error handler. */ error_handler(); } @@ -138,11 +138,11 @@ int status; sigemptyset(&wait_set); sigaddset(&wait_set, 12); status = sigwait(&wait_set, &signal_received); - + /* Check for an error. */ if ((status) || (signal_received != 12)) { - + /* Call error handler. */ error_handler(); } @@ -161,7 +161,7 @@ int status; called from pthread 0. */ if (pthread_self() != pthread_0) { - + /* Call error handler. */ error_handler(); } @@ -169,7 +169,7 @@ int status; /* Check for proper signal. */ if (signo != 14) { - + /* Call error handler. */ error_handler(); } @@ -181,11 +181,11 @@ int status; sigemptyset(&wait_set); sigaddset(&wait_set, 13); status = sigwait(&wait_set, &signal_received); - + /* Check for an error. */ if ((status) || (signal_received != 13)) { - + /* Call error handler. */ error_handler(); } @@ -204,7 +204,7 @@ int status; called from pthread 0. */ if (pthread_self() != pthread_0) { - + /* Call error handler. */ error_handler(); } @@ -212,7 +212,7 @@ int status; /* Check for proper signal. */ if (signo != 15) { - + /* Call error handler. */ error_handler(); } @@ -224,11 +224,11 @@ int status; sigemptyset(&wait_set); sigaddset(&wait_set, 14); status = sigwait(&wait_set, &signal_received); - + /* Check for an error. */ if ((status) || (signal_received != 14)) { - + /* Call error handler. */ error_handler(); } @@ -242,7 +242,7 @@ VOID pthread_0_signal_handler16(int signo) called from pthread 0. */ if (pthread_self() != pthread_0) { - + /* Call error handler. */ error_handler(); } @@ -250,7 +250,7 @@ VOID pthread_0_signal_handler16(int signo) /* Check for proper signal. */ if (signo != 16) { - + /* Call error handler. */ error_handler(); } @@ -304,7 +304,7 @@ int signal_received; sigemptyset(&new_mask); sigaddset(&new_mask, 15); pt0_status = pthread_sigmask(SIG_BLOCK, &new_mask, &old_mask); - + /* Check for error. */ if (pt0_status) error_handler(); @@ -313,21 +313,21 @@ int signal_received; sigemptyset(&new_mask); sigaddset(&new_mask, 16); pt0_status = pthread_sigmask(SIG_BLOCK, &new_mask, &old_mask); - + /* Check for error. */ if (pt0_status) error_handler(); /* Simply restore the signal for this first test. */ pt0_status = pthread_sigmask(SIG_SETMASK, &old_mask, &old_mask); - + /* Check for error. */ if (pt0_status) error_handler(); - + /* Now do it again, but set a signal when the signal is masked. */ pt0_status = pthread_sigmask(SIG_BLOCK, &new_mask, &old_mask); - + /* Check for error. */ if (pt0_status) error_handler(); @@ -338,7 +338,7 @@ int signal_received; /* Check for error. */ if (pt0_status) error_handler(); - + /* Now unblock this signal to trigger the actual activation of the signal. */ pt0_status = pthread_sigmask(SIG_UNBLOCK, &new_mask, &old_mask); @@ -348,7 +348,7 @@ int signal_received; /* Now do it all again, but perform a sigwait when the signal is masked and pending. */ pt0_status = pthread_sigmask(SIG_BLOCK, &new_mask, &old_mask); - + /* Check for error. */ if (pt0_status) error_handler(); @@ -363,23 +363,23 @@ int signal_received; /* Wait on signal 16. */ sigemptyset(&wait_set); sigaddset(&wait_set, 16); - + /* Now perform a sigwait on signal 16. */ pt0_status = sigwait(&wait_set, &signal_received); - + /* Check for error. */ if ((pt0_status) || (pthread_0_signal_counter16 != 2) || (signal_received != 16)) error_handler(); - + /* Now unblock this signal to trigger the actual activation of the signal. */ pt0_status = pthread_sigmask(SIG_UNBLOCK, &new_mask, &old_mask); - + /* Check for error. */ if (pt0_status) error_handler(); - /* This pthread simply sits in while-forever-sleep loop */ - while(1) + /* This pthread simply sits in while-forever-sleep loop */ + while(1) { /* Increment the pthread counter.*/ pthread_0_counter++; @@ -388,22 +388,22 @@ int signal_received; sigemptyset(&wait_set); sigaddset(&wait_set, 15); - /* Signal wait. */ + /* Signal wait. */ pt0_status = sigwait(&wait_set, &signal_received); /* Check for errors. */ - if ((pt0_status) || + if ((pt0_status) || (signal_received != 15) || - (pthread_0_counter != pthread_0_signal_counter15) || + (pthread_0_counter != pthread_0_signal_counter15) || (pthread_0_counter != pthread_0_signal_counter14) || (pthread_0_counter != pthread_0_signal_counter13)) { - + /* In this test, this thread should never resume! */ error_handler(); /* Break out of the loop. */ - break; + break; } } @@ -415,12 +415,12 @@ INT pt1_status=0; VOID *pthread_1_entry(VOID *pthread1_input) { - + /* This thread simply sends a messages to a queue shared by pthread 2. */ while(1) { - + /* Increment the thread counter. */ pthread_1_counter++; @@ -434,9 +434,9 @@ VOID *pthread_1_entry(VOID *pthread1_input) pt1_status += pthread_kill(pthread_0, 12); /* Check for errors. */ - if ((pt1_status) || + if ((pt1_status) || (pthread_0_counter != (pthread_1_counter+1)) || - (pthread_1_counter != pthread_0_signal_counter15) || + (pthread_1_counter != pthread_0_signal_counter15) || (pthread_1_counter != pthread_0_signal_counter14) || (pthread_1_counter != pthread_0_signal_counter13)) { @@ -445,6 +445,6 @@ VOID *pthread_1_entry(VOID *pthread1_input) break; } } - + return(&pt1_status); } diff --git a/utility/rtos_compatibility_layers/posix/posix_signal_sigwait_test.c b/utility/rtos_compatibility_layers/posix/posix_signal_sigwait_test.c index 80d6402a..aa459735 100644 --- a/utility/rtos_compatibility_layers/posix/posix_signal_sigwait_test.c +++ b/utility/rtos_compatibility_layers/posix/posix_signal_sigwait_test.c @@ -59,7 +59,7 @@ VOID tx_application_define(VOID *first_unused_memory) struct sched_param param; - + /* Init POSIX Wrapper */ storage_ptr = (VOID*) posix_initialize((VOID*)free_memory); @@ -72,15 +72,15 @@ struct sched_param param; /* Create a sched_param structure */ memset(¶m, 0, sizeof(param)); - + /* Now create all pthreads , firstly modify respective ptheread attribute with desired priority and stack start address and then create the pthread */ - + /* Create pthread 0. */ param.sched_priority = 15; pthread_attr_setschedparam(&ptattr0, ¶m); pthread_attr_setstackaddr(&ptattr0, storage_ptr ); - storage_ptr = (UINT *) storage_ptr + DEMO_STACK_SIZE; + storage_ptr = (UINT *) storage_ptr + DEMO_STACK_SIZE; pthread_create (&pthread_0, &ptattr0,pthread_0_entry,NULL); @@ -88,7 +88,7 @@ struct sched_param param; param.sched_priority = 10; pthread_attr_setschedparam(&ptattr1, ¶m); pthread_attr_setstackaddr(&ptattr1, (VOID*) storage_ptr ); - storage_ptr = (UINT *) storage_ptr + DEMO_STACK_SIZE; + storage_ptr = (UINT *) storage_ptr + DEMO_STACK_SIZE; pthread_create (&pthread_1, &ptattr1,pthread_1_entry,NULL); } @@ -116,7 +116,7 @@ int status; called from pthread 0. */ if (pthread_self() != pthread_0) { - + /* Call error handler. */ error_handler(); } @@ -124,7 +124,7 @@ int status; /* Check for proper signal. */ if (signo != 13) { - + /* Call error handler. */ error_handler(); } @@ -136,11 +136,11 @@ int status; sigemptyset(&wait_set); sigaddset(&wait_set, 12); status = sigwait(&wait_set, &signal_received); - + /* Check for an error. */ if ((status) || (signal_received != 12)) { - + /* Call error handler. */ error_handler(); } @@ -159,7 +159,7 @@ int status; called from pthread 0. */ if (pthread_self() != pthread_0) { - + /* Call error handler. */ error_handler(); } @@ -167,7 +167,7 @@ int status; /* Check for proper signal. */ if (signo != 14) { - + /* Call error handler. */ error_handler(); } @@ -179,11 +179,11 @@ int status; sigemptyset(&wait_set); sigaddset(&wait_set, 13); status = sigwait(&wait_set, &signal_received); - + /* Check for an error. */ if ((status) || (signal_received != 13)) { - + /* Call error handler. */ error_handler(); } @@ -202,7 +202,7 @@ int status; called from pthread 0. */ if (pthread_self() != pthread_0) { - + /* Call error handler. */ error_handler(); } @@ -210,7 +210,7 @@ int status; /* Check for proper signal. */ if (signo != 15) { - + /* Call error handler. */ error_handler(); } @@ -222,11 +222,11 @@ int status; sigemptyset(&wait_set); sigaddset(&wait_set, 14); status = sigwait(&wait_set, &signal_received); - + /* Check for an error. */ if ((status) || (signal_received != 14)) { - + /* Call error handler. */ error_handler(); } @@ -265,8 +265,8 @@ int signal_received; if (pt0_status) error_handler(); - /* This pthread simply sits in while-forever-sleep loop */ - while(1) + /* This pthread simply sits in while-forever-sleep loop */ + while(1) { /* Increment the pthread counter.*/ pthread_0_counter++; @@ -275,22 +275,22 @@ int signal_received; sigemptyset(&wait_set); sigaddset(&wait_set, 15); - /* Signal wait. */ + /* Signal wait. */ pt0_status = sigwait(&wait_set, &signal_received); /* Check for errors. */ - if ((pt0_status) || + if ((pt0_status) || (signal_received != 15) || - (pthread_0_counter != pthread_0_signal_counter15) || + (pthread_0_counter != pthread_0_signal_counter15) || (pthread_0_counter != pthread_0_signal_counter14) || (pthread_0_counter != pthread_0_signal_counter13)) { - + /* In this test, this thread should never resume! */ error_handler(); /* Break out of the loop. */ - break; + break; } } @@ -302,12 +302,12 @@ INT pt1_status=0; VOID *pthread_1_entry(VOID *pthread1_input) { - + /* This thread simply sends a messages to a queue shared by pthread 2. */ while(1) { - + /* Increment the thread counter. */ pthread_1_counter++; @@ -321,9 +321,9 @@ VOID *pthread_1_entry(VOID *pthread1_input) pt1_status += pthread_kill(pthread_0, 12); /* Check for errors. */ - if ((pt1_status) || + if ((pt1_status) || (pthread_0_counter != (pthread_1_counter+1)) || - (pthread_1_counter != pthread_0_signal_counter15) || + (pthread_1_counter != pthread_0_signal_counter15) || (pthread_1_counter != pthread_0_signal_counter14) || (pthread_1_counter != pthread_0_signal_counter13)) { @@ -332,7 +332,7 @@ VOID *pthread_1_entry(VOID *pthread1_input) break; } } - + return(&pt1_status); } diff --git a/utility/rtos_compatibility_layers/posix/posix_signal_suspended_thread_test.c b/utility/rtos_compatibility_layers/posix/posix_signal_suspended_thread_test.c index 723c80db..40d11eea 100644 --- a/utility/rtos_compatibility_layers/posix/posix_signal_suspended_thread_test.c +++ b/utility/rtos_compatibility_layers/posix/posix_signal_suspended_thread_test.c @@ -66,7 +66,7 @@ VOID tx_application_define(VOID *first_unused_memory) struct sched_param param; - + /* Init POSIX Wrapper */ storage_ptr = (VOID*) posix_initialize((VOID*)free_memory); @@ -79,15 +79,15 @@ struct sched_param param; /* Create a sched_param structure */ memset(¶m, 0, sizeof(param)); - + /* Now create all pthreads , firstly modify respective ptheread attribute with desired priority and stack start address and then create the pthread */ - + /* Create pthread 0. */ param.sched_priority = 15; pthread_attr_setschedparam(&ptattr0, ¶m); pthread_attr_setstackaddr(&ptattr0, storage_ptr ); - storage_ptr = (UINT *) storage_ptr + DEMO_STACK_SIZE; + storage_ptr = (UINT *) storage_ptr + DEMO_STACK_SIZE; pthread_create (&pthread_0, &ptattr0,pthread_0_entry,NULL); @@ -95,7 +95,7 @@ struct sched_param param; param.sched_priority = 10; pthread_attr_setschedparam(&ptattr1, ¶m); pthread_attr_setstackaddr(&ptattr1, (VOID*) storage_ptr ); - storage_ptr = (UINT *) storage_ptr + DEMO_STACK_SIZE; + storage_ptr = (UINT *) storage_ptr + DEMO_STACK_SIZE; pthread_create (&pthread_1, &ptattr1,pthread_1_entry,NULL); @@ -123,7 +123,7 @@ VOID pthread_0_signal_handler13(int signo) called from pthread 0. */ if (pthread_self() != pthread_0) { - + /* Call error handler. */ error_handler(); } @@ -131,7 +131,7 @@ VOID pthread_0_signal_handler13(int signo) /* Check for proper signal. */ if (signo != 13) { - + /* Call error handler. */ error_handler(); } @@ -148,7 +148,7 @@ VOID pthread_0_signal_handler14(int signo) called from pthread 0. */ if (pthread_self() != pthread_0) { - + /* Call error handler. */ error_handler(); } @@ -156,7 +156,7 @@ VOID pthread_0_signal_handler14(int signo) /* Check for proper signal. */ if (signo != 14) { - + /* Call error handler. */ error_handler(); } @@ -176,7 +176,7 @@ VOID pthread_0_signal_handler15(int signo) called from pthread 0. */ if (pthread_self() != pthread_0) { - + /* Call error handler. */ error_handler(); } @@ -184,7 +184,7 @@ VOID pthread_0_signal_handler15(int signo) /* Check for proper signal. */ if (signo != 15) { - + /* Call error handler. */ error_handler(); } @@ -226,16 +226,16 @@ VOID *pthread_0_entry(VOID *pthread0_input) error_handler(); - /* Get the semaphore with suspension. */ + /* Get the semaphore with suspension. */ pt0_status = sem_wait(sem); - /* This pthread simply sits in while-forever-sleep loop */ - while(1) + /* This pthread simply sits in while-forever-sleep loop */ + while(1) { /* Increment the pthread counter.*/ pthread_0_counter++; - /* Get the semaphore with suspension. */ + /* Get the semaphore with suspension. */ pt0_status = sem_wait(sem); /* In this test, this thread should never resume! */ @@ -244,9 +244,9 @@ VOID *pthread_0_entry(VOID *pthread0_input) /* Check for error condition. */ if (pt0_status) { - + /* Break out of the loop. */ - break; + break; } } @@ -258,12 +258,12 @@ INT pt1_status=0; VOID *pthread_1_entry(VOID *pthread1_input) { - + /* This thread simply sends a messages to a queue shared by pthread 2. */ while(1) { - + /* Increment the thread counter. */ pthread_1_counter++; @@ -271,9 +271,9 @@ VOID *pthread_1_entry(VOID *pthread1_input) pt1_status = pthread_kill(pthread_0, 15); /* Check for errors. */ - if ((pt1_status) || + if ((pt1_status) || (pthread_0_counter != 1) || - (pthread_1_counter != pthread_0_signal_counter15) || + (pthread_1_counter != pthread_0_signal_counter15) || (pthread_1_counter != pthread_0_signal_counter14) || (pthread_1_counter != pthread_0_signal_counter13)) { @@ -282,7 +282,7 @@ VOID *pthread_1_entry(VOID *pthread1_input) break; } } - + return(&pt1_status); } diff --git a/utility/rtos_compatibility_layers/posix/pthread.h b/utility/rtos_compatibility_layers/posix/pthread.h index bbd0761c..b248a38b 100644 --- a/utility/rtos_compatibility_layers/posix/pthread.h +++ b/utility/rtos_compatibility_layers/posix/pthread.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -33,13 +34,6 @@ /* This file defines the constants, structures, etc.needed to */ /* implement the Evacuation Kit for POSIX Users (POSIX) */ /* */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ #ifndef _PTHREAD_H diff --git a/utility/rtos_compatibility_layers/posix/px_abs_time_to_rel_ticks.c b/utility/rtos_compatibility_layers/posix/px_abs_time_to_rel_ticks.c index 18a64e35..79a7b90f 100644 --- a/utility/rtos_compatibility_layers/posix/px_abs_time_to_rel_ticks.c +++ b/utility/rtos_compatibility_layers/posix/px_abs_time_to_rel_ticks.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -43,12 +44,6 @@ /* timespec structure into the relative number of timer ticks until */ /* that time will occur. */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ ULONG posix_abs_time_to_rel_ticks(struct timespec *abs_timeout) { @@ -57,7 +52,7 @@ ULONG posix_abs_time_to_rel_ticks(struct timespec *abs_timeout) current_ticks = tx_time_get(); /* convert ns to ticks (will lose any ns < 1 tick) */ ticks_ns = abs_timeout->tv_nsec / NANOSECONDS_IN_CPU_TICK; - /* + /* * if ns < 1 tick were lost, bump up to next tick so the delay is never * less than what was specified. */ diff --git a/utility/rtos_compatibility_layers/posix/px_clock_getres.c b/utility/rtos_compatibility_layers/posix/px_clock_getres.c index 80d16f66..5153500b 100644 --- a/utility/rtos_compatibility_layers/posix/px_clock_getres.c +++ b/utility/rtos_compatibility_layers/posix/px_clock_getres.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,51 +27,45 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* clock_getres PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* clock_getres PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This subroutine returns the Clock resolution of the Threadx real */ /* time clock in nanoseconds */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* clockid_t, tspec */ /* */ -/* OUTPUT */ -/* */ +/* OUTPUT */ +/* */ /* error code */ /* */ -/* CALLS */ -/* */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* CALLS */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT clock_getres(clockid_t t, struct timespec * tspec) { - + if(t==CLOCK_REALTIME) { if(tspec) tspec->tv_nsec= NANOSECONDS_IN_CPU_TICK; return(OK); } else return(EINVAL); - + } diff --git a/utility/rtos_compatibility_layers/posix/px_clock_gettime.c b/utility/rtos_compatibility_layers/posix/px_clock_gettime.c index f7c96797..964c10c7 100644 --- a/utility/rtos_compatibility_layers/posix/px_clock_gettime.c +++ b/utility/rtos_compatibility_layers/posix/px_clock_gettime.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,49 +27,43 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* clock_gettime PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* clock_gettime PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This subroutine returns the time. The source of the time */ /* is the internal Threadx timer variable, which keeps track */ /* of the number of ticks of the Threadx timer ISR. */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* clockid_t, tspec */ /* */ -/* OUTPUT */ -/* */ +/* OUTPUT */ +/* */ /* error code */ /* */ -/* CALLS */ -/* */ -/* tx_time_get ThreadX function */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* CALLS */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* tx_time_get ThreadX function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT clock_gettime(clockid_t t, struct timespec * tspec) { ULONG tx_time; - + if(t==CLOCK_REALTIME) { tx_time=tx_time_get(); @@ -76,9 +71,9 @@ INT clock_gettime(clockid_t t, struct timespec * tspec) tspec->tv_sec = tx_time / CPU_TICKS_PER_SECOND; tspec->tv_nsec = (ULONG) ((tx_time - tspec->tv_sec*CPU_TICKS_PER_SECOND) * NANOSECONDS_IN_CPU_TICK); - + return(OK); } else return(EINVAL); - + } diff --git a/utility/rtos_compatibility_layers/posix/px_clock_settime.c b/utility/rtos_compatibility_layers/posix/px_clock_settime.c index 588de88f..70dbbe86 100644 --- a/utility/rtos_compatibility_layers/posix/px_clock_settime.c +++ b/utility/rtos_compatibility_layers/posix/px_clock_settime.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,50 +27,44 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* clock_settime PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* clock_settime PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This subroutine sets the internal Threadx timer tick variable */ /* to the time specificed in the tspec variable after conversion */ /* if tspec->tv_sec is 0 the clock with be set to the value of */ /* tspec->tv_nsec */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* clockid_t, tspec */ /* */ -/* OUTPUT */ -/* */ +/* OUTPUT */ +/* */ /* error code */ /* */ -/* CALLS */ -/* */ -/* tx_time_set ThreadX function */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* CALLS */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* tx_time_set ThreadX function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT clock_settime(clockid_t t, const struct timespec * tspec) { ULONG tx_time; - + if(t==CLOCK_REALTIME) { tx_time=(ULONG)((tspec->tv_sec * CPU_TICKS_PER_SECOND) + (tspec->tv_nsec / NANOSECONDS_IN_CPU_TICK)); diff --git a/utility/rtos_compatibility_layers/posix/px_cond_broadcast.c b/utility/rtos_compatibility_layers/posix/px_cond_broadcast.c index b9c5faee..f9c8f151 100644 --- a/utility/rtos_compatibility_layers/posix/px_cond_broadcast.c +++ b/utility/rtos_compatibility_layers/posix/px_cond_broadcast.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,18 +27,18 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_cond_broadcast PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_cond_broadcast PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* These functions shall unblock all threads currently blocked on a */ /* specified condition variable cond. */ /* If more than one thread is blocked on a condition variable, */ @@ -53,20 +54,20 @@ /* calling pthread_cond_wait or pthread_cond_timedwait have associated */ /* with the condition variable during their waits; however, */ /* if predictable scheduling behavior is required, then that mutex */ -/* shall be locked by the thread calling pthread_cond_broadcast. */ +/* shall be locked by the thread calling pthread_cond_broadcast. */ /* The pthread_cond_broadcast function shall have no effect if there */ /* are no threads currently blocked on cond. */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* cond condition variable */ /* */ -/* OUTPUT */ -/* */ +/* OUTPUT */ +/* */ /* Ok if successful */ /* Error in case of any errors */ /* */ -/* CALLS */ +/* CALLS */ /* */ /* tx_semaphore_prioritize line up pthreads waiting at semaphore*/ /* tx_thread_identify to check which pthread? */ @@ -74,20 +75,14 @@ /* tx_semaphore_put ThreadX semaphore put service */ /* tx_thread_preemption_change to enable thread preemption */ /* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* CALLED BY */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_cond_broadcast(pthread_cond_t *cond) { - + TX_SEMAPHORE *semaphore_ptr; TX_THREAD *thread; UINT status; @@ -96,13 +91,13 @@ UINT old_threshold,dummy; /* Get the condition variable's internal semaphore. */ - /* Simply convert the condition variable control block into a semaphore a cast */ + /* Simply convert the condition variable control block into a semaphore a cast */ semaphore_ptr = (&( cond->cond_semaphore )); sem_count = semaphore_ptr->tx_semaphore_suspended_count; if (!sem_count) return(OK); - + status = tx_semaphore_prioritize(semaphore_ptr); if ( status != TX_SUCCESS) @@ -111,17 +106,17 @@ UINT old_threshold,dummy; posix_set_pthread_errno(EINVAL); return(EINVAL); } - + /* get to know about current thread */ thread = tx_thread_identify(); /* Got the current thread , now raise its preemption threshold */ /* that way the current thread does not get descheduled when */ /* threads with higher priority are activated */ - tx_thread_preemption_change(thread,0,&old_threshold); + tx_thread_preemption_change(thread,0,&old_threshold); while( sem_count) - { + { status = tx_semaphore_put(semaphore_ptr); if ( status != TX_SUCCESS) diff --git a/utility/rtos_compatibility_layers/posix/px_cond_destroy.c b/utility/rtos_compatibility_layers/posix/px_cond_destroy.c index 54dd1eb7..efa99be1 100644 --- a/utility/rtos_compatibility_layers/posix/px_cond_destroy.c +++ b/utility/rtos_compatibility_layers/posix/px_cond_destroy.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -25,18 +26,18 @@ #include "pthread.h" /* Posix API */ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_cond_destroy PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_cond_destroy PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* The pthread_cond_destroy function shall destroy the given condition */ /* variable specified by cond; the object becomes, in effect, */ /* uninitialized. */ @@ -44,29 +45,23 @@ /* pthread_cond_init;referencing the object after it has been destroyed*/ /* returns error. */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* cond condition variable object */ /* */ /* OUTPUT */ -/* */ -/* OK If successful */ -/* EINVAL If error */ /* */ -/* CALLS */ +/* OK If successful */ +/* EINVAL If error */ +/* */ +/* CALLS */ /* */ /* tx_semaphore_delete Deletes a semaphore internal to */ /* to the cond variable */ /* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* CALLED BY */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_cond_destroy(pthread_cond_t *cond) @@ -74,18 +69,18 @@ INT pthread_cond_destroy(pthread_cond_t *cond) TX_SEMAPHORE *semaphore_ptr; UINT status; - + if (cond->in_use == TX_FALSE) { posix_errno = EINVAL; posix_set_pthread_errno(EINVAL); return(EINVAL); - } + } else { cond->in_use = TX_FALSE; /* Get the condition variable's internal semaphore. */ - /* Simply convert the Condition variable control block into a semaphore a cast */ + /* Simply convert the Condition variable control block into a semaphore a cast */ semaphore_ptr = (&( cond->cond_semaphore )); status = tx_semaphore_delete(semaphore_ptr); if (status != TX_SUCCESS) @@ -93,8 +88,8 @@ UINT status; posix_errno = EINVAL; posix_set_pthread_errno(EINVAL); return(EINVAL); - } + } return(OK); - } + } } diff --git a/utility/rtos_compatibility_layers/posix/px_cond_init.c b/utility/rtos_compatibility_layers/posix/px_cond_init.c index e204a13f..b376132d 100644 --- a/utility/rtos_compatibility_layers/posix/px_cond_init.c +++ b/utility/rtos_compatibility_layers/posix/px_cond_init.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,18 +27,18 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_cond_init PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_cond_init PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function shall initialize the condition variable referenced by */ /* cond with attributes referenced by attr. If attr is NULL,the default*/ /* condition variable attributes shall be used; the effect is the same */ @@ -45,28 +46,22 @@ /* object. Upon successful initialization, the state of the condition */ /* variable shall become initialized. */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* Nothing */ /* */ -/* OUTPUT */ -/* */ +/* OUTPUT */ +/* */ /* cond condition variable object */ /* attr attributes */ /* */ -/* CALLS */ -/* */ -/* tx_semaphore_create create a semaphore internal to */ -/* cond variable */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* CALLS */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* tx_semaphore_create create a semaphore internal to */ +/* cond variable */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_cond_init(pthread_cond_t *cond, pthread_condattr_t *attr) @@ -74,11 +69,11 @@ INT pthread_cond_init(pthread_cond_t *cond, pthread_condattr_t *attr) TX_SEMAPHORE *semaphore_ptr; UINT status; - + cond->in_use = TX_TRUE; /* Get the condition variable's internal semaphore. */ - /* Simply convert the COndition variable control block into a semaphore a cast */ - semaphore_ptr = (&( cond->cond_semaphore )); + /* Simply convert the COndition variable control block into a semaphore a cast */ + semaphore_ptr = (&( cond->cond_semaphore )); /* Now create the internal semaphore for this cond variable */ status = tx_semaphore_create(semaphore_ptr,"csem",0); if (status != TX_SUCCESS) diff --git a/utility/rtos_compatibility_layers/posix/px_cond_signal.c b/utility/rtos_compatibility_layers/posix/px_cond_signal.c index 6d01a6e7..b1f4f285 100644 --- a/utility/rtos_compatibility_layers/posix/px_cond_signal.c +++ b/utility/rtos_compatibility_layers/posix/px_cond_signal.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,18 +27,18 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_cond_signal PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_cond_signal PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function shall unblock at least one of the threads that are */ /* blocked on the specified condition variable cond */ /* (if any threads are blocked on cond).If more than one thread is */ @@ -58,28 +59,22 @@ /* This function shall have no effect if there are no threads currently*/ /* blocked on cond. */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* Nothing */ /* */ -/* OUTPUT */ -/* */ +/* OUTPUT */ +/* */ /* Nothing */ /* */ -/* CALLS */ +/* CALLS */ /* */ /* tx_semaphore_prioritize line up pthreads waiting at semaphore*/ /* tx_semaphore_put ThreadX semaphore put service */ /* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* CALLED BY */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_cond_signal(pthread_cond_t *cond) @@ -89,7 +84,7 @@ TX_SEMAPHORE *semaphore_ptr; UINT status; /* Get the condition variable's internal semaphore. */ - /* Simply convert the COndition variable control block into a semaphore a cast */ + /* Simply convert the COndition variable control block into a semaphore a cast */ semaphore_ptr = (&( cond->cond_semaphore )); if ( semaphore_ptr->tx_semaphore_suspended_count) { @@ -107,6 +102,6 @@ UINT status; posix_set_pthread_errno(EINVAL); return(EINVAL); } - } + } return(OK); } diff --git a/utility/rtos_compatibility_layers/posix/px_cond_timedwait.c b/utility/rtos_compatibility_layers/posix/px_cond_timedwait.c index fd82c1d0..1b4660d4 100644 --- a/utility/rtos_compatibility_layers/posix/px_cond_timedwait.c +++ b/utility/rtos_compatibility_layers/posix/px_cond_timedwait.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,17 +27,17 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_cond_timedwait PORTABLE C */ -/* 6.1.7 */ -/* AUTHOR */ -/* */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_cond_timedwait PORTABLE C */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ /* William E. Lamie, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ +/* */ +/* DESCRIPTION */ /* */ /* This function shall block on a condition variable. They shall be */ /* called with mutex locked by the calling thread or undefined behavior*/ @@ -61,38 +62,32 @@ /* pthread_cond_wait operations on the same condition variable is */ /* undefined; that is, a condition variable becomes bound to a unique */ /* mutex when a thread waits on the condition variable, and this */ -/* (dynamic) binding shall end when the wait returns. */ +/* (dynamic) binding shall end when the wait returns. */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* cond condition variable */ /* mutex mutex to be associated with condition */ /* variable */ /* abstime time interval for wait */ /* */ -/* OUTPUT */ -/* */ +/* OUTPUT */ +/* */ /* OK if succesfull */ /* ERROR in case of any error */ /* */ -/* CALLS */ +/* CALLS */ /* */ /* pthread_mutex_unlock unlocks the mutex held by the caller */ /* tx_semaphore_get try to get sempaphore internal to cond */ /* tx_semaphore_prioritize prioritize all suspended pthreads */ /* pthread_mutex_lock lock the mutex */ /* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William Lamie Initial Version 6.1.7 */ -/* */ -/**************************************************************************/ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/**************************************************************************/ INT pthread_cond_timedwait(pthread_cond_t *cond,pthread_mutex_t *mutex, struct timespec *abstime) { @@ -107,11 +102,11 @@ TX_THREAD *thread; thread = tx_thread_identify(); /* Raise its preemption threshold so it does not get descheduled. */ - tx_thread_preemption_change(thread,0,&old_threshold); + tx_thread_preemption_change(thread,0,&old_threshold); pthread_mutex_unlock(mutex); semaphore_ptr = (&( cond->cond_semaphore )); - + wait_option = posix_abs_time_to_rel_ticks(abstime); status = tx_semaphore_get(semaphore_ptr, wait_option); @@ -139,6 +134,6 @@ TX_THREAD *thread; return(EINVAL); } pthread_mutex_lock(mutex); - + return(OK); } diff --git a/utility/rtos_compatibility_layers/posix/px_cond_wait.c b/utility/rtos_compatibility_layers/posix/px_cond_wait.c index 0e05418e..fbbbcd76 100644 --- a/utility/rtos_compatibility_layers/posix/px_cond_wait.c +++ b/utility/rtos_compatibility_layers/posix/px_cond_wait.c @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -25,17 +26,17 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_cond_wait PORTABLE C */ -/* 6.1.7 */ -/* AUTHOR */ -/* */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_cond_wait PORTABLE C */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ /* William E. Lamie, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ +/* */ +/* DESCRIPTION */ /* */ /* This function shall block on a condition variable. They shall be */ /* called with mutex locked by the calling thread or undefined behavior*/ @@ -58,37 +59,31 @@ /* pthread_cond_wait operations on the same condition variable is */ /* undefined; that is, a condition variable becomes bound to a unique */ /* mutex when a thread waits on the condition variable, and this */ -/* (dynamic) binding shall end when the wait returns. */ +/* (dynamic) binding shall end when the wait returns. */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* cond condition variable */ /* mutex mutex to be associated with condition */ /* variable */ /* */ -/* OUTPUT */ -/* */ +/* OUTPUT */ +/* */ /* OK if succesfull */ /* ERROR in case of any error */ /* */ -/* CALLS */ +/* CALLS */ /* */ /* pthread_mutex_unlock unlocks the mutex held by the caller */ /* tx_semaphore_get try to get sempaphore internal to cond */ /* tx_semaphore_prioritize prioritize all suspended pthreads */ /* pthread_mutex_lock lock the mutex */ /* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ -/**************************************************************************/ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/**************************************************************************/ INT pthread_cond_wait(pthread_cond_t *cond, pthread_mutex_t *mutex) { @@ -101,7 +96,7 @@ TX_THREAD *thread; thread = tx_thread_identify(); /* Raise its preemption threshold so it does not get descheduled. */ - tx_thread_preemption_change(thread,0,&old_threshold); + tx_thread_preemption_change(thread,0,&old_threshold); pthread_mutex_unlock(mutex); @@ -128,7 +123,7 @@ TX_THREAD *thread; posix_set_pthread_errno(EINVAL); return(EINVAL); } - + pthread_mutex_lock(mutex); return(OK); } diff --git a/utility/rtos_compatibility_layers/posix/px_error.c b/utility/rtos_compatibility_layers/posix/px_error.c index f7b93cbd..7d950e14 100644 --- a/utility/rtos_compatibility_layers/posix/px_error.c +++ b/utility/rtos_compatibility_layers/posix/px_error.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -56,51 +57,45 @@ /* */ /* POSIX internal code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ VOID posix_error_handler(ULONG error_code) { while (error_code) { ; } } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* posix_internal_error PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* posix_internal_error PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function is invoked whenever an error is encountered */ -/* in the POSIX code. */ -/* */ -/* INPUT */ -/* */ -/* error_code Error code to handle */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* POSIX internal code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function is invoked whenever an error is encountered */ +/* in the POSIX code. */ +/* */ +/* INPUT */ +/* */ +/* error_code Error code to handle */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* POSIX internal code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ diff --git a/utility/rtos_compatibility_layers/posix/px_in_thread_context.c b/utility/rtos_compatibility_layers/posix/px_in_thread_context.c index a03d20a1..919ef2c6 100644 --- a/utility/rtos_compatibility_layers/posix/px_in_thread_context.c +++ b/utility/rtos_compatibility_layers/posix/px_in_thread_context.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -57,12 +58,6 @@ /* */ /* posix internal code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ ULONG posix_in_thread_context(VOID) { @@ -72,7 +67,7 @@ ULONG posix_in_thread_context(VOID) #ifndef TX_TIMER_PROCESS_IN_ISR extern TX_THREAD _tx_timer_thread; #endif - + /* Return TX_FALSE if any of the following are true: - we are in the scheduling loop (not in a thread); - we are in an ISR @@ -90,10 +85,10 @@ ULONG posix_in_thread_context(VOID) || (_tx_thread_system_state) /* In an ISR */ #ifndef TX_TIMER_PROCESS_IN_ISR /* Timer routine */ - || (_tx_thread_current_ptr == &_tx_timer_thread) + || (_tx_thread_current_ptr == &_tx_timer_thread) #endif ) - + { /* We are NOT in thread (thread) context. */ return (TX_FALSE); diff --git a/utility/rtos_compatibility_layers/posix/px_int.h b/utility/rtos_compatibility_layers/posix/px_int.h index f6d67ce4..1b0d085a 100644 --- a/utility/rtos_compatibility_layers/posix/px_int.h +++ b/utility/rtos_compatibility_layers/posix/px_int.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -33,15 +34,6 @@ /* This file defines the constants, structures, etc.needed to */ /* implement the Evacuation Kit for POSIX Users (POSIX) */ /* */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* 10-31-2022 Scott Larson Remove unneeded values, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ #ifndef _TX_PX_INT_H @@ -68,7 +60,7 @@ extern TX_THREAD * _tx_thread_execute_ptr; /* declares posix objects in the px_pth_init.c file */ #ifdef PX_OBJECT_INIT -#define PX_OBJECT_DECLARE +#define PX_OBJECT_DECLARE #else #define PX_OBJECT_DECLARE extern #endif @@ -93,7 +85,7 @@ PX_OBJECT_DECLARE TX_THREAD posix_system_manager; PX_OBJECT_DECLARE TX_BYTE_POOL posix_heap_byte_pool; /* Define a static pool of pthread Control Blocks (TCB). If more pthreades are - required the constant PTHREAD_THREADS_MAX (in tx_posix.h) may be modified. */ + required the constant PTHREAD_THREADS_MAX (in tx_posix.h) may be modified. */ PX_OBJECT_DECLARE POSIX_TCB ptcb_pool[PTHREAD_THREADS_MAX]; #if POSIX_MAX_QUEUES!= 0 @@ -123,11 +115,11 @@ PX_OBJECT_DECLARE pthread_mutexattr_t posix_default_mutex_attr; PX_OBJECT_DECLARE unsigned int posix_errno; - + /**************************************************************************/ /* Local prototypes */ /**************************************************************************/ -/* Define Evacuation Kit for POSIX function prototypes. */ +/* Define Evacuation Kit for POSIX function prototypes. */ INT posix_get_pthread_errno(pthread_t ptid); @@ -159,7 +151,7 @@ VOID posix_internal_error(ULONG error_code); VOID posix_error_handler(ULONG error_code); INT posix_memory_allocate(ULONG size, VOID **memory_ptr); - + INT posix_queue_delete(POSIX_MSG_QUEUE * q_ptr); VOID posix_putback_queue(TX_QUEUE * qid); diff --git a/utility/rtos_compatibility_layers/posix/px_internal_signal_dispatch.c b/utility/rtos_compatibility_layers/posix/px_internal_signal_dispatch.c index e7a7e4be..f23afb60 100644 --- a/utility/rtos_compatibility_layers/posix/px_internal_signal_dispatch.c +++ b/utility/rtos_compatibility_layers/posix/px_internal_signal_dispatch.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -61,12 +62,6 @@ /* */ /* Internal Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ void internal_signal_dispatch(ULONG id) { @@ -81,7 +76,7 @@ VOID (*handler)(int); /* Determine if the desired signal is valid. */ if (id > SIGRTMAX) { - + /* System error! */ posix_internal_error(444); return; @@ -108,7 +103,7 @@ VOID (*handler)(int); /* See if there is a signal handler setup for this signal. */ if (handler) { - + /* Yes, there is a signal handler - call it! */ (handler)((int) id); } @@ -120,47 +115,47 @@ VOID (*handler)(int); tx_event_flags_set(&(target_thread -> signals.signal_event_flags), ~(((ULONG) 1) << id), TX_AND); /* Now we need to clear this signal and terminate this signal handler thread. */ - + /* Disable interrupts. */ TX_DISABLE - + /* Clear this signal from the pending list. */ target_thread -> signals.signal_pending.signal_set = target_thread -> signals.signal_pending.signal_set & ~(((unsigned long) 1) << id); - + /* Decrement the signal nesting count. */ target_thread -> signals.signal_nesting_depth--; - + /* Is this the last nested signal leaving? */ if (target_thread -> signals.signal_nesting_depth == 0) { - + /* Clear the top signal thread link and resume the target thread. */ target_thread -> signals.top_signal_thread = NULL; - + /* Restore interrupts. */ TX_RESTORE - + /* Resume the target thread. */ tx_thread_resume((TX_THREAD *) target_thread); } else { - + /* Otherwise, there are more signal threads still active. */ - + /* Setup the new top signal thread pointer. */ target_thread -> signals.top_signal_thread = signal_thread -> signals.next_signal_thread; /* Restore interrupts. */ TX_RESTORE - + /* Resume the signal handler thread. */ tx_thread_resume((TX_THREAD *) signal_thread -> signals.next_signal_thread); } /* Now we need to mark this signal thread for destruction. */ posix_destroy_pthread(signal_thread,(VOID *) 0); - + /* Self-suspend the current signal thread. */ - tx_thread_suspend((TX_THREAD *) signal_thread); + tx_thread_suspend((TX_THREAD *) signal_thread); } diff --git a/utility/rtos_compatibility_layers/posix/px_memory_allocate.c b/utility/rtos_compatibility_layers/posix/px_memory_allocate.c index c30a6c0b..5024e8d1 100644 --- a/utility/rtos_compatibility_layers/posix/px_memory_allocate.c +++ b/utility/rtos_compatibility_layers/posix/px_memory_allocate.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -60,12 +61,6 @@ /* */ /* POSIX internal code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ INT posix_memory_allocate(ULONG size, VOID **memory_ptr) { @@ -84,7 +79,7 @@ INT retval; /* Attempt to allocate the desired memory from the POSIX heap. Do not wait - if memory isn't available, flag an error. */ retval = tx_byte_allocate((TX_BYTE_POOL *)&posix_heap_byte_pool, memory_ptr, - size, TX_NO_WAIT); + size, TX_NO_WAIT); /* Make sure the memory was obtained successfully. */ if (retval) @@ -95,5 +90,5 @@ INT retval; return(ERROR); } /* Return to caller. */ - return(retval); + return(retval); } diff --git a/utility/rtos_compatibility_layers/posix/px_memory_release.c b/utility/rtos_compatibility_layers/posix/px_memory_release.c index c071b97a..b028c47a 100644 --- a/utility/rtos_compatibility_layers/posix/px_memory_release.c +++ b/utility/rtos_compatibility_layers/posix/px_memory_release.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -58,22 +59,16 @@ /* */ /* POSIX internal code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ VOID posix_memory_release(VOID * memory_ptr) { - /* Check if memory_ptr is part of the POSIX byte pool, - * if not just return */ - if (((CHAR *)memory_ptr >= - (CHAR *)&posix_heap_byte_pool.tx_byte_pool_start) || - ((CHAR *)memory_ptr <= - (CHAR *)posix_heap_byte_pool.tx_byte_pool_start + /* Check if memory_ptr is part of the POSIX byte pool, + * if not just return */ + if (((CHAR *)memory_ptr >= + (CHAR *)&posix_heap_byte_pool.tx_byte_pool_start) || + ((CHAR *)memory_ptr <= + (CHAR *)posix_heap_byte_pool.tx_byte_pool_start + posix_heap_byte_pool.tx_byte_pool_size)) { tx_byte_release(memory_ptr); } diff --git a/utility/rtos_compatibility_layers/posix/px_mq_arrange_msg.c b/utility/rtos_compatibility_layers/posix/px_mq_arrange_msg.c index 02649614..f72d0245 100644 --- a/utility/rtos_compatibility_layers/posix/px_mq_arrange_msg.c +++ b/utility/rtos_compatibility_layers/posix/px_mq_arrange_msg.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -57,15 +58,6 @@ /* */ /* POSIX internal Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* 10-31-2022 Scott Larson Modified comments, */ -/* fixed message swap logic, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ ULONG posix_arrange_msg(TX_QUEUE *Queue, ULONG *pMsgPrio) { @@ -115,7 +107,7 @@ ULONG posix_arrange_msg(TX_QUEUE *Queue, ULONG *pMsgPrio) /* copy FIFO order to the message */ minNo = *q_read; - + /* Found higher priority message. */ maxPrio = priority; @@ -131,10 +123,10 @@ ULONG posix_arrange_msg(TX_QUEUE *Queue, ULONG *pMsgPrio) /* copy number to the local variable. */ number2 = *q_read; - + /* Go to next message. */ q_read++; - + /* find the oldest of the messages in this priority level. */ if( number2 < minNo ) { diff --git a/utility/rtos_compatibility_layers/posix/px_mq_attr_init.c b/utility/rtos_compatibility_layers/posix/px_mq_attr_init.c index e06ec746..e79bd6a2 100644 --- a/utility/rtos_compatibility_layers/posix/px_mq_attr_init.c +++ b/utility/rtos_compatibility_layers/posix/px_mq_attr_init.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -57,12 +58,6 @@ /* */ /* POSIX internal Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ VOID posix_qattr_init(VOID) { @@ -70,7 +65,7 @@ VOID posix_qattr_init(VOID) struct mq_attr * q_attr; q_attr = &(posix_qattr_default); - + /* This queue is not currently in use. */ q_attr->mq_flags = MQ_FLAGS; q_attr->mq_maxmsg = MQ_MAXMSG; diff --git a/utility/rtos_compatibility_layers/posix/px_mq_close.c b/utility/rtos_compatibility_layers/posix/px_mq_close.c index 7bc067f5..69cfc2b9 100644 --- a/utility/rtos_compatibility_layers/posix/px_mq_close.c +++ b/utility/rtos_compatibility_layers/posix/px_mq_close.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -60,24 +61,18 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ INT mq_close(mqd_t mqdes) { TX_INTERRUPT_SAVE_AREA -TX_QUEUE * Queue; +TX_QUEUE * Queue; POSIX_MSG_QUEUE * q_ptr; - /* Assign a temporary variable for clarity. */ - Queue = &(mqdes->f_data->queue); - q_ptr = (POSIX_MSG_QUEUE * )Queue; + /* Assign a temporary variable for clarity. */ + Queue = &(mqdes->f_data->queue); + q_ptr = (POSIX_MSG_QUEUE * )Queue; /* First, check for an invalid queue pointer. */ if ( (!q_ptr) || ( (q_ptr -> px_queue_id) != PX_QUEUE_ID)) @@ -119,7 +114,7 @@ POSIX_MSG_QUEUE * q_ptr; q_ptr ->open_count--; - /* Destroy the basic Queue is the ref count is zero and + /* Destroy the basic Queue is the ref count is zero and it is marked by unlink. */ if( (! q_ptr ->open_count ) && (q_ptr->unlink_flag == TX_TRUE)) { diff --git a/utility/rtos_compatibility_layers/posix/px_mq_create.c b/utility/rtos_compatibility_layers/posix/px_mq_create.c index 4b077bb0..dc9f0fc3 100644 --- a/utility/rtos_compatibility_layers/posix/px_mq_create.c +++ b/utility/rtos_compatibility_layers/posix/px_mq_create.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -68,14 +69,6 @@ /* */ /* POSIX internal Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* 10-31-2022 Scott Larson Add 64-bit support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ POSIX_MSG_QUEUE * posix_mq_create (const CHAR * mq_name, struct mq_attr * msgq_attr) @@ -121,7 +114,7 @@ TX_QUEUE *TheQ; return(TX_NULL); } - /* Now create a ThreadX message queue. + /* Now create a ThreadX message queue. to store only the message pointer and message length. */ temp1 = tx_queue_create((&(posix_q->queue)), (CHAR *)mq_name, @@ -147,11 +140,11 @@ TX_QUEUE *TheQ; /* Restore maximum message length. */ posix_q->q_attr.mq_msgsize = msgq_attr->mq_msgsize; - /* Flags are stored in que descriptor structure and + /* Flags are stored in que descriptor structure and not in mq_att structure. */ - /* Create a byte pool for the queue. - Determine how much memory we need to store all messages in this queue. + /* Create a byte pool for the queue. + Determine how much memory we need to store all messages in this queue. 11 bytes are added to counter overhead as well as alignment problem if any. */ size = ( ((msgq_attr->mq_maxmsg) + 1) * (msgq_attr->mq_msgsize + 11) ); @@ -188,7 +181,7 @@ TX_QUEUE *TheQ; return(TX_NULL); } /* Put the queue back into the POSIX queue pool. */ - posix_putback_queue(TheQ); + posix_putback_queue(TheQ); /* User configuration error - not enough memory. */ posix_errno = EBADF; @@ -211,7 +204,7 @@ TX_QUEUE *TheQ; /* Restore interrupts. */ TX_RESTORE - /* Return ERROR.*/ + /* Return ERROR.*/ return(TX_NULL); } diff --git a/utility/rtos_compatibility_layers/posix/px_mq_find_queue.c b/utility/rtos_compatibility_layers/posix/px_mq_find_queue.c index 3e7c7863..2788cd19 100644 --- a/utility/rtos_compatibility_layers/posix/px_mq_find_queue.c +++ b/utility/rtos_compatibility_layers/posix/px_mq_find_queue.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -56,12 +57,6 @@ /* */ /* POSIX internal Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ POSIX_MSG_QUEUE * posix_find_queue(const CHAR *mq_name) { diff --git a/utility/rtos_compatibility_layers/posix/px_mq_get_new_queue.c b/utility/rtos_compatibility_layers/posix/px_mq_get_new_queue.c index 6157bc6f..c9479806 100644 --- a/utility/rtos_compatibility_layers/posix/px_mq_get_new_queue.c +++ b/utility/rtos_compatibility_layers/posix/px_mq_get_new_queue.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -58,24 +59,18 @@ /* */ /* POSIX internal Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ POSIX_MSG_QUEUE * posix_get_new_queue(ULONG maxnum) { -ULONG i; -POSIX_MSG_QUEUE *q_ptr; -VOID *bp; -INT retval; -ULONG size; +ULONG i; +POSIX_MSG_QUEUE *q_ptr; +VOID *bp; +INT retval; +ULONG size; - /* Determine how much memory we need for the queue. + /* Determine how much memory we need for the queue. The queue holds "maxnum" entries; each entry is 2 ULONG. */ size = (maxnum * (TX_4_ULONG * sizeof(ULONG))); @@ -91,14 +86,14 @@ ULONG size; /* try to find one that is not "in use". */ /* Search the queue pool for an available queue. */ for (i = 0, q_ptr = &(posix_queue_pool[0]); - i < POSIX_MAX_QUEUES; + i < POSIX_MAX_QUEUES; i++, q_ptr++) { /* Make sure the queue is not "in use". */ if (q_ptr->in_use == TX_FALSE) { /* This queue is now in use. */ - q_ptr->in_use = TX_TRUE; + q_ptr->in_use = TX_TRUE; /* Point to allocated memory. */ q_ptr->storage = bp; @@ -106,10 +101,10 @@ ULONG size; q_ptr->px_queue_id = PX_QUEUE_ID; /* Stop searching. */ - break; + break; } } - /* If we didn't find a free queue, free the allocated memory. */ + /* If we didn't find a free queue, free the allocated memory. */ if ( i >= POSIX_MAX_QUEUES) { posix_memory_release(bp); diff --git a/utility/rtos_compatibility_layers/posix/px_mq_get_queue_desc.c b/utility/rtos_compatibility_layers/posix/px_mq_get_queue_desc.c index b26883e2..f311b02f 100644 --- a/utility/rtos_compatibility_layers/posix/px_mq_get_queue_desc.c +++ b/utility/rtos_compatibility_layers/posix/px_mq_get_queue_desc.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -58,12 +59,6 @@ /* */ /* POSIX internal Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ struct mq_des * posix_get_queue_des(POSIX_MSG_QUEUE * q_ptr) { diff --git a/utility/rtos_compatibility_layers/posix/px_mq_open.c b/utility/rtos_compatibility_layers/posix/px_mq_open.c index dbcb0b94..17bb7719 100644 --- a/utility/rtos_compatibility_layers/posix/px_mq_open.c +++ b/utility/rtos_compatibility_layers/posix/px_mq_open.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -63,14 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* 10-31-2022 Scott Larson Update comparison with NULL, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ mqd_t mq_open(const CHAR * mqName, ULONG oflags,...) { @@ -81,7 +74,7 @@ struct mq_attr *q_attr; mode_t mode; va_list create_queue; ULONG len; -ULONG temp1; +ULONG temp1; len = strlen(mqName); if(len > PATH_MAX) @@ -134,16 +127,16 @@ ULONG temp1; return((struct mq_des *)ERROR); } - /* If q_attr is NULL then the default attributes of the struct + /* If q_attr is NULL then the default attributes of the struct mq_attr are used */ if(q_attr == NULL) { q_attr = &(posix_qattr_default); temp1 = q_attr->mq_maxmsg; - temp1= temp1 ; /* Just to keep complier happy */ + temp1= temp1 ; /* Just to keep complier happy */ } - /* Create a queue which returns posix queue if successful and + /* Create a queue which returns posix queue if successful and NULL if fails. */ if(!(posix_queue = posix_mq_create(mqName, q_attr))) { diff --git a/utility/rtos_compatibility_layers/posix/px_mq_priority_search.c b/utility/rtos_compatibility_layers/posix/px_mq_priority_search.c index 137db751..da7c5996 100644 --- a/utility/rtos_compatibility_layers/posix/px_mq_priority_search.c +++ b/utility/rtos_compatibility_layers/posix/px_mq_priority_search.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -58,14 +59,6 @@ /* */ /* POSIX internal Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* 10-31-2022 Scott Larson Add 64-bit support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ ULONG posix_priority_search(mqd_t msgQId, ULONG priority) { diff --git a/utility/rtos_compatibility_layers/posix/px_mq_putback_queue.c b/utility/rtos_compatibility_layers/posix/px_mq_putback_queue.c index dd6ae866..e3d67cad 100644 --- a/utility/rtos_compatibility_layers/posix/px_mq_putback_queue.c +++ b/utility/rtos_compatibility_layers/posix/px_mq_putback_queue.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -56,12 +57,6 @@ /* */ /* POSIX internal Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ VOID posix_putback_queue(TX_QUEUE * qid) { diff --git a/utility/rtos_compatibility_layers/posix/px_mq_queue_delete.c b/utility/rtos_compatibility_layers/posix/px_mq_queue_delete.c index ce677daf..aeb79f98 100644 --- a/utility/rtos_compatibility_layers/posix/px_mq_queue_delete.c +++ b/utility/rtos_compatibility_layers/posix/px_mq_queue_delete.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -59,12 +60,6 @@ /* */ /* POSIX internal Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ INT posix_queue_delete(POSIX_MSG_QUEUE * q_ptr) { diff --git a/utility/rtos_compatibility_layers/posix/px_mq_queue_init.c b/utility/rtos_compatibility_layers/posix/px_mq_queue_init.c index b8ba1935..2db344fc 100644 --- a/utility/rtos_compatibility_layers/posix/px_mq_queue_init.c +++ b/utility/rtos_compatibility_layers/posix/px_mq_queue_init.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -57,12 +58,6 @@ /* */ /* POSIX internal Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ VOID posix_queue_init(VOID) { diff --git a/utility/rtos_compatibility_layers/posix/px_mq_receive.c b/utility/rtos_compatibility_layers/posix/px_mq_receive.c index 8fac9832..bbc799a8 100644 --- a/utility/rtos_compatibility_layers/posix/px_mq_receive.c +++ b/utility/rtos_compatibility_layers/posix/px_mq_receive.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -66,14 +67,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* 10-31-2022 Scott Larson Add 64-bit support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ ssize_t mq_receive( mqd_t mqdes, VOID * pMsg, size_t msgLen, ULONG *pMsgPrio) { @@ -88,9 +81,9 @@ VOID * msgbuf1; UCHAR * msgbuf2; VOID * message_source; - /* Assign a temporary variable for clarity. */ - Queue = &(mqdes->f_data->queue); - q_ptr = (POSIX_MSG_QUEUE * )mqdes->f_data; + /* Assign a temporary variable for clarity. */ + Queue = &(mqdes->f_data->queue); + q_ptr = (POSIX_MSG_QUEUE * )mqdes->f_data; /* First, check for an invalid queue pointer. */ if ((!q_ptr) || ( (q_ptr -> px_queue_id) != PX_QUEUE_ID)) @@ -139,7 +132,7 @@ VOID * message_source; else wait_option = TX_WAIT_FOREVER; - + /* Try to get a message from the message queue. */ /* Create a temporary buffer to get message pointer and message length. */ temp1 = posix_memory_allocate((sizeof(ULONG)) * TX_POSIX_MESSAGE_SIZE, (VOID**)&msgbuf1); @@ -163,12 +156,12 @@ VOID * message_source; /* All ok */ temp1 = OK; - break; + break; } case TX_DELETED: { - break; + break; } case TX_QUEUE_EMPTY: @@ -208,7 +201,7 @@ VOID * message_source; return(temp1); } } - + /* Assign a variable for clarity. */ my_ptr = ( ULONG *)msgbuf1; @@ -221,10 +214,10 @@ VOID * message_source; this_ptr = (CHAR *)(*my_ptr); length_of_message = *(++my_ptr); priority_of_message = *(++my_ptr); - + #endif message_source = (VOID *)this_ptr; - + /* Copy message into supplied buffer. */ msgbuf2 = (UCHAR *)pMsg; @@ -246,7 +239,7 @@ VOID * message_source; { *(msgbuf2++) = *((UCHAR *)(this_ptr++)); } - + temp1 = mycount; } @@ -261,12 +254,12 @@ VOID * message_source; return(ERROR); } - /* Copy message priority */ - if (pMsgPrio) + /* Copy message priority */ + if (pMsgPrio) { *pMsgPrio = priority_of_message; } - + /* All done */ return(length_of_message); } diff --git a/utility/rtos_compatibility_layers/posix/px_mq_reset_queue.c b/utility/rtos_compatibility_layers/posix/px_mq_reset_queue.c index 88aa4beb..4710509d 100644 --- a/utility/rtos_compatibility_layers/posix/px_mq_reset_queue.c +++ b/utility/rtos_compatibility_layers/posix/px_mq_reset_queue.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -57,12 +58,6 @@ /* */ /* POSIX internal code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ VOID posix_reset_queue(POSIX_MSG_QUEUE * q_ptr) { diff --git a/utility/rtos_compatibility_layers/posix/px_mq_send.c b/utility/rtos_compatibility_layers/posix/px_mq_send.c index e67af7d3..464af01f 100644 --- a/utility/rtos_compatibility_layers/posix/px_mq_send.c +++ b/utility/rtos_compatibility_layers/posix/px_mq_send.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -67,22 +68,14 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* 10-31-2022 Scott Larson Add 64-bit support, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ -INT mq_send( mqd_t mqdes, const CHAR * msg_ptr, size_t msg_len, +INT mq_send( mqd_t mqdes, const CHAR * msg_ptr, size_t msg_len, ULONG msg_prio ) { -TX_QUEUE *Queue; -UINT temp1; -POSIX_MSG_QUEUE *q_ptr; +TX_QUEUE *Queue; +UINT temp1; +POSIX_MSG_QUEUE *q_ptr; VOID *bp; UCHAR *source; UCHAR *destination; @@ -90,9 +83,9 @@ UCHAR *save_ptr; ULONG mycount; ULONG msg[TX_POSIX_MESSAGE_SIZE]; - /* Assign a temporary variable for clarity. */ - Queue = &(mqdes->f_data->queue); - q_ptr = (POSIX_MSG_QUEUE * )mqdes->f_data; + /* Assign a temporary variable for clarity. */ + Queue = &(mqdes->f_data->queue); + q_ptr = (POSIX_MSG_QUEUE * )mqdes->f_data; /* First, check for an invalid queue pointer. */ if ( (!q_ptr) || ( (q_ptr -> px_queue_id) != PX_QUEUE_ID)) @@ -104,9 +97,9 @@ ULONG msg[TX_POSIX_MESSAGE_SIZE]; /* Return ERROR. */ return(ERROR); } - /* Make sure if we're calling this routine from a ISR timeout - is set to zero. */ - if (!(tx_thread_identify())) + /* Make sure if we're calling this routine from a ISR timeout + is set to zero. */ + if (!(tx_thread_identify())) { /* POSIX doesn't have error for this, hence give default. */ posix_errno = EINTR ; @@ -166,7 +159,7 @@ ULONG msg[TX_POSIX_MESSAGE_SIZE]; return(ERROR); } - /* Now try to allocate memory to save the message from the + /* Now try to allocate memory to save the message from the queue's byte pool. */ temp1 = tx_byte_allocate((TX_BYTE_POOL * )&(q_ptr->vq_message_area), &bp, msg_len, TX_NO_WAIT); @@ -174,8 +167,8 @@ ULONG msg[TX_POSIX_MESSAGE_SIZE]; if (temp1 != TX_SUCCESS) { posix_internal_error(9999); - } - /* Got the memory , Setup source and destination pointers + } + /* Got the memory , Setup source and destination pointers Cast them in UCHAR as message length is in bytes. */ source = (UCHAR * ) msg_ptr; destination = (UCHAR * ) bp; diff --git a/utility/rtos_compatibility_layers/posix/px_mq_unlink.c b/utility/rtos_compatibility_layers/posix/px_mq_unlink.c index d755d02f..e3e5f683 100644 --- a/utility/rtos_compatibility_layers/posix/px_mq_unlink.c +++ b/utility/rtos_compatibility_layers/posix/px_mq_unlink.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -59,12 +60,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ INT mq_unlink(const CHAR * mqName) { diff --git a/utility/rtos_compatibility_layers/posix/px_mx_attr_destroy.c b/utility/rtos_compatibility_layers/posix/px_mx_attr_destroy.c index 692db80c..3a36b8ed 100644 --- a/utility/rtos_compatibility_layers/posix/px_mx_attr_destroy.c +++ b/utility/rtos_compatibility_layers/posix/px_mx_attr_destroy.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,48 +27,42 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_mutexattr_destroy PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_mutexattr_destroy PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function shall destroy a mutex attributes object; the object */ /* becomes,in effect,uninitialized.A destroyed attr attributes object */ /* can be reinitialized using pthread_mutexattr_init(); */ -/* */ -/* */ -/* INPUT */ +/* */ +/* */ +/* INPUT */ /* */ /* attr Address of the mutex attributes */ -/* object to be destroyed. */ -/* */ -/* OUTPUT */ -/* */ -/* 0 If successful */ +/* object to be destroyed. */ +/* */ +/* OUTPUT */ +/* */ +/* 0 If successful */ /* Value In case of any error or the results */ /* of referencing the object after it */ -/* has been destroyed. */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* has been destroyed. */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_mutexattr_destroy(pthread_mutexattr_t *attr) diff --git a/utility/rtos_compatibility_layers/posix/px_mx_attr_getprotocol.c b/utility/rtos_compatibility_layers/posix/px_mx_attr_getprotocol.c index 50a5572b..6526c155 100644 --- a/utility/rtos_compatibility_layers/posix/px_mx_attr_getprotocol.c +++ b/utility/rtos_compatibility_layers/posix/px_mx_attr_getprotocol.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,46 +27,40 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_mutexattr_getprotocol PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_mutexattr_getprotocol PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function shall gets the mutex protocol attribute. */ /* The protocol of a mutex is contained in the protocol attribute. */ /* attributes. */ /* */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* attr Pointer to the mutex attributes */ /* protocol Pointer to return mutex protocol */ -/* */ -/* OUTPUT */ -/* */ -/* 0 If successful */ -/* Value In case of any error */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* OUTPUT */ +/* */ +/* 0 If successful */ +/* Value In case of any error */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_mutexattr_getprotocol( pthread_mutexattr_t *attr, INT *protocol) diff --git a/utility/rtos_compatibility_layers/posix/px_mx_attr_getpshared.c b/utility/rtos_compatibility_layers/posix/px_mx_attr_getpshared.c index e3ea3df8..8621df8b 100644 --- a/utility/rtos_compatibility_layers/posix/px_mx_attr_getpshared.c +++ b/utility/rtos_compatibility_layers/posix/px_mx_attr_getpshared.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,46 +27,40 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_mutexattr_getpshared PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_mutexattr_getpshared PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function shall gets the mutex protocol attribute. */ /* The protocol of a mutex is contained in the protocol attribute. */ /* attributes. */ /* */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* attr Pointer to the mutex attributes */ /* pshared Pointer to return mutex pshared attr */ -/* */ -/* OUTPUT */ -/* */ -/* 0 If successful */ -/* Value In case of any error */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* OUTPUT */ +/* */ +/* 0 If successful */ +/* Value In case of any error */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_mutexattr_getpshared( pthread_mutexattr_t *attr, INT *pshared) diff --git a/utility/rtos_compatibility_layers/posix/px_mx_attr_gettype.c b/utility/rtos_compatibility_layers/posix/px_mx_attr_gettype.c index 7d391916..2b70d61e 100644 --- a/utility/rtos_compatibility_layers/posix/px_mx_attr_gettype.c +++ b/utility/rtos_compatibility_layers/posix/px_mx_attr_gettype.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,46 +27,40 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_mutexattr_gettype PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_mutexattr_gettype PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function shall gets the mutex type attribute. */ /* The type of mutex is contained in the type attribute of the mutex */ /* attributes. */ /* */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* attr Address of the mutex attributes */ /* type Pointer to return mutex type */ -/* */ -/* OUTPUT */ -/* */ -/* 0 If successful */ -/* Value In case of any error */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* OUTPUT */ +/* */ +/* 0 If successful */ +/* Value In case of any error */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_mutexattr_gettype( pthread_mutexattr_t *attr, INT *type) diff --git a/utility/rtos_compatibility_layers/posix/px_mx_attr_initi.c b/utility/rtos_compatibility_layers/posix/px_mx_attr_initi.c index f9778997..dd41b9a2 100644 --- a/utility/rtos_compatibility_layers/posix/px_mx_attr_initi.c +++ b/utility/rtos_compatibility_layers/posix/px_mx_attr_initi.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,45 +27,39 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_mutexattr_init PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_mutexattr_init PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function initializes a pthread mutex attributes object to */ /* default values, if the object is already created this call will */ /* return an error. */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* attr Pointer to a mutex attributes */ -/* */ -/* OUTPUT */ -/* */ -/* 0 If successful */ -/* Value In case of any error */ -/* */ -/* CALLS */ -/* */ -/* posix_allocate_pthread_mutexattr Get a new mutexattr object */ -/* set_default_mutexattr Set mutexattr with default values */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* OUTPUT */ +/* */ +/* 0 If successful */ +/* Value In case of any error */ +/* */ +/* CALLS */ +/* */ +/* posix_allocate_pthread_mutexattr Get a new mutexattr object */ +/* set_default_mutexattr Set mutexattr with default values */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_mutexattr_init(pthread_mutexattr_t *attr) @@ -73,7 +68,7 @@ INT pthread_mutexattr_init(pthread_mutexattr_t *attr) TX_INTERRUPT_SAVE_AREA - /* Disable interrupts. */ + /* Disable interrupts. */ TX_DISABLE /* Check this attributes object exists ? */ diff --git a/utility/rtos_compatibility_layers/posix/px_mx_attr_setprotocol.c b/utility/rtos_compatibility_layers/posix/px_mx_attr_setprotocol.c index 52fa39ff..5654be6b 100644 --- a/utility/rtos_compatibility_layers/posix/px_mx_attr_setprotocol.c +++ b/utility/rtos_compatibility_layers/posix/px_mx_attr_setprotocol.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,46 +27,40 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_mutexattr_setprotocol PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_mutexattr_setprotocol PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function shall sets the mutex protocol attribute. */ /* The protocol of a mutex is contained in the protocol attribute of */ /* the mutex attributes */ /* */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* attr Pointer to the mutex attributes */ /* protocol mutex protocol */ -/* */ -/* OUTPUT */ -/* */ -/* 0 If successful */ -/* Value In case of any error */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* OUTPUT */ +/* */ +/* 0 If successful */ +/* Value In case of any error */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_mutexattr_setprotocol(pthread_mutexattr_t *attr, INT protocol) @@ -81,8 +76,8 @@ INT pthread_mutexattr_setprotocol(pthread_mutexattr_t *attr, INT protocol) else { if (protocol == PTHREAD_PRIO_INHERIT ) - { - attr->protocol = protocol; + { + attr->protocol = protocol; return(OK); } else diff --git a/utility/rtos_compatibility_layers/posix/px_mx_attr_setpshared.c b/utility/rtos_compatibility_layers/posix/px_mx_attr_setpshared.c index b1790e35..22b3d8c5 100644 --- a/utility/rtos_compatibility_layers/posix/px_mx_attr_setpshared.c +++ b/utility/rtos_compatibility_layers/posix/px_mx_attr_setpshared.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,44 +27,38 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_mutexattr_setpshared PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_mutexattr_setpshared PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function shall sets the mutex pshared attribute. */ /* */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* attr Pointer to the mutex attributes */ /* pshared mutex pshared attr */ -/* */ -/* OUTPUT */ -/* */ -/* 0 If successful */ -/* Value In case of any error */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* OUTPUT */ +/* */ +/* 0 If successful */ +/* Value In case of any error */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_mutexattr_setpshared (pthread_mutexattr_t *attr, INT pshared) @@ -79,8 +74,8 @@ INT pthread_mutexattr_setpshared (pthread_mutexattr_t *attr, INT pshared) else { if ((pshared == PTHREAD_PROCESS_PRIVATE)||(pshared == PTHREAD_PROCESS_SHARED) ) - { - attr->type = pshared; + { + attr->type = pshared; return(OK); } else diff --git a/utility/rtos_compatibility_layers/posix/px_mx_attr_settype.c b/utility/rtos_compatibility_layers/posix/px_mx_attr_settype.c index f5524b17..68184a3c 100644 --- a/utility/rtos_compatibility_layers/posix/px_mx_attr_settype.c +++ b/utility/rtos_compatibility_layers/posix/px_mx_attr_settype.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,46 +27,40 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_mutexattr_settype PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_mutexattr_settype PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function shall sets the mutex type attribute. */ /* The type of mutex is contained in the type attribute of the mutex */ /* attributes. */ /* ***** Only PTHREAD_MUTEX_RECURSIVE type is supported ****** */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* attr Address of the mutex attributes */ /* type mutex type. */ -/* */ -/* OUTPUT */ -/* */ -/* 0 if successful */ -/* Value in case of any error */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* OUTPUT */ +/* */ +/* 0 if successful */ +/* Value in case of any error */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_mutexattr_settype( pthread_mutexattr_t *attr, INT type) @@ -81,8 +76,8 @@ INT pthread_mutexattr_settype( pthread_mutexattr_t *attr, INT type) else { if (type == PTHREAD_MUTEX_RECURSIVE) - { - attr->type = type ; + { + attr->type = type ; return(OK); } else diff --git a/utility/rtos_compatibility_layers/posix/px_mx_destroy.c b/utility/rtos_compatibility_layers/posix/px_mx_destroy.c index 479b160c..804c48d9 100644 --- a/utility/rtos_compatibility_layers/posix/px_mx_destroy.c +++ b/utility/rtos_compatibility_layers/posix/px_mx_destroy.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,46 +27,40 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_mutex_destroy PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_mutex_destroy PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function shall destroy the mutex object referenced by mutex; */ /* the mutex object becomes,in effect, uninitialized.A destroyed mutex */ /* object can be reinitialized using pthread_mutex_init() */ /* It shall be safe to destroy an initialized mutex that is unlocked. */ /* Attempting to destroy a locked mutex results in undefined behavior. */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* mutex Address of the mutex */ -/* */ -/* OUTPUT */ -/* */ -/* 0 If successful */ -/* Value In case of any error */ -/* */ -/* CALLS */ -/* */ -/* tx_mutex_delete ThreadX Mutex service */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* OUTPUT */ +/* */ +/* 0 If successful */ +/* Value In case of any error */ +/* */ +/* CALLS */ +/* */ +/* tx_mutex_delete ThreadX Mutex service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_mutex_destroy(pthread_mutex_t *mutex) @@ -75,7 +70,7 @@ TX_INTERRUPT_SAVE_AREA TX_MUTEX *mutex_ptr; INT status,retval; - + /* Disable interrupts. */ TX_DISABLE @@ -85,7 +80,7 @@ INT status,retval; if (status == TX_SUCCESS) { mutex->in_use = TX_FALSE; - retval = OK; + retval = OK; } else { diff --git a/utility/rtos_compatibility_layers/posix/px_mx_init.c b/utility/rtos_compatibility_layers/posix/px_mx_init.c index 36821392..db4269d7 100644 --- a/utility/rtos_compatibility_layers/posix/px_mx_init.c +++ b/utility/rtos_compatibility_layers/posix/px_mx_init.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,18 +27,18 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_mutex_init PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_mutex_init PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function shall init the mutex object referenced by mutex with */ /* attributes specified by attr. */ /* If attr is NULL, the default mutex attributes are used; the effect */ @@ -45,31 +46,25 @@ /* attributes object. Upon successful initialization,the state of the */ /* mutex becomes initialized and unlocked. */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* mutex Pointer to a pthread mutex object */ /* attr Pointer to mutex attributes */ -/* */ -/* OUTPUT */ -/* */ -/* 0 If successful */ -/* Value In case of any error */ -/* */ -/* CALLS */ -/* */ -/* posix_internal_error In case of some special errors */ -/* posix_in_thread_context Check whether called from a thread */ -/* tx_mutex_create Create a ThreadX Mutex object */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* OUTPUT */ +/* */ +/* 0 If successful */ +/* Value In case of any error */ +/* */ +/* CALLS */ +/* */ +/* posix_internal_error In case of some special errors */ +/* posix_in_thread_context Check whether called from a thread */ +/* tx_mutex_create Create a ThreadX Mutex object */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_mutex_init(pthread_mutex_t *mutex ,pthread_mutexattr_t *attr) @@ -89,7 +84,7 @@ ULONG status,retval; posix_internal_error(444); } - /* Disable interrupts. */ + /* Disable interrupts. */ TX_DISABLE /* Check for any pthread_mutexattr_t suggested */ @@ -102,9 +97,9 @@ ULONG status,retval; { /* attributes passed , check for validity */ if (( (attr->in_use) == TX_FALSE)|| (attr->type!=PTHREAD_MUTEX_RECURSIVE)) - { + { /* attributes passed is not valid, return with an error */ - /* Restore interrupts. */ + /* Restore interrupts. */ TX_RESTORE posix_errno = EINVAL; posix_set_pthread_errno(EINVAL); @@ -114,13 +109,13 @@ ULONG status,retval; mutex_ptr = (&(mutex->mutex_info)) ; - /* Now actually create the mutex */ + /* Now actually create the mutex */ status = tx_mutex_create(mutex_ptr, "PMTX", TX_INHERIT); - + if ( status == TX_SUCCESS) { mutex->in_use = TX_TRUE; - retval = OK; + retval = OK; } else { @@ -129,7 +124,7 @@ ULONG status,retval; posix_set_pthread_errno(EINVAL); retval = EINVAL; } - + TX_RESTORE - return(retval); + return(retval); } diff --git a/utility/rtos_compatibility_layers/posix/px_mx_lock.c b/utility/rtos_compatibility_layers/posix/px_mx_lock.c index 2754b6ac..226f2ea2 100644 --- a/utility/rtos_compatibility_layers/posix/px_mx_lock.c +++ b/utility/rtos_compatibility_layers/posix/px_mx_lock.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,52 +27,46 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_mutex_lock PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_mutex_lock PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function locks the mutex object referenced. If the mutex is */ /* already locked, the calling thread shall block until the mutex */ /* becomes available. This operation shall return with the mutex object*/ /* referenced by mutex in the locked state with the calling thread as */ /* its owner. */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* mutex Address of the mutex */ -/* */ -/* OUTPUT */ -/* */ -/* 0 if successful */ -/* Value in case of any error */ -/* */ -/* CALLS */ -/* */ -/* tx_thread_identify Get calling thread's pointer */ -/* tx_mutex_get ThreadX Mutex Service */ /* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* OUTPUT */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* 0 if successful */ +/* Value in case of any error */ +/* */ +/* CALLS */ +/* */ +/* tx_thread_identify Get calling thread's pointer */ +/* tx_mutex_get ThreadX Mutex Service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_mutex_lock(pthread_mutex_t *mutex ) { - + TX_MUTEX *mutex_ptr; TX_THREAD *thread_ptr; INT retval,status; @@ -91,7 +86,7 @@ INT retval,status; case TX_SUCCESS: retval = OK; break; - + default: posix_errno = EINVAL; posix_set_pthread_errno(EINVAL); diff --git a/utility/rtos_compatibility_layers/posix/px_mx_set_default_mutexattr.c b/utility/rtos_compatibility_layers/posix/px_mx_set_default_mutexattr.c index d3a72e62..87d93ce0 100644 --- a/utility/rtos_compatibility_layers/posix/px_mx_set_default_mutexattr.c +++ b/utility/rtos_compatibility_layers/posix/px_mx_set_default_mutexattr.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -27,41 +28,35 @@ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* set_default_mutexattr PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* set_default_mutexattr PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function sets default mutex attr w/ default information. */ -/* */ -/* INPUT */ -/* */ -/* mutexattr mutex attr object pointer */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Start-up code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* This function sets default mutex attr w/ default information. */ +/* */ +/* INPUT */ +/* */ +/* mutexattr mutex attr object pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Start-up code */ /* */ /**************************************************************************/ VOID set_default_mutexattr(pthread_mutexattr_t *mutexattr) diff --git a/utility/rtos_compatibility_layers/posix/px_mx_timedlock.c b/utility/rtos_compatibility_layers/posix/px_mx_timedlock.c index 9e8b82ef..b08338ce 100644 --- a/utility/rtos_compatibility_layers/posix/px_mx_timedlock.c +++ b/utility/rtos_compatibility_layers/posix/px_mx_timedlock.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,18 +27,18 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_mutex_timedlock PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_mutex_timedlock PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function locks the mutex object referenced. If the mutex is */ /* already locked, the calling thread shall block until the mutex */ /* becomes available as in the pthread_mutex_lock( ) function. If the */ @@ -47,31 +48,25 @@ /* referenced by mutex in the locked state with the calling thread as */ /* its owner. */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* mutex Address of the mutex */ /* timespec Pointer to timespec structure which */ /* holds timeout period in clock ticks */ -/* */ -/* OUTPUT */ -/* */ -/* 0 if successful */ -/* Value in case of any error */ -/* */ -/* CALLS */ -/* */ -/* tx_thread_identify Get calling thread's pointer */ -/* tx_mutex_get ThreadX Mutex Service */ /* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* OUTPUT */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* 0 if successful */ +/* Value in case of any error */ +/* */ +/* CALLS */ +/* */ +/* tx_thread_identify Get calling thread's pointer */ +/* tx_mutex_get ThreadX Mutex Service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_mutex_timedlock(pthread_mutex_t *mutex, struct timespec *abs_timeout) diff --git a/utility/rtos_compatibility_layers/posix/px_mx_trylock.c b/utility/rtos_compatibility_layers/posix/px_mx_trylock.c index 3f10c5a7..b4ec642b 100644 --- a/utility/rtos_compatibility_layers/posix/px_mx_trylock.c +++ b/utility/rtos_compatibility_layers/posix/px_mx_trylock.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,48 +27,42 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_mutex_trylock PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_mutex_trylock PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function shall be equivalent to pthread_mutex_lock(), except */ /* that if the mutex object referenced by mutex is currently locked */ /* (by any thread,including the current thread), the call shall return */ /* immediately. If the mutex type is PTHREAD_MUTEX_RECURSIVE and the */ /* mutex is currently owned by the calling thread,the mutex lock count */ /* shall be incremented by one and the pthread_mutex_trylock()function */ -/* shall immediately return success. */ +/* shall immediately return success. */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* mutex Pointer to the mutex object */ -/* */ -/* OUTPUT */ -/* */ -/* 0 If successful */ -/* Value In case of any error */ -/* */ -/* CALLS */ -/* */ -/* tx_mutex_get ThreadX Mutex get service. */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* OUTPUT */ +/* */ +/* 0 If successful */ +/* Value In case of any error */ +/* */ +/* CALLS */ +/* */ +/* tx_mutex_get ThreadX Mutex get service. */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_mutex_trylock(pthread_mutex_t *mutex) @@ -81,13 +76,13 @@ INT retval,status; /* Try to get the mutex */ status = tx_mutex_get( mutex_ptr, TX_NO_WAIT); - + switch ( status) { case TX_SUCCESS: retval = OK; break; - + case TX_DELETED: posix_errno = EINVAL; posix_set_pthread_errno(EINVAL); diff --git a/utility/rtos_compatibility_layers/posix/px_mx_unlock.c b/utility/rtos_compatibility_layers/posix/px_mx_unlock.c index 0f0b7504..eb5a730f 100644 --- a/utility/rtos_compatibility_layers/posix/px_mx_unlock.c +++ b/utility/rtos_compatibility_layers/posix/px_mx_unlock.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,18 +27,18 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_mutex_unlock PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_mutex_unlock PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function shall release the mutex object referenced by mutex. */ /* The manner in which a mutex is released is dependent upon the mutex */ /* type attribute. If there are threads blocked on the mutex object */ @@ -45,33 +46,27 @@ /* in the mutex becoming available,the scheduling policy shall */ /* determine which thread shall acquire the mutex. */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* mutex Address of the mutex */ -/* */ -/* OUTPUT */ -/* */ -/* 0 if successful */ -/* Value in case of any error */ -/* */ -/* CALLS */ -/* */ -/* tx_mutex_put ThreadX Mutex service */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* OUTPUT */ +/* */ +/* 0 if successful */ +/* Value in case of any error */ +/* */ +/* CALLS */ +/* */ +/* tx_mutex_put ThreadX Mutex service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_mutex_unlock(pthread_mutex_t *mutex ) { - + TX_MUTEX *mutex_ptr; INT retval,status; @@ -84,7 +79,7 @@ INT retval,status; case TX_SUCCESS: retval = OK; break; - + case TX_MUTEX_ERROR: posix_errno = EINVAL; posix_set_pthread_errno(EINVAL); diff --git a/utility/rtos_compatibility_layers/posix/px_nanosleep.c b/utility/rtos_compatibility_layers/posix/px_nanosleep.c index 1460c5cb..6d09e71f 100644 --- a/utility/rtos_compatibility_layers/posix/px_nanosleep.c +++ b/utility/rtos_compatibility_layers/posix/px_nanosleep.c @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -68,14 +69,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* 10-31-2022 Scott Larson Fix bounds check, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ INT nanosleep(struct timespec *req, struct timespec *rem) { @@ -91,7 +84,7 @@ ULONG timer_ticks; return(ERROR); } - /* Add padding of 1 so that the thread will sleep no less than the specified time, + /* Add padding of 1 so that the thread will sleep no less than the specified time, except in the case that timer_ticks is ULONG_MAX */ if(timer_ticks != ULONG_MAX) { @@ -100,7 +93,7 @@ ULONG timer_ticks; /* Now call ThreadX thread sleep service. */ tx_thread_sleep(timer_ticks); - + /* Sleep completed. */ if (rem) { diff --git a/utility/rtos_compatibility_layers/posix/px_pth_attr_destroy.c b/utility/rtos_compatibility_layers/posix/px_pth_attr_destroy.c index b11fc26c..133f64e1 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_attr_destroy.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_attr_destroy.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,49 +27,43 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_attr_destroy PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_attr_destroy PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function destroys a pthread attributes object and allows the */ /* system to reclaim any resources associated with that pthread */ /* attributes object.This doesn't have an effect on any threads created*/ /* using this pthread attributes object. */ -/* */ -/* */ -/* INPUT */ +/* */ +/* */ +/* INPUT */ /* */ /* attr Address of the pthread attributes */ -/* object to be destroyed. */ -/* */ -/* OUTPUT */ -/* */ -/* 0 If successful */ +/* object to be destroyed. */ +/* */ +/* OUTPUT */ +/* */ +/* 0 If successful */ /* Value In case of any error or the results */ /* of referencing the object after it */ -/* has been destroyed. */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* has been destroyed. */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_attr_destroy(pthread_attr_t *attr) diff --git a/utility/rtos_compatibility_layers/posix/px_pth_attr_getdetachstate.c b/utility/rtos_compatibility_layers/posix/px_pth_attr_getdetachstate.c index ed6fa3e6..a52464f4 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_attr_getdetachstate.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_attr_getdetachstate.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,52 +27,46 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_attr_getdetachstate PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_attr_getdetachstate PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function returns the detach state attribute from a pthread */ /* attributes object specified.The detach state of a thread indicates */ /* whether the system is allowed to free thread resources when the */ /* thread terminates. */ /* The detach state specifies one of: */ -/* PTHREAD_CREATE_DETACHED or PTHREAD_CREATE_JOINABLE. */ +/* PTHREAD_CREATE_DETACHED or PTHREAD_CREATE_JOINABLE. */ /* The default detach state (DEFAULT_DETACHSTATE) is: */ /* PTHREAD_CREATE_JOINABLE. */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* attr Address of the thread attributes */ /* detachstate Address of variable to contain the */ -/* returned detach state */ -/* */ -/* */ -/* OUTPUT */ -/* */ -/* 0 if successful */ -/* Value in case of any error */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* returned detach state */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* */ +/* OUTPUT */ +/* */ +/* 0 if successful */ +/* Value in case of any error */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_attr_getdetachstate( pthread_attr_t *attr,INT *detachstate) @@ -83,7 +78,7 @@ INT pthread_attr_getdetachstate( pthread_attr_t *attr,INT *detachstate) posix_errno = EINVAL; posix_set_pthread_errno(EINVAL); return(EINVAL); - } + } else { *detachstate = attr->detach_state ; diff --git a/utility/rtos_compatibility_layers/posix/px_pth_attr_getinheritsched.c b/utility/rtos_compatibility_layers/posix/px_pth_attr_getinheritsched.c index 336e1317..db1b1622 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_attr_getinheritsched.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_attr_getinheritsched.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,18 +27,18 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_attr_getinheritsched PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_attr_getinheritsched PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function returns the inheritsched attribute from the thread */ /* attributes object specified.The inheritsched attribute will be one */ /* of PTHREAD_EXPLICIT_SCHED or PTHREAD_INHERIT_SCHED. */ @@ -47,31 +48,25 @@ /* scheduling attributes when creating new threads. */ /* */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* attr Address of the thread attributes */ /* inheritsched Address of variable to contain the */ -/* returned inheritsched attribute */ -/* */ -/* */ -/* OUTPUT */ -/* */ -/* 0 if successful */ -/* Value in case of any error */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* returned inheritsched attribute */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* */ +/* OUTPUT */ +/* */ +/* 0 if successful */ +/* Value in case of any error */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_attr_getinheritsched(pthread_attr_t *attr, INT *inheritsched) @@ -82,7 +77,7 @@ INT pthread_attr_getinheritsched(pthread_attr_t *attr, INT *inheritsched) posix_errno = EINVAL; posix_set_pthread_errno(EINVAL); return(EINVAL); - } + } else { *inheritsched = attr->inherit_sched ; diff --git a/utility/rtos_compatibility_layers/posix/px_pth_attr_getschedparam.c b/utility/rtos_compatibility_layers/posix/px_pth_attr_getschedparam.c index 6fee2683..722a3178 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_attr_getschedparam.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_attr_getschedparam.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,47 +27,41 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_attr_getschedparam PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_attr_getschedparam PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function returns the scheduling parameters attribute from the */ /* pthread attributes object. */ /* */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* attr Address of the thread attributes */ /* sched_param Address of structure to contain the */ -/* returned scheduling parameters */ -/* */ -/* */ -/* OUTPUT */ -/* */ -/* 0 if successful */ -/* Value in case of any error */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* returned scheduling parameters */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* */ +/* OUTPUT */ +/* */ +/* 0 if successful */ +/* Value in case of any error */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_attr_getschedparam(pthread_attr_t *attr,struct sched_param *param) @@ -77,7 +72,7 @@ INT pthread_attr_getschedparam(pthread_attr_t *attr,struct sched_param *param) posix_errno = EINVAL; posix_set_pthread_errno(EINVAL); return(EINVAL); - } + } else { param->sched_priority = attr->sched_attr.sched_priority; diff --git a/utility/rtos_compatibility_layers/posix/px_pth_attr_getschedpolicy.c b/utility/rtos_compatibility_layers/posix/px_pth_attr_getschedpolicy.c index 1d752762..de0d6610 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_attr_getschedpolicy.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_attr_getschedpolicy.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -25,47 +26,41 @@ #include "pthread.h" /* Posix API */ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_attr_getschedpolicy PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_attr_getschedpolicy PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function returns the scheduling policy from the pthread */ /* attributes object. */ /* */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* attr Address of the thread attributes */ /* policy Address of variable to contain the */ -/* returned scheduling policy */ -/* */ -/* */ -/* OUTPUT */ -/* */ -/* 0 if successful */ -/* Value in case of any error */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* returned scheduling policy */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* */ +/* OUTPUT */ +/* */ +/* 0 if successful */ +/* Value in case of any error */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_attr_getschedpolicy(pthread_attr_t *attr, INT *policy) @@ -76,7 +71,7 @@ INT pthread_attr_getschedpolicy(pthread_attr_t *attr, INT *policy) posix_errno = EINVAL; posix_set_pthread_errno(EINVAL); return(EINVAL); - } + } else { *policy = attr->sched_policy; diff --git a/utility/rtos_compatibility_layers/posix/px_pth_attr_getstack.c b/utility/rtos_compatibility_layers/posix/px_pth_attr_getstack.c index 728c5380..44ac5058 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_attr_getstack.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_attr_getstack.c @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -25,51 +26,45 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_attr_getstack PORTABLE C */ -/* 6.1.7 */ -/* AUTHOR */ -/* */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_attr_getstack PORTABLE C */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ /* William E. Lamie, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ +/* */ +/* DESCRIPTION */ +/* */ /* This function gets the thread creation stack attributes stackaddr */ /* and stacksize in the attr object. */ /* The stack attributes specify the area of storage to be used for the*/ /* created thread's stack. The base (lowest addressable byte) of the */ /* storage shall be stackaddr , and the size of the storage shall be */ -/* stacksize bytes. */ +/* stacksize bytes. */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* attr Address of the thread attributes */ /* stackaddr Pointer to hold Address of stack */ -/* stacksize Holds the stack size */ -/* */ -/* OUTPUT */ -/* */ -/* 0 if successful */ -/* Value in case of any error */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ -/**************************************************************************/ +/* stacksize Holds the stack size */ +/* */ +/* OUTPUT */ +/* */ +/* 0 if successful */ +/* Value in case of any error */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/**************************************************************************/ INT pthread_attr_getstack( pthread_attr_t *attr,void **stackaddr, size_t *stacksize) { @@ -79,7 +74,7 @@ INT pthread_attr_getstack( pthread_attr_t *attr,void **stackaddr, posix_errno = EINVAL; posix_set_pthread_errno(EINVAL); return(EINVAL); - } + } else { *stackaddr = attr->stack_address; diff --git a/utility/rtos_compatibility_layers/posix/px_pth_attr_getstackaddr.c b/utility/rtos_compatibility_layers/posix/px_pth_attr_getstackaddr.c index b8c1345e..56c5769c 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_attr_getstackaddr.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_attr_getstackaddr.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -25,46 +26,40 @@ #include "pthread.h" /* Posix API */ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_attr_getstackaddr PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_attr_getstackaddr PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function returns the stack address associated with a pthread */ -/* attributes */ +/* DESCRIPTION */ /* */ -/* INPUT */ +/* This function returns the stack address associated with a pthread */ +/* attributes */ +/* */ +/* INPUT */ /* */ /* attr Address of the thread attributes */ /* stackaddr Address of variable to contain the */ -/* returned stack address */ -/* */ -/* */ -/* OUTPUT */ -/* */ -/* 0 if successful */ -/* Value in case of any error */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* returned stack address */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* */ +/* OUTPUT */ +/* */ +/* 0 if successful */ +/* Value in case of any error */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_attr_getstackaddr( pthread_attr_t *attr,void **stackaddr) diff --git a/utility/rtos_compatibility_layers/posix/px_pth_attr_getstacksize.c b/utility/rtos_compatibility_layers/posix/px_pth_attr_getstacksize.c index b25633b8..9f650e8a 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_attr_getstacksize.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_attr_getstacksize.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,47 +27,41 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_attr_getstacksize PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_attr_getstacksize PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function returns the stack size associated with a pthread */ /* The stacksize is the minimum stack size (in bytes) allocated for */ /* the created threads stack. */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* attr Address of the thread attributes */ /* stacksize Address of variable to contain the */ -/* returned stack size */ -/* */ -/* */ -/* OUTPUT */ -/* */ -/* 0 if successful */ -/* Value in case of any error */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* returned stack size */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* */ +/* OUTPUT */ +/* */ +/* 0 if successful */ +/* Value in case of any error */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_attr_getstacksize(pthread_attr_t *attr, size_t *stacksize) @@ -78,7 +73,7 @@ INT pthread_attr_getstacksize(pthread_attr_t *attr, size_t *stacksize) posix_errno = EINVAL; posix_set_pthread_errno(EINVAL); return(EINVAL); - } + } else { *stacksize = attr->stack_size; diff --git a/utility/rtos_compatibility_layers/posix/px_pth_attr_init.c b/utility/rtos_compatibility_layers/posix/px_pth_attr_init.c index 8bdb6d16..d2a1113c 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_attr_init.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_attr_init.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,45 +27,39 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_attr_init PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_attr_init PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function initializes a pthread attributes object to default */ /* values,if the object is already created this call will reinitialize */ -/* it else it will create a new attr object and initializes it. */ +/* it else it will create a new attr object and initializes it. */ /* */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* attr Address of the thread attributes */ -/* */ -/* OUTPUT */ -/* */ -/* 0 if successful */ -/* Value in case of any error */ -/* */ -/* CALLS */ -/* */ -/* set_default_pthread_attr to reset with defualt parameters */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* OUTPUT */ +/* */ +/* 0 if successful */ +/* Value in case of any error */ +/* */ +/* CALLS */ +/* */ +/* set_default_pthread_attr to reset with defualt parameters */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_attr_init(pthread_attr_t *attr) @@ -73,7 +68,7 @@ INT pthread_attr_init(pthread_attr_t *attr) TX_INTERRUPT_SAVE_AREA TX_DISABLE - + /* Check this attributes object exists ? */ if (attr->inuse == TX_FALSE) attr->inuse = TX_TRUE; diff --git a/utility/rtos_compatibility_layers/posix/px_pth_attr_setdetachstate.c b/utility/rtos_compatibility_layers/posix/px_pth_attr_setdetachstate.c index 7ebc3bb6..a6c902cb 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_attr_setdetachstate.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_attr_setdetachstate.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,51 +27,45 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_attr_setdetachstate PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_attr_setdetachstate PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function sets the detach state attribute from a pthread */ /* attributes object specified.The detach state of a thread indicates */ /* whether the system is allowed to free thread resources when the */ /* thread terminates. */ /* The detach state specifies one of: */ -/* PTHREAD_CREATE_DETACHED or PTHREAD_CREATE_JOINABLE. */ +/* PTHREAD_CREATE_DETACHED or PTHREAD_CREATE_JOINABLE. */ /* The default detach state (DEFAULT_DETACHSTATE) is: */ /* PTHREAD_CREATE_JOINABLE. */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* attr Address of the thread attributes */ -/* detachstate detach state to set */ -/* */ -/* */ -/* OUTPUT */ -/* */ -/* 0 if successful */ -/* Value in case of any error */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* detachstate detach state to set */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* */ +/* OUTPUT */ +/* */ +/* 0 if successful */ +/* Value in case of any error */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ @@ -82,7 +77,7 @@ INT pthread_attr_setdetachstate(pthread_attr_t *attr,INT detachstate) posix_errno = EINVAL; posix_set_pthread_errno(EINVAL); return(EINVAL); - } + } else { attr->detach_state = detachstate ; diff --git a/utility/rtos_compatibility_layers/posix/px_pth_attr_setinheritsched.c b/utility/rtos_compatibility_layers/posix/px_pth_attr_setinheritsched.c index 7d2f6980..466daf36 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_attr_setinheritsched.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_attr_setinheritsched.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -25,18 +26,18 @@ #include "pthread.h" /* Posix API */ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_attr_setinheritsched PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_attr_setinheritsched PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function sets the inheritsched attribute from the thread */ /* attributes object specified.The inheritsched attribute will be one */ /* of PTHREAD_EXPLICIT_SCHED or PTHREAD_INHERIT_SCHED. */ @@ -46,30 +47,24 @@ /* scheduling attributes when creating new threads. */ /* */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* attr Address of the thread attributes */ /* inheritsched inheritsched attribute to set */ -/* */ -/* */ -/* OUTPUT */ -/* */ -/* 0 if successful */ -/* Value in case of any error */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* */ +/* OUTPUT */ +/* */ +/* 0 if successful */ +/* Value in case of any error */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_attr_setinheritsched(pthread_attr_t *attr, INT inheritsched) @@ -80,7 +75,7 @@ INT pthread_attr_setinheritsched(pthread_attr_t *attr, INT inheritsched) posix_errno = EINVAL; posix_set_pthread_errno(EINVAL); return(EINVAL); - } + } else { attr->inherit_sched = inheritsched ; diff --git a/utility/rtos_compatibility_layers/posix/px_pth_attr_setschedparam.c b/utility/rtos_compatibility_layers/posix/px_pth_attr_setschedparam.c index ecc0e8de..7b2ed9e6 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_attr_setschedparam.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_attr_setschedparam.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,18 +27,18 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_attr_setschedparam PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_attr_setschedparam PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function sets the scheduling parameters attribute for the */ /* pthread attributes object. */ /* */ @@ -46,27 +47,21 @@ /* */ /* attr Address of the thread attributes */ /* sched_param Address of structure containing the */ -/* scheduling parameters to set */ -/* */ -/* */ -/* OUTPUT */ -/* */ -/* 0 if successful */ -/* Value in case of any error */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* scheduling parameters to set */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* */ +/* OUTPUT */ +/* */ +/* 0 if successful */ +/* Value in case of any error */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_attr_setschedparam(pthread_attr_t *attr,struct sched_param *param) @@ -77,7 +72,7 @@ INT pthread_attr_setschedparam(pthread_attr_t *attr,struct sched_param *param) posix_errno = EINVAL; posix_set_pthread_errno(EINVAL); return(EINVAL); - } + } if (param->sched_priority == 0) { posix_errno = EINVAL; @@ -88,7 +83,7 @@ INT pthread_attr_setschedparam(pthread_attr_t *attr,struct sched_param *param) { attr->sched_attr.sched_priority = param->sched_priority; - } + } return(OK); } diff --git a/utility/rtos_compatibility_layers/posix/px_pth_attr_setschedpolicyl.c b/utility/rtos_compatibility_layers/posix/px_pth_attr_setschedpolicyl.c index cde63a7c..01b27ed7 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_attr_setschedpolicyl.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_attr_setschedpolicyl.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -25,47 +26,41 @@ #include "pthread.h" /* Posix API */ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_attr_setschedpolicy PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_attr_setschedpolicy PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function sets the scheduling policy from the pthread */ /* attributes object. */ /* */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* attr Address of the thread attributes */ /* policy variable holding the scheduling */ -/* policy to set */ -/* */ -/* */ -/* OUTPUT */ -/* */ -/* 0 if successful */ -/* Value in case of any error */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* policy to set */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* */ +/* OUTPUT */ +/* */ +/* 0 if successful */ +/* Value in case of any error */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_attr_setschedpolicy(pthread_attr_t *attr, INT policy) @@ -76,7 +71,7 @@ INT pthread_attr_setschedpolicy(pthread_attr_t *attr, INT policy) posix_errno = EINVAL; posix_set_pthread_errno(EINVAL); return(EINVAL); - } + } else { attr->sched_policy = policy; diff --git a/utility/rtos_compatibility_layers/posix/px_pth_attr_setstack.c b/utility/rtos_compatibility_layers/posix/px_pth_attr_setstack.c index 31c92b7f..def00736 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_attr_setstack.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_attr_setstack.c @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -25,51 +26,45 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_attr_setstack PORTABLE C */ -/* 6.1.7 */ -/* AUTHOR */ -/* */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_attr_setstack PORTABLE C */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ /* William E. Lamie, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ +/* */ +/* DESCRIPTION */ +/* */ /* This function sets the thread creation stack attributes stackaddr */ /* and stacksize in the attr object. */ /* The stack attributes specify the area of storage to be used for the*/ /* created thread�s stack. The base (lowest addressable byte) of */ /* the storage shall be stackaddr , and the size of the storage shall */ -/* be stacksize bytes. */ +/* be stacksize bytes. */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* attr Address of the thread attributes */ /* stackaddr Address of stack */ -/* stacksize Holds the stack size */ -/* */ -/* OUTPUT */ -/* */ -/* 0 if successful */ -/* Value in case of any error */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ -/**************************************************************************/ +/* stacksize Holds the stack size */ +/* */ +/* OUTPUT */ +/* */ +/* 0 if successful */ +/* Value in case of any error */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/**************************************************************************/ INT pthread_attr_setstack( pthread_attr_t *attr,void *stackaddr, size_t stacksize) { @@ -85,5 +80,5 @@ INT pthread_attr_setstack( pthread_attr_t *attr,void *stackaddr, attr->stack_address = stackaddr; /* This has got no effect */ attr->stack_size = stacksize; return(OK); - } + } } diff --git a/utility/rtos_compatibility_layers/posix/px_pth_attr_setstackaddr.c b/utility/rtos_compatibility_layers/posix/px_pth_attr_setstackaddr.c index 533bc4a1..9e58e627 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_attr_setstackaddr.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_attr_setstackaddr.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,45 +27,39 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_attr_setstackaddr PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_attr_setstackaddr PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function sets the stack address associated with a pthread */ -/* attributes */ +/* DESCRIPTION */ /* */ -/* INPUT */ +/* This function sets the stack address associated with a pthread */ +/* attributes */ +/* */ +/* INPUT */ /* */ /* attr Address of the thread attributes */ /* stackaddr Address of variable to contain the */ -/* stack address to set */ -/* */ -/* OUTPUT */ -/* */ -/* 0 if successful */ -/* Value in case of any error */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* stack address to set */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* OUTPUT */ +/* */ +/* 0 if successful */ +/* Value in case of any error */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_attr_setstackaddr(pthread_attr_t *attr,void *stackaddr) @@ -76,7 +71,7 @@ INT pthread_attr_setstackaddr(pthread_attr_t *attr,void *stackaddr) posix_errno = EINVAL; posix_set_pthread_errno(EINVAL); return(EINVAL); - } + } else { attr->stack_address = stackaddr; diff --git a/utility/rtos_compatibility_layers/posix/px_pth_attr_setstacksize.c b/utility/rtos_compatibility_layers/posix/px_pth_attr_setstacksize.c index 66eda7a1..e63d19cf 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_attr_setstacksize.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_attr_setstacksize.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,46 +27,40 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_attr_setstacksize PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_attr_setstacksize PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function sets the stack size associated with a pthread attr */ /* The stacksize is the minimum stack size (in bytes) allocated for */ /* the created threads stack. */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* attr Address of the thread attributes */ /* stacksize stack size */ -/* */ -/* */ -/* OUTPUT */ -/* */ -/* 0 if successful */ -/* Value in case of any error */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* */ +/* OUTPUT */ +/* */ +/* 0 if successful */ +/* Value in case of any error */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_attr_setstacksize(pthread_attr_t *attr, size_t stacksize) diff --git a/utility/rtos_compatibility_layers/posix/px_pth_cancel.c b/utility/rtos_compatibility_layers/posix/px_pth_cancel.c index 7e0c7a52..faaed386 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_cancel.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_cancel.c @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ INT pthread_cancel(pthread_t thread) { @@ -74,12 +69,12 @@ INT pthread_cancel(pthread_t thread) TX_THREAD *thread_ptr; POSIX_TCB *pthread_ptr; - - - - /* Get the thread identifier of the pthread to be canceled */ - thread_ptr = posix_tid2thread(thread); - + + + + /* Get the thread identifier of the pthread to be canceled */ + thread_ptr = posix_tid2thread(thread); + if( (thread_ptr->tx_thread_state == TX_COMPLETED) || (thread_ptr->tx_thread_state == TX_TERMINATED) ) { posix_errno = EINVAL; @@ -103,9 +98,9 @@ POSIX_TCB *pthread_ptr; } else if(pthread_ptr->cancel_type==PTHREAD_CANCEL_ASYNCHRONOUS ) { - /* Signal the housekeeping ThreadX thread to cancel (delete) the requested pthread now */ + /* Signal the housekeeping ThreadX thread to cancel (delete) the requested pthread now */ - posix_destroy_pthread(pthread_ptr,(VOID *)0); + posix_destroy_pthread(pthread_ptr,(VOID *)0); } else /* illegal value in pthread_ptr->cancel_type */ { @@ -114,6 +109,6 @@ POSIX_TCB *pthread_ptr; return(EINVAL); } - /* Indicate success. */ - return(OK); + /* Indicate success. */ + return(OK); } diff --git a/utility/rtos_compatibility_layers/posix/px_pth_create.c b/utility/rtos_compatibility_layers/posix/px_pth_create.c index a6322414..4f5f9095 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_create.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_create.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -72,15 +73,15 @@ /* or the system-imposed limit on */ /* the number of pthreads in */ /* a process PTHREAD_THREADS_MAX */ -/* would be exceeded. */ +/* would be exceeded. */ /* [EINVAL] value specified by attr is */ /* invalid. */ /* [EPERM] The caller does not have */ /* appropriate permission to set */ /* the required scheduling */ -/* parameters or scheduling policy*/ -/* */ -/* This call will not return an error code of [EINTR]*/ +/* parameters or scheduling policy*/ +/* */ +/* This call will not return an error code of [EINTR]*/ /* */ /* */ /* CALLS */ @@ -93,29 +94,20 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* 10-31-2022 Scott Larson Add 64-bit support, */ -/* remove double parenthesis, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ INT pthread_create (pthread_t *thread, pthread_attr_t *attr, void *(*start_routine)(void*),void *arg) -{ +{ TX_INTERRUPT_SAVE_AREA TX_THREAD *thread_ptr; -POSIX_TCB *pthread_ptr, *current_thread_ptr; +POSIX_TCB *pthread_ptr, *current_thread_ptr; INT status,retval; - + /* Make sure we're calling this routine from a thread context. */ if (!posix_in_thread_context()) { @@ -123,7 +115,7 @@ INT status,retval; posix_internal_error(444); } - /* Disable interrupts. */ + /* Disable interrupts. */ /* check for any pthread_t attr suggested */ @@ -136,25 +128,25 @@ INT status,retval; { /* Check attributes passed , check for validity */ if ( (attr->inuse) == TX_FALSE) - { + { /* attributes passed are not valid, return with an error */ - posix_errno = EINVAL; + posix_errno = EINVAL; posix_set_pthread_errno(EINVAL); return(EINVAL); } } - /* Get a pthread control block for this new pthread */ + /* Get a pthread control block for this new pthread */ TX_DISABLE - status = posix_allocate_pthread_t(&pthread_ptr); + status = posix_allocate_pthread_t(&pthread_ptr); TX_RESTORE - /* Make sure we got a Thread control block */ + /* Make sure we got a Thread control block */ if ((status == ERROR) || (!pthread_ptr)) { - /* Configuration/resource error. */ - return(EAGAIN); - } + /* Configuration/resource error. */ + return(EAGAIN); + } if(attr->inherit_sched==PTHREAD_INHERIT_SCHED) { @@ -187,17 +179,17 @@ INT status,retval; } /* Now set up pthread initial parameters */ - + pthread_ptr->entry_parameter = arg; pthread_ptr->start_routine = start_routine; /* Newly created pthread not joined by anybody! */ pthread_ptr->is_joined_by = TX_FALSE; pthread_ptr->joined_by_pthreadID =TX_FALSE; - /* Newly created pthread not yet joined to any other pthread */ - pthread_ptr->is_joined_to = TX_FALSE; + /* Newly created pthread not yet joined to any other pthread */ + pthread_ptr->is_joined_to = TX_FALSE; pthread_ptr->joined_to_pthreadID = TX_FALSE; - - + + /* Allow cancel */ pthread_ptr->cancel_state = PTHREAD_CANCEL_ENABLE; pthread_ptr->cancel_type = PTHREAD_CANCEL_DEFERRED; @@ -215,18 +207,18 @@ INT status,retval; /* problem allocating stack space */ if (status == ERROR) { - /* Configuration/resource error. */ - return(EAGAIN); + /* Configuration/resource error. */ + return(EAGAIN); } - + } /* Create an event flags group for sigwait. */ retval = tx_event_flags_create(&(pthread_ptr -> signals.signal_event_flags), "posix sigwait events"); - - /* Get the thread info from the TCB. */ - thread_ptr = posix_tcb2thread(pthread_ptr); - + + /* Get the thread info from the TCB. */ + thread_ptr = posix_tcb2thread(pthread_ptr); + /* Now actually create and start the thread. */ /* convert Posix priorities to Threadx priority */ retval += tx_thread_create(thread_ptr, @@ -238,27 +230,27 @@ INT status,retval; (TX_LOWEST_PRIORITY - pthread_ptr->current_priority + 1), (TX_LOWEST_PRIORITY - pthread_ptr->threshold + 1), pthread_ptr->time_slice, - TX_AUTO_START); - + TX_AUTO_START); + TX_THREAD_EXTENSION_PTR_SET(thread_ptr, pthread_ptr) - - /* See if ThreadX encountered an error */ + + /* See if ThreadX encountered an error */ if (retval) { - /* Internal error */ - posix_error_handler(3333); - retval = EACCES; + /* Internal error */ + posix_error_handler(3333); + retval = EACCES; } else { - /* Everything is fine. */ + /* Everything is fine. */ /* create a pthreadID by type casting POSIX_TCB into pthread_t */ pthread_ptr->pthreadID = (pthread_t )pthread_ptr; *thread = pthread_ptr->pthreadID ; - retval = OK; + retval = OK; } - - /* Everything worked fine if we got here */ - return(retval); + + /* Everything worked fine if we got here */ + return(retval); } diff --git a/utility/rtos_compatibility_layers/posix/px_pth_detach.c b/utility/rtos_compatibility_layers/posix/px_pth_detach.c index 67569584..5f25a98c 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_detach.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_detach.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -48,11 +49,11 @@ /* Eventually, you should call pthread_join() or pthread_detach() for */ /* every thread that is created joinable (with a detachstate of */ /* PTHREAD_CREATE_JOINABLE)so that the system can reclaim all resources*/ -/* associated with the thread. Failure to join to or detach joinable */ +/* associated with the thread. Failure to join to or detach joinable */ /* threads will result in memory and other resource leaks until the */ /* process ends. If thread doesn't represent a valid undetached thread,*/ -/* pthread_detach() will return ESRCH. */ -/* */ +/* pthread_detach() will return ESRCH. */ +/* */ /* */ /* INPUT */ /* */ @@ -71,12 +72,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ INT pthread_detach(pthread_t thread) @@ -100,7 +95,7 @@ POSIX_TCB *pthread_ptr; return (EINVAL); } pthread_ptr->is_detached = TX_TRUE; - + TX_RESTORE return(OK); } diff --git a/utility/rtos_compatibility_layers/posix/px_pth_equal.c b/utility/rtos_compatibility_layers/posix/px_pth_equal.c index 314c3981..26397606 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_equal.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_equal.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -41,7 +42,7 @@ /* */ /* This function compares two pthread handles for equality. */ /* */ -/* */ +/* */ /* */ /* INPUT */ /* */ @@ -53,7 +54,7 @@ /* 0 The pthread handles do not refer to the */ /* same thread */ /* 1 The pthread handles refer to the same */ -/* thread */ +/* thread */ /* */ /* CALLS */ /* */ @@ -62,12 +63,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ INT pthread_equal(pthread_t thread1, pthread_t thread2) { diff --git a/utility/rtos_compatibility_layers/posix/px_pth_exit.c b/utility/rtos_compatibility_layers/posix/px_pth_exit.c index a072777e..d25a8ac0 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_exit.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_exit.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -48,9 +49,9 @@ /* at which time an implicit call to exit() occurs). */ /* The pthread_exit() function provides an interface similar to exit()*/ /* but on a per-thread basis. */ -/* */ -/* pthread_exit() does not return. */ -/* */ +/* */ +/* pthread_exit() does not return. */ +/* */ /* */ /* INPUT */ /* value_ptr exit parameter */ @@ -66,12 +67,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ VOID pthread_exit(void *value_ptr) { @@ -79,15 +74,15 @@ VOID pthread_exit(void *value_ptr) TX_THREAD *thread_ptr; POSIX_TCB *pthread_ptr; - /* Get the thread identifier of the currently running thread */ - thread_ptr = tx_thread_identify(); + /* Get the thread identifier of the currently running thread */ + thread_ptr = tx_thread_identify(); /* get posix TCB for this pthread */ pthread_ptr = (POSIX_TCB *)thread_ptr; - - /* Signal the housekeeping ThreadX thread to delete the requested pthread */ - posix_destroy_pthread(pthread_ptr,value_ptr); - /* Indicate success. */ - return; + /* Signal the housekeeping ThreadX thread to delete the requested pthread */ + posix_destroy_pthread(pthread_ptr,value_ptr); + + /* Indicate success. */ + return; } diff --git a/utility/rtos_compatibility_layers/posix/px_pth_getcanceltype.c b/utility/rtos_compatibility_layers/posix/px_pth_getcanceltype.c index bec5c512..63362e2b 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_getcanceltype.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_getcanceltype.c @@ -1,16 +1,17 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -24,17 +25,17 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_getcanceltype PORTABLE C */ -/* 6.1.7 */ -/* AUTHOR */ -/* */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_getcanceltype PORTABLE C */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ /* William E. Lamie, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ +/* */ +/* DESCRIPTION */ /* */ /* The pthread_fetcancelstate()function shall atomically both get the */ /* calling thread�s cancelability type to the indicated type and */ @@ -42,31 +43,25 @@ /* by oldtype. Legal values for type are PTHREAD_CANCEL_DEFERRED and */ /* PTHREAD_CANCEL_ASYNCHRONOUS. */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* type New cancelability type to be set */ /* oldtype Pointer to old cancelability type */ -/* */ -/* OUTPUT */ -/* */ -/* 0 if successful */ -/* Value in case of any error */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ -/**************************************************************************/ +/* */ +/* OUTPUT */ +/* */ +/* 0 if successful */ +/* Value in case of any error */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/**************************************************************************/ INT pthread_getcanceltype (INT type, INT *oldtype) { TX_INTERRUPT_SAVE_AREA @@ -75,12 +70,12 @@ TX_THREAD *thread_ptr; POSIX_TCB *pthread_ptr; /* First check for validity of the new cancel type to be set */ - if ( ( type == PTHREAD_CANCEL_DEFERRED ) || ( type == PTHREAD_CANCEL_ASYNCHRONOUS ) ) + if ( ( type == PTHREAD_CANCEL_DEFERRED ) || ( type == PTHREAD_CANCEL_ASYNCHRONOUS ) ) { TX_DISABLE - /* Get the thread identifier of the currently running thread */ - thread_ptr = tx_thread_identify(); + /* Get the thread identifier of the currently running thread */ + thread_ptr = tx_thread_identify(); /* get posix TCB for this pthread */ pthread_ptr = (POSIX_TCB *)thread_ptr; *oldtype = pthread_ptr->cancel_type; @@ -96,4 +91,4 @@ POSIX_TCB *pthread_ptr; posix_set_pthread_errno(EINVAL); return(EINVAL); } -} +} diff --git a/utility/rtos_compatibility_layers/posix/px_pth_getschedparam.c b/utility/rtos_compatibility_layers/posix/px_pth_getschedparam.c index b0b0c920..b21345b5 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_getschedparam.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_getschedparam.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,48 +27,42 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_getschedparam PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_getschedparam PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function returns the scheduling parameters attribute from the */ /* pthread TCB. */ /* */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* thread POSIX thread ID */ /* policy Address of the scheduling policy */ /* sched_param Address of structure to contain the */ -/* returned scheduling parameters */ -/* */ -/* */ -/* OUTPUT */ -/* */ -/* 0 if successful */ -/* Value in case of any error */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* returned scheduling parameters */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* */ +/* OUTPUT */ +/* */ +/* 0 if successful */ +/* Value in case of any error */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_getschedparam(pthread_t thread, INT *policy, struct sched_param *param) @@ -81,7 +76,7 @@ INT pthread_getschedparam(pthread_t thread, INT *policy, struct sched_param *par if(thread_tcb==NULL) { return(ESRCH); - } + } else { *policy=thread_tcb->sched_policy; diff --git a/utility/rtos_compatibility_layers/posix/px_pth_init.c b/utility/rtos_compatibility_layers/posix/px_pth_init.c index 2a35474b..5d2f36ad 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_init.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_init.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -43,16 +44,16 @@ /* */ /* DESCRIPTION */ /* */ -/* Verify that the control block belongs to a POSIX thread and not */ -/* a ThreadX thread */ +/* Verify that the control block belongs to a POSIX thread and not */ +/* a ThreadX thread */ /* */ /* INPUT */ /* */ -/* thread_ptr Pointer to a thread control block */ +/* thread_ptr Pointer to a thread control block */ /* */ /* OUTPUT */ /* */ -/* TX_FALSE if not POSIX thread. TX_TRUE if POSIX thread. */ +/* TX_FALSE if not POSIX thread. TX_TRUE if POSIX thread. */ /* */ /* CALLS */ /* */ @@ -62,58 +63,52 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ static INT is_posix_thread(TX_THREAD *thread_ptr) { if (((POSIX_TCB *)thread_ptr < ptcb_pool) || ((POSIX_TCB *)thread_ptr > &ptcb_pool[PTHREAD_THREADS_MAX - 1])) { - return TX_FALSE; + return TX_FALSE; } - return TX_TRUE; + return TX_TRUE; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* posix_pthread_init PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* posix_pthread_init PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function sets up / configures / initializes all the */ -/* pthread Control Blocks that we define at compile-time in order to */ -/* ensure that there is sufficient memory. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* posix_reset_pthread_t Reset a task control block */ -/* */ -/* CALLED BY */ -/* */ -/* Start-up code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up / configures / initializes all the */ +/* pthread Control Blocks that we define at compile-time in order to */ +/* ensure that there is sufficient memory. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* posix_reset_pthread_t Reset a task control block */ +/* */ +/* CALLED BY */ +/* */ +/* Start-up code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ @@ -122,47 +117,47 @@ static INT is_posix_thread(TX_THREAD *thread_ptr) VOID posix_pthread_init(VOID) { -ULONG index; +ULONG index; - /* Loop through array of TCBs and initialize each one. */ + /* Loop through array of TCBs and initialize each one. */ for (index = 0; index < PTHREAD_THREADS_MAX; index++) { - posix_reset_pthread_t(&(ptcb_pool[index])); + posix_reset_pthread_t(&(ptcb_pool[index])); } } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* posix_reset_pthread_t PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* posix_reset_pthread_t PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function resets a pthread w/ default information. */ -/* */ -/* INPUT */ -/* */ -/* ptcb pthread control block pointer */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Start-up code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function resets a pthread w/ default information. */ +/* */ +/* INPUT */ +/* */ +/* ptcb pthread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Start-up code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ @@ -170,44 +165,44 @@ ULONG index; /**************************************************************************/ VOID posix_reset_pthread_t (POSIX_TCB *ptcb) { - /* Indicate this entry is not in use. */ - ptcb->in_use = TX_FALSE; + /* Indicate this entry is not in use. */ + ptcb->in_use = TX_FALSE; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* posix_copy_pthread_attr PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* posix_copy_pthread_attr PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function copies pthread attributes from a pthread_attr object */ -/* to a pthread TCB */ -/* */ -/* INPUT */ -/* */ -/* attr pthread attr object pointer */ -/* pthread_ptr target pthread TCB */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Start-up code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* to a pthread TCB */ +/* */ +/* INPUT */ +/* */ +/* attr pthread attr object pointer */ +/* pthread_ptr target pthread TCB */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Start-up code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ @@ -219,50 +214,50 @@ ULONG index; pthread_ptr->current_priority = attr->sched_attr.sched_priority ; pthread_ptr->detach_state = attr->detach_state ; pthread_ptr->inherit_sched = attr->inherit_sched ; - pthread_ptr->orig_priority = attr->sched_attr.sched_priority ; + pthread_ptr->orig_priority = attr->sched_attr.sched_priority ; pthread_ptr->sched_attr.sched_priority= attr->sched_attr.sched_priority ; pthread_ptr->pthread_flags = attr->pthread_flags ; pthread_ptr->sched_policy = attr->sched_policy; pthread_ptr->stack_size = attr->stack_size ; pthread_ptr->stack_address = attr->stack_address; - + return; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* posix_allocate_pthread_t PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* posix_allocate_pthread_t PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function attempts to allocate memory for a pthread stack and */ -/* a POSIX pthread Control Block (PTCB). */ -/* */ -/* INPUT */ -/* */ -/* stack_size Requested task stack size */ -/* tcb_ptr Pointer to tcb pointer */ -/* */ -/* OUTPUT */ -/* */ -/* Completion Status */ -/* */ -/* CALLS */ -/* */ -/* Nothing */ -/* */ -/* CALLED BY */ -/* */ -/* POSIX internal code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function attempts to allocate memory for a pthread stack and */ +/* a POSIX pthread Control Block (PTCB). */ +/* */ +/* INPUT */ +/* */ +/* stack_size Requested task stack size */ +/* tcb_ptr Pointer to tcb pointer */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* Nothing */ +/* */ +/* CALLED BY */ +/* */ +/* POSIX internal code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ @@ -271,84 +266,84 @@ ULONG index; INT posix_allocate_pthread_t(POSIX_TCB **ptcb_ptr) { -POSIX_TCB *ptcb; -ULONG index; +POSIX_TCB *ptcb; +ULONG index; - /* Assume the worst. */ - *ptcb_ptr = (POSIX_TCB *)0; + /* Assume the worst. */ + *ptcb_ptr = (POSIX_TCB *)0; - /* This next search is optimized for simplicity, not speed. */ - for (index = 0, ptcb = ptcb_pool; - index < PTHREAD_THREADS_MAX; + /* This next search is optimized for simplicity, not speed. */ + for (index = 0, ptcb = ptcb_pool; + index < PTHREAD_THREADS_MAX; index++, ptcb++) { - /* Is this guy in use? If not, we can use it. */ + /* Is this guy in use? If not, we can use it. */ if (ptcb->in_use == TX_FALSE) { - /* This pTCB is now in use. */ - ptcb->in_use = TX_TRUE; + /* This pTCB is now in use. */ + ptcb->in_use = TX_TRUE; - /* Stop searching. */ - break; + /* Stop searching. */ + break; } - } /* for each POSIX Thread Control Block */ + } /* for each POSIX Thread Control Block */ - /* Did we search all pTCBs and come up empty? */ + /* Did we search all pTCBs and come up empty? */ if (index == PTHREAD_THREADS_MAX) { - /* No more pTCBs available - user configuration error. */ - return(ERROR); + /* No more pTCBs available - user configuration error. */ + return(ERROR); } else { /* Make sure the signal handler information is cleared when the new TCB is allocated. */ memset(&(ptcb -> signals), 0, sizeof(signal_info)); - - /* Found one. */ - *ptcb_ptr = ptcb; + + /* Found one. */ + *ptcb_ptr = ptcb; } return(OK); } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* posix_thread_wrapper PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* posix_thread_wrapper PORTABLE C */ /* 6.2.0 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* Every thread that is modeling a ThreadX thread has this routine as */ +/* DESCRIPTION */ +/* */ +/* Every thread that is modeling a ThreadX thread has this routine as */ /* its entry point.This routine simply calls the pthread entry routine */ -/* with its sole argument passed in pthread-create(). */ -/* */ -/* The main purpose of this function is to mimic the pthread interface */ -/* which allows 1 argument to be passed to the entry point of a thread */ -/* */ -/* INPUT */ -/* */ -/* pthread_ptr pthread control block pointer */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* *(pthread_start_routine) Application pthread entry */ -/* */ -/* CALLED BY */ -/* */ -/* POSIX only (internal) */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* with its sole argument passed in pthread-create(). */ +/* */ +/* The main purpose of this function is to mimic the pthread interface */ +/* which allows 1 argument to be passed to the entry point of a thread */ +/* */ +/* INPUT */ +/* */ +/* pthread_ptr pthread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* *(pthread_start_routine) Application pthread entry */ +/* */ +/* CALLED BY */ +/* */ +/* POSIX only (internal) */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ @@ -365,48 +360,48 @@ VOID *value_ptr; /* The input argument is really a pointer to the pthread's control block */ TX_THREAD_EXTENSION_PTR_GET(pthread_ptr, POSIX_TCB, pthr_ptr) - /* Invoke the pthread start routine with appropriate arguments */ + /* Invoke the pthread start routine with appropriate arguments */ value_ptr = (pthread_ptr->start_routine)((VOID *)pthread_ptr->entry_parameter); - - /* In ThreadX, when a thread returns from its entry point, it enters the */ - /* "completed" state, which is basically an infinite suspension. */ + + /* In ThreadX, when a thread returns from its entry point, it enters the */ + /* "completed" state, which is basically an infinite suspension. */ /* now use pthread_exit call to end this pthread */ pthread_exit(value_ptr); } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* posix_thread2tcb PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* posix_thread2tcb PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function converts a ThreadX thread identifier into */ -/* a posix pthread control block (TCB) */ -/* */ -/* INPUT */ -/* */ -/* thread_ptr Thread pointer */ -/* */ -/* OUTPUT */ -/* */ -/* pthread pthread Task control block */ -/* */ -/* CALLS */ -/* */ -/* posix_internal_error Internal error */ -/* */ -/* CALLED BY */ -/* */ -/* posix internal code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function converts a ThreadX thread identifier into */ +/* a posix pthread control block (TCB) */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread pointer */ +/* */ +/* OUTPUT */ +/* */ +/* pthread pthread Task control block */ +/* */ +/* CALLS */ +/* */ +/* posix_internal_error Internal error */ +/* */ +/* CALLED BY */ +/* */ +/* posix internal code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ @@ -415,62 +410,62 @@ VOID *value_ptr; POSIX_TCB *posix_thread2tcb(TX_THREAD *thread_ptr) { -POSIX_TCB *p_tcb; +POSIX_TCB *p_tcb; - /* Make sure we were called from a thread. */ + /* Make sure we were called from a thread. */ if (!thread_ptr) { - /* Not called from a thread - error! */ - posix_internal_error(333); + /* Not called from a thread - error! */ + posix_internal_error(333); } - /* Make sure thread is a POSIX thread else following case is illegal. */ + /* Make sure thread is a POSIX thread else following case is illegal. */ if (!is_posix_thread(thread_ptr)) { - /* Not called from a POSIX thread - error! */ - return NULL; + /* Not called from a POSIX thread - error! */ + return NULL; } /* We can do this because the Thread information is intentionally */ /* located as the first field in the structure. */ - p_tcb = (POSIX_TCB *)thread_ptr; + p_tcb = (POSIX_TCB *)thread_ptr; - /* All done. */ - return(p_tcb); + /* All done. */ + return(p_tcb); } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* posix_tcb2thread PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* posix_tcb2thread PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function converts a POSIX TCB into ThreadX thread */ -/* */ -/* */ -/* INPUT */ -/* */ -/* pthread_ptr pthread TCB */ -/* */ -/* OUTPUT */ -/* */ -/* thread ThreadX thread */ -/* */ -/* CALLS */ -/* */ -/* posix_internal_error Internal error */ -/* */ -/* CALLED BY */ -/* */ -/* posix internal code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function converts a POSIX TCB into ThreadX thread */ +/* */ +/* */ +/* INPUT */ +/* */ +/* pthread_ptr pthread TCB */ +/* */ +/* OUTPUT */ +/* */ +/* thread ThreadX thread */ +/* */ +/* CALLS */ +/* */ +/* posix_internal_error Internal error */ +/* */ +/* CALLED BY */ +/* */ +/* posix internal code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ @@ -479,55 +474,55 @@ POSIX_TCB *p_tcb; TX_THREAD *posix_tcb2thread (POSIX_TCB *pthread_ptr) { -TX_THREAD *thread; +TX_THREAD *thread; - /* Make sure we don't have a NULL pointer. */ + /* Make sure we don't have a NULL pointer. */ if (pthread_ptr) { - /* Simply convert the TCB to a Thread via a cast */ - thread = (&(pthread_ptr->thread_info )); + /* Simply convert the TCB to a Thread via a cast */ + thread = (&(pthread_ptr->thread_info )); } else { - thread = ((TX_THREAD *)0); + thread = ((TX_THREAD *)0); } - return(thread); + return(thread); } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* posix_thread2tid PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* posix_thread2tid PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function converts a ThreadX thread identifier into */ -/* posix thread ID */ -/* */ -/* INPUT */ -/* */ -/* thread_ptr Thread pointer */ -/* */ -/* OUTPUT */ -/* */ -/* thread_ID thread_ID */ -/* */ -/* CALLS */ -/* */ -/* posix_internal_error Internal error */ -/* */ -/* CALLED BY */ -/* */ -/* posix internal code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function converts a ThreadX thread identifier into */ +/* posix thread ID */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread pointer */ +/* */ +/* OUTPUT */ +/* */ +/* thread_ID thread_ID */ +/* */ +/* CALLS */ +/* */ +/* posix_internal_error Internal error */ +/* */ +/* CALLED BY */ +/* */ +/* posix internal code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ @@ -539,54 +534,54 @@ TX_THREAD *thread; pthread_t thread_ID; POSIX_TCB *p_tcb; - /* Make sure we were called from a thread. */ + /* Make sure we were called from a thread. */ if (!thread_ptr) { - /* Not called from a thread - error! */ - posix_internal_error(222); + /* Not called from a thread - error! */ + posix_internal_error(222); } /* Get the TCB for this pthread */ p_tcb = posix_thread2tcb(thread_ptr); - thread_ID = p_tcb->pthreadID; + thread_ID = p_tcb->pthreadID; - /* All done. */ - return(thread_ID); + /* All done. */ + return(thread_ID); } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* posix_tid2thread PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* posix_tid2thread PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function converts a posix thread ID into a thread. */ -/* */ -/* INPUT */ -/* */ -/* tid Thread ID */ -/* */ -/* OUTPUT */ -/* */ -/* thread_ptr Thread pointer */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* posix internal code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function converts a posix thread ID into a thread. */ +/* */ +/* INPUT */ +/* */ +/* tid Thread ID */ +/* */ +/* OUTPUT */ +/* */ +/* thread_ptr Thread pointer */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* posix internal code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ @@ -595,56 +590,56 @@ POSIX_TCB *p_tcb; TX_THREAD *posix_tid2thread(pthread_t ptid) { -TX_THREAD *thread; +TX_THREAD *thread; POSIX_TCB *pthread; - /* Make sure we don't have a NULL TID. */ + /* Make sure we don't have a NULL TID. */ if (ptid) { - /* convert the pthread ID to a pThread TCB */ + /* convert the pthread ID to a pThread TCB */ pthread = posix_tid2tcb(ptid); - /* convert the pthread TCB to a pThread TCB */ + /* convert the pthread TCB to a pThread TCB */ thread= posix_tcb2thread(pthread); } else { - thread = ((TX_THREAD *)0); + thread = ((TX_THREAD *)0); } - return(thread); + return(thread); } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* posix_tid2tcb PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* posix_tid2tcb PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function converts a posix thread ID into a posix pthread TCB */ -/* */ -/* INPUT */ -/* */ -/* tid Thread ID */ -/* */ -/* OUTPUT */ -/* */ -/* pthread_ptr pthread pointer */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* posix internal code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function converts a posix thread ID into a posix pthread TCB */ +/* */ +/* INPUT */ +/* */ +/* tid Thread ID */ +/* */ +/* OUTPUT */ +/* */ +/* pthread_ptr pthread pointer */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* posix internal code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ @@ -655,52 +650,52 @@ POSIX_TCB *pthread; POSIX_TCB *pthread; - /* Make sure we don't have a NULL TID. */ + /* Make sure we don't have a NULL TID. */ if (ptid) - /* Simply convert the thread ID to a pthread TCB via a cast */ - pthread = (POSIX_TCB *)ptid; + /* Simply convert the thread ID to a pthread TCB via a cast */ + pthread = (POSIX_TCB *)ptid; else pthread = ((POSIX_TCB *)0); - - return(pthread); + + return(pthread); } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* posix_destroy_pthread PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* posix_destroy_pthread PORTABLE C */ /* 6.2.0 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function performs internal cleanup and housekeeping */ -/* when a pthread exits. */ -/* */ -/* INPUT */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function performs internal cleanup and housekeeping */ +/* when a pthread exits. */ +/* */ +/* INPUT */ +/* */ /* pthread_ptr pointer to TCB of the pthread */ -/* to be deleted */ -/* */ -/* OUTPUT */ -/* */ +/* to be deleted */ +/* */ +/* OUTPUT */ +/* */ /* OK If successful */ -/* ERROR If fails */ -/* */ -/* CALLS */ -/* */ -/* tx_queue_send Send to system mgr queue */ -/* posix_internal_error Internal error handling */ -/* */ -/* CALLED BY */ -/* */ -/* posix internal code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* ERROR If fails */ +/* */ +/* CALLS */ +/* */ +/* tx_queue_send Send to system mgr queue */ +/* posix_internal_error Internal error handling */ +/* */ +/* CALLED BY */ +/* */ +/* posix internal code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ @@ -714,7 +709,7 @@ POSIX_TCB *pthread; ULONG request[WORK_REQ_SIZE]; UINT status; - /* Build the request. */ + /* Build the request. */ #ifdef TX_64_BIT request[0] = (ULONG)((ALIGN_TYPE)pthread_ptr >> 32); @@ -727,59 +722,59 @@ UINT status; #endif /* Send a message to the SysMgr supervisor thread, asking it to delete */ - /* the pthread. Since the SysMgr supervisor thread is the highest */ - /* possible priority, this routine will be preempted when we */ - /* post the message to the SysMgr's work queue. */ - - status = tx_queue_send(&posix_work_queue, request, TX_NO_WAIT); - /* This should always succeed. */ + /* the pthread. Since the SysMgr supervisor thread is the highest */ + /* possible priority, this routine will be preempted when we */ + /* post the message to the SysMgr's work queue. */ + + status = tx_queue_send(&posix_work_queue, request, TX_NO_WAIT); + /* This should always succeed. */ if (status != TX_SUCCESS) { - posix_internal_error(1001); + posix_internal_error(1001); } - + /* Return the pthread's TCB to the pool of available TCB's. */ posix_reset_pthread_t(pthread_ptr); } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* posix_do_pthread_delete PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* posix_do_pthread_delete PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function deletes the pthread and reclaims the stack memory. */ -/* Also it resumes any pthread joined to this exiting pthread. */ -/* */ -/* INPUT */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function deletes the pthread and reclaims the stack memory. */ +/* Also it resumes any pthread joined to this exiting pthread. */ +/* */ +/* INPUT */ +/* */ /* pthread_ptr pointer to TCB of the pthread */ -/* to be deleted */ -/* */ -/* OUTPUT */ -/* */ +/* to be deleted */ +/* */ +/* OUTPUT */ +/* */ /* OK If successful */ -/* ERROR If fails */ -/* */ -/* CALLS */ -/* */ -/* tx_thread_terminate Terminate ThreadX thread */ -/* tx_thread_delete Delete the ThreadX thread */ -/* posix_memory_release Release the task's stack */ -/* posix_free_tcb Free pthread control block */ -/* */ -/* CALLED BY */ -/* */ -/* posix internal code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* ERROR If fails */ +/* */ +/* CALLS */ +/* */ +/* tx_thread_terminate Terminate ThreadX thread */ +/* tx_thread_delete Delete the ThreadX thread */ +/* posix_memory_release Release the task's stack */ +/* posix_free_tcb Free pthread control block */ +/* */ +/* CALLED BY */ +/* */ +/* posix internal code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ @@ -792,45 +787,45 @@ TX_INTERRUPT_SAVE_AREA POSIX_TCB *joined_pthread_ptr; TX_THREAD *thread_ptr,*thread1_ptr; -pthread_t joined_pthread_ID; -ULONG status; +pthread_t joined_pthread_ID; +ULONG status; TX_DISABLE /* preserve the thread's return value regardless */ pthread_ptr->value_ptr = value_ptr; - + if ( pthread_ptr->is_joined_by == TX_TRUE) { joined_pthread_ID = pthread_ptr->joined_by_pthreadID ; joined_pthread_ptr = posix_tid2tcb(joined_pthread_ID); - + joined_pthread_ptr->is_joined_to = TX_FALSE; joined_pthread_ptr->joined_to_pthreadID =TX_FALSE; - + thread_ptr = (TX_THREAD *)joined_pthread_ptr; - + /* Now resume the suspended pthread joined to this pthread */ tx_thread_resume(thread_ptr); - } + } /* Terminate the pthread's ThreadX thread. */ thread1_ptr = posix_tcb2thread(pthread_ptr); - status = tx_thread_terminate(thread1_ptr); + status = tx_thread_terminate(thread1_ptr); if (status != TX_SUCCESS) { - posix_internal_error(2244); + posix_internal_error(2244); } - - /* Delete the pthread's ThreadX thread. */ - status = tx_thread_delete(&(pthread_ptr->thread_info)); + + /* Delete the pthread's ThreadX thread. */ + status = tx_thread_delete(&(pthread_ptr->thread_info)); if (status != TX_SUCCESS) { - posix_internal_error(2255); + posix_internal_error(2255); } /* Free the memory allocated for pthread's stack allocated from the posix heap */ /* if the memory was not from the posix heap this call has no effect */ /* it will be the user's responsibility to manage such memory */ - - posix_memory_release(pthread_ptr->stack_address); + + posix_memory_release(pthread_ptr->stack_address); /* Determine if this thread is NOT a signal handler thread. If this is the case, delete the event flag group. */ @@ -841,62 +836,62 @@ ULONG status; tx_event_flags_delete(&(pthread_ptr -> signals.signal_event_flags)); } - /* Return the pthread's TCB to the pool of available TCB's. */ - pthread_ptr->in_use = TX_FALSE; + /* Return the pthread's TCB to the pool of available TCB's. */ + pthread_ptr->in_use = TX_FALSE; TX_RESTORE - - /* All done. */ - return; + + /* All done. */ + return; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* posix_set_pthread_errno PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* posix_set_pthread_errno PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function sets the pthread error number. */ -/* Each pthread has got its very own erron number. */ -/* */ -/* INPUT */ -/* */ -/* errno_set error number to set */ -/* */ -/* */ -/* OUTPUT */ -/* */ -/* OK Always return successful */ -/* */ -/* CALLS */ -/* */ -/* tx_thread_identify get calling ThreadX thread */ +/* DESCRIPTION */ +/* */ +/* This function sets the pthread error number. */ +/* Each pthread has got its very own erron number. */ +/* */ +/* INPUT */ +/* */ +/* errno_set error number to set */ +/* */ +/* */ +/* OUTPUT */ +/* */ +/* OK Always return successful */ +/* */ +/* CALLS */ +/* */ +/* tx_thread_identify get calling ThreadX thread */ +/* */ +/* CALLED BY */ +/* */ +/* posix internal code */ +/* */ +/* RELEASE HISTORY */ /* */ -/* CALLED BY */ -/* */ -/* posix internal code */ -/* */ -/* RELEASE HISTORY */ -/* */ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ /* */ /**************************************************************************/ INT posix_set_pthread_errno(ULONG errno_set) -{ +{ TX_THREAD *thread_ptr; POSIX_TCB *pthread_ptr; - /* Get the thread identifier of the currently running thread */ - thread_ptr = tx_thread_identify(); + /* Get the thread identifier of the currently running thread */ + thread_ptr = tx_thread_identify(); /* get posix TCB for this pthread */ pthread_ptr = (POSIX_TCB *)thread_ptr; /* Set the error number */ @@ -904,43 +899,43 @@ POSIX_TCB *pthread_ptr; /* Always return success!*/ return(OK); -} +} -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* posix_get_pthread_errno PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* posix_get_pthread_errno PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function gets the erron number for a pthread. */ -/* Each pthread has got its very own erron number. */ -/* */ -/* INPUT */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the erron number for a pthread. */ +/* Each pthread has got its very own erron number. */ +/* */ +/* INPUT */ +/* */ /* ptid pthread id */ -/* */ -/* */ -/* OUTPUT */ -/* */ +/* */ +/* */ +/* OUTPUT */ +/* */ /* error_number error number for the pthread */ /* ERROR In case of any error */ -/* */ -/* CALLS */ -/* */ -/* tx_thread_identify get calling ThreadX thread */ /* */ -/* CALLED BY */ -/* */ -/* posix internal code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* CALLS */ +/* */ +/* tx_thread_identify get calling ThreadX thread */ +/* */ +/* CALLED BY */ +/* */ +/* posix internal code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ /* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ @@ -964,7 +959,7 @@ POSIX_TCB *pthread_ptr; error_number = pthread_ptr->perrno; else error_number = ERROR; - + TX_RESTORE return(error_number); } diff --git a/utility/rtos_compatibility_layers/posix/px_pth_join.c b/utility/rtos_compatibility_layers/posix/px_pth_join.c index 10a9302e..461ab617 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_join.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_join.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -51,12 +52,12 @@ /* Eventually, you should call pthread_join() or pthread_detach() for */ /* every thread that is created joinable (with a detachstate of */ /* PTHREAD_CREATE_JOINABLE)so that the system can reclaim all resources*/ -/* associated with the thread. Failure to join to or detach joinable */ +/* associated with the thread. Failure to join to or detach joinable */ /* threads will result in memory and other resource leaks until the */ /* process ends. If thread doesn't represent a valid undetached thread,*/ -/* pthread_detach() will return ESRCH. */ -/* */ -/* Note: this function must be called from a POSIX context; if it is */ +/* pthread_detach() will return ESRCH. */ +/* */ +/* Note: this function must be called from a POSIX context; if it is */ /* called from ThreadX context an error is returned. */ /* */ /* INPUT */ @@ -77,12 +78,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ INT pthread_join(pthread_t thread, VOID **value_ptr) @@ -93,9 +88,9 @@ INT pthread_join(pthread_t thread, VOID **value_ptr) TX_THREAD *target_thread; - /* Get the TCB for the currently running pthread */ + /* Get the TCB for the currently running pthread */ current_ptr = posix_thread2tcb(tx_thread_identify()); - + /* Make sure that a TCB was returned. */ if (!current_ptr) { @@ -136,7 +131,7 @@ INT pthread_join(pthread_t thread, VOID **value_ptr) /* but target pthread is already terminated */ /* return the return value of the terminated thread */ target_ptr = posix_tid2tcb(thread); - if(value_ptr)*value_ptr = target_ptr->value_ptr; + if(value_ptr)*value_ptr = target_ptr->value_ptr; return(OK); } @@ -176,9 +171,9 @@ INT pthread_join(pthread_t thread, VOID **value_ptr) TX_RESTORE /* Now calling pthread will suspend itself and wait till target pthread exits */ - tx_thread_suspend ( &(current_ptr->thread_info)); + tx_thread_suspend ( &(current_ptr->thread_info)); /* target pthread exited and thus current pthread will resume now */ /* store return value if value_ptr is valid */ - if(value_ptr)*value_ptr = target_ptr->value_ptr; + if(value_ptr)*value_ptr = target_ptr->value_ptr; return(OK); } diff --git a/utility/rtos_compatibility_layers/posix/px_pth_kill.c b/utility/rtos_compatibility_layers/posix/px_pth_kill.c index b112a4b2..30bf54d6 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_kill.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_kill.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -68,15 +69,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* 10-31-2022 Scott Larson Remove double parenthesis, */ -/* update argument type, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ int pthread_kill(ALIGN_TYPE thread_id, int sig) { @@ -101,7 +93,7 @@ UINT retval; /* Determine if the desired signal is valid. */ if ((sig < 0) || (sig > SIGRTMAX)) { - + /* Return an error. */ posix_set_pthread_errno(EINVAL); return(ERROR); @@ -126,9 +118,9 @@ UINT retval; /* See if there is a signal handler setup for this signal. */ if (!handler) { - + /* No handler, just set/clear the event flags to handle the sigwait condition. */ - + /* Set the event flag corresponding the signal. */ tx_event_flags_set(&(target_thread -> signals.signal_event_flags), (((ULONG) 1) << sig), TX_OR); @@ -142,7 +134,7 @@ UINT retval; /* Now, let's look to see if the same signal is already pending. */ if (target_thread -> signals.signal_pending.signal_set & (((unsigned long) 1) << sig)) { - + /* Yes, the same signal is already pending, just return. */ return(OK); } @@ -150,17 +142,17 @@ UINT retval; /* Now determine if the thread's signals are masked by pthread_sigmask. */ if (target_thread -> signals.signal_mask.signal_set & (((unsigned long) 1) << sig)) { - - /* Yes, simply set the pending bit so we know that the signal must be activated later when the + + /* Yes, simply set the pending bit so we know that the signal must be activated later when the signal mask for this signal is cleared. */ target_thread -> signals.signal_pending.signal_set = target_thread -> signals.signal_pending.signal_set | (((unsigned long) 1) << sig); return(OK); } /* At this point we know that we need to create a new signal handler thread for processing this signal. */ - - /* Get a pthread control block for this new signal pthread */ - + + /* Get a pthread control block for this new signal pthread */ + /* Disable interrupts for protection. */ TX_DISABLE @@ -168,12 +160,12 @@ UINT retval; _tx_thread_preempt_disable++; /* Allocate a POSIX thread control block. */ - status = posix_allocate_pthread_t(&new_signal_thread); + status = posix_allocate_pthread_t(&new_signal_thread); /* Restore interrupts. */ TX_RESTORE - - /* Make sure we got a new thread control block */ + + /* Make sure we got a new thread control block */ if ((status == ERROR) || (!new_signal_thread)) { @@ -186,10 +178,10 @@ UINT retval; /* Restore interrupts. */ TX_RESTORE - /* Configuration/resource error. */ + /* Configuration/resource error. */ posix_set_pthread_errno(EAGAIN); - return(ERROR); - } + return(ERROR); + } /* Inherit the stack size for the new signal thread. */ new_signal_thread -> stack_size = target_thread -> stack_size ; @@ -200,10 +192,10 @@ UINT retval; /* problem allocating stack space */ if (status == ERROR) { - + /* Mark the previously allocated control block as available. */ new_signal_thread -> in_use = FALSE; - + /* Disable interrupts. */ TX_DISABLE @@ -213,11 +205,11 @@ UINT retval; /* Restore interrupts. */ TX_RESTORE - /* Configuration/resource error. */ + /* Configuration/resource error. */ posix_set_pthread_errno(EAGAIN); - return(ERROR); - } - + return(ERROR); + } + /* Inherit scheduling attributes from base thread. */ new_signal_thread -> current_priority = target_thread -> current_priority ; new_signal_thread -> detach_state = target_thread -> detach_state ; @@ -228,7 +220,7 @@ UINT retval; new_signal_thread -> sched_policy = target_thread -> sched_policy; new_signal_thread -> is_joined_by = TX_FALSE; new_signal_thread -> joined_by_pthreadID = TX_FALSE; - new_signal_thread -> is_joined_to = TX_FALSE; + new_signal_thread -> is_joined_to = TX_FALSE; new_signal_thread -> joined_to_pthreadID = TX_FALSE; new_signal_thread -> cancel_state = PTHREAD_CANCEL_ENABLE; new_signal_thread -> cancel_type = PTHREAD_CANCEL_DEFERRED; @@ -244,7 +236,7 @@ UINT retval; /* Mark the new thread as a signal thread, clear signal info, and setup links. */ new_signal_thread -> signals.signal_handler = TRUE; new_signal_thread -> signals.signal_nesting_depth = target_thread -> signals.signal_nesting_depth; - new_signal_thread -> signals.signal_pending.signal_set = target_thread -> signals.signal_pending.signal_set; + new_signal_thread -> signals.signal_pending.signal_set = target_thread -> signals.signal_pending.signal_set; new_signal_thread -> signals.saved_thread_state = ((TX_THREAD *) target_thread) -> tx_thread_state; new_signal_thread -> signals.base_thread_ptr = target_thread; new_signal_thread -> signals.next_signal_thread = target_thread -> signals.top_signal_thread; @@ -262,9 +254,9 @@ UINT retval; (TX_LOWEST_PRIORITY - new_signal_thread -> current_priority + 1), (TX_LOWEST_PRIORITY - new_signal_thread -> current_priority + 1), new_signal_thread -> time_slice, - TX_AUTO_START); + TX_AUTO_START); - /* See if ThreadX encountered an error */ + /* See if ThreadX encountered an error */ if (retval) { @@ -273,10 +265,10 @@ UINT retval; /* Release the stack memory. */ posix_memory_release(new_signal_thread -> stack_address); - + /* Mark the previously allocated control block as available. */ new_signal_thread -> in_use = FALSE; - + /* Disable interrupts. */ TX_DISABLE @@ -286,10 +278,10 @@ UINT retval; /* Restore interrupts. */ TX_RESTORE - /* Internal error */ - posix_error_handler(3333); + /* Internal error */ + posix_error_handler(3333); posix_set_pthread_errno(EACCES); - return(ERROR); + return(ERROR); } /* Disable interrupts. */ @@ -304,13 +296,13 @@ UINT retval; /* Restore interrupts. */ TX_RESTORE - + /* Suspend the base thread so that it doesn't run again until all the signals have been processed. */ tx_thread_suspend((TX_THREAD *) target_thread); } else if (new_signal_thread -> signals.next_signal_thread) { - + /* Restore interrupts. */ TX_RESTORE @@ -322,7 +314,7 @@ UINT retval; /* Check for a preemption condition. */ _tx_thread_system_preempt_check(); - + /* Return success! */ return(OK); } diff --git a/utility/rtos_compatibility_layers/posix/px_pth_once.c b/utility/rtos_compatibility_layers/posix/px_pth_once.c index 8b140971..6c6288ba 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_once.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_once.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -65,12 +66,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ INT pthread_once (pthread_once_t * once_control, VOID (*init_routine) (VOID)) { @@ -84,7 +79,7 @@ INT pthread_once (pthread_once_t * once_control, VOID (*init_routine) (VOID)) } else { - if ( once_control->state==PTH_ONCE_DONE) + if ( once_control->state==PTH_ONCE_DONE) { result = 0; } @@ -106,7 +101,7 @@ INT pthread_once (pthread_once_t * once_control, VOID (*init_routine) (VOID)) once_control->state=PTH_ONCE_DONE; } - /* enable preemption */ + /* enable preemption */ tx_thread_preemption_change( tx_thread_identify(),old_treshold, &temp); if (once_control->state==PTH_ONCE_STARTED) diff --git a/utility/rtos_compatibility_layers/posix/px_pth_self.c b/utility/rtos_compatibility_layers/posix/px_pth_self.c index d4499afb..fd876459 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_self.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_self.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -41,8 +42,8 @@ /* */ /* This function returns thread ID of the calling pthread . */ /* */ -/* */ -/* */ +/* */ +/* */ /* */ /* INPUT */ /* */ @@ -59,35 +60,29 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ pthread_t pthread_self(VOID) { TX_THREAD *thread_ptr; -pthread_t thread_ID; +pthread_t thread_ID; - /* Get the thread identifier of the currently running thread */ - thread_ptr = tx_thread_identify(); + /* Get the thread identifier of the currently running thread */ + thread_ptr = tx_thread_identify(); - /* Convert thread identifier to posix thread ID */ - - thread_ID = posix_thread2tid(thread_ptr); + /* Convert thread identifier to posix thread ID */ + + thread_ID = posix_thread2tid(thread_ptr); /* Determine if this thread is actually the signal thread helper. */ if (((POSIX_TCB *) thread_ptr) -> signals.signal_handler) { - + /* Yes, override the thread_ID with the non-signal thread ID. */ thread_ID = (pthread_t) ((POSIX_TCB *) thread_ptr) -> signals.base_thread_ptr; } - /* All done. */ - return(thread_ID); + /* All done. */ + return(thread_ID); } diff --git a/utility/rtos_compatibility_layers/posix/px_pth_set_default_pthread_attr.c b/utility/rtos_compatibility_layers/posix/px_pth_set_default_pthread_attr.c index ad8d306e..b1964206 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_set_default_pthread_attr.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_set_default_pthread_attr.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -25,41 +26,35 @@ #include "pthread.h" /* Posix API */ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* set_default_pthread_attr PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* set_default_pthread_attr PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function sets default pthread attr w/ default information. */ -/* */ -/* INPUT */ -/* */ -/* attr pthread attr object pointer */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Start-up code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* DESCRIPTION */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* This function sets default pthread attr w/ default information. */ +/* */ +/* INPUT */ +/* */ +/* attr pthread attr object pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Start-up code */ /* */ /**************************************************************************/ VOID set_default_pthread_attr(pthread_attr_t *attr) diff --git a/utility/rtos_compatibility_layers/posix/px_pth_setcancelstate.c b/utility/rtos_compatibility_layers/posix/px_pth_setcancelstate.c index 824c0888..55d2a008 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_setcancelstate.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_setcancelstate.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,16 +27,16 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_setcancelstate PORTABLE C */ -/* 6.1.7 */ -/* AUTHOR */ -/* */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_setcancelstate PORTABLE C */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ /* William E. Lamie, Microsoft Corporation */ -/* */ +/* */ /* DESCRIPTION */ /* */ /* The pthread_setcancelstate()function shall atomically both set the */ @@ -44,31 +45,25 @@ /* by oldstate.Legal values for state are PTHREAD_CANCEL_ENABLE and */ /* PTHREAD_CANCEL_DISABLE. */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* state New cancelability state to be set */ /* oldstate Pointer to old cancelability state */ -/* */ -/* OUTPUT */ /* */ -/* 0 if successful */ -/* Value in case of any error */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ -/**************************************************************************/ +/* OUTPUT */ +/* */ +/* 0 if successful */ +/* Value in case of any error */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/**************************************************************************/ INT pthread_setcancelstate (INT state, INT *oldstate) { @@ -78,12 +73,12 @@ TX_THREAD *thread_ptr; POSIX_TCB *pthread_ptr; /* First check for validity of the new cancel state to be set */ - if ( (state == PTHREAD_CANCEL_ENABLE) || (state == PTHREAD_CANCEL_DISABLE) ) + if ( (state == PTHREAD_CANCEL_ENABLE) || (state == PTHREAD_CANCEL_DISABLE) ) { TX_DISABLE - /* Get the thread identifier of the currently running thread */ - thread_ptr = tx_thread_identify(); + /* Get the thread identifier of the currently running thread */ + thread_ptr = tx_thread_identify(); /* get posix TCB for this pthread */ pthread_ptr = (POSIX_TCB *)thread_ptr; *oldstate = pthread_ptr->cancel_state; @@ -99,4 +94,4 @@ POSIX_TCB *pthread_ptr; posix_set_pthread_errno(EINVAL); return (EINVAL); } -} +} diff --git a/utility/rtos_compatibility_layers/posix/px_pth_setcanceltype.c b/utility/rtos_compatibility_layers/posix/px_pth_setcanceltype.c index 73fa0623..0d403a08 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_setcanceltype.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_setcanceltype.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,17 +27,17 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_setcanceltype PORTABLE C */ -/* 6.1.7 */ -/* AUTHOR */ -/* */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_setcanceltype PORTABLE C */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ /* William E. Lamie, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ +/* */ +/* DESCRIPTION */ /* */ /* The pthread_setcancelstate()function shall atomically both get the */ /* calling thread's cancelability type to the indicated type and */ @@ -44,31 +45,25 @@ /* by oldtype. Legal values for type are PTHREAD_CANCEL_DEFERRED and */ /* PTHREAD_CANCEL_ASYNCHRONOUS. */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* type New cancelability type to be set */ /* oldtype Pointer to old cancelability type */ -/* */ -/* OUTPUT */ -/* */ -/* 0 if successful */ -/* Value in case of any error */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ -/**************************************************************************/ +/* */ +/* OUTPUT */ +/* */ +/* 0 if successful */ +/* Value in case of any error */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/**************************************************************************/ INT pthread_setcanceltype (INT type, INT *oldtype) { TX_INTERRUPT_SAVE_AREA @@ -77,12 +72,12 @@ TX_THREAD *thread_ptr; POSIX_TCB *pthread_ptr; /* First check for validity of the new cancel type to be set */ - if ( ( type == PTHREAD_CANCEL_DEFERRED ) || ( type == PTHREAD_CANCEL_ASYNCHRONOUS ) ) + if ( ( type == PTHREAD_CANCEL_DEFERRED ) || ( type == PTHREAD_CANCEL_ASYNCHRONOUS ) ) { TX_DISABLE - /* Get the thread identifier of the currently running thread */ - thread_ptr = tx_thread_identify(); + /* Get the thread identifier of the currently running thread */ + thread_ptr = tx_thread_identify(); /* get posix TCB for this pthread */ pthread_ptr = (POSIX_TCB *)thread_ptr; *oldtype = pthread_ptr->cancel_type; @@ -98,4 +93,4 @@ POSIX_TCB *pthread_ptr; posix_set_pthread_errno(EINVAL); return(EINVAL); } -} +} diff --git a/utility/rtos_compatibility_layers/posix/px_pth_setschedparam.c b/utility/rtos_compatibility_layers/posix/px_pth_setschedparam.c index ec4067c1..9970b900 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_setschedparam.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_setschedparam.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,50 +27,44 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_setschedparam PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_setschedparam PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This function changes the scheduling parameters of a pthread. */ /* */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* thread POSIX thread ID */ /* policy Address of the thread attributes */ /* sched_param Address of structure to contain the */ -/* returned scheduling parameters */ -/* */ -/* */ -/* OUTPUT */ -/* */ -/* 0 if successful */ -/* Value in case of any error */ -/* */ -/* CALLS */ -/* */ +/* returned scheduling parameters */ +/* */ +/* */ +/* OUTPUT */ +/* */ +/* 0 if successful */ +/* Value in case of any error */ +/* */ +/* CALLS */ +/* */ /* posix_tid2tcb */ /* posix_tcb2thread */ /* tx_thread_priority_change */ /* */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ INT pthread_setschedparam(pthread_t thread, INT policy, const struct sched_param *param) diff --git a/utility/rtos_compatibility_layers/posix/px_pth_sigmask.c b/utility/rtos_compatibility_layers/posix/px_pth_sigmask.c index 9838fda3..8957f0ae 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_sigmask.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_sigmask.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -63,15 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* 10-31-2022 Scott Larson Update pthread_kill argument */ -/* cast, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ int pthread_sigmask(int how, const sigset_t *newmask, sigset_t *oldmask) @@ -90,7 +82,7 @@ ULONG reissue_flag; /* Check for a valid how parameter. */ if ((how != SIG_BLOCK) && (how != SIG_SETMASK) & (how != SIG_UNBLOCK)) { - + /* Return an error. */ posix_set_pthread_errno(EINVAL); return(EINVAL); @@ -99,7 +91,7 @@ ULONG reissue_flag; /* Check for valid signal masks. */ if ((newmask == NULL) || (oldmask == NULL)) { - + /* Return an error. */ posix_set_pthread_errno(EINVAL); return(EINVAL); @@ -121,7 +113,7 @@ ULONG reissue_flag; /* Determine if the current thread is a signal handler thread. */ if (base_thread -> signals.signal_handler) { - + /* Pickup target thread. */ base_thread = base_thread -> signals.base_thread_ptr; } @@ -132,7 +124,7 @@ ULONG reissue_flag; /* Now process based on how the mask is to be changed. */ if (how == SIG_BLOCK) { - + /* Simply set the mask to block the signal(s). */ base_thread -> signals.signal_mask.signal_set = base_thread -> signals.signal_mask.signal_set | newmask -> signal_set; } @@ -145,17 +137,17 @@ ULONG reissue_flag; /* Now modify the singal mask correspondingly. */ if (how == SIG_UNBLOCK) { - + /* Clear only the signals specified in the new signal mask. */ base_thread -> signals.signal_mask.signal_set = base_thread -> signals.signal_mask.signal_set & ~(newmask -> signal_set); } else { - + /* Simply set the signal mask to the new signal mask value. */ base_thread -> signals.signal_mask.signal_set = newmask -> signal_set; } - + /* Now determine if there are any signals that need to be activated. */ released_signals = blocked_signals & ~(base_thread -> signals.signal_mask.signal_set); @@ -168,34 +160,34 @@ ULONG reissue_flag; /* Temporarily disable preemption. */ _tx_thread_preempt_disable++; - + /* Restore interrupts. */ TX_RESTORE - + /* Set the reissue flag to false. */ reissue_flag = TX_FALSE; - + /* Loop to process all the blocked signals. */ signal_number = 0; while ((released_signals) && (signal_number < 32)) { - + /* Determine if this signal was released. */ if (released_signals & 1) { - + /* Yes, this signal was released. We need to make it active again. */ - + /* Clear the pending bit so the pthread_kill call will not discard the signal (signals are not queued in this implementation). */ base_thread -> signals.signal_pending.signal_set = base_thread -> signals.signal_pending.signal_set & ~(((unsigned long) 1) << signal_number); /* Call pthread_kill to reissue the signal. */ pthread_kill((ALIGN_TYPE) base_thread, signal_number); - + /* Set the reissue flag. */ reissue_flag = TX_TRUE; } - + /* Look for next signal. */ released_signals = released_signals >> 1; signal_number++; @@ -206,22 +198,22 @@ ULONG reissue_flag; /* Release preemption. */ _tx_thread_preempt_disable--; - + /* Restore interrupts. */ TX_RESTORE /* Check for a preemption condition. */ _tx_thread_system_preempt_check(); - + /* Determine if the reissue flag is set. */ if (reissue_flag == TX_TRUE) { /* Relinquish to allow signal thread at same priority to run before we return. */ - _tx_thread_relinquish(); + _tx_thread_relinquish(); } } - } + } /* Setup return mask. */ oldmask -> signal_set = previous_mask; diff --git a/utility/rtos_compatibility_layers/posix/px_pth_testcancel.c b/utility/rtos_compatibility_layers/posix/px_pth_testcancel.c index 6e84dd32..e64729df 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_testcancel.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_testcancel.c @@ -1,17 +1,18 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -62,29 +63,23 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ VOID pthread_testcancel(VOID) { POSIX_TCB *pthread_ptr; - - /* Get the thread identifier of the calling pthread */ - pthread_ptr = posix_tid2tcb(pthread_self()); + + /* Get the thread identifier of the calling pthread */ + pthread_ptr = posix_tid2tcb(pthread_self()); /* Check if thread was created with cancel enable */ if ( (pthread_ptr->cancel_state == PTHREAD_CANCEL_ENABLE) && (pthread_ptr->cancel_type==PTHREAD_CANCEL_DEFERRED) && (pthread_ptr->cancel_request==TRUE) ) { - - /* Signal the housekeeping ThreadX thread to cancel (delete) this pthread */ + + /* Signal the housekeeping ThreadX thread to cancel (delete) this pthread */ posix_destroy_pthread(pthread_ptr,(VOID *)0); } } diff --git a/utility/rtos_compatibility_layers/posix/px_pth_yield.c b/utility/rtos_compatibility_layers/posix/px_pth_yield.c index 20113844..a6c17278 100644 --- a/utility/rtos_compatibility_layers/posix/px_pth_yield.c +++ b/utility/rtos_compatibility_layers/posix/px_pth_yield.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,45 +27,39 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* pthread_yield PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* pthread_yield PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This subroutine forces the calling thread to relinquish use of its */ /* processor,and to wait in the run queue before it is scheduled again.*/ /* If the run queue is empty when this subroutine is called, the */ /* calling thread is immediately rescheduled. */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* Nothing */ /* */ -/* OUTPUT */ -/* */ +/* OUTPUT */ +/* */ /* None */ /* */ -/* CALLS */ -/* */ -/* posix_internal_error posix internal error function */ -/* tx_thread_relinquish ThreadX function */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* CALLS */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* posix_internal_error posix internal error function */ +/* tx_thread_relinquish ThreadX function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ VOID pthread_yield(VOID) diff --git a/utility/rtos_compatibility_layers/posix/px_px_initialize.c b/utility/rtos_compatibility_layers/posix/px_px_initialize.c index 94ea3a06..0ad147a0 100644 --- a/utility/rtos_compatibility_layers/posix/px_px_initialize.c +++ b/utility/rtos_compatibility_layers/posix/px_px_initialize.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -27,8 +28,8 @@ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -77,12 +78,6 @@ /* */ /* POSIX internal code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ static VOID posix_memory_init(VOID * posix_heap_ptr) { @@ -94,7 +89,7 @@ INT retval; retval = tx_byte_pool_create((TX_BYTE_POOL *)&posix_heap_byte_pool, "POSIX HEAP", posix_heap_ptr, - POSIX_HEAP_SIZE_IN_BYTES); + POSIX_HEAP_SIZE_IN_BYTES); /* Make sure the byte pool was created successfully. */ if (retval) @@ -146,11 +141,11 @@ INT retval; static VOID posix_semaphore_init(VOID) { -ULONG i; -sem_t *sem_ptr; +ULONG i; +sem_t *sem_ptr; /* Start at the front of the pool. */ - sem_ptr = &(posix_sem_pool[0]); + sem_ptr = &(posix_sem_pool[0]); for (i = 0; i < SEM_NSEMS_MAX; i++, sem_ptr++) { @@ -219,20 +214,20 @@ VOID *posix_initialize(VOID * posix_memory) UCHAR *pointer; - /* Setup temporary memory pointer, so we can start allocating - space for the posix data structures. The important thing to + /* Setup temporary memory pointer, so we can start allocating + space for the posix data structures. The important thing to remember here is that the system thread's stack, the region0 memory, and the queue are allocated sequentially from the address specified by posix_memory. */ pointer = (UCHAR *)posix_memory; - - /* Start up the System Manager thread. */ + + /* Start up the System Manager thread. */ tx_thread_create(&posix_system_manager, "POSIX System Manager", posix_system_manager_entry, 0, pointer, POSIX_SYSTEM_STACK_SIZE, SYSMGR_PRIORITY, SYSMGR_THRESHOLD, - TX_NO_TIME_SLICE, TX_AUTO_START); - + TX_NO_TIME_SLICE, TX_AUTO_START); + pointer = pointer + POSIX_SYSTEM_STACK_SIZE; /* Set up a memory "heap" used internally by the POSIX. */ @@ -243,11 +238,11 @@ UCHAR *pointer; /* Create the work item message queue. */ tx_queue_create(&posix_work_queue, "POSIX work queue", WORK_REQ_SIZE, pointer, WORK_QUEUE_DEPTH*WORK_REQ_SIZE); - + pointer = pointer + (WORK_QUEUE_DEPTH * WORK_REQ_SIZE); - /* Initialize static pool of pthreads Control blocks. */ - posix_pthread_init(); + /* Initialize static pool of pthreads Control blocks. */ + posix_pthread_init(); /* Create a default pthread_attr */ set_default_pthread_attr(&posix_default_pthread_attr); @@ -264,7 +259,7 @@ UCHAR *pointer; /* Set up a pool of semaphores used internally by the POSIX. */ posix_semaphore_init(); #endif - + /* Create a default mutex_attr */ set_default_mutexattr(&posix_default_mutex_attr); diff --git a/utility/rtos_compatibility_layers/posix/px_sched_get_prio.c b/utility/rtos_compatibility_layers/posix/px_sched_get_prio.c index af2ec4c4..253622d7 100644 --- a/utility/rtos_compatibility_layers/posix/px_sched_get_prio.c +++ b/utility/rtos_compatibility_layers/posix/px_sched_get_prio.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -58,12 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ diff --git a/utility/rtos_compatibility_layers/posix/px_sched_yield.c b/utility/rtos_compatibility_layers/posix/px_sched_yield.c index fc2297bf..870a2572 100644 --- a/utility/rtos_compatibility_layers/posix/px_sched_yield.c +++ b/utility/rtos_compatibility_layers/posix/px_sched_yield.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ INT sched_yield(VOID) { diff --git a/utility/rtos_compatibility_layers/posix/px_sem_close.c b/utility/rtos_compatibility_layers/posix/px_sem_close.c index c695000d..8beb79a2 100644 --- a/utility/rtos_compatibility_layers/posix/px_sem_close.c +++ b/utility/rtos_compatibility_layers/posix/px_sem_close.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -60,12 +61,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ INT sem_close(sem_t * sem) { diff --git a/utility/rtos_compatibility_layers/posix/px_sem_destroy.c b/utility/rtos_compatibility_layers/posix/px_sem_destroy.c index 7f5db2fe..8cdbe619 100644 --- a/utility/rtos_compatibility_layers/posix/px_sem_destroy.c +++ b/utility/rtos_compatibility_layers/posix/px_sem_destroy.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -60,12 +61,6 @@ /* */ /* POSIX internal Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ INT sem_destroy(sem_t *sem) { @@ -76,7 +71,7 @@ INT sem_destroy(sem_t *sem) result = EINVAL; /* general error */ } - else + else { if(sem->sem.tx_semaphore_suspended_count > 0 ) result = EBUSY; else result = NO_ERROR; diff --git a/utility/rtos_compatibility_layers/posix/px_sem_find_sem.c b/utility/rtos_compatibility_layers/posix/px_sem_find_sem.c index c8e3c85b..ada7fe37 100644 --- a/utility/rtos_compatibility_layers/posix/px_sem_find_sem.c +++ b/utility/rtos_compatibility_layers/posix/px_sem_find_sem.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -58,14 +59,6 @@ /* */ /* POSIX internal Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* 08-02-2021 Scott Larson Removed unneeded semicolon, */ -/* resulting in version 6.1.8 */ -/* */ /**************************************************************************/ sem_t* posix_find_sem(const CHAR * name) { diff --git a/utility/rtos_compatibility_layers/posix/px_sem_get_new_sem.c b/utility/rtos_compatibility_layers/posix/px_sem_get_new_sem.c index 0a7e56a0..e5e9239f 100644 --- a/utility/rtos_compatibility_layers/posix/px_sem_get_new_sem.c +++ b/utility/rtos_compatibility_layers/posix/px_sem_get_new_sem.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -57,12 +58,6 @@ /* */ /* POSIX internal Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ TX_SEMAPHORE * posix_get_new_sem(VOID) { @@ -85,7 +80,7 @@ sem_t *sem_ptr; if (sem_ptr->in_use == TX_FALSE) { - /* Found one! */ + /* Found one! */ tx_sem = MAKE_TX_SEM(sem_ptr); /* This semaphore is now in use. */ diff --git a/utility/rtos_compatibility_layers/posix/px_sem_getvalue.c b/utility/rtos_compatibility_layers/posix/px_sem_getvalue.c index 0e751697..291c59d0 100644 --- a/utility/rtos_compatibility_layers/posix/px_sem_getvalue.c +++ b/utility/rtos_compatibility_layers/posix/px_sem_getvalue.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -60,12 +61,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ INT sem_getvalue(sem_t * sem,ULONG * sval) { @@ -74,7 +69,7 @@ TX_INTERRUPT_SAVE_AREA TX_SEMAPHORE *TheSem; - /* get ThreadX semaphore. */ + /* get ThreadX semaphore. */ TheSem = (TX_SEMAPHORE *)sem; /* First, check for an invalid semaphore pointer. */ diff --git a/utility/rtos_compatibility_layers/posix/px_sem_init.c b/utility/rtos_compatibility_layers/posix/px_sem_init.c index 48cab2ea..532491e6 100644 --- a/utility/rtos_compatibility_layers/posix/px_sem_init.c +++ b/utility/rtos_compatibility_layers/posix/px_sem_init.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -60,12 +61,6 @@ /* */ /* POSIX internal Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ INT sem_init(sem_t *sem , INT pshared, UINT value) { @@ -76,7 +71,7 @@ INT sem_init(sem_t *sem , INT pshared, UINT value) result = EINVAL; /* general error */ } - else + else { if(tx_semaphore_create(&(sem->sem),"",value)) result = EINVAL; else diff --git a/utility/rtos_compatibility_layers/posix/px_sem_open.c b/utility/rtos_compatibility_layers/posix/px_sem_open.c index 18ef1462..ad9468a8 100644 --- a/utility/rtos_compatibility_layers/posix/px_sem_open.c +++ b/utility/rtos_compatibility_layers/posix/px_sem_open.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -64,21 +65,13 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* 10-31-2022 Scott Larson Update comparison with NULL, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ sem_t * sem_open(const CHAR * name, ULONG oflag, ...) { TX_INTERRUPT_SAVE_AREA -TX_SEMAPHORE *TheSem; +TX_SEMAPHORE *TheSem; sem_t *semid; ULONG retval; ULONG len; @@ -92,7 +85,7 @@ mode_t mode; { /* return POSIX error. */ posix_internal_error(444); - + /* return error. */ return (( sem_t * )SEM_FAILED); } @@ -134,7 +127,7 @@ mode_t mode; posix_set_pthread_errno(ENOENT); /* Return the SEM_FAILED error. */ - return(( sem_t * )SEM_FAILED); + return(( sem_t * )SEM_FAILED); } if( (oflag == O_CREAT) || ( (oflag & (O_CREAT|O_EXCL )) == (O_CREAT|O_EXCL) ) ) { @@ -206,7 +199,7 @@ mode_t mode; posix_sem->refCnt = value; /* Give the caller the semaphore ID. */ - semid = (sem_t * )TheSem; + semid = (sem_t * )TheSem; /* Restore interrupts. */ TX_RESTORE diff --git a/utility/rtos_compatibility_layers/posix/px_sem_post.c b/utility/rtos_compatibility_layers/posix/px_sem_post.c index 0b72935d..a1164a0d 100644 --- a/utility/rtos_compatibility_layers/posix/px_sem_post.c +++ b/utility/rtos_compatibility_layers/posix/px_sem_post.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -58,12 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ INT sem_post(sem_t * sem) { diff --git a/utility/rtos_compatibility_layers/posix/px_sem_reset.c b/utility/rtos_compatibility_layers/posix/px_sem_reset.c index 2a663e74..0d94e269 100644 --- a/utility/rtos_compatibility_layers/posix/px_sem_reset.c +++ b/utility/rtos_compatibility_layers/posix/px_sem_reset.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -56,12 +57,6 @@ /* */ /* POSIX internal Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ VOID posix_sem_reset(sem_t *sem ) { diff --git a/utility/rtos_compatibility_layers/posix/px_sem_set_sem_name.c b/utility/rtos_compatibility_layers/posix/px_sem_set_sem_name.c index 2f40abae..f662bfca 100644 --- a/utility/rtos_compatibility_layers/posix/px_sem_set_sem_name.c +++ b/utility/rtos_compatibility_layers/posix/px_sem_set_sem_name.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -57,12 +58,6 @@ /* */ /* POSIX internal code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ VOID posix_set_sem_name(sem_t * sem, CHAR *name) { diff --git a/utility/rtos_compatibility_layers/posix/px_sem_trywait.c b/utility/rtos_compatibility_layers/posix/px_sem_trywait.c index db482a7d..04a9afeb 100644 --- a/utility/rtos_compatibility_layers/posix/px_sem_trywait.c +++ b/utility/rtos_compatibility_layers/posix/px_sem_trywait.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -60,12 +61,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ INT sem_trywait(sem_t * sem) { diff --git a/utility/rtos_compatibility_layers/posix/px_sem_unlink.c b/utility/rtos_compatibility_layers/posix/px_sem_unlink.c index 7bba322b..92ec02a0 100644 --- a/utility/rtos_compatibility_layers/posix/px_sem_unlink.c +++ b/utility/rtos_compatibility_layers/posix/px_sem_unlink.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -60,14 +61,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* 10-31-2022 Scott Larson Remove double parenthesis, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ INT sem_unlink(const CHAR * name) { @@ -96,7 +89,7 @@ ULONG len; posix_set_pthread_errno(ENOENT); /* Return Error. */ - return(ERROR); + return(ERROR); } if(sem) diff --git a/utility/rtos_compatibility_layers/posix/px_sem_wait.c b/utility/rtos_compatibility_layers/posix/px_sem_wait.c index a7f510f2..f1be786d 100644 --- a/utility/rtos_compatibility_layers/posix/px_sem_wait.c +++ b/utility/rtos_compatibility_layers/posix/px_sem_wait.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -59,12 +60,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ INT sem_wait( sem_t * sem ) { diff --git a/utility/rtos_compatibility_layers/posix/px_sig_addset.c b/utility/rtos_compatibility_layers/posix/px_sig_addset.c index b94db0a6..a0e657c8 100644 --- a/utility/rtos_compatibility_layers/posix/px_sig_addset.c +++ b/utility/rtos_compatibility_layers/posix/px_sig_addset.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -59,12 +60,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ int sigaddset(sigset_t *set, int signo) { @@ -72,7 +67,7 @@ int sigaddset(sigset_t *set, int signo) /* Determine if the desired signal is valid. */ if ((signo < 0) || (signo > SIGRTMAX)) { - + /* Return an error. */ posix_set_pthread_errno(EINVAL); return(ERROR); @@ -82,5 +77,5 @@ int sigaddset(sigset_t *set, int signo) set -> signal_set = set -> signal_set | (((ULONG) 1) << signo); /* Return success! */ - return(OK); + return(OK); } diff --git a/utility/rtos_compatibility_layers/posix/px_sig_delset.c b/utility/rtos_compatibility_layers/posix/px_sig_delset.c index a2867781..eb2943d3 100644 --- a/utility/rtos_compatibility_layers/posix/px_sig_delset.c +++ b/utility/rtos_compatibility_layers/posix/px_sig_delset.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -59,12 +60,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ int sigdelset(sigset_t *set, int signo) { @@ -72,7 +67,7 @@ int sigdelset(sigset_t *set, int signo) /* Determine if the desired signal is valid. */ if ((signo < 0) || (signo > SIGRTMAX)) { - + /* Return an error. */ posix_set_pthread_errno(EINVAL); return(EINVAL); @@ -82,5 +77,5 @@ int sigdelset(sigset_t *set, int signo) set -> signal_set = set -> signal_set & ~(((unsigned long) 1) << signo); /* Return success! */ - return(OK); + return(OK); } diff --git a/utility/rtos_compatibility_layers/posix/px_sig_emptyset.c b/utility/rtos_compatibility_layers/posix/px_sig_emptyset.c index 8cc92aa9..3bf716df 100644 --- a/utility/rtos_compatibility_layers/posix/px_sig_emptyset.c +++ b/utility/rtos_compatibility_layers/posix/px_sig_emptyset.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -57,12 +58,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ int sigemptyset(sigset_t *set) { @@ -70,7 +65,7 @@ int sigemptyset(sigset_t *set) /* Is there a pointer. */ if (!set) { - + /* Return an error. */ posix_set_pthread_errno(EINVAL); return(ERROR); diff --git a/utility/rtos_compatibility_layers/posix/px_sig_fillset.c b/utility/rtos_compatibility_layers/posix/px_sig_fillset.c index 46447ff8..d769a6e8 100644 --- a/utility/rtos_compatibility_layers/posix/px_sig_fillset.c +++ b/utility/rtos_compatibility_layers/posix/px_sig_fillset.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -58,12 +59,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ int sigfillset(sigset_t *set) { @@ -71,7 +66,7 @@ int sigfillset(sigset_t *set) /* Is there a pointer. */ if (!set) { - + /* Return an error. */ posix_set_pthread_errno(EINVAL); return(ERROR); diff --git a/utility/rtos_compatibility_layers/posix/px_sig_signal.c b/utility/rtos_compatibility_layers/posix/px_sig_signal.c index 7cbdd012..d086adce 100644 --- a/utility/rtos_compatibility_layers/posix/px_sig_signal.c +++ b/utility/rtos_compatibility_layers/posix/px_sig_signal.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -61,12 +62,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ int signal(int signo, void (*func)(int)) { @@ -85,7 +80,7 @@ POSIX_TCB *current_thread; /* Determine if the desired signal is valid. */ if ((signo < 0) || (signo > SIGRTMAX)) { - + /* Return an error. */ posix_set_pthread_errno(EINVAL); return(ERROR); @@ -93,10 +88,10 @@ POSIX_TCB *current_thread; /* Now pickup the current thread pointer. */ current_thread = (POSIX_TCB *) tx_thread_identify(); - + /* Now index into the array of signal handlers and insert this one. */ current_thread -> signals.signal_func[signo] = func; - + /* Return success! */ return(OK); } diff --git a/utility/rtos_compatibility_layers/posix/px_sig_wait.c b/utility/rtos_compatibility_layers/posix/px_sig_wait.c index 92294a73..35ea6531 100644 --- a/utility/rtos_compatibility_layers/posix/px_sig_wait.c +++ b/utility/rtos_compatibility_layers/posix/px_sig_wait.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /**************************************************************************/ /**************************************************************************/ @@ -63,12 +64,6 @@ /* */ /* Application Code */ /* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ int sigwait(const sigset_t *set, int *sig) { @@ -99,7 +94,7 @@ POSIX_TCB *base_thread; /* Determine if the current thread is a signal handler thread. */ if (base_thread -> signals.signal_handler) { - + /* Pickup target thread. */ base_thread = base_thread -> signals.base_thread_ptr; } @@ -114,9 +109,9 @@ POSIX_TCB *base_thread; /* Are there any. */ if (pending_signals) { - + /* Yes, there are signals being masked currently that would satisfy this request. */ - + /* Save the current mask. */ saved_mask = base_thread -> signals.signal_mask.signal_set; @@ -125,31 +120,31 @@ POSIX_TCB *base_thread; /* Call pthread_sigmask to temporarily unblock these signals which will release them as well. */ pthread_sigmask(SIG_UNBLOCK, set, &original_set); - + /* Now determine if the changed mask is still in effect, i.e., there wasn't a pthread_sigmask call from any subsequent signal handlers. */ if (base_thread -> signals.signal_mask.signal_set == changed_mask) { - + /* Yes, restore the previous signal mask. */ base_thread -> signals.signal_mask.signal_set = saved_mask; } - + /* Derived the signal number from the bit map. */ TX_LOWEST_SET_BIT_CALCULATE(pending_signals, signal_number); - + /* Return the signal number. */ *sig = (int) signal_number; - + /* Return success! */ return(OK); } - + /* Determine if there are any signals that have to be temporarily cleared. */ if (base_thread -> signals.signal_mask.signal_set & set -> signal_set) { - + /* Yes, there are signals being masked needed to satisfy this request. */ - + /* Save the current mask. */ saved_mask = base_thread -> signals.signal_mask.signal_set; @@ -159,14 +154,14 @@ POSIX_TCB *base_thread; /* Apply the changed signal mask. */ base_thread -> signals.signal_mask.signal_set = changed_mask; } - + /* Suspend on the signal specified by the input. */ status = tx_event_flags_get(&(base_thread -> signals.signal_event_flags), (ULONG) set -> signal_set, TX_OR_CLEAR, &signal_bit_map, TX_WAIT_FOREVER); /* Determine if we need to restore the signal mask. */ if ((saved_mask) && (changed_mask == base_thread -> signals.signal_mask.signal_set)) { - + /* Yes, the signal mask should be restored. */ base_thread -> signals.signal_mask.signal_set = saved_mask; } @@ -174,19 +169,19 @@ POSIX_TCB *base_thread; /* Check for successful status. */ if (status == TX_SUCCESS) { - + /* Derived the signal number from the bit map. */ TX_LOWEST_SET_BIT_CALCULATE(signal_bit_map, signal_number); - + /* Return the signal number. */ *sig = (int) signal_number; - + /* Return success! */ return(OK); } else { - + /* Return error! */ return(EINVAL); } diff --git a/utility/rtos_compatibility_layers/posix/px_sleep.c b/utility/rtos_compatibility_layers/posix/px_sleep.c index 1ed878f4..87eda03e 100644 --- a/utility/rtos_compatibility_layers/posix/px_sleep.c +++ b/utility/rtos_compatibility_layers/posix/px_sleep.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -26,49 +27,43 @@ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* sleep PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* sleep PORTABLE C */ /* 6.1.7 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ +/* DESCRIPTION */ /* */ /* This function shall cause the calling thread to be suspended from */ /* execution until either the number of realtime seconds specified by */ -/* the argument seconds has elapsed */ +/* the argument seconds has elapsed */ /* */ -/* INPUT */ +/* INPUT */ /* */ /* seconds Is the number of real-time (as opposed */ /* to CPU-time) seconds to suspend the */ /* calling thread. */ /* */ -/* OUTPUT */ -/* */ +/* OUTPUT */ +/* */ /* number of seconds remaining to sleep */ /* A nonzero value indicates sleep was */ /* interrupted. Zero is successful */ /* completion */ /* */ /* */ -/* CALLS */ +/* CALLS */ /* */ /* tx_thread_sleep ThreadX thread sleep service */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ +/* CALLED BY */ +/* */ +/* Application Code */ /* */ /**************************************************************************/ UINT sleep(ULONG seconds) @@ -90,7 +85,7 @@ UINT temp1, temp2, diff, result; result = ((seconds * CPU_TICKS_PER_SECOND) - diff); } - return (result/CPU_TICKS_PER_SECOND); - + return (result/CPU_TICKS_PER_SECOND); + } diff --git a/utility/rtos_compatibility_layers/posix/px_system_manager.c b/utility/rtos_compatibility_layers/posix/px_system_manager.c index ef24202b..92b71414 100644 --- a/utility/rtos_compatibility_layers/posix/px_system_manager.c +++ b/utility/rtos_compatibility_layers/posix/px_system_manager.c @@ -1,18 +1,19 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ /**************************************************************************/ /**************************************************************************/ -/** */ -/** POSIX wrapper for THREADX */ +/** */ +/** POSIX wrapper for THREADX */ /** */ /** */ /** */ @@ -25,46 +26,38 @@ #include "pthread.h" /* Posix API */ #include "px_int.h" /* Posix helper functions */ -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* posix_system_manager_entry PORTABLE C */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* posix_system_manager_entry PORTABLE C */ /* 6.2.0 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ +/* DESCRIPTION */ +/* */ /* This is the System Manager thread for the POSIX> The system */ /* manager thread cleans up terminated threads and releases */ /* the stack memory associated with the thread */ -/* */ -/* INPUT */ -/* */ -/* input Not used */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ /* */ -/* tx_queue_receive Receive system request */ +/* INPUT */ +/* */ +/* input Not used */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* tx_queue_receive Receive system request */ /* posix_do_pthread_delete Delete a pthread */ /* */ -/* CALLED BY */ -/* */ -/* Start-up code */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ +/* CALLED BY */ /* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* 10-31-2022 Scott Larson Add 64-bit support, */ -/* resulting in version 6.2.0 */ +/* Start-up code */ /* */ /**************************************************************************/ VOID posix_system_manager_entry(ULONG input) @@ -79,18 +72,18 @@ VOID *value_ptr; /* Avoid compiler warning. */ TX_PARAMETER_NOT_USED(input); - /* Loop forever, waiting for work requests. */ + /* Loop forever, waiting for work requests. */ while(1) { /* Wait forever for the next work request. */ status = tx_queue_receive(&posix_work_queue, &request, TX_WAIT_FOREVER); - /* Make sure we didn't encounter any trouble. */ + /* Make sure we didn't encounter any trouble. */ if (status != TX_SUCCESS) { /* Get the next message. */ continue; } - + #ifdef TX_64_BIT pthread_ptr = (POSIX_TCB *)((((ALIGN_TYPE)request[0]) << 32) | request[1]); value_ptr = (VOID *)((((ALIGN_TYPE)request[2]) << 32) | request[3]); @@ -101,7 +94,7 @@ VOID *value_ptr; /* Delete the pthread */ posix_do_pthread_delete(pthread_ptr, value_ptr); - + } /* System Manager forever loop */ } diff --git a/utility/rtos_compatibility_layers/posix/readme_release_history.txt b/utility/rtos_compatibility_layers/posix/readme_release_history.txt index 2eb4eaa0..fe6ea047 100644 --- a/utility/rtos_compatibility_layers/posix/readme_release_history.txt +++ b/utility/rtos_compatibility_layers/posix/readme_release_history.txt @@ -1,4 +1,4 @@ - + px_abs_time_to_rel_ticks.c Casted size_t to ULONG. px_clock_gettime.c Casted size_t to ULONG. @@ -12,18 +12,18 @@ tx_posix.h Reduced default object pool sizes, added posix_initialize prototype. Improved default stack size symbol name - px_memory_release.c When thread completes and posix_do_pthread_delete() is called, - posix_memory_release() returns with error if stack was not + px_memory_release.c When thread completes and posix_do_pthread_delete() is called, + posix_memory_release() returns with error if stack was not allocated from the posix pool but rather stack is a static array. - px_mq_open.c Fixed bug to handle a NULL attribute in mq_open(). + px_mq_open.c Fixed bug to handle a NULL attribute in mq_open(). px_pth_create.c Call to pthread_create() with pthread_attr_t set to NULL or with the default values as set by pthread_attr_init() has unexpected behavior. Fixed by adding code to use defaults. - px_pth_init.c Fixed memory leak when threads are released or killed by - calling posix_reset_pthread after posix_destroy_pthread() + px_pth_init.c Fixed memory leak when threads are released or killed by + calling posix_reset_pthread after posix_destroy_pthread() which was not returning memory to the TCB pool Fixed bug when trying to join threads from ThreadX context when diff --git a/utility/rtos_compatibility_layers/posix/readme_threadx_posix.txt b/utility/rtos_compatibility_layers/posix/readme_threadx_posix.txt index 5aeb5d52..d9321396 100644 --- a/utility/rtos_compatibility_layers/posix/readme_threadx_posix.txt +++ b/utility/rtos_compatibility_layers/posix/readme_threadx_posix.txt @@ -12,17 +12,17 @@ ThreadX primitives and bypasses basic ThreadX error checking. 1.1 POSIX Compliancy Wrapper Source -The Wrapper source code is designed for simplicity and is comprised of separate source -files for most functions. Including the supplied pthread.h file will import +The Wrapper source code is designed for simplicity and is comprised of separate source +files for most functions. Including the supplied pthread.h file will import all the necessary POSIX constants and subroutine prototypes. 1.2 POSIX Compliancy Wrapper Documentation This document itself serves as a POSIX Compliancy Wrapper User Guide by -providing an overview of the porting process, including various caveats and -pitfalls to watch out for. In addition, each covered POSIX call is documented, -including information about supported/unsupported options, limitations, deviations, +providing an overview of the porting process, including various caveats and +pitfalls to watch out for. In addition, each covered POSIX call is documented, +including information about supported/unsupported options, limitations, deviations, and suggestions on how to work-around any limitations. @@ -31,32 +31,32 @@ and suggestions on how to work-around any limitations. The POSIX Compliancy Wrapper is easily installed by adding the the posix library to your current application build. Make sure your application build references the same header files as the ones the posix library has been built with. -The file pthread.h must be included in your application source where POSIX +The file pthread.h must be included in your application source where POSIX calls are required. Since the POSIX compliancy wrapper does not cover the complete standard, not all prototypes are provided. Most notably is the header file tx_px_time.h. 2.1 Initialization -The POSIX Compliancy Wrapper requires that a special initialization function is called +The POSIX Compliancy Wrapper requires that a special initialization function is called prior to accessing any POSIX calls. The function to call and its prototype is: VOID *posix_initialize(VOID * posix_memory); This function is usually called from the application specific ThreadX -initialization routine, tx_application_define(). The memory pointer supplied -to posix_initialize must be a contiguouis reserved section of memory +initialization routine, tx_application_define(). The memory pointer supplied +to posix_initialize must be a contiguouis reserved section of memory that has at least the following number of bytes: POSIX_SYSTEM_STACK_SIZE + TX_REGION0_SIZE_IN_BYTES + /* Region0 size */ (WORK_QUEUE_DEPTH * WORK_REQ_SIZE) + /* system queue size */ - POSIX_HEAP_SIZE_IN_BYTES + POSIX_HEAP_SIZE_IN_BYTES These equates are defined in tx_posix.h. The following additional equates -define the number of POSIX objects supported by the POSIX Wrapper (default +define the number of POSIX objects supported by the POSIX Wrapper (default value is shown): SEM_NSEMS_MAX 100 /* simultaneous POSIX semaphores */ @@ -77,7 +77,7 @@ value is shown): POSIX mutexes sported. */ -The function posix_initialize will return a pointer to the next free +The function posix_initialize will return a pointer to the next free available memory location for the application. @@ -119,7 +119,7 @@ INT sem_destroy(sem_t *sem); /***********************************************************************/ INT sched_yield(VOID); -INT pthread_create (pthread_t *thread, +INT pthread_create (pthread_t *thread, pthread_attr_t *attr, VOID *(*start_routine)(VOID*),VOID *arg); INT pthread_detach(pthread_t thread); @@ -220,35 +220,35 @@ throughout the Wrapper, as follows: posix_error_handler posix_internal_error -In general these routines are called when basic usage errors occur. These -routines may also be used as a place to catch errors that are not detected if the -application source is not checking the return status. The default processing for each of +In general these routines are called when basic usage errors occur. These +routines may also be used as a place to catch errors that are not detected if the +application source is not checking the return status. The default processing for each of these is a simple spin loop. Most functions can provide an error number. The means by which each function -provides its error numbers is specified in its description. Some functions -provide the error number in a variable accessed through the symbol posix_errno. -While other functions return an error number directly as the function value. Functions -return a value of zero to indicate success. If more than one error occurs in -processing a function call, any one of the possible errors may be returned, as the order +provides its error numbers is specified in its description. Some functions +provide the error number in a variable accessed through the symbol posix_errno. +While other functions return an error number directly as the function value. Functions +return a value of zero to indicate success. If more than one error occurs in +processing a function call, any one of the possible errors may be returned, as the order of detection is undefined. Some functions may return [ENOSYS] suggesting that an attempt was made to use a function that is not available in this implementation. -Each pthread has its own error number, which can be obtained through a +Each pthread has its own error number, which can be obtained through a function call: INT posix_get_pthread_errno(pthread_t ptid) -This call will return the last generated error code for the pthread having +This call will return the last generated error code for the pthread having ptid as an ID. 5.1 POSIX Compliancy Wrapper Limitations Due to performance and architecture issues, this POSIX Compliancy Wrapper -does not support all the POSIX calls. A summary of the POSIX Compliancy +does not support all the POSIX calls. A summary of the POSIX Compliancy Wrapper limitations is as follows: · Configuration @@ -288,8 +288,8 @@ Following calls are implemented with some limitations: space becomes available in that queue, the message with the highest priority will be unblocked. THIS FEATURE IS NOT IMPLEMENTED. - b.) If a message is sent (or received) to a queue with out opening the named - queue, in such a case mqdes (message queue descriptor) pointer is + b.) If a message is sent (or received) to a queue with out opening the named + queue, in such a case mqdes (message queue descriptor) pointer is invalid and may result in erratic behavior. 3.) mq_receive() @@ -323,11 +323,11 @@ Following calls are implemented with some limitations: 7.) Thread Cancelation pthread cancelation cleanup handlers are not supported which means -pthread_cleanup_push( ) and pthread_cleanup_pop( ) functions are not +pthread_cleanup_push( ) and pthread_cleanup_pop( ) functions are not implemented. When the pthread_cancel( ) function is called the target thread is canceled -with immediate effect. (provided cancelability is enabled for the target +with immediate effect. (provided cancelability is enabled for the target pthread) The cancelation processing in the target thread shall run asynchronously @@ -337,7 +337,7 @@ with respect to the ailing thread returning from pthread_cancel( ). No attributes are supported for condition variable in this implementation. 9.) pthreads suspended by nanosleep() and sleep() calls can not be awakened -by signals, once in the suspension both these calls will complete the +by signals, once in the suspension both these calls will complete the suspension period. 10.) pthread_once (pthread_once_t * once_control, VOID (*init_routine) (VOID)) @@ -347,8 +347,8 @@ There is no provision if the init_routine contains a cancellation point. 6.0 Demonstration System The file posix_demo.c contains a demonstration system that utilizes POSIX -calls. This Demo application will demonstrate some of the basic POSIX -calls. This demo application should be used as an example of how to integrate the POSIX +calls. This Demo application will demonstrate some of the basic POSIX +calls. This demo application should be used as an example of how to integrate the POSIX Compliancy Wrapper into your application. diff --git a/utility/rtos_compatibility_layers/posix/sched.h b/utility/rtos_compatibility_layers/posix/sched.h index 3a150170..2f37b05c 100644 --- a/utility/rtos_compatibility_layers/posix/sched.h +++ b/utility/rtos_compatibility_layers/posix/sched.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -33,20 +34,13 @@ /* This file defines the constants, structures, etc.needed to */ /* implement the Evacuation Kit for POSIX Users (POSIX) */ /* */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ #ifndef _SCHED_H #define _SCHED_H -struct sched_param +struct sched_param { INT sched_priority; }; diff --git a/utility/rtos_compatibility_layers/posix/signal.h b/utility/rtos_compatibility_layers/posix/signal.h index 72722c67..0da4adea 100644 --- a/utility/rtos_compatibility_layers/posix/signal.h +++ b/utility/rtos_compatibility_layers/posix/signal.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -33,23 +34,13 @@ /* This file defines the constants, structures, etc.needed to */ /* implement signals functionality for POSIX Users (POSIX) */ /* */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* 10-31-2022 Scott Larson Update pthread_kill argument */ -/* type, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ #ifndef _SIGNAL_H #define _SIGNAL_H -/* The POSIX wrapper for ThreadX supports a maximum of 32 signals, from 0 +/* The POSIX wrapper for ThreadX supports a maximum of 32 signals, from 0 through 31, inclusive. In this implemenation, signals are NOT queued. */ @@ -87,15 +78,15 @@ typedef struct signal_info_struct UINT signal_handler; /* This is a flag. If TRUE, this thread is being used as a signal handler. If FALSE, it is a regular thread. */ UINT signal_nesting_depth; /* A positive value indicates the level of nested signal handling the POSIX thread is currently processing. */ - sigset_t signal_pending; /* Bit map of signals pending. */ - sigset_t signal_mask; /* Signal mask, bit blocks the signal until cleared. */ + sigset_t signal_pending; /* Bit map of signals pending. */ + sigset_t signal_mask; /* Signal mask, bit blocks the signal until cleared. */ UINT saved_thread_state; /* Saved ThreadX state of the POSIX thread, at the time of the first signal. */ - struct pthread_control_block *base_thread_ptr; /* Pointer to the thread associated with the signal. */ - struct pthread_control_block *top_signal_thread; /* Pointer to the top (most recent) signal thread. */ - struct pthread_control_block *next_signal_thread; /* Pointer to the next most recent signal thread. */ - void (*signal_func[MAX_SIGNALS])(int); /* Array of signal handlers for this thread. */ - TX_EVENT_FLAGS_GROUP signal_event_flags; /* ThreadX event flag group used for sigwait */ - + struct pthread_control_block *base_thread_ptr; /* Pointer to the thread associated with the signal. */ + struct pthread_control_block *top_signal_thread; /* Pointer to the top (most recent) signal thread. */ + struct pthread_control_block *next_signal_thread; /* Pointer to the next most recent signal thread. */ + void (*signal_func[MAX_SIGNALS])(int); /* Array of signal handlers for this thread. */ + TX_EVENT_FLAGS_GROUP signal_event_flags; /* ThreadX event flag group used for sigwait */ + } signal_info; diff --git a/utility/rtos_compatibility_layers/posix/time.h b/utility/rtos_compatibility_layers/posix/time.h index 51f30be9..9fabdec5 100644 --- a/utility/rtos_compatibility_layers/posix/time.h +++ b/utility/rtos_compatibility_layers/posix/time.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -34,13 +35,6 @@ /* implement time related functionality for the Evacuation Kit */ /* for POSIX Users (POSIX) */ /* */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ #ifndef _TX_PX_TIME_H @@ -53,7 +47,7 @@ typedef ULONG time_t; typedef INT clockid_t; -struct timespec +struct timespec { time_t tv_sec; /* time in terms of seconds */ ULONG tv_nsec; /* remaining time in terms of nano seconds*/ @@ -62,7 +56,7 @@ struct timespec struct itimerspec { struct timespec it_interval ; /* Timer period. */ - struct timespec it_value; /* Timer expiration. */ + struct timespec it_value; /* Timer expiration. */ }; #define CLOCK_REALTIME 1 diff --git a/utility/rtos_compatibility_layers/posix/tx_posix.h b/utility/rtos_compatibility_layers/posix/tx_posix.h index 88986402..ce533dd8 100644 --- a/utility/rtos_compatibility_layers/posix/tx_posix.h +++ b/utility/rtos_compatibility_layers/posix/tx_posix.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -33,16 +34,6 @@ /* This file defines the constants, structures, etc.needed to */ /* implement the Evacuation Kit for POSIX Users (POSIX) */ /* */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* 10-31-2022 Scott Larson Update WORK_REQ_SIZE value, */ -/* update pthread_t typedef, */ -/* resulting in version 6.2.0 */ -/* */ /**************************************************************************/ #ifndef TX_POSIX @@ -84,15 +75,15 @@ #endif */ -/* Define the system configuration constants for the Evacuation Kit for - POSIX Users.This is where the number of system objects +/* Define the system configuration constants for the Evacuation Kit for + POSIX Users.This is where the number of system objects (pthreads, message queues, semaphores etc.)are defined. */ /************************************************************************/ /* SYSTEM CONFIGURATION PARAMETERS */ /************************************************************************/ -/* Define the maximum number of simultaneous POSIX semaphores +/* Define the maximum number of simultaneous POSIX semaphores supported. */ #define SEM_NSEMS_MAX 16 @@ -103,14 +94,14 @@ #define SEM_VALUE_MAX 100 /* Define the maximum number of simultaneous POSIX message queues supported. */ - + #define POSIX_MAX_QUEUES 16 /* Define the maximum number of simultaneous POSIX pthreads supported. */ #define PTHREAD_THREADS_MAX 16 /* Define the maximum number of simultaneous POSIX mutexes supported. */ - + #define POSIX_MAX_MUTEX 16 /* Define the maximum length of name of message queue. */ @@ -131,8 +122,8 @@ /* Define number of CPU ticks per second */ -#define CPU_TICKS_PER_SECOND 100 /* assuming 10 mSec tick */ -#define NANOSECONDS_IN_CPU_TICK 10000000 /* assuming 10 mSec tick */ +#define CPU_TICKS_PER_SECOND 100 /* assuming 10 mSec tick */ +#define NANOSECONDS_IN_CPU_TICK 10000000 /* assuming 10 mSec tick */ /* Define queue control specific data definitions. */ @@ -146,7 +137,7 @@ /************************************************************************/ #define POSIX_STACK_PADDING 1024 #define POSIX_SYSTEM_STACK_SIZE 1024 -#define POSIX_PTHREAD_STACK_SIZE 1024 +#define POSIX_PTHREAD_STACK_SIZE 1024 /************************************************************************/ /* ARCHITECTURE DEFINITIONS */ @@ -172,9 +163,9 @@ #define MIN_STACKSIZE_POWERPC 2048 -/************************************************************************/ -/* MISCELLANEOUS CONSTANTS */ -/************************************************************************/ +/************************************************************************/ +/* MISCELLANEOUS CONSTANTS */ +/************************************************************************/ /* Requests/commands to SysMgr task. */ #define SYSMGR_DELETE_TASK 0 @@ -183,7 +174,7 @@ #define PTHREAD_NAME_LEN 4 #define PTHREAD_CREATE_DETACHED 1 -#define PTHREAD_CREATE_JOINABLE 0 +#define PTHREAD_CREATE_JOINABLE 0 /* scheduler related constants */ @@ -224,9 +215,9 @@ enum pth_once_state { PTH_ONCE_CANCELLED = 0x3 }; -/************************************************************************/ -/* ERROR CODES (those defined outside of POSIX) */ -/************************************************************************/ +/************************************************************************/ +/* ERROR CODES (those defined outside of POSIX) */ +/************************************************************************/ #ifdef ERROR #undef ERROR @@ -277,14 +268,14 @@ typedef ULONG BOOL; typedef struct pthread_attr_obj { ULONG pthread_flags; - INT detach_state; + INT detach_state; INT inherit_sched; INT sched_policy; struct sched_param sched_attr; VOID *stack_address; ULONG stack_size; INT inuse; -} pthread_attr_t; +} pthread_attr_t; typedef INT ssize_t ; /* this should be pulled in from sys\types.h */ @@ -297,24 +288,24 @@ typedef ULONG mode_t; typedef struct pthread_control_block { - /* This pthread's ThreadX TCB. */ + /* This pthread's ThreadX TCB. */ TX_THREAD thread_info; /* This pthread's unique identifier */ pthread_t pthreadID; /* To check if posix Pthread is in use. */ UINT in_use; /* All pthread attributes contained in the a pthread_attr_t object */ - ULONG pthread_flags; - INT detach_state; + ULONG pthread_flags; + INT detach_state; INT inherit_sched; INT sched_policy; struct sched_param sched_attr; VOID *stack_address; ULONG stack_size; INT cancel_state; - INT cancel_type; + INT cancel_type; /* Identifier of the target thread to which this pthread is joined */ - pthread_t joined_to_pthreadID; + pthread_t joined_to_pthreadID; /* Identifier of the caller thread which has joined to this thread*/ pthread_t joined_by_pthreadID; /* To check if posix pthread is joined to any other pthread */ @@ -325,16 +316,16 @@ typedef struct pthread_control_block UINT is_detached; /* Value returned by the terminating thread which is joined to this thread */ VOID *value_ptr; - /* Define the original pthread priority. */ + /* Define the original pthread priority. */ ULONG orig_priority; - /* Define the current pthread priority. */ + /* Define the current pthread priority. */ ULONG current_priority; - /* Define the pthread's pre-emption threshold. */ + /* Define the pthread's pre-emption threshold. */ ULONG threshold; - /* Define the pthread's timeslice. */ + /* Define the pthread's timeslice. */ ULONG time_slice; /* specify pthread start routine */ - VOID *(*start_routine)(VOID *); + VOID *(*start_routine)(VOID *); /* specify argument for start up routine */ ULONG *entry_parameter; /* to hold error code for this pthread */ @@ -353,15 +344,15 @@ typedef struct pthread_mutex_attr_obj INT protocol; INT pshared; INT in_use; - + } pthread_mutexattr_t; /* Define POSIX mutex structure. */ typedef struct pthread_mutex_control_block { - /* This mutex's ThreadX Control block */ - TX_MUTEX mutex_info; + /* This mutex's ThreadX Control block */ + TX_MUTEX mutex_info; /* This mutex's attributes */ INT type; /* Is this Mutex object is in use? */ @@ -381,7 +372,7 @@ struct mq_attr ULONG mq_msgsize; /* Flags are ignored as these are passed separately in open(). */ ULONG mq_flags; -}; +}; /* Define POSIX message queue structure. */ typedef struct msg_que @@ -410,17 +401,17 @@ typedef struct msg_que /* Define Queue Descriptor. */ typedef struct mq_des { - /* Queue FLAGS. */ + /* Queue FLAGS. */ ULONG f_flag; /* message Queue structure. */ POSIX_MSG_QUEUE * f_data; - + } *mqd_t; /* STRUCTURES RELATED TO POSIX SEMAPHORES */ -typedef struct POSIX_SEMAPHORE_STRUCT +typedef struct POSIX_SEMAPHORE_STRUCT { /* ThreadX semaphore. */ TX_SEMAPHORE sem; @@ -439,23 +430,23 @@ typedef struct POSIX_SEMAPHORE_STRUCT } sem_t; -typedef sem_t *SEM_ID; +typedef sem_t *SEM_ID; typedef struct pthread_cond_obj { - /* This pthread condition variable's internal counting Semaphore */ + /* This pthread condition variable's internal counting Semaphore */ TX_SEMAPHORE cond_semaphore; - + INT type; INT in_use; - + } pthread_cond_t; typedef struct pthread_condattr_obj { /* INT type; */ INT in_use; - + } pthread_condattr_t; @@ -478,10 +469,10 @@ extern unsigned int posix_errno; VOID *posix_initialize(VOID * posix_memory); -/* Define POSIX API function prototypes. */ +/* Define POSIX API function prototypes. */ INT mq_send(mqd_t mqdes, const char * msg_ptr, - size_t msg_len,ULONG msg_prio ); + size_t msg_len,ULONG msg_prio ); ssize_t mq_receive(mqd_t mqdes, VOID *pMsg, size_t msgLen, ULONG *pMsgPrio ); INT mq_unlink(const char * mqName); @@ -497,7 +488,7 @@ INT sem_wait( sem_t * sem ); INT sem_init(sem_t *sem , INT pshared, UINT value); INT sem_destroy(sem_t *sem); -INT pthread_create (pthread_t *thread, pthread_attr_t *attr, +INT pthread_create (pthread_t *thread, pthread_attr_t *attr, VOID *(*start_routine)(VOID*),VOID *arg); INT pthread_detach(pthread_t thread); INT pthread_join(pthread_t thread, VOID **value_ptr); diff --git a/utility/rtos_compatibility_layers/posix/tx_px_time.h b/utility/rtos_compatibility_layers/posix/tx_px_time.h index fcd80338..cf0476f0 100644 --- a/utility/rtos_compatibility_layers/posix/tx_px_time.h +++ b/utility/rtos_compatibility_layers/posix/tx_px_time.h @@ -1,10 +1,11 @@ /*************************************************************************** - * Copyright (c) 2024 Microsoft Corporation - * + * Copyright (c) 2024 Microsoft Corporation + * Copyright (c) 2026-present Eclipse ThreadX contributors + * * This program and the accompanying materials are made available under the * terms of the MIT License which is available at * https://opensource.org/licenses/MIT. - * + * * SPDX-License-Identifier: MIT **************************************************************************/ @@ -34,13 +35,6 @@ /* implement time related functionality for the Evacuation Kit */ /* for POSIX Users (POSIX) */ /* */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */ -/* */ /**************************************************************************/ #ifndef _TX_PX_TIME_H @@ -52,7 +46,7 @@ typedef ULONG time_t; #endif -struct timespec +struct timespec { ULONG timeout_value; /* time in terms of CPU ticks */ time_t tv_sec; /* time in terms of Seconds */